src/gallium/drivers/radeonsi/si_pm4.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #include "../radeon/r600_cs.h"
  28 #include "util/u_memory.h"
  29 #include "si_pipe.h"
  30 #include "sid.h"
  31
  32 #define NUMBER_OF_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
  33
  34 void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode)
  35 {
  36         state->last_opcode = opcode;
  37         state->last_pm4 = state->ndw++;
  38 }
  39
  40 void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw)
  41 {
  42         state->pm4[state->ndw++] = dw;
  43 }
  44
  45 void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate)
  46 {
  47         unsigned count;
  48         count = state->ndw - state->last_pm4 - 2;
  49         state->pm4[state->last_pm4] =
  50                 PKT3(state->last_opcode, count, predicate)
  51                    | PKT3_SHADER_TYPE_S(state->compute_pkt);
  52
  53         assert(state->ndw <= SI_PM4_MAX_DW);
  54 }
  55
  56 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
  57 {
  58         unsigned opcode;
  59
  60         if (reg >= SI_CONFIG_REG_OFFSET && reg < SI_CONFIG_REG_END) {
  61                 opcode = PKT3_SET_CONFIG_REG;
  62                 reg -= SI_CONFIG_REG_OFFSET;
  63
  64         } else if (reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END) {
  65                 opcode = PKT3_SET_SH_REG;
  66                 reg -= SI_SH_REG_OFFSET;
  67
  68         } else if (reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END) {
  69                 opcode = PKT3_SET_CONTEXT_REG;
  70                 reg -= SI_CONTEXT_REG_OFFSET;
  71
  72         } else if (reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END) {
  73                 opcode = PKT3_SET_UCONFIG_REG;
  74                 reg -= CIK_UCONFIG_REG_OFFSET;
  75
  76         } else {
  77                 R600_ERR("Invalid register offset %08x!\n", reg);
  78                 return;
  79         }
  80
  81         reg >>= 2;
  82
  83         if (opcode != state->last_opcode || reg != (state->last_reg + 1)) {
  84                 si_pm4_cmd_begin(state, opcode);
  85                 si_pm4_cmd_add(state, reg);
  86         }
  87
  88         state->last_reg = reg;
  89         si_pm4_cmd_add(state, val);
  90         si_pm4_cmd_end(state, false);
  91 }
  92
  93 void si_pm4_add_bo(struct si_pm4_state *state,
  94                    struct r600_resource *bo,
  95                    enum radeon_bo_usage usage,
  96                    enum radeon_bo_priority priority)
  97 {
  98         unsigned idx = state->nbo++;
  99         assert(idx < SI_PM4_MAX_BO);
 100
 101         r600_resource_reference(&state->bo[idx], bo);
 102         state->bo_usage[idx] = usage;
 103         state->bo_priority[idx] = priority;
 104 }
 105
 106 void si_pm4_sh_data_begin(struct si_pm4_state *state)
 107 {
 108         si_pm4_cmd_begin(state, PKT3_NOP);
 109 }
 110
 111 void si_pm4_sh_data_add(struct si_pm4_state *state, uint32_t dw)
 112 {
 113         si_pm4_cmd_add(state, dw);
 114 }
 115
 116 void si_pm4_sh_data_end(struct si_pm4_state *state, unsigned base, unsigned idx)
 117 {
 118         unsigned offs = state->last_pm4 + 1;
 119         unsigned reg = base + idx * 4;
 120
 121         /* Bail if no data was added */
 122         if (state->ndw == offs) {
 123                 state->ndw--;
 124                 return;
 125         }
 126
 127         si_pm4_cmd_end(state, false);
 128
 129         si_pm4_cmd_begin(state, PKT3_SET_SH_REG_OFFSET);
 130         si_pm4_cmd_add(state, (reg - SI_SH_REG_OFFSET) >> 2);
 131         state->relocs[state->nrelocs++] = state->ndw;
 132         si_pm4_cmd_add(state, offs << 2);
 133         si_pm4_cmd_add(state, 0);
 134         si_pm4_cmd_end(state, false);
 135 }
 136
 137 void si_pm4_inval_shader_cache(struct si_pm4_state *state)
 138 {
 139         state->cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
 140         state->cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
 141 }
 142
 143 void si_pm4_inval_texture_cache(struct si_pm4_state *state)
 144 {
 145         state->cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
 146         state->cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
 147 }
 148
 149 void si_pm4_free_state(struct si_context *sctx,
 150                        struct si_pm4_state *state,
 151                        unsigned idx)
 152 {
 153         if (state == NULL)
 154                 return;
 155
 156         if (idx != ~0 && sctx->emitted.array[idx] == state) {
 157                 sctx->emitted.array[idx] = NULL;
 158         }
 159
 160         for (int i = 0; i < state->nbo; ++i) {
 161                 r600_resource_reference(&state->bo[i], NULL);
 162         }
 163         FREE(state);
 164 }
 165
 166 struct si_pm4_state * si_pm4_alloc_state(struct si_context *sctx)
 167 {
 168         struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
 169
 170         if (pm4 == NULL)
 171                 return NULL;
 172
 173         pm4->chip_class = sctx->b.chip_class;
 174
 175         return pm4;
 176 }
 177
 178 uint32_t si_pm4_sync_flags(struct si_context *sctx)
 179 {
 180         uint32_t cp_coher_cntl = 0;
 181
 182         for (int i = 0; i < NUMBER_OF_STATES; ++i) {
 183                 struct si_pm4_state *state = sctx->queued.array[i];
 184
 185                 if (!state || sctx->emitted.array[i] == state)
 186                         continue;
 187
 188                 cp_coher_cntl |= state->cp_coher_cntl;
 189         }
 190         return cp_coher_cntl;
 191 }
 192
 193 unsigned si_pm4_dirty_dw(struct si_context *sctx)
 194 {
 195         unsigned count = 0;
 196
 197         for (int i = 0; i < NUMBER_OF_STATES; ++i) {
 198                 struct si_pm4_state *state = sctx->queued.array[i];
 199
 200                 if (!state || sctx->emitted.array[i] == state)
 201                         continue;
 202
 203                 count += state->ndw;
 204 #if SI_TRACE_CS
 205                 /* for tracing each states */
 206                 if (sctx->screen->b.trace_bo) {
 207                         count += SI_TRACE_CS_DWORDS;
 208                 }
 209 #endif
 210         }
 211
 212         return count;
 213 }
 214
 215 void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
 216 {
 217         struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
 218         for (int i = 0; i < state->nbo; ++i) {
 219                 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, state->bo[i],
 220                                       state->bo_usage[i], state->bo_priority[i]);
 221         }
 222
 223         memcpy(&cs->buf[cs->cdw], state->pm4, state->ndw * 4);
 224
 225         for (int i = 0; i < state->nrelocs; ++i) {
 226                 cs->buf[cs->cdw + state->relocs[i]] += cs->cdw << 2;
 227         }
 228
 229         cs->cdw += state->ndw;
 230
 231 #if SI_TRACE_CS
 232         if (sctx->screen->b.trace_bo) {
 233                 si_trace_emit(sctx);
 234         }
 235 #endif
 236 }
 237
 238 void si_pm4_emit_dirty(struct si_context *sctx)
 239 {
 240         for (int i = 0; i < NUMBER_OF_STATES; ++i) {
 241                 struct si_pm4_state *state = sctx->queued.array[i];
 242
 243                 if (!state || sctx->emitted.array[i] == state)
 244                         continue;
 245
 246                 assert(state != sctx->queued.named.init);
 247                 si_pm4_emit(sctx, state);
 248                 sctx->emitted.array[i] = state;
 249         }
 250 }
 251
 252 void si_pm4_reset_emitted(struct si_context *sctx)
 253 {
 254         memset(&sctx->emitted, 0, sizeof(sctx->emitted));
 255 }
 256
 257 void si_pm4_cleanup(struct si_context *sctx)
 258 {
 259         for (int i = 0; i < NUMBER_OF_STATES; ++i) {
 260                 si_pm4_free_state(sctx, sctx->queued.array[i], i);
 261         }
 262 }