2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
27 #include "../radeon/r600_cs.h"
28 #include "util/u_memory.h"
32 #define NUMBER_OF_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
34 void si_pm4_cmd_begin(struct si_pm4_state
*state
, unsigned opcode
)
36 state
->last_opcode
= opcode
;
37 state
->last_pm4
= state
->ndw
++;
40 void si_pm4_cmd_add(struct si_pm4_state
*state
, uint32_t dw
)
42 state
->pm4
[state
->ndw
++] = dw
;
45 void si_pm4_cmd_end(struct si_pm4_state
*state
, bool predicate
)
48 count
= state
->ndw
- state
->last_pm4
- 2;
49 state
->pm4
[state
->last_pm4
] =
50 PKT3(state
->last_opcode
, count
, predicate
)
51 | PKT3_SHADER_TYPE_S(state
->compute_pkt
);
53 assert(state
->ndw
<= SI_PM4_MAX_DW
);
56 void si_pm4_set_reg(struct si_pm4_state
*state
, unsigned reg
, uint32_t val
)
60 if (reg
>= SI_CONFIG_REG_OFFSET
&& reg
< SI_CONFIG_REG_END
) {
61 opcode
= PKT3_SET_CONFIG_REG
;
62 reg
-= SI_CONFIG_REG_OFFSET
;
64 } else if (reg
>= SI_SH_REG_OFFSET
&& reg
< SI_SH_REG_END
) {
65 opcode
= PKT3_SET_SH_REG
;
66 reg
-= SI_SH_REG_OFFSET
;
68 } else if (reg
>= SI_CONTEXT_REG_OFFSET
&& reg
< SI_CONTEXT_REG_END
) {
69 opcode
= PKT3_SET_CONTEXT_REG
;
70 reg
-= SI_CONTEXT_REG_OFFSET
;
72 } else if (reg
>= CIK_UCONFIG_REG_OFFSET
&& reg
< CIK_UCONFIG_REG_END
) {
73 opcode
= PKT3_SET_UCONFIG_REG
;
74 reg
-= CIK_UCONFIG_REG_OFFSET
;
77 R600_ERR("Invalid register offset %08x!\n", reg
);
83 if (opcode
!= state
->last_opcode
|| reg
!= (state
->last_reg
+ 1)) {
84 si_pm4_cmd_begin(state
, opcode
);
85 si_pm4_cmd_add(state
, reg
);
88 state
->last_reg
= reg
;
89 si_pm4_cmd_add(state
, val
);
90 si_pm4_cmd_end(state
, false);
93 void si_pm4_add_bo(struct si_pm4_state
*state
,
94 struct r600_resource
*bo
,
95 enum radeon_bo_usage usage
,
96 enum radeon_bo_priority priority
)
98 unsigned idx
= state
->nbo
++;
99 assert(idx
< SI_PM4_MAX_BO
);
101 r600_resource_reference(&state
->bo
[idx
], bo
);
102 state
->bo_usage
[idx
] = usage
;
103 state
->bo_priority
[idx
] = priority
;
106 void si_pm4_sh_data_begin(struct si_pm4_state
*state
)
108 si_pm4_cmd_begin(state
, PKT3_NOP
);
111 void si_pm4_sh_data_add(struct si_pm4_state
*state
, uint32_t dw
)
113 si_pm4_cmd_add(state
, dw
);
116 void si_pm4_sh_data_end(struct si_pm4_state
*state
, unsigned base
, unsigned idx
)
118 unsigned offs
= state
->last_pm4
+ 1;
119 unsigned reg
= base
+ idx
* 4;
121 /* Bail if no data was added */
122 if (state
->ndw
== offs
) {
127 si_pm4_cmd_end(state
, false);
129 si_pm4_cmd_begin(state
, PKT3_SET_SH_REG_OFFSET
);
130 si_pm4_cmd_add(state
, (reg
- SI_SH_REG_OFFSET
) >> 2);
131 state
->relocs
[state
->nrelocs
++] = state
->ndw
;
132 si_pm4_cmd_add(state
, offs
<< 2);
133 si_pm4_cmd_add(state
, 0);
134 si_pm4_cmd_end(state
, false);
137 void si_pm4_inval_shader_cache(struct si_pm4_state
*state
)
139 state
->cp_coher_cntl
|= S_0085F0_SH_ICACHE_ACTION_ENA(1);
140 state
->cp_coher_cntl
|= S_0085F0_SH_KCACHE_ACTION_ENA(1);
143 void si_pm4_inval_texture_cache(struct si_pm4_state
*state
)
145 state
->cp_coher_cntl
|= S_0085F0_TC_ACTION_ENA(1);
146 state
->cp_coher_cntl
|= S_0085F0_TCL1_ACTION_ENA(1);
149 void si_pm4_free_state(struct si_context
*sctx
,
150 struct si_pm4_state
*state
,
156 if (idx
!= ~0 && sctx
->emitted
.array
[idx
] == state
) {
157 sctx
->emitted
.array
[idx
] = NULL
;
160 for (int i
= 0; i
< state
->nbo
; ++i
) {
161 r600_resource_reference(&state
->bo
[i
], NULL
);
166 struct si_pm4_state
* si_pm4_alloc_state(struct si_context
*sctx
)
168 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
173 pm4
->chip_class
= sctx
->b
.chip_class
;
178 uint32_t si_pm4_sync_flags(struct si_context
*sctx
)
180 uint32_t cp_coher_cntl
= 0;
182 for (int i
= 0; i
< NUMBER_OF_STATES
; ++i
) {
183 struct si_pm4_state
*state
= sctx
->queued
.array
[i
];
185 if (!state
|| sctx
->emitted
.array
[i
] == state
)
188 cp_coher_cntl
|= state
->cp_coher_cntl
;
190 return cp_coher_cntl
;
193 unsigned si_pm4_dirty_dw(struct si_context
*sctx
)
197 for (int i
= 0; i
< NUMBER_OF_STATES
; ++i
) {
198 struct si_pm4_state
*state
= sctx
->queued
.array
[i
];
200 if (!state
|| sctx
->emitted
.array
[i
] == state
)
205 /* for tracing each states */
206 if (sctx
->screen
->b
.trace_bo
) {
207 count
+= SI_TRACE_CS_DWORDS
;
215 void si_pm4_emit(struct si_context
*sctx
, struct si_pm4_state
*state
)
217 struct radeon_winsys_cs
*cs
= sctx
->b
.rings
.gfx
.cs
;
218 for (int i
= 0; i
< state
->nbo
; ++i
) {
219 r600_context_bo_reloc(&sctx
->b
, &sctx
->b
.rings
.gfx
, state
->bo
[i
],
220 state
->bo_usage
[i
], state
->bo_priority
[i
]);
223 memcpy(&cs
->buf
[cs
->cdw
], state
->pm4
, state
->ndw
* 4);
225 for (int i
= 0; i
< state
->nrelocs
; ++i
) {
226 cs
->buf
[cs
->cdw
+ state
->relocs
[i
]] += cs
->cdw
<< 2;
229 cs
->cdw
+= state
->ndw
;
232 if (sctx
->screen
->b
.trace_bo
) {
238 void si_pm4_emit_dirty(struct si_context
*sctx
)
240 for (int i
= 0; i
< NUMBER_OF_STATES
; ++i
) {
241 struct si_pm4_state
*state
= sctx
->queued
.array
[i
];
243 if (!state
|| sctx
->emitted
.array
[i
] == state
)
246 assert(state
!= sctx
->queued
.named
.init
);
247 si_pm4_emit(sctx
, state
);
248 sctx
->emitted
.array
[i
] = state
;
252 void si_pm4_reset_emitted(struct si_context
*sctx
)
254 memset(&sctx
->emitted
, 0, sizeof(sctx
->emitted
));
257 void si_pm4_cleanup(struct si_context
*sctx
)
259 for (int i
= 0; i
< NUMBER_OF_STATES
; ++i
) {
260 si_pm4_free_state(sctx
, sctx
->queued
.array
[i
], i
);