src/gallium/drivers/radeonsi/si_pm4.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "sid.h"
  27 #include "util/u_memory.h"
  28
  29 void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode)
  30 {
  31    state->last_opcode = opcode;
  32    state->last_pm4 = state->ndw++;
  33 }
  34
  35 void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw)
  36 {
  37    state->pm4[state->ndw++] = dw;
  38 }
  39
  40 void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate)
  41 {
  42    unsigned count;
  43    count = state->ndw - state->last_pm4 - 2;
  44    state->pm4[state->last_pm4] = PKT3(state->last_opcode, count, predicate);
  45
  46    assert(state->ndw <= SI_PM4_MAX_DW);
  47 }
  48
  49 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
  50 {
  51    unsigned opcode;
  52
  53    if (reg >= SI_CONFIG_REG_OFFSET && reg < SI_CONFIG_REG_END) {
  54       opcode = PKT3_SET_CONFIG_REG;
  55       reg -= SI_CONFIG_REG_OFFSET;
  56
  57    } else if (reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END) {
  58       opcode = PKT3_SET_SH_REG;
  59       reg -= SI_SH_REG_OFFSET;
  60
  61    } else if (reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END) {
  62       opcode = PKT3_SET_CONTEXT_REG;
  63       reg -= SI_CONTEXT_REG_OFFSET;
  64
  65    } else if (reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END) {
  66       opcode = PKT3_SET_UCONFIG_REG;
  67       reg -= CIK_UCONFIG_REG_OFFSET;
  68
  69    } else {
  70       PRINT_ERR("Invalid register offset %08x!\n", reg);
  71       return;
  72    }
  73
  74    reg >>= 2;
  75
  76    if (opcode != state->last_opcode || reg != (state->last_reg + 1)) {
  77       si_pm4_cmd_begin(state, opcode);
  78       si_pm4_cmd_add(state, reg);
  79    }
  80
  81    state->last_reg = reg;
  82    si_pm4_cmd_add(state, val);
  83    si_pm4_cmd_end(state, false);
  84 }
  85
  86 void si_pm4_add_bo(struct si_pm4_state *state, struct si_resource *bo, enum radeon_bo_usage usage,
  87                    enum radeon_bo_priority priority)
  88 {
  89    unsigned idx = state->nbo++;
  90    assert(idx < SI_PM4_MAX_BO);
  91
  92    si_resource_reference(&state->bo[idx], bo);
  93    state->bo_usage[idx] = usage;
  94    state->bo_priority[idx] = priority;
  95 }
  96
  97 void si_pm4_clear_state(struct si_pm4_state *state)
  98 {
  99    for (int i = 0; i < state->nbo; ++i)
 100       si_resource_reference(&state->bo[i], NULL);
 101    si_resource_reference(&state->indirect_buffer, NULL);
 102    state->nbo = 0;
 103    state->ndw = 0;
 104 }
 105
 106 void si_pm4_free_state(struct si_context *sctx, struct si_pm4_state *state, unsigned idx)
 107 {
 108    if (!state)
 109       return;
 110
 111    if (idx != ~0 && sctx->emitted.array[idx] == state) {
 112       sctx->emitted.array[idx] = NULL;
 113    }
 114
 115    si_pm4_clear_state(state);
 116    FREE(state);
 117 }
 118
 119 void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
 120 {
 121    struct radeon_cmdbuf *cs = sctx->gfx_cs;
 122
 123    for (int i = 0; i < state->nbo; ++i) {
 124       radeon_add_to_buffer_list(sctx, sctx->gfx_cs, state->bo[i], state->bo_usage[i],
 125                                 state->bo_priority[i]);
 126    }
 127
 128    if (!state->indirect_buffer) {
 129       radeon_emit_array(cs, state->pm4, state->ndw);
 130    } else {
 131       struct si_resource *ib = state->indirect_buffer;
 132
 133       radeon_add_to_buffer_list(sctx, sctx->gfx_cs, ib, RADEON_USAGE_READ, RADEON_PRIO_IB2);
 134
 135       radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
 136       radeon_emit(cs, ib->gpu_address);
 137       radeon_emit(cs, ib->gpu_address >> 32);
 138       radeon_emit(cs, (ib->b.b.width0 >> 2) & 0xfffff);
 139    }
 140
 141    if (state->atom.emit)
 142       state->atom.emit(sctx);
 143 }
 144
 145 void si_pm4_reset_emitted(struct si_context *sctx)
 146 {
 147    memset(&sctx->emitted, 0, sizeof(sctx->emitted));
 148    sctx->dirty_states |= u_bit_consecutive(0, SI_NUM_STATES);
 149 }
 150
 151 void si_pm4_upload_indirect_buffer(struct si_context *sctx, struct si_pm4_state *state)
 152 {
 153    struct pipe_screen *screen = sctx->b.screen;
 154    unsigned aligned_ndw = align(state->ndw, 8);
 155
 156    /* only supported on GFX7 and later */
 157    if (sctx->chip_class < GFX7)
 158       return;
 159
 160    assert(state->ndw);
 161    assert(aligned_ndw <= SI_PM4_MAX_DW);
 162
 163    si_resource_reference(&state->indirect_buffer, NULL);
 164    /* TODO: this hangs with 1024 or higher alignment on GFX9. */
 165    state->indirect_buffer =
 166       si_aligned_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, aligned_ndw * 4, 256);
 167    if (!state->indirect_buffer)
 168       return;
 169
 170    /* Pad the IB to 8 DWs to meet CP fetch alignment requirements. */
 171    if (sctx->screen->info.gfx_ib_pad_with_type2) {
 172       for (int i = state->ndw; i < aligned_ndw; i++)
 173          state->pm4[i] = 0x80000000; /* type2 nop packet */
 174    } else {
 175       for (int i = state->ndw; i < aligned_ndw; i++)
 176          state->pm4[i] = 0xffff1000; /* type3 nop packet */
 177    }
 178
 179    pipe_buffer_write(&sctx->b, &state->indirect_buffer->b.b, 0, aligned_ndw * 4, state->pm4);
 180 }