src/gallium/drivers/radeonsi/si_pm4.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "sid.h"
  27 #include "util/u_memory.h"
  28
  29 void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode)
  30 {
  31    state->last_opcode = opcode;
  32    state->last_pm4 = state->ndw++;
  33 }
  34
  35 void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw)
  36 {
  37    state->pm4[state->ndw++] = dw;
  38 }
  39
  40 void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate)
  41 {
  42    unsigned count;
  43    count = state->ndw - state->last_pm4 - 2;
  44    state->pm4[state->last_pm4] = PKT3(state->last_opcode, count, predicate);
  45
  46    assert(state->ndw <= SI_PM4_MAX_DW);
  47 }
  48
  49 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
  50 {
  51    unsigned opcode;
  52
  53    if (reg >= SI_CONFIG_REG_OFFSET && reg < SI_CONFIG_REG_END) {
  54       opcode = PKT3_SET_CONFIG_REG;
  55       reg -= SI_CONFIG_REG_OFFSET;
  56
  57    } else if (reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END) {
  58       opcode = PKT3_SET_SH_REG;
  59       reg -= SI_SH_REG_OFFSET;
  60
  61    } else if (reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END) {
  62       opcode = PKT3_SET_CONTEXT_REG;
  63       reg -= SI_CONTEXT_REG_OFFSET;
  64
  65    } else if (reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END) {
  66       opcode = PKT3_SET_UCONFIG_REG;
  67       reg -= CIK_UCONFIG_REG_OFFSET;
  68
  69    } else {
  70       PRINT_ERR("Invalid register offset %08x!\n", reg);
  71       return;
  72    }
  73
  74    reg >>= 2;
  75
  76    if (opcode != state->last_opcode || reg != (state->last_reg + 1)) {
  77       si_pm4_cmd_begin(state, opcode);
  78       si_pm4_cmd_add(state, reg);
  79    }
  80
  81    state->last_reg = reg;
  82    si_pm4_cmd_add(state, val);
  83    si_pm4_cmd_end(state, false);
  84 }
  85
  86 void si_pm4_add_bo(struct si_pm4_state *state, struct si_resource *bo, enum radeon_bo_usage usage,
  87                    enum radeon_bo_priority priority)
  88 {
  89    unsigned idx = state->nbo++;
  90    assert(idx < SI_PM4_MAX_BO);
  91
  92    si_resource_reference(&state->bo[idx], bo);
  93    state->bo_usage[idx] = usage;
  94    state->bo_priority[idx] = priority;
  95 }
  96
  97 void si_pm4_clear_state(struct si_pm4_state *state)
  98 {
  99    for (int i = 0; i < state->nbo; ++i)
 100       si_resource_reference(&state->bo[i], NULL);
 101    state->nbo = 0;
 102    state->ndw = 0;
 103 }
 104
 105 void si_pm4_free_state(struct si_context *sctx, struct si_pm4_state *state, unsigned idx)
 106 {
 107    if (!state)
 108       return;
 109
 110    if (idx != ~0 && sctx->emitted.array[idx] == state) {
 111       sctx->emitted.array[idx] = NULL;
 112    }
 113
 114    si_pm4_clear_state(state);
 115    FREE(state);
 116 }
 117
 118 void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
 119 {
 120    struct radeon_cmdbuf *cs = sctx->gfx_cs;
 121
 122    for (int i = 0; i < state->nbo; ++i) {
 123       radeon_add_to_buffer_list(sctx, sctx->gfx_cs, state->bo[i], state->bo_usage[i],
 124                                 state->bo_priority[i]);
 125    }
 126
 127    radeon_emit_array(cs, state->pm4, state->ndw);
 128
 129    if (state->atom.emit)
 130       state->atom.emit(sctx);
 131 }
 132
 133 void si_pm4_reset_emitted(struct si_context *sctx)
 134 {
 135    memset(&sctx->emitted, 0, sizeof(sctx->emitted));
 136    sctx->dirty_states |= u_bit_consecutive(0, SI_NUM_STATES);
 137 }