2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "util/u_memory.h"
29 static void si_pm4_cmd_begin(struct si_pm4_state
*state
, unsigned opcode
)
31 assert(state
->ndw
< SI_PM4_MAX_DW
);
32 state
->last_opcode
= opcode
;
33 state
->last_pm4
= state
->ndw
++;
36 void si_pm4_cmd_add(struct si_pm4_state
*state
, uint32_t dw
)
38 assert(state
->ndw
< SI_PM4_MAX_DW
);
39 state
->pm4
[state
->ndw
++] = dw
;
42 static void si_pm4_cmd_end(struct si_pm4_state
*state
, bool predicate
)
45 count
= state
->ndw
- state
->last_pm4
- 2;
46 state
->pm4
[state
->last_pm4
] = PKT3(state
->last_opcode
, count
, predicate
);
49 void si_pm4_set_reg(struct si_pm4_state
*state
, unsigned reg
, uint32_t val
)
53 if (reg
>= SI_CONFIG_REG_OFFSET
&& reg
< SI_CONFIG_REG_END
) {
54 opcode
= PKT3_SET_CONFIG_REG
;
55 reg
-= SI_CONFIG_REG_OFFSET
;
57 } else if (reg
>= SI_SH_REG_OFFSET
&& reg
< SI_SH_REG_END
) {
58 opcode
= PKT3_SET_SH_REG
;
59 reg
-= SI_SH_REG_OFFSET
;
61 } else if (reg
>= SI_CONTEXT_REG_OFFSET
&& reg
< SI_CONTEXT_REG_END
) {
62 opcode
= PKT3_SET_CONTEXT_REG
;
63 reg
-= SI_CONTEXT_REG_OFFSET
;
65 } else if (reg
>= CIK_UCONFIG_REG_OFFSET
&& reg
< CIK_UCONFIG_REG_END
) {
66 opcode
= PKT3_SET_UCONFIG_REG
;
67 reg
-= CIK_UCONFIG_REG_OFFSET
;
70 PRINT_ERR("Invalid register offset %08x!\n", reg
);
76 if (opcode
!= state
->last_opcode
|| reg
!= (state
->last_reg
+ 1)) {
77 si_pm4_cmd_begin(state
, opcode
);
78 si_pm4_cmd_add(state
, reg
);
81 state
->last_reg
= reg
;
82 si_pm4_cmd_add(state
, val
);
83 si_pm4_cmd_end(state
, false);
86 void si_pm4_clear_state(struct si_pm4_state
*state
)
91 void si_pm4_free_state(struct si_context
*sctx
, struct si_pm4_state
*state
, unsigned idx
)
96 if (idx
!= ~0 && sctx
->emitted
.array
[idx
] == state
) {
97 sctx
->emitted
.array
[idx
] = NULL
;
100 si_pm4_clear_state(state
);
104 void si_pm4_emit(struct si_context
*sctx
, struct si_pm4_state
*state
)
106 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
109 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, state
->shader
->bo
,
110 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
113 radeon_emit_array(cs
, state
->pm4
, state
->ndw
);
115 if (state
->atom
.emit
)
116 state
->atom
.emit(sctx
);
119 void si_pm4_reset_emitted(struct si_context
*sctx
)
121 memset(&sctx
->emitted
, 0, sizeof(sctx
->emitted
));
122 sctx
->dirty_states
|= u_bit_consecutive(0, SI_NUM_STATES
);