src/gallium/drivers/radeonsi/si_pm4.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #include "radeon/r600_cs.h"
  28 #include "util/u_memory.h"
  29 #include "si_pipe.h"
  30 #include "sid.h"
  31
  32 void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode)
  33 {
  34         state->last_opcode = opcode;
  35         state->last_pm4 = state->ndw++;
  36 }
  37
  38 void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw)
  39 {
  40         state->pm4[state->ndw++] = dw;
  41 }
  42
  43 void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate)
  44 {
  45         unsigned count;
  46         count = state->ndw - state->last_pm4 - 2;
  47         state->pm4[state->last_pm4] =
  48                 PKT3(state->last_opcode, count, predicate)
  49                    | PKT3_SHADER_TYPE_S(state->compute_pkt);
  50
  51         assert(state->ndw <= SI_PM4_MAX_DW);
  52 }
  53
  54 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
  55 {
  56         unsigned opcode;
  57
  58         if (reg >= SI_CONFIG_REG_OFFSET && reg < SI_CONFIG_REG_END) {
  59                 opcode = PKT3_SET_CONFIG_REG;
  60                 reg -= SI_CONFIG_REG_OFFSET;
  61
  62         } else if (reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END) {
  63                 opcode = PKT3_SET_SH_REG;
  64                 reg -= SI_SH_REG_OFFSET;
  65
  66         } else if (reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END) {
  67                 opcode = PKT3_SET_CONTEXT_REG;
  68                 reg -= SI_CONTEXT_REG_OFFSET;
  69
  70         } else if (reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END) {
  71                 opcode = PKT3_SET_UCONFIG_REG;
  72                 reg -= CIK_UCONFIG_REG_OFFSET;
  73
  74         } else {
  75                 R600_ERR("Invalid register offset %08x!\n", reg);
  76                 return;
  77         }
  78
  79         reg >>= 2;
  80
  81         if (opcode != state->last_opcode || reg != (state->last_reg + 1)) {
  82                 si_pm4_cmd_begin(state, opcode);
  83                 si_pm4_cmd_add(state, reg);
  84         }
  85
  86         state->last_reg = reg;
  87         si_pm4_cmd_add(state, val);
  88         si_pm4_cmd_end(state, false);
  89 }
  90
  91 void si_pm4_add_bo(struct si_pm4_state *state,
  92                    struct r600_resource *bo,
  93                    enum radeon_bo_usage usage,
  94                    enum radeon_bo_priority priority)
  95 {
  96         unsigned idx = state->nbo++;
  97         assert(idx < SI_PM4_MAX_BO);
  98
  99         r600_resource_reference(&state->bo[idx], bo);
 100         state->bo_usage[idx] = usage;
 101         state->bo_priority[idx] = priority;
 102 }
 103
 104 void si_pm4_clear_state(struct si_pm4_state *state)
 105 {
 106         for (int i = 0; i < state->nbo; ++i)
 107                 r600_resource_reference(&state->bo[i], NULL);
 108         r600_resource_reference(&state->indirect_buffer, NULL);
 109         state->nbo = 0;
 110         state->ndw = 0;
 111 }
 112
 113 void si_pm4_free_state_simple(struct si_pm4_state *state)
 114 {
 115         si_pm4_clear_state(state);
 116         FREE(state);
 117 }
 118
 119 void si_pm4_free_state(struct si_context *sctx,
 120                        struct si_pm4_state *state,
 121                        unsigned idx)
 122 {
 123         if (!state)
 124                 return;
 125
 126         if (idx != ~0 && sctx->emitted.array[idx] == state) {
 127                 sctx->emitted.array[idx] = NULL;
 128         }
 129
 130         si_pm4_free_state_simple(state);
 131 }
 132
 133 void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
 134 {
 135         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 136
 137         for (int i = 0; i < state->nbo; ++i) {
 138                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, state->bo[i],
 139                                       state->bo_usage[i], state->bo_priority[i]);
 140         }
 141
 142         if (!state->indirect_buffer) {
 143                 radeon_emit_array(cs, state->pm4, state->ndw);
 144         } else {
 145                 struct r600_resource *ib = state->indirect_buffer;
 146
 147                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, ib,
 148                                           RADEON_USAGE_READ,
 149                                           RADEON_PRIO_IB2);
 150
 151                 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
 152                 radeon_emit(cs, ib->gpu_address);
 153                 radeon_emit(cs, ib->gpu_address >> 32);
 154                 radeon_emit(cs, (ib->b.b.width0 >> 2) & 0xfffff);
 155         }
 156 }
 157
 158 void si_pm4_reset_emitted(struct si_context *sctx)
 159 {
 160         memset(&sctx->emitted, 0, sizeof(sctx->emitted));
 161         sctx->dirty_states |= u_bit_consecutive(0, SI_NUM_STATES);
 162 }
 163
 164 void si_pm4_upload_indirect_buffer(struct si_context *sctx,
 165                                    struct si_pm4_state *state)
 166 {
 167         struct pipe_screen *screen = sctx->b.b.screen;
 168         unsigned aligned_ndw = align(state->ndw, 8);
 169
 170         /* only supported on CIK and later */
 171         if (sctx->b.chip_class < CIK)
 172                 return;
 173
 174         assert(state->ndw);
 175         assert(aligned_ndw <= SI_PM4_MAX_DW);
 176
 177         r600_resource_reference(&state->indirect_buffer, NULL);
 178         state->indirect_buffer = (struct r600_resource*)
 179                 pipe_buffer_create(screen, 0,
 180                                    PIPE_USAGE_DEFAULT, aligned_ndw * 4);
 181         if (!state->indirect_buffer)
 182                 return;
 183
 184         /* Pad the IB to 8 DWs to meet CP fetch alignment requirements. */
 185         if (sctx->screen->b.info.gfx_ib_pad_with_type2) {
 186                 for (int i = state->ndw; i < aligned_ndw; i++)
 187                         state->pm4[i] = 0x80000000; /* type2 nop packet */
 188         } else {
 189                 for (int i = state->ndw; i < aligned_ndw; i++)
 190                         state->pm4[i] = 0xffff1000; /* type3 nop packet */
 191         }
 192
 193         pipe_buffer_write(&sctx->b.b, &state->indirect_buffer->b.b,
 194                           0, aligned_ndw *4, state->pm4);
 195 }