src/gallium/drivers/radeonsi/si_pm4.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "radeon/r600_cs.h"
  26 #include "util/u_memory.h"
  27 #include "si_pipe.h"
  28 #include "sid.h"
  29
  30 void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode)
  31 {
  32         state->last_opcode = opcode;
  33         state->last_pm4 = state->ndw++;
  34 }
  35
  36 void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw)
  37 {
  38         state->pm4[state->ndw++] = dw;
  39 }
  40
  41 void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate)
  42 {
  43         unsigned count;
  44         count = state->ndw - state->last_pm4 - 2;
  45         state->pm4[state->last_pm4] =
  46                 PKT3(state->last_opcode, count, predicate);
  47
  48         assert(state->ndw <= SI_PM4_MAX_DW);
  49 }
  50
  51 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
  52 {
  53         unsigned opcode;
  54
  55         if (reg >= SI_CONFIG_REG_OFFSET && reg < SI_CONFIG_REG_END) {
  56                 opcode = PKT3_SET_CONFIG_REG;
  57                 reg -= SI_CONFIG_REG_OFFSET;
  58
  59         } else if (reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END) {
  60                 opcode = PKT3_SET_SH_REG;
  61                 reg -= SI_SH_REG_OFFSET;
  62
  63         } else if (reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END) {
  64                 opcode = PKT3_SET_CONTEXT_REG;
  65                 reg -= SI_CONTEXT_REG_OFFSET;
  66
  67         } else if (reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END) {
  68                 opcode = PKT3_SET_UCONFIG_REG;
  69                 reg -= CIK_UCONFIG_REG_OFFSET;
  70
  71         } else {
  72                 R600_ERR("Invalid register offset %08x!\n", reg);
  73                 return;
  74         }
  75
  76         reg >>= 2;
  77
  78         if (opcode != state->last_opcode || reg != (state->last_reg + 1)) {
  79                 si_pm4_cmd_begin(state, opcode);
  80                 si_pm4_cmd_add(state, reg);
  81         }
  82
  83         state->last_reg = reg;
  84         si_pm4_cmd_add(state, val);
  85         si_pm4_cmd_end(state, false);
  86 }
  87
  88 void si_pm4_add_bo(struct si_pm4_state *state,
  89                    struct r600_resource *bo,
  90                    enum radeon_bo_usage usage,
  91                    enum radeon_bo_priority priority)
  92 {
  93         unsigned idx = state->nbo++;
  94         assert(idx < SI_PM4_MAX_BO);
  95
  96         r600_resource_reference(&state->bo[idx], bo);
  97         state->bo_usage[idx] = usage;
  98         state->bo_priority[idx] = priority;
  99 }
 100
 101 void si_pm4_clear_state(struct si_pm4_state *state)
 102 {
 103         for (int i = 0; i < state->nbo; ++i)
 104                 r600_resource_reference(&state->bo[i], NULL);
 105         r600_resource_reference(&state->indirect_buffer, NULL);
 106         state->nbo = 0;
 107         state->ndw = 0;
 108 }
 109
 110 void si_pm4_free_state(struct si_context *sctx,
 111                        struct si_pm4_state *state,
 112                        unsigned idx)
 113 {
 114         if (!state)
 115                 return;
 116
 117         if (idx != ~0 && sctx->emitted.array[idx] == state) {
 118                 sctx->emitted.array[idx] = NULL;
 119         }
 120
 121         si_pm4_clear_state(state);
 122         FREE(state);
 123 }
 124
 125 void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
 126 {
 127         struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
 128
 129         for (int i = 0; i < state->nbo; ++i) {
 130                 radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs, state->bo[i],
 131                                       state->bo_usage[i], state->bo_priority[i]);
 132         }
 133
 134         if (!state->indirect_buffer) {
 135                 radeon_emit_array(cs, state->pm4, state->ndw);
 136         } else {
 137                 struct r600_resource *ib = state->indirect_buffer;
 138
 139                 radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs, ib,
 140                                           RADEON_USAGE_READ,
 141                                           RADEON_PRIO_IB2);
 142
 143                 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
 144                 radeon_emit(cs, ib->gpu_address);
 145                 radeon_emit(cs, ib->gpu_address >> 32);
 146                 radeon_emit(cs, (ib->b.b.width0 >> 2) & 0xfffff);
 147         }
 148 }
 149
 150 void si_pm4_reset_emitted(struct si_context *sctx)
 151 {
 152         memset(&sctx->emitted, 0, sizeof(sctx->emitted));
 153         sctx->dirty_states |= u_bit_consecutive(0, SI_NUM_STATES);
 154 }
 155
 156 void si_pm4_upload_indirect_buffer(struct si_context *sctx,
 157                                    struct si_pm4_state *state)
 158 {
 159         struct pipe_screen *screen = sctx->b.b.screen;
 160         unsigned aligned_ndw = align(state->ndw, 8);
 161
 162         /* only supported on CIK and later */
 163         if (sctx->b.chip_class < CIK)
 164                 return;
 165
 166         assert(state->ndw);
 167         assert(aligned_ndw <= SI_PM4_MAX_DW);
 168
 169         r600_resource_reference(&state->indirect_buffer, NULL);
 170         /* TODO: this hangs with 1024 or higher alignment on GFX9. */
 171         state->indirect_buffer = (struct r600_resource*)
 172                 si_aligned_buffer_create(screen, 0,
 173                                          PIPE_USAGE_DEFAULT, aligned_ndw * 4,
 174                                          256);
 175         if (!state->indirect_buffer)
 176                 return;
 177
 178         /* Pad the IB to 8 DWs to meet CP fetch alignment requirements. */
 179         if (sctx->screen->info.gfx_ib_pad_with_type2) {
 180                 for (int i = state->ndw; i < aligned_ndw; i++)
 181                         state->pm4[i] = 0x80000000; /* type2 nop packet */
 182         } else {
 183                 for (int i = state->ndw; i < aligned_ndw; i++)
 184                         state->pm4[i] = 0xffff1000; /* type3 nop packet */
 185         }
 186
 187         pipe_buffer_write(&sctx->b.b, &state->indirect_buffer->b.b,
 188                           0, aligned_ndw *4, state->pm4);
 189 }