7a8f5a025506f12845a4a0b2963621fc9f82b51c
[mesa.git] / src / gallium / drivers / radeonsi / si_pm4.h
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #ifndef SI_PM4_H
28 #define SI_PM4_H
29
30 #include "radeon/radeon_winsys.h"
31
32 #define SI_PM4_MAX_DW 256
33 #define SI_PM4_MAX_BO 32
34 #define SI_PM4_MAX_RELOCS 4
35
36 // forward defines
37 struct si_context;
38 enum chip_class;
39
40 struct si_pm4_state
41 {
42 /* PKT3_SET_*_REG handling */
43 unsigned last_opcode;
44 unsigned last_reg;
45 unsigned last_pm4;
46
47 /* commands for the DE */
48 unsigned ndw;
49 uint32_t pm4[SI_PM4_MAX_DW];
50
51 /* BO's referenced by this state */
52 unsigned nbo;
53 struct r600_resource *bo[SI_PM4_MAX_BO];
54 enum radeon_bo_usage bo_usage[SI_PM4_MAX_BO];
55 enum radeon_bo_priority bo_priority[SI_PM4_MAX_BO];
56
57 bool compute_pkt;
58 };
59
60 void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode);
61 void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw);
62 void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate);
63
64 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
65 void si_pm4_add_bo(struct si_pm4_state *state,
66 struct r600_resource *bo,
67 enum radeon_bo_usage usage,
68 enum radeon_bo_priority priority);
69
70 void si_pm4_free_state_simple(struct si_pm4_state *state);
71 void si_pm4_free_state(struct si_context *sctx,
72 struct si_pm4_state *state,
73 unsigned idx);
74
75 void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state);
76 void si_pm4_emit_dirty(struct si_context *sctx);
77 void si_pm4_reset_emitted(struct si_context *sctx);
78 void si_pm4_cleanup(struct si_context *sctx);
79
80 #endif