2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2014 Marek Olšák <marek.olsak@amd.com>
4 * Copyright 2018 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * on the rights to use, copy, modify, merge, publish, distribute, sub
11 * license, and/or sell copies of the Software, and to permit persons to whom
12 * the Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "util/u_memory.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/os_time.h"
32 #include "util/u_suballoc.h"
33 #include "amd/common/sid.h"
35 #define SI_MAX_STREAMS 4
37 struct si_hw_query_params
{
38 unsigned start_offset
;
40 unsigned fence_offset
;
45 /* Queries without buffer handling or suspend/resume. */
49 uint64_t begin_result
;
55 /* Fence for GPU_FINISHED. */
56 struct pipe_fence_handle
*fence
;
59 static void si_query_sw_destroy(struct si_screen
*sscreen
,
60 struct si_query
*rquery
)
62 struct si_query_sw
*query
= (struct si_query_sw
*)rquery
;
64 sscreen
->b
.fence_reference(&sscreen
->b
, &query
->fence
, NULL
);
68 static enum radeon_value_id
winsys_id_from_type(unsigned type
)
71 case SI_QUERY_REQUESTED_VRAM
: return RADEON_REQUESTED_VRAM_MEMORY
;
72 case SI_QUERY_REQUESTED_GTT
: return RADEON_REQUESTED_GTT_MEMORY
;
73 case SI_QUERY_MAPPED_VRAM
: return RADEON_MAPPED_VRAM
;
74 case SI_QUERY_MAPPED_GTT
: return RADEON_MAPPED_GTT
;
75 case SI_QUERY_BUFFER_WAIT_TIME
: return RADEON_BUFFER_WAIT_TIME_NS
;
76 case SI_QUERY_NUM_MAPPED_BUFFERS
: return RADEON_NUM_MAPPED_BUFFERS
;
77 case SI_QUERY_NUM_GFX_IBS
: return RADEON_NUM_GFX_IBS
;
78 case SI_QUERY_NUM_SDMA_IBS
: return RADEON_NUM_SDMA_IBS
;
79 case SI_QUERY_GFX_BO_LIST_SIZE
: return RADEON_GFX_BO_LIST_COUNTER
;
80 case SI_QUERY_GFX_IB_SIZE
: return RADEON_GFX_IB_SIZE_COUNTER
;
81 case SI_QUERY_NUM_BYTES_MOVED
: return RADEON_NUM_BYTES_MOVED
;
82 case SI_QUERY_NUM_EVICTIONS
: return RADEON_NUM_EVICTIONS
;
83 case SI_QUERY_NUM_VRAM_CPU_PAGE_FAULTS
: return RADEON_NUM_VRAM_CPU_PAGE_FAULTS
;
84 case SI_QUERY_VRAM_USAGE
: return RADEON_VRAM_USAGE
;
85 case SI_QUERY_VRAM_VIS_USAGE
: return RADEON_VRAM_VIS_USAGE
;
86 case SI_QUERY_GTT_USAGE
: return RADEON_GTT_USAGE
;
87 case SI_QUERY_GPU_TEMPERATURE
: return RADEON_GPU_TEMPERATURE
;
88 case SI_QUERY_CURRENT_GPU_SCLK
: return RADEON_CURRENT_SCLK
;
89 case SI_QUERY_CURRENT_GPU_MCLK
: return RADEON_CURRENT_MCLK
;
90 case SI_QUERY_CS_THREAD_BUSY
: return RADEON_CS_THREAD_TIME
;
91 default: unreachable("query type does not correspond to winsys id");
95 static bool si_query_sw_begin(struct si_context
*sctx
,
96 struct si_query
*rquery
)
98 struct si_query_sw
*query
= (struct si_query_sw
*)rquery
;
99 enum radeon_value_id ws_id
;
101 switch(query
->b
.type
) {
102 case PIPE_QUERY_TIMESTAMP_DISJOINT
:
103 case PIPE_QUERY_GPU_FINISHED
:
105 case SI_QUERY_DRAW_CALLS
:
106 query
->begin_result
= sctx
->num_draw_calls
;
108 case SI_QUERY_DECOMPRESS_CALLS
:
109 query
->begin_result
= sctx
->num_decompress_calls
;
111 case SI_QUERY_MRT_DRAW_CALLS
:
112 query
->begin_result
= sctx
->num_mrt_draw_calls
;
114 case SI_QUERY_PRIM_RESTART_CALLS
:
115 query
->begin_result
= sctx
->num_prim_restart_calls
;
117 case SI_QUERY_SPILL_DRAW_CALLS
:
118 query
->begin_result
= sctx
->num_spill_draw_calls
;
120 case SI_QUERY_COMPUTE_CALLS
:
121 query
->begin_result
= sctx
->num_compute_calls
;
123 case SI_QUERY_SPILL_COMPUTE_CALLS
:
124 query
->begin_result
= sctx
->num_spill_compute_calls
;
126 case SI_QUERY_DMA_CALLS
:
127 query
->begin_result
= sctx
->num_dma_calls
;
129 case SI_QUERY_CP_DMA_CALLS
:
130 query
->begin_result
= sctx
->num_cp_dma_calls
;
132 case SI_QUERY_NUM_VS_FLUSHES
:
133 query
->begin_result
= sctx
->num_vs_flushes
;
135 case SI_QUERY_NUM_PS_FLUSHES
:
136 query
->begin_result
= sctx
->num_ps_flushes
;
138 case SI_QUERY_NUM_CS_FLUSHES
:
139 query
->begin_result
= sctx
->num_cs_flushes
;
141 case SI_QUERY_NUM_CB_CACHE_FLUSHES
:
142 query
->begin_result
= sctx
->num_cb_cache_flushes
;
144 case SI_QUERY_NUM_DB_CACHE_FLUSHES
:
145 query
->begin_result
= sctx
->num_db_cache_flushes
;
147 case SI_QUERY_NUM_L2_INVALIDATES
:
148 query
->begin_result
= sctx
->num_L2_invalidates
;
150 case SI_QUERY_NUM_L2_WRITEBACKS
:
151 query
->begin_result
= sctx
->num_L2_writebacks
;
153 case SI_QUERY_NUM_RESIDENT_HANDLES
:
154 query
->begin_result
= sctx
->num_resident_handles
;
156 case SI_QUERY_TC_OFFLOADED_SLOTS
:
157 query
->begin_result
= sctx
->tc
? sctx
->tc
->num_offloaded_slots
: 0;
159 case SI_QUERY_TC_DIRECT_SLOTS
:
160 query
->begin_result
= sctx
->tc
? sctx
->tc
->num_direct_slots
: 0;
162 case SI_QUERY_TC_NUM_SYNCS
:
163 query
->begin_result
= sctx
->tc
? sctx
->tc
->num_syncs
: 0;
165 case SI_QUERY_REQUESTED_VRAM
:
166 case SI_QUERY_REQUESTED_GTT
:
167 case SI_QUERY_MAPPED_VRAM
:
168 case SI_QUERY_MAPPED_GTT
:
169 case SI_QUERY_VRAM_USAGE
:
170 case SI_QUERY_VRAM_VIS_USAGE
:
171 case SI_QUERY_GTT_USAGE
:
172 case SI_QUERY_GPU_TEMPERATURE
:
173 case SI_QUERY_CURRENT_GPU_SCLK
:
174 case SI_QUERY_CURRENT_GPU_MCLK
:
175 case SI_QUERY_BACK_BUFFER_PS_DRAW_RATIO
:
176 case SI_QUERY_NUM_MAPPED_BUFFERS
:
177 query
->begin_result
= 0;
179 case SI_QUERY_BUFFER_WAIT_TIME
:
180 case SI_QUERY_GFX_IB_SIZE
:
181 case SI_QUERY_NUM_GFX_IBS
:
182 case SI_QUERY_NUM_SDMA_IBS
:
183 case SI_QUERY_NUM_BYTES_MOVED
:
184 case SI_QUERY_NUM_EVICTIONS
:
185 case SI_QUERY_NUM_VRAM_CPU_PAGE_FAULTS
: {
186 enum radeon_value_id ws_id
= winsys_id_from_type(query
->b
.type
);
187 query
->begin_result
= sctx
->ws
->query_value(sctx
->ws
, ws_id
);
190 case SI_QUERY_GFX_BO_LIST_SIZE
:
191 ws_id
= winsys_id_from_type(query
->b
.type
);
192 query
->begin_result
= sctx
->ws
->query_value(sctx
->ws
, ws_id
);
193 query
->begin_time
= sctx
->ws
->query_value(sctx
->ws
,
196 case SI_QUERY_CS_THREAD_BUSY
:
197 ws_id
= winsys_id_from_type(query
->b
.type
);
198 query
->begin_result
= sctx
->ws
->query_value(sctx
->ws
, ws_id
);
199 query
->begin_time
= os_time_get_nano();
201 case SI_QUERY_GALLIUM_THREAD_BUSY
:
202 query
->begin_result
=
203 sctx
->tc
? util_queue_get_thread_time_nano(&sctx
->tc
->queue
, 0) : 0;
204 query
->begin_time
= os_time_get_nano();
206 case SI_QUERY_GPU_LOAD
:
207 case SI_QUERY_GPU_SHADERS_BUSY
:
208 case SI_QUERY_GPU_TA_BUSY
:
209 case SI_QUERY_GPU_GDS_BUSY
:
210 case SI_QUERY_GPU_VGT_BUSY
:
211 case SI_QUERY_GPU_IA_BUSY
:
212 case SI_QUERY_GPU_SX_BUSY
:
213 case SI_QUERY_GPU_WD_BUSY
:
214 case SI_QUERY_GPU_BCI_BUSY
:
215 case SI_QUERY_GPU_SC_BUSY
:
216 case SI_QUERY_GPU_PA_BUSY
:
217 case SI_QUERY_GPU_DB_BUSY
:
218 case SI_QUERY_GPU_CP_BUSY
:
219 case SI_QUERY_GPU_CB_BUSY
:
220 case SI_QUERY_GPU_SDMA_BUSY
:
221 case SI_QUERY_GPU_PFP_BUSY
:
222 case SI_QUERY_GPU_MEQ_BUSY
:
223 case SI_QUERY_GPU_ME_BUSY
:
224 case SI_QUERY_GPU_SURF_SYNC_BUSY
:
225 case SI_QUERY_GPU_CP_DMA_BUSY
:
226 case SI_QUERY_GPU_SCRATCH_RAM_BUSY
:
227 query
->begin_result
= si_begin_counter(sctx
->screen
,
230 case SI_QUERY_NUM_COMPILATIONS
:
231 query
->begin_result
= p_atomic_read(&sctx
->screen
->num_compilations
);
233 case SI_QUERY_NUM_SHADERS_CREATED
:
234 query
->begin_result
= p_atomic_read(&sctx
->screen
->num_shaders_created
);
236 case SI_QUERY_NUM_SHADER_CACHE_HITS
:
237 query
->begin_result
=
238 p_atomic_read(&sctx
->screen
->num_shader_cache_hits
);
240 case SI_QUERY_GPIN_ASIC_ID
:
241 case SI_QUERY_GPIN_NUM_SIMD
:
242 case SI_QUERY_GPIN_NUM_RB
:
243 case SI_QUERY_GPIN_NUM_SPI
:
244 case SI_QUERY_GPIN_NUM_SE
:
247 unreachable("si_query_sw_begin: bad query type");
253 static bool si_query_sw_end(struct si_context
*sctx
,
254 struct si_query
*rquery
)
256 struct si_query_sw
*query
= (struct si_query_sw
*)rquery
;
257 enum radeon_value_id ws_id
;
259 switch(query
->b
.type
) {
260 case PIPE_QUERY_TIMESTAMP_DISJOINT
:
262 case PIPE_QUERY_GPU_FINISHED
:
263 sctx
->b
.flush(&sctx
->b
, &query
->fence
, PIPE_FLUSH_DEFERRED
);
265 case SI_QUERY_DRAW_CALLS
:
266 query
->end_result
= sctx
->num_draw_calls
;
268 case SI_QUERY_DECOMPRESS_CALLS
:
269 query
->end_result
= sctx
->num_decompress_calls
;
271 case SI_QUERY_MRT_DRAW_CALLS
:
272 query
->end_result
= sctx
->num_mrt_draw_calls
;
274 case SI_QUERY_PRIM_RESTART_CALLS
:
275 query
->end_result
= sctx
->num_prim_restart_calls
;
277 case SI_QUERY_SPILL_DRAW_CALLS
:
278 query
->end_result
= sctx
->num_spill_draw_calls
;
280 case SI_QUERY_COMPUTE_CALLS
:
281 query
->end_result
= sctx
->num_compute_calls
;
283 case SI_QUERY_SPILL_COMPUTE_CALLS
:
284 query
->end_result
= sctx
->num_spill_compute_calls
;
286 case SI_QUERY_DMA_CALLS
:
287 query
->end_result
= sctx
->num_dma_calls
;
289 case SI_QUERY_CP_DMA_CALLS
:
290 query
->end_result
= sctx
->num_cp_dma_calls
;
292 case SI_QUERY_NUM_VS_FLUSHES
:
293 query
->end_result
= sctx
->num_vs_flushes
;
295 case SI_QUERY_NUM_PS_FLUSHES
:
296 query
->end_result
= sctx
->num_ps_flushes
;
298 case SI_QUERY_NUM_CS_FLUSHES
:
299 query
->end_result
= sctx
->num_cs_flushes
;
301 case SI_QUERY_NUM_CB_CACHE_FLUSHES
:
302 query
->end_result
= sctx
->num_cb_cache_flushes
;
304 case SI_QUERY_NUM_DB_CACHE_FLUSHES
:
305 query
->end_result
= sctx
->num_db_cache_flushes
;
307 case SI_QUERY_NUM_L2_INVALIDATES
:
308 query
->end_result
= sctx
->num_L2_invalidates
;
310 case SI_QUERY_NUM_L2_WRITEBACKS
:
311 query
->end_result
= sctx
->num_L2_writebacks
;
313 case SI_QUERY_NUM_RESIDENT_HANDLES
:
314 query
->end_result
= sctx
->num_resident_handles
;
316 case SI_QUERY_TC_OFFLOADED_SLOTS
:
317 query
->end_result
= sctx
->tc
? sctx
->tc
->num_offloaded_slots
: 0;
319 case SI_QUERY_TC_DIRECT_SLOTS
:
320 query
->end_result
= sctx
->tc
? sctx
->tc
->num_direct_slots
: 0;
322 case SI_QUERY_TC_NUM_SYNCS
:
323 query
->end_result
= sctx
->tc
? sctx
->tc
->num_syncs
: 0;
325 case SI_QUERY_REQUESTED_VRAM
:
326 case SI_QUERY_REQUESTED_GTT
:
327 case SI_QUERY_MAPPED_VRAM
:
328 case SI_QUERY_MAPPED_GTT
:
329 case SI_QUERY_VRAM_USAGE
:
330 case SI_QUERY_VRAM_VIS_USAGE
:
331 case SI_QUERY_GTT_USAGE
:
332 case SI_QUERY_GPU_TEMPERATURE
:
333 case SI_QUERY_CURRENT_GPU_SCLK
:
334 case SI_QUERY_CURRENT_GPU_MCLK
:
335 case SI_QUERY_BUFFER_WAIT_TIME
:
336 case SI_QUERY_GFX_IB_SIZE
:
337 case SI_QUERY_NUM_MAPPED_BUFFERS
:
338 case SI_QUERY_NUM_GFX_IBS
:
339 case SI_QUERY_NUM_SDMA_IBS
:
340 case SI_QUERY_NUM_BYTES_MOVED
:
341 case SI_QUERY_NUM_EVICTIONS
:
342 case SI_QUERY_NUM_VRAM_CPU_PAGE_FAULTS
: {
343 enum radeon_value_id ws_id
= winsys_id_from_type(query
->b
.type
);
344 query
->end_result
= sctx
->ws
->query_value(sctx
->ws
, ws_id
);
347 case SI_QUERY_GFX_BO_LIST_SIZE
:
348 ws_id
= winsys_id_from_type(query
->b
.type
);
349 query
->end_result
= sctx
->ws
->query_value(sctx
->ws
, ws_id
);
350 query
->end_time
= sctx
->ws
->query_value(sctx
->ws
,
353 case SI_QUERY_CS_THREAD_BUSY
:
354 ws_id
= winsys_id_from_type(query
->b
.type
);
355 query
->end_result
= sctx
->ws
->query_value(sctx
->ws
, ws_id
);
356 query
->end_time
= os_time_get_nano();
358 case SI_QUERY_GALLIUM_THREAD_BUSY
:
360 sctx
->tc
? util_queue_get_thread_time_nano(&sctx
->tc
->queue
, 0) : 0;
361 query
->end_time
= os_time_get_nano();
363 case SI_QUERY_GPU_LOAD
:
364 case SI_QUERY_GPU_SHADERS_BUSY
:
365 case SI_QUERY_GPU_TA_BUSY
:
366 case SI_QUERY_GPU_GDS_BUSY
:
367 case SI_QUERY_GPU_VGT_BUSY
:
368 case SI_QUERY_GPU_IA_BUSY
:
369 case SI_QUERY_GPU_SX_BUSY
:
370 case SI_QUERY_GPU_WD_BUSY
:
371 case SI_QUERY_GPU_BCI_BUSY
:
372 case SI_QUERY_GPU_SC_BUSY
:
373 case SI_QUERY_GPU_PA_BUSY
:
374 case SI_QUERY_GPU_DB_BUSY
:
375 case SI_QUERY_GPU_CP_BUSY
:
376 case SI_QUERY_GPU_CB_BUSY
:
377 case SI_QUERY_GPU_SDMA_BUSY
:
378 case SI_QUERY_GPU_PFP_BUSY
:
379 case SI_QUERY_GPU_MEQ_BUSY
:
380 case SI_QUERY_GPU_ME_BUSY
:
381 case SI_QUERY_GPU_SURF_SYNC_BUSY
:
382 case SI_QUERY_GPU_CP_DMA_BUSY
:
383 case SI_QUERY_GPU_SCRATCH_RAM_BUSY
:
384 query
->end_result
= si_end_counter(sctx
->screen
,
386 query
->begin_result
);
387 query
->begin_result
= 0;
389 case SI_QUERY_NUM_COMPILATIONS
:
390 query
->end_result
= p_atomic_read(&sctx
->screen
->num_compilations
);
392 case SI_QUERY_NUM_SHADERS_CREATED
:
393 query
->end_result
= p_atomic_read(&sctx
->screen
->num_shaders_created
);
395 case SI_QUERY_BACK_BUFFER_PS_DRAW_RATIO
:
396 query
->end_result
= sctx
->last_tex_ps_draw_ratio
;
398 case SI_QUERY_NUM_SHADER_CACHE_HITS
:
400 p_atomic_read(&sctx
->screen
->num_shader_cache_hits
);
402 case SI_QUERY_GPIN_ASIC_ID
:
403 case SI_QUERY_GPIN_NUM_SIMD
:
404 case SI_QUERY_GPIN_NUM_RB
:
405 case SI_QUERY_GPIN_NUM_SPI
:
406 case SI_QUERY_GPIN_NUM_SE
:
409 unreachable("si_query_sw_end: bad query type");
415 static bool si_query_sw_get_result(struct si_context
*sctx
,
416 struct si_query
*rquery
,
418 union pipe_query_result
*result
)
420 struct si_query_sw
*query
= (struct si_query_sw
*)rquery
;
422 switch (query
->b
.type
) {
423 case PIPE_QUERY_TIMESTAMP_DISJOINT
:
424 /* Convert from cycles per millisecond to cycles per second (Hz). */
425 result
->timestamp_disjoint
.frequency
=
426 (uint64_t)sctx
->screen
->info
.clock_crystal_freq
* 1000;
427 result
->timestamp_disjoint
.disjoint
= false;
429 case PIPE_QUERY_GPU_FINISHED
: {
430 struct pipe_screen
*screen
= sctx
->b
.screen
;
431 struct pipe_context
*ctx
= rquery
->b
.flushed
? NULL
: &sctx
->b
;
433 result
->b
= screen
->fence_finish(screen
, ctx
, query
->fence
,
434 wait
? PIPE_TIMEOUT_INFINITE
: 0);
438 case SI_QUERY_GFX_BO_LIST_SIZE
:
439 result
->u64
= (query
->end_result
- query
->begin_result
) /
440 (query
->end_time
- query
->begin_time
);
442 case SI_QUERY_CS_THREAD_BUSY
:
443 case SI_QUERY_GALLIUM_THREAD_BUSY
:
444 result
->u64
= (query
->end_result
- query
->begin_result
) * 100 /
445 (query
->end_time
- query
->begin_time
);
447 case SI_QUERY_GPIN_ASIC_ID
:
450 case SI_QUERY_GPIN_NUM_SIMD
:
451 result
->u32
= sctx
->screen
->info
.num_good_compute_units
;
453 case SI_QUERY_GPIN_NUM_RB
:
454 result
->u32
= sctx
->screen
->info
.num_render_backends
;
456 case SI_QUERY_GPIN_NUM_SPI
:
457 result
->u32
= 1; /* all supported chips have one SPI per SE */
459 case SI_QUERY_GPIN_NUM_SE
:
460 result
->u32
= sctx
->screen
->info
.max_se
;
464 result
->u64
= query
->end_result
- query
->begin_result
;
466 switch (query
->b
.type
) {
467 case SI_QUERY_BUFFER_WAIT_TIME
:
468 case SI_QUERY_GPU_TEMPERATURE
:
471 case SI_QUERY_CURRENT_GPU_SCLK
:
472 case SI_QUERY_CURRENT_GPU_MCLK
:
473 result
->u64
*= 1000000;
481 static struct si_query_ops sw_query_ops
= {
482 .destroy
= si_query_sw_destroy
,
483 .begin
= si_query_sw_begin
,
484 .end
= si_query_sw_end
,
485 .get_result
= si_query_sw_get_result
,
486 .get_result_resource
= NULL
489 static struct pipe_query
*si_query_sw_create(unsigned query_type
)
491 struct si_query_sw
*query
;
493 query
= CALLOC_STRUCT(si_query_sw
);
497 query
->b
.type
= query_type
;
498 query
->b
.ops
= &sw_query_ops
;
500 return (struct pipe_query
*)query
;
503 void si_query_hw_destroy(struct si_screen
*sscreen
,
504 struct si_query
*rquery
)
506 struct si_query_hw
*query
= (struct si_query_hw
*)rquery
;
507 struct si_query_buffer
*prev
= query
->buffer
.previous
;
509 /* Release all query buffers. */
511 struct si_query_buffer
*qbuf
= prev
;
512 prev
= prev
->previous
;
513 r600_resource_reference(&qbuf
->buf
, NULL
);
517 r600_resource_reference(&query
->buffer
.buf
, NULL
);
518 r600_resource_reference(&query
->workaround_buf
, NULL
);
522 static struct r600_resource
*si_new_query_buffer(struct si_screen
*sscreen
,
523 struct si_query_hw
*query
)
525 unsigned buf_size
= MAX2(query
->result_size
,
526 sscreen
->info
.min_alloc_size
);
528 /* Queries are normally read by the CPU after
529 * being written by the gpu, hence staging is probably a good
532 struct r600_resource
*buf
= r600_resource(
533 pipe_buffer_create(&sscreen
->b
, 0,
534 PIPE_USAGE_STAGING
, buf_size
));
538 if (!query
->ops
->prepare_buffer(sscreen
, query
, buf
)) {
539 r600_resource_reference(&buf
, NULL
);
546 static bool si_query_hw_prepare_buffer(struct si_screen
*sscreen
,
547 struct si_query_hw
*query
,
548 struct r600_resource
*buffer
)
550 /* Callers ensure that the buffer is currently unused by the GPU. */
551 uint32_t *results
= sscreen
->ws
->buffer_map(buffer
->buf
, NULL
,
552 PIPE_TRANSFER_WRITE
|
553 PIPE_TRANSFER_UNSYNCHRONIZED
);
557 memset(results
, 0, buffer
->b
.b
.width0
);
559 if (query
->b
.type
== PIPE_QUERY_OCCLUSION_COUNTER
||
560 query
->b
.type
== PIPE_QUERY_OCCLUSION_PREDICATE
||
561 query
->b
.type
== PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
) {
562 unsigned max_rbs
= sscreen
->info
.num_render_backends
;
563 unsigned enabled_rb_mask
= sscreen
->info
.enabled_rb_mask
;
564 unsigned num_results
;
567 /* Set top bits for unused backends. */
568 num_results
= buffer
->b
.b
.width0
/ query
->result_size
;
569 for (j
= 0; j
< num_results
; j
++) {
570 for (i
= 0; i
< max_rbs
; i
++) {
571 if (!(enabled_rb_mask
& (1<<i
))) {
572 results
[(i
* 4)+1] = 0x80000000;
573 results
[(i
* 4)+3] = 0x80000000;
576 results
+= 4 * max_rbs
;
583 static void si_query_hw_get_result_resource(struct si_context
*sctx
,
584 struct si_query
*rquery
,
586 enum pipe_query_value_type result_type
,
588 struct pipe_resource
*resource
,
591 static struct si_query_ops query_hw_ops
= {
592 .destroy
= si_query_hw_destroy
,
593 .begin
= si_query_hw_begin
,
594 .end
= si_query_hw_end
,
595 .get_result
= si_query_hw_get_result
,
596 .get_result_resource
= si_query_hw_get_result_resource
,
599 static void si_query_hw_do_emit_start(struct si_context
*sctx
,
600 struct si_query_hw
*query
,
601 struct r600_resource
*buffer
,
603 static void si_query_hw_do_emit_stop(struct si_context
*sctx
,
604 struct si_query_hw
*query
,
605 struct r600_resource
*buffer
,
607 static void si_query_hw_add_result(struct si_screen
*sscreen
,
608 struct si_query_hw
*, void *buffer
,
609 union pipe_query_result
*result
);
610 static void si_query_hw_clear_result(struct si_query_hw
*,
611 union pipe_query_result
*);
613 static struct si_query_hw_ops query_hw_default_hw_ops
= {
614 .prepare_buffer
= si_query_hw_prepare_buffer
,
615 .emit_start
= si_query_hw_do_emit_start
,
616 .emit_stop
= si_query_hw_do_emit_stop
,
617 .clear_result
= si_query_hw_clear_result
,
618 .add_result
= si_query_hw_add_result
,
621 bool si_query_hw_init(struct si_screen
*sscreen
,
622 struct si_query_hw
*query
)
624 query
->buffer
.buf
= si_new_query_buffer(sscreen
, query
);
625 if (!query
->buffer
.buf
)
631 static struct pipe_query
*si_query_hw_create(struct si_screen
*sscreen
,
635 struct si_query_hw
*query
= CALLOC_STRUCT(si_query_hw
);
639 query
->b
.type
= query_type
;
640 query
->b
.ops
= &query_hw_ops
;
641 query
->ops
= &query_hw_default_hw_ops
;
643 switch (query_type
) {
644 case PIPE_QUERY_OCCLUSION_COUNTER
:
645 case PIPE_QUERY_OCCLUSION_PREDICATE
:
646 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
647 query
->result_size
= 16 * sscreen
->info
.num_render_backends
;
648 query
->result_size
+= 16; /* for the fence + alignment */
649 query
->num_cs_dw_end
= 6 + si_gfx_write_fence_dwords(sscreen
);
651 case SI_QUERY_TIME_ELAPSED_SDMA
:
652 /* GET_GLOBAL_TIMESTAMP only works if the offset is a multiple of 32. */
653 query
->result_size
= 64;
654 query
->num_cs_dw_end
= 0;
656 case PIPE_QUERY_TIME_ELAPSED
:
657 query
->result_size
= 24;
658 query
->num_cs_dw_end
= 8 + si_gfx_write_fence_dwords(sscreen
);
660 case PIPE_QUERY_TIMESTAMP
:
661 query
->result_size
= 16;
662 query
->num_cs_dw_end
= 8 + si_gfx_write_fence_dwords(sscreen
);
663 query
->flags
= SI_QUERY_HW_FLAG_NO_START
;
665 case PIPE_QUERY_PRIMITIVES_EMITTED
:
666 case PIPE_QUERY_PRIMITIVES_GENERATED
:
667 case PIPE_QUERY_SO_STATISTICS
:
668 case PIPE_QUERY_SO_OVERFLOW_PREDICATE
:
669 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
670 query
->result_size
= 32;
671 query
->num_cs_dw_end
= 6;
672 query
->stream
= index
;
674 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE
:
675 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
676 query
->result_size
= 32 * SI_MAX_STREAMS
;
677 query
->num_cs_dw_end
= 6 * SI_MAX_STREAMS
;
679 case PIPE_QUERY_PIPELINE_STATISTICS
:
680 /* 11 values on GCN. */
681 query
->result_size
= 11 * 16;
682 query
->result_size
+= 8; /* for the fence + alignment */
683 query
->num_cs_dw_end
= 6 + si_gfx_write_fence_dwords(sscreen
);
691 if (!si_query_hw_init(sscreen
, query
)) {
696 return (struct pipe_query
*)query
;
699 static void si_update_occlusion_query_state(struct si_context
*sctx
,
700 unsigned type
, int diff
)
702 if (type
== PIPE_QUERY_OCCLUSION_COUNTER
||
703 type
== PIPE_QUERY_OCCLUSION_PREDICATE
||
704 type
== PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
) {
705 bool old_enable
= sctx
->num_occlusion_queries
!= 0;
706 bool old_perfect_enable
=
707 sctx
->num_perfect_occlusion_queries
!= 0;
708 bool enable
, perfect_enable
;
710 sctx
->num_occlusion_queries
+= diff
;
711 assert(sctx
->num_occlusion_queries
>= 0);
713 if (type
!= PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
) {
714 sctx
->num_perfect_occlusion_queries
+= diff
;
715 assert(sctx
->num_perfect_occlusion_queries
>= 0);
718 enable
= sctx
->num_occlusion_queries
!= 0;
719 perfect_enable
= sctx
->num_perfect_occlusion_queries
!= 0;
721 if (enable
!= old_enable
|| perfect_enable
!= old_perfect_enable
) {
722 si_set_occlusion_query_state(sctx
, old_perfect_enable
);
727 static unsigned event_type_for_stream(unsigned stream
)
731 case 0: return V_028A90_SAMPLE_STREAMOUTSTATS
;
732 case 1: return V_028A90_SAMPLE_STREAMOUTSTATS1
;
733 case 2: return V_028A90_SAMPLE_STREAMOUTSTATS2
;
734 case 3: return V_028A90_SAMPLE_STREAMOUTSTATS3
;
738 static void emit_sample_streamout(struct radeon_cmdbuf
*cs
, uint64_t va
,
741 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
742 radeon_emit(cs
, EVENT_TYPE(event_type_for_stream(stream
)) | EVENT_INDEX(3));
744 radeon_emit(cs
, va
>> 32);
747 static void si_query_hw_do_emit_start(struct si_context
*sctx
,
748 struct si_query_hw
*query
,
749 struct r600_resource
*buffer
,
752 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
754 switch (query
->b
.type
) {
755 case SI_QUERY_TIME_ELAPSED_SDMA
:
756 si_dma_emit_timestamp(sctx
, buffer
, va
- buffer
->gpu_address
);
758 case PIPE_QUERY_OCCLUSION_COUNTER
:
759 case PIPE_QUERY_OCCLUSION_PREDICATE
:
760 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
761 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
762 radeon_emit(cs
, EVENT_TYPE(V_028A90_ZPASS_DONE
) | EVENT_INDEX(1));
764 radeon_emit(cs
, va
>> 32);
766 case PIPE_QUERY_PRIMITIVES_EMITTED
:
767 case PIPE_QUERY_PRIMITIVES_GENERATED
:
768 case PIPE_QUERY_SO_STATISTICS
:
769 case PIPE_QUERY_SO_OVERFLOW_PREDICATE
:
770 emit_sample_streamout(cs
, va
, query
->stream
);
772 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE
:
773 for (unsigned stream
= 0; stream
< SI_MAX_STREAMS
; ++stream
)
774 emit_sample_streamout(cs
, va
+ 32 * stream
, stream
);
776 case PIPE_QUERY_TIME_ELAPSED
:
777 /* Write the timestamp from the CP not waiting for
778 * outstanding draws (top-of-pipe).
780 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
781 radeon_emit(cs
, COPY_DATA_COUNT_SEL
|
782 COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP
) |
783 COPY_DATA_DST_SEL(COPY_DATA_MEM_ASYNC
));
787 radeon_emit(cs
, va
>> 32);
789 case PIPE_QUERY_PIPELINE_STATISTICS
:
790 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
791 radeon_emit(cs
, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT
) | EVENT_INDEX(2));
793 radeon_emit(cs
, va
>> 32);
798 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, query
->buffer
.buf
, RADEON_USAGE_WRITE
,
802 static void si_query_hw_emit_start(struct si_context
*sctx
,
803 struct si_query_hw
*query
)
807 if (!query
->buffer
.buf
)
808 return; // previous buffer allocation failure
810 si_update_occlusion_query_state(sctx
, query
->b
.type
, 1);
811 si_update_prims_generated_query_state(sctx
, query
->b
.type
, 1);
813 if (query
->b
.type
!= SI_QUERY_TIME_ELAPSED_SDMA
)
814 si_need_gfx_cs_space(sctx
);
816 /* Get a new query buffer if needed. */
817 if (query
->buffer
.results_end
+ query
->result_size
> query
->buffer
.buf
->b
.b
.width0
) {
818 struct si_query_buffer
*qbuf
= MALLOC_STRUCT(si_query_buffer
);
819 *qbuf
= query
->buffer
;
820 query
->buffer
.results_end
= 0;
821 query
->buffer
.previous
= qbuf
;
822 query
->buffer
.buf
= si_new_query_buffer(sctx
->screen
, query
);
823 if (!query
->buffer
.buf
)
827 /* emit begin query */
828 va
= query
->buffer
.buf
->gpu_address
+ query
->buffer
.results_end
;
830 query
->ops
->emit_start(sctx
, query
, query
->buffer
.buf
, va
);
832 sctx
->num_cs_dw_queries_suspend
+= query
->num_cs_dw_end
;
835 static void si_query_hw_do_emit_stop(struct si_context
*sctx
,
836 struct si_query_hw
*query
,
837 struct r600_resource
*buffer
,
840 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
841 uint64_t fence_va
= 0;
843 switch (query
->b
.type
) {
844 case SI_QUERY_TIME_ELAPSED_SDMA
:
845 si_dma_emit_timestamp(sctx
, buffer
, va
+ 32 - buffer
->gpu_address
);
847 case PIPE_QUERY_OCCLUSION_COUNTER
:
848 case PIPE_QUERY_OCCLUSION_PREDICATE
:
849 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
851 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
852 radeon_emit(cs
, EVENT_TYPE(V_028A90_ZPASS_DONE
) | EVENT_INDEX(1));
854 radeon_emit(cs
, va
>> 32);
856 fence_va
= va
+ sctx
->screen
->info
.num_render_backends
* 16 - 8;
858 case PIPE_QUERY_PRIMITIVES_EMITTED
:
859 case PIPE_QUERY_PRIMITIVES_GENERATED
:
860 case PIPE_QUERY_SO_STATISTICS
:
861 case PIPE_QUERY_SO_OVERFLOW_PREDICATE
:
863 emit_sample_streamout(cs
, va
, query
->stream
);
865 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE
:
867 for (unsigned stream
= 0; stream
< SI_MAX_STREAMS
; ++stream
)
868 emit_sample_streamout(cs
, va
+ 32 * stream
, stream
);
870 case PIPE_QUERY_TIME_ELAPSED
:
873 case PIPE_QUERY_TIMESTAMP
:
874 si_gfx_write_event_eop(sctx
, V_028A90_BOTTOM_OF_PIPE_TS
,
875 0, EOP_DATA_SEL_TIMESTAMP
, NULL
, va
,
879 case PIPE_QUERY_PIPELINE_STATISTICS
: {
880 unsigned sample_size
= (query
->result_size
- 8) / 2;
883 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
884 radeon_emit(cs
, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT
) | EVENT_INDEX(2));
886 radeon_emit(cs
, va
>> 32);
888 fence_va
= va
+ sample_size
;
894 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, query
->buffer
.buf
, RADEON_USAGE_WRITE
,
898 si_gfx_write_event_eop(sctx
, V_028A90_BOTTOM_OF_PIPE_TS
, 0,
899 EOP_DATA_SEL_VALUE_32BIT
,
900 query
->buffer
.buf
, fence_va
, 0x80000000,
904 static void si_query_hw_emit_stop(struct si_context
*sctx
,
905 struct si_query_hw
*query
)
909 if (!query
->buffer
.buf
)
910 return; // previous buffer allocation failure
912 /* The queries which need begin already called this in begin_query. */
913 if (query
->flags
& SI_QUERY_HW_FLAG_NO_START
)
914 si_need_gfx_cs_space(sctx
);
917 va
= query
->buffer
.buf
->gpu_address
+ query
->buffer
.results_end
;
919 query
->ops
->emit_stop(sctx
, query
, query
->buffer
.buf
, va
);
921 query
->buffer
.results_end
+= query
->result_size
;
923 if (!(query
->flags
& SI_QUERY_HW_FLAG_NO_START
))
924 sctx
->num_cs_dw_queries_suspend
-= query
->num_cs_dw_end
;
926 si_update_occlusion_query_state(sctx
, query
->b
.type
, -1);
927 si_update_prims_generated_query_state(sctx
, query
->b
.type
, -1);
930 static void emit_set_predicate(struct si_context
*ctx
,
931 struct r600_resource
*buf
, uint64_t va
,
934 struct radeon_cmdbuf
*cs
= ctx
->gfx_cs
;
936 if (ctx
->chip_class
>= GFX9
) {
937 radeon_emit(cs
, PKT3(PKT3_SET_PREDICATION
, 2, 0));
940 radeon_emit(cs
, va
>> 32);
942 radeon_emit(cs
, PKT3(PKT3_SET_PREDICATION
, 1, 0));
944 radeon_emit(cs
, op
| ((va
>> 32) & 0xFF));
946 radeon_add_to_buffer_list(ctx
, ctx
->gfx_cs
, buf
, RADEON_USAGE_READ
,
950 static void si_emit_query_predication(struct si_context
*ctx
)
952 struct si_query_hw
*query
= (struct si_query_hw
*)ctx
->render_cond
;
953 struct si_query_buffer
*qbuf
;
955 bool flag_wait
, invert
;
960 invert
= ctx
->render_cond_invert
;
961 flag_wait
= ctx
->render_cond_mode
== PIPE_RENDER_COND_WAIT
||
962 ctx
->render_cond_mode
== PIPE_RENDER_COND_BY_REGION_WAIT
;
964 if (query
->workaround_buf
) {
965 op
= PRED_OP(PREDICATION_OP_BOOL64
);
967 switch (query
->b
.type
) {
968 case PIPE_QUERY_OCCLUSION_COUNTER
:
969 case PIPE_QUERY_OCCLUSION_PREDICATE
:
970 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
971 op
= PRED_OP(PREDICATION_OP_ZPASS
);
973 case PIPE_QUERY_SO_OVERFLOW_PREDICATE
:
974 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE
:
975 op
= PRED_OP(PREDICATION_OP_PRIMCOUNT
);
984 /* if true then invert, see GL_ARB_conditional_render_inverted */
986 op
|= PREDICATION_DRAW_NOT_VISIBLE
; /* Draw if not visible or overflow */
988 op
|= PREDICATION_DRAW_VISIBLE
; /* Draw if visible or no overflow */
990 /* Use the value written by compute shader as a workaround. Note that
991 * the wait flag does not apply in this predication mode.
993 * The shader outputs the result value to L2. Workarounds only affect VI
994 * and later, where the CP reads data from L2, so we don't need an
997 if (query
->workaround_buf
) {
998 uint64_t va
= query
->workaround_buf
->gpu_address
+ query
->workaround_offset
;
999 emit_set_predicate(ctx
, query
->workaround_buf
, va
, op
);
1003 op
|= flag_wait
? PREDICATION_HINT_WAIT
: PREDICATION_HINT_NOWAIT_DRAW
;
1005 /* emit predicate packets for all data blocks */
1006 for (qbuf
= &query
->buffer
; qbuf
; qbuf
= qbuf
->previous
) {
1007 unsigned results_base
= 0;
1008 uint64_t va_base
= qbuf
->buf
->gpu_address
;
1010 while (results_base
< qbuf
->results_end
) {
1011 uint64_t va
= va_base
+ results_base
;
1013 if (query
->b
.type
== PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE
) {
1014 for (unsigned stream
= 0; stream
< SI_MAX_STREAMS
; ++stream
) {
1015 emit_set_predicate(ctx
, qbuf
->buf
, va
+ 32 * stream
, op
);
1017 /* set CONTINUE bit for all packets except the first */
1018 op
|= PREDICATION_CONTINUE
;
1021 emit_set_predicate(ctx
, qbuf
->buf
, va
, op
);
1022 op
|= PREDICATION_CONTINUE
;
1025 results_base
+= query
->result_size
;
1030 static struct pipe_query
*si_create_query(struct pipe_context
*ctx
, unsigned query_type
, unsigned index
)
1032 struct si_screen
*sscreen
=
1033 (struct si_screen
*)ctx
->screen
;
1035 if (query_type
== PIPE_QUERY_TIMESTAMP_DISJOINT
||
1036 query_type
== PIPE_QUERY_GPU_FINISHED
||
1037 (query_type
>= PIPE_QUERY_DRIVER_SPECIFIC
&&
1038 query_type
!= SI_QUERY_TIME_ELAPSED_SDMA
))
1039 return si_query_sw_create(query_type
);
1041 return si_query_hw_create(sscreen
, query_type
, index
);
1044 static void si_destroy_query(struct pipe_context
*ctx
, struct pipe_query
*query
)
1046 struct si_context
*sctx
= (struct si_context
*)ctx
;
1047 struct si_query
*rquery
= (struct si_query
*)query
;
1049 rquery
->ops
->destroy(sctx
->screen
, rquery
);
1052 static boolean
si_begin_query(struct pipe_context
*ctx
,
1053 struct pipe_query
*query
)
1055 struct si_context
*sctx
= (struct si_context
*)ctx
;
1056 struct si_query
*rquery
= (struct si_query
*)query
;
1058 return rquery
->ops
->begin(sctx
, rquery
);
1061 void si_query_hw_reset_buffers(struct si_context
*sctx
,
1062 struct si_query_hw
*query
)
1064 struct si_query_buffer
*prev
= query
->buffer
.previous
;
1066 /* Discard the old query buffers. */
1068 struct si_query_buffer
*qbuf
= prev
;
1069 prev
= prev
->previous
;
1070 r600_resource_reference(&qbuf
->buf
, NULL
);
1074 query
->buffer
.results_end
= 0;
1075 query
->buffer
.previous
= NULL
;
1077 /* Obtain a new buffer if the current one can't be mapped without a stall. */
1078 if (si_rings_is_buffer_referenced(sctx
, query
->buffer
.buf
->buf
, RADEON_USAGE_READWRITE
) ||
1079 !sctx
->ws
->buffer_wait(query
->buffer
.buf
->buf
, 0, RADEON_USAGE_READWRITE
)) {
1080 r600_resource_reference(&query
->buffer
.buf
, NULL
);
1081 query
->buffer
.buf
= si_new_query_buffer(sctx
->screen
, query
);
1083 if (!query
->ops
->prepare_buffer(sctx
->screen
, query
, query
->buffer
.buf
))
1084 r600_resource_reference(&query
->buffer
.buf
, NULL
);
1088 bool si_query_hw_begin(struct si_context
*sctx
,
1089 struct si_query
*rquery
)
1091 struct si_query_hw
*query
= (struct si_query_hw
*)rquery
;
1093 if (query
->flags
& SI_QUERY_HW_FLAG_NO_START
) {
1098 if (!(query
->flags
& SI_QUERY_HW_FLAG_BEGIN_RESUMES
))
1099 si_query_hw_reset_buffers(sctx
, query
);
1101 r600_resource_reference(&query
->workaround_buf
, NULL
);
1103 si_query_hw_emit_start(sctx
, query
);
1104 if (!query
->buffer
.buf
)
1107 LIST_ADDTAIL(&query
->list
, &sctx
->active_queries
);
1111 static bool si_end_query(struct pipe_context
*ctx
, struct pipe_query
*query
)
1113 struct si_context
*sctx
= (struct si_context
*)ctx
;
1114 struct si_query
*rquery
= (struct si_query
*)query
;
1116 return rquery
->ops
->end(sctx
, rquery
);
1119 bool si_query_hw_end(struct si_context
*sctx
,
1120 struct si_query
*rquery
)
1122 struct si_query_hw
*query
= (struct si_query_hw
*)rquery
;
1124 if (query
->flags
& SI_QUERY_HW_FLAG_NO_START
)
1125 si_query_hw_reset_buffers(sctx
, query
);
1127 si_query_hw_emit_stop(sctx
, query
);
1129 if (!(query
->flags
& SI_QUERY_HW_FLAG_NO_START
))
1130 LIST_DELINIT(&query
->list
);
1132 if (!query
->buffer
.buf
)
1138 static void si_get_hw_query_params(struct si_context
*sctx
,
1139 struct si_query_hw
*rquery
, int index
,
1140 struct si_hw_query_params
*params
)
1142 unsigned max_rbs
= sctx
->screen
->info
.num_render_backends
;
1144 params
->pair_stride
= 0;
1145 params
->pair_count
= 1;
1147 switch (rquery
->b
.type
) {
1148 case PIPE_QUERY_OCCLUSION_COUNTER
:
1149 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1150 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1151 params
->start_offset
= 0;
1152 params
->end_offset
= 8;
1153 params
->fence_offset
= max_rbs
* 16;
1154 params
->pair_stride
= 16;
1155 params
->pair_count
= max_rbs
;
1157 case PIPE_QUERY_TIME_ELAPSED
:
1158 params
->start_offset
= 0;
1159 params
->end_offset
= 8;
1160 params
->fence_offset
= 16;
1162 case PIPE_QUERY_TIMESTAMP
:
1163 params
->start_offset
= 0;
1164 params
->end_offset
= 0;
1165 params
->fence_offset
= 8;
1167 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1168 params
->start_offset
= 8;
1169 params
->end_offset
= 24;
1170 params
->fence_offset
= params
->end_offset
+ 4;
1172 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1173 params
->start_offset
= 0;
1174 params
->end_offset
= 16;
1175 params
->fence_offset
= params
->end_offset
+ 4;
1177 case PIPE_QUERY_SO_STATISTICS
:
1178 params
->start_offset
= 8 - index
* 8;
1179 params
->end_offset
= 24 - index
* 8;
1180 params
->fence_offset
= params
->end_offset
+ 4;
1182 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE
:
1183 params
->pair_count
= SI_MAX_STREAMS
;
1184 params
->pair_stride
= 32;
1185 case PIPE_QUERY_SO_OVERFLOW_PREDICATE
:
1186 params
->start_offset
= 0;
1187 params
->end_offset
= 16;
1189 /* We can re-use the high dword of the last 64-bit value as a
1190 * fence: it is initialized as 0, and the high bit is set by
1191 * the write of the streamout stats event.
1193 params
->fence_offset
= rquery
->result_size
- 4;
1195 case PIPE_QUERY_PIPELINE_STATISTICS
:
1197 static const unsigned offsets
[] = {56, 48, 24, 32, 40, 16, 8, 0, 64, 72, 80};
1198 params
->start_offset
= offsets
[index
];
1199 params
->end_offset
= 88 + offsets
[index
];
1200 params
->fence_offset
= 2 * 88;
1204 unreachable("si_get_hw_query_params unsupported");
1208 static unsigned si_query_read_result(void *map
, unsigned start_index
, unsigned end_index
,
1209 bool test_status_bit
)
1211 uint32_t *current_result
= (uint32_t*)map
;
1212 uint64_t start
, end
;
1214 start
= (uint64_t)current_result
[start_index
] |
1215 (uint64_t)current_result
[start_index
+1] << 32;
1216 end
= (uint64_t)current_result
[end_index
] |
1217 (uint64_t)current_result
[end_index
+1] << 32;
1219 if (!test_status_bit
||
1220 ((start
& 0x8000000000000000UL
) && (end
& 0x8000000000000000UL
))) {
1226 static void si_query_hw_add_result(struct si_screen
*sscreen
,
1227 struct si_query_hw
*query
,
1229 union pipe_query_result
*result
)
1231 unsigned max_rbs
= sscreen
->info
.num_render_backends
;
1233 switch (query
->b
.type
) {
1234 case PIPE_QUERY_OCCLUSION_COUNTER
: {
1235 for (unsigned i
= 0; i
< max_rbs
; ++i
) {
1236 unsigned results_base
= i
* 16;
1238 si_query_read_result(buffer
+ results_base
, 0, 2, true);
1242 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1243 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
1244 for (unsigned i
= 0; i
< max_rbs
; ++i
) {
1245 unsigned results_base
= i
* 16;
1246 result
->b
= result
->b
||
1247 si_query_read_result(buffer
+ results_base
, 0, 2, true) != 0;
1251 case PIPE_QUERY_TIME_ELAPSED
:
1252 result
->u64
+= si_query_read_result(buffer
, 0, 2, false);
1254 case SI_QUERY_TIME_ELAPSED_SDMA
:
1255 result
->u64
+= si_query_read_result(buffer
, 0, 32/4, false);
1257 case PIPE_QUERY_TIMESTAMP
:
1258 result
->u64
= *(uint64_t*)buffer
;
1260 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1261 /* SAMPLE_STREAMOUTSTATS stores this structure:
1263 * u64 NumPrimitivesWritten;
1264 * u64 PrimitiveStorageNeeded;
1266 * We only need NumPrimitivesWritten here. */
1267 result
->u64
+= si_query_read_result(buffer
, 2, 6, true);
1269 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1270 /* Here we read PrimitiveStorageNeeded. */
1271 result
->u64
+= si_query_read_result(buffer
, 0, 4, true);
1273 case PIPE_QUERY_SO_STATISTICS
:
1274 result
->so_statistics
.num_primitives_written
+=
1275 si_query_read_result(buffer
, 2, 6, true);
1276 result
->so_statistics
.primitives_storage_needed
+=
1277 si_query_read_result(buffer
, 0, 4, true);
1279 case PIPE_QUERY_SO_OVERFLOW_PREDICATE
:
1280 result
->b
= result
->b
||
1281 si_query_read_result(buffer
, 2, 6, true) !=
1282 si_query_read_result(buffer
, 0, 4, true);
1284 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE
:
1285 for (unsigned stream
= 0; stream
< SI_MAX_STREAMS
; ++stream
) {
1286 result
->b
= result
->b
||
1287 si_query_read_result(buffer
, 2, 6, true) !=
1288 si_query_read_result(buffer
, 0, 4, true);
1289 buffer
= (char *)buffer
+ 32;
1292 case PIPE_QUERY_PIPELINE_STATISTICS
:
1293 result
->pipeline_statistics
.ps_invocations
+=
1294 si_query_read_result(buffer
, 0, 22, false);
1295 result
->pipeline_statistics
.c_primitives
+=
1296 si_query_read_result(buffer
, 2, 24, false);
1297 result
->pipeline_statistics
.c_invocations
+=
1298 si_query_read_result(buffer
, 4, 26, false);
1299 result
->pipeline_statistics
.vs_invocations
+=
1300 si_query_read_result(buffer
, 6, 28, false);
1301 result
->pipeline_statistics
.gs_invocations
+=
1302 si_query_read_result(buffer
, 8, 30, false);
1303 result
->pipeline_statistics
.gs_primitives
+=
1304 si_query_read_result(buffer
, 10, 32, false);
1305 result
->pipeline_statistics
.ia_primitives
+=
1306 si_query_read_result(buffer
, 12, 34, false);
1307 result
->pipeline_statistics
.ia_vertices
+=
1308 si_query_read_result(buffer
, 14, 36, false);
1309 result
->pipeline_statistics
.hs_invocations
+=
1310 si_query_read_result(buffer
, 16, 38, false);
1311 result
->pipeline_statistics
.ds_invocations
+=
1312 si_query_read_result(buffer
, 18, 40, false);
1313 result
->pipeline_statistics
.cs_invocations
+=
1314 si_query_read_result(buffer
, 20, 42, false);
1315 #if 0 /* for testing */
1316 printf("Pipeline stats: IA verts=%llu, IA prims=%llu, VS=%llu, HS=%llu, "
1317 "DS=%llu, GS=%llu, GS prims=%llu, Clipper=%llu, "
1318 "Clipper prims=%llu, PS=%llu, CS=%llu\n",
1319 result
->pipeline_statistics
.ia_vertices
,
1320 result
->pipeline_statistics
.ia_primitives
,
1321 result
->pipeline_statistics
.vs_invocations
,
1322 result
->pipeline_statistics
.hs_invocations
,
1323 result
->pipeline_statistics
.ds_invocations
,
1324 result
->pipeline_statistics
.gs_invocations
,
1325 result
->pipeline_statistics
.gs_primitives
,
1326 result
->pipeline_statistics
.c_invocations
,
1327 result
->pipeline_statistics
.c_primitives
,
1328 result
->pipeline_statistics
.ps_invocations
,
1329 result
->pipeline_statistics
.cs_invocations
);
1337 static boolean
si_get_query_result(struct pipe_context
*ctx
,
1338 struct pipe_query
*query
, boolean wait
,
1339 union pipe_query_result
*result
)
1341 struct si_context
*sctx
= (struct si_context
*)ctx
;
1342 struct si_query
*rquery
= (struct si_query
*)query
;
1344 return rquery
->ops
->get_result(sctx
, rquery
, wait
, result
);
1347 static void si_get_query_result_resource(struct pipe_context
*ctx
,
1348 struct pipe_query
*query
,
1350 enum pipe_query_value_type result_type
,
1352 struct pipe_resource
*resource
,
1355 struct si_context
*sctx
= (struct si_context
*)ctx
;
1356 struct si_query
*rquery
= (struct si_query
*)query
;
1358 rquery
->ops
->get_result_resource(sctx
, rquery
, wait
, result_type
, index
,
1362 static void si_query_hw_clear_result(struct si_query_hw
*query
,
1363 union pipe_query_result
*result
)
1365 util_query_clear_result(result
, query
->b
.type
);
1368 bool si_query_hw_get_result(struct si_context
*sctx
,
1369 struct si_query
*rquery
,
1370 bool wait
, union pipe_query_result
*result
)
1372 struct si_screen
*sscreen
= sctx
->screen
;
1373 struct si_query_hw
*query
= (struct si_query_hw
*)rquery
;
1374 struct si_query_buffer
*qbuf
;
1376 query
->ops
->clear_result(query
, result
);
1378 for (qbuf
= &query
->buffer
; qbuf
; qbuf
= qbuf
->previous
) {
1379 unsigned usage
= PIPE_TRANSFER_READ
|
1380 (wait
? 0 : PIPE_TRANSFER_DONTBLOCK
);
1381 unsigned results_base
= 0;
1384 if (rquery
->b
.flushed
)
1385 map
= sctx
->ws
->buffer_map(qbuf
->buf
->buf
, NULL
, usage
);
1387 map
= si_buffer_map_sync_with_rings(sctx
, qbuf
->buf
, usage
);
1392 while (results_base
!= qbuf
->results_end
) {
1393 query
->ops
->add_result(sscreen
, query
, map
+ results_base
,
1395 results_base
+= query
->result_size
;
1399 /* Convert the time to expected units. */
1400 if (rquery
->type
== PIPE_QUERY_TIME_ELAPSED
||
1401 rquery
->type
== SI_QUERY_TIME_ELAPSED_SDMA
||
1402 rquery
->type
== PIPE_QUERY_TIMESTAMP
) {
1403 result
->u64
= (1000000 * result
->u64
) / sscreen
->info
.clock_crystal_freq
;
1408 static void si_restore_qbo_state(struct si_context
*sctx
,
1409 struct si_qbo_state
*st
)
1411 sctx
->b
.bind_compute_state(&sctx
->b
, st
->saved_compute
);
1413 sctx
->b
.set_constant_buffer(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1414 pipe_resource_reference(&st
->saved_const0
.buffer
, NULL
);
1416 sctx
->b
.set_shader_buffers(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1417 for (unsigned i
= 0; i
< 3; ++i
)
1418 pipe_resource_reference(&st
->saved_ssbo
[i
].buffer
, NULL
);
1421 static void si_query_hw_get_result_resource(struct si_context
*sctx
,
1422 struct si_query
*rquery
,
1424 enum pipe_query_value_type result_type
,
1426 struct pipe_resource
*resource
,
1429 struct si_query_hw
*query
= (struct si_query_hw
*)rquery
;
1430 struct si_query_buffer
*qbuf
;
1431 struct si_query_buffer
*qbuf_prev
;
1432 struct pipe_resource
*tmp_buffer
= NULL
;
1433 unsigned tmp_buffer_offset
= 0;
1434 struct si_qbo_state saved_state
= {};
1435 struct pipe_grid_info grid
= {};
1436 struct pipe_constant_buffer constant_buffer
= {};
1437 struct pipe_shader_buffer ssbo
[3];
1438 struct si_hw_query_params params
;
1440 uint32_t end_offset
;
1441 uint32_t result_stride
;
1442 uint32_t result_count
;
1444 uint32_t fence_offset
;
1445 uint32_t pair_stride
;
1446 uint32_t pair_count
;
1449 if (!sctx
->query_result_shader
) {
1450 sctx
->query_result_shader
= si_create_query_result_cs(sctx
);
1451 if (!sctx
->query_result_shader
)
1455 if (query
->buffer
.previous
) {
1456 u_suballocator_alloc(sctx
->allocator_zeroed_memory
, 16, 16,
1457 &tmp_buffer_offset
, &tmp_buffer
);
1462 si_save_qbo_state(sctx
, &saved_state
);
1464 si_get_hw_query_params(sctx
, query
, index
>= 0 ? index
: 0, ¶ms
);
1465 consts
.end_offset
= params
.end_offset
- params
.start_offset
;
1466 consts
.fence_offset
= params
.fence_offset
- params
.start_offset
;
1467 consts
.result_stride
= query
->result_size
;
1468 consts
.pair_stride
= params
.pair_stride
;
1469 consts
.pair_count
= params
.pair_count
;
1471 constant_buffer
.buffer_size
= sizeof(consts
);
1472 constant_buffer
.user_buffer
= &consts
;
1474 ssbo
[1].buffer
= tmp_buffer
;
1475 ssbo
[1].buffer_offset
= tmp_buffer_offset
;
1476 ssbo
[1].buffer_size
= 16;
1480 sctx
->b
.bind_compute_state(&sctx
->b
, sctx
->query_result_shader
);
1492 if (query
->b
.type
== PIPE_QUERY_OCCLUSION_PREDICATE
||
1493 query
->b
.type
== PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
)
1495 else if (query
->b
.type
== PIPE_QUERY_SO_OVERFLOW_PREDICATE
||
1496 query
->b
.type
== PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE
)
1497 consts
.config
|= 8 | 256;
1498 else if (query
->b
.type
== PIPE_QUERY_TIMESTAMP
||
1499 query
->b
.type
== PIPE_QUERY_TIME_ELAPSED
)
1500 consts
.config
|= 32;
1502 switch (result_type
) {
1503 case PIPE_QUERY_TYPE_U64
:
1504 case PIPE_QUERY_TYPE_I64
:
1505 consts
.config
|= 64;
1507 case PIPE_QUERY_TYPE_I32
:
1508 consts
.config
|= 128;
1510 case PIPE_QUERY_TYPE_U32
:
1514 sctx
->flags
|= sctx
->screen
->barrier_flags
.cp_to_L2
;
1516 for (qbuf
= &query
->buffer
; qbuf
; qbuf
= qbuf_prev
) {
1517 if (query
->b
.type
!= PIPE_QUERY_TIMESTAMP
) {
1518 qbuf_prev
= qbuf
->previous
;
1519 consts
.result_count
= qbuf
->results_end
/ query
->result_size
;
1520 consts
.config
&= ~3;
1521 if (qbuf
!= &query
->buffer
)
1526 /* Only read the last timestamp. */
1528 consts
.result_count
= 0;
1529 consts
.config
|= 16;
1530 params
.start_offset
+= qbuf
->results_end
- query
->result_size
;
1533 sctx
->b
.set_constant_buffer(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, &constant_buffer
);
1535 ssbo
[0].buffer
= &qbuf
->buf
->b
.b
;
1536 ssbo
[0].buffer_offset
= params
.start_offset
;
1537 ssbo
[0].buffer_size
= qbuf
->results_end
- params
.start_offset
;
1539 if (!qbuf
->previous
) {
1540 ssbo
[2].buffer
= resource
;
1541 ssbo
[2].buffer_offset
= offset
;
1542 ssbo
[2].buffer_size
= 8;
1544 r600_resource(resource
)->TC_L2_dirty
= true;
1547 sctx
->b
.set_shader_buffers(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, 3, ssbo
);
1549 if (wait
&& qbuf
== &query
->buffer
) {
1552 /* Wait for result availability. Wait only for readiness
1553 * of the last entry, since the fence writes should be
1554 * serialized in the CP.
1556 va
= qbuf
->buf
->gpu_address
+ qbuf
->results_end
- query
->result_size
;
1557 va
+= params
.fence_offset
;
1559 si_gfx_wait_fence(sctx
, va
, 0x80000000, 0x80000000);
1562 sctx
->b
.launch_grid(&sctx
->b
, &grid
);
1563 sctx
->flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
1566 si_restore_qbo_state(sctx
, &saved_state
);
1567 pipe_resource_reference(&tmp_buffer
, NULL
);
1570 static void si_render_condition(struct pipe_context
*ctx
,
1571 struct pipe_query
*query
,
1573 enum pipe_render_cond_flag mode
)
1575 struct si_context
*sctx
= (struct si_context
*)ctx
;
1576 struct si_query_hw
*rquery
= (struct si_query_hw
*)query
;
1577 struct si_atom
*atom
= &sctx
->atoms
.s
.render_cond
;
1580 bool needs_workaround
= false;
1582 /* There was a firmware regression in VI which causes successive
1583 * SET_PREDICATION packets to give the wrong answer for
1584 * non-inverted stream overflow predication.
1586 if (((sctx
->chip_class
== VI
&& sctx
->screen
->info
.pfp_fw_feature
< 49) ||
1587 (sctx
->chip_class
== GFX9
&& sctx
->screen
->info
.pfp_fw_feature
< 38)) &&
1589 (rquery
->b
.type
== PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE
||
1590 (rquery
->b
.type
== PIPE_QUERY_SO_OVERFLOW_PREDICATE
&&
1591 (rquery
->buffer
.previous
||
1592 rquery
->buffer
.results_end
> rquery
->result_size
)))) {
1593 needs_workaround
= true;
1596 if (needs_workaround
&& !rquery
->workaround_buf
) {
1597 bool old_force_off
= sctx
->render_cond_force_off
;
1598 sctx
->render_cond_force_off
= true;
1600 u_suballocator_alloc(
1601 sctx
->allocator_zeroed_memory
, 8, 8,
1602 &rquery
->workaround_offset
,
1603 (struct pipe_resource
**)&rquery
->workaround_buf
);
1605 /* Reset to NULL to avoid a redundant SET_PREDICATION
1606 * from launching the compute grid.
1608 sctx
->render_cond
= NULL
;
1610 ctx
->get_query_result_resource(
1611 ctx
, query
, true, PIPE_QUERY_TYPE_U64
, 0,
1612 &rquery
->workaround_buf
->b
.b
, rquery
->workaround_offset
);
1614 /* Settings this in the render cond atom is too late,
1615 * so set it here. */
1616 sctx
->flags
|= sctx
->screen
->barrier_flags
.L2_to_cp
|
1617 SI_CONTEXT_FLUSH_FOR_RENDER_COND
;
1619 sctx
->render_cond_force_off
= old_force_off
;
1623 sctx
->render_cond
= query
;
1624 sctx
->render_cond_invert
= condition
;
1625 sctx
->render_cond_mode
= mode
;
1627 si_set_atom_dirty(sctx
, atom
, query
!= NULL
);
1630 void si_suspend_queries(struct si_context
*sctx
)
1632 struct si_query_hw
*query
;
1634 LIST_FOR_EACH_ENTRY(query
, &sctx
->active_queries
, list
) {
1635 si_query_hw_emit_stop(sctx
, query
);
1637 assert(sctx
->num_cs_dw_queries_suspend
== 0);
1640 void si_resume_queries(struct si_context
*sctx
)
1642 struct si_query_hw
*query
;
1644 assert(sctx
->num_cs_dw_queries_suspend
== 0);
1646 /* Check CS space here. Resuming must not be interrupted by flushes. */
1647 si_need_gfx_cs_space(sctx
);
1649 LIST_FOR_EACH_ENTRY(query
, &sctx
->active_queries
, list
) {
1650 si_query_hw_emit_start(sctx
, query
);
1654 #define XFULL(name_, query_type_, type_, result_type_, group_id_) \
1657 .query_type = SI_QUERY_##query_type_, \
1658 .type = PIPE_DRIVER_QUERY_TYPE_##type_, \
1659 .result_type = PIPE_DRIVER_QUERY_RESULT_TYPE_##result_type_, \
1660 .group_id = group_id_ \
1663 #define X(name_, query_type_, type_, result_type_) \
1664 XFULL(name_, query_type_, type_, result_type_, ~(unsigned)0)
1666 #define XG(group_, name_, query_type_, type_, result_type_) \
1667 XFULL(name_, query_type_, type_, result_type_, SI_QUERY_GROUP_##group_)
1669 static struct pipe_driver_query_info si_driver_query_list
[] = {
1670 X("num-compilations", NUM_COMPILATIONS
, UINT64
, CUMULATIVE
),
1671 X("num-shaders-created", NUM_SHADERS_CREATED
, UINT64
, CUMULATIVE
),
1672 X("num-shader-cache-hits", NUM_SHADER_CACHE_HITS
, UINT64
, CUMULATIVE
),
1673 X("draw-calls", DRAW_CALLS
, UINT64
, AVERAGE
),
1674 X("decompress-calls", DECOMPRESS_CALLS
, UINT64
, AVERAGE
),
1675 X("MRT-draw-calls", MRT_DRAW_CALLS
, UINT64
, AVERAGE
),
1676 X("prim-restart-calls", PRIM_RESTART_CALLS
, UINT64
, AVERAGE
),
1677 X("spill-draw-calls", SPILL_DRAW_CALLS
, UINT64
, AVERAGE
),
1678 X("compute-calls", COMPUTE_CALLS
, UINT64
, AVERAGE
),
1679 X("spill-compute-calls", SPILL_COMPUTE_CALLS
, UINT64
, AVERAGE
),
1680 X("dma-calls", DMA_CALLS
, UINT64
, AVERAGE
),
1681 X("cp-dma-calls", CP_DMA_CALLS
, UINT64
, AVERAGE
),
1682 X("num-vs-flushes", NUM_VS_FLUSHES
, UINT64
, AVERAGE
),
1683 X("num-ps-flushes", NUM_PS_FLUSHES
, UINT64
, AVERAGE
),
1684 X("num-cs-flushes", NUM_CS_FLUSHES
, UINT64
, AVERAGE
),
1685 X("num-CB-cache-flushes", NUM_CB_CACHE_FLUSHES
, UINT64
, AVERAGE
),
1686 X("num-DB-cache-flushes", NUM_DB_CACHE_FLUSHES
, UINT64
, AVERAGE
),
1687 X("num-L2-invalidates", NUM_L2_INVALIDATES
, UINT64
, AVERAGE
),
1688 X("num-L2-writebacks", NUM_L2_WRITEBACKS
, UINT64
, AVERAGE
),
1689 X("num-resident-handles", NUM_RESIDENT_HANDLES
, UINT64
, AVERAGE
),
1690 X("tc-offloaded-slots", TC_OFFLOADED_SLOTS
, UINT64
, AVERAGE
),
1691 X("tc-direct-slots", TC_DIRECT_SLOTS
, UINT64
, AVERAGE
),
1692 X("tc-num-syncs", TC_NUM_SYNCS
, UINT64
, AVERAGE
),
1693 X("CS-thread-busy", CS_THREAD_BUSY
, UINT64
, AVERAGE
),
1694 X("gallium-thread-busy", GALLIUM_THREAD_BUSY
, UINT64
, AVERAGE
),
1695 X("requested-VRAM", REQUESTED_VRAM
, BYTES
, AVERAGE
),
1696 X("requested-GTT", REQUESTED_GTT
, BYTES
, AVERAGE
),
1697 X("mapped-VRAM", MAPPED_VRAM
, BYTES
, AVERAGE
),
1698 X("mapped-GTT", MAPPED_GTT
, BYTES
, AVERAGE
),
1699 X("buffer-wait-time", BUFFER_WAIT_TIME
, MICROSECONDS
, CUMULATIVE
),
1700 X("num-mapped-buffers", NUM_MAPPED_BUFFERS
, UINT64
, AVERAGE
),
1701 X("num-GFX-IBs", NUM_GFX_IBS
, UINT64
, AVERAGE
),
1702 X("num-SDMA-IBs", NUM_SDMA_IBS
, UINT64
, AVERAGE
),
1703 X("GFX-BO-list-size", GFX_BO_LIST_SIZE
, UINT64
, AVERAGE
),
1704 X("GFX-IB-size", GFX_IB_SIZE
, UINT64
, AVERAGE
),
1705 X("num-bytes-moved", NUM_BYTES_MOVED
, BYTES
, CUMULATIVE
),
1706 X("num-evictions", NUM_EVICTIONS
, UINT64
, CUMULATIVE
),
1707 X("VRAM-CPU-page-faults", NUM_VRAM_CPU_PAGE_FAULTS
, UINT64
, CUMULATIVE
),
1708 X("VRAM-usage", VRAM_USAGE
, BYTES
, AVERAGE
),
1709 X("VRAM-vis-usage", VRAM_VIS_USAGE
, BYTES
, AVERAGE
),
1710 X("GTT-usage", GTT_USAGE
, BYTES
, AVERAGE
),
1711 X("back-buffer-ps-draw-ratio", BACK_BUFFER_PS_DRAW_RATIO
, UINT64
, AVERAGE
),
1713 /* GPIN queries are for the benefit of old versions of GPUPerfStudio,
1714 * which use it as a fallback path to detect the GPU type.
1716 * Note: The names of these queries are significant for GPUPerfStudio
1717 * (and possibly their order as well). */
1718 XG(GPIN
, "GPIN_000", GPIN_ASIC_ID
, UINT
, AVERAGE
),
1719 XG(GPIN
, "GPIN_001", GPIN_NUM_SIMD
, UINT
, AVERAGE
),
1720 XG(GPIN
, "GPIN_002", GPIN_NUM_RB
, UINT
, AVERAGE
),
1721 XG(GPIN
, "GPIN_003", GPIN_NUM_SPI
, UINT
, AVERAGE
),
1722 XG(GPIN
, "GPIN_004", GPIN_NUM_SE
, UINT
, AVERAGE
),
1724 X("temperature", GPU_TEMPERATURE
, UINT64
, AVERAGE
),
1725 X("shader-clock", CURRENT_GPU_SCLK
, HZ
, AVERAGE
),
1726 X("memory-clock", CURRENT_GPU_MCLK
, HZ
, AVERAGE
),
1728 /* The following queries must be at the end of the list because their
1729 * availability is adjusted dynamically based on the DRM version. */
1730 X("GPU-load", GPU_LOAD
, UINT64
, AVERAGE
),
1731 X("GPU-shaders-busy", GPU_SHADERS_BUSY
, UINT64
, AVERAGE
),
1732 X("GPU-ta-busy", GPU_TA_BUSY
, UINT64
, AVERAGE
),
1733 X("GPU-gds-busy", GPU_GDS_BUSY
, UINT64
, AVERAGE
),
1734 X("GPU-vgt-busy", GPU_VGT_BUSY
, UINT64
, AVERAGE
),
1735 X("GPU-ia-busy", GPU_IA_BUSY
, UINT64
, AVERAGE
),
1736 X("GPU-sx-busy", GPU_SX_BUSY
, UINT64
, AVERAGE
),
1737 X("GPU-wd-busy", GPU_WD_BUSY
, UINT64
, AVERAGE
),
1738 X("GPU-bci-busy", GPU_BCI_BUSY
, UINT64
, AVERAGE
),
1739 X("GPU-sc-busy", GPU_SC_BUSY
, UINT64
, AVERAGE
),
1740 X("GPU-pa-busy", GPU_PA_BUSY
, UINT64
, AVERAGE
),
1741 X("GPU-db-busy", GPU_DB_BUSY
, UINT64
, AVERAGE
),
1742 X("GPU-cp-busy", GPU_CP_BUSY
, UINT64
, AVERAGE
),
1743 X("GPU-cb-busy", GPU_CB_BUSY
, UINT64
, AVERAGE
),
1746 X("GPU-sdma-busy", GPU_SDMA_BUSY
, UINT64
, AVERAGE
),
1749 X("GPU-pfp-busy", GPU_PFP_BUSY
, UINT64
, AVERAGE
),
1750 X("GPU-meq-busy", GPU_MEQ_BUSY
, UINT64
, AVERAGE
),
1751 X("GPU-me-busy", GPU_ME_BUSY
, UINT64
, AVERAGE
),
1752 X("GPU-surf-sync-busy", GPU_SURF_SYNC_BUSY
, UINT64
, AVERAGE
),
1753 X("GPU-cp-dma-busy", GPU_CP_DMA_BUSY
, UINT64
, AVERAGE
),
1754 X("GPU-scratch-ram-busy", GPU_SCRATCH_RAM_BUSY
, UINT64
, AVERAGE
),
1761 static unsigned si_get_num_queries(struct si_screen
*sscreen
)
1764 if (sscreen
->info
.drm_major
== 3) {
1765 if (sscreen
->info
.chip_class
>= VI
)
1766 return ARRAY_SIZE(si_driver_query_list
);
1768 return ARRAY_SIZE(si_driver_query_list
) - 7;
1772 if (sscreen
->info
.has_read_registers_query
) {
1773 if (sscreen
->info
.chip_class
== CIK
)
1774 return ARRAY_SIZE(si_driver_query_list
) - 6;
1776 return ARRAY_SIZE(si_driver_query_list
) - 7;
1779 return ARRAY_SIZE(si_driver_query_list
) - 21;
1782 static int si_get_driver_query_info(struct pipe_screen
*screen
,
1784 struct pipe_driver_query_info
*info
)
1786 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1787 unsigned num_queries
= si_get_num_queries(sscreen
);
1790 unsigned num_perfcounters
=
1791 si_get_perfcounter_info(sscreen
, 0, NULL
);
1793 return num_queries
+ num_perfcounters
;
1796 if (index
>= num_queries
)
1797 return si_get_perfcounter_info(sscreen
, index
- num_queries
, info
);
1799 *info
= si_driver_query_list
[index
];
1801 switch (info
->query_type
) {
1802 case SI_QUERY_REQUESTED_VRAM
:
1803 case SI_QUERY_VRAM_USAGE
:
1804 case SI_QUERY_MAPPED_VRAM
:
1805 info
->max_value
.u64
= sscreen
->info
.vram_size
;
1807 case SI_QUERY_REQUESTED_GTT
:
1808 case SI_QUERY_GTT_USAGE
:
1809 case SI_QUERY_MAPPED_GTT
:
1810 info
->max_value
.u64
= sscreen
->info
.gart_size
;
1812 case SI_QUERY_GPU_TEMPERATURE
:
1813 info
->max_value
.u64
= 125;
1815 case SI_QUERY_VRAM_VIS_USAGE
:
1816 info
->max_value
.u64
= sscreen
->info
.vram_vis_size
;
1820 if (info
->group_id
!= ~(unsigned)0 && sscreen
->perfcounters
)
1821 info
->group_id
+= sscreen
->perfcounters
->num_groups
;
1826 /* Note: Unfortunately, GPUPerfStudio hardcodes the order of hardware
1827 * performance counter groups, so be careful when changing this and related
1830 static int si_get_driver_query_group_info(struct pipe_screen
*screen
,
1832 struct pipe_driver_query_group_info
*info
)
1834 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1835 unsigned num_pc_groups
= 0;
1837 if (sscreen
->perfcounters
)
1838 num_pc_groups
= sscreen
->perfcounters
->num_groups
;
1841 return num_pc_groups
+ SI_NUM_SW_QUERY_GROUPS
;
1843 if (index
< num_pc_groups
)
1844 return si_get_perfcounter_group_info(sscreen
, index
, info
);
1846 index
-= num_pc_groups
;
1847 if (index
>= SI_NUM_SW_QUERY_GROUPS
)
1850 info
->name
= "GPIN";
1851 info
->max_active_queries
= 5;
1852 info
->num_queries
= 5;
1856 void si_init_query_functions(struct si_context
*sctx
)
1858 sctx
->b
.create_query
= si_create_query
;
1859 sctx
->b
.create_batch_query
= si_create_batch_query
;
1860 sctx
->b
.destroy_query
= si_destroy_query
;
1861 sctx
->b
.begin_query
= si_begin_query
;
1862 sctx
->b
.end_query
= si_end_query
;
1863 sctx
->b
.get_query_result
= si_get_query_result
;
1864 sctx
->b
.get_query_result_resource
= si_get_query_result_resource
;
1865 sctx
->atoms
.s
.render_cond
.emit
= si_emit_query_predication
;
1867 if (((struct si_screen
*)sctx
->b
.screen
)->info
.num_render_backends
> 0)
1868 sctx
->b
.render_condition
= si_render_condition
;
1870 LIST_INITHEAD(&sctx
->active_queries
);
1873 void si_init_screen_query_functions(struct si_screen
*sscreen
)
1875 sscreen
->b
.get_driver_query_info
= si_get_driver_query_info
;
1876 sscreen
->b
.get_driver_query_group_info
= si_get_driver_query_group_info
;