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ae6498e1895cafb7b51ce839cb08d3f502c100bc
[mesa.git] / src / gallium / drivers / radeonsi / si_query.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2014 Marek Olšák <marek.olsak@amd.com>
4 * Copyright 2018 Advanced Micro Devices, Inc.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * on the rights to use, copy, modify, merge, publish, distribute, sub
11 * license, and/or sell copies of the Software, and to permit persons to whom
12 * the Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27 #include "si_pipe.h"
28 #include "si_query.h"
29 #include "util/u_memory.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/os_time.h"
32 #include "util/u_suballoc.h"
33 #include "amd/common/sid.h"
34
35 #define SI_MAX_STREAMS 4
36
37 static const struct si_query_ops query_hw_ops;
38
39 struct si_hw_query_params {
40 unsigned start_offset;
41 unsigned end_offset;
42 unsigned fence_offset;
43 unsigned pair_stride;
44 unsigned pair_count;
45 };
46
47 /* Queries without buffer handling or suspend/resume. */
48 struct si_query_sw {
49 struct si_query b;
50
51 uint64_t begin_result;
52 uint64_t end_result;
53
54 uint64_t begin_time;
55 uint64_t end_time;
56
57 /* Fence for GPU_FINISHED. */
58 struct pipe_fence_handle *fence;
59 };
60
61 static void si_query_sw_destroy(struct si_context *sctx,
62 struct si_query *squery)
63 {
64 struct si_query_sw *query = (struct si_query_sw *)squery;
65
66 sctx->b.screen->fence_reference(sctx->b.screen, &query->fence, NULL);
67 FREE(query);
68 }
69
70 static enum radeon_value_id winsys_id_from_type(unsigned type)
71 {
72 switch (type) {
73 case SI_QUERY_REQUESTED_VRAM: return RADEON_REQUESTED_VRAM_MEMORY;
74 case SI_QUERY_REQUESTED_GTT: return RADEON_REQUESTED_GTT_MEMORY;
75 case SI_QUERY_MAPPED_VRAM: return RADEON_MAPPED_VRAM;
76 case SI_QUERY_MAPPED_GTT: return RADEON_MAPPED_GTT;
77 case SI_QUERY_BUFFER_WAIT_TIME: return RADEON_BUFFER_WAIT_TIME_NS;
78 case SI_QUERY_NUM_MAPPED_BUFFERS: return RADEON_NUM_MAPPED_BUFFERS;
79 case SI_QUERY_NUM_GFX_IBS: return RADEON_NUM_GFX_IBS;
80 case SI_QUERY_NUM_SDMA_IBS: return RADEON_NUM_SDMA_IBS;
81 case SI_QUERY_GFX_BO_LIST_SIZE: return RADEON_GFX_BO_LIST_COUNTER;
82 case SI_QUERY_GFX_IB_SIZE: return RADEON_GFX_IB_SIZE_COUNTER;
83 case SI_QUERY_NUM_BYTES_MOVED: return RADEON_NUM_BYTES_MOVED;
84 case SI_QUERY_NUM_EVICTIONS: return RADEON_NUM_EVICTIONS;
85 case SI_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: return RADEON_NUM_VRAM_CPU_PAGE_FAULTS;
86 case SI_QUERY_VRAM_USAGE: return RADEON_VRAM_USAGE;
87 case SI_QUERY_VRAM_VIS_USAGE: return RADEON_VRAM_VIS_USAGE;
88 case SI_QUERY_GTT_USAGE: return RADEON_GTT_USAGE;
89 case SI_QUERY_GPU_TEMPERATURE: return RADEON_GPU_TEMPERATURE;
90 case SI_QUERY_CURRENT_GPU_SCLK: return RADEON_CURRENT_SCLK;
91 case SI_QUERY_CURRENT_GPU_MCLK: return RADEON_CURRENT_MCLK;
92 case SI_QUERY_CS_THREAD_BUSY: return RADEON_CS_THREAD_TIME;
93 default: unreachable("query type does not correspond to winsys id");
94 }
95 }
96
97 static int64_t si_finish_dma_get_cpu_time(struct si_context *sctx)
98 {
99 struct pipe_fence_handle *fence = NULL;
100
101 si_flush_dma_cs(sctx, 0, &fence);
102 if (fence) {
103 sctx->ws->fence_wait(sctx->ws, fence, PIPE_TIMEOUT_INFINITE);
104 sctx->ws->fence_reference(&fence, NULL);
105 }
106
107 return os_time_get_nano();
108 }
109
110 static bool si_query_sw_begin(struct si_context *sctx,
111 struct si_query *squery)
112 {
113 struct si_query_sw *query = (struct si_query_sw *)squery;
114 enum radeon_value_id ws_id;
115
116 switch(query->b.type) {
117 case PIPE_QUERY_TIMESTAMP_DISJOINT:
118 case PIPE_QUERY_GPU_FINISHED:
119 break;
120 case SI_QUERY_TIME_ELAPSED_SDMA_SI:
121 query->begin_result = si_finish_dma_get_cpu_time(sctx);
122 break;
123 case SI_QUERY_DRAW_CALLS:
124 query->begin_result = sctx->num_draw_calls;
125 break;
126 case SI_QUERY_DECOMPRESS_CALLS:
127 query->begin_result = sctx->num_decompress_calls;
128 break;
129 case SI_QUERY_MRT_DRAW_CALLS:
130 query->begin_result = sctx->num_mrt_draw_calls;
131 break;
132 case SI_QUERY_PRIM_RESTART_CALLS:
133 query->begin_result = sctx->num_prim_restart_calls;
134 break;
135 case SI_QUERY_SPILL_DRAW_CALLS:
136 query->begin_result = sctx->num_spill_draw_calls;
137 break;
138 case SI_QUERY_COMPUTE_CALLS:
139 query->begin_result = sctx->num_compute_calls;
140 break;
141 case SI_QUERY_SPILL_COMPUTE_CALLS:
142 query->begin_result = sctx->num_spill_compute_calls;
143 break;
144 case SI_QUERY_DMA_CALLS:
145 query->begin_result = sctx->num_dma_calls;
146 break;
147 case SI_QUERY_CP_DMA_CALLS:
148 query->begin_result = sctx->num_cp_dma_calls;
149 break;
150 case SI_QUERY_NUM_VS_FLUSHES:
151 query->begin_result = sctx->num_vs_flushes;
152 break;
153 case SI_QUERY_NUM_PS_FLUSHES:
154 query->begin_result = sctx->num_ps_flushes;
155 break;
156 case SI_QUERY_NUM_CS_FLUSHES:
157 query->begin_result = sctx->num_cs_flushes;
158 break;
159 case SI_QUERY_NUM_CB_CACHE_FLUSHES:
160 query->begin_result = sctx->num_cb_cache_flushes;
161 break;
162 case SI_QUERY_NUM_DB_CACHE_FLUSHES:
163 query->begin_result = sctx->num_db_cache_flushes;
164 break;
165 case SI_QUERY_NUM_L2_INVALIDATES:
166 query->begin_result = sctx->num_L2_invalidates;
167 break;
168 case SI_QUERY_NUM_L2_WRITEBACKS:
169 query->begin_result = sctx->num_L2_writebacks;
170 break;
171 case SI_QUERY_NUM_RESIDENT_HANDLES:
172 query->begin_result = sctx->num_resident_handles;
173 break;
174 case SI_QUERY_TC_OFFLOADED_SLOTS:
175 query->begin_result = sctx->tc ? sctx->tc->num_offloaded_slots : 0;
176 break;
177 case SI_QUERY_TC_DIRECT_SLOTS:
178 query->begin_result = sctx->tc ? sctx->tc->num_direct_slots : 0;
179 break;
180 case SI_QUERY_TC_NUM_SYNCS:
181 query->begin_result = sctx->tc ? sctx->tc->num_syncs : 0;
182 break;
183 case SI_QUERY_REQUESTED_VRAM:
184 case SI_QUERY_REQUESTED_GTT:
185 case SI_QUERY_MAPPED_VRAM:
186 case SI_QUERY_MAPPED_GTT:
187 case SI_QUERY_VRAM_USAGE:
188 case SI_QUERY_VRAM_VIS_USAGE:
189 case SI_QUERY_GTT_USAGE:
190 case SI_QUERY_GPU_TEMPERATURE:
191 case SI_QUERY_CURRENT_GPU_SCLK:
192 case SI_QUERY_CURRENT_GPU_MCLK:
193 case SI_QUERY_BACK_BUFFER_PS_DRAW_RATIO:
194 case SI_QUERY_NUM_MAPPED_BUFFERS:
195 query->begin_result = 0;
196 break;
197 case SI_QUERY_BUFFER_WAIT_TIME:
198 case SI_QUERY_GFX_IB_SIZE:
199 case SI_QUERY_NUM_GFX_IBS:
200 case SI_QUERY_NUM_SDMA_IBS:
201 case SI_QUERY_NUM_BYTES_MOVED:
202 case SI_QUERY_NUM_EVICTIONS:
203 case SI_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: {
204 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
205 query->begin_result = sctx->ws->query_value(sctx->ws, ws_id);
206 break;
207 }
208 case SI_QUERY_GFX_BO_LIST_SIZE:
209 ws_id = winsys_id_from_type(query->b.type);
210 query->begin_result = sctx->ws->query_value(sctx->ws, ws_id);
211 query->begin_time = sctx->ws->query_value(sctx->ws,
212 RADEON_NUM_GFX_IBS);
213 break;
214 case SI_QUERY_CS_THREAD_BUSY:
215 ws_id = winsys_id_from_type(query->b.type);
216 query->begin_result = sctx->ws->query_value(sctx->ws, ws_id);
217 query->begin_time = os_time_get_nano();
218 break;
219 case SI_QUERY_GALLIUM_THREAD_BUSY:
220 query->begin_result =
221 sctx->tc ? util_queue_get_thread_time_nano(&sctx->tc->queue, 0) : 0;
222 query->begin_time = os_time_get_nano();
223 break;
224 case SI_QUERY_GPU_LOAD:
225 case SI_QUERY_GPU_SHADERS_BUSY:
226 case SI_QUERY_GPU_TA_BUSY:
227 case SI_QUERY_GPU_GDS_BUSY:
228 case SI_QUERY_GPU_VGT_BUSY:
229 case SI_QUERY_GPU_IA_BUSY:
230 case SI_QUERY_GPU_SX_BUSY:
231 case SI_QUERY_GPU_WD_BUSY:
232 case SI_QUERY_GPU_BCI_BUSY:
233 case SI_QUERY_GPU_SC_BUSY:
234 case SI_QUERY_GPU_PA_BUSY:
235 case SI_QUERY_GPU_DB_BUSY:
236 case SI_QUERY_GPU_CP_BUSY:
237 case SI_QUERY_GPU_CB_BUSY:
238 case SI_QUERY_GPU_SDMA_BUSY:
239 case SI_QUERY_GPU_PFP_BUSY:
240 case SI_QUERY_GPU_MEQ_BUSY:
241 case SI_QUERY_GPU_ME_BUSY:
242 case SI_QUERY_GPU_SURF_SYNC_BUSY:
243 case SI_QUERY_GPU_CP_DMA_BUSY:
244 case SI_QUERY_GPU_SCRATCH_RAM_BUSY:
245 query->begin_result = si_begin_counter(sctx->screen,
246 query->b.type);
247 break;
248 case SI_QUERY_NUM_COMPILATIONS:
249 query->begin_result = p_atomic_read(&sctx->screen->num_compilations);
250 break;
251 case SI_QUERY_NUM_SHADERS_CREATED:
252 query->begin_result = p_atomic_read(&sctx->screen->num_shaders_created);
253 break;
254 case SI_QUERY_NUM_SHADER_CACHE_HITS:
255 query->begin_result =
256 p_atomic_read(&sctx->screen->num_shader_cache_hits);
257 break;
258 case SI_QUERY_PD_NUM_PRIMS_ACCEPTED:
259 query->begin_result = sctx->compute_num_verts_accepted;
260 break;
261 case SI_QUERY_PD_NUM_PRIMS_REJECTED:
262 query->begin_result = sctx->compute_num_verts_rejected;
263 break;
264 case SI_QUERY_PD_NUM_PRIMS_INELIGIBLE:
265 query->begin_result = sctx->compute_num_verts_ineligible;
266 break;
267 case SI_QUERY_GPIN_ASIC_ID:
268 case SI_QUERY_GPIN_NUM_SIMD:
269 case SI_QUERY_GPIN_NUM_RB:
270 case SI_QUERY_GPIN_NUM_SPI:
271 case SI_QUERY_GPIN_NUM_SE:
272 break;
273 default:
274 unreachable("si_query_sw_begin: bad query type");
275 }
276
277 return true;
278 }
279
280 static bool si_query_sw_end(struct si_context *sctx,
281 struct si_query *squery)
282 {
283 struct si_query_sw *query = (struct si_query_sw *)squery;
284 enum radeon_value_id ws_id;
285
286 switch(query->b.type) {
287 case PIPE_QUERY_TIMESTAMP_DISJOINT:
288 break;
289 case PIPE_QUERY_GPU_FINISHED:
290 sctx->b.flush(&sctx->b, &query->fence, PIPE_FLUSH_DEFERRED);
291 break;
292 case SI_QUERY_TIME_ELAPSED_SDMA_SI:
293 query->end_result = si_finish_dma_get_cpu_time(sctx);
294 break;
295 case SI_QUERY_DRAW_CALLS:
296 query->end_result = sctx->num_draw_calls;
297 break;
298 case SI_QUERY_DECOMPRESS_CALLS:
299 query->end_result = sctx->num_decompress_calls;
300 break;
301 case SI_QUERY_MRT_DRAW_CALLS:
302 query->end_result = sctx->num_mrt_draw_calls;
303 break;
304 case SI_QUERY_PRIM_RESTART_CALLS:
305 query->end_result = sctx->num_prim_restart_calls;
306 break;
307 case SI_QUERY_SPILL_DRAW_CALLS:
308 query->end_result = sctx->num_spill_draw_calls;
309 break;
310 case SI_QUERY_COMPUTE_CALLS:
311 query->end_result = sctx->num_compute_calls;
312 break;
313 case SI_QUERY_SPILL_COMPUTE_CALLS:
314 query->end_result = sctx->num_spill_compute_calls;
315 break;
316 case SI_QUERY_DMA_CALLS:
317 query->end_result = sctx->num_dma_calls;
318 break;
319 case SI_QUERY_CP_DMA_CALLS:
320 query->end_result = sctx->num_cp_dma_calls;
321 break;
322 case SI_QUERY_NUM_VS_FLUSHES:
323 query->end_result = sctx->num_vs_flushes;
324 break;
325 case SI_QUERY_NUM_PS_FLUSHES:
326 query->end_result = sctx->num_ps_flushes;
327 break;
328 case SI_QUERY_NUM_CS_FLUSHES:
329 query->end_result = sctx->num_cs_flushes;
330 break;
331 case SI_QUERY_NUM_CB_CACHE_FLUSHES:
332 query->end_result = sctx->num_cb_cache_flushes;
333 break;
334 case SI_QUERY_NUM_DB_CACHE_FLUSHES:
335 query->end_result = sctx->num_db_cache_flushes;
336 break;
337 case SI_QUERY_NUM_L2_INVALIDATES:
338 query->end_result = sctx->num_L2_invalidates;
339 break;
340 case SI_QUERY_NUM_L2_WRITEBACKS:
341 query->end_result = sctx->num_L2_writebacks;
342 break;
343 case SI_QUERY_NUM_RESIDENT_HANDLES:
344 query->end_result = sctx->num_resident_handles;
345 break;
346 case SI_QUERY_TC_OFFLOADED_SLOTS:
347 query->end_result = sctx->tc ? sctx->tc->num_offloaded_slots : 0;
348 break;
349 case SI_QUERY_TC_DIRECT_SLOTS:
350 query->end_result = sctx->tc ? sctx->tc->num_direct_slots : 0;
351 break;
352 case SI_QUERY_TC_NUM_SYNCS:
353 query->end_result = sctx->tc ? sctx->tc->num_syncs : 0;
354 break;
355 case SI_QUERY_REQUESTED_VRAM:
356 case SI_QUERY_REQUESTED_GTT:
357 case SI_QUERY_MAPPED_VRAM:
358 case SI_QUERY_MAPPED_GTT:
359 case SI_QUERY_VRAM_USAGE:
360 case SI_QUERY_VRAM_VIS_USAGE:
361 case SI_QUERY_GTT_USAGE:
362 case SI_QUERY_GPU_TEMPERATURE:
363 case SI_QUERY_CURRENT_GPU_SCLK:
364 case SI_QUERY_CURRENT_GPU_MCLK:
365 case SI_QUERY_BUFFER_WAIT_TIME:
366 case SI_QUERY_GFX_IB_SIZE:
367 case SI_QUERY_NUM_MAPPED_BUFFERS:
368 case SI_QUERY_NUM_GFX_IBS:
369 case SI_QUERY_NUM_SDMA_IBS:
370 case SI_QUERY_NUM_BYTES_MOVED:
371 case SI_QUERY_NUM_EVICTIONS:
372 case SI_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: {
373 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
374 query->end_result = sctx->ws->query_value(sctx->ws, ws_id);
375 break;
376 }
377 case SI_QUERY_GFX_BO_LIST_SIZE:
378 ws_id = winsys_id_from_type(query->b.type);
379 query->end_result = sctx->ws->query_value(sctx->ws, ws_id);
380 query->end_time = sctx->ws->query_value(sctx->ws,
381 RADEON_NUM_GFX_IBS);
382 break;
383 case SI_QUERY_CS_THREAD_BUSY:
384 ws_id = winsys_id_from_type(query->b.type);
385 query->end_result = sctx->ws->query_value(sctx->ws, ws_id);
386 query->end_time = os_time_get_nano();
387 break;
388 case SI_QUERY_GALLIUM_THREAD_BUSY:
389 query->end_result =
390 sctx->tc ? util_queue_get_thread_time_nano(&sctx->tc->queue, 0) : 0;
391 query->end_time = os_time_get_nano();
392 break;
393 case SI_QUERY_GPU_LOAD:
394 case SI_QUERY_GPU_SHADERS_BUSY:
395 case SI_QUERY_GPU_TA_BUSY:
396 case SI_QUERY_GPU_GDS_BUSY:
397 case SI_QUERY_GPU_VGT_BUSY:
398 case SI_QUERY_GPU_IA_BUSY:
399 case SI_QUERY_GPU_SX_BUSY:
400 case SI_QUERY_GPU_WD_BUSY:
401 case SI_QUERY_GPU_BCI_BUSY:
402 case SI_QUERY_GPU_SC_BUSY:
403 case SI_QUERY_GPU_PA_BUSY:
404 case SI_QUERY_GPU_DB_BUSY:
405 case SI_QUERY_GPU_CP_BUSY:
406 case SI_QUERY_GPU_CB_BUSY:
407 case SI_QUERY_GPU_SDMA_BUSY:
408 case SI_QUERY_GPU_PFP_BUSY:
409 case SI_QUERY_GPU_MEQ_BUSY:
410 case SI_QUERY_GPU_ME_BUSY:
411 case SI_QUERY_GPU_SURF_SYNC_BUSY:
412 case SI_QUERY_GPU_CP_DMA_BUSY:
413 case SI_QUERY_GPU_SCRATCH_RAM_BUSY:
414 query->end_result = si_end_counter(sctx->screen,
415 query->b.type,
416 query->begin_result);
417 query->begin_result = 0;
418 break;
419 case SI_QUERY_NUM_COMPILATIONS:
420 query->end_result = p_atomic_read(&sctx->screen->num_compilations);
421 break;
422 case SI_QUERY_NUM_SHADERS_CREATED:
423 query->end_result = p_atomic_read(&sctx->screen->num_shaders_created);
424 break;
425 case SI_QUERY_BACK_BUFFER_PS_DRAW_RATIO:
426 query->end_result = sctx->last_tex_ps_draw_ratio;
427 break;
428 case SI_QUERY_NUM_SHADER_CACHE_HITS:
429 query->end_result =
430 p_atomic_read(&sctx->screen->num_shader_cache_hits);
431 break;
432 case SI_QUERY_PD_NUM_PRIMS_ACCEPTED:
433 query->end_result = sctx->compute_num_verts_accepted;
434 break;
435 case SI_QUERY_PD_NUM_PRIMS_REJECTED:
436 query->end_result = sctx->compute_num_verts_rejected;
437 break;
438 case SI_QUERY_PD_NUM_PRIMS_INELIGIBLE:
439 query->end_result = sctx->compute_num_verts_ineligible;
440 break;
441 case SI_QUERY_GPIN_ASIC_ID:
442 case SI_QUERY_GPIN_NUM_SIMD:
443 case SI_QUERY_GPIN_NUM_RB:
444 case SI_QUERY_GPIN_NUM_SPI:
445 case SI_QUERY_GPIN_NUM_SE:
446 break;
447 default:
448 unreachable("si_query_sw_end: bad query type");
449 }
450
451 return true;
452 }
453
454 static bool si_query_sw_get_result(struct si_context *sctx,
455 struct si_query *squery,
456 bool wait,
457 union pipe_query_result *result)
458 {
459 struct si_query_sw *query = (struct si_query_sw *)squery;
460
461 switch (query->b.type) {
462 case PIPE_QUERY_TIMESTAMP_DISJOINT:
463 /* Convert from cycles per millisecond to cycles per second (Hz). */
464 result->timestamp_disjoint.frequency =
465 (uint64_t)sctx->screen->info.clock_crystal_freq * 1000;
466 result->timestamp_disjoint.disjoint = false;
467 return true;
468 case PIPE_QUERY_GPU_FINISHED: {
469 struct pipe_screen *screen = sctx->b.screen;
470 struct pipe_context *ctx = squery->b.flushed ? NULL : &sctx->b;
471
472 result->b = screen->fence_finish(screen, ctx, query->fence,
473 wait ? PIPE_TIMEOUT_INFINITE : 0);
474 return result->b;
475 }
476
477 case SI_QUERY_GFX_BO_LIST_SIZE:
478 result->u64 = (query->end_result - query->begin_result) /
479 (query->end_time - query->begin_time);
480 return true;
481 case SI_QUERY_CS_THREAD_BUSY:
482 case SI_QUERY_GALLIUM_THREAD_BUSY:
483 result->u64 = (query->end_result - query->begin_result) * 100 /
484 (query->end_time - query->begin_time);
485 return true;
486 case SI_QUERY_PD_NUM_PRIMS_ACCEPTED:
487 case SI_QUERY_PD_NUM_PRIMS_REJECTED:
488 case SI_QUERY_PD_NUM_PRIMS_INELIGIBLE:
489 result->u64 = ((unsigned)query->end_result -
490 (unsigned)query->begin_result) / 3;
491 return true;
492 case SI_QUERY_GPIN_ASIC_ID:
493 result->u32 = 0;
494 return true;
495 case SI_QUERY_GPIN_NUM_SIMD:
496 result->u32 = sctx->screen->info.num_good_compute_units;
497 return true;
498 case SI_QUERY_GPIN_NUM_RB:
499 result->u32 = sctx->screen->info.num_render_backends;
500 return true;
501 case SI_QUERY_GPIN_NUM_SPI:
502 result->u32 = 1; /* all supported chips have one SPI per SE */
503 return true;
504 case SI_QUERY_GPIN_NUM_SE:
505 result->u32 = sctx->screen->info.max_se;
506 return true;
507 }
508
509 result->u64 = query->end_result - query->begin_result;
510
511 switch (query->b.type) {
512 case SI_QUERY_BUFFER_WAIT_TIME:
513 case SI_QUERY_GPU_TEMPERATURE:
514 result->u64 /= 1000;
515 break;
516 case SI_QUERY_CURRENT_GPU_SCLK:
517 case SI_QUERY_CURRENT_GPU_MCLK:
518 result->u64 *= 1000000;
519 break;
520 }
521
522 return true;
523 }
524
525
526 static const struct si_query_ops sw_query_ops = {
527 .destroy = si_query_sw_destroy,
528 .begin = si_query_sw_begin,
529 .end = si_query_sw_end,
530 .get_result = si_query_sw_get_result,
531 .get_result_resource = NULL
532 };
533
534 static struct pipe_query *si_query_sw_create(unsigned query_type)
535 {
536 struct si_query_sw *query;
537
538 query = CALLOC_STRUCT(si_query_sw);
539 if (!query)
540 return NULL;
541
542 query->b.type = query_type;
543 query->b.ops = &sw_query_ops;
544
545 return (struct pipe_query *)query;
546 }
547
548 void si_query_buffer_destroy(struct si_screen *sscreen, struct si_query_buffer *buffer)
549 {
550 struct si_query_buffer *prev = buffer->previous;
551
552 /* Release all query buffers. */
553 while (prev) {
554 struct si_query_buffer *qbuf = prev;
555 prev = prev->previous;
556 si_resource_reference(&qbuf->buf, NULL);
557 FREE(qbuf);
558 }
559
560 si_resource_reference(&buffer->buf, NULL);
561 }
562
563 void si_query_buffer_reset(struct si_context *sctx, struct si_query_buffer *buffer)
564 {
565 /* Discard all query buffers except for the oldest. */
566 while (buffer->previous) {
567 struct si_query_buffer *qbuf = buffer->previous;
568 buffer->previous = qbuf->previous;
569
570 si_resource_reference(&buffer->buf, NULL);
571 buffer->buf = qbuf->buf; /* move ownership */
572 FREE(qbuf);
573 }
574 buffer->results_end = 0;
575
576 if (!buffer->buf)
577 return;
578
579 /* Discard even the oldest buffer if it can't be mapped without a stall. */
580 if (si_rings_is_buffer_referenced(sctx, buffer->buf->buf, RADEON_USAGE_READWRITE) ||
581 !sctx->ws->buffer_wait(buffer->buf->buf, 0, RADEON_USAGE_READWRITE)) {
582 si_resource_reference(&buffer->buf, NULL);
583 } else {
584 buffer->unprepared = true;
585 }
586 }
587
588 bool si_query_buffer_alloc(struct si_context *sctx, struct si_query_buffer *buffer,
589 bool (*prepare_buffer)(struct si_context *, struct si_query_buffer*),
590 unsigned size)
591 {
592 bool unprepared = buffer->unprepared;
593 buffer->unprepared = false;
594
595 if (!buffer->buf || buffer->results_end + size > buffer->buf->b.b.width0) {
596 if (buffer->buf) {
597 struct si_query_buffer *qbuf = MALLOC_STRUCT(si_query_buffer);
598 memcpy(qbuf, buffer, sizeof(*qbuf));
599 buffer->previous = qbuf;
600 }
601 buffer->results_end = 0;
602
603 /* Queries are normally read by the CPU after
604 * being written by the gpu, hence staging is probably a good
605 * usage pattern.
606 */
607 struct si_screen *screen = sctx->screen;
608 unsigned buf_size = MAX2(size, screen->info.min_alloc_size);
609 buffer->buf = si_resource(
610 pipe_buffer_create(&screen->b, 0, PIPE_USAGE_STAGING, buf_size));
611 if (unlikely(!buffer->buf))
612 return false;
613 unprepared = true;
614 }
615
616 if (unprepared && prepare_buffer) {
617 if (unlikely(!prepare_buffer(sctx, buffer))) {
618 si_resource_reference(&buffer->buf, NULL);
619 return false;
620 }
621 }
622
623 return true;
624 }
625
626
627 void si_query_hw_destroy(struct si_context *sctx, struct si_query *squery)
628 {
629 struct si_query_hw *query = (struct si_query_hw *)squery;
630
631 si_query_buffer_destroy(sctx->screen, &query->buffer);
632 si_resource_reference(&query->workaround_buf, NULL);
633 FREE(squery);
634 }
635
636 static bool si_query_hw_prepare_buffer(struct si_context *sctx,
637 struct si_query_buffer *qbuf)
638 {
639 static const struct si_query_hw si_query_hw_s;
640 struct si_query_hw *query = container_of(qbuf, &si_query_hw_s, buffer);
641 struct si_screen *screen = sctx->screen;
642
643 /* The caller ensures that the buffer is currently unused by the GPU. */
644 uint32_t *results = screen->ws->buffer_map(qbuf->buf->buf, NULL,
645 PIPE_TRANSFER_WRITE |
646 PIPE_TRANSFER_UNSYNCHRONIZED);
647 if (!results)
648 return false;
649
650 memset(results, 0, qbuf->buf->b.b.width0);
651
652 if (query->b.type == PIPE_QUERY_OCCLUSION_COUNTER ||
653 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE ||
654 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
655 unsigned max_rbs = screen->info.num_render_backends;
656 unsigned enabled_rb_mask = screen->info.enabled_rb_mask;
657 unsigned num_results;
658 unsigned i, j;
659
660 /* Set top bits for unused backends. */
661 num_results = qbuf->buf->b.b.width0 / query->result_size;
662 for (j = 0; j < num_results; j++) {
663 for (i = 0; i < max_rbs; i++) {
664 if (!(enabled_rb_mask & (1<<i))) {
665 results[(i * 4)+1] = 0x80000000;
666 results[(i * 4)+3] = 0x80000000;
667 }
668 }
669 results += 4 * max_rbs;
670 }
671 }
672
673 return true;
674 }
675
676 static void si_query_hw_get_result_resource(struct si_context *sctx,
677 struct si_query *squery,
678 bool wait,
679 enum pipe_query_value_type result_type,
680 int index,
681 struct pipe_resource *resource,
682 unsigned offset);
683
684 static void si_query_hw_do_emit_start(struct si_context *sctx,
685 struct si_query_hw *query,
686 struct si_resource *buffer,
687 uint64_t va);
688 static void si_query_hw_do_emit_stop(struct si_context *sctx,
689 struct si_query_hw *query,
690 struct si_resource *buffer,
691 uint64_t va);
692 static void si_query_hw_add_result(struct si_screen *sscreen,
693 struct si_query_hw *, void *buffer,
694 union pipe_query_result *result);
695 static void si_query_hw_clear_result(struct si_query_hw *,
696 union pipe_query_result *);
697
698 static struct si_query_hw_ops query_hw_default_hw_ops = {
699 .prepare_buffer = si_query_hw_prepare_buffer,
700 .emit_start = si_query_hw_do_emit_start,
701 .emit_stop = si_query_hw_do_emit_stop,
702 .clear_result = si_query_hw_clear_result,
703 .add_result = si_query_hw_add_result,
704 };
705
706 static struct pipe_query *si_query_hw_create(struct si_screen *sscreen,
707 unsigned query_type,
708 unsigned index)
709 {
710 struct si_query_hw *query = CALLOC_STRUCT(si_query_hw);
711 if (!query)
712 return NULL;
713
714 query->b.type = query_type;
715 query->b.ops = &query_hw_ops;
716 query->ops = &query_hw_default_hw_ops;
717
718 switch (query_type) {
719 case PIPE_QUERY_OCCLUSION_COUNTER:
720 case PIPE_QUERY_OCCLUSION_PREDICATE:
721 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
722 query->result_size = 16 * sscreen->info.num_render_backends;
723 query->result_size += 16; /* for the fence + alignment */
724 query->b.num_cs_dw_suspend = 6 + si_cp_write_fence_dwords(sscreen);
725 break;
726 case SI_QUERY_TIME_ELAPSED_SDMA:
727 /* GET_GLOBAL_TIMESTAMP only works if the offset is a multiple of 32. */
728 query->result_size = 64;
729 break;
730 case PIPE_QUERY_TIME_ELAPSED:
731 query->result_size = 24;
732 query->b.num_cs_dw_suspend = 8 + si_cp_write_fence_dwords(sscreen);
733 break;
734 case PIPE_QUERY_TIMESTAMP:
735 query->result_size = 16;
736 query->b.num_cs_dw_suspend = 8 + si_cp_write_fence_dwords(sscreen);
737 query->flags = SI_QUERY_HW_FLAG_NO_START;
738 break;
739 case PIPE_QUERY_PRIMITIVES_EMITTED:
740 case PIPE_QUERY_PRIMITIVES_GENERATED:
741 case PIPE_QUERY_SO_STATISTICS:
742 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
743 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
744 query->result_size = 32;
745 query->b.num_cs_dw_suspend = 6;
746 query->stream = index;
747 break;
748 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
749 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
750 query->result_size = 32 * SI_MAX_STREAMS;
751 query->b.num_cs_dw_suspend = 6 * SI_MAX_STREAMS;
752 break;
753 case PIPE_QUERY_PIPELINE_STATISTICS:
754 /* 11 values on GCN. */
755 query->result_size = 11 * 16;
756 query->result_size += 8; /* for the fence + alignment */
757 query->b.num_cs_dw_suspend = 6 + si_cp_write_fence_dwords(sscreen);
758 break;
759 default:
760 assert(0);
761 FREE(query);
762 return NULL;
763 }
764
765 return (struct pipe_query *)query;
766 }
767
768 static void si_update_occlusion_query_state(struct si_context *sctx,
769 unsigned type, int diff)
770 {
771 if (type == PIPE_QUERY_OCCLUSION_COUNTER ||
772 type == PIPE_QUERY_OCCLUSION_PREDICATE ||
773 type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
774 bool old_enable = sctx->num_occlusion_queries != 0;
775 bool old_perfect_enable =
776 sctx->num_perfect_occlusion_queries != 0;
777 bool enable, perfect_enable;
778
779 sctx->num_occlusion_queries += diff;
780 assert(sctx->num_occlusion_queries >= 0);
781
782 if (type != PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
783 sctx->num_perfect_occlusion_queries += diff;
784 assert(sctx->num_perfect_occlusion_queries >= 0);
785 }
786
787 enable = sctx->num_occlusion_queries != 0;
788 perfect_enable = sctx->num_perfect_occlusion_queries != 0;
789
790 if (enable != old_enable || perfect_enable != old_perfect_enable) {
791 si_set_occlusion_query_state(sctx, old_perfect_enable);
792 }
793 }
794 }
795
796 static unsigned event_type_for_stream(unsigned stream)
797 {
798 switch (stream) {
799 default:
800 case 0: return V_028A90_SAMPLE_STREAMOUTSTATS;
801 case 1: return V_028A90_SAMPLE_STREAMOUTSTATS1;
802 case 2: return V_028A90_SAMPLE_STREAMOUTSTATS2;
803 case 3: return V_028A90_SAMPLE_STREAMOUTSTATS3;
804 }
805 }
806
807 static void emit_sample_streamout(struct radeon_cmdbuf *cs, uint64_t va,
808 unsigned stream)
809 {
810 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
811 radeon_emit(cs, EVENT_TYPE(event_type_for_stream(stream)) | EVENT_INDEX(3));
812 radeon_emit(cs, va);
813 radeon_emit(cs, va >> 32);
814 }
815
816 static void si_query_hw_do_emit_start(struct si_context *sctx,
817 struct si_query_hw *query,
818 struct si_resource *buffer,
819 uint64_t va)
820 {
821 struct radeon_cmdbuf *cs = sctx->gfx_cs;
822
823 switch (query->b.type) {
824 case SI_QUERY_TIME_ELAPSED_SDMA:
825 si_dma_emit_timestamp(sctx, buffer, va - buffer->gpu_address);
826 return;
827 case PIPE_QUERY_OCCLUSION_COUNTER:
828 case PIPE_QUERY_OCCLUSION_PREDICATE:
829 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
830 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
831 radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
832 radeon_emit(cs, va);
833 radeon_emit(cs, va >> 32);
834 break;
835 case PIPE_QUERY_PRIMITIVES_EMITTED:
836 case PIPE_QUERY_PRIMITIVES_GENERATED:
837 case PIPE_QUERY_SO_STATISTICS:
838 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
839 emit_sample_streamout(cs, va, query->stream);
840 break;
841 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
842 for (unsigned stream = 0; stream < SI_MAX_STREAMS; ++stream)
843 emit_sample_streamout(cs, va + 32 * stream, stream);
844 break;
845 case PIPE_QUERY_TIME_ELAPSED:
846 si_cp_release_mem(sctx, cs, V_028A90_BOTTOM_OF_PIPE_TS, 0,
847 EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
848 EOP_DATA_SEL_TIMESTAMP, NULL, va,
849 0, query->b.type);
850 break;
851 case PIPE_QUERY_PIPELINE_STATISTICS:
852 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
853 radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
854 radeon_emit(cs, va);
855 radeon_emit(cs, va >> 32);
856 break;
857 default:
858 assert(0);
859 }
860 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, query->buffer.buf, RADEON_USAGE_WRITE,
861 RADEON_PRIO_QUERY);
862 }
863
864 static void si_query_hw_emit_start(struct si_context *sctx,
865 struct si_query_hw *query)
866 {
867 uint64_t va;
868
869 if (!si_query_buffer_alloc(sctx, &query->buffer, query->ops->prepare_buffer,
870 query->result_size))
871 return;
872
873 si_update_occlusion_query_state(sctx, query->b.type, 1);
874 si_update_prims_generated_query_state(sctx, query->b.type, 1);
875
876 if (query->b.type == PIPE_QUERY_PIPELINE_STATISTICS)
877 sctx->num_pipeline_stat_queries++;
878
879 if (query->b.type != SI_QUERY_TIME_ELAPSED_SDMA)
880 si_need_gfx_cs_space(sctx);
881
882 va = query->buffer.buf->gpu_address + query->buffer.results_end;
883 query->ops->emit_start(sctx, query, query->buffer.buf, va);
884 }
885
886 static void si_query_hw_do_emit_stop(struct si_context *sctx,
887 struct si_query_hw *query,
888 struct si_resource *buffer,
889 uint64_t va)
890 {
891 struct radeon_cmdbuf *cs = sctx->gfx_cs;
892 uint64_t fence_va = 0;
893
894 switch (query->b.type) {
895 case SI_QUERY_TIME_ELAPSED_SDMA:
896 si_dma_emit_timestamp(sctx, buffer, va + 32 - buffer->gpu_address);
897 return;
898 case PIPE_QUERY_OCCLUSION_COUNTER:
899 case PIPE_QUERY_OCCLUSION_PREDICATE:
900 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
901 va += 8;
902 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
903 radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
904 radeon_emit(cs, va);
905 radeon_emit(cs, va >> 32);
906
907 fence_va = va + sctx->screen->info.num_render_backends * 16 - 8;
908 break;
909 case PIPE_QUERY_PRIMITIVES_EMITTED:
910 case PIPE_QUERY_PRIMITIVES_GENERATED:
911 case PIPE_QUERY_SO_STATISTICS:
912 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
913 va += 16;
914 emit_sample_streamout(cs, va, query->stream);
915 break;
916 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
917 va += 16;
918 for (unsigned stream = 0; stream < SI_MAX_STREAMS; ++stream)
919 emit_sample_streamout(cs, va + 32 * stream, stream);
920 break;
921 case PIPE_QUERY_TIME_ELAPSED:
922 va += 8;
923 /* fall through */
924 case PIPE_QUERY_TIMESTAMP:
925 si_cp_release_mem(sctx, cs, V_028A90_BOTTOM_OF_PIPE_TS, 0,
926 EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
927 EOP_DATA_SEL_TIMESTAMP, NULL, va,
928 0, query->b.type);
929 fence_va = va + 8;
930 break;
931 case PIPE_QUERY_PIPELINE_STATISTICS: {
932 unsigned sample_size = (query->result_size - 8) / 2;
933
934 va += sample_size;
935 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
936 radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
937 radeon_emit(cs, va);
938 radeon_emit(cs, va >> 32);
939
940 fence_va = va + sample_size;
941 break;
942 }
943 default:
944 assert(0);
945 }
946 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, query->buffer.buf, RADEON_USAGE_WRITE,
947 RADEON_PRIO_QUERY);
948
949 if (fence_va) {
950 si_cp_release_mem(sctx, cs, V_028A90_BOTTOM_OF_PIPE_TS, 0,
951 EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
952 EOP_DATA_SEL_VALUE_32BIT,
953 query->buffer.buf, fence_va, 0x80000000,
954 query->b.type);
955 }
956 }
957
958 static void si_query_hw_emit_stop(struct si_context *sctx,
959 struct si_query_hw *query)
960 {
961 uint64_t va;
962
963 /* The queries which need begin already called this in begin_query. */
964 if (query->flags & SI_QUERY_HW_FLAG_NO_START) {
965 si_need_gfx_cs_space(sctx);
966 if (!si_query_buffer_alloc(sctx, &query->buffer, query->ops->prepare_buffer,
967 query->result_size))
968 return;
969 }
970
971 if (!query->buffer.buf)
972 return; // previous buffer allocation failure
973
974 /* emit end query */
975 va = query->buffer.buf->gpu_address + query->buffer.results_end;
976
977 query->ops->emit_stop(sctx, query, query->buffer.buf, va);
978
979 query->buffer.results_end += query->result_size;
980
981 si_update_occlusion_query_state(sctx, query->b.type, -1);
982 si_update_prims_generated_query_state(sctx, query->b.type, -1);
983
984 if (query->b.type == PIPE_QUERY_PIPELINE_STATISTICS)
985 sctx->num_pipeline_stat_queries--;
986 }
987
988 static void emit_set_predicate(struct si_context *ctx,
989 struct si_resource *buf, uint64_t va,
990 uint32_t op)
991 {
992 struct radeon_cmdbuf *cs = ctx->gfx_cs;
993
994 if (ctx->chip_class >= GFX9) {
995 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
996 radeon_emit(cs, op);
997 radeon_emit(cs, va);
998 radeon_emit(cs, va >> 32);
999 } else {
1000 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1001 radeon_emit(cs, va);
1002 radeon_emit(cs, op | ((va >> 32) & 0xFF));
1003 }
1004 radeon_add_to_buffer_list(ctx, ctx->gfx_cs, buf, RADEON_USAGE_READ,
1005 RADEON_PRIO_QUERY);
1006 }
1007
1008 static void si_emit_query_predication(struct si_context *ctx)
1009 {
1010 struct si_query_hw *query = (struct si_query_hw *)ctx->render_cond;
1011 struct si_query_buffer *qbuf;
1012 uint32_t op;
1013 bool flag_wait, invert;
1014
1015 if (!query)
1016 return;
1017
1018 invert = ctx->render_cond_invert;
1019 flag_wait = ctx->render_cond_mode == PIPE_RENDER_COND_WAIT ||
1020 ctx->render_cond_mode == PIPE_RENDER_COND_BY_REGION_WAIT;
1021
1022 if (query->workaround_buf) {
1023 op = PRED_OP(PREDICATION_OP_BOOL64);
1024 } else {
1025 switch (query->b.type) {
1026 case PIPE_QUERY_OCCLUSION_COUNTER:
1027 case PIPE_QUERY_OCCLUSION_PREDICATE:
1028 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1029 op = PRED_OP(PREDICATION_OP_ZPASS);
1030 break;
1031 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1032 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
1033 op = PRED_OP(PREDICATION_OP_PRIMCOUNT);
1034 invert = !invert;
1035 break;
1036 default:
1037 assert(0);
1038 return;
1039 }
1040 }
1041
1042 /* if true then invert, see GL_ARB_conditional_render_inverted */
1043 if (invert)
1044 op |= PREDICATION_DRAW_NOT_VISIBLE; /* Draw if not visible or overflow */
1045 else
1046 op |= PREDICATION_DRAW_VISIBLE; /* Draw if visible or no overflow */
1047
1048 /* Use the value written by compute shader as a workaround. Note that
1049 * the wait flag does not apply in this predication mode.
1050 *
1051 * The shader outputs the result value to L2. Workarounds only affect GFX8
1052 * and later, where the CP reads data from L2, so we don't need an
1053 * additional flush.
1054 */
1055 if (query->workaround_buf) {
1056 uint64_t va = query->workaround_buf->gpu_address + query->workaround_offset;
1057 emit_set_predicate(ctx, query->workaround_buf, va, op);
1058 return;
1059 }
1060
1061 op |= flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW;
1062
1063 /* emit predicate packets for all data blocks */
1064 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
1065 unsigned results_base = 0;
1066 uint64_t va_base = qbuf->buf->gpu_address;
1067
1068 while (results_base < qbuf->results_end) {
1069 uint64_t va = va_base + results_base;
1070
1071 if (query->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE) {
1072 for (unsigned stream = 0; stream < SI_MAX_STREAMS; ++stream) {
1073 emit_set_predicate(ctx, qbuf->buf, va + 32 * stream, op);
1074
1075 /* set CONTINUE bit for all packets except the first */
1076 op |= PREDICATION_CONTINUE;
1077 }
1078 } else {
1079 emit_set_predicate(ctx, qbuf->buf, va, op);
1080 op |= PREDICATION_CONTINUE;
1081 }
1082
1083 results_base += query->result_size;
1084 }
1085 }
1086 }
1087
1088 static struct pipe_query *si_create_query(struct pipe_context *ctx, unsigned query_type, unsigned index)
1089 {
1090 struct si_screen *sscreen =
1091 (struct si_screen *)ctx->screen;
1092
1093 if (query_type == PIPE_QUERY_TIMESTAMP_DISJOINT ||
1094 query_type == PIPE_QUERY_GPU_FINISHED ||
1095 (query_type >= PIPE_QUERY_DRIVER_SPECIFIC &&
1096 query_type != SI_QUERY_TIME_ELAPSED_SDMA))
1097 return si_query_sw_create(query_type);
1098
1099 return si_query_hw_create(sscreen, query_type, index);
1100 }
1101
1102 static void si_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
1103 {
1104 struct si_context *sctx = (struct si_context *)ctx;
1105 struct si_query *squery = (struct si_query *)query;
1106
1107 squery->ops->destroy(sctx, squery);
1108 }
1109
1110 static boolean si_begin_query(struct pipe_context *ctx,
1111 struct pipe_query *query)
1112 {
1113 struct si_context *sctx = (struct si_context *)ctx;
1114 struct si_query *squery = (struct si_query *)query;
1115
1116 return squery->ops->begin(sctx, squery);
1117 }
1118
1119 bool si_query_hw_begin(struct si_context *sctx,
1120 struct si_query *squery)
1121 {
1122 struct si_query_hw *query = (struct si_query_hw *)squery;
1123
1124 if (query->flags & SI_QUERY_HW_FLAG_NO_START) {
1125 assert(0);
1126 return false;
1127 }
1128
1129 if (!(query->flags & SI_QUERY_HW_FLAG_BEGIN_RESUMES))
1130 si_query_buffer_reset(sctx, &query->buffer);
1131
1132 si_resource_reference(&query->workaround_buf, NULL);
1133
1134 si_query_hw_emit_start(sctx, query);
1135 if (!query->buffer.buf)
1136 return false;
1137
1138 LIST_ADDTAIL(&query->b.active_list, &sctx->active_queries);
1139 sctx->num_cs_dw_queries_suspend += query->b.num_cs_dw_suspend;
1140 return true;
1141 }
1142
1143 static bool si_end_query(struct pipe_context *ctx, struct pipe_query *query)
1144 {
1145 struct si_context *sctx = (struct si_context *)ctx;
1146 struct si_query *squery = (struct si_query *)query;
1147
1148 return squery->ops->end(sctx, squery);
1149 }
1150
1151 bool si_query_hw_end(struct si_context *sctx,
1152 struct si_query *squery)
1153 {
1154 struct si_query_hw *query = (struct si_query_hw *)squery;
1155
1156 if (query->flags & SI_QUERY_HW_FLAG_NO_START)
1157 si_query_buffer_reset(sctx, &query->buffer);
1158
1159 si_query_hw_emit_stop(sctx, query);
1160
1161 if (!(query->flags & SI_QUERY_HW_FLAG_NO_START)) {
1162 LIST_DELINIT(&query->b.active_list);
1163 sctx->num_cs_dw_queries_suspend -= query->b.num_cs_dw_suspend;
1164 }
1165
1166 if (!query->buffer.buf)
1167 return false;
1168
1169 return true;
1170 }
1171
1172 static void si_get_hw_query_params(struct si_context *sctx,
1173 struct si_query_hw *squery, int index,
1174 struct si_hw_query_params *params)
1175 {
1176 unsigned max_rbs = sctx->screen->info.num_render_backends;
1177
1178 params->pair_stride = 0;
1179 params->pair_count = 1;
1180
1181 switch (squery->b.type) {
1182 case PIPE_QUERY_OCCLUSION_COUNTER:
1183 case PIPE_QUERY_OCCLUSION_PREDICATE:
1184 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1185 params->start_offset = 0;
1186 params->end_offset = 8;
1187 params->fence_offset = max_rbs * 16;
1188 params->pair_stride = 16;
1189 params->pair_count = max_rbs;
1190 break;
1191 case PIPE_QUERY_TIME_ELAPSED:
1192 params->start_offset = 0;
1193 params->end_offset = 8;
1194 params->fence_offset = 16;
1195 break;
1196 case PIPE_QUERY_TIMESTAMP:
1197 params->start_offset = 0;
1198 params->end_offset = 0;
1199 params->fence_offset = 8;
1200 break;
1201 case PIPE_QUERY_PRIMITIVES_EMITTED:
1202 params->start_offset = 8;
1203 params->end_offset = 24;
1204 params->fence_offset = params->end_offset + 4;
1205 break;
1206 case PIPE_QUERY_PRIMITIVES_GENERATED:
1207 params->start_offset = 0;
1208 params->end_offset = 16;
1209 params->fence_offset = params->end_offset + 4;
1210 break;
1211 case PIPE_QUERY_SO_STATISTICS:
1212 params->start_offset = 8 - index * 8;
1213 params->end_offset = 24 - index * 8;
1214 params->fence_offset = params->end_offset + 4;
1215 break;
1216 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
1217 params->pair_count = SI_MAX_STREAMS;
1218 params->pair_stride = 32;
1219 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1220 params->start_offset = 0;
1221 params->end_offset = 16;
1222
1223 /* We can re-use the high dword of the last 64-bit value as a
1224 * fence: it is initialized as 0, and the high bit is set by
1225 * the write of the streamout stats event.
1226 */
1227 params->fence_offset = squery->result_size - 4;
1228 break;
1229 case PIPE_QUERY_PIPELINE_STATISTICS:
1230 {
1231 static const unsigned offsets[] = {56, 48, 24, 32, 40, 16, 8, 0, 64, 72, 80};
1232 params->start_offset = offsets[index];
1233 params->end_offset = 88 + offsets[index];
1234 params->fence_offset = 2 * 88;
1235 break;
1236 }
1237 default:
1238 unreachable("si_get_hw_query_params unsupported");
1239 }
1240 }
1241
1242 static unsigned si_query_read_result(void *map, unsigned start_index, unsigned end_index,
1243 bool test_status_bit)
1244 {
1245 uint32_t *current_result = (uint32_t*)map;
1246 uint64_t start, end;
1247
1248 start = (uint64_t)current_result[start_index] |
1249 (uint64_t)current_result[start_index+1] << 32;
1250 end = (uint64_t)current_result[end_index] |
1251 (uint64_t)current_result[end_index+1] << 32;
1252
1253 if (!test_status_bit ||
1254 ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) {
1255 return end - start;
1256 }
1257 return 0;
1258 }
1259
1260 static void si_query_hw_add_result(struct si_screen *sscreen,
1261 struct si_query_hw *query,
1262 void *buffer,
1263 union pipe_query_result *result)
1264 {
1265 unsigned max_rbs = sscreen->info.num_render_backends;
1266
1267 switch (query->b.type) {
1268 case PIPE_QUERY_OCCLUSION_COUNTER: {
1269 for (unsigned i = 0; i < max_rbs; ++i) {
1270 unsigned results_base = i * 16;
1271 result->u64 +=
1272 si_query_read_result(buffer + results_base, 0, 2, true);
1273 }
1274 break;
1275 }
1276 case PIPE_QUERY_OCCLUSION_PREDICATE:
1277 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: {
1278 for (unsigned i = 0; i < max_rbs; ++i) {
1279 unsigned results_base = i * 16;
1280 result->b = result->b ||
1281 si_query_read_result(buffer + results_base, 0, 2, true) != 0;
1282 }
1283 break;
1284 }
1285 case PIPE_QUERY_TIME_ELAPSED:
1286 result->u64 += si_query_read_result(buffer, 0, 2, false);
1287 break;
1288 case SI_QUERY_TIME_ELAPSED_SDMA:
1289 result->u64 += si_query_read_result(buffer, 0, 32/4, false);
1290 break;
1291 case PIPE_QUERY_TIMESTAMP:
1292 result->u64 = *(uint64_t*)buffer;
1293 break;
1294 case PIPE_QUERY_PRIMITIVES_EMITTED:
1295 /* SAMPLE_STREAMOUTSTATS stores this structure:
1296 * {
1297 * u64 NumPrimitivesWritten;
1298 * u64 PrimitiveStorageNeeded;
1299 * }
1300 * We only need NumPrimitivesWritten here. */
1301 result->u64 += si_query_read_result(buffer, 2, 6, true);
1302 break;
1303 case PIPE_QUERY_PRIMITIVES_GENERATED:
1304 /* Here we read PrimitiveStorageNeeded. */
1305 result->u64 += si_query_read_result(buffer, 0, 4, true);
1306 break;
1307 case PIPE_QUERY_SO_STATISTICS:
1308 result->so_statistics.num_primitives_written +=
1309 si_query_read_result(buffer, 2, 6, true);
1310 result->so_statistics.primitives_storage_needed +=
1311 si_query_read_result(buffer, 0, 4, true);
1312 break;
1313 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1314 result->b = result->b ||
1315 si_query_read_result(buffer, 2, 6, true) !=
1316 si_query_read_result(buffer, 0, 4, true);
1317 break;
1318 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
1319 for (unsigned stream = 0; stream < SI_MAX_STREAMS; ++stream) {
1320 result->b = result->b ||
1321 si_query_read_result(buffer, 2, 6, true) !=
1322 si_query_read_result(buffer, 0, 4, true);
1323 buffer = (char *)buffer + 32;
1324 }
1325 break;
1326 case PIPE_QUERY_PIPELINE_STATISTICS:
1327 result->pipeline_statistics.ps_invocations +=
1328 si_query_read_result(buffer, 0, 22, false);
1329 result->pipeline_statistics.c_primitives +=
1330 si_query_read_result(buffer, 2, 24, false);
1331 result->pipeline_statistics.c_invocations +=
1332 si_query_read_result(buffer, 4, 26, false);
1333 result->pipeline_statistics.vs_invocations +=
1334 si_query_read_result(buffer, 6, 28, false);
1335 result->pipeline_statistics.gs_invocations +=
1336 si_query_read_result(buffer, 8, 30, false);
1337 result->pipeline_statistics.gs_primitives +=
1338 si_query_read_result(buffer, 10, 32, false);
1339 result->pipeline_statistics.ia_primitives +=
1340 si_query_read_result(buffer, 12, 34, false);
1341 result->pipeline_statistics.ia_vertices +=
1342 si_query_read_result(buffer, 14, 36, false);
1343 result->pipeline_statistics.hs_invocations +=
1344 si_query_read_result(buffer, 16, 38, false);
1345 result->pipeline_statistics.ds_invocations +=
1346 si_query_read_result(buffer, 18, 40, false);
1347 result->pipeline_statistics.cs_invocations +=
1348 si_query_read_result(buffer, 20, 42, false);
1349 #if 0 /* for testing */
1350 printf("Pipeline stats: IA verts=%llu, IA prims=%llu, VS=%llu, HS=%llu, "
1351 "DS=%llu, GS=%llu, GS prims=%llu, Clipper=%llu, "
1352 "Clipper prims=%llu, PS=%llu, CS=%llu\n",
1353 result->pipeline_statistics.ia_vertices,
1354 result->pipeline_statistics.ia_primitives,
1355 result->pipeline_statistics.vs_invocations,
1356 result->pipeline_statistics.hs_invocations,
1357 result->pipeline_statistics.ds_invocations,
1358 result->pipeline_statistics.gs_invocations,
1359 result->pipeline_statistics.gs_primitives,
1360 result->pipeline_statistics.c_invocations,
1361 result->pipeline_statistics.c_primitives,
1362 result->pipeline_statistics.ps_invocations,
1363 result->pipeline_statistics.cs_invocations);
1364 #endif
1365 break;
1366 default:
1367 assert(0);
1368 }
1369 }
1370
1371 void si_query_hw_suspend(struct si_context *sctx, struct si_query *query)
1372 {
1373 si_query_hw_emit_stop(sctx, (struct si_query_hw *)query);
1374 }
1375
1376 void si_query_hw_resume(struct si_context *sctx, struct si_query *query)
1377 {
1378 si_query_hw_emit_start(sctx, (struct si_query_hw *)query);
1379 }
1380
1381 static const struct si_query_ops query_hw_ops = {
1382 .destroy = si_query_hw_destroy,
1383 .begin = si_query_hw_begin,
1384 .end = si_query_hw_end,
1385 .get_result = si_query_hw_get_result,
1386 .get_result_resource = si_query_hw_get_result_resource,
1387
1388 .suspend = si_query_hw_suspend,
1389 .resume = si_query_hw_resume,
1390 };
1391
1392 static boolean si_get_query_result(struct pipe_context *ctx,
1393 struct pipe_query *query, boolean wait,
1394 union pipe_query_result *result)
1395 {
1396 struct si_context *sctx = (struct si_context *)ctx;
1397 struct si_query *squery = (struct si_query *)query;
1398
1399 return squery->ops->get_result(sctx, squery, wait, result);
1400 }
1401
1402 static void si_get_query_result_resource(struct pipe_context *ctx,
1403 struct pipe_query *query,
1404 boolean wait,
1405 enum pipe_query_value_type result_type,
1406 int index,
1407 struct pipe_resource *resource,
1408 unsigned offset)
1409 {
1410 struct si_context *sctx = (struct si_context *)ctx;
1411 struct si_query *squery = (struct si_query *)query;
1412
1413 squery->ops->get_result_resource(sctx, squery, wait, result_type, index,
1414 resource, offset);
1415 }
1416
1417 static void si_query_hw_clear_result(struct si_query_hw *query,
1418 union pipe_query_result *result)
1419 {
1420 util_query_clear_result(result, query->b.type);
1421 }
1422
1423 bool si_query_hw_get_result(struct si_context *sctx,
1424 struct si_query *squery,
1425 bool wait, union pipe_query_result *result)
1426 {
1427 struct si_screen *sscreen = sctx->screen;
1428 struct si_query_hw *query = (struct si_query_hw *)squery;
1429 struct si_query_buffer *qbuf;
1430
1431 query->ops->clear_result(query, result);
1432
1433 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
1434 unsigned usage = PIPE_TRANSFER_READ |
1435 (wait ? 0 : PIPE_TRANSFER_DONTBLOCK);
1436 unsigned results_base = 0;
1437 void *map;
1438
1439 if (squery->b.flushed)
1440 map = sctx->ws->buffer_map(qbuf->buf->buf, NULL, usage);
1441 else
1442 map = si_buffer_map_sync_with_rings(sctx, qbuf->buf, usage);
1443
1444 if (!map)
1445 return false;
1446
1447 while (results_base != qbuf->results_end) {
1448 query->ops->add_result(sscreen, query, map + results_base,
1449 result);
1450 results_base += query->result_size;
1451 }
1452 }
1453
1454 /* Convert the time to expected units. */
1455 if (squery->type == PIPE_QUERY_TIME_ELAPSED ||
1456 squery->type == SI_QUERY_TIME_ELAPSED_SDMA ||
1457 squery->type == PIPE_QUERY_TIMESTAMP) {
1458 result->u64 = (1000000 * result->u64) / sscreen->info.clock_crystal_freq;
1459 }
1460 return true;
1461 }
1462
1463 static void si_query_hw_get_result_resource(struct si_context *sctx,
1464 struct si_query *squery,
1465 bool wait,
1466 enum pipe_query_value_type result_type,
1467 int index,
1468 struct pipe_resource *resource,
1469 unsigned offset)
1470 {
1471 struct si_query_hw *query = (struct si_query_hw *)squery;
1472 struct si_query_buffer *qbuf;
1473 struct si_query_buffer *qbuf_prev;
1474 struct pipe_resource *tmp_buffer = NULL;
1475 unsigned tmp_buffer_offset = 0;
1476 struct si_qbo_state saved_state = {};
1477 struct pipe_grid_info grid = {};
1478 struct pipe_constant_buffer constant_buffer = {};
1479 struct pipe_shader_buffer ssbo[3];
1480 struct si_hw_query_params params;
1481 struct {
1482 uint32_t end_offset;
1483 uint32_t result_stride;
1484 uint32_t result_count;
1485 uint32_t config;
1486 uint32_t fence_offset;
1487 uint32_t pair_stride;
1488 uint32_t pair_count;
1489 } consts;
1490
1491 if (!sctx->query_result_shader) {
1492 sctx->query_result_shader = si_create_query_result_cs(sctx);
1493 if (!sctx->query_result_shader)
1494 return;
1495 }
1496
1497 if (query->buffer.previous) {
1498 u_suballocator_alloc(sctx->allocator_zeroed_memory, 16, 16,
1499 &tmp_buffer_offset, &tmp_buffer);
1500 if (!tmp_buffer)
1501 return;
1502 }
1503
1504 si_save_qbo_state(sctx, &saved_state);
1505
1506 si_get_hw_query_params(sctx, query, index >= 0 ? index : 0, &params);
1507 consts.end_offset = params.end_offset - params.start_offset;
1508 consts.fence_offset = params.fence_offset - params.start_offset;
1509 consts.result_stride = query->result_size;
1510 consts.pair_stride = params.pair_stride;
1511 consts.pair_count = params.pair_count;
1512
1513 constant_buffer.buffer_size = sizeof(consts);
1514 constant_buffer.user_buffer = &consts;
1515
1516 ssbo[1].buffer = tmp_buffer;
1517 ssbo[1].buffer_offset = tmp_buffer_offset;
1518 ssbo[1].buffer_size = 16;
1519
1520 ssbo[2] = ssbo[1];
1521
1522 sctx->b.bind_compute_state(&sctx->b, sctx->query_result_shader);
1523
1524 grid.block[0] = 1;
1525 grid.block[1] = 1;
1526 grid.block[2] = 1;
1527 grid.grid[0] = 1;
1528 grid.grid[1] = 1;
1529 grid.grid[2] = 1;
1530
1531 consts.config = 0;
1532 if (index < 0)
1533 consts.config |= 4;
1534 if (query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE ||
1535 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE)
1536 consts.config |= 8;
1537 else if (query->b.type == PIPE_QUERY_SO_OVERFLOW_PREDICATE ||
1538 query->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE)
1539 consts.config |= 8 | 256;
1540 else if (query->b.type == PIPE_QUERY_TIMESTAMP ||
1541 query->b.type == PIPE_QUERY_TIME_ELAPSED)
1542 consts.config |= 32;
1543
1544 switch (result_type) {
1545 case PIPE_QUERY_TYPE_U64:
1546 case PIPE_QUERY_TYPE_I64:
1547 consts.config |= 64;
1548 break;
1549 case PIPE_QUERY_TYPE_I32:
1550 consts.config |= 128;
1551 break;
1552 case PIPE_QUERY_TYPE_U32:
1553 break;
1554 }
1555
1556 sctx->flags |= sctx->screen->barrier_flags.cp_to_L2;
1557
1558 for (qbuf = &query->buffer; qbuf; qbuf = qbuf_prev) {
1559 if (query->b.type != PIPE_QUERY_TIMESTAMP) {
1560 qbuf_prev = qbuf->previous;
1561 consts.result_count = qbuf->results_end / query->result_size;
1562 consts.config &= ~3;
1563 if (qbuf != &query->buffer)
1564 consts.config |= 1;
1565 if (qbuf->previous)
1566 consts.config |= 2;
1567 } else {
1568 /* Only read the last timestamp. */
1569 qbuf_prev = NULL;
1570 consts.result_count = 0;
1571 consts.config |= 16;
1572 params.start_offset += qbuf->results_end - query->result_size;
1573 }
1574
1575 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, &constant_buffer);
1576
1577 ssbo[0].buffer = &qbuf->buf->b.b;
1578 ssbo[0].buffer_offset = params.start_offset;
1579 ssbo[0].buffer_size = qbuf->results_end - params.start_offset;
1580
1581 if (!qbuf->previous) {
1582 ssbo[2].buffer = resource;
1583 ssbo[2].buffer_offset = offset;
1584 ssbo[2].buffer_size = 8;
1585
1586 si_resource(resource)->TC_L2_dirty = true;
1587 }
1588
1589 sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, ssbo,
1590 1 << 2);
1591
1592 if (wait && qbuf == &query->buffer) {
1593 uint64_t va;
1594
1595 /* Wait for result availability. Wait only for readiness
1596 * of the last entry, since the fence writes should be
1597 * serialized in the CP.
1598 */
1599 va = qbuf->buf->gpu_address + qbuf->results_end - query->result_size;
1600 va += params.fence_offset;
1601
1602 si_cp_wait_mem(sctx, sctx->gfx_cs, va, 0x80000000,
1603 0x80000000, WAIT_REG_MEM_EQUAL);
1604 }
1605
1606 sctx->b.launch_grid(&sctx->b, &grid);
1607 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
1608 }
1609
1610 si_restore_qbo_state(sctx, &saved_state);
1611 pipe_resource_reference(&tmp_buffer, NULL);
1612 }
1613
1614 static void si_render_condition(struct pipe_context *ctx,
1615 struct pipe_query *query,
1616 boolean condition,
1617 enum pipe_render_cond_flag mode)
1618 {
1619 struct si_context *sctx = (struct si_context *)ctx;
1620 struct si_query_hw *squery = (struct si_query_hw *)query;
1621 struct si_atom *atom = &sctx->atoms.s.render_cond;
1622
1623 if (query) {
1624 bool needs_workaround = false;
1625
1626 /* There was a firmware regression in GFX8 which causes successive
1627 * SET_PREDICATION packets to give the wrong answer for
1628 * non-inverted stream overflow predication.
1629 */
1630 if (((sctx->chip_class == GFX8 && sctx->screen->info.pfp_fw_feature < 49) ||
1631 (sctx->chip_class == GFX9 && sctx->screen->info.pfp_fw_feature < 38)) &&
1632 !condition &&
1633 (squery->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE ||
1634 (squery->b.type == PIPE_QUERY_SO_OVERFLOW_PREDICATE &&
1635 (squery->buffer.previous ||
1636 squery->buffer.results_end > squery->result_size)))) {
1637 needs_workaround = true;
1638 }
1639
1640 if (needs_workaround && !squery->workaround_buf) {
1641 bool old_force_off = sctx->render_cond_force_off;
1642 sctx->render_cond_force_off = true;
1643
1644 u_suballocator_alloc(
1645 sctx->allocator_zeroed_memory, 8, 8,
1646 &squery->workaround_offset,
1647 (struct pipe_resource **)&squery->workaround_buf);
1648
1649 /* Reset to NULL to avoid a redundant SET_PREDICATION
1650 * from launching the compute grid.
1651 */
1652 sctx->render_cond = NULL;
1653
1654 ctx->get_query_result_resource(
1655 ctx, query, true, PIPE_QUERY_TYPE_U64, 0,
1656 &squery->workaround_buf->b.b, squery->workaround_offset);
1657
1658 /* Settings this in the render cond atom is too late,
1659 * so set it here. */
1660 sctx->flags |= sctx->screen->barrier_flags.L2_to_cp |
1661 SI_CONTEXT_FLUSH_FOR_RENDER_COND;
1662
1663 sctx->render_cond_force_off = old_force_off;
1664 }
1665 }
1666
1667 sctx->render_cond = query;
1668 sctx->render_cond_invert = condition;
1669 sctx->render_cond_mode = mode;
1670
1671 si_set_atom_dirty(sctx, atom, query != NULL);
1672 }
1673
1674 void si_suspend_queries(struct si_context *sctx)
1675 {
1676 struct si_query *query;
1677
1678 LIST_FOR_EACH_ENTRY(query, &sctx->active_queries, active_list)
1679 query->ops->suspend(sctx, query);
1680 }
1681
1682 void si_resume_queries(struct si_context *sctx)
1683 {
1684 struct si_query *query;
1685
1686 /* Check CS space here. Resuming must not be interrupted by flushes. */
1687 si_need_gfx_cs_space(sctx);
1688
1689 LIST_FOR_EACH_ENTRY(query, &sctx->active_queries, active_list)
1690 query->ops->resume(sctx, query);
1691 }
1692
1693 #define XFULL(name_, query_type_, type_, result_type_, group_id_) \
1694 { \
1695 .name = name_, \
1696 .query_type = SI_QUERY_##query_type_, \
1697 .type = PIPE_DRIVER_QUERY_TYPE_##type_, \
1698 .result_type = PIPE_DRIVER_QUERY_RESULT_TYPE_##result_type_, \
1699 .group_id = group_id_ \
1700 }
1701
1702 #define X(name_, query_type_, type_, result_type_) \
1703 XFULL(name_, query_type_, type_, result_type_, ~(unsigned)0)
1704
1705 #define XG(group_, name_, query_type_, type_, result_type_) \
1706 XFULL(name_, query_type_, type_, result_type_, SI_QUERY_GROUP_##group_)
1707
1708 static struct pipe_driver_query_info si_driver_query_list[] = {
1709 X("num-compilations", NUM_COMPILATIONS, UINT64, CUMULATIVE),
1710 X("num-shaders-created", NUM_SHADERS_CREATED, UINT64, CUMULATIVE),
1711 X("num-shader-cache-hits", NUM_SHADER_CACHE_HITS, UINT64, CUMULATIVE),
1712 X("draw-calls", DRAW_CALLS, UINT64, AVERAGE),
1713 X("decompress-calls", DECOMPRESS_CALLS, UINT64, AVERAGE),
1714 X("MRT-draw-calls", MRT_DRAW_CALLS, UINT64, AVERAGE),
1715 X("prim-restart-calls", PRIM_RESTART_CALLS, UINT64, AVERAGE),
1716 X("spill-draw-calls", SPILL_DRAW_CALLS, UINT64, AVERAGE),
1717 X("compute-calls", COMPUTE_CALLS, UINT64, AVERAGE),
1718 X("spill-compute-calls", SPILL_COMPUTE_CALLS, UINT64, AVERAGE),
1719 X("dma-calls", DMA_CALLS, UINT64, AVERAGE),
1720 X("cp-dma-calls", CP_DMA_CALLS, UINT64, AVERAGE),
1721 X("num-vs-flushes", NUM_VS_FLUSHES, UINT64, AVERAGE),
1722 X("num-ps-flushes", NUM_PS_FLUSHES, UINT64, AVERAGE),
1723 X("num-cs-flushes", NUM_CS_FLUSHES, UINT64, AVERAGE),
1724 X("num-CB-cache-flushes", NUM_CB_CACHE_FLUSHES, UINT64, AVERAGE),
1725 X("num-DB-cache-flushes", NUM_DB_CACHE_FLUSHES, UINT64, AVERAGE),
1726 X("num-L2-invalidates", NUM_L2_INVALIDATES, UINT64, AVERAGE),
1727 X("num-L2-writebacks", NUM_L2_WRITEBACKS, UINT64, AVERAGE),
1728 X("num-resident-handles", NUM_RESIDENT_HANDLES, UINT64, AVERAGE),
1729 X("tc-offloaded-slots", TC_OFFLOADED_SLOTS, UINT64, AVERAGE),
1730 X("tc-direct-slots", TC_DIRECT_SLOTS, UINT64, AVERAGE),
1731 X("tc-num-syncs", TC_NUM_SYNCS, UINT64, AVERAGE),
1732 X("CS-thread-busy", CS_THREAD_BUSY, UINT64, AVERAGE),
1733 X("gallium-thread-busy", GALLIUM_THREAD_BUSY, UINT64, AVERAGE),
1734 X("requested-VRAM", REQUESTED_VRAM, BYTES, AVERAGE),
1735 X("requested-GTT", REQUESTED_GTT, BYTES, AVERAGE),
1736 X("mapped-VRAM", MAPPED_VRAM, BYTES, AVERAGE),
1737 X("mapped-GTT", MAPPED_GTT, BYTES, AVERAGE),
1738 X("buffer-wait-time", BUFFER_WAIT_TIME, MICROSECONDS, CUMULATIVE),
1739 X("num-mapped-buffers", NUM_MAPPED_BUFFERS, UINT64, AVERAGE),
1740 X("num-GFX-IBs", NUM_GFX_IBS, UINT64, AVERAGE),
1741 X("num-SDMA-IBs", NUM_SDMA_IBS, UINT64, AVERAGE),
1742 X("GFX-BO-list-size", GFX_BO_LIST_SIZE, UINT64, AVERAGE),
1743 X("GFX-IB-size", GFX_IB_SIZE, UINT64, AVERAGE),
1744 X("num-bytes-moved", NUM_BYTES_MOVED, BYTES, CUMULATIVE),
1745 X("num-evictions", NUM_EVICTIONS, UINT64, CUMULATIVE),
1746 X("VRAM-CPU-page-faults", NUM_VRAM_CPU_PAGE_FAULTS, UINT64, CUMULATIVE),
1747 X("VRAM-usage", VRAM_USAGE, BYTES, AVERAGE),
1748 X("VRAM-vis-usage", VRAM_VIS_USAGE, BYTES, AVERAGE),
1749 X("GTT-usage", GTT_USAGE, BYTES, AVERAGE),
1750 X("back-buffer-ps-draw-ratio", BACK_BUFFER_PS_DRAW_RATIO, UINT64, AVERAGE),
1751
1752 /* GPIN queries are for the benefit of old versions of GPUPerfStudio,
1753 * which use it as a fallback path to detect the GPU type.
1754 *
1755 * Note: The names of these queries are significant for GPUPerfStudio
1756 * (and possibly their order as well). */
1757 XG(GPIN, "GPIN_000", GPIN_ASIC_ID, UINT, AVERAGE),
1758 XG(GPIN, "GPIN_001", GPIN_NUM_SIMD, UINT, AVERAGE),
1759 XG(GPIN, "GPIN_002", GPIN_NUM_RB, UINT, AVERAGE),
1760 XG(GPIN, "GPIN_003", GPIN_NUM_SPI, UINT, AVERAGE),
1761 XG(GPIN, "GPIN_004", GPIN_NUM_SE, UINT, AVERAGE),
1762
1763 X("temperature", GPU_TEMPERATURE, UINT64, AVERAGE),
1764 X("shader-clock", CURRENT_GPU_SCLK, HZ, AVERAGE),
1765 X("memory-clock", CURRENT_GPU_MCLK, HZ, AVERAGE),
1766
1767 /* The following queries must be at the end of the list because their
1768 * availability is adjusted dynamically based on the DRM version. */
1769 X("GPU-load", GPU_LOAD, UINT64, AVERAGE),
1770 X("GPU-shaders-busy", GPU_SHADERS_BUSY, UINT64, AVERAGE),
1771 X("GPU-ta-busy", GPU_TA_BUSY, UINT64, AVERAGE),
1772 X("GPU-gds-busy", GPU_GDS_BUSY, UINT64, AVERAGE),
1773 X("GPU-vgt-busy", GPU_VGT_BUSY, UINT64, AVERAGE),
1774 X("GPU-ia-busy", GPU_IA_BUSY, UINT64, AVERAGE),
1775 X("GPU-sx-busy", GPU_SX_BUSY, UINT64, AVERAGE),
1776 X("GPU-wd-busy", GPU_WD_BUSY, UINT64, AVERAGE),
1777 X("GPU-bci-busy", GPU_BCI_BUSY, UINT64, AVERAGE),
1778 X("GPU-sc-busy", GPU_SC_BUSY, UINT64, AVERAGE),
1779 X("GPU-pa-busy", GPU_PA_BUSY, UINT64, AVERAGE),
1780 X("GPU-db-busy", GPU_DB_BUSY, UINT64, AVERAGE),
1781 X("GPU-cp-busy", GPU_CP_BUSY, UINT64, AVERAGE),
1782 X("GPU-cb-busy", GPU_CB_BUSY, UINT64, AVERAGE),
1783
1784 /* SRBM_STATUS2 */
1785 X("GPU-sdma-busy", GPU_SDMA_BUSY, UINT64, AVERAGE),
1786
1787 /* CP_STAT */
1788 X("GPU-pfp-busy", GPU_PFP_BUSY, UINT64, AVERAGE),
1789 X("GPU-meq-busy", GPU_MEQ_BUSY, UINT64, AVERAGE),
1790 X("GPU-me-busy", GPU_ME_BUSY, UINT64, AVERAGE),
1791 X("GPU-surf-sync-busy", GPU_SURF_SYNC_BUSY, UINT64, AVERAGE),
1792 X("GPU-cp-dma-busy", GPU_CP_DMA_BUSY, UINT64, AVERAGE),
1793 X("GPU-scratch-ram-busy", GPU_SCRATCH_RAM_BUSY, UINT64, AVERAGE),
1794
1795 X("pd-num-prims-accepted", PD_NUM_PRIMS_ACCEPTED, UINT64, AVERAGE),
1796 X("pd-num-prims-rejected", PD_NUM_PRIMS_REJECTED, UINT64, AVERAGE),
1797 X("pd-num-prims-ineligible", PD_NUM_PRIMS_INELIGIBLE,UINT64, AVERAGE),
1798 };
1799
1800 #undef X
1801 #undef XG
1802 #undef XFULL
1803
1804 static unsigned si_get_num_queries(struct si_screen *sscreen)
1805 {
1806 /* amdgpu */
1807 if (sscreen->info.is_amdgpu) {
1808 if (sscreen->info.chip_class >= GFX8)
1809 return ARRAY_SIZE(si_driver_query_list);
1810 else
1811 return ARRAY_SIZE(si_driver_query_list) - 7;
1812 }
1813
1814 /* radeon */
1815 if (sscreen->info.has_read_registers_query) {
1816 if (sscreen->info.chip_class == GFX7)
1817 return ARRAY_SIZE(si_driver_query_list) - 6;
1818 else
1819 return ARRAY_SIZE(si_driver_query_list) - 7;
1820 }
1821
1822 return ARRAY_SIZE(si_driver_query_list) - 21;
1823 }
1824
1825 static int si_get_driver_query_info(struct pipe_screen *screen,
1826 unsigned index,
1827 struct pipe_driver_query_info *info)
1828 {
1829 struct si_screen *sscreen = (struct si_screen*)screen;
1830 unsigned num_queries = si_get_num_queries(sscreen);
1831
1832 if (!info) {
1833 unsigned num_perfcounters =
1834 si_get_perfcounter_info(sscreen, 0, NULL);
1835
1836 return num_queries + num_perfcounters;
1837 }
1838
1839 if (index >= num_queries)
1840 return si_get_perfcounter_info(sscreen, index - num_queries, info);
1841
1842 *info = si_driver_query_list[index];
1843
1844 switch (info->query_type) {
1845 case SI_QUERY_REQUESTED_VRAM:
1846 case SI_QUERY_VRAM_USAGE:
1847 case SI_QUERY_MAPPED_VRAM:
1848 info->max_value.u64 = sscreen->info.vram_size;
1849 break;
1850 case SI_QUERY_REQUESTED_GTT:
1851 case SI_QUERY_GTT_USAGE:
1852 case SI_QUERY_MAPPED_GTT:
1853 info->max_value.u64 = sscreen->info.gart_size;
1854 break;
1855 case SI_QUERY_GPU_TEMPERATURE:
1856 info->max_value.u64 = 125;
1857 break;
1858 case SI_QUERY_VRAM_VIS_USAGE:
1859 info->max_value.u64 = sscreen->info.vram_vis_size;
1860 break;
1861 }
1862
1863 if (info->group_id != ~(unsigned)0 && sscreen->perfcounters)
1864 info->group_id += sscreen->perfcounters->num_groups;
1865
1866 return 1;
1867 }
1868
1869 /* Note: Unfortunately, GPUPerfStudio hardcodes the order of hardware
1870 * performance counter groups, so be careful when changing this and related
1871 * functions.
1872 */
1873 static int si_get_driver_query_group_info(struct pipe_screen *screen,
1874 unsigned index,
1875 struct pipe_driver_query_group_info *info)
1876 {
1877 struct si_screen *sscreen = (struct si_screen *)screen;
1878 unsigned num_pc_groups = 0;
1879
1880 if (sscreen->perfcounters)
1881 num_pc_groups = sscreen->perfcounters->num_groups;
1882
1883 if (!info)
1884 return num_pc_groups + SI_NUM_SW_QUERY_GROUPS;
1885
1886 if (index < num_pc_groups)
1887 return si_get_perfcounter_group_info(sscreen, index, info);
1888
1889 index -= num_pc_groups;
1890 if (index >= SI_NUM_SW_QUERY_GROUPS)
1891 return 0;
1892
1893 info->name = "GPIN";
1894 info->max_active_queries = 5;
1895 info->num_queries = 5;
1896 return 1;
1897 }
1898
1899 void si_init_query_functions(struct si_context *sctx)
1900 {
1901 sctx->b.create_query = si_create_query;
1902 sctx->b.create_batch_query = si_create_batch_query;
1903 sctx->b.destroy_query = si_destroy_query;
1904 sctx->b.begin_query = si_begin_query;
1905 sctx->b.end_query = si_end_query;
1906 sctx->b.get_query_result = si_get_query_result;
1907 sctx->b.get_query_result_resource = si_get_query_result_resource;
1908
1909 if (sctx->has_graphics) {
1910 sctx->atoms.s.render_cond.emit = si_emit_query_predication;
1911 sctx->b.render_condition = si_render_condition;
1912 }
1913
1914 LIST_INITHEAD(&sctx->active_queries);
1915 }
1916
1917 void si_init_screen_query_functions(struct si_screen *sscreen)
1918 {
1919 sscreen->b.get_driver_query_info = si_get_driver_query_info;
1920 sscreen->b.get_driver_query_group_info = si_get_driver_query_group_info;
1921 }