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e29ce7150bd1d6394f6f810aa0caceac71a04591
[mesa.git] / src / gallium / drivers / radeonsi / si_query.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2014 Marek Olšák <marek.olsak@amd.com>
4 * Copyright 2018 Advanced Micro Devices, Inc.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * on the rights to use, copy, modify, merge, publish, distribute, sub
11 * license, and/or sell copies of the Software, and to permit persons to whom
12 * the Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27 #include "si_pipe.h"
28 #include "si_query.h"
29 #include "util/u_memory.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/os_time.h"
32 #include "util/u_suballoc.h"
33 #include "tgsi/tgsi_text.h"
34 #include "amd/common/sid.h"
35
36 #define SI_MAX_STREAMS 4
37
38 struct si_hw_query_params {
39 unsigned start_offset;
40 unsigned end_offset;
41 unsigned fence_offset;
42 unsigned pair_stride;
43 unsigned pair_count;
44 };
45
46 /* Queries without buffer handling or suspend/resume. */
47 struct si_query_sw {
48 struct si_query b;
49
50 uint64_t begin_result;
51 uint64_t end_result;
52
53 uint64_t begin_time;
54 uint64_t end_time;
55
56 /* Fence for GPU_FINISHED. */
57 struct pipe_fence_handle *fence;
58 };
59
60 static void si_query_sw_destroy(struct si_screen *sscreen,
61 struct si_query *rquery)
62 {
63 struct si_query_sw *query = (struct si_query_sw *)rquery;
64
65 sscreen->b.fence_reference(&sscreen->b, &query->fence, NULL);
66 FREE(query);
67 }
68
69 static enum radeon_value_id winsys_id_from_type(unsigned type)
70 {
71 switch (type) {
72 case SI_QUERY_REQUESTED_VRAM: return RADEON_REQUESTED_VRAM_MEMORY;
73 case SI_QUERY_REQUESTED_GTT: return RADEON_REQUESTED_GTT_MEMORY;
74 case SI_QUERY_MAPPED_VRAM: return RADEON_MAPPED_VRAM;
75 case SI_QUERY_MAPPED_GTT: return RADEON_MAPPED_GTT;
76 case SI_QUERY_BUFFER_WAIT_TIME: return RADEON_BUFFER_WAIT_TIME_NS;
77 case SI_QUERY_NUM_MAPPED_BUFFERS: return RADEON_NUM_MAPPED_BUFFERS;
78 case SI_QUERY_NUM_GFX_IBS: return RADEON_NUM_GFX_IBS;
79 case SI_QUERY_NUM_SDMA_IBS: return RADEON_NUM_SDMA_IBS;
80 case SI_QUERY_GFX_BO_LIST_SIZE: return RADEON_GFX_BO_LIST_COUNTER;
81 case SI_QUERY_GFX_IB_SIZE: return RADEON_GFX_IB_SIZE_COUNTER;
82 case SI_QUERY_NUM_BYTES_MOVED: return RADEON_NUM_BYTES_MOVED;
83 case SI_QUERY_NUM_EVICTIONS: return RADEON_NUM_EVICTIONS;
84 case SI_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: return RADEON_NUM_VRAM_CPU_PAGE_FAULTS;
85 case SI_QUERY_VRAM_USAGE: return RADEON_VRAM_USAGE;
86 case SI_QUERY_VRAM_VIS_USAGE: return RADEON_VRAM_VIS_USAGE;
87 case SI_QUERY_GTT_USAGE: return RADEON_GTT_USAGE;
88 case SI_QUERY_GPU_TEMPERATURE: return RADEON_GPU_TEMPERATURE;
89 case SI_QUERY_CURRENT_GPU_SCLK: return RADEON_CURRENT_SCLK;
90 case SI_QUERY_CURRENT_GPU_MCLK: return RADEON_CURRENT_MCLK;
91 case SI_QUERY_CS_THREAD_BUSY: return RADEON_CS_THREAD_TIME;
92 default: unreachable("query type does not correspond to winsys id");
93 }
94 }
95
96 static bool si_query_sw_begin(struct si_context *sctx,
97 struct si_query *rquery)
98 {
99 struct si_query_sw *query = (struct si_query_sw *)rquery;
100 enum radeon_value_id ws_id;
101
102 switch(query->b.type) {
103 case PIPE_QUERY_TIMESTAMP_DISJOINT:
104 case PIPE_QUERY_GPU_FINISHED:
105 break;
106 case SI_QUERY_DRAW_CALLS:
107 query->begin_result = sctx->num_draw_calls;
108 break;
109 case SI_QUERY_DECOMPRESS_CALLS:
110 query->begin_result = sctx->num_decompress_calls;
111 break;
112 case SI_QUERY_MRT_DRAW_CALLS:
113 query->begin_result = sctx->num_mrt_draw_calls;
114 break;
115 case SI_QUERY_PRIM_RESTART_CALLS:
116 query->begin_result = sctx->num_prim_restart_calls;
117 break;
118 case SI_QUERY_SPILL_DRAW_CALLS:
119 query->begin_result = sctx->num_spill_draw_calls;
120 break;
121 case SI_QUERY_COMPUTE_CALLS:
122 query->begin_result = sctx->num_compute_calls;
123 break;
124 case SI_QUERY_SPILL_COMPUTE_CALLS:
125 query->begin_result = sctx->num_spill_compute_calls;
126 break;
127 case SI_QUERY_DMA_CALLS:
128 query->begin_result = sctx->num_dma_calls;
129 break;
130 case SI_QUERY_CP_DMA_CALLS:
131 query->begin_result = sctx->num_cp_dma_calls;
132 break;
133 case SI_QUERY_NUM_VS_FLUSHES:
134 query->begin_result = sctx->num_vs_flushes;
135 break;
136 case SI_QUERY_NUM_PS_FLUSHES:
137 query->begin_result = sctx->num_ps_flushes;
138 break;
139 case SI_QUERY_NUM_CS_FLUSHES:
140 query->begin_result = sctx->num_cs_flushes;
141 break;
142 case SI_QUERY_NUM_CB_CACHE_FLUSHES:
143 query->begin_result = sctx->num_cb_cache_flushes;
144 break;
145 case SI_QUERY_NUM_DB_CACHE_FLUSHES:
146 query->begin_result = sctx->num_db_cache_flushes;
147 break;
148 case SI_QUERY_NUM_L2_INVALIDATES:
149 query->begin_result = sctx->num_L2_invalidates;
150 break;
151 case SI_QUERY_NUM_L2_WRITEBACKS:
152 query->begin_result = sctx->num_L2_writebacks;
153 break;
154 case SI_QUERY_NUM_RESIDENT_HANDLES:
155 query->begin_result = sctx->num_resident_handles;
156 break;
157 case SI_QUERY_TC_OFFLOADED_SLOTS:
158 query->begin_result = sctx->tc ? sctx->tc->num_offloaded_slots : 0;
159 break;
160 case SI_QUERY_TC_DIRECT_SLOTS:
161 query->begin_result = sctx->tc ? sctx->tc->num_direct_slots : 0;
162 break;
163 case SI_QUERY_TC_NUM_SYNCS:
164 query->begin_result = sctx->tc ? sctx->tc->num_syncs : 0;
165 break;
166 case SI_QUERY_REQUESTED_VRAM:
167 case SI_QUERY_REQUESTED_GTT:
168 case SI_QUERY_MAPPED_VRAM:
169 case SI_QUERY_MAPPED_GTT:
170 case SI_QUERY_VRAM_USAGE:
171 case SI_QUERY_VRAM_VIS_USAGE:
172 case SI_QUERY_GTT_USAGE:
173 case SI_QUERY_GPU_TEMPERATURE:
174 case SI_QUERY_CURRENT_GPU_SCLK:
175 case SI_QUERY_CURRENT_GPU_MCLK:
176 case SI_QUERY_BACK_BUFFER_PS_DRAW_RATIO:
177 case SI_QUERY_NUM_MAPPED_BUFFERS:
178 query->begin_result = 0;
179 break;
180 case SI_QUERY_BUFFER_WAIT_TIME:
181 case SI_QUERY_GFX_IB_SIZE:
182 case SI_QUERY_NUM_GFX_IBS:
183 case SI_QUERY_NUM_SDMA_IBS:
184 case SI_QUERY_NUM_BYTES_MOVED:
185 case SI_QUERY_NUM_EVICTIONS:
186 case SI_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: {
187 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
188 query->begin_result = sctx->ws->query_value(sctx->ws, ws_id);
189 break;
190 }
191 case SI_QUERY_GFX_BO_LIST_SIZE:
192 ws_id = winsys_id_from_type(query->b.type);
193 query->begin_result = sctx->ws->query_value(sctx->ws, ws_id);
194 query->begin_time = sctx->ws->query_value(sctx->ws,
195 RADEON_NUM_GFX_IBS);
196 break;
197 case SI_QUERY_CS_THREAD_BUSY:
198 ws_id = winsys_id_from_type(query->b.type);
199 query->begin_result = sctx->ws->query_value(sctx->ws, ws_id);
200 query->begin_time = os_time_get_nano();
201 break;
202 case SI_QUERY_GALLIUM_THREAD_BUSY:
203 query->begin_result =
204 sctx->tc ? util_queue_get_thread_time_nano(&sctx->tc->queue, 0) : 0;
205 query->begin_time = os_time_get_nano();
206 break;
207 case SI_QUERY_GPU_LOAD:
208 case SI_QUERY_GPU_SHADERS_BUSY:
209 case SI_QUERY_GPU_TA_BUSY:
210 case SI_QUERY_GPU_GDS_BUSY:
211 case SI_QUERY_GPU_VGT_BUSY:
212 case SI_QUERY_GPU_IA_BUSY:
213 case SI_QUERY_GPU_SX_BUSY:
214 case SI_QUERY_GPU_WD_BUSY:
215 case SI_QUERY_GPU_BCI_BUSY:
216 case SI_QUERY_GPU_SC_BUSY:
217 case SI_QUERY_GPU_PA_BUSY:
218 case SI_QUERY_GPU_DB_BUSY:
219 case SI_QUERY_GPU_CP_BUSY:
220 case SI_QUERY_GPU_CB_BUSY:
221 case SI_QUERY_GPU_SDMA_BUSY:
222 case SI_QUERY_GPU_PFP_BUSY:
223 case SI_QUERY_GPU_MEQ_BUSY:
224 case SI_QUERY_GPU_ME_BUSY:
225 case SI_QUERY_GPU_SURF_SYNC_BUSY:
226 case SI_QUERY_GPU_CP_DMA_BUSY:
227 case SI_QUERY_GPU_SCRATCH_RAM_BUSY:
228 query->begin_result = si_begin_counter(sctx->screen,
229 query->b.type);
230 break;
231 case SI_QUERY_NUM_COMPILATIONS:
232 query->begin_result = p_atomic_read(&sctx->screen->num_compilations);
233 break;
234 case SI_QUERY_NUM_SHADERS_CREATED:
235 query->begin_result = p_atomic_read(&sctx->screen->num_shaders_created);
236 break;
237 case SI_QUERY_NUM_SHADER_CACHE_HITS:
238 query->begin_result =
239 p_atomic_read(&sctx->screen->num_shader_cache_hits);
240 break;
241 case SI_QUERY_GPIN_ASIC_ID:
242 case SI_QUERY_GPIN_NUM_SIMD:
243 case SI_QUERY_GPIN_NUM_RB:
244 case SI_QUERY_GPIN_NUM_SPI:
245 case SI_QUERY_GPIN_NUM_SE:
246 break;
247 default:
248 unreachable("si_query_sw_begin: bad query type");
249 }
250
251 return true;
252 }
253
254 static bool si_query_sw_end(struct si_context *sctx,
255 struct si_query *rquery)
256 {
257 struct si_query_sw *query = (struct si_query_sw *)rquery;
258 enum radeon_value_id ws_id;
259
260 switch(query->b.type) {
261 case PIPE_QUERY_TIMESTAMP_DISJOINT:
262 break;
263 case PIPE_QUERY_GPU_FINISHED:
264 sctx->b.flush(&sctx->b, &query->fence, PIPE_FLUSH_DEFERRED);
265 break;
266 case SI_QUERY_DRAW_CALLS:
267 query->end_result = sctx->num_draw_calls;
268 break;
269 case SI_QUERY_DECOMPRESS_CALLS:
270 query->end_result = sctx->num_decompress_calls;
271 break;
272 case SI_QUERY_MRT_DRAW_CALLS:
273 query->end_result = sctx->num_mrt_draw_calls;
274 break;
275 case SI_QUERY_PRIM_RESTART_CALLS:
276 query->end_result = sctx->num_prim_restart_calls;
277 break;
278 case SI_QUERY_SPILL_DRAW_CALLS:
279 query->end_result = sctx->num_spill_draw_calls;
280 break;
281 case SI_QUERY_COMPUTE_CALLS:
282 query->end_result = sctx->num_compute_calls;
283 break;
284 case SI_QUERY_SPILL_COMPUTE_CALLS:
285 query->end_result = sctx->num_spill_compute_calls;
286 break;
287 case SI_QUERY_DMA_CALLS:
288 query->end_result = sctx->num_dma_calls;
289 break;
290 case SI_QUERY_CP_DMA_CALLS:
291 query->end_result = sctx->num_cp_dma_calls;
292 break;
293 case SI_QUERY_NUM_VS_FLUSHES:
294 query->end_result = sctx->num_vs_flushes;
295 break;
296 case SI_QUERY_NUM_PS_FLUSHES:
297 query->end_result = sctx->num_ps_flushes;
298 break;
299 case SI_QUERY_NUM_CS_FLUSHES:
300 query->end_result = sctx->num_cs_flushes;
301 break;
302 case SI_QUERY_NUM_CB_CACHE_FLUSHES:
303 query->end_result = sctx->num_cb_cache_flushes;
304 break;
305 case SI_QUERY_NUM_DB_CACHE_FLUSHES:
306 query->end_result = sctx->num_db_cache_flushes;
307 break;
308 case SI_QUERY_NUM_L2_INVALIDATES:
309 query->end_result = sctx->num_L2_invalidates;
310 break;
311 case SI_QUERY_NUM_L2_WRITEBACKS:
312 query->end_result = sctx->num_L2_writebacks;
313 break;
314 case SI_QUERY_NUM_RESIDENT_HANDLES:
315 query->end_result = sctx->num_resident_handles;
316 break;
317 case SI_QUERY_TC_OFFLOADED_SLOTS:
318 query->end_result = sctx->tc ? sctx->tc->num_offloaded_slots : 0;
319 break;
320 case SI_QUERY_TC_DIRECT_SLOTS:
321 query->end_result = sctx->tc ? sctx->tc->num_direct_slots : 0;
322 break;
323 case SI_QUERY_TC_NUM_SYNCS:
324 query->end_result = sctx->tc ? sctx->tc->num_syncs : 0;
325 break;
326 case SI_QUERY_REQUESTED_VRAM:
327 case SI_QUERY_REQUESTED_GTT:
328 case SI_QUERY_MAPPED_VRAM:
329 case SI_QUERY_MAPPED_GTT:
330 case SI_QUERY_VRAM_USAGE:
331 case SI_QUERY_VRAM_VIS_USAGE:
332 case SI_QUERY_GTT_USAGE:
333 case SI_QUERY_GPU_TEMPERATURE:
334 case SI_QUERY_CURRENT_GPU_SCLK:
335 case SI_QUERY_CURRENT_GPU_MCLK:
336 case SI_QUERY_BUFFER_WAIT_TIME:
337 case SI_QUERY_GFX_IB_SIZE:
338 case SI_QUERY_NUM_MAPPED_BUFFERS:
339 case SI_QUERY_NUM_GFX_IBS:
340 case SI_QUERY_NUM_SDMA_IBS:
341 case SI_QUERY_NUM_BYTES_MOVED:
342 case SI_QUERY_NUM_EVICTIONS:
343 case SI_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: {
344 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
345 query->end_result = sctx->ws->query_value(sctx->ws, ws_id);
346 break;
347 }
348 case SI_QUERY_GFX_BO_LIST_SIZE:
349 ws_id = winsys_id_from_type(query->b.type);
350 query->end_result = sctx->ws->query_value(sctx->ws, ws_id);
351 query->end_time = sctx->ws->query_value(sctx->ws,
352 RADEON_NUM_GFX_IBS);
353 break;
354 case SI_QUERY_CS_THREAD_BUSY:
355 ws_id = winsys_id_from_type(query->b.type);
356 query->end_result = sctx->ws->query_value(sctx->ws, ws_id);
357 query->end_time = os_time_get_nano();
358 break;
359 case SI_QUERY_GALLIUM_THREAD_BUSY:
360 query->end_result =
361 sctx->tc ? util_queue_get_thread_time_nano(&sctx->tc->queue, 0) : 0;
362 query->end_time = os_time_get_nano();
363 break;
364 case SI_QUERY_GPU_LOAD:
365 case SI_QUERY_GPU_SHADERS_BUSY:
366 case SI_QUERY_GPU_TA_BUSY:
367 case SI_QUERY_GPU_GDS_BUSY:
368 case SI_QUERY_GPU_VGT_BUSY:
369 case SI_QUERY_GPU_IA_BUSY:
370 case SI_QUERY_GPU_SX_BUSY:
371 case SI_QUERY_GPU_WD_BUSY:
372 case SI_QUERY_GPU_BCI_BUSY:
373 case SI_QUERY_GPU_SC_BUSY:
374 case SI_QUERY_GPU_PA_BUSY:
375 case SI_QUERY_GPU_DB_BUSY:
376 case SI_QUERY_GPU_CP_BUSY:
377 case SI_QUERY_GPU_CB_BUSY:
378 case SI_QUERY_GPU_SDMA_BUSY:
379 case SI_QUERY_GPU_PFP_BUSY:
380 case SI_QUERY_GPU_MEQ_BUSY:
381 case SI_QUERY_GPU_ME_BUSY:
382 case SI_QUERY_GPU_SURF_SYNC_BUSY:
383 case SI_QUERY_GPU_CP_DMA_BUSY:
384 case SI_QUERY_GPU_SCRATCH_RAM_BUSY:
385 query->end_result = si_end_counter(sctx->screen,
386 query->b.type,
387 query->begin_result);
388 query->begin_result = 0;
389 break;
390 case SI_QUERY_NUM_COMPILATIONS:
391 query->end_result = p_atomic_read(&sctx->screen->num_compilations);
392 break;
393 case SI_QUERY_NUM_SHADERS_CREATED:
394 query->end_result = p_atomic_read(&sctx->screen->num_shaders_created);
395 break;
396 case SI_QUERY_BACK_BUFFER_PS_DRAW_RATIO:
397 query->end_result = sctx->last_tex_ps_draw_ratio;
398 break;
399 case SI_QUERY_NUM_SHADER_CACHE_HITS:
400 query->end_result =
401 p_atomic_read(&sctx->screen->num_shader_cache_hits);
402 break;
403 case SI_QUERY_GPIN_ASIC_ID:
404 case SI_QUERY_GPIN_NUM_SIMD:
405 case SI_QUERY_GPIN_NUM_RB:
406 case SI_QUERY_GPIN_NUM_SPI:
407 case SI_QUERY_GPIN_NUM_SE:
408 break;
409 default:
410 unreachable("si_query_sw_end: bad query type");
411 }
412
413 return true;
414 }
415
416 static bool si_query_sw_get_result(struct si_context *sctx,
417 struct si_query *rquery,
418 bool wait,
419 union pipe_query_result *result)
420 {
421 struct si_query_sw *query = (struct si_query_sw *)rquery;
422
423 switch (query->b.type) {
424 case PIPE_QUERY_TIMESTAMP_DISJOINT:
425 /* Convert from cycles per millisecond to cycles per second (Hz). */
426 result->timestamp_disjoint.frequency =
427 (uint64_t)sctx->screen->info.clock_crystal_freq * 1000;
428 result->timestamp_disjoint.disjoint = false;
429 return true;
430 case PIPE_QUERY_GPU_FINISHED: {
431 struct pipe_screen *screen = sctx->b.screen;
432 struct pipe_context *ctx = rquery->b.flushed ? NULL : &sctx->b;
433
434 result->b = screen->fence_finish(screen, ctx, query->fence,
435 wait ? PIPE_TIMEOUT_INFINITE : 0);
436 return result->b;
437 }
438
439 case SI_QUERY_GFX_BO_LIST_SIZE:
440 result->u64 = (query->end_result - query->begin_result) /
441 (query->end_time - query->begin_time);
442 return true;
443 case SI_QUERY_CS_THREAD_BUSY:
444 case SI_QUERY_GALLIUM_THREAD_BUSY:
445 result->u64 = (query->end_result - query->begin_result) * 100 /
446 (query->end_time - query->begin_time);
447 return true;
448 case SI_QUERY_GPIN_ASIC_ID:
449 result->u32 = 0;
450 return true;
451 case SI_QUERY_GPIN_NUM_SIMD:
452 result->u32 = sctx->screen->info.num_good_compute_units;
453 return true;
454 case SI_QUERY_GPIN_NUM_RB:
455 result->u32 = sctx->screen->info.num_render_backends;
456 return true;
457 case SI_QUERY_GPIN_NUM_SPI:
458 result->u32 = 1; /* all supported chips have one SPI per SE */
459 return true;
460 case SI_QUERY_GPIN_NUM_SE:
461 result->u32 = sctx->screen->info.max_se;
462 return true;
463 }
464
465 result->u64 = query->end_result - query->begin_result;
466
467 switch (query->b.type) {
468 case SI_QUERY_BUFFER_WAIT_TIME:
469 case SI_QUERY_GPU_TEMPERATURE:
470 result->u64 /= 1000;
471 break;
472 case SI_QUERY_CURRENT_GPU_SCLK:
473 case SI_QUERY_CURRENT_GPU_MCLK:
474 result->u64 *= 1000000;
475 break;
476 }
477
478 return true;
479 }
480
481
482 static struct si_query_ops sw_query_ops = {
483 .destroy = si_query_sw_destroy,
484 .begin = si_query_sw_begin,
485 .end = si_query_sw_end,
486 .get_result = si_query_sw_get_result,
487 .get_result_resource = NULL
488 };
489
490 static struct pipe_query *si_query_sw_create(unsigned query_type)
491 {
492 struct si_query_sw *query;
493
494 query = CALLOC_STRUCT(si_query_sw);
495 if (!query)
496 return NULL;
497
498 query->b.type = query_type;
499 query->b.ops = &sw_query_ops;
500
501 return (struct pipe_query *)query;
502 }
503
504 void si_query_hw_destroy(struct si_screen *sscreen,
505 struct si_query *rquery)
506 {
507 struct si_query_hw *query = (struct si_query_hw *)rquery;
508 struct si_query_buffer *prev = query->buffer.previous;
509
510 /* Release all query buffers. */
511 while (prev) {
512 struct si_query_buffer *qbuf = prev;
513 prev = prev->previous;
514 r600_resource_reference(&qbuf->buf, NULL);
515 FREE(qbuf);
516 }
517
518 r600_resource_reference(&query->buffer.buf, NULL);
519 r600_resource_reference(&query->workaround_buf, NULL);
520 FREE(rquery);
521 }
522
523 static struct r600_resource *si_new_query_buffer(struct si_screen *sscreen,
524 struct si_query_hw *query)
525 {
526 unsigned buf_size = MAX2(query->result_size,
527 sscreen->info.min_alloc_size);
528
529 /* Queries are normally read by the CPU after
530 * being written by the gpu, hence staging is probably a good
531 * usage pattern.
532 */
533 struct r600_resource *buf = r600_resource(
534 pipe_buffer_create(&sscreen->b, 0,
535 PIPE_USAGE_STAGING, buf_size));
536 if (!buf)
537 return NULL;
538
539 if (!query->ops->prepare_buffer(sscreen, query, buf)) {
540 r600_resource_reference(&buf, NULL);
541 return NULL;
542 }
543
544 return buf;
545 }
546
547 static bool si_query_hw_prepare_buffer(struct si_screen *sscreen,
548 struct si_query_hw *query,
549 struct r600_resource *buffer)
550 {
551 /* Callers ensure that the buffer is currently unused by the GPU. */
552 uint32_t *results = sscreen->ws->buffer_map(buffer->buf, NULL,
553 PIPE_TRANSFER_WRITE |
554 PIPE_TRANSFER_UNSYNCHRONIZED);
555 if (!results)
556 return false;
557
558 memset(results, 0, buffer->b.b.width0);
559
560 if (query->b.type == PIPE_QUERY_OCCLUSION_COUNTER ||
561 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE ||
562 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
563 unsigned max_rbs = sscreen->info.num_render_backends;
564 unsigned enabled_rb_mask = sscreen->info.enabled_rb_mask;
565 unsigned num_results;
566 unsigned i, j;
567
568 /* Set top bits for unused backends. */
569 num_results = buffer->b.b.width0 / query->result_size;
570 for (j = 0; j < num_results; j++) {
571 for (i = 0; i < max_rbs; i++) {
572 if (!(enabled_rb_mask & (1<<i))) {
573 results[(i * 4)+1] = 0x80000000;
574 results[(i * 4)+3] = 0x80000000;
575 }
576 }
577 results += 4 * max_rbs;
578 }
579 }
580
581 return true;
582 }
583
584 static void si_query_hw_get_result_resource(struct si_context *sctx,
585 struct si_query *rquery,
586 bool wait,
587 enum pipe_query_value_type result_type,
588 int index,
589 struct pipe_resource *resource,
590 unsigned offset);
591
592 static struct si_query_ops query_hw_ops = {
593 .destroy = si_query_hw_destroy,
594 .begin = si_query_hw_begin,
595 .end = si_query_hw_end,
596 .get_result = si_query_hw_get_result,
597 .get_result_resource = si_query_hw_get_result_resource,
598 };
599
600 static void si_query_hw_do_emit_start(struct si_context *sctx,
601 struct si_query_hw *query,
602 struct r600_resource *buffer,
603 uint64_t va);
604 static void si_query_hw_do_emit_stop(struct si_context *sctx,
605 struct si_query_hw *query,
606 struct r600_resource *buffer,
607 uint64_t va);
608 static void si_query_hw_add_result(struct si_screen *sscreen,
609 struct si_query_hw *, void *buffer,
610 union pipe_query_result *result);
611 static void si_query_hw_clear_result(struct si_query_hw *,
612 union pipe_query_result *);
613
614 static struct si_query_hw_ops query_hw_default_hw_ops = {
615 .prepare_buffer = si_query_hw_prepare_buffer,
616 .emit_start = si_query_hw_do_emit_start,
617 .emit_stop = si_query_hw_do_emit_stop,
618 .clear_result = si_query_hw_clear_result,
619 .add_result = si_query_hw_add_result,
620 };
621
622 bool si_query_hw_init(struct si_screen *sscreen,
623 struct si_query_hw *query)
624 {
625 query->buffer.buf = si_new_query_buffer(sscreen, query);
626 if (!query->buffer.buf)
627 return false;
628
629 return true;
630 }
631
632 static struct pipe_query *si_query_hw_create(struct si_screen *sscreen,
633 unsigned query_type,
634 unsigned index)
635 {
636 struct si_query_hw *query = CALLOC_STRUCT(si_query_hw);
637 if (!query)
638 return NULL;
639
640 query->b.type = query_type;
641 query->b.ops = &query_hw_ops;
642 query->ops = &query_hw_default_hw_ops;
643
644 switch (query_type) {
645 case PIPE_QUERY_OCCLUSION_COUNTER:
646 case PIPE_QUERY_OCCLUSION_PREDICATE:
647 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
648 query->result_size = 16 * sscreen->info.num_render_backends;
649 query->result_size += 16; /* for the fence + alignment */
650 query->num_cs_dw_end = 6 + si_gfx_write_fence_dwords(sscreen);
651 break;
652 case PIPE_QUERY_TIME_ELAPSED:
653 query->result_size = 24;
654 query->num_cs_dw_end = 8 + si_gfx_write_fence_dwords(sscreen);
655 break;
656 case PIPE_QUERY_TIMESTAMP:
657 query->result_size = 16;
658 query->num_cs_dw_end = 8 + si_gfx_write_fence_dwords(sscreen);
659 query->flags = SI_QUERY_HW_FLAG_NO_START;
660 break;
661 case PIPE_QUERY_PRIMITIVES_EMITTED:
662 case PIPE_QUERY_PRIMITIVES_GENERATED:
663 case PIPE_QUERY_SO_STATISTICS:
664 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
665 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
666 query->result_size = 32;
667 query->num_cs_dw_end = 6;
668 query->stream = index;
669 break;
670 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
671 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
672 query->result_size = 32 * SI_MAX_STREAMS;
673 query->num_cs_dw_end = 6 * SI_MAX_STREAMS;
674 break;
675 case PIPE_QUERY_PIPELINE_STATISTICS:
676 /* 11 values on GCN. */
677 query->result_size = 11 * 16;
678 query->result_size += 8; /* for the fence + alignment */
679 query->num_cs_dw_end = 6 + si_gfx_write_fence_dwords(sscreen);
680 break;
681 default:
682 assert(0);
683 FREE(query);
684 return NULL;
685 }
686
687 if (!si_query_hw_init(sscreen, query)) {
688 FREE(query);
689 return NULL;
690 }
691
692 return (struct pipe_query *)query;
693 }
694
695 static void si_update_occlusion_query_state(struct si_context *sctx,
696 unsigned type, int diff)
697 {
698 if (type == PIPE_QUERY_OCCLUSION_COUNTER ||
699 type == PIPE_QUERY_OCCLUSION_PREDICATE ||
700 type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
701 bool old_enable = sctx->num_occlusion_queries != 0;
702 bool old_perfect_enable =
703 sctx->num_perfect_occlusion_queries != 0;
704 bool enable, perfect_enable;
705
706 sctx->num_occlusion_queries += diff;
707 assert(sctx->num_occlusion_queries >= 0);
708
709 if (type != PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
710 sctx->num_perfect_occlusion_queries += diff;
711 assert(sctx->num_perfect_occlusion_queries >= 0);
712 }
713
714 enable = sctx->num_occlusion_queries != 0;
715 perfect_enable = sctx->num_perfect_occlusion_queries != 0;
716
717 if (enable != old_enable || perfect_enable != old_perfect_enable) {
718 si_set_occlusion_query_state(sctx, old_perfect_enable);
719 }
720 }
721 }
722
723 static unsigned event_type_for_stream(unsigned stream)
724 {
725 switch (stream) {
726 default:
727 case 0: return V_028A90_SAMPLE_STREAMOUTSTATS;
728 case 1: return V_028A90_SAMPLE_STREAMOUTSTATS1;
729 case 2: return V_028A90_SAMPLE_STREAMOUTSTATS2;
730 case 3: return V_028A90_SAMPLE_STREAMOUTSTATS3;
731 }
732 }
733
734 static void emit_sample_streamout(struct radeon_cmdbuf *cs, uint64_t va,
735 unsigned stream)
736 {
737 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
738 radeon_emit(cs, EVENT_TYPE(event_type_for_stream(stream)) | EVENT_INDEX(3));
739 radeon_emit(cs, va);
740 radeon_emit(cs, va >> 32);
741 }
742
743 static void si_query_hw_do_emit_start(struct si_context *sctx,
744 struct si_query_hw *query,
745 struct r600_resource *buffer,
746 uint64_t va)
747 {
748 struct radeon_cmdbuf *cs = sctx->gfx_cs;
749
750 switch (query->b.type) {
751 case PIPE_QUERY_OCCLUSION_COUNTER:
752 case PIPE_QUERY_OCCLUSION_PREDICATE:
753 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
754 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
755 radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
756 radeon_emit(cs, va);
757 radeon_emit(cs, va >> 32);
758 break;
759 case PIPE_QUERY_PRIMITIVES_EMITTED:
760 case PIPE_QUERY_PRIMITIVES_GENERATED:
761 case PIPE_QUERY_SO_STATISTICS:
762 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
763 emit_sample_streamout(cs, va, query->stream);
764 break;
765 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
766 for (unsigned stream = 0; stream < SI_MAX_STREAMS; ++stream)
767 emit_sample_streamout(cs, va + 32 * stream, stream);
768 break;
769 case PIPE_QUERY_TIME_ELAPSED:
770 /* Write the timestamp from the CP not waiting for
771 * outstanding draws (top-of-pipe).
772 */
773 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
774 radeon_emit(cs, COPY_DATA_COUNT_SEL |
775 COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
776 COPY_DATA_DST_SEL(COPY_DATA_MEM_ASYNC));
777 radeon_emit(cs, 0);
778 radeon_emit(cs, 0);
779 radeon_emit(cs, va);
780 radeon_emit(cs, va >> 32);
781 break;
782 case PIPE_QUERY_PIPELINE_STATISTICS:
783 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
784 radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
785 radeon_emit(cs, va);
786 radeon_emit(cs, va >> 32);
787 break;
788 default:
789 assert(0);
790 }
791 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, query->buffer.buf, RADEON_USAGE_WRITE,
792 RADEON_PRIO_QUERY);
793 }
794
795 static void si_query_hw_emit_start(struct si_context *sctx,
796 struct si_query_hw *query)
797 {
798 uint64_t va;
799
800 if (!query->buffer.buf)
801 return; // previous buffer allocation failure
802
803 si_update_occlusion_query_state(sctx, query->b.type, 1);
804 si_update_prims_generated_query_state(sctx, query->b.type, 1);
805
806 si_need_gfx_cs_space(sctx);
807
808 /* Get a new query buffer if needed. */
809 if (query->buffer.results_end + query->result_size > query->buffer.buf->b.b.width0) {
810 struct si_query_buffer *qbuf = MALLOC_STRUCT(si_query_buffer);
811 *qbuf = query->buffer;
812 query->buffer.results_end = 0;
813 query->buffer.previous = qbuf;
814 query->buffer.buf = si_new_query_buffer(sctx->screen, query);
815 if (!query->buffer.buf)
816 return;
817 }
818
819 /* emit begin query */
820 va = query->buffer.buf->gpu_address + query->buffer.results_end;
821
822 query->ops->emit_start(sctx, query, query->buffer.buf, va);
823
824 sctx->num_cs_dw_queries_suspend += query->num_cs_dw_end;
825 }
826
827 static void si_query_hw_do_emit_stop(struct si_context *sctx,
828 struct si_query_hw *query,
829 struct r600_resource *buffer,
830 uint64_t va)
831 {
832 struct radeon_cmdbuf *cs = sctx->gfx_cs;
833 uint64_t fence_va = 0;
834
835 switch (query->b.type) {
836 case PIPE_QUERY_OCCLUSION_COUNTER:
837 case PIPE_QUERY_OCCLUSION_PREDICATE:
838 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
839 va += 8;
840 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
841 radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
842 radeon_emit(cs, va);
843 radeon_emit(cs, va >> 32);
844
845 fence_va = va + sctx->screen->info.num_render_backends * 16 - 8;
846 break;
847 case PIPE_QUERY_PRIMITIVES_EMITTED:
848 case PIPE_QUERY_PRIMITIVES_GENERATED:
849 case PIPE_QUERY_SO_STATISTICS:
850 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
851 va += 16;
852 emit_sample_streamout(cs, va, query->stream);
853 break;
854 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
855 va += 16;
856 for (unsigned stream = 0; stream < SI_MAX_STREAMS; ++stream)
857 emit_sample_streamout(cs, va + 32 * stream, stream);
858 break;
859 case PIPE_QUERY_TIME_ELAPSED:
860 va += 8;
861 /* fall through */
862 case PIPE_QUERY_TIMESTAMP:
863 si_gfx_write_event_eop(sctx, V_028A90_BOTTOM_OF_PIPE_TS,
864 0, EOP_DATA_SEL_TIMESTAMP, NULL, va,
865 0, query->b.type);
866 fence_va = va + 8;
867 break;
868 case PIPE_QUERY_PIPELINE_STATISTICS: {
869 unsigned sample_size = (query->result_size - 8) / 2;
870
871 va += sample_size;
872 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
873 radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
874 radeon_emit(cs, va);
875 radeon_emit(cs, va >> 32);
876
877 fence_va = va + sample_size;
878 break;
879 }
880 default:
881 assert(0);
882 }
883 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, query->buffer.buf, RADEON_USAGE_WRITE,
884 RADEON_PRIO_QUERY);
885
886 if (fence_va)
887 si_gfx_write_event_eop(sctx, V_028A90_BOTTOM_OF_PIPE_TS, 0,
888 EOP_DATA_SEL_VALUE_32BIT,
889 query->buffer.buf, fence_va, 0x80000000,
890 query->b.type);
891 }
892
893 static void si_query_hw_emit_stop(struct si_context *sctx,
894 struct si_query_hw *query)
895 {
896 uint64_t va;
897
898 if (!query->buffer.buf)
899 return; // previous buffer allocation failure
900
901 /* The queries which need begin already called this in begin_query. */
902 if (query->flags & SI_QUERY_HW_FLAG_NO_START)
903 si_need_gfx_cs_space(sctx);
904
905 /* emit end query */
906 va = query->buffer.buf->gpu_address + query->buffer.results_end;
907
908 query->ops->emit_stop(sctx, query, query->buffer.buf, va);
909
910 query->buffer.results_end += query->result_size;
911
912 if (!(query->flags & SI_QUERY_HW_FLAG_NO_START))
913 sctx->num_cs_dw_queries_suspend -= query->num_cs_dw_end;
914
915 si_update_occlusion_query_state(sctx, query->b.type, -1);
916 si_update_prims_generated_query_state(sctx, query->b.type, -1);
917 }
918
919 static void emit_set_predicate(struct si_context *ctx,
920 struct r600_resource *buf, uint64_t va,
921 uint32_t op)
922 {
923 struct radeon_cmdbuf *cs = ctx->gfx_cs;
924
925 if (ctx->chip_class >= GFX9) {
926 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
927 radeon_emit(cs, op);
928 radeon_emit(cs, va);
929 radeon_emit(cs, va >> 32);
930 } else {
931 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
932 radeon_emit(cs, va);
933 radeon_emit(cs, op | ((va >> 32) & 0xFF));
934 }
935 radeon_add_to_buffer_list(ctx, ctx->gfx_cs, buf, RADEON_USAGE_READ,
936 RADEON_PRIO_QUERY);
937 }
938
939 static void si_emit_query_predication(struct si_context *ctx)
940 {
941 struct si_query_hw *query = (struct si_query_hw *)ctx->render_cond;
942 struct si_query_buffer *qbuf;
943 uint32_t op;
944 bool flag_wait, invert;
945
946 if (!query)
947 return;
948
949 invert = ctx->render_cond_invert;
950 flag_wait = ctx->render_cond_mode == PIPE_RENDER_COND_WAIT ||
951 ctx->render_cond_mode == PIPE_RENDER_COND_BY_REGION_WAIT;
952
953 if (query->workaround_buf) {
954 op = PRED_OP(PREDICATION_OP_BOOL64);
955 } else {
956 switch (query->b.type) {
957 case PIPE_QUERY_OCCLUSION_COUNTER:
958 case PIPE_QUERY_OCCLUSION_PREDICATE:
959 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
960 op = PRED_OP(PREDICATION_OP_ZPASS);
961 break;
962 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
963 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
964 op = PRED_OP(PREDICATION_OP_PRIMCOUNT);
965 invert = !invert;
966 break;
967 default:
968 assert(0);
969 return;
970 }
971 }
972
973 /* if true then invert, see GL_ARB_conditional_render_inverted */
974 if (invert)
975 op |= PREDICATION_DRAW_NOT_VISIBLE; /* Draw if not visible or overflow */
976 else
977 op |= PREDICATION_DRAW_VISIBLE; /* Draw if visible or no overflow */
978
979 /* Use the value written by compute shader as a workaround. Note that
980 * the wait flag does not apply in this predication mode.
981 *
982 * The shader outputs the result value to L2. Workarounds only affect VI
983 * and later, where the CP reads data from L2, so we don't need an
984 * additional flush.
985 */
986 if (query->workaround_buf) {
987 uint64_t va = query->workaround_buf->gpu_address + query->workaround_offset;
988 emit_set_predicate(ctx, query->workaround_buf, va, op);
989 return;
990 }
991
992 op |= flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW;
993
994 /* emit predicate packets for all data blocks */
995 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
996 unsigned results_base = 0;
997 uint64_t va_base = qbuf->buf->gpu_address;
998
999 while (results_base < qbuf->results_end) {
1000 uint64_t va = va_base + results_base;
1001
1002 if (query->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE) {
1003 for (unsigned stream = 0; stream < SI_MAX_STREAMS; ++stream) {
1004 emit_set_predicate(ctx, qbuf->buf, va + 32 * stream, op);
1005
1006 /* set CONTINUE bit for all packets except the first */
1007 op |= PREDICATION_CONTINUE;
1008 }
1009 } else {
1010 emit_set_predicate(ctx, qbuf->buf, va, op);
1011 op |= PREDICATION_CONTINUE;
1012 }
1013
1014 results_base += query->result_size;
1015 }
1016 }
1017 }
1018
1019 static struct pipe_query *si_create_query(struct pipe_context *ctx, unsigned query_type, unsigned index)
1020 {
1021 struct si_screen *sscreen =
1022 (struct si_screen *)ctx->screen;
1023
1024 if (query_type == PIPE_QUERY_TIMESTAMP_DISJOINT ||
1025 query_type == PIPE_QUERY_GPU_FINISHED ||
1026 query_type >= PIPE_QUERY_DRIVER_SPECIFIC)
1027 return si_query_sw_create(query_type);
1028
1029 return si_query_hw_create(sscreen, query_type, index);
1030 }
1031
1032 static void si_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
1033 {
1034 struct si_context *sctx = (struct si_context *)ctx;
1035 struct si_query *rquery = (struct si_query *)query;
1036
1037 rquery->ops->destroy(sctx->screen, rquery);
1038 }
1039
1040 static boolean si_begin_query(struct pipe_context *ctx,
1041 struct pipe_query *query)
1042 {
1043 struct si_context *sctx = (struct si_context *)ctx;
1044 struct si_query *rquery = (struct si_query *)query;
1045
1046 return rquery->ops->begin(sctx, rquery);
1047 }
1048
1049 void si_query_hw_reset_buffers(struct si_context *sctx,
1050 struct si_query_hw *query)
1051 {
1052 struct si_query_buffer *prev = query->buffer.previous;
1053
1054 /* Discard the old query buffers. */
1055 while (prev) {
1056 struct si_query_buffer *qbuf = prev;
1057 prev = prev->previous;
1058 r600_resource_reference(&qbuf->buf, NULL);
1059 FREE(qbuf);
1060 }
1061
1062 query->buffer.results_end = 0;
1063 query->buffer.previous = NULL;
1064
1065 /* Obtain a new buffer if the current one can't be mapped without a stall. */
1066 if (si_rings_is_buffer_referenced(sctx, query->buffer.buf->buf, RADEON_USAGE_READWRITE) ||
1067 !sctx->ws->buffer_wait(query->buffer.buf->buf, 0, RADEON_USAGE_READWRITE)) {
1068 r600_resource_reference(&query->buffer.buf, NULL);
1069 query->buffer.buf = si_new_query_buffer(sctx->screen, query);
1070 } else {
1071 if (!query->ops->prepare_buffer(sctx->screen, query, query->buffer.buf))
1072 r600_resource_reference(&query->buffer.buf, NULL);
1073 }
1074 }
1075
1076 bool si_query_hw_begin(struct si_context *sctx,
1077 struct si_query *rquery)
1078 {
1079 struct si_query_hw *query = (struct si_query_hw *)rquery;
1080
1081 if (query->flags & SI_QUERY_HW_FLAG_NO_START) {
1082 assert(0);
1083 return false;
1084 }
1085
1086 if (!(query->flags & SI_QUERY_HW_FLAG_BEGIN_RESUMES))
1087 si_query_hw_reset_buffers(sctx, query);
1088
1089 r600_resource_reference(&query->workaround_buf, NULL);
1090
1091 si_query_hw_emit_start(sctx, query);
1092 if (!query->buffer.buf)
1093 return false;
1094
1095 LIST_ADDTAIL(&query->list, &sctx->active_queries);
1096 return true;
1097 }
1098
1099 static bool si_end_query(struct pipe_context *ctx, struct pipe_query *query)
1100 {
1101 struct si_context *sctx = (struct si_context *)ctx;
1102 struct si_query *rquery = (struct si_query *)query;
1103
1104 return rquery->ops->end(sctx, rquery);
1105 }
1106
1107 bool si_query_hw_end(struct si_context *sctx,
1108 struct si_query *rquery)
1109 {
1110 struct si_query_hw *query = (struct si_query_hw *)rquery;
1111
1112 if (query->flags & SI_QUERY_HW_FLAG_NO_START)
1113 si_query_hw_reset_buffers(sctx, query);
1114
1115 si_query_hw_emit_stop(sctx, query);
1116
1117 if (!(query->flags & SI_QUERY_HW_FLAG_NO_START))
1118 LIST_DELINIT(&query->list);
1119
1120 if (!query->buffer.buf)
1121 return false;
1122
1123 return true;
1124 }
1125
1126 static void si_get_hw_query_params(struct si_context *sctx,
1127 struct si_query_hw *rquery, int index,
1128 struct si_hw_query_params *params)
1129 {
1130 unsigned max_rbs = sctx->screen->info.num_render_backends;
1131
1132 params->pair_stride = 0;
1133 params->pair_count = 1;
1134
1135 switch (rquery->b.type) {
1136 case PIPE_QUERY_OCCLUSION_COUNTER:
1137 case PIPE_QUERY_OCCLUSION_PREDICATE:
1138 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1139 params->start_offset = 0;
1140 params->end_offset = 8;
1141 params->fence_offset = max_rbs * 16;
1142 params->pair_stride = 16;
1143 params->pair_count = max_rbs;
1144 break;
1145 case PIPE_QUERY_TIME_ELAPSED:
1146 params->start_offset = 0;
1147 params->end_offset = 8;
1148 params->fence_offset = 16;
1149 break;
1150 case PIPE_QUERY_TIMESTAMP:
1151 params->start_offset = 0;
1152 params->end_offset = 0;
1153 params->fence_offset = 8;
1154 break;
1155 case PIPE_QUERY_PRIMITIVES_EMITTED:
1156 params->start_offset = 8;
1157 params->end_offset = 24;
1158 params->fence_offset = params->end_offset + 4;
1159 break;
1160 case PIPE_QUERY_PRIMITIVES_GENERATED:
1161 params->start_offset = 0;
1162 params->end_offset = 16;
1163 params->fence_offset = params->end_offset + 4;
1164 break;
1165 case PIPE_QUERY_SO_STATISTICS:
1166 params->start_offset = 8 - index * 8;
1167 params->end_offset = 24 - index * 8;
1168 params->fence_offset = params->end_offset + 4;
1169 break;
1170 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
1171 params->pair_count = SI_MAX_STREAMS;
1172 params->pair_stride = 32;
1173 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1174 params->start_offset = 0;
1175 params->end_offset = 16;
1176
1177 /* We can re-use the high dword of the last 64-bit value as a
1178 * fence: it is initialized as 0, and the high bit is set by
1179 * the write of the streamout stats event.
1180 */
1181 params->fence_offset = rquery->result_size - 4;
1182 break;
1183 case PIPE_QUERY_PIPELINE_STATISTICS:
1184 {
1185 static const unsigned offsets[] = {56, 48, 24, 32, 40, 16, 8, 0, 64, 72, 80};
1186 params->start_offset = offsets[index];
1187 params->end_offset = 88 + offsets[index];
1188 params->fence_offset = 2 * 88;
1189 break;
1190 }
1191 default:
1192 unreachable("si_get_hw_query_params unsupported");
1193 }
1194 }
1195
1196 static unsigned si_query_read_result(void *map, unsigned start_index, unsigned end_index,
1197 bool test_status_bit)
1198 {
1199 uint32_t *current_result = (uint32_t*)map;
1200 uint64_t start, end;
1201
1202 start = (uint64_t)current_result[start_index] |
1203 (uint64_t)current_result[start_index+1] << 32;
1204 end = (uint64_t)current_result[end_index] |
1205 (uint64_t)current_result[end_index+1] << 32;
1206
1207 if (!test_status_bit ||
1208 ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) {
1209 return end - start;
1210 }
1211 return 0;
1212 }
1213
1214 static void si_query_hw_add_result(struct si_screen *sscreen,
1215 struct si_query_hw *query,
1216 void *buffer,
1217 union pipe_query_result *result)
1218 {
1219 unsigned max_rbs = sscreen->info.num_render_backends;
1220
1221 switch (query->b.type) {
1222 case PIPE_QUERY_OCCLUSION_COUNTER: {
1223 for (unsigned i = 0; i < max_rbs; ++i) {
1224 unsigned results_base = i * 16;
1225 result->u64 +=
1226 si_query_read_result(buffer + results_base, 0, 2, true);
1227 }
1228 break;
1229 }
1230 case PIPE_QUERY_OCCLUSION_PREDICATE:
1231 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: {
1232 for (unsigned i = 0; i < max_rbs; ++i) {
1233 unsigned results_base = i * 16;
1234 result->b = result->b ||
1235 si_query_read_result(buffer + results_base, 0, 2, true) != 0;
1236 }
1237 break;
1238 }
1239 case PIPE_QUERY_TIME_ELAPSED:
1240 result->u64 += si_query_read_result(buffer, 0, 2, false);
1241 break;
1242 case PIPE_QUERY_TIMESTAMP:
1243 result->u64 = *(uint64_t*)buffer;
1244 break;
1245 case PIPE_QUERY_PRIMITIVES_EMITTED:
1246 /* SAMPLE_STREAMOUTSTATS stores this structure:
1247 * {
1248 * u64 NumPrimitivesWritten;
1249 * u64 PrimitiveStorageNeeded;
1250 * }
1251 * We only need NumPrimitivesWritten here. */
1252 result->u64 += si_query_read_result(buffer, 2, 6, true);
1253 break;
1254 case PIPE_QUERY_PRIMITIVES_GENERATED:
1255 /* Here we read PrimitiveStorageNeeded. */
1256 result->u64 += si_query_read_result(buffer, 0, 4, true);
1257 break;
1258 case PIPE_QUERY_SO_STATISTICS:
1259 result->so_statistics.num_primitives_written +=
1260 si_query_read_result(buffer, 2, 6, true);
1261 result->so_statistics.primitives_storage_needed +=
1262 si_query_read_result(buffer, 0, 4, true);
1263 break;
1264 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1265 result->b = result->b ||
1266 si_query_read_result(buffer, 2, 6, true) !=
1267 si_query_read_result(buffer, 0, 4, true);
1268 break;
1269 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
1270 for (unsigned stream = 0; stream < SI_MAX_STREAMS; ++stream) {
1271 result->b = result->b ||
1272 si_query_read_result(buffer, 2, 6, true) !=
1273 si_query_read_result(buffer, 0, 4, true);
1274 buffer = (char *)buffer + 32;
1275 }
1276 break;
1277 case PIPE_QUERY_PIPELINE_STATISTICS:
1278 result->pipeline_statistics.ps_invocations +=
1279 si_query_read_result(buffer, 0, 22, false);
1280 result->pipeline_statistics.c_primitives +=
1281 si_query_read_result(buffer, 2, 24, false);
1282 result->pipeline_statistics.c_invocations +=
1283 si_query_read_result(buffer, 4, 26, false);
1284 result->pipeline_statistics.vs_invocations +=
1285 si_query_read_result(buffer, 6, 28, false);
1286 result->pipeline_statistics.gs_invocations +=
1287 si_query_read_result(buffer, 8, 30, false);
1288 result->pipeline_statistics.gs_primitives +=
1289 si_query_read_result(buffer, 10, 32, false);
1290 result->pipeline_statistics.ia_primitives +=
1291 si_query_read_result(buffer, 12, 34, false);
1292 result->pipeline_statistics.ia_vertices +=
1293 si_query_read_result(buffer, 14, 36, false);
1294 result->pipeline_statistics.hs_invocations +=
1295 si_query_read_result(buffer, 16, 38, false);
1296 result->pipeline_statistics.ds_invocations +=
1297 si_query_read_result(buffer, 18, 40, false);
1298 result->pipeline_statistics.cs_invocations +=
1299 si_query_read_result(buffer, 20, 42, false);
1300 #if 0 /* for testing */
1301 printf("Pipeline stats: IA verts=%llu, IA prims=%llu, VS=%llu, HS=%llu, "
1302 "DS=%llu, GS=%llu, GS prims=%llu, Clipper=%llu, "
1303 "Clipper prims=%llu, PS=%llu, CS=%llu\n",
1304 result->pipeline_statistics.ia_vertices,
1305 result->pipeline_statistics.ia_primitives,
1306 result->pipeline_statistics.vs_invocations,
1307 result->pipeline_statistics.hs_invocations,
1308 result->pipeline_statistics.ds_invocations,
1309 result->pipeline_statistics.gs_invocations,
1310 result->pipeline_statistics.gs_primitives,
1311 result->pipeline_statistics.c_invocations,
1312 result->pipeline_statistics.c_primitives,
1313 result->pipeline_statistics.ps_invocations,
1314 result->pipeline_statistics.cs_invocations);
1315 #endif
1316 break;
1317 default:
1318 assert(0);
1319 }
1320 }
1321
1322 static boolean si_get_query_result(struct pipe_context *ctx,
1323 struct pipe_query *query, boolean wait,
1324 union pipe_query_result *result)
1325 {
1326 struct si_context *sctx = (struct si_context *)ctx;
1327 struct si_query *rquery = (struct si_query *)query;
1328
1329 return rquery->ops->get_result(sctx, rquery, wait, result);
1330 }
1331
1332 static void si_get_query_result_resource(struct pipe_context *ctx,
1333 struct pipe_query *query,
1334 boolean wait,
1335 enum pipe_query_value_type result_type,
1336 int index,
1337 struct pipe_resource *resource,
1338 unsigned offset)
1339 {
1340 struct si_context *sctx = (struct si_context *)ctx;
1341 struct si_query *rquery = (struct si_query *)query;
1342
1343 rquery->ops->get_result_resource(sctx, rquery, wait, result_type, index,
1344 resource, offset);
1345 }
1346
1347 static void si_query_hw_clear_result(struct si_query_hw *query,
1348 union pipe_query_result *result)
1349 {
1350 util_query_clear_result(result, query->b.type);
1351 }
1352
1353 bool si_query_hw_get_result(struct si_context *sctx,
1354 struct si_query *rquery,
1355 bool wait, union pipe_query_result *result)
1356 {
1357 struct si_screen *sscreen = sctx->screen;
1358 struct si_query_hw *query = (struct si_query_hw *)rquery;
1359 struct si_query_buffer *qbuf;
1360
1361 query->ops->clear_result(query, result);
1362
1363 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
1364 unsigned usage = PIPE_TRANSFER_READ |
1365 (wait ? 0 : PIPE_TRANSFER_DONTBLOCK);
1366 unsigned results_base = 0;
1367 void *map;
1368
1369 if (rquery->b.flushed)
1370 map = sctx->ws->buffer_map(qbuf->buf->buf, NULL, usage);
1371 else
1372 map = si_buffer_map_sync_with_rings(sctx, qbuf->buf, usage);
1373
1374 if (!map)
1375 return false;
1376
1377 while (results_base != qbuf->results_end) {
1378 query->ops->add_result(sscreen, query, map + results_base,
1379 result);
1380 results_base += query->result_size;
1381 }
1382 }
1383
1384 /* Convert the time to expected units. */
1385 if (rquery->type == PIPE_QUERY_TIME_ELAPSED ||
1386 rquery->type == PIPE_QUERY_TIMESTAMP) {
1387 result->u64 = (1000000 * result->u64) / sscreen->info.clock_crystal_freq;
1388 }
1389 return true;
1390 }
1391
1392 /* Create the compute shader that is used to collect the results.
1393 *
1394 * One compute grid with a single thread is launched for every query result
1395 * buffer. The thread (optionally) reads a previous summary buffer, then
1396 * accumulates data from the query result buffer, and writes the result either
1397 * to a summary buffer to be consumed by the next grid invocation or to the
1398 * user-supplied buffer.
1399 *
1400 * Data layout:
1401 *
1402 * CONST
1403 * 0.x = end_offset
1404 * 0.y = result_stride
1405 * 0.z = result_count
1406 * 0.w = bit field:
1407 * 1: read previously accumulated values
1408 * 2: write accumulated values for chaining
1409 * 4: write result available
1410 * 8: convert result to boolean (0/1)
1411 * 16: only read one dword and use that as result
1412 * 32: apply timestamp conversion
1413 * 64: store full 64 bits result
1414 * 128: store signed 32 bits result
1415 * 256: SO_OVERFLOW mode: take the difference of two successive half-pairs
1416 * 1.x = fence_offset
1417 * 1.y = pair_stride
1418 * 1.z = pair_count
1419 *
1420 * BUFFER[0] = query result buffer
1421 * BUFFER[1] = previous summary buffer
1422 * BUFFER[2] = next summary buffer or user-supplied buffer
1423 */
1424 static void si_create_query_result_shader(struct si_context *sctx)
1425 {
1426 /* TEMP[0].xy = accumulated result so far
1427 * TEMP[0].z = result not available
1428 *
1429 * TEMP[1].x = current result index
1430 * TEMP[1].y = current pair index
1431 */
1432 static const char text_tmpl[] =
1433 "COMP\n"
1434 "PROPERTY CS_FIXED_BLOCK_WIDTH 1\n"
1435 "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
1436 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
1437 "DCL BUFFER[0]\n"
1438 "DCL BUFFER[1]\n"
1439 "DCL BUFFER[2]\n"
1440 "DCL CONST[0][0..1]\n"
1441 "DCL TEMP[0..5]\n"
1442 "IMM[0] UINT32 {0, 31, 2147483647, 4294967295}\n"
1443 "IMM[1] UINT32 {1, 2, 4, 8}\n"
1444 "IMM[2] UINT32 {16, 32, 64, 128}\n"
1445 "IMM[3] UINT32 {1000000, 0, %u, 0}\n" /* for timestamp conversion */
1446 "IMM[4] UINT32 {256, 0, 0, 0}\n"
1447
1448 "AND TEMP[5], CONST[0][0].wwww, IMM[2].xxxx\n"
1449 "UIF TEMP[5]\n"
1450 /* Check result availability. */
1451 "LOAD TEMP[1].x, BUFFER[0], CONST[0][1].xxxx\n"
1452 "ISHR TEMP[0].z, TEMP[1].xxxx, IMM[0].yyyy\n"
1453 "MOV TEMP[1], TEMP[0].zzzz\n"
1454 "NOT TEMP[0].z, TEMP[0].zzzz\n"
1455
1456 /* Load result if available. */
1457 "UIF TEMP[1]\n"
1458 "LOAD TEMP[0].xy, BUFFER[0], IMM[0].xxxx\n"
1459 "ENDIF\n"
1460 "ELSE\n"
1461 /* Load previously accumulated result if requested. */
1462 "MOV TEMP[0], IMM[0].xxxx\n"
1463 "AND TEMP[4], CONST[0][0].wwww, IMM[1].xxxx\n"
1464 "UIF TEMP[4]\n"
1465 "LOAD TEMP[0].xyz, BUFFER[1], IMM[0].xxxx\n"
1466 "ENDIF\n"
1467
1468 "MOV TEMP[1].x, IMM[0].xxxx\n"
1469 "BGNLOOP\n"
1470 /* Break if accumulated result so far is not available. */
1471 "UIF TEMP[0].zzzz\n"
1472 "BRK\n"
1473 "ENDIF\n"
1474
1475 /* Break if result_index >= result_count. */
1476 "USGE TEMP[5], TEMP[1].xxxx, CONST[0][0].zzzz\n"
1477 "UIF TEMP[5]\n"
1478 "BRK\n"
1479 "ENDIF\n"
1480
1481 /* Load fence and check result availability */
1482 "UMAD TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy, CONST[0][1].xxxx\n"
1483 "LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n"
1484 "ISHR TEMP[0].z, TEMP[5].xxxx, IMM[0].yyyy\n"
1485 "NOT TEMP[0].z, TEMP[0].zzzz\n"
1486 "UIF TEMP[0].zzzz\n"
1487 "BRK\n"
1488 "ENDIF\n"
1489
1490 "MOV TEMP[1].y, IMM[0].xxxx\n"
1491 "BGNLOOP\n"
1492 /* Load start and end. */
1493 "UMUL TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy\n"
1494 "UMAD TEMP[5].x, TEMP[1].yyyy, CONST[0][1].yyyy, TEMP[5].xxxx\n"
1495 "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
1496
1497 "UADD TEMP[5].y, TEMP[5].xxxx, CONST[0][0].xxxx\n"
1498 "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
1499
1500 "U64ADD TEMP[4].xy, TEMP[3], -TEMP[2]\n"
1501
1502 "AND TEMP[5].z, CONST[0][0].wwww, IMM[4].xxxx\n"
1503 "UIF TEMP[5].zzzz\n"
1504 /* Load second start/end half-pair and
1505 * take the difference
1506 */
1507 "UADD TEMP[5].xy, TEMP[5], IMM[1].wwww\n"
1508 "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
1509 "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
1510
1511 "U64ADD TEMP[3].xy, TEMP[3], -TEMP[2]\n"
1512 "U64ADD TEMP[4].xy, TEMP[4], -TEMP[3]\n"
1513 "ENDIF\n"
1514
1515 "U64ADD TEMP[0].xy, TEMP[0], TEMP[4]\n"
1516
1517 /* Increment pair index */
1518 "UADD TEMP[1].y, TEMP[1].yyyy, IMM[1].xxxx\n"
1519 "USGE TEMP[5], TEMP[1].yyyy, CONST[0][1].zzzz\n"
1520 "UIF TEMP[5]\n"
1521 "BRK\n"
1522 "ENDIF\n"
1523 "ENDLOOP\n"
1524
1525 /* Increment result index */
1526 "UADD TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx\n"
1527 "ENDLOOP\n"
1528 "ENDIF\n"
1529
1530 "AND TEMP[4], CONST[0][0].wwww, IMM[1].yyyy\n"
1531 "UIF TEMP[4]\n"
1532 /* Store accumulated data for chaining. */
1533 "STORE BUFFER[2].xyz, IMM[0].xxxx, TEMP[0]\n"
1534 "ELSE\n"
1535 "AND TEMP[4], CONST[0][0].wwww, IMM[1].zzzz\n"
1536 "UIF TEMP[4]\n"
1537 /* Store result availability. */
1538 "NOT TEMP[0].z, TEMP[0]\n"
1539 "AND TEMP[0].z, TEMP[0].zzzz, IMM[1].xxxx\n"
1540 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].zzzz\n"
1541
1542 "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
1543 "UIF TEMP[4]\n"
1544 "STORE BUFFER[2].y, IMM[0].xxxx, IMM[0].xxxx\n"
1545 "ENDIF\n"
1546 "ELSE\n"
1547 /* Store result if it is available. */
1548 "NOT TEMP[4], TEMP[0].zzzz\n"
1549 "UIF TEMP[4]\n"
1550 /* Apply timestamp conversion */
1551 "AND TEMP[4], CONST[0][0].wwww, IMM[2].yyyy\n"
1552 "UIF TEMP[4]\n"
1553 "U64MUL TEMP[0].xy, TEMP[0], IMM[3].xyxy\n"
1554 "U64DIV TEMP[0].xy, TEMP[0], IMM[3].zwzw\n"
1555 "ENDIF\n"
1556
1557 /* Convert to boolean */
1558 "AND TEMP[4], CONST[0][0].wwww, IMM[1].wwww\n"
1559 "UIF TEMP[4]\n"
1560 "U64SNE TEMP[0].x, TEMP[0].xyxy, IMM[4].zwzw\n"
1561 "AND TEMP[0].x, TEMP[0].xxxx, IMM[1].xxxx\n"
1562 "MOV TEMP[0].y, IMM[0].xxxx\n"
1563 "ENDIF\n"
1564
1565 "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
1566 "UIF TEMP[4]\n"
1567 "STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0].xyxy\n"
1568 "ELSE\n"
1569 /* Clamping */
1570 "UIF TEMP[0].yyyy\n"
1571 "MOV TEMP[0].x, IMM[0].wwww\n"
1572 "ENDIF\n"
1573
1574 "AND TEMP[4], CONST[0][0].wwww, IMM[2].wwww\n"
1575 "UIF TEMP[4]\n"
1576 "UMIN TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz\n"
1577 "ENDIF\n"
1578
1579 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].xxxx\n"
1580 "ENDIF\n"
1581 "ENDIF\n"
1582 "ENDIF\n"
1583 "ENDIF\n"
1584
1585 "END\n";
1586
1587 char text[sizeof(text_tmpl) + 32];
1588 struct tgsi_token tokens[1024];
1589 struct pipe_compute_state state = {};
1590
1591 /* Hard code the frequency into the shader so that the backend can
1592 * use the full range of optimizations for divide-by-constant.
1593 */
1594 snprintf(text, sizeof(text), text_tmpl,
1595 sctx->screen->info.clock_crystal_freq);
1596
1597 if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
1598 assert(false);
1599 return;
1600 }
1601
1602 state.ir_type = PIPE_SHADER_IR_TGSI;
1603 state.prog = tokens;
1604
1605 sctx->query_result_shader = sctx->b.create_compute_state(&sctx->b, &state);
1606 }
1607
1608 static void si_restore_qbo_state(struct si_context *sctx,
1609 struct si_qbo_state *st)
1610 {
1611 sctx->b.bind_compute_state(&sctx->b, st->saved_compute);
1612
1613 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1614 pipe_resource_reference(&st->saved_const0.buffer, NULL);
1615
1616 sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1617 for (unsigned i = 0; i < 3; ++i)
1618 pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
1619 }
1620
1621 static void si_query_hw_get_result_resource(struct si_context *sctx,
1622 struct si_query *rquery,
1623 bool wait,
1624 enum pipe_query_value_type result_type,
1625 int index,
1626 struct pipe_resource *resource,
1627 unsigned offset)
1628 {
1629 struct si_query_hw *query = (struct si_query_hw *)rquery;
1630 struct si_query_buffer *qbuf;
1631 struct si_query_buffer *qbuf_prev;
1632 struct pipe_resource *tmp_buffer = NULL;
1633 unsigned tmp_buffer_offset = 0;
1634 struct si_qbo_state saved_state = {};
1635 struct pipe_grid_info grid = {};
1636 struct pipe_constant_buffer constant_buffer = {};
1637 struct pipe_shader_buffer ssbo[3];
1638 struct si_hw_query_params params;
1639 struct {
1640 uint32_t end_offset;
1641 uint32_t result_stride;
1642 uint32_t result_count;
1643 uint32_t config;
1644 uint32_t fence_offset;
1645 uint32_t pair_stride;
1646 uint32_t pair_count;
1647 } consts;
1648
1649 if (!sctx->query_result_shader) {
1650 si_create_query_result_shader(sctx);
1651 if (!sctx->query_result_shader)
1652 return;
1653 }
1654
1655 if (query->buffer.previous) {
1656 u_suballocator_alloc(sctx->allocator_zeroed_memory, 16, 16,
1657 &tmp_buffer_offset, &tmp_buffer);
1658 if (!tmp_buffer)
1659 return;
1660 }
1661
1662 si_save_qbo_state(sctx, &saved_state);
1663
1664 si_get_hw_query_params(sctx, query, index >= 0 ? index : 0, &params);
1665 consts.end_offset = params.end_offset - params.start_offset;
1666 consts.fence_offset = params.fence_offset - params.start_offset;
1667 consts.result_stride = query->result_size;
1668 consts.pair_stride = params.pair_stride;
1669 consts.pair_count = params.pair_count;
1670
1671 constant_buffer.buffer_size = sizeof(consts);
1672 constant_buffer.user_buffer = &consts;
1673
1674 ssbo[1].buffer = tmp_buffer;
1675 ssbo[1].buffer_offset = tmp_buffer_offset;
1676 ssbo[1].buffer_size = 16;
1677
1678 ssbo[2] = ssbo[1];
1679
1680 sctx->b.bind_compute_state(&sctx->b, sctx->query_result_shader);
1681
1682 grid.block[0] = 1;
1683 grid.block[1] = 1;
1684 grid.block[2] = 1;
1685 grid.grid[0] = 1;
1686 grid.grid[1] = 1;
1687 grid.grid[2] = 1;
1688
1689 consts.config = 0;
1690 if (index < 0)
1691 consts.config |= 4;
1692 if (query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE ||
1693 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE)
1694 consts.config |= 8;
1695 else if (query->b.type == PIPE_QUERY_SO_OVERFLOW_PREDICATE ||
1696 query->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE)
1697 consts.config |= 8 | 256;
1698 else if (query->b.type == PIPE_QUERY_TIMESTAMP ||
1699 query->b.type == PIPE_QUERY_TIME_ELAPSED)
1700 consts.config |= 32;
1701
1702 switch (result_type) {
1703 case PIPE_QUERY_TYPE_U64:
1704 case PIPE_QUERY_TYPE_I64:
1705 consts.config |= 64;
1706 break;
1707 case PIPE_QUERY_TYPE_I32:
1708 consts.config |= 128;
1709 break;
1710 case PIPE_QUERY_TYPE_U32:
1711 break;
1712 }
1713
1714 sctx->flags |= sctx->screen->barrier_flags.cp_to_L2;
1715
1716 for (qbuf = &query->buffer; qbuf; qbuf = qbuf_prev) {
1717 if (query->b.type != PIPE_QUERY_TIMESTAMP) {
1718 qbuf_prev = qbuf->previous;
1719 consts.result_count = qbuf->results_end / query->result_size;
1720 consts.config &= ~3;
1721 if (qbuf != &query->buffer)
1722 consts.config |= 1;
1723 if (qbuf->previous)
1724 consts.config |= 2;
1725 } else {
1726 /* Only read the last timestamp. */
1727 qbuf_prev = NULL;
1728 consts.result_count = 0;
1729 consts.config |= 16;
1730 params.start_offset += qbuf->results_end - query->result_size;
1731 }
1732
1733 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, &constant_buffer);
1734
1735 ssbo[0].buffer = &qbuf->buf->b.b;
1736 ssbo[0].buffer_offset = params.start_offset;
1737 ssbo[0].buffer_size = qbuf->results_end - params.start_offset;
1738
1739 if (!qbuf->previous) {
1740 ssbo[2].buffer = resource;
1741 ssbo[2].buffer_offset = offset;
1742 ssbo[2].buffer_size = 8;
1743
1744 r600_resource(resource)->TC_L2_dirty = true;
1745 }
1746
1747 sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, ssbo);
1748
1749 if (wait && qbuf == &query->buffer) {
1750 uint64_t va;
1751
1752 /* Wait for result availability. Wait only for readiness
1753 * of the last entry, since the fence writes should be
1754 * serialized in the CP.
1755 */
1756 va = qbuf->buf->gpu_address + qbuf->results_end - query->result_size;
1757 va += params.fence_offset;
1758
1759 si_gfx_wait_fence(sctx, va, 0x80000000, 0x80000000);
1760 }
1761
1762 sctx->b.launch_grid(&sctx->b, &grid);
1763 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
1764 }
1765
1766 si_restore_qbo_state(sctx, &saved_state);
1767 pipe_resource_reference(&tmp_buffer, NULL);
1768 }
1769
1770 static void si_render_condition(struct pipe_context *ctx,
1771 struct pipe_query *query,
1772 boolean condition,
1773 enum pipe_render_cond_flag mode)
1774 {
1775 struct si_context *sctx = (struct si_context *)ctx;
1776 struct si_query_hw *rquery = (struct si_query_hw *)query;
1777 struct si_atom *atom = &sctx->atoms.s.render_cond;
1778
1779 if (query) {
1780 bool needs_workaround = false;
1781
1782 /* There was a firmware regression in VI which causes successive
1783 * SET_PREDICATION packets to give the wrong answer for
1784 * non-inverted stream overflow predication.
1785 */
1786 if (((sctx->chip_class == VI && sctx->screen->info.pfp_fw_feature < 49) ||
1787 (sctx->chip_class == GFX9 && sctx->screen->info.pfp_fw_feature < 38)) &&
1788 !condition &&
1789 (rquery->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE ||
1790 (rquery->b.type == PIPE_QUERY_SO_OVERFLOW_PREDICATE &&
1791 (rquery->buffer.previous ||
1792 rquery->buffer.results_end > rquery->result_size)))) {
1793 needs_workaround = true;
1794 }
1795
1796 if (needs_workaround && !rquery->workaround_buf) {
1797 bool old_force_off = sctx->render_cond_force_off;
1798 sctx->render_cond_force_off = true;
1799
1800 u_suballocator_alloc(
1801 sctx->allocator_zeroed_memory, 8, 8,
1802 &rquery->workaround_offset,
1803 (struct pipe_resource **)&rquery->workaround_buf);
1804
1805 /* Reset to NULL to avoid a redundant SET_PREDICATION
1806 * from launching the compute grid.
1807 */
1808 sctx->render_cond = NULL;
1809
1810 ctx->get_query_result_resource(
1811 ctx, query, true, PIPE_QUERY_TYPE_U64, 0,
1812 &rquery->workaround_buf->b.b, rquery->workaround_offset);
1813
1814 /* Settings this in the render cond atom is too late,
1815 * so set it here. */
1816 sctx->flags |= sctx->screen->barrier_flags.L2_to_cp |
1817 SI_CONTEXT_FLUSH_FOR_RENDER_COND;
1818
1819 sctx->render_cond_force_off = old_force_off;
1820 }
1821 }
1822
1823 sctx->render_cond = query;
1824 sctx->render_cond_invert = condition;
1825 sctx->render_cond_mode = mode;
1826
1827 si_set_atom_dirty(sctx, atom, query != NULL);
1828 }
1829
1830 void si_suspend_queries(struct si_context *sctx)
1831 {
1832 struct si_query_hw *query;
1833
1834 LIST_FOR_EACH_ENTRY(query, &sctx->active_queries, list) {
1835 si_query_hw_emit_stop(sctx, query);
1836 }
1837 assert(sctx->num_cs_dw_queries_suspend == 0);
1838 }
1839
1840 void si_resume_queries(struct si_context *sctx)
1841 {
1842 struct si_query_hw *query;
1843
1844 assert(sctx->num_cs_dw_queries_suspend == 0);
1845
1846 /* Check CS space here. Resuming must not be interrupted by flushes. */
1847 si_need_gfx_cs_space(sctx);
1848
1849 LIST_FOR_EACH_ENTRY(query, &sctx->active_queries, list) {
1850 si_query_hw_emit_start(sctx, query);
1851 }
1852 }
1853
1854 #define XFULL(name_, query_type_, type_, result_type_, group_id_) \
1855 { \
1856 .name = name_, \
1857 .query_type = SI_QUERY_##query_type_, \
1858 .type = PIPE_DRIVER_QUERY_TYPE_##type_, \
1859 .result_type = PIPE_DRIVER_QUERY_RESULT_TYPE_##result_type_, \
1860 .group_id = group_id_ \
1861 }
1862
1863 #define X(name_, query_type_, type_, result_type_) \
1864 XFULL(name_, query_type_, type_, result_type_, ~(unsigned)0)
1865
1866 #define XG(group_, name_, query_type_, type_, result_type_) \
1867 XFULL(name_, query_type_, type_, result_type_, SI_QUERY_GROUP_##group_)
1868
1869 static struct pipe_driver_query_info si_driver_query_list[] = {
1870 X("num-compilations", NUM_COMPILATIONS, UINT64, CUMULATIVE),
1871 X("num-shaders-created", NUM_SHADERS_CREATED, UINT64, CUMULATIVE),
1872 X("num-shader-cache-hits", NUM_SHADER_CACHE_HITS, UINT64, CUMULATIVE),
1873 X("draw-calls", DRAW_CALLS, UINT64, AVERAGE),
1874 X("decompress-calls", DECOMPRESS_CALLS, UINT64, AVERAGE),
1875 X("MRT-draw-calls", MRT_DRAW_CALLS, UINT64, AVERAGE),
1876 X("prim-restart-calls", PRIM_RESTART_CALLS, UINT64, AVERAGE),
1877 X("spill-draw-calls", SPILL_DRAW_CALLS, UINT64, AVERAGE),
1878 X("compute-calls", COMPUTE_CALLS, UINT64, AVERAGE),
1879 X("spill-compute-calls", SPILL_COMPUTE_CALLS, UINT64, AVERAGE),
1880 X("dma-calls", DMA_CALLS, UINT64, AVERAGE),
1881 X("cp-dma-calls", CP_DMA_CALLS, UINT64, AVERAGE),
1882 X("num-vs-flushes", NUM_VS_FLUSHES, UINT64, AVERAGE),
1883 X("num-ps-flushes", NUM_PS_FLUSHES, UINT64, AVERAGE),
1884 X("num-cs-flushes", NUM_CS_FLUSHES, UINT64, AVERAGE),
1885 X("num-CB-cache-flushes", NUM_CB_CACHE_FLUSHES, UINT64, AVERAGE),
1886 X("num-DB-cache-flushes", NUM_DB_CACHE_FLUSHES, UINT64, AVERAGE),
1887 X("num-L2-invalidates", NUM_L2_INVALIDATES, UINT64, AVERAGE),
1888 X("num-L2-writebacks", NUM_L2_WRITEBACKS, UINT64, AVERAGE),
1889 X("num-resident-handles", NUM_RESIDENT_HANDLES, UINT64, AVERAGE),
1890 X("tc-offloaded-slots", TC_OFFLOADED_SLOTS, UINT64, AVERAGE),
1891 X("tc-direct-slots", TC_DIRECT_SLOTS, UINT64, AVERAGE),
1892 X("tc-num-syncs", TC_NUM_SYNCS, UINT64, AVERAGE),
1893 X("CS-thread-busy", CS_THREAD_BUSY, UINT64, AVERAGE),
1894 X("gallium-thread-busy", GALLIUM_THREAD_BUSY, UINT64, AVERAGE),
1895 X("requested-VRAM", REQUESTED_VRAM, BYTES, AVERAGE),
1896 X("requested-GTT", REQUESTED_GTT, BYTES, AVERAGE),
1897 X("mapped-VRAM", MAPPED_VRAM, BYTES, AVERAGE),
1898 X("mapped-GTT", MAPPED_GTT, BYTES, AVERAGE),
1899 X("buffer-wait-time", BUFFER_WAIT_TIME, MICROSECONDS, CUMULATIVE),
1900 X("num-mapped-buffers", NUM_MAPPED_BUFFERS, UINT64, AVERAGE),
1901 X("num-GFX-IBs", NUM_GFX_IBS, UINT64, AVERAGE),
1902 X("num-SDMA-IBs", NUM_SDMA_IBS, UINT64, AVERAGE),
1903 X("GFX-BO-list-size", GFX_BO_LIST_SIZE, UINT64, AVERAGE),
1904 X("GFX-IB-size", GFX_IB_SIZE, UINT64, AVERAGE),
1905 X("num-bytes-moved", NUM_BYTES_MOVED, BYTES, CUMULATIVE),
1906 X("num-evictions", NUM_EVICTIONS, UINT64, CUMULATIVE),
1907 X("VRAM-CPU-page-faults", NUM_VRAM_CPU_PAGE_FAULTS, UINT64, CUMULATIVE),
1908 X("VRAM-usage", VRAM_USAGE, BYTES, AVERAGE),
1909 X("VRAM-vis-usage", VRAM_VIS_USAGE, BYTES, AVERAGE),
1910 X("GTT-usage", GTT_USAGE, BYTES, AVERAGE),
1911 X("back-buffer-ps-draw-ratio", BACK_BUFFER_PS_DRAW_RATIO, UINT64, AVERAGE),
1912
1913 /* GPIN queries are for the benefit of old versions of GPUPerfStudio,
1914 * which use it as a fallback path to detect the GPU type.
1915 *
1916 * Note: The names of these queries are significant for GPUPerfStudio
1917 * (and possibly their order as well). */
1918 XG(GPIN, "GPIN_000", GPIN_ASIC_ID, UINT, AVERAGE),
1919 XG(GPIN, "GPIN_001", GPIN_NUM_SIMD, UINT, AVERAGE),
1920 XG(GPIN, "GPIN_002", GPIN_NUM_RB, UINT, AVERAGE),
1921 XG(GPIN, "GPIN_003", GPIN_NUM_SPI, UINT, AVERAGE),
1922 XG(GPIN, "GPIN_004", GPIN_NUM_SE, UINT, AVERAGE),
1923
1924 X("temperature", GPU_TEMPERATURE, UINT64, AVERAGE),
1925 X("shader-clock", CURRENT_GPU_SCLK, HZ, AVERAGE),
1926 X("memory-clock", CURRENT_GPU_MCLK, HZ, AVERAGE),
1927
1928 /* The following queries must be at the end of the list because their
1929 * availability is adjusted dynamically based on the DRM version. */
1930 X("GPU-load", GPU_LOAD, UINT64, AVERAGE),
1931 X("GPU-shaders-busy", GPU_SHADERS_BUSY, UINT64, AVERAGE),
1932 X("GPU-ta-busy", GPU_TA_BUSY, UINT64, AVERAGE),
1933 X("GPU-gds-busy", GPU_GDS_BUSY, UINT64, AVERAGE),
1934 X("GPU-vgt-busy", GPU_VGT_BUSY, UINT64, AVERAGE),
1935 X("GPU-ia-busy", GPU_IA_BUSY, UINT64, AVERAGE),
1936 X("GPU-sx-busy", GPU_SX_BUSY, UINT64, AVERAGE),
1937 X("GPU-wd-busy", GPU_WD_BUSY, UINT64, AVERAGE),
1938 X("GPU-bci-busy", GPU_BCI_BUSY, UINT64, AVERAGE),
1939 X("GPU-sc-busy", GPU_SC_BUSY, UINT64, AVERAGE),
1940 X("GPU-pa-busy", GPU_PA_BUSY, UINT64, AVERAGE),
1941 X("GPU-db-busy", GPU_DB_BUSY, UINT64, AVERAGE),
1942 X("GPU-cp-busy", GPU_CP_BUSY, UINT64, AVERAGE),
1943 X("GPU-cb-busy", GPU_CB_BUSY, UINT64, AVERAGE),
1944
1945 /* SRBM_STATUS2 */
1946 X("GPU-sdma-busy", GPU_SDMA_BUSY, UINT64, AVERAGE),
1947
1948 /* CP_STAT */
1949 X("GPU-pfp-busy", GPU_PFP_BUSY, UINT64, AVERAGE),
1950 X("GPU-meq-busy", GPU_MEQ_BUSY, UINT64, AVERAGE),
1951 X("GPU-me-busy", GPU_ME_BUSY, UINT64, AVERAGE),
1952 X("GPU-surf-sync-busy", GPU_SURF_SYNC_BUSY, UINT64, AVERAGE),
1953 X("GPU-cp-dma-busy", GPU_CP_DMA_BUSY, UINT64, AVERAGE),
1954 X("GPU-scratch-ram-busy", GPU_SCRATCH_RAM_BUSY, UINT64, AVERAGE),
1955 };
1956
1957 #undef X
1958 #undef XG
1959 #undef XFULL
1960
1961 static unsigned si_get_num_queries(struct si_screen *sscreen)
1962 {
1963 /* amdgpu */
1964 if (sscreen->info.drm_major == 3) {
1965 if (sscreen->info.chip_class >= VI)
1966 return ARRAY_SIZE(si_driver_query_list);
1967 else
1968 return ARRAY_SIZE(si_driver_query_list) - 7;
1969 }
1970
1971 /* radeon */
1972 if (sscreen->info.has_read_registers_query) {
1973 if (sscreen->info.chip_class == CIK)
1974 return ARRAY_SIZE(si_driver_query_list) - 6;
1975 else
1976 return ARRAY_SIZE(si_driver_query_list) - 7;
1977 }
1978
1979 return ARRAY_SIZE(si_driver_query_list) - 21;
1980 }
1981
1982 static int si_get_driver_query_info(struct pipe_screen *screen,
1983 unsigned index,
1984 struct pipe_driver_query_info *info)
1985 {
1986 struct si_screen *sscreen = (struct si_screen*)screen;
1987 unsigned num_queries = si_get_num_queries(sscreen);
1988
1989 if (!info) {
1990 unsigned num_perfcounters =
1991 si_get_perfcounter_info(sscreen, 0, NULL);
1992
1993 return num_queries + num_perfcounters;
1994 }
1995
1996 if (index >= num_queries)
1997 return si_get_perfcounter_info(sscreen, index - num_queries, info);
1998
1999 *info = si_driver_query_list[index];
2000
2001 switch (info->query_type) {
2002 case SI_QUERY_REQUESTED_VRAM:
2003 case SI_QUERY_VRAM_USAGE:
2004 case SI_QUERY_MAPPED_VRAM:
2005 info->max_value.u64 = sscreen->info.vram_size;
2006 break;
2007 case SI_QUERY_REQUESTED_GTT:
2008 case SI_QUERY_GTT_USAGE:
2009 case SI_QUERY_MAPPED_GTT:
2010 info->max_value.u64 = sscreen->info.gart_size;
2011 break;
2012 case SI_QUERY_GPU_TEMPERATURE:
2013 info->max_value.u64 = 125;
2014 break;
2015 case SI_QUERY_VRAM_VIS_USAGE:
2016 info->max_value.u64 = sscreen->info.vram_vis_size;
2017 break;
2018 }
2019
2020 if (info->group_id != ~(unsigned)0 && sscreen->perfcounters)
2021 info->group_id += sscreen->perfcounters->num_groups;
2022
2023 return 1;
2024 }
2025
2026 /* Note: Unfortunately, GPUPerfStudio hardcodes the order of hardware
2027 * performance counter groups, so be careful when changing this and related
2028 * functions.
2029 */
2030 static int si_get_driver_query_group_info(struct pipe_screen *screen,
2031 unsigned index,
2032 struct pipe_driver_query_group_info *info)
2033 {
2034 struct si_screen *sscreen = (struct si_screen *)screen;
2035 unsigned num_pc_groups = 0;
2036
2037 if (sscreen->perfcounters)
2038 num_pc_groups = sscreen->perfcounters->num_groups;
2039
2040 if (!info)
2041 return num_pc_groups + SI_NUM_SW_QUERY_GROUPS;
2042
2043 if (index < num_pc_groups)
2044 return si_get_perfcounter_group_info(sscreen, index, info);
2045
2046 index -= num_pc_groups;
2047 if (index >= SI_NUM_SW_QUERY_GROUPS)
2048 return 0;
2049
2050 info->name = "GPIN";
2051 info->max_active_queries = 5;
2052 info->num_queries = 5;
2053 return 1;
2054 }
2055
2056 void si_init_query_functions(struct si_context *sctx)
2057 {
2058 sctx->b.create_query = si_create_query;
2059 sctx->b.create_batch_query = si_create_batch_query;
2060 sctx->b.destroy_query = si_destroy_query;
2061 sctx->b.begin_query = si_begin_query;
2062 sctx->b.end_query = si_end_query;
2063 sctx->b.get_query_result = si_get_query_result;
2064 sctx->b.get_query_result_resource = si_get_query_result_resource;
2065 sctx->atoms.s.render_cond.emit = si_emit_query_predication;
2066
2067 if (((struct si_screen*)sctx->b.screen)->info.num_render_backends > 0)
2068 sctx->b.render_condition = si_render_condition;
2069
2070 LIST_INITHEAD(&sctx->active_queries);
2071 }
2072
2073 void si_init_screen_query_functions(struct si_screen *sscreen)
2074 {
2075 sscreen->b.get_driver_query_info = si_get_driver_query_info;
2076 sscreen->b.get_driver_query_group_info = si_get_driver_query_group_info;
2077 }