projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: move r600_query.c/h files to si_query.c/h
[mesa.git] / src / gallium / drivers / radeonsi / si_query.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2014 Marek Olšák <marek.olsak@amd.com>
4 * Copyright 2018 Advanced Micro Devices, Inc.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * on the rights to use, copy, modify, merge, publish, distribute, sub
11 * license, and/or sell copies of the Software, and to permit persons to whom
12 * the Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27 #include "si_pipe.h"
28 #include "si_query.h"
29 #include "util/u_memory.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/os_time.h"
32 #include "tgsi/tgsi_text.h"
33 #include "amd/common/sid.h"
34
35 #define SI_MAX_STREAMS 4
36
37 struct si_hw_query_params {
38 unsigned start_offset;
39 unsigned end_offset;
40 unsigned fence_offset;
41 unsigned pair_stride;
42 unsigned pair_count;
43 };
44
45 /* Queries without buffer handling or suspend/resume. */
46 struct si_query_sw {
47 struct si_query b;
48
49 uint64_t begin_result;
50 uint64_t end_result;
51
52 uint64_t begin_time;
53 uint64_t end_time;
54
55 /* Fence for GPU_FINISHED. */
56 struct pipe_fence_handle *fence;
57 };
58
59 static void si_query_sw_destroy(struct si_screen *sscreen,
60 struct si_query *rquery)
61 {
62 struct si_query_sw *query = (struct si_query_sw *)rquery;
63
64 sscreen->b.fence_reference(&sscreen->b, &query->fence, NULL);
65 FREE(query);
66 }
67
68 static enum radeon_value_id winsys_id_from_type(unsigned type)
69 {
70 switch (type) {
71 case SI_QUERY_REQUESTED_VRAM: return RADEON_REQUESTED_VRAM_MEMORY;
72 case SI_QUERY_REQUESTED_GTT: return RADEON_REQUESTED_GTT_MEMORY;
73 case SI_QUERY_MAPPED_VRAM: return RADEON_MAPPED_VRAM;
74 case SI_QUERY_MAPPED_GTT: return RADEON_MAPPED_GTT;
75 case SI_QUERY_BUFFER_WAIT_TIME: return RADEON_BUFFER_WAIT_TIME_NS;
76 case SI_QUERY_NUM_MAPPED_BUFFERS: return RADEON_NUM_MAPPED_BUFFERS;
77 case SI_QUERY_NUM_GFX_IBS: return RADEON_NUM_GFX_IBS;
78 case SI_QUERY_NUM_SDMA_IBS: return RADEON_NUM_SDMA_IBS;
79 case SI_QUERY_GFX_BO_LIST_SIZE: return RADEON_GFX_BO_LIST_COUNTER;
80 case SI_QUERY_GFX_IB_SIZE: return RADEON_GFX_IB_SIZE_COUNTER;
81 case SI_QUERY_NUM_BYTES_MOVED: return RADEON_NUM_BYTES_MOVED;
82 case SI_QUERY_NUM_EVICTIONS: return RADEON_NUM_EVICTIONS;
83 case SI_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: return RADEON_NUM_VRAM_CPU_PAGE_FAULTS;
84 case SI_QUERY_VRAM_USAGE: return RADEON_VRAM_USAGE;
85 case SI_QUERY_VRAM_VIS_USAGE: return RADEON_VRAM_VIS_USAGE;
86 case SI_QUERY_GTT_USAGE: return RADEON_GTT_USAGE;
87 case SI_QUERY_GPU_TEMPERATURE: return RADEON_GPU_TEMPERATURE;
88 case SI_QUERY_CURRENT_GPU_SCLK: return RADEON_CURRENT_SCLK;
89 case SI_QUERY_CURRENT_GPU_MCLK: return RADEON_CURRENT_MCLK;
90 case SI_QUERY_CS_THREAD_BUSY: return RADEON_CS_THREAD_TIME;
91 default: unreachable("query type does not correspond to winsys id");
92 }
93 }
94
95 static bool si_query_sw_begin(struct si_context *sctx,
96 struct si_query *rquery)
97 {
98 struct si_query_sw *query = (struct si_query_sw *)rquery;
99 enum radeon_value_id ws_id;
100
101 switch(query->b.type) {
102 case PIPE_QUERY_TIMESTAMP_DISJOINT:
103 case PIPE_QUERY_GPU_FINISHED:
104 break;
105 case SI_QUERY_DRAW_CALLS:
106 query->begin_result = sctx->b.num_draw_calls;
107 break;
108 case SI_QUERY_DECOMPRESS_CALLS:
109 query->begin_result = sctx->b.num_decompress_calls;
110 break;
111 case SI_QUERY_MRT_DRAW_CALLS:
112 query->begin_result = sctx->b.num_mrt_draw_calls;
113 break;
114 case SI_QUERY_PRIM_RESTART_CALLS:
115 query->begin_result = sctx->b.num_prim_restart_calls;
116 break;
117 case SI_QUERY_SPILL_DRAW_CALLS:
118 query->begin_result = sctx->b.num_spill_draw_calls;
119 break;
120 case SI_QUERY_COMPUTE_CALLS:
121 query->begin_result = sctx->b.num_compute_calls;
122 break;
123 case SI_QUERY_SPILL_COMPUTE_CALLS:
124 query->begin_result = sctx->b.num_spill_compute_calls;
125 break;
126 case SI_QUERY_DMA_CALLS:
127 query->begin_result = sctx->b.num_dma_calls;
128 break;
129 case SI_QUERY_CP_DMA_CALLS:
130 query->begin_result = sctx->b.num_cp_dma_calls;
131 break;
132 case SI_QUERY_NUM_VS_FLUSHES:
133 query->begin_result = sctx->b.num_vs_flushes;
134 break;
135 case SI_QUERY_NUM_PS_FLUSHES:
136 query->begin_result = sctx->b.num_ps_flushes;
137 break;
138 case SI_QUERY_NUM_CS_FLUSHES:
139 query->begin_result = sctx->b.num_cs_flushes;
140 break;
141 case SI_QUERY_NUM_CB_CACHE_FLUSHES:
142 query->begin_result = sctx->b.num_cb_cache_flushes;
143 break;
144 case SI_QUERY_NUM_DB_CACHE_FLUSHES:
145 query->begin_result = sctx->b.num_db_cache_flushes;
146 break;
147 case SI_QUERY_NUM_L2_INVALIDATES:
148 query->begin_result = sctx->b.num_L2_invalidates;
149 break;
150 case SI_QUERY_NUM_L2_WRITEBACKS:
151 query->begin_result = sctx->b.num_L2_writebacks;
152 break;
153 case SI_QUERY_NUM_RESIDENT_HANDLES:
154 query->begin_result = sctx->b.num_resident_handles;
155 break;
156 case SI_QUERY_TC_OFFLOADED_SLOTS:
157 query->begin_result = sctx->b.tc ? sctx->b.tc->num_offloaded_slots : 0;
158 break;
159 case SI_QUERY_TC_DIRECT_SLOTS:
160 query->begin_result = sctx->b.tc ? sctx->b.tc->num_direct_slots : 0;
161 break;
162 case SI_QUERY_TC_NUM_SYNCS:
163 query->begin_result = sctx->b.tc ? sctx->b.tc->num_syncs : 0;
164 break;
165 case SI_QUERY_REQUESTED_VRAM:
166 case SI_QUERY_REQUESTED_GTT:
167 case SI_QUERY_MAPPED_VRAM:
168 case SI_QUERY_MAPPED_GTT:
169 case SI_QUERY_VRAM_USAGE:
170 case SI_QUERY_VRAM_VIS_USAGE:
171 case SI_QUERY_GTT_USAGE:
172 case SI_QUERY_GPU_TEMPERATURE:
173 case SI_QUERY_CURRENT_GPU_SCLK:
174 case SI_QUERY_CURRENT_GPU_MCLK:
175 case SI_QUERY_BACK_BUFFER_PS_DRAW_RATIO:
176 case SI_QUERY_NUM_MAPPED_BUFFERS:
177 query->begin_result = 0;
178 break;
179 case SI_QUERY_BUFFER_WAIT_TIME:
180 case SI_QUERY_GFX_IB_SIZE:
181 case SI_QUERY_NUM_GFX_IBS:
182 case SI_QUERY_NUM_SDMA_IBS:
183 case SI_QUERY_NUM_BYTES_MOVED:
184 case SI_QUERY_NUM_EVICTIONS:
185 case SI_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: {
186 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
187 query->begin_result = sctx->b.ws->query_value(sctx->b.ws, ws_id);
188 break;
189 }
190 case SI_QUERY_GFX_BO_LIST_SIZE:
191 ws_id = winsys_id_from_type(query->b.type);
192 query->begin_result = sctx->b.ws->query_value(sctx->b.ws, ws_id);
193 query->begin_time = sctx->b.ws->query_value(sctx->b.ws,
194 RADEON_NUM_GFX_IBS);
195 break;
196 case SI_QUERY_CS_THREAD_BUSY:
197 ws_id = winsys_id_from_type(query->b.type);
198 query->begin_result = sctx->b.ws->query_value(sctx->b.ws, ws_id);
199 query->begin_time = os_time_get_nano();
200 break;
201 case SI_QUERY_GALLIUM_THREAD_BUSY:
202 query->begin_result =
203 sctx->b.tc ? util_queue_get_thread_time_nano(&sctx->b.tc->queue, 0) : 0;
204 query->begin_time = os_time_get_nano();
205 break;
206 case SI_QUERY_GPU_LOAD:
207 case SI_QUERY_GPU_SHADERS_BUSY:
208 case SI_QUERY_GPU_TA_BUSY:
209 case SI_QUERY_GPU_GDS_BUSY:
210 case SI_QUERY_GPU_VGT_BUSY:
211 case SI_QUERY_GPU_IA_BUSY:
212 case SI_QUERY_GPU_SX_BUSY:
213 case SI_QUERY_GPU_WD_BUSY:
214 case SI_QUERY_GPU_BCI_BUSY:
215 case SI_QUERY_GPU_SC_BUSY:
216 case SI_QUERY_GPU_PA_BUSY:
217 case SI_QUERY_GPU_DB_BUSY:
218 case SI_QUERY_GPU_CP_BUSY:
219 case SI_QUERY_GPU_CB_BUSY:
220 case SI_QUERY_GPU_SDMA_BUSY:
221 case SI_QUERY_GPU_PFP_BUSY:
222 case SI_QUERY_GPU_MEQ_BUSY:
223 case SI_QUERY_GPU_ME_BUSY:
224 case SI_QUERY_GPU_SURF_SYNC_BUSY:
225 case SI_QUERY_GPU_CP_DMA_BUSY:
226 case SI_QUERY_GPU_SCRATCH_RAM_BUSY:
227 query->begin_result = si_begin_counter(sctx->screen,
228 query->b.type);
229 break;
230 case SI_QUERY_NUM_COMPILATIONS:
231 query->begin_result = p_atomic_read(&sctx->screen->num_compilations);
232 break;
233 case SI_QUERY_NUM_SHADERS_CREATED:
234 query->begin_result = p_atomic_read(&sctx->screen->num_shaders_created);
235 break;
236 case SI_QUERY_NUM_SHADER_CACHE_HITS:
237 query->begin_result =
238 p_atomic_read(&sctx->screen->num_shader_cache_hits);
239 break;
240 case SI_QUERY_GPIN_ASIC_ID:
241 case SI_QUERY_GPIN_NUM_SIMD:
242 case SI_QUERY_GPIN_NUM_RB:
243 case SI_QUERY_GPIN_NUM_SPI:
244 case SI_QUERY_GPIN_NUM_SE:
245 break;
246 default:
247 unreachable("si_query_sw_begin: bad query type");
248 }
249
250 return true;
251 }
252
253 static bool si_query_sw_end(struct si_context *sctx,
254 struct si_query *rquery)
255 {
256 struct si_query_sw *query = (struct si_query_sw *)rquery;
257 enum radeon_value_id ws_id;
258
259 switch(query->b.type) {
260 case PIPE_QUERY_TIMESTAMP_DISJOINT:
261 break;
262 case PIPE_QUERY_GPU_FINISHED:
263 sctx->b.b.flush(&sctx->b.b, &query->fence, PIPE_FLUSH_DEFERRED);
264 break;
265 case SI_QUERY_DRAW_CALLS:
266 query->end_result = sctx->b.num_draw_calls;
267 break;
268 case SI_QUERY_DECOMPRESS_CALLS:
269 query->end_result = sctx->b.num_decompress_calls;
270 break;
271 case SI_QUERY_MRT_DRAW_CALLS:
272 query->end_result = sctx->b.num_mrt_draw_calls;
273 break;
274 case SI_QUERY_PRIM_RESTART_CALLS:
275 query->end_result = sctx->b.num_prim_restart_calls;
276 break;
277 case SI_QUERY_SPILL_DRAW_CALLS:
278 query->end_result = sctx->b.num_spill_draw_calls;
279 break;
280 case SI_QUERY_COMPUTE_CALLS:
281 query->end_result = sctx->b.num_compute_calls;
282 break;
283 case SI_QUERY_SPILL_COMPUTE_CALLS:
284 query->end_result = sctx->b.num_spill_compute_calls;
285 break;
286 case SI_QUERY_DMA_CALLS:
287 query->end_result = sctx->b.num_dma_calls;
288 break;
289 case SI_QUERY_CP_DMA_CALLS:
290 query->end_result = sctx->b.num_cp_dma_calls;
291 break;
292 case SI_QUERY_NUM_VS_FLUSHES:
293 query->end_result = sctx->b.num_vs_flushes;
294 break;
295 case SI_QUERY_NUM_PS_FLUSHES:
296 query->end_result = sctx->b.num_ps_flushes;
297 break;
298 case SI_QUERY_NUM_CS_FLUSHES:
299 query->end_result = sctx->b.num_cs_flushes;
300 break;
301 case SI_QUERY_NUM_CB_CACHE_FLUSHES:
302 query->end_result = sctx->b.num_cb_cache_flushes;
303 break;
304 case SI_QUERY_NUM_DB_CACHE_FLUSHES:
305 query->end_result = sctx->b.num_db_cache_flushes;
306 break;
307 case SI_QUERY_NUM_L2_INVALIDATES:
308 query->end_result = sctx->b.num_L2_invalidates;
309 break;
310 case SI_QUERY_NUM_L2_WRITEBACKS:
311 query->end_result = sctx->b.num_L2_writebacks;
312 break;
313 case SI_QUERY_NUM_RESIDENT_HANDLES:
314 query->end_result = sctx->b.num_resident_handles;
315 break;
316 case SI_QUERY_TC_OFFLOADED_SLOTS:
317 query->end_result = sctx->b.tc ? sctx->b.tc->num_offloaded_slots : 0;
318 break;
319 case SI_QUERY_TC_DIRECT_SLOTS:
320 query->end_result = sctx->b.tc ? sctx->b.tc->num_direct_slots : 0;
321 break;
322 case SI_QUERY_TC_NUM_SYNCS:
323 query->end_result = sctx->b.tc ? sctx->b.tc->num_syncs : 0;
324 break;
325 case SI_QUERY_REQUESTED_VRAM:
326 case SI_QUERY_REQUESTED_GTT:
327 case SI_QUERY_MAPPED_VRAM:
328 case SI_QUERY_MAPPED_GTT:
329 case SI_QUERY_VRAM_USAGE:
330 case SI_QUERY_VRAM_VIS_USAGE:
331 case SI_QUERY_GTT_USAGE:
332 case SI_QUERY_GPU_TEMPERATURE:
333 case SI_QUERY_CURRENT_GPU_SCLK:
334 case SI_QUERY_CURRENT_GPU_MCLK:
335 case SI_QUERY_BUFFER_WAIT_TIME:
336 case SI_QUERY_GFX_IB_SIZE:
337 case SI_QUERY_NUM_MAPPED_BUFFERS:
338 case SI_QUERY_NUM_GFX_IBS:
339 case SI_QUERY_NUM_SDMA_IBS:
340 case SI_QUERY_NUM_BYTES_MOVED:
341 case SI_QUERY_NUM_EVICTIONS:
342 case SI_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: {
343 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
344 query->end_result = sctx->b.ws->query_value(sctx->b.ws, ws_id);
345 break;
346 }
347 case SI_QUERY_GFX_BO_LIST_SIZE:
348 ws_id = winsys_id_from_type(query->b.type);
349 query->end_result = sctx->b.ws->query_value(sctx->b.ws, ws_id);
350 query->end_time = sctx->b.ws->query_value(sctx->b.ws,
351 RADEON_NUM_GFX_IBS);
352 break;
353 case SI_QUERY_CS_THREAD_BUSY:
354 ws_id = winsys_id_from_type(query->b.type);
355 query->end_result = sctx->b.ws->query_value(sctx->b.ws, ws_id);
356 query->end_time = os_time_get_nano();
357 break;
358 case SI_QUERY_GALLIUM_THREAD_BUSY:
359 query->end_result =
360 sctx->b.tc ? util_queue_get_thread_time_nano(&sctx->b.tc->queue, 0) : 0;
361 query->end_time = os_time_get_nano();
362 break;
363 case SI_QUERY_GPU_LOAD:
364 case SI_QUERY_GPU_SHADERS_BUSY:
365 case SI_QUERY_GPU_TA_BUSY:
366 case SI_QUERY_GPU_GDS_BUSY:
367 case SI_QUERY_GPU_VGT_BUSY:
368 case SI_QUERY_GPU_IA_BUSY:
369 case SI_QUERY_GPU_SX_BUSY:
370 case SI_QUERY_GPU_WD_BUSY:
371 case SI_QUERY_GPU_BCI_BUSY:
372 case SI_QUERY_GPU_SC_BUSY:
373 case SI_QUERY_GPU_PA_BUSY:
374 case SI_QUERY_GPU_DB_BUSY:
375 case SI_QUERY_GPU_CP_BUSY:
376 case SI_QUERY_GPU_CB_BUSY:
377 case SI_QUERY_GPU_SDMA_BUSY:
378 case SI_QUERY_GPU_PFP_BUSY:
379 case SI_QUERY_GPU_MEQ_BUSY:
380 case SI_QUERY_GPU_ME_BUSY:
381 case SI_QUERY_GPU_SURF_SYNC_BUSY:
382 case SI_QUERY_GPU_CP_DMA_BUSY:
383 case SI_QUERY_GPU_SCRATCH_RAM_BUSY:
384 query->end_result = si_end_counter(sctx->screen,
385 query->b.type,
386 query->begin_result);
387 query->begin_result = 0;
388 break;
389 case SI_QUERY_NUM_COMPILATIONS:
390 query->end_result = p_atomic_read(&sctx->screen->num_compilations);
391 break;
392 case SI_QUERY_NUM_SHADERS_CREATED:
393 query->end_result = p_atomic_read(&sctx->screen->num_shaders_created);
394 break;
395 case SI_QUERY_BACK_BUFFER_PS_DRAW_RATIO:
396 query->end_result = sctx->b.last_tex_ps_draw_ratio;
397 break;
398 case SI_QUERY_NUM_SHADER_CACHE_HITS:
399 query->end_result =
400 p_atomic_read(&sctx->screen->num_shader_cache_hits);
401 break;
402 case SI_QUERY_GPIN_ASIC_ID:
403 case SI_QUERY_GPIN_NUM_SIMD:
404 case SI_QUERY_GPIN_NUM_RB:
405 case SI_QUERY_GPIN_NUM_SPI:
406 case SI_QUERY_GPIN_NUM_SE:
407 break;
408 default:
409 unreachable("si_query_sw_end: bad query type");
410 }
411
412 return true;
413 }
414
415 static bool si_query_sw_get_result(struct si_context *sctx,
416 struct si_query *rquery,
417 bool wait,
418 union pipe_query_result *result)
419 {
420 struct si_query_sw *query = (struct si_query_sw *)rquery;
421
422 switch (query->b.type) {
423 case PIPE_QUERY_TIMESTAMP_DISJOINT:
424 /* Convert from cycles per millisecond to cycles per second (Hz). */
425 result->timestamp_disjoint.frequency =
426 (uint64_t)sctx->screen->info.clock_crystal_freq * 1000;
427 result->timestamp_disjoint.disjoint = false;
428 return true;
429 case PIPE_QUERY_GPU_FINISHED: {
430 struct pipe_screen *screen = sctx->b.b.screen;
431 struct pipe_context *ctx = rquery->b.flushed ? NULL : &sctx->b.b;
432
433 result->b = screen->fence_finish(screen, ctx, query->fence,
434 wait ? PIPE_TIMEOUT_INFINITE : 0);
435 return result->b;
436 }
437
438 case SI_QUERY_GFX_BO_LIST_SIZE:
439 result->u64 = (query->end_result - query->begin_result) /
440 (query->end_time - query->begin_time);
441 return true;
442 case SI_QUERY_CS_THREAD_BUSY:
443 case SI_QUERY_GALLIUM_THREAD_BUSY:
444 result->u64 = (query->end_result - query->begin_result) * 100 /
445 (query->end_time - query->begin_time);
446 return true;
447 case SI_QUERY_GPIN_ASIC_ID:
448 result->u32 = 0;
449 return true;
450 case SI_QUERY_GPIN_NUM_SIMD:
451 result->u32 = sctx->screen->info.num_good_compute_units;
452 return true;
453 case SI_QUERY_GPIN_NUM_RB:
454 result->u32 = sctx->screen->info.num_render_backends;
455 return true;
456 case SI_QUERY_GPIN_NUM_SPI:
457 result->u32 = 1; /* all supported chips have one SPI per SE */
458 return true;
459 case SI_QUERY_GPIN_NUM_SE:
460 result->u32 = sctx->screen->info.max_se;
461 return true;
462 }
463
464 result->u64 = query->end_result - query->begin_result;
465
466 switch (query->b.type) {
467 case SI_QUERY_BUFFER_WAIT_TIME:
468 case SI_QUERY_GPU_TEMPERATURE:
469 result->u64 /= 1000;
470 break;
471 case SI_QUERY_CURRENT_GPU_SCLK:
472 case SI_QUERY_CURRENT_GPU_MCLK:
473 result->u64 *= 1000000;
474 break;
475 }
476
477 return true;
478 }
479
480
481 static struct si_query_ops sw_query_ops = {
482 .destroy = si_query_sw_destroy,
483 .begin = si_query_sw_begin,
484 .end = si_query_sw_end,
485 .get_result = si_query_sw_get_result,
486 .get_result_resource = NULL
487 };
488
489 static struct pipe_query *si_query_sw_create(unsigned query_type)
490 {
491 struct si_query_sw *query;
492
493 query = CALLOC_STRUCT(si_query_sw);
494 if (!query)
495 return NULL;
496
497 query->b.type = query_type;
498 query->b.ops = &sw_query_ops;
499
500 return (struct pipe_query *)query;
501 }
502
503 void si_query_hw_destroy(struct si_screen *sscreen,
504 struct si_query *rquery)
505 {
506 struct si_query_hw *query = (struct si_query_hw *)rquery;
507 struct si_query_buffer *prev = query->buffer.previous;
508
509 /* Release all query buffers. */
510 while (prev) {
511 struct si_query_buffer *qbuf = prev;
512 prev = prev->previous;
513 r600_resource_reference(&qbuf->buf, NULL);
514 FREE(qbuf);
515 }
516
517 r600_resource_reference(&query->buffer.buf, NULL);
518 r600_resource_reference(&query->workaround_buf, NULL);
519 FREE(rquery);
520 }
521
522 static struct r600_resource *si_new_query_buffer(struct si_screen *sscreen,
523 struct si_query_hw *query)
524 {
525 unsigned buf_size = MAX2(query->result_size,
526 sscreen->info.min_alloc_size);
527
528 /* Queries are normally read by the CPU after
529 * being written by the gpu, hence staging is probably a good
530 * usage pattern.
531 */
532 struct r600_resource *buf = (struct r600_resource*)
533 pipe_buffer_create(&sscreen->b, 0,
534 PIPE_USAGE_STAGING, buf_size);
535 if (!buf)
536 return NULL;
537
538 if (!query->ops->prepare_buffer(sscreen, query, buf)) {
539 r600_resource_reference(&buf, NULL);
540 return NULL;
541 }
542
543 return buf;
544 }
545
546 static bool si_query_hw_prepare_buffer(struct si_screen *sscreen,
547 struct si_query_hw *query,
548 struct r600_resource *buffer)
549 {
550 /* Callers ensure that the buffer is currently unused by the GPU. */
551 uint32_t *results = sscreen->ws->buffer_map(buffer->buf, NULL,
552 PIPE_TRANSFER_WRITE |
553 PIPE_TRANSFER_UNSYNCHRONIZED);
554 if (!results)
555 return false;
556
557 memset(results, 0, buffer->b.b.width0);
558
559 if (query->b.type == PIPE_QUERY_OCCLUSION_COUNTER ||
560 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE ||
561 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
562 unsigned max_rbs = sscreen->info.num_render_backends;
563 unsigned enabled_rb_mask = sscreen->info.enabled_rb_mask;
564 unsigned num_results;
565 unsigned i, j;
566
567 /* Set top bits for unused backends. */
568 num_results = buffer->b.b.width0 / query->result_size;
569 for (j = 0; j < num_results; j++) {
570 for (i = 0; i < max_rbs; i++) {
571 if (!(enabled_rb_mask & (1<<i))) {
572 results[(i * 4)+1] = 0x80000000;
573 results[(i * 4)+3] = 0x80000000;
574 }
575 }
576 results += 4 * max_rbs;
577 }
578 }
579
580 return true;
581 }
582
583 static void si_query_hw_get_result_resource(struct si_context *sctx,
584 struct si_query *rquery,
585 bool wait,
586 enum pipe_query_value_type result_type,
587 int index,
588 struct pipe_resource *resource,
589 unsigned offset);
590
591 static struct si_query_ops query_hw_ops = {
592 .destroy = si_query_hw_destroy,
593 .begin = si_query_hw_begin,
594 .end = si_query_hw_end,
595 .get_result = si_query_hw_get_result,
596 .get_result_resource = si_query_hw_get_result_resource,
597 };
598
599 static void si_query_hw_do_emit_start(struct si_context *sctx,
600 struct si_query_hw *query,
601 struct r600_resource *buffer,
602 uint64_t va);
603 static void si_query_hw_do_emit_stop(struct si_context *sctx,
604 struct si_query_hw *query,
605 struct r600_resource *buffer,
606 uint64_t va);
607 static void si_query_hw_add_result(struct si_screen *sscreen,
608 struct si_query_hw *, void *buffer,
609 union pipe_query_result *result);
610 static void si_query_hw_clear_result(struct si_query_hw *,
611 union pipe_query_result *);
612
613 static struct si_query_hw_ops query_hw_default_hw_ops = {
614 .prepare_buffer = si_query_hw_prepare_buffer,
615 .emit_start = si_query_hw_do_emit_start,
616 .emit_stop = si_query_hw_do_emit_stop,
617 .clear_result = si_query_hw_clear_result,
618 .add_result = si_query_hw_add_result,
619 };
620
621 bool si_query_hw_init(struct si_screen *sscreen,
622 struct si_query_hw *query)
623 {
624 query->buffer.buf = si_new_query_buffer(sscreen, query);
625 if (!query->buffer.buf)
626 return false;
627
628 return true;
629 }
630
631 static struct pipe_query *si_query_hw_create(struct si_screen *sscreen,
632 unsigned query_type,
633 unsigned index)
634 {
635 struct si_query_hw *query = CALLOC_STRUCT(si_query_hw);
636 if (!query)
637 return NULL;
638
639 query->b.type = query_type;
640 query->b.ops = &query_hw_ops;
641 query->ops = &query_hw_default_hw_ops;
642
643 switch (query_type) {
644 case PIPE_QUERY_OCCLUSION_COUNTER:
645 case PIPE_QUERY_OCCLUSION_PREDICATE:
646 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
647 query->result_size = 16 * sscreen->info.num_render_backends;
648 query->result_size += 16; /* for the fence + alignment */
649 query->num_cs_dw_end = 6 + si_gfx_write_fence_dwords(sscreen);
650 break;
651 case PIPE_QUERY_TIME_ELAPSED:
652 query->result_size = 24;
653 query->num_cs_dw_end = 8 + si_gfx_write_fence_dwords(sscreen);
654 break;
655 case PIPE_QUERY_TIMESTAMP:
656 query->result_size = 16;
657 query->num_cs_dw_end = 8 + si_gfx_write_fence_dwords(sscreen);
658 query->flags = SI_QUERY_HW_FLAG_NO_START;
659 break;
660 case PIPE_QUERY_PRIMITIVES_EMITTED:
661 case PIPE_QUERY_PRIMITIVES_GENERATED:
662 case PIPE_QUERY_SO_STATISTICS:
663 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
664 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
665 query->result_size = 32;
666 query->num_cs_dw_end = 6;
667 query->stream = index;
668 break;
669 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
670 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
671 query->result_size = 32 * SI_MAX_STREAMS;
672 query->num_cs_dw_end = 6 * SI_MAX_STREAMS;
673 break;
674 case PIPE_QUERY_PIPELINE_STATISTICS:
675 /* 11 values on GCN. */
676 query->result_size = 11 * 16;
677 query->result_size += 8; /* for the fence + alignment */
678 query->num_cs_dw_end = 6 + si_gfx_write_fence_dwords(sscreen);
679 break;
680 default:
681 assert(0);
682 FREE(query);
683 return NULL;
684 }
685
686 if (!si_query_hw_init(sscreen, query)) {
687 FREE(query);
688 return NULL;
689 }
690
691 return (struct pipe_query *)query;
692 }
693
694 static void si_update_occlusion_query_state(struct si_context *sctx,
695 unsigned type, int diff)
696 {
697 if (type == PIPE_QUERY_OCCLUSION_COUNTER ||
698 type == PIPE_QUERY_OCCLUSION_PREDICATE ||
699 type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
700 bool old_enable = sctx->b.num_occlusion_queries != 0;
701 bool old_perfect_enable =
702 sctx->b.num_perfect_occlusion_queries != 0;
703 bool enable, perfect_enable;
704
705 sctx->b.num_occlusion_queries += diff;
706 assert(sctx->b.num_occlusion_queries >= 0);
707
708 if (type != PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
709 sctx->b.num_perfect_occlusion_queries += diff;
710 assert(sctx->b.num_perfect_occlusion_queries >= 0);
711 }
712
713 enable = sctx->b.num_occlusion_queries != 0;
714 perfect_enable = sctx->b.num_perfect_occlusion_queries != 0;
715
716 if (enable != old_enable || perfect_enable != old_perfect_enable) {
717 si_set_occlusion_query_state(sctx, old_perfect_enable);
718 }
719 }
720 }
721
722 static unsigned event_type_for_stream(unsigned stream)
723 {
724 switch (stream) {
725 default:
726 case 0: return V_028A90_SAMPLE_STREAMOUTSTATS;
727 case 1: return V_028A90_SAMPLE_STREAMOUTSTATS1;
728 case 2: return V_028A90_SAMPLE_STREAMOUTSTATS2;
729 case 3: return V_028A90_SAMPLE_STREAMOUTSTATS3;
730 }
731 }
732
733 static void emit_sample_streamout(struct radeon_winsys_cs *cs, uint64_t va,
734 unsigned stream)
735 {
736 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
737 radeon_emit(cs, EVENT_TYPE(event_type_for_stream(stream)) | EVENT_INDEX(3));
738 radeon_emit(cs, va);
739 radeon_emit(cs, va >> 32);
740 }
741
742 static void si_query_hw_do_emit_start(struct si_context *sctx,
743 struct si_query_hw *query,
744 struct r600_resource *buffer,
745 uint64_t va)
746 {
747 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
748
749 switch (query->b.type) {
750 case PIPE_QUERY_OCCLUSION_COUNTER:
751 case PIPE_QUERY_OCCLUSION_PREDICATE:
752 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
753 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
754 radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
755 radeon_emit(cs, va);
756 radeon_emit(cs, va >> 32);
757 break;
758 case PIPE_QUERY_PRIMITIVES_EMITTED:
759 case PIPE_QUERY_PRIMITIVES_GENERATED:
760 case PIPE_QUERY_SO_STATISTICS:
761 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
762 emit_sample_streamout(cs, va, query->stream);
763 break;
764 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
765 for (unsigned stream = 0; stream < SI_MAX_STREAMS; ++stream)
766 emit_sample_streamout(cs, va + 32 * stream, stream);
767 break;
768 case PIPE_QUERY_TIME_ELAPSED:
769 /* Write the timestamp from the CP not waiting for
770 * outstanding draws (top-of-pipe).
771 */
772 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
773 radeon_emit(cs, COPY_DATA_COUNT_SEL |
774 COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
775 COPY_DATA_DST_SEL(COPY_DATA_MEM_ASYNC));
776 radeon_emit(cs, 0);
777 radeon_emit(cs, 0);
778 radeon_emit(cs, va);
779 radeon_emit(cs, va >> 32);
780 break;
781 case PIPE_QUERY_PIPELINE_STATISTICS:
782 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
783 radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
784 radeon_emit(cs, va);
785 radeon_emit(cs, va >> 32);
786 break;
787 default:
788 assert(0);
789 }
790 radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs, query->buffer.buf, RADEON_USAGE_WRITE,
791 RADEON_PRIO_QUERY);
792 }
793
794 static void si_query_hw_emit_start(struct si_context *sctx,
795 struct si_query_hw *query)
796 {
797 uint64_t va;
798
799 if (!query->buffer.buf)
800 return; // previous buffer allocation failure
801
802 si_update_occlusion_query_state(sctx, query->b.type, 1);
803 si_update_prims_generated_query_state(sctx, query->b.type, 1);
804
805 si_need_gfx_cs_space(sctx);
806
807 /* Get a new query buffer if needed. */
808 if (query->buffer.results_end + query->result_size > query->buffer.buf->b.b.width0) {
809 struct si_query_buffer *qbuf = MALLOC_STRUCT(si_query_buffer);
810 *qbuf = query->buffer;
811 query->buffer.results_end = 0;
812 query->buffer.previous = qbuf;
813 query->buffer.buf = si_new_query_buffer(sctx->screen, query);
814 if (!query->buffer.buf)
815 return;
816 }
817
818 /* emit begin query */
819 va = query->buffer.buf->gpu_address + query->buffer.results_end;
820
821 query->ops->emit_start(sctx, query, query->buffer.buf, va);
822
823 sctx->b.num_cs_dw_queries_suspend += query->num_cs_dw_end;
824 }
825
826 static void si_query_hw_do_emit_stop(struct si_context *sctx,
827 struct si_query_hw *query,
828 struct r600_resource *buffer,
829 uint64_t va)
830 {
831 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
832 uint64_t fence_va = 0;
833
834 switch (query->b.type) {
835 case PIPE_QUERY_OCCLUSION_COUNTER:
836 case PIPE_QUERY_OCCLUSION_PREDICATE:
837 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
838 va += 8;
839 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
840 radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
841 radeon_emit(cs, va);
842 radeon_emit(cs, va >> 32);
843
844 fence_va = va + sctx->screen->info.num_render_backends * 16 - 8;
845 break;
846 case PIPE_QUERY_PRIMITIVES_EMITTED:
847 case PIPE_QUERY_PRIMITIVES_GENERATED:
848 case PIPE_QUERY_SO_STATISTICS:
849 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
850 va += 16;
851 emit_sample_streamout(cs, va, query->stream);
852 break;
853 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
854 va += 16;
855 for (unsigned stream = 0; stream < SI_MAX_STREAMS; ++stream)
856 emit_sample_streamout(cs, va + 32 * stream, stream);
857 break;
858 case PIPE_QUERY_TIME_ELAPSED:
859 va += 8;
860 /* fall through */
861 case PIPE_QUERY_TIMESTAMP:
862 si_gfx_write_event_eop(sctx, V_028A90_BOTTOM_OF_PIPE_TS,
863 0, EOP_DATA_SEL_TIMESTAMP, NULL, va,
864 0, query->b.type);
865 fence_va = va + 8;
866 break;
867 case PIPE_QUERY_PIPELINE_STATISTICS: {
868 unsigned sample_size = (query->result_size - 8) / 2;
869
870 va += sample_size;
871 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
872 radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
873 radeon_emit(cs, va);
874 radeon_emit(cs, va >> 32);
875
876 fence_va = va + sample_size;
877 break;
878 }
879 default:
880 assert(0);
881 }
882 radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs, query->buffer.buf, RADEON_USAGE_WRITE,
883 RADEON_PRIO_QUERY);
884
885 if (fence_va)
886 si_gfx_write_event_eop(sctx, V_028A90_BOTTOM_OF_PIPE_TS, 0,
887 EOP_DATA_SEL_VALUE_32BIT,
888 query->buffer.buf, fence_va, 0x80000000,
889 query->b.type);
890 }
891
892 static void si_query_hw_emit_stop(struct si_context *sctx,
893 struct si_query_hw *query)
894 {
895 uint64_t va;
896
897 if (!query->buffer.buf)
898 return; // previous buffer allocation failure
899
900 /* The queries which need begin already called this in begin_query. */
901 if (query->flags & SI_QUERY_HW_FLAG_NO_START)
902 si_need_gfx_cs_space(sctx);
903
904 /* emit end query */
905 va = query->buffer.buf->gpu_address + query->buffer.results_end;
906
907 query->ops->emit_stop(sctx, query, query->buffer.buf, va);
908
909 query->buffer.results_end += query->result_size;
910
911 if (!(query->flags & SI_QUERY_HW_FLAG_NO_START))
912 sctx->b.num_cs_dw_queries_suspend -= query->num_cs_dw_end;
913
914 si_update_occlusion_query_state(sctx, query->b.type, -1);
915 si_update_prims_generated_query_state(sctx, query->b.type, -1);
916 }
917
918 static void emit_set_predicate(struct si_context *ctx,
919 struct r600_resource *buf, uint64_t va,
920 uint32_t op)
921 {
922 struct radeon_winsys_cs *cs = ctx->b.gfx_cs;
923
924 if (ctx->b.chip_class >= GFX9) {
925 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
926 radeon_emit(cs, op);
927 radeon_emit(cs, va);
928 radeon_emit(cs, va >> 32);
929 } else {
930 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
931 radeon_emit(cs, va);
932 radeon_emit(cs, op | ((va >> 32) & 0xFF));
933 }
934 radeon_add_to_buffer_list(ctx, ctx->b.gfx_cs, buf, RADEON_USAGE_READ,
935 RADEON_PRIO_QUERY);
936 }
937
938 static void si_emit_query_predication(struct si_context *ctx,
939 struct r600_atom *atom)
940 {
941 struct si_query_hw *query = (struct si_query_hw *)ctx->b.render_cond;
942 struct si_query_buffer *qbuf;
943 uint32_t op;
944 bool flag_wait, invert;
945
946 if (!query)
947 return;
948
949 invert = ctx->b.render_cond_invert;
950 flag_wait = ctx->b.render_cond_mode == PIPE_RENDER_COND_WAIT ||
951 ctx->b.render_cond_mode == PIPE_RENDER_COND_BY_REGION_WAIT;
952
953 if (query->workaround_buf) {
954 op = PRED_OP(PREDICATION_OP_BOOL64);
955 } else {
956 switch (query->b.type) {
957 case PIPE_QUERY_OCCLUSION_COUNTER:
958 case PIPE_QUERY_OCCLUSION_PREDICATE:
959 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
960 op = PRED_OP(PREDICATION_OP_ZPASS);
961 break;
962 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
963 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
964 op = PRED_OP(PREDICATION_OP_PRIMCOUNT);
965 invert = !invert;
966 break;
967 default:
968 assert(0);
969 return;
970 }
971 }
972
973 /* if true then invert, see GL_ARB_conditional_render_inverted */
974 if (invert)
975 op |= PREDICATION_DRAW_NOT_VISIBLE; /* Draw if not visible or overflow */
976 else
977 op |= PREDICATION_DRAW_VISIBLE; /* Draw if visible or no overflow */
978
979 /* Use the value written by compute shader as a workaround. Note that
980 * the wait flag does not apply in this predication mode.
981 *
982 * The shader outputs the result value to L2. Workarounds only affect VI
983 * and later, where the CP reads data from L2, so we don't need an
984 * additional flush.
985 */
986 if (query->workaround_buf) {
987 uint64_t va = query->workaround_buf->gpu_address + query->workaround_offset;
988 emit_set_predicate(ctx, query->workaround_buf, va, op);
989 return;
990 }
991
992 op |= flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW;
993
994 /* emit predicate packets for all data blocks */
995 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
996 unsigned results_base = 0;
997 uint64_t va_base = qbuf->buf->gpu_address;
998
999 while (results_base < qbuf->results_end) {
1000 uint64_t va = va_base + results_base;
1001
1002 if (query->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE) {
1003 for (unsigned stream = 0; stream < SI_MAX_STREAMS; ++stream) {
1004 emit_set_predicate(ctx, qbuf->buf, va + 32 * stream, op);
1005
1006 /* set CONTINUE bit for all packets except the first */
1007 op |= PREDICATION_CONTINUE;
1008 }
1009 } else {
1010 emit_set_predicate(ctx, qbuf->buf, va, op);
1011 op |= PREDICATION_CONTINUE;
1012 }
1013
1014 results_base += query->result_size;
1015 }
1016 }
1017 }
1018
1019 static struct pipe_query *si_create_query(struct pipe_context *ctx, unsigned query_type, unsigned index)
1020 {
1021 struct si_screen *sscreen =
1022 (struct si_screen *)ctx->screen;
1023
1024 if (query_type == PIPE_QUERY_TIMESTAMP_DISJOINT ||
1025 query_type == PIPE_QUERY_GPU_FINISHED ||
1026 query_type >= PIPE_QUERY_DRIVER_SPECIFIC)
1027 return si_query_sw_create(query_type);
1028
1029 return si_query_hw_create(sscreen, query_type, index);
1030 }
1031
1032 static void si_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
1033 {
1034 struct si_context *sctx = (struct si_context *)ctx;
1035 struct si_query *rquery = (struct si_query *)query;
1036
1037 rquery->ops->destroy(sctx->screen, rquery);
1038 }
1039
1040 static boolean si_begin_query(struct pipe_context *ctx,
1041 struct pipe_query *query)
1042 {
1043 struct si_context *sctx = (struct si_context *)ctx;
1044 struct si_query *rquery = (struct si_query *)query;
1045
1046 return rquery->ops->begin(sctx, rquery);
1047 }
1048
1049 void si_query_hw_reset_buffers(struct si_context *sctx,
1050 struct si_query_hw *query)
1051 {
1052 struct si_query_buffer *prev = query->buffer.previous;
1053
1054 /* Discard the old query buffers. */
1055 while (prev) {
1056 struct si_query_buffer *qbuf = prev;
1057 prev = prev->previous;
1058 r600_resource_reference(&qbuf->buf, NULL);
1059 FREE(qbuf);
1060 }
1061
1062 query->buffer.results_end = 0;
1063 query->buffer.previous = NULL;
1064
1065 /* Obtain a new buffer if the current one can't be mapped without a stall. */
1066 if (si_rings_is_buffer_referenced(sctx, query->buffer.buf->buf, RADEON_USAGE_READWRITE) ||
1067 !sctx->b.ws->buffer_wait(query->buffer.buf->buf, 0, RADEON_USAGE_READWRITE)) {
1068 r600_resource_reference(&query->buffer.buf, NULL);
1069 query->buffer.buf = si_new_query_buffer(sctx->screen, query);
1070 } else {
1071 if (!query->ops->prepare_buffer(sctx->screen, query, query->buffer.buf))
1072 r600_resource_reference(&query->buffer.buf, NULL);
1073 }
1074 }
1075
1076 bool si_query_hw_begin(struct si_context *sctx,
1077 struct si_query *rquery)
1078 {
1079 struct si_query_hw *query = (struct si_query_hw *)rquery;
1080
1081 if (query->flags & SI_QUERY_HW_FLAG_NO_START) {
1082 assert(0);
1083 return false;
1084 }
1085
1086 if (!(query->flags & SI_QUERY_HW_FLAG_BEGIN_RESUMES))
1087 si_query_hw_reset_buffers(sctx, query);
1088
1089 r600_resource_reference(&query->workaround_buf, NULL);
1090
1091 si_query_hw_emit_start(sctx, query);
1092 if (!query->buffer.buf)
1093 return false;
1094
1095 LIST_ADDTAIL(&query->list, &sctx->b.active_queries);
1096 return true;
1097 }
1098
1099 static bool si_end_query(struct pipe_context *ctx, struct pipe_query *query)
1100 {
1101 struct si_context *sctx = (struct si_context *)ctx;
1102 struct si_query *rquery = (struct si_query *)query;
1103
1104 return rquery->ops->end(sctx, rquery);
1105 }
1106
1107 bool si_query_hw_end(struct si_context *sctx,
1108 struct si_query *rquery)
1109 {
1110 struct si_query_hw *query = (struct si_query_hw *)rquery;
1111
1112 if (query->flags & SI_QUERY_HW_FLAG_NO_START)
1113 si_query_hw_reset_buffers(sctx, query);
1114
1115 si_query_hw_emit_stop(sctx, query);
1116
1117 if (!(query->flags & SI_QUERY_HW_FLAG_NO_START))
1118 LIST_DELINIT(&query->list);
1119
1120 if (!query->buffer.buf)
1121 return false;
1122
1123 return true;
1124 }
1125
1126 static void si_get_hw_query_params(struct si_context *sctx,
1127 struct si_query_hw *rquery, int index,
1128 struct si_hw_query_params *params)
1129 {
1130 unsigned max_rbs = sctx->screen->info.num_render_backends;
1131
1132 params->pair_stride = 0;
1133 params->pair_count = 1;
1134
1135 switch (rquery->b.type) {
1136 case PIPE_QUERY_OCCLUSION_COUNTER:
1137 case PIPE_QUERY_OCCLUSION_PREDICATE:
1138 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1139 params->start_offset = 0;
1140 params->end_offset = 8;
1141 params->fence_offset = max_rbs * 16;
1142 params->pair_stride = 16;
1143 params->pair_count = max_rbs;
1144 break;
1145 case PIPE_QUERY_TIME_ELAPSED:
1146 params->start_offset = 0;
1147 params->end_offset = 8;
1148 params->fence_offset = 16;
1149 break;
1150 case PIPE_QUERY_TIMESTAMP:
1151 params->start_offset = 0;
1152 params->end_offset = 0;
1153 params->fence_offset = 8;
1154 break;
1155 case PIPE_QUERY_PRIMITIVES_EMITTED:
1156 params->start_offset = 8;
1157 params->end_offset = 24;
1158 params->fence_offset = params->end_offset + 4;
1159 break;
1160 case PIPE_QUERY_PRIMITIVES_GENERATED:
1161 params->start_offset = 0;
1162 params->end_offset = 16;
1163 params->fence_offset = params->end_offset + 4;
1164 break;
1165 case PIPE_QUERY_SO_STATISTICS:
1166 params->start_offset = 8 - index * 8;
1167 params->end_offset = 24 - index * 8;
1168 params->fence_offset = params->end_offset + 4;
1169 break;
1170 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
1171 params->pair_count = SI_MAX_STREAMS;
1172 params->pair_stride = 32;
1173 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1174 params->start_offset = 0;
1175 params->end_offset = 16;
1176
1177 /* We can re-use the high dword of the last 64-bit value as a
1178 * fence: it is initialized as 0, and the high bit is set by
1179 * the write of the streamout stats event.
1180 */
1181 params->fence_offset = rquery->result_size - 4;
1182 break;
1183 case PIPE_QUERY_PIPELINE_STATISTICS:
1184 {
1185 /* Offsets apply to EG+ */
1186 static const unsigned offsets[] = {56, 48, 24, 32, 40, 16, 8, 0, 64, 72, 80};
1187 params->start_offset = offsets[index];
1188 params->end_offset = 88 + offsets[index];
1189 params->fence_offset = 2 * 88;
1190 break;
1191 }
1192 default:
1193 unreachable("si_get_hw_query_params unsupported");
1194 }
1195 }
1196
1197 static unsigned si_query_read_result(void *map, unsigned start_index, unsigned end_index,
1198 bool test_status_bit)
1199 {
1200 uint32_t *current_result = (uint32_t*)map;
1201 uint64_t start, end;
1202
1203 start = (uint64_t)current_result[start_index] |
1204 (uint64_t)current_result[start_index+1] << 32;
1205 end = (uint64_t)current_result[end_index] |
1206 (uint64_t)current_result[end_index+1] << 32;
1207
1208 if (!test_status_bit ||
1209 ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) {
1210 return end - start;
1211 }
1212 return 0;
1213 }
1214
1215 static void si_query_hw_add_result(struct si_screen *sscreen,
1216 struct si_query_hw *query,
1217 void *buffer,
1218 union pipe_query_result *result)
1219 {
1220 unsigned max_rbs = sscreen->info.num_render_backends;
1221
1222 switch (query->b.type) {
1223 case PIPE_QUERY_OCCLUSION_COUNTER: {
1224 for (unsigned i = 0; i < max_rbs; ++i) {
1225 unsigned results_base = i * 16;
1226 result->u64 +=
1227 si_query_read_result(buffer + results_base, 0, 2, true);
1228 }
1229 break;
1230 }
1231 case PIPE_QUERY_OCCLUSION_PREDICATE:
1232 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: {
1233 for (unsigned i = 0; i < max_rbs; ++i) {
1234 unsigned results_base = i * 16;
1235 result->b = result->b ||
1236 si_query_read_result(buffer + results_base, 0, 2, true) != 0;
1237 }
1238 break;
1239 }
1240 case PIPE_QUERY_TIME_ELAPSED:
1241 result->u64 += si_query_read_result(buffer, 0, 2, false);
1242 break;
1243 case PIPE_QUERY_TIMESTAMP:
1244 result->u64 = *(uint64_t*)buffer;
1245 break;
1246 case PIPE_QUERY_PRIMITIVES_EMITTED:
1247 /* SAMPLE_STREAMOUTSTATS stores this structure:
1248 * {
1249 * u64 NumPrimitivesWritten;
1250 * u64 PrimitiveStorageNeeded;
1251 * }
1252 * We only need NumPrimitivesWritten here. */
1253 result->u64 += si_query_read_result(buffer, 2, 6, true);
1254 break;
1255 case PIPE_QUERY_PRIMITIVES_GENERATED:
1256 /* Here we read PrimitiveStorageNeeded. */
1257 result->u64 += si_query_read_result(buffer, 0, 4, true);
1258 break;
1259 case PIPE_QUERY_SO_STATISTICS:
1260 result->so_statistics.num_primitives_written +=
1261 si_query_read_result(buffer, 2, 6, true);
1262 result->so_statistics.primitives_storage_needed +=
1263 si_query_read_result(buffer, 0, 4, true);
1264 break;
1265 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1266 result->b = result->b ||
1267 si_query_read_result(buffer, 2, 6, true) !=
1268 si_query_read_result(buffer, 0, 4, true);
1269 break;
1270 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
1271 for (unsigned stream = 0; stream < SI_MAX_STREAMS; ++stream) {
1272 result->b = result->b ||
1273 si_query_read_result(buffer, 2, 6, true) !=
1274 si_query_read_result(buffer, 0, 4, true);
1275 buffer = (char *)buffer + 32;
1276 }
1277 break;
1278 case PIPE_QUERY_PIPELINE_STATISTICS:
1279 result->pipeline_statistics.ps_invocations +=
1280 si_query_read_result(buffer, 0, 22, false);
1281 result->pipeline_statistics.c_primitives +=
1282 si_query_read_result(buffer, 2, 24, false);
1283 result->pipeline_statistics.c_invocations +=
1284 si_query_read_result(buffer, 4, 26, false);
1285 result->pipeline_statistics.vs_invocations +=
1286 si_query_read_result(buffer, 6, 28, false);
1287 result->pipeline_statistics.gs_invocations +=
1288 si_query_read_result(buffer, 8, 30, false);
1289 result->pipeline_statistics.gs_primitives +=
1290 si_query_read_result(buffer, 10, 32, false);
1291 result->pipeline_statistics.ia_primitives +=
1292 si_query_read_result(buffer, 12, 34, false);
1293 result->pipeline_statistics.ia_vertices +=
1294 si_query_read_result(buffer, 14, 36, false);
1295 result->pipeline_statistics.hs_invocations +=
1296 si_query_read_result(buffer, 16, 38, false);
1297 result->pipeline_statistics.ds_invocations +=
1298 si_query_read_result(buffer, 18, 40, false);
1299 result->pipeline_statistics.cs_invocations +=
1300 si_query_read_result(buffer, 20, 42, false);
1301 #if 0 /* for testing */
1302 printf("Pipeline stats: IA verts=%llu, IA prims=%llu, VS=%llu, HS=%llu, "
1303 "DS=%llu, GS=%llu, GS prims=%llu, Clipper=%llu, "
1304 "Clipper prims=%llu, PS=%llu, CS=%llu\n",
1305 result->pipeline_statistics.ia_vertices,
1306 result->pipeline_statistics.ia_primitives,
1307 result->pipeline_statistics.vs_invocations,
1308 result->pipeline_statistics.hs_invocations,
1309 result->pipeline_statistics.ds_invocations,
1310 result->pipeline_statistics.gs_invocations,
1311 result->pipeline_statistics.gs_primitives,
1312 result->pipeline_statistics.c_invocations,
1313 result->pipeline_statistics.c_primitives,
1314 result->pipeline_statistics.ps_invocations,
1315 result->pipeline_statistics.cs_invocations);
1316 #endif
1317 break;
1318 default:
1319 assert(0);
1320 }
1321 }
1322
1323 static boolean si_get_query_result(struct pipe_context *ctx,
1324 struct pipe_query *query, boolean wait,
1325 union pipe_query_result *result)
1326 {
1327 struct si_context *sctx = (struct si_context *)ctx;
1328 struct si_query *rquery = (struct si_query *)query;
1329
1330 return rquery->ops->get_result(sctx, rquery, wait, result);
1331 }
1332
1333 static void si_get_query_result_resource(struct pipe_context *ctx,
1334 struct pipe_query *query,
1335 boolean wait,
1336 enum pipe_query_value_type result_type,
1337 int index,
1338 struct pipe_resource *resource,
1339 unsigned offset)
1340 {
1341 struct si_context *sctx = (struct si_context *)ctx;
1342 struct si_query *rquery = (struct si_query *)query;
1343
1344 rquery->ops->get_result_resource(sctx, rquery, wait, result_type, index,
1345 resource, offset);
1346 }
1347
1348 static void si_query_hw_clear_result(struct si_query_hw *query,
1349 union pipe_query_result *result)
1350 {
1351 util_query_clear_result(result, query->b.type);
1352 }
1353
1354 bool si_query_hw_get_result(struct si_context *sctx,
1355 struct si_query *rquery,
1356 bool wait, union pipe_query_result *result)
1357 {
1358 struct si_screen *sscreen = sctx->screen;
1359 struct si_query_hw *query = (struct si_query_hw *)rquery;
1360 struct si_query_buffer *qbuf;
1361
1362 query->ops->clear_result(query, result);
1363
1364 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
1365 unsigned usage = PIPE_TRANSFER_READ |
1366 (wait ? 0 : PIPE_TRANSFER_DONTBLOCK);
1367 unsigned results_base = 0;
1368 void *map;
1369
1370 if (rquery->b.flushed)
1371 map = sctx->b.ws->buffer_map(qbuf->buf->buf, NULL, usage);
1372 else
1373 map = si_buffer_map_sync_with_rings(sctx, qbuf->buf, usage);
1374
1375 if (!map)
1376 return false;
1377
1378 while (results_base != qbuf->results_end) {
1379 query->ops->add_result(sscreen, query, map + results_base,
1380 result);
1381 results_base += query->result_size;
1382 }
1383 }
1384
1385 /* Convert the time to expected units. */
1386 if (rquery->type == PIPE_QUERY_TIME_ELAPSED ||
1387 rquery->type == PIPE_QUERY_TIMESTAMP) {
1388 result->u64 = (1000000 * result->u64) / sscreen->info.clock_crystal_freq;
1389 }
1390 return true;
1391 }
1392
1393 /* Create the compute shader that is used to collect the results.
1394 *
1395 * One compute grid with a single thread is launched for every query result
1396 * buffer. The thread (optionally) reads a previous summary buffer, then
1397 * accumulates data from the query result buffer, and writes the result either
1398 * to a summary buffer to be consumed by the next grid invocation or to the
1399 * user-supplied buffer.
1400 *
1401 * Data layout:
1402 *
1403 * CONST
1404 * 0.x = end_offset
1405 * 0.y = result_stride
1406 * 0.z = result_count
1407 * 0.w = bit field:
1408 * 1: read previously accumulated values
1409 * 2: write accumulated values for chaining
1410 * 4: write result available
1411 * 8: convert result to boolean (0/1)
1412 * 16: only read one dword and use that as result
1413 * 32: apply timestamp conversion
1414 * 64: store full 64 bits result
1415 * 128: store signed 32 bits result
1416 * 256: SO_OVERFLOW mode: take the difference of two successive half-pairs
1417 * 1.x = fence_offset
1418 * 1.y = pair_stride
1419 * 1.z = pair_count
1420 *
1421 * BUFFER[0] = query result buffer
1422 * BUFFER[1] = previous summary buffer
1423 * BUFFER[2] = next summary buffer or user-supplied buffer
1424 */
1425 static void si_create_query_result_shader(struct si_context *sctx)
1426 {
1427 /* TEMP[0].xy = accumulated result so far
1428 * TEMP[0].z = result not available
1429 *
1430 * TEMP[1].x = current result index
1431 * TEMP[1].y = current pair index
1432 */
1433 static const char text_tmpl[] =
1434 "COMP\n"
1435 "PROPERTY CS_FIXED_BLOCK_WIDTH 1\n"
1436 "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
1437 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
1438 "DCL BUFFER[0]\n"
1439 "DCL BUFFER[1]\n"
1440 "DCL BUFFER[2]\n"
1441 "DCL CONST[0][0..1]\n"
1442 "DCL TEMP[0..5]\n"
1443 "IMM[0] UINT32 {0, 31, 2147483647, 4294967295}\n"
1444 "IMM[1] UINT32 {1, 2, 4, 8}\n"
1445 "IMM[2] UINT32 {16, 32, 64, 128}\n"
1446 "IMM[3] UINT32 {1000000, 0, %u, 0}\n" /* for timestamp conversion */
1447 "IMM[4] UINT32 {256, 0, 0, 0}\n"
1448
1449 "AND TEMP[5], CONST[0][0].wwww, IMM[2].xxxx\n"
1450 "UIF TEMP[5]\n"
1451 /* Check result availability. */
1452 "LOAD TEMP[1].x, BUFFER[0], CONST[0][1].xxxx\n"
1453 "ISHR TEMP[0].z, TEMP[1].xxxx, IMM[0].yyyy\n"
1454 "MOV TEMP[1], TEMP[0].zzzz\n"
1455 "NOT TEMP[0].z, TEMP[0].zzzz\n"
1456
1457 /* Load result if available. */
1458 "UIF TEMP[1]\n"
1459 "LOAD TEMP[0].xy, BUFFER[0], IMM[0].xxxx\n"
1460 "ENDIF\n"
1461 "ELSE\n"
1462 /* Load previously accumulated result if requested. */
1463 "MOV TEMP[0], IMM[0].xxxx\n"
1464 "AND TEMP[4], CONST[0][0].wwww, IMM[1].xxxx\n"
1465 "UIF TEMP[4]\n"
1466 "LOAD TEMP[0].xyz, BUFFER[1], IMM[0].xxxx\n"
1467 "ENDIF\n"
1468
1469 "MOV TEMP[1].x, IMM[0].xxxx\n"
1470 "BGNLOOP\n"
1471 /* Break if accumulated result so far is not available. */
1472 "UIF TEMP[0].zzzz\n"
1473 "BRK\n"
1474 "ENDIF\n"
1475
1476 /* Break if result_index >= result_count. */
1477 "USGE TEMP[5], TEMP[1].xxxx, CONST[0][0].zzzz\n"
1478 "UIF TEMP[5]\n"
1479 "BRK\n"
1480 "ENDIF\n"
1481
1482 /* Load fence and check result availability */
1483 "UMAD TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy, CONST[0][1].xxxx\n"
1484 "LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n"
1485 "ISHR TEMP[0].z, TEMP[5].xxxx, IMM[0].yyyy\n"
1486 "NOT TEMP[0].z, TEMP[0].zzzz\n"
1487 "UIF TEMP[0].zzzz\n"
1488 "BRK\n"
1489 "ENDIF\n"
1490
1491 "MOV TEMP[1].y, IMM[0].xxxx\n"
1492 "BGNLOOP\n"
1493 /* Load start and end. */
1494 "UMUL TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy\n"
1495 "UMAD TEMP[5].x, TEMP[1].yyyy, CONST[0][1].yyyy, TEMP[5].xxxx\n"
1496 "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
1497
1498 "UADD TEMP[5].y, TEMP[5].xxxx, CONST[0][0].xxxx\n"
1499 "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
1500
1501 "U64ADD TEMP[4].xy, TEMP[3], -TEMP[2]\n"
1502
1503 "AND TEMP[5].z, CONST[0][0].wwww, IMM[4].xxxx\n"
1504 "UIF TEMP[5].zzzz\n"
1505 /* Load second start/end half-pair and
1506 * take the difference
1507 */
1508 "UADD TEMP[5].xy, TEMP[5], IMM[1].wwww\n"
1509 "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
1510 "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
1511
1512 "U64ADD TEMP[3].xy, TEMP[3], -TEMP[2]\n"
1513 "U64ADD TEMP[4].xy, TEMP[4], -TEMP[3]\n"
1514 "ENDIF\n"
1515
1516 "U64ADD TEMP[0].xy, TEMP[0], TEMP[4]\n"
1517
1518 /* Increment pair index */
1519 "UADD TEMP[1].y, TEMP[1].yyyy, IMM[1].xxxx\n"
1520 "USGE TEMP[5], TEMP[1].yyyy, CONST[0][1].zzzz\n"
1521 "UIF TEMP[5]\n"
1522 "BRK\n"
1523 "ENDIF\n"
1524 "ENDLOOP\n"
1525
1526 /* Increment result index */
1527 "UADD TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx\n"
1528 "ENDLOOP\n"
1529 "ENDIF\n"
1530
1531 "AND TEMP[4], CONST[0][0].wwww, IMM[1].yyyy\n"
1532 "UIF TEMP[4]\n"
1533 /* Store accumulated data for chaining. */
1534 "STORE BUFFER[2].xyz, IMM[0].xxxx, TEMP[0]\n"
1535 "ELSE\n"
1536 "AND TEMP[4], CONST[0][0].wwww, IMM[1].zzzz\n"
1537 "UIF TEMP[4]\n"
1538 /* Store result availability. */
1539 "NOT TEMP[0].z, TEMP[0]\n"
1540 "AND TEMP[0].z, TEMP[0].zzzz, IMM[1].xxxx\n"
1541 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].zzzz\n"
1542
1543 "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
1544 "UIF TEMP[4]\n"
1545 "STORE BUFFER[2].y, IMM[0].xxxx, IMM[0].xxxx\n"
1546 "ENDIF\n"
1547 "ELSE\n"
1548 /* Store result if it is available. */
1549 "NOT TEMP[4], TEMP[0].zzzz\n"
1550 "UIF TEMP[4]\n"
1551 /* Apply timestamp conversion */
1552 "AND TEMP[4], CONST[0][0].wwww, IMM[2].yyyy\n"
1553 "UIF TEMP[4]\n"
1554 "U64MUL TEMP[0].xy, TEMP[0], IMM[3].xyxy\n"
1555 "U64DIV TEMP[0].xy, TEMP[0], IMM[3].zwzw\n"
1556 "ENDIF\n"
1557
1558 /* Convert to boolean */
1559 "AND TEMP[4], CONST[0][0].wwww, IMM[1].wwww\n"
1560 "UIF TEMP[4]\n"
1561 "U64SNE TEMP[0].x, TEMP[0].xyxy, IMM[4].zwzw\n"
1562 "AND TEMP[0].x, TEMP[0].xxxx, IMM[1].xxxx\n"
1563 "MOV TEMP[0].y, IMM[0].xxxx\n"
1564 "ENDIF\n"
1565
1566 "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
1567 "UIF TEMP[4]\n"
1568 "STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0].xyxy\n"
1569 "ELSE\n"
1570 /* Clamping */
1571 "UIF TEMP[0].yyyy\n"
1572 "MOV TEMP[0].x, IMM[0].wwww\n"
1573 "ENDIF\n"
1574
1575 "AND TEMP[4], CONST[0][0].wwww, IMM[2].wwww\n"
1576 "UIF TEMP[4]\n"
1577 "UMIN TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz\n"
1578 "ENDIF\n"
1579
1580 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].xxxx\n"
1581 "ENDIF\n"
1582 "ENDIF\n"
1583 "ENDIF\n"
1584 "ENDIF\n"
1585
1586 "END\n";
1587
1588 char text[sizeof(text_tmpl) + 32];
1589 struct tgsi_token tokens[1024];
1590 struct pipe_compute_state state = {};
1591
1592 /* Hard code the frequency into the shader so that the backend can
1593 * use the full range of optimizations for divide-by-constant.
1594 */
1595 snprintf(text, sizeof(text), text_tmpl,
1596 sctx->screen->info.clock_crystal_freq);
1597
1598 if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
1599 assert(false);
1600 return;
1601 }
1602
1603 state.ir_type = PIPE_SHADER_IR_TGSI;
1604 state.prog = tokens;
1605
1606 sctx->b.query_result_shader = sctx->b.b.create_compute_state(&sctx->b.b, &state);
1607 }
1608
1609 static void si_restore_qbo_state(struct si_context *sctx,
1610 struct si_qbo_state *st)
1611 {
1612 sctx->b.b.bind_compute_state(&sctx->b.b, st->saved_compute);
1613
1614 sctx->b.b.set_constant_buffer(&sctx->b.b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1615 pipe_resource_reference(&st->saved_const0.buffer, NULL);
1616
1617 sctx->b.b.set_shader_buffers(&sctx->b.b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1618 for (unsigned i = 0; i < 3; ++i)
1619 pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
1620 }
1621
1622 static void si_query_hw_get_result_resource(struct si_context *sctx,
1623 struct si_query *rquery,
1624 bool wait,
1625 enum pipe_query_value_type result_type,
1626 int index,
1627 struct pipe_resource *resource,
1628 unsigned offset)
1629 {
1630 struct si_query_hw *query = (struct si_query_hw *)rquery;
1631 struct si_query_buffer *qbuf;
1632 struct si_query_buffer *qbuf_prev;
1633 struct pipe_resource *tmp_buffer = NULL;
1634 unsigned tmp_buffer_offset = 0;
1635 struct si_qbo_state saved_state = {};
1636 struct pipe_grid_info grid = {};
1637 struct pipe_constant_buffer constant_buffer = {};
1638 struct pipe_shader_buffer ssbo[3];
1639 struct si_hw_query_params params;
1640 struct {
1641 uint32_t end_offset;
1642 uint32_t result_stride;
1643 uint32_t result_count;
1644 uint32_t config;
1645 uint32_t fence_offset;
1646 uint32_t pair_stride;
1647 uint32_t pair_count;
1648 } consts;
1649
1650 if (!sctx->b.query_result_shader) {
1651 si_create_query_result_shader(sctx);
1652 if (!sctx->b.query_result_shader)
1653 return;
1654 }
1655
1656 if (query->buffer.previous) {
1657 u_suballocator_alloc(sctx->b.allocator_zeroed_memory, 16, 16,
1658 &tmp_buffer_offset, &tmp_buffer);
1659 if (!tmp_buffer)
1660 return;
1661 }
1662
1663 si_save_qbo_state(sctx, &saved_state);
1664
1665 si_get_hw_query_params(sctx, query, index >= 0 ? index : 0, &params);
1666 consts.end_offset = params.end_offset - params.start_offset;
1667 consts.fence_offset = params.fence_offset - params.start_offset;
1668 consts.result_stride = query->result_size;
1669 consts.pair_stride = params.pair_stride;
1670 consts.pair_count = params.pair_count;
1671
1672 constant_buffer.buffer_size = sizeof(consts);
1673 constant_buffer.user_buffer = &consts;
1674
1675 ssbo[1].buffer = tmp_buffer;
1676 ssbo[1].buffer_offset = tmp_buffer_offset;
1677 ssbo[1].buffer_size = 16;
1678
1679 ssbo[2] = ssbo[1];
1680
1681 sctx->b.b.bind_compute_state(&sctx->b.b, sctx->b.query_result_shader);
1682
1683 grid.block[0] = 1;
1684 grid.block[1] = 1;
1685 grid.block[2] = 1;
1686 grid.grid[0] = 1;
1687 grid.grid[1] = 1;
1688 grid.grid[2] = 1;
1689
1690 consts.config = 0;
1691 if (index < 0)
1692 consts.config |= 4;
1693 if (query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE ||
1694 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE)
1695 consts.config |= 8;
1696 else if (query->b.type == PIPE_QUERY_SO_OVERFLOW_PREDICATE ||
1697 query->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE)
1698 consts.config |= 8 | 256;
1699 else if (query->b.type == PIPE_QUERY_TIMESTAMP ||
1700 query->b.type == PIPE_QUERY_TIME_ELAPSED)
1701 consts.config |= 32;
1702
1703 switch (result_type) {
1704 case PIPE_QUERY_TYPE_U64:
1705 case PIPE_QUERY_TYPE_I64:
1706 consts.config |= 64;
1707 break;
1708 case PIPE_QUERY_TYPE_I32:
1709 consts.config |= 128;
1710 break;
1711 case PIPE_QUERY_TYPE_U32:
1712 break;
1713 }
1714
1715 sctx->b.flags |= sctx->screen->barrier_flags.cp_to_L2;
1716
1717 for (qbuf = &query->buffer; qbuf; qbuf = qbuf_prev) {
1718 if (query->b.type != PIPE_QUERY_TIMESTAMP) {
1719 qbuf_prev = qbuf->previous;
1720 consts.result_count = qbuf->results_end / query->result_size;
1721 consts.config &= ~3;
1722 if (qbuf != &query->buffer)
1723 consts.config |= 1;
1724 if (qbuf->previous)
1725 consts.config |= 2;
1726 } else {
1727 /* Only read the last timestamp. */
1728 qbuf_prev = NULL;
1729 consts.result_count = 0;
1730 consts.config |= 16;
1731 params.start_offset += qbuf->results_end - query->result_size;
1732 }
1733
1734 sctx->b.b.set_constant_buffer(&sctx->b.b, PIPE_SHADER_COMPUTE, 0, &constant_buffer);
1735
1736 ssbo[0].buffer = &qbuf->buf->b.b;
1737 ssbo[0].buffer_offset = params.start_offset;
1738 ssbo[0].buffer_size = qbuf->results_end - params.start_offset;
1739
1740 if (!qbuf->previous) {
1741 ssbo[2].buffer = resource;
1742 ssbo[2].buffer_offset = offset;
1743 ssbo[2].buffer_size = 8;
1744
1745 ((struct r600_resource *)resource)->TC_L2_dirty = true;
1746 }
1747
1748 sctx->b.b.set_shader_buffers(&sctx->b.b, PIPE_SHADER_COMPUTE, 0, 3, ssbo);
1749
1750 if (wait && qbuf == &query->buffer) {
1751 uint64_t va;
1752
1753 /* Wait for result availability. Wait only for readiness
1754 * of the last entry, since the fence writes should be
1755 * serialized in the CP.
1756 */
1757 va = qbuf->buf->gpu_address + qbuf->results_end - query->result_size;
1758 va += params.fence_offset;
1759
1760 si_gfx_wait_fence(sctx, va, 0x80000000, 0x80000000);
1761 }
1762
1763 sctx->b.b.launch_grid(&sctx->b.b, &grid);
1764 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
1765 }
1766
1767 si_restore_qbo_state(sctx, &saved_state);
1768 pipe_resource_reference(&tmp_buffer, NULL);
1769 }
1770
1771 static void si_render_condition(struct pipe_context *ctx,
1772 struct pipe_query *query,
1773 boolean condition,
1774 enum pipe_render_cond_flag mode)
1775 {
1776 struct si_context *sctx = (struct si_context *)ctx;
1777 struct si_query_hw *rquery = (struct si_query_hw *)query;
1778 struct r600_atom *atom = &sctx->b.render_cond_atom;
1779
1780 if (query) {
1781 bool needs_workaround = false;
1782
1783 /* There was a firmware regression in VI which causes successive
1784 * SET_PREDICATION packets to give the wrong answer for
1785 * non-inverted stream overflow predication.
1786 */
1787 if (((sctx->b.chip_class == VI && sctx->screen->info.pfp_fw_feature < 49) ||
1788 (sctx->b.chip_class == GFX9 && sctx->screen->info.pfp_fw_feature < 38)) &&
1789 !condition &&
1790 (rquery->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE ||
1791 (rquery->b.type == PIPE_QUERY_SO_OVERFLOW_PREDICATE &&
1792 (rquery->buffer.previous ||
1793 rquery->buffer.results_end > rquery->result_size)))) {
1794 needs_workaround = true;
1795 }
1796
1797 if (needs_workaround && !rquery->workaround_buf) {
1798 bool old_force_off = sctx->b.render_cond_force_off;
1799 sctx->b.render_cond_force_off = true;
1800
1801 u_suballocator_alloc(
1802 sctx->b.allocator_zeroed_memory, 8, 8,
1803 &rquery->workaround_offset,
1804 (struct pipe_resource **)&rquery->workaround_buf);
1805
1806 /* Reset to NULL to avoid a redundant SET_PREDICATION
1807 * from launching the compute grid.
1808 */
1809 sctx->b.render_cond = NULL;
1810
1811 ctx->get_query_result_resource(
1812 ctx, query, true, PIPE_QUERY_TYPE_U64, 0,
1813 &rquery->workaround_buf->b.b, rquery->workaround_offset);
1814
1815 /* Settings this in the render cond atom is too late,
1816 * so set it here. */
1817 sctx->b.flags |= sctx->screen->barrier_flags.L2_to_cp |
1818 SI_CONTEXT_FLUSH_FOR_RENDER_COND;
1819
1820 sctx->b.render_cond_force_off = old_force_off;
1821 }
1822 }
1823
1824 sctx->b.render_cond = query;
1825 sctx->b.render_cond_invert = condition;
1826 sctx->b.render_cond_mode = mode;
1827
1828 si_set_atom_dirty(sctx, atom, query != NULL);
1829 }
1830
1831 void si_suspend_queries(struct si_context *sctx)
1832 {
1833 struct si_query_hw *query;
1834
1835 LIST_FOR_EACH_ENTRY(query, &sctx->b.active_queries, list) {
1836 si_query_hw_emit_stop(sctx, query);
1837 }
1838 assert(sctx->b.num_cs_dw_queries_suspend == 0);
1839 }
1840
1841 void si_resume_queries(struct si_context *sctx)
1842 {
1843 struct si_query_hw *query;
1844
1845 assert(sctx->b.num_cs_dw_queries_suspend == 0);
1846
1847 /* Check CS space here. Resuming must not be interrupted by flushes. */
1848 si_need_gfx_cs_space(sctx);
1849
1850 LIST_FOR_EACH_ENTRY(query, &sctx->b.active_queries, list) {
1851 si_query_hw_emit_start(sctx, query);
1852 }
1853 }
1854
1855 #define XFULL(name_, query_type_, type_, result_type_, group_id_) \
1856 { \
1857 .name = name_, \
1858 .query_type = SI_QUERY_##query_type_, \
1859 .type = PIPE_DRIVER_QUERY_TYPE_##type_, \
1860 .result_type = PIPE_DRIVER_QUERY_RESULT_TYPE_##result_type_, \
1861 .group_id = group_id_ \
1862 }
1863
1864 #define X(name_, query_type_, type_, result_type_) \
1865 XFULL(name_, query_type_, type_, result_type_, ~(unsigned)0)
1866
1867 #define XG(group_, name_, query_type_, type_, result_type_) \
1868 XFULL(name_, query_type_, type_, result_type_, SI_QUERY_GROUP_##group_)
1869
1870 static struct pipe_driver_query_info si_driver_query_list[] = {
1871 X("num-compilations", NUM_COMPILATIONS, UINT64, CUMULATIVE),
1872 X("num-shaders-created", NUM_SHADERS_CREATED, UINT64, CUMULATIVE),
1873 X("num-shader-cache-hits", NUM_SHADER_CACHE_HITS, UINT64, CUMULATIVE),
1874 X("draw-calls", DRAW_CALLS, UINT64, AVERAGE),
1875 X("decompress-calls", DECOMPRESS_CALLS, UINT64, AVERAGE),
1876 X("MRT-draw-calls", MRT_DRAW_CALLS, UINT64, AVERAGE),
1877 X("prim-restart-calls", PRIM_RESTART_CALLS, UINT64, AVERAGE),
1878 X("spill-draw-calls", SPILL_DRAW_CALLS, UINT64, AVERAGE),
1879 X("compute-calls", COMPUTE_CALLS, UINT64, AVERAGE),
1880 X("spill-compute-calls", SPILL_COMPUTE_CALLS, UINT64, AVERAGE),
1881 X("dma-calls", DMA_CALLS, UINT64, AVERAGE),
1882 X("cp-dma-calls", CP_DMA_CALLS, UINT64, AVERAGE),
1883 X("num-vs-flushes", NUM_VS_FLUSHES, UINT64, AVERAGE),
1884 X("num-ps-flushes", NUM_PS_FLUSHES, UINT64, AVERAGE),
1885 X("num-cs-flushes", NUM_CS_FLUSHES, UINT64, AVERAGE),
1886 X("num-CB-cache-flushes", NUM_CB_CACHE_FLUSHES, UINT64, AVERAGE),
1887 X("num-DB-cache-flushes", NUM_DB_CACHE_FLUSHES, UINT64, AVERAGE),
1888 X("num-L2-invalidates", NUM_L2_INVALIDATES, UINT64, AVERAGE),
1889 X("num-L2-writebacks", NUM_L2_WRITEBACKS, UINT64, AVERAGE),
1890 X("num-resident-handles", NUM_RESIDENT_HANDLES, UINT64, AVERAGE),
1891 X("tc-offloaded-slots", TC_OFFLOADED_SLOTS, UINT64, AVERAGE),
1892 X("tc-direct-slots", TC_DIRECT_SLOTS, UINT64, AVERAGE),
1893 X("tc-num-syncs", TC_NUM_SYNCS, UINT64, AVERAGE),
1894 X("CS-thread-busy", CS_THREAD_BUSY, UINT64, AVERAGE),
1895 X("gallium-thread-busy", GALLIUM_THREAD_BUSY, UINT64, AVERAGE),
1896 X("requested-VRAM", REQUESTED_VRAM, BYTES, AVERAGE),
1897 X("requested-GTT", REQUESTED_GTT, BYTES, AVERAGE),
1898 X("mapped-VRAM", MAPPED_VRAM, BYTES, AVERAGE),
1899 X("mapped-GTT", MAPPED_GTT, BYTES, AVERAGE),
1900 X("buffer-wait-time", BUFFER_WAIT_TIME, MICROSECONDS, CUMULATIVE),
1901 X("num-mapped-buffers", NUM_MAPPED_BUFFERS, UINT64, AVERAGE),
1902 X("num-GFX-IBs", NUM_GFX_IBS, UINT64, AVERAGE),
1903 X("num-SDMA-IBs", NUM_SDMA_IBS, UINT64, AVERAGE),
1904 X("GFX-BO-list-size", GFX_BO_LIST_SIZE, UINT64, AVERAGE),
1905 X("GFX-IB-size", GFX_IB_SIZE, UINT64, AVERAGE),
1906 X("num-bytes-moved", NUM_BYTES_MOVED, BYTES, CUMULATIVE),
1907 X("num-evictions", NUM_EVICTIONS, UINT64, CUMULATIVE),
1908 X("VRAM-CPU-page-faults", NUM_VRAM_CPU_PAGE_FAULTS, UINT64, CUMULATIVE),
1909 X("VRAM-usage", VRAM_USAGE, BYTES, AVERAGE),
1910 X("VRAM-vis-usage", VRAM_VIS_USAGE, BYTES, AVERAGE),
1911 X("GTT-usage", GTT_USAGE, BYTES, AVERAGE),
1912 X("back-buffer-ps-draw-ratio", BACK_BUFFER_PS_DRAW_RATIO, UINT64, AVERAGE),
1913
1914 /* GPIN queries are for the benefit of old versions of GPUPerfStudio,
1915 * which use it as a fallback path to detect the GPU type.
1916 *
1917 * Note: The names of these queries are significant for GPUPerfStudio
1918 * (and possibly their order as well). */
1919 XG(GPIN, "GPIN_000", GPIN_ASIC_ID, UINT, AVERAGE),
1920 XG(GPIN, "GPIN_001", GPIN_NUM_SIMD, UINT, AVERAGE),
1921 XG(GPIN, "GPIN_002", GPIN_NUM_RB, UINT, AVERAGE),
1922 XG(GPIN, "GPIN_003", GPIN_NUM_SPI, UINT, AVERAGE),
1923 XG(GPIN, "GPIN_004", GPIN_NUM_SE, UINT, AVERAGE),
1924
1925 X("temperature", GPU_TEMPERATURE, UINT64, AVERAGE),
1926 X("shader-clock", CURRENT_GPU_SCLK, HZ, AVERAGE),
1927 X("memory-clock", CURRENT_GPU_MCLK, HZ, AVERAGE),
1928
1929 /* The following queries must be at the end of the list because their
1930 * availability is adjusted dynamically based on the DRM version. */
1931 X("GPU-load", GPU_LOAD, UINT64, AVERAGE),
1932 X("GPU-shaders-busy", GPU_SHADERS_BUSY, UINT64, AVERAGE),
1933 X("GPU-ta-busy", GPU_TA_BUSY, UINT64, AVERAGE),
1934 X("GPU-gds-busy", GPU_GDS_BUSY, UINT64, AVERAGE),
1935 X("GPU-vgt-busy", GPU_VGT_BUSY, UINT64, AVERAGE),
1936 X("GPU-ia-busy", GPU_IA_BUSY, UINT64, AVERAGE),
1937 X("GPU-sx-busy", GPU_SX_BUSY, UINT64, AVERAGE),
1938 X("GPU-wd-busy", GPU_WD_BUSY, UINT64, AVERAGE),
1939 X("GPU-bci-busy", GPU_BCI_BUSY, UINT64, AVERAGE),
1940 X("GPU-sc-busy", GPU_SC_BUSY, UINT64, AVERAGE),
1941 X("GPU-pa-busy", GPU_PA_BUSY, UINT64, AVERAGE),
1942 X("GPU-db-busy", GPU_DB_BUSY, UINT64, AVERAGE),
1943 X("GPU-cp-busy", GPU_CP_BUSY, UINT64, AVERAGE),
1944 X("GPU-cb-busy", GPU_CB_BUSY, UINT64, AVERAGE),
1945 X("GPU-sdma-busy", GPU_SDMA_BUSY, UINT64, AVERAGE),
1946 X("GPU-pfp-busy", GPU_PFP_BUSY, UINT64, AVERAGE),
1947 X("GPU-meq-busy", GPU_MEQ_BUSY, UINT64, AVERAGE),
1948 X("GPU-me-busy", GPU_ME_BUSY, UINT64, AVERAGE),
1949 X("GPU-surf-sync-busy", GPU_SURF_SYNC_BUSY, UINT64, AVERAGE),
1950 X("GPU-cp-dma-busy", GPU_CP_DMA_BUSY, UINT64, AVERAGE),
1951 X("GPU-scratch-ram-busy", GPU_SCRATCH_RAM_BUSY, UINT64, AVERAGE),
1952 };
1953
1954 #undef X
1955 #undef XG
1956 #undef XFULL
1957
1958 static unsigned si_get_num_queries(struct si_screen *sscreen)
1959 {
1960 if (sscreen->info.drm_major == 2 && sscreen->info.drm_minor >= 42)
1961 return ARRAY_SIZE(si_driver_query_list);
1962 else if (sscreen->info.drm_major == 3) {
1963 if (sscreen->info.chip_class >= VI)
1964 return ARRAY_SIZE(si_driver_query_list);
1965 else
1966 return ARRAY_SIZE(si_driver_query_list) - 7;
1967 }
1968 else
1969 return ARRAY_SIZE(si_driver_query_list) - 25;
1970 }
1971
1972 static int si_get_driver_query_info(struct pipe_screen *screen,
1973 unsigned index,
1974 struct pipe_driver_query_info *info)
1975 {
1976 struct si_screen *sscreen = (struct si_screen*)screen;
1977 unsigned num_queries = si_get_num_queries(sscreen);
1978
1979 if (!info) {
1980 unsigned num_perfcounters =
1981 si_get_perfcounter_info(sscreen, 0, NULL);
1982
1983 return num_queries + num_perfcounters;
1984 }
1985
1986 if (index >= num_queries)
1987 return si_get_perfcounter_info(sscreen, index - num_queries, info);
1988
1989 *info = si_driver_query_list[index];
1990
1991 switch (info->query_type) {
1992 case SI_QUERY_REQUESTED_VRAM:
1993 case SI_QUERY_VRAM_USAGE:
1994 case SI_QUERY_MAPPED_VRAM:
1995 info->max_value.u64 = sscreen->info.vram_size;
1996 break;
1997 case SI_QUERY_REQUESTED_GTT:
1998 case SI_QUERY_GTT_USAGE:
1999 case SI_QUERY_MAPPED_GTT:
2000 info->max_value.u64 = sscreen->info.gart_size;
2001 break;
2002 case SI_QUERY_GPU_TEMPERATURE:
2003 info->max_value.u64 = 125;
2004 break;
2005 case SI_QUERY_VRAM_VIS_USAGE:
2006 info->max_value.u64 = sscreen->info.vram_vis_size;
2007 break;
2008 }
2009
2010 if (info->group_id != ~(unsigned)0 && sscreen->perfcounters)
2011 info->group_id += sscreen->perfcounters->num_groups;
2012
2013 return 1;
2014 }
2015
2016 /* Note: Unfortunately, GPUPerfStudio hardcodes the order of hardware
2017 * performance counter groups, so be careful when changing this and related
2018 * functions.
2019 */
2020 static int si_get_driver_query_group_info(struct pipe_screen *screen,
2021 unsigned index,
2022 struct pipe_driver_query_group_info *info)
2023 {
2024 struct si_screen *sscreen = (struct si_screen *)screen;
2025 unsigned num_pc_groups = 0;
2026
2027 if (sscreen->perfcounters)
2028 num_pc_groups = sscreen->perfcounters->num_groups;
2029
2030 if (!info)
2031 return num_pc_groups + SI_NUM_SW_QUERY_GROUPS;
2032
2033 if (index < num_pc_groups)
2034 return si_get_perfcounter_group_info(sscreen, index, info);
2035
2036 index -= num_pc_groups;
2037 if (index >= SI_NUM_SW_QUERY_GROUPS)
2038 return 0;
2039
2040 info->name = "GPIN";
2041 info->max_active_queries = 5;
2042 info->num_queries = 5;
2043 return 1;
2044 }
2045
2046 void si_init_query_functions(struct si_context *sctx)
2047 {
2048 sctx->b.b.create_query = si_create_query;
2049 sctx->b.b.create_batch_query = si_create_batch_query;
2050 sctx->b.b.destroy_query = si_destroy_query;
2051 sctx->b.b.begin_query = si_begin_query;
2052 sctx->b.b.end_query = si_end_query;
2053 sctx->b.b.get_query_result = si_get_query_result;
2054 sctx->b.b.get_query_result_resource = si_get_query_result_resource;
2055 sctx->b.render_cond_atom.emit = si_emit_query_predication;
2056
2057 if (((struct si_screen*)sctx->b.b.screen)->info.num_render_backends > 0)
2058 sctx->b.b.render_condition = si_render_condition;
2059
2060 LIST_INITHEAD(&sctx->b.active_queries);
2061 }
2062
2063 void si_init_screen_query_functions(struct si_screen *sscreen)
2064 {
2065 sscreen->b.get_driver_query_info = si_get_driver_query_info;
2066 sscreen->b.get_driver_query_group_info = si_get_driver_query_group_info;
2067 }