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broadcom/vc5: Use u_transfer_helper for MSAA mappings.
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "gallivm/lp_bld_const.h"
25 #include "gallivm/lp_bld_gather.h"
26 #include "gallivm/lp_bld_intr.h"
27 #include "gallivm/lp_bld_logic.h"
28 #include "gallivm/lp_bld_arit.h"
29 #include "gallivm/lp_bld_flow.h"
30 #include "gallivm/lp_bld_misc.h"
31 #include "util/u_memory.h"
32 #include "util/u_string.h"
33 #include "tgsi/tgsi_build.h"
34 #include "tgsi/tgsi_util.h"
35 #include "tgsi/tgsi_dump.h"
36
37 #include "ac_binary.h"
38 #include "ac_llvm_util.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41 #include "si_shader_internal.h"
42 #include "si_pipe.h"
43 #include "sid.h"
44
45 #include "compiler/nir/nir.h"
46
47 static const char *scratch_rsrc_dword0_symbol =
48 "SCRATCH_RSRC_DWORD0";
49
50 static const char *scratch_rsrc_dword1_symbol =
51 "SCRATCH_RSRC_DWORD1";
52
53 struct si_shader_output_values
54 {
55 LLVMValueRef values[4];
56 unsigned semantic_name;
57 unsigned semantic_index;
58 ubyte vertex_stream[4];
59 };
60
61 /**
62 * Used to collect types and other info about arguments of the LLVM function
63 * before the function is created.
64 */
65 struct si_function_info {
66 LLVMTypeRef types[100];
67 LLVMValueRef *assign[100];
68 unsigned num_sgpr_params;
69 unsigned num_params;
70 };
71
72 enum si_arg_regfile {
73 ARG_SGPR,
74 ARG_VGPR
75 };
76
77 static void si_init_shader_ctx(struct si_shader_context *ctx,
78 struct si_screen *sscreen,
79 LLVMTargetMachineRef tm);
80
81 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
82 struct lp_build_tgsi_context *bld_base,
83 struct lp_build_emit_data *emit_data);
84
85 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
86 FILE *f);
87
88 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
89 union si_shader_part_key *key);
90 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
91 union si_shader_part_key *key);
92 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
93 union si_shader_part_key *key);
94 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
95 union si_shader_part_key *key);
96
97 /* Ideally pass the sample mask input to the PS epilog as v14, which
98 * is its usual location, so that the shader doesn't have to add v_mov.
99 */
100 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
101
102 enum {
103 CONST_ADDR_SPACE = 2,
104 LOCAL_ADDR_SPACE = 3,
105 };
106
107 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
108 LLVMTypeRef type)
109 {
110 if (type == ctx->ac.i64 || type == ctx->ac.f64)
111 return true;
112
113 return false;
114 }
115
116 static bool is_merged_shader(struct si_shader *shader)
117 {
118 if (shader->selector->screen->info.chip_class <= VI)
119 return false;
120
121 return shader->key.as_ls ||
122 shader->key.as_es ||
123 shader->selector->type == PIPE_SHADER_TESS_CTRL ||
124 shader->selector->type == PIPE_SHADER_GEOMETRY;
125 }
126
127 static void si_init_function_info(struct si_function_info *fninfo)
128 {
129 fninfo->num_params = 0;
130 fninfo->num_sgpr_params = 0;
131 }
132
133 static unsigned add_arg_assign(struct si_function_info *fninfo,
134 enum si_arg_regfile regfile, LLVMTypeRef type,
135 LLVMValueRef *assign)
136 {
137 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
138
139 unsigned idx = fninfo->num_params++;
140 assert(idx < ARRAY_SIZE(fninfo->types));
141
142 if (regfile == ARG_SGPR)
143 fninfo->num_sgpr_params = fninfo->num_params;
144
145 fninfo->types[idx] = type;
146 fninfo->assign[idx] = assign;
147 return idx;
148 }
149
150 static unsigned add_arg(struct si_function_info *fninfo,
151 enum si_arg_regfile regfile, LLVMTypeRef type)
152 {
153 return add_arg_assign(fninfo, regfile, type, NULL);
154 }
155
156 static void add_arg_assign_checked(struct si_function_info *fninfo,
157 enum si_arg_regfile regfile, LLVMTypeRef type,
158 LLVMValueRef *assign, unsigned idx)
159 {
160 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
161 assert(actual == idx);
162 }
163
164 static void add_arg_checked(struct si_function_info *fninfo,
165 enum si_arg_regfile regfile, LLVMTypeRef type,
166 unsigned idx)
167 {
168 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
169 }
170
171 /**
172 * Returns a unique index for a per-patch semantic name and index. The index
173 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
174 * can be calculated.
175 */
176 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
177 {
178 switch (semantic_name) {
179 case TGSI_SEMANTIC_TESSOUTER:
180 return 0;
181 case TGSI_SEMANTIC_TESSINNER:
182 return 1;
183 case TGSI_SEMANTIC_PATCH:
184 assert(index < 30);
185 return 2 + index;
186
187 default:
188 assert(!"invalid semantic name");
189 return 0;
190 }
191 }
192
193 /**
194 * Returns a unique index for a semantic name and index. The index must be
195 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
196 * calculated.
197 */
198 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
199 {
200 switch (semantic_name) {
201 case TGSI_SEMANTIC_POSITION:
202 return 0;
203 case TGSI_SEMANTIC_GENERIC:
204 /* Since some shader stages use the the highest used IO index
205 * to determine the size to allocate for inputs/outputs
206 * (in LDS, tess and GS rings). GENERIC should be placed right
207 * after POSITION to make that size as small as possible.
208 */
209 if (index < SI_MAX_IO_GENERIC)
210 return 1 + index;
211
212 assert(!"invalid generic index");
213 return 0;
214 case TGSI_SEMANTIC_PSIZE:
215 return SI_MAX_IO_GENERIC + 1;
216 case TGSI_SEMANTIC_CLIPDIST:
217 assert(index <= 1);
218 return SI_MAX_IO_GENERIC + 2 + index;
219 case TGSI_SEMANTIC_FOG:
220 return SI_MAX_IO_GENERIC + 4;
221 case TGSI_SEMANTIC_LAYER:
222 return SI_MAX_IO_GENERIC + 5;
223 case TGSI_SEMANTIC_VIEWPORT_INDEX:
224 return SI_MAX_IO_GENERIC + 6;
225 case TGSI_SEMANTIC_PRIMID:
226 return SI_MAX_IO_GENERIC + 7;
227 case TGSI_SEMANTIC_COLOR: /* these alias */
228 case TGSI_SEMANTIC_BCOLOR:
229 assert(index < 2);
230 return SI_MAX_IO_GENERIC + 8 + index;
231 case TGSI_SEMANTIC_TEXCOORD:
232 assert(index < 8);
233 assert(SI_MAX_IO_GENERIC + 10 + index < 64);
234 return SI_MAX_IO_GENERIC + 10 + index;
235 default:
236 assert(!"invalid semantic name");
237 return 0;
238 }
239 }
240
241 /**
242 * Get the value of a shader input parameter and extract a bitfield.
243 */
244 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
245 unsigned param, unsigned rshift,
246 unsigned bitwidth)
247 {
248 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
249 param);
250
251 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
252 value = ac_to_integer(&ctx->ac, value);
253
254 if (rshift)
255 value = LLVMBuildLShr(ctx->ac.builder, value,
256 LLVMConstInt(ctx->i32, rshift, 0), "");
257
258 if (rshift + bitwidth < 32) {
259 unsigned mask = (1 << bitwidth) - 1;
260 value = LLVMBuildAnd(ctx->ac.builder, value,
261 LLVMConstInt(ctx->i32, mask, 0), "");
262 }
263
264 return value;
265 }
266
267 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
268 {
269 switch (ctx->type) {
270 case PIPE_SHADER_TESS_CTRL:
271 return unpack_param(ctx, ctx->param_tcs_rel_ids, 0, 8);
272
273 case PIPE_SHADER_TESS_EVAL:
274 return LLVMGetParam(ctx->main_fn,
275 ctx->param_tes_rel_patch_id);
276
277 default:
278 assert(0);
279 return NULL;
280 }
281 }
282
283 /* Tessellation shaders pass outputs to the next shader using LDS.
284 *
285 * LS outputs = TCS inputs
286 * TCS outputs = TES inputs
287 *
288 * The LDS layout is:
289 * - TCS inputs for patch 0
290 * - TCS inputs for patch 1
291 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
292 * - ...
293 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
294 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
295 * - TCS outputs for patch 1
296 * - Per-patch TCS outputs for patch 1
297 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
298 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
299 * - ...
300 *
301 * All three shaders VS(LS), TCS, TES share the same LDS space.
302 */
303
304 static LLVMValueRef
305 get_tcs_in_patch_stride(struct si_shader_context *ctx)
306 {
307 return unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
308 }
309
310 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
311 {
312 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
313
314 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
315 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
316
317 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
318 }
319
320 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
321 {
322 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
323
324 return LLVMConstInt(ctx->i32, stride, 0);
325 }
326
327 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
328 {
329 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
330 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
331
332 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
333 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
334 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
335 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
336 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
337 num_patch_outputs * 4;
338 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
339 }
340
341 static LLVMValueRef
342 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
343 {
344 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
345 unpack_param(ctx,
346 ctx->param_tcs_out_lds_offsets,
347 0, 16),
348 4);
349 }
350
351 static LLVMValueRef
352 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
353 {
354 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
355 unpack_param(ctx,
356 ctx->param_tcs_out_lds_offsets,
357 16, 16),
358 4);
359 }
360
361 static LLVMValueRef
362 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
363 {
364 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
365 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
366
367 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
368 }
369
370 static LLVMValueRef
371 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
372 {
373 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
374 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
375 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
376
377 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
378 LLVMBuildMul(ctx->ac.builder, patch_stride,
379 rel_patch_id, ""),
380 "");
381 }
382
383 static LLVMValueRef
384 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
385 {
386 LLVMValueRef patch0_patch_data_offset =
387 get_tcs_out_patch0_patch_data_offset(ctx);
388 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
389 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
390
391 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
392 LLVMBuildMul(ctx->ac.builder, patch_stride,
393 rel_patch_id, ""),
394 "");
395 }
396
397 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
398 {
399 unsigned tcs_out_vertices =
400 ctx->shader->selector ?
401 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
402
403 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
404 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
405 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
406
407 return unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
408 }
409
410 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
411 {
412 unsigned stride;
413
414 switch (ctx->type) {
415 case PIPE_SHADER_VERTEX:
416 stride = util_last_bit64(ctx->shader->selector->outputs_written);
417 return LLVMConstInt(ctx->i32, stride * 4, 0);
418
419 case PIPE_SHADER_TESS_CTRL:
420 if (ctx->screen->info.chip_class >= GFX9 &&
421 ctx->shader->is_monolithic) {
422 stride = util_last_bit64(ctx->shader->key.part.tcs.ls->outputs_written);
423 return LLVMConstInt(ctx->i32, stride * 4, 0);
424 }
425 return unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
426
427 default:
428 assert(0);
429 return NULL;
430 }
431 }
432
433 static LLVMValueRef get_instance_index_for_fetch(
434 struct si_shader_context *ctx,
435 unsigned param_start_instance, LLVMValueRef divisor)
436 {
437 LLVMValueRef result = ctx->abi.instance_id;
438
439 /* The division must be done before START_INSTANCE is added. */
440 if (divisor != ctx->i32_1)
441 result = LLVMBuildUDiv(ctx->ac.builder, result, divisor, "");
442
443 return LLVMBuildAdd(ctx->ac.builder, result,
444 LLVMGetParam(ctx->main_fn, param_start_instance), "");
445 }
446
447 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
448 * to float. */
449 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
450 LLVMValueRef vec4,
451 unsigned double_index)
452 {
453 LLVMBuilderRef builder = ctx->ac.builder;
454 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->ac.context);
455 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
456 LLVMVectorType(f64, 2), "");
457 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
458 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
459 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
460 }
461
462 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
463 LLVMValueRef i32, unsigned index)
464 {
465 assert(index <= 1);
466
467 if (index == 1)
468 return LLVMBuildAShr(ctx->ac.builder, i32,
469 LLVMConstInt(ctx->i32, 16, 0), "");
470
471 return LLVMBuildSExt(ctx->ac.builder,
472 LLVMBuildTrunc(ctx->ac.builder, i32,
473 ctx->ac.i16, ""),
474 ctx->i32, "");
475 }
476
477 void si_llvm_load_input_vs(
478 struct si_shader_context *ctx,
479 unsigned input_index,
480 LLVMValueRef out[4])
481 {
482 unsigned vs_blit_property =
483 ctx->shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
484
485 if (vs_blit_property) {
486 LLVMValueRef vertex_id = ctx->abi.vertex_id;
487 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
488 LLVMIntULE, vertex_id,
489 ctx->i32_1, "");
490 /* Use LLVMIntNE, because we have 3 vertices and only
491 * the middle one should use y2.
492 */
493 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
494 LLVMIntNE, vertex_id,
495 ctx->i32_1, "");
496
497 if (input_index == 0) {
498 /* Position: */
499 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
500 ctx->param_vs_blit_inputs);
501 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
502 ctx->param_vs_blit_inputs + 1);
503
504 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
505 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
506 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
507 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
508
509 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
510 x1, x2, "");
511 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
512 y1, y2, "");
513
514 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
515 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
516 out[2] = LLVMGetParam(ctx->main_fn,
517 ctx->param_vs_blit_inputs + 2);
518 out[3] = ctx->ac.f32_1;
519 return;
520 }
521
522 /* Color or texture coordinates: */
523 assert(input_index == 1);
524
525 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
526 for (int i = 0; i < 4; i++) {
527 out[i] = LLVMGetParam(ctx->main_fn,
528 ctx->param_vs_blit_inputs + 3 + i);
529 }
530 } else {
531 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
532 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
533 ctx->param_vs_blit_inputs + 3);
534 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
535 ctx->param_vs_blit_inputs + 4);
536 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
537 ctx->param_vs_blit_inputs + 5);
538 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
539 ctx->param_vs_blit_inputs + 6);
540
541 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
542 x1, x2, "");
543 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
544 y1, y2, "");
545 out[2] = LLVMGetParam(ctx->main_fn,
546 ctx->param_vs_blit_inputs + 7);
547 out[3] = LLVMGetParam(ctx->main_fn,
548 ctx->param_vs_blit_inputs + 8);
549 }
550 return;
551 }
552
553 unsigned chan;
554 unsigned fix_fetch;
555 unsigned num_fetches;
556 unsigned fetch_stride;
557
558 LLVMValueRef t_list_ptr;
559 LLVMValueRef t_offset;
560 LLVMValueRef t_list;
561 LLVMValueRef vertex_index;
562 LLVMValueRef input[3];
563
564 /* Load the T list */
565 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
566
567 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
568
569 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
570
571 vertex_index = LLVMGetParam(ctx->main_fn,
572 ctx->param_vertex_index0 +
573 input_index);
574
575 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
576
577 /* Do multiple loads for special formats. */
578 switch (fix_fetch) {
579 case SI_FIX_FETCH_RGB_64_FLOAT:
580 num_fetches = 3; /* 3 2-dword loads */
581 fetch_stride = 8;
582 break;
583 case SI_FIX_FETCH_RGBA_64_FLOAT:
584 num_fetches = 2; /* 2 4-dword loads */
585 fetch_stride = 16;
586 break;
587 case SI_FIX_FETCH_RGB_8:
588 case SI_FIX_FETCH_RGB_8_INT:
589 num_fetches = 3;
590 fetch_stride = 1;
591 break;
592 case SI_FIX_FETCH_RGB_16:
593 case SI_FIX_FETCH_RGB_16_INT:
594 num_fetches = 3;
595 fetch_stride = 2;
596 break;
597 default:
598 num_fetches = 1;
599 fetch_stride = 0;
600 }
601
602 for (unsigned i = 0; i < num_fetches; i++) {
603 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
604
605 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
606 vertex_index, voffset,
607 true);
608 }
609
610 /* Break up the vec4 into individual components */
611 for (chan = 0; chan < 4; chan++) {
612 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
613 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
614 input[0], llvm_chan, "");
615 }
616
617 switch (fix_fetch) {
618 case SI_FIX_FETCH_A2_SNORM:
619 case SI_FIX_FETCH_A2_SSCALED:
620 case SI_FIX_FETCH_A2_SINT: {
621 /* The hardware returns an unsigned value; convert it to a
622 * signed one.
623 */
624 LLVMValueRef tmp = out[3];
625 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
626
627 /* First, recover the sign-extended signed integer value. */
628 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
629 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
630 else
631 tmp = ac_to_integer(&ctx->ac, tmp);
632
633 /* For the integer-like cases, do a natural sign extension.
634 *
635 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
636 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
637 * exponent.
638 */
639 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
640 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
641 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
642 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
643
644 /* Convert back to the right type. */
645 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
646 LLVMValueRef clamp;
647 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
648 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
649 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
650 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
651 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
652 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
653 }
654
655 out[3] = tmp;
656 break;
657 }
658 case SI_FIX_FETCH_RGBA_32_UNORM:
659 case SI_FIX_FETCH_RGBX_32_UNORM:
660 for (chan = 0; chan < 4; chan++) {
661 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
662 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
663 out[chan], ctx->f32, "");
664 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
665 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
666 }
667 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
668 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
669 out[3] = LLVMConstReal(ctx->f32, 1);
670 break;
671 case SI_FIX_FETCH_RGBA_32_SNORM:
672 case SI_FIX_FETCH_RGBX_32_SNORM:
673 case SI_FIX_FETCH_RGBA_32_FIXED:
674 case SI_FIX_FETCH_RGBX_32_FIXED: {
675 double scale;
676 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
677 scale = 1.0 / 0x10000;
678 else
679 scale = 1.0 / INT_MAX;
680
681 for (chan = 0; chan < 4; chan++) {
682 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
683 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
684 out[chan], ctx->f32, "");
685 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
686 LLVMConstReal(ctx->f32, scale), "");
687 }
688 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
689 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
690 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
691 out[3] = LLVMConstReal(ctx->f32, 1);
692 break;
693 }
694 case SI_FIX_FETCH_RGBA_32_USCALED:
695 for (chan = 0; chan < 4; chan++) {
696 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
697 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
698 out[chan], ctx->f32, "");
699 }
700 break;
701 case SI_FIX_FETCH_RGBA_32_SSCALED:
702 for (chan = 0; chan < 4; chan++) {
703 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
704 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
705 out[chan], ctx->f32, "");
706 }
707 break;
708 case SI_FIX_FETCH_RG_64_FLOAT:
709 for (chan = 0; chan < 2; chan++)
710 out[chan] = extract_double_to_float(ctx, input[0], chan);
711
712 out[2] = LLVMConstReal(ctx->f32, 0);
713 out[3] = LLVMConstReal(ctx->f32, 1);
714 break;
715 case SI_FIX_FETCH_RGB_64_FLOAT:
716 for (chan = 0; chan < 3; chan++)
717 out[chan] = extract_double_to_float(ctx, input[chan], 0);
718
719 out[3] = LLVMConstReal(ctx->f32, 1);
720 break;
721 case SI_FIX_FETCH_RGBA_64_FLOAT:
722 for (chan = 0; chan < 4; chan++) {
723 out[chan] = extract_double_to_float(ctx, input[chan / 2],
724 chan % 2);
725 }
726 break;
727 case SI_FIX_FETCH_RGB_8:
728 case SI_FIX_FETCH_RGB_8_INT:
729 case SI_FIX_FETCH_RGB_16:
730 case SI_FIX_FETCH_RGB_16_INT:
731 for (chan = 0; chan < 3; chan++) {
732 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
733 input[chan],
734 ctx->i32_0, "");
735 }
736 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
737 fix_fetch == SI_FIX_FETCH_RGB_16) {
738 out[3] = LLVMConstReal(ctx->f32, 1);
739 } else {
740 out[3] = ac_to_float(&ctx->ac, ctx->i32_1);
741 }
742 break;
743 }
744 }
745
746 static void declare_input_vs(
747 struct si_shader_context *ctx,
748 unsigned input_index,
749 const struct tgsi_full_declaration *decl,
750 LLVMValueRef out[4])
751 {
752 si_llvm_load_input_vs(ctx, input_index, out);
753 }
754
755 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
756 unsigned swizzle)
757 {
758 if (swizzle > 0)
759 return ctx->i32_0;
760
761 switch (ctx->type) {
762 case PIPE_SHADER_VERTEX:
763 return LLVMGetParam(ctx->main_fn,
764 ctx->param_vs_prim_id);
765 case PIPE_SHADER_TESS_CTRL:
766 return LLVMGetParam(ctx->main_fn,
767 ctx->param_tcs_patch_id);
768 case PIPE_SHADER_TESS_EVAL:
769 return LLVMGetParam(ctx->main_fn,
770 ctx->param_tes_patch_id);
771 case PIPE_SHADER_GEOMETRY:
772 return ctx->abi.gs_prim_id;
773 default:
774 assert(0);
775 return ctx->i32_0;
776 }
777 }
778
779 /**
780 * Return the value of tgsi_ind_register for indexing.
781 * This is the indirect index with the constant offset added to it.
782 */
783 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
784 const struct tgsi_ind_register *ind,
785 unsigned addr_mul,
786 int rel_index)
787 {
788 LLVMValueRef result;
789
790 if (ind->File == TGSI_FILE_ADDRESS) {
791 result = ctx->addrs[ind->Index][ind->Swizzle];
792 result = LLVMBuildLoad(ctx->ac.builder, result, "");
793 } else {
794 struct tgsi_full_src_register src = {};
795
796 src.Register.File = ind->File;
797 src.Register.Index = ind->Index;
798
799 /* Set the second index to 0 for constants. */
800 if (ind->File == TGSI_FILE_CONSTANT)
801 src.Register.Dimension = 1;
802
803 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
804 TGSI_TYPE_SIGNED,
805 ind->Swizzle);
806 result = ac_to_integer(&ctx->ac, result);
807 }
808
809 if (addr_mul != 1)
810 result = LLVMBuildMul(ctx->ac.builder, result,
811 LLVMConstInt(ctx->i32, addr_mul, 0), "");
812 result = LLVMBuildAdd(ctx->ac.builder, result,
813 LLVMConstInt(ctx->i32, rel_index, 0), "");
814 return result;
815 }
816
817 /**
818 * Like si_get_indirect_index, but restricts the return value to a (possibly
819 * undefined) value inside [0..num).
820 */
821 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
822 const struct tgsi_ind_register *ind,
823 int rel_index, unsigned num)
824 {
825 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
826
827 return si_llvm_bound_index(ctx, result, num);
828 }
829
830
831 /**
832 * Calculate a dword address given an input or output register and a stride.
833 */
834 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
835 const struct tgsi_full_dst_register *dst,
836 const struct tgsi_full_src_register *src,
837 LLVMValueRef vertex_dw_stride,
838 LLVMValueRef base_addr)
839 {
840 struct tgsi_shader_info *info = &ctx->shader->selector->info;
841 ubyte *name, *index, *array_first;
842 int first, param;
843 struct tgsi_full_dst_register reg;
844
845 /* Set the register description. The address computation is the same
846 * for sources and destinations. */
847 if (src) {
848 reg.Register.File = src->Register.File;
849 reg.Register.Index = src->Register.Index;
850 reg.Register.Indirect = src->Register.Indirect;
851 reg.Register.Dimension = src->Register.Dimension;
852 reg.Indirect = src->Indirect;
853 reg.Dimension = src->Dimension;
854 reg.DimIndirect = src->DimIndirect;
855 } else
856 reg = *dst;
857
858 /* If the register is 2-dimensional (e.g. an array of vertices
859 * in a primitive), calculate the base address of the vertex. */
860 if (reg.Register.Dimension) {
861 LLVMValueRef index;
862
863 if (reg.Dimension.Indirect)
864 index = si_get_indirect_index(ctx, &reg.DimIndirect,
865 1, reg.Dimension.Index);
866 else
867 index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
868
869 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
870 LLVMBuildMul(ctx->ac.builder, index,
871 vertex_dw_stride, ""), "");
872 }
873
874 /* Get information about the register. */
875 if (reg.Register.File == TGSI_FILE_INPUT) {
876 name = info->input_semantic_name;
877 index = info->input_semantic_index;
878 array_first = info->input_array_first;
879 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
880 name = info->output_semantic_name;
881 index = info->output_semantic_index;
882 array_first = info->output_array_first;
883 } else {
884 assert(0);
885 return NULL;
886 }
887
888 if (reg.Register.Indirect) {
889 /* Add the relative address of the element. */
890 LLVMValueRef ind_index;
891
892 if (reg.Indirect.ArrayID)
893 first = array_first[reg.Indirect.ArrayID];
894 else
895 first = reg.Register.Index;
896
897 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
898 1, reg.Register.Index - first);
899
900 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
901 LLVMBuildMul(ctx->ac.builder, ind_index,
902 LLVMConstInt(ctx->i32, 4, 0), ""), "");
903
904 param = reg.Register.Dimension ?
905 si_shader_io_get_unique_index(name[first], index[first]) :
906 si_shader_io_get_unique_index_patch(name[first], index[first]);
907 } else {
908 param = reg.Register.Dimension ?
909 si_shader_io_get_unique_index(name[reg.Register.Index],
910 index[reg.Register.Index]) :
911 si_shader_io_get_unique_index_patch(name[reg.Register.Index],
912 index[reg.Register.Index]);
913 }
914
915 /* Add the base address of the element. */
916 return LLVMBuildAdd(ctx->ac.builder, base_addr,
917 LLVMConstInt(ctx->i32, param * 4, 0), "");
918 }
919
920 /* The offchip buffer layout for TCS->TES is
921 *
922 * - attribute 0 of patch 0 vertex 0
923 * - attribute 0 of patch 0 vertex 1
924 * - attribute 0 of patch 0 vertex 2
925 * ...
926 * - attribute 0 of patch 1 vertex 0
927 * - attribute 0 of patch 1 vertex 1
928 * ...
929 * - attribute 1 of patch 0 vertex 0
930 * - attribute 1 of patch 0 vertex 1
931 * ...
932 * - per patch attribute 0 of patch 0
933 * - per patch attribute 0 of patch 1
934 * ...
935 *
936 * Note that every attribute has 4 components.
937 */
938 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
939 LLVMValueRef rel_patch_id,
940 LLVMValueRef vertex_index,
941 LLVMValueRef param_index)
942 {
943 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
944 LLVMValueRef param_stride, constant16;
945
946 vertices_per_patch = get_num_tcs_out_vertices(ctx);
947 num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
948 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
949 num_patches, "");
950
951 constant16 = LLVMConstInt(ctx->i32, 16, 0);
952 if (vertex_index) {
953 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
954 vertices_per_patch, "");
955
956 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
957 vertex_index, "");
958
959 param_stride = total_vertices;
960 } else {
961 base_addr = rel_patch_id;
962 param_stride = num_patches;
963 }
964
965 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
966 LLVMBuildMul(ctx->ac.builder, param_index,
967 param_stride, ""), "");
968
969 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
970
971 if (!vertex_index) {
972 LLVMValueRef patch_data_offset =
973 unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
974
975 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
976 patch_data_offset, "");
977 }
978 return base_addr;
979 }
980
981 /* This is a generic helper that can be shared by the NIR and TGSI backends */
982 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
983 struct si_shader_context *ctx,
984 LLVMValueRef vertex_index,
985 LLVMValueRef param_index,
986 unsigned param_base,
987 ubyte *name,
988 ubyte *index,
989 bool is_patch)
990 {
991 unsigned param_index_base;
992
993 param_index_base = is_patch ?
994 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
995 si_shader_io_get_unique_index(name[param_base], index[param_base]);
996
997 if (param_index) {
998 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
999 LLVMConstInt(ctx->i32, param_index_base, 0),
1000 "");
1001 } else {
1002 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
1003 }
1004
1005 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
1006 vertex_index, param_index);
1007 }
1008
1009 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
1010 struct si_shader_context *ctx,
1011 const struct tgsi_full_dst_register *dst,
1012 const struct tgsi_full_src_register *src)
1013 {
1014 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1015 ubyte *name, *index, *array_first;
1016 struct tgsi_full_src_register reg;
1017 LLVMValueRef vertex_index = NULL;
1018 LLVMValueRef param_index = NULL;
1019 unsigned param_base;
1020
1021 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
1022
1023 if (reg.Register.Dimension) {
1024
1025 if (reg.Dimension.Indirect)
1026 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
1027 1, reg.Dimension.Index);
1028 else
1029 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
1030 }
1031
1032 /* Get information about the register. */
1033 if (reg.Register.File == TGSI_FILE_INPUT) {
1034 name = info->input_semantic_name;
1035 index = info->input_semantic_index;
1036 array_first = info->input_array_first;
1037 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1038 name = info->output_semantic_name;
1039 index = info->output_semantic_index;
1040 array_first = info->output_array_first;
1041 } else {
1042 assert(0);
1043 return NULL;
1044 }
1045
1046 if (reg.Register.Indirect) {
1047 if (reg.Indirect.ArrayID)
1048 param_base = array_first[reg.Indirect.ArrayID];
1049 else
1050 param_base = reg.Register.Index;
1051
1052 param_index = si_get_indirect_index(ctx, &reg.Indirect,
1053 1, reg.Register.Index - param_base);
1054
1055 } else {
1056 param_base = reg.Register.Index;
1057 }
1058
1059 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1060 param_index, param_base,
1061 name, index, !reg.Register.Dimension);
1062 }
1063
1064 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
1065 LLVMTypeRef type, unsigned swizzle,
1066 LLVMValueRef buffer, LLVMValueRef offset,
1067 LLVMValueRef base, bool can_speculate)
1068 {
1069 struct si_shader_context *ctx = si_shader_context(bld_base);
1070 LLVMValueRef value, value2;
1071 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
1072
1073 if (swizzle == ~0) {
1074 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1075 0, 1, 0, can_speculate, false);
1076
1077 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1078 }
1079
1080 if (!llvm_type_is_64bit(ctx, type)) {
1081 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1082 0, 1, 0, can_speculate, false);
1083
1084 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1085 return LLVMBuildExtractElement(ctx->ac.builder, value,
1086 LLVMConstInt(ctx->i32, swizzle, 0), "");
1087 }
1088
1089 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1090 swizzle * 4, 1, 0, can_speculate, false);
1091
1092 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1093 swizzle * 4 + 4, 1, 0, can_speculate, false);
1094
1095 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1096 }
1097
1098 /**
1099 * Load from LDS.
1100 *
1101 * \param type output value type
1102 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1103 * \param dw_addr address in dwords
1104 */
1105 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1106 LLVMTypeRef type, unsigned swizzle,
1107 LLVMValueRef dw_addr)
1108 {
1109 struct si_shader_context *ctx = si_shader_context(bld_base);
1110 LLVMValueRef value;
1111
1112 if (swizzle == ~0) {
1113 LLVMValueRef values[TGSI_NUM_CHANNELS];
1114
1115 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1116 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1117
1118 return lp_build_gather_values(&ctx->gallivm, values,
1119 TGSI_NUM_CHANNELS);
1120 }
1121
1122 /* Split 64-bit loads. */
1123 if (llvm_type_is_64bit(ctx, type)) {
1124 LLVMValueRef lo, hi;
1125
1126 lo = lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1127 hi = lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1128 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1129 }
1130
1131 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1132 LLVMConstInt(ctx->i32, swizzle, 0));
1133
1134 value = ac_lds_load(&ctx->ac, dw_addr);
1135
1136 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1137 }
1138
1139 /**
1140 * Store to LDS.
1141 *
1142 * \param swizzle offset (typically 0..3)
1143 * \param dw_addr address in dwords
1144 * \param value value to store
1145 */
1146 static void lds_store(struct si_shader_context *ctx,
1147 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1148 LLVMValueRef value)
1149 {
1150 dw_addr = lp_build_add(&ctx->bld_base.uint_bld, dw_addr,
1151 LLVMConstInt(ctx->i32, dw_offset_imm, 0));
1152
1153 ac_lds_store(&ctx->ac, dw_addr, value);
1154 }
1155
1156 static LLVMValueRef desc_from_addr_base64k(struct si_shader_context *ctx,
1157 unsigned param)
1158 {
1159 LLVMBuilderRef builder = ctx->ac.builder;
1160
1161 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1162 addr = LLVMBuildZExt(builder, addr, ctx->i64, "");
1163 addr = LLVMBuildShl(builder, addr, LLVMConstInt(ctx->i64, 16, 0), "");
1164
1165 uint64_t desc2 = 0xffffffff;
1166 uint64_t desc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1167 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1168 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1169 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1170 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1171 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1172 LLVMValueRef hi = LLVMConstInt(ctx->i64, desc2 | (desc3 << 32), 0);
1173
1174 LLVMValueRef desc = LLVMGetUndef(LLVMVectorType(ctx->i64, 2));
1175 desc = LLVMBuildInsertElement(builder, desc, addr, ctx->i32_0, "");
1176 desc = LLVMBuildInsertElement(builder, desc, hi, ctx->i32_1, "");
1177 return LLVMBuildBitCast(builder, desc, ctx->v4i32, "");
1178 }
1179
1180 static LLVMValueRef fetch_input_tcs(
1181 struct lp_build_tgsi_context *bld_base,
1182 const struct tgsi_full_src_register *reg,
1183 enum tgsi_opcode_type type, unsigned swizzle)
1184 {
1185 struct si_shader_context *ctx = si_shader_context(bld_base);
1186 LLVMValueRef dw_addr, stride;
1187
1188 stride = get_tcs_in_vertex_dw_stride(ctx);
1189 dw_addr = get_tcs_in_current_patch_offset(ctx);
1190 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1191
1192 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1193 }
1194
1195 static LLVMValueRef fetch_output_tcs(
1196 struct lp_build_tgsi_context *bld_base,
1197 const struct tgsi_full_src_register *reg,
1198 enum tgsi_opcode_type type, unsigned swizzle)
1199 {
1200 struct si_shader_context *ctx = si_shader_context(bld_base);
1201 LLVMValueRef dw_addr, stride;
1202
1203 if (reg->Register.Dimension) {
1204 stride = get_tcs_out_vertex_dw_stride(ctx);
1205 dw_addr = get_tcs_out_current_patch_offset(ctx);
1206 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1207 } else {
1208 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1209 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1210 }
1211
1212 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1213 }
1214
1215 static LLVMValueRef fetch_input_tes(
1216 struct lp_build_tgsi_context *bld_base,
1217 const struct tgsi_full_src_register *reg,
1218 enum tgsi_opcode_type type, unsigned swizzle)
1219 {
1220 struct si_shader_context *ctx = si_shader_context(bld_base);
1221 LLVMValueRef buffer, base, addr;
1222
1223 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1224
1225 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1226 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1227
1228 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1229 buffer, base, addr, true);
1230 }
1231
1232 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1233 const struct tgsi_full_instruction *inst,
1234 const struct tgsi_opcode_info *info,
1235 unsigned index,
1236 LLVMValueRef dst[4])
1237 {
1238 struct si_shader_context *ctx = si_shader_context(bld_base);
1239 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1240 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1241 unsigned chan_index;
1242 LLVMValueRef dw_addr, stride;
1243 LLVMValueRef buffer, base, buf_addr;
1244 LLVMValueRef values[4];
1245 bool skip_lds_store;
1246 bool is_tess_factor = false, is_tess_inner = false;
1247
1248 /* Only handle per-patch and per-vertex outputs here.
1249 * Vectors will be lowered to scalars and this function will be called again.
1250 */
1251 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1252 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1253 si_llvm_emit_store(bld_base, inst, info, index, dst);
1254 return;
1255 }
1256
1257 if (reg->Register.Dimension) {
1258 stride = get_tcs_out_vertex_dw_stride(ctx);
1259 dw_addr = get_tcs_out_current_patch_offset(ctx);
1260 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1261 skip_lds_store = !sh_info->reads_pervertex_outputs;
1262 } else {
1263 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1264 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1265 skip_lds_store = !sh_info->reads_perpatch_outputs;
1266
1267 if (!reg->Register.Indirect) {
1268 int name = sh_info->output_semantic_name[reg->Register.Index];
1269
1270 /* Always write tess factors into LDS for the TCS epilog. */
1271 if (name == TGSI_SEMANTIC_TESSINNER ||
1272 name == TGSI_SEMANTIC_TESSOUTER) {
1273 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1274 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1275 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1276 is_tess_factor = true;
1277 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1278 }
1279 }
1280 }
1281
1282 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1283
1284 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1285 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1286
1287 uint32_t writemask = reg->Register.WriteMask;
1288 while (writemask) {
1289 chan_index = u_bit_scan(&writemask);
1290 LLVMValueRef value = dst[chan_index];
1291
1292 if (inst->Instruction.Saturate)
1293 value = ac_build_clamp(&ctx->ac, value);
1294
1295 /* Skip LDS stores if there is no LDS read of this output. */
1296 if (!skip_lds_store)
1297 lds_store(ctx, chan_index, dw_addr, value);
1298
1299 value = ac_to_integer(&ctx->ac, value);
1300 values[chan_index] = value;
1301
1302 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1303 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1304 buf_addr, base,
1305 4 * chan_index, 1, 0, true, false);
1306 }
1307
1308 /* Write tess factors into VGPRs for the epilog. */
1309 if (is_tess_factor &&
1310 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1311 if (!is_tess_inner) {
1312 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1313 ctx->invoc0_tess_factors[chan_index]);
1314 } else if (chan_index < 2) {
1315 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1316 ctx->invoc0_tess_factors[4 + chan_index]);
1317 }
1318 }
1319 }
1320
1321 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1322 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1323 values, 4);
1324 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1325 base, 0, 1, 0, true, false);
1326 }
1327 }
1328
1329 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1330 unsigned input_index,
1331 unsigned vtx_offset_param,
1332 LLVMTypeRef type,
1333 unsigned swizzle)
1334 {
1335 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1336 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1337 struct si_shader *shader = ctx->shader;
1338 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1339 LLVMValueRef vtx_offset, soffset;
1340 struct tgsi_shader_info *info = &shader->selector->info;
1341 unsigned semantic_name = info->input_semantic_name[input_index];
1342 unsigned semantic_index = info->input_semantic_index[input_index];
1343 unsigned param;
1344 LLVMValueRef value;
1345
1346 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1347
1348 /* GFX9 has the ESGS ring in LDS. */
1349 if (ctx->screen->info.chip_class >= GFX9) {
1350 unsigned index = vtx_offset_param;
1351
1352 switch (index / 2) {
1353 case 0:
1354 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx01_offset,
1355 index % 2 ? 16 : 0, 16);
1356 break;
1357 case 1:
1358 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx23_offset,
1359 index % 2 ? 16 : 0, 16);
1360 break;
1361 case 2:
1362 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx45_offset,
1363 index % 2 ? 16 : 0, 16);
1364 break;
1365 default:
1366 assert(0);
1367 return NULL;
1368 }
1369
1370 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1371 LLVMConstInt(ctx->i32, param * 4, 0), "");
1372 return lds_load(bld_base, type, swizzle, vtx_offset);
1373 }
1374
1375 /* GFX6: input load from the ESGS ring in memory. */
1376 if (swizzle == ~0) {
1377 LLVMValueRef values[TGSI_NUM_CHANNELS];
1378 unsigned chan;
1379 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1380 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1381 type, chan);
1382 }
1383 return lp_build_gather_values(&ctx->gallivm, values,
1384 TGSI_NUM_CHANNELS);
1385 }
1386
1387 /* Get the vertex offset parameter on GFX6. */
1388 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1389
1390 vtx_offset = lp_build_mul_imm(uint, gs_vtx_offset, 4);
1391
1392 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1393
1394 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1395 vtx_offset, soffset, 0, 1, 0, true, false);
1396 if (llvm_type_is_64bit(ctx, type)) {
1397 LLVMValueRef value2;
1398 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1399
1400 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1401 ctx->i32_0, vtx_offset, soffset,
1402 0, 1, 0, true, false);
1403 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1404 }
1405 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1406 }
1407
1408 static LLVMValueRef fetch_input_gs(
1409 struct lp_build_tgsi_context *bld_base,
1410 const struct tgsi_full_src_register *reg,
1411 enum tgsi_opcode_type type,
1412 unsigned swizzle)
1413 {
1414 struct si_shader_context *ctx = si_shader_context(bld_base);
1415 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1416
1417 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1418 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1419 return get_primitive_id(ctx, swizzle);
1420
1421 if (!reg->Register.Dimension)
1422 return NULL;
1423
1424 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1425 reg->Dimension.Index,
1426 tgsi2llvmtype(bld_base, type),
1427 swizzle);
1428 }
1429
1430 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1431 {
1432 switch (interpolate) {
1433 case TGSI_INTERPOLATE_CONSTANT:
1434 return 0;
1435
1436 case TGSI_INTERPOLATE_LINEAR:
1437 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1438 return SI_PARAM_LINEAR_SAMPLE;
1439 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1440 return SI_PARAM_LINEAR_CENTROID;
1441 else
1442 return SI_PARAM_LINEAR_CENTER;
1443 break;
1444 case TGSI_INTERPOLATE_COLOR:
1445 case TGSI_INTERPOLATE_PERSPECTIVE:
1446 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1447 return SI_PARAM_PERSP_SAMPLE;
1448 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1449 return SI_PARAM_PERSP_CENTROID;
1450 else
1451 return SI_PARAM_PERSP_CENTER;
1452 break;
1453 default:
1454 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1455 return -1;
1456 }
1457 }
1458
1459 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1460 unsigned attr_index, unsigned chan,
1461 LLVMValueRef prim_mask,
1462 LLVMValueRef i, LLVMValueRef j)
1463 {
1464 if (i || j) {
1465 return ac_build_fs_interp(&ctx->ac,
1466 LLVMConstInt(ctx->i32, chan, 0),
1467 LLVMConstInt(ctx->i32, attr_index, 0),
1468 prim_mask, i, j);
1469 }
1470 return ac_build_fs_interp_mov(&ctx->ac,
1471 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1472 LLVMConstInt(ctx->i32, chan, 0),
1473 LLVMConstInt(ctx->i32, attr_index, 0),
1474 prim_mask);
1475 }
1476
1477 /**
1478 * Interpolate a fragment shader input.
1479 *
1480 * @param ctx context
1481 * @param input_index index of the input in hardware
1482 * @param semantic_name TGSI_SEMANTIC_*
1483 * @param semantic_index semantic index
1484 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1485 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1486 * @param interp_param interpolation weights (i,j)
1487 * @param prim_mask SI_PARAM_PRIM_MASK
1488 * @param face SI_PARAM_FRONT_FACE
1489 * @param result the return value (4 components)
1490 */
1491 static void interp_fs_input(struct si_shader_context *ctx,
1492 unsigned input_index,
1493 unsigned semantic_name,
1494 unsigned semantic_index,
1495 unsigned num_interp_inputs,
1496 unsigned colors_read_mask,
1497 LLVMValueRef interp_param,
1498 LLVMValueRef prim_mask,
1499 LLVMValueRef face,
1500 LLVMValueRef result[4])
1501 {
1502 LLVMValueRef i = NULL, j = NULL;
1503 unsigned chan;
1504
1505 /* fs.constant returns the param from the middle vertex, so it's not
1506 * really useful for flat shading. It's meant to be used for custom
1507 * interpolation (but the intrinsic can't fetch from the other two
1508 * vertices).
1509 *
1510 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1511 * to do the right thing. The only reason we use fs.constant is that
1512 * fs.interp cannot be used on integers, because they can be equal
1513 * to NaN.
1514 *
1515 * When interp is false we will use fs.constant or for newer llvm,
1516 * amdgcn.interp.mov.
1517 */
1518 bool interp = interp_param != NULL;
1519
1520 if (interp) {
1521 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1522 LLVMVectorType(ctx->f32, 2), "");
1523
1524 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1525 ctx->i32_0, "");
1526 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1527 ctx->i32_1, "");
1528 }
1529
1530 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1531 ctx->shader->key.part.ps.prolog.color_two_side) {
1532 LLVMValueRef is_face_positive;
1533
1534 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1535 * otherwise it's at offset "num_inputs".
1536 */
1537 unsigned back_attr_offset = num_interp_inputs;
1538 if (semantic_index == 1 && colors_read_mask & 0xf)
1539 back_attr_offset += 1;
1540
1541 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1542 face, ctx->i32_0, "");
1543
1544 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1545 LLVMValueRef front, back;
1546
1547 front = si_build_fs_interp(ctx,
1548 input_index, chan,
1549 prim_mask, i, j);
1550 back = si_build_fs_interp(ctx,
1551 back_attr_offset, chan,
1552 prim_mask, i, j);
1553
1554 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1555 is_face_positive,
1556 front,
1557 back,
1558 "");
1559 }
1560 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1561 result[0] = si_build_fs_interp(ctx, input_index,
1562 0, prim_mask, i, j);
1563 result[1] =
1564 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1565 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1566 } else {
1567 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1568 result[chan] = si_build_fs_interp(ctx,
1569 input_index, chan,
1570 prim_mask, i, j);
1571 }
1572 }
1573 }
1574
1575 void si_llvm_load_input_fs(
1576 struct si_shader_context *ctx,
1577 unsigned input_index,
1578 LLVMValueRef out[4])
1579 {
1580 struct lp_build_context *base = &ctx->bld_base.base;
1581 struct si_shader *shader = ctx->shader;
1582 struct tgsi_shader_info *info = &shader->selector->info;
1583 LLVMValueRef main_fn = ctx->main_fn;
1584 LLVMValueRef interp_param = NULL;
1585 int interp_param_idx;
1586 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1587 unsigned semantic_index = info->input_semantic_index[input_index];
1588 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1589 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1590
1591 /* Get colors from input VGPRs (set by the prolog). */
1592 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1593 unsigned colors_read = shader->selector->info.colors_read;
1594 unsigned mask = colors_read >> (semantic_index * 4);
1595 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1596 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1597
1598 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1599 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1600 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1601 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1602 return;
1603 }
1604
1605 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1606 if (interp_param_idx == -1)
1607 return;
1608 else if (interp_param_idx) {
1609 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1610 }
1611
1612 interp_fs_input(ctx, input_index, semantic_name,
1613 semantic_index, 0, /* this param is unused */
1614 shader->selector->info.colors_read, interp_param,
1615 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1616 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1617 &out[0]);
1618 }
1619
1620 static void declare_input_fs(
1621 struct si_shader_context *ctx,
1622 unsigned input_index,
1623 const struct tgsi_full_declaration *decl,
1624 LLVMValueRef out[4])
1625 {
1626 si_llvm_load_input_fs(ctx, input_index, out);
1627 }
1628
1629 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1630 {
1631 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1632 }
1633
1634
1635 /**
1636 * Load a dword from a constant buffer.
1637 */
1638 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1639 LLVMValueRef resource,
1640 LLVMValueRef offset)
1641 {
1642 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1643 0, 0, 0, true, true);
1644 }
1645
1646 static LLVMValueRef load_sample_position(struct si_shader_context *ctx, LLVMValueRef sample_id)
1647 {
1648 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1649 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1650 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1651 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1652
1653 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1654 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1655 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1656
1657 LLVMValueRef pos[4] = {
1658 buffer_load_const(ctx, resource, offset0),
1659 buffer_load_const(ctx, resource, offset1),
1660 LLVMConstReal(ctx->f32, 0),
1661 LLVMConstReal(ctx->f32, 0)
1662 };
1663
1664 return lp_build_gather_values(&ctx->gallivm, pos, 4);
1665 }
1666
1667 void si_load_system_value(struct si_shader_context *ctx,
1668 unsigned index,
1669 const struct tgsi_full_declaration *decl)
1670 {
1671 struct lp_build_context *bld = &ctx->bld_base.base;
1672 LLVMValueRef value = 0;
1673
1674 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
1675
1676 switch (decl->Semantic.Name) {
1677 case TGSI_SEMANTIC_INSTANCEID:
1678 value = ctx->abi.instance_id;
1679 break;
1680
1681 case TGSI_SEMANTIC_VERTEXID:
1682 value = LLVMBuildAdd(ctx->ac.builder,
1683 ctx->abi.vertex_id,
1684 ctx->abi.base_vertex, "");
1685 break;
1686
1687 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1688 /* Unused. Clarify the meaning in indexed vs. non-indexed
1689 * draws if this is ever used again. */
1690 assert(false);
1691 break;
1692
1693 case TGSI_SEMANTIC_BASEVERTEX:
1694 {
1695 /* For non-indexed draws, the base vertex set by the driver
1696 * (for direct draws) or the CP (for indirect draws) is the
1697 * first vertex ID, but GLSL expects 0 to be returned.
1698 */
1699 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
1700 LLVMValueRef indexed;
1701
1702 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1703 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1704
1705 value = LLVMBuildSelect(ctx->ac.builder, indexed,
1706 ctx->abi.base_vertex, ctx->i32_0, "");
1707 break;
1708 }
1709
1710 case TGSI_SEMANTIC_BASEINSTANCE:
1711 value = ctx->abi.start_instance;
1712 break;
1713
1714 case TGSI_SEMANTIC_DRAWID:
1715 value = ctx->abi.draw_id;
1716 break;
1717
1718 case TGSI_SEMANTIC_INVOCATIONID:
1719 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1720 value = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
1721 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1722 value = ctx->abi.gs_invocation_id;
1723 else
1724 assert(!"INVOCATIONID not implemented");
1725 break;
1726
1727 case TGSI_SEMANTIC_POSITION:
1728 {
1729 LLVMValueRef pos[4] = {
1730 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1731 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1732 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
1733 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
1734 LLVMGetParam(ctx->main_fn,
1735 SI_PARAM_POS_W_FLOAT)),
1736 };
1737 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
1738 break;
1739 }
1740
1741 case TGSI_SEMANTIC_FACE:
1742 value = ctx->abi.front_face;
1743 break;
1744
1745 case TGSI_SEMANTIC_SAMPLEID:
1746 value = get_sample_id(ctx);
1747 break;
1748
1749 case TGSI_SEMANTIC_SAMPLEPOS: {
1750 LLVMValueRef pos[4] = {
1751 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1752 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1753 LLVMConstReal(ctx->f32, 0),
1754 LLVMConstReal(ctx->f32, 0)
1755 };
1756 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
1757 TGSI_OPCODE_FRC, pos[0]);
1758 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
1759 TGSI_OPCODE_FRC, pos[1]);
1760 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
1761 break;
1762 }
1763
1764 case TGSI_SEMANTIC_SAMPLEMASK:
1765 /* This can only occur with the OpenGL Core profile, which
1766 * doesn't support smoothing.
1767 */
1768 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1769 break;
1770
1771 case TGSI_SEMANTIC_TESSCOORD:
1772 {
1773 LLVMValueRef coord[4] = {
1774 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1775 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1776 ctx->ac.f32_0,
1777 ctx->ac.f32_0
1778 };
1779
1780 /* For triangles, the vector should be (u, v, 1-u-v). */
1781 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1782 PIPE_PRIM_TRIANGLES)
1783 coord[2] = lp_build_sub(bld, ctx->ac.f32_1,
1784 lp_build_add(bld, coord[0], coord[1]));
1785
1786 value = lp_build_gather_values(&ctx->gallivm, coord, 4);
1787 break;
1788 }
1789
1790 case TGSI_SEMANTIC_VERTICESIN:
1791 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1792 value = unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6);
1793 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1794 value = get_num_tcs_out_vertices(ctx);
1795 else
1796 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1797 break;
1798
1799 case TGSI_SEMANTIC_TESSINNER:
1800 case TGSI_SEMANTIC_TESSOUTER:
1801 {
1802 LLVMValueRef buffer, base, addr;
1803 int param = si_shader_io_get_unique_index_patch(decl->Semantic.Name, 0);
1804
1805 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1806
1807 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1808 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1809 LLVMConstInt(ctx->i32, param, 0));
1810
1811 value = buffer_load(&ctx->bld_base, ctx->f32,
1812 ~0, buffer, base, addr, true);
1813
1814 break;
1815 }
1816
1817 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1818 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1819 {
1820 LLVMValueRef buf, slot, val[4];
1821 int i, offset;
1822
1823 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
1824 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1825 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
1826 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1827
1828 for (i = 0; i < 4; i++)
1829 val[i] = buffer_load_const(ctx, buf,
1830 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
1831 value = lp_build_gather_values(&ctx->gallivm, val, 4);
1832 break;
1833 }
1834
1835 case TGSI_SEMANTIC_PRIMID:
1836 value = get_primitive_id(ctx, 0);
1837 break;
1838
1839 case TGSI_SEMANTIC_GRID_SIZE:
1840 value = LLVMGetParam(ctx->main_fn, ctx->param_grid_size);
1841 break;
1842
1843 case TGSI_SEMANTIC_BLOCK_SIZE:
1844 {
1845 LLVMValueRef values[3];
1846 unsigned i;
1847 unsigned *properties = ctx->shader->selector->info.properties;
1848
1849 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1850 unsigned sizes[3] = {
1851 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1852 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1853 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1854 };
1855
1856 for (i = 0; i < 3; ++i)
1857 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1858
1859 value = lp_build_gather_values(&ctx->gallivm, values, 3);
1860 } else {
1861 value = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1862 }
1863 break;
1864 }
1865
1866 case TGSI_SEMANTIC_BLOCK_ID:
1867 {
1868 LLVMValueRef values[3];
1869
1870 for (int i = 0; i < 3; i++) {
1871 values[i] = ctx->i32_0;
1872 if (ctx->param_block_id[i] >= 0) {
1873 values[i] = LLVMGetParam(ctx->main_fn,
1874 ctx->param_block_id[i]);
1875 }
1876 }
1877 value = lp_build_gather_values(&ctx->gallivm, values, 3);
1878 break;
1879 }
1880
1881 case TGSI_SEMANTIC_THREAD_ID:
1882 value = LLVMGetParam(ctx->main_fn, ctx->param_thread_id);
1883 break;
1884
1885 case TGSI_SEMANTIC_HELPER_INVOCATION:
1886 value = lp_build_intrinsic(ctx->ac.builder,
1887 "llvm.amdgcn.ps.live",
1888 ctx->i1, NULL, 0,
1889 LP_FUNC_ATTR_READNONE);
1890 value = LLVMBuildNot(ctx->ac.builder, value, "");
1891 value = LLVMBuildSExt(ctx->ac.builder, value, ctx->i32, "");
1892 break;
1893
1894 case TGSI_SEMANTIC_SUBGROUP_SIZE:
1895 value = LLVMConstInt(ctx->i32, 64, 0);
1896 break;
1897
1898 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
1899 value = ac_get_thread_id(&ctx->ac);
1900 break;
1901
1902 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
1903 {
1904 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1905 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
1906 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
1907 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
1908 break;
1909 }
1910
1911 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
1912 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
1913 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
1914 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
1915 {
1916 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1917 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
1918 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
1919 /* All bits set except LSB */
1920 value = LLVMConstInt(ctx->i64, -2, 0);
1921 } else {
1922 /* All bits set */
1923 value = LLVMConstInt(ctx->i64, -1, 0);
1924 }
1925 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
1926 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
1927 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
1928 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
1929 value = LLVMBuildNot(ctx->ac.builder, value, "");
1930 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
1931 break;
1932 }
1933
1934 default:
1935 assert(!"unknown system value");
1936 return;
1937 }
1938
1939 ctx->system_values[index] = value;
1940 }
1941
1942 void si_declare_compute_memory(struct si_shader_context *ctx,
1943 const struct tgsi_full_declaration *decl)
1944 {
1945 struct si_shader_selector *sel = ctx->shader->selector;
1946
1947 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1948 LLVMValueRef var;
1949
1950 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1951 assert(decl->Range.First == decl->Range.Last);
1952 assert(!ctx->ac.lds);
1953
1954 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
1955 LLVMArrayType(ctx->i8, sel->local_size),
1956 "compute_lds",
1957 LOCAL_ADDR_SPACE);
1958 LLVMSetAlignment(var, 4);
1959
1960 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
1961 }
1962
1963 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1964 {
1965 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1966 ctx->param_const_and_shader_buffers);
1967
1968 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
1969 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
1970 }
1971
1972 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
1973 {
1974 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1975 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
1976
1977 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
1978 index = LLVMBuildAdd(ctx->ac.builder, index,
1979 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
1980
1981 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
1982 }
1983
1984 static LLVMValueRef
1985 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
1986 {
1987 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1988 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
1989 ctx->param_const_and_shader_buffers);
1990
1991 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
1992 index = LLVMBuildSub(ctx->ac.builder,
1993 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
1994 index, "");
1995
1996 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
1997 }
1998
1999 static LLVMValueRef fetch_constant(
2000 struct lp_build_tgsi_context *bld_base,
2001 const struct tgsi_full_src_register *reg,
2002 enum tgsi_opcode_type type,
2003 unsigned swizzle)
2004 {
2005 struct si_shader_context *ctx = si_shader_context(bld_base);
2006 struct si_shader_selector *sel = ctx->shader->selector;
2007 const struct tgsi_ind_register *ireg = &reg->Indirect;
2008 unsigned buf, idx;
2009
2010 LLVMValueRef addr, bufp;
2011
2012 if (swizzle == LP_CHAN_ALL) {
2013 unsigned chan;
2014 LLVMValueRef values[4];
2015 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2016 values[chan] = fetch_constant(bld_base, reg, type, chan);
2017
2018 return lp_build_gather_values(&ctx->gallivm, values, 4);
2019 }
2020
2021 /* Split 64-bit loads. */
2022 if (tgsi_type_is_64bit(type)) {
2023 LLVMValueRef lo, hi;
2024
2025 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2026 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle + 1);
2027 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2028 lo, hi);
2029 }
2030
2031 idx = reg->Register.Index * 4 + swizzle;
2032 if (reg->Register.Indirect) {
2033 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2034 } else {
2035 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2036 }
2037
2038 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2039 if (sel->info.const_buffers_declared == 1 &&
2040 sel->info.shader_buffers_declared == 0) {
2041 LLVMValueRef ptr =
2042 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2043
2044 /* This enables use of s_load_dword and flat_load_dword for const buffer 0
2045 * loads, and up to x4 load opcode merging. However, it leads to horrible
2046 * code reducing SIMD wave occupancy from 8 to 2 in many cases.
2047 *
2048 * Using s_buffer_load_dword (x1) seems to be the best option right now.
2049 *
2050 * LLVM 5.0 on SI doesn't insert a required s_nop between SALU setting
2051 * a descriptor and s_buffer_load_dword using it, so we can't expand
2052 * the pointer into a full descriptor like below. We have to use
2053 * s_load_dword instead. The only case when LLVM 5.0 would select
2054 * s_buffer_load_dword (that we have to prevent) is when we use use
2055 * a literal offset where we don't need bounds checking.
2056 */
2057 if (ctx->screen->info.chip_class == SI &&
2058 HAVE_LLVM < 0x0600 &&
2059 !reg->Register.Indirect) {
2060 addr = LLVMBuildLShr(ctx->ac.builder, addr, LLVMConstInt(ctx->i32, 2, 0), "");
2061 LLVMValueRef result = ac_build_load_invariant(&ctx->ac, ptr, addr);
2062 return bitcast(bld_base, type, result);
2063 }
2064
2065 /* Do the bounds checking with a descriptor, because
2066 * doing computation and manual bounds checking of 64-bit
2067 * addresses generates horrible VALU code with very high
2068 * VGPR usage and very low SIMD occupancy.
2069 */
2070 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->i64, "");
2071 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ctx->v2i32, "");
2072
2073 LLVMValueRef desc_elems[] = {
2074 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_0, ""),
2075 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_1, ""),
2076 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2077 LLVMConstInt(ctx->i32,
2078 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2079 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2080 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2081 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2082 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2083 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2084 };
2085 LLVMValueRef desc = ac_build_gather_values(&ctx->ac, desc_elems, 4);
2086 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2087 return bitcast(bld_base, type, result);
2088 }
2089
2090 assert(reg->Register.Dimension);
2091 buf = reg->Dimension.Index;
2092
2093 if (reg->Dimension.Indirect) {
2094 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2095 LLVMValueRef index;
2096 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2097 reg->Dimension.Index,
2098 ctx->num_const_buffers);
2099 index = LLVMBuildAdd(ctx->ac.builder, index,
2100 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2101 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2102 } else
2103 bufp = load_const_buffer_desc(ctx, buf);
2104
2105 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2106 }
2107
2108 /* Upper 16 bits must be zero. */
2109 static LLVMValueRef si_llvm_pack_two_int16(struct si_shader_context *ctx,
2110 LLVMValueRef val[2])
2111 {
2112 return LLVMBuildOr(ctx->ac.builder, val[0],
2113 LLVMBuildShl(ctx->ac.builder, val[1],
2114 LLVMConstInt(ctx->i32, 16, 0),
2115 ""), "");
2116 }
2117
2118 /* Upper 16 bits are ignored and will be dropped. */
2119 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct si_shader_context *ctx,
2120 LLVMValueRef val[2])
2121 {
2122 LLVMValueRef v[2] = {
2123 LLVMBuildAnd(ctx->ac.builder, val[0],
2124 LLVMConstInt(ctx->i32, 0xffff, 0), ""),
2125 val[1],
2126 };
2127 return si_llvm_pack_two_int16(ctx, v);
2128 }
2129
2130 /* Initialize arguments for the shader export intrinsic */
2131 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2132 LLVMValueRef *values,
2133 unsigned target,
2134 struct ac_export_args *args)
2135 {
2136 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2137 LLVMBuilderRef builder = ctx->ac.builder;
2138 LLVMValueRef val[4];
2139 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2140 unsigned chan;
2141 bool is_int8, is_int10;
2142
2143 /* Default is 0xf. Adjusted below depending on the format. */
2144 args->enabled_channels = 0xf; /* writemask */
2145
2146 /* Specify whether the EXEC mask represents the valid mask */
2147 args->valid_mask = 0;
2148
2149 /* Specify whether this is the last export */
2150 args->done = 0;
2151
2152 /* Specify the target we are exporting */
2153 args->target = target;
2154
2155 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2156 const struct si_shader_key *key = &ctx->shader->key;
2157 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2158 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2159
2160 assert(cbuf >= 0 && cbuf < 8);
2161 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2162 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2163 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2164 }
2165
2166 args->compr = false;
2167 args->out[0] = f32undef;
2168 args->out[1] = f32undef;
2169 args->out[2] = f32undef;
2170 args->out[3] = f32undef;
2171
2172 switch (spi_shader_col_format) {
2173 case V_028714_SPI_SHADER_ZERO:
2174 args->enabled_channels = 0; /* writemask */
2175 args->target = V_008DFC_SQ_EXP_NULL;
2176 break;
2177
2178 case V_028714_SPI_SHADER_32_R:
2179 args->enabled_channels = 1; /* writemask */
2180 args->out[0] = values[0];
2181 break;
2182
2183 case V_028714_SPI_SHADER_32_GR:
2184 args->enabled_channels = 0x3; /* writemask */
2185 args->out[0] = values[0];
2186 args->out[1] = values[1];
2187 break;
2188
2189 case V_028714_SPI_SHADER_32_AR:
2190 args->enabled_channels = 0x9; /* writemask */
2191 args->out[0] = values[0];
2192 args->out[3] = values[3];
2193 break;
2194
2195 case V_028714_SPI_SHADER_FP16_ABGR:
2196 args->compr = 1; /* COMPR flag */
2197
2198 for (chan = 0; chan < 2; chan++) {
2199 LLVMValueRef pack_args[2] = {
2200 values[2 * chan],
2201 values[2 * chan + 1]
2202 };
2203 LLVMValueRef packed;
2204
2205 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
2206 args->out[chan] = ac_to_float(&ctx->ac, packed);
2207 }
2208 break;
2209
2210 case V_028714_SPI_SHADER_UNORM16_ABGR:
2211 for (chan = 0; chan < 4; chan++) {
2212 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
2213 val[chan] = LLVMBuildFMul(builder, val[chan],
2214 LLVMConstReal(ctx->f32, 65535), "");
2215 val[chan] = LLVMBuildFAdd(builder, val[chan],
2216 LLVMConstReal(ctx->f32, 0.5), "");
2217 val[chan] = LLVMBuildFPToUI(builder, val[chan],
2218 ctx->i32, "");
2219 }
2220
2221 args->compr = 1; /* COMPR flag */
2222 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val));
2223 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val+2));
2224 break;
2225
2226 case V_028714_SPI_SHADER_SNORM16_ABGR:
2227 for (chan = 0; chan < 4; chan++) {
2228 /* Clamp between [-1, 1]. */
2229 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base, TGSI_OPCODE_MIN,
2230 values[chan],
2231 LLVMConstReal(ctx->f32, 1));
2232 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base, TGSI_OPCODE_MAX,
2233 val[chan],
2234 LLVMConstReal(ctx->f32, -1));
2235 /* Convert to a signed integer in [-32767, 32767]. */
2236 val[chan] = LLVMBuildFMul(builder, val[chan],
2237 LLVMConstReal(ctx->f32, 32767), "");
2238 /* If positive, add 0.5, else add -0.5. */
2239 val[chan] = LLVMBuildFAdd(builder, val[chan],
2240 LLVMBuildSelect(builder,
2241 LLVMBuildFCmp(builder, LLVMRealOGE,
2242 val[chan], ctx->ac.f32_0, ""),
2243 LLVMConstReal(ctx->f32, 0.5),
2244 LLVMConstReal(ctx->f32, -0.5), ""), "");
2245 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2246 }
2247
2248 args->compr = 1; /* COMPR flag */
2249 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val));
2250 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val+2));
2251 break;
2252
2253 case V_028714_SPI_SHADER_UINT16_ABGR: {
2254 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2255 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
2256 LLVMValueRef max_alpha =
2257 !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
2258
2259 /* Clamp. */
2260 for (chan = 0; chan < 4; chan++) {
2261 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
2262 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base, TGSI_OPCODE_UMIN,
2263 val[chan],
2264 chan == 3 ? max_alpha : max_rgb);
2265 }
2266
2267 args->compr = 1; /* COMPR flag */
2268 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val));
2269 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val+2));
2270 break;
2271 }
2272
2273 case V_028714_SPI_SHADER_SINT16_ABGR: {
2274 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2275 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
2276 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
2277 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
2278 LLVMValueRef max_alpha =
2279 !is_int10 ? max_rgb : ctx->i32_1;
2280 LLVMValueRef min_alpha =
2281 !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
2282
2283 /* Clamp. */
2284 for (chan = 0; chan < 4; chan++) {
2285 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
2286 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base,
2287 TGSI_OPCODE_IMIN,
2288 val[chan], chan == 3 ? max_alpha : max_rgb);
2289 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base,
2290 TGSI_OPCODE_IMAX,
2291 val[chan], chan == 3 ? min_alpha : min_rgb);
2292 }
2293
2294 args->compr = 1; /* COMPR flag */
2295 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val));
2296 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val+2));
2297 break;
2298 }
2299
2300 case V_028714_SPI_SHADER_32_ABGR:
2301 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2302 break;
2303 }
2304 }
2305
2306 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2307 LLVMValueRef alpha)
2308 {
2309 struct si_shader_context *ctx = si_shader_context(bld_base);
2310
2311 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2312 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2313 [PIPE_FUNC_LESS] = LLVMRealOLT,
2314 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2315 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2316 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2317 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2318 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2319 };
2320 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2321 assert(cond);
2322
2323 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2324 SI_PARAM_ALPHA_REF);
2325 LLVMValueRef alpha_pass =
2326 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2327 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2328 } else {
2329 ac_build_kill_if_false(&ctx->ac, LLVMConstInt(ctx->i1, 0, 0));
2330 }
2331 }
2332
2333 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2334 LLVMValueRef alpha,
2335 unsigned samplemask_param)
2336 {
2337 struct si_shader_context *ctx = si_shader_context(bld_base);
2338 LLVMValueRef coverage;
2339
2340 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2341 coverage = LLVMGetParam(ctx->main_fn,
2342 samplemask_param);
2343 coverage = ac_to_integer(&ctx->ac, coverage);
2344
2345 coverage = lp_build_intrinsic(ctx->ac.builder, "llvm.ctpop.i32",
2346 ctx->i32,
2347 &coverage, 1, LP_FUNC_ATTR_READNONE);
2348
2349 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2350 ctx->f32, "");
2351
2352 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2353 LLVMConstReal(ctx->f32,
2354 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2355
2356 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2357 }
2358
2359 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2360 struct ac_export_args *pos, LLVMValueRef *out_elts)
2361 {
2362 unsigned reg_index;
2363 unsigned chan;
2364 unsigned const_chan;
2365 LLVMValueRef base_elt;
2366 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2367 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2368 SI_VS_CONST_CLIP_PLANES, 0);
2369 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2370
2371 for (reg_index = 0; reg_index < 2; reg_index ++) {
2372 struct ac_export_args *args = &pos[2 + reg_index];
2373
2374 args->out[0] =
2375 args->out[1] =
2376 args->out[2] =
2377 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2378
2379 /* Compute dot products of position and user clip plane vectors */
2380 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2381 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2382 LLVMValueRef addr =
2383 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2384 const_chan) * 4, 0);
2385 base_elt = buffer_load_const(ctx, const_resource,
2386 addr);
2387 args->out[chan] =
2388 lp_build_add(&ctx->bld_base.base, args->out[chan],
2389 lp_build_mul(&ctx->bld_base.base, base_elt,
2390 out_elts[const_chan]));
2391 }
2392 }
2393
2394 args->enabled_channels = 0xf;
2395 args->valid_mask = 0;
2396 args->done = 0;
2397 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2398 args->compr = 0;
2399 }
2400 }
2401
2402 static void si_dump_streamout(struct pipe_stream_output_info *so)
2403 {
2404 unsigned i;
2405
2406 if (so->num_outputs)
2407 fprintf(stderr, "STREAMOUT\n");
2408
2409 for (i = 0; i < so->num_outputs; i++) {
2410 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2411 so->output[i].start_component;
2412 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2413 i, so->output[i].output_buffer,
2414 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2415 so->output[i].register_index,
2416 mask & 1 ? "x" : "",
2417 mask & 2 ? "y" : "",
2418 mask & 4 ? "z" : "",
2419 mask & 8 ? "w" : "");
2420 }
2421 }
2422
2423 static void emit_streamout_output(struct si_shader_context *ctx,
2424 LLVMValueRef const *so_buffers,
2425 LLVMValueRef const *so_write_offsets,
2426 struct pipe_stream_output *stream_out,
2427 struct si_shader_output_values *shader_out)
2428 {
2429 unsigned buf_idx = stream_out->output_buffer;
2430 unsigned start = stream_out->start_component;
2431 unsigned num_comps = stream_out->num_components;
2432 LLVMValueRef out[4];
2433
2434 assert(num_comps && num_comps <= 4);
2435 if (!num_comps || num_comps > 4)
2436 return;
2437
2438 /* Load the output as int. */
2439 for (int j = 0; j < num_comps; j++) {
2440 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2441
2442 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2443 }
2444
2445 /* Pack the output. */
2446 LLVMValueRef vdata = NULL;
2447
2448 switch (num_comps) {
2449 case 1: /* as i32 */
2450 vdata = out[0];
2451 break;
2452 case 2: /* as v2i32 */
2453 case 3: /* as v4i32 (aligned to 4) */
2454 case 4: /* as v4i32 */
2455 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2456 for (int j = 0; j < num_comps; j++) {
2457 vdata = LLVMBuildInsertElement(ctx->ac.builder, vdata, out[j],
2458 LLVMConstInt(ctx->i32, j, 0), "");
2459 }
2460 break;
2461 }
2462
2463 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2464 vdata, num_comps,
2465 so_write_offsets[buf_idx],
2466 ctx->i32_0,
2467 stream_out->dst_offset * 4, 1, 1, true, false);
2468 }
2469
2470 /**
2471 * Write streamout data to buffers for vertex stream @p stream (different
2472 * vertex streams can occur for GS copy shaders).
2473 */
2474 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2475 struct si_shader_output_values *outputs,
2476 unsigned noutput, unsigned stream)
2477 {
2478 struct si_shader_selector *sel = ctx->shader->selector;
2479 struct pipe_stream_output_info *so = &sel->so;
2480 LLVMBuilderRef builder = ctx->ac.builder;
2481 int i;
2482 struct lp_build_if_state if_ctx;
2483
2484 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2485 LLVMValueRef so_vtx_count =
2486 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2487
2488 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2489
2490 /* can_emit = tid < so_vtx_count; */
2491 LLVMValueRef can_emit =
2492 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2493
2494 /* Emit the streamout code conditionally. This actually avoids
2495 * out-of-bounds buffer access. The hw tells us via the SGPR
2496 * (so_vtx_count) which threads are allowed to emit streamout data. */
2497 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2498 {
2499 /* The buffer offset is computed as follows:
2500 * ByteOffset = streamout_offset[buffer_id]*4 +
2501 * (streamout_write_index + thread_id)*stride[buffer_id] +
2502 * attrib_offset
2503 */
2504
2505 LLVMValueRef so_write_index =
2506 LLVMGetParam(ctx->main_fn,
2507 ctx->param_streamout_write_index);
2508
2509 /* Compute (streamout_write_index + thread_id). */
2510 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2511
2512 /* Load the descriptor and compute the write offset for each
2513 * enabled buffer. */
2514 LLVMValueRef so_write_offset[4] = {};
2515 LLVMValueRef so_buffers[4];
2516 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2517 ctx->param_rw_buffers);
2518
2519 for (i = 0; i < 4; i++) {
2520 if (!so->stride[i])
2521 continue;
2522
2523 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2524 SI_VS_STREAMOUT_BUF0 + i, 0);
2525
2526 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2527
2528 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2529 ctx->param_streamout_offset[i]);
2530 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2531
2532 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2533 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2534 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2535 }
2536
2537 /* Write streamout data. */
2538 for (i = 0; i < so->num_outputs; i++) {
2539 unsigned reg = so->output[i].register_index;
2540
2541 if (reg >= noutput)
2542 continue;
2543
2544 if (stream != so->output[i].stream)
2545 continue;
2546
2547 emit_streamout_output(ctx, so_buffers, so_write_offset,
2548 &so->output[i], &outputs[reg]);
2549 }
2550 }
2551 lp_build_endif(&if_ctx);
2552 }
2553
2554 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2555 LLVMValueRef *values)
2556 {
2557 struct ac_export_args args;
2558
2559 si_llvm_init_export_args(ctx, values,
2560 V_008DFC_SQ_EXP_PARAM + index, &args);
2561 ac_build_export(&ctx->ac, &args);
2562 }
2563
2564 static void si_build_param_exports(struct si_shader_context *ctx,
2565 struct si_shader_output_values *outputs,
2566 unsigned noutput)
2567 {
2568 struct si_shader *shader = ctx->shader;
2569 unsigned param_count = 0;
2570
2571 for (unsigned i = 0; i < noutput; i++) {
2572 unsigned semantic_name = outputs[i].semantic_name;
2573 unsigned semantic_index = outputs[i].semantic_index;
2574
2575 if (outputs[i].vertex_stream[0] != 0 &&
2576 outputs[i].vertex_stream[1] != 0 &&
2577 outputs[i].vertex_stream[2] != 0 &&
2578 outputs[i].vertex_stream[3] != 0)
2579 continue;
2580
2581 switch (semantic_name) {
2582 case TGSI_SEMANTIC_LAYER:
2583 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2584 case TGSI_SEMANTIC_CLIPDIST:
2585 case TGSI_SEMANTIC_COLOR:
2586 case TGSI_SEMANTIC_BCOLOR:
2587 case TGSI_SEMANTIC_PRIMID:
2588 case TGSI_SEMANTIC_FOG:
2589 case TGSI_SEMANTIC_TEXCOORD:
2590 case TGSI_SEMANTIC_GENERIC:
2591 break;
2592 default:
2593 continue;
2594 }
2595
2596 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2597 semantic_index < SI_MAX_IO_GENERIC) &&
2598 shader->key.opt.kill_outputs &
2599 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2600 continue;
2601
2602 si_export_param(ctx, param_count, outputs[i].values);
2603
2604 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2605 shader->info.vs_output_param_offset[i] = param_count++;
2606 }
2607
2608 shader->info.nr_param_exports = param_count;
2609 }
2610
2611 /* Generate export instructions for hardware VS shader stage */
2612 static void si_llvm_export_vs(struct si_shader_context *ctx,
2613 struct si_shader_output_values *outputs,
2614 unsigned noutput)
2615 {
2616 struct si_shader *shader = ctx->shader;
2617 struct ac_export_args pos_args[4] = {};
2618 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2619 unsigned pos_idx;
2620 int i;
2621
2622 /* Build position exports. */
2623 for (i = 0; i < noutput; i++) {
2624 switch (outputs[i].semantic_name) {
2625 case TGSI_SEMANTIC_POSITION:
2626 si_llvm_init_export_args(ctx, outputs[i].values,
2627 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2628 break;
2629 case TGSI_SEMANTIC_PSIZE:
2630 psize_value = outputs[i].values[0];
2631 break;
2632 case TGSI_SEMANTIC_LAYER:
2633 layer_value = outputs[i].values[0];
2634 break;
2635 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2636 viewport_index_value = outputs[i].values[0];
2637 break;
2638 case TGSI_SEMANTIC_EDGEFLAG:
2639 edgeflag_value = outputs[i].values[0];
2640 break;
2641 case TGSI_SEMANTIC_CLIPDIST:
2642 if (!shader->key.opt.clip_disable) {
2643 unsigned index = 2 + outputs[i].semantic_index;
2644 si_llvm_init_export_args(ctx, outputs[i].values,
2645 V_008DFC_SQ_EXP_POS + index,
2646 &pos_args[index]);
2647 }
2648 break;
2649 case TGSI_SEMANTIC_CLIPVERTEX:
2650 if (!shader->key.opt.clip_disable) {
2651 si_llvm_emit_clipvertex(ctx, pos_args,
2652 outputs[i].values);
2653 }
2654 break;
2655 }
2656 }
2657
2658 /* We need to add the position output manually if it's missing. */
2659 if (!pos_args[0].out[0]) {
2660 pos_args[0].enabled_channels = 0xf; /* writemask */
2661 pos_args[0].valid_mask = 0; /* EXEC mask */
2662 pos_args[0].done = 0; /* last export? */
2663 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2664 pos_args[0].compr = 0; /* COMPR flag */
2665 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2666 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2667 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2668 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2669 }
2670
2671 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2672 if (shader->selector->info.writes_psize ||
2673 shader->selector->info.writes_edgeflag ||
2674 shader->selector->info.writes_viewport_index ||
2675 shader->selector->info.writes_layer) {
2676 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2677 (shader->selector->info.writes_edgeflag << 1) |
2678 (shader->selector->info.writes_layer << 2);
2679
2680 pos_args[1].valid_mask = 0; /* EXEC mask */
2681 pos_args[1].done = 0; /* last export? */
2682 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2683 pos_args[1].compr = 0; /* COMPR flag */
2684 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2685 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2686 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2687 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2688
2689 if (shader->selector->info.writes_psize)
2690 pos_args[1].out[0] = psize_value;
2691
2692 if (shader->selector->info.writes_edgeflag) {
2693 /* The output is a float, but the hw expects an integer
2694 * with the first bit containing the edge flag. */
2695 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2696 edgeflag_value,
2697 ctx->i32, "");
2698 edgeflag_value = ac_build_umin(&ctx->ac,
2699 edgeflag_value,
2700 ctx->i32_1);
2701
2702 /* The LLVM intrinsic expects a float. */
2703 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2704 }
2705
2706 if (ctx->screen->info.chip_class >= GFX9) {
2707 /* GFX9 has the layer in out.z[10:0] and the viewport
2708 * index in out.z[19:16].
2709 */
2710 if (shader->selector->info.writes_layer)
2711 pos_args[1].out[2] = layer_value;
2712
2713 if (shader->selector->info.writes_viewport_index) {
2714 LLVMValueRef v = viewport_index_value;
2715
2716 v = ac_to_integer(&ctx->ac, v);
2717 v = LLVMBuildShl(ctx->ac.builder, v,
2718 LLVMConstInt(ctx->i32, 16, 0), "");
2719 v = LLVMBuildOr(ctx->ac.builder, v,
2720 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2721 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2722 pos_args[1].enabled_channels |= 1 << 2;
2723 }
2724 } else {
2725 if (shader->selector->info.writes_layer)
2726 pos_args[1].out[2] = layer_value;
2727
2728 if (shader->selector->info.writes_viewport_index) {
2729 pos_args[1].out[3] = viewport_index_value;
2730 pos_args[1].enabled_channels |= 1 << 3;
2731 }
2732 }
2733 }
2734
2735 for (i = 0; i < 4; i++)
2736 if (pos_args[i].out[0])
2737 shader->info.nr_pos_exports++;
2738
2739 pos_idx = 0;
2740 for (i = 0; i < 4; i++) {
2741 if (!pos_args[i].out[0])
2742 continue;
2743
2744 /* Specify the target we are exporting */
2745 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2746
2747 if (pos_idx == shader->info.nr_pos_exports)
2748 /* Specify that this is the last export */
2749 pos_args[i].done = 1;
2750
2751 ac_build_export(&ctx->ac, &pos_args[i]);
2752 }
2753
2754 /* Build parameter exports. */
2755 si_build_param_exports(ctx, outputs, noutput);
2756 }
2757
2758 /**
2759 * Forward all outputs from the vertex shader to the TES. This is only used
2760 * for the fixed function TCS.
2761 */
2762 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2763 {
2764 struct si_shader_context *ctx = si_shader_context(bld_base);
2765 LLVMValueRef invocation_id, buffer, buffer_offset;
2766 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2767 uint64_t inputs;
2768
2769 invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
2770 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
2771 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2772
2773 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
2774 lds_vertex_offset = LLVMBuildMul(ctx->ac.builder, invocation_id,
2775 lds_vertex_stride, "");
2776 lds_base = get_tcs_in_current_patch_offset(ctx);
2777 lds_base = LLVMBuildAdd(ctx->ac.builder, lds_base, lds_vertex_offset, "");
2778
2779 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
2780 while (inputs) {
2781 unsigned i = u_bit_scan64(&inputs);
2782
2783 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2784 LLVMConstInt(ctx->i32, 4 * i, 0),
2785 "");
2786
2787 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2788 get_rel_patch_id(ctx),
2789 invocation_id,
2790 LLVMConstInt(ctx->i32, i, 0));
2791
2792 LLVMValueRef value = lds_load(bld_base, ctx->ac.i32, ~0,
2793 lds_ptr);
2794
2795 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
2796 buffer_offset, 0, 1, 0, true, false);
2797 }
2798 }
2799
2800 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2801 LLVMValueRef rel_patch_id,
2802 LLVMValueRef invocation_id,
2803 LLVMValueRef tcs_out_current_patch_data_offset,
2804 LLVMValueRef invoc0_tf_outer[4],
2805 LLVMValueRef invoc0_tf_inner[2])
2806 {
2807 struct si_shader_context *ctx = si_shader_context(bld_base);
2808 struct si_shader *shader = ctx->shader;
2809 unsigned tess_inner_index, tess_outer_index;
2810 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2811 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2812 unsigned stride, outer_comps, inner_comps, i, offset;
2813 struct lp_build_if_state if_ctx, inner_if_ctx;
2814
2815 /* Add a barrier before loading tess factors from LDS. */
2816 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
2817 si_llvm_emit_barrier(NULL, bld_base, NULL);
2818
2819 /* Do this only for invocation 0, because the tess levels are per-patch,
2820 * not per-vertex.
2821 *
2822 * This can't jump, because invocation 0 executes this. It should
2823 * at least mask out the loads and stores for other invocations.
2824 */
2825 lp_build_if(&if_ctx, &ctx->gallivm,
2826 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2827 invocation_id, ctx->i32_0, ""));
2828
2829 /* Determine the layout of one tess factor element in the buffer. */
2830 switch (shader->key.part.tcs.epilog.prim_mode) {
2831 case PIPE_PRIM_LINES:
2832 stride = 2; /* 2 dwords, 1 vec2 store */
2833 outer_comps = 2;
2834 inner_comps = 0;
2835 break;
2836 case PIPE_PRIM_TRIANGLES:
2837 stride = 4; /* 4 dwords, 1 vec4 store */
2838 outer_comps = 3;
2839 inner_comps = 1;
2840 break;
2841 case PIPE_PRIM_QUADS:
2842 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2843 outer_comps = 4;
2844 inner_comps = 2;
2845 break;
2846 default:
2847 assert(0);
2848 return;
2849 }
2850
2851 for (i = 0; i < 4; i++) {
2852 inner[i] = LLVMGetUndef(ctx->i32);
2853 outer[i] = LLVMGetUndef(ctx->i32);
2854 }
2855
2856 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
2857 /* Tess factors are in VGPRs. */
2858 for (i = 0; i < outer_comps; i++)
2859 outer[i] = out[i] = invoc0_tf_outer[i];
2860 for (i = 0; i < inner_comps; i++)
2861 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
2862 } else {
2863 /* Load tess_inner and tess_outer from LDS.
2864 * Any invocation can write them, so we can't get them from a temporary.
2865 */
2866 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
2867 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
2868
2869 lds_base = tcs_out_current_patch_data_offset;
2870 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2871 LLVMConstInt(ctx->i32,
2872 tess_inner_index * 4, 0), "");
2873 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2874 LLVMConstInt(ctx->i32,
2875 tess_outer_index * 4, 0), "");
2876
2877 for (i = 0; i < outer_comps; i++) {
2878 outer[i] = out[i] =
2879 lds_load(bld_base, ctx->ac.i32, i, lds_outer);
2880 }
2881 for (i = 0; i < inner_comps; i++) {
2882 inner[i] = out[outer_comps+i] =
2883 lds_load(bld_base, ctx->ac.i32, i, lds_inner);
2884 }
2885 }
2886
2887 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2888 /* For isolines, the hardware expects tess factors in the
2889 * reverse order from what GLSL / TGSI specify.
2890 */
2891 LLVMValueRef tmp = out[0];
2892 out[0] = out[1];
2893 out[1] = tmp;
2894 }
2895
2896 /* Convert the outputs to vectors for stores. */
2897 vec0 = lp_build_gather_values(&ctx->gallivm, out, MIN2(stride, 4));
2898 vec1 = NULL;
2899
2900 if (stride > 4)
2901 vec1 = lp_build_gather_values(&ctx->gallivm, out+4, stride - 4);
2902
2903 /* Get the buffer. */
2904 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_factor_addr_base64k);
2905
2906 /* Get the offset. */
2907 tf_base = LLVMGetParam(ctx->main_fn,
2908 ctx->param_tcs_factor_offset);
2909 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2910 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
2911
2912 lp_build_if(&inner_if_ctx, &ctx->gallivm,
2913 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2914 rel_patch_id, ctx->i32_0, ""));
2915
2916 /* Store the dynamic HS control word. */
2917 offset = 0;
2918 if (ctx->screen->info.chip_class <= VI) {
2919 ac_build_buffer_store_dword(&ctx->ac, buffer,
2920 LLVMConstInt(ctx->i32, 0x80000000, 0),
2921 1, ctx->i32_0, tf_base,
2922 offset, 1, 0, true, false);
2923 offset += 4;
2924 }
2925
2926 lp_build_endif(&inner_if_ctx);
2927
2928 /* Store the tessellation factors. */
2929 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2930 MIN2(stride, 4), byteoffset, tf_base,
2931 offset, 1, 0, true, false);
2932 offset += 16;
2933 if (vec1)
2934 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2935 stride - 4, byteoffset, tf_base,
2936 offset, 1, 0, true, false);
2937
2938 /* Store the tess factors into the offchip buffer if TES reads them. */
2939 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
2940 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
2941 LLVMValueRef tf_inner_offset;
2942 unsigned param_outer, param_inner;
2943
2944 buf = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
2945 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2946
2947 param_outer = si_shader_io_get_unique_index_patch(
2948 TGSI_SEMANTIC_TESSOUTER, 0);
2949 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2950 LLVMConstInt(ctx->i32, param_outer, 0));
2951
2952 outer_vec = lp_build_gather_values(&ctx->gallivm, outer,
2953 util_next_power_of_two(outer_comps));
2954
2955 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
2956 outer_comps, tf_outer_offset,
2957 base, 0, 1, 0, true, false);
2958 if (inner_comps) {
2959 param_inner = si_shader_io_get_unique_index_patch(
2960 TGSI_SEMANTIC_TESSINNER, 0);
2961 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2962 LLVMConstInt(ctx->i32, param_inner, 0));
2963
2964 inner_vec = inner_comps == 1 ? inner[0] :
2965 lp_build_gather_values(&ctx->gallivm, inner, inner_comps);
2966 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
2967 inner_comps, tf_inner_offset,
2968 base, 0, 1, 0, true, false);
2969 }
2970 }
2971
2972 lp_build_endif(&if_ctx);
2973 }
2974
2975 static LLVMValueRef
2976 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
2977 unsigned param, unsigned return_index)
2978 {
2979 return LLVMBuildInsertValue(ctx->ac.builder, ret,
2980 LLVMGetParam(ctx->main_fn, param),
2981 return_index, "");
2982 }
2983
2984 static LLVMValueRef
2985 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
2986 unsigned param, unsigned return_index)
2987 {
2988 LLVMBuilderRef builder = ctx->ac.builder;
2989 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
2990
2991 return LLVMBuildInsertValue(builder, ret,
2992 ac_to_float(&ctx->ac, p),
2993 return_index, "");
2994 }
2995
2996 static LLVMValueRef
2997 si_insert_input_ptr_as_2xi32(struct si_shader_context *ctx, LLVMValueRef ret,
2998 unsigned param, unsigned return_index)
2999 {
3000 LLVMBuilderRef builder = ctx->ac.builder;
3001 LLVMValueRef ptr, lo, hi;
3002
3003 ptr = LLVMGetParam(ctx->main_fn, param);
3004 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
3005 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
3006 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
3007 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
3008 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
3009 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
3010 }
3011
3012 /* This only writes the tessellation factor levels. */
3013 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
3014 {
3015 struct si_shader_context *ctx = si_shader_context(bld_base);
3016 LLVMBuilderRef builder = ctx->ac.builder;
3017 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3018
3019 si_copy_tcs_inputs(bld_base);
3020
3021 rel_patch_id = get_rel_patch_id(ctx);
3022 invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
3023 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3024
3025 if (ctx->screen->info.chip_class >= GFX9) {
3026 LLVMBasicBlockRef blocks[2] = {
3027 LLVMGetInsertBlock(builder),
3028 ctx->merged_wrap_if_state.entry_block
3029 };
3030 LLVMValueRef values[2];
3031
3032 lp_build_endif(&ctx->merged_wrap_if_state);
3033
3034 values[0] = rel_patch_id;
3035 values[1] = LLVMGetUndef(ctx->i32);
3036 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3037
3038 values[0] = tf_lds_offset;
3039 values[1] = LLVMGetUndef(ctx->i32);
3040 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3041
3042 values[0] = invocation_id;
3043 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3044 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3045 }
3046
3047 /* Return epilog parameters from this function. */
3048 LLVMValueRef ret = ctx->return_value;
3049 unsigned vgpr;
3050
3051 if (ctx->screen->info.chip_class >= GFX9) {
3052 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3053 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3054 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3055 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3056 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3057 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
3058 /* Tess offchip and tess factor offsets are at the beginning. */
3059 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3060 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3061 vgpr = 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K + 1;
3062 } else {
3063 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3064 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3065 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3066 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3067 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3068 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K);
3069 /* Tess offchip and tess factor offsets are after user SGPRs. */
3070 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3071 GFX6_TCS_NUM_USER_SGPR);
3072 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3073 GFX6_TCS_NUM_USER_SGPR + 1);
3074 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3075 }
3076
3077 /* VGPRs */
3078 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3079 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3080 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3081
3082 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3083 * the invocation_id output does not alias the param_tcs_rel_ids input,
3084 * which saves a V_MOV on gfx9.
3085 */
3086 vgpr += 2;
3087
3088 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3089 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3090
3091 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3092 vgpr++; /* skip the tess factor LDS offset */
3093 for (unsigned i = 0; i < 6; i++) {
3094 LLVMValueRef value =
3095 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3096 value = ac_to_float(&ctx->ac, value);
3097 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3098 }
3099 } else {
3100 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3101 }
3102 ctx->return_value = ret;
3103 }
3104
3105 /* Pass TCS inputs from LS to TCS on GFX9. */
3106 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3107 {
3108 LLVMValueRef ret = ctx->return_value;
3109
3110 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3111 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3112 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3113 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3114
3115 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
3116 8 + SI_SGPR_RW_BUFFERS);
3117 ret = si_insert_input_ptr_as_2xi32(ctx, ret,
3118 ctx->param_bindless_samplers_and_images,
3119 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3120
3121 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3122 8 + SI_SGPR_VS_STATE_BITS);
3123 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3124 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3125 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3126 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3127 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3128 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3129 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3130 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3131 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3132 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
3133
3134 unsigned desc_param = ctx->param_tcs_factor_addr_base64k + 2;
3135 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
3136 8 + GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS);
3137 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
3138 8 + GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES);
3139
3140 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3141 ret = si_insert_input_ret_float(ctx, ret,
3142 ctx->param_tcs_patch_id, vgpr++);
3143 ret = si_insert_input_ret_float(ctx, ret,
3144 ctx->param_tcs_rel_ids, vgpr++);
3145 ctx->return_value = ret;
3146 }
3147
3148 /* Pass GS inputs from ES to GS on GFX9. */
3149 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3150 {
3151 LLVMValueRef ret = ctx->return_value;
3152
3153 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3154 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3155 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3156
3157 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
3158 8 + SI_SGPR_RW_BUFFERS);
3159 ret = si_insert_input_ptr_as_2xi32(ctx, ret,
3160 ctx->param_bindless_samplers_and_images,
3161 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3162
3163 unsigned desc_param = ctx->param_vs_state_bits + 1;
3164 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
3165 8 + GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS);
3166 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
3167 8 + GFX9_SGPR_GS_SAMPLERS_AND_IMAGES);
3168
3169 unsigned vgpr = 8 + GFX9_GS_NUM_USER_SGPR;
3170 for (unsigned i = 0; i < 5; i++) {
3171 unsigned param = ctx->param_gs_vtx01_offset + i;
3172 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3173 }
3174 ctx->return_value = ret;
3175 }
3176
3177 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3178 unsigned max_outputs,
3179 LLVMValueRef *addrs)
3180 {
3181 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3182 struct si_shader *shader = ctx->shader;
3183 struct tgsi_shader_info *info = &shader->selector->info;
3184 unsigned i, chan;
3185 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3186 ctx->param_rel_auto_id);
3187 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3188 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3189 vertex_dw_stride, "");
3190
3191 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3192 * its inputs from it. */
3193 for (i = 0; i < info->num_outputs; i++) {
3194 unsigned name = info->output_semantic_name[i];
3195 unsigned index = info->output_semantic_index[i];
3196
3197 /* The ARB_shader_viewport_layer_array spec contains the
3198 * following issue:
3199 *
3200 * 2) What happens if gl_ViewportIndex or gl_Layer is
3201 * written in the vertex shader and a geometry shader is
3202 * present?
3203 *
3204 * RESOLVED: The value written by the last vertex processing
3205 * stage is used. If the last vertex processing stage
3206 * (vertex, tessellation evaluation or geometry) does not
3207 * statically assign to gl_ViewportIndex or gl_Layer, index
3208 * or layer zero is assumed.
3209 *
3210 * So writes to those outputs in VS-as-LS are simply ignored.
3211 */
3212 if (name == TGSI_SEMANTIC_LAYER ||
3213 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3214 continue;
3215
3216 int param = si_shader_io_get_unique_index(name, index);
3217 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3218 LLVMConstInt(ctx->i32, param * 4, 0), "");
3219
3220 for (chan = 0; chan < 4; chan++) {
3221 if (!(info->output_usagemask[i] & (1 << chan)))
3222 continue;
3223
3224 lds_store(ctx, chan, dw_addr,
3225 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3226 }
3227 }
3228
3229 if (ctx->screen->info.chip_class >= GFX9)
3230 si_set_ls_return_value_for_tcs(ctx);
3231 }
3232
3233 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3234 unsigned max_outputs,
3235 LLVMValueRef *addrs)
3236 {
3237 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3238 struct si_shader *es = ctx->shader;
3239 struct tgsi_shader_info *info = &es->selector->info;
3240 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3241 ctx->param_es2gs_offset);
3242 LLVMValueRef lds_base = NULL;
3243 unsigned chan;
3244 int i;
3245
3246 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3247 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3248 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3249 LLVMValueRef wave_idx = unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3250 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3251 LLVMBuildMul(ctx->ac.builder, wave_idx,
3252 LLVMConstInt(ctx->i32, 64, false), ""), "");
3253 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3254 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3255 }
3256
3257 for (i = 0; i < info->num_outputs; i++) {
3258 int param;
3259
3260 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3261 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3262 continue;
3263
3264 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3265 info->output_semantic_index[i]);
3266
3267 for (chan = 0; chan < 4; chan++) {
3268 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3269 out_val = ac_to_integer(&ctx->ac, out_val);
3270
3271 /* GFX9 has the ESGS ring in LDS. */
3272 if (ctx->screen->info.chip_class >= GFX9) {
3273 lds_store(ctx, param * 4 + chan, lds_base, out_val);
3274 continue;
3275 }
3276
3277 ac_build_buffer_store_dword(&ctx->ac,
3278 ctx->esgs_ring,
3279 out_val, 1, NULL, soffset,
3280 (4 * param + chan) * 4,
3281 1, 1, true, true);
3282 }
3283 }
3284
3285 if (ctx->screen->info.chip_class >= GFX9)
3286 si_set_es_return_value_for_gs(ctx);
3287 }
3288
3289 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3290 {
3291 if (ctx->screen->info.chip_class >= GFX9)
3292 return unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3293 else
3294 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3295 }
3296
3297 static void emit_gs_epilogue(struct si_shader_context *ctx)
3298 {
3299 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3300 si_get_gs_wave_id(ctx));
3301
3302 if (ctx->screen->info.chip_class >= GFX9)
3303 lp_build_endif(&ctx->merged_wrap_if_state);
3304 }
3305
3306 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3307 unsigned max_outputs,
3308 LLVMValueRef *addrs)
3309 {
3310 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3311 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3312
3313 assert(info->num_outputs <= max_outputs);
3314
3315 emit_gs_epilogue(ctx);
3316 }
3317
3318 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3319 {
3320 struct si_shader_context *ctx = si_shader_context(bld_base);
3321 emit_gs_epilogue(ctx);
3322 }
3323
3324 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3325 unsigned max_outputs,
3326 LLVMValueRef *addrs)
3327 {
3328 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3329 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3330 struct si_shader_output_values *outputs = NULL;
3331 int i,j;
3332
3333 assert(!ctx->shader->is_gs_copy_shader);
3334 assert(info->num_outputs <= max_outputs);
3335
3336 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3337
3338 /* Vertex color clamping.
3339 *
3340 * This uses a state constant loaded in a user data SGPR and
3341 * an IF statement is added that clamps all colors if the constant
3342 * is true.
3343 */
3344 if (ctx->type == PIPE_SHADER_VERTEX) {
3345 struct lp_build_if_state if_ctx;
3346 LLVMValueRef cond = NULL;
3347 LLVMValueRef addr, val;
3348
3349 for (i = 0; i < info->num_outputs; i++) {
3350 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3351 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3352 continue;
3353
3354 /* We've found a color. */
3355 if (!cond) {
3356 /* The state is in the first bit of the user SGPR. */
3357 cond = LLVMGetParam(ctx->main_fn,
3358 ctx->param_vs_state_bits);
3359 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3360 ctx->i1, "");
3361 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3362 }
3363
3364 for (j = 0; j < 4; j++) {
3365 addr = addrs[4 * i + j];
3366 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3367 val = ac_build_clamp(&ctx->ac, val);
3368 LLVMBuildStore(ctx->ac.builder, val, addr);
3369 }
3370 }
3371
3372 if (cond)
3373 lp_build_endif(&if_ctx);
3374 }
3375
3376 for (i = 0; i < info->num_outputs; i++) {
3377 outputs[i].semantic_name = info->output_semantic_name[i];
3378 outputs[i].semantic_index = info->output_semantic_index[i];
3379
3380 for (j = 0; j < 4; j++) {
3381 outputs[i].values[j] =
3382 LLVMBuildLoad(ctx->ac.builder,
3383 addrs[4 * i + j],
3384 "");
3385 outputs[i].vertex_stream[j] =
3386 (info->output_streams[i] >> (2 * j)) & 3;
3387 }
3388 }
3389
3390 if (ctx->shader->selector->so.num_outputs)
3391 si_llvm_emit_streamout(ctx, outputs, i, 0);
3392
3393 /* Export PrimitiveID. */
3394 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3395 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3396 outputs[i].semantic_index = 0;
3397 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3398 for (j = 1; j < 4; j++)
3399 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3400
3401 memset(outputs[i].vertex_stream, 0,
3402 sizeof(outputs[i].vertex_stream));
3403 i++;
3404 }
3405
3406 si_llvm_export_vs(ctx, outputs, i);
3407 FREE(outputs);
3408 }
3409
3410 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3411 {
3412 struct si_shader_context *ctx = si_shader_context(bld_base);
3413
3414 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3415 &ctx->outputs[0][0]);
3416 }
3417
3418 struct si_ps_exports {
3419 unsigned num;
3420 struct ac_export_args args[10];
3421 };
3422
3423 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3424 LLVMValueRef depth, LLVMValueRef stencil,
3425 LLVMValueRef samplemask, struct si_ps_exports *exp)
3426 {
3427 struct si_shader_context *ctx = si_shader_context(bld_base);
3428 struct lp_build_context *base = &bld_base->base;
3429 struct ac_export_args args;
3430 unsigned mask = 0;
3431 unsigned format = ac_get_spi_shader_z_format(depth != NULL,
3432 stencil != NULL,
3433 samplemask != NULL);
3434
3435 assert(depth || stencil || samplemask);
3436
3437 args.valid_mask = 1; /* whether the EXEC mask is valid */
3438 args.done = 1; /* DONE bit */
3439
3440 /* Specify the target we are exporting */
3441 args.target = V_008DFC_SQ_EXP_MRTZ;
3442
3443 args.compr = 0; /* COMP flag */
3444 args.out[0] = base->undef; /* R, depth */
3445 args.out[1] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
3446 args.out[2] = base->undef; /* B, sample mask */
3447 args.out[3] = base->undef; /* A, alpha to mask */
3448
3449 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
3450 assert(!depth);
3451 args.compr = 1; /* COMPR flag */
3452
3453 if (stencil) {
3454 /* Stencil should be in X[23:16]. */
3455 stencil = ac_to_integer(&ctx->ac, stencil);
3456 stencil = LLVMBuildShl(ctx->ac.builder, stencil,
3457 LLVMConstInt(ctx->i32, 16, 0), "");
3458 args.out[0] = ac_to_float(&ctx->ac, stencil);
3459 mask |= 0x3;
3460 }
3461 if (samplemask) {
3462 /* SampleMask should be in Y[15:0]. */
3463 args.out[1] = samplemask;
3464 mask |= 0xc;
3465 }
3466 } else {
3467 if (depth) {
3468 args.out[0] = depth;
3469 mask |= 0x1;
3470 }
3471 if (stencil) {
3472 args.out[1] = stencil;
3473 mask |= 0x2;
3474 }
3475 if (samplemask) {
3476 args.out[2] = samplemask;
3477 mask |= 0x4;
3478 }
3479 }
3480
3481 /* SI (except OLAND and HAINAN) has a bug that it only looks
3482 * at the X writemask component. */
3483 if (ctx->screen->info.chip_class == SI &&
3484 ctx->screen->info.family != CHIP_OLAND &&
3485 ctx->screen->info.family != CHIP_HAINAN)
3486 mask |= 0x1;
3487
3488 /* Specify which components to enable */
3489 args.enabled_channels = mask;
3490
3491 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3492 }
3493
3494 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3495 LLVMValueRef *color, unsigned index,
3496 unsigned samplemask_param,
3497 bool is_last, struct si_ps_exports *exp)
3498 {
3499 struct si_shader_context *ctx = si_shader_context(bld_base);
3500 int i;
3501
3502 /* Clamp color */
3503 if (ctx->shader->key.part.ps.epilog.clamp_color)
3504 for (i = 0; i < 4; i++)
3505 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3506
3507 /* Alpha to one */
3508 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3509 color[3] = ctx->ac.f32_1;
3510
3511 /* Alpha test */
3512 if (index == 0 &&
3513 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3514 si_alpha_test(bld_base, color[3]);
3515
3516 /* Line & polygon smoothing */
3517 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3518 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3519 samplemask_param);
3520
3521 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3522 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3523 struct ac_export_args args[8];
3524 int c, last = -1;
3525
3526 /* Get the export arguments, also find out what the last one is. */
3527 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3528 si_llvm_init_export_args(ctx, color,
3529 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3530 if (args[c].enabled_channels)
3531 last = c;
3532 }
3533
3534 /* Emit all exports. */
3535 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3536 if (is_last && last == c) {
3537 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3538 args[c].done = 1; /* DONE bit */
3539 } else if (!args[c].enabled_channels)
3540 continue; /* unnecessary NULL export */
3541
3542 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3543 }
3544 } else {
3545 struct ac_export_args args;
3546
3547 /* Export */
3548 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3549 &args);
3550 if (is_last) {
3551 args.valid_mask = 1; /* whether the EXEC mask is valid */
3552 args.done = 1; /* DONE bit */
3553 } else if (!args.enabled_channels)
3554 return; /* unnecessary NULL export */
3555
3556 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3557 }
3558 }
3559
3560 static void si_emit_ps_exports(struct si_shader_context *ctx,
3561 struct si_ps_exports *exp)
3562 {
3563 for (unsigned i = 0; i < exp->num; i++)
3564 ac_build_export(&ctx->ac, &exp->args[i]);
3565 }
3566
3567 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3568 {
3569 struct si_shader_context *ctx = si_shader_context(bld_base);
3570 struct lp_build_context *base = &bld_base->base;
3571 struct ac_export_args args;
3572
3573 args.enabled_channels = 0x0; /* enabled channels */
3574 args.valid_mask = 1; /* whether the EXEC mask is valid */
3575 args.done = 1; /* DONE bit */
3576 args.target = V_008DFC_SQ_EXP_NULL;
3577 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
3578 args.out[0] = base->undef; /* R */
3579 args.out[1] = base->undef; /* G */
3580 args.out[2] = base->undef; /* B */
3581 args.out[3] = base->undef; /* A */
3582
3583 ac_build_export(&ctx->ac, &args);
3584 }
3585
3586 /**
3587 * Return PS outputs in this order:
3588 *
3589 * v[0:3] = color0.xyzw
3590 * v[4:7] = color1.xyzw
3591 * ...
3592 * vN+0 = Depth
3593 * vN+1 = Stencil
3594 * vN+2 = SampleMask
3595 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3596 *
3597 * The alpha-ref SGPR is returned via its original location.
3598 */
3599 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3600 unsigned max_outputs,
3601 LLVMValueRef *addrs)
3602 {
3603 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3604 struct si_shader *shader = ctx->shader;
3605 struct tgsi_shader_info *info = &shader->selector->info;
3606 LLVMBuilderRef builder = ctx->ac.builder;
3607 unsigned i, j, first_vgpr, vgpr;
3608
3609 LLVMValueRef color[8][4] = {};
3610 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3611 LLVMValueRef ret;
3612
3613 if (ctx->postponed_kill)
3614 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3615
3616 /* Read the output values. */
3617 for (i = 0; i < info->num_outputs; i++) {
3618 unsigned semantic_name = info->output_semantic_name[i];
3619 unsigned semantic_index = info->output_semantic_index[i];
3620
3621 switch (semantic_name) {
3622 case TGSI_SEMANTIC_COLOR:
3623 assert(semantic_index < 8);
3624 for (j = 0; j < 4; j++) {
3625 LLVMValueRef ptr = addrs[4 * i + j];
3626 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3627 color[semantic_index][j] = result;
3628 }
3629 break;
3630 case TGSI_SEMANTIC_POSITION:
3631 depth = LLVMBuildLoad(builder,
3632 addrs[4 * i + 2], "");
3633 break;
3634 case TGSI_SEMANTIC_STENCIL:
3635 stencil = LLVMBuildLoad(builder,
3636 addrs[4 * i + 1], "");
3637 break;
3638 case TGSI_SEMANTIC_SAMPLEMASK:
3639 samplemask = LLVMBuildLoad(builder,
3640 addrs[4 * i + 0], "");
3641 break;
3642 default:
3643 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3644 semantic_name);
3645 }
3646 }
3647
3648 /* Fill the return structure. */
3649 ret = ctx->return_value;
3650
3651 /* Set SGPRs. */
3652 ret = LLVMBuildInsertValue(builder, ret,
3653 ac_to_integer(&ctx->ac,
3654 LLVMGetParam(ctx->main_fn,
3655 SI_PARAM_ALPHA_REF)),
3656 SI_SGPR_ALPHA_REF, "");
3657
3658 /* Set VGPRs */
3659 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3660 for (i = 0; i < ARRAY_SIZE(color); i++) {
3661 if (!color[i][0])
3662 continue;
3663
3664 for (j = 0; j < 4; j++)
3665 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3666 }
3667 if (depth)
3668 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3669 if (stencil)
3670 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3671 if (samplemask)
3672 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3673
3674 /* Add the input sample mask for smoothing at the end. */
3675 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3676 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3677 ret = LLVMBuildInsertValue(builder, ret,
3678 LLVMGetParam(ctx->main_fn,
3679 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3680
3681 ctx->return_value = ret;
3682 }
3683
3684 static void membar_emit(
3685 const struct lp_build_tgsi_action *action,
3686 struct lp_build_tgsi_context *bld_base,
3687 struct lp_build_emit_data *emit_data)
3688 {
3689 struct si_shader_context *ctx = si_shader_context(bld_base);
3690 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3691 unsigned flags = LLVMConstIntGetZExtValue(src0);
3692 unsigned waitcnt = NOOP_WAITCNT;
3693
3694 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3695 waitcnt &= VM_CNT & LGKM_CNT;
3696
3697 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3698 TGSI_MEMBAR_SHADER_BUFFER |
3699 TGSI_MEMBAR_SHADER_IMAGE))
3700 waitcnt &= VM_CNT;
3701
3702 if (flags & TGSI_MEMBAR_SHARED)
3703 waitcnt &= LGKM_CNT;
3704
3705 if (waitcnt != NOOP_WAITCNT)
3706 ac_build_waitcnt(&ctx->ac, waitcnt);
3707 }
3708
3709 static void clock_emit(
3710 const struct lp_build_tgsi_action *action,
3711 struct lp_build_tgsi_context *bld_base,
3712 struct lp_build_emit_data *emit_data)
3713 {
3714 struct si_shader_context *ctx = si_shader_context(bld_base);
3715 LLVMValueRef tmp;
3716
3717 tmp = lp_build_intrinsic(ctx->ac.builder, "llvm.readcyclecounter",
3718 ctx->i64, NULL, 0, 0);
3719 tmp = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->v2i32, "");
3720
3721 emit_data->output[0] =
3722 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3723 emit_data->output[1] =
3724 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3725 }
3726
3727 LLVMTypeRef si_const_array(LLVMTypeRef elem_type, int num_elements)
3728 {
3729 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3730 CONST_ADDR_SPACE);
3731 }
3732
3733 static void si_llvm_emit_ddxy(
3734 const struct lp_build_tgsi_action *action,
3735 struct lp_build_tgsi_context *bld_base,
3736 struct lp_build_emit_data *emit_data)
3737 {
3738 struct si_shader_context *ctx = si_shader_context(bld_base);
3739 unsigned opcode = emit_data->info->opcode;
3740 LLVMValueRef val;
3741 int idx;
3742 unsigned mask;
3743
3744 if (opcode == TGSI_OPCODE_DDX_FINE)
3745 mask = AC_TID_MASK_LEFT;
3746 else if (opcode == TGSI_OPCODE_DDY_FINE)
3747 mask = AC_TID_MASK_TOP;
3748 else
3749 mask = AC_TID_MASK_TOP_LEFT;
3750
3751 /* for DDX we want to next X pixel, DDY next Y pixel. */
3752 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3753
3754 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3755 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3756 emit_data->output[emit_data->chan] = val;
3757 }
3758
3759 /*
3760 * this takes an I,J coordinate pair,
3761 * and works out the X and Y derivatives.
3762 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3763 */
3764 static LLVMValueRef si_llvm_emit_ddxy_interp(
3765 struct lp_build_tgsi_context *bld_base,
3766 LLVMValueRef interp_ij)
3767 {
3768 struct si_shader_context *ctx = si_shader_context(bld_base);
3769 LLVMValueRef result[4], a;
3770 unsigned i;
3771
3772 for (i = 0; i < 2; i++) {
3773 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
3774 LLVMConstInt(ctx->i32, i, 0), "");
3775 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
3776 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
3777 }
3778
3779 return lp_build_gather_values(&ctx->gallivm, result, 4);
3780 }
3781
3782 static void interp_fetch_args(
3783 struct lp_build_tgsi_context *bld_base,
3784 struct lp_build_emit_data *emit_data)
3785 {
3786 struct si_shader_context *ctx = si_shader_context(bld_base);
3787 const struct tgsi_full_instruction *inst = emit_data->inst;
3788
3789 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3790 /* offset is in second src, first two channels */
3791 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3792 emit_data->inst, 1,
3793 TGSI_CHAN_X);
3794 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3795 emit_data->inst, 1,
3796 TGSI_CHAN_Y);
3797 emit_data->arg_count = 2;
3798 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3799 LLVMValueRef sample_position;
3800 LLVMValueRef sample_id;
3801 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3802
3803 /* fetch sample ID, then fetch its sample position,
3804 * and place into first two channels.
3805 */
3806 sample_id = lp_build_emit_fetch(bld_base,
3807 emit_data->inst, 1, TGSI_CHAN_X);
3808 sample_id = ac_to_integer(&ctx->ac, sample_id);
3809
3810 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
3811 * Language 4.50 spec says about interpolateAtSample:
3812 *
3813 * "Returns the value of the input interpolant variable at
3814 * the location of sample number sample. If multisample
3815 * buffers are not available, the input variable will be
3816 * evaluated at the center of the pixel. If sample sample
3817 * does not exist, the position used to interpolate the
3818 * input variable is undefined."
3819 *
3820 * This means that sample_id values outside of the valid are
3821 * in fact valid input, and the usual mechanism for loading the
3822 * sample position doesn't work.
3823 */
3824 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
3825 LLVMValueRef center[4] = {
3826 LLVMConstReal(ctx->f32, 0.5),
3827 LLVMConstReal(ctx->f32, 0.5),
3828 ctx->ac.f32_0,
3829 ctx->ac.f32_0,
3830 };
3831
3832 sample_position = lp_build_gather_values(&ctx->gallivm, center, 4);
3833 } else {
3834 sample_position = load_sample_position(ctx, sample_id);
3835 }
3836
3837 emit_data->args[0] = LLVMBuildExtractElement(ctx->ac.builder,
3838 sample_position,
3839 ctx->i32_0, "");
3840
3841 emit_data->args[0] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[0], halfval, "");
3842 emit_data->args[1] = LLVMBuildExtractElement(ctx->ac.builder,
3843 sample_position,
3844 ctx->i32_1, "");
3845 emit_data->args[1] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[1], halfval, "");
3846 emit_data->arg_count = 2;
3847 }
3848 }
3849
3850 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3851 struct lp_build_tgsi_context *bld_base,
3852 struct lp_build_emit_data *emit_data)
3853 {
3854 struct si_shader_context *ctx = si_shader_context(bld_base);
3855 struct si_shader *shader = ctx->shader;
3856 const struct tgsi_shader_info *info = &shader->selector->info;
3857 LLVMValueRef interp_param;
3858 const struct tgsi_full_instruction *inst = emit_data->inst;
3859 const struct tgsi_full_src_register *input = &inst->Src[0];
3860 int input_base, input_array_size;
3861 int chan;
3862 int i;
3863 LLVMValueRef prim_mask = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
3864 LLVMValueRef array_idx;
3865 int interp_param_idx;
3866 unsigned interp;
3867 unsigned location;
3868
3869 assert(input->Register.File == TGSI_FILE_INPUT);
3870
3871 if (input->Register.Indirect) {
3872 unsigned array_id = input->Indirect.ArrayID;
3873
3874 if (array_id) {
3875 input_base = info->input_array_first[array_id];
3876 input_array_size = info->input_array_last[array_id] - input_base + 1;
3877 } else {
3878 input_base = inst->Src[0].Register.Index;
3879 input_array_size = info->num_inputs - input_base;
3880 }
3881
3882 array_idx = si_get_indirect_index(ctx, &input->Indirect,
3883 1, input->Register.Index - input_base);
3884 } else {
3885 input_base = inst->Src[0].Register.Index;
3886 input_array_size = 1;
3887 array_idx = ctx->i32_0;
3888 }
3889
3890 interp = shader->selector->info.input_interpolate[input_base];
3891
3892 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3893 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3894 location = TGSI_INTERPOLATE_LOC_CENTER;
3895 else
3896 location = TGSI_INTERPOLATE_LOC_CENTROID;
3897
3898 interp_param_idx = lookup_interp_param_index(interp, location);
3899 if (interp_param_idx == -1)
3900 return;
3901 else if (interp_param_idx)
3902 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
3903 else
3904 interp_param = NULL;
3905
3906 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3907 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3908 LLVMValueRef ij_out[2];
3909 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3910
3911 /*
3912 * take the I then J parameters, and the DDX/Y for it, and
3913 * calculate the IJ inputs for the interpolator.
3914 * temp1 = ddx * offset/sample.x + I;
3915 * interp_param.I = ddy * offset/sample.y + temp1;
3916 * temp1 = ddx * offset/sample.x + J;
3917 * interp_param.J = ddy * offset/sample.y + temp1;
3918 */
3919 for (i = 0; i < 2; i++) {
3920 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
3921 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
3922 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
3923 ddxy_out, ix_ll, "");
3924 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
3925 ddxy_out, iy_ll, "");
3926 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
3927 interp_param, ix_ll, "");
3928 LLVMValueRef temp1, temp2;
3929
3930 interp_el = ac_to_float(&ctx->ac, interp_el);
3931
3932 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, emit_data->args[0], "");
3933
3934 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
3935
3936 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, emit_data->args[1], "");
3937
3938 ij_out[i] = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
3939 }
3940 interp_param = lp_build_gather_values(&ctx->gallivm, ij_out, 2);
3941 }
3942
3943 if (interp_param)
3944 interp_param = ac_to_float(&ctx->ac, interp_param);
3945
3946 for (chan = 0; chan < 4; chan++) {
3947 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
3948 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3949
3950 for (unsigned idx = 0; idx < input_array_size; ++idx) {
3951 LLVMValueRef v, i = NULL, j = NULL;
3952
3953 if (interp_param) {
3954 i = LLVMBuildExtractElement(
3955 ctx->ac.builder, interp_param, ctx->i32_0, "");
3956 j = LLVMBuildExtractElement(
3957 ctx->ac.builder, interp_param, ctx->i32_1, "");
3958 }
3959 v = si_build_fs_interp(ctx, input_base + idx, schan,
3960 prim_mask, i, j);
3961
3962 gather = LLVMBuildInsertElement(ctx->ac.builder,
3963 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
3964 }
3965
3966 emit_data->output[chan] = LLVMBuildExtractElement(
3967 ctx->ac.builder, gather, array_idx, "");
3968 }
3969 }
3970
3971 static void vote_all_emit(
3972 const struct lp_build_tgsi_action *action,
3973 struct lp_build_tgsi_context *bld_base,
3974 struct lp_build_emit_data *emit_data)
3975 {
3976 struct si_shader_context *ctx = si_shader_context(bld_base);
3977
3978 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
3979 emit_data->output[emit_data->chan] =
3980 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
3981 }
3982
3983 static void vote_any_emit(
3984 const struct lp_build_tgsi_action *action,
3985 struct lp_build_tgsi_context *bld_base,
3986 struct lp_build_emit_data *emit_data)
3987 {
3988 struct si_shader_context *ctx = si_shader_context(bld_base);
3989
3990 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
3991 emit_data->output[emit_data->chan] =
3992 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
3993 }
3994
3995 static void vote_eq_emit(
3996 const struct lp_build_tgsi_action *action,
3997 struct lp_build_tgsi_context *bld_base,
3998 struct lp_build_emit_data *emit_data)
3999 {
4000 struct si_shader_context *ctx = si_shader_context(bld_base);
4001
4002 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4003 emit_data->output[emit_data->chan] =
4004 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4005 }
4006
4007 static void ballot_emit(
4008 const struct lp_build_tgsi_action *action,
4009 struct lp_build_tgsi_context *bld_base,
4010 struct lp_build_emit_data *emit_data)
4011 {
4012 struct si_shader_context *ctx = si_shader_context(bld_base);
4013 LLVMBuilderRef builder = ctx->ac.builder;
4014 LLVMValueRef tmp;
4015
4016 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4017 tmp = ac_build_ballot(&ctx->ac, tmp);
4018 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4019
4020 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4021 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4022 }
4023
4024 static void read_invoc_fetch_args(
4025 struct lp_build_tgsi_context *bld_base,
4026 struct lp_build_emit_data *emit_data)
4027 {
4028 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4029 0, emit_data->src_chan);
4030
4031 /* Always read the source invocation (= lane) from the X channel. */
4032 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4033 1, TGSI_CHAN_X);
4034 emit_data->arg_count = 2;
4035 }
4036
4037 static void read_lane_emit(
4038 const struct lp_build_tgsi_action *action,
4039 struct lp_build_tgsi_context *bld_base,
4040 struct lp_build_emit_data *emit_data)
4041 {
4042 struct si_shader_context *ctx = si_shader_context(bld_base);
4043
4044 /* We currently have no other way to prevent LLVM from lifting the icmp
4045 * calls to a dominating basic block.
4046 */
4047 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4048
4049 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4050 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4051
4052 emit_data->output[emit_data->chan] =
4053 ac_build_intrinsic(&ctx->ac, action->intr_name,
4054 ctx->i32, emit_data->args, emit_data->arg_count,
4055 AC_FUNC_ATTR_READNONE |
4056 AC_FUNC_ATTR_CONVERGENT);
4057 }
4058
4059 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4060 struct lp_build_emit_data *emit_data)
4061 {
4062 struct si_shader_context *ctx = si_shader_context(bld_base);
4063 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4064 LLVMValueRef imm;
4065 unsigned stream;
4066
4067 assert(src0.File == TGSI_FILE_IMMEDIATE);
4068
4069 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4070 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4071 return stream;
4072 }
4073
4074 /* Emit one vertex from the geometry shader */
4075 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4076 unsigned stream,
4077 LLVMValueRef *addrs)
4078 {
4079 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4080 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4081 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
4082 struct si_shader *shader = ctx->shader;
4083 struct lp_build_if_state if_state;
4084 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4085 ctx->param_gs2vs_offset);
4086 LLVMValueRef gs_next_vertex;
4087 LLVMValueRef can_emit;
4088 unsigned chan, offset;
4089 int i;
4090
4091 /* Write vertex attribute values to GSVS ring */
4092 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4093 ctx->gs_next_vertex[stream],
4094 "");
4095
4096 /* If this thread has already emitted the declared maximum number of
4097 * vertices, skip the write: excessive vertex emissions are not
4098 * supposed to have any effect.
4099 *
4100 * If the shader has no writes to memory, kill it instead. This skips
4101 * further memory loads and may allow LLVM to skip to the end
4102 * altogether.
4103 */
4104 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4105 LLVMConstInt(ctx->i32,
4106 shader->selector->gs_max_out_vertices, 0), "");
4107
4108 bool use_kill = !info->writes_memory;
4109 if (use_kill) {
4110 ac_build_kill_if_false(&ctx->ac, can_emit);
4111 } else {
4112 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4113 }
4114
4115 offset = 0;
4116 for (i = 0; i < info->num_outputs; i++) {
4117 for (chan = 0; chan < 4; chan++) {
4118 if (!(info->output_usagemask[i] & (1 << chan)) ||
4119 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4120 continue;
4121
4122 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4123 LLVMValueRef voffset =
4124 LLVMConstInt(ctx->i32, offset *
4125 shader->selector->gs_max_out_vertices, 0);
4126 offset++;
4127
4128 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4129 voffset = lp_build_mul_imm(uint, voffset, 4);
4130
4131 out_val = ac_to_integer(&ctx->ac, out_val);
4132
4133 ac_build_buffer_store_dword(&ctx->ac,
4134 ctx->gsvs_ring[stream],
4135 out_val, 1,
4136 voffset, soffset, 0,
4137 1, 1, true, true);
4138 }
4139 }
4140
4141 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4142 ctx->i32_1);
4143
4144 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4145
4146 /* Signal vertex emission */
4147 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4148 si_get_gs_wave_id(ctx));
4149 if (!use_kill)
4150 lp_build_endif(&if_state);
4151 }
4152
4153 /* Emit one vertex from the geometry shader */
4154 static void si_tgsi_emit_vertex(
4155 const struct lp_build_tgsi_action *action,
4156 struct lp_build_tgsi_context *bld_base,
4157 struct lp_build_emit_data *emit_data)
4158 {
4159 struct si_shader_context *ctx = si_shader_context(bld_base);
4160 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4161
4162 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4163 }
4164
4165 /* Cut one primitive from the geometry shader */
4166 static void si_llvm_emit_primitive(
4167 const struct lp_build_tgsi_action *action,
4168 struct lp_build_tgsi_context *bld_base,
4169 struct lp_build_emit_data *emit_data)
4170 {
4171 struct si_shader_context *ctx = si_shader_context(bld_base);
4172 unsigned stream;
4173
4174 /* Signal primitive cut */
4175 stream = si_llvm_get_stream(bld_base, emit_data);
4176 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4177 si_get_gs_wave_id(ctx));
4178 }
4179
4180 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4181 struct lp_build_tgsi_context *bld_base,
4182 struct lp_build_emit_data *emit_data)
4183 {
4184 struct si_shader_context *ctx = si_shader_context(bld_base);
4185
4186 /* SI only (thanks to a hw bug workaround):
4187 * The real barrier instruction isn’t needed, because an entire patch
4188 * always fits into a single wave.
4189 */
4190 if (ctx->screen->info.chip_class == SI &&
4191 ctx->type == PIPE_SHADER_TESS_CTRL) {
4192 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
4193 return;
4194 }
4195
4196 lp_build_intrinsic(ctx->ac.builder,
4197 "llvm.amdgcn.s.barrier",
4198 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
4199 }
4200
4201 static const struct lp_build_tgsi_action interp_action = {
4202 .fetch_args = interp_fetch_args,
4203 .emit = build_interp_intrinsic,
4204 };
4205
4206 static void si_create_function(struct si_shader_context *ctx,
4207 const char *name,
4208 LLVMTypeRef *returns, unsigned num_returns,
4209 struct si_function_info *fninfo,
4210 unsigned max_workgroup_size)
4211 {
4212 int i;
4213
4214 si_llvm_create_func(ctx, name, returns, num_returns,
4215 fninfo->types, fninfo->num_params);
4216 ctx->return_value = LLVMGetUndef(ctx->return_type);
4217
4218 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4219 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4220
4221 /* The combination of:
4222 * - ByVal
4223 * - dereferenceable
4224 * - invariant.load
4225 * allows the optimization passes to move loads and reduces
4226 * SGPR spilling significantly.
4227 */
4228 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4229 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
4230 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
4231 ac_add_attr_dereferenceable(P, UINT64_MAX);
4232 } else
4233 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
4234 }
4235
4236 for (i = 0; i < fninfo->num_params; ++i) {
4237 if (fninfo->assign[i])
4238 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4239 }
4240
4241 if (max_workgroup_size) {
4242 si_llvm_add_attribute(ctx->main_fn, "amdgpu-max-work-group-size",
4243 max_workgroup_size);
4244 }
4245 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4246 "no-signed-zeros-fp-math",
4247 "true");
4248
4249 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4250 /* These were copied from some LLVM test. */
4251 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4252 "less-precise-fpmad",
4253 "true");
4254 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4255 "no-infs-fp-math",
4256 "true");
4257 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4258 "no-nans-fp-math",
4259 "true");
4260 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4261 "unsafe-fp-math",
4262 "true");
4263 }
4264 }
4265
4266 static void declare_streamout_params(struct si_shader_context *ctx,
4267 struct pipe_stream_output_info *so,
4268 struct si_function_info *fninfo)
4269 {
4270 int i;
4271
4272 /* Streamout SGPRs. */
4273 if (so->num_outputs) {
4274 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4275 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4276 else
4277 ctx->param_streamout_config = fninfo->num_params - 1;
4278
4279 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4280 }
4281 /* A streamout buffer offset is loaded if the stride is non-zero. */
4282 for (i = 0; i < 4; i++) {
4283 if (!so->stride[i])
4284 continue;
4285
4286 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4287 }
4288 }
4289
4290 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4291 {
4292 switch (shader->selector->type) {
4293 case PIPE_SHADER_TESS_CTRL:
4294 /* Return this so that LLVM doesn't remove s_barrier
4295 * instructions on chips where we use s_barrier. */
4296 return shader->selector->screen->info.chip_class >= CIK ? 128 : 64;
4297
4298 case PIPE_SHADER_GEOMETRY:
4299 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4300
4301 case PIPE_SHADER_COMPUTE:
4302 break; /* see below */
4303
4304 default:
4305 return 0;
4306 }
4307
4308 const unsigned *properties = shader->selector->info.properties;
4309 unsigned max_work_group_size =
4310 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4311 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4312 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4313
4314 if (!max_work_group_size) {
4315 /* This is a variable group size compute shader,
4316 * compile it for the maximum possible group size.
4317 */
4318 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4319 }
4320 return max_work_group_size;
4321 }
4322
4323 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4324 struct si_function_info *fninfo,
4325 bool assign_params)
4326 {
4327 LLVMTypeRef const_shader_buf_type;
4328
4329 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4330 ctx->shader->selector->info.shader_buffers_declared == 0)
4331 const_shader_buf_type = ctx->f32;
4332 else
4333 const_shader_buf_type = ctx->v4i32;
4334
4335 unsigned const_and_shader_buffers =
4336 add_arg(fninfo, ARG_SGPR,
4337 si_const_array(const_shader_buf_type, 0));
4338
4339 unsigned samplers_and_images =
4340 add_arg(fninfo, ARG_SGPR,
4341 si_const_array(ctx->v8i32,
4342 SI_NUM_IMAGES + SI_NUM_SAMPLERS * 2));
4343
4344 if (assign_params) {
4345 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4346 ctx->param_samplers_and_images = samplers_and_images;
4347 }
4348 }
4349
4350 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4351 struct si_function_info *fninfo)
4352 {
4353 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4354 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS));
4355 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4356 si_const_array(ctx->v8i32, 0));
4357 }
4358
4359 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4360 struct si_function_info *fninfo)
4361 {
4362 ctx->param_vertex_buffers = add_arg(fninfo, ARG_SGPR,
4363 si_const_array(ctx->v4i32, SI_NUM_VERTEX_BUFFERS));
4364 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4365 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4366 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4367 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4368 }
4369
4370 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4371 struct si_function_info *fninfo,
4372 unsigned *num_prolog_vgprs)
4373 {
4374 struct si_shader *shader = ctx->shader;
4375
4376 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4377 if (shader->key.as_ls) {
4378 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4379 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4380 } else {
4381 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4382 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4383 }
4384 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4385
4386 if (!shader->is_gs_copy_shader) {
4387 /* Vertex load indices. */
4388 ctx->param_vertex_index0 = fninfo->num_params;
4389 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4390 add_arg(fninfo, ARG_VGPR, ctx->i32);
4391 *num_prolog_vgprs += shader->selector->info.num_inputs;
4392 }
4393 }
4394
4395 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4396 struct si_function_info *fninfo)
4397 {
4398 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4399 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4400 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4401 ctx->param_tes_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4402 }
4403
4404 enum {
4405 /* Convenient merged shader definitions. */
4406 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4407 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4408 };
4409
4410 static void create_function(struct si_shader_context *ctx)
4411 {
4412 struct si_shader *shader = ctx->shader;
4413 struct si_function_info fninfo;
4414 LLVMTypeRef returns[16+32*4];
4415 unsigned i, num_return_sgprs;
4416 unsigned num_returns = 0;
4417 unsigned num_prolog_vgprs = 0;
4418 unsigned type = ctx->type;
4419 unsigned vs_blit_property =
4420 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4421
4422 si_init_function_info(&fninfo);
4423
4424 /* Set MERGED shaders. */
4425 if (ctx->screen->info.chip_class >= GFX9) {
4426 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4427 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4428 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4429 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4430 }
4431
4432 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4433
4434 switch (type) {
4435 case PIPE_SHADER_VERTEX:
4436 declare_global_desc_pointers(ctx, &fninfo);
4437
4438 if (vs_blit_property) {
4439 ctx->param_vs_blit_inputs = fninfo.num_params;
4440 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4441 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4442 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* depth */
4443
4444 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4445 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color0 */
4446 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color1 */
4447 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color2 */
4448 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color3 */
4449 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4450 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4451 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4452 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4453 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4454 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4455 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4456 }
4457
4458 /* VGPRs */
4459 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4460 break;
4461 }
4462
4463 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4464 declare_vs_specific_input_sgprs(ctx, &fninfo);
4465
4466 if (shader->key.as_es) {
4467 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4468 } else if (shader->key.as_ls) {
4469 /* no extra parameters */
4470 } else {
4471 if (shader->is_gs_copy_shader) {
4472 fninfo.num_params = ctx->param_rw_buffers + 1;
4473 fninfo.num_sgpr_params = fninfo.num_params;
4474 }
4475
4476 /* The locations of the other parameters are assigned dynamically. */
4477 declare_streamout_params(ctx, &shader->selector->so,
4478 &fninfo);
4479 }
4480
4481 /* VGPRs */
4482 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4483 break;
4484
4485 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4486 declare_global_desc_pointers(ctx, &fninfo);
4487 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4488 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4489 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4490 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4491 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4492 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4493 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4494 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4495 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4496
4497 /* VGPRs */
4498 ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4499 ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4500
4501 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4502 * placed after the user SGPRs.
4503 */
4504 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4505 returns[num_returns++] = ctx->i32; /* SGPRs */
4506 for (i = 0; i < 11; i++)
4507 returns[num_returns++] = ctx->f32; /* VGPRs */
4508 break;
4509
4510 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4511 /* Merged stages have 8 system SGPRs at the beginning. */
4512 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_LO_HS */
4513 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_HI_HS */
4514 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4515 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4516 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4517 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4518 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4519 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4520
4521 declare_global_desc_pointers(ctx, &fninfo);
4522 declare_per_stage_desc_pointers(ctx, &fninfo,
4523 ctx->type == PIPE_SHADER_VERTEX);
4524 declare_vs_specific_input_sgprs(ctx, &fninfo);
4525
4526 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4527 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4528 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4529 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4530 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4531 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4532
4533 declare_per_stage_desc_pointers(ctx, &fninfo,
4534 ctx->type == PIPE_SHADER_TESS_CTRL);
4535
4536 /* VGPRs (first TCS, then VS) */
4537 ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4538 ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4539
4540 if (ctx->type == PIPE_SHADER_VERTEX) {
4541 declare_vs_input_vgprs(ctx, &fninfo,
4542 &num_prolog_vgprs);
4543
4544 /* LS return values are inputs to the TCS main shader part. */
4545 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4546 returns[num_returns++] = ctx->i32; /* SGPRs */
4547 for (i = 0; i < 2; i++)
4548 returns[num_returns++] = ctx->f32; /* VGPRs */
4549 } else {
4550 /* TCS return values are inputs to the TCS epilog.
4551 *
4552 * param_tcs_offchip_offset, param_tcs_factor_offset,
4553 * param_tcs_offchip_layout, and param_rw_buffers
4554 * should be passed to the epilog.
4555 */
4556 for (i = 0; i <= 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K; i++)
4557 returns[num_returns++] = ctx->i32; /* SGPRs */
4558 for (i = 0; i < 11; i++)
4559 returns[num_returns++] = ctx->f32; /* VGPRs */
4560 }
4561 break;
4562
4563 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4564 /* Merged stages have 8 system SGPRs at the beginning. */
4565 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_LO_GS) */
4566 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_HI_GS) */
4567 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4568 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4569 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4570 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4571 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4572 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4573
4574 declare_global_desc_pointers(ctx, &fninfo);
4575 declare_per_stage_desc_pointers(ctx, &fninfo,
4576 (ctx->type == PIPE_SHADER_VERTEX ||
4577 ctx->type == PIPE_SHADER_TESS_EVAL));
4578 if (ctx->type == PIPE_SHADER_VERTEX) {
4579 declare_vs_specific_input_sgprs(ctx, &fninfo);
4580 } else {
4581 /* TESS_EVAL (and also GEOMETRY):
4582 * Declare as many input SGPRs as the VS has. */
4583 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4584 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4585 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4586 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4587 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4588 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4589 }
4590
4591 declare_per_stage_desc_pointers(ctx, &fninfo,
4592 ctx->type == PIPE_SHADER_GEOMETRY);
4593
4594 /* VGPRs (first GS, then VS/TES) */
4595 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4596 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4597 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4598 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4599 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4600
4601 if (ctx->type == PIPE_SHADER_VERTEX) {
4602 declare_vs_input_vgprs(ctx, &fninfo,
4603 &num_prolog_vgprs);
4604 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4605 declare_tes_input_vgprs(ctx, &fninfo);
4606 }
4607
4608 if (ctx->type == PIPE_SHADER_VERTEX ||
4609 ctx->type == PIPE_SHADER_TESS_EVAL) {
4610 /* ES return values are inputs to GS. */
4611 for (i = 0; i < 8 + GFX9_GS_NUM_USER_SGPR; i++)
4612 returns[num_returns++] = ctx->i32; /* SGPRs */
4613 for (i = 0; i < 5; i++)
4614 returns[num_returns++] = ctx->f32; /* VGPRs */
4615 }
4616 break;
4617
4618 case PIPE_SHADER_TESS_EVAL:
4619 declare_global_desc_pointers(ctx, &fninfo);
4620 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4621 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4622 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4623
4624 if (shader->key.as_es) {
4625 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4626 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4627 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4628 } else {
4629 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4630 declare_streamout_params(ctx, &shader->selector->so,
4631 &fninfo);
4632 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4633 }
4634
4635 /* VGPRs */
4636 declare_tes_input_vgprs(ctx, &fninfo);
4637 break;
4638
4639 case PIPE_SHADER_GEOMETRY:
4640 declare_global_desc_pointers(ctx, &fninfo);
4641 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4642 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4643 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4644
4645 /* VGPRs */
4646 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4647 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4648 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4649 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4650 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4651 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4652 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4653 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4654 break;
4655
4656 case PIPE_SHADER_FRAGMENT:
4657 declare_global_desc_pointers(ctx, &fninfo);
4658 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4659 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4660 add_arg_checked(&fninfo, ARG_SGPR, ctx->i32, SI_PARAM_PRIM_MASK);
4661
4662 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4663 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4664 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4665 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4666 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4667 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4668 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4669 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4670 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4671 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4672 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4673 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4674 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4675 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4676 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4677 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4678 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4679 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4680 shader->info.face_vgpr_index = 20;
4681 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4682 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4683 shader->info.ancillary_vgpr_index = 21;
4684 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4685 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4686 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4687
4688 /* Color inputs from the prolog. */
4689 if (shader->selector->info.colors_read) {
4690 unsigned num_color_elements =
4691 util_bitcount(shader->selector->info.colors_read);
4692
4693 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4694 for (i = 0; i < num_color_elements; i++)
4695 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4696
4697 num_prolog_vgprs += num_color_elements;
4698 }
4699
4700 /* Outputs for the epilog. */
4701 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4702 num_returns =
4703 num_return_sgprs +
4704 util_bitcount(shader->selector->info.colors_written) * 4 +
4705 shader->selector->info.writes_z +
4706 shader->selector->info.writes_stencil +
4707 shader->selector->info.writes_samplemask +
4708 1 /* SampleMaskIn */;
4709
4710 num_returns = MAX2(num_returns,
4711 num_return_sgprs +
4712 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4713
4714 for (i = 0; i < num_return_sgprs; i++)
4715 returns[i] = ctx->i32;
4716 for (; i < num_returns; i++)
4717 returns[i] = ctx->f32;
4718 break;
4719
4720 case PIPE_SHADER_COMPUTE:
4721 declare_global_desc_pointers(ctx, &fninfo);
4722 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4723 if (shader->selector->info.uses_grid_size)
4724 ctx->param_grid_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4725 if (shader->selector->info.uses_block_size)
4726 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4727
4728 for (i = 0; i < 3; i++) {
4729 ctx->param_block_id[i] = -1;
4730 if (shader->selector->info.uses_block_id[i])
4731 ctx->param_block_id[i] = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4732 }
4733
4734 ctx->param_thread_id = add_arg(&fninfo, ARG_VGPR, v3i32);
4735 break;
4736 default:
4737 assert(0 && "unimplemented shader");
4738 return;
4739 }
4740
4741 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4742 si_get_max_workgroup_size(shader));
4743
4744 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4745 if (ctx->type == PIPE_SHADER_FRAGMENT &&
4746 ctx->separate_prolog) {
4747 si_llvm_add_attribute(ctx->main_fn,
4748 "InitialPSInputAddr",
4749 S_0286D0_PERSP_SAMPLE_ENA(1) |
4750 S_0286D0_PERSP_CENTER_ENA(1) |
4751 S_0286D0_PERSP_CENTROID_ENA(1) |
4752 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4753 S_0286D0_LINEAR_CENTER_ENA(1) |
4754 S_0286D0_LINEAR_CENTROID_ENA(1) |
4755 S_0286D0_FRONT_FACE_ENA(1) |
4756 S_0286D0_ANCILLARY_ENA(1) |
4757 S_0286D0_POS_FIXED_PT_ENA(1));
4758 }
4759
4760 shader->info.num_input_sgprs = 0;
4761 shader->info.num_input_vgprs = 0;
4762
4763 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4764 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
4765
4766 for (; i < fninfo.num_params; ++i)
4767 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
4768
4769 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4770 shader->info.num_input_vgprs -= num_prolog_vgprs;
4771
4772 if (shader->key.as_ls ||
4773 ctx->type == PIPE_SHADER_TESS_CTRL ||
4774 /* GFX9 has the ESGS ring buffer in LDS. */
4775 type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY)
4776 ac_declare_lds_as_pointer(&ctx->ac);
4777 }
4778
4779 /**
4780 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4781 * for later use.
4782 */
4783 static void preload_ring_buffers(struct si_shader_context *ctx)
4784 {
4785 LLVMBuilderRef builder = ctx->ac.builder;
4786
4787 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
4788 ctx->param_rw_buffers);
4789
4790 if (ctx->screen->info.chip_class <= VI &&
4791 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
4792 unsigned ring =
4793 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
4794 : SI_ES_RING_ESGS;
4795 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
4796
4797 ctx->esgs_ring =
4798 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4799 }
4800
4801 if (ctx->shader->is_gs_copy_shader) {
4802 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4803
4804 ctx->gsvs_ring[0] =
4805 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4806 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
4807 const struct si_shader_selector *sel = ctx->shader->selector;
4808 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4809 LLVMValueRef base_ring;
4810
4811 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4812
4813 /* The conceptual layout of the GSVS ring is
4814 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4815 * but the real memory layout is swizzled across
4816 * threads:
4817 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4818 * t16v0c0 ..
4819 * Override the buffer descriptor accordingly.
4820 */
4821 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
4822 uint64_t stream_offset = 0;
4823
4824 for (unsigned stream = 0; stream < 4; ++stream) {
4825 unsigned num_components;
4826 unsigned stride;
4827 unsigned num_records;
4828 LLVMValueRef ring, tmp;
4829
4830 num_components = sel->info.num_stream_output_components[stream];
4831 if (!num_components)
4832 continue;
4833
4834 stride = 4 * num_components * sel->gs_max_out_vertices;
4835
4836 /* Limit on the stride field for <= CIK. */
4837 assert(stride < (1 << 14));
4838
4839 num_records = 64;
4840
4841 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
4842 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
4843 tmp = LLVMBuildAdd(builder, tmp,
4844 LLVMConstInt(ctx->i64,
4845 stream_offset, 0), "");
4846 stream_offset += stride * 64;
4847
4848 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
4849 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
4850 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
4851 tmp = LLVMBuildOr(builder, tmp,
4852 LLVMConstInt(ctx->i32,
4853 S_008F04_STRIDE(stride) |
4854 S_008F04_SWIZZLE_ENABLE(1), 0), "");
4855 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
4856 ring = LLVMBuildInsertElement(builder, ring,
4857 LLVMConstInt(ctx->i32, num_records, 0),
4858 LLVMConstInt(ctx->i32, 2, 0), "");
4859 ring = LLVMBuildInsertElement(builder, ring,
4860 LLVMConstInt(ctx->i32,
4861 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4862 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4863 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4864 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
4865 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4866 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
4867 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
4868 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
4869 S_008F0C_ADD_TID_ENABLE(1),
4870 0),
4871 LLVMConstInt(ctx->i32, 3, 0), "");
4872
4873 ctx->gsvs_ring[stream] = ring;
4874 }
4875 }
4876 }
4877
4878 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
4879 LLVMValueRef param_rw_buffers,
4880 unsigned param_pos_fixed_pt)
4881 {
4882 LLVMBuilderRef builder = ctx->ac.builder;
4883 LLVMValueRef slot, desc, offset, row, bit, address[2];
4884
4885 /* Use the fixed-point gl_FragCoord input.
4886 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
4887 * per coordinate to get the repeating effect.
4888 */
4889 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
4890 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
4891
4892 /* Load the buffer descriptor. */
4893 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
4894 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
4895
4896 /* The stipple pattern is 32x32, each row has 32 bits. */
4897 offset = LLVMBuildMul(builder, address[1],
4898 LLVMConstInt(ctx->i32, 4, 0), "");
4899 row = buffer_load_const(ctx, desc, offset);
4900 row = ac_to_integer(&ctx->ac, row);
4901 bit = LLVMBuildLShr(builder, row, address[0], "");
4902 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
4903 ac_build_kill_if_false(&ctx->ac, bit);
4904 }
4905
4906 void si_shader_binary_read_config(struct ac_shader_binary *binary,
4907 struct si_shader_config *conf,
4908 unsigned symbol_offset)
4909 {
4910 unsigned i;
4911 const unsigned char *config =
4912 ac_shader_binary_config_start(binary, symbol_offset);
4913 bool really_needs_scratch = false;
4914
4915 /* LLVM adds SGPR spills to the scratch size.
4916 * Find out if we really need the scratch buffer.
4917 */
4918 for (i = 0; i < binary->reloc_count; i++) {
4919 const struct ac_shader_reloc *reloc = &binary->relocs[i];
4920
4921 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
4922 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4923 really_needs_scratch = true;
4924 break;
4925 }
4926 }
4927
4928 /* XXX: We may be able to emit some of these values directly rather than
4929 * extracting fields to be emitted later.
4930 */
4931
4932 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
4933 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
4934 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
4935 switch (reg) {
4936 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
4937 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
4938 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
4939 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
4940 case R_00B848_COMPUTE_PGM_RSRC1:
4941 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
4942 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
4943 conf->float_mode = G_00B028_FLOAT_MODE(value);
4944 conf->rsrc1 = value;
4945 break;
4946 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
4947 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
4948 break;
4949 case R_00B84C_COMPUTE_PGM_RSRC2:
4950 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
4951 conf->rsrc2 = value;
4952 break;
4953 case R_0286CC_SPI_PS_INPUT_ENA:
4954 conf->spi_ps_input_ena = value;
4955 break;
4956 case R_0286D0_SPI_PS_INPUT_ADDR:
4957 conf->spi_ps_input_addr = value;
4958 break;
4959 case R_0286E8_SPI_TMPRING_SIZE:
4960 case R_00B860_COMPUTE_TMPRING_SIZE:
4961 /* WAVESIZE is in units of 256 dwords. */
4962 if (really_needs_scratch)
4963 conf->scratch_bytes_per_wave =
4964 G_00B860_WAVESIZE(value) * 256 * 4;
4965 break;
4966 case 0x4: /* SPILLED_SGPRS */
4967 conf->spilled_sgprs = value;
4968 break;
4969 case 0x8: /* SPILLED_VGPRS */
4970 conf->spilled_vgprs = value;
4971 break;
4972 default:
4973 {
4974 static bool printed;
4975
4976 if (!printed) {
4977 fprintf(stderr, "Warning: LLVM emitted unknown "
4978 "config register: 0x%x\n", reg);
4979 printed = true;
4980 }
4981 }
4982 break;
4983 }
4984 }
4985
4986 if (!conf->spi_ps_input_addr)
4987 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
4988 }
4989
4990 void si_shader_apply_scratch_relocs(struct si_shader *shader,
4991 uint64_t scratch_va)
4992 {
4993 unsigned i;
4994 uint32_t scratch_rsrc_dword0 = scratch_va;
4995 uint32_t scratch_rsrc_dword1 =
4996 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
4997
4998 /* Enable scratch coalescing. */
4999 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5000
5001 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5002 const struct ac_shader_reloc *reloc =
5003 &shader->binary.relocs[i];
5004 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5005 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5006 &scratch_rsrc_dword0, 4);
5007 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5008 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5009 &scratch_rsrc_dword1, 4);
5010 }
5011 }
5012 }
5013
5014 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
5015 {
5016 unsigned size = shader->binary.code_size;
5017
5018 if (shader->prolog)
5019 size += shader->prolog->binary.code_size;
5020 if (shader->previous_stage)
5021 size += shader->previous_stage->binary.code_size;
5022 if (shader->prolog2)
5023 size += shader->prolog2->binary.code_size;
5024 if (shader->epilog)
5025 size += shader->epilog->binary.code_size;
5026 return size;
5027 }
5028
5029 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5030 {
5031 const struct ac_shader_binary *prolog =
5032 shader->prolog ? &shader->prolog->binary : NULL;
5033 const struct ac_shader_binary *previous_stage =
5034 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5035 const struct ac_shader_binary *prolog2 =
5036 shader->prolog2 ? &shader->prolog2->binary : NULL;
5037 const struct ac_shader_binary *epilog =
5038 shader->epilog ? &shader->epilog->binary : NULL;
5039 const struct ac_shader_binary *mainb = &shader->binary;
5040 unsigned bo_size = si_get_shader_binary_size(shader) +
5041 (!epilog ? mainb->rodata_size : 0);
5042 unsigned char *ptr;
5043
5044 assert(!prolog || !prolog->rodata_size);
5045 assert(!previous_stage || !previous_stage->rodata_size);
5046 assert(!prolog2 || !prolog2->rodata_size);
5047 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5048 !mainb->rodata_size);
5049 assert(!epilog || !epilog->rodata_size);
5050
5051 r600_resource_reference(&shader->bo, NULL);
5052 shader->bo = (struct r600_resource*)
5053 si_aligned_buffer_create(&sscreen->b,
5054 sscreen->cpdma_prefetch_writes_memory ?
5055 0 : R600_RESOURCE_FLAG_READ_ONLY,
5056 PIPE_USAGE_IMMUTABLE,
5057 align(bo_size, SI_CPDMA_ALIGNMENT),
5058 256);
5059 if (!shader->bo)
5060 return -ENOMEM;
5061
5062 /* Upload. */
5063 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5064 PIPE_TRANSFER_READ_WRITE |
5065 PIPE_TRANSFER_UNSYNCHRONIZED);
5066
5067 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5068 * endian-independent. */
5069 if (prolog) {
5070 memcpy(ptr, prolog->code, prolog->code_size);
5071 ptr += prolog->code_size;
5072 }
5073 if (previous_stage) {
5074 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5075 ptr += previous_stage->code_size;
5076 }
5077 if (prolog2) {
5078 memcpy(ptr, prolog2->code, prolog2->code_size);
5079 ptr += prolog2->code_size;
5080 }
5081
5082 memcpy(ptr, mainb->code, mainb->code_size);
5083 ptr += mainb->code_size;
5084
5085 if (epilog)
5086 memcpy(ptr, epilog->code, epilog->code_size);
5087 else if (mainb->rodata_size > 0)
5088 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5089
5090 sscreen->ws->buffer_unmap(shader->bo->buf);
5091 return 0;
5092 }
5093
5094 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5095 struct pipe_debug_callback *debug,
5096 const char *name, FILE *file)
5097 {
5098 char *line, *p;
5099 unsigned i, count;
5100
5101 if (binary->disasm_string) {
5102 fprintf(file, "Shader %s disassembly:\n", name);
5103 fprintf(file, "%s", binary->disasm_string);
5104
5105 if (debug && debug->debug_message) {
5106 /* Very long debug messages are cut off, so send the
5107 * disassembly one line at a time. This causes more
5108 * overhead, but on the plus side it simplifies
5109 * parsing of resulting logs.
5110 */
5111 pipe_debug_message(debug, SHADER_INFO,
5112 "Shader Disassembly Begin");
5113
5114 line = binary->disasm_string;
5115 while (*line) {
5116 p = util_strchrnul(line, '\n');
5117 count = p - line;
5118
5119 if (count) {
5120 pipe_debug_message(debug, SHADER_INFO,
5121 "%.*s", count, line);
5122 }
5123
5124 if (!*p)
5125 break;
5126 line = p + 1;
5127 }
5128
5129 pipe_debug_message(debug, SHADER_INFO,
5130 "Shader Disassembly End");
5131 }
5132 } else {
5133 fprintf(file, "Shader %s binary:\n", name);
5134 for (i = 0; i < binary->code_size; i += 4) {
5135 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5136 binary->code[i + 3], binary->code[i + 2],
5137 binary->code[i + 1], binary->code[i]);
5138 }
5139 }
5140 }
5141
5142 static void si_shader_dump_stats(struct si_screen *sscreen,
5143 const struct si_shader *shader,
5144 struct pipe_debug_callback *debug,
5145 unsigned processor,
5146 FILE *file,
5147 bool check_debug_option)
5148 {
5149 const struct si_shader_config *conf = &shader->config;
5150 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
5151 unsigned code_size = si_get_shader_binary_size(shader);
5152 unsigned lds_increment = sscreen->info.chip_class >= CIK ? 512 : 256;
5153 unsigned lds_per_wave = 0;
5154 unsigned max_simd_waves;
5155
5156 switch (sscreen->info.family) {
5157 /* These always have 8 waves: */
5158 case CHIP_POLARIS10:
5159 case CHIP_POLARIS11:
5160 case CHIP_POLARIS12:
5161 max_simd_waves = 8;
5162 break;
5163 default:
5164 max_simd_waves = 10;
5165 }
5166
5167 /* Compute LDS usage for PS. */
5168 switch (processor) {
5169 case PIPE_SHADER_FRAGMENT:
5170 /* The minimum usage per wave is (num_inputs * 48). The maximum
5171 * usage is (num_inputs * 48 * 16).
5172 * We can get anything in between and it varies between waves.
5173 *
5174 * The 48 bytes per input for a single primitive is equal to
5175 * 4 bytes/component * 4 components/input * 3 points.
5176 *
5177 * Other stages don't know the size at compile time or don't
5178 * allocate LDS per wave, but instead they do it per thread group.
5179 */
5180 lds_per_wave = conf->lds_size * lds_increment +
5181 align(num_inputs * 48, lds_increment);
5182 break;
5183 case PIPE_SHADER_COMPUTE:
5184 if (shader->selector) {
5185 unsigned max_workgroup_size =
5186 si_get_max_workgroup_size(shader);
5187 lds_per_wave = (conf->lds_size * lds_increment) /
5188 DIV_ROUND_UP(max_workgroup_size, 64);
5189 }
5190 break;
5191 }
5192
5193 /* Compute the per-SIMD wave counts. */
5194 if (conf->num_sgprs) {
5195 if (sscreen->info.chip_class >= VI)
5196 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5197 else
5198 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5199 }
5200
5201 if (conf->num_vgprs)
5202 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5203
5204 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5205 * 16KB makes some SIMDs unoccupied). */
5206 if (lds_per_wave)
5207 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5208
5209 if (!check_debug_option ||
5210 si_can_dump_shader(sscreen, processor)) {
5211 if (processor == PIPE_SHADER_FRAGMENT) {
5212 fprintf(file, "*** SHADER CONFIG ***\n"
5213 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5214 "SPI_PS_INPUT_ENA = 0x%04x\n",
5215 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5216 }
5217
5218 fprintf(file, "*** SHADER STATS ***\n"
5219 "SGPRS: %d\n"
5220 "VGPRS: %d\n"
5221 "Spilled SGPRs: %d\n"
5222 "Spilled VGPRs: %d\n"
5223 "Private memory VGPRs: %d\n"
5224 "Code Size: %d bytes\n"
5225 "LDS: %d blocks\n"
5226 "Scratch: %d bytes per wave\n"
5227 "Max Waves: %d\n"
5228 "********************\n\n\n",
5229 conf->num_sgprs, conf->num_vgprs,
5230 conf->spilled_sgprs, conf->spilled_vgprs,
5231 conf->private_mem_vgprs, code_size,
5232 conf->lds_size, conf->scratch_bytes_per_wave,
5233 max_simd_waves);
5234 }
5235
5236 pipe_debug_message(debug, SHADER_INFO,
5237 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5238 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5239 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5240 conf->num_sgprs, conf->num_vgprs, code_size,
5241 conf->lds_size, conf->scratch_bytes_per_wave,
5242 max_simd_waves, conf->spilled_sgprs,
5243 conf->spilled_vgprs, conf->private_mem_vgprs);
5244 }
5245
5246 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5247 {
5248 switch (processor) {
5249 case PIPE_SHADER_VERTEX:
5250 if (shader->key.as_es)
5251 return "Vertex Shader as ES";
5252 else if (shader->key.as_ls)
5253 return "Vertex Shader as LS";
5254 else
5255 return "Vertex Shader as VS";
5256 case PIPE_SHADER_TESS_CTRL:
5257 return "Tessellation Control Shader";
5258 case PIPE_SHADER_TESS_EVAL:
5259 if (shader->key.as_es)
5260 return "Tessellation Evaluation Shader as ES";
5261 else
5262 return "Tessellation Evaluation Shader as VS";
5263 case PIPE_SHADER_GEOMETRY:
5264 if (shader->is_gs_copy_shader)
5265 return "GS Copy Shader as VS";
5266 else
5267 return "Geometry Shader";
5268 case PIPE_SHADER_FRAGMENT:
5269 return "Pixel Shader";
5270 case PIPE_SHADER_COMPUTE:
5271 return "Compute Shader";
5272 default:
5273 return "Unknown Shader";
5274 }
5275 }
5276
5277 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5278 struct pipe_debug_callback *debug, unsigned processor,
5279 FILE *file, bool check_debug_option)
5280 {
5281 if (!check_debug_option ||
5282 si_can_dump_shader(sscreen, processor))
5283 si_dump_shader_key(processor, shader, file);
5284
5285 if (!check_debug_option && shader->binary.llvm_ir_string) {
5286 if (shader->previous_stage &&
5287 shader->previous_stage->binary.llvm_ir_string) {
5288 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5289 si_get_shader_name(shader, processor));
5290 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5291 }
5292
5293 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5294 si_get_shader_name(shader, processor));
5295 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5296 }
5297
5298 if (!check_debug_option ||
5299 (si_can_dump_shader(sscreen, processor) &&
5300 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5301 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5302
5303 if (shader->prolog)
5304 si_shader_dump_disassembly(&shader->prolog->binary,
5305 debug, "prolog", file);
5306 if (shader->previous_stage)
5307 si_shader_dump_disassembly(&shader->previous_stage->binary,
5308 debug, "previous stage", file);
5309 if (shader->prolog2)
5310 si_shader_dump_disassembly(&shader->prolog2->binary,
5311 debug, "prolog2", file);
5312
5313 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5314
5315 if (shader->epilog)
5316 si_shader_dump_disassembly(&shader->epilog->binary,
5317 debug, "epilog", file);
5318 fprintf(file, "\n");
5319 }
5320
5321 si_shader_dump_stats(sscreen, shader, debug, processor, file,
5322 check_debug_option);
5323 }
5324
5325 static int si_compile_llvm(struct si_screen *sscreen,
5326 struct ac_shader_binary *binary,
5327 struct si_shader_config *conf,
5328 LLVMTargetMachineRef tm,
5329 LLVMModuleRef mod,
5330 struct pipe_debug_callback *debug,
5331 unsigned processor,
5332 const char *name)
5333 {
5334 int r = 0;
5335 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5336
5337 if (si_can_dump_shader(sscreen, processor)) {
5338 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5339
5340 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5341 fprintf(stderr, "%s LLVM IR:\n\n", name);
5342 ac_dump_module(mod);
5343 fprintf(stderr, "\n");
5344 }
5345 }
5346
5347 if (sscreen->record_llvm_ir) {
5348 char *ir = LLVMPrintModuleToString(mod);
5349 binary->llvm_ir_string = strdup(ir);
5350 LLVMDisposeMessage(ir);
5351 }
5352
5353 if (!si_replace_shader(count, binary)) {
5354 r = si_llvm_compile(mod, binary, tm, debug);
5355 if (r)
5356 return r;
5357 }
5358
5359 si_shader_binary_read_config(binary, conf, 0);
5360
5361 /* Enable 64-bit and 16-bit denormals, because there is no performance
5362 * cost.
5363 *
5364 * If denormals are enabled, all floating-point output modifiers are
5365 * ignored.
5366 *
5367 * Don't enable denormals for 32-bit floats, because:
5368 * - Floating-point output modifiers would be ignored by the hw.
5369 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5370 * have to stop using those.
5371 * - SI & CI would be very slow.
5372 */
5373 conf->float_mode |= V_00B028_FP_64_DENORMS;
5374
5375 FREE(binary->config);
5376 FREE(binary->global_symbol_offsets);
5377 binary->config = NULL;
5378 binary->global_symbol_offsets = NULL;
5379
5380 /* Some shaders can't have rodata because their binaries can be
5381 * concatenated.
5382 */
5383 if (binary->rodata_size &&
5384 (processor == PIPE_SHADER_VERTEX ||
5385 processor == PIPE_SHADER_TESS_CTRL ||
5386 processor == PIPE_SHADER_TESS_EVAL ||
5387 processor == PIPE_SHADER_FRAGMENT)) {
5388 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5389 return -EINVAL;
5390 }
5391
5392 return r;
5393 }
5394
5395 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5396 {
5397 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5398 LLVMBuildRetVoid(ctx->ac.builder);
5399 else
5400 LLVMBuildRet(ctx->ac.builder, ret);
5401 }
5402
5403 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5404 struct si_shader *
5405 si_generate_gs_copy_shader(struct si_screen *sscreen,
5406 LLVMTargetMachineRef tm,
5407 struct si_shader_selector *gs_selector,
5408 struct pipe_debug_callback *debug)
5409 {
5410 struct si_shader_context ctx;
5411 struct si_shader *shader;
5412 LLVMBuilderRef builder;
5413 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
5414 struct lp_build_context *uint = &bld_base->uint_bld;
5415 struct si_shader_output_values *outputs;
5416 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5417 int i, r;
5418
5419 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5420
5421 if (!outputs)
5422 return NULL;
5423
5424 shader = CALLOC_STRUCT(si_shader);
5425 if (!shader) {
5426 FREE(outputs);
5427 return NULL;
5428 }
5429
5430 /* We can leave the fence as permanently signaled because the GS copy
5431 * shader only becomes visible globally after it has been compiled. */
5432 util_queue_fence_init(&shader->ready);
5433
5434 shader->selector = gs_selector;
5435 shader->is_gs_copy_shader = true;
5436
5437 si_init_shader_ctx(&ctx, sscreen, tm);
5438 ctx.shader = shader;
5439 ctx.type = PIPE_SHADER_VERTEX;
5440
5441 builder = ctx.ac.builder;
5442
5443 create_function(&ctx);
5444 preload_ring_buffers(&ctx);
5445
5446 LLVMValueRef voffset =
5447 lp_build_mul_imm(uint, ctx.abi.vertex_id, 4);
5448
5449 /* Fetch the vertex stream ID.*/
5450 LLVMValueRef stream_id;
5451
5452 if (gs_selector->so.num_outputs)
5453 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5454 else
5455 stream_id = ctx.i32_0;
5456
5457 /* Fill in output information. */
5458 for (i = 0; i < gsinfo->num_outputs; ++i) {
5459 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5460 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5461
5462 for (int chan = 0; chan < 4; chan++) {
5463 outputs[i].vertex_stream[chan] =
5464 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5465 }
5466 }
5467
5468 LLVMBasicBlockRef end_bb;
5469 LLVMValueRef switch_inst;
5470
5471 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5472 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5473
5474 for (int stream = 0; stream < 4; stream++) {
5475 LLVMBasicBlockRef bb;
5476 unsigned offset;
5477
5478 if (!gsinfo->num_stream_output_components[stream])
5479 continue;
5480
5481 if (stream > 0 && !gs_selector->so.num_outputs)
5482 continue;
5483
5484 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5485 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5486 LLVMPositionBuilderAtEnd(builder, bb);
5487
5488 /* Fetch vertex data from GSVS ring */
5489 offset = 0;
5490 for (i = 0; i < gsinfo->num_outputs; ++i) {
5491 for (unsigned chan = 0; chan < 4; chan++) {
5492 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5493 outputs[i].vertex_stream[chan] != stream) {
5494 outputs[i].values[chan] = ctx.bld_base.base.undef;
5495 continue;
5496 }
5497
5498 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5499 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5500 offset++;
5501
5502 outputs[i].values[chan] =
5503 ac_build_buffer_load(&ctx.ac,
5504 ctx.gsvs_ring[0], 1,
5505 ctx.i32_0, voffset,
5506 soffset, 0, 1, 1,
5507 true, false);
5508 }
5509 }
5510
5511 /* Streamout and exports. */
5512 if (gs_selector->so.num_outputs) {
5513 si_llvm_emit_streamout(&ctx, outputs,
5514 gsinfo->num_outputs,
5515 stream);
5516 }
5517
5518 if (stream == 0)
5519 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5520
5521 LLVMBuildBr(builder, end_bb);
5522 }
5523
5524 LLVMPositionBuilderAtEnd(builder, end_bb);
5525
5526 LLVMBuildRetVoid(ctx.ac.builder);
5527
5528 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5529 si_llvm_optimize_module(&ctx);
5530
5531 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5532 &ctx.shader->config, ctx.tm,
5533 ctx.gallivm.module,
5534 debug, PIPE_SHADER_GEOMETRY,
5535 "GS Copy Shader");
5536 if (!r) {
5537 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5538 fprintf(stderr, "GS Copy Shader:\n");
5539 si_shader_dump(sscreen, ctx.shader, debug,
5540 PIPE_SHADER_GEOMETRY, stderr, true);
5541 r = si_shader_binary_upload(sscreen, ctx.shader);
5542 }
5543
5544 si_llvm_dispose(&ctx);
5545
5546 FREE(outputs);
5547
5548 if (r != 0) {
5549 FREE(shader);
5550 shader = NULL;
5551 }
5552 return shader;
5553 }
5554
5555 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5556 const struct si_vs_prolog_bits *prolog,
5557 const char *prefix, FILE *f)
5558 {
5559 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5560 prefix, prolog->instance_divisor_is_one);
5561 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5562 prefix, prolog->instance_divisor_is_fetched);
5563 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5564 prefix, prolog->ls_vgpr_fix);
5565
5566 fprintf(f, " mono.vs.fix_fetch = {");
5567 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5568 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5569 fprintf(f, "}\n");
5570 }
5571
5572 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5573 FILE *f)
5574 {
5575 const struct si_shader_key *key = &shader->key;
5576
5577 fprintf(f, "SHADER KEY\n");
5578
5579 switch (processor) {
5580 case PIPE_SHADER_VERTEX:
5581 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5582 "part.vs.prolog", f);
5583 fprintf(f, " as_es = %u\n", key->as_es);
5584 fprintf(f, " as_ls = %u\n", key->as_ls);
5585 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5586 key->mono.u.vs_export_prim_id);
5587 break;
5588
5589 case PIPE_SHADER_TESS_CTRL:
5590 if (shader->selector->screen->info.chip_class >= GFX9) {
5591 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5592 "part.tcs.ls_prolog", f);
5593 }
5594 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5595 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5596 break;
5597
5598 case PIPE_SHADER_TESS_EVAL:
5599 fprintf(f, " as_es = %u\n", key->as_es);
5600 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5601 key->mono.u.vs_export_prim_id);
5602 break;
5603
5604 case PIPE_SHADER_GEOMETRY:
5605 if (shader->is_gs_copy_shader)
5606 break;
5607
5608 if (shader->selector->screen->info.chip_class >= GFX9 &&
5609 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5610 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5611 "part.gs.vs_prolog", f);
5612 }
5613 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5614 break;
5615
5616 case PIPE_SHADER_COMPUTE:
5617 break;
5618
5619 case PIPE_SHADER_FRAGMENT:
5620 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5621 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5622 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5623 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5624 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5625 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5626 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5627 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5628 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5629 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5630 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5631 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5632 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5633 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5634 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5635 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5636 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5637 break;
5638
5639 default:
5640 assert(0);
5641 }
5642
5643 if ((processor == PIPE_SHADER_GEOMETRY ||
5644 processor == PIPE_SHADER_TESS_EVAL ||
5645 processor == PIPE_SHADER_VERTEX) &&
5646 !key->as_es && !key->as_ls) {
5647 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5648 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5649 }
5650 }
5651
5652 static void si_init_shader_ctx(struct si_shader_context *ctx,
5653 struct si_screen *sscreen,
5654 LLVMTargetMachineRef tm)
5655 {
5656 struct lp_build_tgsi_context *bld_base;
5657
5658 si_llvm_context_init(ctx, sscreen, tm);
5659
5660 bld_base = &ctx->bld_base;
5661 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5662
5663 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5664 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5665 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5666
5667 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5668
5669 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5670
5671 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5672 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5673 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5674 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5675
5676 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5677 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5678 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5679 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5680 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5681 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5682 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5683 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
5684 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5685
5686 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5687 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
5688 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5689 }
5690
5691 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5692 {
5693 struct si_shader *shader = ctx->shader;
5694 struct tgsi_shader_info *info = &shader->selector->info;
5695
5696 if ((ctx->type != PIPE_SHADER_VERTEX &&
5697 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5698 shader->key.as_ls ||
5699 shader->key.as_es)
5700 return;
5701
5702 ac_optimize_vs_outputs(&ctx->ac,
5703 ctx->main_fn,
5704 shader->info.vs_output_param_offset,
5705 info->num_outputs,
5706 &shader->info.nr_param_exports);
5707 }
5708
5709 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
5710 {
5711 ctx->shader->config.private_mem_vgprs = 0;
5712
5713 /* Process all LLVM instructions. */
5714 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
5715 while (bb) {
5716 LLVMValueRef next = LLVMGetFirstInstruction(bb);
5717
5718 while (next) {
5719 LLVMValueRef inst = next;
5720 next = LLVMGetNextInstruction(next);
5721
5722 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
5723 continue;
5724
5725 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
5726 /* No idea why LLVM aligns allocas to 4 elements. */
5727 unsigned alignment = LLVMGetAlignment(inst);
5728 unsigned dw_size = align(ac_get_type_size(type) / 4, alignment);
5729 ctx->shader->config.private_mem_vgprs += dw_size;
5730 }
5731 bb = LLVMGetNextBasicBlock(bb);
5732 }
5733 }
5734
5735 static void si_init_exec_full_mask(struct si_shader_context *ctx)
5736 {
5737 LLVMValueRef full_mask = LLVMConstInt(ctx->i64, ~0ull, 0);
5738 lp_build_intrinsic(ctx->ac.builder,
5739 "llvm.amdgcn.init.exec", ctx->voidt,
5740 &full_mask, 1, LP_FUNC_ATTR_CONVERGENT);
5741 }
5742
5743 static void si_init_exec_from_input(struct si_shader_context *ctx,
5744 unsigned param, unsigned bitoffset)
5745 {
5746 LLVMValueRef args[] = {
5747 LLVMGetParam(ctx->main_fn, param),
5748 LLVMConstInt(ctx->i32, bitoffset, 0),
5749 };
5750 lp_build_intrinsic(ctx->ac.builder,
5751 "llvm.amdgcn.init.exec.from.input",
5752 ctx->voidt, args, 2, LP_FUNC_ATTR_CONVERGENT);
5753 }
5754
5755 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
5756 const struct si_vs_prolog_bits *key)
5757 {
5758 /* VGPR initialization fixup for Vega10 and Raven is always done in the
5759 * VS prolog. */
5760 return sel->vs_needs_prolog || key->ls_vgpr_fix;
5761 }
5762
5763 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
5764 bool is_monolithic)
5765 {
5766 struct si_shader *shader = ctx->shader;
5767 struct si_shader_selector *sel = shader->selector;
5768 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5769
5770 // TODO clean all this up!
5771 switch (ctx->type) {
5772 case PIPE_SHADER_VERTEX:
5773 ctx->load_input = declare_input_vs;
5774 if (shader->key.as_ls)
5775 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
5776 else if (shader->key.as_es)
5777 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5778 else
5779 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5780 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5781 break;
5782 case PIPE_SHADER_TESS_CTRL:
5783 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5784 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5785 bld_base->emit_store = store_output_tcs;
5786 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
5787 break;
5788 case PIPE_SHADER_TESS_EVAL:
5789 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
5790 if (shader->key.as_es)
5791 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5792 else
5793 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5794 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5795 break;
5796 case PIPE_SHADER_GEOMETRY:
5797 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
5798 ctx->abi.load_inputs = si_nir_load_input_gs;
5799 ctx->abi.emit_vertex = si_llvm_emit_vertex;
5800 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
5801 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
5802 break;
5803 case PIPE_SHADER_FRAGMENT:
5804 ctx->load_input = declare_input_fs;
5805 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
5806 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5807 break;
5808 case PIPE_SHADER_COMPUTE:
5809 break;
5810 default:
5811 assert(!"Unsupported shader type");
5812 return false;
5813 }
5814
5815 ctx->abi.load_ubo = load_ubo;
5816 ctx->abi.load_ssbo = load_ssbo;
5817
5818 create_function(ctx);
5819 preload_ring_buffers(ctx);
5820
5821 /* For GFX9 merged shaders:
5822 * - Set EXEC for the first shader. If the prolog is present, set
5823 * EXEC there instead.
5824 * - Add a barrier before the second shader.
5825 * - In the second shader, reset EXEC to ~0 and wrap the main part in
5826 * an if-statement. This is required for correctness in geometry
5827 * shaders, to ensure that empty GS waves do not send GS_EMIT and
5828 * GS_CUT messages.
5829 *
5830 * For monolithic merged shaders, the first shader is wrapped in an
5831 * if-block together with its prolog in si_build_wrapper_function.
5832 */
5833 if (ctx->screen->info.chip_class >= GFX9) {
5834 if (!is_monolithic &&
5835 sel->info.num_instructions > 1 && /* not empty shader */
5836 (shader->key.as_es || shader->key.as_ls) &&
5837 (ctx->type == PIPE_SHADER_TESS_EVAL ||
5838 (ctx->type == PIPE_SHADER_VERTEX &&
5839 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
5840 si_init_exec_from_input(ctx,
5841 ctx->param_merged_wave_info, 0);
5842 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
5843 ctx->type == PIPE_SHADER_GEOMETRY) {
5844 if (!is_monolithic)
5845 si_init_exec_full_mask(ctx);
5846
5847 /* The barrier must execute for all shaders in a
5848 * threadgroup.
5849 */
5850 si_llvm_emit_barrier(NULL, bld_base, NULL);
5851
5852 LLVMValueRef num_threads = unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
5853 LLVMValueRef ena =
5854 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
5855 ac_get_thread_id(&ctx->ac), num_threads, "");
5856 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
5857 }
5858 }
5859
5860 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
5861 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
5862 for (unsigned i = 0; i < 6; i++) {
5863 ctx->invoc0_tess_factors[i] =
5864 lp_build_alloca_undef(&ctx->gallivm, ctx->i32, "");
5865 }
5866 }
5867
5868 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5869 int i;
5870 for (i = 0; i < 4; i++) {
5871 ctx->gs_next_vertex[i] =
5872 lp_build_alloca(&ctx->gallivm,
5873 ctx->i32, "");
5874 }
5875 }
5876
5877 if (sel->force_correct_derivs_after_kill) {
5878 ctx->postponed_kill = lp_build_alloca_undef(&ctx->gallivm, ctx->i1, "");
5879 /* true = don't kill. */
5880 LLVMBuildStore(ctx->ac.builder, LLVMConstInt(ctx->i1, 1, 0),
5881 ctx->postponed_kill);
5882 }
5883
5884 if (sel->tokens) {
5885 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
5886 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
5887 return false;
5888 }
5889 } else {
5890 if (!si_nir_build_llvm(ctx, sel->nir)) {
5891 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
5892 return false;
5893 }
5894 }
5895
5896 si_llvm_build_ret(ctx, ctx->return_value);
5897 return true;
5898 }
5899
5900 /**
5901 * Compute the VS prolog key, which contains all the information needed to
5902 * build the VS prolog function, and set shader->info bits where needed.
5903 *
5904 * \param info Shader info of the vertex shader.
5905 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
5906 * \param prolog_key Key of the VS prolog
5907 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
5908 * \param key Output shader part key.
5909 */
5910 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
5911 unsigned num_input_sgprs,
5912 const struct si_vs_prolog_bits *prolog_key,
5913 struct si_shader *shader_out,
5914 union si_shader_part_key *key)
5915 {
5916 memset(key, 0, sizeof(*key));
5917 key->vs_prolog.states = *prolog_key;
5918 key->vs_prolog.num_input_sgprs = num_input_sgprs;
5919 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
5920 key->vs_prolog.as_ls = shader_out->key.as_ls;
5921 key->vs_prolog.as_es = shader_out->key.as_es;
5922
5923 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
5924 key->vs_prolog.as_ls = 1;
5925 key->vs_prolog.num_merged_next_stage_vgprs = 2;
5926 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
5927 key->vs_prolog.as_es = 1;
5928 key->vs_prolog.num_merged_next_stage_vgprs = 5;
5929 }
5930
5931 /* Enable loading the InstanceID VGPR. */
5932 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
5933
5934 if ((key->vs_prolog.states.instance_divisor_is_one |
5935 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
5936 shader_out->info.uses_instanceid = true;
5937 }
5938
5939 /**
5940 * Compute the PS prolog key, which contains all the information needed to
5941 * build the PS prolog function, and set related bits in shader->config.
5942 */
5943 static void si_get_ps_prolog_key(struct si_shader *shader,
5944 union si_shader_part_key *key,
5945 bool separate_prolog)
5946 {
5947 struct tgsi_shader_info *info = &shader->selector->info;
5948
5949 memset(key, 0, sizeof(*key));
5950 key->ps_prolog.states = shader->key.part.ps.prolog;
5951 key->ps_prolog.colors_read = info->colors_read;
5952 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
5953 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
5954 key->ps_prolog.wqm = info->uses_derivatives &&
5955 (key->ps_prolog.colors_read ||
5956 key->ps_prolog.states.force_persp_sample_interp ||
5957 key->ps_prolog.states.force_linear_sample_interp ||
5958 key->ps_prolog.states.force_persp_center_interp ||
5959 key->ps_prolog.states.force_linear_center_interp ||
5960 key->ps_prolog.states.bc_optimize_for_persp ||
5961 key->ps_prolog.states.bc_optimize_for_linear);
5962 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
5963
5964 if (info->colors_read) {
5965 unsigned *color = shader->selector->color_attr_index;
5966
5967 if (shader->key.part.ps.prolog.color_two_side) {
5968 /* BCOLORs are stored after the last input. */
5969 key->ps_prolog.num_interp_inputs = info->num_inputs;
5970 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
5971 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
5972 }
5973
5974 for (unsigned i = 0; i < 2; i++) {
5975 unsigned interp = info->input_interpolate[color[i]];
5976 unsigned location = info->input_interpolate_loc[color[i]];
5977
5978 if (!(info->colors_read & (0xf << i*4)))
5979 continue;
5980
5981 key->ps_prolog.color_attr_index[i] = color[i];
5982
5983 if (shader->key.part.ps.prolog.flatshade_colors &&
5984 interp == TGSI_INTERPOLATE_COLOR)
5985 interp = TGSI_INTERPOLATE_CONSTANT;
5986
5987 switch (interp) {
5988 case TGSI_INTERPOLATE_CONSTANT:
5989 key->ps_prolog.color_interp_vgpr_index[i] = -1;
5990 break;
5991 case TGSI_INTERPOLATE_PERSPECTIVE:
5992 case TGSI_INTERPOLATE_COLOR:
5993 /* Force the interpolation location for colors here. */
5994 if (shader->key.part.ps.prolog.force_persp_sample_interp)
5995 location = TGSI_INTERPOLATE_LOC_SAMPLE;
5996 if (shader->key.part.ps.prolog.force_persp_center_interp)
5997 location = TGSI_INTERPOLATE_LOC_CENTER;
5998
5999 switch (location) {
6000 case TGSI_INTERPOLATE_LOC_SAMPLE:
6001 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6002 shader->config.spi_ps_input_ena |=
6003 S_0286CC_PERSP_SAMPLE_ENA(1);
6004 break;
6005 case TGSI_INTERPOLATE_LOC_CENTER:
6006 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6007 shader->config.spi_ps_input_ena |=
6008 S_0286CC_PERSP_CENTER_ENA(1);
6009 break;
6010 case TGSI_INTERPOLATE_LOC_CENTROID:
6011 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6012 shader->config.spi_ps_input_ena |=
6013 S_0286CC_PERSP_CENTROID_ENA(1);
6014 break;
6015 default:
6016 assert(0);
6017 }
6018 break;
6019 case TGSI_INTERPOLATE_LINEAR:
6020 /* Force the interpolation location for colors here. */
6021 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6022 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6023 if (shader->key.part.ps.prolog.force_linear_center_interp)
6024 location = TGSI_INTERPOLATE_LOC_CENTER;
6025
6026 /* The VGPR assignment for non-monolithic shaders
6027 * works because InitialPSInputAddr is set on the
6028 * main shader and PERSP_PULL_MODEL is never used.
6029 */
6030 switch (location) {
6031 case TGSI_INTERPOLATE_LOC_SAMPLE:
6032 key->ps_prolog.color_interp_vgpr_index[i] =
6033 separate_prolog ? 6 : 9;
6034 shader->config.spi_ps_input_ena |=
6035 S_0286CC_LINEAR_SAMPLE_ENA(1);
6036 break;
6037 case TGSI_INTERPOLATE_LOC_CENTER:
6038 key->ps_prolog.color_interp_vgpr_index[i] =
6039 separate_prolog ? 8 : 11;
6040 shader->config.spi_ps_input_ena |=
6041 S_0286CC_LINEAR_CENTER_ENA(1);
6042 break;
6043 case TGSI_INTERPOLATE_LOC_CENTROID:
6044 key->ps_prolog.color_interp_vgpr_index[i] =
6045 separate_prolog ? 10 : 13;
6046 shader->config.spi_ps_input_ena |=
6047 S_0286CC_LINEAR_CENTROID_ENA(1);
6048 break;
6049 default:
6050 assert(0);
6051 }
6052 break;
6053 default:
6054 assert(0);
6055 }
6056 }
6057 }
6058 }
6059
6060 /**
6061 * Check whether a PS prolog is required based on the key.
6062 */
6063 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6064 {
6065 return key->ps_prolog.colors_read ||
6066 key->ps_prolog.states.force_persp_sample_interp ||
6067 key->ps_prolog.states.force_linear_sample_interp ||
6068 key->ps_prolog.states.force_persp_center_interp ||
6069 key->ps_prolog.states.force_linear_center_interp ||
6070 key->ps_prolog.states.bc_optimize_for_persp ||
6071 key->ps_prolog.states.bc_optimize_for_linear ||
6072 key->ps_prolog.states.poly_stipple ||
6073 key->ps_prolog.states.samplemask_log_ps_iter;
6074 }
6075
6076 /**
6077 * Compute the PS epilog key, which contains all the information needed to
6078 * build the PS epilog function.
6079 */
6080 static void si_get_ps_epilog_key(struct si_shader *shader,
6081 union si_shader_part_key *key)
6082 {
6083 struct tgsi_shader_info *info = &shader->selector->info;
6084 memset(key, 0, sizeof(*key));
6085 key->ps_epilog.colors_written = info->colors_written;
6086 key->ps_epilog.writes_z = info->writes_z;
6087 key->ps_epilog.writes_stencil = info->writes_stencil;
6088 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6089 key->ps_epilog.states = shader->key.part.ps.epilog;
6090 }
6091
6092 /**
6093 * Build the GS prolog function. Rotate the input vertices for triangle strips
6094 * with adjacency.
6095 */
6096 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6097 union si_shader_part_key *key)
6098 {
6099 unsigned num_sgprs, num_vgprs;
6100 struct si_function_info fninfo;
6101 LLVMBuilderRef builder = ctx->ac.builder;
6102 LLVMTypeRef returns[48];
6103 LLVMValueRef func, ret;
6104
6105 si_init_function_info(&fninfo);
6106
6107 if (ctx->screen->info.chip_class >= GFX9) {
6108 num_sgprs = 8 + GFX9_GS_NUM_USER_SGPR;
6109 num_vgprs = 5; /* ES inputs are not needed by GS */
6110 } else {
6111 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6112 num_vgprs = 8;
6113 }
6114
6115 for (unsigned i = 0; i < num_sgprs; ++i) {
6116 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6117 returns[i] = ctx->i32;
6118 }
6119
6120 for (unsigned i = 0; i < num_vgprs; ++i) {
6121 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6122 returns[num_sgprs + i] = ctx->f32;
6123 }
6124
6125 /* Create the function. */
6126 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6127 &fninfo, 0);
6128 func = ctx->main_fn;
6129
6130 /* Set the full EXEC mask for the prolog, because we are only fiddling
6131 * with registers here. The main shader part will set the correct EXEC
6132 * mask.
6133 */
6134 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6135 si_init_exec_full_mask(ctx);
6136
6137 /* Copy inputs to outputs. This should be no-op, as the registers match,
6138 * but it will prevent the compiler from overwriting them unintentionally.
6139 */
6140 ret = ctx->return_value;
6141 for (unsigned i = 0; i < num_sgprs; i++) {
6142 LLVMValueRef p = LLVMGetParam(func, i);
6143 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6144 }
6145 for (unsigned i = 0; i < num_vgprs; i++) {
6146 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6147 p = ac_to_float(&ctx->ac, p);
6148 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6149 }
6150
6151 if (key->gs_prolog.states.tri_strip_adj_fix) {
6152 /* Remap the input vertices for every other primitive. */
6153 const unsigned gfx6_vtx_params[6] = {
6154 num_sgprs,
6155 num_sgprs + 1,
6156 num_sgprs + 3,
6157 num_sgprs + 4,
6158 num_sgprs + 5,
6159 num_sgprs + 6
6160 };
6161 const unsigned gfx9_vtx_params[3] = {
6162 num_sgprs,
6163 num_sgprs + 1,
6164 num_sgprs + 4,
6165 };
6166 LLVMValueRef vtx_in[6], vtx_out[6];
6167 LLVMValueRef prim_id, rotate;
6168
6169 if (ctx->screen->info.chip_class >= GFX9) {
6170 for (unsigned i = 0; i < 3; i++) {
6171 vtx_in[i*2] = unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6172 vtx_in[i*2+1] = unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6173 }
6174 } else {
6175 for (unsigned i = 0; i < 6; i++)
6176 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6177 }
6178
6179 prim_id = LLVMGetParam(func, num_sgprs + 2);
6180 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6181
6182 for (unsigned i = 0; i < 6; ++i) {
6183 LLVMValueRef base, rotated;
6184 base = vtx_in[i];
6185 rotated = vtx_in[(i + 4) % 6];
6186 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6187 }
6188
6189 if (ctx->screen->info.chip_class >= GFX9) {
6190 for (unsigned i = 0; i < 3; i++) {
6191 LLVMValueRef hi, out;
6192
6193 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6194 LLVMConstInt(ctx->i32, 16, 0), "");
6195 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6196 out = ac_to_float(&ctx->ac, out);
6197 ret = LLVMBuildInsertValue(builder, ret, out,
6198 gfx9_vtx_params[i], "");
6199 }
6200 } else {
6201 for (unsigned i = 0; i < 6; i++) {
6202 LLVMValueRef out;
6203
6204 out = ac_to_float(&ctx->ac, vtx_out[i]);
6205 ret = LLVMBuildInsertValue(builder, ret, out,
6206 gfx6_vtx_params[i], "");
6207 }
6208 }
6209 }
6210
6211 LLVMBuildRet(builder, ret);
6212 }
6213
6214 /**
6215 * Given a list of shader part functions, build a wrapper function that
6216 * runs them in sequence to form a monolithic shader.
6217 */
6218 static void si_build_wrapper_function(struct si_shader_context *ctx,
6219 LLVMValueRef *parts,
6220 unsigned num_parts,
6221 unsigned main_part,
6222 unsigned next_shader_first_part)
6223 {
6224 LLVMBuilderRef builder = ctx->ac.builder;
6225 /* PS epilog has one arg per color component; gfx9 merged shader
6226 * prologs need to forward 32 user SGPRs.
6227 */
6228 struct si_function_info fninfo;
6229 LLVMValueRef initial[64], out[64];
6230 LLVMTypeRef function_type;
6231 unsigned num_first_params;
6232 unsigned num_out, initial_num_out;
6233 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6234 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6235 unsigned num_sgprs, num_vgprs;
6236 unsigned gprs;
6237 struct lp_build_if_state if_state;
6238
6239 si_init_function_info(&fninfo);
6240
6241 for (unsigned i = 0; i < num_parts; ++i) {
6242 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6243 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6244 }
6245
6246 /* The parameters of the wrapper function correspond to those of the
6247 * first part in terms of SGPRs and VGPRs, but we use the types of the
6248 * main part to get the right types. This is relevant for the
6249 * dereferenceable attribute on descriptor table pointers.
6250 */
6251 num_sgprs = 0;
6252 num_vgprs = 0;
6253
6254 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6255 num_first_params = LLVMCountParamTypes(function_type);
6256
6257 for (unsigned i = 0; i < num_first_params; ++i) {
6258 LLVMValueRef param = LLVMGetParam(parts[0], i);
6259
6260 if (ac_is_sgpr_param(param)) {
6261 assert(num_vgprs == 0);
6262 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6263 } else {
6264 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6265 }
6266 }
6267
6268 gprs = 0;
6269 while (gprs < num_sgprs + num_vgprs) {
6270 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6271 LLVMTypeRef type = LLVMTypeOf(param);
6272 unsigned size = ac_get_type_size(type) / 4;
6273
6274 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6275
6276 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6277 assert(gprs + size <= num_sgprs + num_vgprs &&
6278 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6279
6280 gprs += size;
6281 }
6282
6283 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6284 si_get_max_workgroup_size(ctx->shader));
6285
6286 if (is_merged_shader(ctx->shader))
6287 si_init_exec_full_mask(ctx);
6288
6289 /* Record the arguments of the function as if they were an output of
6290 * a previous part.
6291 */
6292 num_out = 0;
6293 num_out_sgpr = 0;
6294
6295 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6296 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6297 LLVMTypeRef param_type = LLVMTypeOf(param);
6298 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6299 unsigned size = ac_get_type_size(param_type) / 4;
6300
6301 if (size == 1) {
6302 if (param_type != out_type)
6303 param = LLVMBuildBitCast(builder, param, out_type, "");
6304 out[num_out++] = param;
6305 } else {
6306 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6307
6308 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6309 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6310 param_type = ctx->i64;
6311 }
6312
6313 if (param_type != vector_type)
6314 param = LLVMBuildBitCast(builder, param, vector_type, "");
6315
6316 for (unsigned j = 0; j < size; ++j)
6317 out[num_out++] = LLVMBuildExtractElement(
6318 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6319 }
6320
6321 if (i < fninfo.num_sgpr_params)
6322 num_out_sgpr = num_out;
6323 }
6324
6325 memcpy(initial, out, sizeof(out));
6326 initial_num_out = num_out;
6327 initial_num_out_sgpr = num_out_sgpr;
6328
6329 /* Now chain the parts. */
6330 for (unsigned part = 0; part < num_parts; ++part) {
6331 LLVMValueRef in[48];
6332 LLVMValueRef ret;
6333 LLVMTypeRef ret_type;
6334 unsigned out_idx = 0;
6335 unsigned num_params = LLVMCountParams(parts[part]);
6336
6337 /* Merged shaders are executed conditionally depending
6338 * on the number of enabled threads passed in the input SGPRs. */
6339 if (is_merged_shader(ctx->shader) && part == 0) {
6340 LLVMValueRef ena, count = initial[3];
6341
6342 count = LLVMBuildAnd(builder, count,
6343 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6344 ena = LLVMBuildICmp(builder, LLVMIntULT,
6345 ac_get_thread_id(&ctx->ac), count, "");
6346 lp_build_if(&if_state, &ctx->gallivm, ena);
6347 }
6348
6349 /* Derive arguments for the next part from outputs of the
6350 * previous one.
6351 */
6352 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6353 LLVMValueRef param;
6354 LLVMTypeRef param_type;
6355 bool is_sgpr;
6356 unsigned param_size;
6357 LLVMValueRef arg = NULL;
6358
6359 param = LLVMGetParam(parts[part], param_idx);
6360 param_type = LLVMTypeOf(param);
6361 param_size = ac_get_type_size(param_type) / 4;
6362 is_sgpr = ac_is_sgpr_param(param);
6363
6364 if (is_sgpr) {
6365 #if HAVE_LLVM < 0x0400
6366 LLVMRemoveAttribute(param, LLVMByValAttribute);
6367 #else
6368 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
6369 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
6370 #endif
6371 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
6372 }
6373
6374 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6375 assert(is_sgpr || out_idx >= num_out_sgpr);
6376
6377 if (param_size == 1)
6378 arg = out[out_idx];
6379 else
6380 arg = lp_build_gather_values(&ctx->gallivm, &out[out_idx], param_size);
6381
6382 if (LLVMTypeOf(arg) != param_type) {
6383 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6384 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6385 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6386 } else {
6387 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6388 }
6389 }
6390
6391 in[param_idx] = arg;
6392 out_idx += param_size;
6393 }
6394
6395 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6396
6397 if (is_merged_shader(ctx->shader) &&
6398 part + 1 == next_shader_first_part) {
6399 lp_build_endif(&if_state);
6400
6401 /* The second half of the merged shader should use
6402 * the inputs from the toplevel (wrapper) function,
6403 * not the return value from the last call.
6404 *
6405 * That's because the last call was executed condi-
6406 * tionally, so we can't consume it in the main
6407 * block.
6408 */
6409 memcpy(out, initial, sizeof(initial));
6410 num_out = initial_num_out;
6411 num_out_sgpr = initial_num_out_sgpr;
6412 continue;
6413 }
6414
6415 /* Extract the returned GPRs. */
6416 ret_type = LLVMTypeOf(ret);
6417 num_out = 0;
6418 num_out_sgpr = 0;
6419
6420 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6421 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6422
6423 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6424
6425 for (unsigned i = 0; i < ret_size; ++i) {
6426 LLVMValueRef val =
6427 LLVMBuildExtractValue(builder, ret, i, "");
6428
6429 assert(num_out < ARRAY_SIZE(out));
6430 out[num_out++] = val;
6431
6432 if (LLVMTypeOf(val) == ctx->i32) {
6433 assert(num_out_sgpr + 1 == num_out);
6434 num_out_sgpr = num_out;
6435 }
6436 }
6437 }
6438 }
6439
6440 LLVMBuildRetVoid(builder);
6441 }
6442
6443 int si_compile_tgsi_shader(struct si_screen *sscreen,
6444 LLVMTargetMachineRef tm,
6445 struct si_shader *shader,
6446 bool is_monolithic,
6447 struct pipe_debug_callback *debug)
6448 {
6449 struct si_shader_selector *sel = shader->selector;
6450 struct si_shader_context ctx;
6451 int r = -1;
6452
6453 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6454 * conversion fails. */
6455 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6456 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6457 if (sel->tokens)
6458 tgsi_dump(sel->tokens, 0);
6459 else
6460 nir_print_shader(sel->nir, stderr);
6461 si_dump_streamout(&sel->so);
6462 }
6463
6464 si_init_shader_ctx(&ctx, sscreen, tm);
6465 si_llvm_context_set_tgsi(&ctx, shader);
6466 ctx.separate_prolog = !is_monolithic;
6467
6468 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6469 sizeof(shader->info.vs_output_param_offset));
6470
6471 shader->info.uses_instanceid = sel->info.uses_instanceid;
6472
6473 if (!si_compile_tgsi_main(&ctx, is_monolithic)) {
6474 si_llvm_dispose(&ctx);
6475 return -1;
6476 }
6477
6478 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6479 LLVMValueRef parts[2];
6480 bool need_prolog = sel->vs_needs_prolog;
6481
6482 parts[1] = ctx.main_fn;
6483
6484 if (need_prolog) {
6485 union si_shader_part_key prolog_key;
6486 si_get_vs_prolog_key(&sel->info,
6487 shader->info.num_input_sgprs,
6488 &shader->key.part.vs.prolog,
6489 shader, &prolog_key);
6490 si_build_vs_prolog_function(&ctx, &prolog_key);
6491 parts[0] = ctx.main_fn;
6492 }
6493
6494 si_build_wrapper_function(&ctx, parts + !need_prolog,
6495 1 + need_prolog, need_prolog, 0);
6496 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6497 if (sscreen->info.chip_class >= GFX9) {
6498 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6499 LLVMValueRef parts[4];
6500 bool vs_needs_prolog =
6501 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6502
6503 /* TCS main part */
6504 parts[2] = ctx.main_fn;
6505
6506 /* TCS epilog */
6507 union si_shader_part_key tcs_epilog_key;
6508 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6509 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6510 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6511 parts[3] = ctx.main_fn;
6512
6513 /* VS prolog */
6514 if (vs_needs_prolog) {
6515 union si_shader_part_key vs_prolog_key;
6516 si_get_vs_prolog_key(&ls->info,
6517 shader->info.num_input_sgprs,
6518 &shader->key.part.tcs.ls_prolog,
6519 shader, &vs_prolog_key);
6520 vs_prolog_key.vs_prolog.is_monolithic = true;
6521 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6522 parts[0] = ctx.main_fn;
6523 }
6524
6525 /* VS as LS main part */
6526 struct si_shader shader_ls = {};
6527 shader_ls.selector = ls;
6528 shader_ls.key.as_ls = 1;
6529 shader_ls.key.mono = shader->key.mono;
6530 shader_ls.key.opt = shader->key.opt;
6531 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6532
6533 if (!si_compile_tgsi_main(&ctx, true)) {
6534 si_llvm_dispose(&ctx);
6535 return -1;
6536 }
6537 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6538 parts[1] = ctx.main_fn;
6539
6540 /* Reset the shader context. */
6541 ctx.shader = shader;
6542 ctx.type = PIPE_SHADER_TESS_CTRL;
6543
6544 si_build_wrapper_function(&ctx,
6545 parts + !vs_needs_prolog,
6546 4 - !vs_needs_prolog, 0,
6547 vs_needs_prolog ? 2 : 1);
6548 } else {
6549 LLVMValueRef parts[2];
6550 union si_shader_part_key epilog_key;
6551
6552 parts[0] = ctx.main_fn;
6553
6554 memset(&epilog_key, 0, sizeof(epilog_key));
6555 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6556 si_build_tcs_epilog_function(&ctx, &epilog_key);
6557 parts[1] = ctx.main_fn;
6558
6559 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6560 }
6561 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6562 if (ctx.screen->info.chip_class >= GFX9) {
6563 struct si_shader_selector *es = shader->key.part.gs.es;
6564 LLVMValueRef es_prolog = NULL;
6565 LLVMValueRef es_main = NULL;
6566 LLVMValueRef gs_prolog = NULL;
6567 LLVMValueRef gs_main = ctx.main_fn;
6568
6569 /* GS prolog */
6570 union si_shader_part_key gs_prolog_key;
6571 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6572 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6573 gs_prolog_key.gs_prolog.is_monolithic = true;
6574 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6575 gs_prolog = ctx.main_fn;
6576
6577 /* ES prolog */
6578 if (es->vs_needs_prolog) {
6579 union si_shader_part_key vs_prolog_key;
6580 si_get_vs_prolog_key(&es->info,
6581 shader->info.num_input_sgprs,
6582 &shader->key.part.gs.vs_prolog,
6583 shader, &vs_prolog_key);
6584 vs_prolog_key.vs_prolog.is_monolithic = true;
6585 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6586 es_prolog = ctx.main_fn;
6587 }
6588
6589 /* ES main part */
6590 struct si_shader shader_es = {};
6591 shader_es.selector = es;
6592 shader_es.key.as_es = 1;
6593 shader_es.key.mono = shader->key.mono;
6594 shader_es.key.opt = shader->key.opt;
6595 si_llvm_context_set_tgsi(&ctx, &shader_es);
6596
6597 if (!si_compile_tgsi_main(&ctx, true)) {
6598 si_llvm_dispose(&ctx);
6599 return -1;
6600 }
6601 shader->info.uses_instanceid |= es->info.uses_instanceid;
6602 es_main = ctx.main_fn;
6603
6604 /* Reset the shader context. */
6605 ctx.shader = shader;
6606 ctx.type = PIPE_SHADER_GEOMETRY;
6607
6608 /* Prepare the array of shader parts. */
6609 LLVMValueRef parts[4];
6610 unsigned num_parts = 0, main_part, next_first_part;
6611
6612 if (es_prolog)
6613 parts[num_parts++] = es_prolog;
6614
6615 parts[main_part = num_parts++] = es_main;
6616 parts[next_first_part = num_parts++] = gs_prolog;
6617 parts[num_parts++] = gs_main;
6618
6619 si_build_wrapper_function(&ctx, parts, num_parts,
6620 main_part, next_first_part);
6621 } else {
6622 LLVMValueRef parts[2];
6623 union si_shader_part_key prolog_key;
6624
6625 parts[1] = ctx.main_fn;
6626
6627 memset(&prolog_key, 0, sizeof(prolog_key));
6628 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6629 si_build_gs_prolog_function(&ctx, &prolog_key);
6630 parts[0] = ctx.main_fn;
6631
6632 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6633 }
6634 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6635 LLVMValueRef parts[3];
6636 union si_shader_part_key prolog_key;
6637 union si_shader_part_key epilog_key;
6638 bool need_prolog;
6639
6640 si_get_ps_prolog_key(shader, &prolog_key, false);
6641 need_prolog = si_need_ps_prolog(&prolog_key);
6642
6643 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6644
6645 if (need_prolog) {
6646 si_build_ps_prolog_function(&ctx, &prolog_key);
6647 parts[0] = ctx.main_fn;
6648 }
6649
6650 si_get_ps_epilog_key(shader, &epilog_key);
6651 si_build_ps_epilog_function(&ctx, &epilog_key);
6652 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6653
6654 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6655 need_prolog ? 1 : 0, 0);
6656 }
6657
6658 si_llvm_optimize_module(&ctx);
6659
6660 /* Post-optimization transformations and analysis. */
6661 si_optimize_vs_outputs(&ctx);
6662
6663 if ((debug && debug->debug_message) ||
6664 si_can_dump_shader(sscreen, ctx.type))
6665 si_count_scratch_private_memory(&ctx);
6666
6667 /* Compile to bytecode. */
6668 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6669 ctx.gallivm.module, debug, ctx.type, "TGSI shader");
6670 si_llvm_dispose(&ctx);
6671 if (r) {
6672 fprintf(stderr, "LLVM failed to compile shader\n");
6673 return r;
6674 }
6675
6676 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6677 * LLVM 3.9svn has this bug.
6678 */
6679 if (sel->type == PIPE_SHADER_COMPUTE) {
6680 unsigned wave_size = 64;
6681 unsigned max_vgprs = 256;
6682 unsigned max_sgprs = sscreen->info.chip_class >= VI ? 800 : 512;
6683 unsigned max_sgprs_per_wave = 128;
6684 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6685 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6686 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6687
6688 max_vgprs = max_vgprs / min_waves_per_simd;
6689 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6690
6691 if (shader->config.num_sgprs > max_sgprs ||
6692 shader->config.num_vgprs > max_vgprs) {
6693 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6694 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6695 shader->config.num_sgprs, shader->config.num_vgprs,
6696 max_sgprs, max_vgprs);
6697
6698 /* Just terminate the process, because dependent
6699 * shaders can hang due to bad input data, but use
6700 * the env var to allow shader-db to work.
6701 */
6702 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6703 abort();
6704 }
6705 }
6706
6707 /* Add the scratch offset to input SGPRs. */
6708 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(shader))
6709 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6710
6711 /* Calculate the number of fragment input VGPRs. */
6712 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6713 shader->info.num_input_vgprs = 0;
6714 shader->info.face_vgpr_index = -1;
6715 shader->info.ancillary_vgpr_index = -1;
6716
6717 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6718 shader->info.num_input_vgprs += 2;
6719 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6720 shader->info.num_input_vgprs += 2;
6721 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6722 shader->info.num_input_vgprs += 2;
6723 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6724 shader->info.num_input_vgprs += 3;
6725 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6726 shader->info.num_input_vgprs += 2;
6727 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6728 shader->info.num_input_vgprs += 2;
6729 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6730 shader->info.num_input_vgprs += 2;
6731 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6732 shader->info.num_input_vgprs += 1;
6733 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6734 shader->info.num_input_vgprs += 1;
6735 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6736 shader->info.num_input_vgprs += 1;
6737 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6738 shader->info.num_input_vgprs += 1;
6739 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6740 shader->info.num_input_vgprs += 1;
6741 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6742 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6743 shader->info.num_input_vgprs += 1;
6744 }
6745 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
6746 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
6747 shader->info.num_input_vgprs += 1;
6748 }
6749 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6750 shader->info.num_input_vgprs += 1;
6751 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6752 shader->info.num_input_vgprs += 1;
6753 }
6754
6755 return 0;
6756 }
6757
6758 /**
6759 * Create, compile and return a shader part (prolog or epilog).
6760 *
6761 * \param sscreen screen
6762 * \param list list of shader parts of the same category
6763 * \param type shader type
6764 * \param key shader part key
6765 * \param prolog whether the part being requested is a prolog
6766 * \param tm LLVM target machine
6767 * \param debug debug callback
6768 * \param build the callback responsible for building the main function
6769 * \return non-NULL on success
6770 */
6771 static struct si_shader_part *
6772 si_get_shader_part(struct si_screen *sscreen,
6773 struct si_shader_part **list,
6774 enum pipe_shader_type type,
6775 bool prolog,
6776 union si_shader_part_key *key,
6777 LLVMTargetMachineRef tm,
6778 struct pipe_debug_callback *debug,
6779 void (*build)(struct si_shader_context *,
6780 union si_shader_part_key *),
6781 const char *name)
6782 {
6783 struct si_shader_part *result;
6784
6785 mtx_lock(&sscreen->shader_parts_mutex);
6786
6787 /* Find existing. */
6788 for (result = *list; result; result = result->next) {
6789 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6790 mtx_unlock(&sscreen->shader_parts_mutex);
6791 return result;
6792 }
6793 }
6794
6795 /* Compile a new one. */
6796 result = CALLOC_STRUCT(si_shader_part);
6797 result->key = *key;
6798
6799 struct si_shader shader = {};
6800 struct si_shader_context ctx;
6801
6802 si_init_shader_ctx(&ctx, sscreen, tm);
6803 ctx.shader = &shader;
6804 ctx.type = type;
6805
6806 switch (type) {
6807 case PIPE_SHADER_VERTEX:
6808 shader.key.as_ls = key->vs_prolog.as_ls;
6809 shader.key.as_es = key->vs_prolog.as_es;
6810 break;
6811 case PIPE_SHADER_TESS_CTRL:
6812 assert(!prolog);
6813 shader.key.part.tcs.epilog = key->tcs_epilog.states;
6814 break;
6815 case PIPE_SHADER_GEOMETRY:
6816 assert(prolog);
6817 break;
6818 case PIPE_SHADER_FRAGMENT:
6819 if (prolog)
6820 shader.key.part.ps.prolog = key->ps_prolog.states;
6821 else
6822 shader.key.part.ps.epilog = key->ps_epilog.states;
6823 break;
6824 default:
6825 unreachable("bad shader part");
6826 }
6827
6828 build(&ctx, key);
6829
6830 /* Compile. */
6831 si_llvm_optimize_module(&ctx);
6832
6833 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
6834 ctx.ac.module, debug, ctx.type, name)) {
6835 FREE(result);
6836 result = NULL;
6837 goto out;
6838 }
6839
6840 result->next = *list;
6841 *list = result;
6842
6843 out:
6844 si_llvm_dispose(&ctx);
6845 mtx_unlock(&sscreen->shader_parts_mutex);
6846 return result;
6847 }
6848
6849 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
6850 {
6851 LLVMValueRef ptr[2], list;
6852 bool is_merged_shader =
6853 ctx->screen->info.chip_class >= GFX9 &&
6854 (ctx->type == PIPE_SHADER_TESS_CTRL ||
6855 ctx->type == PIPE_SHADER_GEOMETRY ||
6856 ctx->shader->key.as_ls || ctx->shader->key.as_es);
6857
6858 /* Get the pointer to rw buffers. */
6859 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
6860 ptr[1] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS_HI);
6861 list = lp_build_gather_values(&ctx->gallivm, ptr, 2);
6862 list = LLVMBuildBitCast(ctx->ac.builder, list, ctx->i64, "");
6863 list = LLVMBuildIntToPtr(ctx->ac.builder, list,
6864 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS), "");
6865 return list;
6866 }
6867
6868 /**
6869 * Build the vertex shader prolog function.
6870 *
6871 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6872 * All inputs are returned unmodified. The vertex load indices are
6873 * stored after them, which will be used by the API VS for fetching inputs.
6874 *
6875 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6876 * input_v0,
6877 * input_v1,
6878 * input_v2,
6879 * input_v3,
6880 * (VertexID + BaseVertex),
6881 * (InstanceID + StartInstance),
6882 * (InstanceID / 2 + StartInstance)
6883 */
6884 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
6885 union si_shader_part_key *key)
6886 {
6887 struct si_function_info fninfo;
6888 LLVMTypeRef *returns;
6889 LLVMValueRef ret, func;
6890 int num_returns, i;
6891 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
6892 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
6893 LLVMValueRef input_vgprs[9];
6894 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
6895 num_input_vgprs;
6896 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
6897
6898 si_init_function_info(&fninfo);
6899
6900 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6901 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
6902 sizeof(LLVMTypeRef));
6903 num_returns = 0;
6904
6905 /* Declare input and output SGPRs. */
6906 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6907 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6908 returns[num_returns++] = ctx->i32;
6909 }
6910
6911 /* Preloaded VGPRs (outputs must be floats) */
6912 for (i = 0; i < num_input_vgprs; i++) {
6913 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
6914 returns[num_returns++] = ctx->f32;
6915 }
6916
6917 /* Vertex load indices. */
6918 for (i = 0; i <= key->vs_prolog.last_input; i++)
6919 returns[num_returns++] = ctx->f32;
6920
6921 /* Create the function. */
6922 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
6923 func = ctx->main_fn;
6924
6925 if (key->vs_prolog.num_merged_next_stage_vgprs) {
6926 if (!key->vs_prolog.is_monolithic)
6927 si_init_exec_from_input(ctx, 3, 0);
6928
6929 if (key->vs_prolog.as_ls &&
6930 ctx->screen->has_ls_vgpr_init_bug) {
6931 /* If there are no HS threads, SPI loads the LS VGPRs
6932 * starting at VGPR 0. Shift them back to where they
6933 * belong.
6934 */
6935 LLVMValueRef has_hs_threads =
6936 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
6937 unpack_param(ctx, 3, 8, 8),
6938 ctx->i32_0, "");
6939
6940 for (i = 4; i > 0; --i) {
6941 input_vgprs[i + 1] =
6942 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
6943 input_vgprs[i + 1],
6944 input_vgprs[i - 1], "");
6945 }
6946 }
6947 }
6948
6949 ctx->abi.vertex_id = input_vgprs[first_vs_vgpr];
6950 ctx->abi.instance_id = input_vgprs[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)];
6951
6952 /* Copy inputs to outputs. This should be no-op, as the registers match,
6953 * but it will prevent the compiler from overwriting them unintentionally.
6954 */
6955 ret = ctx->return_value;
6956 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6957 LLVMValueRef p = LLVMGetParam(func, i);
6958 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
6959 }
6960 for (i = 0; i < num_input_vgprs; i++) {
6961 LLVMValueRef p = input_vgprs[i];
6962 p = ac_to_float(&ctx->ac, p);
6963 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
6964 key->vs_prolog.num_input_sgprs + i, "");
6965 }
6966
6967 /* Compute vertex load indices from instance divisors. */
6968 LLVMValueRef instance_divisor_constbuf = NULL;
6969
6970 if (key->vs_prolog.states.instance_divisor_is_fetched) {
6971 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
6972 LLVMValueRef buf_index =
6973 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
6974 instance_divisor_constbuf =
6975 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
6976 }
6977
6978 for (i = 0; i <= key->vs_prolog.last_input; i++) {
6979 bool divisor_is_one =
6980 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
6981 bool divisor_is_fetched =
6982 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
6983 LLVMValueRef index;
6984
6985 if (divisor_is_one || divisor_is_fetched) {
6986 LLVMValueRef divisor = ctx->i32_1;
6987
6988 if (divisor_is_fetched) {
6989 divisor = buffer_load_const(ctx, instance_divisor_constbuf,
6990 LLVMConstInt(ctx->i32, i * 4, 0));
6991 divisor = ac_to_integer(&ctx->ac, divisor);
6992 }
6993
6994 /* InstanceID / Divisor + StartInstance */
6995 index = get_instance_index_for_fetch(ctx,
6996 user_sgpr_base +
6997 SI_SGPR_START_INSTANCE,
6998 divisor);
6999 } else {
7000 /* VertexID + BaseVertex */
7001 index = LLVMBuildAdd(ctx->ac.builder,
7002 ctx->abi.vertex_id,
7003 LLVMGetParam(func, user_sgpr_base +
7004 SI_SGPR_BASE_VERTEX), "");
7005 }
7006
7007 index = ac_to_float(&ctx->ac, index);
7008 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7009 fninfo.num_params + i, "");
7010 }
7011
7012 si_llvm_build_ret(ctx, ret);
7013 }
7014
7015 static bool si_get_vs_prolog(struct si_screen *sscreen,
7016 LLVMTargetMachineRef tm,
7017 struct si_shader *shader,
7018 struct pipe_debug_callback *debug,
7019 struct si_shader *main_part,
7020 const struct si_vs_prolog_bits *key)
7021 {
7022 struct si_shader_selector *vs = main_part->selector;
7023
7024 if (!si_vs_needs_prolog(vs, key))
7025 return true;
7026
7027 /* Get the prolog. */
7028 union si_shader_part_key prolog_key;
7029 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7030 key, shader, &prolog_key);
7031
7032 shader->prolog =
7033 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7034 PIPE_SHADER_VERTEX, true, &prolog_key, tm,
7035 debug, si_build_vs_prolog_function,
7036 "Vertex Shader Prolog");
7037 return shader->prolog != NULL;
7038 }
7039
7040 /**
7041 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7042 */
7043 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7044 LLVMTargetMachineRef tm,
7045 struct si_shader *shader,
7046 struct pipe_debug_callback *debug)
7047 {
7048 return si_get_vs_prolog(sscreen, tm, shader, debug, shader,
7049 &shader->key.part.vs.prolog);
7050 }
7051
7052 /**
7053 * Compile the TCS epilog function. This writes tesselation factors to memory
7054 * based on the output primitive type of the tesselator (determined by TES).
7055 */
7056 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7057 union si_shader_part_key *key)
7058 {
7059 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7060 struct si_function_info fninfo;
7061 LLVMValueRef func;
7062
7063 si_init_function_info(&fninfo);
7064
7065 if (ctx->screen->info.chip_class >= GFX9) {
7066 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7067 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7068 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7069 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7070 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7071 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7072 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7073 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7074 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7075 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7076 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7077 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7078 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7079 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7080 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7081 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7082 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7083 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7084 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7085 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7086 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7087 } else {
7088 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7089 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7090 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7091 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7092 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7093 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7094 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7095 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7096 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7097 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7098 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7099 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7100 }
7101
7102 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7103 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7104 unsigned tess_factors_idx =
7105 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7106 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7107 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7108
7109 for (unsigned i = 0; i < 6; i++)
7110 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7111
7112 /* Create the function. */
7113 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7114 ctx->screen->info.chip_class >= CIK ? 128 : 64);
7115 ac_declare_lds_as_pointer(&ctx->ac);
7116 func = ctx->main_fn;
7117
7118 LLVMValueRef invoc0_tess_factors[6];
7119 for (unsigned i = 0; i < 6; i++)
7120 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7121
7122 si_write_tess_factors(bld_base,
7123 LLVMGetParam(func, tess_factors_idx),
7124 LLVMGetParam(func, tess_factors_idx + 1),
7125 LLVMGetParam(func, tess_factors_idx + 2),
7126 invoc0_tess_factors, invoc0_tess_factors + 4);
7127
7128 LLVMBuildRetVoid(ctx->ac.builder);
7129 }
7130
7131 /**
7132 * Select and compile (or reuse) TCS parts (epilog).
7133 */
7134 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7135 LLVMTargetMachineRef tm,
7136 struct si_shader *shader,
7137 struct pipe_debug_callback *debug)
7138 {
7139 if (sscreen->info.chip_class >= GFX9) {
7140 struct si_shader *ls_main_part =
7141 shader->key.part.tcs.ls->main_shader_part_ls;
7142
7143 if (!si_get_vs_prolog(sscreen, tm, shader, debug, ls_main_part,
7144 &shader->key.part.tcs.ls_prolog))
7145 return false;
7146
7147 shader->previous_stage = ls_main_part;
7148 }
7149
7150 /* Get the epilog. */
7151 union si_shader_part_key epilog_key;
7152 memset(&epilog_key, 0, sizeof(epilog_key));
7153 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7154
7155 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7156 PIPE_SHADER_TESS_CTRL, false,
7157 &epilog_key, tm, debug,
7158 si_build_tcs_epilog_function,
7159 "Tessellation Control Shader Epilog");
7160 return shader->epilog != NULL;
7161 }
7162
7163 /**
7164 * Select and compile (or reuse) GS parts (prolog).
7165 */
7166 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7167 LLVMTargetMachineRef tm,
7168 struct si_shader *shader,
7169 struct pipe_debug_callback *debug)
7170 {
7171 if (sscreen->info.chip_class >= GFX9) {
7172 struct si_shader *es_main_part =
7173 shader->key.part.gs.es->main_shader_part_es;
7174
7175 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7176 !si_get_vs_prolog(sscreen, tm, shader, debug, es_main_part,
7177 &shader->key.part.gs.vs_prolog))
7178 return false;
7179
7180 shader->previous_stage = es_main_part;
7181 }
7182
7183 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7184 return true;
7185
7186 union si_shader_part_key prolog_key;
7187 memset(&prolog_key, 0, sizeof(prolog_key));
7188 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7189
7190 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7191 PIPE_SHADER_GEOMETRY, true,
7192 &prolog_key, tm, debug,
7193 si_build_gs_prolog_function,
7194 "Geometry Shader Prolog");
7195 return shader->prolog2 != NULL;
7196 }
7197
7198 /**
7199 * Build the pixel shader prolog function. This handles:
7200 * - two-side color selection and interpolation
7201 * - overriding interpolation parameters for the API PS
7202 * - polygon stippling
7203 *
7204 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7205 * overriden by other states. (e.g. per-sample interpolation)
7206 * Interpolated colors are stored after the preloaded VGPRs.
7207 */
7208 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7209 union si_shader_part_key *key)
7210 {
7211 struct si_function_info fninfo;
7212 LLVMValueRef ret, func;
7213 int num_returns, i, num_color_channels;
7214
7215 assert(si_need_ps_prolog(key));
7216
7217 si_init_function_info(&fninfo);
7218
7219 /* Declare inputs. */
7220 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7221 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7222
7223 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7224 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7225
7226 /* Declare outputs (same as inputs + add colors if needed) */
7227 num_returns = fninfo.num_params;
7228 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7229 for (i = 0; i < num_color_channels; i++)
7230 fninfo.types[num_returns++] = ctx->f32;
7231
7232 /* Create the function. */
7233 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7234 &fninfo, 0);
7235 func = ctx->main_fn;
7236
7237 /* Copy inputs to outputs. This should be no-op, as the registers match,
7238 * but it will prevent the compiler from overwriting them unintentionally.
7239 */
7240 ret = ctx->return_value;
7241 for (i = 0; i < fninfo.num_params; i++) {
7242 LLVMValueRef p = LLVMGetParam(func, i);
7243 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7244 }
7245
7246 /* Polygon stippling. */
7247 if (key->ps_prolog.states.poly_stipple) {
7248 /* POS_FIXED_PT is always last. */
7249 unsigned pos = key->ps_prolog.num_input_sgprs +
7250 key->ps_prolog.num_input_vgprs - 1;
7251 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7252
7253 si_llvm_emit_polygon_stipple(ctx, list, pos);
7254 }
7255
7256 if (key->ps_prolog.states.bc_optimize_for_persp ||
7257 key->ps_prolog.states.bc_optimize_for_linear) {
7258 unsigned i, base = key->ps_prolog.num_input_sgprs;
7259 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7260
7261 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7262 * The hw doesn't compute CENTROID if the whole wave only
7263 * contains fully-covered quads.
7264 *
7265 * PRIM_MASK is after user SGPRs.
7266 */
7267 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7268 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7269 LLVMConstInt(ctx->i32, 31, 0), "");
7270 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7271 ctx->i1, "");
7272
7273 if (key->ps_prolog.states.bc_optimize_for_persp) {
7274 /* Read PERSP_CENTER. */
7275 for (i = 0; i < 2; i++)
7276 center[i] = LLVMGetParam(func, base + 2 + i);
7277 /* Read PERSP_CENTROID. */
7278 for (i = 0; i < 2; i++)
7279 centroid[i] = LLVMGetParam(func, base + 4 + i);
7280 /* Select PERSP_CENTROID. */
7281 for (i = 0; i < 2; i++) {
7282 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7283 center[i], centroid[i], "");
7284 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7285 tmp, base + 4 + i, "");
7286 }
7287 }
7288 if (key->ps_prolog.states.bc_optimize_for_linear) {
7289 /* Read LINEAR_CENTER. */
7290 for (i = 0; i < 2; i++)
7291 center[i] = LLVMGetParam(func, base + 8 + i);
7292 /* Read LINEAR_CENTROID. */
7293 for (i = 0; i < 2; i++)
7294 centroid[i] = LLVMGetParam(func, base + 10 + i);
7295 /* Select LINEAR_CENTROID. */
7296 for (i = 0; i < 2; i++) {
7297 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7298 center[i], centroid[i], "");
7299 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7300 tmp, base + 10 + i, "");
7301 }
7302 }
7303 }
7304
7305 /* Force per-sample interpolation. */
7306 if (key->ps_prolog.states.force_persp_sample_interp) {
7307 unsigned i, base = key->ps_prolog.num_input_sgprs;
7308 LLVMValueRef persp_sample[2];
7309
7310 /* Read PERSP_SAMPLE. */
7311 for (i = 0; i < 2; i++)
7312 persp_sample[i] = LLVMGetParam(func, base + i);
7313 /* Overwrite PERSP_CENTER. */
7314 for (i = 0; i < 2; i++)
7315 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7316 persp_sample[i], base + 2 + i, "");
7317 /* Overwrite PERSP_CENTROID. */
7318 for (i = 0; i < 2; i++)
7319 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7320 persp_sample[i], base + 4 + i, "");
7321 }
7322 if (key->ps_prolog.states.force_linear_sample_interp) {
7323 unsigned i, base = key->ps_prolog.num_input_sgprs;
7324 LLVMValueRef linear_sample[2];
7325
7326 /* Read LINEAR_SAMPLE. */
7327 for (i = 0; i < 2; i++)
7328 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7329 /* Overwrite LINEAR_CENTER. */
7330 for (i = 0; i < 2; i++)
7331 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7332 linear_sample[i], base + 8 + i, "");
7333 /* Overwrite LINEAR_CENTROID. */
7334 for (i = 0; i < 2; i++)
7335 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7336 linear_sample[i], base + 10 + i, "");
7337 }
7338
7339 /* Force center interpolation. */
7340 if (key->ps_prolog.states.force_persp_center_interp) {
7341 unsigned i, base = key->ps_prolog.num_input_sgprs;
7342 LLVMValueRef persp_center[2];
7343
7344 /* Read PERSP_CENTER. */
7345 for (i = 0; i < 2; i++)
7346 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7347 /* Overwrite PERSP_SAMPLE. */
7348 for (i = 0; i < 2; i++)
7349 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7350 persp_center[i], base + i, "");
7351 /* Overwrite PERSP_CENTROID. */
7352 for (i = 0; i < 2; i++)
7353 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7354 persp_center[i], base + 4 + i, "");
7355 }
7356 if (key->ps_prolog.states.force_linear_center_interp) {
7357 unsigned i, base = key->ps_prolog.num_input_sgprs;
7358 LLVMValueRef linear_center[2];
7359
7360 /* Read LINEAR_CENTER. */
7361 for (i = 0; i < 2; i++)
7362 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7363 /* Overwrite LINEAR_SAMPLE. */
7364 for (i = 0; i < 2; i++)
7365 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7366 linear_center[i], base + 6 + i, "");
7367 /* Overwrite LINEAR_CENTROID. */
7368 for (i = 0; i < 2; i++)
7369 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7370 linear_center[i], base + 10 + i, "");
7371 }
7372
7373 /* Interpolate colors. */
7374 unsigned color_out_idx = 0;
7375 for (i = 0; i < 2; i++) {
7376 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7377 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7378 key->ps_prolog.face_vgpr_index;
7379 LLVMValueRef interp[2], color[4];
7380 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7381
7382 if (!writemask)
7383 continue;
7384
7385 /* If the interpolation qualifier is not CONSTANT (-1). */
7386 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7387 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7388 key->ps_prolog.color_interp_vgpr_index[i];
7389
7390 /* Get the (i,j) updated by bc_optimize handling. */
7391 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7392 interp_vgpr, "");
7393 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7394 interp_vgpr + 1, "");
7395 interp_ij = lp_build_gather_values(&ctx->gallivm, interp, 2);
7396 }
7397
7398 /* Use the absolute location of the input. */
7399 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7400
7401 if (key->ps_prolog.states.color_two_side) {
7402 face = LLVMGetParam(func, face_vgpr);
7403 face = ac_to_integer(&ctx->ac, face);
7404 }
7405
7406 interp_fs_input(ctx,
7407 key->ps_prolog.color_attr_index[i],
7408 TGSI_SEMANTIC_COLOR, i,
7409 key->ps_prolog.num_interp_inputs,
7410 key->ps_prolog.colors_read, interp_ij,
7411 prim_mask, face, color);
7412
7413 while (writemask) {
7414 unsigned chan = u_bit_scan(&writemask);
7415 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7416 fninfo.num_params + color_out_idx++, "");
7417 }
7418 }
7419
7420 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7421 * says:
7422 *
7423 * "When per-sample shading is active due to the use of a fragment
7424 * input qualified by sample or due to the use of the gl_SampleID
7425 * or gl_SamplePosition variables, only the bit for the current
7426 * sample is set in gl_SampleMaskIn. When state specifies multiple
7427 * fragment shader invocations for a given fragment, the sample
7428 * mask for any single fragment shader invocation may specify a
7429 * subset of the covered samples for the fragment. In this case,
7430 * the bit corresponding to each covered sample will be set in
7431 * exactly one fragment shader invocation."
7432 *
7433 * The samplemask loaded by hardware is always the coverage of the
7434 * entire pixel/fragment, so mask bits out based on the sample ID.
7435 */
7436 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7437 /* The bit pattern matches that used by fixed function fragment
7438 * processing. */
7439 static const uint16_t ps_iter_masks[] = {
7440 0xffff, /* not used */
7441 0x5555,
7442 0x1111,
7443 0x0101,
7444 0x0001,
7445 };
7446 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7447
7448 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7449 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7450 key->ps_prolog.ancillary_vgpr_index;
7451 LLVMValueRef sampleid = unpack_param(ctx, ancillary_vgpr, 8, 4);
7452 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7453
7454 samplemask = ac_to_integer(&ctx->ac, samplemask);
7455 samplemask = LLVMBuildAnd(
7456 ctx->ac.builder,
7457 samplemask,
7458 LLVMBuildShl(ctx->ac.builder,
7459 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7460 sampleid, ""),
7461 "");
7462 samplemask = ac_to_float(&ctx->ac, samplemask);
7463
7464 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7465 ancillary_vgpr + 1, "");
7466 }
7467
7468 /* Tell LLVM to insert WQM instruction sequence when needed. */
7469 if (key->ps_prolog.wqm) {
7470 LLVMAddTargetDependentFunctionAttr(func,
7471 "amdgpu-ps-wqm-outputs", "");
7472 }
7473
7474 si_llvm_build_ret(ctx, ret);
7475 }
7476
7477 /**
7478 * Build the pixel shader epilog function. This handles everything that must be
7479 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7480 */
7481 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7482 union si_shader_part_key *key)
7483 {
7484 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7485 struct si_function_info fninfo;
7486 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7487 int i;
7488 struct si_ps_exports exp = {};
7489
7490 si_init_function_info(&fninfo);
7491
7492 /* Declare input SGPRs. */
7493 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7494 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7495 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7496 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7497 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7498
7499 /* Declare input VGPRs. */
7500 unsigned required_num_params =
7501 fninfo.num_sgpr_params +
7502 util_bitcount(key->ps_epilog.colors_written) * 4 +
7503 key->ps_epilog.writes_z +
7504 key->ps_epilog.writes_stencil +
7505 key->ps_epilog.writes_samplemask;
7506
7507 required_num_params = MAX2(required_num_params,
7508 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7509
7510 while (fninfo.num_params < required_num_params)
7511 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7512
7513 /* Create the function. */
7514 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7515 /* Disable elimination of unused inputs. */
7516 si_llvm_add_attribute(ctx->main_fn,
7517 "InitialPSInputAddr", 0xffffff);
7518
7519 /* Process colors. */
7520 unsigned vgpr = fninfo.num_sgpr_params;
7521 unsigned colors_written = key->ps_epilog.colors_written;
7522 int last_color_export = -1;
7523
7524 /* Find the last color export. */
7525 if (!key->ps_epilog.writes_z &&
7526 !key->ps_epilog.writes_stencil &&
7527 !key->ps_epilog.writes_samplemask) {
7528 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7529
7530 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7531 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7532 /* Just set this if any of the colorbuffers are enabled. */
7533 if (spi_format &
7534 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7535 last_color_export = 0;
7536 } else {
7537 for (i = 0; i < 8; i++)
7538 if (colors_written & (1 << i) &&
7539 (spi_format >> (i * 4)) & 0xf)
7540 last_color_export = i;
7541 }
7542 }
7543
7544 while (colors_written) {
7545 LLVMValueRef color[4];
7546 int mrt = u_bit_scan(&colors_written);
7547
7548 for (i = 0; i < 4; i++)
7549 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7550
7551 si_export_mrt_color(bld_base, color, mrt,
7552 fninfo.num_params - 1,
7553 mrt == last_color_export, &exp);
7554 }
7555
7556 /* Process depth, stencil, samplemask. */
7557 if (key->ps_epilog.writes_z)
7558 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7559 if (key->ps_epilog.writes_stencil)
7560 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7561 if (key->ps_epilog.writes_samplemask)
7562 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7563
7564 if (depth || stencil || samplemask)
7565 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7566 else if (last_color_export == -1)
7567 si_export_null(bld_base);
7568
7569 if (exp.num)
7570 si_emit_ps_exports(ctx, &exp);
7571
7572 /* Compile. */
7573 LLVMBuildRetVoid(ctx->ac.builder);
7574 }
7575
7576 /**
7577 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7578 */
7579 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7580 LLVMTargetMachineRef tm,
7581 struct si_shader *shader,
7582 struct pipe_debug_callback *debug)
7583 {
7584 union si_shader_part_key prolog_key;
7585 union si_shader_part_key epilog_key;
7586
7587 /* Get the prolog. */
7588 si_get_ps_prolog_key(shader, &prolog_key, true);
7589
7590 /* The prolog is a no-op if these aren't set. */
7591 if (si_need_ps_prolog(&prolog_key)) {
7592 shader->prolog =
7593 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7594 PIPE_SHADER_FRAGMENT, true,
7595 &prolog_key, tm, debug,
7596 si_build_ps_prolog_function,
7597 "Fragment Shader Prolog");
7598 if (!shader->prolog)
7599 return false;
7600 }
7601
7602 /* Get the epilog. */
7603 si_get_ps_epilog_key(shader, &epilog_key);
7604
7605 shader->epilog =
7606 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7607 PIPE_SHADER_FRAGMENT, false,
7608 &epilog_key, tm, debug,
7609 si_build_ps_epilog_function,
7610 "Fragment Shader Epilog");
7611 if (!shader->epilog)
7612 return false;
7613
7614 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7615 if (shader->key.part.ps.prolog.poly_stipple) {
7616 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7617 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7618 }
7619
7620 /* Set up the enable bits for per-sample shading if needed. */
7621 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7622 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7623 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7624 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7625 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7626 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7627 }
7628 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7629 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7630 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7631 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7632 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7633 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7634 }
7635 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7636 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7637 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7638 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7639 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7640 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7641 }
7642 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7643 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7644 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7645 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7646 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7647 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7648 }
7649
7650 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7651 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7652 !(shader->config.spi_ps_input_ena & 0xf)) {
7653 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7654 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7655 }
7656
7657 /* At least one pair of interpolation weights must be enabled. */
7658 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7659 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7660 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7661 }
7662
7663 /* Samplemask fixup requires the sample ID. */
7664 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7665 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7666 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7667 }
7668
7669 /* The sample mask input is always enabled, because the API shader always
7670 * passes it through to the epilog. Disable it here if it's unused.
7671 */
7672 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7673 !shader->selector->info.reads_samplemask)
7674 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7675
7676 return true;
7677 }
7678
7679 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7680 unsigned *lds_size)
7681 {
7682 /* SPI barrier management bug:
7683 * Make sure we have at least 4k of LDS in use to avoid the bug.
7684 * It applies to workgroup sizes of more than one wavefront.
7685 */
7686 if (sscreen->info.family == CHIP_BONAIRE ||
7687 sscreen->info.family == CHIP_KABINI ||
7688 sscreen->info.family == CHIP_MULLINS)
7689 *lds_size = MAX2(*lds_size, 8);
7690 }
7691
7692 static void si_fix_resource_usage(struct si_screen *sscreen,
7693 struct si_shader *shader)
7694 {
7695 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7696
7697 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7698
7699 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7700 si_get_max_workgroup_size(shader) > 64) {
7701 si_multiwave_lds_size_workaround(sscreen,
7702 &shader->config.lds_size);
7703 }
7704 }
7705
7706 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7707 struct si_shader *shader,
7708 struct pipe_debug_callback *debug)
7709 {
7710 struct si_shader_selector *sel = shader->selector;
7711 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7712 int r;
7713
7714 /* LS, ES, VS are compiled on demand if the main part hasn't been
7715 * compiled for that stage.
7716 *
7717 * Vertex shaders are compiled on demand when a vertex fetch
7718 * workaround must be applied.
7719 */
7720 if (shader->is_monolithic) {
7721 /* Monolithic shader (compiled as a whole, has many variants,
7722 * may take a long time to compile).
7723 */
7724 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7725 if (r)
7726 return r;
7727 } else {
7728 /* The shader consists of several parts:
7729 *
7730 * - the middle part is the user shader, it has 1 variant only
7731 * and it was compiled during the creation of the shader
7732 * selector
7733 * - the prolog part is inserted at the beginning
7734 * - the epilog part is inserted at the end
7735 *
7736 * The prolog and epilog have many (but simple) variants.
7737 *
7738 * Starting with gfx9, geometry and tessellation control
7739 * shaders also contain the prolog and user shader parts of
7740 * the previous shader stage.
7741 */
7742
7743 if (!mainp)
7744 return -1;
7745
7746 /* Copy the compiled TGSI shader data over. */
7747 shader->is_binary_shared = true;
7748 shader->binary = mainp->binary;
7749 shader->config = mainp->config;
7750 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7751 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7752 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7753 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
7754 memcpy(shader->info.vs_output_param_offset,
7755 mainp->info.vs_output_param_offset,
7756 sizeof(mainp->info.vs_output_param_offset));
7757 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7758 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7759 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7760
7761 /* Select prologs and/or epilogs. */
7762 switch (sel->type) {
7763 case PIPE_SHADER_VERTEX:
7764 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7765 return -1;
7766 break;
7767 case PIPE_SHADER_TESS_CTRL:
7768 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7769 return -1;
7770 break;
7771 case PIPE_SHADER_TESS_EVAL:
7772 break;
7773 case PIPE_SHADER_GEOMETRY:
7774 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
7775 return -1;
7776 break;
7777 case PIPE_SHADER_FRAGMENT:
7778 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7779 return -1;
7780
7781 /* Make sure we have at least as many VGPRs as there
7782 * are allocated inputs.
7783 */
7784 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7785 shader->info.num_input_vgprs);
7786 break;
7787 }
7788
7789 /* Update SGPR and VGPR counts. */
7790 if (shader->prolog) {
7791 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7792 shader->prolog->config.num_sgprs);
7793 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7794 shader->prolog->config.num_vgprs);
7795 }
7796 if (shader->previous_stage) {
7797 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7798 shader->previous_stage->config.num_sgprs);
7799 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7800 shader->previous_stage->config.num_vgprs);
7801 shader->config.spilled_sgprs =
7802 MAX2(shader->config.spilled_sgprs,
7803 shader->previous_stage->config.spilled_sgprs);
7804 shader->config.spilled_vgprs =
7805 MAX2(shader->config.spilled_vgprs,
7806 shader->previous_stage->config.spilled_vgprs);
7807 shader->config.private_mem_vgprs =
7808 MAX2(shader->config.private_mem_vgprs,
7809 shader->previous_stage->config.private_mem_vgprs);
7810 shader->config.scratch_bytes_per_wave =
7811 MAX2(shader->config.scratch_bytes_per_wave,
7812 shader->previous_stage->config.scratch_bytes_per_wave);
7813 shader->info.uses_instanceid |=
7814 shader->previous_stage->info.uses_instanceid;
7815 }
7816 if (shader->prolog2) {
7817 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7818 shader->prolog2->config.num_sgprs);
7819 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7820 shader->prolog2->config.num_vgprs);
7821 }
7822 if (shader->epilog) {
7823 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7824 shader->epilog->config.num_sgprs);
7825 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7826 shader->epilog->config.num_vgprs);
7827 }
7828 }
7829
7830 si_fix_resource_usage(sscreen, shader);
7831 si_shader_dump(sscreen, shader, debug, sel->info.processor,
7832 stderr, true);
7833
7834 /* Upload. */
7835 r = si_shader_binary_upload(sscreen, shader);
7836 if (r) {
7837 fprintf(stderr, "LLVM failed to upload shader\n");
7838 return r;
7839 }
7840
7841 return 0;
7842 }
7843
7844 void si_shader_destroy(struct si_shader *shader)
7845 {
7846 if (shader->scratch_bo)
7847 r600_resource_reference(&shader->scratch_bo, NULL);
7848
7849 r600_resource_reference(&shader->bo, NULL);
7850
7851 if (!shader->is_binary_shared)
7852 ac_shader_binary_clean(&shader->binary);
7853
7854 free(shader->shader_log);
7855 }