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radeonsi: remove an unused ctx parameter in si_shader_destroy
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_dump.h"
45
46 #include "si_pipe.h"
47 #include "si_shader.h"
48 #include "sid.h"
49
50 #include <errno.h>
51
52 static const char *scratch_rsrc_dword0_symbol =
53 "SCRATCH_RSRC_DWORD0";
54
55 static const char *scratch_rsrc_dword1_symbol =
56 "SCRATCH_RSRC_DWORD1";
57
58 struct si_shader_output_values
59 {
60 LLVMValueRef values[4];
61 unsigned name;
62 unsigned sid;
63 };
64
65 struct si_shader_context
66 {
67 struct radeon_llvm_context radeon_bld;
68 struct si_shader *shader;
69 struct si_screen *screen;
70 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
71 int param_streamout_config;
72 int param_streamout_write_index;
73 int param_streamout_offset[4];
74 int param_vertex_id;
75 int param_rel_auto_id;
76 int param_vs_prim_id;
77 int param_instance_id;
78 int param_tes_u;
79 int param_tes_v;
80 int param_tes_rel_patch_id;
81 int param_tes_patch_id;
82 int param_es2gs_offset;
83 LLVMTargetMachineRef tm;
84 LLVMValueRef const_md;
85 LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
86 LLVMValueRef lds;
87 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
88 LLVMValueRef resources[SI_NUM_SAMPLER_VIEWS];
89 LLVMValueRef samplers[SI_NUM_SAMPLER_STATES];
90 LLVMValueRef so_buffers[4];
91 LLVMValueRef esgs_ring;
92 LLVMValueRef gsvs_ring[4];
93 LLVMValueRef gs_next_vertex[4];
94 };
95
96 static struct si_shader_context * si_shader_context(
97 struct lp_build_tgsi_context * bld_base)
98 {
99 return (struct si_shader_context *)bld_base;
100 }
101
102
103 #define PERSPECTIVE_BASE 0
104 #define LINEAR_BASE 9
105
106 #define SAMPLE_OFFSET 0
107 #define CENTER_OFFSET 2
108 #define CENTROID_OFSET 4
109
110 #define USE_SGPR_MAX_SUFFIX_LEN 5
111 #define CONST_ADDR_SPACE 2
112 #define LOCAL_ADDR_SPACE 3
113 #define USER_SGPR_ADDR_SPACE 8
114
115
116 #define SENDMSG_GS 2
117 #define SENDMSG_GS_DONE 3
118
119 #define SENDMSG_GS_OP_NOP (0 << 4)
120 #define SENDMSG_GS_OP_CUT (1 << 4)
121 #define SENDMSG_GS_OP_EMIT (2 << 4)
122 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
123
124 /**
125 * Returns a unique index for a semantic name and index. The index must be
126 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
127 * calculated.
128 */
129 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
130 {
131 switch (semantic_name) {
132 case TGSI_SEMANTIC_POSITION:
133 return 0;
134 case TGSI_SEMANTIC_PSIZE:
135 return 1;
136 case TGSI_SEMANTIC_CLIPDIST:
137 assert(index <= 1);
138 return 2 + index;
139 case TGSI_SEMANTIC_GENERIC:
140 if (index <= 63-4)
141 return 4 + index;
142 else
143 /* same explanation as in the default statement,
144 * the only user hitting this is st/nine.
145 */
146 return 0;
147
148 /* patch indices are completely separate and thus start from 0 */
149 case TGSI_SEMANTIC_TESSOUTER:
150 return 0;
151 case TGSI_SEMANTIC_TESSINNER:
152 return 1;
153 case TGSI_SEMANTIC_PATCH:
154 return 2 + index;
155
156 default:
157 /* Don't fail here. The result of this function is only used
158 * for LS, TCS, TES, and GS, where legacy GL semantics can't
159 * occur, but this function is called for all vertex shaders
160 * before it's known whether LS will be compiled or not.
161 */
162 return 0;
163 }
164 }
165
166 /**
167 * Given a semantic name and index of a parameter and a mask of used parameters
168 * (inputs or outputs), return the index of the parameter in the list of all
169 * used parameters.
170 *
171 * For example, assume this list of parameters:
172 * POSITION, PSIZE, GENERIC0, GENERIC2
173 * which has the mask:
174 * 11000000000101
175 * Then:
176 * querying POSITION returns 0,
177 * querying PSIZE returns 1,
178 * querying GENERIC0 returns 2,
179 * querying GENERIC2 returns 3.
180 *
181 * Which can be used as an offset to a parameter buffer in units of vec4s.
182 */
183 static int get_param_index(unsigned semantic_name, unsigned index,
184 uint64_t mask)
185 {
186 unsigned unique_index = si_shader_io_get_unique_index(semantic_name, index);
187 int i, param_index = 0;
188
189 /* If not present... */
190 if (!((1llu << unique_index) & mask))
191 return -1;
192
193 for (i = 0; mask; i++) {
194 uint64_t bit = 1llu << i;
195
196 if (bit & mask) {
197 if (i == unique_index)
198 return param_index;
199
200 mask &= ~bit;
201 param_index++;
202 }
203 }
204
205 assert(!"unreachable");
206 return -1;
207 }
208
209 /**
210 * Get the value of a shader input parameter and extract a bitfield.
211 */
212 static LLVMValueRef unpack_param(struct si_shader_context *si_shader_ctx,
213 unsigned param, unsigned rshift,
214 unsigned bitwidth)
215 {
216 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
217 LLVMValueRef value = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
218 param);
219
220 if (rshift)
221 value = LLVMBuildLShr(gallivm->builder, value,
222 lp_build_const_int32(gallivm, rshift), "");
223
224 if (rshift + bitwidth < 32) {
225 unsigned mask = (1 << bitwidth) - 1;
226 value = LLVMBuildAnd(gallivm->builder, value,
227 lp_build_const_int32(gallivm, mask), "");
228 }
229
230 return value;
231 }
232
233 static LLVMValueRef get_rel_patch_id(struct si_shader_context *si_shader_ctx)
234 {
235 switch (si_shader_ctx->type) {
236 case TGSI_PROCESSOR_TESS_CTRL:
237 return unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 0, 8);
238
239 case TGSI_PROCESSOR_TESS_EVAL:
240 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
241 si_shader_ctx->param_tes_rel_patch_id);
242
243 default:
244 assert(0);
245 return NULL;
246 }
247 }
248
249 /* Tessellation shaders pass outputs to the next shader using LDS.
250 *
251 * LS outputs = TCS inputs
252 * TCS outputs = TES inputs
253 *
254 * The LDS layout is:
255 * - TCS inputs for patch 0
256 * - TCS inputs for patch 1
257 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
258 * - ...
259 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
260 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
261 * - TCS outputs for patch 1
262 * - Per-patch TCS outputs for patch 1
263 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
264 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
265 * - ...
266 *
267 * All three shaders VS(LS), TCS, TES share the same LDS space.
268 */
269
270 static LLVMValueRef
271 get_tcs_in_patch_stride(struct si_shader_context *si_shader_ctx)
272 {
273 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX)
274 return unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
275 else if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
276 return unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
277 else {
278 assert(0);
279 return NULL;
280 }
281 }
282
283 static LLVMValueRef
284 get_tcs_out_patch_stride(struct si_shader_context *si_shader_ctx)
285 {
286 return unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
287 }
288
289 static LLVMValueRef
290 get_tcs_out_patch0_offset(struct si_shader_context *si_shader_ctx)
291 {
292 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
293 unpack_param(si_shader_ctx,
294 SI_PARAM_TCS_OUT_OFFSETS,
295 0, 16),
296 4);
297 }
298
299 static LLVMValueRef
300 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *si_shader_ctx)
301 {
302 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
303 unpack_param(si_shader_ctx,
304 SI_PARAM_TCS_OUT_OFFSETS,
305 16, 16),
306 4);
307 }
308
309 static LLVMValueRef
310 get_tcs_in_current_patch_offset(struct si_shader_context *si_shader_ctx)
311 {
312 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
313 LLVMValueRef patch_stride = get_tcs_in_patch_stride(si_shader_ctx);
314 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
315
316 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
317 }
318
319 static LLVMValueRef
320 get_tcs_out_current_patch_offset(struct si_shader_context *si_shader_ctx)
321 {
322 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
323 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(si_shader_ctx);
324 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
325 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
326
327 return LLVMBuildAdd(gallivm->builder, patch0_offset,
328 LLVMBuildMul(gallivm->builder, patch_stride,
329 rel_patch_id, ""),
330 "");
331 }
332
333 static LLVMValueRef
334 get_tcs_out_current_patch_data_offset(struct si_shader_context *si_shader_ctx)
335 {
336 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
337 LLVMValueRef patch0_patch_data_offset =
338 get_tcs_out_patch0_patch_data_offset(si_shader_ctx);
339 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
340 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
341
342 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
343 LLVMBuildMul(gallivm->builder, patch_stride,
344 rel_patch_id, ""),
345 "");
346 }
347
348 static void build_indexed_store(struct si_shader_context *si_shader_ctx,
349 LLVMValueRef base_ptr, LLVMValueRef index,
350 LLVMValueRef value)
351 {
352 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
353 struct gallivm_state *gallivm = bld_base->base.gallivm;
354 LLVMValueRef indices[2], pointer;
355
356 indices[0] = bld_base->uint_bld.zero;
357 indices[1] = index;
358
359 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
360 LLVMBuildStore(gallivm->builder, value, pointer);
361 }
362
363 /**
364 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
365 * It's equivalent to doing a load from &base_ptr[index].
366 *
367 * \param base_ptr Where the array starts.
368 * \param index The element index into the array.
369 */
370 static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
371 LLVMValueRef base_ptr, LLVMValueRef index)
372 {
373 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
374 struct gallivm_state *gallivm = bld_base->base.gallivm;
375 LLVMValueRef indices[2], pointer;
376
377 indices[0] = bld_base->uint_bld.zero;
378 indices[1] = index;
379
380 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
381 return LLVMBuildLoad(gallivm->builder, pointer, "");
382 }
383
384 /**
385 * Do a load from &base_ptr[index], but also add a flag that it's loading
386 * a constant.
387 */
388 static LLVMValueRef build_indexed_load_const(
389 struct si_shader_context * si_shader_ctx,
390 LLVMValueRef base_ptr, LLVMValueRef index)
391 {
392 LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
393 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
394 return result;
395 }
396
397 static LLVMValueRef get_instance_index_for_fetch(
398 struct radeon_llvm_context * radeon_bld,
399 unsigned divisor)
400 {
401 struct si_shader_context *si_shader_ctx =
402 si_shader_context(&radeon_bld->soa.bld_base);
403 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
404
405 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
406 si_shader_ctx->param_instance_id);
407
408 /* The division must be done before START_INSTANCE is added. */
409 if (divisor > 1)
410 result = LLVMBuildUDiv(gallivm->builder, result,
411 lp_build_const_int32(gallivm, divisor), "");
412
413 return LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
414 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
415 }
416
417 static void declare_input_vs(
418 struct radeon_llvm_context *radeon_bld,
419 unsigned input_index,
420 const struct tgsi_full_declaration *decl)
421 {
422 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
423 struct gallivm_state *gallivm = base->gallivm;
424 struct si_shader_context *si_shader_ctx =
425 si_shader_context(&radeon_bld->soa.bld_base);
426 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
427
428 unsigned chan;
429
430 LLVMValueRef t_list_ptr;
431 LLVMValueRef t_offset;
432 LLVMValueRef t_list;
433 LLVMValueRef attribute_offset;
434 LLVMValueRef buffer_index;
435 LLVMValueRef args[3];
436 LLVMTypeRef vec4_type;
437 LLVMValueRef input;
438
439 /* Load the T list */
440 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
441
442 t_offset = lp_build_const_int32(gallivm, input_index);
443
444 t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
445
446 /* Build the attribute offset */
447 attribute_offset = lp_build_const_int32(gallivm, 0);
448
449 if (divisor) {
450 /* Build index from instance ID, start instance and divisor */
451 si_shader_ctx->shader->uses_instanceid = true;
452 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
453 } else {
454 /* Load the buffer index for vertices. */
455 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
456 si_shader_ctx->param_vertex_id);
457 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
458 SI_PARAM_BASE_VERTEX);
459 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
460 }
461
462 vec4_type = LLVMVectorType(base->elem_type, 4);
463 args[0] = t_list;
464 args[1] = attribute_offset;
465 args[2] = buffer_index;
466 input = lp_build_intrinsic(gallivm->builder,
467 "llvm.SI.vs.load.input", vec4_type, args, 3,
468 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
469
470 /* Break up the vec4 into individual components */
471 for (chan = 0; chan < 4; chan++) {
472 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
473 /* XXX: Use a helper function for this. There is one in
474 * tgsi_llvm.c. */
475 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
476 LLVMBuildExtractElement(gallivm->builder,
477 input, llvm_chan, "");
478 }
479 }
480
481 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
482 unsigned swizzle)
483 {
484 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
485
486 if (swizzle > 0)
487 return bld_base->uint_bld.zero;
488
489 switch (si_shader_ctx->type) {
490 case TGSI_PROCESSOR_VERTEX:
491 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
492 si_shader_ctx->param_vs_prim_id);
493 case TGSI_PROCESSOR_TESS_CTRL:
494 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
495 SI_PARAM_PATCH_ID);
496 case TGSI_PROCESSOR_TESS_EVAL:
497 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
498 si_shader_ctx->param_tes_patch_id);
499 case TGSI_PROCESSOR_GEOMETRY:
500 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
501 SI_PARAM_PRIMITIVE_ID);
502 default:
503 assert(0);
504 return bld_base->uint_bld.zero;
505 }
506 }
507
508 /**
509 * Return the value of tgsi_ind_register for indexing.
510 * This is the indirect index with the constant offset added to it.
511 */
512 static LLVMValueRef get_indirect_index(struct si_shader_context *si_shader_ctx,
513 const struct tgsi_ind_register *ind,
514 int rel_index)
515 {
516 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
517 LLVMValueRef result;
518
519 result = si_shader_ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
520 result = LLVMBuildLoad(gallivm->builder, result, "");
521 result = LLVMBuildAdd(gallivm->builder, result,
522 lp_build_const_int32(gallivm, rel_index), "");
523 return result;
524 }
525
526 /**
527 * Calculate a dword address given an input or output register and a stride.
528 */
529 static LLVMValueRef get_dw_address(struct si_shader_context *si_shader_ctx,
530 const struct tgsi_full_dst_register *dst,
531 const struct tgsi_full_src_register *src,
532 LLVMValueRef vertex_dw_stride,
533 LLVMValueRef base_addr)
534 {
535 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
536 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
537 ubyte *name, *index, *array_first;
538 int first, param;
539 struct tgsi_full_dst_register reg;
540
541 /* Set the register description. The address computation is the same
542 * for sources and destinations. */
543 if (src) {
544 reg.Register.File = src->Register.File;
545 reg.Register.Index = src->Register.Index;
546 reg.Register.Indirect = src->Register.Indirect;
547 reg.Register.Dimension = src->Register.Dimension;
548 reg.Indirect = src->Indirect;
549 reg.Dimension = src->Dimension;
550 reg.DimIndirect = src->DimIndirect;
551 } else
552 reg = *dst;
553
554 /* If the register is 2-dimensional (e.g. an array of vertices
555 * in a primitive), calculate the base address of the vertex. */
556 if (reg.Register.Dimension) {
557 LLVMValueRef index;
558
559 if (reg.Dimension.Indirect)
560 index = get_indirect_index(si_shader_ctx, &reg.DimIndirect,
561 reg.Dimension.Index);
562 else
563 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
564
565 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
566 LLVMBuildMul(gallivm->builder, index,
567 vertex_dw_stride, ""), "");
568 }
569
570 /* Get information about the register. */
571 if (reg.Register.File == TGSI_FILE_INPUT) {
572 name = info->input_semantic_name;
573 index = info->input_semantic_index;
574 array_first = info->input_array_first;
575 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
576 name = info->output_semantic_name;
577 index = info->output_semantic_index;
578 array_first = info->output_array_first;
579 } else {
580 assert(0);
581 return NULL;
582 }
583
584 if (reg.Register.Indirect) {
585 /* Add the relative address of the element. */
586 LLVMValueRef ind_index;
587
588 if (reg.Indirect.ArrayID)
589 first = array_first[reg.Indirect.ArrayID];
590 else
591 first = reg.Register.Index;
592
593 ind_index = get_indirect_index(si_shader_ctx, &reg.Indirect,
594 reg.Register.Index - first);
595
596 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
597 LLVMBuildMul(gallivm->builder, ind_index,
598 lp_build_const_int32(gallivm, 4), ""), "");
599
600 param = si_shader_io_get_unique_index(name[first], index[first]);
601 } else {
602 param = si_shader_io_get_unique_index(name[reg.Register.Index],
603 index[reg.Register.Index]);
604 }
605
606 /* Add the base address of the element. */
607 return LLVMBuildAdd(gallivm->builder, base_addr,
608 lp_build_const_int32(gallivm, param * 4), "");
609 }
610
611 /**
612 * Load from LDS.
613 *
614 * \param type output value type
615 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
616 * \param dw_addr address in dwords
617 */
618 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
619 enum tgsi_opcode_type type, unsigned swizzle,
620 LLVMValueRef dw_addr)
621 {
622 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
623 struct gallivm_state *gallivm = bld_base->base.gallivm;
624 LLVMValueRef value;
625
626 if (swizzle == ~0) {
627 LLVMValueRef values[TGSI_NUM_CHANNELS];
628
629 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
630 values[chan] = lds_load(bld_base, type, chan, dw_addr);
631
632 return lp_build_gather_values(bld_base->base.gallivm, values,
633 TGSI_NUM_CHANNELS);
634 }
635
636 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
637 lp_build_const_int32(gallivm, swizzle));
638
639 value = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
640 return LLVMBuildBitCast(gallivm->builder, value,
641 tgsi2llvmtype(bld_base, type), "");
642 }
643
644 /**
645 * Store to LDS.
646 *
647 * \param swizzle offset (typically 0..3)
648 * \param dw_addr address in dwords
649 * \param value value to store
650 */
651 static void lds_store(struct lp_build_tgsi_context * bld_base,
652 unsigned swizzle, LLVMValueRef dw_addr,
653 LLVMValueRef value)
654 {
655 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
656 struct gallivm_state *gallivm = bld_base->base.gallivm;
657
658 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
659 lp_build_const_int32(gallivm, swizzle));
660
661 value = LLVMBuildBitCast(gallivm->builder, value,
662 LLVMInt32TypeInContext(gallivm->context), "");
663 build_indexed_store(si_shader_ctx, si_shader_ctx->lds,
664 dw_addr, value);
665 }
666
667 static LLVMValueRef fetch_input_tcs(
668 struct lp_build_tgsi_context *bld_base,
669 const struct tgsi_full_src_register *reg,
670 enum tgsi_opcode_type type, unsigned swizzle)
671 {
672 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
673 LLVMValueRef dw_addr, stride;
674
675 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
676 dw_addr = get_tcs_in_current_patch_offset(si_shader_ctx);
677 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
678
679 return lds_load(bld_base, type, swizzle, dw_addr);
680 }
681
682 static LLVMValueRef fetch_output_tcs(
683 struct lp_build_tgsi_context *bld_base,
684 const struct tgsi_full_src_register *reg,
685 enum tgsi_opcode_type type, unsigned swizzle)
686 {
687 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
688 LLVMValueRef dw_addr, stride;
689
690 if (reg->Register.Dimension) {
691 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
692 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
693 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
694 } else {
695 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
696 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
697 }
698
699 return lds_load(bld_base, type, swizzle, dw_addr);
700 }
701
702 static LLVMValueRef fetch_input_tes(
703 struct lp_build_tgsi_context *bld_base,
704 const struct tgsi_full_src_register *reg,
705 enum tgsi_opcode_type type, unsigned swizzle)
706 {
707 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
708 LLVMValueRef dw_addr, stride;
709
710 if (reg->Register.Dimension) {
711 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
712 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
713 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
714 } else {
715 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
716 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
717 }
718
719 return lds_load(bld_base, type, swizzle, dw_addr);
720 }
721
722 static void store_output_tcs(struct lp_build_tgsi_context * bld_base,
723 const struct tgsi_full_instruction * inst,
724 const struct tgsi_opcode_info * info,
725 LLVMValueRef dst[4])
726 {
727 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
728 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
729 unsigned chan_index;
730 LLVMValueRef dw_addr, stride;
731
732 /* Only handle per-patch and per-vertex outputs here.
733 * Vectors will be lowered to scalars and this function will be called again.
734 */
735 if (reg->Register.File != TGSI_FILE_OUTPUT ||
736 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
737 radeon_llvm_emit_store(bld_base, inst, info, dst);
738 return;
739 }
740
741 if (reg->Register.Dimension) {
742 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
743 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
744 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, stride, dw_addr);
745 } else {
746 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
747 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, NULL, dw_addr);
748 }
749
750 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
751 LLVMValueRef value = dst[chan_index];
752
753 if (inst->Instruction.Saturate)
754 value = radeon_llvm_saturate(bld_base, value);
755
756 lds_store(bld_base, chan_index, dw_addr, value);
757 }
758 }
759
760 static LLVMValueRef fetch_input_gs(
761 struct lp_build_tgsi_context *bld_base,
762 const struct tgsi_full_src_register *reg,
763 enum tgsi_opcode_type type,
764 unsigned swizzle)
765 {
766 struct lp_build_context *base = &bld_base->base;
767 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
768 struct si_shader *shader = si_shader_ctx->shader;
769 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
770 struct gallivm_state *gallivm = base->gallivm;
771 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
772 LLVMValueRef vtx_offset;
773 LLVMValueRef args[9];
774 unsigned vtx_offset_param;
775 struct tgsi_shader_info *info = &shader->selector->info;
776 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
777 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
778
779 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
780 return get_primitive_id(bld_base, swizzle);
781
782 if (!reg->Register.Dimension)
783 return NULL;
784
785 if (swizzle == ~0) {
786 LLVMValueRef values[TGSI_NUM_CHANNELS];
787 unsigned chan;
788 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
789 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
790 }
791 return lp_build_gather_values(bld_base->base.gallivm, values,
792 TGSI_NUM_CHANNELS);
793 }
794
795 /* Get the vertex offset parameter */
796 vtx_offset_param = reg->Dimension.Index;
797 if (vtx_offset_param < 2) {
798 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
799 } else {
800 assert(vtx_offset_param < 6);
801 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
802 }
803 vtx_offset = lp_build_mul_imm(uint,
804 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
805 vtx_offset_param),
806 4);
807
808 args[0] = si_shader_ctx->esgs_ring;
809 args[1] = vtx_offset;
810 args[2] = lp_build_const_int32(gallivm,
811 (get_param_index(semantic_name, semantic_index,
812 shader->selector->inputs_read) * 4 +
813 swizzle) * 256);
814 args[3] = uint->zero;
815 args[4] = uint->one; /* OFFEN */
816 args[5] = uint->zero; /* IDXEN */
817 args[6] = uint->one; /* GLC */
818 args[7] = uint->zero; /* SLC */
819 args[8] = uint->zero; /* TFE */
820
821 return LLVMBuildBitCast(gallivm->builder,
822 lp_build_intrinsic(gallivm->builder,
823 "llvm.SI.buffer.load.dword.i32.i32",
824 i32, args, 9,
825 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
826 tgsi2llvmtype(bld_base, type), "");
827 }
828
829 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
830 {
831 switch (interpolate) {
832 case TGSI_INTERPOLATE_CONSTANT:
833 return 0;
834
835 case TGSI_INTERPOLATE_LINEAR:
836 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
837 return SI_PARAM_LINEAR_SAMPLE;
838 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
839 return SI_PARAM_LINEAR_CENTROID;
840 else
841 return SI_PARAM_LINEAR_CENTER;
842 break;
843 case TGSI_INTERPOLATE_COLOR:
844 case TGSI_INTERPOLATE_PERSPECTIVE:
845 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
846 return SI_PARAM_PERSP_SAMPLE;
847 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
848 return SI_PARAM_PERSP_CENTROID;
849 else
850 return SI_PARAM_PERSP_CENTER;
851 break;
852 default:
853 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
854 return -1;
855 }
856 }
857
858 /* This shouldn't be used by explicit INTERP opcodes. */
859 static LLVMValueRef get_interp_param(struct si_shader_context *si_shader_ctx,
860 unsigned param)
861 {
862 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
863 unsigned sample_param = 0;
864 LLVMValueRef default_ij, sample_ij, force_sample;
865
866 default_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, param);
867
868 /* If the shader doesn't use center/centroid, just return the parameter.
869 *
870 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
871 * switch between center/centroid and sample without shader changes.
872 */
873 switch (param) {
874 case SI_PARAM_PERSP_CENTROID:
875 case SI_PARAM_PERSP_CENTER:
876 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_persp)
877 return default_ij;
878
879 sample_param = SI_PARAM_PERSP_SAMPLE;
880 break;
881
882 case SI_PARAM_LINEAR_CENTROID:
883 case SI_PARAM_LINEAR_CENTER:
884 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_linear)
885 return default_ij;
886
887 sample_param = SI_PARAM_LINEAR_SAMPLE;
888 break;
889
890 default:
891 return default_ij;
892 }
893
894 /* Otherwise, we have to select (i,j) based on a user data SGPR. */
895 sample_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, sample_param);
896
897 /* TODO: this can be done more efficiently by switching between
898 * 2 prologs.
899 */
900 force_sample = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
901 SI_PARAM_PS_STATE_BITS);
902 force_sample = LLVMBuildTrunc(gallivm->builder, force_sample,
903 LLVMInt1TypeInContext(gallivm->context), "");
904 return LLVMBuildSelect(gallivm->builder, force_sample,
905 sample_ij, default_ij, "");
906 }
907
908 static void declare_input_fs(
909 struct radeon_llvm_context *radeon_bld,
910 unsigned input_index,
911 const struct tgsi_full_declaration *decl)
912 {
913 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
914 struct si_shader_context *si_shader_ctx =
915 si_shader_context(&radeon_bld->soa.bld_base);
916 struct si_shader *shader = si_shader_ctx->shader;
917 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
918 struct gallivm_state *gallivm = base->gallivm;
919 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
920 LLVMValueRef main_fn = radeon_bld->main_fn;
921
922 LLVMValueRef interp_param = NULL;
923 int interp_param_idx;
924 const char * intr_name;
925
926 /* This value is:
927 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
928 * quad begins a new primitive. Bit 0 always needs
929 * to be unset)
930 * [32:16] ParamOffset
931 *
932 */
933 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
934 LLVMValueRef attr_number;
935
936 unsigned chan;
937
938 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
939 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
940 unsigned soa_index =
941 radeon_llvm_reg_index_soa(input_index, chan);
942 radeon_bld->inputs[soa_index] =
943 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
944
945 if (chan == 3)
946 /* RCP for fragcoord.w */
947 radeon_bld->inputs[soa_index] =
948 LLVMBuildFDiv(gallivm->builder,
949 lp_build_const_float(gallivm, 1.0f),
950 radeon_bld->inputs[soa_index],
951 "");
952 }
953 return;
954 }
955
956 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
957 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
958 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
959 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
960 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
961 lp_build_const_float(gallivm, 0.0f);
962 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
963 lp_build_const_float(gallivm, 1.0f);
964
965 return;
966 }
967
968 shader->ps_input_param_offset[input_index] = shader->nparam++;
969 attr_number = lp_build_const_int32(gallivm,
970 shader->ps_input_param_offset[input_index]);
971
972 shader->ps_input_interpolate[input_index] = decl->Interp.Interpolate;
973 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
974 decl->Interp.Location);
975 if (interp_param_idx == -1)
976 return;
977 else if (interp_param_idx)
978 interp_param = get_interp_param(si_shader_ctx, interp_param_idx);
979
980 /* fs.constant returns the param from the middle vertex, so it's not
981 * really useful for flat shading. It's meant to be used for custom
982 * interpolation (but the intrinsic can't fetch from the other two
983 * vertices).
984 *
985 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
986 * to do the right thing. The only reason we use fs.constant is that
987 * fs.interp cannot be used on integers, because they can be equal
988 * to NaN.
989 */
990 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
991
992 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
993 si_shader_ctx->shader->key.ps.color_two_side) {
994 LLVMValueRef args[4];
995 LLVMValueRef face, is_face_positive;
996 LLVMValueRef back_attr_number =
997 lp_build_const_int32(gallivm,
998 shader->ps_input_param_offset[input_index] + 1);
999
1000 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
1001
1002 is_face_positive = LLVMBuildFCmp(gallivm->builder,
1003 LLVMRealOGT, face,
1004 lp_build_const_float(gallivm, 0.0f),
1005 "");
1006
1007 args[2] = params;
1008 args[3] = interp_param;
1009 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1010 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1011 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
1012 LLVMValueRef front, back;
1013
1014 args[0] = llvm_chan;
1015 args[1] = attr_number;
1016 front = lp_build_intrinsic(gallivm->builder, intr_name,
1017 input_type, args, args[3] ? 4 : 3,
1018 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1019
1020 args[1] = back_attr_number;
1021 back = lp_build_intrinsic(gallivm->builder, intr_name,
1022 input_type, args, args[3] ? 4 : 3,
1023 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1024
1025 radeon_bld->inputs[soa_index] =
1026 LLVMBuildSelect(gallivm->builder,
1027 is_face_positive,
1028 front,
1029 back,
1030 "");
1031 }
1032
1033 shader->nparam++;
1034 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
1035 LLVMValueRef args[4];
1036
1037 args[0] = uint->zero;
1038 args[1] = attr_number;
1039 args[2] = params;
1040 args[3] = interp_param;
1041 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
1042 lp_build_intrinsic(gallivm->builder, intr_name,
1043 input_type, args, args[3] ? 4 : 3,
1044 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1045 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
1046 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
1047 lp_build_const_float(gallivm, 0.0f);
1048 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
1049 lp_build_const_float(gallivm, 1.0f);
1050 } else {
1051 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1052 LLVMValueRef args[4];
1053 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1054 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
1055 args[0] = llvm_chan;
1056 args[1] = attr_number;
1057 args[2] = params;
1058 args[3] = interp_param;
1059 radeon_bld->inputs[soa_index] =
1060 lp_build_intrinsic(gallivm->builder, intr_name,
1061 input_type, args, args[3] ? 4 : 3,
1062 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1063 }
1064 }
1065 }
1066
1067 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1068 {
1069 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1070 SI_PARAM_ANCILLARY, 8, 4);
1071 }
1072
1073 /**
1074 * Load a dword from a constant buffer.
1075 */
1076 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1077 LLVMValueRef offset, LLVMTypeRef return_type)
1078 {
1079 LLVMValueRef args[2] = {resource, offset};
1080
1081 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1082 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1083 }
1084
1085 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1086 {
1087 struct si_shader_context *si_shader_ctx =
1088 si_shader_context(&radeon_bld->soa.bld_base);
1089 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1090 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1091 LLVMBuilderRef builder = gallivm->builder;
1092 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1093 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
1094 LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
1095
1096 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1097 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1098 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1099
1100 LLVMValueRef pos[4] = {
1101 buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
1102 buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
1103 lp_build_const_float(gallivm, 0),
1104 lp_build_const_float(gallivm, 0)
1105 };
1106
1107 return lp_build_gather_values(gallivm, pos, 4);
1108 }
1109
1110 static void declare_system_value(
1111 struct radeon_llvm_context * radeon_bld,
1112 unsigned index,
1113 const struct tgsi_full_declaration *decl)
1114 {
1115 struct si_shader_context *si_shader_ctx =
1116 si_shader_context(&radeon_bld->soa.bld_base);
1117 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1118 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1119 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1120 LLVMValueRef value = 0;
1121
1122 switch (decl->Semantic.Name) {
1123 case TGSI_SEMANTIC_INSTANCEID:
1124 value = LLVMGetParam(radeon_bld->main_fn,
1125 si_shader_ctx->param_instance_id);
1126 break;
1127
1128 case TGSI_SEMANTIC_VERTEXID:
1129 value = LLVMBuildAdd(gallivm->builder,
1130 LLVMGetParam(radeon_bld->main_fn,
1131 si_shader_ctx->param_vertex_id),
1132 LLVMGetParam(radeon_bld->main_fn,
1133 SI_PARAM_BASE_VERTEX), "");
1134 break;
1135
1136 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1137 value = LLVMGetParam(radeon_bld->main_fn,
1138 si_shader_ctx->param_vertex_id);
1139 break;
1140
1141 case TGSI_SEMANTIC_BASEVERTEX:
1142 value = LLVMGetParam(radeon_bld->main_fn,
1143 SI_PARAM_BASE_VERTEX);
1144 break;
1145
1146 case TGSI_SEMANTIC_INVOCATIONID:
1147 if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
1148 value = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1149 else if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY)
1150 value = LLVMGetParam(radeon_bld->main_fn,
1151 SI_PARAM_GS_INSTANCE_ID);
1152 else
1153 assert(!"INVOCATIONID not implemented");
1154 break;
1155
1156 case TGSI_SEMANTIC_SAMPLEID:
1157 value = get_sample_id(radeon_bld);
1158 break;
1159
1160 case TGSI_SEMANTIC_SAMPLEPOS:
1161 value = load_sample_position(radeon_bld, get_sample_id(radeon_bld));
1162 break;
1163
1164 case TGSI_SEMANTIC_SAMPLEMASK:
1165 /* Smoothing isn't MSAA in GL, but it's MSAA in hardware.
1166 * Therefore, force gl_SampleMaskIn to 1 for GL. */
1167 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
1168 value = uint_bld->one;
1169 else
1170 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1171 break;
1172
1173 case TGSI_SEMANTIC_TESSCOORD:
1174 {
1175 LLVMValueRef coord[4] = {
1176 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_u),
1177 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_v),
1178 bld->zero,
1179 bld->zero
1180 };
1181
1182 /* For triangles, the vector should be (u, v, 1-u-v). */
1183 if (si_shader_ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1184 PIPE_PRIM_TRIANGLES)
1185 coord[2] = lp_build_sub(bld, bld->one,
1186 lp_build_add(bld, coord[0], coord[1]));
1187
1188 value = lp_build_gather_values(gallivm, coord, 4);
1189 break;
1190 }
1191
1192 case TGSI_SEMANTIC_VERTICESIN:
1193 value = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1194 break;
1195
1196 case TGSI_SEMANTIC_TESSINNER:
1197 case TGSI_SEMANTIC_TESSOUTER:
1198 {
1199 LLVMValueRef dw_addr;
1200 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1201
1202 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1203 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1204 lp_build_const_int32(gallivm, param * 4), "");
1205
1206 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1207 ~0, dw_addr);
1208 break;
1209 }
1210
1211 case TGSI_SEMANTIC_PRIMID:
1212 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1213 break;
1214
1215 default:
1216 assert(!"unknown system value");
1217 return;
1218 }
1219
1220 radeon_bld->system_values[index] = value;
1221 }
1222
1223 static LLVMValueRef fetch_constant(
1224 struct lp_build_tgsi_context * bld_base,
1225 const struct tgsi_full_src_register *reg,
1226 enum tgsi_opcode_type type,
1227 unsigned swizzle)
1228 {
1229 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1230 struct lp_build_context * base = &bld_base->base;
1231 const struct tgsi_ind_register *ireg = &reg->Indirect;
1232 unsigned buf, idx;
1233
1234 LLVMValueRef addr, bufp;
1235 LLVMValueRef result;
1236
1237 if (swizzle == LP_CHAN_ALL) {
1238 unsigned chan;
1239 LLVMValueRef values[4];
1240 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1241 values[chan] = fetch_constant(bld_base, reg, type, chan);
1242
1243 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1244 }
1245
1246 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1247 idx = reg->Register.Index * 4 + swizzle;
1248
1249 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1250 if (type != TGSI_TYPE_DOUBLE)
1251 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
1252 else {
1253 return radeon_llvm_emit_fetch_double(bld_base,
1254 si_shader_ctx->constants[buf][idx],
1255 si_shader_ctx->constants[buf][idx + 1]);
1256 }
1257 }
1258
1259 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1260 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1261 LLVMValueRef index;
1262 index = get_indirect_index(si_shader_ctx, &reg->DimIndirect,
1263 reg->Dimension.Index);
1264 bufp = build_indexed_load_const(si_shader_ctx, ptr, index);
1265 } else
1266 bufp = si_shader_ctx->const_resource[buf];
1267
1268 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1269 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1270 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1271 addr = lp_build_add(&bld_base->uint_bld, addr,
1272 lp_build_const_int32(base->gallivm, idx * 4));
1273
1274 result = buffer_load_const(base->gallivm->builder, bufp,
1275 addr, bld_base->base.elem_type);
1276
1277 if (type != TGSI_TYPE_DOUBLE)
1278 result = bitcast(bld_base, type, result);
1279 else {
1280 LLVMValueRef addr2, result2;
1281 addr2 = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1282 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1283 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1284 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1285 lp_build_const_int32(base->gallivm, idx * 4));
1286
1287 result2 = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
1288 addr2, bld_base->base.elem_type);
1289
1290 result = radeon_llvm_emit_fetch_double(bld_base,
1291 result, result2);
1292 }
1293 return result;
1294 }
1295
1296 /* Initialize arguments for the shader export intrinsic */
1297 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1298 LLVMValueRef *values,
1299 unsigned target,
1300 LLVMValueRef *args)
1301 {
1302 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1303 struct lp_build_context *uint =
1304 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1305 struct lp_build_context *base = &bld_base->base;
1306 unsigned compressed = 0;
1307 unsigned chan;
1308
1309 /* XXX: This controls which components of the output
1310 * registers actually get exported. (e.g bit 0 means export
1311 * X component, bit 1 means export Y component, etc.) I'm
1312 * hard coding this to 0xf for now. In the future, we might
1313 * want to do something else.
1314 */
1315 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1316
1317 /* Specify whether the EXEC mask represents the valid mask */
1318 args[1] = uint->zero;
1319
1320 /* Specify whether this is the last export */
1321 args[2] = uint->zero;
1322
1323 /* Specify the target we are exporting */
1324 args[3] = lp_build_const_int32(base->gallivm, target);
1325
1326 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
1327 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1328
1329 if (cbuf >= 0 && cbuf < 8) {
1330 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
1331
1332 if (compressed)
1333 si_shader_ctx->shader->spi_shader_col_format |=
1334 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
1335 else
1336 si_shader_ctx->shader->spi_shader_col_format |=
1337 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
1338
1339 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
1340 }
1341 }
1342
1343 /* Set COMPR flag */
1344 args[4] = compressed ? uint->one : uint->zero;
1345
1346 if (compressed) {
1347 /* Pixel shader needs to pack output values before export */
1348 for (chan = 0; chan < 2; chan++) {
1349 LLVMValueRef pack_args[2] = {
1350 values[2 * chan],
1351 values[2 * chan + 1]
1352 };
1353 LLVMValueRef packed;
1354
1355 packed = lp_build_intrinsic(base->gallivm->builder,
1356 "llvm.SI.packf16",
1357 LLVMInt32TypeInContext(base->gallivm->context),
1358 pack_args, 2,
1359 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1360 args[chan + 7] = args[chan + 5] =
1361 LLVMBuildBitCast(base->gallivm->builder,
1362 packed,
1363 LLVMFloatTypeInContext(base->gallivm->context),
1364 "");
1365 }
1366 } else
1367 memcpy(&args[5], values, sizeof(values[0]) * 4);
1368 }
1369
1370 /* Load from output pointers and initialize arguments for the shader export intrinsic */
1371 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
1372 LLVMValueRef *out_ptr,
1373 unsigned target,
1374 LLVMValueRef *args)
1375 {
1376 struct gallivm_state *gallivm = bld_base->base.gallivm;
1377 LLVMValueRef values[4];
1378 int i;
1379
1380 for (i = 0; i < 4; i++)
1381 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
1382
1383 si_llvm_init_export_args(bld_base, values, target, args);
1384 }
1385
1386 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1387 LLVMValueRef alpha_ptr)
1388 {
1389 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1390 struct gallivm_state *gallivm = bld_base->base.gallivm;
1391
1392 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
1393 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1394 SI_PARAM_ALPHA_REF);
1395
1396 LLVMValueRef alpha_pass =
1397 lp_build_cmp(&bld_base->base,
1398 si_shader_ctx->shader->key.ps.alpha_func,
1399 LLVMBuildLoad(gallivm->builder, alpha_ptr, ""),
1400 alpha_ref);
1401 LLVMValueRef arg =
1402 lp_build_select(&bld_base->base,
1403 alpha_pass,
1404 lp_build_const_float(gallivm, 1.0f),
1405 lp_build_const_float(gallivm, -1.0f));
1406
1407 lp_build_intrinsic(gallivm->builder,
1408 "llvm.AMDGPU.kill",
1409 LLVMVoidTypeInContext(gallivm->context),
1410 &arg, 1, 0);
1411 } else {
1412 lp_build_intrinsic(gallivm->builder,
1413 "llvm.AMDGPU.kilp",
1414 LLVMVoidTypeInContext(gallivm->context),
1415 NULL, 0, 0);
1416 }
1417
1418 si_shader_ctx->shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
1419 }
1420
1421 static void si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1422 LLVMValueRef alpha_ptr)
1423 {
1424 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1425 struct gallivm_state *gallivm = bld_base->base.gallivm;
1426 LLVMValueRef coverage, alpha;
1427
1428 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1429 coverage = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1430 SI_PARAM_SAMPLE_COVERAGE);
1431 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1432
1433 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1434 bld_base->int_bld.elem_type,
1435 &coverage, 1, LLVMReadNoneAttribute);
1436
1437 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1438 bld_base->base.elem_type, "");
1439
1440 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1441 lp_build_const_float(gallivm,
1442 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1443
1444 alpha = LLVMBuildLoad(gallivm->builder, alpha_ptr, "");
1445 alpha = LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1446 LLVMBuildStore(gallivm->builder, alpha, alpha_ptr);
1447 }
1448
1449 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
1450 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1451 {
1452 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1453 struct lp_build_context *base = &bld_base->base;
1454 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1455 unsigned reg_index;
1456 unsigned chan;
1457 unsigned const_chan;
1458 LLVMValueRef base_elt;
1459 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1460 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
1461 LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
1462
1463 for (reg_index = 0; reg_index < 2; reg_index ++) {
1464 LLVMValueRef *args = pos[2 + reg_index];
1465
1466 args[5] =
1467 args[6] =
1468 args[7] =
1469 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1470
1471 /* Compute dot products of position and user clip plane vectors */
1472 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1473 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1474 args[1] = lp_build_const_int32(base->gallivm,
1475 ((reg_index * 4 + chan) * 4 +
1476 const_chan) * 4);
1477 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1478 args[1], base->elem_type);
1479 args[5 + chan] =
1480 lp_build_add(base, args[5 + chan],
1481 lp_build_mul(base, base_elt,
1482 out_elts[const_chan]));
1483 }
1484 }
1485
1486 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1487 args[1] = uint->zero;
1488 args[2] = uint->zero;
1489 args[3] = lp_build_const_int32(base->gallivm,
1490 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1491 args[4] = uint->zero;
1492 }
1493 }
1494
1495 static void si_dump_streamout(struct pipe_stream_output_info *so)
1496 {
1497 unsigned i;
1498
1499 if (so->num_outputs)
1500 fprintf(stderr, "STREAMOUT\n");
1501
1502 for (i = 0; i < so->num_outputs; i++) {
1503 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1504 so->output[i].start_component;
1505 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1506 i, so->output[i].output_buffer,
1507 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1508 so->output[i].register_index,
1509 mask & 1 ? "x" : "",
1510 mask & 2 ? "y" : "",
1511 mask & 4 ? "z" : "",
1512 mask & 8 ? "w" : "");
1513 }
1514 }
1515
1516 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1517 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1518 * or v4i32 (num_channels=3,4). */
1519 static void build_tbuffer_store(struct si_shader_context *shader,
1520 LLVMValueRef rsrc,
1521 LLVMValueRef vdata,
1522 unsigned num_channels,
1523 LLVMValueRef vaddr,
1524 LLVMValueRef soffset,
1525 unsigned inst_offset,
1526 unsigned dfmt,
1527 unsigned nfmt,
1528 unsigned offen,
1529 unsigned idxen,
1530 unsigned glc,
1531 unsigned slc,
1532 unsigned tfe)
1533 {
1534 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1535 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1536 LLVMValueRef args[] = {
1537 rsrc,
1538 vdata,
1539 LLVMConstInt(i32, num_channels, 0),
1540 vaddr,
1541 soffset,
1542 LLVMConstInt(i32, inst_offset, 0),
1543 LLVMConstInt(i32, dfmt, 0),
1544 LLVMConstInt(i32, nfmt, 0),
1545 LLVMConstInt(i32, offen, 0),
1546 LLVMConstInt(i32, idxen, 0),
1547 LLVMConstInt(i32, glc, 0),
1548 LLVMConstInt(i32, slc, 0),
1549 LLVMConstInt(i32, tfe, 0)
1550 };
1551
1552 /* The instruction offset field has 12 bits */
1553 assert(offen || inst_offset < (1 << 12));
1554
1555 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1556 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1557 const char *types[] = {"i32", "v2i32", "v4i32"};
1558 char name[256];
1559 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1560
1561 lp_build_intrinsic(gallivm->builder, name,
1562 LLVMVoidTypeInContext(gallivm->context),
1563 args, Elements(args), 0);
1564 }
1565
1566 static void build_tbuffer_store_dwords(struct si_shader_context *shader,
1567 LLVMValueRef rsrc,
1568 LLVMValueRef vdata,
1569 unsigned num_channels,
1570 LLVMValueRef vaddr,
1571 LLVMValueRef soffset,
1572 unsigned inst_offset)
1573 {
1574 static unsigned dfmt[] = {
1575 V_008F0C_BUF_DATA_FORMAT_32,
1576 V_008F0C_BUF_DATA_FORMAT_32_32,
1577 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1578 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1579 };
1580 assert(num_channels >= 1 && num_channels <= 4);
1581
1582 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
1583 inst_offset, dfmt[num_channels-1],
1584 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1585 }
1586
1587 /* On SI, the vertex shader is responsible for writing streamout data
1588 * to buffers. */
1589 static void si_llvm_emit_streamout(struct si_shader_context *shader,
1590 struct si_shader_output_values *outputs,
1591 unsigned noutput)
1592 {
1593 struct pipe_stream_output_info *so = &shader->shader->selector->so;
1594 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1595 LLVMBuilderRef builder = gallivm->builder;
1596 int i, j;
1597 struct lp_build_if_state if_ctx;
1598
1599 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1600
1601 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1602 LLVMValueRef so_vtx_count =
1603 unpack_param(shader, shader->param_streamout_config, 16, 7);
1604
1605 LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", i32,
1606 NULL, 0, LLVMReadNoneAttribute);
1607
1608 /* can_emit = tid < so_vtx_count; */
1609 LLVMValueRef can_emit =
1610 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1611
1612 LLVMValueRef stream_id =
1613 unpack_param(shader, shader->param_streamout_config, 24, 2);
1614
1615 /* Emit the streamout code conditionally. This actually avoids
1616 * out-of-bounds buffer access. The hw tells us via the SGPR
1617 * (so_vtx_count) which threads are allowed to emit streamout data. */
1618 lp_build_if(&if_ctx, gallivm, can_emit);
1619 {
1620 /* The buffer offset is computed as follows:
1621 * ByteOffset = streamout_offset[buffer_id]*4 +
1622 * (streamout_write_index + thread_id)*stride[buffer_id] +
1623 * attrib_offset
1624 */
1625
1626 LLVMValueRef so_write_index =
1627 LLVMGetParam(shader->radeon_bld.main_fn,
1628 shader->param_streamout_write_index);
1629
1630 /* Compute (streamout_write_index + thread_id). */
1631 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1632
1633 /* Compute the write offset for each enabled buffer. */
1634 LLVMValueRef so_write_offset[4] = {};
1635 for (i = 0; i < 4; i++) {
1636 if (!so->stride[i])
1637 continue;
1638
1639 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1640 shader->param_streamout_offset[i]);
1641 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1642
1643 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1644 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1645 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1646 }
1647
1648 /* Write streamout data. */
1649 for (i = 0; i < so->num_outputs; i++) {
1650 unsigned buf_idx = so->output[i].output_buffer;
1651 unsigned reg = so->output[i].register_index;
1652 unsigned start = so->output[i].start_component;
1653 unsigned num_comps = so->output[i].num_components;
1654 unsigned stream = so->output[i].stream;
1655 LLVMValueRef out[4];
1656 struct lp_build_if_state if_ctx_stream;
1657
1658 assert(num_comps && num_comps <= 4);
1659 if (!num_comps || num_comps > 4)
1660 continue;
1661
1662 if (reg >= noutput)
1663 continue;
1664
1665 /* Load the output as int. */
1666 for (j = 0; j < num_comps; j++) {
1667 out[j] = LLVMBuildBitCast(builder,
1668 outputs[reg].values[start+j],
1669 i32, "");
1670 }
1671
1672 /* Pack the output. */
1673 LLVMValueRef vdata = NULL;
1674
1675 switch (num_comps) {
1676 case 1: /* as i32 */
1677 vdata = out[0];
1678 break;
1679 case 2: /* as v2i32 */
1680 case 3: /* as v4i32 (aligned to 4) */
1681 case 4: /* as v4i32 */
1682 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1683 for (j = 0; j < num_comps; j++) {
1684 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1685 LLVMConstInt(i32, j, 0), "");
1686 }
1687 break;
1688 }
1689
1690 LLVMValueRef can_emit_stream =
1691 LLVMBuildICmp(builder, LLVMIntEQ,
1692 stream_id,
1693 lp_build_const_int32(gallivm, stream), "");
1694
1695 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1696 build_tbuffer_store_dwords(shader, shader->so_buffers[buf_idx],
1697 vdata, num_comps,
1698 so_write_offset[buf_idx],
1699 LLVMConstInt(i32, 0, 0),
1700 so->output[i].dst_offset*4);
1701 lp_build_endif(&if_ctx_stream);
1702 }
1703 }
1704 lp_build_endif(&if_ctx);
1705 }
1706
1707
1708 /* Generate export instructions for hardware VS shader stage */
1709 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1710 struct si_shader_output_values *outputs,
1711 unsigned noutput)
1712 {
1713 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1714 struct si_shader * shader = si_shader_ctx->shader;
1715 struct lp_build_context * base = &bld_base->base;
1716 struct lp_build_context * uint =
1717 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1718 LLVMValueRef args[9];
1719 LLVMValueRef pos_args[4][9] = { { 0 } };
1720 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1721 unsigned semantic_name, semantic_index;
1722 unsigned target;
1723 unsigned param_count = 0;
1724 unsigned pos_idx;
1725 int i;
1726
1727 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1728 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1729 }
1730
1731 for (i = 0; i < noutput; i++) {
1732 semantic_name = outputs[i].name;
1733 semantic_index = outputs[i].sid;
1734
1735 handle_semantic:
1736 /* Select the correct target */
1737 switch(semantic_name) {
1738 case TGSI_SEMANTIC_PSIZE:
1739 psize_value = outputs[i].values[0];
1740 continue;
1741 case TGSI_SEMANTIC_EDGEFLAG:
1742 edgeflag_value = outputs[i].values[0];
1743 continue;
1744 case TGSI_SEMANTIC_LAYER:
1745 layer_value = outputs[i].values[0];
1746 semantic_name = TGSI_SEMANTIC_GENERIC;
1747 goto handle_semantic;
1748 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1749 viewport_index_value = outputs[i].values[0];
1750 semantic_name = TGSI_SEMANTIC_GENERIC;
1751 goto handle_semantic;
1752 case TGSI_SEMANTIC_POSITION:
1753 target = V_008DFC_SQ_EXP_POS;
1754 break;
1755 case TGSI_SEMANTIC_COLOR:
1756 case TGSI_SEMANTIC_BCOLOR:
1757 target = V_008DFC_SQ_EXP_PARAM + param_count;
1758 shader->vs_output_param_offset[i] = param_count;
1759 param_count++;
1760 break;
1761 case TGSI_SEMANTIC_CLIPDIST:
1762 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1763 break;
1764 case TGSI_SEMANTIC_CLIPVERTEX:
1765 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1766 continue;
1767 case TGSI_SEMANTIC_PRIMID:
1768 case TGSI_SEMANTIC_FOG:
1769 case TGSI_SEMANTIC_TEXCOORD:
1770 case TGSI_SEMANTIC_GENERIC:
1771 target = V_008DFC_SQ_EXP_PARAM + param_count;
1772 shader->vs_output_param_offset[i] = param_count;
1773 param_count++;
1774 break;
1775 default:
1776 target = 0;
1777 fprintf(stderr,
1778 "Warning: SI unhandled vs output type:%d\n",
1779 semantic_name);
1780 }
1781
1782 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1783
1784 if (target >= V_008DFC_SQ_EXP_POS &&
1785 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1786 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1787 args, sizeof(args));
1788 } else {
1789 lp_build_intrinsic(base->gallivm->builder,
1790 "llvm.SI.export",
1791 LLVMVoidTypeInContext(base->gallivm->context),
1792 args, 9, 0);
1793 }
1794
1795 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1796 semantic_name = TGSI_SEMANTIC_GENERIC;
1797 goto handle_semantic;
1798 }
1799 }
1800
1801 shader->nr_param_exports = param_count;
1802
1803 /* We need to add the position output manually if it's missing. */
1804 if (!pos_args[0][0]) {
1805 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1806 pos_args[0][1] = uint->zero; /* EXEC mask */
1807 pos_args[0][2] = uint->zero; /* last export? */
1808 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1809 pos_args[0][4] = uint->zero; /* COMPR flag */
1810 pos_args[0][5] = base->zero; /* X */
1811 pos_args[0][6] = base->zero; /* Y */
1812 pos_args[0][7] = base->zero; /* Z */
1813 pos_args[0][8] = base->one; /* W */
1814 }
1815
1816 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1817 if (shader->selector->info.writes_psize ||
1818 shader->selector->info.writes_edgeflag ||
1819 shader->selector->info.writes_viewport_index ||
1820 shader->selector->info.writes_layer) {
1821 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1822 shader->selector->info.writes_psize |
1823 (shader->selector->info.writes_edgeflag << 1) |
1824 (shader->selector->info.writes_layer << 2) |
1825 (shader->selector->info.writes_viewport_index << 3));
1826 pos_args[1][1] = uint->zero; /* EXEC mask */
1827 pos_args[1][2] = uint->zero; /* last export? */
1828 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1829 pos_args[1][4] = uint->zero; /* COMPR flag */
1830 pos_args[1][5] = base->zero; /* X */
1831 pos_args[1][6] = base->zero; /* Y */
1832 pos_args[1][7] = base->zero; /* Z */
1833 pos_args[1][8] = base->zero; /* W */
1834
1835 if (shader->selector->info.writes_psize)
1836 pos_args[1][5] = psize_value;
1837
1838 if (shader->selector->info.writes_edgeflag) {
1839 /* The output is a float, but the hw expects an integer
1840 * with the first bit containing the edge flag. */
1841 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1842 edgeflag_value,
1843 bld_base->uint_bld.elem_type, "");
1844 edgeflag_value = lp_build_min(&bld_base->int_bld,
1845 edgeflag_value,
1846 bld_base->int_bld.one);
1847
1848 /* The LLVM intrinsic expects a float. */
1849 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1850 edgeflag_value,
1851 base->elem_type, "");
1852 }
1853
1854 if (shader->selector->info.writes_layer)
1855 pos_args[1][7] = layer_value;
1856
1857 if (shader->selector->info.writes_viewport_index)
1858 pos_args[1][8] = viewport_index_value;
1859 }
1860
1861 for (i = 0; i < 4; i++)
1862 if (pos_args[i][0])
1863 shader->nr_pos_exports++;
1864
1865 pos_idx = 0;
1866 for (i = 0; i < 4; i++) {
1867 if (!pos_args[i][0])
1868 continue;
1869
1870 /* Specify the target we are exporting */
1871 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1872
1873 if (pos_idx == shader->nr_pos_exports)
1874 /* Specify that this is the last export */
1875 pos_args[i][2] = uint->one;
1876
1877 lp_build_intrinsic(base->gallivm->builder,
1878 "llvm.SI.export",
1879 LLVMVoidTypeInContext(base->gallivm->context),
1880 pos_args[i], 9, 0);
1881 }
1882 }
1883
1884 /* This only writes the tessellation factor levels. */
1885 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
1886 {
1887 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1888 struct gallivm_state *gallivm = bld_base->base.gallivm;
1889 struct si_shader *shader = si_shader_ctx->shader;
1890 unsigned tess_inner_index, tess_outer_index;
1891 LLVMValueRef lds_base, lds_inner, lds_outer;
1892 LLVMValueRef tf_base, rel_patch_id, byteoffset, buffer, rw_buffers;
1893 LLVMValueRef out[6], vec0, vec1, invocation_id;
1894 unsigned stride, outer_comps, inner_comps, i;
1895 struct lp_build_if_state if_ctx;
1896
1897 invocation_id = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1898
1899 /* Do this only for invocation 0, because the tess levels are per-patch,
1900 * not per-vertex.
1901 *
1902 * This can't jump, because invocation 0 executes this. It should
1903 * at least mask out the loads and stores for other invocations.
1904 */
1905 lp_build_if(&if_ctx, gallivm,
1906 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
1907 invocation_id, bld_base->uint_bld.zero, ""));
1908
1909 /* Determine the layout of one tess factor element in the buffer. */
1910 switch (shader->key.tcs.prim_mode) {
1911 case PIPE_PRIM_LINES:
1912 stride = 2; /* 2 dwords, 1 vec2 store */
1913 outer_comps = 2;
1914 inner_comps = 0;
1915 break;
1916 case PIPE_PRIM_TRIANGLES:
1917 stride = 4; /* 4 dwords, 1 vec4 store */
1918 outer_comps = 3;
1919 inner_comps = 1;
1920 break;
1921 case PIPE_PRIM_QUADS:
1922 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
1923 outer_comps = 4;
1924 inner_comps = 2;
1925 break;
1926 default:
1927 assert(0);
1928 return;
1929 }
1930
1931 /* Load tess_inner and tess_outer from LDS.
1932 * Any invocation can write them, so we can't get them from a temporary.
1933 */
1934 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
1935 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
1936
1937 lds_base = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1938 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
1939 lp_build_const_int32(gallivm,
1940 tess_inner_index * 4), "");
1941 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
1942 lp_build_const_int32(gallivm,
1943 tess_outer_index * 4), "");
1944
1945 for (i = 0; i < outer_comps; i++)
1946 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
1947 for (i = 0; i < inner_comps; i++)
1948 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
1949
1950 /* Convert the outputs to vectors for stores. */
1951 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
1952 vec1 = NULL;
1953
1954 if (stride > 4)
1955 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
1956
1957 /* Get the buffer. */
1958 rw_buffers = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1959 SI_PARAM_RW_BUFFERS);
1960 buffer = build_indexed_load_const(si_shader_ctx, rw_buffers,
1961 lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR));
1962
1963 /* Get the offset. */
1964 tf_base = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1965 SI_PARAM_TESS_FACTOR_OFFSET);
1966 rel_patch_id = get_rel_patch_id(si_shader_ctx);
1967 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
1968 lp_build_const_int32(gallivm, 4 * stride), "");
1969
1970 /* Store the outputs. */
1971 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec0,
1972 MIN2(stride, 4), byteoffset, tf_base, 0);
1973 if (vec1)
1974 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec1,
1975 stride - 4, byteoffset, tf_base, 16);
1976 lp_build_endif(&if_ctx);
1977 }
1978
1979 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context * bld_base)
1980 {
1981 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1982 struct si_shader *shader = si_shader_ctx->shader;
1983 struct tgsi_shader_info *info = &shader->selector->info;
1984 struct gallivm_state *gallivm = bld_base->base.gallivm;
1985 unsigned i, chan;
1986 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1987 si_shader_ctx->param_rel_auto_id);
1988 LLVMValueRef vertex_dw_stride =
1989 unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
1990 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
1991 vertex_dw_stride, "");
1992
1993 /* Write outputs to LDS. The next shader (TCS aka HS) will read
1994 * its inputs from it. */
1995 for (i = 0; i < info->num_outputs; i++) {
1996 LLVMValueRef *out_ptr = si_shader_ctx->radeon_bld.soa.outputs[i];
1997 unsigned name = info->output_semantic_name[i];
1998 unsigned index = info->output_semantic_index[i];
1999 int param = si_shader_io_get_unique_index(name, index);
2000 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2001 lp_build_const_int32(gallivm, param * 4), "");
2002
2003 for (chan = 0; chan < 4; chan++) {
2004 lds_store(bld_base, chan, dw_addr,
2005 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2006 }
2007 }
2008 }
2009
2010 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
2011 {
2012 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2013 struct gallivm_state *gallivm = bld_base->base.gallivm;
2014 struct si_shader *es = si_shader_ctx->shader;
2015 struct tgsi_shader_info *info = &es->selector->info;
2016 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2017 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2018 si_shader_ctx->param_es2gs_offset);
2019 uint64_t enabled_outputs = si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL ?
2020 es->key.tes.es_enabled_outputs :
2021 es->key.vs.es_enabled_outputs;
2022 unsigned chan;
2023 int i;
2024
2025 for (i = 0; i < info->num_outputs; i++) {
2026 LLVMValueRef *out_ptr =
2027 si_shader_ctx->radeon_bld.soa.outputs[i];
2028 int param_index;
2029
2030 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2031 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2032 continue;
2033
2034 param_index = get_param_index(info->output_semantic_name[i],
2035 info->output_semantic_index[i],
2036 enabled_outputs);
2037 if (param_index < 0)
2038 continue;
2039
2040 for (chan = 0; chan < 4; chan++) {
2041 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2042 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2043
2044 build_tbuffer_store(si_shader_ctx,
2045 si_shader_ctx->esgs_ring,
2046 out_val, 1,
2047 LLVMGetUndef(i32), soffset,
2048 (4 * param_index + chan) * 4,
2049 V_008F0C_BUF_DATA_FORMAT_32,
2050 V_008F0C_BUF_NUM_FORMAT_UINT,
2051 0, 0, 1, 1, 0);
2052 }
2053 }
2054 }
2055
2056 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2057 {
2058 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2059 struct gallivm_state *gallivm = bld_base->base.gallivm;
2060 LLVMValueRef args[2];
2061
2062 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2063 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2064 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2065 LLVMVoidTypeInContext(gallivm->context), args, 2,
2066 LLVMNoUnwindAttribute);
2067 }
2068
2069 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
2070 {
2071 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2072 struct gallivm_state *gallivm = bld_base->base.gallivm;
2073 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
2074 struct si_shader_output_values *outputs = NULL;
2075 int i,j;
2076
2077 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2078
2079 for (i = 0; i < info->num_outputs; i++) {
2080 outputs[i].name = info->output_semantic_name[i];
2081 outputs[i].sid = info->output_semantic_index[i];
2082
2083 for (j = 0; j < 4; j++)
2084 outputs[i].values[j] =
2085 LLVMBuildLoad(gallivm->builder,
2086 si_shader_ctx->radeon_bld.soa.outputs[i][j],
2087 "");
2088 }
2089
2090 /* Export PrimitiveID when PS needs it. */
2091 if (si_vs_exports_prim_id(si_shader_ctx->shader)) {
2092 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2093 outputs[i].sid = 0;
2094 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2095 get_primitive_id(bld_base, 0));
2096 outputs[i].values[1] = bld_base->base.undef;
2097 outputs[i].values[2] = bld_base->base.undef;
2098 outputs[i].values[3] = bld_base->base.undef;
2099 i++;
2100 }
2101
2102 si_llvm_export_vs(bld_base, outputs, i);
2103 FREE(outputs);
2104 }
2105
2106 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
2107 {
2108 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
2109 struct si_shader * shader = si_shader_ctx->shader;
2110 struct lp_build_context * base = &bld_base->base;
2111 struct lp_build_context * uint = &bld_base->uint_bld;
2112 struct tgsi_shader_info *info = &shader->selector->info;
2113 LLVMValueRef args[9];
2114 LLVMValueRef last_args[9] = { 0 };
2115 int depth_index = -1, stencil_index = -1, samplemask_index = -1;
2116 int i;
2117
2118 for (i = 0; i < info->num_outputs; i++) {
2119 unsigned semantic_name = info->output_semantic_name[i];
2120 unsigned semantic_index = info->output_semantic_index[i];
2121 unsigned target;
2122 LLVMValueRef alpha_ptr;
2123
2124 /* Select the correct target */
2125 switch (semantic_name) {
2126 case TGSI_SEMANTIC_POSITION:
2127 depth_index = i;
2128 continue;
2129 case TGSI_SEMANTIC_STENCIL:
2130 stencil_index = i;
2131 continue;
2132 case TGSI_SEMANTIC_SAMPLEMASK:
2133 samplemask_index = i;
2134 continue;
2135 case TGSI_SEMANTIC_COLOR:
2136 target = V_008DFC_SQ_EXP_MRT + semantic_index;
2137 alpha_ptr = si_shader_ctx->radeon_bld.soa.outputs[i][3];
2138
2139 if (si_shader_ctx->shader->key.ps.alpha_to_one)
2140 LLVMBuildStore(base->gallivm->builder,
2141 base->one, alpha_ptr);
2142
2143 if (semantic_index == 0 &&
2144 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
2145 si_alpha_test(bld_base, alpha_ptr);
2146
2147 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
2148 si_scale_alpha_by_sample_mask(bld_base, alpha_ptr);
2149 break;
2150 default:
2151 target = 0;
2152 fprintf(stderr,
2153 "Warning: SI unhandled fs output type:%d\n",
2154 semantic_name);
2155 }
2156
2157 si_llvm_init_export_args_load(bld_base,
2158 si_shader_ctx->radeon_bld.soa.outputs[i],
2159 target, args);
2160
2161 if (semantic_name == TGSI_SEMANTIC_COLOR) {
2162 /* If there is an export instruction waiting to be emitted, do so now. */
2163 if (last_args[0]) {
2164 lp_build_intrinsic(base->gallivm->builder,
2165 "llvm.SI.export",
2166 LLVMVoidTypeInContext(base->gallivm->context),
2167 last_args, 9, 0);
2168 }
2169
2170 /* This instruction will be emitted at the end of the shader. */
2171 memcpy(last_args, args, sizeof(args));
2172
2173 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
2174 if (shader->selector->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
2175 semantic_index == 0 &&
2176 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
2177 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
2178 si_llvm_init_export_args_load(bld_base,
2179 si_shader_ctx->radeon_bld.soa.outputs[i],
2180 V_008DFC_SQ_EXP_MRT + c, args);
2181 lp_build_intrinsic(base->gallivm->builder,
2182 "llvm.SI.export",
2183 LLVMVoidTypeInContext(base->gallivm->context),
2184 args, 9, 0);
2185 }
2186 }
2187 } else {
2188 lp_build_intrinsic(base->gallivm->builder,
2189 "llvm.SI.export",
2190 LLVMVoidTypeInContext(base->gallivm->context),
2191 args, 9, 0);
2192 }
2193 }
2194
2195 if (depth_index >= 0 || stencil_index >= 0 || samplemask_index >= 0) {
2196 LLVMValueRef out_ptr;
2197 unsigned mask = 0;
2198
2199 /* Specify the target we are exporting */
2200 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2201
2202 args[5] = base->zero; /* R, depth */
2203 args[6] = base->zero; /* G, stencil test value[0:7], stencil op value[8:15] */
2204 args[7] = base->zero; /* B, sample mask */
2205 args[8] = base->zero; /* A, alpha to mask */
2206
2207 if (depth_index >= 0) {
2208 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
2209 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2210 mask |= 0x1;
2211 si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2212 }
2213
2214 if (stencil_index >= 0) {
2215 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
2216 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2217 mask |= 0x2;
2218 si_shader_ctx->shader->db_shader_control |=
2219 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
2220 }
2221
2222 if (samplemask_index >= 0) {
2223 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[samplemask_index][0];
2224 args[7] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2225 mask |= 0x4;
2226 si_shader_ctx->shader->db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(1);
2227 }
2228
2229 /* SI (except OLAND) has a bug that it only looks
2230 * at the X writemask component. */
2231 if (si_shader_ctx->screen->b.chip_class == SI &&
2232 si_shader_ctx->screen->b.family != CHIP_OLAND)
2233 mask |= 0x1;
2234
2235 if (samplemask_index >= 0)
2236 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
2237 else if (stencil_index >= 0)
2238 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
2239 else
2240 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
2241
2242 /* Specify which components to enable */
2243 args[0] = lp_build_const_int32(base->gallivm, mask);
2244
2245 args[1] =
2246 args[2] =
2247 args[4] = uint->zero;
2248
2249 if (last_args[0])
2250 lp_build_intrinsic(base->gallivm->builder,
2251 "llvm.SI.export",
2252 LLVMVoidTypeInContext(base->gallivm->context),
2253 args, 9, 0);
2254 else
2255 memcpy(last_args, args, sizeof(args));
2256 }
2257
2258 if (!last_args[0]) {
2259 /* Specify which components to enable */
2260 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
2261
2262 /* Specify the target we are exporting */
2263 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
2264
2265 /* Set COMPR flag to zero to export data as 32-bit */
2266 last_args[4] = uint->zero;
2267
2268 /* dummy bits */
2269 last_args[5]= uint->zero;
2270 last_args[6]= uint->zero;
2271 last_args[7]= uint->zero;
2272 last_args[8]= uint->zero;
2273 }
2274
2275 /* Specify whether the EXEC mask represents the valid mask */
2276 last_args[1] = uint->one;
2277
2278 /* Specify that this is the last export */
2279 last_args[2] = lp_build_const_int32(base->gallivm, 1);
2280
2281 lp_build_intrinsic(base->gallivm->builder,
2282 "llvm.SI.export",
2283 LLVMVoidTypeInContext(base->gallivm->context),
2284 last_args, 9, 0);
2285 }
2286
2287 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2288 struct lp_build_tgsi_context * bld_base,
2289 struct lp_build_emit_data * emit_data);
2290
2291 static bool tgsi_is_array_sampler(unsigned target)
2292 {
2293 return target == TGSI_TEXTURE_1D_ARRAY ||
2294 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2295 target == TGSI_TEXTURE_2D_ARRAY ||
2296 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2297 target == TGSI_TEXTURE_CUBE_ARRAY ||
2298 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2299 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2300 }
2301
2302 static void set_tex_fetch_args(struct gallivm_state *gallivm,
2303 struct lp_build_emit_data *emit_data,
2304 unsigned opcode, unsigned target,
2305 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
2306 LLVMValueRef *param, unsigned count,
2307 unsigned dmask)
2308 {
2309 unsigned num_args;
2310 unsigned is_rect = target == TGSI_TEXTURE_RECT;
2311 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2312
2313 /* Pad to power of two vector */
2314 while (count < util_next_power_of_two(count))
2315 param[count++] = LLVMGetUndef(i32);
2316
2317 /* Texture coordinates. */
2318 if (count > 1)
2319 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
2320 else
2321 emit_data->args[0] = param[0];
2322
2323 /* Resource. */
2324 emit_data->args[1] = res_ptr;
2325 num_args = 2;
2326
2327 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
2328 emit_data->dst_type = LLVMVectorType(i32, 4);
2329 else {
2330 emit_data->dst_type = LLVMVectorType(
2331 LLVMFloatTypeInContext(gallivm->context), 4);
2332
2333 emit_data->args[num_args++] = samp_ptr;
2334 }
2335
2336 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
2337 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
2338 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
2339 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
2340 tgsi_is_array_sampler(target)); /* da */
2341 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
2342 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
2343 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
2344 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
2345
2346 emit_data->arg_count = num_args;
2347 }
2348
2349 static const struct lp_build_tgsi_action tex_action;
2350
2351 static void tex_fetch_ptrs(
2352 struct lp_build_tgsi_context * bld_base,
2353 struct lp_build_emit_data * emit_data,
2354 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
2355 {
2356 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2357 struct gallivm_state *gallivm = bld_base->base.gallivm;
2358 const struct tgsi_full_instruction * inst = emit_data->inst;
2359 unsigned target = inst->Texture.Texture;
2360 unsigned sampler_src;
2361 unsigned sampler_index;
2362
2363 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
2364 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
2365
2366 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
2367 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
2368 LLVMValueRef ind_index;
2369
2370 ind_index = get_indirect_index(si_shader_ctx, &reg->Indirect, reg->Register.Index);
2371
2372 *res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2373 *res_ptr = build_indexed_load_const(si_shader_ctx, *res_ptr, ind_index);
2374
2375 *samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2376 *samp_ptr = build_indexed_load_const(si_shader_ctx, *samp_ptr, ind_index);
2377
2378 if (target == TGSI_TEXTURE_2D_MSAA ||
2379 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2380 ind_index = LLVMBuildAdd(gallivm->builder, ind_index,
2381 lp_build_const_int32(gallivm,
2382 SI_FMASK_TEX_OFFSET), "");
2383 *fmask_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2384 *fmask_ptr = build_indexed_load_const(si_shader_ctx, *fmask_ptr, ind_index);
2385 }
2386 } else {
2387 *res_ptr = si_shader_ctx->resources[sampler_index];
2388 *samp_ptr = si_shader_ctx->samplers[sampler_index];
2389 *fmask_ptr = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
2390 }
2391 }
2392
2393 static void tex_fetch_args(
2394 struct lp_build_tgsi_context * bld_base,
2395 struct lp_build_emit_data * emit_data)
2396 {
2397 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2398 struct gallivm_state *gallivm = bld_base->base.gallivm;
2399 LLVMBuilderRef builder = gallivm->builder;
2400 const struct tgsi_full_instruction * inst = emit_data->inst;
2401 unsigned opcode = inst->Instruction.Opcode;
2402 unsigned target = inst->Texture.Texture;
2403 LLVMValueRef coords[5], derivs[6];
2404 LLVMValueRef address[16];
2405 int ref_pos;
2406 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
2407 unsigned count = 0;
2408 unsigned chan;
2409 unsigned num_deriv_channels = 0;
2410 bool has_offset = inst->Texture.NumOffsets > 0;
2411 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2412 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2413 unsigned dmask = 0xf;
2414
2415 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2416
2417 if (opcode == TGSI_OPCODE_TXQ) {
2418 if (target == TGSI_TEXTURE_BUFFER) {
2419 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2420
2421 /* Read the size from the buffer descriptor directly. */
2422 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2423 LLVMValueRef size = LLVMBuildExtractElement(builder, res,
2424 lp_build_const_int32(gallivm, 6), "");
2425
2426 if (si_shader_ctx->screen->b.chip_class >= VI) {
2427 /* On VI, the descriptor contains the size in bytes,
2428 * but TXQ must return the size in elements.
2429 * The stride is always non-zero for resources using TXQ.
2430 */
2431 LLVMValueRef stride =
2432 LLVMBuildExtractElement(builder, res,
2433 lp_build_const_int32(gallivm, 5), "");
2434 stride = LLVMBuildLShr(builder, stride,
2435 lp_build_const_int32(gallivm, 16), "");
2436 stride = LLVMBuildAnd(builder, stride,
2437 lp_build_const_int32(gallivm, 0x3FFF), "");
2438
2439 size = LLVMBuildUDiv(builder, size, stride, "");
2440 }
2441
2442 emit_data->args[0] = size;
2443 return;
2444 }
2445
2446 /* Textures - set the mip level. */
2447 address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2448
2449 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2450 NULL, address, count, 0xf);
2451 return;
2452 }
2453
2454 if (target == TGSI_TEXTURE_BUFFER) {
2455 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
2456 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
2457 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
2458 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
2459
2460 /* Bitcast and truncate v8i32 to v16i8. */
2461 LLVMValueRef res = res_ptr;
2462 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
2463 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
2464 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
2465
2466 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
2467 emit_data->args[0] = res;
2468 emit_data->args[1] = bld_base->uint_bld.zero;
2469 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
2470 emit_data->arg_count = 3;
2471 return;
2472 }
2473
2474 /* Fetch and project texture coordinates */
2475 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
2476 for (chan = 0; chan < 3; chan++ ) {
2477 coords[chan] = lp_build_emit_fetch(bld_base,
2478 emit_data->inst, 0,
2479 chan);
2480 if (opcode == TGSI_OPCODE_TXP)
2481 coords[chan] = lp_build_emit_llvm_binary(bld_base,
2482 TGSI_OPCODE_DIV,
2483 coords[chan],
2484 coords[3]);
2485 }
2486
2487 if (opcode == TGSI_OPCODE_TXP)
2488 coords[3] = bld_base->base.one;
2489
2490 /* Pack offsets. */
2491 if (has_offset && opcode != TGSI_OPCODE_TXF) {
2492 /* The offsets are six-bit signed integers packed like this:
2493 * X=[5:0], Y=[13:8], and Z=[21:16].
2494 */
2495 LLVMValueRef offset[3], pack;
2496
2497 assert(inst->Texture.NumOffsets == 1);
2498
2499 for (chan = 0; chan < 3; chan++) {
2500 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
2501 emit_data->inst, 0, chan);
2502 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
2503 lp_build_const_int32(gallivm, 0x3f), "");
2504 if (chan)
2505 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
2506 lp_build_const_int32(gallivm, chan*8), "");
2507 }
2508
2509 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
2510 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
2511 address[count++] = pack;
2512 }
2513
2514 /* Pack LOD bias value */
2515 if (opcode == TGSI_OPCODE_TXB)
2516 address[count++] = coords[3];
2517 if (opcode == TGSI_OPCODE_TXB2)
2518 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2519
2520 /* Pack depth comparison value */
2521 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
2522 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2523 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2524 } else {
2525 assert(ref_pos >= 0);
2526 address[count++] = coords[ref_pos];
2527 }
2528 }
2529
2530 /* Pack user derivatives */
2531 if (opcode == TGSI_OPCODE_TXD) {
2532 int param, num_src_deriv_channels;
2533
2534 switch (target) {
2535 case TGSI_TEXTURE_3D:
2536 num_src_deriv_channels = 3;
2537 num_deriv_channels = 3;
2538 break;
2539 case TGSI_TEXTURE_2D:
2540 case TGSI_TEXTURE_SHADOW2D:
2541 case TGSI_TEXTURE_RECT:
2542 case TGSI_TEXTURE_SHADOWRECT:
2543 case TGSI_TEXTURE_2D_ARRAY:
2544 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2545 num_src_deriv_channels = 2;
2546 num_deriv_channels = 2;
2547 break;
2548 case TGSI_TEXTURE_CUBE:
2549 case TGSI_TEXTURE_SHADOWCUBE:
2550 case TGSI_TEXTURE_CUBE_ARRAY:
2551 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
2552 /* Cube derivatives will be converted to 2D. */
2553 num_src_deriv_channels = 3;
2554 num_deriv_channels = 2;
2555 break;
2556 case TGSI_TEXTURE_1D:
2557 case TGSI_TEXTURE_SHADOW1D:
2558 case TGSI_TEXTURE_1D_ARRAY:
2559 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2560 num_src_deriv_channels = 1;
2561 num_deriv_channels = 1;
2562 break;
2563 default:
2564 unreachable("invalid target");
2565 }
2566
2567 for (param = 0; param < 2; param++)
2568 for (chan = 0; chan < num_src_deriv_channels; chan++)
2569 derivs[param * num_src_deriv_channels + chan] =
2570 lp_build_emit_fetch(bld_base, inst, param+1, chan);
2571 }
2572
2573 if (target == TGSI_TEXTURE_CUBE ||
2574 target == TGSI_TEXTURE_CUBE_ARRAY ||
2575 target == TGSI_TEXTURE_SHADOWCUBE ||
2576 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2577 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
2578
2579 if (opcode == TGSI_OPCODE_TXD)
2580 for (int i = 0; i < num_deriv_channels * 2; i++)
2581 address[count++] = derivs[i];
2582
2583 /* Pack texture coordinates */
2584 address[count++] = coords[0];
2585 if (num_coords > 1)
2586 address[count++] = coords[1];
2587 if (num_coords > 2)
2588 address[count++] = coords[2];
2589
2590 /* Pack LOD or sample index */
2591 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
2592 address[count++] = coords[3];
2593 else if (opcode == TGSI_OPCODE_TXL2)
2594 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2595
2596 if (count > 16) {
2597 assert(!"Cannot handle more than 16 texture address parameters");
2598 count = 16;
2599 }
2600
2601 for (chan = 0; chan < count; chan++ ) {
2602 address[chan] = LLVMBuildBitCast(gallivm->builder,
2603 address[chan], i32, "");
2604 }
2605
2606 /* Adjust the sample index according to FMASK.
2607 *
2608 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2609 * which is the identity mapping. Each nibble says which physical sample
2610 * should be fetched to get that sample.
2611 *
2612 * For example, 0x11111100 means there are only 2 samples stored and
2613 * the second sample covers 3/4 of the pixel. When reading samples 0
2614 * and 1, return physical sample 0 (determined by the first two 0s
2615 * in FMASK), otherwise return physical sample 1.
2616 *
2617 * The sample index should be adjusted as follows:
2618 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2619 */
2620 if (target == TGSI_TEXTURE_2D_MSAA ||
2621 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2622 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2623 struct lp_build_emit_data txf_emit_data = *emit_data;
2624 LLVMValueRef txf_address[4];
2625 unsigned txf_count = count;
2626 struct tgsi_full_instruction inst = {};
2627
2628 memcpy(txf_address, address, sizeof(txf_address));
2629
2630 if (target == TGSI_TEXTURE_2D_MSAA) {
2631 txf_address[2] = bld_base->uint_bld.zero;
2632 }
2633 txf_address[3] = bld_base->uint_bld.zero;
2634
2635 /* Read FMASK using TXF. */
2636 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
2637 inst.Texture.Texture = target;
2638 txf_emit_data.inst = &inst;
2639 txf_emit_data.chan = 0;
2640 set_tex_fetch_args(gallivm, &txf_emit_data, TGSI_OPCODE_TXF,
2641 target, fmask_ptr, NULL,
2642 txf_address, txf_count, 0xf);
2643 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
2644
2645 /* Initialize some constants. */
2646 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
2647 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
2648
2649 /* Apply the formula. */
2650 LLVMValueRef fmask =
2651 LLVMBuildExtractElement(gallivm->builder,
2652 txf_emit_data.output[0],
2653 uint_bld->zero, "");
2654
2655 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
2656
2657 LLVMValueRef sample_index4 =
2658 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
2659
2660 LLVMValueRef shifted_fmask =
2661 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
2662
2663 LLVMValueRef final_sample =
2664 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
2665
2666 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2667 * resource descriptor is 0 (invalid),
2668 */
2669 LLVMValueRef fmask_desc =
2670 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
2671 LLVMVectorType(uint_bld->elem_type, 8), "");
2672
2673 LLVMValueRef fmask_word1 =
2674 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
2675 uint_bld->one, "");
2676
2677 LLVMValueRef word1_is_nonzero =
2678 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
2679 fmask_word1, uint_bld->zero, "");
2680
2681 /* Replace the MSAA sample index. */
2682 address[sample_chan] =
2683 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
2684 final_sample, address[sample_chan], "");
2685 }
2686
2687 if (opcode == TGSI_OPCODE_TXF) {
2688 /* add tex offsets */
2689 if (inst->Texture.NumOffsets) {
2690 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2691 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
2692 const struct tgsi_texture_offset * off = inst->TexOffsets;
2693
2694 assert(inst->Texture.NumOffsets == 1);
2695
2696 switch (target) {
2697 case TGSI_TEXTURE_3D:
2698 address[2] = lp_build_add(uint_bld, address[2],
2699 bld->immediates[off->Index][off->SwizzleZ]);
2700 /* fall through */
2701 case TGSI_TEXTURE_2D:
2702 case TGSI_TEXTURE_SHADOW2D:
2703 case TGSI_TEXTURE_RECT:
2704 case TGSI_TEXTURE_SHADOWRECT:
2705 case TGSI_TEXTURE_2D_ARRAY:
2706 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2707 address[1] =
2708 lp_build_add(uint_bld, address[1],
2709 bld->immediates[off->Index][off->SwizzleY]);
2710 /* fall through */
2711 case TGSI_TEXTURE_1D:
2712 case TGSI_TEXTURE_SHADOW1D:
2713 case TGSI_TEXTURE_1D_ARRAY:
2714 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2715 address[0] =
2716 lp_build_add(uint_bld, address[0],
2717 bld->immediates[off->Index][off->SwizzleX]);
2718 break;
2719 /* texture offsets do not apply to other texture targets */
2720 }
2721 }
2722 }
2723
2724 if (opcode == TGSI_OPCODE_TG4) {
2725 unsigned gather_comp = 0;
2726
2727 /* DMASK was repurposed for GATHER4. 4 components are always
2728 * returned and DMASK works like a swizzle - it selects
2729 * the component to fetch. The only valid DMASK values are
2730 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2731 * (red,red,red,red) etc.) The ISA document doesn't mention
2732 * this.
2733 */
2734
2735 /* Get the component index from src1.x for Gather4. */
2736 if (!tgsi_is_shadow_target(target)) {
2737 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
2738 LLVMValueRef comp_imm;
2739 struct tgsi_src_register src1 = inst->Src[1].Register;
2740
2741 assert(src1.File == TGSI_FILE_IMMEDIATE);
2742
2743 comp_imm = imms[src1.Index][src1.SwizzleX];
2744 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
2745 gather_comp = CLAMP(gather_comp, 0, 3);
2746 }
2747
2748 dmask = 1 << gather_comp;
2749 }
2750
2751 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2752 samp_ptr, address, count, dmask);
2753 }
2754
2755 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2756 struct lp_build_tgsi_context * bld_base,
2757 struct lp_build_emit_data * emit_data)
2758 {
2759 struct lp_build_context * base = &bld_base->base;
2760 unsigned opcode = emit_data->inst->Instruction.Opcode;
2761 unsigned target = emit_data->inst->Texture.Texture;
2762 char intr_name[127];
2763 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
2764 bool is_shadow = tgsi_is_shadow_target(target);
2765 char type[64];
2766 const char *name = "llvm.SI.image.sample";
2767 const char *infix = "";
2768
2769 if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
2770 /* Just return the buffer size. */
2771 emit_data->output[emit_data->chan] = emit_data->args[0];
2772 return;
2773 }
2774
2775 if (target == TGSI_TEXTURE_BUFFER) {
2776 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2777 base->gallivm->builder,
2778 "llvm.SI.vs.load.input", emit_data->dst_type,
2779 emit_data->args, emit_data->arg_count,
2780 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2781 return;
2782 }
2783
2784 switch (opcode) {
2785 case TGSI_OPCODE_TXF:
2786 name = target == TGSI_TEXTURE_2D_MSAA ||
2787 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
2788 "llvm.SI.image.load" :
2789 "llvm.SI.image.load.mip";
2790 is_shadow = false;
2791 has_offset = false;
2792 break;
2793 case TGSI_OPCODE_TXQ:
2794 name = "llvm.SI.getresinfo";
2795 is_shadow = false;
2796 has_offset = false;
2797 break;
2798 case TGSI_OPCODE_LODQ:
2799 name = "llvm.SI.getlod";
2800 is_shadow = false;
2801 has_offset = false;
2802 break;
2803 case TGSI_OPCODE_TEX:
2804 case TGSI_OPCODE_TEX2:
2805 case TGSI_OPCODE_TXP:
2806 break;
2807 case TGSI_OPCODE_TXB:
2808 case TGSI_OPCODE_TXB2:
2809 infix = ".b";
2810 break;
2811 case TGSI_OPCODE_TXL:
2812 case TGSI_OPCODE_TXL2:
2813 infix = ".l";
2814 break;
2815 case TGSI_OPCODE_TXD:
2816 infix = ".d";
2817 break;
2818 case TGSI_OPCODE_TG4:
2819 name = "llvm.SI.gather4";
2820 break;
2821 default:
2822 assert(0);
2823 return;
2824 }
2825
2826 if (LLVMGetTypeKind(LLVMTypeOf(emit_data->args[0])) == LLVMVectorTypeKind)
2827 sprintf(type, ".v%ui32",
2828 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2829 else
2830 strcpy(type, ".i32");
2831
2832 /* Add the type and suffixes .c, .o if needed. */
2833 sprintf(intr_name, "%s%s%s%s%s",
2834 name, is_shadow ? ".c" : "", infix,
2835 has_offset ? ".o" : "", type);
2836
2837 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2838 base->gallivm->builder, intr_name, emit_data->dst_type,
2839 emit_data->args, emit_data->arg_count,
2840 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2841
2842 /* Divide the number of layers by 6 to get the number of cubes. */
2843 if (opcode == TGSI_OPCODE_TXQ &&
2844 (target == TGSI_TEXTURE_CUBE_ARRAY ||
2845 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
2846 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2847 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2848 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2849
2850 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2851 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2852 z = LLVMBuildSDiv(builder, z, six, "");
2853
2854 emit_data->output[emit_data->chan] =
2855 LLVMBuildInsertElement(builder, v4, z, two, "");
2856 }
2857 }
2858
2859 static void si_llvm_emit_txqs(
2860 const struct lp_build_tgsi_action * action,
2861 struct lp_build_tgsi_context * bld_base,
2862 struct lp_build_emit_data * emit_data)
2863 {
2864 struct gallivm_state *gallivm = bld_base->base.gallivm;
2865 LLVMBuilderRef builder = gallivm->builder;
2866 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2867 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2868 LLVMValueRef res, samples;
2869 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2870
2871 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2872
2873
2874 /* Read the samples from the descriptor directly. */
2875 res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2876 samples = LLVMBuildExtractElement(
2877 builder, res,
2878 lp_build_const_int32(gallivm, 3), "");
2879 samples = LLVMBuildLShr(builder, samples,
2880 lp_build_const_int32(gallivm, 16), "");
2881 samples = LLVMBuildAnd(builder, samples,
2882 lp_build_const_int32(gallivm, 0xf), "");
2883 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
2884 samples, "");
2885
2886 emit_data->output[emit_data->chan] = samples;
2887 }
2888
2889 /*
2890 * SI implements derivatives using the local data store (LDS)
2891 * All writes to the LDS happen in all executing threads at
2892 * the same time. TID is the Thread ID for the current
2893 * thread and is a value between 0 and 63, representing
2894 * the thread's position in the wavefront.
2895 *
2896 * For the pixel shader threads are grouped into quads of four pixels.
2897 * The TIDs of the pixels of a quad are:
2898 *
2899 * +------+------+
2900 * |4n + 0|4n + 1|
2901 * +------+------+
2902 * |4n + 2|4n + 3|
2903 * +------+------+
2904 *
2905 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
2906 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
2907 * the current pixel's column, and masking with 0xfffffffe yields the TID
2908 * of the left pixel of the current pixel's row.
2909 *
2910 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
2911 * adding 2 yields the TID of the pixel below the top pixel.
2912 */
2913 /* masks for thread ID. */
2914 #define TID_MASK_TOP_LEFT 0xfffffffc
2915 #define TID_MASK_TOP 0xfffffffd
2916 #define TID_MASK_LEFT 0xfffffffe
2917
2918 static void si_llvm_emit_ddxy(
2919 const struct lp_build_tgsi_action * action,
2920 struct lp_build_tgsi_context * bld_base,
2921 struct lp_build_emit_data * emit_data)
2922 {
2923 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2924 struct gallivm_state *gallivm = bld_base->base.gallivm;
2925 struct lp_build_context * base = &bld_base->base;
2926 const struct tgsi_full_instruction *inst = emit_data->inst;
2927 unsigned opcode = inst->Instruction.Opcode;
2928 LLVMValueRef indices[2];
2929 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2930 LLVMValueRef tl, trbl, result[4];
2931 LLVMTypeRef i32;
2932 unsigned swizzle[4];
2933 unsigned c;
2934 int idx;
2935 unsigned mask;
2936
2937 i32 = LLVMInt32TypeInContext(gallivm->context);
2938
2939 indices[0] = bld_base->uint_bld.zero;
2940 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2941 NULL, 0, LLVMReadNoneAttribute);
2942 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2943 indices, 2, "");
2944
2945 if (opcode == TGSI_OPCODE_DDX_FINE)
2946 mask = TID_MASK_LEFT;
2947 else if (opcode == TGSI_OPCODE_DDY_FINE)
2948 mask = TID_MASK_TOP;
2949 else
2950 mask = TID_MASK_TOP_LEFT;
2951
2952 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2953 lp_build_const_int32(gallivm, mask), "");
2954 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2955 indices, 2, "");
2956
2957 /* for DDX we want to next X pixel, DDY next Y pixel. */
2958 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
2959 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
2960 lp_build_const_int32(gallivm, idx), "");
2961 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2962 indices, 2, "");
2963
2964 for (c = 0; c < 4; ++c) {
2965 unsigned i;
2966
2967 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
2968 for (i = 0; i < c; ++i) {
2969 if (swizzle[i] == swizzle[c]) {
2970 result[c] = result[i];
2971 break;
2972 }
2973 }
2974 if (i != c)
2975 continue;
2976
2977 LLVMBuildStore(gallivm->builder,
2978 LLVMBuildBitCast(gallivm->builder,
2979 lp_build_emit_fetch(bld_base, inst, 0, c),
2980 i32, ""),
2981 store_ptr);
2982
2983 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
2984 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
2985
2986 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
2987 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
2988
2989 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
2990 }
2991
2992 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
2993 }
2994
2995 /*
2996 * this takes an I,J coordinate pair,
2997 * and works out the X and Y derivatives.
2998 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
2999 */
3000 static LLVMValueRef si_llvm_emit_ddxy_interp(
3001 struct lp_build_tgsi_context *bld_base,
3002 LLVMValueRef interp_ij)
3003 {
3004 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3005 struct gallivm_state *gallivm = bld_base->base.gallivm;
3006 struct lp_build_context *base = &bld_base->base;
3007 LLVMValueRef indices[2];
3008 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
3009 LLVMValueRef tl, tr, bl, result[4];
3010 LLVMTypeRef i32;
3011 unsigned c;
3012
3013 i32 = LLVMInt32TypeInContext(gallivm->context);
3014
3015 indices[0] = bld_base->uint_bld.zero;
3016 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
3017 NULL, 0, LLVMReadNoneAttribute);
3018 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3019 indices, 2, "");
3020
3021 temp = LLVMBuildAnd(gallivm->builder, indices[1],
3022 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
3023
3024 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
3025 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
3026
3027 indices[1] = temp;
3028 load_ptr_x = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3029 indices, 2, "");
3030
3031 indices[1] = temp2;
3032 load_ptr_y = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3033 indices, 2, "");
3034
3035 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
3036 lp_build_const_int32(gallivm, 1), "");
3037 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3038 indices, 2, "");
3039
3040 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
3041 lp_build_const_int32(gallivm, 2), "");
3042 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3043 indices, 2, "");
3044
3045 for (c = 0; c < 2; ++c) {
3046 LLVMValueRef store_val;
3047 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
3048
3049 store_val = LLVMBuildExtractElement(gallivm->builder,
3050 interp_ij, c_ll, "");
3051 LLVMBuildStore(gallivm->builder,
3052 store_val,
3053 store_ptr);
3054
3055 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
3056 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3057
3058 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
3059 tr = LLVMBuildBitCast(gallivm->builder, tr, base->elem_type, "");
3060
3061 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
3062
3063 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
3064 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3065
3066 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
3067 bl = LLVMBuildBitCast(gallivm->builder, bl, base->elem_type, "");
3068
3069 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
3070 }
3071
3072 return lp_build_gather_values(gallivm, result, 4);
3073 }
3074
3075 static void interp_fetch_args(
3076 struct lp_build_tgsi_context *bld_base,
3077 struct lp_build_emit_data *emit_data)
3078 {
3079 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3080 struct gallivm_state *gallivm = bld_base->base.gallivm;
3081 const struct tgsi_full_instruction *inst = emit_data->inst;
3082
3083 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3084 /* offset is in second src, first two channels */
3085 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3086 emit_data->inst, 1,
3087 0);
3088 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3089 emit_data->inst, 1,
3090 1);
3091 emit_data->arg_count = 2;
3092 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3093 LLVMValueRef sample_position;
3094 LLVMValueRef sample_id;
3095 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
3096
3097 /* fetch sample ID, then fetch its sample position,
3098 * and place into first two channels.
3099 */
3100 sample_id = lp_build_emit_fetch(bld_base,
3101 emit_data->inst, 1, 0);
3102 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
3103 LLVMInt32TypeInContext(gallivm->context),
3104 "");
3105 sample_position = load_sample_position(&si_shader_ctx->radeon_bld, sample_id);
3106
3107 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
3108 sample_position,
3109 lp_build_const_int32(gallivm, 0), "");
3110
3111 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
3112 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
3113 sample_position,
3114 lp_build_const_int32(gallivm, 1), "");
3115 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
3116 emit_data->arg_count = 2;
3117 }
3118 }
3119
3120 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3121 struct lp_build_tgsi_context *bld_base,
3122 struct lp_build_emit_data *emit_data)
3123 {
3124 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3125 struct si_shader *shader = si_shader_ctx->shader;
3126 struct gallivm_state *gallivm = bld_base->base.gallivm;
3127 LLVMValueRef interp_param;
3128 const struct tgsi_full_instruction *inst = emit_data->inst;
3129 const char *intr_name;
3130 int input_index;
3131 int chan;
3132 int i;
3133 LLVMValueRef attr_number;
3134 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
3135 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
3136 int interp_param_idx;
3137 unsigned location;
3138
3139 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
3140 input_index = inst->Src[0].Register.Index;
3141
3142 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3143 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3144 location = TGSI_INTERPOLATE_LOC_CENTER;
3145 else
3146 location = TGSI_INTERPOLATE_LOC_CENTROID;
3147
3148 interp_param_idx = lookup_interp_param_index(shader->ps_input_interpolate[input_index],
3149 location);
3150 if (interp_param_idx == -1)
3151 return;
3152 else if (interp_param_idx)
3153 interp_param = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, interp_param_idx);
3154 else
3155 interp_param = NULL;
3156
3157 attr_number = lp_build_const_int32(gallivm,
3158 shader->ps_input_param_offset[input_index]);
3159
3160 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3161 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3162 LLVMValueRef ij_out[2];
3163 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3164
3165 /*
3166 * take the I then J parameters, and the DDX/Y for it, and
3167 * calculate the IJ inputs for the interpolator.
3168 * temp1 = ddx * offset/sample.x + I;
3169 * interp_param.I = ddy * offset/sample.y + temp1;
3170 * temp1 = ddx * offset/sample.x + J;
3171 * interp_param.J = ddy * offset/sample.y + temp1;
3172 */
3173 for (i = 0; i < 2; i++) {
3174 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
3175 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
3176 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
3177 ddxy_out, ix_ll, "");
3178 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
3179 ddxy_out, iy_ll, "");
3180 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
3181 interp_param, ix_ll, "");
3182 LLVMValueRef temp1, temp2;
3183
3184 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
3185 LLVMFloatTypeInContext(gallivm->context), "");
3186
3187 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
3188
3189 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
3190
3191 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
3192
3193 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
3194
3195 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
3196 temp2,
3197 LLVMIntTypeInContext(gallivm->context, 32), "");
3198 }
3199 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
3200 }
3201
3202 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3203 for (chan = 0; chan < 2; chan++) {
3204 LLVMValueRef args[4];
3205 LLVMValueRef llvm_chan;
3206 unsigned schan;
3207
3208 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3209 llvm_chan = lp_build_const_int32(gallivm, schan);
3210
3211 args[0] = llvm_chan;
3212 args[1] = attr_number;
3213 args[2] = params;
3214 args[3] = interp_param;
3215
3216 emit_data->output[chan] =
3217 lp_build_intrinsic(gallivm->builder, intr_name,
3218 input_type, args, args[3] ? 4 : 3,
3219 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3220 }
3221 }
3222
3223 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
3224 struct lp_build_emit_data *emit_data)
3225 {
3226 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3227 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
3228 unsigned stream;
3229
3230 assert(src0.File == TGSI_FILE_IMMEDIATE);
3231
3232 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
3233 return stream;
3234 }
3235
3236 /* Emit one vertex from the geometry shader */
3237 static void si_llvm_emit_vertex(
3238 const struct lp_build_tgsi_action *action,
3239 struct lp_build_tgsi_context *bld_base,
3240 struct lp_build_emit_data *emit_data)
3241 {
3242 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3243 struct lp_build_context *uint = &bld_base->uint_bld;
3244 struct si_shader *shader = si_shader_ctx->shader;
3245 struct tgsi_shader_info *info = &shader->selector->info;
3246 struct gallivm_state *gallivm = bld_base->base.gallivm;
3247 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
3248 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3249 SI_PARAM_GS2VS_OFFSET);
3250 LLVMValueRef gs_next_vertex;
3251 LLVMValueRef can_emit, kill;
3252 LLVMValueRef args[2];
3253 unsigned chan;
3254 int i;
3255 unsigned stream;
3256
3257 stream = si_llvm_get_stream(bld_base, emit_data);
3258
3259 /* Write vertex attribute values to GSVS ring */
3260 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
3261 si_shader_ctx->gs_next_vertex[stream],
3262 "");
3263
3264 /* If this thread has already emitted the declared maximum number of
3265 * vertices, kill it: excessive vertex emissions are not supposed to
3266 * have any effect, and GS threads have no externally observable
3267 * effects other than emitting vertices.
3268 */
3269 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
3270 lp_build_const_int32(gallivm,
3271 shader->selector->gs_max_out_vertices), "");
3272 kill = lp_build_select(&bld_base->base, can_emit,
3273 lp_build_const_float(gallivm, 1.0f),
3274 lp_build_const_float(gallivm, -1.0f));
3275
3276 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
3277 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
3278
3279 for (i = 0; i < info->num_outputs; i++) {
3280 LLVMValueRef *out_ptr =
3281 si_shader_ctx->radeon_bld.soa.outputs[i];
3282
3283 for (chan = 0; chan < 4; chan++) {
3284 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3285 LLVMValueRef voffset =
3286 lp_build_const_int32(gallivm, (i * 4 + chan) *
3287 shader->selector->gs_max_out_vertices);
3288
3289 voffset = lp_build_add(uint, voffset, gs_next_vertex);
3290 voffset = lp_build_mul_imm(uint, voffset, 4);
3291
3292 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
3293
3294 build_tbuffer_store(si_shader_ctx,
3295 si_shader_ctx->gsvs_ring[stream],
3296 out_val, 1,
3297 voffset, soffset, 0,
3298 V_008F0C_BUF_DATA_FORMAT_32,
3299 V_008F0C_BUF_NUM_FORMAT_UINT,
3300 1, 0, 1, 1, 0);
3301 }
3302 }
3303 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
3304 lp_build_const_int32(gallivm, 1));
3305
3306 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex[stream]);
3307
3308 /* Signal vertex emission */
3309 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
3310 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3311 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3312 LLVMVoidTypeInContext(gallivm->context), args, 2,
3313 LLVMNoUnwindAttribute);
3314 }
3315
3316 /* Cut one primitive from the geometry shader */
3317 static void si_llvm_emit_primitive(
3318 const struct lp_build_tgsi_action *action,
3319 struct lp_build_tgsi_context *bld_base,
3320 struct lp_build_emit_data *emit_data)
3321 {
3322 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3323 struct gallivm_state *gallivm = bld_base->base.gallivm;
3324 LLVMValueRef args[2];
3325 unsigned stream;
3326
3327 /* Signal primitive cut */
3328 stream = si_llvm_get_stream(bld_base, emit_data);
3329 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
3330 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3331 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3332 LLVMVoidTypeInContext(gallivm->context), args, 2,
3333 LLVMNoUnwindAttribute);
3334 }
3335
3336 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
3337 struct lp_build_tgsi_context *bld_base,
3338 struct lp_build_emit_data *emit_data)
3339 {
3340 struct gallivm_state *gallivm = bld_base->base.gallivm;
3341
3342 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.barrier.local",
3343 LLVMVoidTypeInContext(gallivm->context), NULL, 0,
3344 LLVMNoUnwindAttribute);
3345 }
3346
3347 static const struct lp_build_tgsi_action tex_action = {
3348 .fetch_args = tex_fetch_args,
3349 .emit = build_tex_intrinsic,
3350 };
3351
3352 static const struct lp_build_tgsi_action interp_action = {
3353 .fetch_args = interp_fetch_args,
3354 .emit = build_interp_intrinsic,
3355 };
3356
3357 static void create_meta_data(struct si_shader_context *si_shader_ctx)
3358 {
3359 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3360 LLVMValueRef args[3];
3361
3362 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
3363 args[1] = 0;
3364 args[2] = lp_build_const_int32(gallivm, 1);
3365
3366 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
3367 }
3368
3369 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3370 {
3371 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3372 CONST_ADDR_SPACE);
3373 }
3374
3375 static void declare_streamout_params(struct si_shader_context *si_shader_ctx,
3376 struct pipe_stream_output_info *so,
3377 LLVMTypeRef *params, LLVMTypeRef i32,
3378 unsigned *num_params)
3379 {
3380 int i;
3381
3382 /* Streamout SGPRs. */
3383 if (so->num_outputs) {
3384 params[si_shader_ctx->param_streamout_config = (*num_params)++] = i32;
3385 params[si_shader_ctx->param_streamout_write_index = (*num_params)++] = i32;
3386 }
3387 /* A streamout buffer offset is loaded if the stride is non-zero. */
3388 for (i = 0; i < 4; i++) {
3389 if (!so->stride[i])
3390 continue;
3391
3392 params[si_shader_ctx->param_streamout_offset[i] = (*num_params)++] = i32;
3393 }
3394 }
3395
3396 static void create_function(struct si_shader_context *si_shader_ctx)
3397 {
3398 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3399 struct gallivm_state *gallivm = bld_base->base.gallivm;
3400 struct si_shader *shader = si_shader_ctx->shader;
3401 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
3402 unsigned i, last_array_pointer, last_sgpr, num_params;
3403
3404 i8 = LLVMInt8TypeInContext(gallivm->context);
3405 i32 = LLVMInt32TypeInContext(gallivm->context);
3406 f32 = LLVMFloatTypeInContext(gallivm->context);
3407 v2i32 = LLVMVectorType(i32, 2);
3408 v3i32 = LLVMVectorType(i32, 3);
3409 v4i32 = LLVMVectorType(i32, 4);
3410 v8i32 = LLVMVectorType(i32, 8);
3411 v16i8 = LLVMVectorType(i8, 16);
3412
3413 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
3414 params[SI_PARAM_CONST] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
3415 params[SI_PARAM_SAMPLER] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
3416 params[SI_PARAM_RESOURCE] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
3417 last_array_pointer = SI_PARAM_RESOURCE;
3418
3419 switch (si_shader_ctx->type) {
3420 case TGSI_PROCESSOR_VERTEX:
3421 params[SI_PARAM_VERTEX_BUFFER] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
3422 last_array_pointer = SI_PARAM_VERTEX_BUFFER;
3423 params[SI_PARAM_BASE_VERTEX] = i32;
3424 params[SI_PARAM_START_INSTANCE] = i32;
3425 num_params = SI_PARAM_START_INSTANCE+1;
3426
3427 if (shader->key.vs.as_es) {
3428 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3429 } else if (shader->key.vs.as_ls) {
3430 params[SI_PARAM_LS_OUT_LAYOUT] = i32;
3431 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
3432 } else {
3433 if (shader->is_gs_copy_shader) {
3434 last_array_pointer = SI_PARAM_CONST;
3435 num_params = SI_PARAM_CONST+1;
3436 }
3437
3438 /* The locations of the other parameters are assigned dynamically. */
3439 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3440 params, i32, &num_params);
3441 }
3442
3443 last_sgpr = num_params-1;
3444
3445 /* VGPRs */
3446 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
3447 params[si_shader_ctx->param_rel_auto_id = num_params++] = i32;
3448 params[si_shader_ctx->param_vs_prim_id = num_params++] = i32;
3449 params[si_shader_ctx->param_instance_id = num_params++] = i32;
3450 break;
3451
3452 case TGSI_PROCESSOR_TESS_CTRL:
3453 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3454 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3455 params[SI_PARAM_TCS_IN_LAYOUT] = i32;
3456 params[SI_PARAM_TESS_FACTOR_OFFSET] = i32;
3457 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
3458
3459 /* VGPRs */
3460 params[SI_PARAM_PATCH_ID] = i32;
3461 params[SI_PARAM_REL_IDS] = i32;
3462 num_params = SI_PARAM_REL_IDS+1;
3463 break;
3464
3465 case TGSI_PROCESSOR_TESS_EVAL:
3466 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3467 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3468 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
3469
3470 if (shader->key.tes.as_es) {
3471 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3472 } else {
3473 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3474 params, i32, &num_params);
3475 }
3476 last_sgpr = num_params - 1;
3477
3478 /* VGPRs */
3479 params[si_shader_ctx->param_tes_u = num_params++] = f32;
3480 params[si_shader_ctx->param_tes_v = num_params++] = f32;
3481 params[si_shader_ctx->param_tes_rel_patch_id = num_params++] = i32;
3482 params[si_shader_ctx->param_tes_patch_id = num_params++] = i32;
3483 break;
3484
3485 case TGSI_PROCESSOR_GEOMETRY:
3486 params[SI_PARAM_GS2VS_OFFSET] = i32;
3487 params[SI_PARAM_GS_WAVE_ID] = i32;
3488 last_sgpr = SI_PARAM_GS_WAVE_ID;
3489
3490 /* VGPRs */
3491 params[SI_PARAM_VTX0_OFFSET] = i32;
3492 params[SI_PARAM_VTX1_OFFSET] = i32;
3493 params[SI_PARAM_PRIMITIVE_ID] = i32;
3494 params[SI_PARAM_VTX2_OFFSET] = i32;
3495 params[SI_PARAM_VTX3_OFFSET] = i32;
3496 params[SI_PARAM_VTX4_OFFSET] = i32;
3497 params[SI_PARAM_VTX5_OFFSET] = i32;
3498 params[SI_PARAM_GS_INSTANCE_ID] = i32;
3499 num_params = SI_PARAM_GS_INSTANCE_ID+1;
3500 break;
3501
3502 case TGSI_PROCESSOR_FRAGMENT:
3503 params[SI_PARAM_ALPHA_REF] = f32;
3504 params[SI_PARAM_PS_STATE_BITS] = i32;
3505 params[SI_PARAM_PRIM_MASK] = i32;
3506 last_sgpr = SI_PARAM_PRIM_MASK;
3507 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
3508 params[SI_PARAM_PERSP_CENTER] = v2i32;
3509 params[SI_PARAM_PERSP_CENTROID] = v2i32;
3510 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
3511 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
3512 params[SI_PARAM_LINEAR_CENTER] = v2i32;
3513 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
3514 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
3515 params[SI_PARAM_POS_X_FLOAT] = f32;
3516 params[SI_PARAM_POS_Y_FLOAT] = f32;
3517 params[SI_PARAM_POS_Z_FLOAT] = f32;
3518 params[SI_PARAM_POS_W_FLOAT] = f32;
3519 params[SI_PARAM_FRONT_FACE] = f32;
3520 params[SI_PARAM_ANCILLARY] = i32;
3521 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
3522 params[SI_PARAM_POS_FIXED_PT] = f32;
3523 num_params = SI_PARAM_POS_FIXED_PT+1;
3524 break;
3525
3526 default:
3527 assert(0 && "unimplemented shader");
3528 return;
3529 }
3530
3531 assert(num_params <= Elements(params));
3532 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
3533 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
3534
3535 if (shader->dx10_clamp_mode)
3536 LLVMAddTargetDependentFunctionAttr(si_shader_ctx->radeon_bld.main_fn,
3537 "enable-no-nans-fp-math", "true");
3538
3539 for (i = 0; i <= last_sgpr; ++i) {
3540 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
3541
3542 /* We tell llvm that array inputs are passed by value to allow Sinking pass
3543 * to move load. Inputs are constant so this is fine. */
3544 if (i <= last_array_pointer)
3545 LLVMAddAttribute(P, LLVMByValAttribute);
3546 else
3547 LLVMAddAttribute(P, LLVMInRegAttribute);
3548 }
3549
3550 if (bld_base->info &&
3551 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
3552 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
3553 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
3554 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
3555 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
3556 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
3557 si_shader_ctx->lds =
3558 LLVMAddGlobalInAddressSpace(gallivm->module,
3559 LLVMArrayType(i32, 64),
3560 "ddxy_lds",
3561 LOCAL_ADDR_SPACE);
3562
3563 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
3564 si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
3565 si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL) {
3566 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
3567 unsigned vertex_data_dw_size = 32*32*4;
3568 unsigned patch_data_dw_size = 32*4;
3569 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
3570 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
3571 unsigned lds_dwords = patch_dw_size;
3572
3573 /* The actual size is computed outside of the shader to reduce
3574 * the number of shader variants. */
3575 si_shader_ctx->lds =
3576 LLVMAddGlobalInAddressSpace(gallivm->module,
3577 LLVMArrayType(i32, lds_dwords),
3578 "tess_lds",
3579 LOCAL_ADDR_SPACE);
3580 }
3581 }
3582
3583 static void preload_constants(struct si_shader_context *si_shader_ctx)
3584 {
3585 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3586 struct gallivm_state * gallivm = bld_base->base.gallivm;
3587 const struct tgsi_shader_info * info = bld_base->info;
3588 unsigned buf;
3589 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
3590
3591 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
3592 unsigned i, num_const = info->const_file_max[buf] + 1;
3593
3594 if (num_const == 0)
3595 continue;
3596
3597 /* Allocate space for the constant values */
3598 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
3599
3600 /* Load the resource descriptor */
3601 si_shader_ctx->const_resource[buf] =
3602 build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
3603
3604 /* Load the constants, we rely on the code sinking to do the rest */
3605 for (i = 0; i < num_const * 4; ++i) {
3606 si_shader_ctx->constants[buf][i] =
3607 buffer_load_const(gallivm->builder,
3608 si_shader_ctx->const_resource[buf],
3609 lp_build_const_int32(gallivm, i * 4),
3610 bld_base->base.elem_type);
3611 }
3612 }
3613 }
3614
3615 static void preload_samplers(struct si_shader_context *si_shader_ctx)
3616 {
3617 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3618 struct gallivm_state * gallivm = bld_base->base.gallivm;
3619 const struct tgsi_shader_info * info = bld_base->info;
3620
3621 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
3622
3623 LLVMValueRef res_ptr, samp_ptr;
3624 LLVMValueRef offset;
3625
3626 if (num_samplers == 0)
3627 return;
3628
3629 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
3630 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
3631
3632 /* Load the resources and samplers, we rely on the code sinking to do the rest */
3633 for (i = 0; i < num_samplers; ++i) {
3634 /* Resource */
3635 offset = lp_build_const_int32(gallivm, i);
3636 si_shader_ctx->resources[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3637
3638 /* Sampler */
3639 offset = lp_build_const_int32(gallivm, i);
3640 si_shader_ctx->samplers[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
3641
3642 /* FMASK resource */
3643 if (info->is_msaa_sampler[i]) {
3644 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
3645 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + i] =
3646 build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3647 }
3648 }
3649 }
3650
3651 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
3652 {
3653 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3654 struct gallivm_state * gallivm = bld_base->base.gallivm;
3655 unsigned i;
3656
3657 /* Streamout can only be used if the shader is compiled as VS. */
3658 if (!si_shader_ctx->shader->selector->so.num_outputs ||
3659 (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3660 (si_shader_ctx->shader->key.vs.as_es ||
3661 si_shader_ctx->shader->key.vs.as_ls)) ||
3662 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3663 si_shader_ctx->shader->key.tes.as_es))
3664 return;
3665
3666 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3667 SI_PARAM_RW_BUFFERS);
3668
3669 /* Load the resources, we rely on the code sinking to do the rest */
3670 for (i = 0; i < 4; ++i) {
3671 if (si_shader_ctx->shader->selector->so.stride[i]) {
3672 LLVMValueRef offset = lp_build_const_int32(gallivm,
3673 SI_SO_BUF_OFFSET + i);
3674
3675 si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3676 }
3677 }
3678 }
3679
3680 /**
3681 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
3682 * for later use.
3683 */
3684 static void preload_ring_buffers(struct si_shader_context *si_shader_ctx)
3685 {
3686 struct gallivm_state *gallivm =
3687 si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3688
3689 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3690 SI_PARAM_RW_BUFFERS);
3691
3692 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3693 si_shader_ctx->shader->key.vs.as_es) ||
3694 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3695 si_shader_ctx->shader->key.tes.as_es) ||
3696 si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3697 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
3698
3699 si_shader_ctx->esgs_ring =
3700 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3701 }
3702
3703 if (si_shader_ctx->shader->is_gs_copy_shader) {
3704 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
3705
3706 si_shader_ctx->gsvs_ring[0] =
3707 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3708 }
3709 if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3710 int i;
3711 for (i = 0; i < 4; i++) {
3712 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i);
3713
3714 si_shader_ctx->gsvs_ring[i] =
3715 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3716 }
3717 }
3718 }
3719
3720 void si_shader_binary_read_config(const struct si_screen *sscreen,
3721 struct si_shader *shader,
3722 unsigned symbol_offset)
3723 {
3724 unsigned i;
3725 const unsigned char *config =
3726 radeon_shader_binary_config_start(&shader->binary,
3727 symbol_offset);
3728
3729 /* XXX: We may be able to emit some of these values directly rather than
3730 * extracting fields to be emitted later.
3731 */
3732
3733 for (i = 0; i < shader->binary.config_size_per_symbol; i+= 8) {
3734 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
3735 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
3736 switch (reg) {
3737 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
3738 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
3739 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
3740 case R_00B848_COMPUTE_PGM_RSRC1:
3741 shader->num_sgprs = MAX2(shader->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
3742 shader->num_vgprs = MAX2(shader->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
3743 shader->float_mode = G_00B028_FLOAT_MODE(value);
3744 break;
3745 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
3746 shader->lds_size = MAX2(shader->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
3747 break;
3748 case R_00B84C_COMPUTE_PGM_RSRC2:
3749 shader->lds_size = MAX2(shader->lds_size, G_00B84C_LDS_SIZE(value));
3750 break;
3751 case R_0286CC_SPI_PS_INPUT_ENA:
3752 shader->spi_ps_input_ena = value;
3753 break;
3754 case R_0286E8_SPI_TMPRING_SIZE:
3755 case R_00B860_COMPUTE_TMPRING_SIZE:
3756 /* WAVESIZE is in units of 256 dwords. */
3757 shader->scratch_bytes_per_wave =
3758 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
3759 break;
3760 default:
3761 fprintf(stderr, "Warning: Compiler emitted unknown "
3762 "config register: 0x%x\n", reg);
3763 break;
3764 }
3765 }
3766 }
3767
3768 void si_shader_apply_scratch_relocs(struct si_context *sctx,
3769 struct si_shader *shader,
3770 uint64_t scratch_va)
3771 {
3772 unsigned i;
3773 uint32_t scratch_rsrc_dword0 = scratch_va;
3774 uint32_t scratch_rsrc_dword1 =
3775 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
3776 | S_008F04_STRIDE(shader->scratch_bytes_per_wave / 64);
3777
3778 for (i = 0 ; i < shader->binary.reloc_count; i++) {
3779 const struct radeon_shader_reloc *reloc =
3780 &shader->binary.relocs[i];
3781 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
3782 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3783 &scratch_rsrc_dword0, 4);
3784 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
3785 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3786 &scratch_rsrc_dword1, 4);
3787 }
3788 }
3789 }
3790
3791 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
3792 {
3793 const struct radeon_shader_binary *binary = &shader->binary;
3794 unsigned code_size = binary->code_size + binary->rodata_size;
3795 unsigned char *ptr;
3796
3797 r600_resource_reference(&shader->bo, NULL);
3798 shader->bo = si_resource_create_custom(&sscreen->b.b,
3799 PIPE_USAGE_IMMUTABLE,
3800 code_size);
3801 if (!shader->bo)
3802 return -ENOMEM;
3803
3804 ptr = sscreen->b.ws->buffer_map(shader->bo->cs_buf, NULL,
3805 PIPE_TRANSFER_READ_WRITE);
3806 util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
3807 if (binary->rodata_size > 0) {
3808 ptr += binary->code_size;
3809 util_memcpy_cpu_to_le32(ptr, binary->rodata,
3810 binary->rodata_size);
3811 }
3812
3813 sscreen->b.ws->buffer_unmap(shader->bo->cs_buf);
3814 return 0;
3815 }
3816
3817 int si_shader_binary_read(struct si_screen *sscreen, struct si_shader *shader)
3818 {
3819 const struct radeon_shader_binary *binary = &shader->binary;
3820 unsigned i;
3821 int r;
3822 bool dump = r600_can_dump_shader(&sscreen->b,
3823 shader->selector ? shader->selector->tokens : NULL);
3824
3825 si_shader_binary_read_config(sscreen, shader, 0);
3826 r = si_shader_binary_upload(sscreen, shader);
3827 if (r)
3828 return r;
3829
3830 if (dump) {
3831 if (!(sscreen->b.debug_flags & DBG_NO_ASM)) {
3832 if (binary->disasm_string) {
3833 fprintf(stderr, "\nShader Disassembly:\n\n");
3834 fprintf(stderr, "%s\n", binary->disasm_string);
3835 } else {
3836 fprintf(stderr, "SI CODE:\n");
3837 for (i = 0; i < binary->code_size; i+=4 ) {
3838 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i, binary->code[i + 3],
3839 binary->code[i + 2], binary->code[i + 1],
3840 binary->code[i]);
3841 }
3842 }
3843 }
3844
3845 fprintf(stderr, "*** SHADER STATS ***\n"
3846 "SGPRS: %d\nVGPRS: %d\nCode Size: %d bytes\nLDS: %d blocks\n"
3847 "Scratch: %d bytes per wave\n********************\n",
3848 shader->num_sgprs, shader->num_vgprs, binary->code_size,
3849 shader->lds_size, shader->scratch_bytes_per_wave);
3850 }
3851 return 0;
3852 }
3853
3854 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
3855 LLVMTargetMachineRef tm, LLVMModuleRef mod)
3856 {
3857 int r = 0;
3858 bool dump_asm = r600_can_dump_shader(&sscreen->b,
3859 shader->selector ? shader->selector->tokens : NULL);
3860 bool dump_ir = dump_asm && !(sscreen->b.debug_flags & DBG_NO_IR);
3861
3862 r = radeon_llvm_compile(mod, &shader->binary,
3863 r600_get_llvm_processor_name(sscreen->b.family), dump_ir, dump_asm, tm);
3864 if (r)
3865 return r;
3866
3867 r = si_shader_binary_read(sscreen, shader);
3868
3869 FREE(shader->binary.config);
3870 FREE(shader->binary.rodata);
3871 FREE(shader->binary.global_symbol_offsets);
3872 if (shader->scratch_bytes_per_wave == 0) {
3873 FREE(shader->binary.code);
3874 FREE(shader->binary.relocs);
3875 memset(&shader->binary, 0,
3876 offsetof(struct radeon_shader_binary, disasm_string));
3877 }
3878 return r;
3879 }
3880
3881 /* Generate code for the hardware VS shader stage to go with a geometry shader */
3882 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
3883 struct si_shader_context *si_shader_ctx,
3884 struct si_shader *gs, bool dump)
3885 {
3886 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
3887 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3888 struct lp_build_context *base = &bld_base->base;
3889 struct lp_build_context *uint = &bld_base->uint_bld;
3890 struct si_shader *shader = si_shader_ctx->shader;
3891 struct si_shader_output_values *outputs;
3892 struct tgsi_shader_info *gsinfo = &gs->selector->info;
3893 LLVMValueRef args[9];
3894 int i, r;
3895
3896 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
3897
3898 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
3899 shader->is_gs_copy_shader = true;
3900
3901 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
3902
3903 create_meta_data(si_shader_ctx);
3904 create_function(si_shader_ctx);
3905 preload_streamout_buffers(si_shader_ctx);
3906 preload_ring_buffers(si_shader_ctx);
3907
3908 args[0] = si_shader_ctx->gsvs_ring[0];
3909 args[1] = lp_build_mul_imm(uint,
3910 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3911 si_shader_ctx->param_vertex_id),
3912 4);
3913 args[3] = uint->zero;
3914 args[4] = uint->one; /* OFFEN */
3915 args[5] = uint->zero; /* IDXEN */
3916 args[6] = uint->one; /* GLC */
3917 args[7] = uint->one; /* SLC */
3918 args[8] = uint->zero; /* TFE */
3919
3920 /* Fetch vertex data from GSVS ring */
3921 for (i = 0; i < gsinfo->num_outputs; ++i) {
3922 unsigned chan;
3923
3924 outputs[i].name = gsinfo->output_semantic_name[i];
3925 outputs[i].sid = gsinfo->output_semantic_index[i];
3926
3927 for (chan = 0; chan < 4; chan++) {
3928 args[2] = lp_build_const_int32(gallivm,
3929 (i * 4 + chan) *
3930 gs->selector->gs_max_out_vertices * 16 * 4);
3931
3932 outputs[i].values[chan] =
3933 LLVMBuildBitCast(gallivm->builder,
3934 lp_build_intrinsic(gallivm->builder,
3935 "llvm.SI.buffer.load.dword.i32.i32",
3936 LLVMInt32TypeInContext(gallivm->context),
3937 args, 9,
3938 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
3939 base->elem_type, "");
3940 }
3941 }
3942
3943 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
3944
3945 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
3946
3947 if (dump)
3948 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
3949
3950 r = si_compile_llvm(sscreen, si_shader_ctx->shader,
3951 si_shader_ctx->tm, bld_base->base.gallivm->module);
3952
3953 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
3954
3955 FREE(outputs);
3956 return r;
3957 }
3958
3959 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
3960 {
3961 int i;
3962
3963 fprintf(f, "SHADER KEY\n");
3964
3965 switch (shader) {
3966 case PIPE_SHADER_VERTEX:
3967 fprintf(f, " instance_divisors = {");
3968 for (i = 0; i < Elements(key->vs.instance_divisors); i++)
3969 fprintf(f, !i ? "%u" : ", %u",
3970 key->vs.instance_divisors[i]);
3971 fprintf(f, "}\n");
3972
3973 if (key->vs.as_es)
3974 fprintf(f, " es_enabled_outputs = 0x%"PRIx64"\n",
3975 key->vs.es_enabled_outputs);
3976 fprintf(f, " as_es = %u\n", key->vs.as_es);
3977 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
3978 fprintf(f, " export_prim_id = %u\n", key->vs.export_prim_id);
3979 break;
3980
3981 case PIPE_SHADER_TESS_CTRL:
3982 fprintf(f, " prim_mode = %u\n", key->tcs.prim_mode);
3983 break;
3984
3985 case PIPE_SHADER_TESS_EVAL:
3986 if (key->tes.as_es)
3987 fprintf(f, " es_enabled_outputs = 0x%"PRIx64"\n",
3988 key->tes.es_enabled_outputs);
3989 fprintf(f, " as_es = %u\n", key->tes.as_es);
3990 fprintf(f, " export_prim_id = %u\n", key->tes.export_prim_id);
3991 break;
3992
3993 case PIPE_SHADER_GEOMETRY:
3994 break;
3995
3996 case PIPE_SHADER_FRAGMENT:
3997 fprintf(f, " export_16bpc = 0x%X\n", key->ps.export_16bpc);
3998 fprintf(f, " last_cbuf = %u\n", key->ps.last_cbuf);
3999 fprintf(f, " color_two_side = %u\n", key->ps.color_two_side);
4000 fprintf(f, " alpha_func = %u\n", key->ps.alpha_func);
4001 fprintf(f, " alpha_to_one = %u\n", key->ps.alpha_to_one);
4002 fprintf(f, " poly_stipple = %u\n", key->ps.poly_stipple);
4003 break;
4004
4005 default:
4006 assert(0);
4007 }
4008 }
4009
4010 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
4011 struct si_shader *shader)
4012 {
4013 struct si_shader_selector *sel = shader->selector;
4014 struct tgsi_token *tokens = sel->tokens;
4015 struct si_shader_context si_shader_ctx;
4016 struct lp_build_tgsi_context * bld_base;
4017 struct tgsi_shader_info stipple_shader_info;
4018 LLVMModuleRef mod;
4019 int r = 0;
4020 bool poly_stipple = sel->type == PIPE_SHADER_FRAGMENT &&
4021 shader->key.ps.poly_stipple;
4022 bool dump = r600_can_dump_shader(&sscreen->b, sel->tokens);
4023
4024 if (poly_stipple) {
4025 tokens = util_pstipple_create_fragment_shader(tokens, NULL,
4026 SI_POLY_STIPPLE_SAMPLER);
4027 tgsi_scan_shader(tokens, &stipple_shader_info);
4028 }
4029
4030 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
4031 * conversion fails. */
4032 if (dump && !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
4033 si_dump_shader_key(sel->type, &shader->key, stderr);
4034 tgsi_dump(tokens, 0);
4035 si_dump_streamout(&sel->so);
4036 }
4037
4038 assert(shader->nparam == 0);
4039
4040 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
4041 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
4042 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
4043
4044 if (sel->type != PIPE_SHADER_COMPUTE)
4045 shader->dx10_clamp_mode = true;
4046
4047 if (sel->info.uses_kill)
4048 shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
4049
4050 shader->uses_instanceid = sel->info.uses_instanceid;
4051 bld_base->info = poly_stipple ? &stipple_shader_info : &sel->info;
4052 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
4053
4054 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
4055 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
4056 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
4057
4058 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
4059 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
4060 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
4061 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
4062 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
4063 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
4064 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
4065 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
4066 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
4067 bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
4068 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
4069 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
4070 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
4071
4072 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
4073 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
4074 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
4075 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
4076
4077 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
4078 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
4079 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
4080
4081 if (HAVE_LLVM >= 0x0306) {
4082 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
4083 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
4084 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
4085 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
4086 }
4087
4088 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
4089 si_shader_ctx.shader = shader;
4090 si_shader_ctx.type = tgsi_get_processor_type(tokens);
4091 si_shader_ctx.screen = sscreen;
4092 si_shader_ctx.tm = tm;
4093
4094 switch (si_shader_ctx.type) {
4095 case TGSI_PROCESSOR_VERTEX:
4096 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
4097 if (shader->key.vs.as_ls)
4098 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
4099 else if (shader->key.vs.as_es)
4100 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4101 else
4102 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4103 break;
4104 case TGSI_PROCESSOR_TESS_CTRL:
4105 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
4106 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
4107 bld_base->emit_store = store_output_tcs;
4108 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
4109 break;
4110 case TGSI_PROCESSOR_TESS_EVAL:
4111 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
4112 if (shader->key.tes.as_es)
4113 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4114 else
4115 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4116 break;
4117 case TGSI_PROCESSOR_GEOMETRY:
4118 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
4119 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
4120 break;
4121 case TGSI_PROCESSOR_FRAGMENT:
4122 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
4123 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
4124
4125 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
4126 case TGSI_FS_DEPTH_LAYOUT_GREATER:
4127 shader->db_shader_control |=
4128 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
4129 break;
4130 case TGSI_FS_DEPTH_LAYOUT_LESS:
4131 shader->db_shader_control |=
4132 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
4133 break;
4134 }
4135 break;
4136 default:
4137 assert(!"Unsupported shader type");
4138 return -1;
4139 }
4140
4141 create_meta_data(&si_shader_ctx);
4142 create_function(&si_shader_ctx);
4143 preload_constants(&si_shader_ctx);
4144 preload_samplers(&si_shader_ctx);
4145 preload_streamout_buffers(&si_shader_ctx);
4146 preload_ring_buffers(&si_shader_ctx);
4147
4148 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4149 int i;
4150 for (i = 0; i < 4; i++) {
4151 si_shader_ctx.gs_next_vertex[i] =
4152 lp_build_alloca(bld_base->base.gallivm,
4153 bld_base->uint_bld.elem_type, "");
4154 }
4155 }
4156
4157 if (!lp_build_tgsi_llvm(bld_base, tokens)) {
4158 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
4159 goto out;
4160 }
4161
4162 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
4163
4164 mod = bld_base->base.gallivm->module;
4165 r = si_compile_llvm(sscreen, shader, tm, mod);
4166 if (r) {
4167 fprintf(stderr, "LLVM failed to compile shader\n");
4168 goto out;
4169 }
4170
4171 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
4172
4173 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4174 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
4175 shader->gs_copy_shader->selector = shader->selector;
4176 shader->gs_copy_shader->key = shader->key;
4177 si_shader_ctx.shader = shader->gs_copy_shader;
4178 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
4179 shader, dump))) {
4180 free(shader->gs_copy_shader);
4181 shader->gs_copy_shader = NULL;
4182 goto out;
4183 }
4184 }
4185
4186 out:
4187 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
4188 FREE(si_shader_ctx.constants[i]);
4189 if (poly_stipple)
4190 tgsi_free_tokens(tokens);
4191 return r;
4192 }
4193
4194 void si_shader_destroy(struct si_shader *shader)
4195 {
4196 if (shader->gs_copy_shader)
4197 si_shader_destroy(shader->gs_copy_shader);
4198
4199 if (shader->scratch_bo)
4200 r600_resource_reference(&shader->scratch_bo, NULL);
4201
4202 r600_resource_reference(&shader->bo, NULL);
4203
4204 FREE(shader->binary.code);
4205 FREE(shader->binary.relocs);
4206 FREE(shader->binary.disasm_string);
4207 }