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0bda187cfd2c2207128fa8379093f4841e778c08
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "util/u_memory.h"
37 #include "util/u_string.h"
38 #include "tgsi/tgsi_build.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "si_shader_internal.h"
45 #include "si_pipe.h"
46 #include "sid.h"
47
48
49 static const char *scratch_rsrc_dword0_symbol =
50 "SCRATCH_RSRC_DWORD0";
51
52 static const char *scratch_rsrc_dword1_symbol =
53 "SCRATCH_RSRC_DWORD1";
54
55 struct si_shader_output_values
56 {
57 LLVMValueRef values[4];
58 unsigned semantic_name;
59 unsigned semantic_index;
60 ubyte vertex_stream[4];
61 };
62
63 static void si_init_shader_ctx(struct si_shader_context *ctx,
64 struct si_screen *sscreen,
65 struct si_shader *shader,
66 LLVMTargetMachineRef tm);
67
68 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
69 struct lp_build_tgsi_context *bld_base,
70 struct lp_build_emit_data *emit_data);
71
72 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
73 FILE *f);
74
75 static unsigned llvm_get_type_size(LLVMTypeRef type);
76
77 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
78 union si_shader_part_key *key);
79 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
80 union si_shader_part_key *key);
81 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
82 union si_shader_part_key *key);
83 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
84 union si_shader_part_key *key);
85 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
86 union si_shader_part_key *key);
87
88 /* Ideally pass the sample mask input to the PS epilog as v13, which
89 * is its usual location, so that the shader doesn't have to add v_mov.
90 */
91 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
92
93 /* The VS location of the PrimitiveID input is the same in the epilog,
94 * so that the main shader part doesn't have to move it.
95 */
96 #define VS_EPILOG_PRIMID_LOC 2
97
98 enum {
99 CONST_ADDR_SPACE = 2,
100 LOCAL_ADDR_SPACE = 3,
101 };
102
103 /**
104 * Returns a unique index for a semantic name and index. The index must be
105 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
106 * calculated.
107 */
108 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
109 {
110 switch (semantic_name) {
111 case TGSI_SEMANTIC_POSITION:
112 return 0;
113 case TGSI_SEMANTIC_PSIZE:
114 return 1;
115 case TGSI_SEMANTIC_CLIPDIST:
116 assert(index <= 1);
117 return 2 + index;
118 case TGSI_SEMANTIC_GENERIC:
119 if (index <= 63-4)
120 return 4 + index;
121
122 assert(!"invalid generic index");
123 return 0;
124
125 /* patch indices are completely separate and thus start from 0 */
126 case TGSI_SEMANTIC_TESSOUTER:
127 return 0;
128 case TGSI_SEMANTIC_TESSINNER:
129 return 1;
130 case TGSI_SEMANTIC_PATCH:
131 return 2 + index;
132
133 default:
134 assert(!"invalid semantic name");
135 return 0;
136 }
137 }
138
139 unsigned si_shader_io_get_unique_index2(unsigned name, unsigned index)
140 {
141 switch (name) {
142 case TGSI_SEMANTIC_FOG:
143 return 0;
144 case TGSI_SEMANTIC_LAYER:
145 return 1;
146 case TGSI_SEMANTIC_VIEWPORT_INDEX:
147 return 2;
148 case TGSI_SEMANTIC_PRIMID:
149 return 3;
150 case TGSI_SEMANTIC_COLOR: /* these alias */
151 case TGSI_SEMANTIC_BCOLOR:
152 return 4 + index;
153 case TGSI_SEMANTIC_TEXCOORD:
154 return 6 + index;
155 default:
156 assert(!"invalid semantic name");
157 return 0;
158 }
159 }
160
161 /**
162 * Get the value of a shader input parameter and extract a bitfield.
163 */
164 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
165 unsigned param, unsigned rshift,
166 unsigned bitwidth)
167 {
168 struct gallivm_state *gallivm = &ctx->gallivm;
169 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
170 param);
171
172 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
173 value = bitcast(&ctx->bld_base,
174 TGSI_TYPE_UNSIGNED, value);
175
176 if (rshift)
177 value = LLVMBuildLShr(gallivm->builder, value,
178 LLVMConstInt(ctx->i32, rshift, 0), "");
179
180 if (rshift + bitwidth < 32) {
181 unsigned mask = (1 << bitwidth) - 1;
182 value = LLVMBuildAnd(gallivm->builder, value,
183 LLVMConstInt(ctx->i32, mask, 0), "");
184 }
185
186 return value;
187 }
188
189 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
190 {
191 switch (ctx->type) {
192 case PIPE_SHADER_TESS_CTRL:
193 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
194
195 case PIPE_SHADER_TESS_EVAL:
196 return LLVMGetParam(ctx->main_fn,
197 ctx->param_tes_rel_patch_id);
198
199 default:
200 assert(0);
201 return NULL;
202 }
203 }
204
205 /* Tessellation shaders pass outputs to the next shader using LDS.
206 *
207 * LS outputs = TCS inputs
208 * TCS outputs = TES inputs
209 *
210 * The LDS layout is:
211 * - TCS inputs for patch 0
212 * - TCS inputs for patch 1
213 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
214 * - ...
215 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
216 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
217 * - TCS outputs for patch 1
218 * - Per-patch TCS outputs for patch 1
219 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
220 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
221 * - ...
222 *
223 * All three shaders VS(LS), TCS, TES share the same LDS space.
224 */
225
226 static LLVMValueRef
227 get_tcs_in_patch_stride(struct si_shader_context *ctx)
228 {
229 if (ctx->type == PIPE_SHADER_VERTEX)
230 return unpack_param(ctx, SI_PARAM_VS_STATE_BITS, 8, 13);
231 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
232 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 8, 13);
233 else {
234 assert(0);
235 return NULL;
236 }
237 }
238
239 static LLVMValueRef
240 get_tcs_out_patch_stride(struct si_shader_context *ctx)
241 {
242 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
243 }
244
245 static LLVMValueRef
246 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
247 {
248 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
249 unpack_param(ctx,
250 SI_PARAM_TCS_OUT_OFFSETS,
251 0, 16),
252 4);
253 }
254
255 static LLVMValueRef
256 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
257 {
258 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
259 unpack_param(ctx,
260 SI_PARAM_TCS_OUT_OFFSETS,
261 16, 16),
262 4);
263 }
264
265 static LLVMValueRef
266 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
267 {
268 struct gallivm_state *gallivm = &ctx->gallivm;
269 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
270 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
271
272 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
273 }
274
275 static LLVMValueRef
276 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
277 {
278 struct gallivm_state *gallivm = &ctx->gallivm;
279 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
280 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
281 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
282
283 return LLVMBuildAdd(gallivm->builder, patch0_offset,
284 LLVMBuildMul(gallivm->builder, patch_stride,
285 rel_patch_id, ""),
286 "");
287 }
288
289 static LLVMValueRef
290 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
291 {
292 struct gallivm_state *gallivm = &ctx->gallivm;
293 LLVMValueRef patch0_patch_data_offset =
294 get_tcs_out_patch0_patch_data_offset(ctx);
295 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
296 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
297
298 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
299 LLVMBuildMul(gallivm->builder, patch_stride,
300 rel_patch_id, ""),
301 "");
302 }
303
304 static LLVMValueRef get_instance_index_for_fetch(
305 struct si_shader_context *ctx,
306 unsigned param_start_instance, unsigned divisor)
307 {
308 struct gallivm_state *gallivm = &ctx->gallivm;
309
310 LLVMValueRef result = LLVMGetParam(ctx->main_fn,
311 ctx->param_instance_id);
312
313 /* The division must be done before START_INSTANCE is added. */
314 if (divisor > 1)
315 result = LLVMBuildUDiv(gallivm->builder, result,
316 LLVMConstInt(ctx->i32, divisor, 0), "");
317
318 return LLVMBuildAdd(gallivm->builder, result,
319 LLVMGetParam(ctx->main_fn, param_start_instance), "");
320 }
321
322 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
323 * to float. */
324 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
325 LLVMValueRef vec4,
326 unsigned double_index)
327 {
328 LLVMBuilderRef builder = ctx->gallivm.builder;
329 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->gallivm.context);
330 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
331 LLVMVectorType(f64, 2), "");
332 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
333 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
334 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
335 }
336
337 static void declare_input_vs(
338 struct si_shader_context *ctx,
339 unsigned input_index,
340 const struct tgsi_full_declaration *decl,
341 LLVMValueRef out[4])
342 {
343 struct gallivm_state *gallivm = &ctx->gallivm;
344
345 unsigned chan;
346 unsigned fix_fetch;
347 unsigned num_fetches;
348 unsigned fetch_stride;
349
350 LLVMValueRef t_list_ptr;
351 LLVMValueRef t_offset;
352 LLVMValueRef t_list;
353 LLVMValueRef vertex_index;
354 LLVMValueRef input[3];
355
356 /* Load the T list */
357 t_list_ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_VERTEX_BUFFERS);
358
359 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
360
361 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
362
363 vertex_index = LLVMGetParam(ctx->main_fn,
364 ctx->param_vertex_index0 +
365 input_index);
366
367 fix_fetch = ctx->shader->key.mono.vs.fix_fetch[input_index];
368
369 /* Do multiple loads for special formats. */
370 switch (fix_fetch) {
371 case SI_FIX_FETCH_RGB_64_FLOAT:
372 num_fetches = 3; /* 3 2-dword loads */
373 fetch_stride = 8;
374 break;
375 case SI_FIX_FETCH_RGBA_64_FLOAT:
376 num_fetches = 2; /* 2 4-dword loads */
377 fetch_stride = 16;
378 break;
379 case SI_FIX_FETCH_RGB_8:
380 case SI_FIX_FETCH_RGB_8_INT:
381 num_fetches = 3;
382 fetch_stride = 1;
383 break;
384 case SI_FIX_FETCH_RGB_16:
385 case SI_FIX_FETCH_RGB_16_INT:
386 num_fetches = 3;
387 fetch_stride = 2;
388 break;
389 default:
390 num_fetches = 1;
391 fetch_stride = 0;
392 }
393
394 for (unsigned i = 0; i < num_fetches; i++) {
395 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
396
397 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
398 vertex_index, voffset,
399 true);
400 }
401
402 /* Break up the vec4 into individual components */
403 for (chan = 0; chan < 4; chan++) {
404 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
405 out[chan] = LLVMBuildExtractElement(gallivm->builder,
406 input[0], llvm_chan, "");
407 }
408
409 switch (fix_fetch) {
410 case SI_FIX_FETCH_A2_SNORM:
411 case SI_FIX_FETCH_A2_SSCALED:
412 case SI_FIX_FETCH_A2_SINT: {
413 /* The hardware returns an unsigned value; convert it to a
414 * signed one.
415 */
416 LLVMValueRef tmp = out[3];
417 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
418
419 /* First, recover the sign-extended signed integer value. */
420 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
421 tmp = LLVMBuildFPToUI(gallivm->builder, tmp, ctx->i32, "");
422 else
423 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->i32, "");
424
425 /* For the integer-like cases, do a natural sign extension.
426 *
427 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
428 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
429 * exponent.
430 */
431 tmp = LLVMBuildShl(gallivm->builder, tmp,
432 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
433 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
434 tmp = LLVMBuildAShr(gallivm->builder, tmp, c30, "");
435
436 /* Convert back to the right type. */
437 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
438 LLVMValueRef clamp;
439 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
440 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
441 clamp = LLVMBuildFCmp(gallivm->builder, LLVMRealULT, tmp, neg_one, "");
442 tmp = LLVMBuildSelect(gallivm->builder, clamp, neg_one, tmp, "");
443 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
444 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
445 }
446
447 out[3] = tmp;
448 break;
449 }
450 case SI_FIX_FETCH_RGBA_32_UNORM:
451 case SI_FIX_FETCH_RGBX_32_UNORM:
452 for (chan = 0; chan < 4; chan++) {
453 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
454 ctx->i32, "");
455 out[chan] = LLVMBuildUIToFP(gallivm->builder,
456 out[chan], ctx->f32, "");
457 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
458 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
459 }
460 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
461 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
462 out[3] = LLVMConstReal(ctx->f32, 1);
463 break;
464 case SI_FIX_FETCH_RGBA_32_SNORM:
465 case SI_FIX_FETCH_RGBX_32_SNORM:
466 case SI_FIX_FETCH_RGBA_32_FIXED:
467 case SI_FIX_FETCH_RGBX_32_FIXED: {
468 double scale;
469 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
470 scale = 1.0 / 0x10000;
471 else
472 scale = 1.0 / INT_MAX;
473
474 for (chan = 0; chan < 4; chan++) {
475 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
476 ctx->i32, "");
477 out[chan] = LLVMBuildSIToFP(gallivm->builder,
478 out[chan], ctx->f32, "");
479 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
480 LLVMConstReal(ctx->f32, scale), "");
481 }
482 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
483 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
484 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
485 out[3] = LLVMConstReal(ctx->f32, 1);
486 break;
487 }
488 case SI_FIX_FETCH_RGBA_32_USCALED:
489 for (chan = 0; chan < 4; chan++) {
490 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
491 ctx->i32, "");
492 out[chan] = LLVMBuildUIToFP(gallivm->builder,
493 out[chan], ctx->f32, "");
494 }
495 break;
496 case SI_FIX_FETCH_RGBA_32_SSCALED:
497 for (chan = 0; chan < 4; chan++) {
498 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
499 ctx->i32, "");
500 out[chan] = LLVMBuildSIToFP(gallivm->builder,
501 out[chan], ctx->f32, "");
502 }
503 break;
504 case SI_FIX_FETCH_RG_64_FLOAT:
505 for (chan = 0; chan < 2; chan++)
506 out[chan] = extract_double_to_float(ctx, input[0], chan);
507
508 out[2] = LLVMConstReal(ctx->f32, 0);
509 out[3] = LLVMConstReal(ctx->f32, 1);
510 break;
511 case SI_FIX_FETCH_RGB_64_FLOAT:
512 for (chan = 0; chan < 3; chan++)
513 out[chan] = extract_double_to_float(ctx, input[chan], 0);
514
515 out[3] = LLVMConstReal(ctx->f32, 1);
516 break;
517 case SI_FIX_FETCH_RGBA_64_FLOAT:
518 for (chan = 0; chan < 4; chan++) {
519 out[chan] = extract_double_to_float(ctx, input[chan / 2],
520 chan % 2);
521 }
522 break;
523 case SI_FIX_FETCH_RGB_8:
524 case SI_FIX_FETCH_RGB_8_INT:
525 case SI_FIX_FETCH_RGB_16:
526 case SI_FIX_FETCH_RGB_16_INT:
527 for (chan = 0; chan < 3; chan++) {
528 out[chan] = LLVMBuildExtractElement(gallivm->builder,
529 input[chan],
530 ctx->i32_0, "");
531 }
532 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
533 fix_fetch == SI_FIX_FETCH_RGB_16) {
534 out[3] = LLVMConstReal(ctx->f32, 1);
535 } else {
536 out[3] = LLVMBuildBitCast(gallivm->builder, ctx->i32_1,
537 ctx->f32, "");
538 }
539 break;
540 }
541 }
542
543 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
544 unsigned swizzle)
545 {
546 struct si_shader_context *ctx = si_shader_context(bld_base);
547
548 if (swizzle > 0)
549 return ctx->i32_0;
550
551 switch (ctx->type) {
552 case PIPE_SHADER_VERTEX:
553 return LLVMGetParam(ctx->main_fn,
554 ctx->param_vs_prim_id);
555 case PIPE_SHADER_TESS_CTRL:
556 return LLVMGetParam(ctx->main_fn,
557 SI_PARAM_PATCH_ID);
558 case PIPE_SHADER_TESS_EVAL:
559 return LLVMGetParam(ctx->main_fn,
560 ctx->param_tes_patch_id);
561 case PIPE_SHADER_GEOMETRY:
562 return LLVMGetParam(ctx->main_fn,
563 SI_PARAM_PRIMITIVE_ID);
564 default:
565 assert(0);
566 return ctx->i32_0;
567 }
568 }
569
570 /**
571 * Return the value of tgsi_ind_register for indexing.
572 * This is the indirect index with the constant offset added to it.
573 */
574 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
575 const struct tgsi_ind_register *ind,
576 int rel_index)
577 {
578 struct gallivm_state *gallivm = &ctx->gallivm;
579 LLVMValueRef result;
580
581 result = ctx->addrs[ind->Index][ind->Swizzle];
582 result = LLVMBuildLoad(gallivm->builder, result, "");
583 result = LLVMBuildAdd(gallivm->builder, result,
584 LLVMConstInt(ctx->i32, rel_index, 0), "");
585 return result;
586 }
587
588 /**
589 * Like get_indirect_index, but restricts the return value to a (possibly
590 * undefined) value inside [0..num).
591 */
592 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
593 const struct tgsi_ind_register *ind,
594 int rel_index, unsigned num)
595 {
596 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
597
598 /* LLVM 3.8: If indirect resource indexing is used:
599 * - SI & CIK hang
600 * - VI crashes
601 */
602 if (HAVE_LLVM == 0x0308)
603 return LLVMGetUndef(ctx->i32);
604
605 return si_llvm_bound_index(ctx, result, num);
606 }
607
608
609 /**
610 * Calculate a dword address given an input or output register and a stride.
611 */
612 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
613 const struct tgsi_full_dst_register *dst,
614 const struct tgsi_full_src_register *src,
615 LLVMValueRef vertex_dw_stride,
616 LLVMValueRef base_addr)
617 {
618 struct gallivm_state *gallivm = &ctx->gallivm;
619 struct tgsi_shader_info *info = &ctx->shader->selector->info;
620 ubyte *name, *index, *array_first;
621 int first, param;
622 struct tgsi_full_dst_register reg;
623
624 /* Set the register description. The address computation is the same
625 * for sources and destinations. */
626 if (src) {
627 reg.Register.File = src->Register.File;
628 reg.Register.Index = src->Register.Index;
629 reg.Register.Indirect = src->Register.Indirect;
630 reg.Register.Dimension = src->Register.Dimension;
631 reg.Indirect = src->Indirect;
632 reg.Dimension = src->Dimension;
633 reg.DimIndirect = src->DimIndirect;
634 } else
635 reg = *dst;
636
637 /* If the register is 2-dimensional (e.g. an array of vertices
638 * in a primitive), calculate the base address of the vertex. */
639 if (reg.Register.Dimension) {
640 LLVMValueRef index;
641
642 if (reg.Dimension.Indirect)
643 index = get_indirect_index(ctx, &reg.DimIndirect,
644 reg.Dimension.Index);
645 else
646 index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
647
648 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
649 LLVMBuildMul(gallivm->builder, index,
650 vertex_dw_stride, ""), "");
651 }
652
653 /* Get information about the register. */
654 if (reg.Register.File == TGSI_FILE_INPUT) {
655 name = info->input_semantic_name;
656 index = info->input_semantic_index;
657 array_first = info->input_array_first;
658 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
659 name = info->output_semantic_name;
660 index = info->output_semantic_index;
661 array_first = info->output_array_first;
662 } else {
663 assert(0);
664 return NULL;
665 }
666
667 if (reg.Register.Indirect) {
668 /* Add the relative address of the element. */
669 LLVMValueRef ind_index;
670
671 if (reg.Indirect.ArrayID)
672 first = array_first[reg.Indirect.ArrayID];
673 else
674 first = reg.Register.Index;
675
676 ind_index = get_indirect_index(ctx, &reg.Indirect,
677 reg.Register.Index - first);
678
679 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
680 LLVMBuildMul(gallivm->builder, ind_index,
681 LLVMConstInt(ctx->i32, 4, 0), ""), "");
682
683 param = si_shader_io_get_unique_index(name[first], index[first]);
684 } else {
685 param = si_shader_io_get_unique_index(name[reg.Register.Index],
686 index[reg.Register.Index]);
687 }
688
689 /* Add the base address of the element. */
690 return LLVMBuildAdd(gallivm->builder, base_addr,
691 LLVMConstInt(ctx->i32, param * 4, 0), "");
692 }
693
694 /* The offchip buffer layout for TCS->TES is
695 *
696 * - attribute 0 of patch 0 vertex 0
697 * - attribute 0 of patch 0 vertex 1
698 * - attribute 0 of patch 0 vertex 2
699 * ...
700 * - attribute 0 of patch 1 vertex 0
701 * - attribute 0 of patch 1 vertex 1
702 * ...
703 * - attribute 1 of patch 0 vertex 0
704 * - attribute 1 of patch 0 vertex 1
705 * ...
706 * - per patch attribute 0 of patch 0
707 * - per patch attribute 0 of patch 1
708 * ...
709 *
710 * Note that every attribute has 4 components.
711 */
712 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
713 LLVMValueRef rel_patch_id,
714 LLVMValueRef vertex_index,
715 LLVMValueRef param_index)
716 {
717 struct gallivm_state *gallivm = &ctx->gallivm;
718 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
719 LLVMValueRef param_stride, constant16;
720
721 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
722 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
723 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
724 num_patches, "");
725
726 constant16 = LLVMConstInt(ctx->i32, 16, 0);
727 if (vertex_index) {
728 base_addr = LLVMBuildMul(gallivm->builder, rel_patch_id,
729 vertices_per_patch, "");
730
731 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
732 vertex_index, "");
733
734 param_stride = total_vertices;
735 } else {
736 base_addr = rel_patch_id;
737 param_stride = num_patches;
738 }
739
740 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
741 LLVMBuildMul(gallivm->builder, param_index,
742 param_stride, ""), "");
743
744 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
745
746 if (!vertex_index) {
747 LLVMValueRef patch_data_offset =
748 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
749
750 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
751 patch_data_offset, "");
752 }
753 return base_addr;
754 }
755
756 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
757 struct si_shader_context *ctx,
758 const struct tgsi_full_dst_register *dst,
759 const struct tgsi_full_src_register *src)
760 {
761 struct gallivm_state *gallivm = &ctx->gallivm;
762 struct tgsi_shader_info *info = &ctx->shader->selector->info;
763 ubyte *name, *index, *array_first;
764 struct tgsi_full_src_register reg;
765 LLVMValueRef vertex_index = NULL;
766 LLVMValueRef param_index = NULL;
767 unsigned param_index_base, param_base;
768
769 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
770
771 if (reg.Register.Dimension) {
772
773 if (reg.Dimension.Indirect)
774 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
775 reg.Dimension.Index);
776 else
777 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
778 }
779
780 /* Get information about the register. */
781 if (reg.Register.File == TGSI_FILE_INPUT) {
782 name = info->input_semantic_name;
783 index = info->input_semantic_index;
784 array_first = info->input_array_first;
785 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
786 name = info->output_semantic_name;
787 index = info->output_semantic_index;
788 array_first = info->output_array_first;
789 } else {
790 assert(0);
791 return NULL;
792 }
793
794 if (reg.Register.Indirect) {
795 if (reg.Indirect.ArrayID)
796 param_base = array_first[reg.Indirect.ArrayID];
797 else
798 param_base = reg.Register.Index;
799
800 param_index = get_indirect_index(ctx, &reg.Indirect,
801 reg.Register.Index - param_base);
802
803 } else {
804 param_base = reg.Register.Index;
805 param_index = ctx->i32_0;
806 }
807
808 param_index_base = si_shader_io_get_unique_index(name[param_base],
809 index[param_base]);
810
811 param_index = LLVMBuildAdd(gallivm->builder, param_index,
812 LLVMConstInt(ctx->i32, param_index_base, 0),
813 "");
814
815 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
816 vertex_index, param_index);
817 }
818
819 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
820 enum tgsi_opcode_type type, unsigned swizzle,
821 LLVMValueRef buffer, LLVMValueRef offset,
822 LLVMValueRef base, bool readonly_memory)
823 {
824 struct si_shader_context *ctx = si_shader_context(bld_base);
825 struct gallivm_state *gallivm = &ctx->gallivm;
826 LLVMValueRef value, value2;
827 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
828 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
829
830 if (swizzle == ~0) {
831 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
832 0, 1, 0, readonly_memory);
833
834 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
835 }
836
837 if (!tgsi_type_is_64bit(type)) {
838 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
839 0, 1, 0, readonly_memory);
840
841 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
842 return LLVMBuildExtractElement(gallivm->builder, value,
843 LLVMConstInt(ctx->i32, swizzle, 0), "");
844 }
845
846 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
847 swizzle * 4, 1, 0, readonly_memory);
848
849 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
850 swizzle * 4 + 4, 1, 0, readonly_memory);
851
852 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
853 }
854
855 /**
856 * Load from LDS.
857 *
858 * \param type output value type
859 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
860 * \param dw_addr address in dwords
861 */
862 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
863 enum tgsi_opcode_type type, unsigned swizzle,
864 LLVMValueRef dw_addr)
865 {
866 struct si_shader_context *ctx = si_shader_context(bld_base);
867 struct gallivm_state *gallivm = &ctx->gallivm;
868 LLVMValueRef value;
869
870 if (swizzle == ~0) {
871 LLVMValueRef values[TGSI_NUM_CHANNELS];
872
873 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
874 values[chan] = lds_load(bld_base, type, chan, dw_addr);
875
876 return lp_build_gather_values(gallivm, values,
877 TGSI_NUM_CHANNELS);
878 }
879
880 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
881 LLVMConstInt(ctx->i32, swizzle, 0));
882
883 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
884 if (tgsi_type_is_64bit(type)) {
885 LLVMValueRef value2;
886 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
887 ctx->i32_1);
888 value2 = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
889 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
890 }
891
892 return LLVMBuildBitCast(gallivm->builder, value,
893 tgsi2llvmtype(bld_base, type), "");
894 }
895
896 /**
897 * Store to LDS.
898 *
899 * \param swizzle offset (typically 0..3)
900 * \param dw_addr address in dwords
901 * \param value value to store
902 */
903 static void lds_store(struct lp_build_tgsi_context *bld_base,
904 unsigned swizzle, LLVMValueRef dw_addr,
905 LLVMValueRef value)
906 {
907 struct si_shader_context *ctx = si_shader_context(bld_base);
908 struct gallivm_state *gallivm = &ctx->gallivm;
909
910 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
911 LLVMConstInt(ctx->i32, swizzle, 0));
912
913 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
914 ac_build_indexed_store(&ctx->ac, ctx->lds,
915 dw_addr, value);
916 }
917
918 static LLVMValueRef fetch_input_tcs(
919 struct lp_build_tgsi_context *bld_base,
920 const struct tgsi_full_src_register *reg,
921 enum tgsi_opcode_type type, unsigned swizzle)
922 {
923 struct si_shader_context *ctx = si_shader_context(bld_base);
924 LLVMValueRef dw_addr, stride;
925
926 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 24, 8);
927 dw_addr = get_tcs_in_current_patch_offset(ctx);
928 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
929
930 return lds_load(bld_base, type, swizzle, dw_addr);
931 }
932
933 static LLVMValueRef fetch_output_tcs(
934 struct lp_build_tgsi_context *bld_base,
935 const struct tgsi_full_src_register *reg,
936 enum tgsi_opcode_type type, unsigned swizzle)
937 {
938 struct si_shader_context *ctx = si_shader_context(bld_base);
939 LLVMValueRef dw_addr, stride;
940
941 if (reg->Register.Dimension) {
942 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
943 dw_addr = get_tcs_out_current_patch_offset(ctx);
944 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
945 } else {
946 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
947 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
948 }
949
950 return lds_load(bld_base, type, swizzle, dw_addr);
951 }
952
953 static LLVMValueRef fetch_input_tes(
954 struct lp_build_tgsi_context *bld_base,
955 const struct tgsi_full_src_register *reg,
956 enum tgsi_opcode_type type, unsigned swizzle)
957 {
958 struct si_shader_context *ctx = si_shader_context(bld_base);
959 LLVMValueRef rw_buffers, buffer, base, addr;
960
961 rw_buffers = LLVMGetParam(ctx->main_fn,
962 SI_PARAM_RW_BUFFERS);
963 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
964 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
965
966 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
967 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
968
969 return buffer_load(bld_base, type, swizzle, buffer, base, addr, true);
970 }
971
972 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
973 const struct tgsi_full_instruction *inst,
974 const struct tgsi_opcode_info *info,
975 LLVMValueRef dst[4])
976 {
977 struct si_shader_context *ctx = si_shader_context(bld_base);
978 struct gallivm_state *gallivm = &ctx->gallivm;
979 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
980 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
981 unsigned chan_index;
982 LLVMValueRef dw_addr, stride;
983 LLVMValueRef rw_buffers, buffer, base, buf_addr;
984 LLVMValueRef values[4];
985 bool skip_lds_store;
986 bool is_tess_factor = false;
987
988 /* Only handle per-patch and per-vertex outputs here.
989 * Vectors will be lowered to scalars and this function will be called again.
990 */
991 if (reg->Register.File != TGSI_FILE_OUTPUT ||
992 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
993 si_llvm_emit_store(bld_base, inst, info, dst);
994 return;
995 }
996
997 if (reg->Register.Dimension) {
998 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
999 dw_addr = get_tcs_out_current_patch_offset(ctx);
1000 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1001 skip_lds_store = !sh_info->reads_pervertex_outputs;
1002 } else {
1003 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1004 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1005 skip_lds_store = !sh_info->reads_perpatch_outputs;
1006
1007 if (!reg->Register.Indirect) {
1008 int name = sh_info->output_semantic_name[reg->Register.Index];
1009
1010 /* Always write tess factors into LDS for the TCS epilog. */
1011 if (name == TGSI_SEMANTIC_TESSINNER ||
1012 name == TGSI_SEMANTIC_TESSOUTER) {
1013 skip_lds_store = false;
1014 is_tess_factor = true;
1015 }
1016 }
1017 }
1018
1019 rw_buffers = LLVMGetParam(ctx->main_fn,
1020 SI_PARAM_RW_BUFFERS);
1021 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
1022 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
1023
1024 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1025 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1026
1027
1028 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1029 LLVMValueRef value = dst[chan_index];
1030
1031 if (inst->Instruction.Saturate)
1032 value = ac_build_clamp(&ctx->ac, value);
1033
1034 /* Skip LDS stores if there is no LDS read of this output. */
1035 if (!skip_lds_store)
1036 lds_store(bld_base, chan_index, dw_addr, value);
1037
1038 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1039 values[chan_index] = value;
1040
1041 if (inst->Dst[0].Register.WriteMask != 0xF && !is_tess_factor) {
1042 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1043 buf_addr, base,
1044 4 * chan_index, 1, 0, true, false);
1045 }
1046 }
1047
1048 if (inst->Dst[0].Register.WriteMask == 0xF && !is_tess_factor) {
1049 LLVMValueRef value = lp_build_gather_values(gallivm,
1050 values, 4);
1051 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1052 base, 0, 1, 0, true, false);
1053 }
1054 }
1055
1056 static LLVMValueRef fetch_input_gs(
1057 struct lp_build_tgsi_context *bld_base,
1058 const struct tgsi_full_src_register *reg,
1059 enum tgsi_opcode_type type,
1060 unsigned swizzle)
1061 {
1062 struct si_shader_context *ctx = si_shader_context(bld_base);
1063 struct si_shader *shader = ctx->shader;
1064 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1065 struct gallivm_state *gallivm = &ctx->gallivm;
1066 LLVMValueRef vtx_offset, soffset;
1067 unsigned vtx_offset_param;
1068 struct tgsi_shader_info *info = &shader->selector->info;
1069 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1070 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1071 unsigned param;
1072 LLVMValueRef value;
1073
1074 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1075 return get_primitive_id(bld_base, swizzle);
1076
1077 if (!reg->Register.Dimension)
1078 return NULL;
1079
1080 if (swizzle == ~0) {
1081 LLVMValueRef values[TGSI_NUM_CHANNELS];
1082 unsigned chan;
1083 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1084 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1085 }
1086 return lp_build_gather_values(gallivm, values,
1087 TGSI_NUM_CHANNELS);
1088 }
1089
1090 /* Get the vertex offset parameter */
1091 vtx_offset_param = reg->Dimension.Index;
1092 if (vtx_offset_param < 2) {
1093 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1094 } else {
1095 assert(vtx_offset_param < 6);
1096 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1097 }
1098 vtx_offset = lp_build_mul_imm(uint,
1099 LLVMGetParam(ctx->main_fn,
1100 vtx_offset_param),
1101 4);
1102
1103 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1104 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1105
1106 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1107 vtx_offset, soffset, 0, 1, 0, true);
1108 if (tgsi_type_is_64bit(type)) {
1109 LLVMValueRef value2;
1110 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1111
1112 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1113 ctx->i32_0, vtx_offset, soffset,
1114 0, 1, 0, true);
1115 return si_llvm_emit_fetch_64bit(bld_base, type,
1116 value, value2);
1117 }
1118 return LLVMBuildBitCast(gallivm->builder,
1119 value,
1120 tgsi2llvmtype(bld_base, type), "");
1121 }
1122
1123 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1124 {
1125 switch (interpolate) {
1126 case TGSI_INTERPOLATE_CONSTANT:
1127 return 0;
1128
1129 case TGSI_INTERPOLATE_LINEAR:
1130 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1131 return SI_PARAM_LINEAR_SAMPLE;
1132 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1133 return SI_PARAM_LINEAR_CENTROID;
1134 else
1135 return SI_PARAM_LINEAR_CENTER;
1136 break;
1137 case TGSI_INTERPOLATE_COLOR:
1138 case TGSI_INTERPOLATE_PERSPECTIVE:
1139 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1140 return SI_PARAM_PERSP_SAMPLE;
1141 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1142 return SI_PARAM_PERSP_CENTROID;
1143 else
1144 return SI_PARAM_PERSP_CENTER;
1145 break;
1146 default:
1147 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1148 return -1;
1149 }
1150 }
1151
1152 /**
1153 * Interpolate a fragment shader input.
1154 *
1155 * @param ctx context
1156 * @param input_index index of the input in hardware
1157 * @param semantic_name TGSI_SEMANTIC_*
1158 * @param semantic_index semantic index
1159 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1160 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1161 * @param interp_param interpolation weights (i,j)
1162 * @param prim_mask SI_PARAM_PRIM_MASK
1163 * @param face SI_PARAM_FRONT_FACE
1164 * @param result the return value (4 components)
1165 */
1166 static void interp_fs_input(struct si_shader_context *ctx,
1167 unsigned input_index,
1168 unsigned semantic_name,
1169 unsigned semantic_index,
1170 unsigned num_interp_inputs,
1171 unsigned colors_read_mask,
1172 LLVMValueRef interp_param,
1173 LLVMValueRef prim_mask,
1174 LLVMValueRef face,
1175 LLVMValueRef result[4])
1176 {
1177 struct gallivm_state *gallivm = &ctx->gallivm;
1178 LLVMValueRef attr_number;
1179 LLVMValueRef i, j;
1180
1181 unsigned chan;
1182
1183 /* fs.constant returns the param from the middle vertex, so it's not
1184 * really useful for flat shading. It's meant to be used for custom
1185 * interpolation (but the intrinsic can't fetch from the other two
1186 * vertices).
1187 *
1188 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1189 * to do the right thing. The only reason we use fs.constant is that
1190 * fs.interp cannot be used on integers, because they can be equal
1191 * to NaN.
1192 *
1193 * When interp is false we will use fs.constant or for newer llvm,
1194 * amdgcn.interp.mov.
1195 */
1196 bool interp = interp_param != NULL;
1197
1198 attr_number = LLVMConstInt(ctx->i32, input_index, 0);
1199
1200 if (interp) {
1201 interp_param = LLVMBuildBitCast(gallivm->builder, interp_param,
1202 LLVMVectorType(ctx->f32, 2), "");
1203
1204 i = LLVMBuildExtractElement(gallivm->builder, interp_param,
1205 ctx->i32_0, "");
1206 j = LLVMBuildExtractElement(gallivm->builder, interp_param,
1207 ctx->i32_1, "");
1208 }
1209
1210 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1211 ctx->shader->key.part.ps.prolog.color_two_side) {
1212 LLVMValueRef is_face_positive;
1213 LLVMValueRef back_attr_number;
1214
1215 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1216 * otherwise it's at offset "num_inputs".
1217 */
1218 unsigned back_attr_offset = num_interp_inputs;
1219 if (semantic_index == 1 && colors_read_mask & 0xf)
1220 back_attr_offset += 1;
1221
1222 back_attr_number = LLVMConstInt(ctx->i32, back_attr_offset, 0);
1223
1224 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1225 face, ctx->i32_0, "");
1226
1227 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1228 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
1229 LLVMValueRef front, back;
1230
1231 if (interp) {
1232 front = ac_build_fs_interp(&ctx->ac, llvm_chan,
1233 attr_number, prim_mask,
1234 i, j);
1235 back = ac_build_fs_interp(&ctx->ac, llvm_chan,
1236 back_attr_number, prim_mask,
1237 i, j);
1238 } else {
1239 front = ac_build_fs_interp_mov(&ctx->ac,
1240 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1241 llvm_chan, attr_number, prim_mask);
1242 back = ac_build_fs_interp_mov(&ctx->ac,
1243 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1244 llvm_chan, back_attr_number, prim_mask);
1245 }
1246
1247 result[chan] = LLVMBuildSelect(gallivm->builder,
1248 is_face_positive,
1249 front,
1250 back,
1251 "");
1252 }
1253 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1254 if (interp) {
1255 result[0] = ac_build_fs_interp(&ctx->ac, ctx->i32_0,
1256 attr_number, prim_mask, i, j);
1257 } else {
1258 result[0] = ac_build_fs_interp_mov(&ctx->ac, ctx->i32_0,
1259 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1260 attr_number, prim_mask);
1261 }
1262 result[1] =
1263 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1264 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1265 } else {
1266 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1267 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
1268
1269 if (interp) {
1270 result[chan] = ac_build_fs_interp(&ctx->ac,
1271 llvm_chan, attr_number, prim_mask, i, j);
1272 } else {
1273 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
1274 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1275 llvm_chan, attr_number, prim_mask);
1276 }
1277 }
1278 }
1279 }
1280
1281 static void declare_input_fs(
1282 struct si_shader_context *ctx,
1283 unsigned input_index,
1284 const struct tgsi_full_declaration *decl,
1285 LLVMValueRef out[4])
1286 {
1287 struct lp_build_context *base = &ctx->bld_base.base;
1288 struct si_shader *shader = ctx->shader;
1289 LLVMValueRef main_fn = ctx->main_fn;
1290 LLVMValueRef interp_param = NULL;
1291 int interp_param_idx;
1292
1293 /* Get colors from input VGPRs (set by the prolog). */
1294 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1295 unsigned i = decl->Semantic.Index;
1296 unsigned colors_read = shader->selector->info.colors_read;
1297 unsigned mask = colors_read >> (i * 4);
1298 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1299 (i ? util_bitcount(colors_read & 0xf) : 0);
1300
1301 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1302 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1303 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1304 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1305 return;
1306 }
1307
1308 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1309 decl->Interp.Location);
1310 if (interp_param_idx == -1)
1311 return;
1312 else if (interp_param_idx) {
1313 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1314 }
1315
1316 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
1317 decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR &&
1318 ctx->shader->key.part.ps.prolog.flatshade_colors)
1319 interp_param = NULL; /* load the constant color */
1320
1321 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1322 decl->Semantic.Index, shader->selector->info.num_inputs,
1323 shader->selector->info.colors_read, interp_param,
1324 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1325 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1326 &out[0]);
1327 }
1328
1329 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1330 {
1331 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1332 }
1333
1334
1335 /**
1336 * Load a dword from a constant buffer.
1337 */
1338 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1339 LLVMValueRef resource,
1340 LLVMValueRef offset)
1341 {
1342 LLVMBuilderRef builder = ctx->gallivm.builder;
1343 LLVMValueRef args[2] = {resource, offset};
1344
1345 return lp_build_intrinsic(builder, "llvm.SI.load.const", ctx->f32, args, 2,
1346 LP_FUNC_ATTR_READNONE |
1347 LP_FUNC_ATTR_LEGACY);
1348 }
1349
1350 static LLVMValueRef load_sample_position(struct si_shader_context *ctx, LLVMValueRef sample_id)
1351 {
1352 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1353 struct gallivm_state *gallivm = &ctx->gallivm;
1354 LLVMBuilderRef builder = gallivm->builder;
1355 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1356 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1357 LLVMValueRef resource = ac_build_indexed_load_const(&ctx->ac, desc, buf_index);
1358
1359 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1360 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1361 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1362
1363 LLVMValueRef pos[4] = {
1364 buffer_load_const(ctx, resource, offset0),
1365 buffer_load_const(ctx, resource, offset1),
1366 LLVMConstReal(ctx->f32, 0),
1367 LLVMConstReal(ctx->f32, 0)
1368 };
1369
1370 return lp_build_gather_values(gallivm, pos, 4);
1371 }
1372
1373 static void declare_system_value(struct si_shader_context *ctx,
1374 unsigned index,
1375 const struct tgsi_full_declaration *decl)
1376 {
1377 struct lp_build_context *bld = &ctx->bld_base.base;
1378 struct gallivm_state *gallivm = &ctx->gallivm;
1379 LLVMValueRef value = 0;
1380
1381 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
1382
1383 switch (decl->Semantic.Name) {
1384 case TGSI_SEMANTIC_INSTANCEID:
1385 value = LLVMGetParam(ctx->main_fn,
1386 ctx->param_instance_id);
1387 break;
1388
1389 case TGSI_SEMANTIC_VERTEXID:
1390 value = LLVMBuildAdd(gallivm->builder,
1391 LLVMGetParam(ctx->main_fn,
1392 ctx->param_vertex_id),
1393 LLVMGetParam(ctx->main_fn,
1394 SI_PARAM_BASE_VERTEX), "");
1395 break;
1396
1397 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1398 /* Unused. Clarify the meaning in indexed vs. non-indexed
1399 * draws if this is ever used again. */
1400 assert(false);
1401 break;
1402
1403 case TGSI_SEMANTIC_BASEVERTEX:
1404 {
1405 /* For non-indexed draws, the base vertex set by the driver
1406 * (for direct draws) or the CP (for indirect draws) is the
1407 * first vertex ID, but GLSL expects 0 to be returned.
1408 */
1409 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn, SI_PARAM_VS_STATE_BITS);
1410 LLVMValueRef indexed;
1411
1412 indexed = LLVMBuildLShr(gallivm->builder, vs_state, ctx->i32_1, "");
1413 indexed = LLVMBuildTrunc(gallivm->builder, indexed, ctx->i1, "");
1414
1415 value = LLVMBuildSelect(gallivm->builder, indexed,
1416 LLVMGetParam(ctx->main_fn, SI_PARAM_BASE_VERTEX),
1417 ctx->i32_0, "");
1418 break;
1419 }
1420
1421 case TGSI_SEMANTIC_BASEINSTANCE:
1422 value = LLVMGetParam(ctx->main_fn,
1423 SI_PARAM_START_INSTANCE);
1424 break;
1425
1426 case TGSI_SEMANTIC_DRAWID:
1427 value = LLVMGetParam(ctx->main_fn,
1428 SI_PARAM_DRAWID);
1429 break;
1430
1431 case TGSI_SEMANTIC_INVOCATIONID:
1432 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1433 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1434 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1435 value = LLVMGetParam(ctx->main_fn,
1436 SI_PARAM_GS_INSTANCE_ID);
1437 else
1438 assert(!"INVOCATIONID not implemented");
1439 break;
1440
1441 case TGSI_SEMANTIC_POSITION:
1442 {
1443 LLVMValueRef pos[4] = {
1444 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1445 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1446 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
1447 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
1448 LLVMGetParam(ctx->main_fn,
1449 SI_PARAM_POS_W_FLOAT)),
1450 };
1451 value = lp_build_gather_values(gallivm, pos, 4);
1452 break;
1453 }
1454
1455 case TGSI_SEMANTIC_FACE:
1456 value = LLVMGetParam(ctx->main_fn, SI_PARAM_FRONT_FACE);
1457 break;
1458
1459 case TGSI_SEMANTIC_SAMPLEID:
1460 value = get_sample_id(ctx);
1461 break;
1462
1463 case TGSI_SEMANTIC_SAMPLEPOS: {
1464 LLVMValueRef pos[4] = {
1465 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1466 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1467 LLVMConstReal(ctx->f32, 0),
1468 LLVMConstReal(ctx->f32, 0)
1469 };
1470 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
1471 TGSI_OPCODE_FRC, pos[0]);
1472 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
1473 TGSI_OPCODE_FRC, pos[1]);
1474 value = lp_build_gather_values(gallivm, pos, 4);
1475 break;
1476 }
1477
1478 case TGSI_SEMANTIC_SAMPLEMASK:
1479 /* This can only occur with the OpenGL Core profile, which
1480 * doesn't support smoothing.
1481 */
1482 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1483 break;
1484
1485 case TGSI_SEMANTIC_TESSCOORD:
1486 {
1487 LLVMValueRef coord[4] = {
1488 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1489 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1490 bld->zero,
1491 bld->zero
1492 };
1493
1494 /* For triangles, the vector should be (u, v, 1-u-v). */
1495 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1496 PIPE_PRIM_TRIANGLES)
1497 coord[2] = lp_build_sub(bld, bld->one,
1498 lp_build_add(bld, coord[0], coord[1]));
1499
1500 value = lp_build_gather_values(gallivm, coord, 4);
1501 break;
1502 }
1503
1504 case TGSI_SEMANTIC_VERTICESIN:
1505 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1506 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1507 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1508 value = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 7);
1509 else
1510 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1511 break;
1512
1513 case TGSI_SEMANTIC_TESSINNER:
1514 case TGSI_SEMANTIC_TESSOUTER:
1515 {
1516 LLVMValueRef rw_buffers, buffer, base, addr;
1517 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1518
1519 rw_buffers = LLVMGetParam(ctx->main_fn,
1520 SI_PARAM_RW_BUFFERS);
1521 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
1522 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
1523
1524 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1525 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1526 LLVMConstInt(ctx->i32, param, 0));
1527
1528 value = buffer_load(&ctx->bld_base, TGSI_TYPE_FLOAT,
1529 ~0, buffer, base, addr, true);
1530
1531 break;
1532 }
1533
1534 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1535 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1536 {
1537 LLVMValueRef buf, slot, val[4];
1538 int i, offset;
1539
1540 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
1541 buf = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1542 buf = ac_build_indexed_load_const(&ctx->ac, buf, slot);
1543 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1544
1545 for (i = 0; i < 4; i++)
1546 val[i] = buffer_load_const(ctx, buf,
1547 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
1548 value = lp_build_gather_values(gallivm, val, 4);
1549 break;
1550 }
1551
1552 case TGSI_SEMANTIC_PRIMID:
1553 value = get_primitive_id(&ctx->bld_base, 0);
1554 break;
1555
1556 case TGSI_SEMANTIC_GRID_SIZE:
1557 value = LLVMGetParam(ctx->main_fn, SI_PARAM_GRID_SIZE);
1558 break;
1559
1560 case TGSI_SEMANTIC_BLOCK_SIZE:
1561 {
1562 LLVMValueRef values[3];
1563 unsigned i;
1564 unsigned *properties = ctx->shader->selector->info.properties;
1565
1566 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1567 unsigned sizes[3] = {
1568 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1569 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1570 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1571 };
1572
1573 for (i = 0; i < 3; ++i)
1574 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1575
1576 value = lp_build_gather_values(gallivm, values, 3);
1577 } else {
1578 value = LLVMGetParam(ctx->main_fn, SI_PARAM_BLOCK_SIZE);
1579 }
1580 break;
1581 }
1582
1583 case TGSI_SEMANTIC_BLOCK_ID:
1584 value = LLVMGetParam(ctx->main_fn, SI_PARAM_BLOCK_ID);
1585 break;
1586
1587 case TGSI_SEMANTIC_THREAD_ID:
1588 value = LLVMGetParam(ctx->main_fn, SI_PARAM_THREAD_ID);
1589 break;
1590
1591 case TGSI_SEMANTIC_HELPER_INVOCATION:
1592 if (HAVE_LLVM >= 0x0309) {
1593 value = lp_build_intrinsic(gallivm->builder,
1594 "llvm.amdgcn.ps.live",
1595 ctx->i1, NULL, 0,
1596 LP_FUNC_ATTR_READNONE);
1597 value = LLVMBuildNot(gallivm->builder, value, "");
1598 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1599 } else {
1600 assert(!"TGSI_SEMANTIC_HELPER_INVOCATION unsupported");
1601 return;
1602 }
1603 break;
1604
1605 case TGSI_SEMANTIC_SUBGROUP_SIZE:
1606 value = LLVMConstInt(ctx->i32, 64, 0);
1607 break;
1608
1609 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
1610 value = ac_get_thread_id(&ctx->ac);
1611 break;
1612
1613 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
1614 {
1615 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1616 id = LLVMBuildZExt(gallivm->builder, id, ctx->i64, "");
1617 value = LLVMBuildShl(gallivm->builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
1618 value = LLVMBuildBitCast(gallivm->builder, value, ctx->v2i32, "");
1619 break;
1620 }
1621
1622 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
1623 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
1624 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
1625 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
1626 {
1627 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1628 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
1629 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
1630 /* All bits set except LSB */
1631 value = LLVMConstInt(ctx->i64, -2, 0);
1632 } else {
1633 /* All bits set */
1634 value = LLVMConstInt(ctx->i64, -1, 0);
1635 }
1636 id = LLVMBuildZExt(gallivm->builder, id, ctx->i64, "");
1637 value = LLVMBuildShl(gallivm->builder, value, id, "");
1638 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
1639 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
1640 value = LLVMBuildNot(gallivm->builder, value, "");
1641 value = LLVMBuildBitCast(gallivm->builder, value, ctx->v2i32, "");
1642 break;
1643 }
1644
1645 default:
1646 assert(!"unknown system value");
1647 return;
1648 }
1649
1650 ctx->system_values[index] = value;
1651 }
1652
1653 static void declare_compute_memory(struct si_shader_context *ctx,
1654 const struct tgsi_full_declaration *decl)
1655 {
1656 struct si_shader_selector *sel = ctx->shader->selector;
1657 struct gallivm_state *gallivm = &ctx->gallivm;
1658
1659 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1660 LLVMValueRef var;
1661
1662 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1663 assert(decl->Range.First == decl->Range.Last);
1664 assert(!ctx->shared_memory);
1665
1666 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1667 LLVMArrayType(ctx->i8, sel->local_size),
1668 "compute_lds",
1669 LOCAL_ADDR_SPACE);
1670 LLVMSetAlignment(var, 4);
1671
1672 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1673 }
1674
1675 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1676 {
1677 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1678 SI_PARAM_CONST_BUFFERS);
1679
1680 return ac_build_indexed_load_const(&ctx->ac, list_ptr,
1681 LLVMConstInt(ctx->i32, i, 0));
1682 }
1683
1684 static LLVMValueRef fetch_constant(
1685 struct lp_build_tgsi_context *bld_base,
1686 const struct tgsi_full_src_register *reg,
1687 enum tgsi_opcode_type type,
1688 unsigned swizzle)
1689 {
1690 struct si_shader_context *ctx = si_shader_context(bld_base);
1691 struct lp_build_context *base = &bld_base->base;
1692 const struct tgsi_ind_register *ireg = &reg->Indirect;
1693 unsigned buf, idx;
1694
1695 LLVMValueRef addr, bufp;
1696 LLVMValueRef result;
1697
1698 if (swizzle == LP_CHAN_ALL) {
1699 unsigned chan;
1700 LLVMValueRef values[4];
1701 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1702 values[chan] = fetch_constant(bld_base, reg, type, chan);
1703
1704 return lp_build_gather_values(&ctx->gallivm, values, 4);
1705 }
1706
1707 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1708 idx = reg->Register.Index * 4 + swizzle;
1709
1710 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1711 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_CONST_BUFFERS);
1712 LLVMValueRef index;
1713 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1714 reg->Dimension.Index,
1715 SI_NUM_CONST_BUFFERS);
1716 bufp = ac_build_indexed_load_const(&ctx->ac, ptr, index);
1717 } else
1718 bufp = load_const_buffer_desc(ctx, buf);
1719
1720 if (reg->Register.Indirect) {
1721 addr = ctx->addrs[ireg->Index][ireg->Swizzle];
1722 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1723 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1724 addr = lp_build_add(&bld_base->uint_bld, addr,
1725 LLVMConstInt(ctx->i32, idx * 4, 0));
1726 } else {
1727 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
1728 }
1729
1730 result = buffer_load_const(ctx, bufp, addr);
1731
1732 if (!tgsi_type_is_64bit(type))
1733 result = bitcast(bld_base, type, result);
1734 else {
1735 LLVMValueRef addr2, result2;
1736
1737 addr2 = lp_build_add(&bld_base->uint_bld, addr,
1738 LLVMConstInt(ctx->i32, 4, 0));
1739 result2 = buffer_load_const(ctx, bufp, addr2);
1740
1741 result = si_llvm_emit_fetch_64bit(bld_base, type,
1742 result, result2);
1743 }
1744 return result;
1745 }
1746
1747 /* Upper 16 bits must be zero. */
1748 static LLVMValueRef si_llvm_pack_two_int16(struct si_shader_context *ctx,
1749 LLVMValueRef val[2])
1750 {
1751 return LLVMBuildOr(ctx->gallivm.builder, val[0],
1752 LLVMBuildShl(ctx->gallivm.builder, val[1],
1753 LLVMConstInt(ctx->i32, 16, 0),
1754 ""), "");
1755 }
1756
1757 /* Upper 16 bits are ignored and will be dropped. */
1758 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct si_shader_context *ctx,
1759 LLVMValueRef val[2])
1760 {
1761 LLVMValueRef v[2] = {
1762 LLVMBuildAnd(ctx->gallivm.builder, val[0],
1763 LLVMConstInt(ctx->i32, 0xffff, 0), ""),
1764 val[1],
1765 };
1766 return si_llvm_pack_two_int16(ctx, v);
1767 }
1768
1769 /* Initialize arguments for the shader export intrinsic */
1770 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1771 LLVMValueRef *values,
1772 unsigned target,
1773 struct ac_export_args *args)
1774 {
1775 struct si_shader_context *ctx = si_shader_context(bld_base);
1776 struct lp_build_context *base = &bld_base->base;
1777 LLVMBuilderRef builder = ctx->gallivm.builder;
1778 LLVMValueRef val[4];
1779 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1780 unsigned chan;
1781 bool is_int8, is_int10;
1782
1783 /* Default is 0xf. Adjusted below depending on the format. */
1784 args->enabled_channels = 0xf; /* writemask */
1785
1786 /* Specify whether the EXEC mask represents the valid mask */
1787 args->valid_mask = 0;
1788
1789 /* Specify whether this is the last export */
1790 args->done = 0;
1791
1792 /* Specify the target we are exporting */
1793 args->target = target;
1794
1795 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1796 const struct si_shader_key *key = &ctx->shader->key;
1797 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
1798 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1799
1800 assert(cbuf >= 0 && cbuf < 8);
1801 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1802 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
1803 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
1804 }
1805
1806 args->compr = false;
1807 args->out[0] = base->undef;
1808 args->out[1] = base->undef;
1809 args->out[2] = base->undef;
1810 args->out[3] = base->undef;
1811
1812 switch (spi_shader_col_format) {
1813 case V_028714_SPI_SHADER_ZERO:
1814 args->enabled_channels = 0; /* writemask */
1815 args->target = V_008DFC_SQ_EXP_NULL;
1816 break;
1817
1818 case V_028714_SPI_SHADER_32_R:
1819 args->enabled_channels = 1; /* writemask */
1820 args->out[0] = values[0];
1821 break;
1822
1823 case V_028714_SPI_SHADER_32_GR:
1824 args->enabled_channels = 0x3; /* writemask */
1825 args->out[0] = values[0];
1826 args->out[1] = values[1];
1827 break;
1828
1829 case V_028714_SPI_SHADER_32_AR:
1830 args->enabled_channels = 0x9; /* writemask */
1831 args->out[0] = values[0];
1832 args->out[3] = values[3];
1833 break;
1834
1835 case V_028714_SPI_SHADER_FP16_ABGR:
1836 args->compr = 1; /* COMPR flag */
1837
1838 for (chan = 0; chan < 2; chan++) {
1839 LLVMValueRef pack_args[2] = {
1840 values[2 * chan],
1841 values[2 * chan + 1]
1842 };
1843 LLVMValueRef packed;
1844
1845 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
1846 args->out[chan] =
1847 LLVMBuildBitCast(ctx->gallivm.builder,
1848 packed, ctx->f32, "");
1849 }
1850 break;
1851
1852 case V_028714_SPI_SHADER_UNORM16_ABGR:
1853 for (chan = 0; chan < 4; chan++) {
1854 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
1855 val[chan] = LLVMBuildFMul(builder, val[chan],
1856 LLVMConstReal(ctx->f32, 65535), "");
1857 val[chan] = LLVMBuildFAdd(builder, val[chan],
1858 LLVMConstReal(ctx->f32, 0.5), "");
1859 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1860 ctx->i32, "");
1861 }
1862
1863 args->compr = 1; /* COMPR flag */
1864 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1865 si_llvm_pack_two_int16(ctx, val));
1866 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1867 si_llvm_pack_two_int16(ctx, val+2));
1868 break;
1869
1870 case V_028714_SPI_SHADER_SNORM16_ABGR:
1871 for (chan = 0; chan < 4; chan++) {
1872 /* Clamp between [-1, 1]. */
1873 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1874 values[chan],
1875 LLVMConstReal(ctx->f32, 1));
1876 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1877 val[chan],
1878 LLVMConstReal(ctx->f32, -1));
1879 /* Convert to a signed integer in [-32767, 32767]. */
1880 val[chan] = LLVMBuildFMul(builder, val[chan],
1881 LLVMConstReal(ctx->f32, 32767), "");
1882 /* If positive, add 0.5, else add -0.5. */
1883 val[chan] = LLVMBuildFAdd(builder, val[chan],
1884 LLVMBuildSelect(builder,
1885 LLVMBuildFCmp(builder, LLVMRealOGE,
1886 val[chan], base->zero, ""),
1887 LLVMConstReal(ctx->f32, 0.5),
1888 LLVMConstReal(ctx->f32, -0.5), ""), "");
1889 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
1890 }
1891
1892 args->compr = 1; /* COMPR flag */
1893 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1894 si_llvm_pack_two_int32_as_int16(ctx, val));
1895 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1896 si_llvm_pack_two_int32_as_int16(ctx, val+2));
1897 break;
1898
1899 case V_028714_SPI_SHADER_UINT16_ABGR: {
1900 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
1901 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
1902 LLVMValueRef max_alpha =
1903 !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
1904
1905 /* Clamp. */
1906 for (chan = 0; chan < 4; chan++) {
1907 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1908 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1909 val[chan],
1910 chan == 3 ? max_alpha : max_rgb);
1911 }
1912
1913 args->compr = 1; /* COMPR flag */
1914 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1915 si_llvm_pack_two_int16(ctx, val));
1916 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1917 si_llvm_pack_two_int16(ctx, val+2));
1918 break;
1919 }
1920
1921 case V_028714_SPI_SHADER_SINT16_ABGR: {
1922 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
1923 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
1924 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
1925 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
1926 LLVMValueRef max_alpha =
1927 !is_int10 ? max_rgb : ctx->i32_1;
1928 LLVMValueRef min_alpha =
1929 !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
1930
1931 /* Clamp. */
1932 for (chan = 0; chan < 4; chan++) {
1933 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1934 val[chan] = lp_build_emit_llvm_binary(bld_base,
1935 TGSI_OPCODE_IMIN,
1936 val[chan], chan == 3 ? max_alpha : max_rgb);
1937 val[chan] = lp_build_emit_llvm_binary(bld_base,
1938 TGSI_OPCODE_IMAX,
1939 val[chan], chan == 3 ? min_alpha : min_rgb);
1940 }
1941
1942 args->compr = 1; /* COMPR flag */
1943 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1944 si_llvm_pack_two_int32_as_int16(ctx, val));
1945 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1946 si_llvm_pack_two_int32_as_int16(ctx, val+2));
1947 break;
1948 }
1949
1950 case V_028714_SPI_SHADER_32_ABGR:
1951 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1952 break;
1953 }
1954 }
1955
1956 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1957 LLVMValueRef alpha)
1958 {
1959 struct si_shader_context *ctx = si_shader_context(bld_base);
1960
1961 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
1962 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
1963 SI_PARAM_ALPHA_REF);
1964
1965 LLVMValueRef alpha_pass =
1966 lp_build_cmp(&bld_base->base,
1967 ctx->shader->key.part.ps.epilog.alpha_func,
1968 alpha, alpha_ref);
1969 LLVMValueRef arg =
1970 lp_build_select(&bld_base->base,
1971 alpha_pass,
1972 LLVMConstReal(ctx->f32, 1.0f),
1973 LLVMConstReal(ctx->f32, -1.0f));
1974
1975 ac_build_kill(&ctx->ac, arg);
1976 } else {
1977 ac_build_kill(&ctx->ac, NULL);
1978 }
1979 }
1980
1981 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1982 LLVMValueRef alpha,
1983 unsigned samplemask_param)
1984 {
1985 struct si_shader_context *ctx = si_shader_context(bld_base);
1986 struct gallivm_state *gallivm = &ctx->gallivm;
1987 LLVMValueRef coverage;
1988
1989 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1990 coverage = LLVMGetParam(ctx->main_fn,
1991 samplemask_param);
1992 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1993
1994 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1995 ctx->i32,
1996 &coverage, 1, LP_FUNC_ATTR_READNONE);
1997
1998 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1999 ctx->f32, "");
2000
2001 coverage = LLVMBuildFMul(gallivm->builder, coverage,
2002 LLVMConstReal(ctx->f32,
2003 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2004
2005 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
2006 }
2007
2008 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2009 struct ac_export_args *pos, LLVMValueRef *out_elts)
2010 {
2011 struct si_shader_context *ctx = si_shader_context(bld_base);
2012 struct lp_build_context *base = &bld_base->base;
2013 unsigned reg_index;
2014 unsigned chan;
2015 unsigned const_chan;
2016 LLVMValueRef base_elt;
2017 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2018 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2019 SI_VS_CONST_CLIP_PLANES, 0);
2020 LLVMValueRef const_resource = ac_build_indexed_load_const(&ctx->ac, ptr, constbuf_index);
2021
2022 for (reg_index = 0; reg_index < 2; reg_index ++) {
2023 struct ac_export_args *args = &pos[2 + reg_index];
2024
2025 args->out[0] =
2026 args->out[1] =
2027 args->out[2] =
2028 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2029
2030 /* Compute dot products of position and user clip plane vectors */
2031 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2032 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2033 LLVMValueRef addr =
2034 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2035 const_chan) * 4, 0);
2036 base_elt = buffer_load_const(ctx, const_resource,
2037 addr);
2038 args->out[chan] =
2039 lp_build_add(base, args->out[chan],
2040 lp_build_mul(base, base_elt,
2041 out_elts[const_chan]));
2042 }
2043 }
2044
2045 args->enabled_channels = 0xf;
2046 args->valid_mask = 0;
2047 args->done = 0;
2048 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2049 args->compr = 0;
2050 }
2051 }
2052
2053 static void si_dump_streamout(struct pipe_stream_output_info *so)
2054 {
2055 unsigned i;
2056
2057 if (so->num_outputs)
2058 fprintf(stderr, "STREAMOUT\n");
2059
2060 for (i = 0; i < so->num_outputs; i++) {
2061 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2062 so->output[i].start_component;
2063 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2064 i, so->output[i].output_buffer,
2065 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2066 so->output[i].register_index,
2067 mask & 1 ? "x" : "",
2068 mask & 2 ? "y" : "",
2069 mask & 4 ? "z" : "",
2070 mask & 8 ? "w" : "");
2071 }
2072 }
2073
2074 static void emit_streamout_output(struct si_shader_context *ctx,
2075 LLVMValueRef const *so_buffers,
2076 LLVMValueRef const *so_write_offsets,
2077 struct pipe_stream_output *stream_out,
2078 struct si_shader_output_values *shader_out)
2079 {
2080 struct gallivm_state *gallivm = &ctx->gallivm;
2081 LLVMBuilderRef builder = gallivm->builder;
2082 unsigned buf_idx = stream_out->output_buffer;
2083 unsigned start = stream_out->start_component;
2084 unsigned num_comps = stream_out->num_components;
2085 LLVMValueRef out[4];
2086
2087 assert(num_comps && num_comps <= 4);
2088 if (!num_comps || num_comps > 4)
2089 return;
2090
2091 /* Load the output as int. */
2092 for (int j = 0; j < num_comps; j++) {
2093 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2094
2095 out[j] = LLVMBuildBitCast(builder,
2096 shader_out->values[start + j],
2097 ctx->i32, "");
2098 }
2099
2100 /* Pack the output. */
2101 LLVMValueRef vdata = NULL;
2102
2103 switch (num_comps) {
2104 case 1: /* as i32 */
2105 vdata = out[0];
2106 break;
2107 case 2: /* as v2i32 */
2108 case 3: /* as v4i32 (aligned to 4) */
2109 case 4: /* as v4i32 */
2110 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2111 for (int j = 0; j < num_comps; j++) {
2112 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2113 LLVMConstInt(ctx->i32, j, 0), "");
2114 }
2115 break;
2116 }
2117
2118 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2119 vdata, num_comps,
2120 so_write_offsets[buf_idx],
2121 ctx->i32_0,
2122 stream_out->dst_offset * 4, 1, 1, true, false);
2123 }
2124
2125 /**
2126 * Write streamout data to buffers for vertex stream @p stream (different
2127 * vertex streams can occur for GS copy shaders).
2128 */
2129 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2130 struct si_shader_output_values *outputs,
2131 unsigned noutput, unsigned stream)
2132 {
2133 struct si_shader_selector *sel = ctx->shader->selector;
2134 struct pipe_stream_output_info *so = &sel->so;
2135 struct gallivm_state *gallivm = &ctx->gallivm;
2136 LLVMBuilderRef builder = gallivm->builder;
2137 int i;
2138 struct lp_build_if_state if_ctx;
2139
2140 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2141 LLVMValueRef so_vtx_count =
2142 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2143
2144 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2145
2146 /* can_emit = tid < so_vtx_count; */
2147 LLVMValueRef can_emit =
2148 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2149
2150 /* Emit the streamout code conditionally. This actually avoids
2151 * out-of-bounds buffer access. The hw tells us via the SGPR
2152 * (so_vtx_count) which threads are allowed to emit streamout data. */
2153 lp_build_if(&if_ctx, gallivm, can_emit);
2154 {
2155 /* The buffer offset is computed as follows:
2156 * ByteOffset = streamout_offset[buffer_id]*4 +
2157 * (streamout_write_index + thread_id)*stride[buffer_id] +
2158 * attrib_offset
2159 */
2160
2161 LLVMValueRef so_write_index =
2162 LLVMGetParam(ctx->main_fn,
2163 ctx->param_streamout_write_index);
2164
2165 /* Compute (streamout_write_index + thread_id). */
2166 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2167
2168 /* Load the descriptor and compute the write offset for each
2169 * enabled buffer. */
2170 LLVMValueRef so_write_offset[4] = {};
2171 LLVMValueRef so_buffers[4];
2172 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2173 SI_PARAM_RW_BUFFERS);
2174
2175 for (i = 0; i < 4; i++) {
2176 if (!so->stride[i])
2177 continue;
2178
2179 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2180 SI_VS_STREAMOUT_BUF0 + i, 0);
2181
2182 so_buffers[i] = ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
2183
2184 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2185 ctx->param_streamout_offset[i]);
2186 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2187
2188 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2189 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2190 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2191 }
2192
2193 /* Write streamout data. */
2194 for (i = 0; i < so->num_outputs; i++) {
2195 unsigned reg = so->output[i].register_index;
2196
2197 if (reg >= noutput)
2198 continue;
2199
2200 if (stream != so->output[i].stream)
2201 continue;
2202
2203 emit_streamout_output(ctx, so_buffers, so_write_offset,
2204 &so->output[i], &outputs[reg]);
2205 }
2206 }
2207 lp_build_endif(&if_ctx);
2208 }
2209
2210
2211 /* Generate export instructions for hardware VS shader stage */
2212 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2213 struct si_shader_output_values *outputs,
2214 unsigned noutput)
2215 {
2216 struct si_shader_context *ctx = si_shader_context(bld_base);
2217 struct si_shader *shader = ctx->shader;
2218 struct lp_build_context *base = &bld_base->base;
2219 struct ac_export_args args, pos_args[4] = {};
2220 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2221 unsigned semantic_name, semantic_index;
2222 unsigned target;
2223 unsigned param_count = 0;
2224 unsigned pos_idx;
2225 int i;
2226
2227 for (i = 0; i < noutput; i++) {
2228 semantic_name = outputs[i].semantic_name;
2229 semantic_index = outputs[i].semantic_index;
2230 bool export_param = true;
2231
2232 switch (semantic_name) {
2233 case TGSI_SEMANTIC_POSITION: /* ignore these */
2234 case TGSI_SEMANTIC_PSIZE:
2235 case TGSI_SEMANTIC_CLIPVERTEX:
2236 case TGSI_SEMANTIC_EDGEFLAG:
2237 break;
2238 case TGSI_SEMANTIC_GENERIC:
2239 case TGSI_SEMANTIC_CLIPDIST:
2240 if (shader->key.opt.hw_vs.kill_outputs &
2241 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2242 export_param = false;
2243 break;
2244 default:
2245 if (shader->key.opt.hw_vs.kill_outputs2 &
2246 (1u << si_shader_io_get_unique_index2(semantic_name, semantic_index)))
2247 export_param = false;
2248 break;
2249 }
2250
2251 if (outputs[i].vertex_stream[0] != 0 &&
2252 outputs[i].vertex_stream[1] != 0 &&
2253 outputs[i].vertex_stream[2] != 0 &&
2254 outputs[i].vertex_stream[3] != 0)
2255 export_param = false;
2256
2257 handle_semantic:
2258 /* Select the correct target */
2259 switch(semantic_name) {
2260 case TGSI_SEMANTIC_PSIZE:
2261 psize_value = outputs[i].values[0];
2262 continue;
2263 case TGSI_SEMANTIC_EDGEFLAG:
2264 edgeflag_value = outputs[i].values[0];
2265 continue;
2266 case TGSI_SEMANTIC_LAYER:
2267 layer_value = outputs[i].values[0];
2268 semantic_name = TGSI_SEMANTIC_GENERIC;
2269 goto handle_semantic;
2270 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2271 viewport_index_value = outputs[i].values[0];
2272 semantic_name = TGSI_SEMANTIC_GENERIC;
2273 goto handle_semantic;
2274 case TGSI_SEMANTIC_POSITION:
2275 target = V_008DFC_SQ_EXP_POS;
2276 break;
2277 case TGSI_SEMANTIC_CLIPDIST:
2278 if (shader->key.opt.hw_vs.clip_disable) {
2279 semantic_name = TGSI_SEMANTIC_GENERIC;
2280 goto handle_semantic;
2281 }
2282 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2283 break;
2284 case TGSI_SEMANTIC_CLIPVERTEX:
2285 if (shader->key.opt.hw_vs.clip_disable)
2286 continue;
2287 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2288 continue;
2289 case TGSI_SEMANTIC_COLOR:
2290 case TGSI_SEMANTIC_BCOLOR:
2291 case TGSI_SEMANTIC_PRIMID:
2292 case TGSI_SEMANTIC_FOG:
2293 case TGSI_SEMANTIC_TEXCOORD:
2294 case TGSI_SEMANTIC_GENERIC:
2295 if (!export_param)
2296 continue;
2297 target = V_008DFC_SQ_EXP_PARAM + param_count;
2298 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2299 shader->info.vs_output_param_offset[i] = param_count;
2300 param_count++;
2301 break;
2302 default:
2303 target = 0;
2304 fprintf(stderr,
2305 "Warning: SI unhandled vs output type:%d\n",
2306 semantic_name);
2307 }
2308
2309 si_llvm_init_export_args(bld_base, outputs[i].values, target, &args);
2310
2311 if (target >= V_008DFC_SQ_EXP_POS &&
2312 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2313 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2314 &args, sizeof(args));
2315 } else {
2316 ac_build_export(&ctx->ac, &args);
2317 }
2318
2319 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2320 semantic_name = TGSI_SEMANTIC_GENERIC;
2321 goto handle_semantic;
2322 }
2323 }
2324
2325 shader->info.nr_param_exports = param_count;
2326
2327 /* We need to add the position output manually if it's missing. */
2328 if (!pos_args[0].out[0]) {
2329 pos_args[0].enabled_channels = 0xf; /* writemask */
2330 pos_args[0].valid_mask = 0; /* EXEC mask */
2331 pos_args[0].done = 0; /* last export? */
2332 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2333 pos_args[0].compr = 0; /* COMPR flag */
2334 pos_args[0].out[0] = base->zero; /* X */
2335 pos_args[0].out[1] = base->zero; /* Y */
2336 pos_args[0].out[2] = base->zero; /* Z */
2337 pos_args[0].out[3] = base->one; /* W */
2338 }
2339
2340 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2341 if (shader->selector->info.writes_psize ||
2342 shader->selector->info.writes_edgeflag ||
2343 shader->selector->info.writes_viewport_index ||
2344 shader->selector->info.writes_layer) {
2345 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2346 (shader->selector->info.writes_edgeflag << 1) |
2347 (shader->selector->info.writes_layer << 2) |
2348 (shader->selector->info.writes_viewport_index << 3);
2349 pos_args[1].valid_mask = 0; /* EXEC mask */
2350 pos_args[1].done = 0; /* last export? */
2351 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2352 pos_args[1].compr = 0; /* COMPR flag */
2353 pos_args[1].out[0] = base->zero; /* X */
2354 pos_args[1].out[1] = base->zero; /* Y */
2355 pos_args[1].out[2] = base->zero; /* Z */
2356 pos_args[1].out[3] = base->zero; /* W */
2357
2358 if (shader->selector->info.writes_psize)
2359 pos_args[1].out[0] = psize_value;
2360
2361 if (shader->selector->info.writes_edgeflag) {
2362 /* The output is a float, but the hw expects an integer
2363 * with the first bit containing the edge flag. */
2364 edgeflag_value = LLVMBuildFPToUI(ctx->gallivm.builder,
2365 edgeflag_value,
2366 ctx->i32, "");
2367 edgeflag_value = lp_build_min(&bld_base->int_bld,
2368 edgeflag_value,
2369 ctx->i32_1);
2370
2371 /* The LLVM intrinsic expects a float. */
2372 pos_args[1].out[1] = LLVMBuildBitCast(ctx->gallivm.builder,
2373 edgeflag_value,
2374 ctx->f32, "");
2375 }
2376
2377 if (shader->selector->info.writes_layer)
2378 pos_args[1].out[2] = layer_value;
2379
2380 if (shader->selector->info.writes_viewport_index)
2381 pos_args[1].out[3] = viewport_index_value;
2382 }
2383
2384 for (i = 0; i < 4; i++)
2385 if (pos_args[i].out[0])
2386 shader->info.nr_pos_exports++;
2387
2388 pos_idx = 0;
2389 for (i = 0; i < 4; i++) {
2390 if (!pos_args[i].out[0])
2391 continue;
2392
2393 /* Specify the target we are exporting */
2394 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2395
2396 if (pos_idx == shader->info.nr_pos_exports)
2397 /* Specify that this is the last export */
2398 pos_args[i].done = 1;
2399
2400 ac_build_export(&ctx->ac, &pos_args[i]);
2401 }
2402 }
2403
2404 /**
2405 * Forward all outputs from the vertex shader to the TES. This is only used
2406 * for the fixed function TCS.
2407 */
2408 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2409 {
2410 struct si_shader_context *ctx = si_shader_context(bld_base);
2411 struct gallivm_state *gallivm = &ctx->gallivm;
2412 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2413 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2414 uint64_t inputs;
2415
2416 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2417
2418 rw_buffers = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2419 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
2420 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
2421
2422 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2423
2424 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 24, 8);
2425 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2426 lds_vertex_stride, "");
2427 lds_base = get_tcs_in_current_patch_offset(ctx);
2428 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2429
2430 inputs = ctx->shader->key.mono.tcs.inputs_to_copy;
2431 while (inputs) {
2432 unsigned i = u_bit_scan64(&inputs);
2433
2434 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2435 LLVMConstInt(ctx->i32, 4 * i, 0),
2436 "");
2437
2438 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2439 get_rel_patch_id(ctx),
2440 invocation_id,
2441 LLVMConstInt(ctx->i32, i, 0));
2442
2443 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2444 lds_ptr);
2445
2446 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
2447 buffer_offset, 0, 1, 0, true, false);
2448 }
2449 }
2450
2451 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2452 LLVMValueRef rel_patch_id,
2453 LLVMValueRef invocation_id,
2454 LLVMValueRef tcs_out_current_patch_data_offset)
2455 {
2456 struct si_shader_context *ctx = si_shader_context(bld_base);
2457 struct gallivm_state *gallivm = &ctx->gallivm;
2458 struct si_shader *shader = ctx->shader;
2459 unsigned tess_inner_index, tess_outer_index;
2460 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2461 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base, inner[4], outer[4];
2462 unsigned stride, outer_comps, inner_comps, i;
2463 struct lp_build_if_state if_ctx, inner_if_ctx;
2464
2465 si_llvm_emit_barrier(NULL, bld_base, NULL);
2466
2467 /* Do this only for invocation 0, because the tess levels are per-patch,
2468 * not per-vertex.
2469 *
2470 * This can't jump, because invocation 0 executes this. It should
2471 * at least mask out the loads and stores for other invocations.
2472 */
2473 lp_build_if(&if_ctx, gallivm,
2474 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2475 invocation_id, ctx->i32_0, ""));
2476
2477 /* Determine the layout of one tess factor element in the buffer. */
2478 switch (shader->key.part.tcs.epilog.prim_mode) {
2479 case PIPE_PRIM_LINES:
2480 stride = 2; /* 2 dwords, 1 vec2 store */
2481 outer_comps = 2;
2482 inner_comps = 0;
2483 break;
2484 case PIPE_PRIM_TRIANGLES:
2485 stride = 4; /* 4 dwords, 1 vec4 store */
2486 outer_comps = 3;
2487 inner_comps = 1;
2488 break;
2489 case PIPE_PRIM_QUADS:
2490 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2491 outer_comps = 4;
2492 inner_comps = 2;
2493 break;
2494 default:
2495 assert(0);
2496 return;
2497 }
2498
2499 /* Load tess_inner and tess_outer from LDS.
2500 * Any invocation can write them, so we can't get them from a temporary.
2501 */
2502 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2503 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2504
2505 lds_base = tcs_out_current_patch_data_offset;
2506 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2507 LLVMConstInt(ctx->i32,
2508 tess_inner_index * 4, 0), "");
2509 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2510 LLVMConstInt(ctx->i32,
2511 tess_outer_index * 4, 0), "");
2512
2513 for (i = 0; i < 4; i++) {
2514 inner[i] = LLVMGetUndef(ctx->i32);
2515 outer[i] = LLVMGetUndef(ctx->i32);
2516 }
2517
2518 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2519 /* For isolines, the hardware expects tess factors in the
2520 * reverse order from what GLSL / TGSI specify.
2521 */
2522 outer[0] = out[1] = lds_load(bld_base, TGSI_TYPE_SIGNED, 0, lds_outer);
2523 outer[1] = out[0] = lds_load(bld_base, TGSI_TYPE_SIGNED, 1, lds_outer);
2524 } else {
2525 for (i = 0; i < outer_comps; i++) {
2526 outer[i] = out[i] =
2527 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2528 }
2529 for (i = 0; i < inner_comps; i++) {
2530 inner[i] = out[outer_comps+i] =
2531 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2532 }
2533 }
2534
2535 /* Convert the outputs to vectors for stores. */
2536 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2537 vec1 = NULL;
2538
2539 if (stride > 4)
2540 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2541
2542 /* Get the buffer. */
2543 rw_buffers = LLVMGetParam(ctx->main_fn,
2544 SI_PARAM_RW_BUFFERS);
2545 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
2546 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_FACTOR, 0));
2547
2548 /* Get the offset. */
2549 tf_base = LLVMGetParam(ctx->main_fn,
2550 SI_PARAM_TESS_FACTOR_OFFSET);
2551 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2552 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
2553
2554 lp_build_if(&inner_if_ctx, gallivm,
2555 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2556 rel_patch_id, ctx->i32_0, ""));
2557
2558 /* Store the dynamic HS control word. */
2559 ac_build_buffer_store_dword(&ctx->ac, buffer,
2560 LLVMConstInt(ctx->i32, 0x80000000, 0),
2561 1, ctx->i32_0, tf_base,
2562 0, 1, 0, true, false);
2563
2564 lp_build_endif(&inner_if_ctx);
2565
2566 /* Store the tessellation factors. */
2567 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2568 MIN2(stride, 4), byteoffset, tf_base,
2569 4, 1, 0, true, false);
2570 if (vec1)
2571 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2572 stride - 4, byteoffset, tf_base,
2573 20, 1, 0, true, false);
2574
2575 /* Store the tess factors into the offchip buffer if TES reads them. */
2576 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
2577 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
2578 LLVMValueRef tf_inner_offset;
2579 unsigned param_outer, param_inner;
2580
2581 buf = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
2582 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
2583 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2584
2585 param_outer = si_shader_io_get_unique_index(
2586 TGSI_SEMANTIC_TESSOUTER, 0);
2587 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2588 LLVMConstInt(ctx->i32, param_outer, 0));
2589
2590 outer_vec = lp_build_gather_values(gallivm, outer,
2591 util_next_power_of_two(outer_comps));
2592
2593 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
2594 outer_comps, tf_outer_offset,
2595 base, 0, 1, 0, true, false);
2596 if (inner_comps) {
2597 param_inner = si_shader_io_get_unique_index(
2598 TGSI_SEMANTIC_TESSINNER, 0);
2599 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2600 LLVMConstInt(ctx->i32, param_inner, 0));
2601
2602 inner_vec = inner_comps == 1 ? inner[0] :
2603 lp_build_gather_values(gallivm, inner, inner_comps);
2604 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
2605 inner_comps, tf_inner_offset,
2606 base, 0, 1, 0, true, false);
2607 }
2608 }
2609
2610 lp_build_endif(&if_ctx);
2611 }
2612
2613 /* This only writes the tessellation factor levels. */
2614 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2615 {
2616 struct si_shader_context *ctx = si_shader_context(bld_base);
2617 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2618 LLVMValueRef offchip_soffset, offchip_layout;
2619
2620 si_copy_tcs_inputs(bld_base);
2621
2622 rel_patch_id = get_rel_patch_id(ctx);
2623 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2624 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2625
2626 /* Return epilog parameters from this function. */
2627 LLVMBuilderRef builder = ctx->gallivm.builder;
2628 LLVMValueRef ret = ctx->return_value;
2629 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2630 unsigned vgpr;
2631
2632 /* RW_BUFFERS pointer */
2633 rw_buffers = LLVMGetParam(ctx->main_fn,
2634 SI_PARAM_RW_BUFFERS);
2635 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2636 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2637 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2638 ctx->i32_0, "");
2639 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2640 ctx->i32_1, "");
2641 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2642 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2643
2644 /* Tess offchip and factor buffer soffset are after user SGPRs. */
2645 offchip_layout = LLVMGetParam(ctx->main_fn,
2646 SI_PARAM_TCS_OFFCHIP_LAYOUT);
2647 offchip_soffset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2648 tf_soffset = LLVMGetParam(ctx->main_fn,
2649 SI_PARAM_TESS_FACTOR_OFFSET);
2650 ret = LLVMBuildInsertValue(builder, ret, offchip_layout,
2651 SI_SGPR_TCS_OFFCHIP_LAYOUT, "");
2652 ret = LLVMBuildInsertValue(builder, ret, offchip_soffset,
2653 SI_TCS_NUM_USER_SGPR, "");
2654 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2655 SI_TCS_NUM_USER_SGPR + 1, "");
2656
2657 /* VGPRs */
2658 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2659 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2660 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2661
2662 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2663 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2664 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2665 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2666 ctx->return_value = ret;
2667 }
2668
2669 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2670 {
2671 struct si_shader_context *ctx = si_shader_context(bld_base);
2672 struct si_shader *shader = ctx->shader;
2673 struct tgsi_shader_info *info = &shader->selector->info;
2674 struct gallivm_state *gallivm = &ctx->gallivm;
2675 unsigned i, chan;
2676 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
2677 ctx->param_rel_auto_id);
2678 LLVMValueRef vertex_dw_stride =
2679 unpack_param(ctx, SI_PARAM_VS_STATE_BITS, 24, 8);
2680 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2681 vertex_dw_stride, "");
2682
2683 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2684 * its inputs from it. */
2685 for (i = 0; i < info->num_outputs; i++) {
2686 LLVMValueRef *out_ptr = ctx->outputs[i];
2687 unsigned name = info->output_semantic_name[i];
2688 unsigned index = info->output_semantic_index[i];
2689 int param = si_shader_io_get_unique_index(name, index);
2690 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2691 LLVMConstInt(ctx->i32, param * 4, 0), "");
2692
2693 for (chan = 0; chan < 4; chan++) {
2694 lds_store(bld_base, chan, dw_addr,
2695 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2696 }
2697 }
2698 }
2699
2700 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2701 {
2702 struct si_shader_context *ctx = si_shader_context(bld_base);
2703 struct gallivm_state *gallivm = &ctx->gallivm;
2704 struct si_shader *es = ctx->shader;
2705 struct tgsi_shader_info *info = &es->selector->info;
2706 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
2707 ctx->param_es2gs_offset);
2708 unsigned chan;
2709 int i;
2710
2711 for (i = 0; i < info->num_outputs; i++) {
2712 LLVMValueRef *out_ptr = ctx->outputs[i];
2713 int param_index;
2714
2715 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2716 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2717 continue;
2718
2719 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2720 info->output_semantic_index[i]);
2721
2722 for (chan = 0; chan < 4; chan++) {
2723 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2724 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2725
2726 ac_build_buffer_store_dword(&ctx->ac,
2727 ctx->esgs_ring,
2728 out_val, 1, NULL, soffset,
2729 (4 * param_index + chan) * 4,
2730 1, 1, true, true);
2731 }
2732 }
2733 }
2734
2735 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2736 {
2737 struct si_shader_context *ctx = si_shader_context(bld_base);
2738
2739 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
2740 LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID));
2741 }
2742
2743 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2744 {
2745 struct si_shader_context *ctx = si_shader_context(bld_base);
2746 struct gallivm_state *gallivm = &ctx->gallivm;
2747 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2748 struct si_shader_output_values *outputs = NULL;
2749 int i,j;
2750
2751 assert(!ctx->shader->is_gs_copy_shader);
2752
2753 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2754
2755 /* Vertex color clamping.
2756 *
2757 * This uses a state constant loaded in a user data SGPR and
2758 * an IF statement is added that clamps all colors if the constant
2759 * is true.
2760 */
2761 if (ctx->type == PIPE_SHADER_VERTEX) {
2762 struct lp_build_if_state if_ctx;
2763 LLVMValueRef cond = NULL;
2764 LLVMValueRef addr, val;
2765
2766 for (i = 0; i < info->num_outputs; i++) {
2767 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2768 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2769 continue;
2770
2771 /* We've found a color. */
2772 if (!cond) {
2773 /* The state is in the first bit of the user SGPR. */
2774 cond = LLVMGetParam(ctx->main_fn,
2775 SI_PARAM_VS_STATE_BITS);
2776 cond = LLVMBuildTrunc(gallivm->builder, cond,
2777 ctx->i1, "");
2778 lp_build_if(&if_ctx, gallivm, cond);
2779 }
2780
2781 for (j = 0; j < 4; j++) {
2782 addr = ctx->outputs[i][j];
2783 val = LLVMBuildLoad(gallivm->builder, addr, "");
2784 val = ac_build_clamp(&ctx->ac, val);
2785 LLVMBuildStore(gallivm->builder, val, addr);
2786 }
2787 }
2788
2789 if (cond)
2790 lp_build_endif(&if_ctx);
2791 }
2792
2793 for (i = 0; i < info->num_outputs; i++) {
2794 outputs[i].semantic_name = info->output_semantic_name[i];
2795 outputs[i].semantic_index = info->output_semantic_index[i];
2796
2797 for (j = 0; j < 4; j++) {
2798 outputs[i].values[j] =
2799 LLVMBuildLoad(gallivm->builder,
2800 ctx->outputs[i][j],
2801 "");
2802 outputs[i].vertex_stream[j] =
2803 (info->output_streams[i] >> (2 * j)) & 3;
2804 }
2805
2806 }
2807
2808 /* Return the primitive ID from the LLVM function. */
2809 ctx->return_value =
2810 LLVMBuildInsertValue(gallivm->builder,
2811 ctx->return_value,
2812 bitcast(bld_base, TGSI_TYPE_FLOAT,
2813 get_primitive_id(bld_base, 0)),
2814 VS_EPILOG_PRIMID_LOC, "");
2815
2816 if (ctx->shader->selector->so.num_outputs)
2817 si_llvm_emit_streamout(ctx, outputs, i, 0);
2818 si_llvm_export_vs(bld_base, outputs, i);
2819 FREE(outputs);
2820 }
2821
2822 struct si_ps_exports {
2823 unsigned num;
2824 struct ac_export_args args[10];
2825 };
2826
2827 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
2828 bool writes_samplemask)
2829 {
2830 if (writes_z) {
2831 /* Z needs 32 bits. */
2832 if (writes_samplemask)
2833 return V_028710_SPI_SHADER_32_ABGR;
2834 else if (writes_stencil)
2835 return V_028710_SPI_SHADER_32_GR;
2836 else
2837 return V_028710_SPI_SHADER_32_R;
2838 } else if (writes_stencil || writes_samplemask) {
2839 /* Both stencil and sample mask need only 16 bits. */
2840 return V_028710_SPI_SHADER_UINT16_ABGR;
2841 } else {
2842 return V_028710_SPI_SHADER_ZERO;
2843 }
2844 }
2845
2846 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2847 LLVMValueRef depth, LLVMValueRef stencil,
2848 LLVMValueRef samplemask, struct si_ps_exports *exp)
2849 {
2850 struct si_shader_context *ctx = si_shader_context(bld_base);
2851 struct lp_build_context *base = &bld_base->base;
2852 struct ac_export_args args;
2853 unsigned mask = 0;
2854 unsigned format = si_get_spi_shader_z_format(depth != NULL,
2855 stencil != NULL,
2856 samplemask != NULL);
2857
2858 assert(depth || stencil || samplemask);
2859
2860 args.valid_mask = 1; /* whether the EXEC mask is valid */
2861 args.done = 1; /* DONE bit */
2862
2863 /* Specify the target we are exporting */
2864 args.target = V_008DFC_SQ_EXP_MRTZ;
2865
2866 args.compr = 0; /* COMP flag */
2867 args.out[0] = base->undef; /* R, depth */
2868 args.out[1] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2869 args.out[2] = base->undef; /* B, sample mask */
2870 args.out[3] = base->undef; /* A, alpha to mask */
2871
2872 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
2873 assert(!depth);
2874 args.compr = 1; /* COMPR flag */
2875
2876 if (stencil) {
2877 /* Stencil should be in X[23:16]. */
2878 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
2879 stencil = LLVMBuildShl(ctx->gallivm.builder, stencil,
2880 LLVMConstInt(ctx->i32, 16, 0), "");
2881 args.out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
2882 mask |= 0x3;
2883 }
2884 if (samplemask) {
2885 /* SampleMask should be in Y[15:0]. */
2886 args.out[1] = samplemask;
2887 mask |= 0xc;
2888 }
2889 } else {
2890 if (depth) {
2891 args.out[0] = depth;
2892 mask |= 0x1;
2893 }
2894 if (stencil) {
2895 args.out[1] = stencil;
2896 mask |= 0x2;
2897 }
2898 if (samplemask) {
2899 args.out[2] = samplemask;
2900 mask |= 0x4;
2901 }
2902 }
2903
2904 /* SI (except OLAND and HAINAN) has a bug that it only looks
2905 * at the X writemask component. */
2906 if (ctx->screen->b.chip_class == SI &&
2907 ctx->screen->b.family != CHIP_OLAND &&
2908 ctx->screen->b.family != CHIP_HAINAN)
2909 mask |= 0x1;
2910
2911 /* Specify which components to enable */
2912 args.enabled_channels = mask;
2913
2914 memcpy(&exp->args[exp->num++], &args, sizeof(args));
2915 }
2916
2917 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2918 LLVMValueRef *color, unsigned index,
2919 unsigned samplemask_param,
2920 bool is_last, struct si_ps_exports *exp)
2921 {
2922 struct si_shader_context *ctx = si_shader_context(bld_base);
2923 struct lp_build_context *base = &bld_base->base;
2924 int i;
2925
2926 /* Clamp color */
2927 if (ctx->shader->key.part.ps.epilog.clamp_color)
2928 for (i = 0; i < 4; i++)
2929 color[i] = ac_build_clamp(&ctx->ac, color[i]);
2930
2931 /* Alpha to one */
2932 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
2933 color[3] = base->one;
2934
2935 /* Alpha test */
2936 if (index == 0 &&
2937 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2938 si_alpha_test(bld_base, color[3]);
2939
2940 /* Line & polygon smoothing */
2941 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
2942 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
2943 samplemask_param);
2944
2945 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2946 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
2947 struct ac_export_args args[8];
2948 int c, last = -1;
2949
2950 /* Get the export arguments, also find out what the last one is. */
2951 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2952 si_llvm_init_export_args(bld_base, color,
2953 V_008DFC_SQ_EXP_MRT + c, &args[c]);
2954 if (args[c].enabled_channels)
2955 last = c;
2956 }
2957
2958 /* Emit all exports. */
2959 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2960 if (is_last && last == c) {
2961 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
2962 args[c].done = 1; /* DONE bit */
2963 } else if (!args[c].enabled_channels)
2964 continue; /* unnecessary NULL export */
2965
2966 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
2967 }
2968 } else {
2969 struct ac_export_args args;
2970
2971 /* Export */
2972 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2973 &args);
2974 if (is_last) {
2975 args.valid_mask = 1; /* whether the EXEC mask is valid */
2976 args.done = 1; /* DONE bit */
2977 } else if (!args.enabled_channels)
2978 return; /* unnecessary NULL export */
2979
2980 memcpy(&exp->args[exp->num++], &args, sizeof(args));
2981 }
2982 }
2983
2984 static void si_emit_ps_exports(struct si_shader_context *ctx,
2985 struct si_ps_exports *exp)
2986 {
2987 for (unsigned i = 0; i < exp->num; i++)
2988 ac_build_export(&ctx->ac, &exp->args[i]);
2989 }
2990
2991 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2992 {
2993 struct si_shader_context *ctx = si_shader_context(bld_base);
2994 struct lp_build_context *base = &bld_base->base;
2995 struct ac_export_args args;
2996
2997 args.enabled_channels = 0x0; /* enabled channels */
2998 args.valid_mask = 1; /* whether the EXEC mask is valid */
2999 args.done = 1; /* DONE bit */
3000 args.target = V_008DFC_SQ_EXP_NULL;
3001 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
3002 args.out[0] = base->undef; /* R */
3003 args.out[1] = base->undef; /* G */
3004 args.out[2] = base->undef; /* B */
3005 args.out[3] = base->undef; /* A */
3006
3007 ac_build_export(&ctx->ac, &args);
3008 }
3009
3010 /**
3011 * Return PS outputs in this order:
3012 *
3013 * v[0:3] = color0.xyzw
3014 * v[4:7] = color1.xyzw
3015 * ...
3016 * vN+0 = Depth
3017 * vN+1 = Stencil
3018 * vN+2 = SampleMask
3019 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3020 *
3021 * The alpha-ref SGPR is returned via its original location.
3022 */
3023 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
3024 {
3025 struct si_shader_context *ctx = si_shader_context(bld_base);
3026 struct si_shader *shader = ctx->shader;
3027 struct tgsi_shader_info *info = &shader->selector->info;
3028 LLVMBuilderRef builder = ctx->gallivm.builder;
3029 unsigned i, j, first_vgpr, vgpr;
3030
3031 LLVMValueRef color[8][4] = {};
3032 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3033 LLVMValueRef ret;
3034
3035 /* Read the output values. */
3036 for (i = 0; i < info->num_outputs; i++) {
3037 unsigned semantic_name = info->output_semantic_name[i];
3038 unsigned semantic_index = info->output_semantic_index[i];
3039
3040 switch (semantic_name) {
3041 case TGSI_SEMANTIC_COLOR:
3042 assert(semantic_index < 8);
3043 for (j = 0; j < 4; j++) {
3044 LLVMValueRef ptr = ctx->outputs[i][j];
3045 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3046 color[semantic_index][j] = result;
3047 }
3048 break;
3049 case TGSI_SEMANTIC_POSITION:
3050 depth = LLVMBuildLoad(builder,
3051 ctx->outputs[i][2], "");
3052 break;
3053 case TGSI_SEMANTIC_STENCIL:
3054 stencil = LLVMBuildLoad(builder,
3055 ctx->outputs[i][1], "");
3056 break;
3057 case TGSI_SEMANTIC_SAMPLEMASK:
3058 samplemask = LLVMBuildLoad(builder,
3059 ctx->outputs[i][0], "");
3060 break;
3061 default:
3062 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3063 semantic_name);
3064 }
3065 }
3066
3067 /* Fill the return structure. */
3068 ret = ctx->return_value;
3069
3070 /* Set SGPRs. */
3071 ret = LLVMBuildInsertValue(builder, ret,
3072 bitcast(bld_base, TGSI_TYPE_SIGNED,
3073 LLVMGetParam(ctx->main_fn,
3074 SI_PARAM_ALPHA_REF)),
3075 SI_SGPR_ALPHA_REF, "");
3076
3077 /* Set VGPRs */
3078 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3079 for (i = 0; i < ARRAY_SIZE(color); i++) {
3080 if (!color[i][0])
3081 continue;
3082
3083 for (j = 0; j < 4; j++)
3084 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3085 }
3086 if (depth)
3087 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3088 if (stencil)
3089 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3090 if (samplemask)
3091 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3092
3093 /* Add the input sample mask for smoothing at the end. */
3094 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3095 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3096 ret = LLVMBuildInsertValue(builder, ret,
3097 LLVMGetParam(ctx->main_fn,
3098 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3099
3100 ctx->return_value = ret;
3101 }
3102
3103 /**
3104 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3105 * buffer in number of elements and return it as an i32.
3106 */
3107 static LLVMValueRef get_buffer_size(
3108 struct lp_build_tgsi_context *bld_base,
3109 LLVMValueRef descriptor)
3110 {
3111 struct si_shader_context *ctx = si_shader_context(bld_base);
3112 struct gallivm_state *gallivm = &ctx->gallivm;
3113 LLVMBuilderRef builder = gallivm->builder;
3114 LLVMValueRef size =
3115 LLVMBuildExtractElement(builder, descriptor,
3116 LLVMConstInt(ctx->i32, 2, 0), "");
3117
3118 if (ctx->screen->b.chip_class == VI) {
3119 /* On VI, the descriptor contains the size in bytes,
3120 * but TXQ must return the size in elements.
3121 * The stride is always non-zero for resources using TXQ.
3122 */
3123 LLVMValueRef stride =
3124 LLVMBuildExtractElement(builder, descriptor,
3125 ctx->i32_1, "");
3126 stride = LLVMBuildLShr(builder, stride,
3127 LLVMConstInt(ctx->i32, 16, 0), "");
3128 stride = LLVMBuildAnd(builder, stride,
3129 LLVMConstInt(ctx->i32, 0x3FFF, 0), "");
3130
3131 size = LLVMBuildUDiv(builder, size, stride, "");
3132 }
3133
3134 return size;
3135 }
3136
3137 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3138 struct lp_build_tgsi_context *bld_base,
3139 struct lp_build_emit_data *emit_data);
3140
3141 /* Prevent optimizations (at least of memory accesses) across the current
3142 * point in the program by emitting empty inline assembly that is marked as
3143 * having side effects.
3144 *
3145 * Optionally, a value can be passed through the inline assembly to prevent
3146 * LLVM from hoisting calls to ReadNone functions.
3147 */
3148 static void emit_optimization_barrier(struct si_shader_context *ctx,
3149 LLVMValueRef *pvgpr)
3150 {
3151 static int counter = 0;
3152
3153 LLVMBuilderRef builder = ctx->gallivm.builder;
3154 char code[16];
3155
3156 snprintf(code, sizeof(code), "; %d", p_atomic_inc_return(&counter));
3157
3158 if (!pvgpr) {
3159 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3160 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, code, "", true, false);
3161 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3162 } else {
3163 LLVMTypeRef ftype = LLVMFunctionType(ctx->i32, &ctx->i32, 1, false);
3164 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, code, "=v,0", true, false);
3165 LLVMValueRef vgpr = *pvgpr;
3166 LLVMTypeRef vgpr_type = LLVMTypeOf(vgpr);
3167 unsigned vgpr_size = llvm_get_type_size(vgpr_type);
3168 LLVMValueRef vgpr0;
3169
3170 assert(vgpr_size % 4 == 0);
3171
3172 vgpr = LLVMBuildBitCast(builder, vgpr, LLVMVectorType(ctx->i32, vgpr_size / 4), "");
3173 vgpr0 = LLVMBuildExtractElement(builder, vgpr, ctx->i32_0, "");
3174 vgpr0 = LLVMBuildCall(builder, inlineasm, &vgpr0, 1, "");
3175 vgpr = LLVMBuildInsertElement(builder, vgpr, vgpr0, ctx->i32_0, "");
3176 vgpr = LLVMBuildBitCast(builder, vgpr, vgpr_type, "");
3177
3178 *pvgpr = vgpr;
3179 }
3180 }
3181
3182 /* Combine these with & instead of |. */
3183 #define NOOP_WAITCNT 0xf7f
3184 #define LGKM_CNT 0x07f
3185 #define VM_CNT 0xf70
3186
3187 static void emit_waitcnt(struct si_shader_context *ctx, unsigned simm16)
3188 {
3189 struct gallivm_state *gallivm = &ctx->gallivm;
3190 LLVMBuilderRef builder = gallivm->builder;
3191 LLVMValueRef args[1] = {
3192 LLVMConstInt(ctx->i32, simm16, 0)
3193 };
3194 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3195 ctx->voidt, args, 1, 0);
3196 }
3197
3198 static void membar_emit(
3199 const struct lp_build_tgsi_action *action,
3200 struct lp_build_tgsi_context *bld_base,
3201 struct lp_build_emit_data *emit_data)
3202 {
3203 struct si_shader_context *ctx = si_shader_context(bld_base);
3204 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3205 unsigned flags = LLVMConstIntGetZExtValue(src0);
3206 unsigned waitcnt = NOOP_WAITCNT;
3207
3208 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3209 waitcnt &= VM_CNT & LGKM_CNT;
3210
3211 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3212 TGSI_MEMBAR_SHADER_BUFFER |
3213 TGSI_MEMBAR_SHADER_IMAGE))
3214 waitcnt &= VM_CNT;
3215
3216 if (flags & TGSI_MEMBAR_SHARED)
3217 waitcnt &= LGKM_CNT;
3218
3219 if (waitcnt != NOOP_WAITCNT)
3220 emit_waitcnt(ctx, waitcnt);
3221 }
3222
3223 static void clock_emit(
3224 const struct lp_build_tgsi_action *action,
3225 struct lp_build_tgsi_context *bld_base,
3226 struct lp_build_emit_data *emit_data)
3227 {
3228 struct si_shader_context *ctx = si_shader_context(bld_base);
3229 struct gallivm_state *gallivm = &ctx->gallivm;
3230 LLVMValueRef tmp;
3231
3232 tmp = lp_build_intrinsic(gallivm->builder, "llvm.readcyclecounter",
3233 ctx->i64, NULL, 0, 0);
3234 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->v2i32, "");
3235
3236 emit_data->output[0] =
3237 LLVMBuildExtractElement(gallivm->builder, tmp, ctx->i32_0, "");
3238 emit_data->output[1] =
3239 LLVMBuildExtractElement(gallivm->builder, tmp, ctx->i32_1, "");
3240 }
3241
3242 static LLVMValueRef
3243 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3244 const struct tgsi_full_src_register *reg)
3245 {
3246 LLVMValueRef index;
3247 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3248 SI_PARAM_SHADER_BUFFERS);
3249
3250 if (!reg->Register.Indirect)
3251 index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
3252 else
3253 index = get_bounded_indirect_index(ctx, &reg->Indirect,
3254 reg->Register.Index,
3255 SI_NUM_SHADER_BUFFERS);
3256
3257 return ac_build_indexed_load_const(&ctx->ac, rsrc_ptr, index);
3258 }
3259
3260 static bool tgsi_is_array_sampler(unsigned target)
3261 {
3262 return target == TGSI_TEXTURE_1D_ARRAY ||
3263 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3264 target == TGSI_TEXTURE_2D_ARRAY ||
3265 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3266 target == TGSI_TEXTURE_CUBE_ARRAY ||
3267 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3268 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3269 }
3270
3271 static bool tgsi_is_array_image(unsigned target)
3272 {
3273 return target == TGSI_TEXTURE_3D ||
3274 target == TGSI_TEXTURE_CUBE ||
3275 target == TGSI_TEXTURE_1D_ARRAY ||
3276 target == TGSI_TEXTURE_2D_ARRAY ||
3277 target == TGSI_TEXTURE_CUBE_ARRAY ||
3278 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3279 }
3280
3281 /**
3282 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3283 *
3284 * At least on Tonga, executing image stores on images with DCC enabled and
3285 * non-trivial can eventually lead to lockups. This can occur when an
3286 * application binds an image as read-only but then uses a shader that writes
3287 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3288 * program termination) in this case, but it doesn't cost much to be a bit
3289 * nicer: disabling DCC in the shader still leads to undefined results but
3290 * avoids the lockup.
3291 */
3292 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3293 LLVMValueRef rsrc)
3294 {
3295 if (ctx->screen->b.chip_class <= CIK) {
3296 return rsrc;
3297 } else {
3298 LLVMBuilderRef builder = ctx->gallivm.builder;
3299 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3300 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3301 LLVMValueRef tmp;
3302
3303 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3304 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3305 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3306 }
3307 }
3308
3309 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3310 {
3311 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3312 CONST_ADDR_SPACE);
3313 }
3314
3315 static LLVMValueRef load_image_desc(struct si_shader_context *ctx,
3316 LLVMValueRef list, LLVMValueRef index,
3317 unsigned target)
3318 {
3319 LLVMBuilderRef builder = ctx->gallivm.builder;
3320
3321 if (target == TGSI_TEXTURE_BUFFER) {
3322 index = LLVMBuildMul(builder, index,
3323 LLVMConstInt(ctx->i32, 2, 0), "");
3324 index = LLVMBuildAdd(builder, index,
3325 ctx->i32_1, "");
3326 list = LLVMBuildPointerCast(builder, list,
3327 const_array(ctx->v4i32, 0), "");
3328 }
3329
3330 return ac_build_indexed_load_const(&ctx->ac, list, index);
3331 }
3332
3333 /**
3334 * Load the resource descriptor for \p image.
3335 */
3336 static void
3337 image_fetch_rsrc(
3338 struct lp_build_tgsi_context *bld_base,
3339 const struct tgsi_full_src_register *image,
3340 bool is_store, unsigned target,
3341 LLVMValueRef *rsrc)
3342 {
3343 struct si_shader_context *ctx = si_shader_context(bld_base);
3344 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3345 SI_PARAM_IMAGES);
3346 LLVMValueRef index;
3347 bool dcc_off = is_store;
3348
3349 assert(image->Register.File == TGSI_FILE_IMAGE);
3350
3351 if (!image->Register.Indirect) {
3352 const struct tgsi_shader_info *info = bld_base->info;
3353 unsigned images_writemask = info->images_store |
3354 info->images_atomic;
3355
3356 index = LLVMConstInt(ctx->i32, image->Register.Index, 0);
3357
3358 if (images_writemask & (1 << image->Register.Index))
3359 dcc_off = true;
3360 } else {
3361 /* From the GL_ARB_shader_image_load_store extension spec:
3362 *
3363 * If a shader performs an image load, store, or atomic
3364 * operation using an image variable declared as an array,
3365 * and if the index used to select an individual element is
3366 * negative or greater than or equal to the size of the
3367 * array, the results of the operation are undefined but may
3368 * not lead to termination.
3369 */
3370 index = get_bounded_indirect_index(ctx, &image->Indirect,
3371 image->Register.Index,
3372 SI_NUM_IMAGES);
3373 }
3374
3375 *rsrc = load_image_desc(ctx, rsrc_ptr, index, target);
3376 if (dcc_off && target != TGSI_TEXTURE_BUFFER)
3377 *rsrc = force_dcc_off(ctx, *rsrc);
3378 }
3379
3380 static LLVMValueRef image_fetch_coords(
3381 struct lp_build_tgsi_context *bld_base,
3382 const struct tgsi_full_instruction *inst,
3383 unsigned src)
3384 {
3385 struct si_shader_context *ctx = si_shader_context(bld_base);
3386 struct gallivm_state *gallivm = &ctx->gallivm;
3387 LLVMBuilderRef builder = gallivm->builder;
3388 unsigned target = inst->Memory.Texture;
3389 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3390 LLVMValueRef coords[4];
3391 LLVMValueRef tmp;
3392 int chan;
3393
3394 for (chan = 0; chan < num_coords; ++chan) {
3395 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3396 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
3397 coords[chan] = tmp;
3398 }
3399
3400 /* 1D textures are allocated and used as 2D on GFX9. */
3401 if (ctx->screen->b.chip_class >= GFX9) {
3402 if (target == TGSI_TEXTURE_1D) {
3403 coords[1] = ctx->i32_0;
3404 num_coords++;
3405 } else if (target == TGSI_TEXTURE_1D_ARRAY) {
3406 coords[2] = coords[1];
3407 coords[1] = ctx->i32_0;
3408 }
3409 }
3410
3411 if (num_coords == 1)
3412 return coords[0];
3413
3414 if (num_coords == 3) {
3415 /* LLVM has difficulties lowering 3-element vectors. */
3416 coords[3] = bld_base->uint_bld.undef;
3417 num_coords = 4;
3418 }
3419
3420 return lp_build_gather_values(gallivm, coords, num_coords);
3421 }
3422
3423 /**
3424 * Append the extra mode bits that are used by image load and store.
3425 */
3426 static void image_append_args(
3427 struct si_shader_context *ctx,
3428 struct lp_build_emit_data * emit_data,
3429 unsigned target,
3430 bool atomic,
3431 bool force_glc)
3432 {
3433 const struct tgsi_full_instruction *inst = emit_data->inst;
3434 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3435 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3436 LLVMValueRef r128 = i1false;
3437 LLVMValueRef da = tgsi_is_array_image(target) ? i1true : i1false;
3438 LLVMValueRef glc =
3439 force_glc ||
3440 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3441 i1true : i1false;
3442 LLVMValueRef slc = i1false;
3443 LLVMValueRef lwe = i1false;
3444
3445 if (atomic || (HAVE_LLVM <= 0x0309)) {
3446 emit_data->args[emit_data->arg_count++] = r128;
3447 emit_data->args[emit_data->arg_count++] = da;
3448 if (!atomic) {
3449 emit_data->args[emit_data->arg_count++] = glc;
3450 }
3451 emit_data->args[emit_data->arg_count++] = slc;
3452 return;
3453 }
3454
3455 /* HAVE_LLVM >= 0x0400 */
3456 emit_data->args[emit_data->arg_count++] = glc;
3457 emit_data->args[emit_data->arg_count++] = slc;
3458 emit_data->args[emit_data->arg_count++] = lwe;
3459 emit_data->args[emit_data->arg_count++] = da;
3460 }
3461
3462 /**
3463 * Append the resource and indexing arguments for buffer intrinsics.
3464 *
3465 * \param rsrc the v4i32 buffer resource
3466 * \param index index into the buffer (stride-based)
3467 * \param offset byte offset into the buffer
3468 */
3469 static void buffer_append_args(
3470 struct si_shader_context *ctx,
3471 struct lp_build_emit_data *emit_data,
3472 LLVMValueRef rsrc,
3473 LLVMValueRef index,
3474 LLVMValueRef offset,
3475 bool atomic,
3476 bool force_glc)
3477 {
3478 const struct tgsi_full_instruction *inst = emit_data->inst;
3479 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3480 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3481
3482 emit_data->args[emit_data->arg_count++] = rsrc;
3483 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3484 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3485 if (!atomic) {
3486 emit_data->args[emit_data->arg_count++] =
3487 force_glc ||
3488 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3489 i1true : i1false; /* glc */
3490 }
3491 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3492 }
3493
3494 static void load_fetch_args(
3495 struct lp_build_tgsi_context * bld_base,
3496 struct lp_build_emit_data * emit_data)
3497 {
3498 struct si_shader_context *ctx = si_shader_context(bld_base);
3499 struct gallivm_state *gallivm = &ctx->gallivm;
3500 const struct tgsi_full_instruction * inst = emit_data->inst;
3501 unsigned target = inst->Memory.Texture;
3502 LLVMValueRef rsrc;
3503
3504 emit_data->dst_type = ctx->v4f32;
3505
3506 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3507 LLVMBuilderRef builder = gallivm->builder;
3508 LLVMValueRef offset;
3509 LLVMValueRef tmp;
3510
3511 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3512
3513 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3514 offset = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
3515
3516 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
3517 offset, false, false);
3518 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3519 LLVMValueRef coords;
3520
3521 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
3522 coords = image_fetch_coords(bld_base, inst, 1);
3523
3524 if (target == TGSI_TEXTURE_BUFFER) {
3525 buffer_append_args(ctx, emit_data, rsrc, coords,
3526 ctx->i32_0, false, false);
3527 } else {
3528 emit_data->args[0] = coords;
3529 emit_data->args[1] = rsrc;
3530 emit_data->args[2] = LLVMConstInt(ctx->i32, 15, 0); /* dmask */
3531 emit_data->arg_count = 3;
3532
3533 image_append_args(ctx, emit_data, target, false, false);
3534 }
3535 }
3536 }
3537
3538 static unsigned get_load_intr_attribs(bool readonly_memory)
3539 {
3540 /* READNONE means writes can't affect it, while READONLY means that
3541 * writes can affect it. */
3542 return readonly_memory && HAVE_LLVM >= 0x0400 ?
3543 LP_FUNC_ATTR_READNONE :
3544 LP_FUNC_ATTR_READONLY;
3545 }
3546
3547 static unsigned get_store_intr_attribs(bool writeonly_memory)
3548 {
3549 return writeonly_memory && HAVE_LLVM >= 0x0400 ?
3550 LP_FUNC_ATTR_INACCESSIBLE_MEM_ONLY :
3551 LP_FUNC_ATTR_WRITEONLY;
3552 }
3553
3554 static void load_emit_buffer(struct si_shader_context *ctx,
3555 struct lp_build_emit_data *emit_data,
3556 bool readonly_memory)
3557 {
3558 const struct tgsi_full_instruction *inst = emit_data->inst;
3559 struct gallivm_state *gallivm = &ctx->gallivm;
3560 LLVMBuilderRef builder = gallivm->builder;
3561 uint writemask = inst->Dst[0].Register.WriteMask;
3562 uint count = util_last_bit(writemask);
3563 const char *intrinsic_name;
3564 LLVMTypeRef dst_type;
3565
3566 switch (count) {
3567 case 1:
3568 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3569 dst_type = ctx->f32;
3570 break;
3571 case 2:
3572 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3573 dst_type = LLVMVectorType(ctx->f32, 2);
3574 break;
3575 default: // 3 & 4
3576 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3577 dst_type = ctx->v4f32;
3578 count = 4;
3579 }
3580
3581 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3582 builder, intrinsic_name, dst_type,
3583 emit_data->args, emit_data->arg_count,
3584 get_load_intr_attribs(readonly_memory));
3585 }
3586
3587 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3588 const struct tgsi_full_instruction *inst,
3589 LLVMTypeRef type, int arg)
3590 {
3591 struct gallivm_state *gallivm = &ctx->gallivm;
3592 LLVMBuilderRef builder = gallivm->builder;
3593 LLVMValueRef offset, ptr;
3594 int addr_space;
3595
3596 offset = lp_build_emit_fetch(&ctx->bld_base, inst, arg, 0);
3597 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3598
3599 ptr = ctx->shared_memory;
3600 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3601 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3602 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3603
3604 return ptr;
3605 }
3606
3607 static void load_emit_memory(
3608 struct si_shader_context *ctx,
3609 struct lp_build_emit_data *emit_data)
3610 {
3611 const struct tgsi_full_instruction *inst = emit_data->inst;
3612 struct gallivm_state *gallivm = &ctx->gallivm;
3613 LLVMBuilderRef builder = gallivm->builder;
3614 unsigned writemask = inst->Dst[0].Register.WriteMask;
3615 LLVMValueRef channels[4], ptr, derived_ptr, index;
3616 int chan;
3617
3618 ptr = get_memory_ptr(ctx, inst, ctx->f32, 1);
3619
3620 for (chan = 0; chan < 4; ++chan) {
3621 if (!(writemask & (1 << chan))) {
3622 channels[chan] = LLVMGetUndef(ctx->f32);
3623 continue;
3624 }
3625
3626 index = LLVMConstInt(ctx->i32, chan, 0);
3627 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3628 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3629 }
3630 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3631 }
3632
3633 /**
3634 * Return true if the memory accessed by a LOAD or STORE instruction is
3635 * read-only or write-only, respectively.
3636 *
3637 * \param shader_buffers_reverse_access_mask
3638 * For LOAD, set this to (store | atomic) slot usage in the shader.
3639 * For STORE, set this to (load | atomic) slot usage in the shader.
3640 * \param images_reverse_access_mask Same as above, but for images.
3641 */
3642 static bool is_oneway_access_only(const struct tgsi_full_instruction *inst,
3643 const struct tgsi_shader_info *info,
3644 unsigned shader_buffers_reverse_access_mask,
3645 unsigned images_reverse_access_mask)
3646 {
3647 /* RESTRICT means NOALIAS.
3648 * If there are no writes, we can assume the accessed memory is read-only.
3649 * If there are no reads, we can assume the accessed memory is write-only.
3650 */
3651 if (inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT) {
3652 unsigned reverse_access_mask;
3653
3654 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3655 reverse_access_mask = shader_buffers_reverse_access_mask;
3656 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3657 reverse_access_mask = info->images_buffers &
3658 images_reverse_access_mask;
3659 } else {
3660 reverse_access_mask = ~info->images_buffers &
3661 images_reverse_access_mask;
3662 }
3663
3664 if (inst->Src[0].Register.Indirect) {
3665 if (!reverse_access_mask)
3666 return true;
3667 } else {
3668 if (!(reverse_access_mask &
3669 (1u << inst->Src[0].Register.Index)))
3670 return true;
3671 }
3672 }
3673
3674 /* If there are no buffer writes (for both shader buffers & image
3675 * buffers), it implies that buffer memory is read-only.
3676 * If there are no buffer reads (for both shader buffers & image
3677 * buffers), it implies that buffer memory is write-only.
3678 *
3679 * Same for the case when there are no writes/reads for non-buffer
3680 * images.
3681 */
3682 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
3683 (inst->Src[0].Register.File == TGSI_FILE_IMAGE &&
3684 inst->Memory.Texture == TGSI_TEXTURE_BUFFER)) {
3685 if (!shader_buffers_reverse_access_mask &&
3686 !(info->images_buffers & images_reverse_access_mask))
3687 return true;
3688 } else {
3689 if (!(~info->images_buffers & images_reverse_access_mask))
3690 return true;
3691 }
3692 return false;
3693 }
3694
3695 static void load_emit(
3696 const struct lp_build_tgsi_action *action,
3697 struct lp_build_tgsi_context *bld_base,
3698 struct lp_build_emit_data *emit_data)
3699 {
3700 struct si_shader_context *ctx = si_shader_context(bld_base);
3701 struct gallivm_state *gallivm = &ctx->gallivm;
3702 LLVMBuilderRef builder = gallivm->builder;
3703 const struct tgsi_full_instruction * inst = emit_data->inst;
3704 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
3705 char intrinsic_name[64];
3706 bool readonly_memory = false;
3707
3708 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3709 load_emit_memory(ctx, emit_data);
3710 return;
3711 }
3712
3713 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3714 emit_waitcnt(ctx, VM_CNT);
3715
3716 readonly_memory = !(inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE) &&
3717 is_oneway_access_only(inst, info,
3718 info->shader_buffers_store |
3719 info->shader_buffers_atomic,
3720 info->images_store |
3721 info->images_atomic);
3722
3723 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3724 load_emit_buffer(ctx, emit_data, readonly_memory);
3725 return;
3726 }
3727
3728 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3729 emit_data->output[emit_data->chan] =
3730 lp_build_intrinsic(
3731 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3732 emit_data->args, emit_data->arg_count,
3733 get_load_intr_attribs(readonly_memory));
3734 } else {
3735 ac_get_image_intr_name("llvm.amdgcn.image.load",
3736 emit_data->dst_type, /* vdata */
3737 LLVMTypeOf(emit_data->args[0]), /* coords */
3738 LLVMTypeOf(emit_data->args[1]), /* rsrc */
3739 intrinsic_name, sizeof(intrinsic_name));
3740
3741 emit_data->output[emit_data->chan] =
3742 lp_build_intrinsic(
3743 builder, intrinsic_name, emit_data->dst_type,
3744 emit_data->args, emit_data->arg_count,
3745 get_load_intr_attribs(readonly_memory));
3746 }
3747 }
3748
3749 static void store_fetch_args(
3750 struct lp_build_tgsi_context * bld_base,
3751 struct lp_build_emit_data * emit_data)
3752 {
3753 struct si_shader_context *ctx = si_shader_context(bld_base);
3754 struct gallivm_state *gallivm = &ctx->gallivm;
3755 LLVMBuilderRef builder = gallivm->builder;
3756 const struct tgsi_full_instruction * inst = emit_data->inst;
3757 struct tgsi_full_src_register memory;
3758 LLVMValueRef chans[4];
3759 LLVMValueRef data;
3760 LLVMValueRef rsrc;
3761 unsigned chan;
3762
3763 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3764
3765 for (chan = 0; chan < 4; ++chan) {
3766 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3767 }
3768 data = lp_build_gather_values(gallivm, chans, 4);
3769
3770 emit_data->args[emit_data->arg_count++] = data;
3771
3772 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3773
3774 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3775 LLVMValueRef offset;
3776 LLVMValueRef tmp;
3777
3778 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3779
3780 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3781 offset = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
3782
3783 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
3784 offset, false, false);
3785 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3786 unsigned target = inst->Memory.Texture;
3787 LLVMValueRef coords;
3788
3789 /* 8bit/16bit TC L1 write corruption bug on SI.
3790 * All store opcodes not aligned to a dword are affected.
3791 *
3792 * The only way to get unaligned stores in radeonsi is through
3793 * shader images.
3794 */
3795 bool force_glc = ctx->screen->b.chip_class == SI;
3796
3797 coords = image_fetch_coords(bld_base, inst, 0);
3798
3799 if (target == TGSI_TEXTURE_BUFFER) {
3800 image_fetch_rsrc(bld_base, &memory, true, target, &rsrc);
3801 buffer_append_args(ctx, emit_data, rsrc, coords,
3802 ctx->i32_0, false, force_glc);
3803 } else {
3804 emit_data->args[1] = coords;
3805 image_fetch_rsrc(bld_base, &memory, true, target,
3806 &emit_data->args[2]);
3807 emit_data->args[3] = LLVMConstInt(ctx->i32, 15, 0); /* dmask */
3808 emit_data->arg_count = 4;
3809
3810 image_append_args(ctx, emit_data, target, false, force_glc);
3811 }
3812 }
3813 }
3814
3815 static void store_emit_buffer(
3816 struct si_shader_context *ctx,
3817 struct lp_build_emit_data *emit_data,
3818 bool writeonly_memory)
3819 {
3820 const struct tgsi_full_instruction *inst = emit_data->inst;
3821 struct gallivm_state *gallivm = &ctx->gallivm;
3822 LLVMBuilderRef builder = gallivm->builder;
3823 LLVMValueRef base_data = emit_data->args[0];
3824 LLVMValueRef base_offset = emit_data->args[3];
3825 unsigned writemask = inst->Dst[0].Register.WriteMask;
3826
3827 while (writemask) {
3828 int start, count;
3829 const char *intrinsic_name;
3830 LLVMValueRef data;
3831 LLVMValueRef offset;
3832 LLVMValueRef tmp;
3833
3834 u_bit_scan_consecutive_range(&writemask, &start, &count);
3835
3836 /* Due to an LLVM limitation, split 3-element writes
3837 * into a 2-element and a 1-element write. */
3838 if (count == 3) {
3839 writemask |= 1 << (start + 2);
3840 count = 2;
3841 }
3842
3843 if (count == 4) {
3844 data = base_data;
3845 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3846 } else if (count == 2) {
3847 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3848
3849 tmp = LLVMBuildExtractElement(
3850 builder, base_data,
3851 LLVMConstInt(ctx->i32, start, 0), "");
3852 data = LLVMBuildInsertElement(
3853 builder, LLVMGetUndef(v2f32), tmp,
3854 ctx->i32_0, "");
3855
3856 tmp = LLVMBuildExtractElement(
3857 builder, base_data,
3858 LLVMConstInt(ctx->i32, start + 1, 0), "");
3859 data = LLVMBuildInsertElement(
3860 builder, data, tmp, ctx->i32_1, "");
3861
3862 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3863 } else {
3864 assert(count == 1);
3865 data = LLVMBuildExtractElement(
3866 builder, base_data,
3867 LLVMConstInt(ctx->i32, start, 0), "");
3868 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3869 }
3870
3871 offset = base_offset;
3872 if (start != 0) {
3873 offset = LLVMBuildAdd(
3874 builder, offset,
3875 LLVMConstInt(ctx->i32, start * 4, 0), "");
3876 }
3877
3878 emit_data->args[0] = data;
3879 emit_data->args[3] = offset;
3880
3881 lp_build_intrinsic(
3882 builder, intrinsic_name, emit_data->dst_type,
3883 emit_data->args, emit_data->arg_count,
3884 get_store_intr_attribs(writeonly_memory));
3885 }
3886 }
3887
3888 static void store_emit_memory(
3889 struct si_shader_context *ctx,
3890 struct lp_build_emit_data *emit_data)
3891 {
3892 const struct tgsi_full_instruction *inst = emit_data->inst;
3893 struct gallivm_state *gallivm = &ctx->gallivm;
3894 LLVMBuilderRef builder = gallivm->builder;
3895 unsigned writemask = inst->Dst[0].Register.WriteMask;
3896 LLVMValueRef ptr, derived_ptr, data, index;
3897 int chan;
3898
3899 ptr = get_memory_ptr(ctx, inst, ctx->f32, 0);
3900
3901 for (chan = 0; chan < 4; ++chan) {
3902 if (!(writemask & (1 << chan))) {
3903 continue;
3904 }
3905 data = lp_build_emit_fetch(&ctx->bld_base, inst, 1, chan);
3906 index = LLVMConstInt(ctx->i32, chan, 0);
3907 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3908 LLVMBuildStore(builder, data, derived_ptr);
3909 }
3910 }
3911
3912 static void store_emit(
3913 const struct lp_build_tgsi_action *action,
3914 struct lp_build_tgsi_context *bld_base,
3915 struct lp_build_emit_data *emit_data)
3916 {
3917 struct si_shader_context *ctx = si_shader_context(bld_base);
3918 struct gallivm_state *gallivm = &ctx->gallivm;
3919 LLVMBuilderRef builder = gallivm->builder;
3920 const struct tgsi_full_instruction * inst = emit_data->inst;
3921 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
3922 unsigned target = inst->Memory.Texture;
3923 char intrinsic_name[64];
3924 bool writeonly_memory = false;
3925
3926 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3927 store_emit_memory(ctx, emit_data);
3928 return;
3929 }
3930
3931 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3932 emit_waitcnt(ctx, VM_CNT);
3933
3934 writeonly_memory = is_oneway_access_only(inst, info,
3935 info->shader_buffers_load |
3936 info->shader_buffers_atomic,
3937 info->images_load |
3938 info->images_atomic);
3939
3940 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3941 store_emit_buffer(ctx, emit_data, writeonly_memory);
3942 return;
3943 }
3944
3945 if (target == TGSI_TEXTURE_BUFFER) {
3946 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3947 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3948 emit_data->dst_type, emit_data->args,
3949 emit_data->arg_count,
3950 get_store_intr_attribs(writeonly_memory));
3951 } else {
3952 ac_get_image_intr_name("llvm.amdgcn.image.store",
3953 LLVMTypeOf(emit_data->args[0]), /* vdata */
3954 LLVMTypeOf(emit_data->args[1]), /* coords */
3955 LLVMTypeOf(emit_data->args[2]), /* rsrc */
3956 intrinsic_name, sizeof(intrinsic_name));
3957
3958 emit_data->output[emit_data->chan] =
3959 lp_build_intrinsic(
3960 builder, intrinsic_name, emit_data->dst_type,
3961 emit_data->args, emit_data->arg_count,
3962 get_store_intr_attribs(writeonly_memory));
3963 }
3964 }
3965
3966 static void atomic_fetch_args(
3967 struct lp_build_tgsi_context * bld_base,
3968 struct lp_build_emit_data * emit_data)
3969 {
3970 struct si_shader_context *ctx = si_shader_context(bld_base);
3971 struct gallivm_state *gallivm = &ctx->gallivm;
3972 LLVMBuilderRef builder = gallivm->builder;
3973 const struct tgsi_full_instruction * inst = emit_data->inst;
3974 LLVMValueRef data1, data2;
3975 LLVMValueRef rsrc;
3976 LLVMValueRef tmp;
3977
3978 emit_data->dst_type = ctx->f32;
3979
3980 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
3981 data1 = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
3982
3983 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3984 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
3985 data2 = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
3986 }
3987
3988 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3989 * of arguments, which is reversed relative to TGSI (and GLSL)
3990 */
3991 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3992 emit_data->args[emit_data->arg_count++] = data2;
3993 emit_data->args[emit_data->arg_count++] = data1;
3994
3995 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3996 LLVMValueRef offset;
3997
3998 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3999
4000 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
4001 offset = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4002
4003 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
4004 offset, true, false);
4005 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
4006 unsigned target = inst->Memory.Texture;
4007 LLVMValueRef coords;
4008
4009 image_fetch_rsrc(bld_base, &inst->Src[0], true, target, &rsrc);
4010 coords = image_fetch_coords(bld_base, inst, 1);
4011
4012 if (target == TGSI_TEXTURE_BUFFER) {
4013 buffer_append_args(ctx, emit_data, rsrc, coords,
4014 ctx->i32_0, true, false);
4015 } else {
4016 emit_data->args[emit_data->arg_count++] = coords;
4017 emit_data->args[emit_data->arg_count++] = rsrc;
4018
4019 image_append_args(ctx, emit_data, target, true, false);
4020 }
4021 }
4022 }
4023
4024 static void atomic_emit_memory(struct si_shader_context *ctx,
4025 struct lp_build_emit_data *emit_data) {
4026 struct gallivm_state *gallivm = &ctx->gallivm;
4027 LLVMBuilderRef builder = gallivm->builder;
4028 const struct tgsi_full_instruction * inst = emit_data->inst;
4029 LLVMValueRef ptr, result, arg;
4030
4031 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
4032
4033 arg = lp_build_emit_fetch(&ctx->bld_base, inst, 2, 0);
4034 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
4035
4036 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4037 LLVMValueRef new_data;
4038 new_data = lp_build_emit_fetch(&ctx->bld_base,
4039 inst, 3, 0);
4040
4041 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
4042
4043 #if HAVE_LLVM >= 0x309
4044 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
4045 LLVMAtomicOrderingSequentiallyConsistent,
4046 LLVMAtomicOrderingSequentiallyConsistent,
4047 false);
4048 #endif
4049
4050 result = LLVMBuildExtractValue(builder, result, 0, "");
4051 } else {
4052 LLVMAtomicRMWBinOp op;
4053
4054 switch(inst->Instruction.Opcode) {
4055 case TGSI_OPCODE_ATOMUADD:
4056 op = LLVMAtomicRMWBinOpAdd;
4057 break;
4058 case TGSI_OPCODE_ATOMXCHG:
4059 op = LLVMAtomicRMWBinOpXchg;
4060 break;
4061 case TGSI_OPCODE_ATOMAND:
4062 op = LLVMAtomicRMWBinOpAnd;
4063 break;
4064 case TGSI_OPCODE_ATOMOR:
4065 op = LLVMAtomicRMWBinOpOr;
4066 break;
4067 case TGSI_OPCODE_ATOMXOR:
4068 op = LLVMAtomicRMWBinOpXor;
4069 break;
4070 case TGSI_OPCODE_ATOMUMIN:
4071 op = LLVMAtomicRMWBinOpUMin;
4072 break;
4073 case TGSI_OPCODE_ATOMUMAX:
4074 op = LLVMAtomicRMWBinOpUMax;
4075 break;
4076 case TGSI_OPCODE_ATOMIMIN:
4077 op = LLVMAtomicRMWBinOpMin;
4078 break;
4079 case TGSI_OPCODE_ATOMIMAX:
4080 op = LLVMAtomicRMWBinOpMax;
4081 break;
4082 default:
4083 unreachable("unknown atomic opcode");
4084 }
4085
4086 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
4087 LLVMAtomicOrderingSequentiallyConsistent,
4088 false);
4089 }
4090 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
4091 }
4092
4093 static void atomic_emit(
4094 const struct lp_build_tgsi_action *action,
4095 struct lp_build_tgsi_context *bld_base,
4096 struct lp_build_emit_data *emit_data)
4097 {
4098 struct si_shader_context *ctx = si_shader_context(bld_base);
4099 struct gallivm_state *gallivm = &ctx->gallivm;
4100 LLVMBuilderRef builder = gallivm->builder;
4101 const struct tgsi_full_instruction * inst = emit_data->inst;
4102 char intrinsic_name[40];
4103 LLVMValueRef tmp;
4104
4105 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
4106 atomic_emit_memory(ctx, emit_data);
4107 return;
4108 }
4109
4110 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
4111 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4112 snprintf(intrinsic_name, sizeof(intrinsic_name),
4113 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
4114 } else {
4115 LLVMValueRef coords;
4116 char coords_type[8];
4117
4118 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4119 coords = emit_data->args[2];
4120 else
4121 coords = emit_data->args[1];
4122
4123 ac_build_type_name_for_intr(LLVMTypeOf(coords), coords_type, sizeof(coords_type));
4124 snprintf(intrinsic_name, sizeof(intrinsic_name),
4125 "llvm.amdgcn.image.atomic.%s.%s",
4126 action->intr_name, coords_type);
4127 }
4128
4129 tmp = lp_build_intrinsic(
4130 builder, intrinsic_name, ctx->i32,
4131 emit_data->args, emit_data->arg_count, 0);
4132 emit_data->output[emit_data->chan] =
4133 LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4134 }
4135
4136 static void set_tex_fetch_args(struct si_shader_context *ctx,
4137 struct lp_build_emit_data *emit_data,
4138 unsigned target,
4139 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4140 LLVMValueRef *param, unsigned count,
4141 unsigned dmask)
4142 {
4143 struct gallivm_state *gallivm = &ctx->gallivm;
4144 struct ac_image_args args = {};
4145
4146 /* Pad to power of two vector */
4147 while (count < util_next_power_of_two(count))
4148 param[count++] = LLVMGetUndef(ctx->i32);
4149
4150 if (count > 1)
4151 args.addr = lp_build_gather_values(gallivm, param, count);
4152 else
4153 args.addr = param[0];
4154
4155 args.resource = res_ptr;
4156 args.sampler = samp_ptr;
4157 args.dmask = dmask;
4158 args.unorm = target == TGSI_TEXTURE_RECT ||
4159 target == TGSI_TEXTURE_SHADOWRECT;
4160 args.da = tgsi_is_array_sampler(target);
4161
4162 /* Ugly, but we seem to have no other choice right now. */
4163 STATIC_ASSERT(sizeof(args) <= sizeof(emit_data->args));
4164 memcpy(emit_data->args, &args, sizeof(args));
4165 }
4166
4167 static LLVMValueRef fix_resinfo(struct si_shader_context *ctx,
4168 unsigned target, LLVMValueRef out)
4169 {
4170 LLVMBuilderRef builder = ctx->gallivm.builder;
4171
4172 /* 1D textures are allocated and used as 2D on GFX9. */
4173 if (ctx->screen->b.chip_class >= GFX9 &&
4174 (target == TGSI_TEXTURE_1D_ARRAY ||
4175 target == TGSI_TEXTURE_SHADOW1D_ARRAY)) {
4176 LLVMValueRef layers =
4177 LLVMBuildExtractElement(builder, out,
4178 LLVMConstInt(ctx->i32, 2, 0), "");
4179 out = LLVMBuildInsertElement(builder, out, layers,
4180 ctx->i32_1, "");
4181 }
4182
4183 /* Divide the number of layers by 6 to get the number of cubes. */
4184 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4185 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4186 LLVMValueRef imm2 = LLVMConstInt(ctx->i32, 2, 0);
4187
4188 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4189 z = LLVMBuildSDiv(builder, z, LLVMConstInt(ctx->i32, 6, 0), "");
4190
4191 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4192 }
4193 return out;
4194 }
4195
4196 static void resq_fetch_args(
4197 struct lp_build_tgsi_context * bld_base,
4198 struct lp_build_emit_data * emit_data)
4199 {
4200 struct si_shader_context *ctx = si_shader_context(bld_base);
4201 const struct tgsi_full_instruction *inst = emit_data->inst;
4202 const struct tgsi_full_src_register *reg = &inst->Src[0];
4203
4204 emit_data->dst_type = ctx->v4i32;
4205
4206 if (reg->Register.File == TGSI_FILE_BUFFER) {
4207 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4208 emit_data->arg_count = 1;
4209 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4210 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4211 &emit_data->args[0]);
4212 emit_data->arg_count = 1;
4213 } else {
4214 LLVMValueRef res_ptr;
4215 unsigned image_target;
4216
4217 if (inst->Memory.Texture == TGSI_TEXTURE_3D)
4218 image_target = TGSI_TEXTURE_2D_ARRAY;
4219 else
4220 image_target = inst->Memory.Texture;
4221
4222 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4223 &res_ptr);
4224 set_tex_fetch_args(ctx, emit_data, image_target,
4225 res_ptr, NULL, &ctx->i32_0, 1,
4226 0xf);
4227 }
4228 }
4229
4230 static void resq_emit(
4231 const struct lp_build_tgsi_action *action,
4232 struct lp_build_tgsi_context *bld_base,
4233 struct lp_build_emit_data *emit_data)
4234 {
4235 struct si_shader_context *ctx = si_shader_context(bld_base);
4236 struct gallivm_state *gallivm = &ctx->gallivm;
4237 LLVMBuilderRef builder = gallivm->builder;
4238 const struct tgsi_full_instruction *inst = emit_data->inst;
4239 LLVMValueRef out;
4240
4241 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4242 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4243 LLVMConstInt(ctx->i32, 2, 0), "");
4244 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4245 out = get_buffer_size(bld_base, emit_data->args[0]);
4246 } else {
4247 struct ac_image_args args;
4248
4249 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
4250 args.opcode = ac_image_get_resinfo;
4251 out = ac_build_image_opcode(&ctx->ac, &args);
4252
4253 out = fix_resinfo(ctx, inst->Memory.Texture, out);
4254 }
4255
4256 emit_data->output[emit_data->chan] = out;
4257 }
4258
4259 static const struct lp_build_tgsi_action tex_action;
4260
4261 enum desc_type {
4262 DESC_IMAGE,
4263 DESC_BUFFER,
4264 DESC_FMASK,
4265 DESC_SAMPLER,
4266 };
4267
4268 /**
4269 * Load an image view, fmask view. or sampler state descriptor.
4270 */
4271 static LLVMValueRef load_sampler_desc(struct si_shader_context *ctx,
4272 LLVMValueRef list, LLVMValueRef index,
4273 enum desc_type type)
4274 {
4275 struct gallivm_state *gallivm = &ctx->gallivm;
4276 LLVMBuilderRef builder = gallivm->builder;
4277
4278 switch (type) {
4279 case DESC_IMAGE:
4280 /* The image is at [0:7]. */
4281 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4282 break;
4283 case DESC_BUFFER:
4284 /* The buffer is in [4:7]. */
4285 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4286 index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
4287 list = LLVMBuildPointerCast(builder, list,
4288 const_array(ctx->v4i32, 0), "");
4289 break;
4290 case DESC_FMASK:
4291 /* The FMASK is at [8:15]. */
4292 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4293 index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
4294 break;
4295 case DESC_SAMPLER:
4296 /* The sampler state is at [12:15]. */
4297 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4298 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4299 list = LLVMBuildPointerCast(builder, list,
4300 const_array(ctx->v4i32, 0), "");
4301 break;
4302 }
4303
4304 return ac_build_indexed_load_const(&ctx->ac, list, index);
4305 }
4306
4307 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4308 *
4309 * SI-CI:
4310 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4311 * filtering manually. The driver sets img7 to a mask clearing
4312 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4313 * s_and_b32 samp0, samp0, img7
4314 *
4315 * VI:
4316 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4317 */
4318 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4319 LLVMValueRef res, LLVMValueRef samp)
4320 {
4321 LLVMBuilderRef builder = ctx->gallivm.builder;
4322 LLVMValueRef img7, samp0;
4323
4324 if (ctx->screen->b.chip_class >= VI)
4325 return samp;
4326
4327 img7 = LLVMBuildExtractElement(builder, res,
4328 LLVMConstInt(ctx->i32, 7, 0), "");
4329 samp0 = LLVMBuildExtractElement(builder, samp,
4330 ctx->i32_0, "");
4331 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4332 return LLVMBuildInsertElement(builder, samp, samp0,
4333 ctx->i32_0, "");
4334 }
4335
4336 static void tex_fetch_ptrs(
4337 struct lp_build_tgsi_context *bld_base,
4338 struct lp_build_emit_data *emit_data,
4339 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4340 {
4341 struct si_shader_context *ctx = si_shader_context(bld_base);
4342 LLVMValueRef list = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLERS);
4343 const struct tgsi_full_instruction *inst = emit_data->inst;
4344 const struct tgsi_full_src_register *reg;
4345 unsigned target = inst->Texture.Texture;
4346 unsigned sampler_src;
4347 LLVMValueRef index;
4348
4349 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4350 reg = &emit_data->inst->Src[sampler_src];
4351
4352 if (reg->Register.Indirect) {
4353 index = get_bounded_indirect_index(ctx,
4354 &reg->Indirect,
4355 reg->Register.Index,
4356 SI_NUM_SAMPLERS);
4357 } else {
4358 index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
4359 }
4360
4361 if (target == TGSI_TEXTURE_BUFFER)
4362 *res_ptr = load_sampler_desc(ctx, list, index, DESC_BUFFER);
4363 else
4364 *res_ptr = load_sampler_desc(ctx, list, index, DESC_IMAGE);
4365
4366 if (samp_ptr)
4367 *samp_ptr = NULL;
4368 if (fmask_ptr)
4369 *fmask_ptr = NULL;
4370
4371 if (target == TGSI_TEXTURE_2D_MSAA ||
4372 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4373 if (fmask_ptr)
4374 *fmask_ptr = load_sampler_desc(ctx, list, index,
4375 DESC_FMASK);
4376 } else if (target != TGSI_TEXTURE_BUFFER) {
4377 if (samp_ptr) {
4378 *samp_ptr = load_sampler_desc(ctx, list, index,
4379 DESC_SAMPLER);
4380 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4381 }
4382 }
4383 }
4384
4385 static void txq_fetch_args(
4386 struct lp_build_tgsi_context *bld_base,
4387 struct lp_build_emit_data *emit_data)
4388 {
4389 struct si_shader_context *ctx = si_shader_context(bld_base);
4390 const struct tgsi_full_instruction *inst = emit_data->inst;
4391 unsigned target = inst->Texture.Texture;
4392 LLVMValueRef res_ptr;
4393 LLVMValueRef address;
4394
4395 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4396
4397 if (target == TGSI_TEXTURE_BUFFER) {
4398 /* Read the size from the buffer descriptor directly. */
4399 emit_data->args[0] = get_buffer_size(bld_base, res_ptr);
4400 return;
4401 }
4402
4403 /* Textures - set the mip level. */
4404 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4405
4406 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
4407 NULL, &address, 1, 0xf);
4408 }
4409
4410 static void txq_emit(const struct lp_build_tgsi_action *action,
4411 struct lp_build_tgsi_context *bld_base,
4412 struct lp_build_emit_data *emit_data)
4413 {
4414 struct si_shader_context *ctx = si_shader_context(bld_base);
4415 struct ac_image_args args;
4416 unsigned target = emit_data->inst->Texture.Texture;
4417
4418 if (target == TGSI_TEXTURE_BUFFER) {
4419 /* Just return the buffer size. */
4420 emit_data->output[emit_data->chan] = emit_data->args[0];
4421 return;
4422 }
4423
4424 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
4425
4426 args.opcode = ac_image_get_resinfo;
4427 LLVMValueRef result = ac_build_image_opcode(&ctx->ac, &args);
4428
4429 emit_data->output[emit_data->chan] = fix_resinfo(ctx, target, result);
4430 }
4431
4432 static void tex_fetch_args(
4433 struct lp_build_tgsi_context *bld_base,
4434 struct lp_build_emit_data *emit_data)
4435 {
4436 struct si_shader_context *ctx = si_shader_context(bld_base);
4437 struct gallivm_state *gallivm = &ctx->gallivm;
4438 const struct tgsi_full_instruction *inst = emit_data->inst;
4439 unsigned opcode = inst->Instruction.Opcode;
4440 unsigned target = inst->Texture.Texture;
4441 LLVMValueRef coords[5], derivs[6];
4442 LLVMValueRef address[16];
4443 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4444 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4445 unsigned count = 0;
4446 unsigned chan;
4447 unsigned num_deriv_channels = 0;
4448 bool has_offset = inst->Texture.NumOffsets > 0;
4449 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4450 unsigned dmask = 0xf;
4451
4452 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4453
4454 if (target == TGSI_TEXTURE_BUFFER) {
4455 emit_data->dst_type = ctx->v4f32;
4456 emit_data->args[0] = LLVMBuildBitCast(gallivm->builder, res_ptr,
4457 ctx->v16i8, "");
4458 emit_data->args[1] = ctx->i32_0;
4459 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4460 emit_data->arg_count = 3;
4461 return;
4462 }
4463
4464 /* Fetch and project texture coordinates */
4465 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4466 for (chan = 0; chan < 3; chan++ ) {
4467 coords[chan] = lp_build_emit_fetch(bld_base,
4468 emit_data->inst, 0,
4469 chan);
4470 if (opcode == TGSI_OPCODE_TXP)
4471 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4472 TGSI_OPCODE_DIV,
4473 coords[chan],
4474 coords[3]);
4475 }
4476
4477 if (opcode == TGSI_OPCODE_TXP)
4478 coords[3] = bld_base->base.one;
4479
4480 /* Pack offsets. */
4481 if (has_offset &&
4482 opcode != TGSI_OPCODE_TXF &&
4483 opcode != TGSI_OPCODE_TXF_LZ) {
4484 /* The offsets are six-bit signed integers packed like this:
4485 * X=[5:0], Y=[13:8], and Z=[21:16].
4486 */
4487 LLVMValueRef offset[3], pack;
4488
4489 assert(inst->Texture.NumOffsets == 1);
4490
4491 for (chan = 0; chan < 3; chan++) {
4492 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4493 emit_data->inst, 0, chan);
4494 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4495 LLVMConstInt(ctx->i32, 0x3f, 0), "");
4496 if (chan)
4497 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4498 LLVMConstInt(ctx->i32, chan*8, 0), "");
4499 }
4500
4501 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4502 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4503 address[count++] = pack;
4504 }
4505
4506 /* Pack LOD bias value */
4507 if (opcode == TGSI_OPCODE_TXB)
4508 address[count++] = coords[3];
4509 if (opcode == TGSI_OPCODE_TXB2)
4510 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4511
4512 /* Pack depth comparison value */
4513 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4514 LLVMValueRef z;
4515
4516 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4517 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4518 } else {
4519 assert(ref_pos >= 0);
4520 z = coords[ref_pos];
4521 }
4522
4523 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4524 * so the depth comparison value isn't clamped for Z16 and
4525 * Z24 anymore. Do it manually here.
4526 *
4527 * It's unnecessary if the original texture format was
4528 * Z32_FLOAT, but we don't know that here.
4529 */
4530 if (ctx->screen->b.chip_class == VI)
4531 z = ac_build_clamp(&ctx->ac, z);
4532
4533 address[count++] = z;
4534 }
4535
4536 /* Pack user derivatives */
4537 if (opcode == TGSI_OPCODE_TXD) {
4538 int param, num_src_deriv_channels, num_dst_deriv_channels;
4539
4540 switch (target) {
4541 case TGSI_TEXTURE_3D:
4542 num_src_deriv_channels = 3;
4543 num_dst_deriv_channels = 3;
4544 num_deriv_channels = 3;
4545 break;
4546 case TGSI_TEXTURE_2D:
4547 case TGSI_TEXTURE_SHADOW2D:
4548 case TGSI_TEXTURE_RECT:
4549 case TGSI_TEXTURE_SHADOWRECT:
4550 case TGSI_TEXTURE_2D_ARRAY:
4551 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4552 num_src_deriv_channels = 2;
4553 num_dst_deriv_channels = 2;
4554 num_deriv_channels = 2;
4555 break;
4556 case TGSI_TEXTURE_CUBE:
4557 case TGSI_TEXTURE_SHADOWCUBE:
4558 case TGSI_TEXTURE_CUBE_ARRAY:
4559 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4560 /* Cube derivatives will be converted to 2D. */
4561 num_src_deriv_channels = 3;
4562 num_dst_deriv_channels = 3;
4563 num_deriv_channels = 2;
4564 break;
4565 case TGSI_TEXTURE_1D:
4566 case TGSI_TEXTURE_SHADOW1D:
4567 case TGSI_TEXTURE_1D_ARRAY:
4568 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4569 num_src_deriv_channels = 1;
4570
4571 /* 1D textures are allocated and used as 2D on GFX9. */
4572 if (ctx->screen->b.chip_class >= GFX9) {
4573 num_dst_deriv_channels = 2;
4574 num_deriv_channels = 2;
4575 } else {
4576 num_dst_deriv_channels = 1;
4577 num_deriv_channels = 1;
4578 }
4579 break;
4580 default:
4581 unreachable("invalid target");
4582 }
4583
4584 for (param = 0; param < 2; param++) {
4585 for (chan = 0; chan < num_src_deriv_channels; chan++)
4586 derivs[param * num_dst_deriv_channels + chan] =
4587 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4588
4589 /* Fill in the rest with zeros. */
4590 for (chan = num_src_deriv_channels;
4591 chan < num_dst_deriv_channels; chan++)
4592 derivs[param * num_dst_deriv_channels + chan] =
4593 bld_base->base.zero;
4594 }
4595 }
4596
4597 if (target == TGSI_TEXTURE_CUBE ||
4598 target == TGSI_TEXTURE_CUBE_ARRAY ||
4599 target == TGSI_TEXTURE_SHADOWCUBE ||
4600 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4601 ac_prepare_cube_coords(&ctx->ac,
4602 opcode == TGSI_OPCODE_TXD,
4603 target == TGSI_TEXTURE_CUBE_ARRAY ||
4604 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
4605 coords, derivs);
4606
4607 if (opcode == TGSI_OPCODE_TXD)
4608 for (int i = 0; i < num_deriv_channels * 2; i++)
4609 address[count++] = derivs[i];
4610
4611 /* Pack texture coordinates */
4612 address[count++] = coords[0];
4613 if (num_coords > 1)
4614 address[count++] = coords[1];
4615 if (num_coords > 2)
4616 address[count++] = coords[2];
4617
4618 /* 1D textures are allocated and used as 2D on GFX9. */
4619 if (ctx->screen->b.chip_class >= GFX9) {
4620 LLVMValueRef filler;
4621
4622 /* Use 0.5, so that we don't sample the border color. */
4623 if (opcode == TGSI_OPCODE_TXF)
4624 filler = ctx->i32_0;
4625 else
4626 filler = LLVMConstReal(ctx->f32, 0.5);
4627
4628 if (target == TGSI_TEXTURE_1D ||
4629 target == TGSI_TEXTURE_SHADOW1D) {
4630 address[count++] = filler;
4631 } else if (target == TGSI_TEXTURE_1D_ARRAY ||
4632 target == TGSI_TEXTURE_SHADOW1D_ARRAY) {
4633 address[count] = address[count - 1];
4634 address[count - 1] = filler;
4635 count++;
4636 }
4637 }
4638
4639 /* Pack LOD or sample index */
4640 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4641 address[count++] = coords[3];
4642 else if (opcode == TGSI_OPCODE_TXL2)
4643 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4644
4645 if (count > 16) {
4646 assert(!"Cannot handle more than 16 texture address parameters");
4647 count = 16;
4648 }
4649
4650 for (chan = 0; chan < count; chan++ ) {
4651 address[chan] = LLVMBuildBitCast(gallivm->builder,
4652 address[chan], ctx->i32, "");
4653 }
4654
4655 /* Adjust the sample index according to FMASK.
4656 *
4657 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4658 * which is the identity mapping. Each nibble says which physical sample
4659 * should be fetched to get that sample.
4660 *
4661 * For example, 0x11111100 means there are only 2 samples stored and
4662 * the second sample covers 3/4 of the pixel. When reading samples 0
4663 * and 1, return physical sample 0 (determined by the first two 0s
4664 * in FMASK), otherwise return physical sample 1.
4665 *
4666 * The sample index should be adjusted as follows:
4667 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4668 */
4669 if (target == TGSI_TEXTURE_2D_MSAA ||
4670 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4671 struct lp_build_emit_data txf_emit_data = *emit_data;
4672 LLVMValueRef txf_address[4];
4673 /* We only need .xy for non-arrays, and .xyz for arrays. */
4674 unsigned txf_count = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4675 struct tgsi_full_instruction inst = {};
4676
4677 memcpy(txf_address, address, sizeof(txf_address));
4678
4679 /* Read FMASK using TXF_LZ. */
4680 inst.Instruction.Opcode = TGSI_OPCODE_TXF_LZ;
4681 inst.Texture.Texture = target;
4682 txf_emit_data.inst = &inst;
4683 txf_emit_data.chan = 0;
4684 set_tex_fetch_args(ctx, &txf_emit_data,
4685 target, fmask_ptr, NULL,
4686 txf_address, txf_count, 0xf);
4687 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4688
4689 /* Initialize some constants. */
4690 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4691 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4692
4693 /* Apply the formula. */
4694 LLVMValueRef fmask =
4695 LLVMBuildExtractElement(gallivm->builder,
4696 txf_emit_data.output[0],
4697 ctx->i32_0, "");
4698
4699 unsigned sample_chan = txf_count; /* the sample index is last */
4700
4701 LLVMValueRef sample_index4 =
4702 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4703
4704 LLVMValueRef shifted_fmask =
4705 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4706
4707 LLVMValueRef final_sample =
4708 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4709
4710 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4711 * resource descriptor is 0 (invalid),
4712 */
4713 LLVMValueRef fmask_desc =
4714 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4715 ctx->v8i32, "");
4716
4717 LLVMValueRef fmask_word1 =
4718 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4719 ctx->i32_1, "");
4720
4721 LLVMValueRef word1_is_nonzero =
4722 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4723 fmask_word1, ctx->i32_0, "");
4724
4725 /* Replace the MSAA sample index. */
4726 address[sample_chan] =
4727 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4728 final_sample, address[sample_chan], "");
4729 }
4730
4731 if (opcode == TGSI_OPCODE_TXF ||
4732 opcode == TGSI_OPCODE_TXF_LZ) {
4733 /* add tex offsets */
4734 if (inst->Texture.NumOffsets) {
4735 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4736 const struct tgsi_texture_offset *off = inst->TexOffsets;
4737
4738 assert(inst->Texture.NumOffsets == 1);
4739
4740 switch (target) {
4741 case TGSI_TEXTURE_3D:
4742 address[2] = lp_build_add(uint_bld, address[2],
4743 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ]);
4744 /* fall through */
4745 case TGSI_TEXTURE_2D:
4746 case TGSI_TEXTURE_SHADOW2D:
4747 case TGSI_TEXTURE_RECT:
4748 case TGSI_TEXTURE_SHADOWRECT:
4749 case TGSI_TEXTURE_2D_ARRAY:
4750 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4751 address[1] =
4752 lp_build_add(uint_bld, address[1],
4753 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY]);
4754 /* fall through */
4755 case TGSI_TEXTURE_1D:
4756 case TGSI_TEXTURE_SHADOW1D:
4757 case TGSI_TEXTURE_1D_ARRAY:
4758 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4759 address[0] =
4760 lp_build_add(uint_bld, address[0],
4761 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX]);
4762 break;
4763 /* texture offsets do not apply to other texture targets */
4764 }
4765 }
4766 }
4767
4768 if (opcode == TGSI_OPCODE_TG4) {
4769 unsigned gather_comp = 0;
4770
4771 /* DMASK was repurposed for GATHER4. 4 components are always
4772 * returned and DMASK works like a swizzle - it selects
4773 * the component to fetch. The only valid DMASK values are
4774 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4775 * (red,red,red,red) etc.) The ISA document doesn't mention
4776 * this.
4777 */
4778
4779 /* Get the component index from src1.x for Gather4. */
4780 if (!tgsi_is_shadow_target(target)) {
4781 LLVMValueRef comp_imm;
4782 struct tgsi_src_register src1 = inst->Src[1].Register;
4783
4784 assert(src1.File == TGSI_FILE_IMMEDIATE);
4785
4786 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX];
4787 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4788 gather_comp = CLAMP(gather_comp, 0, 3);
4789 }
4790
4791 dmask = 1 << gather_comp;
4792 }
4793
4794 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
4795 samp_ptr, address, count, dmask);
4796 }
4797
4798 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
4799 * incorrectly forces nearest filtering if the texture format is integer.
4800 * The only effect it has on Gather4, which always returns 4 texels for
4801 * bilinear filtering, is that the final coordinates are off by 0.5 of
4802 * the texel size.
4803 *
4804 * The workaround is to subtract 0.5 from the unnormalized coordinates,
4805 * or (0.5 / size) from the normalized coordinates.
4806 */
4807 static void si_lower_gather4_integer(struct si_shader_context *ctx,
4808 struct ac_image_args *args,
4809 unsigned target)
4810 {
4811 LLVMBuilderRef builder = ctx->gallivm.builder;
4812 LLVMValueRef coord = args->addr;
4813 LLVMValueRef half_texel[2];
4814 /* Texture coordinates start after:
4815 * {offset, bias, z-compare, derivatives}
4816 * Only the offset and z-compare can occur here.
4817 */
4818 unsigned coord_vgpr_index = (int)args->offset + (int)args->compare;
4819 int c;
4820
4821 if (target == TGSI_TEXTURE_RECT ||
4822 target == TGSI_TEXTURE_SHADOWRECT) {
4823 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
4824 } else {
4825 struct tgsi_full_instruction txq_inst = {};
4826 struct lp_build_emit_data txq_emit_data = {};
4827
4828 /* Query the texture size. */
4829 txq_inst.Texture.Texture = target;
4830 txq_emit_data.inst = &txq_inst;
4831 txq_emit_data.dst_type = ctx->v4i32;
4832 set_tex_fetch_args(ctx, &txq_emit_data, target,
4833 args->resource, NULL, &ctx->i32_0,
4834 1, 0xf);
4835 txq_emit(NULL, &ctx->bld_base, &txq_emit_data);
4836
4837 /* Compute -0.5 / size. */
4838 for (c = 0; c < 2; c++) {
4839 half_texel[c] =
4840 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
4841 LLVMConstInt(ctx->i32, c, 0), "");
4842 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
4843 half_texel[c] =
4844 lp_build_emit_llvm_unary(&ctx->bld_base,
4845 TGSI_OPCODE_RCP, half_texel[c]);
4846 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
4847 LLVMConstReal(ctx->f32, -0.5), "");
4848 }
4849 }
4850
4851 for (c = 0; c < 2; c++) {
4852 LLVMValueRef tmp;
4853 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
4854
4855 tmp = LLVMBuildExtractElement(builder, coord, index, "");
4856 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4857 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
4858 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4859 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
4860 }
4861
4862 args->addr = coord;
4863 }
4864
4865 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4866 struct lp_build_tgsi_context *bld_base,
4867 struct lp_build_emit_data *emit_data)
4868 {
4869 struct si_shader_context *ctx = si_shader_context(bld_base);
4870 const struct tgsi_full_instruction *inst = emit_data->inst;
4871 struct ac_image_args args;
4872 unsigned opcode = inst->Instruction.Opcode;
4873 unsigned target = inst->Texture.Texture;
4874
4875 if (target == TGSI_TEXTURE_BUFFER) {
4876 emit_data->output[emit_data->chan] =
4877 ac_build_buffer_load_format(&ctx->ac,
4878 emit_data->args[0],
4879 emit_data->args[2],
4880 emit_data->args[1],
4881 true);
4882 return;
4883 }
4884
4885 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
4886
4887 args.opcode = ac_image_sample;
4888 args.compare = tgsi_is_shadow_target(target);
4889 args.offset = inst->Texture.NumOffsets > 0;
4890
4891 switch (opcode) {
4892 case TGSI_OPCODE_TXF:
4893 case TGSI_OPCODE_TXF_LZ:
4894 args.opcode = opcode == TGSI_OPCODE_TXF_LZ ||
4895 target == TGSI_TEXTURE_2D_MSAA ||
4896 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4897 ac_image_load : ac_image_load_mip;
4898 args.compare = false;
4899 args.offset = false;
4900 break;
4901 case TGSI_OPCODE_LODQ:
4902 args.opcode = ac_image_get_lod;
4903 args.compare = false;
4904 args.offset = false;
4905 break;
4906 case TGSI_OPCODE_TEX:
4907 case TGSI_OPCODE_TEX2:
4908 case TGSI_OPCODE_TXP:
4909 if (ctx->type != PIPE_SHADER_FRAGMENT)
4910 args.level_zero = true;
4911 break;
4912 case TGSI_OPCODE_TEX_LZ:
4913 args.level_zero = true;
4914 break;
4915 case TGSI_OPCODE_TXB:
4916 case TGSI_OPCODE_TXB2:
4917 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4918 args.bias = true;
4919 break;
4920 case TGSI_OPCODE_TXL:
4921 case TGSI_OPCODE_TXL2:
4922 args.lod = true;
4923 break;
4924 case TGSI_OPCODE_TXD:
4925 args.deriv = true;
4926 break;
4927 case TGSI_OPCODE_TG4:
4928 args.opcode = ac_image_gather4;
4929 args.level_zero = true;
4930 break;
4931 default:
4932 assert(0);
4933 return;
4934 }
4935
4936 /* The hardware needs special lowering for Gather4 with integer formats. */
4937 if (ctx->screen->b.chip_class <= VI &&
4938 opcode == TGSI_OPCODE_TG4) {
4939 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4940 /* This will also work with non-constant indexing because of how
4941 * glsl_to_tgsi works and we intent to preserve that behavior.
4942 */
4943 const unsigned src_idx = 2;
4944 unsigned sampler = inst->Src[src_idx].Register.Index;
4945
4946 assert(inst->Src[src_idx].Register.File == TGSI_FILE_SAMPLER);
4947
4948 if (info->sampler_type[sampler] == TGSI_RETURN_TYPE_SINT ||
4949 info->sampler_type[sampler] == TGSI_RETURN_TYPE_UINT)
4950 si_lower_gather4_integer(ctx, &args, target);
4951 }
4952
4953 emit_data->output[emit_data->chan] =
4954 ac_build_image_opcode(&ctx->ac, &args);
4955 }
4956
4957 static void si_llvm_emit_txqs(
4958 const struct lp_build_tgsi_action *action,
4959 struct lp_build_tgsi_context *bld_base,
4960 struct lp_build_emit_data *emit_data)
4961 {
4962 struct si_shader_context *ctx = si_shader_context(bld_base);
4963 struct gallivm_state *gallivm = &ctx->gallivm;
4964 LLVMBuilderRef builder = gallivm->builder;
4965 LLVMValueRef res, samples;
4966 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4967
4968 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4969
4970
4971 /* Read the samples from the descriptor directly. */
4972 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4973 samples = LLVMBuildExtractElement(
4974 builder, res,
4975 LLVMConstInt(ctx->i32, 3, 0), "");
4976 samples = LLVMBuildLShr(builder, samples,
4977 LLVMConstInt(ctx->i32, 16, 0), "");
4978 samples = LLVMBuildAnd(builder, samples,
4979 LLVMConstInt(ctx->i32, 0xf, 0), "");
4980 samples = LLVMBuildShl(builder, ctx->i32_1,
4981 samples, "");
4982
4983 emit_data->output[emit_data->chan] = samples;
4984 }
4985
4986 static void si_llvm_emit_ddxy(
4987 const struct lp_build_tgsi_action *action,
4988 struct lp_build_tgsi_context *bld_base,
4989 struct lp_build_emit_data *emit_data)
4990 {
4991 struct si_shader_context *ctx = si_shader_context(bld_base);
4992 struct gallivm_state *gallivm = &ctx->gallivm;
4993 unsigned opcode = emit_data->info->opcode;
4994 LLVMValueRef val;
4995 int idx;
4996 unsigned mask;
4997
4998 if (opcode == TGSI_OPCODE_DDX_FINE)
4999 mask = AC_TID_MASK_LEFT;
5000 else if (opcode == TGSI_OPCODE_DDY_FINE)
5001 mask = AC_TID_MASK_TOP;
5002 else
5003 mask = AC_TID_MASK_TOP_LEFT;
5004
5005 /* for DDX we want to next X pixel, DDY next Y pixel. */
5006 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
5007
5008 val = LLVMBuildBitCast(gallivm->builder, emit_data->args[0], ctx->i32, "");
5009 val = ac_build_ddxy(&ctx->ac, ctx->screen->has_ds_bpermute,
5010 mask, idx, ctx->lds, val);
5011 emit_data->output[emit_data->chan] = val;
5012 }
5013
5014 /*
5015 * this takes an I,J coordinate pair,
5016 * and works out the X and Y derivatives.
5017 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
5018 */
5019 static LLVMValueRef si_llvm_emit_ddxy_interp(
5020 struct lp_build_tgsi_context *bld_base,
5021 LLVMValueRef interp_ij)
5022 {
5023 struct si_shader_context *ctx = si_shader_context(bld_base);
5024 struct gallivm_state *gallivm = &ctx->gallivm;
5025 LLVMValueRef result[4], a;
5026 unsigned i;
5027
5028 for (i = 0; i < 2; i++) {
5029 a = LLVMBuildExtractElement(gallivm->builder, interp_ij,
5030 LLVMConstInt(ctx->i32, i, 0), "");
5031 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
5032 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
5033 }
5034
5035 return lp_build_gather_values(gallivm, result, 4);
5036 }
5037
5038 static void interp_fetch_args(
5039 struct lp_build_tgsi_context *bld_base,
5040 struct lp_build_emit_data *emit_data)
5041 {
5042 struct si_shader_context *ctx = si_shader_context(bld_base);
5043 struct gallivm_state *gallivm = &ctx->gallivm;
5044 const struct tgsi_full_instruction *inst = emit_data->inst;
5045
5046 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
5047 /* offset is in second src, first two channels */
5048 emit_data->args[0] = lp_build_emit_fetch(bld_base,
5049 emit_data->inst, 1,
5050 TGSI_CHAN_X);
5051 emit_data->args[1] = lp_build_emit_fetch(bld_base,
5052 emit_data->inst, 1,
5053 TGSI_CHAN_Y);
5054 emit_data->arg_count = 2;
5055 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5056 LLVMValueRef sample_position;
5057 LLVMValueRef sample_id;
5058 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
5059
5060 /* fetch sample ID, then fetch its sample position,
5061 * and place into first two channels.
5062 */
5063 sample_id = lp_build_emit_fetch(bld_base,
5064 emit_data->inst, 1, TGSI_CHAN_X);
5065 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
5066 ctx->i32, "");
5067 sample_position = load_sample_position(ctx, sample_id);
5068
5069 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
5070 sample_position,
5071 ctx->i32_0, "");
5072
5073 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
5074 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
5075 sample_position,
5076 ctx->i32_1, "");
5077 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
5078 emit_data->arg_count = 2;
5079 }
5080 }
5081
5082 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
5083 struct lp_build_tgsi_context *bld_base,
5084 struct lp_build_emit_data *emit_data)
5085 {
5086 struct si_shader_context *ctx = si_shader_context(bld_base);
5087 struct si_shader *shader = ctx->shader;
5088 struct gallivm_state *gallivm = &ctx->gallivm;
5089 LLVMValueRef interp_param;
5090 const struct tgsi_full_instruction *inst = emit_data->inst;
5091 int input_index = inst->Src[0].Register.Index;
5092 int chan;
5093 int i;
5094 LLVMValueRef attr_number;
5095 LLVMValueRef params = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
5096 int interp_param_idx;
5097 unsigned interp = shader->selector->info.input_interpolate[input_index];
5098 unsigned location;
5099
5100 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5101
5102 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5103 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
5104 location = TGSI_INTERPOLATE_LOC_CENTER;
5105 else
5106 location = TGSI_INTERPOLATE_LOC_CENTROID;
5107
5108 interp_param_idx = lookup_interp_param_index(interp, location);
5109 if (interp_param_idx == -1)
5110 return;
5111 else if (interp_param_idx)
5112 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
5113 else
5114 interp_param = NULL;
5115
5116 attr_number = LLVMConstInt(ctx->i32, input_index, 0);
5117
5118 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5119 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5120 LLVMValueRef ij_out[2];
5121 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
5122
5123 /*
5124 * take the I then J parameters, and the DDX/Y for it, and
5125 * calculate the IJ inputs for the interpolator.
5126 * temp1 = ddx * offset/sample.x + I;
5127 * interp_param.I = ddy * offset/sample.y + temp1;
5128 * temp1 = ddx * offset/sample.x + J;
5129 * interp_param.J = ddy * offset/sample.y + temp1;
5130 */
5131 for (i = 0; i < 2; i++) {
5132 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
5133 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
5134 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
5135 ddxy_out, ix_ll, "");
5136 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
5137 ddxy_out, iy_ll, "");
5138 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5139 interp_param, ix_ll, "");
5140 LLVMValueRef temp1, temp2;
5141
5142 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5143 ctx->f32, "");
5144
5145 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5146
5147 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5148
5149 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5150
5151 ij_out[i] = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5152 }
5153 interp_param = lp_build_gather_values(gallivm, ij_out, 2);
5154 }
5155
5156 for (chan = 0; chan < 4; chan++) {
5157 LLVMValueRef llvm_chan;
5158 unsigned schan;
5159
5160 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5161 llvm_chan = LLVMConstInt(ctx->i32, schan, 0);
5162
5163 if (interp_param) {
5164 interp_param = LLVMBuildBitCast(gallivm->builder,
5165 interp_param, LLVMVectorType(ctx->f32, 2), "");
5166 LLVMValueRef i = LLVMBuildExtractElement(
5167 gallivm->builder, interp_param, ctx->i32_0, "");
5168 LLVMValueRef j = LLVMBuildExtractElement(
5169 gallivm->builder, interp_param, ctx->i32_1, "");
5170 emit_data->output[chan] = ac_build_fs_interp(&ctx->ac,
5171 llvm_chan, attr_number, params,
5172 i, j);
5173 } else {
5174 emit_data->output[chan] = ac_build_fs_interp_mov(&ctx->ac,
5175 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
5176 llvm_chan, attr_number, params);
5177 }
5178 }
5179 }
5180
5181 static LLVMValueRef si_emit_ballot(struct si_shader_context *ctx,
5182 LLVMValueRef value)
5183 {
5184 struct gallivm_state *gallivm = &ctx->gallivm;
5185 LLVMValueRef args[3] = {
5186 value,
5187 ctx->i32_0,
5188 LLVMConstInt(ctx->i32, LLVMIntNE, 0)
5189 };
5190
5191 /* We currently have no other way to prevent LLVM from lifting the icmp
5192 * calls to a dominating basic block.
5193 */
5194 emit_optimization_barrier(ctx, &args[0]);
5195
5196 if (LLVMTypeOf(args[0]) != ctx->i32)
5197 args[0] = LLVMBuildBitCast(gallivm->builder, args[0], ctx->i32, "");
5198
5199 return lp_build_intrinsic(gallivm->builder,
5200 "llvm.amdgcn.icmp.i32",
5201 ctx->i64, args, 3,
5202 LP_FUNC_ATTR_NOUNWIND |
5203 LP_FUNC_ATTR_READNONE |
5204 LP_FUNC_ATTR_CONVERGENT);
5205 }
5206
5207 static void vote_all_emit(
5208 const struct lp_build_tgsi_action *action,
5209 struct lp_build_tgsi_context *bld_base,
5210 struct lp_build_emit_data *emit_data)
5211 {
5212 struct si_shader_context *ctx = si_shader_context(bld_base);
5213 struct gallivm_state *gallivm = &ctx->gallivm;
5214 LLVMValueRef active_set, vote_set;
5215 LLVMValueRef tmp;
5216
5217 active_set = si_emit_ballot(ctx, ctx->i32_1);
5218 vote_set = si_emit_ballot(ctx, emit_data->args[0]);
5219
5220 tmp = LLVMBuildICmp(gallivm->builder, LLVMIntEQ, vote_set, active_set, "");
5221 emit_data->output[emit_data->chan] =
5222 LLVMBuildSExt(gallivm->builder, tmp, ctx->i32, "");
5223 }
5224
5225 static void vote_any_emit(
5226 const struct lp_build_tgsi_action *action,
5227 struct lp_build_tgsi_context *bld_base,
5228 struct lp_build_emit_data *emit_data)
5229 {
5230 struct si_shader_context *ctx = si_shader_context(bld_base);
5231 struct gallivm_state *gallivm = &ctx->gallivm;
5232 LLVMValueRef vote_set;
5233 LLVMValueRef tmp;
5234
5235 vote_set = si_emit_ballot(ctx, emit_data->args[0]);
5236
5237 tmp = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
5238 vote_set, LLVMConstInt(ctx->i64, 0, 0), "");
5239 emit_data->output[emit_data->chan] =
5240 LLVMBuildSExt(gallivm->builder, tmp, ctx->i32, "");
5241 }
5242
5243 static void vote_eq_emit(
5244 const struct lp_build_tgsi_action *action,
5245 struct lp_build_tgsi_context *bld_base,
5246 struct lp_build_emit_data *emit_data)
5247 {
5248 struct si_shader_context *ctx = si_shader_context(bld_base);
5249 struct gallivm_state *gallivm = &ctx->gallivm;
5250 LLVMValueRef active_set, vote_set;
5251 LLVMValueRef all, none, tmp;
5252
5253 active_set = si_emit_ballot(ctx, ctx->i32_1);
5254 vote_set = si_emit_ballot(ctx, emit_data->args[0]);
5255
5256 all = LLVMBuildICmp(gallivm->builder, LLVMIntEQ, vote_set, active_set, "");
5257 none = LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
5258 vote_set, LLVMConstInt(ctx->i64, 0, 0), "");
5259 tmp = LLVMBuildOr(gallivm->builder, all, none, "");
5260 emit_data->output[emit_data->chan] =
5261 LLVMBuildSExt(gallivm->builder, tmp, ctx->i32, "");
5262 }
5263
5264 static void ballot_emit(
5265 const struct lp_build_tgsi_action *action,
5266 struct lp_build_tgsi_context *bld_base,
5267 struct lp_build_emit_data *emit_data)
5268 {
5269 struct si_shader_context *ctx = si_shader_context(bld_base);
5270 LLVMBuilderRef builder = ctx->gallivm.builder;
5271 LLVMValueRef tmp;
5272
5273 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
5274 tmp = si_emit_ballot(ctx, tmp);
5275 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
5276
5277 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
5278 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
5279 }
5280
5281 static void read_invoc_fetch_args(
5282 struct lp_build_tgsi_context *bld_base,
5283 struct lp_build_emit_data *emit_data)
5284 {
5285 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
5286 0, emit_data->src_chan);
5287
5288 /* Always read the source invocation (= lane) from the X channel. */
5289 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
5290 1, TGSI_CHAN_X);
5291 emit_data->arg_count = 2;
5292 }
5293
5294 static void read_lane_emit(
5295 const struct lp_build_tgsi_action *action,
5296 struct lp_build_tgsi_context *bld_base,
5297 struct lp_build_emit_data *emit_data)
5298 {
5299 struct si_shader_context *ctx = si_shader_context(bld_base);
5300 LLVMBuilderRef builder = ctx->gallivm.builder;
5301
5302 /* We currently have no other way to prevent LLVM from lifting the icmp
5303 * calls to a dominating basic block.
5304 */
5305 emit_optimization_barrier(ctx, &emit_data->args[0]);
5306
5307 for (unsigned i = 0; i < emit_data->arg_count; ++i) {
5308 emit_data->args[i] = LLVMBuildBitCast(builder, emit_data->args[i],
5309 ctx->i32, "");
5310 }
5311
5312 emit_data->output[emit_data->chan] =
5313 ac_build_intrinsic(&ctx->ac, action->intr_name,
5314 ctx->i32, emit_data->args, emit_data->arg_count,
5315 AC_FUNC_ATTR_READNONE |
5316 AC_FUNC_ATTR_CONVERGENT);
5317 }
5318
5319 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5320 struct lp_build_emit_data *emit_data)
5321 {
5322 struct si_shader_context *ctx = si_shader_context(bld_base);
5323 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5324 LLVMValueRef imm;
5325 unsigned stream;
5326
5327 assert(src0.File == TGSI_FILE_IMMEDIATE);
5328
5329 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
5330 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
5331 return stream;
5332 }
5333
5334 /* Emit one vertex from the geometry shader */
5335 static void si_llvm_emit_vertex(
5336 const struct lp_build_tgsi_action *action,
5337 struct lp_build_tgsi_context *bld_base,
5338 struct lp_build_emit_data *emit_data)
5339 {
5340 struct si_shader_context *ctx = si_shader_context(bld_base);
5341 struct lp_build_context *uint = &bld_base->uint_bld;
5342 struct si_shader *shader = ctx->shader;
5343 struct tgsi_shader_info *info = &shader->selector->info;
5344 struct gallivm_state *gallivm = &ctx->gallivm;
5345 struct lp_build_if_state if_state;
5346 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
5347 SI_PARAM_GS2VS_OFFSET);
5348 LLVMValueRef gs_next_vertex;
5349 LLVMValueRef can_emit, kill;
5350 unsigned chan, offset;
5351 int i;
5352 unsigned stream;
5353
5354 stream = si_llvm_get_stream(bld_base, emit_data);
5355
5356 /* Write vertex attribute values to GSVS ring */
5357 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5358 ctx->gs_next_vertex[stream],
5359 "");
5360
5361 /* If this thread has already emitted the declared maximum number of
5362 * vertices, skip the write: excessive vertex emissions are not
5363 * supposed to have any effect.
5364 *
5365 * If the shader has no writes to memory, kill it instead. This skips
5366 * further memory loads and may allow LLVM to skip to the end
5367 * altogether.
5368 */
5369 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULT, gs_next_vertex,
5370 LLVMConstInt(ctx->i32,
5371 shader->selector->gs_max_out_vertices, 0), "");
5372
5373 bool use_kill = !info->writes_memory;
5374 if (use_kill) {
5375 kill = lp_build_select(&bld_base->base, can_emit,
5376 LLVMConstReal(ctx->f32, 1.0f),
5377 LLVMConstReal(ctx->f32, -1.0f));
5378
5379 ac_build_kill(&ctx->ac, kill);
5380 } else {
5381 lp_build_if(&if_state, gallivm, can_emit);
5382 }
5383
5384 offset = 0;
5385 for (i = 0; i < info->num_outputs; i++) {
5386 LLVMValueRef *out_ptr = ctx->outputs[i];
5387
5388 for (chan = 0; chan < 4; chan++) {
5389 if (!(info->output_usagemask[i] & (1 << chan)) ||
5390 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
5391 continue;
5392
5393 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5394 LLVMValueRef voffset =
5395 LLVMConstInt(ctx->i32, offset *
5396 shader->selector->gs_max_out_vertices, 0);
5397 offset++;
5398
5399 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5400 voffset = lp_build_mul_imm(uint, voffset, 4);
5401
5402 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5403
5404 ac_build_buffer_store_dword(&ctx->ac,
5405 ctx->gsvs_ring[stream],
5406 out_val, 1,
5407 voffset, soffset, 0,
5408 1, 1, true, true);
5409 }
5410 }
5411
5412 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5413 ctx->i32_1);
5414
5415 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5416
5417 /* Signal vertex emission */
5418 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
5419 LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID));
5420 if (!use_kill)
5421 lp_build_endif(&if_state);
5422 }
5423
5424 /* Cut one primitive from the geometry shader */
5425 static void si_llvm_emit_primitive(
5426 const struct lp_build_tgsi_action *action,
5427 struct lp_build_tgsi_context *bld_base,
5428 struct lp_build_emit_data *emit_data)
5429 {
5430 struct si_shader_context *ctx = si_shader_context(bld_base);
5431 unsigned stream;
5432
5433 /* Signal primitive cut */
5434 stream = si_llvm_get_stream(bld_base, emit_data);
5435 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
5436 LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID));
5437 }
5438
5439 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5440 struct lp_build_tgsi_context *bld_base,
5441 struct lp_build_emit_data *emit_data)
5442 {
5443 struct si_shader_context *ctx = si_shader_context(bld_base);
5444 struct gallivm_state *gallivm = &ctx->gallivm;
5445
5446 /* SI only (thanks to a hw bug workaround):
5447 * The real barrier instruction isn’t needed, because an entire patch
5448 * always fits into a single wave.
5449 */
5450 if (HAVE_LLVM >= 0x0309 &&
5451 ctx->screen->b.chip_class == SI &&
5452 ctx->type == PIPE_SHADER_TESS_CTRL) {
5453 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
5454 return;
5455 }
5456
5457 lp_build_intrinsic(gallivm->builder,
5458 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5459 : "llvm.AMDGPU.barrier.local",
5460 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
5461 }
5462
5463 static const struct lp_build_tgsi_action tex_action = {
5464 .fetch_args = tex_fetch_args,
5465 .emit = build_tex_intrinsic,
5466 };
5467
5468 static const struct lp_build_tgsi_action interp_action = {
5469 .fetch_args = interp_fetch_args,
5470 .emit = build_interp_intrinsic,
5471 };
5472
5473 static void si_create_function(struct si_shader_context *ctx,
5474 const char *name,
5475 LLVMTypeRef *returns, unsigned num_returns,
5476 LLVMTypeRef *params, unsigned num_params,
5477 int last_sgpr)
5478 {
5479 int i;
5480
5481 si_llvm_create_func(ctx, name, returns, num_returns,
5482 params, num_params);
5483 si_llvm_shader_type(ctx->main_fn, ctx->type);
5484 ctx->return_value = LLVMGetUndef(ctx->return_type);
5485
5486 for (i = 0; i <= last_sgpr; ++i) {
5487 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
5488
5489 /* The combination of:
5490 * - ByVal
5491 * - dereferenceable
5492 * - invariant.load
5493 * allows the optimization passes to move loads and reduces
5494 * SGPR spilling significantly.
5495 */
5496 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
5497 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
5498 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
5499 ac_add_attr_dereferenceable(P, UINT64_MAX);
5500 } else
5501 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
5502 }
5503
5504 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5505 "no-signed-zeros-fp-math",
5506 "true");
5507
5508 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5509 /* These were copied from some LLVM test. */
5510 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5511 "less-precise-fpmad",
5512 "true");
5513 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5514 "no-infs-fp-math",
5515 "true");
5516 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5517 "no-nans-fp-math",
5518 "true");
5519 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5520 "unsafe-fp-math",
5521 "true");
5522 }
5523 }
5524
5525 static void declare_streamout_params(struct si_shader_context *ctx,
5526 struct pipe_stream_output_info *so,
5527 LLVMTypeRef *params, LLVMTypeRef i32,
5528 unsigned *num_params)
5529 {
5530 int i;
5531
5532 /* Streamout SGPRs. */
5533 if (so->num_outputs) {
5534 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5535 params[ctx->param_streamout_config = (*num_params)++] = i32;
5536 else
5537 ctx->param_streamout_config = *num_params - 1;
5538
5539 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5540 }
5541 /* A streamout buffer offset is loaded if the stride is non-zero. */
5542 for (i = 0; i < 4; i++) {
5543 if (!so->stride[i])
5544 continue;
5545
5546 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5547 }
5548 }
5549
5550 static unsigned llvm_get_type_size(LLVMTypeRef type)
5551 {
5552 LLVMTypeKind kind = LLVMGetTypeKind(type);
5553
5554 switch (kind) {
5555 case LLVMIntegerTypeKind:
5556 return LLVMGetIntTypeWidth(type) / 8;
5557 case LLVMFloatTypeKind:
5558 return 4;
5559 case LLVMPointerTypeKind:
5560 return 8;
5561 case LLVMVectorTypeKind:
5562 return LLVMGetVectorSize(type) *
5563 llvm_get_type_size(LLVMGetElementType(type));
5564 case LLVMArrayTypeKind:
5565 return LLVMGetArrayLength(type) *
5566 llvm_get_type_size(LLVMGetElementType(type));
5567 default:
5568 assert(0);
5569 return 0;
5570 }
5571 }
5572
5573 static void declare_tess_lds(struct si_shader_context *ctx)
5574 {
5575 struct gallivm_state *gallivm = &ctx->gallivm;
5576
5577 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5578 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, ctx->i32_0,
5579 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
5580 "tess_lds");
5581 }
5582
5583 static unsigned si_get_max_workgroup_size(struct si_shader *shader)
5584 {
5585 const unsigned *properties = shader->selector->info.properties;
5586 unsigned max_work_group_size =
5587 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5588 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5589 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5590
5591 if (!max_work_group_size) {
5592 /* This is a variable group size compute shader,
5593 * compile it for the maximum possible group size.
5594 */
5595 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
5596 }
5597 return max_work_group_size;
5598 }
5599
5600 static void create_function(struct si_shader_context *ctx)
5601 {
5602 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5603 struct gallivm_state *gallivm = &ctx->gallivm;
5604 struct si_shader *shader = ctx->shader;
5605 LLVMTypeRef params[SI_NUM_PARAMS + SI_MAX_ATTRIBS], v3i32;
5606 LLVMTypeRef returns[16+32*4];
5607 unsigned i, last_sgpr, num_params, num_return_sgprs;
5608 unsigned num_returns = 0;
5609 unsigned num_prolog_vgprs = 0;
5610
5611 v3i32 = LLVMVectorType(ctx->i32, 3);
5612
5613 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5614 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5615 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5616 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5617 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5618
5619 switch (ctx->type) {
5620 case PIPE_SHADER_VERTEX:
5621 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_MAX_ATTRIBS);
5622 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5623 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5624 params[SI_PARAM_DRAWID] = ctx->i32;
5625 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5626 num_params = SI_PARAM_VS_STATE_BITS+1;
5627
5628 if (shader->key.as_es) {
5629 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5630 } else if (shader->key.as_ls) {
5631 /* no extra parameters */
5632 } else {
5633 if (shader->is_gs_copy_shader) {
5634 num_params = SI_PARAM_RW_BUFFERS+1;
5635 }
5636
5637 /* The locations of the other parameters are assigned dynamically. */
5638 declare_streamout_params(ctx, &shader->selector->so,
5639 params, ctx->i32, &num_params);
5640 }
5641
5642 last_sgpr = num_params-1;
5643
5644 /* VGPRs */
5645 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5646 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5647 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5648 params[ctx->param_instance_id = num_params++] = ctx->i32;
5649
5650 if (!shader->is_gs_copy_shader) {
5651 /* Vertex load indices. */
5652 ctx->param_vertex_index0 = num_params;
5653
5654 for (i = 0; i < shader->selector->info.num_inputs; i++)
5655 params[num_params++] = ctx->i32;
5656
5657 num_prolog_vgprs += shader->selector->info.num_inputs;
5658
5659 /* PrimitiveID output. */
5660 if (!shader->key.as_es && !shader->key.as_ls)
5661 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5662 returns[num_returns++] = ctx->f32;
5663 }
5664 break;
5665
5666 case PIPE_SHADER_TESS_CTRL:
5667 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5668 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5669 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5670 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5671 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5672 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5673 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5674
5675 /* VGPRs */
5676 params[SI_PARAM_PATCH_ID] = ctx->i32;
5677 params[SI_PARAM_REL_IDS] = ctx->i32;
5678 num_params = SI_PARAM_REL_IDS+1;
5679
5680 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5681 * placed after the user SGPRs.
5682 */
5683 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5684 returns[num_returns++] = ctx->i32; /* SGPRs */
5685
5686 for (i = 0; i < 3; i++)
5687 returns[num_returns++] = ctx->f32; /* VGPRs */
5688 break;
5689
5690 case PIPE_SHADER_TESS_EVAL:
5691 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5692 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5693
5694 if (shader->key.as_es) {
5695 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5696 params[num_params++] = ctx->i32;
5697 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5698 } else {
5699 params[num_params++] = ctx->i32;
5700 declare_streamout_params(ctx, &shader->selector->so,
5701 params, ctx->i32, &num_params);
5702 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5703 }
5704 last_sgpr = num_params - 1;
5705
5706 /* VGPRs */
5707 params[ctx->param_tes_u = num_params++] = ctx->f32;
5708 params[ctx->param_tes_v = num_params++] = ctx->f32;
5709 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5710 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5711
5712 /* PrimitiveID output. */
5713 if (!shader->key.as_es)
5714 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5715 returns[num_returns++] = ctx->f32;
5716 break;
5717
5718 case PIPE_SHADER_GEOMETRY:
5719 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5720 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5721 last_sgpr = SI_PARAM_GS_WAVE_ID;
5722
5723 /* VGPRs */
5724 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5725 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5726 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5727 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5728 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5729 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5730 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5731 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5732 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5733 break;
5734
5735 case PIPE_SHADER_FRAGMENT:
5736 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5737 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5738 last_sgpr = SI_PARAM_PRIM_MASK;
5739 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5740 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5741 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5742 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5743 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5744 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5745 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5746 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5747 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5748 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5749 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5750 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5751 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5752 shader->info.face_vgpr_index = 20;
5753 params[SI_PARAM_ANCILLARY] = ctx->i32;
5754 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5755 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5756 num_params = SI_PARAM_POS_FIXED_PT+1;
5757
5758 /* Color inputs from the prolog. */
5759 if (shader->selector->info.colors_read) {
5760 unsigned num_color_elements =
5761 util_bitcount(shader->selector->info.colors_read);
5762
5763 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5764 for (i = 0; i < num_color_elements; i++)
5765 params[num_params++] = ctx->f32;
5766
5767 num_prolog_vgprs += num_color_elements;
5768 }
5769
5770 /* Outputs for the epilog. */
5771 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5772 num_returns =
5773 num_return_sgprs +
5774 util_bitcount(shader->selector->info.colors_written) * 4 +
5775 shader->selector->info.writes_z +
5776 shader->selector->info.writes_stencil +
5777 shader->selector->info.writes_samplemask +
5778 1 /* SampleMaskIn */;
5779
5780 num_returns = MAX2(num_returns,
5781 num_return_sgprs +
5782 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5783
5784 for (i = 0; i < num_return_sgprs; i++)
5785 returns[i] = ctx->i32;
5786 for (; i < num_returns; i++)
5787 returns[i] = ctx->f32;
5788 break;
5789
5790 case PIPE_SHADER_COMPUTE:
5791 params[SI_PARAM_GRID_SIZE] = v3i32;
5792 params[SI_PARAM_BLOCK_SIZE] = v3i32;
5793 params[SI_PARAM_BLOCK_ID] = v3i32;
5794 last_sgpr = SI_PARAM_BLOCK_ID;
5795
5796 params[SI_PARAM_THREAD_ID] = v3i32;
5797 num_params = SI_PARAM_THREAD_ID + 1;
5798 break;
5799 default:
5800 assert(0 && "unimplemented shader");
5801 return;
5802 }
5803
5804 assert(num_params <= ARRAY_SIZE(params));
5805
5806 si_create_function(ctx, "main", returns, num_returns, params,
5807 num_params, last_sgpr);
5808
5809 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5810 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5811 ctx->separate_prolog) {
5812 si_llvm_add_attribute(ctx->main_fn,
5813 "InitialPSInputAddr",
5814 S_0286D0_PERSP_SAMPLE_ENA(1) |
5815 S_0286D0_PERSP_CENTER_ENA(1) |
5816 S_0286D0_PERSP_CENTROID_ENA(1) |
5817 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5818 S_0286D0_LINEAR_CENTER_ENA(1) |
5819 S_0286D0_LINEAR_CENTROID_ENA(1) |
5820 S_0286D0_FRONT_FACE_ENA(1) |
5821 S_0286D0_POS_FIXED_PT_ENA(1));
5822 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5823 si_llvm_add_attribute(ctx->main_fn,
5824 "amdgpu-max-work-group-size",
5825 si_get_max_workgroup_size(shader));
5826 }
5827
5828 shader->info.num_input_sgprs = 0;
5829 shader->info.num_input_vgprs = 0;
5830
5831 for (i = 0; i <= last_sgpr; ++i)
5832 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5833
5834 for (; i < num_params; ++i)
5835 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5836
5837 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5838 shader->info.num_input_vgprs -= num_prolog_vgprs;
5839
5840 if (!ctx->screen->has_ds_bpermute &&
5841 bld_base->info &&
5842 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5843 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5844 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5845 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5846 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5847 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5848 ctx->lds =
5849 LLVMAddGlobalInAddressSpace(gallivm->module,
5850 LLVMArrayType(ctx->i32, 64),
5851 "ddxy_lds",
5852 LOCAL_ADDR_SPACE);
5853
5854 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.as_ls) ||
5855 ctx->type == PIPE_SHADER_TESS_CTRL)
5856 declare_tess_lds(ctx);
5857 }
5858
5859 /**
5860 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5861 * for later use.
5862 */
5863 static void preload_ring_buffers(struct si_shader_context *ctx)
5864 {
5865 struct gallivm_state *gallivm = &ctx->gallivm;
5866 LLVMBuilderRef builder = gallivm->builder;
5867
5868 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5869 SI_PARAM_RW_BUFFERS);
5870
5871 if ((ctx->type == PIPE_SHADER_VERTEX &&
5872 ctx->shader->key.as_es) ||
5873 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5874 ctx->shader->key.as_es) ||
5875 ctx->type == PIPE_SHADER_GEOMETRY) {
5876 unsigned ring =
5877 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5878 : SI_ES_RING_ESGS;
5879 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
5880
5881 ctx->esgs_ring =
5882 ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
5883 }
5884
5885 if (ctx->shader->is_gs_copy_shader) {
5886 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5887
5888 ctx->gsvs_ring[0] =
5889 ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
5890 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5891 const struct si_shader_selector *sel = ctx->shader->selector;
5892 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5893 LLVMValueRef base_ring;
5894
5895 base_ring = ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
5896
5897 /* The conceptual layout of the GSVS ring is
5898 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5899 * but the real memory layout is swizzled across
5900 * threads:
5901 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5902 * t16v0c0 ..
5903 * Override the buffer descriptor accordingly.
5904 */
5905 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5906 uint64_t stream_offset = 0;
5907
5908 for (unsigned stream = 0; stream < 4; ++stream) {
5909 unsigned num_components;
5910 unsigned stride;
5911 unsigned num_records;
5912 LLVMValueRef ring, tmp;
5913
5914 num_components = sel->info.num_stream_output_components[stream];
5915 if (!num_components)
5916 continue;
5917
5918 stride = 4 * num_components * sel->gs_max_out_vertices;
5919
5920 /* Limit on the stride field for <= CIK. */
5921 assert(stride < (1 << 14));
5922
5923 num_records = 64;
5924
5925 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5926 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
5927 tmp = LLVMBuildAdd(builder, tmp,
5928 LLVMConstInt(ctx->i64,
5929 stream_offset, 0), "");
5930 stream_offset += stride * 64;
5931
5932 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5933 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5934 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5935 tmp = LLVMBuildOr(builder, tmp,
5936 LLVMConstInt(ctx->i32,
5937 S_008F04_STRIDE(stride) |
5938 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5939 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5940 ring = LLVMBuildInsertElement(builder, ring,
5941 LLVMConstInt(ctx->i32, num_records, 0),
5942 LLVMConstInt(ctx->i32, 2, 0), "");
5943 ring = LLVMBuildInsertElement(builder, ring,
5944 LLVMConstInt(ctx->i32,
5945 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5946 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5947 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5948 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5949 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5950 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5951 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5952 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5953 S_008F0C_ADD_TID_ENABLE(1),
5954 0),
5955 LLVMConstInt(ctx->i32, 3, 0), "");
5956 ring = LLVMBuildBitCast(builder, ring, ctx->v16i8, "");
5957
5958 ctx->gsvs_ring[stream] = ring;
5959 }
5960 }
5961 }
5962
5963 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5964 LLVMValueRef param_rw_buffers,
5965 unsigned param_pos_fixed_pt)
5966 {
5967 struct gallivm_state *gallivm = &ctx->gallivm;
5968 LLVMBuilderRef builder = gallivm->builder;
5969 LLVMValueRef slot, desc, offset, row, bit, address[2];
5970
5971 /* Use the fixed-point gl_FragCoord input.
5972 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5973 * per coordinate to get the repeating effect.
5974 */
5975 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5976 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5977
5978 /* Load the buffer descriptor. */
5979 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5980 desc = ac_build_indexed_load_const(&ctx->ac, param_rw_buffers, slot);
5981
5982 /* The stipple pattern is 32x32, each row has 32 bits. */
5983 offset = LLVMBuildMul(builder, address[1],
5984 LLVMConstInt(ctx->i32, 4, 0), "");
5985 row = buffer_load_const(ctx, desc, offset);
5986 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
5987 bit = LLVMBuildLShr(builder, row, address[0], "");
5988 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5989
5990 /* The intrinsic kills the thread if arg < 0. */
5991 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
5992 LLVMConstReal(ctx->f32, -1), "");
5993 ac_build_kill(&ctx->ac, bit);
5994 }
5995
5996 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5997 struct si_shader_config *conf,
5998 unsigned symbol_offset)
5999 {
6000 unsigned i;
6001 const unsigned char *config =
6002 ac_shader_binary_config_start(binary, symbol_offset);
6003 bool really_needs_scratch = false;
6004
6005 /* LLVM adds SGPR spills to the scratch size.
6006 * Find out if we really need the scratch buffer.
6007 */
6008 for (i = 0; i < binary->reloc_count; i++) {
6009 const struct ac_shader_reloc *reloc = &binary->relocs[i];
6010
6011 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
6012 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
6013 really_needs_scratch = true;
6014 break;
6015 }
6016 }
6017
6018 /* XXX: We may be able to emit some of these values directly rather than
6019 * extracting fields to be emitted later.
6020 */
6021
6022 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
6023 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
6024 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
6025 switch (reg) {
6026 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
6027 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
6028 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
6029 case R_00B848_COMPUTE_PGM_RSRC1:
6030 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
6031 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
6032 conf->float_mode = G_00B028_FLOAT_MODE(value);
6033 conf->rsrc1 = value;
6034 break;
6035 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
6036 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
6037 break;
6038 case R_00B84C_COMPUTE_PGM_RSRC2:
6039 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
6040 conf->rsrc2 = value;
6041 break;
6042 case R_0286CC_SPI_PS_INPUT_ENA:
6043 conf->spi_ps_input_ena = value;
6044 break;
6045 case R_0286D0_SPI_PS_INPUT_ADDR:
6046 conf->spi_ps_input_addr = value;
6047 break;
6048 case R_0286E8_SPI_TMPRING_SIZE:
6049 case R_00B860_COMPUTE_TMPRING_SIZE:
6050 /* WAVESIZE is in units of 256 dwords. */
6051 if (really_needs_scratch)
6052 conf->scratch_bytes_per_wave =
6053 G_00B860_WAVESIZE(value) * 256 * 4;
6054 break;
6055 case 0x4: /* SPILLED_SGPRS */
6056 conf->spilled_sgprs = value;
6057 break;
6058 case 0x8: /* SPILLED_VGPRS */
6059 conf->spilled_vgprs = value;
6060 break;
6061 default:
6062 {
6063 static bool printed;
6064
6065 if (!printed) {
6066 fprintf(stderr, "Warning: LLVM emitted unknown "
6067 "config register: 0x%x\n", reg);
6068 printed = true;
6069 }
6070 }
6071 break;
6072 }
6073 }
6074
6075 if (!conf->spi_ps_input_addr)
6076 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
6077 }
6078
6079 void si_shader_apply_scratch_relocs(struct si_context *sctx,
6080 struct si_shader *shader,
6081 struct si_shader_config *config,
6082 uint64_t scratch_va)
6083 {
6084 unsigned i;
6085 uint32_t scratch_rsrc_dword0 = scratch_va;
6086 uint32_t scratch_rsrc_dword1 =
6087 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
6088
6089 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
6090 * correctly.
6091 */
6092 if (HAVE_LLVM >= 0x0309)
6093 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
6094 else
6095 scratch_rsrc_dword1 |=
6096 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
6097
6098 for (i = 0 ; i < shader->binary.reloc_count; i++) {
6099 const struct ac_shader_reloc *reloc =
6100 &shader->binary.relocs[i];
6101 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
6102 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
6103 &scratch_rsrc_dword0, 4);
6104 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
6105 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
6106 &scratch_rsrc_dword1, 4);
6107 }
6108 }
6109 }
6110
6111 static unsigned si_get_shader_binary_size(struct si_shader *shader)
6112 {
6113 unsigned size = shader->binary.code_size;
6114
6115 if (shader->prolog)
6116 size += shader->prolog->binary.code_size;
6117 if (shader->epilog)
6118 size += shader->epilog->binary.code_size;
6119 return size;
6120 }
6121
6122 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
6123 {
6124 const struct ac_shader_binary *prolog =
6125 shader->prolog ? &shader->prolog->binary : NULL;
6126 const struct ac_shader_binary *epilog =
6127 shader->epilog ? &shader->epilog->binary : NULL;
6128 const struct ac_shader_binary *mainb = &shader->binary;
6129 unsigned bo_size = si_get_shader_binary_size(shader) +
6130 (!epilog ? mainb->rodata_size : 0);
6131 unsigned char *ptr;
6132
6133 assert(!prolog || !prolog->rodata_size);
6134 assert((!prolog && !epilog) || !mainb->rodata_size);
6135 assert(!epilog || !epilog->rodata_size);
6136
6137 /* GFX9 can fetch at most 128 bytes past the end of the shader.
6138 * Prevent VM faults.
6139 */
6140 if (sscreen->b.chip_class >= GFX9)
6141 bo_size += 128;
6142
6143 r600_resource_reference(&shader->bo, NULL);
6144 shader->bo = (struct r600_resource*)
6145 pipe_buffer_create(&sscreen->b.b, 0,
6146 PIPE_USAGE_IMMUTABLE,
6147 align(bo_size, SI_CPDMA_ALIGNMENT));
6148 if (!shader->bo)
6149 return -ENOMEM;
6150
6151 /* Upload. */
6152 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
6153 PIPE_TRANSFER_READ_WRITE);
6154
6155 if (prolog) {
6156 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
6157 ptr += prolog->code_size;
6158 }
6159
6160 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
6161 ptr += mainb->code_size;
6162
6163 if (epilog)
6164 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
6165 else if (mainb->rodata_size > 0)
6166 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
6167
6168 sscreen->b.ws->buffer_unmap(shader->bo->buf);
6169 return 0;
6170 }
6171
6172 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
6173 struct pipe_debug_callback *debug,
6174 const char *name, FILE *file)
6175 {
6176 char *line, *p;
6177 unsigned i, count;
6178
6179 if (binary->disasm_string) {
6180 fprintf(file, "Shader %s disassembly:\n", name);
6181 fprintf(file, "%s", binary->disasm_string);
6182
6183 if (debug && debug->debug_message) {
6184 /* Very long debug messages are cut off, so send the
6185 * disassembly one line at a time. This causes more
6186 * overhead, but on the plus side it simplifies
6187 * parsing of resulting logs.
6188 */
6189 pipe_debug_message(debug, SHADER_INFO,
6190 "Shader Disassembly Begin");
6191
6192 line = binary->disasm_string;
6193 while (*line) {
6194 p = util_strchrnul(line, '\n');
6195 count = p - line;
6196
6197 if (count) {
6198 pipe_debug_message(debug, SHADER_INFO,
6199 "%.*s", count, line);
6200 }
6201
6202 if (!*p)
6203 break;
6204 line = p + 1;
6205 }
6206
6207 pipe_debug_message(debug, SHADER_INFO,
6208 "Shader Disassembly End");
6209 }
6210 } else {
6211 fprintf(file, "Shader %s binary:\n", name);
6212 for (i = 0; i < binary->code_size; i += 4) {
6213 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
6214 binary->code[i + 3], binary->code[i + 2],
6215 binary->code[i + 1], binary->code[i]);
6216 }
6217 }
6218 }
6219
6220 static void si_shader_dump_stats(struct si_screen *sscreen,
6221 struct si_shader *shader,
6222 struct pipe_debug_callback *debug,
6223 unsigned processor,
6224 FILE *file,
6225 bool check_debug_option)
6226 {
6227 struct si_shader_config *conf = &shader->config;
6228 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
6229 unsigned code_size = si_get_shader_binary_size(shader);
6230 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
6231 unsigned lds_per_wave = 0;
6232 unsigned max_simd_waves = 10;
6233
6234 /* Compute LDS usage for PS. */
6235 switch (processor) {
6236 case PIPE_SHADER_FRAGMENT:
6237 /* The minimum usage per wave is (num_inputs * 48). The maximum
6238 * usage is (num_inputs * 48 * 16).
6239 * We can get anything in between and it varies between waves.
6240 *
6241 * The 48 bytes per input for a single primitive is equal to
6242 * 4 bytes/component * 4 components/input * 3 points.
6243 *
6244 * Other stages don't know the size at compile time or don't
6245 * allocate LDS per wave, but instead they do it per thread group.
6246 */
6247 lds_per_wave = conf->lds_size * lds_increment +
6248 align(num_inputs * 48, lds_increment);
6249 break;
6250 case PIPE_SHADER_COMPUTE:
6251 if (shader->selector) {
6252 unsigned max_workgroup_size =
6253 si_get_max_workgroup_size(shader);
6254 lds_per_wave = (conf->lds_size * lds_increment) /
6255 DIV_ROUND_UP(max_workgroup_size, 64);
6256 }
6257 break;
6258 }
6259
6260 /* Compute the per-SIMD wave counts. */
6261 if (conf->num_sgprs) {
6262 if (sscreen->b.chip_class >= VI)
6263 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
6264 else
6265 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
6266 }
6267
6268 if (conf->num_vgprs)
6269 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
6270
6271 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
6272 * 16KB makes some SIMDs unoccupied). */
6273 if (lds_per_wave)
6274 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
6275
6276 if (!check_debug_option ||
6277 r600_can_dump_shader(&sscreen->b, processor)) {
6278 if (processor == PIPE_SHADER_FRAGMENT) {
6279 fprintf(file, "*** SHADER CONFIG ***\n"
6280 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6281 "SPI_PS_INPUT_ENA = 0x%04x\n",
6282 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
6283 }
6284
6285 fprintf(file, "*** SHADER STATS ***\n"
6286 "SGPRS: %d\n"
6287 "VGPRS: %d\n"
6288 "Spilled SGPRs: %d\n"
6289 "Spilled VGPRs: %d\n"
6290 "Private memory VGPRs: %d\n"
6291 "Code Size: %d bytes\n"
6292 "LDS: %d blocks\n"
6293 "Scratch: %d bytes per wave\n"
6294 "Max Waves: %d\n"
6295 "********************\n\n\n",
6296 conf->num_sgprs, conf->num_vgprs,
6297 conf->spilled_sgprs, conf->spilled_vgprs,
6298 conf->private_mem_vgprs, code_size,
6299 conf->lds_size, conf->scratch_bytes_per_wave,
6300 max_simd_waves);
6301 }
6302
6303 pipe_debug_message(debug, SHADER_INFO,
6304 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6305 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
6306 "Spilled VGPRs: %d PrivMem VGPRs: %d",
6307 conf->num_sgprs, conf->num_vgprs, code_size,
6308 conf->lds_size, conf->scratch_bytes_per_wave,
6309 max_simd_waves, conf->spilled_sgprs,
6310 conf->spilled_vgprs, conf->private_mem_vgprs);
6311 }
6312
6313 const char *si_get_shader_name(struct si_shader *shader, unsigned processor)
6314 {
6315 switch (processor) {
6316 case PIPE_SHADER_VERTEX:
6317 if (shader->key.as_es)
6318 return "Vertex Shader as ES";
6319 else if (shader->key.as_ls)
6320 return "Vertex Shader as LS";
6321 else
6322 return "Vertex Shader as VS";
6323 case PIPE_SHADER_TESS_CTRL:
6324 return "Tessellation Control Shader";
6325 case PIPE_SHADER_TESS_EVAL:
6326 if (shader->key.as_es)
6327 return "Tessellation Evaluation Shader as ES";
6328 else
6329 return "Tessellation Evaluation Shader as VS";
6330 case PIPE_SHADER_GEOMETRY:
6331 if (shader->is_gs_copy_shader)
6332 return "GS Copy Shader as VS";
6333 else
6334 return "Geometry Shader";
6335 case PIPE_SHADER_FRAGMENT:
6336 return "Pixel Shader";
6337 case PIPE_SHADER_COMPUTE:
6338 return "Compute Shader";
6339 default:
6340 return "Unknown Shader";
6341 }
6342 }
6343
6344 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6345 struct pipe_debug_callback *debug, unsigned processor,
6346 FILE *file, bool check_debug_option)
6347 {
6348 if (!check_debug_option ||
6349 r600_can_dump_shader(&sscreen->b, processor))
6350 si_dump_shader_key(processor, &shader->key, file);
6351
6352 if (!check_debug_option && shader->binary.llvm_ir_string) {
6353 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
6354 si_get_shader_name(shader, processor));
6355 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
6356 }
6357
6358 if (!check_debug_option ||
6359 (r600_can_dump_shader(&sscreen->b, processor) &&
6360 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6361 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6362
6363 if (shader->prolog)
6364 si_shader_dump_disassembly(&shader->prolog->binary,
6365 debug, "prolog", file);
6366
6367 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6368
6369 if (shader->epilog)
6370 si_shader_dump_disassembly(&shader->epilog->binary,
6371 debug, "epilog", file);
6372 fprintf(file, "\n");
6373 }
6374
6375 si_shader_dump_stats(sscreen, shader, debug, processor, file,
6376 check_debug_option);
6377 }
6378
6379 int si_compile_llvm(struct si_screen *sscreen,
6380 struct ac_shader_binary *binary,
6381 struct si_shader_config *conf,
6382 LLVMTargetMachineRef tm,
6383 LLVMModuleRef mod,
6384 struct pipe_debug_callback *debug,
6385 unsigned processor,
6386 const char *name)
6387 {
6388 int r = 0;
6389 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6390
6391 if (r600_can_dump_shader(&sscreen->b, processor)) {
6392 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6393
6394 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6395 fprintf(stderr, "%s LLVM IR:\n\n", name);
6396 ac_dump_module(mod);
6397 fprintf(stderr, "\n");
6398 }
6399 }
6400
6401 if (sscreen->record_llvm_ir) {
6402 char *ir = LLVMPrintModuleToString(mod);
6403 binary->llvm_ir_string = strdup(ir);
6404 LLVMDisposeMessage(ir);
6405 }
6406
6407 if (!si_replace_shader(count, binary)) {
6408 r = si_llvm_compile(mod, binary, tm, debug);
6409 if (r)
6410 return r;
6411 }
6412
6413 si_shader_binary_read_config(binary, conf, 0);
6414
6415 /* Enable 64-bit and 16-bit denormals, because there is no performance
6416 * cost.
6417 *
6418 * If denormals are enabled, all floating-point output modifiers are
6419 * ignored.
6420 *
6421 * Don't enable denormals for 32-bit floats, because:
6422 * - Floating-point output modifiers would be ignored by the hw.
6423 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6424 * have to stop using those.
6425 * - SI & CI would be very slow.
6426 */
6427 conf->float_mode |= V_00B028_FP_64_DENORMS;
6428
6429 FREE(binary->config);
6430 FREE(binary->global_symbol_offsets);
6431 binary->config = NULL;
6432 binary->global_symbol_offsets = NULL;
6433
6434 /* Some shaders can't have rodata because their binaries can be
6435 * concatenated.
6436 */
6437 if (binary->rodata_size &&
6438 (processor == PIPE_SHADER_VERTEX ||
6439 processor == PIPE_SHADER_TESS_CTRL ||
6440 processor == PIPE_SHADER_TESS_EVAL ||
6441 processor == PIPE_SHADER_FRAGMENT)) {
6442 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6443 return -EINVAL;
6444 }
6445
6446 return r;
6447 }
6448
6449 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6450 {
6451 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6452 LLVMBuildRetVoid(ctx->gallivm.builder);
6453 else
6454 LLVMBuildRet(ctx->gallivm.builder, ret);
6455 }
6456
6457 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6458 struct si_shader *
6459 si_generate_gs_copy_shader(struct si_screen *sscreen,
6460 LLVMTargetMachineRef tm,
6461 struct si_shader_selector *gs_selector,
6462 struct pipe_debug_callback *debug)
6463 {
6464 struct si_shader_context ctx;
6465 struct si_shader *shader;
6466 struct gallivm_state *gallivm = &ctx.gallivm;
6467 LLVMBuilderRef builder;
6468 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
6469 struct lp_build_context *uint = &bld_base->uint_bld;
6470 struct si_shader_output_values *outputs;
6471 struct tgsi_shader_info *gsinfo = &gs_selector->info;
6472 int i, r;
6473
6474 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6475
6476 if (!outputs)
6477 return NULL;
6478
6479 shader = CALLOC_STRUCT(si_shader);
6480 if (!shader) {
6481 FREE(outputs);
6482 return NULL;
6483 }
6484
6485
6486 shader->selector = gs_selector;
6487 shader->is_gs_copy_shader = true;
6488
6489 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6490 ctx.type = PIPE_SHADER_VERTEX;
6491
6492 builder = gallivm->builder;
6493
6494 create_function(&ctx);
6495 preload_ring_buffers(&ctx);
6496
6497 LLVMValueRef voffset =
6498 lp_build_mul_imm(uint, LLVMGetParam(ctx.main_fn,
6499 ctx.param_vertex_id), 4);
6500
6501 /* Fetch the vertex stream ID.*/
6502 LLVMValueRef stream_id;
6503
6504 if (gs_selector->so.num_outputs)
6505 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
6506 else
6507 stream_id = ctx.i32_0;
6508
6509 /* Fill in output information. */
6510 for (i = 0; i < gsinfo->num_outputs; ++i) {
6511 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
6512 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
6513
6514 for (int chan = 0; chan < 4; chan++) {
6515 outputs[i].vertex_stream[chan] =
6516 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
6517 }
6518 }
6519
6520 LLVMBasicBlockRef end_bb;
6521 LLVMValueRef switch_inst;
6522
6523 end_bb = LLVMAppendBasicBlockInContext(gallivm->context, ctx.main_fn, "end");
6524 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
6525
6526 for (int stream = 0; stream < 4; stream++) {
6527 LLVMBasicBlockRef bb;
6528 unsigned offset;
6529
6530 if (!gsinfo->num_stream_output_components[stream])
6531 continue;
6532
6533 if (stream > 0 && !gs_selector->so.num_outputs)
6534 continue;
6535
6536 bb = LLVMInsertBasicBlockInContext(gallivm->context, end_bb, "out");
6537 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
6538 LLVMPositionBuilderAtEnd(builder, bb);
6539
6540 /* Fetch vertex data from GSVS ring */
6541 offset = 0;
6542 for (i = 0; i < gsinfo->num_outputs; ++i) {
6543 for (unsigned chan = 0; chan < 4; chan++) {
6544 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
6545 outputs[i].vertex_stream[chan] != stream) {
6546 outputs[i].values[chan] = ctx.bld_base.base.undef;
6547 continue;
6548 }
6549
6550 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
6551 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
6552 offset++;
6553
6554 outputs[i].values[chan] =
6555 ac_build_buffer_load(&ctx.ac,
6556 ctx.gsvs_ring[0], 1,
6557 ctx.i32_0, voffset,
6558 soffset, 0, 1, 1, true);
6559 }
6560 }
6561
6562 /* Streamout and exports. */
6563 if (gs_selector->so.num_outputs) {
6564 si_llvm_emit_streamout(&ctx, outputs,
6565 gsinfo->num_outputs,
6566 stream);
6567 }
6568
6569 if (stream == 0)
6570 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6571
6572 LLVMBuildBr(builder, end_bb);
6573 }
6574
6575 LLVMPositionBuilderAtEnd(builder, end_bb);
6576
6577 LLVMBuildRetVoid(gallivm->builder);
6578
6579 /* Dump LLVM IR before any optimization passes */
6580 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6581 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6582 ac_dump_module(ctx.gallivm.module);
6583
6584 si_llvm_finalize_module(&ctx,
6585 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_GEOMETRY));
6586
6587 r = si_compile_llvm(sscreen, &ctx.shader->binary,
6588 &ctx.shader->config, ctx.tm,
6589 ctx.gallivm.module,
6590 debug, PIPE_SHADER_GEOMETRY,
6591 "GS Copy Shader");
6592 if (!r) {
6593 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6594 fprintf(stderr, "GS Copy Shader:\n");
6595 si_shader_dump(sscreen, ctx.shader, debug,
6596 PIPE_SHADER_GEOMETRY, stderr, true);
6597 r = si_shader_binary_upload(sscreen, ctx.shader);
6598 }
6599
6600 si_llvm_dispose(&ctx);
6601
6602 FREE(outputs);
6603
6604 if (r != 0) {
6605 FREE(shader);
6606 shader = NULL;
6607 }
6608 return shader;
6609 }
6610
6611 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
6612 FILE *f)
6613 {
6614 int i;
6615
6616 fprintf(f, "SHADER KEY\n");
6617
6618 switch (shader) {
6619 case PIPE_SHADER_VERTEX:
6620 fprintf(f, " part.vs.prolog.instance_divisors = {");
6621 for (i = 0; i < ARRAY_SIZE(key->part.vs.prolog.instance_divisors); i++)
6622 fprintf(f, !i ? "%u" : ", %u",
6623 key->part.vs.prolog.instance_divisors[i]);
6624 fprintf(f, "}\n");
6625 fprintf(f, " part.vs.epilog.export_prim_id = %u\n", key->part.vs.epilog.export_prim_id);
6626 fprintf(f, " as_es = %u\n", key->as_es);
6627 fprintf(f, " as_ls = %u\n", key->as_ls);
6628
6629 fprintf(f, " mono.vs.fix_fetch = {");
6630 for (i = 0; i < SI_MAX_ATTRIBS; i++)
6631 fprintf(f, !i ? "%u" : ", %u", key->mono.vs.fix_fetch[i]);
6632 fprintf(f, "}\n");
6633 break;
6634
6635 case PIPE_SHADER_TESS_CTRL:
6636 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
6637 fprintf(f, " mono.tcs.inputs_to_copy = 0x%"PRIx64"\n", key->mono.tcs.inputs_to_copy);
6638 break;
6639
6640 case PIPE_SHADER_TESS_EVAL:
6641 fprintf(f, " part.tes.epilog.export_prim_id = %u\n", key->part.tes.epilog.export_prim_id);
6642 fprintf(f, " as_es = %u\n", key->as_es);
6643 break;
6644
6645 case PIPE_SHADER_GEOMETRY:
6646 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
6647 break;
6648
6649 case PIPE_SHADER_COMPUTE:
6650 break;
6651
6652 case PIPE_SHADER_FRAGMENT:
6653 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
6654 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
6655 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
6656 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
6657 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
6658 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
6659 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
6660 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
6661 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
6662 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
6663 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
6664 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
6665 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
6666 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
6667 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
6668 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
6669 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
6670 break;
6671
6672 default:
6673 assert(0);
6674 }
6675
6676 if ((shader == PIPE_SHADER_GEOMETRY ||
6677 shader == PIPE_SHADER_TESS_EVAL ||
6678 shader == PIPE_SHADER_VERTEX) &&
6679 !key->as_es && !key->as_ls) {
6680 fprintf(f, " opt.hw_vs.kill_outputs = 0x%"PRIx64"\n", key->opt.hw_vs.kill_outputs);
6681 fprintf(f, " opt.hw_vs.kill_outputs2 = 0x%x\n", key->opt.hw_vs.kill_outputs2);
6682 fprintf(f, " opt.hw_vs.clip_disable = %u\n", key->opt.hw_vs.clip_disable);
6683 }
6684 }
6685
6686 static void si_init_shader_ctx(struct si_shader_context *ctx,
6687 struct si_screen *sscreen,
6688 struct si_shader *shader,
6689 LLVMTargetMachineRef tm)
6690 {
6691 struct lp_build_tgsi_context *bld_base;
6692 struct lp_build_tgsi_action tmpl = {};
6693
6694 si_llvm_context_init(ctx, sscreen, shader, tm,
6695 (shader && shader->selector) ? &shader->selector->info : NULL,
6696 (shader && shader->selector) ? shader->selector->tokens : NULL);
6697
6698 bld_base = &ctx->bld_base;
6699 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6700
6701 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6702 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6703 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6704
6705 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6706 bld_base->op_actions[TGSI_OPCODE_TEX_LZ] = tex_action;
6707 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6708 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6709 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6710 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6711 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6712 bld_base->op_actions[TGSI_OPCODE_TXF_LZ] = tex_action;
6713 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6714 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6715 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6716 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6717 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6718 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6719 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6720 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6721
6722 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6723 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6724 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6725 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6726 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6727 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6728
6729 tmpl.fetch_args = atomic_fetch_args;
6730 tmpl.emit = atomic_emit;
6731 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6732 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6733 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6734 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6735 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6736 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6737 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6738 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6739 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6740 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6741 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6742 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6743 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6744 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6745 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6746 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6747 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6748 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6749 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6750 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6751
6752 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6753
6754 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
6755
6756 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6757 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6758 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6759 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6760
6761 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
6762 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
6763 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
6764 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
6765 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
6766 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
6767 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
6768 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
6769 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
6770
6771 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6772 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6773 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6774 }
6775
6776 #define EXP_TARGET (HAVE_LLVM >= 0x0500 ? 0 : 3)
6777 #define EXP_OUT0 (HAVE_LLVM >= 0x0500 ? 2 : 5)
6778
6779 /* Return true if the PARAM export has been eliminated. */
6780 static bool si_eliminate_const_output(struct si_shader_context *ctx,
6781 LLVMValueRef inst, unsigned offset)
6782 {
6783 struct si_shader *shader = ctx->shader;
6784 unsigned num_outputs = shader->selector->info.num_outputs;
6785 unsigned i, default_val; /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL */
6786 bool is_zero[4] = {}, is_one[4] = {};
6787
6788 for (i = 0; i < 4; i++) {
6789 LLVMBool loses_info;
6790 LLVMValueRef p = LLVMGetOperand(inst, EXP_OUT0 + i);
6791
6792 /* It's a constant expression. Undef outputs are eliminated too. */
6793 if (LLVMIsUndef(p)) {
6794 is_zero[i] = true;
6795 is_one[i] = true;
6796 } else if (LLVMIsAConstantFP(p)) {
6797 double a = LLVMConstRealGetDouble(p, &loses_info);
6798
6799 if (a == 0)
6800 is_zero[i] = true;
6801 else if (a == 1)
6802 is_one[i] = true;
6803 else
6804 return false; /* other constant */
6805 } else
6806 return false;
6807 }
6808
6809 /* Only certain combinations of 0 and 1 can be eliminated. */
6810 if (is_zero[0] && is_zero[1] && is_zero[2])
6811 default_val = is_zero[3] ? 0 : 1;
6812 else if (is_one[0] && is_one[1] && is_one[2])
6813 default_val = is_zero[3] ? 2 : 3;
6814 else
6815 return false;
6816
6817 /* The PARAM export can be represented as DEFAULT_VAL. Kill it. */
6818 LLVMInstructionEraseFromParent(inst);
6819
6820 /* Change OFFSET to DEFAULT_VAL. */
6821 for (i = 0; i < num_outputs; i++) {
6822 if (shader->info.vs_output_param_offset[i] == offset) {
6823 shader->info.vs_output_param_offset[i] =
6824 EXP_PARAM_DEFAULT_VAL_0000 + default_val;
6825 break;
6826 }
6827 }
6828 return true;
6829 }
6830
6831 struct si_vs_exports {
6832 unsigned num;
6833 unsigned offset[SI_MAX_VS_OUTPUTS];
6834 LLVMValueRef inst[SI_MAX_VS_OUTPUTS];
6835 };
6836
6837 static void si_eliminate_const_vs_outputs(struct si_shader_context *ctx)
6838 {
6839 struct si_shader *shader = ctx->shader;
6840 struct tgsi_shader_info *info = &shader->selector->info;
6841 LLVMBasicBlockRef bb;
6842 struct si_vs_exports exports;
6843 bool removed_any = false;
6844
6845 exports.num = 0;
6846
6847 if (ctx->type == PIPE_SHADER_FRAGMENT ||
6848 ctx->type == PIPE_SHADER_COMPUTE ||
6849 shader->key.as_es ||
6850 shader->key.as_ls)
6851 return;
6852
6853 /* Process all LLVM instructions. */
6854 bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6855 while (bb) {
6856 LLVMValueRef inst = LLVMGetFirstInstruction(bb);
6857
6858 while (inst) {
6859 LLVMValueRef cur = inst;
6860 inst = LLVMGetNextInstruction(inst);
6861
6862 if (LLVMGetInstructionOpcode(cur) != LLVMCall)
6863 continue;
6864
6865 LLVMValueRef callee = lp_get_called_value(cur);
6866
6867 if (!lp_is_function(callee))
6868 continue;
6869
6870 const char *name = LLVMGetValueName(callee);
6871 unsigned num_args = LLVMCountParams(callee);
6872
6873 /* Check if this is an export instruction. */
6874 if ((num_args != 9 && num_args != 8) ||
6875 (strcmp(name, "llvm.SI.export") &&
6876 strcmp(name, "llvm.amdgcn.exp.f32")))
6877 continue;
6878
6879 LLVMValueRef arg = LLVMGetOperand(cur, EXP_TARGET);
6880 unsigned target = LLVMConstIntGetZExtValue(arg);
6881
6882 if (target < V_008DFC_SQ_EXP_PARAM)
6883 continue;
6884
6885 target -= V_008DFC_SQ_EXP_PARAM;
6886
6887 /* Eliminate constant value PARAM exports. */
6888 if (si_eliminate_const_output(ctx, cur, target)) {
6889 removed_any = true;
6890 } else {
6891 exports.offset[exports.num] = target;
6892 exports.inst[exports.num] = cur;
6893 exports.num++;
6894 }
6895 }
6896 bb = LLVMGetNextBasicBlock(bb);
6897 }
6898
6899 /* Remove holes in export memory due to removed PARAM exports.
6900 * This is done by renumbering all PARAM exports.
6901 */
6902 if (removed_any) {
6903 ubyte current_offset[SI_MAX_VS_OUTPUTS];
6904 unsigned new_count = 0;
6905 unsigned out, i;
6906
6907 /* Make a copy of the offsets. We need the old version while
6908 * we are modifying some of them. */
6909 assert(sizeof(current_offset) ==
6910 sizeof(shader->info.vs_output_param_offset));
6911 memcpy(current_offset, shader->info.vs_output_param_offset,
6912 sizeof(current_offset));
6913
6914 for (i = 0; i < exports.num; i++) {
6915 unsigned offset = exports.offset[i];
6916
6917 for (out = 0; out < info->num_outputs; out++) {
6918 if (current_offset[out] != offset)
6919 continue;
6920
6921 LLVMSetOperand(exports.inst[i], EXP_TARGET,
6922 LLVMConstInt(ctx->i32,
6923 V_008DFC_SQ_EXP_PARAM + new_count, 0));
6924 shader->info.vs_output_param_offset[out] = new_count;
6925 new_count++;
6926 break;
6927 }
6928 }
6929 shader->info.nr_param_exports = new_count;
6930 }
6931 }
6932
6933 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
6934 {
6935 ctx->shader->config.private_mem_vgprs = 0;
6936
6937 /* Process all LLVM instructions. */
6938 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6939 while (bb) {
6940 LLVMValueRef next = LLVMGetFirstInstruction(bb);
6941
6942 while (next) {
6943 LLVMValueRef inst = next;
6944 next = LLVMGetNextInstruction(next);
6945
6946 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
6947 continue;
6948
6949 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
6950 /* No idea why LLVM aligns allocas to 4 elements. */
6951 unsigned alignment = LLVMGetAlignment(inst);
6952 unsigned dw_size = align(llvm_get_type_size(type) / 4, alignment);
6953 ctx->shader->config.private_mem_vgprs += dw_size;
6954 }
6955 bb = LLVMGetNextBasicBlock(bb);
6956 }
6957 }
6958
6959 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
6960 struct si_shader *shader)
6961 {
6962 struct si_shader_selector *sel = shader->selector;
6963 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6964
6965 switch (ctx->type) {
6966 case PIPE_SHADER_VERTEX:
6967 ctx->load_input = declare_input_vs;
6968 if (shader->key.as_ls)
6969 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6970 else if (shader->key.as_es)
6971 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6972 else
6973 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6974 break;
6975 case PIPE_SHADER_TESS_CTRL:
6976 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6977 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6978 bld_base->emit_store = store_output_tcs;
6979 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6980 break;
6981 case PIPE_SHADER_TESS_EVAL:
6982 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6983 if (shader->key.as_es)
6984 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6985 else
6986 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6987 break;
6988 case PIPE_SHADER_GEOMETRY:
6989 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6990 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6991 break;
6992 case PIPE_SHADER_FRAGMENT:
6993 ctx->load_input = declare_input_fs;
6994 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6995 break;
6996 case PIPE_SHADER_COMPUTE:
6997 ctx->declare_memory_region = declare_compute_memory;
6998 break;
6999 default:
7000 assert(!"Unsupported shader type");
7001 return false;
7002 }
7003
7004 create_function(ctx);
7005 preload_ring_buffers(ctx);
7006
7007 if (ctx->type == PIPE_SHADER_GEOMETRY) {
7008 int i;
7009 for (i = 0; i < 4; i++) {
7010 ctx->gs_next_vertex[i] =
7011 lp_build_alloca(&ctx->gallivm,
7012 ctx->i32, "");
7013 }
7014 }
7015
7016 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
7017 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
7018 return false;
7019 }
7020
7021 si_llvm_build_ret(ctx, ctx->return_value);
7022 return true;
7023 }
7024
7025 /**
7026 * Compute the VS prolog key, which contains all the information needed to
7027 * build the VS prolog function, and set shader->info bits where needed.
7028 */
7029 static void si_get_vs_prolog_key(struct si_shader *shader,
7030 union si_shader_part_key *key)
7031 {
7032 struct tgsi_shader_info *info = &shader->selector->info;
7033
7034 memset(key, 0, sizeof(*key));
7035 key->vs_prolog.states = shader->key.part.vs.prolog;
7036 key->vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7037 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
7038
7039 /* Set the instanceID flag. */
7040 for (unsigned i = 0; i < info->num_inputs; i++)
7041 if (key->vs_prolog.states.instance_divisors[i])
7042 shader->info.uses_instanceid = true;
7043 }
7044
7045 /**
7046 * Compute the VS epilog key, which contains all the information needed to
7047 * build the VS epilog function, and set the PrimitiveID output offset.
7048 */
7049 static void si_get_vs_epilog_key(struct si_shader *shader,
7050 struct si_vs_epilog_bits *states,
7051 union si_shader_part_key *key)
7052 {
7053 memset(key, 0, sizeof(*key));
7054 key->vs_epilog.states = *states;
7055
7056 /* Set up the PrimitiveID output. */
7057 if (shader->key.part.vs.epilog.export_prim_id) {
7058 unsigned index = shader->selector->info.num_outputs;
7059 unsigned offset = shader->info.nr_param_exports++;
7060
7061 key->vs_epilog.prim_id_param_offset = offset;
7062 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
7063 shader->info.vs_output_param_offset[index] = offset;
7064 }
7065 }
7066
7067 /**
7068 * Compute the PS prolog key, which contains all the information needed to
7069 * build the PS prolog function, and set related bits in shader->config.
7070 */
7071 static void si_get_ps_prolog_key(struct si_shader *shader,
7072 union si_shader_part_key *key,
7073 bool separate_prolog)
7074 {
7075 struct tgsi_shader_info *info = &shader->selector->info;
7076
7077 memset(key, 0, sizeof(*key));
7078 key->ps_prolog.states = shader->key.part.ps.prolog;
7079 key->ps_prolog.colors_read = info->colors_read;
7080 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7081 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
7082 key->ps_prolog.wqm = info->uses_derivatives &&
7083 (key->ps_prolog.colors_read ||
7084 key->ps_prolog.states.force_persp_sample_interp ||
7085 key->ps_prolog.states.force_linear_sample_interp ||
7086 key->ps_prolog.states.force_persp_center_interp ||
7087 key->ps_prolog.states.force_linear_center_interp ||
7088 key->ps_prolog.states.bc_optimize_for_persp ||
7089 key->ps_prolog.states.bc_optimize_for_linear);
7090
7091 if (info->colors_read) {
7092 unsigned *color = shader->selector->color_attr_index;
7093
7094 if (shader->key.part.ps.prolog.color_two_side) {
7095 /* BCOLORs are stored after the last input. */
7096 key->ps_prolog.num_interp_inputs = info->num_inputs;
7097 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
7098 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
7099 }
7100
7101 for (unsigned i = 0; i < 2; i++) {
7102 unsigned interp = info->input_interpolate[color[i]];
7103 unsigned location = info->input_interpolate_loc[color[i]];
7104
7105 if (!(info->colors_read & (0xf << i*4)))
7106 continue;
7107
7108 key->ps_prolog.color_attr_index[i] = color[i];
7109
7110 if (shader->key.part.ps.prolog.flatshade_colors &&
7111 interp == TGSI_INTERPOLATE_COLOR)
7112 interp = TGSI_INTERPOLATE_CONSTANT;
7113
7114 switch (interp) {
7115 case TGSI_INTERPOLATE_CONSTANT:
7116 key->ps_prolog.color_interp_vgpr_index[i] = -1;
7117 break;
7118 case TGSI_INTERPOLATE_PERSPECTIVE:
7119 case TGSI_INTERPOLATE_COLOR:
7120 /* Force the interpolation location for colors here. */
7121 if (shader->key.part.ps.prolog.force_persp_sample_interp)
7122 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7123 if (shader->key.part.ps.prolog.force_persp_center_interp)
7124 location = TGSI_INTERPOLATE_LOC_CENTER;
7125
7126 switch (location) {
7127 case TGSI_INTERPOLATE_LOC_SAMPLE:
7128 key->ps_prolog.color_interp_vgpr_index[i] = 0;
7129 shader->config.spi_ps_input_ena |=
7130 S_0286CC_PERSP_SAMPLE_ENA(1);
7131 break;
7132 case TGSI_INTERPOLATE_LOC_CENTER:
7133 key->ps_prolog.color_interp_vgpr_index[i] = 2;
7134 shader->config.spi_ps_input_ena |=
7135 S_0286CC_PERSP_CENTER_ENA(1);
7136 break;
7137 case TGSI_INTERPOLATE_LOC_CENTROID:
7138 key->ps_prolog.color_interp_vgpr_index[i] = 4;
7139 shader->config.spi_ps_input_ena |=
7140 S_0286CC_PERSP_CENTROID_ENA(1);
7141 break;
7142 default:
7143 assert(0);
7144 }
7145 break;
7146 case TGSI_INTERPOLATE_LINEAR:
7147 /* Force the interpolation location for colors here. */
7148 if (shader->key.part.ps.prolog.force_linear_sample_interp)
7149 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7150 if (shader->key.part.ps.prolog.force_linear_center_interp)
7151 location = TGSI_INTERPOLATE_LOC_CENTER;
7152
7153 /* The VGPR assignment for non-monolithic shaders
7154 * works because InitialPSInputAddr is set on the
7155 * main shader and PERSP_PULL_MODEL is never used.
7156 */
7157 switch (location) {
7158 case TGSI_INTERPOLATE_LOC_SAMPLE:
7159 key->ps_prolog.color_interp_vgpr_index[i] =
7160 separate_prolog ? 6 : 9;
7161 shader->config.spi_ps_input_ena |=
7162 S_0286CC_LINEAR_SAMPLE_ENA(1);
7163 break;
7164 case TGSI_INTERPOLATE_LOC_CENTER:
7165 key->ps_prolog.color_interp_vgpr_index[i] =
7166 separate_prolog ? 8 : 11;
7167 shader->config.spi_ps_input_ena |=
7168 S_0286CC_LINEAR_CENTER_ENA(1);
7169 break;
7170 case TGSI_INTERPOLATE_LOC_CENTROID:
7171 key->ps_prolog.color_interp_vgpr_index[i] =
7172 separate_prolog ? 10 : 13;
7173 shader->config.spi_ps_input_ena |=
7174 S_0286CC_LINEAR_CENTROID_ENA(1);
7175 break;
7176 default:
7177 assert(0);
7178 }
7179 break;
7180 default:
7181 assert(0);
7182 }
7183 }
7184 }
7185 }
7186
7187 /**
7188 * Check whether a PS prolog is required based on the key.
7189 */
7190 static bool si_need_ps_prolog(const union si_shader_part_key *key)
7191 {
7192 return key->ps_prolog.colors_read ||
7193 key->ps_prolog.states.force_persp_sample_interp ||
7194 key->ps_prolog.states.force_linear_sample_interp ||
7195 key->ps_prolog.states.force_persp_center_interp ||
7196 key->ps_prolog.states.force_linear_center_interp ||
7197 key->ps_prolog.states.bc_optimize_for_persp ||
7198 key->ps_prolog.states.bc_optimize_for_linear ||
7199 key->ps_prolog.states.poly_stipple;
7200 }
7201
7202 /**
7203 * Compute the PS epilog key, which contains all the information needed to
7204 * build the PS epilog function.
7205 */
7206 static void si_get_ps_epilog_key(struct si_shader *shader,
7207 union si_shader_part_key *key)
7208 {
7209 struct tgsi_shader_info *info = &shader->selector->info;
7210 memset(key, 0, sizeof(*key));
7211 key->ps_epilog.colors_written = info->colors_written;
7212 key->ps_epilog.writes_z = info->writes_z;
7213 key->ps_epilog.writes_stencil = info->writes_stencil;
7214 key->ps_epilog.writes_samplemask = info->writes_samplemask;
7215 key->ps_epilog.states = shader->key.part.ps.epilog;
7216 }
7217
7218 /**
7219 * Build the GS prolog function. Rotate the input vertices for triangle strips
7220 * with adjacency.
7221 */
7222 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
7223 union si_shader_part_key *key)
7224 {
7225 const unsigned num_sgprs = SI_GS_NUM_USER_SGPR + 2;
7226 const unsigned num_vgprs = 8;
7227 struct gallivm_state *gallivm = &ctx->gallivm;
7228 LLVMBuilderRef builder = gallivm->builder;
7229 LLVMTypeRef params[32];
7230 LLVMTypeRef returns[32];
7231 LLVMValueRef func, ret;
7232
7233 for (unsigned i = 0; i < num_sgprs; ++i) {
7234 params[i] = ctx->i32;
7235 returns[i] = ctx->i32;
7236 }
7237
7238 for (unsigned i = 0; i < num_vgprs; ++i) {
7239 params[num_sgprs + i] = ctx->i32;
7240 returns[num_sgprs + i] = ctx->f32;
7241 }
7242
7243 /* Create the function. */
7244 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
7245 params, num_sgprs + num_vgprs, num_sgprs - 1);
7246 func = ctx->main_fn;
7247
7248 /* Copy inputs to outputs. This should be no-op, as the registers match,
7249 * but it will prevent the compiler from overwriting them unintentionally.
7250 */
7251 ret = ctx->return_value;
7252 for (unsigned i = 0; i < num_sgprs; i++) {
7253 LLVMValueRef p = LLVMGetParam(func, i);
7254 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
7255 }
7256 for (unsigned i = 0; i < num_vgprs; i++) {
7257 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
7258 p = LLVMBuildBitCast(builder, p, ctx->f32, "");
7259 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
7260 }
7261
7262 if (key->gs_prolog.states.tri_strip_adj_fix) {
7263 /* Remap the input vertices for every other primitive. */
7264 const unsigned vtx_params[6] = {
7265 num_sgprs,
7266 num_sgprs + 1,
7267 num_sgprs + 3,
7268 num_sgprs + 4,
7269 num_sgprs + 5,
7270 num_sgprs + 6
7271 };
7272 LLVMValueRef prim_id, rotate;
7273
7274 prim_id = LLVMGetParam(func, num_sgprs + 2);
7275 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
7276
7277 for (unsigned i = 0; i < 6; ++i) {
7278 LLVMValueRef base, rotated, actual;
7279 base = LLVMGetParam(func, vtx_params[i]);
7280 rotated = LLVMGetParam(func, vtx_params[(i + 4) % 6]);
7281 actual = LLVMBuildSelect(builder, rotate, rotated, base, "");
7282 actual = LLVMBuildBitCast(builder, actual, ctx->f32, "");
7283 ret = LLVMBuildInsertValue(builder, ret, actual, vtx_params[i], "");
7284 }
7285 }
7286
7287 LLVMBuildRet(builder, ret);
7288 }
7289
7290 /**
7291 * Given a list of shader part functions, build a wrapper function that
7292 * runs them in sequence to form a monolithic shader.
7293 */
7294 static void si_build_wrapper_function(struct si_shader_context *ctx,
7295 LLVMValueRef *parts,
7296 unsigned num_parts,
7297 unsigned main_part)
7298 {
7299 struct gallivm_state *gallivm = &ctx->gallivm;
7300 LLVMBuilderRef builder = ctx->gallivm.builder;
7301 /* PS epilog has one arg per color component */
7302 LLVMTypeRef param_types[48];
7303 LLVMValueRef out[48];
7304 LLVMTypeRef function_type;
7305 unsigned num_params;
7306 unsigned num_out;
7307 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
7308 unsigned num_sgprs, num_vgprs;
7309 unsigned last_sgpr_param;
7310 unsigned gprs;
7311
7312 for (unsigned i = 0; i < num_parts; ++i) {
7313 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
7314 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
7315 }
7316
7317 /* The parameters of the wrapper function correspond to those of the
7318 * first part in terms of SGPRs and VGPRs, but we use the types of the
7319 * main part to get the right types. This is relevant for the
7320 * dereferenceable attribute on descriptor table pointers.
7321 */
7322 num_sgprs = 0;
7323 num_vgprs = 0;
7324
7325 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
7326 num_params = LLVMCountParamTypes(function_type);
7327
7328 for (unsigned i = 0; i < num_params; ++i) {
7329 LLVMValueRef param = LLVMGetParam(parts[0], i);
7330
7331 if (ac_is_sgpr_param(param)) {
7332 assert(num_vgprs == 0);
7333 num_sgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
7334 } else {
7335 num_vgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
7336 }
7337 }
7338 assert(num_vgprs + num_sgprs <= ARRAY_SIZE(param_types));
7339
7340 num_params = 0;
7341 last_sgpr_param = 0;
7342 gprs = 0;
7343 while (gprs < num_sgprs + num_vgprs) {
7344 LLVMValueRef param = LLVMGetParam(parts[main_part], num_params);
7345 unsigned size;
7346
7347 param_types[num_params] = LLVMTypeOf(param);
7348 if (gprs < num_sgprs)
7349 last_sgpr_param = num_params;
7350 size = llvm_get_type_size(param_types[num_params]) / 4;
7351 num_params++;
7352
7353 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
7354 assert(gprs + size <= num_sgprs + num_vgprs &&
7355 (gprs >= num_sgprs || gprs + size <= num_sgprs));
7356
7357 gprs += size;
7358 }
7359
7360 si_create_function(ctx, "wrapper", NULL, 0, param_types, num_params, last_sgpr_param);
7361
7362 /* Record the arguments of the function as if they were an output of
7363 * a previous part.
7364 */
7365 num_out = 0;
7366 num_out_sgpr = 0;
7367
7368 for (unsigned i = 0; i < num_params; ++i) {
7369 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
7370 LLVMTypeRef param_type = LLVMTypeOf(param);
7371 LLVMTypeRef out_type = i <= last_sgpr_param ? ctx->i32 : ctx->f32;
7372 unsigned size = llvm_get_type_size(param_type) / 4;
7373
7374 if (size == 1) {
7375 if (param_type != out_type)
7376 param = LLVMBuildBitCast(builder, param, out_type, "");
7377 out[num_out++] = param;
7378 } else {
7379 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
7380
7381 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7382 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
7383 param_type = ctx->i64;
7384 }
7385
7386 if (param_type != vector_type)
7387 param = LLVMBuildBitCast(builder, param, vector_type, "");
7388
7389 for (unsigned j = 0; j < size; ++j)
7390 out[num_out++] = LLVMBuildExtractElement(
7391 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
7392 }
7393
7394 if (i <= last_sgpr_param)
7395 num_out_sgpr = num_out;
7396 }
7397
7398 /* Now chain the parts. */
7399 for (unsigned part = 0; part < num_parts; ++part) {
7400 LLVMValueRef in[48];
7401 LLVMValueRef ret;
7402 LLVMTypeRef ret_type;
7403 unsigned out_idx = 0;
7404
7405 num_params = LLVMCountParams(parts[part]);
7406 assert(num_params <= ARRAY_SIZE(param_types));
7407
7408 /* Derive arguments for the next part from outputs of the
7409 * previous one.
7410 */
7411 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
7412 LLVMValueRef param;
7413 LLVMTypeRef param_type;
7414 bool is_sgpr;
7415 unsigned param_size;
7416 LLVMValueRef arg = NULL;
7417
7418 param = LLVMGetParam(parts[part], param_idx);
7419 param_type = LLVMTypeOf(param);
7420 param_size = llvm_get_type_size(param_type) / 4;
7421 is_sgpr = ac_is_sgpr_param(param);
7422
7423 if (is_sgpr) {
7424 #if HAVE_LLVM < 0x0400
7425 LLVMRemoveAttribute(param, LLVMByValAttribute);
7426 #else
7427 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
7428 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
7429 #endif
7430 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
7431 }
7432
7433 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
7434 assert(is_sgpr || out_idx >= num_out_sgpr);
7435
7436 if (param_size == 1)
7437 arg = out[out_idx];
7438 else
7439 arg = lp_build_gather_values(gallivm, &out[out_idx], param_size);
7440
7441 if (LLVMTypeOf(arg) != param_type) {
7442 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7443 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
7444 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
7445 } else {
7446 arg = LLVMBuildBitCast(builder, arg, param_type, "");
7447 }
7448 }
7449
7450 in[param_idx] = arg;
7451 out_idx += param_size;
7452 }
7453
7454 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
7455 ret_type = LLVMTypeOf(ret);
7456
7457 /* Extract the returned GPRs. */
7458 num_out = 0;
7459 num_out_sgpr = 0;
7460
7461 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
7462 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
7463
7464 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
7465
7466 for (unsigned i = 0; i < ret_size; ++i) {
7467 LLVMValueRef val =
7468 LLVMBuildExtractValue(builder, ret, i, "");
7469
7470 out[num_out++] = val;
7471
7472 if (LLVMTypeOf(val) == ctx->i32) {
7473 assert(num_out_sgpr + 1 == num_out);
7474 num_out_sgpr = num_out;
7475 }
7476 }
7477 }
7478 }
7479
7480 LLVMBuildRetVoid(builder);
7481 }
7482
7483 int si_compile_tgsi_shader(struct si_screen *sscreen,
7484 LLVMTargetMachineRef tm,
7485 struct si_shader *shader,
7486 bool is_monolithic,
7487 struct pipe_debug_callback *debug)
7488 {
7489 struct si_shader_selector *sel = shader->selector;
7490 struct si_shader_context ctx;
7491 LLVMModuleRef mod;
7492 int r = -1;
7493
7494 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
7495 * conversion fails. */
7496 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
7497 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
7498 tgsi_dump(sel->tokens, 0);
7499 si_dump_streamout(&sel->so);
7500 }
7501
7502 si_init_shader_ctx(&ctx, sscreen, shader, tm);
7503 ctx.separate_prolog = !is_monolithic;
7504
7505 memset(shader->info.vs_output_param_offset, EXP_PARAM_UNDEFINED,
7506 sizeof(shader->info.vs_output_param_offset));
7507
7508 shader->info.uses_instanceid = sel->info.uses_instanceid;
7509
7510 ctx.load_system_value = declare_system_value;
7511
7512 if (!si_compile_tgsi_main(&ctx, shader)) {
7513 si_llvm_dispose(&ctx);
7514 return -1;
7515 }
7516
7517 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
7518 LLVMValueRef parts[3];
7519 bool need_prolog;
7520 bool need_epilog;
7521
7522 need_prolog = sel->info.num_inputs;
7523 need_epilog = !shader->key.as_es && !shader->key.as_ls;
7524
7525 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7526
7527 if (need_prolog) {
7528 union si_shader_part_key prolog_key;
7529 si_get_vs_prolog_key(shader, &prolog_key);
7530 si_build_vs_prolog_function(&ctx, &prolog_key);
7531 parts[0] = ctx.main_fn;
7532 }
7533
7534 if (need_epilog) {
7535 union si_shader_part_key epilog_key;
7536 si_get_vs_epilog_key(shader, &shader->key.part.vs.epilog, &epilog_key);
7537 si_build_vs_epilog_function(&ctx, &epilog_key);
7538 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7539 }
7540
7541 si_build_wrapper_function(&ctx, parts, 1 + need_prolog + need_epilog,
7542 need_prolog ? 1 : 0);
7543 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
7544 LLVMValueRef parts[2];
7545 union si_shader_part_key epilog_key;
7546
7547 parts[0] = ctx.main_fn;
7548
7549 memset(&epilog_key, 0, sizeof(epilog_key));
7550 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7551 si_build_tcs_epilog_function(&ctx, &epilog_key);
7552 parts[1] = ctx.main_fn;
7553
7554 si_build_wrapper_function(&ctx, parts, 2, 0);
7555 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_EVAL &&
7556 !shader->key.as_es) {
7557 LLVMValueRef parts[2];
7558 union si_shader_part_key epilog_key;
7559
7560 parts[0] = ctx.main_fn;
7561
7562 si_get_vs_epilog_key(shader, &shader->key.part.tes.epilog, &epilog_key);
7563 si_build_vs_epilog_function(&ctx, &epilog_key);
7564 parts[1] = ctx.main_fn;
7565
7566 si_build_wrapper_function(&ctx, parts, 2, 0);
7567 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
7568 LLVMValueRef parts[2];
7569 union si_shader_part_key prolog_key;
7570
7571 parts[1] = ctx.main_fn;
7572
7573 memset(&prolog_key, 0, sizeof(prolog_key));
7574 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7575 si_build_gs_prolog_function(&ctx, &prolog_key);
7576 parts[0] = ctx.main_fn;
7577
7578 si_build_wrapper_function(&ctx, parts, 2, 1);
7579 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
7580 LLVMValueRef parts[3];
7581 union si_shader_part_key prolog_key;
7582 union si_shader_part_key epilog_key;
7583 bool need_prolog;
7584
7585 si_get_ps_prolog_key(shader, &prolog_key, false);
7586 need_prolog = si_need_ps_prolog(&prolog_key);
7587
7588 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7589
7590 if (need_prolog) {
7591 si_build_ps_prolog_function(&ctx, &prolog_key);
7592 parts[0] = ctx.main_fn;
7593 }
7594
7595 si_get_ps_epilog_key(shader, &epilog_key);
7596 si_build_ps_epilog_function(&ctx, &epilog_key);
7597 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7598
7599 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2, need_prolog ? 1 : 0);
7600 }
7601
7602 mod = ctx.gallivm.module;
7603
7604 /* Dump LLVM IR before any optimization passes */
7605 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
7606 r600_can_dump_shader(&sscreen->b, ctx.type))
7607 ac_dump_module(mod);
7608
7609 si_llvm_finalize_module(&ctx,
7610 r600_extra_shader_checks(&sscreen->b, ctx.type));
7611
7612 /* Post-optimization transformations and analysis. */
7613 si_eliminate_const_vs_outputs(&ctx);
7614
7615 if ((debug && debug->debug_message) ||
7616 r600_can_dump_shader(&sscreen->b, ctx.type))
7617 si_count_scratch_private_memory(&ctx);
7618
7619 /* Compile to bytecode. */
7620 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
7621 mod, debug, ctx.type, "TGSI shader");
7622 si_llvm_dispose(&ctx);
7623 if (r) {
7624 fprintf(stderr, "LLVM failed to compile shader\n");
7625 return r;
7626 }
7627
7628 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
7629 * LLVM 3.9svn has this bug.
7630 */
7631 if (sel->type == PIPE_SHADER_COMPUTE) {
7632 unsigned wave_size = 64;
7633 unsigned max_vgprs = 256;
7634 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
7635 unsigned max_sgprs_per_wave = 128;
7636 unsigned max_block_threads = si_get_max_workgroup_size(shader);
7637 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
7638 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
7639
7640 max_vgprs = max_vgprs / min_waves_per_simd;
7641 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
7642
7643 if (shader->config.num_sgprs > max_sgprs ||
7644 shader->config.num_vgprs > max_vgprs) {
7645 fprintf(stderr, "LLVM failed to compile a shader correctly: "
7646 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7647 shader->config.num_sgprs, shader->config.num_vgprs,
7648 max_sgprs, max_vgprs);
7649
7650 /* Just terminate the process, because dependent
7651 * shaders can hang due to bad input data, but use
7652 * the env var to allow shader-db to work.
7653 */
7654 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7655 abort();
7656 }
7657 }
7658
7659 /* Add the scratch offset to input SGPRs. */
7660 if (shader->config.scratch_bytes_per_wave)
7661 shader->info.num_input_sgprs += 1; /* scratch byte offset */
7662
7663 /* Calculate the number of fragment input VGPRs. */
7664 if (ctx.type == PIPE_SHADER_FRAGMENT) {
7665 shader->info.num_input_vgprs = 0;
7666 shader->info.face_vgpr_index = -1;
7667
7668 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7669 shader->info.num_input_vgprs += 2;
7670 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
7671 shader->info.num_input_vgprs += 2;
7672 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
7673 shader->info.num_input_vgprs += 2;
7674 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
7675 shader->info.num_input_vgprs += 3;
7676 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7677 shader->info.num_input_vgprs += 2;
7678 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7679 shader->info.num_input_vgprs += 2;
7680 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7681 shader->info.num_input_vgprs += 2;
7682 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7683 shader->info.num_input_vgprs += 1;
7684 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7685 shader->info.num_input_vgprs += 1;
7686 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7687 shader->info.num_input_vgprs += 1;
7688 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7689 shader->info.num_input_vgprs += 1;
7690 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7691 shader->info.num_input_vgprs += 1;
7692 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7693 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7694 shader->info.num_input_vgprs += 1;
7695 }
7696 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
7697 shader->info.num_input_vgprs += 1;
7698 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7699 shader->info.num_input_vgprs += 1;
7700 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7701 shader->info.num_input_vgprs += 1;
7702 }
7703
7704 return 0;
7705 }
7706
7707 /**
7708 * Create, compile and return a shader part (prolog or epilog).
7709 *
7710 * \param sscreen screen
7711 * \param list list of shader parts of the same category
7712 * \param type shader type
7713 * \param key shader part key
7714 * \param prolog whether the part being requested is a prolog
7715 * \param tm LLVM target machine
7716 * \param debug debug callback
7717 * \param build the callback responsible for building the main function
7718 * \return non-NULL on success
7719 */
7720 static struct si_shader_part *
7721 si_get_shader_part(struct si_screen *sscreen,
7722 struct si_shader_part **list,
7723 enum pipe_shader_type type,
7724 bool prolog,
7725 union si_shader_part_key *key,
7726 LLVMTargetMachineRef tm,
7727 struct pipe_debug_callback *debug,
7728 void (*build)(struct si_shader_context *,
7729 union si_shader_part_key *),
7730 const char *name)
7731 {
7732 struct si_shader_part *result;
7733
7734 mtx_lock(&sscreen->shader_parts_mutex);
7735
7736 /* Find existing. */
7737 for (result = *list; result; result = result->next) {
7738 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7739 mtx_unlock(&sscreen->shader_parts_mutex);
7740 return result;
7741 }
7742 }
7743
7744 /* Compile a new one. */
7745 result = CALLOC_STRUCT(si_shader_part);
7746 result->key = *key;
7747
7748 struct si_shader shader = {};
7749 struct si_shader_context ctx;
7750 struct gallivm_state *gallivm = &ctx.gallivm;
7751
7752 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7753 ctx.type = type;
7754
7755 switch (type) {
7756 case PIPE_SHADER_VERTEX:
7757 break;
7758 case PIPE_SHADER_TESS_CTRL:
7759 assert(!prolog);
7760 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7761 break;
7762 case PIPE_SHADER_GEOMETRY:
7763 assert(prolog);
7764 break;
7765 case PIPE_SHADER_FRAGMENT:
7766 if (prolog)
7767 shader.key.part.ps.prolog = key->ps_prolog.states;
7768 else
7769 shader.key.part.ps.epilog = key->ps_epilog.states;
7770 break;
7771 default:
7772 unreachable("bad shader part");
7773 }
7774
7775 build(&ctx, key);
7776
7777 /* Compile. */
7778 si_llvm_finalize_module(&ctx,
7779 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT));
7780
7781 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7782 gallivm->module, debug, ctx.type, name)) {
7783 FREE(result);
7784 result = NULL;
7785 goto out;
7786 }
7787
7788 result->next = *list;
7789 *list = result;
7790
7791 out:
7792 si_llvm_dispose(&ctx);
7793 mtx_unlock(&sscreen->shader_parts_mutex);
7794 return result;
7795 }
7796
7797 /**
7798 * Build the vertex shader prolog function.
7799 *
7800 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7801 * All inputs are returned unmodified. The vertex load indices are
7802 * stored after them, which will be used by the API VS for fetching inputs.
7803 *
7804 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7805 * input_v0,
7806 * input_v1,
7807 * input_v2,
7808 * input_v3,
7809 * (VertexID + BaseVertex),
7810 * (InstanceID + StartInstance),
7811 * (InstanceID / 2 + StartInstance)
7812 */
7813 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7814 union si_shader_part_key *key)
7815 {
7816 struct gallivm_state *gallivm = &ctx->gallivm;
7817 LLVMTypeRef *params, *returns;
7818 LLVMValueRef ret, func;
7819 int last_sgpr, num_params, num_returns, i;
7820
7821 ctx->param_vertex_id = key->vs_prolog.num_input_sgprs;
7822 ctx->param_instance_id = key->vs_prolog.num_input_sgprs + 3;
7823
7824 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7825 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
7826 sizeof(LLVMTypeRef));
7827 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
7828 key->vs_prolog.last_input + 1) *
7829 sizeof(LLVMTypeRef));
7830 num_params = 0;
7831 num_returns = 0;
7832
7833 /* Declare input and output SGPRs. */
7834 num_params = 0;
7835 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7836 params[num_params++] = ctx->i32;
7837 returns[num_returns++] = ctx->i32;
7838 }
7839 last_sgpr = num_params - 1;
7840
7841 /* 4 preloaded VGPRs (outputs must be floats) */
7842 for (i = 0; i < 4; i++) {
7843 params[num_params++] = ctx->i32;
7844 returns[num_returns++] = ctx->f32;
7845 }
7846
7847 /* Vertex load indices. */
7848 for (i = 0; i <= key->vs_prolog.last_input; i++)
7849 returns[num_returns++] = ctx->f32;
7850
7851 /* Create the function. */
7852 si_create_function(ctx, "vs_prolog", returns, num_returns, params,
7853 num_params, last_sgpr);
7854 func = ctx->main_fn;
7855
7856 /* Copy inputs to outputs. This should be no-op, as the registers match,
7857 * but it will prevent the compiler from overwriting them unintentionally.
7858 */
7859 ret = ctx->return_value;
7860 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7861 LLVMValueRef p = LLVMGetParam(func, i);
7862 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7863 }
7864 for (i = num_params - 4; i < num_params; i++) {
7865 LLVMValueRef p = LLVMGetParam(func, i);
7866 p = LLVMBuildBitCast(gallivm->builder, p, ctx->f32, "");
7867 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7868 }
7869
7870 /* Compute vertex load indices from instance divisors. */
7871 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7872 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
7873 LLVMValueRef index;
7874
7875 if (divisor) {
7876 /* InstanceID / Divisor + StartInstance */
7877 index = get_instance_index_for_fetch(ctx,
7878 SI_SGPR_START_INSTANCE,
7879 divisor);
7880 } else {
7881 /* VertexID + BaseVertex */
7882 index = LLVMBuildAdd(gallivm->builder,
7883 LLVMGetParam(func, ctx->param_vertex_id),
7884 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
7885 }
7886
7887 index = LLVMBuildBitCast(gallivm->builder, index, ctx->f32, "");
7888 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
7889 num_params++, "");
7890 }
7891
7892 si_llvm_build_ret(ctx, ret);
7893 }
7894
7895 /**
7896 * Build the vertex shader epilog function. This is also used by the tessellation
7897 * evaluation shader compiled as VS.
7898 *
7899 * The input is PrimitiveID.
7900 *
7901 * If PrimitiveID is required by the pixel shader, export it.
7902 * Otherwise, do nothing.
7903 */
7904 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
7905 union si_shader_part_key *key)
7906 {
7907 struct gallivm_state *gallivm = &ctx->gallivm;
7908 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7909 LLVMTypeRef params[5];
7910 int num_params, i;
7911
7912 /* Declare input VGPRs. */
7913 num_params = key->vs_epilog.states.export_prim_id ?
7914 (VS_EPILOG_PRIMID_LOC + 1) : 0;
7915 assert(num_params <= ARRAY_SIZE(params));
7916
7917 for (i = 0; i < num_params; i++)
7918 params[i] = ctx->f32;
7919
7920 /* Create the function. */
7921 si_create_function(ctx, "vs_epilog", NULL, 0, params, num_params, -1);
7922
7923 /* Emit exports. */
7924 if (key->vs_epilog.states.export_prim_id) {
7925 struct lp_build_context *base = &bld_base->base;
7926 struct ac_export_args args;
7927
7928 args.enabled_channels = 0x1; /* enabled channels */
7929 args.valid_mask = 0; /* whether the EXEC mask is valid */
7930 args.done = 0; /* DONE bit */
7931 args.target = V_008DFC_SQ_EXP_PARAM +
7932 key->vs_epilog.prim_id_param_offset;
7933 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
7934 args.out[0] = LLVMGetParam(ctx->main_fn,
7935 VS_EPILOG_PRIMID_LOC); /* X */
7936 args.out[1] = base->undef; /* Y */
7937 args.out[2] = base->undef; /* Z */
7938 args.out[3] = base->undef; /* W */
7939
7940 ac_build_export(&ctx->ac, &args);
7941 }
7942
7943 LLVMBuildRetVoid(gallivm->builder);
7944 }
7945
7946 /**
7947 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7948 */
7949 static bool si_get_vs_epilog(struct si_screen *sscreen,
7950 LLVMTargetMachineRef tm,
7951 struct si_shader *shader,
7952 struct pipe_debug_callback *debug,
7953 struct si_vs_epilog_bits *states)
7954 {
7955 union si_shader_part_key epilog_key;
7956
7957 si_get_vs_epilog_key(shader, states, &epilog_key);
7958
7959 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
7960 PIPE_SHADER_VERTEX, true,
7961 &epilog_key, tm, debug,
7962 si_build_vs_epilog_function,
7963 "Vertex Shader Epilog");
7964 return shader->epilog != NULL;
7965 }
7966
7967 /**
7968 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7969 */
7970 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7971 LLVMTargetMachineRef tm,
7972 struct si_shader *shader,
7973 struct pipe_debug_callback *debug)
7974 {
7975 struct tgsi_shader_info *info = &shader->selector->info;
7976 union si_shader_part_key prolog_key;
7977
7978 /* Get the prolog. */
7979 si_get_vs_prolog_key(shader, &prolog_key);
7980
7981 /* The prolog is a no-op if there are no inputs. */
7982 if (info->num_inputs) {
7983 shader->prolog =
7984 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7985 PIPE_SHADER_VERTEX, true,
7986 &prolog_key, tm, debug,
7987 si_build_vs_prolog_function,
7988 "Vertex Shader Prolog");
7989 if (!shader->prolog)
7990 return false;
7991 }
7992
7993 /* Get the epilog. */
7994 if (!shader->key.as_es && !shader->key.as_ls &&
7995 !si_get_vs_epilog(sscreen, tm, shader, debug,
7996 &shader->key.part.vs.epilog))
7997 return false;
7998
7999 return true;
8000 }
8001
8002 /**
8003 * Select and compile (or reuse) TES parts (epilog).
8004 */
8005 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
8006 LLVMTargetMachineRef tm,
8007 struct si_shader *shader,
8008 struct pipe_debug_callback *debug)
8009 {
8010 if (shader->key.as_es)
8011 return true;
8012
8013 /* TES compiled as VS. */
8014 return si_get_vs_epilog(sscreen, tm, shader, debug,
8015 &shader->key.part.tes.epilog);
8016 }
8017
8018 /**
8019 * Compile the TCS epilog function. This writes tesselation factors to memory
8020 * based on the output primitive type of the tesselator (determined by TES).
8021 */
8022 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
8023 union si_shader_part_key *key)
8024 {
8025 struct gallivm_state *gallivm = &ctx->gallivm;
8026 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
8027 LLVMTypeRef params[16];
8028 LLVMValueRef func;
8029 int last_sgpr, num_params;
8030
8031 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
8032 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
8033 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
8034 params[SI_PARAM_SAMPLERS] = ctx->i64;
8035 params[SI_PARAM_IMAGES] = ctx->i64;
8036 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
8037 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
8038 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
8039 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
8040 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
8041 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
8042 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
8043 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
8044 num_params = last_sgpr + 1;
8045
8046 params[num_params++] = ctx->i32; /* patch index within the wave (REL_PATCH_ID) */
8047 params[num_params++] = ctx->i32; /* invocation ID within the patch */
8048 params[num_params++] = ctx->i32; /* LDS offset where tess factors should be loaded from */
8049
8050 /* Create the function. */
8051 si_create_function(ctx, "tcs_epilog", NULL, 0, params, num_params, last_sgpr);
8052 declare_tess_lds(ctx);
8053 func = ctx->main_fn;
8054
8055 si_write_tess_factors(bld_base,
8056 LLVMGetParam(func, last_sgpr + 1),
8057 LLVMGetParam(func, last_sgpr + 2),
8058 LLVMGetParam(func, last_sgpr + 3));
8059
8060 LLVMBuildRetVoid(gallivm->builder);
8061 }
8062
8063 /**
8064 * Select and compile (or reuse) TCS parts (epilog).
8065 */
8066 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
8067 LLVMTargetMachineRef tm,
8068 struct si_shader *shader,
8069 struct pipe_debug_callback *debug)
8070 {
8071 union si_shader_part_key epilog_key;
8072
8073 /* Get the epilog. */
8074 memset(&epilog_key, 0, sizeof(epilog_key));
8075 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
8076
8077 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
8078 PIPE_SHADER_TESS_CTRL, false,
8079 &epilog_key, tm, debug,
8080 si_build_tcs_epilog_function,
8081 "Tessellation Control Shader Epilog");
8082 return shader->epilog != NULL;
8083 }
8084
8085 /**
8086 * Select and compile (or reuse) GS parts (prolog).
8087 */
8088 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
8089 LLVMTargetMachineRef tm,
8090 struct si_shader *shader,
8091 struct pipe_debug_callback *debug)
8092 {
8093 union si_shader_part_key prolog_key;
8094
8095 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
8096 return true;
8097
8098 memset(&prolog_key, 0, sizeof(prolog_key));
8099 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
8100
8101 shader->prolog = si_get_shader_part(sscreen, &sscreen->gs_prologs,
8102 PIPE_SHADER_GEOMETRY, true,
8103 &prolog_key, tm, debug,
8104 si_build_gs_prolog_function,
8105 "Geometry Shader Prolog");
8106 return shader->prolog != NULL;
8107 }
8108
8109 /**
8110 * Build the pixel shader prolog function. This handles:
8111 * - two-side color selection and interpolation
8112 * - overriding interpolation parameters for the API PS
8113 * - polygon stippling
8114 *
8115 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
8116 * overriden by other states. (e.g. per-sample interpolation)
8117 * Interpolated colors are stored after the preloaded VGPRs.
8118 */
8119 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
8120 union si_shader_part_key *key)
8121 {
8122 struct gallivm_state *gallivm = &ctx->gallivm;
8123 LLVMTypeRef *params;
8124 LLVMValueRef ret, func;
8125 int last_sgpr, num_params, num_returns, i, num_color_channels;
8126
8127 assert(si_need_ps_prolog(key));
8128
8129 /* Number of inputs + 8 color elements. */
8130 params = alloca((key->ps_prolog.num_input_sgprs +
8131 key->ps_prolog.num_input_vgprs + 8) *
8132 sizeof(LLVMTypeRef));
8133
8134 /* Declare inputs. */
8135 num_params = 0;
8136 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
8137 params[num_params++] = ctx->i32;
8138 last_sgpr = num_params - 1;
8139
8140 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
8141 params[num_params++] = ctx->f32;
8142
8143 /* Declare outputs (same as inputs + add colors if needed) */
8144 num_returns = num_params;
8145 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
8146 for (i = 0; i < num_color_channels; i++)
8147 params[num_returns++] = ctx->f32;
8148
8149 /* Create the function. */
8150 si_create_function(ctx, "ps_prolog", params, num_returns, params,
8151 num_params, last_sgpr);
8152 func = ctx->main_fn;
8153
8154 /* Copy inputs to outputs. This should be no-op, as the registers match,
8155 * but it will prevent the compiler from overwriting them unintentionally.
8156 */
8157 ret = ctx->return_value;
8158 for (i = 0; i < num_params; i++) {
8159 LLVMValueRef p = LLVMGetParam(func, i);
8160 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
8161 }
8162
8163 /* Polygon stippling. */
8164 if (key->ps_prolog.states.poly_stipple) {
8165 /* POS_FIXED_PT is always last. */
8166 unsigned pos = key->ps_prolog.num_input_sgprs +
8167 key->ps_prolog.num_input_vgprs - 1;
8168 LLVMValueRef ptr[2], list;
8169
8170 /* Get the pointer to rw buffers. */
8171 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
8172 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
8173 list = lp_build_gather_values(gallivm, ptr, 2);
8174 list = LLVMBuildBitCast(gallivm->builder, list, ctx->i64, "");
8175 list = LLVMBuildIntToPtr(gallivm->builder, list,
8176 const_array(ctx->v16i8, SI_NUM_RW_BUFFERS), "");
8177
8178 si_llvm_emit_polygon_stipple(ctx, list, pos);
8179 }
8180
8181 if (key->ps_prolog.states.bc_optimize_for_persp ||
8182 key->ps_prolog.states.bc_optimize_for_linear) {
8183 unsigned i, base = key->ps_prolog.num_input_sgprs;
8184 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
8185
8186 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
8187 * The hw doesn't compute CENTROID if the whole wave only
8188 * contains fully-covered quads.
8189 *
8190 * PRIM_MASK is after user SGPRs.
8191 */
8192 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
8193 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
8194 LLVMConstInt(ctx->i32, 31, 0), "");
8195 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
8196 ctx->i1, "");
8197
8198 if (key->ps_prolog.states.bc_optimize_for_persp) {
8199 /* Read PERSP_CENTER. */
8200 for (i = 0; i < 2; i++)
8201 center[i] = LLVMGetParam(func, base + 2 + i);
8202 /* Read PERSP_CENTROID. */
8203 for (i = 0; i < 2; i++)
8204 centroid[i] = LLVMGetParam(func, base + 4 + i);
8205 /* Select PERSP_CENTROID. */
8206 for (i = 0; i < 2; i++) {
8207 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
8208 center[i], centroid[i], "");
8209 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8210 tmp, base + 4 + i, "");
8211 }
8212 }
8213 if (key->ps_prolog.states.bc_optimize_for_linear) {
8214 /* Read LINEAR_CENTER. */
8215 for (i = 0; i < 2; i++)
8216 center[i] = LLVMGetParam(func, base + 8 + i);
8217 /* Read LINEAR_CENTROID. */
8218 for (i = 0; i < 2; i++)
8219 centroid[i] = LLVMGetParam(func, base + 10 + i);
8220 /* Select LINEAR_CENTROID. */
8221 for (i = 0; i < 2; i++) {
8222 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
8223 center[i], centroid[i], "");
8224 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8225 tmp, base + 10 + i, "");
8226 }
8227 }
8228 }
8229
8230 /* Force per-sample interpolation. */
8231 if (key->ps_prolog.states.force_persp_sample_interp) {
8232 unsigned i, base = key->ps_prolog.num_input_sgprs;
8233 LLVMValueRef persp_sample[2];
8234
8235 /* Read PERSP_SAMPLE. */
8236 for (i = 0; i < 2; i++)
8237 persp_sample[i] = LLVMGetParam(func, base + i);
8238 /* Overwrite PERSP_CENTER. */
8239 for (i = 0; i < 2; i++)
8240 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8241 persp_sample[i], base + 2 + i, "");
8242 /* Overwrite PERSP_CENTROID. */
8243 for (i = 0; i < 2; i++)
8244 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8245 persp_sample[i], base + 4 + i, "");
8246 }
8247 if (key->ps_prolog.states.force_linear_sample_interp) {
8248 unsigned i, base = key->ps_prolog.num_input_sgprs;
8249 LLVMValueRef linear_sample[2];
8250
8251 /* Read LINEAR_SAMPLE. */
8252 for (i = 0; i < 2; i++)
8253 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
8254 /* Overwrite LINEAR_CENTER. */
8255 for (i = 0; i < 2; i++)
8256 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8257 linear_sample[i], base + 8 + i, "");
8258 /* Overwrite LINEAR_CENTROID. */
8259 for (i = 0; i < 2; i++)
8260 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8261 linear_sample[i], base + 10 + i, "");
8262 }
8263
8264 /* Force center interpolation. */
8265 if (key->ps_prolog.states.force_persp_center_interp) {
8266 unsigned i, base = key->ps_prolog.num_input_sgprs;
8267 LLVMValueRef persp_center[2];
8268
8269 /* Read PERSP_CENTER. */
8270 for (i = 0; i < 2; i++)
8271 persp_center[i] = LLVMGetParam(func, base + 2 + i);
8272 /* Overwrite PERSP_SAMPLE. */
8273 for (i = 0; i < 2; i++)
8274 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8275 persp_center[i], base + i, "");
8276 /* Overwrite PERSP_CENTROID. */
8277 for (i = 0; i < 2; i++)
8278 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8279 persp_center[i], base + 4 + i, "");
8280 }
8281 if (key->ps_prolog.states.force_linear_center_interp) {
8282 unsigned i, base = key->ps_prolog.num_input_sgprs;
8283 LLVMValueRef linear_center[2];
8284
8285 /* Read LINEAR_CENTER. */
8286 for (i = 0; i < 2; i++)
8287 linear_center[i] = LLVMGetParam(func, base + 8 + i);
8288 /* Overwrite LINEAR_SAMPLE. */
8289 for (i = 0; i < 2; i++)
8290 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8291 linear_center[i], base + 6 + i, "");
8292 /* Overwrite LINEAR_CENTROID. */
8293 for (i = 0; i < 2; i++)
8294 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8295 linear_center[i], base + 10 + i, "");
8296 }
8297
8298 /* Interpolate colors. */
8299 for (i = 0; i < 2; i++) {
8300 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
8301 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
8302 key->ps_prolog.face_vgpr_index;
8303 LLVMValueRef interp[2], color[4];
8304 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
8305
8306 if (!writemask)
8307 continue;
8308
8309 /* If the interpolation qualifier is not CONSTANT (-1). */
8310 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
8311 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
8312 key->ps_prolog.color_interp_vgpr_index[i];
8313
8314 /* Get the (i,j) updated by bc_optimize handling. */
8315 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
8316 interp_vgpr, "");
8317 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
8318 interp_vgpr + 1, "");
8319 interp_ij = lp_build_gather_values(gallivm, interp, 2);
8320 }
8321
8322 /* Use the absolute location of the input. */
8323 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
8324
8325 if (key->ps_prolog.states.color_two_side) {
8326 face = LLVMGetParam(func, face_vgpr);
8327 face = LLVMBuildBitCast(gallivm->builder, face, ctx->i32, "");
8328 }
8329
8330 interp_fs_input(ctx,
8331 key->ps_prolog.color_attr_index[i],
8332 TGSI_SEMANTIC_COLOR, i,
8333 key->ps_prolog.num_interp_inputs,
8334 key->ps_prolog.colors_read, interp_ij,
8335 prim_mask, face, color);
8336
8337 while (writemask) {
8338 unsigned chan = u_bit_scan(&writemask);
8339 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
8340 num_params++, "");
8341 }
8342 }
8343
8344 /* Tell LLVM to insert WQM instruction sequence when needed. */
8345 if (key->ps_prolog.wqm) {
8346 LLVMAddTargetDependentFunctionAttr(func,
8347 "amdgpu-ps-wqm-outputs", "");
8348 }
8349
8350 si_llvm_build_ret(ctx, ret);
8351 }
8352
8353 /**
8354 * Build the pixel shader epilog function. This handles everything that must be
8355 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
8356 */
8357 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
8358 union si_shader_part_key *key)
8359 {
8360 struct gallivm_state *gallivm = &ctx->gallivm;
8361 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
8362 LLVMTypeRef params[16+8*4+3];
8363 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
8364 int last_sgpr, num_params, i;
8365 struct si_ps_exports exp = {};
8366
8367 /* Declare input SGPRs. */
8368 params[SI_PARAM_RW_BUFFERS] = ctx->i64;
8369 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
8370 params[SI_PARAM_SAMPLERS] = ctx->i64;
8371 params[SI_PARAM_IMAGES] = ctx->i64;
8372 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
8373 params[SI_PARAM_ALPHA_REF] = ctx->f32;
8374 last_sgpr = SI_PARAM_ALPHA_REF;
8375
8376 /* Declare input VGPRs. */
8377 num_params = (last_sgpr + 1) +
8378 util_bitcount(key->ps_epilog.colors_written) * 4 +
8379 key->ps_epilog.writes_z +
8380 key->ps_epilog.writes_stencil +
8381 key->ps_epilog.writes_samplemask;
8382
8383 num_params = MAX2(num_params,
8384 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
8385
8386 assert(num_params <= ARRAY_SIZE(params));
8387
8388 for (i = last_sgpr + 1; i < num_params; i++)
8389 params[i] = ctx->f32;
8390
8391 /* Create the function. */
8392 si_create_function(ctx, "ps_epilog", NULL, 0, params, num_params, last_sgpr);
8393 /* Disable elimination of unused inputs. */
8394 si_llvm_add_attribute(ctx->main_fn,
8395 "InitialPSInputAddr", 0xffffff);
8396
8397 /* Process colors. */
8398 unsigned vgpr = last_sgpr + 1;
8399 unsigned colors_written = key->ps_epilog.colors_written;
8400 int last_color_export = -1;
8401
8402 /* Find the last color export. */
8403 if (!key->ps_epilog.writes_z &&
8404 !key->ps_epilog.writes_stencil &&
8405 !key->ps_epilog.writes_samplemask) {
8406 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
8407
8408 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
8409 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
8410 /* Just set this if any of the colorbuffers are enabled. */
8411 if (spi_format &
8412 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
8413 last_color_export = 0;
8414 } else {
8415 for (i = 0; i < 8; i++)
8416 if (colors_written & (1 << i) &&
8417 (spi_format >> (i * 4)) & 0xf)
8418 last_color_export = i;
8419 }
8420 }
8421
8422 while (colors_written) {
8423 LLVMValueRef color[4];
8424 int mrt = u_bit_scan(&colors_written);
8425
8426 for (i = 0; i < 4; i++)
8427 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
8428
8429 si_export_mrt_color(bld_base, color, mrt,
8430 num_params - 1,
8431 mrt == last_color_export, &exp);
8432 }
8433
8434 /* Process depth, stencil, samplemask. */
8435 if (key->ps_epilog.writes_z)
8436 depth = LLVMGetParam(ctx->main_fn, vgpr++);
8437 if (key->ps_epilog.writes_stencil)
8438 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
8439 if (key->ps_epilog.writes_samplemask)
8440 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
8441
8442 if (depth || stencil || samplemask)
8443 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
8444 else if (last_color_export == -1)
8445 si_export_null(bld_base);
8446
8447 if (exp.num)
8448 si_emit_ps_exports(ctx, &exp);
8449
8450 /* Compile. */
8451 LLVMBuildRetVoid(gallivm->builder);
8452 }
8453
8454 /**
8455 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
8456 */
8457 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
8458 LLVMTargetMachineRef tm,
8459 struct si_shader *shader,
8460 struct pipe_debug_callback *debug)
8461 {
8462 union si_shader_part_key prolog_key;
8463 union si_shader_part_key epilog_key;
8464
8465 /* Get the prolog. */
8466 si_get_ps_prolog_key(shader, &prolog_key, true);
8467
8468 /* The prolog is a no-op if these aren't set. */
8469 if (si_need_ps_prolog(&prolog_key)) {
8470 shader->prolog =
8471 si_get_shader_part(sscreen, &sscreen->ps_prologs,
8472 PIPE_SHADER_FRAGMENT, true,
8473 &prolog_key, tm, debug,
8474 si_build_ps_prolog_function,
8475 "Fragment Shader Prolog");
8476 if (!shader->prolog)
8477 return false;
8478 }
8479
8480 /* Get the epilog. */
8481 si_get_ps_epilog_key(shader, &epilog_key);
8482
8483 shader->epilog =
8484 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
8485 PIPE_SHADER_FRAGMENT, false,
8486 &epilog_key, tm, debug,
8487 si_build_ps_epilog_function,
8488 "Fragment Shader Epilog");
8489 if (!shader->epilog)
8490 return false;
8491
8492 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
8493 if (shader->key.part.ps.prolog.poly_stipple) {
8494 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
8495 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
8496 }
8497
8498 /* Set up the enable bits for per-sample shading if needed. */
8499 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
8500 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8501 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8502 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
8503 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8504 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
8505 }
8506 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
8507 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8508 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8509 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
8510 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8511 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
8512 }
8513 if (shader->key.part.ps.prolog.force_persp_center_interp &&
8514 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8515 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8516 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
8517 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8518 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8519 }
8520 if (shader->key.part.ps.prolog.force_linear_center_interp &&
8521 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8522 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8523 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
8524 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8525 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8526 }
8527
8528 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
8529 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
8530 !(shader->config.spi_ps_input_ena & 0xf)) {
8531 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8532 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
8533 }
8534
8535 /* At least one pair of interpolation weights must be enabled. */
8536 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
8537 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8538 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
8539 }
8540
8541 /* The sample mask input is always enabled, because the API shader always
8542 * passes it through to the epilog. Disable it here if it's unused.
8543 */
8544 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
8545 !shader->selector->info.reads_samplemask)
8546 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
8547
8548 return true;
8549 }
8550
8551 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
8552 unsigned *lds_size)
8553 {
8554 /* SPI barrier management bug:
8555 * Make sure we have at least 4k of LDS in use to avoid the bug.
8556 * It applies to workgroup sizes of more than one wavefront.
8557 */
8558 if (sscreen->b.family == CHIP_BONAIRE ||
8559 sscreen->b.family == CHIP_KABINI ||
8560 sscreen->b.family == CHIP_MULLINS)
8561 *lds_size = MAX2(*lds_size, 8);
8562 }
8563
8564 static void si_fix_resource_usage(struct si_screen *sscreen,
8565 struct si_shader *shader)
8566 {
8567 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
8568
8569 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
8570
8571 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
8572 si_get_max_workgroup_size(shader) > 64) {
8573 si_multiwave_lds_size_workaround(sscreen,
8574 &shader->config.lds_size);
8575 }
8576 }
8577
8578 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
8579 struct si_shader *shader,
8580 struct pipe_debug_callback *debug)
8581 {
8582 struct si_shader_selector *sel = shader->selector;
8583 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
8584 int r;
8585
8586 /* LS, ES, VS are compiled on demand if the main part hasn't been
8587 * compiled for that stage.
8588 *
8589 * Vertex shaders are compiled on demand when a vertex fetch
8590 * workaround must be applied.
8591 */
8592 if (shader->is_monolithic) {
8593 /* Monolithic shader (compiled as a whole, has many variants,
8594 * may take a long time to compile).
8595 */
8596 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
8597 if (r)
8598 return r;
8599 } else {
8600 /* The shader consists of 2-3 parts:
8601 *
8602 * - the middle part is the user shader, it has 1 variant only
8603 * and it was compiled during the creation of the shader
8604 * selector
8605 * - the prolog part is inserted at the beginning
8606 * - the epilog part is inserted at the end
8607 *
8608 * The prolog and epilog have many (but simple) variants.
8609 */
8610
8611 /* Copy the compiled TGSI shader data over. */
8612 shader->is_binary_shared = true;
8613 shader->binary = mainp->binary;
8614 shader->config = mainp->config;
8615 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8616 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8617 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8618 memcpy(shader->info.vs_output_param_offset,
8619 mainp->info.vs_output_param_offset,
8620 sizeof(mainp->info.vs_output_param_offset));
8621 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8622 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8623 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8624
8625 /* Select prologs and/or epilogs. */
8626 switch (sel->type) {
8627 case PIPE_SHADER_VERTEX:
8628 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
8629 return -1;
8630 break;
8631 case PIPE_SHADER_TESS_CTRL:
8632 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
8633 return -1;
8634 break;
8635 case PIPE_SHADER_TESS_EVAL:
8636 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
8637 return -1;
8638 break;
8639 case PIPE_SHADER_GEOMETRY:
8640 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
8641 return -1;
8642 break;
8643 case PIPE_SHADER_FRAGMENT:
8644 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8645 return -1;
8646
8647 /* Make sure we have at least as many VGPRs as there
8648 * are allocated inputs.
8649 */
8650 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8651 shader->info.num_input_vgprs);
8652 break;
8653 }
8654
8655 /* Update SGPR and VGPR counts. */
8656 if (shader->prolog) {
8657 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8658 shader->prolog->config.num_sgprs);
8659 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8660 shader->prolog->config.num_vgprs);
8661 }
8662 if (shader->epilog) {
8663 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8664 shader->epilog->config.num_sgprs);
8665 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8666 shader->epilog->config.num_vgprs);
8667 }
8668 }
8669
8670 si_fix_resource_usage(sscreen, shader);
8671 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8672 stderr, true);
8673
8674 /* Upload. */
8675 r = si_shader_binary_upload(sscreen, shader);
8676 if (r) {
8677 fprintf(stderr, "LLVM failed to upload shader\n");
8678 return r;
8679 }
8680
8681 return 0;
8682 }
8683
8684 void si_shader_destroy(struct si_shader *shader)
8685 {
8686 if (shader->scratch_bo)
8687 r600_resource_reference(&shader->scratch_bo, NULL);
8688
8689 r600_resource_reference(&shader->bo, NULL);
8690
8691 if (!shader->is_binary_shared)
8692 radeon_shader_binary_clean(&shader->binary);
8693
8694 free(shader->shader_log);
8695 }