projects / mesa.git / blob
? search:


1bd617fa147a20634b62a5d6d560cd2c3cefab4e
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_dump.h"
45
46 #include "si_pipe.h"
47 #include "si_shader.h"
48 #include "sid.h"
49
50 #include <errno.h>
51
52 static const char *scratch_rsrc_dword0_symbol =
53 "SCRATCH_RSRC_DWORD0";
54
55 static const char *scratch_rsrc_dword1_symbol =
56 "SCRATCH_RSRC_DWORD1";
57
58 struct si_shader_output_values
59 {
60 LLVMValueRef values[4];
61 unsigned name;
62 unsigned sid;
63 };
64
65 struct si_shader_context
66 {
67 struct radeon_llvm_context radeon_bld;
68 struct si_shader *shader;
69 struct si_screen *screen;
70 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
71 int param_streamout_config;
72 int param_streamout_write_index;
73 int param_streamout_offset[4];
74 int param_vertex_id;
75 int param_rel_auto_id;
76 int param_vs_prim_id;
77 int param_instance_id;
78 int param_tes_u;
79 int param_tes_v;
80 int param_tes_rel_patch_id;
81 int param_tes_patch_id;
82 int param_es2gs_offset;
83 LLVMTargetMachineRef tm;
84 LLVMValueRef const_md;
85 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
86 LLVMValueRef lds;
87 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
88 LLVMValueRef sampler_views[SI_NUM_SAMPLER_VIEWS];
89 LLVMValueRef sampler_states[SI_NUM_SAMPLER_STATES];
90 LLVMValueRef so_buffers[4];
91 LLVMValueRef esgs_ring;
92 LLVMValueRef gsvs_ring[4];
93 LLVMValueRef gs_next_vertex[4];
94 };
95
96 static struct si_shader_context * si_shader_context(
97 struct lp_build_tgsi_context * bld_base)
98 {
99 return (struct si_shader_context *)bld_base;
100 }
101
102
103 #define PERSPECTIVE_BASE 0
104 #define LINEAR_BASE 9
105
106 #define SAMPLE_OFFSET 0
107 #define CENTER_OFFSET 2
108 #define CENTROID_OFSET 4
109
110 #define USE_SGPR_MAX_SUFFIX_LEN 5
111 #define CONST_ADDR_SPACE 2
112 #define LOCAL_ADDR_SPACE 3
113 #define USER_SGPR_ADDR_SPACE 8
114
115
116 #define SENDMSG_GS 2
117 #define SENDMSG_GS_DONE 3
118
119 #define SENDMSG_GS_OP_NOP (0 << 4)
120 #define SENDMSG_GS_OP_CUT (1 << 4)
121 #define SENDMSG_GS_OP_EMIT (2 << 4)
122 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
123
124 /**
125 * Returns a unique index for a semantic name and index. The index must be
126 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
127 * calculated.
128 */
129 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
130 {
131 switch (semantic_name) {
132 case TGSI_SEMANTIC_POSITION:
133 return 0;
134 case TGSI_SEMANTIC_PSIZE:
135 return 1;
136 case TGSI_SEMANTIC_CLIPDIST:
137 assert(index <= 1);
138 return 2 + index;
139 case TGSI_SEMANTIC_GENERIC:
140 if (index <= 63-4)
141 return 4 + index;
142 else
143 /* same explanation as in the default statement,
144 * the only user hitting this is st/nine.
145 */
146 return 0;
147
148 /* patch indices are completely separate and thus start from 0 */
149 case TGSI_SEMANTIC_TESSOUTER:
150 return 0;
151 case TGSI_SEMANTIC_TESSINNER:
152 return 1;
153 case TGSI_SEMANTIC_PATCH:
154 return 2 + index;
155
156 default:
157 /* Don't fail here. The result of this function is only used
158 * for LS, TCS, TES, and GS, where legacy GL semantics can't
159 * occur, but this function is called for all vertex shaders
160 * before it's known whether LS will be compiled or not.
161 */
162 return 0;
163 }
164 }
165
166 /**
167 * Get the value of a shader input parameter and extract a bitfield.
168 */
169 static LLVMValueRef unpack_param(struct si_shader_context *si_shader_ctx,
170 unsigned param, unsigned rshift,
171 unsigned bitwidth)
172 {
173 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
174 LLVMValueRef value = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
175 param);
176
177 if (rshift)
178 value = LLVMBuildLShr(gallivm->builder, value,
179 lp_build_const_int32(gallivm, rshift), "");
180
181 if (rshift + bitwidth < 32) {
182 unsigned mask = (1 << bitwidth) - 1;
183 value = LLVMBuildAnd(gallivm->builder, value,
184 lp_build_const_int32(gallivm, mask), "");
185 }
186
187 return value;
188 }
189
190 static LLVMValueRef get_rel_patch_id(struct si_shader_context *si_shader_ctx)
191 {
192 switch (si_shader_ctx->type) {
193 case TGSI_PROCESSOR_TESS_CTRL:
194 return unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 0, 8);
195
196 case TGSI_PROCESSOR_TESS_EVAL:
197 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
198 si_shader_ctx->param_tes_rel_patch_id);
199
200 default:
201 assert(0);
202 return NULL;
203 }
204 }
205
206 /* Tessellation shaders pass outputs to the next shader using LDS.
207 *
208 * LS outputs = TCS inputs
209 * TCS outputs = TES inputs
210 *
211 * The LDS layout is:
212 * - TCS inputs for patch 0
213 * - TCS inputs for patch 1
214 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
215 * - ...
216 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
217 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
218 * - TCS outputs for patch 1
219 * - Per-patch TCS outputs for patch 1
220 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
221 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
222 * - ...
223 *
224 * All three shaders VS(LS), TCS, TES share the same LDS space.
225 */
226
227 static LLVMValueRef
228 get_tcs_in_patch_stride(struct si_shader_context *si_shader_ctx)
229 {
230 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX)
231 return unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
232 else if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
233 return unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
234 else {
235 assert(0);
236 return NULL;
237 }
238 }
239
240 static LLVMValueRef
241 get_tcs_out_patch_stride(struct si_shader_context *si_shader_ctx)
242 {
243 return unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
244 }
245
246 static LLVMValueRef
247 get_tcs_out_patch0_offset(struct si_shader_context *si_shader_ctx)
248 {
249 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
250 unpack_param(si_shader_ctx,
251 SI_PARAM_TCS_OUT_OFFSETS,
252 0, 16),
253 4);
254 }
255
256 static LLVMValueRef
257 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *si_shader_ctx)
258 {
259 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
260 unpack_param(si_shader_ctx,
261 SI_PARAM_TCS_OUT_OFFSETS,
262 16, 16),
263 4);
264 }
265
266 static LLVMValueRef
267 get_tcs_in_current_patch_offset(struct si_shader_context *si_shader_ctx)
268 {
269 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
270 LLVMValueRef patch_stride = get_tcs_in_patch_stride(si_shader_ctx);
271 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
272
273 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
274 }
275
276 static LLVMValueRef
277 get_tcs_out_current_patch_offset(struct si_shader_context *si_shader_ctx)
278 {
279 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
280 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(si_shader_ctx);
281 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
282 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
283
284 return LLVMBuildAdd(gallivm->builder, patch0_offset,
285 LLVMBuildMul(gallivm->builder, patch_stride,
286 rel_patch_id, ""),
287 "");
288 }
289
290 static LLVMValueRef
291 get_tcs_out_current_patch_data_offset(struct si_shader_context *si_shader_ctx)
292 {
293 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
294 LLVMValueRef patch0_patch_data_offset =
295 get_tcs_out_patch0_patch_data_offset(si_shader_ctx);
296 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
297 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
298
299 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
300 LLVMBuildMul(gallivm->builder, patch_stride,
301 rel_patch_id, ""),
302 "");
303 }
304
305 static void build_indexed_store(struct si_shader_context *si_shader_ctx,
306 LLVMValueRef base_ptr, LLVMValueRef index,
307 LLVMValueRef value)
308 {
309 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
310 struct gallivm_state *gallivm = bld_base->base.gallivm;
311 LLVMValueRef indices[2], pointer;
312
313 indices[0] = bld_base->uint_bld.zero;
314 indices[1] = index;
315
316 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
317 LLVMBuildStore(gallivm->builder, value, pointer);
318 }
319
320 /**
321 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
322 * It's equivalent to doing a load from &base_ptr[index].
323 *
324 * \param base_ptr Where the array starts.
325 * \param index The element index into the array.
326 */
327 static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
328 LLVMValueRef base_ptr, LLVMValueRef index)
329 {
330 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
331 struct gallivm_state *gallivm = bld_base->base.gallivm;
332 LLVMValueRef indices[2], pointer;
333
334 indices[0] = bld_base->uint_bld.zero;
335 indices[1] = index;
336
337 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
338 return LLVMBuildLoad(gallivm->builder, pointer, "");
339 }
340
341 /**
342 * Do a load from &base_ptr[index], but also add a flag that it's loading
343 * a constant.
344 */
345 static LLVMValueRef build_indexed_load_const(
346 struct si_shader_context * si_shader_ctx,
347 LLVMValueRef base_ptr, LLVMValueRef index)
348 {
349 LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
350 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
351 return result;
352 }
353
354 static LLVMValueRef get_instance_index_for_fetch(
355 struct radeon_llvm_context * radeon_bld,
356 unsigned divisor)
357 {
358 struct si_shader_context *si_shader_ctx =
359 si_shader_context(&radeon_bld->soa.bld_base);
360 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
361
362 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
363 si_shader_ctx->param_instance_id);
364
365 /* The division must be done before START_INSTANCE is added. */
366 if (divisor > 1)
367 result = LLVMBuildUDiv(gallivm->builder, result,
368 lp_build_const_int32(gallivm, divisor), "");
369
370 return LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
371 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
372 }
373
374 static void declare_input_vs(
375 struct radeon_llvm_context *radeon_bld,
376 unsigned input_index,
377 const struct tgsi_full_declaration *decl)
378 {
379 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
380 struct gallivm_state *gallivm = base->gallivm;
381 struct si_shader_context *si_shader_ctx =
382 si_shader_context(&radeon_bld->soa.bld_base);
383 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
384
385 unsigned chan;
386
387 LLVMValueRef t_list_ptr;
388 LLVMValueRef t_offset;
389 LLVMValueRef t_list;
390 LLVMValueRef attribute_offset;
391 LLVMValueRef buffer_index;
392 LLVMValueRef args[3];
393 LLVMTypeRef vec4_type;
394 LLVMValueRef input;
395
396 /* Load the T list */
397 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
398
399 t_offset = lp_build_const_int32(gallivm, input_index);
400
401 t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
402
403 /* Build the attribute offset */
404 attribute_offset = lp_build_const_int32(gallivm, 0);
405
406 if (divisor) {
407 /* Build index from instance ID, start instance and divisor */
408 si_shader_ctx->shader->uses_instanceid = true;
409 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
410 } else {
411 /* Load the buffer index for vertices. */
412 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
413 si_shader_ctx->param_vertex_id);
414 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
415 SI_PARAM_BASE_VERTEX);
416 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
417 }
418
419 vec4_type = LLVMVectorType(base->elem_type, 4);
420 args[0] = t_list;
421 args[1] = attribute_offset;
422 args[2] = buffer_index;
423 input = lp_build_intrinsic(gallivm->builder,
424 "llvm.SI.vs.load.input", vec4_type, args, 3,
425 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
426
427 /* Break up the vec4 into individual components */
428 for (chan = 0; chan < 4; chan++) {
429 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
430 /* XXX: Use a helper function for this. There is one in
431 * tgsi_llvm.c. */
432 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
433 LLVMBuildExtractElement(gallivm->builder,
434 input, llvm_chan, "");
435 }
436 }
437
438 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
439 unsigned swizzle)
440 {
441 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
442
443 if (swizzle > 0)
444 return bld_base->uint_bld.zero;
445
446 switch (si_shader_ctx->type) {
447 case TGSI_PROCESSOR_VERTEX:
448 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
449 si_shader_ctx->param_vs_prim_id);
450 case TGSI_PROCESSOR_TESS_CTRL:
451 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
452 SI_PARAM_PATCH_ID);
453 case TGSI_PROCESSOR_TESS_EVAL:
454 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
455 si_shader_ctx->param_tes_patch_id);
456 case TGSI_PROCESSOR_GEOMETRY:
457 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
458 SI_PARAM_PRIMITIVE_ID);
459 default:
460 assert(0);
461 return bld_base->uint_bld.zero;
462 }
463 }
464
465 /**
466 * Return the value of tgsi_ind_register for indexing.
467 * This is the indirect index with the constant offset added to it.
468 */
469 static LLVMValueRef get_indirect_index(struct si_shader_context *si_shader_ctx,
470 const struct tgsi_ind_register *ind,
471 int rel_index)
472 {
473 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
474 LLVMValueRef result;
475
476 result = si_shader_ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
477 result = LLVMBuildLoad(gallivm->builder, result, "");
478 result = LLVMBuildAdd(gallivm->builder, result,
479 lp_build_const_int32(gallivm, rel_index), "");
480 return result;
481 }
482
483 /**
484 * Calculate a dword address given an input or output register and a stride.
485 */
486 static LLVMValueRef get_dw_address(struct si_shader_context *si_shader_ctx,
487 const struct tgsi_full_dst_register *dst,
488 const struct tgsi_full_src_register *src,
489 LLVMValueRef vertex_dw_stride,
490 LLVMValueRef base_addr)
491 {
492 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
493 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
494 ubyte *name, *index, *array_first;
495 int first, param;
496 struct tgsi_full_dst_register reg;
497
498 /* Set the register description. The address computation is the same
499 * for sources and destinations. */
500 if (src) {
501 reg.Register.File = src->Register.File;
502 reg.Register.Index = src->Register.Index;
503 reg.Register.Indirect = src->Register.Indirect;
504 reg.Register.Dimension = src->Register.Dimension;
505 reg.Indirect = src->Indirect;
506 reg.Dimension = src->Dimension;
507 reg.DimIndirect = src->DimIndirect;
508 } else
509 reg = *dst;
510
511 /* If the register is 2-dimensional (e.g. an array of vertices
512 * in a primitive), calculate the base address of the vertex. */
513 if (reg.Register.Dimension) {
514 LLVMValueRef index;
515
516 if (reg.Dimension.Indirect)
517 index = get_indirect_index(si_shader_ctx, &reg.DimIndirect,
518 reg.Dimension.Index);
519 else
520 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
521
522 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
523 LLVMBuildMul(gallivm->builder, index,
524 vertex_dw_stride, ""), "");
525 }
526
527 /* Get information about the register. */
528 if (reg.Register.File == TGSI_FILE_INPUT) {
529 name = info->input_semantic_name;
530 index = info->input_semantic_index;
531 array_first = info->input_array_first;
532 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
533 name = info->output_semantic_name;
534 index = info->output_semantic_index;
535 array_first = info->output_array_first;
536 } else {
537 assert(0);
538 return NULL;
539 }
540
541 if (reg.Register.Indirect) {
542 /* Add the relative address of the element. */
543 LLVMValueRef ind_index;
544
545 if (reg.Indirect.ArrayID)
546 first = array_first[reg.Indirect.ArrayID];
547 else
548 first = reg.Register.Index;
549
550 ind_index = get_indirect_index(si_shader_ctx, &reg.Indirect,
551 reg.Register.Index - first);
552
553 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
554 LLVMBuildMul(gallivm->builder, ind_index,
555 lp_build_const_int32(gallivm, 4), ""), "");
556
557 param = si_shader_io_get_unique_index(name[first], index[first]);
558 } else {
559 param = si_shader_io_get_unique_index(name[reg.Register.Index],
560 index[reg.Register.Index]);
561 }
562
563 /* Add the base address of the element. */
564 return LLVMBuildAdd(gallivm->builder, base_addr,
565 lp_build_const_int32(gallivm, param * 4), "");
566 }
567
568 /**
569 * Load from LDS.
570 *
571 * \param type output value type
572 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
573 * \param dw_addr address in dwords
574 */
575 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
576 enum tgsi_opcode_type type, unsigned swizzle,
577 LLVMValueRef dw_addr)
578 {
579 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
580 struct gallivm_state *gallivm = bld_base->base.gallivm;
581 LLVMValueRef value;
582
583 if (swizzle == ~0) {
584 LLVMValueRef values[TGSI_NUM_CHANNELS];
585
586 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
587 values[chan] = lds_load(bld_base, type, chan, dw_addr);
588
589 return lp_build_gather_values(bld_base->base.gallivm, values,
590 TGSI_NUM_CHANNELS);
591 }
592
593 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
594 lp_build_const_int32(gallivm, swizzle));
595
596 value = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
597 if (type == TGSI_TYPE_DOUBLE) {
598 LLVMValueRef value2;
599 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
600 lp_build_const_int32(gallivm, swizzle + 1));
601 value2 = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
602 return radeon_llvm_emit_fetch_double(bld_base, value, value2);
603 }
604
605 return LLVMBuildBitCast(gallivm->builder, value,
606 tgsi2llvmtype(bld_base, type), "");
607 }
608
609 /**
610 * Store to LDS.
611 *
612 * \param swizzle offset (typically 0..3)
613 * \param dw_addr address in dwords
614 * \param value value to store
615 */
616 static void lds_store(struct lp_build_tgsi_context * bld_base,
617 unsigned swizzle, LLVMValueRef dw_addr,
618 LLVMValueRef value)
619 {
620 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
621 struct gallivm_state *gallivm = bld_base->base.gallivm;
622
623 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
624 lp_build_const_int32(gallivm, swizzle));
625
626 value = LLVMBuildBitCast(gallivm->builder, value,
627 LLVMInt32TypeInContext(gallivm->context), "");
628 build_indexed_store(si_shader_ctx, si_shader_ctx->lds,
629 dw_addr, value);
630 }
631
632 static LLVMValueRef fetch_input_tcs(
633 struct lp_build_tgsi_context *bld_base,
634 const struct tgsi_full_src_register *reg,
635 enum tgsi_opcode_type type, unsigned swizzle)
636 {
637 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
638 LLVMValueRef dw_addr, stride;
639
640 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
641 dw_addr = get_tcs_in_current_patch_offset(si_shader_ctx);
642 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
643
644 return lds_load(bld_base, type, swizzle, dw_addr);
645 }
646
647 static LLVMValueRef fetch_output_tcs(
648 struct lp_build_tgsi_context *bld_base,
649 const struct tgsi_full_src_register *reg,
650 enum tgsi_opcode_type type, unsigned swizzle)
651 {
652 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
653 LLVMValueRef dw_addr, stride;
654
655 if (reg->Register.Dimension) {
656 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
657 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
658 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
659 } else {
660 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
661 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
662 }
663
664 return lds_load(bld_base, type, swizzle, dw_addr);
665 }
666
667 static LLVMValueRef fetch_input_tes(
668 struct lp_build_tgsi_context *bld_base,
669 const struct tgsi_full_src_register *reg,
670 enum tgsi_opcode_type type, unsigned swizzle)
671 {
672 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
673 LLVMValueRef dw_addr, stride;
674
675 if (reg->Register.Dimension) {
676 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
677 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
678 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
679 } else {
680 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
681 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
682 }
683
684 return lds_load(bld_base, type, swizzle, dw_addr);
685 }
686
687 static void store_output_tcs(struct lp_build_tgsi_context * bld_base,
688 const struct tgsi_full_instruction * inst,
689 const struct tgsi_opcode_info * info,
690 LLVMValueRef dst[4])
691 {
692 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
693 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
694 unsigned chan_index;
695 LLVMValueRef dw_addr, stride;
696
697 /* Only handle per-patch and per-vertex outputs here.
698 * Vectors will be lowered to scalars and this function will be called again.
699 */
700 if (reg->Register.File != TGSI_FILE_OUTPUT ||
701 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
702 radeon_llvm_emit_store(bld_base, inst, info, dst);
703 return;
704 }
705
706 if (reg->Register.Dimension) {
707 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
708 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
709 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, stride, dw_addr);
710 } else {
711 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
712 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, NULL, dw_addr);
713 }
714
715 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
716 LLVMValueRef value = dst[chan_index];
717
718 if (inst->Instruction.Saturate)
719 value = radeon_llvm_saturate(bld_base, value);
720
721 lds_store(bld_base, chan_index, dw_addr, value);
722 }
723 }
724
725 static LLVMValueRef fetch_input_gs(
726 struct lp_build_tgsi_context *bld_base,
727 const struct tgsi_full_src_register *reg,
728 enum tgsi_opcode_type type,
729 unsigned swizzle)
730 {
731 struct lp_build_context *base = &bld_base->base;
732 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
733 struct si_shader *shader = si_shader_ctx->shader;
734 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
735 struct gallivm_state *gallivm = base->gallivm;
736 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
737 LLVMValueRef vtx_offset;
738 LLVMValueRef args[9];
739 unsigned vtx_offset_param;
740 struct tgsi_shader_info *info = &shader->selector->info;
741 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
742 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
743 unsigned param;
744 LLVMValueRef value;
745
746 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
747 return get_primitive_id(bld_base, swizzle);
748
749 if (!reg->Register.Dimension)
750 return NULL;
751
752 if (swizzle == ~0) {
753 LLVMValueRef values[TGSI_NUM_CHANNELS];
754 unsigned chan;
755 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
756 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
757 }
758 return lp_build_gather_values(bld_base->base.gallivm, values,
759 TGSI_NUM_CHANNELS);
760 }
761
762 /* Get the vertex offset parameter */
763 vtx_offset_param = reg->Dimension.Index;
764 if (vtx_offset_param < 2) {
765 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
766 } else {
767 assert(vtx_offset_param < 6);
768 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
769 }
770 vtx_offset = lp_build_mul_imm(uint,
771 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
772 vtx_offset_param),
773 4);
774
775 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
776 args[0] = si_shader_ctx->esgs_ring;
777 args[1] = vtx_offset;
778 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
779 args[3] = uint->zero;
780 args[4] = uint->one; /* OFFEN */
781 args[5] = uint->zero; /* IDXEN */
782 args[6] = uint->one; /* GLC */
783 args[7] = uint->zero; /* SLC */
784 args[8] = uint->zero; /* TFE */
785
786 value = lp_build_intrinsic(gallivm->builder,
787 "llvm.SI.buffer.load.dword.i32.i32",
788 i32, args, 9,
789 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
790 if (type == TGSI_TYPE_DOUBLE) {
791 LLVMValueRef value2;
792 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
793 value2 = lp_build_intrinsic(gallivm->builder,
794 "llvm.SI.buffer.load.dword.i32.i32",
795 i32, args, 9,
796 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
797 return radeon_llvm_emit_fetch_double(bld_base,
798 value, value2);
799 }
800 return LLVMBuildBitCast(gallivm->builder,
801 value,
802 tgsi2llvmtype(bld_base, type), "");
803 }
804
805 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
806 {
807 switch (interpolate) {
808 case TGSI_INTERPOLATE_CONSTANT:
809 return 0;
810
811 case TGSI_INTERPOLATE_LINEAR:
812 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
813 return SI_PARAM_LINEAR_SAMPLE;
814 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
815 return SI_PARAM_LINEAR_CENTROID;
816 else
817 return SI_PARAM_LINEAR_CENTER;
818 break;
819 case TGSI_INTERPOLATE_COLOR:
820 case TGSI_INTERPOLATE_PERSPECTIVE:
821 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
822 return SI_PARAM_PERSP_SAMPLE;
823 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
824 return SI_PARAM_PERSP_CENTROID;
825 else
826 return SI_PARAM_PERSP_CENTER;
827 break;
828 default:
829 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
830 return -1;
831 }
832 }
833
834 /* This shouldn't be used by explicit INTERP opcodes. */
835 static LLVMValueRef get_interp_param(struct si_shader_context *si_shader_ctx,
836 unsigned param)
837 {
838 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
839 unsigned sample_param = 0;
840 LLVMValueRef default_ij, sample_ij, force_sample;
841
842 default_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, param);
843
844 /* If the shader doesn't use center/centroid, just return the parameter.
845 *
846 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
847 * switch between center/centroid and sample without shader changes.
848 */
849 switch (param) {
850 case SI_PARAM_PERSP_CENTROID:
851 case SI_PARAM_PERSP_CENTER:
852 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_persp)
853 return default_ij;
854
855 sample_param = SI_PARAM_PERSP_SAMPLE;
856 break;
857
858 case SI_PARAM_LINEAR_CENTROID:
859 case SI_PARAM_LINEAR_CENTER:
860 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_linear)
861 return default_ij;
862
863 sample_param = SI_PARAM_LINEAR_SAMPLE;
864 break;
865
866 default:
867 return default_ij;
868 }
869
870 /* Otherwise, we have to select (i,j) based on a user data SGPR. */
871 sample_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, sample_param);
872
873 /* TODO: this can be done more efficiently by switching between
874 * 2 prologs.
875 */
876 force_sample = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
877 SI_PARAM_PS_STATE_BITS);
878 force_sample = LLVMBuildTrunc(gallivm->builder, force_sample,
879 LLVMInt1TypeInContext(gallivm->context), "");
880 return LLVMBuildSelect(gallivm->builder, force_sample,
881 sample_ij, default_ij, "");
882 }
883
884 static void declare_input_fs(
885 struct radeon_llvm_context *radeon_bld,
886 unsigned input_index,
887 const struct tgsi_full_declaration *decl)
888 {
889 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
890 struct si_shader_context *si_shader_ctx =
891 si_shader_context(&radeon_bld->soa.bld_base);
892 struct si_shader *shader = si_shader_ctx->shader;
893 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
894 struct gallivm_state *gallivm = base->gallivm;
895 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
896 LLVMValueRef main_fn = radeon_bld->main_fn;
897
898 LLVMValueRef interp_param = NULL;
899 int interp_param_idx;
900 const char * intr_name;
901
902 /* This value is:
903 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
904 * quad begins a new primitive. Bit 0 always needs
905 * to be unset)
906 * [32:16] ParamOffset
907 *
908 */
909 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
910 LLVMValueRef attr_number;
911
912 unsigned chan;
913
914 shader->ps_input_param_offset[input_index] = shader->nparam++;
915 attr_number = lp_build_const_int32(gallivm,
916 shader->ps_input_param_offset[input_index]);
917
918 shader->ps_input_interpolate[input_index] = decl->Interp.Interpolate;
919 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
920 decl->Interp.Location);
921 if (interp_param_idx == -1)
922 return;
923 else if (interp_param_idx)
924 interp_param = get_interp_param(si_shader_ctx, interp_param_idx);
925
926 /* fs.constant returns the param from the middle vertex, so it's not
927 * really useful for flat shading. It's meant to be used for custom
928 * interpolation (but the intrinsic can't fetch from the other two
929 * vertices).
930 *
931 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
932 * to do the right thing. The only reason we use fs.constant is that
933 * fs.interp cannot be used on integers, because they can be equal
934 * to NaN.
935 */
936 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
937
938 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
939 si_shader_ctx->shader->key.ps.color_two_side) {
940 LLVMValueRef args[4];
941 LLVMValueRef face, is_face_positive;
942 LLVMValueRef back_attr_number =
943 lp_build_const_int32(gallivm,
944 shader->ps_input_param_offset[input_index] + 1);
945
946 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
947
948 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
949 face, uint->zero, "");
950
951 args[2] = params;
952 args[3] = interp_param;
953 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
954 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
955 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
956 LLVMValueRef front, back;
957
958 args[0] = llvm_chan;
959 args[1] = attr_number;
960 front = lp_build_intrinsic(gallivm->builder, intr_name,
961 input_type, args, args[3] ? 4 : 3,
962 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
963
964 args[1] = back_attr_number;
965 back = lp_build_intrinsic(gallivm->builder, intr_name,
966 input_type, args, args[3] ? 4 : 3,
967 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
968
969 radeon_bld->inputs[soa_index] =
970 LLVMBuildSelect(gallivm->builder,
971 is_face_positive,
972 front,
973 back,
974 "");
975 }
976
977 shader->nparam++;
978 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
979 LLVMValueRef args[4];
980
981 args[0] = uint->zero;
982 args[1] = attr_number;
983 args[2] = params;
984 args[3] = interp_param;
985 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
986 lp_build_intrinsic(gallivm->builder, intr_name,
987 input_type, args, args[3] ? 4 : 3,
988 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
989 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
990 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
991 lp_build_const_float(gallivm, 0.0f);
992 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
993 lp_build_const_float(gallivm, 1.0f);
994 } else {
995 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
996 LLVMValueRef args[4];
997 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
998 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
999 args[0] = llvm_chan;
1000 args[1] = attr_number;
1001 args[2] = params;
1002 args[3] = interp_param;
1003 radeon_bld->inputs[soa_index] =
1004 lp_build_intrinsic(gallivm->builder, intr_name,
1005 input_type, args, args[3] ? 4 : 3,
1006 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1007 }
1008 }
1009 }
1010
1011 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1012 {
1013 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1014 SI_PARAM_ANCILLARY, 8, 4);
1015 }
1016
1017 /**
1018 * Load a dword from a constant buffer.
1019 */
1020 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1021 LLVMValueRef offset, LLVMTypeRef return_type)
1022 {
1023 LLVMValueRef args[2] = {resource, offset};
1024
1025 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1026 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1027 }
1028
1029 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1030 {
1031 struct si_shader_context *si_shader_ctx =
1032 si_shader_context(&radeon_bld->soa.bld_base);
1033 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1034 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1035 LLVMBuilderRef builder = gallivm->builder;
1036 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1037 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
1038 LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
1039
1040 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1041 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1042 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1043
1044 LLVMValueRef pos[4] = {
1045 buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
1046 buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
1047 lp_build_const_float(gallivm, 0),
1048 lp_build_const_float(gallivm, 0)
1049 };
1050
1051 return lp_build_gather_values(gallivm, pos, 4);
1052 }
1053
1054 static void declare_system_value(
1055 struct radeon_llvm_context * radeon_bld,
1056 unsigned index,
1057 const struct tgsi_full_declaration *decl)
1058 {
1059 struct si_shader_context *si_shader_ctx =
1060 si_shader_context(&radeon_bld->soa.bld_base);
1061 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1062 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1063 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1064 LLVMValueRef value = 0;
1065
1066 switch (decl->Semantic.Name) {
1067 case TGSI_SEMANTIC_INSTANCEID:
1068 value = LLVMGetParam(radeon_bld->main_fn,
1069 si_shader_ctx->param_instance_id);
1070 break;
1071
1072 case TGSI_SEMANTIC_VERTEXID:
1073 value = LLVMBuildAdd(gallivm->builder,
1074 LLVMGetParam(radeon_bld->main_fn,
1075 si_shader_ctx->param_vertex_id),
1076 LLVMGetParam(radeon_bld->main_fn,
1077 SI_PARAM_BASE_VERTEX), "");
1078 break;
1079
1080 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1081 value = LLVMGetParam(radeon_bld->main_fn,
1082 si_shader_ctx->param_vertex_id);
1083 break;
1084
1085 case TGSI_SEMANTIC_BASEVERTEX:
1086 value = LLVMGetParam(radeon_bld->main_fn,
1087 SI_PARAM_BASE_VERTEX);
1088 break;
1089
1090 case TGSI_SEMANTIC_INVOCATIONID:
1091 if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
1092 value = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1093 else if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY)
1094 value = LLVMGetParam(radeon_bld->main_fn,
1095 SI_PARAM_GS_INSTANCE_ID);
1096 else
1097 assert(!"INVOCATIONID not implemented");
1098 break;
1099
1100 case TGSI_SEMANTIC_POSITION:
1101 {
1102 LLVMValueRef pos[4] = {
1103 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1104 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1105 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1106 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1107 LLVMGetParam(radeon_bld->main_fn,
1108 SI_PARAM_POS_W_FLOAT)),
1109 };
1110 value = lp_build_gather_values(gallivm, pos, 4);
1111 break;
1112 }
1113
1114 case TGSI_SEMANTIC_FACE:
1115 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1116 break;
1117
1118 case TGSI_SEMANTIC_SAMPLEID:
1119 value = get_sample_id(radeon_bld);
1120 break;
1121
1122 case TGSI_SEMANTIC_SAMPLEPOS: {
1123 LLVMValueRef pos[4] = {
1124 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1125 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1126 lp_build_const_float(gallivm, 0),
1127 lp_build_const_float(gallivm, 0)
1128 };
1129 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1130 TGSI_OPCODE_FRC, pos[0]);
1131 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1132 TGSI_OPCODE_FRC, pos[1]);
1133 value = lp_build_gather_values(gallivm, pos, 4);
1134 break;
1135 }
1136
1137 case TGSI_SEMANTIC_SAMPLEMASK:
1138 /* Smoothing isn't MSAA in GL, but it's MSAA in hardware.
1139 * Therefore, force gl_SampleMaskIn to 1 for GL. */
1140 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
1141 value = uint_bld->one;
1142 else
1143 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1144 break;
1145
1146 case TGSI_SEMANTIC_TESSCOORD:
1147 {
1148 LLVMValueRef coord[4] = {
1149 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_u),
1150 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_v),
1151 bld->zero,
1152 bld->zero
1153 };
1154
1155 /* For triangles, the vector should be (u, v, 1-u-v). */
1156 if (si_shader_ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1157 PIPE_PRIM_TRIANGLES)
1158 coord[2] = lp_build_sub(bld, bld->one,
1159 lp_build_add(bld, coord[0], coord[1]));
1160
1161 value = lp_build_gather_values(gallivm, coord, 4);
1162 break;
1163 }
1164
1165 case TGSI_SEMANTIC_VERTICESIN:
1166 value = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1167 break;
1168
1169 case TGSI_SEMANTIC_TESSINNER:
1170 case TGSI_SEMANTIC_TESSOUTER:
1171 {
1172 LLVMValueRef dw_addr;
1173 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1174
1175 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1176 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1177 lp_build_const_int32(gallivm, param * 4), "");
1178
1179 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1180 ~0, dw_addr);
1181 break;
1182 }
1183
1184 case TGSI_SEMANTIC_PRIMID:
1185 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1186 break;
1187
1188 default:
1189 assert(!"unknown system value");
1190 return;
1191 }
1192
1193 radeon_bld->system_values[index] = value;
1194 }
1195
1196 static LLVMValueRef fetch_constant(
1197 struct lp_build_tgsi_context * bld_base,
1198 const struct tgsi_full_src_register *reg,
1199 enum tgsi_opcode_type type,
1200 unsigned swizzle)
1201 {
1202 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1203 struct lp_build_context * base = &bld_base->base;
1204 const struct tgsi_ind_register *ireg = &reg->Indirect;
1205 unsigned buf, idx;
1206
1207 LLVMValueRef addr, bufp;
1208 LLVMValueRef result;
1209
1210 if (swizzle == LP_CHAN_ALL) {
1211 unsigned chan;
1212 LLVMValueRef values[4];
1213 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1214 values[chan] = fetch_constant(bld_base, reg, type, chan);
1215
1216 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1217 }
1218
1219 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1220 idx = reg->Register.Index * 4 + swizzle;
1221
1222 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1223 if (type != TGSI_TYPE_DOUBLE)
1224 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
1225 else {
1226 return radeon_llvm_emit_fetch_double(bld_base,
1227 si_shader_ctx->constants[buf][idx],
1228 si_shader_ctx->constants[buf][idx + 1]);
1229 }
1230 }
1231
1232 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1233 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1234 LLVMValueRef index;
1235 index = get_indirect_index(si_shader_ctx, &reg->DimIndirect,
1236 reg->Dimension.Index);
1237 bufp = build_indexed_load_const(si_shader_ctx, ptr, index);
1238 } else
1239 bufp = si_shader_ctx->const_buffers[buf];
1240
1241 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1242 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1243 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1244 addr = lp_build_add(&bld_base->uint_bld, addr,
1245 lp_build_const_int32(base->gallivm, idx * 4));
1246
1247 result = buffer_load_const(base->gallivm->builder, bufp,
1248 addr, bld_base->base.elem_type);
1249
1250 if (type != TGSI_TYPE_DOUBLE)
1251 result = bitcast(bld_base, type, result);
1252 else {
1253 LLVMValueRef addr2, result2;
1254 addr2 = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1255 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1256 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1257 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1258 lp_build_const_int32(base->gallivm, idx * 4));
1259
1260 result2 = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_buffers[buf],
1261 addr2, bld_base->base.elem_type);
1262
1263 result = radeon_llvm_emit_fetch_double(bld_base,
1264 result, result2);
1265 }
1266 return result;
1267 }
1268
1269 /* Upper 16 bits must be zero. */
1270 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1271 LLVMValueRef val[2])
1272 {
1273 return LLVMBuildOr(gallivm->builder, val[0],
1274 LLVMBuildShl(gallivm->builder, val[1],
1275 lp_build_const_int32(gallivm, 16),
1276 ""), "");
1277 }
1278
1279 /* Upper 16 bits are ignored and will be dropped. */
1280 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1281 LLVMValueRef val[2])
1282 {
1283 LLVMValueRef v[2] = {
1284 LLVMBuildAnd(gallivm->builder, val[0],
1285 lp_build_const_int32(gallivm, 0xffff), ""),
1286 val[1],
1287 };
1288 return si_llvm_pack_two_int16(gallivm, v);
1289 }
1290
1291 /* Initialize arguments for the shader export intrinsic */
1292 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1293 LLVMValueRef *values,
1294 unsigned target,
1295 LLVMValueRef *args)
1296 {
1297 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1298 struct lp_build_context *uint =
1299 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1300 struct lp_build_context *base = &bld_base->base;
1301 struct gallivm_state *gallivm = base->gallivm;
1302 LLVMBuilderRef builder = base->gallivm->builder;
1303 LLVMValueRef val[4];
1304 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1305 unsigned chan;
1306 bool is_int8;
1307
1308 /* Default is 0xf. Adjusted below depending on the format. */
1309 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1310
1311 /* Specify whether the EXEC mask represents the valid mask */
1312 args[1] = uint->zero;
1313
1314 /* Specify whether this is the last export */
1315 args[2] = uint->zero;
1316
1317 /* Specify the target we are exporting */
1318 args[3] = lp_build_const_int32(base->gallivm, target);
1319
1320 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
1321 const union si_shader_key *key = &si_shader_ctx->shader->key;
1322 unsigned col_formats = key->ps.spi_shader_col_format;
1323 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1324
1325 assert(cbuf >= 0 && cbuf < 8);
1326 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1327 is_int8 = (key->ps.color_is_int8 >> cbuf) & 0x1;
1328 }
1329
1330 args[4] = uint->zero; /* COMPR flag */
1331 args[5] = base->undef;
1332 args[6] = base->undef;
1333 args[7] = base->undef;
1334 args[8] = base->undef;
1335
1336 switch (spi_shader_col_format) {
1337 case V_028714_SPI_SHADER_ZERO:
1338 args[0] = uint->zero; /* writemask */
1339 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
1340 break;
1341
1342 case V_028714_SPI_SHADER_32_R:
1343 args[0] = uint->one; /* writemask */
1344 args[5] = values[0];
1345 break;
1346
1347 case V_028714_SPI_SHADER_32_GR:
1348 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
1349 args[5] = values[0];
1350 args[6] = values[1];
1351 break;
1352
1353 case V_028714_SPI_SHADER_32_AR:
1354 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
1355 args[5] = values[0];
1356 args[8] = values[3];
1357 break;
1358
1359 case V_028714_SPI_SHADER_FP16_ABGR:
1360 args[4] = uint->one; /* COMPR flag */
1361
1362 for (chan = 0; chan < 2; chan++) {
1363 LLVMValueRef pack_args[2] = {
1364 values[2 * chan],
1365 values[2 * chan + 1]
1366 };
1367 LLVMValueRef packed;
1368
1369 packed = lp_build_intrinsic(base->gallivm->builder,
1370 "llvm.SI.packf16",
1371 uint->elem_type, pack_args, 2,
1372 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1373 args[chan + 5] =
1374 LLVMBuildBitCast(base->gallivm->builder,
1375 packed, base->elem_type, "");
1376 }
1377 break;
1378
1379 case V_028714_SPI_SHADER_UNORM16_ABGR:
1380 for (chan = 0; chan < 4; chan++) {
1381 val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
1382 val[chan] = LLVMBuildFMul(builder, val[chan],
1383 lp_build_const_float(gallivm, 65535), "");
1384 val[chan] = LLVMBuildFAdd(builder, val[chan],
1385 lp_build_const_float(gallivm, 0.5), "");
1386 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1387 uint->elem_type, "");
1388 }
1389
1390 args[4] = uint->one; /* COMPR flag */
1391 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1392 si_llvm_pack_two_int16(gallivm, val));
1393 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1394 si_llvm_pack_two_int16(gallivm, val+2));
1395 break;
1396
1397 case V_028714_SPI_SHADER_SNORM16_ABGR:
1398 for (chan = 0; chan < 4; chan++) {
1399 /* Clamp between [-1, 1]. */
1400 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1401 values[chan],
1402 lp_build_const_float(gallivm, 1));
1403 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1404 val[chan],
1405 lp_build_const_float(gallivm, -1));
1406 /* Convert to a signed integer in [-32767, 32767]. */
1407 val[chan] = LLVMBuildFMul(builder, val[chan],
1408 lp_build_const_float(gallivm, 32767), "");
1409 /* If positive, add 0.5, else add -0.5. */
1410 val[chan] = LLVMBuildFAdd(builder, val[chan],
1411 LLVMBuildSelect(builder,
1412 LLVMBuildFCmp(builder, LLVMRealOGE,
1413 val[chan], base->zero, ""),
1414 lp_build_const_float(gallivm, 0.5),
1415 lp_build_const_float(gallivm, -0.5), ""), "");
1416 val[chan] = LLVMBuildFPToSI(builder, val[chan], uint->elem_type, "");
1417 }
1418
1419 args[4] = uint->one; /* COMPR flag */
1420 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1421 si_llvm_pack_two_int32_as_int16(gallivm, val));
1422 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1423 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1424 break;
1425
1426 case V_028714_SPI_SHADER_UINT16_ABGR: {
1427 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1428 255 : 65535);
1429 /* Clamp. */
1430 for (chan = 0; chan < 4; chan++) {
1431 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1432 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1433 val[chan], max);
1434 }
1435
1436 args[4] = uint->one; /* COMPR flag */
1437 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1438 si_llvm_pack_two_int16(gallivm, val));
1439 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1440 si_llvm_pack_two_int16(gallivm, val+2));
1441 break;
1442 }
1443
1444 case V_028714_SPI_SHADER_SINT16_ABGR: {
1445 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1446 127 : 32767);
1447 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
1448 -128 : -32768);
1449 /* Clamp. */
1450 for (chan = 0; chan < 4; chan++) {
1451 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1452 val[chan] = lp_build_emit_llvm_binary(bld_base,
1453 TGSI_OPCODE_IMIN,
1454 val[chan], max);
1455 val[chan] = lp_build_emit_llvm_binary(bld_base,
1456 TGSI_OPCODE_IMAX,
1457 val[chan], min);
1458 }
1459
1460 args[4] = uint->one; /* COMPR flag */
1461 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1462 si_llvm_pack_two_int32_as_int16(gallivm, val));
1463 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1464 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1465 break;
1466 }
1467
1468 case V_028714_SPI_SHADER_32_ABGR:
1469 memcpy(&args[5], values, sizeof(values[0]) * 4);
1470 break;
1471 }
1472 }
1473
1474 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1475 LLVMValueRef alpha)
1476 {
1477 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1478 struct gallivm_state *gallivm = bld_base->base.gallivm;
1479
1480 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
1481 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1482 SI_PARAM_ALPHA_REF);
1483
1484 LLVMValueRef alpha_pass =
1485 lp_build_cmp(&bld_base->base,
1486 si_shader_ctx->shader->key.ps.alpha_func,
1487 alpha, alpha_ref);
1488 LLVMValueRef arg =
1489 lp_build_select(&bld_base->base,
1490 alpha_pass,
1491 lp_build_const_float(gallivm, 1.0f),
1492 lp_build_const_float(gallivm, -1.0f));
1493
1494 lp_build_intrinsic(gallivm->builder,
1495 "llvm.AMDGPU.kill",
1496 LLVMVoidTypeInContext(gallivm->context),
1497 &arg, 1, 0);
1498 } else {
1499 lp_build_intrinsic(gallivm->builder,
1500 "llvm.AMDGPU.kilp",
1501 LLVMVoidTypeInContext(gallivm->context),
1502 NULL, 0, 0);
1503 }
1504 }
1505
1506 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1507 LLVMValueRef alpha)
1508 {
1509 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1510 struct gallivm_state *gallivm = bld_base->base.gallivm;
1511 LLVMValueRef coverage;
1512
1513 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1514 coverage = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1515 SI_PARAM_SAMPLE_COVERAGE);
1516 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1517
1518 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1519 bld_base->int_bld.elem_type,
1520 &coverage, 1, LLVMReadNoneAttribute);
1521
1522 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1523 bld_base->base.elem_type, "");
1524
1525 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1526 lp_build_const_float(gallivm,
1527 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1528
1529 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1530 }
1531
1532 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
1533 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1534 {
1535 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1536 struct lp_build_context *base = &bld_base->base;
1537 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1538 unsigned reg_index;
1539 unsigned chan;
1540 unsigned const_chan;
1541 LLVMValueRef base_elt;
1542 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1543 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
1544 LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
1545
1546 for (reg_index = 0; reg_index < 2; reg_index ++) {
1547 LLVMValueRef *args = pos[2 + reg_index];
1548
1549 args[5] =
1550 args[6] =
1551 args[7] =
1552 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1553
1554 /* Compute dot products of position and user clip plane vectors */
1555 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1556 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1557 args[1] = lp_build_const_int32(base->gallivm,
1558 ((reg_index * 4 + chan) * 4 +
1559 const_chan) * 4);
1560 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1561 args[1], base->elem_type);
1562 args[5 + chan] =
1563 lp_build_add(base, args[5 + chan],
1564 lp_build_mul(base, base_elt,
1565 out_elts[const_chan]));
1566 }
1567 }
1568
1569 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1570 args[1] = uint->zero;
1571 args[2] = uint->zero;
1572 args[3] = lp_build_const_int32(base->gallivm,
1573 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1574 args[4] = uint->zero;
1575 }
1576 }
1577
1578 static void si_dump_streamout(struct pipe_stream_output_info *so)
1579 {
1580 unsigned i;
1581
1582 if (so->num_outputs)
1583 fprintf(stderr, "STREAMOUT\n");
1584
1585 for (i = 0; i < so->num_outputs; i++) {
1586 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1587 so->output[i].start_component;
1588 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1589 i, so->output[i].output_buffer,
1590 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1591 so->output[i].register_index,
1592 mask & 1 ? "x" : "",
1593 mask & 2 ? "y" : "",
1594 mask & 4 ? "z" : "",
1595 mask & 8 ? "w" : "");
1596 }
1597 }
1598
1599 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1600 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1601 * or v4i32 (num_channels=3,4). */
1602 static void build_tbuffer_store(struct si_shader_context *shader,
1603 LLVMValueRef rsrc,
1604 LLVMValueRef vdata,
1605 unsigned num_channels,
1606 LLVMValueRef vaddr,
1607 LLVMValueRef soffset,
1608 unsigned inst_offset,
1609 unsigned dfmt,
1610 unsigned nfmt,
1611 unsigned offen,
1612 unsigned idxen,
1613 unsigned glc,
1614 unsigned slc,
1615 unsigned tfe)
1616 {
1617 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1618 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1619 LLVMValueRef args[] = {
1620 rsrc,
1621 vdata,
1622 LLVMConstInt(i32, num_channels, 0),
1623 vaddr,
1624 soffset,
1625 LLVMConstInt(i32, inst_offset, 0),
1626 LLVMConstInt(i32, dfmt, 0),
1627 LLVMConstInt(i32, nfmt, 0),
1628 LLVMConstInt(i32, offen, 0),
1629 LLVMConstInt(i32, idxen, 0),
1630 LLVMConstInt(i32, glc, 0),
1631 LLVMConstInt(i32, slc, 0),
1632 LLVMConstInt(i32, tfe, 0)
1633 };
1634
1635 /* The instruction offset field has 12 bits */
1636 assert(offen || inst_offset < (1 << 12));
1637
1638 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1639 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1640 const char *types[] = {"i32", "v2i32", "v4i32"};
1641 char name[256];
1642 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1643
1644 lp_build_intrinsic(gallivm->builder, name,
1645 LLVMVoidTypeInContext(gallivm->context),
1646 args, Elements(args), 0);
1647 }
1648
1649 static void build_tbuffer_store_dwords(struct si_shader_context *shader,
1650 LLVMValueRef rsrc,
1651 LLVMValueRef vdata,
1652 unsigned num_channels,
1653 LLVMValueRef vaddr,
1654 LLVMValueRef soffset,
1655 unsigned inst_offset)
1656 {
1657 static unsigned dfmt[] = {
1658 V_008F0C_BUF_DATA_FORMAT_32,
1659 V_008F0C_BUF_DATA_FORMAT_32_32,
1660 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1661 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1662 };
1663 assert(num_channels >= 1 && num_channels <= 4);
1664
1665 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
1666 inst_offset, dfmt[num_channels-1],
1667 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1668 }
1669
1670 /* On SI, the vertex shader is responsible for writing streamout data
1671 * to buffers. */
1672 static void si_llvm_emit_streamout(struct si_shader_context *shader,
1673 struct si_shader_output_values *outputs,
1674 unsigned noutput)
1675 {
1676 struct pipe_stream_output_info *so = &shader->shader->selector->so;
1677 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1678 LLVMBuilderRef builder = gallivm->builder;
1679 int i, j;
1680 struct lp_build_if_state if_ctx;
1681
1682 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1683
1684 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1685 LLVMValueRef so_vtx_count =
1686 unpack_param(shader, shader->param_streamout_config, 16, 7);
1687
1688 LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", i32,
1689 NULL, 0, LLVMReadNoneAttribute);
1690
1691 /* can_emit = tid < so_vtx_count; */
1692 LLVMValueRef can_emit =
1693 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1694
1695 LLVMValueRef stream_id =
1696 unpack_param(shader, shader->param_streamout_config, 24, 2);
1697
1698 /* Emit the streamout code conditionally. This actually avoids
1699 * out-of-bounds buffer access. The hw tells us via the SGPR
1700 * (so_vtx_count) which threads are allowed to emit streamout data. */
1701 lp_build_if(&if_ctx, gallivm, can_emit);
1702 {
1703 /* The buffer offset is computed as follows:
1704 * ByteOffset = streamout_offset[buffer_id]*4 +
1705 * (streamout_write_index + thread_id)*stride[buffer_id] +
1706 * attrib_offset
1707 */
1708
1709 LLVMValueRef so_write_index =
1710 LLVMGetParam(shader->radeon_bld.main_fn,
1711 shader->param_streamout_write_index);
1712
1713 /* Compute (streamout_write_index + thread_id). */
1714 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1715
1716 /* Compute the write offset for each enabled buffer. */
1717 LLVMValueRef so_write_offset[4] = {};
1718 for (i = 0; i < 4; i++) {
1719 if (!so->stride[i])
1720 continue;
1721
1722 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1723 shader->param_streamout_offset[i]);
1724 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1725
1726 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1727 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1728 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1729 }
1730
1731 /* Write streamout data. */
1732 for (i = 0; i < so->num_outputs; i++) {
1733 unsigned buf_idx = so->output[i].output_buffer;
1734 unsigned reg = so->output[i].register_index;
1735 unsigned start = so->output[i].start_component;
1736 unsigned num_comps = so->output[i].num_components;
1737 unsigned stream = so->output[i].stream;
1738 LLVMValueRef out[4];
1739 struct lp_build_if_state if_ctx_stream;
1740
1741 assert(num_comps && num_comps <= 4);
1742 if (!num_comps || num_comps > 4)
1743 continue;
1744
1745 if (reg >= noutput)
1746 continue;
1747
1748 /* Load the output as int. */
1749 for (j = 0; j < num_comps; j++) {
1750 out[j] = LLVMBuildBitCast(builder,
1751 outputs[reg].values[start+j],
1752 i32, "");
1753 }
1754
1755 /* Pack the output. */
1756 LLVMValueRef vdata = NULL;
1757
1758 switch (num_comps) {
1759 case 1: /* as i32 */
1760 vdata = out[0];
1761 break;
1762 case 2: /* as v2i32 */
1763 case 3: /* as v4i32 (aligned to 4) */
1764 case 4: /* as v4i32 */
1765 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1766 for (j = 0; j < num_comps; j++) {
1767 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1768 LLVMConstInt(i32, j, 0), "");
1769 }
1770 break;
1771 }
1772
1773 LLVMValueRef can_emit_stream =
1774 LLVMBuildICmp(builder, LLVMIntEQ,
1775 stream_id,
1776 lp_build_const_int32(gallivm, stream), "");
1777
1778 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1779 build_tbuffer_store_dwords(shader, shader->so_buffers[buf_idx],
1780 vdata, num_comps,
1781 so_write_offset[buf_idx],
1782 LLVMConstInt(i32, 0, 0),
1783 so->output[i].dst_offset*4);
1784 lp_build_endif(&if_ctx_stream);
1785 }
1786 }
1787 lp_build_endif(&if_ctx);
1788 }
1789
1790
1791 /* Generate export instructions for hardware VS shader stage */
1792 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1793 struct si_shader_output_values *outputs,
1794 unsigned noutput)
1795 {
1796 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1797 struct si_shader * shader = si_shader_ctx->shader;
1798 struct lp_build_context * base = &bld_base->base;
1799 struct lp_build_context * uint =
1800 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1801 LLVMValueRef args[9];
1802 LLVMValueRef pos_args[4][9] = { { 0 } };
1803 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1804 unsigned semantic_name, semantic_index;
1805 unsigned target;
1806 unsigned param_count = 0;
1807 unsigned pos_idx;
1808 int i;
1809
1810 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1811 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1812 }
1813
1814 for (i = 0; i < noutput; i++) {
1815 semantic_name = outputs[i].name;
1816 semantic_index = outputs[i].sid;
1817
1818 handle_semantic:
1819 /* Select the correct target */
1820 switch(semantic_name) {
1821 case TGSI_SEMANTIC_PSIZE:
1822 psize_value = outputs[i].values[0];
1823 continue;
1824 case TGSI_SEMANTIC_EDGEFLAG:
1825 edgeflag_value = outputs[i].values[0];
1826 continue;
1827 case TGSI_SEMANTIC_LAYER:
1828 layer_value = outputs[i].values[0];
1829 semantic_name = TGSI_SEMANTIC_GENERIC;
1830 goto handle_semantic;
1831 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1832 viewport_index_value = outputs[i].values[0];
1833 semantic_name = TGSI_SEMANTIC_GENERIC;
1834 goto handle_semantic;
1835 case TGSI_SEMANTIC_POSITION:
1836 target = V_008DFC_SQ_EXP_POS;
1837 break;
1838 case TGSI_SEMANTIC_COLOR:
1839 case TGSI_SEMANTIC_BCOLOR:
1840 target = V_008DFC_SQ_EXP_PARAM + param_count;
1841 shader->vs_output_param_offset[i] = param_count;
1842 param_count++;
1843 break;
1844 case TGSI_SEMANTIC_CLIPDIST:
1845 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1846 break;
1847 case TGSI_SEMANTIC_CLIPVERTEX:
1848 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1849 continue;
1850 case TGSI_SEMANTIC_PRIMID:
1851 case TGSI_SEMANTIC_FOG:
1852 case TGSI_SEMANTIC_TEXCOORD:
1853 case TGSI_SEMANTIC_GENERIC:
1854 target = V_008DFC_SQ_EXP_PARAM + param_count;
1855 shader->vs_output_param_offset[i] = param_count;
1856 param_count++;
1857 break;
1858 default:
1859 target = 0;
1860 fprintf(stderr,
1861 "Warning: SI unhandled vs output type:%d\n",
1862 semantic_name);
1863 }
1864
1865 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1866
1867 if (target >= V_008DFC_SQ_EXP_POS &&
1868 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1869 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1870 args, sizeof(args));
1871 } else {
1872 lp_build_intrinsic(base->gallivm->builder,
1873 "llvm.SI.export",
1874 LLVMVoidTypeInContext(base->gallivm->context),
1875 args, 9, 0);
1876 }
1877
1878 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1879 semantic_name = TGSI_SEMANTIC_GENERIC;
1880 goto handle_semantic;
1881 }
1882 }
1883
1884 shader->nr_param_exports = param_count;
1885
1886 /* We need to add the position output manually if it's missing. */
1887 if (!pos_args[0][0]) {
1888 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1889 pos_args[0][1] = uint->zero; /* EXEC mask */
1890 pos_args[0][2] = uint->zero; /* last export? */
1891 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1892 pos_args[0][4] = uint->zero; /* COMPR flag */
1893 pos_args[0][5] = base->zero; /* X */
1894 pos_args[0][6] = base->zero; /* Y */
1895 pos_args[0][7] = base->zero; /* Z */
1896 pos_args[0][8] = base->one; /* W */
1897 }
1898
1899 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1900 if (shader->selector->info.writes_psize ||
1901 shader->selector->info.writes_edgeflag ||
1902 shader->selector->info.writes_viewport_index ||
1903 shader->selector->info.writes_layer) {
1904 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1905 shader->selector->info.writes_psize |
1906 (shader->selector->info.writes_edgeflag << 1) |
1907 (shader->selector->info.writes_layer << 2) |
1908 (shader->selector->info.writes_viewport_index << 3));
1909 pos_args[1][1] = uint->zero; /* EXEC mask */
1910 pos_args[1][2] = uint->zero; /* last export? */
1911 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1912 pos_args[1][4] = uint->zero; /* COMPR flag */
1913 pos_args[1][5] = base->zero; /* X */
1914 pos_args[1][6] = base->zero; /* Y */
1915 pos_args[1][7] = base->zero; /* Z */
1916 pos_args[1][8] = base->zero; /* W */
1917
1918 if (shader->selector->info.writes_psize)
1919 pos_args[1][5] = psize_value;
1920
1921 if (shader->selector->info.writes_edgeflag) {
1922 /* The output is a float, but the hw expects an integer
1923 * with the first bit containing the edge flag. */
1924 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1925 edgeflag_value,
1926 bld_base->uint_bld.elem_type, "");
1927 edgeflag_value = lp_build_min(&bld_base->int_bld,
1928 edgeflag_value,
1929 bld_base->int_bld.one);
1930
1931 /* The LLVM intrinsic expects a float. */
1932 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1933 edgeflag_value,
1934 base->elem_type, "");
1935 }
1936
1937 if (shader->selector->info.writes_layer)
1938 pos_args[1][7] = layer_value;
1939
1940 if (shader->selector->info.writes_viewport_index)
1941 pos_args[1][8] = viewport_index_value;
1942 }
1943
1944 for (i = 0; i < 4; i++)
1945 if (pos_args[i][0])
1946 shader->nr_pos_exports++;
1947
1948 pos_idx = 0;
1949 for (i = 0; i < 4; i++) {
1950 if (!pos_args[i][0])
1951 continue;
1952
1953 /* Specify the target we are exporting */
1954 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1955
1956 if (pos_idx == shader->nr_pos_exports)
1957 /* Specify that this is the last export */
1958 pos_args[i][2] = uint->one;
1959
1960 lp_build_intrinsic(base->gallivm->builder,
1961 "llvm.SI.export",
1962 LLVMVoidTypeInContext(base->gallivm->context),
1963 pos_args[i], 9, 0);
1964 }
1965 }
1966
1967 /* This only writes the tessellation factor levels. */
1968 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
1969 {
1970 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1971 struct gallivm_state *gallivm = bld_base->base.gallivm;
1972 struct si_shader *shader = si_shader_ctx->shader;
1973 unsigned tess_inner_index, tess_outer_index;
1974 LLVMValueRef lds_base, lds_inner, lds_outer;
1975 LLVMValueRef tf_base, rel_patch_id, byteoffset, buffer, rw_buffers;
1976 LLVMValueRef out[6], vec0, vec1, invocation_id;
1977 unsigned stride, outer_comps, inner_comps, i;
1978 struct lp_build_if_state if_ctx;
1979
1980 invocation_id = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1981
1982 /* Do this only for invocation 0, because the tess levels are per-patch,
1983 * not per-vertex.
1984 *
1985 * This can't jump, because invocation 0 executes this. It should
1986 * at least mask out the loads and stores for other invocations.
1987 */
1988 lp_build_if(&if_ctx, gallivm,
1989 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
1990 invocation_id, bld_base->uint_bld.zero, ""));
1991
1992 /* Determine the layout of one tess factor element in the buffer. */
1993 switch (shader->key.tcs.prim_mode) {
1994 case PIPE_PRIM_LINES:
1995 stride = 2; /* 2 dwords, 1 vec2 store */
1996 outer_comps = 2;
1997 inner_comps = 0;
1998 break;
1999 case PIPE_PRIM_TRIANGLES:
2000 stride = 4; /* 4 dwords, 1 vec4 store */
2001 outer_comps = 3;
2002 inner_comps = 1;
2003 break;
2004 case PIPE_PRIM_QUADS:
2005 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2006 outer_comps = 4;
2007 inner_comps = 2;
2008 break;
2009 default:
2010 assert(0);
2011 return;
2012 }
2013
2014 /* Load tess_inner and tess_outer from LDS.
2015 * Any invocation can write them, so we can't get them from a temporary.
2016 */
2017 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2018 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2019
2020 lds_base = get_tcs_out_current_patch_data_offset(si_shader_ctx);
2021 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2022 lp_build_const_int32(gallivm,
2023 tess_inner_index * 4), "");
2024 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2025 lp_build_const_int32(gallivm,
2026 tess_outer_index * 4), "");
2027
2028 for (i = 0; i < outer_comps; i++)
2029 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2030 for (i = 0; i < inner_comps; i++)
2031 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2032
2033 /* Convert the outputs to vectors for stores. */
2034 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2035 vec1 = NULL;
2036
2037 if (stride > 4)
2038 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2039
2040 /* Get the buffer. */
2041 rw_buffers = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2042 SI_PARAM_RW_BUFFERS);
2043 buffer = build_indexed_load_const(si_shader_ctx, rw_buffers,
2044 lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR));
2045
2046 /* Get the offset. */
2047 tf_base = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2048 SI_PARAM_TESS_FACTOR_OFFSET);
2049 rel_patch_id = get_rel_patch_id(si_shader_ctx);
2050 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2051 lp_build_const_int32(gallivm, 4 * stride), "");
2052
2053 /* Store the outputs. */
2054 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec0,
2055 MIN2(stride, 4), byteoffset, tf_base, 0);
2056 if (vec1)
2057 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec1,
2058 stride - 4, byteoffset, tf_base, 16);
2059 lp_build_endif(&if_ctx);
2060 }
2061
2062 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context * bld_base)
2063 {
2064 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2065 struct si_shader *shader = si_shader_ctx->shader;
2066 struct tgsi_shader_info *info = &shader->selector->info;
2067 struct gallivm_state *gallivm = bld_base->base.gallivm;
2068 unsigned i, chan;
2069 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2070 si_shader_ctx->param_rel_auto_id);
2071 LLVMValueRef vertex_dw_stride =
2072 unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2073 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2074 vertex_dw_stride, "");
2075
2076 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2077 * its inputs from it. */
2078 for (i = 0; i < info->num_outputs; i++) {
2079 LLVMValueRef *out_ptr = si_shader_ctx->radeon_bld.soa.outputs[i];
2080 unsigned name = info->output_semantic_name[i];
2081 unsigned index = info->output_semantic_index[i];
2082 int param = si_shader_io_get_unique_index(name, index);
2083 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2084 lp_build_const_int32(gallivm, param * 4), "");
2085
2086 for (chan = 0; chan < 4; chan++) {
2087 lds_store(bld_base, chan, dw_addr,
2088 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2089 }
2090 }
2091 }
2092
2093 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
2094 {
2095 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2096 struct gallivm_state *gallivm = bld_base->base.gallivm;
2097 struct si_shader *es = si_shader_ctx->shader;
2098 struct tgsi_shader_info *info = &es->selector->info;
2099 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2100 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2101 si_shader_ctx->param_es2gs_offset);
2102 unsigned chan;
2103 int i;
2104
2105 for (i = 0; i < info->num_outputs; i++) {
2106 LLVMValueRef *out_ptr =
2107 si_shader_ctx->radeon_bld.soa.outputs[i];
2108 int param_index;
2109
2110 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2111 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2112 continue;
2113
2114 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2115 info->output_semantic_index[i]);
2116
2117 for (chan = 0; chan < 4; chan++) {
2118 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2119 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2120
2121 build_tbuffer_store(si_shader_ctx,
2122 si_shader_ctx->esgs_ring,
2123 out_val, 1,
2124 LLVMGetUndef(i32), soffset,
2125 (4 * param_index + chan) * 4,
2126 V_008F0C_BUF_DATA_FORMAT_32,
2127 V_008F0C_BUF_NUM_FORMAT_UINT,
2128 0, 0, 1, 1, 0);
2129 }
2130 }
2131 }
2132
2133 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2134 {
2135 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2136 struct gallivm_state *gallivm = bld_base->base.gallivm;
2137 LLVMValueRef args[2];
2138
2139 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2140 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2141 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2142 LLVMVoidTypeInContext(gallivm->context), args, 2,
2143 LLVMNoUnwindAttribute);
2144 }
2145
2146 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
2147 {
2148 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2149 struct gallivm_state *gallivm = bld_base->base.gallivm;
2150 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
2151 struct si_shader_output_values *outputs = NULL;
2152 int i,j;
2153
2154 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2155
2156 /* Vertex color clamping.
2157 *
2158 * This uses a state constant loaded in a user data SGPR and
2159 * an IF statement is added that clamps all colors if the constant
2160 * is true.
2161 */
2162 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
2163 !si_shader_ctx->shader->is_gs_copy_shader) {
2164 struct lp_build_if_state if_ctx;
2165 LLVMValueRef cond = NULL;
2166 LLVMValueRef addr, val;
2167
2168 for (i = 0; i < info->num_outputs; i++) {
2169 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2170 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2171 continue;
2172
2173 /* We've found a color. */
2174 if (!cond) {
2175 /* The state is in the first bit of the user SGPR. */
2176 cond = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2177 SI_PARAM_VS_STATE_BITS);
2178 cond = LLVMBuildTrunc(gallivm->builder, cond,
2179 LLVMInt1TypeInContext(gallivm->context), "");
2180 lp_build_if(&if_ctx, gallivm, cond);
2181 }
2182
2183 for (j = 0; j < 4; j++) {
2184 addr = si_shader_ctx->radeon_bld.soa.outputs[i][j];
2185 val = LLVMBuildLoad(gallivm->builder, addr, "");
2186 val = radeon_llvm_saturate(bld_base, val);
2187 LLVMBuildStore(gallivm->builder, val, addr);
2188 }
2189 }
2190
2191 if (cond)
2192 lp_build_endif(&if_ctx);
2193 }
2194
2195 for (i = 0; i < info->num_outputs; i++) {
2196 outputs[i].name = info->output_semantic_name[i];
2197 outputs[i].sid = info->output_semantic_index[i];
2198
2199 for (j = 0; j < 4; j++)
2200 outputs[i].values[j] =
2201 LLVMBuildLoad(gallivm->builder,
2202 si_shader_ctx->radeon_bld.soa.outputs[i][j],
2203 "");
2204 }
2205
2206 /* Export PrimitiveID when PS needs it. */
2207 if (si_vs_exports_prim_id(si_shader_ctx->shader)) {
2208 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2209 outputs[i].sid = 0;
2210 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2211 get_primitive_id(bld_base, 0));
2212 outputs[i].values[1] = bld_base->base.undef;
2213 outputs[i].values[2] = bld_base->base.undef;
2214 outputs[i].values[3] = bld_base->base.undef;
2215 i++;
2216 }
2217
2218 si_llvm_export_vs(bld_base, outputs, i);
2219 FREE(outputs);
2220 }
2221
2222 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2223 LLVMValueRef depth, LLVMValueRef stencil,
2224 LLVMValueRef samplemask)
2225 {
2226 struct si_screen *sscreen = si_shader_context(bld_base)->screen;
2227 struct lp_build_context *base = &bld_base->base;
2228 struct lp_build_context *uint = &bld_base->uint_bld;
2229 LLVMValueRef args[9];
2230 unsigned mask = 0;
2231
2232 assert(depth || stencil || samplemask);
2233
2234 args[1] = uint->one; /* whether the EXEC mask is valid */
2235 args[2] = uint->one; /* DONE bit */
2236
2237 /* Specify the target we are exporting */
2238 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2239
2240 args[4] = uint->zero; /* COMP flag */
2241 args[5] = base->undef; /* R, depth */
2242 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2243 args[7] = base->undef; /* B, sample mask */
2244 args[8] = base->undef; /* A, alpha to mask */
2245
2246 if (depth) {
2247 args[5] = depth;
2248 mask |= 0x1;
2249 }
2250
2251 if (stencil) {
2252 args[6] = stencil;
2253 mask |= 0x2;
2254 }
2255
2256 if (samplemask) {
2257 args[7] = samplemask;
2258 mask |= 0x4;
2259 }
2260
2261 /* SI (except OLAND) has a bug that it only looks
2262 * at the X writemask component. */
2263 if (sscreen->b.chip_class == SI &&
2264 sscreen->b.family != CHIP_OLAND)
2265 mask |= 0x1;
2266
2267 /* Specify which components to enable */
2268 args[0] = lp_build_const_int32(base->gallivm, mask);
2269
2270 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2271 LLVMVoidTypeInContext(base->gallivm->context),
2272 args, 9, 0);
2273 }
2274
2275 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2276 LLVMValueRef *color, unsigned index,
2277 bool is_last)
2278 {
2279 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2280 struct lp_build_context *base = &bld_base->base;
2281 LLVMValueRef args[9];
2282 int i;
2283
2284 /* Clamp color */
2285 if (si_shader_ctx->shader->key.ps.clamp_color)
2286 for (i = 0; i < 4; i++)
2287 color[i] = radeon_llvm_saturate(bld_base, color[i]);
2288
2289 /* Alpha to one */
2290 if (si_shader_ctx->shader->key.ps.alpha_to_one)
2291 color[3] = base->one;
2292
2293 /* Alpha test */
2294 if (index == 0 &&
2295 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
2296 si_alpha_test(bld_base, color[3]);
2297
2298 /* Line & polygon smoothing */
2299 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
2300 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3]);
2301
2302 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2303 if (index == 0 &&
2304 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
2305 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
2306 si_llvm_init_export_args(bld_base, color,
2307 V_008DFC_SQ_EXP_MRT + c, args);
2308 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2309 LLVMVoidTypeInContext(base->gallivm->context),
2310 args, 9, 0);
2311 }
2312 }
2313
2314 /* Export */
2315 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2316 args);
2317 if (is_last) {
2318 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2319 args[2] = bld_base->uint_bld.one; /* DONE bit */
2320 }
2321 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2322 LLVMVoidTypeInContext(base->gallivm->context),
2323 args, 9, 0);
2324 }
2325
2326 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2327 {
2328 struct lp_build_context *base = &bld_base->base;
2329 struct lp_build_context *uint = &bld_base->uint_bld;
2330 LLVMValueRef args[9];
2331
2332 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
2333 args[1] = uint->one; /* whether the EXEC mask is valid */
2334 args[2] = uint->one; /* DONE bit */
2335 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2336 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
2337 args[5] = uint->undef; /* R */
2338 args[6] = uint->undef; /* G */
2339 args[7] = uint->undef; /* B */
2340 args[8] = uint->undef; /* A */
2341
2342 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2343 LLVMVoidTypeInContext(base->gallivm->context),
2344 args, 9, 0);
2345 }
2346
2347 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
2348 {
2349 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
2350 struct si_shader * shader = si_shader_ctx->shader;
2351 struct lp_build_context * base = &bld_base->base;
2352 struct tgsi_shader_info *info = &shader->selector->info;
2353 LLVMBuilderRef builder = base->gallivm->builder;
2354 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2355 int last_color_export = -1;
2356 int i;
2357
2358 /* If there are no outputs, add a dummy export. */
2359 if (!info->num_outputs) {
2360 si_export_null(bld_base);
2361 return;
2362 }
2363
2364 /* Determine the last export. If MRTZ is present, it's always last.
2365 * Otherwise, find the last color export.
2366 */
2367 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask)
2368 for (i = 0; i < info->num_outputs; i++)
2369 if (info->output_semantic_name[i] == TGSI_SEMANTIC_COLOR)
2370 last_color_export = i;
2371
2372 for (i = 0; i < info->num_outputs; i++) {
2373 unsigned semantic_name = info->output_semantic_name[i];
2374 unsigned semantic_index = info->output_semantic_index[i];
2375 unsigned j;
2376 LLVMValueRef color[4] = {};
2377
2378 /* Select the correct target */
2379 switch (semantic_name) {
2380 case TGSI_SEMANTIC_POSITION:
2381 depth = LLVMBuildLoad(builder,
2382 si_shader_ctx->radeon_bld.soa.outputs[i][2], "");
2383 break;
2384 case TGSI_SEMANTIC_STENCIL:
2385 stencil = LLVMBuildLoad(builder,
2386 si_shader_ctx->radeon_bld.soa.outputs[i][1], "");
2387 break;
2388 case TGSI_SEMANTIC_SAMPLEMASK:
2389 samplemask = LLVMBuildLoad(builder,
2390 si_shader_ctx->radeon_bld.soa.outputs[i][0], "");
2391 break;
2392 case TGSI_SEMANTIC_COLOR:
2393 for (j = 0; j < 4; j++)
2394 color[j] = LLVMBuildLoad(builder,
2395 si_shader_ctx->radeon_bld.soa.outputs[i][j], "");
2396
2397 si_export_mrt_color(bld_base, color, semantic_index,
2398 last_color_export == i);
2399 break;
2400 default:
2401 fprintf(stderr,
2402 "Warning: SI unhandled fs output type:%d\n",
2403 semantic_name);
2404 }
2405 }
2406
2407 if (depth || stencil || samplemask)
2408 si_export_mrt_z(bld_base, depth, stencil, samplemask);
2409 }
2410
2411 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2412 struct lp_build_tgsi_context * bld_base,
2413 struct lp_build_emit_data * emit_data);
2414
2415 static bool tgsi_is_array_sampler(unsigned target)
2416 {
2417 return target == TGSI_TEXTURE_1D_ARRAY ||
2418 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2419 target == TGSI_TEXTURE_2D_ARRAY ||
2420 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2421 target == TGSI_TEXTURE_CUBE_ARRAY ||
2422 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2423 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2424 }
2425
2426 static void set_tex_fetch_args(struct gallivm_state *gallivm,
2427 struct lp_build_emit_data *emit_data,
2428 unsigned opcode, unsigned target,
2429 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
2430 LLVMValueRef *param, unsigned count,
2431 unsigned dmask)
2432 {
2433 unsigned num_args;
2434 unsigned is_rect = target == TGSI_TEXTURE_RECT;
2435 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2436
2437 /* Pad to power of two vector */
2438 while (count < util_next_power_of_two(count))
2439 param[count++] = LLVMGetUndef(i32);
2440
2441 /* Texture coordinates. */
2442 if (count > 1)
2443 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
2444 else
2445 emit_data->args[0] = param[0];
2446
2447 /* Resource. */
2448 emit_data->args[1] = res_ptr;
2449 num_args = 2;
2450
2451 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
2452 emit_data->dst_type = LLVMVectorType(i32, 4);
2453 else {
2454 emit_data->dst_type = LLVMVectorType(
2455 LLVMFloatTypeInContext(gallivm->context), 4);
2456
2457 emit_data->args[num_args++] = samp_ptr;
2458 }
2459
2460 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
2461 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
2462 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
2463 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
2464 tgsi_is_array_sampler(target)); /* da */
2465 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
2466 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
2467 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
2468 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
2469
2470 emit_data->arg_count = num_args;
2471 }
2472
2473 static const struct lp_build_tgsi_action tex_action;
2474
2475 static void tex_fetch_ptrs(
2476 struct lp_build_tgsi_context * bld_base,
2477 struct lp_build_emit_data * emit_data,
2478 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
2479 {
2480 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2481 struct gallivm_state *gallivm = bld_base->base.gallivm;
2482 const struct tgsi_full_instruction * inst = emit_data->inst;
2483 unsigned target = inst->Texture.Texture;
2484 unsigned sampler_src;
2485 unsigned sampler_index;
2486
2487 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
2488 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
2489
2490 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
2491 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
2492 LLVMValueRef ind_index;
2493
2494 ind_index = get_indirect_index(si_shader_ctx, &reg->Indirect, reg->Register.Index);
2495
2496 *res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
2497 *res_ptr = build_indexed_load_const(si_shader_ctx, *res_ptr, ind_index);
2498
2499 *samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
2500 *samp_ptr = build_indexed_load_const(si_shader_ctx, *samp_ptr, ind_index);
2501
2502 if (target == TGSI_TEXTURE_2D_MSAA ||
2503 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2504 ind_index = LLVMBuildAdd(gallivm->builder, ind_index,
2505 lp_build_const_int32(gallivm,
2506 SI_FMASK_TEX_OFFSET), "");
2507 *fmask_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
2508 *fmask_ptr = build_indexed_load_const(si_shader_ctx, *fmask_ptr, ind_index);
2509 }
2510 } else {
2511 *res_ptr = si_shader_ctx->sampler_views[sampler_index];
2512 *samp_ptr = si_shader_ctx->sampler_states[sampler_index];
2513 *fmask_ptr = si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + sampler_index];
2514 }
2515 }
2516
2517 static void tex_fetch_args(
2518 struct lp_build_tgsi_context * bld_base,
2519 struct lp_build_emit_data * emit_data)
2520 {
2521 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2522 struct gallivm_state *gallivm = bld_base->base.gallivm;
2523 LLVMBuilderRef builder = gallivm->builder;
2524 const struct tgsi_full_instruction * inst = emit_data->inst;
2525 unsigned opcode = inst->Instruction.Opcode;
2526 unsigned target = inst->Texture.Texture;
2527 LLVMValueRef coords[5], derivs[6];
2528 LLVMValueRef address[16];
2529 int ref_pos;
2530 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
2531 unsigned count = 0;
2532 unsigned chan;
2533 unsigned num_deriv_channels = 0;
2534 bool has_offset = inst->Texture.NumOffsets > 0;
2535 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2536 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2537 unsigned dmask = 0xf;
2538
2539 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2540
2541 if (opcode == TGSI_OPCODE_TXQ) {
2542 if (target == TGSI_TEXTURE_BUFFER) {
2543 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2544
2545 /* Read the size from the buffer descriptor directly. */
2546 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2547 LLVMValueRef size = LLVMBuildExtractElement(builder, res,
2548 lp_build_const_int32(gallivm, 6), "");
2549
2550 if (si_shader_ctx->screen->b.chip_class >= VI) {
2551 /* On VI, the descriptor contains the size in bytes,
2552 * but TXQ must return the size in elements.
2553 * The stride is always non-zero for resources using TXQ.
2554 */
2555 LLVMValueRef stride =
2556 LLVMBuildExtractElement(builder, res,
2557 lp_build_const_int32(gallivm, 5), "");
2558 stride = LLVMBuildLShr(builder, stride,
2559 lp_build_const_int32(gallivm, 16), "");
2560 stride = LLVMBuildAnd(builder, stride,
2561 lp_build_const_int32(gallivm, 0x3FFF), "");
2562
2563 size = LLVMBuildUDiv(builder, size, stride, "");
2564 }
2565
2566 emit_data->args[0] = size;
2567 return;
2568 }
2569
2570 /* Textures - set the mip level. */
2571 address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2572
2573 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2574 NULL, address, count, 0xf);
2575 return;
2576 }
2577
2578 if (target == TGSI_TEXTURE_BUFFER) {
2579 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
2580 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
2581 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
2582 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
2583
2584 /* Bitcast and truncate v8i32 to v16i8. */
2585 LLVMValueRef res = res_ptr;
2586 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
2587 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
2588 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
2589
2590 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
2591 emit_data->args[0] = res;
2592 emit_data->args[1] = bld_base->uint_bld.zero;
2593 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
2594 emit_data->arg_count = 3;
2595 return;
2596 }
2597
2598 /* Fetch and project texture coordinates */
2599 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
2600 for (chan = 0; chan < 3; chan++ ) {
2601 coords[chan] = lp_build_emit_fetch(bld_base,
2602 emit_data->inst, 0,
2603 chan);
2604 if (opcode == TGSI_OPCODE_TXP)
2605 coords[chan] = lp_build_emit_llvm_binary(bld_base,
2606 TGSI_OPCODE_DIV,
2607 coords[chan],
2608 coords[3]);
2609 }
2610
2611 if (opcode == TGSI_OPCODE_TXP)
2612 coords[3] = bld_base->base.one;
2613
2614 /* Pack offsets. */
2615 if (has_offset && opcode != TGSI_OPCODE_TXF) {
2616 /* The offsets are six-bit signed integers packed like this:
2617 * X=[5:0], Y=[13:8], and Z=[21:16].
2618 */
2619 LLVMValueRef offset[3], pack;
2620
2621 assert(inst->Texture.NumOffsets == 1);
2622
2623 for (chan = 0; chan < 3; chan++) {
2624 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
2625 emit_data->inst, 0, chan);
2626 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
2627 lp_build_const_int32(gallivm, 0x3f), "");
2628 if (chan)
2629 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
2630 lp_build_const_int32(gallivm, chan*8), "");
2631 }
2632
2633 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
2634 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
2635 address[count++] = pack;
2636 }
2637
2638 /* Pack LOD bias value */
2639 if (opcode == TGSI_OPCODE_TXB)
2640 address[count++] = coords[3];
2641 if (opcode == TGSI_OPCODE_TXB2)
2642 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2643
2644 /* Pack depth comparison value */
2645 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
2646 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2647 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2648 } else {
2649 assert(ref_pos >= 0);
2650 address[count++] = coords[ref_pos];
2651 }
2652 }
2653
2654 /* Pack user derivatives */
2655 if (opcode == TGSI_OPCODE_TXD) {
2656 int param, num_src_deriv_channels;
2657
2658 switch (target) {
2659 case TGSI_TEXTURE_3D:
2660 num_src_deriv_channels = 3;
2661 num_deriv_channels = 3;
2662 break;
2663 case TGSI_TEXTURE_2D:
2664 case TGSI_TEXTURE_SHADOW2D:
2665 case TGSI_TEXTURE_RECT:
2666 case TGSI_TEXTURE_SHADOWRECT:
2667 case TGSI_TEXTURE_2D_ARRAY:
2668 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2669 num_src_deriv_channels = 2;
2670 num_deriv_channels = 2;
2671 break;
2672 case TGSI_TEXTURE_CUBE:
2673 case TGSI_TEXTURE_SHADOWCUBE:
2674 case TGSI_TEXTURE_CUBE_ARRAY:
2675 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
2676 /* Cube derivatives will be converted to 2D. */
2677 num_src_deriv_channels = 3;
2678 num_deriv_channels = 2;
2679 break;
2680 case TGSI_TEXTURE_1D:
2681 case TGSI_TEXTURE_SHADOW1D:
2682 case TGSI_TEXTURE_1D_ARRAY:
2683 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2684 num_src_deriv_channels = 1;
2685 num_deriv_channels = 1;
2686 break;
2687 default:
2688 unreachable("invalid target");
2689 }
2690
2691 for (param = 0; param < 2; param++)
2692 for (chan = 0; chan < num_src_deriv_channels; chan++)
2693 derivs[param * num_src_deriv_channels + chan] =
2694 lp_build_emit_fetch(bld_base, inst, param+1, chan);
2695 }
2696
2697 if (target == TGSI_TEXTURE_CUBE ||
2698 target == TGSI_TEXTURE_CUBE_ARRAY ||
2699 target == TGSI_TEXTURE_SHADOWCUBE ||
2700 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2701 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
2702
2703 if (opcode == TGSI_OPCODE_TXD)
2704 for (int i = 0; i < num_deriv_channels * 2; i++)
2705 address[count++] = derivs[i];
2706
2707 /* Pack texture coordinates */
2708 address[count++] = coords[0];
2709 if (num_coords > 1)
2710 address[count++] = coords[1];
2711 if (num_coords > 2)
2712 address[count++] = coords[2];
2713
2714 /* Pack LOD or sample index */
2715 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
2716 address[count++] = coords[3];
2717 else if (opcode == TGSI_OPCODE_TXL2)
2718 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2719
2720 if (count > 16) {
2721 assert(!"Cannot handle more than 16 texture address parameters");
2722 count = 16;
2723 }
2724
2725 for (chan = 0; chan < count; chan++ ) {
2726 address[chan] = LLVMBuildBitCast(gallivm->builder,
2727 address[chan], i32, "");
2728 }
2729
2730 /* Adjust the sample index according to FMASK.
2731 *
2732 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2733 * which is the identity mapping. Each nibble says which physical sample
2734 * should be fetched to get that sample.
2735 *
2736 * For example, 0x11111100 means there are only 2 samples stored and
2737 * the second sample covers 3/4 of the pixel. When reading samples 0
2738 * and 1, return physical sample 0 (determined by the first two 0s
2739 * in FMASK), otherwise return physical sample 1.
2740 *
2741 * The sample index should be adjusted as follows:
2742 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2743 */
2744 if (target == TGSI_TEXTURE_2D_MSAA ||
2745 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2746 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2747 struct lp_build_emit_data txf_emit_data = *emit_data;
2748 LLVMValueRef txf_address[4];
2749 unsigned txf_count = count;
2750 struct tgsi_full_instruction inst = {};
2751
2752 memcpy(txf_address, address, sizeof(txf_address));
2753
2754 if (target == TGSI_TEXTURE_2D_MSAA) {
2755 txf_address[2] = bld_base->uint_bld.zero;
2756 }
2757 txf_address[3] = bld_base->uint_bld.zero;
2758
2759 /* Read FMASK using TXF. */
2760 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
2761 inst.Texture.Texture = target;
2762 txf_emit_data.inst = &inst;
2763 txf_emit_data.chan = 0;
2764 set_tex_fetch_args(gallivm, &txf_emit_data, TGSI_OPCODE_TXF,
2765 target, fmask_ptr, NULL,
2766 txf_address, txf_count, 0xf);
2767 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
2768
2769 /* Initialize some constants. */
2770 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
2771 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
2772
2773 /* Apply the formula. */
2774 LLVMValueRef fmask =
2775 LLVMBuildExtractElement(gallivm->builder,
2776 txf_emit_data.output[0],
2777 uint_bld->zero, "");
2778
2779 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
2780
2781 LLVMValueRef sample_index4 =
2782 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
2783
2784 LLVMValueRef shifted_fmask =
2785 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
2786
2787 LLVMValueRef final_sample =
2788 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
2789
2790 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2791 * resource descriptor is 0 (invalid),
2792 */
2793 LLVMValueRef fmask_desc =
2794 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
2795 LLVMVectorType(uint_bld->elem_type, 8), "");
2796
2797 LLVMValueRef fmask_word1 =
2798 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
2799 uint_bld->one, "");
2800
2801 LLVMValueRef word1_is_nonzero =
2802 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
2803 fmask_word1, uint_bld->zero, "");
2804
2805 /* Replace the MSAA sample index. */
2806 address[sample_chan] =
2807 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
2808 final_sample, address[sample_chan], "");
2809 }
2810
2811 if (opcode == TGSI_OPCODE_TXF) {
2812 /* add tex offsets */
2813 if (inst->Texture.NumOffsets) {
2814 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2815 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
2816 const struct tgsi_texture_offset * off = inst->TexOffsets;
2817
2818 assert(inst->Texture.NumOffsets == 1);
2819
2820 switch (target) {
2821 case TGSI_TEXTURE_3D:
2822 address[2] = lp_build_add(uint_bld, address[2],
2823 bld->immediates[off->Index][off->SwizzleZ]);
2824 /* fall through */
2825 case TGSI_TEXTURE_2D:
2826 case TGSI_TEXTURE_SHADOW2D:
2827 case TGSI_TEXTURE_RECT:
2828 case TGSI_TEXTURE_SHADOWRECT:
2829 case TGSI_TEXTURE_2D_ARRAY:
2830 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2831 address[1] =
2832 lp_build_add(uint_bld, address[1],
2833 bld->immediates[off->Index][off->SwizzleY]);
2834 /* fall through */
2835 case TGSI_TEXTURE_1D:
2836 case TGSI_TEXTURE_SHADOW1D:
2837 case TGSI_TEXTURE_1D_ARRAY:
2838 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2839 address[0] =
2840 lp_build_add(uint_bld, address[0],
2841 bld->immediates[off->Index][off->SwizzleX]);
2842 break;
2843 /* texture offsets do not apply to other texture targets */
2844 }
2845 }
2846 }
2847
2848 if (opcode == TGSI_OPCODE_TG4) {
2849 unsigned gather_comp = 0;
2850
2851 /* DMASK was repurposed for GATHER4. 4 components are always
2852 * returned and DMASK works like a swizzle - it selects
2853 * the component to fetch. The only valid DMASK values are
2854 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2855 * (red,red,red,red) etc.) The ISA document doesn't mention
2856 * this.
2857 */
2858
2859 /* Get the component index from src1.x for Gather4. */
2860 if (!tgsi_is_shadow_target(target)) {
2861 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
2862 LLVMValueRef comp_imm;
2863 struct tgsi_src_register src1 = inst->Src[1].Register;
2864
2865 assert(src1.File == TGSI_FILE_IMMEDIATE);
2866
2867 comp_imm = imms[src1.Index][src1.SwizzleX];
2868 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
2869 gather_comp = CLAMP(gather_comp, 0, 3);
2870 }
2871
2872 dmask = 1 << gather_comp;
2873 }
2874
2875 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2876 samp_ptr, address, count, dmask);
2877 }
2878
2879 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2880 struct lp_build_tgsi_context * bld_base,
2881 struct lp_build_emit_data * emit_data)
2882 {
2883 struct lp_build_context * base = &bld_base->base;
2884 unsigned opcode = emit_data->inst->Instruction.Opcode;
2885 unsigned target = emit_data->inst->Texture.Texture;
2886 char intr_name[127];
2887 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
2888 bool is_shadow = tgsi_is_shadow_target(target);
2889 char type[64];
2890 const char *name = "llvm.SI.image.sample";
2891 const char *infix = "";
2892
2893 if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
2894 /* Just return the buffer size. */
2895 emit_data->output[emit_data->chan] = emit_data->args[0];
2896 return;
2897 }
2898
2899 if (target == TGSI_TEXTURE_BUFFER) {
2900 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2901 base->gallivm->builder,
2902 "llvm.SI.vs.load.input", emit_data->dst_type,
2903 emit_data->args, emit_data->arg_count,
2904 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2905 return;
2906 }
2907
2908 switch (opcode) {
2909 case TGSI_OPCODE_TXF:
2910 name = target == TGSI_TEXTURE_2D_MSAA ||
2911 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
2912 "llvm.SI.image.load" :
2913 "llvm.SI.image.load.mip";
2914 is_shadow = false;
2915 has_offset = false;
2916 break;
2917 case TGSI_OPCODE_TXQ:
2918 name = "llvm.SI.getresinfo";
2919 is_shadow = false;
2920 has_offset = false;
2921 break;
2922 case TGSI_OPCODE_LODQ:
2923 name = "llvm.SI.getlod";
2924 is_shadow = false;
2925 has_offset = false;
2926 break;
2927 case TGSI_OPCODE_TEX:
2928 case TGSI_OPCODE_TEX2:
2929 case TGSI_OPCODE_TXP:
2930 break;
2931 case TGSI_OPCODE_TXB:
2932 case TGSI_OPCODE_TXB2:
2933 infix = ".b";
2934 break;
2935 case TGSI_OPCODE_TXL:
2936 case TGSI_OPCODE_TXL2:
2937 infix = ".l";
2938 break;
2939 case TGSI_OPCODE_TXD:
2940 infix = ".d";
2941 break;
2942 case TGSI_OPCODE_TG4:
2943 name = "llvm.SI.gather4";
2944 break;
2945 default:
2946 assert(0);
2947 return;
2948 }
2949
2950 if (LLVMGetTypeKind(LLVMTypeOf(emit_data->args[0])) == LLVMVectorTypeKind)
2951 sprintf(type, ".v%ui32",
2952 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2953 else
2954 strcpy(type, ".i32");
2955
2956 /* Add the type and suffixes .c, .o if needed. */
2957 sprintf(intr_name, "%s%s%s%s%s",
2958 name, is_shadow ? ".c" : "", infix,
2959 has_offset ? ".o" : "", type);
2960
2961 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2962 base->gallivm->builder, intr_name, emit_data->dst_type,
2963 emit_data->args, emit_data->arg_count,
2964 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2965
2966 /* Divide the number of layers by 6 to get the number of cubes. */
2967 if (opcode == TGSI_OPCODE_TXQ &&
2968 (target == TGSI_TEXTURE_CUBE_ARRAY ||
2969 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
2970 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2971 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2972 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2973
2974 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2975 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2976 z = LLVMBuildSDiv(builder, z, six, "");
2977
2978 emit_data->output[emit_data->chan] =
2979 LLVMBuildInsertElement(builder, v4, z, two, "");
2980 }
2981 }
2982
2983 static void si_llvm_emit_txqs(
2984 const struct lp_build_tgsi_action * action,
2985 struct lp_build_tgsi_context * bld_base,
2986 struct lp_build_emit_data * emit_data)
2987 {
2988 struct gallivm_state *gallivm = bld_base->base.gallivm;
2989 LLVMBuilderRef builder = gallivm->builder;
2990 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2991 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2992 LLVMValueRef res, samples;
2993 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2994
2995 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2996
2997
2998 /* Read the samples from the descriptor directly. */
2999 res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
3000 samples = LLVMBuildExtractElement(
3001 builder, res,
3002 lp_build_const_int32(gallivm, 3), "");
3003 samples = LLVMBuildLShr(builder, samples,
3004 lp_build_const_int32(gallivm, 16), "");
3005 samples = LLVMBuildAnd(builder, samples,
3006 lp_build_const_int32(gallivm, 0xf), "");
3007 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
3008 samples, "");
3009
3010 emit_data->output[emit_data->chan] = samples;
3011 }
3012
3013 /*
3014 * SI implements derivatives using the local data store (LDS)
3015 * All writes to the LDS happen in all executing threads at
3016 * the same time. TID is the Thread ID for the current
3017 * thread and is a value between 0 and 63, representing
3018 * the thread's position in the wavefront.
3019 *
3020 * For the pixel shader threads are grouped into quads of four pixels.
3021 * The TIDs of the pixels of a quad are:
3022 *
3023 * +------+------+
3024 * |4n + 0|4n + 1|
3025 * +------+------+
3026 * |4n + 2|4n + 3|
3027 * +------+------+
3028 *
3029 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
3030 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
3031 * the current pixel's column, and masking with 0xfffffffe yields the TID
3032 * of the left pixel of the current pixel's row.
3033 *
3034 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
3035 * adding 2 yields the TID of the pixel below the top pixel.
3036 */
3037 /* masks for thread ID. */
3038 #define TID_MASK_TOP_LEFT 0xfffffffc
3039 #define TID_MASK_TOP 0xfffffffd
3040 #define TID_MASK_LEFT 0xfffffffe
3041
3042 static void si_llvm_emit_ddxy(
3043 const struct lp_build_tgsi_action * action,
3044 struct lp_build_tgsi_context * bld_base,
3045 struct lp_build_emit_data * emit_data)
3046 {
3047 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3048 struct gallivm_state *gallivm = bld_base->base.gallivm;
3049 struct lp_build_context * base = &bld_base->base;
3050 const struct tgsi_full_instruction *inst = emit_data->inst;
3051 unsigned opcode = inst->Instruction.Opcode;
3052 LLVMValueRef indices[2];
3053 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
3054 LLVMValueRef tl, trbl, result[4];
3055 LLVMTypeRef i32;
3056 unsigned swizzle[4];
3057 unsigned c;
3058 int idx;
3059 unsigned mask;
3060
3061 i32 = LLVMInt32TypeInContext(gallivm->context);
3062
3063 indices[0] = bld_base->uint_bld.zero;
3064 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
3065 NULL, 0, LLVMReadNoneAttribute);
3066 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3067 indices, 2, "");
3068
3069 if (opcode == TGSI_OPCODE_DDX_FINE)
3070 mask = TID_MASK_LEFT;
3071 else if (opcode == TGSI_OPCODE_DDY_FINE)
3072 mask = TID_MASK_TOP;
3073 else
3074 mask = TID_MASK_TOP_LEFT;
3075
3076 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
3077 lp_build_const_int32(gallivm, mask), "");
3078 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3079 indices, 2, "");
3080
3081 /* for DDX we want to next X pixel, DDY next Y pixel. */
3082 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3083 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
3084 lp_build_const_int32(gallivm, idx), "");
3085 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3086 indices, 2, "");
3087
3088 for (c = 0; c < 4; ++c) {
3089 unsigned i;
3090
3091 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
3092 for (i = 0; i < c; ++i) {
3093 if (swizzle[i] == swizzle[c]) {
3094 result[c] = result[i];
3095 break;
3096 }
3097 }
3098 if (i != c)
3099 continue;
3100
3101 LLVMBuildStore(gallivm->builder,
3102 LLVMBuildBitCast(gallivm->builder,
3103 lp_build_emit_fetch(bld_base, inst, 0, c),
3104 i32, ""),
3105 store_ptr);
3106
3107 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
3108 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3109
3110 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
3111 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
3112
3113 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
3114 }
3115
3116 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
3117 }
3118
3119 /*
3120 * this takes an I,J coordinate pair,
3121 * and works out the X and Y derivatives.
3122 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3123 */
3124 static LLVMValueRef si_llvm_emit_ddxy_interp(
3125 struct lp_build_tgsi_context *bld_base,
3126 LLVMValueRef interp_ij)
3127 {
3128 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3129 struct gallivm_state *gallivm = bld_base->base.gallivm;
3130 struct lp_build_context *base = &bld_base->base;
3131 LLVMValueRef indices[2];
3132 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
3133 LLVMValueRef tl, tr, bl, result[4];
3134 LLVMTypeRef i32;
3135 unsigned c;
3136
3137 i32 = LLVMInt32TypeInContext(gallivm->context);
3138
3139 indices[0] = bld_base->uint_bld.zero;
3140 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
3141 NULL, 0, LLVMReadNoneAttribute);
3142 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3143 indices, 2, "");
3144
3145 temp = LLVMBuildAnd(gallivm->builder, indices[1],
3146 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
3147
3148 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
3149 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
3150
3151 indices[1] = temp;
3152 load_ptr_x = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3153 indices, 2, "");
3154
3155 indices[1] = temp2;
3156 load_ptr_y = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3157 indices, 2, "");
3158
3159 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
3160 lp_build_const_int32(gallivm, 1), "");
3161 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3162 indices, 2, "");
3163
3164 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
3165 lp_build_const_int32(gallivm, 2), "");
3166 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3167 indices, 2, "");
3168
3169 for (c = 0; c < 2; ++c) {
3170 LLVMValueRef store_val;
3171 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
3172
3173 store_val = LLVMBuildExtractElement(gallivm->builder,
3174 interp_ij, c_ll, "");
3175 LLVMBuildStore(gallivm->builder,
3176 store_val,
3177 store_ptr);
3178
3179 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
3180 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3181
3182 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
3183 tr = LLVMBuildBitCast(gallivm->builder, tr, base->elem_type, "");
3184
3185 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
3186
3187 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
3188 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3189
3190 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
3191 bl = LLVMBuildBitCast(gallivm->builder, bl, base->elem_type, "");
3192
3193 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
3194 }
3195
3196 return lp_build_gather_values(gallivm, result, 4);
3197 }
3198
3199 static void interp_fetch_args(
3200 struct lp_build_tgsi_context *bld_base,
3201 struct lp_build_emit_data *emit_data)
3202 {
3203 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3204 struct gallivm_state *gallivm = bld_base->base.gallivm;
3205 const struct tgsi_full_instruction *inst = emit_data->inst;
3206
3207 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3208 /* offset is in second src, first two channels */
3209 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3210 emit_data->inst, 1,
3211 TGSI_CHAN_X);
3212 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3213 emit_data->inst, 1,
3214 TGSI_CHAN_Y);
3215 emit_data->arg_count = 2;
3216 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3217 LLVMValueRef sample_position;
3218 LLVMValueRef sample_id;
3219 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
3220
3221 /* fetch sample ID, then fetch its sample position,
3222 * and place into first two channels.
3223 */
3224 sample_id = lp_build_emit_fetch(bld_base,
3225 emit_data->inst, 1, TGSI_CHAN_X);
3226 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
3227 LLVMInt32TypeInContext(gallivm->context),
3228 "");
3229 sample_position = load_sample_position(&si_shader_ctx->radeon_bld, sample_id);
3230
3231 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
3232 sample_position,
3233 lp_build_const_int32(gallivm, 0), "");
3234
3235 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
3236 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
3237 sample_position,
3238 lp_build_const_int32(gallivm, 1), "");
3239 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
3240 emit_data->arg_count = 2;
3241 }
3242 }
3243
3244 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3245 struct lp_build_tgsi_context *bld_base,
3246 struct lp_build_emit_data *emit_data)
3247 {
3248 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3249 struct si_shader *shader = si_shader_ctx->shader;
3250 struct gallivm_state *gallivm = bld_base->base.gallivm;
3251 LLVMValueRef interp_param;
3252 const struct tgsi_full_instruction *inst = emit_data->inst;
3253 const char *intr_name;
3254 int input_index;
3255 int chan;
3256 int i;
3257 LLVMValueRef attr_number;
3258 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
3259 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
3260 int interp_param_idx;
3261 unsigned location;
3262
3263 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
3264 input_index = inst->Src[0].Register.Index;
3265
3266 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3267 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3268 location = TGSI_INTERPOLATE_LOC_CENTER;
3269 else
3270 location = TGSI_INTERPOLATE_LOC_CENTROID;
3271
3272 interp_param_idx = lookup_interp_param_index(shader->ps_input_interpolate[input_index],
3273 location);
3274 if (interp_param_idx == -1)
3275 return;
3276 else if (interp_param_idx)
3277 interp_param = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, interp_param_idx);
3278 else
3279 interp_param = NULL;
3280
3281 attr_number = lp_build_const_int32(gallivm,
3282 shader->ps_input_param_offset[input_index]);
3283
3284 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3285 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3286 LLVMValueRef ij_out[2];
3287 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3288
3289 /*
3290 * take the I then J parameters, and the DDX/Y for it, and
3291 * calculate the IJ inputs for the interpolator.
3292 * temp1 = ddx * offset/sample.x + I;
3293 * interp_param.I = ddy * offset/sample.y + temp1;
3294 * temp1 = ddx * offset/sample.x + J;
3295 * interp_param.J = ddy * offset/sample.y + temp1;
3296 */
3297 for (i = 0; i < 2; i++) {
3298 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
3299 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
3300 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
3301 ddxy_out, ix_ll, "");
3302 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
3303 ddxy_out, iy_ll, "");
3304 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
3305 interp_param, ix_ll, "");
3306 LLVMValueRef temp1, temp2;
3307
3308 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
3309 LLVMFloatTypeInContext(gallivm->context), "");
3310
3311 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
3312
3313 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
3314
3315 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
3316
3317 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
3318
3319 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
3320 temp2,
3321 LLVMIntTypeInContext(gallivm->context, 32), "");
3322 }
3323 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
3324 }
3325
3326 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3327 for (chan = 0; chan < 2; chan++) {
3328 LLVMValueRef args[4];
3329 LLVMValueRef llvm_chan;
3330 unsigned schan;
3331
3332 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3333 llvm_chan = lp_build_const_int32(gallivm, schan);
3334
3335 args[0] = llvm_chan;
3336 args[1] = attr_number;
3337 args[2] = params;
3338 args[3] = interp_param;
3339
3340 emit_data->output[chan] =
3341 lp_build_intrinsic(gallivm->builder, intr_name,
3342 input_type, args, args[3] ? 4 : 3,
3343 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3344 }
3345 }
3346
3347 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
3348 struct lp_build_emit_data *emit_data)
3349 {
3350 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3351 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
3352 unsigned stream;
3353
3354 assert(src0.File == TGSI_FILE_IMMEDIATE);
3355
3356 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
3357 return stream;
3358 }
3359
3360 /* Emit one vertex from the geometry shader */
3361 static void si_llvm_emit_vertex(
3362 const struct lp_build_tgsi_action *action,
3363 struct lp_build_tgsi_context *bld_base,
3364 struct lp_build_emit_data *emit_data)
3365 {
3366 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3367 struct lp_build_context *uint = &bld_base->uint_bld;
3368 struct si_shader *shader = si_shader_ctx->shader;
3369 struct tgsi_shader_info *info = &shader->selector->info;
3370 struct gallivm_state *gallivm = bld_base->base.gallivm;
3371 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
3372 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3373 SI_PARAM_GS2VS_OFFSET);
3374 LLVMValueRef gs_next_vertex;
3375 LLVMValueRef can_emit, kill;
3376 LLVMValueRef args[2];
3377 unsigned chan;
3378 int i;
3379 unsigned stream;
3380
3381 stream = si_llvm_get_stream(bld_base, emit_data);
3382
3383 /* Write vertex attribute values to GSVS ring */
3384 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
3385 si_shader_ctx->gs_next_vertex[stream],
3386 "");
3387
3388 /* If this thread has already emitted the declared maximum number of
3389 * vertices, kill it: excessive vertex emissions are not supposed to
3390 * have any effect, and GS threads have no externally observable
3391 * effects other than emitting vertices.
3392 */
3393 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
3394 lp_build_const_int32(gallivm,
3395 shader->selector->gs_max_out_vertices), "");
3396 kill = lp_build_select(&bld_base->base, can_emit,
3397 lp_build_const_float(gallivm, 1.0f),
3398 lp_build_const_float(gallivm, -1.0f));
3399
3400 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
3401 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
3402
3403 for (i = 0; i < info->num_outputs; i++) {
3404 LLVMValueRef *out_ptr =
3405 si_shader_ctx->radeon_bld.soa.outputs[i];
3406
3407 for (chan = 0; chan < 4; chan++) {
3408 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3409 LLVMValueRef voffset =
3410 lp_build_const_int32(gallivm, (i * 4 + chan) *
3411 shader->selector->gs_max_out_vertices);
3412
3413 voffset = lp_build_add(uint, voffset, gs_next_vertex);
3414 voffset = lp_build_mul_imm(uint, voffset, 4);
3415
3416 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
3417
3418 build_tbuffer_store(si_shader_ctx,
3419 si_shader_ctx->gsvs_ring[stream],
3420 out_val, 1,
3421 voffset, soffset, 0,
3422 V_008F0C_BUF_DATA_FORMAT_32,
3423 V_008F0C_BUF_NUM_FORMAT_UINT,
3424 1, 0, 1, 1, 0);
3425 }
3426 }
3427 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
3428 lp_build_const_int32(gallivm, 1));
3429
3430 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex[stream]);
3431
3432 /* Signal vertex emission */
3433 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
3434 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3435 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3436 LLVMVoidTypeInContext(gallivm->context), args, 2,
3437 LLVMNoUnwindAttribute);
3438 }
3439
3440 /* Cut one primitive from the geometry shader */
3441 static void si_llvm_emit_primitive(
3442 const struct lp_build_tgsi_action *action,
3443 struct lp_build_tgsi_context *bld_base,
3444 struct lp_build_emit_data *emit_data)
3445 {
3446 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3447 struct gallivm_state *gallivm = bld_base->base.gallivm;
3448 LLVMValueRef args[2];
3449 unsigned stream;
3450
3451 /* Signal primitive cut */
3452 stream = si_llvm_get_stream(bld_base, emit_data);
3453 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
3454 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3455 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3456 LLVMVoidTypeInContext(gallivm->context), args, 2,
3457 LLVMNoUnwindAttribute);
3458 }
3459
3460 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
3461 struct lp_build_tgsi_context *bld_base,
3462 struct lp_build_emit_data *emit_data)
3463 {
3464 struct gallivm_state *gallivm = bld_base->base.gallivm;
3465
3466 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.barrier.local",
3467 LLVMVoidTypeInContext(gallivm->context), NULL, 0,
3468 LLVMNoUnwindAttribute);
3469 }
3470
3471 static const struct lp_build_tgsi_action tex_action = {
3472 .fetch_args = tex_fetch_args,
3473 .emit = build_tex_intrinsic,
3474 };
3475
3476 static const struct lp_build_tgsi_action interp_action = {
3477 .fetch_args = interp_fetch_args,
3478 .emit = build_interp_intrinsic,
3479 };
3480
3481 static void create_meta_data(struct si_shader_context *si_shader_ctx)
3482 {
3483 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3484 LLVMValueRef args[3];
3485
3486 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
3487 args[1] = 0;
3488 args[2] = lp_build_const_int32(gallivm, 1);
3489
3490 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
3491 }
3492
3493 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3494 {
3495 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3496 CONST_ADDR_SPACE);
3497 }
3498
3499 static void declare_streamout_params(struct si_shader_context *si_shader_ctx,
3500 struct pipe_stream_output_info *so,
3501 LLVMTypeRef *params, LLVMTypeRef i32,
3502 unsigned *num_params)
3503 {
3504 int i;
3505
3506 /* Streamout SGPRs. */
3507 if (so->num_outputs) {
3508 params[si_shader_ctx->param_streamout_config = (*num_params)++] = i32;
3509 params[si_shader_ctx->param_streamout_write_index = (*num_params)++] = i32;
3510 }
3511 /* A streamout buffer offset is loaded if the stride is non-zero. */
3512 for (i = 0; i < 4; i++) {
3513 if (!so->stride[i])
3514 continue;
3515
3516 params[si_shader_ctx->param_streamout_offset[i] = (*num_params)++] = i32;
3517 }
3518 }
3519
3520 static void create_function(struct si_shader_context *si_shader_ctx)
3521 {
3522 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3523 struct gallivm_state *gallivm = bld_base->base.gallivm;
3524 struct si_shader *shader = si_shader_ctx->shader;
3525 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
3526 unsigned i, last_array_pointer, last_sgpr, num_params;
3527
3528 i8 = LLVMInt8TypeInContext(gallivm->context);
3529 i32 = LLVMInt32TypeInContext(gallivm->context);
3530 f32 = LLVMFloatTypeInContext(gallivm->context);
3531 v2i32 = LLVMVectorType(i32, 2);
3532 v3i32 = LLVMVectorType(i32, 3);
3533 v4i32 = LLVMVectorType(i32, 4);
3534 v8i32 = LLVMVectorType(i32, 8);
3535 v16i8 = LLVMVectorType(i8, 16);
3536
3537 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
3538 params[SI_PARAM_CONST_BUFFERS] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
3539 params[SI_PARAM_SAMPLER_STATES] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
3540 params[SI_PARAM_SAMPLER_VIEWS] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
3541 last_array_pointer = SI_PARAM_SAMPLER_VIEWS;
3542
3543 switch (si_shader_ctx->type) {
3544 case TGSI_PROCESSOR_VERTEX:
3545 params[SI_PARAM_VERTEX_BUFFERS] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
3546 last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
3547 params[SI_PARAM_BASE_VERTEX] = i32;
3548 params[SI_PARAM_START_INSTANCE] = i32;
3549 num_params = SI_PARAM_START_INSTANCE+1;
3550
3551 if (shader->key.vs.as_es) {
3552 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3553 } else if (shader->key.vs.as_ls) {
3554 params[SI_PARAM_LS_OUT_LAYOUT] = i32;
3555 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
3556 } else {
3557 if (shader->is_gs_copy_shader) {
3558 last_array_pointer = SI_PARAM_CONST_BUFFERS;
3559 num_params = SI_PARAM_CONST_BUFFERS+1;
3560 } else {
3561 params[SI_PARAM_VS_STATE_BITS] = i32;
3562 num_params = SI_PARAM_VS_STATE_BITS+1;
3563 }
3564
3565 /* The locations of the other parameters are assigned dynamically. */
3566 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3567 params, i32, &num_params);
3568 }
3569
3570 last_sgpr = num_params-1;
3571
3572 /* VGPRs */
3573 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
3574 params[si_shader_ctx->param_rel_auto_id = num_params++] = i32;
3575 params[si_shader_ctx->param_vs_prim_id = num_params++] = i32;
3576 params[si_shader_ctx->param_instance_id = num_params++] = i32;
3577 break;
3578
3579 case TGSI_PROCESSOR_TESS_CTRL:
3580 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3581 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3582 params[SI_PARAM_TCS_IN_LAYOUT] = i32;
3583 params[SI_PARAM_TESS_FACTOR_OFFSET] = i32;
3584 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
3585
3586 /* VGPRs */
3587 params[SI_PARAM_PATCH_ID] = i32;
3588 params[SI_PARAM_REL_IDS] = i32;
3589 num_params = SI_PARAM_REL_IDS+1;
3590 break;
3591
3592 case TGSI_PROCESSOR_TESS_EVAL:
3593 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3594 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3595 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
3596
3597 if (shader->key.tes.as_es) {
3598 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3599 } else {
3600 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3601 params, i32, &num_params);
3602 }
3603 last_sgpr = num_params - 1;
3604
3605 /* VGPRs */
3606 params[si_shader_ctx->param_tes_u = num_params++] = f32;
3607 params[si_shader_ctx->param_tes_v = num_params++] = f32;
3608 params[si_shader_ctx->param_tes_rel_patch_id = num_params++] = i32;
3609 params[si_shader_ctx->param_tes_patch_id = num_params++] = i32;
3610 break;
3611
3612 case TGSI_PROCESSOR_GEOMETRY:
3613 params[SI_PARAM_GS2VS_OFFSET] = i32;
3614 params[SI_PARAM_GS_WAVE_ID] = i32;
3615 last_sgpr = SI_PARAM_GS_WAVE_ID;
3616
3617 /* VGPRs */
3618 params[SI_PARAM_VTX0_OFFSET] = i32;
3619 params[SI_PARAM_VTX1_OFFSET] = i32;
3620 params[SI_PARAM_PRIMITIVE_ID] = i32;
3621 params[SI_PARAM_VTX2_OFFSET] = i32;
3622 params[SI_PARAM_VTX3_OFFSET] = i32;
3623 params[SI_PARAM_VTX4_OFFSET] = i32;
3624 params[SI_PARAM_VTX5_OFFSET] = i32;
3625 params[SI_PARAM_GS_INSTANCE_ID] = i32;
3626 num_params = SI_PARAM_GS_INSTANCE_ID+1;
3627 break;
3628
3629 case TGSI_PROCESSOR_FRAGMENT:
3630 params[SI_PARAM_ALPHA_REF] = f32;
3631 params[SI_PARAM_PS_STATE_BITS] = i32;
3632 params[SI_PARAM_PRIM_MASK] = i32;
3633 last_sgpr = SI_PARAM_PRIM_MASK;
3634 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
3635 params[SI_PARAM_PERSP_CENTER] = v2i32;
3636 params[SI_PARAM_PERSP_CENTROID] = v2i32;
3637 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
3638 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
3639 params[SI_PARAM_LINEAR_CENTER] = v2i32;
3640 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
3641 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
3642 params[SI_PARAM_POS_X_FLOAT] = f32;
3643 params[SI_PARAM_POS_Y_FLOAT] = f32;
3644 params[SI_PARAM_POS_Z_FLOAT] = f32;
3645 params[SI_PARAM_POS_W_FLOAT] = f32;
3646 params[SI_PARAM_FRONT_FACE] = i32;
3647 params[SI_PARAM_ANCILLARY] = i32;
3648 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
3649 params[SI_PARAM_POS_FIXED_PT] = f32;
3650 num_params = SI_PARAM_POS_FIXED_PT+1;
3651 break;
3652
3653 default:
3654 assert(0 && "unimplemented shader");
3655 return;
3656 }
3657
3658 assert(num_params <= Elements(params));
3659 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
3660 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
3661
3662 if (shader->dx10_clamp_mode)
3663 LLVMAddTargetDependentFunctionAttr(si_shader_ctx->radeon_bld.main_fn,
3664 "enable-no-nans-fp-math", "true");
3665
3666 for (i = 0; i <= last_sgpr; ++i) {
3667 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
3668
3669 /* We tell llvm that array inputs are passed by value to allow Sinking pass
3670 * to move load. Inputs are constant so this is fine. */
3671 if (i <= last_array_pointer)
3672 LLVMAddAttribute(P, LLVMByValAttribute);
3673 else
3674 LLVMAddAttribute(P, LLVMInRegAttribute);
3675 }
3676
3677 if (bld_base->info &&
3678 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
3679 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
3680 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
3681 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
3682 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
3683 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
3684 si_shader_ctx->lds =
3685 LLVMAddGlobalInAddressSpace(gallivm->module,
3686 LLVMArrayType(i32, 64),
3687 "ddxy_lds",
3688 LOCAL_ADDR_SPACE);
3689
3690 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
3691 si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
3692 si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL) {
3693 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
3694 unsigned vertex_data_dw_size = 32*32*4;
3695 unsigned patch_data_dw_size = 32*4;
3696 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
3697 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
3698 unsigned lds_dwords = patch_dw_size;
3699
3700 /* The actual size is computed outside of the shader to reduce
3701 * the number of shader variants. */
3702 si_shader_ctx->lds =
3703 LLVMAddGlobalInAddressSpace(gallivm->module,
3704 LLVMArrayType(i32, lds_dwords),
3705 "tess_lds",
3706 LOCAL_ADDR_SPACE);
3707 }
3708 }
3709
3710 static void preload_constants(struct si_shader_context *si_shader_ctx)
3711 {
3712 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3713 struct gallivm_state * gallivm = bld_base->base.gallivm;
3714 const struct tgsi_shader_info * info = bld_base->info;
3715 unsigned buf;
3716 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
3717
3718 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
3719 unsigned i, num_const = info->const_file_max[buf] + 1;
3720
3721 if (num_const == 0)
3722 continue;
3723
3724 /* Allocate space for the constant values */
3725 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
3726
3727 /* Load the resource descriptor */
3728 si_shader_ctx->const_buffers[buf] =
3729 build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
3730
3731 /* Load the constants, we rely on the code sinking to do the rest */
3732 for (i = 0; i < num_const * 4; ++i) {
3733 si_shader_ctx->constants[buf][i] =
3734 buffer_load_const(gallivm->builder,
3735 si_shader_ctx->const_buffers[buf],
3736 lp_build_const_int32(gallivm, i * 4),
3737 bld_base->base.elem_type);
3738 }
3739 }
3740 }
3741
3742 static void preload_samplers(struct si_shader_context *si_shader_ctx)
3743 {
3744 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3745 struct gallivm_state * gallivm = bld_base->base.gallivm;
3746 const struct tgsi_shader_info * info = bld_base->info;
3747
3748 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
3749
3750 LLVMValueRef res_ptr, samp_ptr;
3751 LLVMValueRef offset;
3752
3753 if (num_samplers == 0)
3754 return;
3755
3756 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
3757 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
3758
3759 /* Load the resources and samplers, we rely on the code sinking to do the rest */
3760 for (i = 0; i < num_samplers; ++i) {
3761 /* Resource */
3762 offset = lp_build_const_int32(gallivm, i);
3763 si_shader_ctx->sampler_views[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3764
3765 /* Sampler */
3766 offset = lp_build_const_int32(gallivm, i);
3767 si_shader_ctx->sampler_states[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
3768
3769 /* FMASK resource */
3770 if (info->is_msaa_sampler[i]) {
3771 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
3772 si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + i] =
3773 build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3774 }
3775 }
3776 }
3777
3778 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
3779 {
3780 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3781 struct gallivm_state * gallivm = bld_base->base.gallivm;
3782 unsigned i;
3783
3784 /* Streamout can only be used if the shader is compiled as VS. */
3785 if (!si_shader_ctx->shader->selector->so.num_outputs ||
3786 (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3787 (si_shader_ctx->shader->key.vs.as_es ||
3788 si_shader_ctx->shader->key.vs.as_ls)) ||
3789 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3790 si_shader_ctx->shader->key.tes.as_es))
3791 return;
3792
3793 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3794 SI_PARAM_RW_BUFFERS);
3795
3796 /* Load the resources, we rely on the code sinking to do the rest */
3797 for (i = 0; i < 4; ++i) {
3798 if (si_shader_ctx->shader->selector->so.stride[i]) {
3799 LLVMValueRef offset = lp_build_const_int32(gallivm,
3800 SI_SO_BUF_OFFSET + i);
3801
3802 si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3803 }
3804 }
3805 }
3806
3807 /**
3808 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
3809 * for later use.
3810 */
3811 static void preload_ring_buffers(struct si_shader_context *si_shader_ctx)
3812 {
3813 struct gallivm_state *gallivm =
3814 si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3815
3816 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3817 SI_PARAM_RW_BUFFERS);
3818
3819 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3820 si_shader_ctx->shader->key.vs.as_es) ||
3821 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3822 si_shader_ctx->shader->key.tes.as_es) ||
3823 si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3824 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
3825
3826 si_shader_ctx->esgs_ring =
3827 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3828 }
3829
3830 if (si_shader_ctx->shader->is_gs_copy_shader) {
3831 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
3832
3833 si_shader_ctx->gsvs_ring[0] =
3834 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3835 }
3836 if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3837 int i;
3838 for (i = 0; i < 4; i++) {
3839 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i);
3840
3841 si_shader_ctx->gsvs_ring[i] =
3842 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3843 }
3844 }
3845 }
3846
3847 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
3848 struct si_shader_config *conf,
3849 unsigned symbol_offset)
3850 {
3851 unsigned i;
3852 const unsigned char *config =
3853 radeon_shader_binary_config_start(binary, symbol_offset);
3854
3855 /* XXX: We may be able to emit some of these values directly rather than
3856 * extracting fields to be emitted later.
3857 */
3858
3859 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
3860 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
3861 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
3862 switch (reg) {
3863 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
3864 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
3865 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
3866 case R_00B848_COMPUTE_PGM_RSRC1:
3867 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
3868 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
3869 conf->float_mode = G_00B028_FLOAT_MODE(value);
3870 conf->rsrc1 = value;
3871 break;
3872 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
3873 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
3874 break;
3875 case R_00B84C_COMPUTE_PGM_RSRC2:
3876 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
3877 conf->rsrc2 = value;
3878 break;
3879 case R_0286CC_SPI_PS_INPUT_ENA:
3880 conf->spi_ps_input_ena = value;
3881 break;
3882 case R_0286D0_SPI_PS_INPUT_ADDR:
3883 /* Not used yet, but will be in the future */
3884 break;
3885 case R_0286E8_SPI_TMPRING_SIZE:
3886 case R_00B860_COMPUTE_TMPRING_SIZE:
3887 /* WAVESIZE is in units of 256 dwords. */
3888 conf->scratch_bytes_per_wave =
3889 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
3890 break;
3891 default:
3892 {
3893 static bool printed;
3894
3895 if (!printed) {
3896 fprintf(stderr, "Warning: LLVM emitted unknown "
3897 "config register: 0x%x\n", reg);
3898 printed = true;
3899 }
3900 }
3901 break;
3902 }
3903 }
3904 }
3905
3906 void si_shader_apply_scratch_relocs(struct si_context *sctx,
3907 struct si_shader *shader,
3908 uint64_t scratch_va)
3909 {
3910 unsigned i;
3911 uint32_t scratch_rsrc_dword0 = scratch_va;
3912 uint32_t scratch_rsrc_dword1 =
3913 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
3914 | S_008F04_STRIDE(shader->config.scratch_bytes_per_wave / 64);
3915
3916 for (i = 0 ; i < shader->binary.reloc_count; i++) {
3917 const struct radeon_shader_reloc *reloc =
3918 &shader->binary.relocs[i];
3919 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
3920 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3921 &scratch_rsrc_dword0, 4);
3922 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
3923 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3924 &scratch_rsrc_dword1, 4);
3925 }
3926 }
3927 }
3928
3929 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
3930 {
3931 const struct radeon_shader_binary *binary = &shader->binary;
3932 unsigned code_size = binary->code_size + binary->rodata_size;
3933 unsigned char *ptr;
3934
3935 r600_resource_reference(&shader->bo, NULL);
3936 shader->bo = si_resource_create_custom(&sscreen->b.b,
3937 PIPE_USAGE_IMMUTABLE,
3938 code_size);
3939 if (!shader->bo)
3940 return -ENOMEM;
3941
3942 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
3943 PIPE_TRANSFER_READ_WRITE);
3944 util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
3945 if (binary->rodata_size > 0) {
3946 ptr += binary->code_size;
3947 util_memcpy_cpu_to_le32(ptr, binary->rodata,
3948 binary->rodata_size);
3949 }
3950
3951 sscreen->b.ws->buffer_unmap(shader->bo->buf);
3952 return 0;
3953 }
3954
3955 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
3956 struct pipe_debug_callback *debug)
3957 {
3958 char *line, *p;
3959 unsigned i, count;
3960
3961 if (binary->disasm_string) {
3962 fprintf(stderr, "\nShader Disassembly:\n\n");
3963 fprintf(stderr, "%s\n", binary->disasm_string);
3964
3965 if (debug && debug->debug_message) {
3966 /* Very long debug messages are cut off, so send the
3967 * disassembly one line at a time. This causes more
3968 * overhead, but on the plus side it simplifies
3969 * parsing of resulting logs.
3970 */
3971 pipe_debug_message(debug, SHADER_INFO,
3972 "Shader Disassembly Begin");
3973
3974 line = binary->disasm_string;
3975 while (*line) {
3976 p = strchrnul(line, '\n');
3977 count = p - line;
3978
3979 if (count) {
3980 pipe_debug_message(debug, SHADER_INFO,
3981 "%.*s", count, line);
3982 }
3983
3984 if (!*p)
3985 break;
3986 line = p + 1;
3987 }
3988
3989 pipe_debug_message(debug, SHADER_INFO,
3990 "Shader Disassembly End");
3991 }
3992 } else {
3993 fprintf(stderr, "SI CODE:\n");
3994 for (i = 0; i < binary->code_size; i += 4) {
3995 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i,
3996 binary->code[i + 3], binary->code[i + 2],
3997 binary->code[i + 1], binary->code[i]);
3998 }
3999 }
4000 }
4001
4002 static void si_shader_dump_stats(struct si_screen *sscreen,
4003 struct si_shader_config *conf,
4004 unsigned code_size,
4005 struct pipe_debug_callback *debug,
4006 unsigned processor)
4007 {
4008 if (r600_can_dump_shader(&sscreen->b, processor)) {
4009 fprintf(stderr, "*** SHADER STATS ***\n"
4010 "SGPRS: %d\nVGPRS: %d\nCode Size: %d bytes\nLDS: %d blocks\n"
4011 "Scratch: %d bytes per wave\n********************\n",
4012 conf->num_sgprs, conf->num_vgprs, code_size,
4013 conf->lds_size, conf->scratch_bytes_per_wave);
4014 }
4015
4016 pipe_debug_message(debug, SHADER_INFO,
4017 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d LDS: %d Scratch: %d",
4018 conf->num_sgprs, conf->num_vgprs, code_size,
4019 conf->lds_size, conf->scratch_bytes_per_wave);
4020 }
4021
4022 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
4023 struct pipe_debug_callback *debug, unsigned processor)
4024 {
4025 if (r600_can_dump_shader(&sscreen->b, processor))
4026 if (!(sscreen->b.debug_flags & DBG_NO_ASM))
4027 si_shader_dump_disassembly(&shader->binary, debug);
4028
4029 si_shader_dump_stats(sscreen, &shader->config,
4030 shader->binary.code_size, debug, processor);
4031 }
4032
4033 int si_compile_llvm(struct si_screen *sscreen,
4034 struct radeon_shader_binary *binary,
4035 struct si_shader_config *conf,
4036 LLVMTargetMachineRef tm,
4037 LLVMModuleRef mod,
4038 struct pipe_debug_callback *debug,
4039 unsigned processor)
4040 {
4041 int r = 0;
4042 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
4043
4044 if (r600_can_dump_shader(&sscreen->b, processor)) {
4045 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
4046
4047 if (!(sscreen->b.debug_flags & DBG_NO_IR))
4048 LLVMDumpModule(mod);
4049 }
4050
4051 if (!si_replace_shader(count, binary)) {
4052 r = radeon_llvm_compile(mod, binary,
4053 r600_get_llvm_processor_name(sscreen->b.family), tm,
4054 debug);
4055 if (r)
4056 return r;
4057 }
4058
4059 si_shader_binary_read_config(binary, conf, 0);
4060
4061 FREE(binary->config);
4062 FREE(binary->global_symbol_offsets);
4063 binary->config = NULL;
4064 binary->global_symbol_offsets = NULL;
4065 return r;
4066 }
4067
4068 /* Generate code for the hardware VS shader stage to go with a geometry shader */
4069 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
4070 struct si_shader_context *si_shader_ctx,
4071 struct si_shader *gs, bool dump,
4072 struct pipe_debug_callback *debug)
4073 {
4074 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
4075 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
4076 struct lp_build_context *base = &bld_base->base;
4077 struct lp_build_context *uint = &bld_base->uint_bld;
4078 struct si_shader *shader = si_shader_ctx->shader;
4079 struct si_shader_output_values *outputs;
4080 struct tgsi_shader_info *gsinfo = &gs->selector->info;
4081 LLVMValueRef args[9];
4082 int i, r;
4083
4084 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
4085
4086 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
4087 shader->is_gs_copy_shader = true;
4088
4089 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
4090
4091 create_meta_data(si_shader_ctx);
4092 create_function(si_shader_ctx);
4093 preload_streamout_buffers(si_shader_ctx);
4094 preload_ring_buffers(si_shader_ctx);
4095
4096 args[0] = si_shader_ctx->gsvs_ring[0];
4097 args[1] = lp_build_mul_imm(uint,
4098 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
4099 si_shader_ctx->param_vertex_id),
4100 4);
4101 args[3] = uint->zero;
4102 args[4] = uint->one; /* OFFEN */
4103 args[5] = uint->zero; /* IDXEN */
4104 args[6] = uint->one; /* GLC */
4105 args[7] = uint->one; /* SLC */
4106 args[8] = uint->zero; /* TFE */
4107
4108 /* Fetch vertex data from GSVS ring */
4109 for (i = 0; i < gsinfo->num_outputs; ++i) {
4110 unsigned chan;
4111
4112 outputs[i].name = gsinfo->output_semantic_name[i];
4113 outputs[i].sid = gsinfo->output_semantic_index[i];
4114
4115 for (chan = 0; chan < 4; chan++) {
4116 args[2] = lp_build_const_int32(gallivm,
4117 (i * 4 + chan) *
4118 gs->selector->gs_max_out_vertices * 16 * 4);
4119
4120 outputs[i].values[chan] =
4121 LLVMBuildBitCast(gallivm->builder,
4122 lp_build_intrinsic(gallivm->builder,
4123 "llvm.SI.buffer.load.dword.i32.i32",
4124 LLVMInt32TypeInContext(gallivm->context),
4125 args, 9,
4126 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
4127 base->elem_type, "");
4128 }
4129 }
4130
4131 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
4132
4133 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
4134
4135 if (dump)
4136 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
4137
4138 r = si_compile_llvm(sscreen, &si_shader_ctx->shader->binary,
4139 &si_shader_ctx->shader->config, si_shader_ctx->tm,
4140 bld_base->base.gallivm->module,
4141 debug, TGSI_PROCESSOR_GEOMETRY);
4142 if (!r) {
4143 si_shader_dump(sscreen, si_shader_ctx->shader, debug,
4144 TGSI_PROCESSOR_GEOMETRY);
4145 r = si_shader_binary_upload(sscreen, si_shader_ctx->shader);
4146 }
4147
4148 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
4149
4150 FREE(outputs);
4151 return r;
4152 }
4153
4154 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
4155 {
4156 int i;
4157
4158 fprintf(f, "SHADER KEY\n");
4159
4160 switch (shader) {
4161 case PIPE_SHADER_VERTEX:
4162 fprintf(f, " instance_divisors = {");
4163 for (i = 0; i < Elements(key->vs.instance_divisors); i++)
4164 fprintf(f, !i ? "%u" : ", %u",
4165 key->vs.instance_divisors[i]);
4166 fprintf(f, "}\n");
4167 fprintf(f, " as_es = %u\n", key->vs.as_es);
4168 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
4169 fprintf(f, " export_prim_id = %u\n", key->vs.export_prim_id);
4170 break;
4171
4172 case PIPE_SHADER_TESS_CTRL:
4173 fprintf(f, " prim_mode = %u\n", key->tcs.prim_mode);
4174 break;
4175
4176 case PIPE_SHADER_TESS_EVAL:
4177 fprintf(f, " as_es = %u\n", key->tes.as_es);
4178 fprintf(f, " export_prim_id = %u\n", key->tes.export_prim_id);
4179 break;
4180
4181 case PIPE_SHADER_GEOMETRY:
4182 break;
4183
4184 case PIPE_SHADER_FRAGMENT:
4185 fprintf(f, " spi_shader_col_format = 0x%x\n", key->ps.spi_shader_col_format);
4186 fprintf(f, " last_cbuf = %u\n", key->ps.last_cbuf);
4187 fprintf(f, " color_two_side = %u\n", key->ps.color_two_side);
4188 fprintf(f, " alpha_func = %u\n", key->ps.alpha_func);
4189 fprintf(f, " alpha_to_one = %u\n", key->ps.alpha_to_one);
4190 fprintf(f, " poly_stipple = %u\n", key->ps.poly_stipple);
4191 fprintf(f, " clamp_color = %u\n", key->ps.clamp_color);
4192 break;
4193
4194 default:
4195 assert(0);
4196 }
4197 }
4198
4199 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
4200 struct si_shader *shader,
4201 struct pipe_debug_callback *debug)
4202 {
4203 struct si_shader_selector *sel = shader->selector;
4204 struct tgsi_token *tokens = sel->tokens;
4205 struct si_shader_context si_shader_ctx;
4206 struct lp_build_tgsi_context * bld_base;
4207 struct tgsi_shader_info stipple_shader_info;
4208 LLVMModuleRef mod;
4209 int r = 0;
4210 bool poly_stipple = sel->type == PIPE_SHADER_FRAGMENT &&
4211 shader->key.ps.poly_stipple;
4212 bool dump = r600_can_dump_shader(&sscreen->b, sel->info.processor);
4213
4214 if (poly_stipple) {
4215 tokens = util_pstipple_create_fragment_shader(tokens, NULL,
4216 SI_POLY_STIPPLE_SAMPLER,
4217 TGSI_FILE_SYSTEM_VALUE);
4218 tgsi_scan_shader(tokens, &stipple_shader_info);
4219 }
4220
4221 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
4222 * conversion fails. */
4223 if (dump && !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
4224 si_dump_shader_key(sel->type, &shader->key, stderr);
4225 tgsi_dump(tokens, 0);
4226 si_dump_streamout(&sel->so);
4227 }
4228
4229 assert(shader->nparam == 0);
4230
4231 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
4232 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
4233 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
4234
4235 if (sel->type != PIPE_SHADER_COMPUTE)
4236 shader->dx10_clamp_mode = true;
4237
4238 shader->uses_instanceid = sel->info.uses_instanceid;
4239 bld_base->info = poly_stipple ? &stipple_shader_info : &sel->info;
4240 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
4241
4242 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
4243 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
4244 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
4245
4246 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
4247 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
4248 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
4249 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
4250 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
4251 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
4252 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
4253 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
4254 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
4255 bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
4256 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
4257 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
4258 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
4259
4260 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
4261 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
4262 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
4263 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
4264
4265 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
4266 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
4267 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
4268
4269 if (HAVE_LLVM >= 0x0306) {
4270 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
4271 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
4272 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
4273 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
4274 }
4275
4276 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
4277 si_shader_ctx.shader = shader;
4278 si_shader_ctx.type = tgsi_get_processor_type(tokens);
4279 si_shader_ctx.screen = sscreen;
4280 si_shader_ctx.tm = tm;
4281
4282 switch (si_shader_ctx.type) {
4283 case TGSI_PROCESSOR_VERTEX:
4284 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
4285 if (shader->key.vs.as_ls)
4286 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
4287 else if (shader->key.vs.as_es)
4288 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4289 else
4290 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4291 break;
4292 case TGSI_PROCESSOR_TESS_CTRL:
4293 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
4294 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
4295 bld_base->emit_store = store_output_tcs;
4296 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
4297 break;
4298 case TGSI_PROCESSOR_TESS_EVAL:
4299 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
4300 if (shader->key.tes.as_es)
4301 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4302 else
4303 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4304 break;
4305 case TGSI_PROCESSOR_GEOMETRY:
4306 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
4307 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
4308 break;
4309 case TGSI_PROCESSOR_FRAGMENT:
4310 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
4311 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
4312 break;
4313 default:
4314 assert(!"Unsupported shader type");
4315 return -1;
4316 }
4317
4318 create_meta_data(&si_shader_ctx);
4319 create_function(&si_shader_ctx);
4320 preload_constants(&si_shader_ctx);
4321 preload_samplers(&si_shader_ctx);
4322 preload_streamout_buffers(&si_shader_ctx);
4323 preload_ring_buffers(&si_shader_ctx);
4324
4325 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4326 int i;
4327 for (i = 0; i < 4; i++) {
4328 si_shader_ctx.gs_next_vertex[i] =
4329 lp_build_alloca(bld_base->base.gallivm,
4330 bld_base->uint_bld.elem_type, "");
4331 }
4332 }
4333
4334 if (!lp_build_tgsi_llvm(bld_base, tokens)) {
4335 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
4336 goto out;
4337 }
4338
4339 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
4340
4341 mod = bld_base->base.gallivm->module;
4342 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
4343 mod, debug, si_shader_ctx.type);
4344 if (r) {
4345 fprintf(stderr, "LLVM failed to compile shader\n");
4346 goto out;
4347 }
4348
4349 si_shader_dump(sscreen, shader, debug, si_shader_ctx.type);
4350
4351 r = si_shader_binary_upload(sscreen, shader);
4352 if (r) {
4353 fprintf(stderr, "LLVM failed to upload shader\n");
4354 goto out;
4355 }
4356
4357 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
4358
4359 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4360 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
4361 shader->gs_copy_shader->selector = shader->selector;
4362 shader->gs_copy_shader->key = shader->key;
4363 si_shader_ctx.shader = shader->gs_copy_shader;
4364 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
4365 shader, dump, debug))) {
4366 free(shader->gs_copy_shader);
4367 shader->gs_copy_shader = NULL;
4368 goto out;
4369 }
4370 }
4371
4372 out:
4373 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
4374 FREE(si_shader_ctx.constants[i]);
4375 if (poly_stipple)
4376 tgsi_free_tokens(tokens);
4377 return r;
4378 }
4379
4380 void si_shader_destroy_binary(struct radeon_shader_binary *binary)
4381 {
4382 FREE(binary->code);
4383 FREE(binary->rodata);
4384 FREE(binary->relocs);
4385 FREE(binary->disasm_string);
4386 }
4387
4388 void si_shader_destroy(struct si_shader *shader)
4389 {
4390 if (shader->gs_copy_shader) {
4391 si_shader_destroy(shader->gs_copy_shader);
4392 FREE(shader->gs_copy_shader);
4393 }
4394
4395 if (shader->scratch_bo)
4396 r600_resource_reference(&shader->scratch_bo, NULL);
4397
4398 r600_resource_reference(&shader->bo, NULL);
4399 si_shader_destroy_binary(&shader->binary);
4400 }