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radeonsi: set dereferenceable attribute on descriptor arrays
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "gallivm/lp_bld_misc.h"
37 #include "radeon/r600_cs.h"
38 #include "radeon/radeon_llvm.h"
39 #include "radeon/radeon_elf_util.h"
40 #include "radeon/radeon_llvm_emit.h"
41 #include "util/u_memory.h"
42 #include "util/u_pstipple.h"
43 #include "util/u_string.h"
44 #include "tgsi/tgsi_parse.h"
45 #include "tgsi/tgsi_build.h"
46 #include "tgsi/tgsi_util.h"
47 #include "tgsi/tgsi_dump.h"
48
49 #include "si_pipe.h"
50 #include "si_shader.h"
51 #include "sid.h"
52
53 #include <errno.h>
54
55 static const char *scratch_rsrc_dword0_symbol =
56 "SCRATCH_RSRC_DWORD0";
57
58 static const char *scratch_rsrc_dword1_symbol =
59 "SCRATCH_RSRC_DWORD1";
60
61 struct si_shader_output_values
62 {
63 LLVMValueRef values[4];
64 unsigned name;
65 unsigned sid;
66 };
67
68 struct si_shader_context
69 {
70 struct radeon_llvm_context radeon_bld;
71 struct si_shader *shader;
72 struct si_screen *screen;
73
74 unsigned type; /* PIPE_SHADER_* specifies the type of shader. */
75 bool is_gs_copy_shader;
76
77 /* Whether to generate the optimized shader variant compiled as a whole
78 * (without a prolog and epilog)
79 */
80 bool is_monolithic;
81
82 int param_streamout_config;
83 int param_streamout_write_index;
84 int param_streamout_offset[4];
85 int param_vertex_id;
86 int param_rel_auto_id;
87 int param_vs_prim_id;
88 int param_instance_id;
89 int param_vertex_index0;
90 int param_tes_u;
91 int param_tes_v;
92 int param_tes_rel_patch_id;
93 int param_tes_patch_id;
94 int param_es2gs_offset;
95 int param_oc_lds;
96
97 /* Sets a bit if the dynamic HS control word was 0x80000000. The bit is
98 * 0x800000 for VS, 0x1 for ES.
99 */
100 int param_tess_offchip;
101
102 LLVMTargetMachineRef tm;
103
104 unsigned range_md_kind;
105 unsigned tbaa_md_kind;
106 unsigned uniform_md_kind;
107 LLVMValueRef tbaa_const_md;
108 LLVMValueRef empty_md;
109
110 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
111 LLVMValueRef lds;
112 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
113 LLVMValueRef shader_buffers[SI_NUM_SHADER_BUFFERS];
114 LLVMValueRef sampler_views[SI_NUM_SAMPLERS];
115 LLVMValueRef sampler_states[SI_NUM_SAMPLERS];
116 LLVMValueRef fmasks[SI_NUM_SAMPLERS];
117 LLVMValueRef images[SI_NUM_IMAGES];
118 LLVMValueRef so_buffers[4];
119 LLVMValueRef esgs_ring;
120 LLVMValueRef gsvs_ring[4];
121 LLVMValueRef gs_next_vertex[4];
122 LLVMValueRef return_value;
123
124 LLVMTypeRef voidt;
125 LLVMTypeRef i1;
126 LLVMTypeRef i8;
127 LLVMTypeRef i32;
128 LLVMTypeRef i64;
129 LLVMTypeRef i128;
130 LLVMTypeRef f32;
131 LLVMTypeRef v16i8;
132 LLVMTypeRef v2i32;
133 LLVMTypeRef v4i32;
134 LLVMTypeRef v4f32;
135 LLVMTypeRef v8i32;
136
137 LLVMValueRef shared_memory;
138 };
139
140 static struct si_shader_context *si_shader_context(
141 struct lp_build_tgsi_context *bld_base)
142 {
143 return (struct si_shader_context *)bld_base;
144 }
145
146 static void si_init_shader_ctx(struct si_shader_context *ctx,
147 struct si_screen *sscreen,
148 struct si_shader *shader,
149 LLVMTargetMachineRef tm);
150
151 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
152 struct lp_build_tgsi_context *bld_base,
153 struct lp_build_emit_data *emit_data);
154
155 /* Ideally pass the sample mask input to the PS epilog as v13, which
156 * is its usual location, so that the shader doesn't have to add v_mov.
157 */
158 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
159
160 /* The VS location of the PrimitiveID input is the same in the epilog,
161 * so that the main shader part doesn't have to move it.
162 */
163 #define VS_EPILOG_PRIMID_LOC 2
164
165 #define PERSPECTIVE_BASE 0
166 #define LINEAR_BASE 9
167
168 #define SAMPLE_OFFSET 0
169 #define CENTER_OFFSET 2
170 #define CENTROID_OFSET 4
171
172 #define USE_SGPR_MAX_SUFFIX_LEN 5
173 #define CONST_ADDR_SPACE 2
174 #define LOCAL_ADDR_SPACE 3
175 #define USER_SGPR_ADDR_SPACE 8
176
177
178 #define SENDMSG_GS 2
179 #define SENDMSG_GS_DONE 3
180
181 #define SENDMSG_GS_OP_NOP (0 << 4)
182 #define SENDMSG_GS_OP_CUT (1 << 4)
183 #define SENDMSG_GS_OP_EMIT (2 << 4)
184 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
185
186 /**
187 * Returns a unique index for a semantic name and index. The index must be
188 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
189 * calculated.
190 */
191 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
192 {
193 switch (semantic_name) {
194 case TGSI_SEMANTIC_POSITION:
195 return 0;
196 case TGSI_SEMANTIC_PSIZE:
197 return 1;
198 case TGSI_SEMANTIC_CLIPDIST:
199 assert(index <= 1);
200 return 2 + index;
201 case TGSI_SEMANTIC_GENERIC:
202 if (index <= 63-4)
203 return 4 + index;
204 else
205 /* same explanation as in the default statement,
206 * the only user hitting this is st/nine.
207 */
208 return 0;
209
210 /* patch indices are completely separate and thus start from 0 */
211 case TGSI_SEMANTIC_TESSOUTER:
212 return 0;
213 case TGSI_SEMANTIC_TESSINNER:
214 return 1;
215 case TGSI_SEMANTIC_PATCH:
216 return 2 + index;
217
218 default:
219 /* Don't fail here. The result of this function is only used
220 * for LS, TCS, TES, and GS, where legacy GL semantics can't
221 * occur, but this function is called for all vertex shaders
222 * before it's known whether LS will be compiled or not.
223 */
224 return 0;
225 }
226 }
227
228 /**
229 * Get the value of a shader input parameter and extract a bitfield.
230 */
231 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
232 unsigned param, unsigned rshift,
233 unsigned bitwidth)
234 {
235 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
236 LLVMValueRef value = LLVMGetParam(ctx->radeon_bld.main_fn,
237 param);
238
239 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
240 value = bitcast(&ctx->radeon_bld.soa.bld_base,
241 TGSI_TYPE_UNSIGNED, value);
242
243 if (rshift)
244 value = LLVMBuildLShr(gallivm->builder, value,
245 lp_build_const_int32(gallivm, rshift), "");
246
247 if (rshift + bitwidth < 32) {
248 unsigned mask = (1 << bitwidth) - 1;
249 value = LLVMBuildAnd(gallivm->builder, value,
250 lp_build_const_int32(gallivm, mask), "");
251 }
252
253 return value;
254 }
255
256 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
257 {
258 switch (ctx->type) {
259 case PIPE_SHADER_TESS_CTRL:
260 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
261
262 case PIPE_SHADER_TESS_EVAL:
263 return LLVMGetParam(ctx->radeon_bld.main_fn,
264 ctx->param_tes_rel_patch_id);
265
266 default:
267 assert(0);
268 return NULL;
269 }
270 }
271
272 /* Tessellation shaders pass outputs to the next shader using LDS.
273 *
274 * LS outputs = TCS inputs
275 * TCS outputs = TES inputs
276 *
277 * The LDS layout is:
278 * - TCS inputs for patch 0
279 * - TCS inputs for patch 1
280 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
281 * - ...
282 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
283 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
284 * - TCS outputs for patch 1
285 * - Per-patch TCS outputs for patch 1
286 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
287 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
288 * - ...
289 *
290 * All three shaders VS(LS), TCS, TES share the same LDS space.
291 */
292
293 static LLVMValueRef
294 get_tcs_in_patch_stride(struct si_shader_context *ctx)
295 {
296 if (ctx->type == PIPE_SHADER_VERTEX)
297 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
298 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
299 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
300 else {
301 assert(0);
302 return NULL;
303 }
304 }
305
306 static LLVMValueRef
307 get_tcs_out_patch_stride(struct si_shader_context *ctx)
308 {
309 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
310 }
311
312 static LLVMValueRef
313 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
314 {
315 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
316 unpack_param(ctx,
317 SI_PARAM_TCS_OUT_OFFSETS,
318 0, 16),
319 4);
320 }
321
322 static LLVMValueRef
323 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
324 {
325 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
326 unpack_param(ctx,
327 SI_PARAM_TCS_OUT_OFFSETS,
328 16, 16),
329 4);
330 }
331
332 static LLVMValueRef
333 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
334 {
335 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
336 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
337 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
338
339 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
340 }
341
342 static LLVMValueRef
343 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
344 {
345 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
346 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
347 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
348 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
349
350 return LLVMBuildAdd(gallivm->builder, patch0_offset,
351 LLVMBuildMul(gallivm->builder, patch_stride,
352 rel_patch_id, ""),
353 "");
354 }
355
356 static LLVMValueRef
357 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
358 {
359 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
360 LLVMValueRef patch0_patch_data_offset =
361 get_tcs_out_patch0_patch_data_offset(ctx);
362 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
363 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
364
365 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
366 LLVMBuildMul(gallivm->builder, patch_stride,
367 rel_patch_id, ""),
368 "");
369 }
370
371 static void build_indexed_store(struct si_shader_context *ctx,
372 LLVMValueRef base_ptr, LLVMValueRef index,
373 LLVMValueRef value)
374 {
375 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
376 struct gallivm_state *gallivm = bld_base->base.gallivm;
377 LLVMValueRef indices[2], pointer;
378
379 indices[0] = bld_base->uint_bld.zero;
380 indices[1] = index;
381
382 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
383 LLVMBuildStore(gallivm->builder, value, pointer);
384 }
385
386 /**
387 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
388 * It's equivalent to doing a load from &base_ptr[index].
389 *
390 * \param base_ptr Where the array starts.
391 * \param index The element index into the array.
392 * \param uniform Whether the base_ptr and index can be assumed to be
393 * dynamically uniform
394 */
395 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
396 LLVMValueRef base_ptr, LLVMValueRef index,
397 bool uniform)
398 {
399 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
400 struct gallivm_state *gallivm = bld_base->base.gallivm;
401 LLVMValueRef indices[2], pointer;
402
403 indices[0] = bld_base->uint_bld.zero;
404 indices[1] = index;
405
406 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
407 if (uniform)
408 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
409 return LLVMBuildLoad(gallivm->builder, pointer, "");
410 }
411
412 /**
413 * Do a load from &base_ptr[index], but also add a flag that it's loading
414 * a constant from a dynamically uniform index.
415 */
416 static LLVMValueRef build_indexed_load_const(
417 struct si_shader_context *ctx,
418 LLVMValueRef base_ptr, LLVMValueRef index)
419 {
420 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
421 LLVMSetMetadata(result, ctx->tbaa_md_kind, ctx->tbaa_const_md);
422 return result;
423 }
424
425 static LLVMValueRef get_instance_index_for_fetch(
426 struct radeon_llvm_context *radeon_bld,
427 unsigned param_start_instance, unsigned divisor)
428 {
429 struct si_shader_context *ctx =
430 si_shader_context(&radeon_bld->soa.bld_base);
431 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
432
433 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
434 ctx->param_instance_id);
435
436 /* The division must be done before START_INSTANCE is added. */
437 if (divisor > 1)
438 result = LLVMBuildUDiv(gallivm->builder, result,
439 lp_build_const_int32(gallivm, divisor), "");
440
441 return LLVMBuildAdd(gallivm->builder, result,
442 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
443 }
444
445 static void declare_input_vs(
446 struct radeon_llvm_context *radeon_bld,
447 unsigned input_index,
448 const struct tgsi_full_declaration *decl)
449 {
450 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
451 struct gallivm_state *gallivm = base->gallivm;
452 struct si_shader_context *ctx =
453 si_shader_context(&radeon_bld->soa.bld_base);
454 unsigned divisor =
455 ctx->shader->key.vs.prolog.instance_divisors[input_index];
456
457 unsigned chan;
458
459 LLVMValueRef t_list_ptr;
460 LLVMValueRef t_offset;
461 LLVMValueRef t_list;
462 LLVMValueRef attribute_offset;
463 LLVMValueRef buffer_index;
464 LLVMValueRef args[3];
465 LLVMValueRef input;
466
467 /* Load the T list */
468 t_list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
469
470 t_offset = lp_build_const_int32(gallivm, input_index);
471
472 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
473
474 /* Build the attribute offset */
475 attribute_offset = lp_build_const_int32(gallivm, 0);
476
477 if (!ctx->is_monolithic) {
478 buffer_index = LLVMGetParam(radeon_bld->main_fn,
479 ctx->param_vertex_index0 +
480 input_index);
481 } else if (divisor) {
482 /* Build index from instance ID, start instance and divisor */
483 ctx->shader->info.uses_instanceid = true;
484 buffer_index = get_instance_index_for_fetch(&ctx->radeon_bld,
485 SI_PARAM_START_INSTANCE,
486 divisor);
487 } else {
488 /* Load the buffer index for vertices. */
489 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
490 ctx->param_vertex_id);
491 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
492 SI_PARAM_BASE_VERTEX);
493 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
494 }
495
496 args[0] = t_list;
497 args[1] = attribute_offset;
498 args[2] = buffer_index;
499 input = lp_build_intrinsic(gallivm->builder,
500 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
501 LLVMReadNoneAttribute);
502
503 /* Break up the vec4 into individual components */
504 for (chan = 0; chan < 4; chan++) {
505 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
506 /* XXX: Use a helper function for this. There is one in
507 * tgsi_llvm.c. */
508 ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
509 LLVMBuildExtractElement(gallivm->builder,
510 input, llvm_chan, "");
511 }
512 }
513
514 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
515 unsigned swizzle)
516 {
517 struct si_shader_context *ctx = si_shader_context(bld_base);
518
519 if (swizzle > 0)
520 return bld_base->uint_bld.zero;
521
522 switch (ctx->type) {
523 case PIPE_SHADER_VERTEX:
524 return LLVMGetParam(ctx->radeon_bld.main_fn,
525 ctx->param_vs_prim_id);
526 case PIPE_SHADER_TESS_CTRL:
527 return LLVMGetParam(ctx->radeon_bld.main_fn,
528 SI_PARAM_PATCH_ID);
529 case PIPE_SHADER_TESS_EVAL:
530 return LLVMGetParam(ctx->radeon_bld.main_fn,
531 ctx->param_tes_patch_id);
532 case PIPE_SHADER_GEOMETRY:
533 return LLVMGetParam(ctx->radeon_bld.main_fn,
534 SI_PARAM_PRIMITIVE_ID);
535 default:
536 assert(0);
537 return bld_base->uint_bld.zero;
538 }
539 }
540
541 /**
542 * Return the value of tgsi_ind_register for indexing.
543 * This is the indirect index with the constant offset added to it.
544 */
545 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
546 const struct tgsi_ind_register *ind,
547 int rel_index)
548 {
549 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
550 LLVMValueRef result;
551
552 result = ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
553 result = LLVMBuildLoad(gallivm->builder, result, "");
554 result = LLVMBuildAdd(gallivm->builder, result,
555 lp_build_const_int32(gallivm, rel_index), "");
556 return result;
557 }
558
559 /**
560 * Like get_indirect_index, but restricts the return value to a (possibly
561 * undefined) value inside [0..num).
562 */
563 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
564 const struct tgsi_ind_register *ind,
565 int rel_index, unsigned num)
566 {
567 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
568 LLVMBuilderRef builder = gallivm->builder;
569 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
570 LLVMValueRef c_max = LLVMConstInt(ctx->i32, num - 1, 0);
571 LLVMValueRef cc;
572
573 /* LLVM 3.8: If indirect resource indexing is used:
574 * - SI & CIK hang
575 * - VI crashes
576 */
577 if (HAVE_LLVM <= 0x0308)
578 return LLVMGetUndef(ctx->i32);
579
580 if (util_is_power_of_two(num)) {
581 result = LLVMBuildAnd(builder, result, c_max, "");
582 } else {
583 /* In theory, this MAX pattern should result in code that is
584 * as good as the bit-wise AND above.
585 *
586 * In practice, LLVM generates worse code (at the time of
587 * writing), because its value tracking is not strong enough.
588 */
589 cc = LLVMBuildICmp(builder, LLVMIntULE, result, c_max, "");
590 result = LLVMBuildSelect(builder, cc, result, c_max, "");
591 }
592
593 return result;
594 }
595
596
597 /**
598 * Calculate a dword address given an input or output register and a stride.
599 */
600 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
601 const struct tgsi_full_dst_register *dst,
602 const struct tgsi_full_src_register *src,
603 LLVMValueRef vertex_dw_stride,
604 LLVMValueRef base_addr)
605 {
606 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
607 struct tgsi_shader_info *info = &ctx->shader->selector->info;
608 ubyte *name, *index, *array_first;
609 int first, param;
610 struct tgsi_full_dst_register reg;
611
612 /* Set the register description. The address computation is the same
613 * for sources and destinations. */
614 if (src) {
615 reg.Register.File = src->Register.File;
616 reg.Register.Index = src->Register.Index;
617 reg.Register.Indirect = src->Register.Indirect;
618 reg.Register.Dimension = src->Register.Dimension;
619 reg.Indirect = src->Indirect;
620 reg.Dimension = src->Dimension;
621 reg.DimIndirect = src->DimIndirect;
622 } else
623 reg = *dst;
624
625 /* If the register is 2-dimensional (e.g. an array of vertices
626 * in a primitive), calculate the base address of the vertex. */
627 if (reg.Register.Dimension) {
628 LLVMValueRef index;
629
630 if (reg.Dimension.Indirect)
631 index = get_indirect_index(ctx, &reg.DimIndirect,
632 reg.Dimension.Index);
633 else
634 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
635
636 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
637 LLVMBuildMul(gallivm->builder, index,
638 vertex_dw_stride, ""), "");
639 }
640
641 /* Get information about the register. */
642 if (reg.Register.File == TGSI_FILE_INPUT) {
643 name = info->input_semantic_name;
644 index = info->input_semantic_index;
645 array_first = info->input_array_first;
646 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
647 name = info->output_semantic_name;
648 index = info->output_semantic_index;
649 array_first = info->output_array_first;
650 } else {
651 assert(0);
652 return NULL;
653 }
654
655 if (reg.Register.Indirect) {
656 /* Add the relative address of the element. */
657 LLVMValueRef ind_index;
658
659 if (reg.Indirect.ArrayID)
660 first = array_first[reg.Indirect.ArrayID];
661 else
662 first = reg.Register.Index;
663
664 ind_index = get_indirect_index(ctx, &reg.Indirect,
665 reg.Register.Index - first);
666
667 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
668 LLVMBuildMul(gallivm->builder, ind_index,
669 lp_build_const_int32(gallivm, 4), ""), "");
670
671 param = si_shader_io_get_unique_index(name[first], index[first]);
672 } else {
673 param = si_shader_io_get_unique_index(name[reg.Register.Index],
674 index[reg.Register.Index]);
675 }
676
677 /* Add the base address of the element. */
678 return LLVMBuildAdd(gallivm->builder, base_addr,
679 lp_build_const_int32(gallivm, param * 4), "");
680 }
681
682 /* The offchip buffer layout for TCS->TES is
683 *
684 * - attribute 0 of patch 0 vertex 0
685 * - attribute 0 of patch 0 vertex 1
686 * - attribute 0 of patch 0 vertex 2
687 * ...
688 * - attribute 0 of patch 1 vertex 0
689 * - attribute 0 of patch 1 vertex 1
690 * ...
691 * - attribute 1 of patch 0 vertex 0
692 * - attribute 1 of patch 0 vertex 1
693 * ...
694 * - per patch attribute 0 of patch 0
695 * - per patch attribute 0 of patch 1
696 * ...
697 *
698 * Note that every attribute has 4 components.
699 */
700 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
701 LLVMValueRef vertex_index,
702 LLVMValueRef param_index)
703 {
704 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
705 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
706 LLVMValueRef param_stride, constant16;
707
708 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
709 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
710 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
711 num_patches, "");
712
713 constant16 = lp_build_const_int32(gallivm, 16);
714 if (vertex_index) {
715 base_addr = LLVMBuildMul(gallivm->builder, get_rel_patch_id(ctx),
716 vertices_per_patch, "");
717
718 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
719 vertex_index, "");
720
721 param_stride = total_vertices;
722 } else {
723 base_addr = get_rel_patch_id(ctx);
724 param_stride = num_patches;
725 }
726
727 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
728 LLVMBuildMul(gallivm->builder, param_index,
729 param_stride, ""), "");
730
731 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
732
733 if (!vertex_index) {
734 LLVMValueRef patch_data_offset =
735 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
736
737 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
738 patch_data_offset, "");
739 }
740 return base_addr;
741 }
742
743 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
744 struct si_shader_context *ctx,
745 const struct tgsi_full_dst_register *dst,
746 const struct tgsi_full_src_register *src)
747 {
748 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
749 struct tgsi_shader_info *info = &ctx->shader->selector->info;
750 ubyte *name, *index, *array_first;
751 struct tgsi_full_src_register reg;
752 LLVMValueRef vertex_index = NULL;
753 LLVMValueRef param_index = NULL;
754 unsigned param_index_base, param_base;
755
756 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
757
758 if (reg.Register.Dimension) {
759
760 if (reg.Dimension.Indirect)
761 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
762 reg.Dimension.Index);
763 else
764 vertex_index = lp_build_const_int32(gallivm,
765 reg.Dimension.Index);
766 }
767
768 /* Get information about the register. */
769 if (reg.Register.File == TGSI_FILE_INPUT) {
770 name = info->input_semantic_name;
771 index = info->input_semantic_index;
772 array_first = info->input_array_first;
773 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
774 name = info->output_semantic_name;
775 index = info->output_semantic_index;
776 array_first = info->output_array_first;
777 } else {
778 assert(0);
779 return NULL;
780 }
781
782 if (reg.Register.Indirect) {
783 if (reg.Indirect.ArrayID)
784 param_base = array_first[reg.Indirect.ArrayID];
785 else
786 param_base = reg.Register.Index;
787
788 param_index = get_indirect_index(ctx, &reg.Indirect,
789 reg.Register.Index - param_base);
790
791 } else {
792 param_base = reg.Register.Index;
793 param_index = lp_build_const_int32(gallivm, 0);
794 }
795
796 param_index_base = si_shader_io_get_unique_index(name[param_base],
797 index[param_base]);
798
799 param_index = LLVMBuildAdd(gallivm->builder, param_index,
800 lp_build_const_int32(gallivm, param_index_base),
801 "");
802
803 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
804 }
805
806 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
807 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
808 * or v4i32 (num_channels=3,4). */
809 static void build_tbuffer_store(struct si_shader_context *ctx,
810 LLVMValueRef rsrc,
811 LLVMValueRef vdata,
812 unsigned num_channels,
813 LLVMValueRef vaddr,
814 LLVMValueRef soffset,
815 unsigned inst_offset,
816 unsigned dfmt,
817 unsigned nfmt,
818 unsigned offen,
819 unsigned idxen,
820 unsigned glc,
821 unsigned slc,
822 unsigned tfe)
823 {
824 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
825 LLVMValueRef args[] = {
826 rsrc,
827 vdata,
828 LLVMConstInt(ctx->i32, num_channels, 0),
829 vaddr,
830 soffset,
831 LLVMConstInt(ctx->i32, inst_offset, 0),
832 LLVMConstInt(ctx->i32, dfmt, 0),
833 LLVMConstInt(ctx->i32, nfmt, 0),
834 LLVMConstInt(ctx->i32, offen, 0),
835 LLVMConstInt(ctx->i32, idxen, 0),
836 LLVMConstInt(ctx->i32, glc, 0),
837 LLVMConstInt(ctx->i32, slc, 0),
838 LLVMConstInt(ctx->i32, tfe, 0)
839 };
840
841 /* The instruction offset field has 12 bits */
842 assert(offen || inst_offset < (1 << 12));
843
844 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
845 unsigned func = CLAMP(num_channels, 1, 3) - 1;
846 const char *types[] = {"i32", "v2i32", "v4i32"};
847 char name[256];
848 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
849
850 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
851 args, ARRAY_SIZE(args), 0);
852 }
853
854 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
855 LLVMValueRef rsrc,
856 LLVMValueRef vdata,
857 unsigned num_channels,
858 LLVMValueRef vaddr,
859 LLVMValueRef soffset,
860 unsigned inst_offset)
861 {
862 static unsigned dfmt[] = {
863 V_008F0C_BUF_DATA_FORMAT_32,
864 V_008F0C_BUF_DATA_FORMAT_32_32,
865 V_008F0C_BUF_DATA_FORMAT_32_32_32,
866 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
867 };
868 assert(num_channels >= 1 && num_channels <= 4);
869
870 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
871 inst_offset, dfmt[num_channels-1],
872 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
873 }
874
875 static LLVMValueRef build_buffer_load(struct si_shader_context *ctx,
876 LLVMValueRef rsrc,
877 int num_channels,
878 LLVMValueRef vindex,
879 LLVMValueRef voffset,
880 LLVMValueRef soffset,
881 unsigned inst_offset,
882 unsigned glc,
883 unsigned slc)
884 {
885 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
886 unsigned func = CLAMP(num_channels, 1, 3) - 1;
887
888 if (HAVE_LLVM >= 0x309) {
889 LLVMValueRef args[] = {
890 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, ""),
891 vindex ? vindex : LLVMConstInt(ctx->i32, 0, 0),
892 LLVMConstInt(ctx->i32, inst_offset, 0),
893 LLVMConstInt(ctx->i1, glc, 0),
894 LLVMConstInt(ctx->i1, slc, 0)
895 };
896
897 LLVMTypeRef types[] = {ctx->f32, LLVMVectorType(ctx->f32, 2),
898 ctx->v4f32};
899 const char *type_names[] = {"f32", "v2f32", "v4f32"};
900 char name[256];
901
902 if (voffset) {
903 args[2] = LLVMBuildAdd(gallivm->builder, args[2], voffset,
904 "");
905 }
906
907 if (soffset) {
908 args[2] = LLVMBuildAdd(gallivm->builder, args[2], soffset,
909 "");
910 }
911
912 snprintf(name, sizeof(name), "llvm.amdgcn.buffer.load.%s",
913 type_names[func]);
914
915 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
916 ARRAY_SIZE(args), LLVMReadOnlyAttribute);
917 } else {
918 LLVMValueRef args[] = {
919 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v16i8, ""),
920 voffset ? voffset : vindex,
921 soffset,
922 LLVMConstInt(ctx->i32, inst_offset, 0),
923 LLVMConstInt(ctx->i32, voffset ? 1 : 0, 0), // offen
924 LLVMConstInt(ctx->i32, vindex ? 1 : 0, 0), //idxen
925 LLVMConstInt(ctx->i32, glc, 0),
926 LLVMConstInt(ctx->i32, slc, 0),
927 LLVMConstInt(ctx->i32, 0, 0), // TFE
928 };
929
930 LLVMTypeRef types[] = {ctx->i32, LLVMVectorType(ctx->i32, 2),
931 ctx->v4i32};
932 const char *type_names[] = {"i32", "v2i32", "v4i32"};
933 const char *arg_type = "i32";
934 char name[256];
935
936 if (voffset && vindex) {
937 LLVMValueRef vaddr[] = {vindex, voffset};
938
939 arg_type = "v2i32";
940 args[1] = lp_build_gather_values(gallivm, vaddr, 2);
941 }
942
943 snprintf(name, sizeof(name), "llvm.SI.buffer.load.dword.%s.%s",
944 type_names[func], arg_type);
945
946 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
947 ARRAY_SIZE(args), LLVMReadOnlyAttribute);
948 }
949 }
950
951 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
952 enum tgsi_opcode_type type, unsigned swizzle,
953 LLVMValueRef buffer, LLVMValueRef offset,
954 LLVMValueRef base)
955 {
956 struct si_shader_context *ctx = si_shader_context(bld_base);
957 struct gallivm_state *gallivm = bld_base->base.gallivm;
958 LLVMValueRef value, value2;
959 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
960 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
961
962 if (swizzle == ~0) {
963 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
964 0, 1, 0);
965
966 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
967 }
968
969 if (!tgsi_type_is_64bit(type)) {
970 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
971 0, 1, 0);
972
973 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
974 return LLVMBuildExtractElement(gallivm->builder, value,
975 lp_build_const_int32(gallivm, swizzle), "");
976 }
977
978 value = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
979 swizzle * 4, 1, 0);
980
981 value2 = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
982 swizzle * 4 + 4, 1, 0);
983
984 return radeon_llvm_emit_fetch_64bit(bld_base, type, value, value2);
985 }
986
987 /**
988 * Load from LDS.
989 *
990 * \param type output value type
991 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
992 * \param dw_addr address in dwords
993 */
994 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
995 enum tgsi_opcode_type type, unsigned swizzle,
996 LLVMValueRef dw_addr)
997 {
998 struct si_shader_context *ctx = si_shader_context(bld_base);
999 struct gallivm_state *gallivm = bld_base->base.gallivm;
1000 LLVMValueRef value;
1001
1002 if (swizzle == ~0) {
1003 LLVMValueRef values[TGSI_NUM_CHANNELS];
1004
1005 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1006 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1007
1008 return lp_build_gather_values(bld_base->base.gallivm, values,
1009 TGSI_NUM_CHANNELS);
1010 }
1011
1012 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1013 lp_build_const_int32(gallivm, swizzle));
1014
1015 value = build_indexed_load(ctx, ctx->lds, dw_addr, false);
1016 if (tgsi_type_is_64bit(type)) {
1017 LLVMValueRef value2;
1018 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1019 lp_build_const_int32(gallivm, swizzle + 1));
1020 value2 = build_indexed_load(ctx, ctx->lds, dw_addr, false);
1021 return radeon_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1022 }
1023
1024 return LLVMBuildBitCast(gallivm->builder, value,
1025 tgsi2llvmtype(bld_base, type), "");
1026 }
1027
1028 /**
1029 * Store to LDS.
1030 *
1031 * \param swizzle offset (typically 0..3)
1032 * \param dw_addr address in dwords
1033 * \param value value to store
1034 */
1035 static void lds_store(struct lp_build_tgsi_context *bld_base,
1036 unsigned swizzle, LLVMValueRef dw_addr,
1037 LLVMValueRef value)
1038 {
1039 struct si_shader_context *ctx = si_shader_context(bld_base);
1040 struct gallivm_state *gallivm = bld_base->base.gallivm;
1041
1042 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1043 lp_build_const_int32(gallivm, swizzle));
1044
1045 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1046 build_indexed_store(ctx, ctx->lds,
1047 dw_addr, value);
1048 }
1049
1050 static LLVMValueRef fetch_input_tcs(
1051 struct lp_build_tgsi_context *bld_base,
1052 const struct tgsi_full_src_register *reg,
1053 enum tgsi_opcode_type type, unsigned swizzle)
1054 {
1055 struct si_shader_context *ctx = si_shader_context(bld_base);
1056 LLVMValueRef dw_addr, stride;
1057
1058 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
1059 dw_addr = get_tcs_in_current_patch_offset(ctx);
1060 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1061
1062 return lds_load(bld_base, type, swizzle, dw_addr);
1063 }
1064
1065 static LLVMValueRef fetch_output_tcs(
1066 struct lp_build_tgsi_context *bld_base,
1067 const struct tgsi_full_src_register *reg,
1068 enum tgsi_opcode_type type, unsigned swizzle)
1069 {
1070 struct si_shader_context *ctx = si_shader_context(bld_base);
1071 LLVMValueRef dw_addr, stride;
1072
1073 if (reg->Register.Dimension) {
1074 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1075 dw_addr = get_tcs_out_current_patch_offset(ctx);
1076 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1077 } else {
1078 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1079 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1080 }
1081
1082 return lds_load(bld_base, type, swizzle, dw_addr);
1083 }
1084
1085 static LLVMValueRef fetch_input_tes(
1086 struct lp_build_tgsi_context *bld_base,
1087 const struct tgsi_full_src_register *reg,
1088 enum tgsi_opcode_type type, unsigned swizzle)
1089 {
1090 struct si_shader_context *ctx = si_shader_context(bld_base);
1091 struct gallivm_state *gallivm = bld_base->base.gallivm;
1092 LLVMValueRef rw_buffers, buffer, base, addr;
1093
1094 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1095 SI_PARAM_RW_BUFFERS);
1096 buffer = build_indexed_load_const(ctx, rw_buffers,
1097 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1098
1099 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1100 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1101
1102 return buffer_load(bld_base, type, swizzle, buffer, base, addr);
1103 }
1104
1105 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1106 const struct tgsi_full_instruction *inst,
1107 const struct tgsi_opcode_info *info,
1108 LLVMValueRef dst[4])
1109 {
1110 struct si_shader_context *ctx = si_shader_context(bld_base);
1111 struct gallivm_state *gallivm = bld_base->base.gallivm;
1112 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
1113 unsigned chan_index;
1114 LLVMValueRef dw_addr, stride;
1115 LLVMValueRef rw_buffers, buffer, base, buf_addr;
1116 LLVMValueRef values[4];
1117
1118 /* Only handle per-patch and per-vertex outputs here.
1119 * Vectors will be lowered to scalars and this function will be called again.
1120 */
1121 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1122 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1123 radeon_llvm_emit_store(bld_base, inst, info, dst);
1124 return;
1125 }
1126
1127 if (reg->Register.Dimension) {
1128 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1129 dw_addr = get_tcs_out_current_patch_offset(ctx);
1130 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1131 } else {
1132 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1133 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1134 }
1135
1136 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1137 SI_PARAM_RW_BUFFERS);
1138 buffer = build_indexed_load_const(ctx, rw_buffers,
1139 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1140
1141 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1142 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1143
1144
1145 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1146 LLVMValueRef value = dst[chan_index];
1147
1148 if (inst->Instruction.Saturate)
1149 value = radeon_llvm_saturate(bld_base, value);
1150
1151 lds_store(bld_base, chan_index, dw_addr, value);
1152
1153 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1154 values[chan_index] = value;
1155
1156 if (inst->Dst[0].Register.WriteMask != 0xF) {
1157 build_tbuffer_store_dwords(ctx, buffer, value, 1,
1158 buf_addr, base,
1159 4 * chan_index);
1160 }
1161 }
1162
1163 if (inst->Dst[0].Register.WriteMask == 0xF) {
1164 LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
1165 values, 4);
1166 build_tbuffer_store_dwords(ctx, buffer, value, 4, buf_addr,
1167 base, 0);
1168 }
1169 }
1170
1171 static LLVMValueRef fetch_input_gs(
1172 struct lp_build_tgsi_context *bld_base,
1173 const struct tgsi_full_src_register *reg,
1174 enum tgsi_opcode_type type,
1175 unsigned swizzle)
1176 {
1177 struct lp_build_context *base = &bld_base->base;
1178 struct si_shader_context *ctx = si_shader_context(bld_base);
1179 struct si_shader *shader = ctx->shader;
1180 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1181 struct gallivm_state *gallivm = base->gallivm;
1182 LLVMValueRef vtx_offset;
1183 LLVMValueRef args[9];
1184 unsigned vtx_offset_param;
1185 struct tgsi_shader_info *info = &shader->selector->info;
1186 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1187 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1188 unsigned param;
1189 LLVMValueRef value;
1190
1191 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1192 return get_primitive_id(bld_base, swizzle);
1193
1194 if (!reg->Register.Dimension)
1195 return NULL;
1196
1197 if (swizzle == ~0) {
1198 LLVMValueRef values[TGSI_NUM_CHANNELS];
1199 unsigned chan;
1200 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1201 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1202 }
1203 return lp_build_gather_values(bld_base->base.gallivm, values,
1204 TGSI_NUM_CHANNELS);
1205 }
1206
1207 /* Get the vertex offset parameter */
1208 vtx_offset_param = reg->Dimension.Index;
1209 if (vtx_offset_param < 2) {
1210 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1211 } else {
1212 assert(vtx_offset_param < 6);
1213 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1214 }
1215 vtx_offset = lp_build_mul_imm(uint,
1216 LLVMGetParam(ctx->radeon_bld.main_fn,
1217 vtx_offset_param),
1218 4);
1219
1220 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1221 args[0] = ctx->esgs_ring;
1222 args[1] = vtx_offset;
1223 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
1224 args[3] = uint->zero;
1225 args[4] = uint->one; /* OFFEN */
1226 args[5] = uint->zero; /* IDXEN */
1227 args[6] = uint->one; /* GLC */
1228 args[7] = uint->zero; /* SLC */
1229 args[8] = uint->zero; /* TFE */
1230
1231 value = lp_build_intrinsic(gallivm->builder,
1232 "llvm.SI.buffer.load.dword.i32.i32",
1233 ctx->i32, args, 9,
1234 LLVMReadOnlyAttribute);
1235 if (tgsi_type_is_64bit(type)) {
1236 LLVMValueRef value2;
1237 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
1238 value2 = lp_build_intrinsic(gallivm->builder,
1239 "llvm.SI.buffer.load.dword.i32.i32",
1240 ctx->i32, args, 9,
1241 LLVMReadOnlyAttribute);
1242 return radeon_llvm_emit_fetch_64bit(bld_base, type,
1243 value, value2);
1244 }
1245 return LLVMBuildBitCast(gallivm->builder,
1246 value,
1247 tgsi2llvmtype(bld_base, type), "");
1248 }
1249
1250 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1251 {
1252 switch (interpolate) {
1253 case TGSI_INTERPOLATE_CONSTANT:
1254 return 0;
1255
1256 case TGSI_INTERPOLATE_LINEAR:
1257 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1258 return SI_PARAM_LINEAR_SAMPLE;
1259 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1260 return SI_PARAM_LINEAR_CENTROID;
1261 else
1262 return SI_PARAM_LINEAR_CENTER;
1263 break;
1264 case TGSI_INTERPOLATE_COLOR:
1265 case TGSI_INTERPOLATE_PERSPECTIVE:
1266 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1267 return SI_PARAM_PERSP_SAMPLE;
1268 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1269 return SI_PARAM_PERSP_CENTROID;
1270 else
1271 return SI_PARAM_PERSP_CENTER;
1272 break;
1273 default:
1274 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1275 return -1;
1276 }
1277 }
1278
1279 /* This shouldn't be used by explicit INTERP opcodes. */
1280 static unsigned select_interp_param(struct si_shader_context *ctx,
1281 unsigned param)
1282 {
1283 if (!ctx->is_monolithic)
1284 return param;
1285
1286 if (ctx->shader->key.ps.prolog.force_persp_sample_interp) {
1287 switch (param) {
1288 case SI_PARAM_PERSP_CENTROID:
1289 case SI_PARAM_PERSP_CENTER:
1290 return SI_PARAM_PERSP_SAMPLE;
1291 }
1292 }
1293 if (ctx->shader->key.ps.prolog.force_linear_sample_interp) {
1294 switch (param) {
1295 case SI_PARAM_LINEAR_CENTROID:
1296 case SI_PARAM_LINEAR_CENTER:
1297 return SI_PARAM_LINEAR_SAMPLE;
1298 }
1299 }
1300 if (ctx->shader->key.ps.prolog.force_persp_center_interp) {
1301 switch (param) {
1302 case SI_PARAM_PERSP_CENTROID:
1303 case SI_PARAM_PERSP_SAMPLE:
1304 return SI_PARAM_PERSP_CENTER;
1305 }
1306 }
1307 if (ctx->shader->key.ps.prolog.force_linear_center_interp) {
1308 switch (param) {
1309 case SI_PARAM_LINEAR_CENTROID:
1310 case SI_PARAM_LINEAR_SAMPLE:
1311 return SI_PARAM_LINEAR_CENTER;
1312 }
1313 }
1314
1315 return param;
1316 }
1317
1318 /**
1319 * Interpolate a fragment shader input.
1320 *
1321 * @param ctx context
1322 * @param input_index index of the input in hardware
1323 * @param semantic_name TGSI_SEMANTIC_*
1324 * @param semantic_index semantic index
1325 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1326 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1327 * @param interp_param interpolation weights (i,j)
1328 * @param prim_mask SI_PARAM_PRIM_MASK
1329 * @param face SI_PARAM_FRONT_FACE
1330 * @param result the return value (4 components)
1331 */
1332 static void interp_fs_input(struct si_shader_context *ctx,
1333 unsigned input_index,
1334 unsigned semantic_name,
1335 unsigned semantic_index,
1336 unsigned num_interp_inputs,
1337 unsigned colors_read_mask,
1338 LLVMValueRef interp_param,
1339 LLVMValueRef prim_mask,
1340 LLVMValueRef face,
1341 LLVMValueRef result[4])
1342 {
1343 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
1344 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1345 struct gallivm_state *gallivm = base->gallivm;
1346 const char *intr_name;
1347 LLVMValueRef attr_number;
1348
1349 unsigned chan;
1350
1351 attr_number = lp_build_const_int32(gallivm, input_index);
1352
1353 /* fs.constant returns the param from the middle vertex, so it's not
1354 * really useful for flat shading. It's meant to be used for custom
1355 * interpolation (but the intrinsic can't fetch from the other two
1356 * vertices).
1357 *
1358 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1359 * to do the right thing. The only reason we use fs.constant is that
1360 * fs.interp cannot be used on integers, because they can be equal
1361 * to NaN.
1362 */
1363 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
1364
1365 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1366 ctx->shader->key.ps.prolog.color_two_side) {
1367 LLVMValueRef args[4];
1368 LLVMValueRef is_face_positive;
1369 LLVMValueRef back_attr_number;
1370
1371 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1372 * otherwise it's at offset "num_inputs".
1373 */
1374 unsigned back_attr_offset = num_interp_inputs;
1375 if (semantic_index == 1 && colors_read_mask & 0xf)
1376 back_attr_offset += 1;
1377
1378 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1379
1380 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1381 face, uint->zero, "");
1382
1383 args[2] = prim_mask;
1384 args[3] = interp_param;
1385 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1386 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1387 LLVMValueRef front, back;
1388
1389 args[0] = llvm_chan;
1390 args[1] = attr_number;
1391 front = lp_build_intrinsic(gallivm->builder, intr_name,
1392 ctx->f32, args, args[3] ? 4 : 3,
1393 LLVMReadNoneAttribute);
1394
1395 args[1] = back_attr_number;
1396 back = lp_build_intrinsic(gallivm->builder, intr_name,
1397 ctx->f32, args, args[3] ? 4 : 3,
1398 LLVMReadNoneAttribute);
1399
1400 result[chan] = LLVMBuildSelect(gallivm->builder,
1401 is_face_positive,
1402 front,
1403 back,
1404 "");
1405 }
1406 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1407 LLVMValueRef args[4];
1408
1409 args[0] = uint->zero;
1410 args[1] = attr_number;
1411 args[2] = prim_mask;
1412 args[3] = interp_param;
1413 result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
1414 ctx->f32, args, args[3] ? 4 : 3,
1415 LLVMReadNoneAttribute);
1416 result[1] =
1417 result[2] = lp_build_const_float(gallivm, 0.0f);
1418 result[3] = lp_build_const_float(gallivm, 1.0f);
1419 } else {
1420 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1421 LLVMValueRef args[4];
1422 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1423
1424 args[0] = llvm_chan;
1425 args[1] = attr_number;
1426 args[2] = prim_mask;
1427 args[3] = interp_param;
1428 result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
1429 ctx->f32, args, args[3] ? 4 : 3,
1430 LLVMReadNoneAttribute);
1431 }
1432 }
1433 }
1434
1435 /* LLVMGetParam with bc_optimize resolved. */
1436 static LLVMValueRef get_interp_param(struct si_shader_context *ctx,
1437 int interp_param_idx)
1438 {
1439 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
1440 LLVMValueRef main_fn = ctx->radeon_bld.main_fn;
1441 LLVMValueRef param = NULL;
1442
1443 /* Handle PRIM_MASK[31] (bc_optimize). */
1444 if (ctx->is_monolithic &&
1445 ((ctx->shader->key.ps.prolog.bc_optimize_for_persp &&
1446 interp_param_idx == SI_PARAM_PERSP_CENTROID) ||
1447 (ctx->shader->key.ps.prolog.bc_optimize_for_linear &&
1448 interp_param_idx == SI_PARAM_LINEAR_CENTROID))) {
1449 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
1450 * The hw doesn't compute CENTROID if the whole wave only
1451 * contains fully-covered quads.
1452 */
1453 LLVMValueRef bc_optimize =
1454 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
1455 bc_optimize = LLVMBuildLShr(builder,
1456 bc_optimize,
1457 LLVMConstInt(ctx->i32, 31, 0), "");
1458 bc_optimize = LLVMBuildTrunc(builder, bc_optimize, ctx->i1, "");
1459
1460 if (ctx->shader->key.ps.prolog.bc_optimize_for_persp &&
1461 interp_param_idx == SI_PARAM_PERSP_CENTROID) {
1462 param = LLVMBuildSelect(builder, bc_optimize,
1463 LLVMGetParam(main_fn,
1464 SI_PARAM_PERSP_CENTER),
1465 LLVMGetParam(main_fn,
1466 SI_PARAM_PERSP_CENTROID),
1467 "");
1468 }
1469 if (ctx->shader->key.ps.prolog.bc_optimize_for_linear &&
1470 interp_param_idx == SI_PARAM_LINEAR_CENTROID) {
1471 param = LLVMBuildSelect(builder, bc_optimize,
1472 LLVMGetParam(main_fn,
1473 SI_PARAM_LINEAR_CENTER),
1474 LLVMGetParam(main_fn,
1475 SI_PARAM_LINEAR_CENTROID),
1476 "");
1477 }
1478 }
1479
1480 if (!param)
1481 param = LLVMGetParam(main_fn, interp_param_idx);
1482 return param;
1483 }
1484
1485 static void declare_input_fs(
1486 struct radeon_llvm_context *radeon_bld,
1487 unsigned input_index,
1488 const struct tgsi_full_declaration *decl)
1489 {
1490 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
1491 struct si_shader_context *ctx =
1492 si_shader_context(&radeon_bld->soa.bld_base);
1493 struct si_shader *shader = ctx->shader;
1494 LLVMValueRef main_fn = radeon_bld->main_fn;
1495 LLVMValueRef interp_param = NULL;
1496 int interp_param_idx;
1497
1498 /* Get colors from input VGPRs (set by the prolog). */
1499 if (!ctx->is_monolithic &&
1500 decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1501 unsigned i = decl->Semantic.Index;
1502 unsigned colors_read = shader->selector->info.colors_read;
1503 unsigned mask = colors_read >> (i * 4);
1504 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1505 (i ? util_bitcount(colors_read & 0xf) : 0);
1506
1507 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
1508 mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1509 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
1510 mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1511 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
1512 mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1513 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
1514 mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1515 return;
1516 }
1517
1518 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1519 decl->Interp.Location);
1520 if (interp_param_idx == -1)
1521 return;
1522 else if (interp_param_idx) {
1523 interp_param_idx = select_interp_param(ctx,
1524 interp_param_idx);
1525 interp_param = get_interp_param(ctx, interp_param_idx);
1526 }
1527
1528 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
1529 decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR &&
1530 ctx->shader->key.ps.prolog.flatshade_colors)
1531 interp_param = NULL; /* load the constant color */
1532
1533 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1534 decl->Semantic.Index, shader->selector->info.num_inputs,
1535 shader->selector->info.colors_read, interp_param,
1536 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1537 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1538 &radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)]);
1539 }
1540
1541 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1542 {
1543 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1544 SI_PARAM_ANCILLARY, 8, 4);
1545 }
1546
1547 /**
1548 * Set range metadata on an instruction. This can only be used on load and
1549 * call instructions. If you know an instruction can only produce the values
1550 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1551 * \p lo is the minimum value inclusive.
1552 * \p hi is the maximum value exclusive.
1553 */
1554 static void set_range_metadata(struct si_shader_context *ctx,
1555 LLVMValueRef value, unsigned lo, unsigned hi)
1556 {
1557 LLVMValueRef range_md, md_args[2];
1558 LLVMTypeRef type = LLVMTypeOf(value);
1559 LLVMContextRef context = LLVMGetTypeContext(type);
1560
1561 md_args[0] = LLVMConstInt(type, lo, false);
1562 md_args[1] = LLVMConstInt(type, hi, false);
1563 range_md = LLVMMDNodeInContext(context, md_args, 2);
1564 LLVMSetMetadata(value, ctx->range_md_kind, range_md);
1565 }
1566
1567 static LLVMValueRef get_thread_id(struct si_shader_context *ctx)
1568 {
1569 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1570 LLVMValueRef tid;
1571
1572 if (HAVE_LLVM < 0x0308) {
1573 tid = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid",
1574 ctx->i32, NULL, 0, LLVMReadNoneAttribute);
1575 } else {
1576 LLVMValueRef tid_args[2];
1577 tid_args[0] = lp_build_const_int32(gallivm, 0xffffffff);
1578 tid_args[1] = lp_build_const_int32(gallivm, 0);
1579 tid_args[1] = lp_build_intrinsic(gallivm->builder,
1580 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1581 tid_args, 2, LLVMReadNoneAttribute);
1582
1583 tid = lp_build_intrinsic(gallivm->builder,
1584 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1585 tid_args, 2, LLVMReadNoneAttribute);
1586 }
1587 set_range_metadata(ctx, tid, 0, 64);
1588 return tid;
1589 }
1590
1591 /**
1592 * Load a dword from a constant buffer.
1593 */
1594 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1595 LLVMValueRef offset, LLVMTypeRef return_type)
1596 {
1597 LLVMValueRef args[2] = {resource, offset};
1598
1599 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1600 LLVMReadNoneAttribute);
1601 }
1602
1603 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1604 {
1605 struct si_shader_context *ctx =
1606 si_shader_context(&radeon_bld->soa.bld_base);
1607 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1608 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1609 LLVMBuilderRef builder = gallivm->builder;
1610 LLVMValueRef desc = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1611 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1612 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1613
1614 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1615 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1616 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1617
1618 LLVMValueRef pos[4] = {
1619 buffer_load_const(builder, resource, offset0, ctx->f32),
1620 buffer_load_const(builder, resource, offset1, ctx->f32),
1621 lp_build_const_float(gallivm, 0),
1622 lp_build_const_float(gallivm, 0)
1623 };
1624
1625 return lp_build_gather_values(gallivm, pos, 4);
1626 }
1627
1628 static void declare_system_value(
1629 struct radeon_llvm_context *radeon_bld,
1630 unsigned index,
1631 const struct tgsi_full_declaration *decl)
1632 {
1633 struct si_shader_context *ctx =
1634 si_shader_context(&radeon_bld->soa.bld_base);
1635 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1636 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1637 LLVMValueRef value = 0;
1638
1639 switch (decl->Semantic.Name) {
1640 case TGSI_SEMANTIC_INSTANCEID:
1641 value = LLVMGetParam(radeon_bld->main_fn,
1642 ctx->param_instance_id);
1643 break;
1644
1645 case TGSI_SEMANTIC_VERTEXID:
1646 value = LLVMBuildAdd(gallivm->builder,
1647 LLVMGetParam(radeon_bld->main_fn,
1648 ctx->param_vertex_id),
1649 LLVMGetParam(radeon_bld->main_fn,
1650 SI_PARAM_BASE_VERTEX), "");
1651 break;
1652
1653 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1654 value = LLVMGetParam(radeon_bld->main_fn,
1655 ctx->param_vertex_id);
1656 break;
1657
1658 case TGSI_SEMANTIC_BASEVERTEX:
1659 value = LLVMGetParam(radeon_bld->main_fn,
1660 SI_PARAM_BASE_VERTEX);
1661 break;
1662
1663 case TGSI_SEMANTIC_INVOCATIONID:
1664 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1665 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1666 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1667 value = LLVMGetParam(radeon_bld->main_fn,
1668 SI_PARAM_GS_INSTANCE_ID);
1669 else
1670 assert(!"INVOCATIONID not implemented");
1671 break;
1672
1673 case TGSI_SEMANTIC_POSITION:
1674 {
1675 LLVMValueRef pos[4] = {
1676 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1677 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1678 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1679 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1680 LLVMGetParam(radeon_bld->main_fn,
1681 SI_PARAM_POS_W_FLOAT)),
1682 };
1683 value = lp_build_gather_values(gallivm, pos, 4);
1684 break;
1685 }
1686
1687 case TGSI_SEMANTIC_FACE:
1688 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1689 break;
1690
1691 case TGSI_SEMANTIC_SAMPLEID:
1692 value = get_sample_id(radeon_bld);
1693 break;
1694
1695 case TGSI_SEMANTIC_SAMPLEPOS: {
1696 LLVMValueRef pos[4] = {
1697 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1698 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1699 lp_build_const_float(gallivm, 0),
1700 lp_build_const_float(gallivm, 0)
1701 };
1702 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1703 TGSI_OPCODE_FRC, pos[0]);
1704 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1705 TGSI_OPCODE_FRC, pos[1]);
1706 value = lp_build_gather_values(gallivm, pos, 4);
1707 break;
1708 }
1709
1710 case TGSI_SEMANTIC_SAMPLEMASK:
1711 /* This can only occur with the OpenGL Core profile, which
1712 * doesn't support smoothing.
1713 */
1714 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1715 break;
1716
1717 case TGSI_SEMANTIC_TESSCOORD:
1718 {
1719 LLVMValueRef coord[4] = {
1720 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1721 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1722 bld->zero,
1723 bld->zero
1724 };
1725
1726 /* For triangles, the vector should be (u, v, 1-u-v). */
1727 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1728 PIPE_PRIM_TRIANGLES)
1729 coord[2] = lp_build_sub(bld, bld->one,
1730 lp_build_add(bld, coord[0], coord[1]));
1731
1732 value = lp_build_gather_values(gallivm, coord, 4);
1733 break;
1734 }
1735
1736 case TGSI_SEMANTIC_VERTICESIN:
1737 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1738 break;
1739
1740 case TGSI_SEMANTIC_TESSINNER:
1741 case TGSI_SEMANTIC_TESSOUTER:
1742 {
1743 LLVMValueRef rw_buffers, buffer, base, addr;
1744 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1745
1746 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1747 SI_PARAM_RW_BUFFERS);
1748 buffer = build_indexed_load_const(ctx, rw_buffers,
1749 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1750
1751 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1752 addr = get_tcs_tes_buffer_address(ctx, NULL,
1753 lp_build_const_int32(gallivm, param));
1754
1755 value = buffer_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1756 ~0, buffer, base, addr);
1757
1758 break;
1759 }
1760
1761 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1762 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1763 {
1764 LLVMValueRef buf, slot, val[4];
1765 int i, offset;
1766
1767 slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
1768 buf = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1769 buf = build_indexed_load_const(ctx, buf, slot);
1770 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1771
1772 for (i = 0; i < 4; i++)
1773 val[i] = buffer_load_const(gallivm->builder, buf,
1774 lp_build_const_int32(gallivm, (offset + i) * 4),
1775 ctx->f32);
1776 value = lp_build_gather_values(gallivm, val, 4);
1777 break;
1778 }
1779
1780 case TGSI_SEMANTIC_PRIMID:
1781 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1782 break;
1783
1784 case TGSI_SEMANTIC_GRID_SIZE:
1785 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1786 break;
1787
1788 case TGSI_SEMANTIC_BLOCK_SIZE:
1789 {
1790 LLVMValueRef values[3];
1791 unsigned i;
1792 unsigned *properties = ctx->shader->selector->info.properties;
1793 unsigned sizes[3] = {
1794 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1795 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1796 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1797 };
1798
1799 for (i = 0; i < 3; ++i)
1800 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1801
1802 value = lp_build_gather_values(gallivm, values, 3);
1803 break;
1804 }
1805
1806 case TGSI_SEMANTIC_BLOCK_ID:
1807 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1808 break;
1809
1810 case TGSI_SEMANTIC_THREAD_ID:
1811 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1812 break;
1813
1814 #if HAVE_LLVM >= 0x0309
1815 case TGSI_SEMANTIC_HELPER_INVOCATION:
1816 value = lp_build_intrinsic(gallivm->builder,
1817 "llvm.amdgcn.ps.live",
1818 ctx->i1, NULL, 0,
1819 LLVMReadNoneAttribute);
1820 value = LLVMBuildNot(gallivm->builder, value, "");
1821 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1822 break;
1823 #endif
1824
1825 default:
1826 assert(!"unknown system value");
1827 return;
1828 }
1829
1830 radeon_bld->system_values[index] = value;
1831 }
1832
1833 static void declare_compute_memory(struct radeon_llvm_context *radeon_bld,
1834 const struct tgsi_full_declaration *decl)
1835 {
1836 struct si_shader_context *ctx =
1837 si_shader_context(&radeon_bld->soa.bld_base);
1838 struct si_shader_selector *sel = ctx->shader->selector;
1839 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1840
1841 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1842 LLVMValueRef var;
1843
1844 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1845 assert(decl->Range.First == decl->Range.Last);
1846 assert(!ctx->shared_memory);
1847
1848 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1849 LLVMArrayType(ctx->i8, sel->local_size),
1850 "compute_lds",
1851 LOCAL_ADDR_SPACE);
1852 LLVMSetAlignment(var, 4);
1853
1854 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1855 }
1856
1857 static LLVMValueRef fetch_constant(
1858 struct lp_build_tgsi_context *bld_base,
1859 const struct tgsi_full_src_register *reg,
1860 enum tgsi_opcode_type type,
1861 unsigned swizzle)
1862 {
1863 struct si_shader_context *ctx = si_shader_context(bld_base);
1864 struct lp_build_context *base = &bld_base->base;
1865 const struct tgsi_ind_register *ireg = &reg->Indirect;
1866 unsigned buf, idx;
1867
1868 LLVMValueRef addr, bufp;
1869 LLVMValueRef result;
1870
1871 if (swizzle == LP_CHAN_ALL) {
1872 unsigned chan;
1873 LLVMValueRef values[4];
1874 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1875 values[chan] = fetch_constant(bld_base, reg, type, chan);
1876
1877 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1878 }
1879
1880 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1881 idx = reg->Register.Index * 4 + swizzle;
1882
1883 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1884 if (!tgsi_type_is_64bit(type))
1885 return bitcast(bld_base, type, ctx->constants[buf][idx]);
1886 else {
1887 return radeon_llvm_emit_fetch_64bit(bld_base, type,
1888 ctx->constants[buf][idx],
1889 ctx->constants[buf][idx + 1]);
1890 }
1891 }
1892
1893 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1894 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1895 LLVMValueRef index;
1896 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1897 reg->Dimension.Index,
1898 SI_NUM_CONST_BUFFERS);
1899 bufp = build_indexed_load_const(ctx, ptr, index);
1900 } else
1901 bufp = ctx->const_buffers[buf];
1902
1903 addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1904 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1905 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1906 addr = lp_build_add(&bld_base->uint_bld, addr,
1907 lp_build_const_int32(base->gallivm, idx * 4));
1908
1909 result = buffer_load_const(base->gallivm->builder, bufp,
1910 addr, ctx->f32);
1911
1912 if (!tgsi_type_is_64bit(type))
1913 result = bitcast(bld_base, type, result);
1914 else {
1915 LLVMValueRef addr2, result2;
1916 addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1917 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1918 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1919 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1920 lp_build_const_int32(base->gallivm, idx * 4));
1921
1922 result2 = buffer_load_const(base->gallivm->builder, ctx->const_buffers[buf],
1923 addr2, ctx->f32);
1924
1925 result = radeon_llvm_emit_fetch_64bit(bld_base, type,
1926 result, result2);
1927 }
1928 return result;
1929 }
1930
1931 /* Upper 16 bits must be zero. */
1932 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1933 LLVMValueRef val[2])
1934 {
1935 return LLVMBuildOr(gallivm->builder, val[0],
1936 LLVMBuildShl(gallivm->builder, val[1],
1937 lp_build_const_int32(gallivm, 16),
1938 ""), "");
1939 }
1940
1941 /* Upper 16 bits are ignored and will be dropped. */
1942 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1943 LLVMValueRef val[2])
1944 {
1945 LLVMValueRef v[2] = {
1946 LLVMBuildAnd(gallivm->builder, val[0],
1947 lp_build_const_int32(gallivm, 0xffff), ""),
1948 val[1],
1949 };
1950 return si_llvm_pack_two_int16(gallivm, v);
1951 }
1952
1953 /* Initialize arguments for the shader export intrinsic */
1954 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1955 LLVMValueRef *values,
1956 unsigned target,
1957 LLVMValueRef *args)
1958 {
1959 struct si_shader_context *ctx = si_shader_context(bld_base);
1960 struct lp_build_context *uint =
1961 &ctx->radeon_bld.soa.bld_base.uint_bld;
1962 struct lp_build_context *base = &bld_base->base;
1963 struct gallivm_state *gallivm = base->gallivm;
1964 LLVMBuilderRef builder = base->gallivm->builder;
1965 LLVMValueRef val[4];
1966 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1967 unsigned chan;
1968 bool is_int8;
1969
1970 /* Default is 0xf. Adjusted below depending on the format. */
1971 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1972
1973 /* Specify whether the EXEC mask represents the valid mask */
1974 args[1] = uint->zero;
1975
1976 /* Specify whether this is the last export */
1977 args[2] = uint->zero;
1978
1979 /* Specify the target we are exporting */
1980 args[3] = lp_build_const_int32(base->gallivm, target);
1981
1982 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1983 const union si_shader_key *key = &ctx->shader->key;
1984 unsigned col_formats = key->ps.epilog.spi_shader_col_format;
1985 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1986
1987 assert(cbuf >= 0 && cbuf < 8);
1988 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1989 is_int8 = (key->ps.epilog.color_is_int8 >> cbuf) & 0x1;
1990 }
1991
1992 args[4] = uint->zero; /* COMPR flag */
1993 args[5] = base->undef;
1994 args[6] = base->undef;
1995 args[7] = base->undef;
1996 args[8] = base->undef;
1997
1998 switch (spi_shader_col_format) {
1999 case V_028714_SPI_SHADER_ZERO:
2000 args[0] = uint->zero; /* writemask */
2001 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2002 break;
2003
2004 case V_028714_SPI_SHADER_32_R:
2005 args[0] = uint->one; /* writemask */
2006 args[5] = values[0];
2007 break;
2008
2009 case V_028714_SPI_SHADER_32_GR:
2010 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
2011 args[5] = values[0];
2012 args[6] = values[1];
2013 break;
2014
2015 case V_028714_SPI_SHADER_32_AR:
2016 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
2017 args[5] = values[0];
2018 args[8] = values[3];
2019 break;
2020
2021 case V_028714_SPI_SHADER_FP16_ABGR:
2022 args[4] = uint->one; /* COMPR flag */
2023
2024 for (chan = 0; chan < 2; chan++) {
2025 LLVMValueRef pack_args[2] = {
2026 values[2 * chan],
2027 values[2 * chan + 1]
2028 };
2029 LLVMValueRef packed;
2030
2031 packed = lp_build_intrinsic(base->gallivm->builder,
2032 "llvm.SI.packf16",
2033 ctx->i32, pack_args, 2,
2034 LLVMReadNoneAttribute);
2035 args[chan + 5] =
2036 LLVMBuildBitCast(base->gallivm->builder,
2037 packed, ctx->f32, "");
2038 }
2039 break;
2040
2041 case V_028714_SPI_SHADER_UNORM16_ABGR:
2042 for (chan = 0; chan < 4; chan++) {
2043 val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
2044 val[chan] = LLVMBuildFMul(builder, val[chan],
2045 lp_build_const_float(gallivm, 65535), "");
2046 val[chan] = LLVMBuildFAdd(builder, val[chan],
2047 lp_build_const_float(gallivm, 0.5), "");
2048 val[chan] = LLVMBuildFPToUI(builder, val[chan],
2049 ctx->i32, "");
2050 }
2051
2052 args[4] = uint->one; /* COMPR flag */
2053 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2054 si_llvm_pack_two_int16(gallivm, val));
2055 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2056 si_llvm_pack_two_int16(gallivm, val+2));
2057 break;
2058
2059 case V_028714_SPI_SHADER_SNORM16_ABGR:
2060 for (chan = 0; chan < 4; chan++) {
2061 /* Clamp between [-1, 1]. */
2062 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
2063 values[chan],
2064 lp_build_const_float(gallivm, 1));
2065 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
2066 val[chan],
2067 lp_build_const_float(gallivm, -1));
2068 /* Convert to a signed integer in [-32767, 32767]. */
2069 val[chan] = LLVMBuildFMul(builder, val[chan],
2070 lp_build_const_float(gallivm, 32767), "");
2071 /* If positive, add 0.5, else add -0.5. */
2072 val[chan] = LLVMBuildFAdd(builder, val[chan],
2073 LLVMBuildSelect(builder,
2074 LLVMBuildFCmp(builder, LLVMRealOGE,
2075 val[chan], base->zero, ""),
2076 lp_build_const_float(gallivm, 0.5),
2077 lp_build_const_float(gallivm, -0.5), ""), "");
2078 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2079 }
2080
2081 args[4] = uint->one; /* COMPR flag */
2082 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2083 si_llvm_pack_two_int32_as_int16(gallivm, val));
2084 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2085 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2086 break;
2087
2088 case V_028714_SPI_SHADER_UINT16_ABGR: {
2089 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2090 255 : 65535);
2091 /* Clamp. */
2092 for (chan = 0; chan < 4; chan++) {
2093 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2094 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
2095 val[chan], max);
2096 }
2097
2098 args[4] = uint->one; /* COMPR flag */
2099 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2100 si_llvm_pack_two_int16(gallivm, val));
2101 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2102 si_llvm_pack_two_int16(gallivm, val+2));
2103 break;
2104 }
2105
2106 case V_028714_SPI_SHADER_SINT16_ABGR: {
2107 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2108 127 : 32767);
2109 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
2110 -128 : -32768);
2111 /* Clamp. */
2112 for (chan = 0; chan < 4; chan++) {
2113 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2114 val[chan] = lp_build_emit_llvm_binary(bld_base,
2115 TGSI_OPCODE_IMIN,
2116 val[chan], max);
2117 val[chan] = lp_build_emit_llvm_binary(bld_base,
2118 TGSI_OPCODE_IMAX,
2119 val[chan], min);
2120 }
2121
2122 args[4] = uint->one; /* COMPR flag */
2123 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2124 si_llvm_pack_two_int32_as_int16(gallivm, val));
2125 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2126 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2127 break;
2128 }
2129
2130 case V_028714_SPI_SHADER_32_ABGR:
2131 memcpy(&args[5], values, sizeof(values[0]) * 4);
2132 break;
2133 }
2134 }
2135
2136 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2137 LLVMValueRef alpha)
2138 {
2139 struct si_shader_context *ctx = si_shader_context(bld_base);
2140 struct gallivm_state *gallivm = bld_base->base.gallivm;
2141
2142 if (ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2143 LLVMValueRef alpha_ref = LLVMGetParam(ctx->radeon_bld.main_fn,
2144 SI_PARAM_ALPHA_REF);
2145
2146 LLVMValueRef alpha_pass =
2147 lp_build_cmp(&bld_base->base,
2148 ctx->shader->key.ps.epilog.alpha_func,
2149 alpha, alpha_ref);
2150 LLVMValueRef arg =
2151 lp_build_select(&bld_base->base,
2152 alpha_pass,
2153 lp_build_const_float(gallivm, 1.0f),
2154 lp_build_const_float(gallivm, -1.0f));
2155
2156 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2157 ctx->voidt, &arg, 1, 0);
2158 } else {
2159 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
2160 ctx->voidt, NULL, 0, 0);
2161 }
2162 }
2163
2164 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2165 LLVMValueRef alpha,
2166 unsigned samplemask_param)
2167 {
2168 struct si_shader_context *ctx = si_shader_context(bld_base);
2169 struct gallivm_state *gallivm = bld_base->base.gallivm;
2170 LLVMValueRef coverage;
2171
2172 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2173 coverage = LLVMGetParam(ctx->radeon_bld.main_fn,
2174 samplemask_param);
2175 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
2176
2177 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
2178 ctx->i32,
2179 &coverage, 1, LLVMReadNoneAttribute);
2180
2181 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
2182 ctx->f32, "");
2183
2184 coverage = LLVMBuildFMul(gallivm->builder, coverage,
2185 lp_build_const_float(gallivm,
2186 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2187
2188 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
2189 }
2190
2191 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2192 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
2193 {
2194 struct si_shader_context *ctx = si_shader_context(bld_base);
2195 struct lp_build_context *base = &bld_base->base;
2196 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
2197 unsigned reg_index;
2198 unsigned chan;
2199 unsigned const_chan;
2200 LLVMValueRef base_elt;
2201 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
2202 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
2203 SI_VS_CONST_CLIP_PLANES);
2204 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
2205
2206 for (reg_index = 0; reg_index < 2; reg_index ++) {
2207 LLVMValueRef *args = pos[2 + reg_index];
2208
2209 args[5] =
2210 args[6] =
2211 args[7] =
2212 args[8] = lp_build_const_float(base->gallivm, 0.0f);
2213
2214 /* Compute dot products of position and user clip plane vectors */
2215 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2216 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2217 args[1] = lp_build_const_int32(base->gallivm,
2218 ((reg_index * 4 + chan) * 4 +
2219 const_chan) * 4);
2220 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
2221 args[1], ctx->f32);
2222 args[5 + chan] =
2223 lp_build_add(base, args[5 + chan],
2224 lp_build_mul(base, base_elt,
2225 out_elts[const_chan]));
2226 }
2227 }
2228
2229 args[0] = lp_build_const_int32(base->gallivm, 0xf);
2230 args[1] = uint->zero;
2231 args[2] = uint->zero;
2232 args[3] = lp_build_const_int32(base->gallivm,
2233 V_008DFC_SQ_EXP_POS + 2 + reg_index);
2234 args[4] = uint->zero;
2235 }
2236 }
2237
2238 static void si_dump_streamout(struct pipe_stream_output_info *so)
2239 {
2240 unsigned i;
2241
2242 if (so->num_outputs)
2243 fprintf(stderr, "STREAMOUT\n");
2244
2245 for (i = 0; i < so->num_outputs; i++) {
2246 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2247 so->output[i].start_component;
2248 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2249 i, so->output[i].output_buffer,
2250 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2251 so->output[i].register_index,
2252 mask & 1 ? "x" : "",
2253 mask & 2 ? "y" : "",
2254 mask & 4 ? "z" : "",
2255 mask & 8 ? "w" : "");
2256 }
2257 }
2258
2259 /* On SI, the vertex shader is responsible for writing streamout data
2260 * to buffers. */
2261 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2262 struct si_shader_output_values *outputs,
2263 unsigned noutput)
2264 {
2265 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
2266 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
2267 LLVMBuilderRef builder = gallivm->builder;
2268 int i, j;
2269 struct lp_build_if_state if_ctx;
2270
2271 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2272 LLVMValueRef so_vtx_count =
2273 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2274
2275 LLVMValueRef tid = get_thread_id(ctx);
2276
2277 /* can_emit = tid < so_vtx_count; */
2278 LLVMValueRef can_emit =
2279 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2280
2281 LLVMValueRef stream_id =
2282 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
2283
2284 /* Emit the streamout code conditionally. This actually avoids
2285 * out-of-bounds buffer access. The hw tells us via the SGPR
2286 * (so_vtx_count) which threads are allowed to emit streamout data. */
2287 lp_build_if(&if_ctx, gallivm, can_emit);
2288 {
2289 /* The buffer offset is computed as follows:
2290 * ByteOffset = streamout_offset[buffer_id]*4 +
2291 * (streamout_write_index + thread_id)*stride[buffer_id] +
2292 * attrib_offset
2293 */
2294
2295 LLVMValueRef so_write_index =
2296 LLVMGetParam(ctx->radeon_bld.main_fn,
2297 ctx->param_streamout_write_index);
2298
2299 /* Compute (streamout_write_index + thread_id). */
2300 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2301
2302 /* Compute the write offset for each enabled buffer. */
2303 LLVMValueRef so_write_offset[4] = {};
2304 for (i = 0; i < 4; i++) {
2305 if (!so->stride[i])
2306 continue;
2307
2308 LLVMValueRef so_offset = LLVMGetParam(ctx->radeon_bld.main_fn,
2309 ctx->param_streamout_offset[i]);
2310 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2311
2312 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2313 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2314 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2315 }
2316
2317 /* Write streamout data. */
2318 for (i = 0; i < so->num_outputs; i++) {
2319 unsigned buf_idx = so->output[i].output_buffer;
2320 unsigned reg = so->output[i].register_index;
2321 unsigned start = so->output[i].start_component;
2322 unsigned num_comps = so->output[i].num_components;
2323 unsigned stream = so->output[i].stream;
2324 LLVMValueRef out[4];
2325 struct lp_build_if_state if_ctx_stream;
2326
2327 assert(num_comps && num_comps <= 4);
2328 if (!num_comps || num_comps > 4)
2329 continue;
2330
2331 if (reg >= noutput)
2332 continue;
2333
2334 /* Load the output as int. */
2335 for (j = 0; j < num_comps; j++) {
2336 out[j] = LLVMBuildBitCast(builder,
2337 outputs[reg].values[start+j],
2338 ctx->i32, "");
2339 }
2340
2341 /* Pack the output. */
2342 LLVMValueRef vdata = NULL;
2343
2344 switch (num_comps) {
2345 case 1: /* as i32 */
2346 vdata = out[0];
2347 break;
2348 case 2: /* as v2i32 */
2349 case 3: /* as v4i32 (aligned to 4) */
2350 case 4: /* as v4i32 */
2351 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2352 for (j = 0; j < num_comps; j++) {
2353 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2354 LLVMConstInt(ctx->i32, j, 0), "");
2355 }
2356 break;
2357 }
2358
2359 LLVMValueRef can_emit_stream =
2360 LLVMBuildICmp(builder, LLVMIntEQ,
2361 stream_id,
2362 lp_build_const_int32(gallivm, stream), "");
2363
2364 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
2365 build_tbuffer_store_dwords(ctx, ctx->so_buffers[buf_idx],
2366 vdata, num_comps,
2367 so_write_offset[buf_idx],
2368 LLVMConstInt(ctx->i32, 0, 0),
2369 so->output[i].dst_offset*4);
2370 lp_build_endif(&if_ctx_stream);
2371 }
2372 }
2373 lp_build_endif(&if_ctx);
2374 }
2375
2376
2377 /* Generate export instructions for hardware VS shader stage */
2378 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2379 struct si_shader_output_values *outputs,
2380 unsigned noutput)
2381 {
2382 struct si_shader_context *ctx = si_shader_context(bld_base);
2383 struct si_shader *shader = ctx->shader;
2384 struct lp_build_context *base = &bld_base->base;
2385 struct lp_build_context *uint =
2386 &ctx->radeon_bld.soa.bld_base.uint_bld;
2387 LLVMValueRef args[9];
2388 LLVMValueRef pos_args[4][9] = { { 0 } };
2389 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2390 unsigned semantic_name, semantic_index;
2391 unsigned target;
2392 unsigned param_count = 0;
2393 unsigned pos_idx;
2394 int i;
2395
2396 if (outputs && ctx->shader->selector->so.num_outputs) {
2397 si_llvm_emit_streamout(ctx, outputs, noutput);
2398 }
2399
2400 for (i = 0; i < noutput; i++) {
2401 semantic_name = outputs[i].name;
2402 semantic_index = outputs[i].sid;
2403
2404 handle_semantic:
2405 /* Select the correct target */
2406 switch(semantic_name) {
2407 case TGSI_SEMANTIC_PSIZE:
2408 psize_value = outputs[i].values[0];
2409 continue;
2410 case TGSI_SEMANTIC_EDGEFLAG:
2411 edgeflag_value = outputs[i].values[0];
2412 continue;
2413 case TGSI_SEMANTIC_LAYER:
2414 layer_value = outputs[i].values[0];
2415 semantic_name = TGSI_SEMANTIC_GENERIC;
2416 goto handle_semantic;
2417 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2418 viewport_index_value = outputs[i].values[0];
2419 semantic_name = TGSI_SEMANTIC_GENERIC;
2420 goto handle_semantic;
2421 case TGSI_SEMANTIC_POSITION:
2422 target = V_008DFC_SQ_EXP_POS;
2423 break;
2424 case TGSI_SEMANTIC_COLOR:
2425 case TGSI_SEMANTIC_BCOLOR:
2426 target = V_008DFC_SQ_EXP_PARAM + param_count;
2427 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2428 shader->info.vs_output_param_offset[i] = param_count;
2429 param_count++;
2430 break;
2431 case TGSI_SEMANTIC_CLIPDIST:
2432 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2433 break;
2434 case TGSI_SEMANTIC_CLIPVERTEX:
2435 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2436 continue;
2437 case TGSI_SEMANTIC_PRIMID:
2438 case TGSI_SEMANTIC_FOG:
2439 case TGSI_SEMANTIC_TEXCOORD:
2440 case TGSI_SEMANTIC_GENERIC:
2441 target = V_008DFC_SQ_EXP_PARAM + param_count;
2442 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2443 shader->info.vs_output_param_offset[i] = param_count;
2444 param_count++;
2445 break;
2446 default:
2447 target = 0;
2448 fprintf(stderr,
2449 "Warning: SI unhandled vs output type:%d\n",
2450 semantic_name);
2451 }
2452
2453 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
2454
2455 if (target >= V_008DFC_SQ_EXP_POS &&
2456 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2457 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
2458 args, sizeof(args));
2459 } else {
2460 lp_build_intrinsic(base->gallivm->builder,
2461 "llvm.SI.export", ctx->voidt,
2462 args, 9, 0);
2463 }
2464
2465 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2466 semantic_name = TGSI_SEMANTIC_GENERIC;
2467 goto handle_semantic;
2468 }
2469 }
2470
2471 shader->info.nr_param_exports = param_count;
2472
2473 /* We need to add the position output manually if it's missing. */
2474 if (!pos_args[0][0]) {
2475 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
2476 pos_args[0][1] = uint->zero; /* EXEC mask */
2477 pos_args[0][2] = uint->zero; /* last export? */
2478 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
2479 pos_args[0][4] = uint->zero; /* COMPR flag */
2480 pos_args[0][5] = base->zero; /* X */
2481 pos_args[0][6] = base->zero; /* Y */
2482 pos_args[0][7] = base->zero; /* Z */
2483 pos_args[0][8] = base->one; /* W */
2484 }
2485
2486 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2487 if (shader->selector->info.writes_psize ||
2488 shader->selector->info.writes_edgeflag ||
2489 shader->selector->info.writes_viewport_index ||
2490 shader->selector->info.writes_layer) {
2491 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
2492 shader->selector->info.writes_psize |
2493 (shader->selector->info.writes_edgeflag << 1) |
2494 (shader->selector->info.writes_layer << 2) |
2495 (shader->selector->info.writes_viewport_index << 3));
2496 pos_args[1][1] = uint->zero; /* EXEC mask */
2497 pos_args[1][2] = uint->zero; /* last export? */
2498 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
2499 pos_args[1][4] = uint->zero; /* COMPR flag */
2500 pos_args[1][5] = base->zero; /* X */
2501 pos_args[1][6] = base->zero; /* Y */
2502 pos_args[1][7] = base->zero; /* Z */
2503 pos_args[1][8] = base->zero; /* W */
2504
2505 if (shader->selector->info.writes_psize)
2506 pos_args[1][5] = psize_value;
2507
2508 if (shader->selector->info.writes_edgeflag) {
2509 /* The output is a float, but the hw expects an integer
2510 * with the first bit containing the edge flag. */
2511 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2512 edgeflag_value,
2513 ctx->i32, "");
2514 edgeflag_value = lp_build_min(&bld_base->int_bld,
2515 edgeflag_value,
2516 bld_base->int_bld.one);
2517
2518 /* The LLVM intrinsic expects a float. */
2519 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
2520 edgeflag_value,
2521 ctx->f32, "");
2522 }
2523
2524 if (shader->selector->info.writes_layer)
2525 pos_args[1][7] = layer_value;
2526
2527 if (shader->selector->info.writes_viewport_index)
2528 pos_args[1][8] = viewport_index_value;
2529 }
2530
2531 for (i = 0; i < 4; i++)
2532 if (pos_args[i][0])
2533 shader->info.nr_pos_exports++;
2534
2535 pos_idx = 0;
2536 for (i = 0; i < 4; i++) {
2537 if (!pos_args[i][0])
2538 continue;
2539
2540 /* Specify the target we are exporting */
2541 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2542
2543 if (pos_idx == shader->info.nr_pos_exports)
2544 /* Specify that this is the last export */
2545 pos_args[i][2] = uint->one;
2546
2547 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2548 ctx->voidt, pos_args[i], 9, 0);
2549 }
2550 }
2551
2552 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2553 {
2554 struct si_shader_context *ctx = si_shader_context(bld_base);
2555 struct gallivm_state *gallivm = bld_base->base.gallivm;
2556 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2557 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2558 uint64_t inputs;
2559
2560 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2561
2562 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
2563 buffer = build_indexed_load_const(ctx, rw_buffers,
2564 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
2565
2566 buffer_offset = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
2567
2568 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
2569 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2570 lds_vertex_stride, "");
2571 lds_base = get_tcs_in_current_patch_offset(ctx);
2572 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2573
2574 inputs = ctx->shader->key.tcs.epilog.inputs_to_copy;
2575 while (inputs) {
2576 unsigned i = u_bit_scan64(&inputs);
2577
2578 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2579 lp_build_const_int32(gallivm, 4 * i),
2580 "");
2581
2582 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2583 invocation_id,
2584 lp_build_const_int32(gallivm, i));
2585
2586 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2587 lds_ptr);
2588
2589 build_tbuffer_store_dwords(ctx, buffer, value, 4, buffer_addr,
2590 buffer_offset, 0);
2591 }
2592 }
2593
2594 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2595 LLVMValueRef rel_patch_id,
2596 LLVMValueRef invocation_id,
2597 LLVMValueRef tcs_out_current_patch_data_offset)
2598 {
2599 struct si_shader_context *ctx = si_shader_context(bld_base);
2600 struct gallivm_state *gallivm = bld_base->base.gallivm;
2601 struct si_shader *shader = ctx->shader;
2602 unsigned tess_inner_index, tess_outer_index;
2603 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2604 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2605 unsigned stride, outer_comps, inner_comps, i;
2606 struct lp_build_if_state if_ctx, inner_if_ctx;
2607
2608 si_llvm_emit_barrier(NULL, bld_base, NULL);
2609
2610 /* Do this only for invocation 0, because the tess levels are per-patch,
2611 * not per-vertex.
2612 *
2613 * This can't jump, because invocation 0 executes this. It should
2614 * at least mask out the loads and stores for other invocations.
2615 */
2616 lp_build_if(&if_ctx, gallivm,
2617 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2618 invocation_id, bld_base->uint_bld.zero, ""));
2619
2620 /* Determine the layout of one tess factor element in the buffer. */
2621 switch (shader->key.tcs.epilog.prim_mode) {
2622 case PIPE_PRIM_LINES:
2623 stride = 2; /* 2 dwords, 1 vec2 store */
2624 outer_comps = 2;
2625 inner_comps = 0;
2626 break;
2627 case PIPE_PRIM_TRIANGLES:
2628 stride = 4; /* 4 dwords, 1 vec4 store */
2629 outer_comps = 3;
2630 inner_comps = 1;
2631 break;
2632 case PIPE_PRIM_QUADS:
2633 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2634 outer_comps = 4;
2635 inner_comps = 2;
2636 break;
2637 default:
2638 assert(0);
2639 return;
2640 }
2641
2642 /* Load tess_inner and tess_outer from LDS.
2643 * Any invocation can write them, so we can't get them from a temporary.
2644 */
2645 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2646 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2647
2648 lds_base = tcs_out_current_patch_data_offset;
2649 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2650 lp_build_const_int32(gallivm,
2651 tess_inner_index * 4), "");
2652 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2653 lp_build_const_int32(gallivm,
2654 tess_outer_index * 4), "");
2655
2656 for (i = 0; i < outer_comps; i++)
2657 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2658 for (i = 0; i < inner_comps; i++)
2659 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2660
2661 /* Convert the outputs to vectors for stores. */
2662 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2663 vec1 = NULL;
2664
2665 if (stride > 4)
2666 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2667
2668 /* Get the buffer. */
2669 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2670 SI_PARAM_RW_BUFFERS);
2671 buffer = build_indexed_load_const(ctx, rw_buffers,
2672 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2673
2674 /* Get the offset. */
2675 tf_base = LLVMGetParam(ctx->radeon_bld.main_fn,
2676 SI_PARAM_TESS_FACTOR_OFFSET);
2677 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2678 lp_build_const_int32(gallivm, 4 * stride), "");
2679
2680 lp_build_if(&inner_if_ctx, gallivm,
2681 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2682 rel_patch_id, bld_base->uint_bld.zero, ""));
2683
2684 /* Store the dynamic HS control word. */
2685 build_tbuffer_store_dwords(ctx, buffer,
2686 lp_build_const_int32(gallivm, 0x80000000),
2687 1, lp_build_const_int32(gallivm, 0), tf_base, 0);
2688
2689 lp_build_endif(&inner_if_ctx);
2690
2691 /* Store the tessellation factors. */
2692 build_tbuffer_store_dwords(ctx, buffer, vec0,
2693 MIN2(stride, 4), byteoffset, tf_base, 4);
2694 if (vec1)
2695 build_tbuffer_store_dwords(ctx, buffer, vec1,
2696 stride - 4, byteoffset, tf_base, 20);
2697 lp_build_endif(&if_ctx);
2698 }
2699
2700 /* This only writes the tessellation factor levels. */
2701 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2702 {
2703 struct si_shader_context *ctx = si_shader_context(bld_base);
2704 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2705
2706 rel_patch_id = get_rel_patch_id(ctx);
2707 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2708 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2709
2710 if (!ctx->is_monolithic) {
2711 /* Return epilog parameters from this function. */
2712 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2713 LLVMValueRef ret = ctx->return_value;
2714 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2715 unsigned vgpr;
2716
2717 /* RW_BUFFERS pointer */
2718 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2719 SI_PARAM_RW_BUFFERS);
2720 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2721 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2722 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2723 bld_base->uint_bld.zero, "");
2724 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2725 bld_base->uint_bld.one, "");
2726 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2727 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2728
2729 /* Tess factor buffer soffset is after user SGPRs. */
2730 tf_soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2731 SI_PARAM_TESS_FACTOR_OFFSET);
2732 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2733 SI_TCS_NUM_USER_SGPR + 1, "");
2734
2735 /* VGPRs */
2736 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2737 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2738 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2739
2740 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2741 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2742 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2743 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2744 ctx->return_value = ret;
2745 return;
2746 }
2747
2748 si_copy_tcs_inputs(bld_base);
2749 si_write_tess_factors(bld_base, rel_patch_id, invocation_id, tf_lds_offset);
2750 }
2751
2752 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2753 {
2754 struct si_shader_context *ctx = si_shader_context(bld_base);
2755 struct si_shader *shader = ctx->shader;
2756 struct tgsi_shader_info *info = &shader->selector->info;
2757 struct gallivm_state *gallivm = bld_base->base.gallivm;
2758 unsigned i, chan;
2759 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
2760 ctx->param_rel_auto_id);
2761 LLVMValueRef vertex_dw_stride =
2762 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2763 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2764 vertex_dw_stride, "");
2765
2766 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2767 * its inputs from it. */
2768 for (i = 0; i < info->num_outputs; i++) {
2769 LLVMValueRef *out_ptr = ctx->radeon_bld.soa.outputs[i];
2770 unsigned name = info->output_semantic_name[i];
2771 unsigned index = info->output_semantic_index[i];
2772 int param = si_shader_io_get_unique_index(name, index);
2773 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2774 lp_build_const_int32(gallivm, param * 4), "");
2775
2776 for (chan = 0; chan < 4; chan++) {
2777 lds_store(bld_base, chan, dw_addr,
2778 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2779 }
2780 }
2781 }
2782
2783 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2784 {
2785 struct si_shader_context *ctx = si_shader_context(bld_base);
2786 struct gallivm_state *gallivm = bld_base->base.gallivm;
2787 struct si_shader *es = ctx->shader;
2788 struct tgsi_shader_info *info = &es->selector->info;
2789 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2790 ctx->param_es2gs_offset);
2791 unsigned chan;
2792 int i;
2793
2794 for (i = 0; i < info->num_outputs; i++) {
2795 LLVMValueRef *out_ptr =
2796 ctx->radeon_bld.soa.outputs[i];
2797 int param_index;
2798
2799 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2800 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2801 continue;
2802
2803 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2804 info->output_semantic_index[i]);
2805
2806 for (chan = 0; chan < 4; chan++) {
2807 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2808 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2809
2810 build_tbuffer_store(ctx,
2811 ctx->esgs_ring,
2812 out_val, 1,
2813 LLVMGetUndef(ctx->i32), soffset,
2814 (4 * param_index + chan) * 4,
2815 V_008F0C_BUF_DATA_FORMAT_32,
2816 V_008F0C_BUF_NUM_FORMAT_UINT,
2817 0, 0, 1, 1, 0);
2818 }
2819 }
2820 }
2821
2822 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2823 {
2824 struct si_shader_context *ctx = si_shader_context(bld_base);
2825 struct gallivm_state *gallivm = bld_base->base.gallivm;
2826 LLVMValueRef args[2];
2827
2828 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2829 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2830 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2831 ctx->voidt, args, 2, 0);
2832 }
2833
2834 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2835 {
2836 struct si_shader_context *ctx = si_shader_context(bld_base);
2837 struct gallivm_state *gallivm = bld_base->base.gallivm;
2838 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2839 struct si_shader_output_values *outputs = NULL;
2840 int i,j;
2841
2842 assert(!ctx->is_gs_copy_shader);
2843
2844 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2845
2846 /* Vertex color clamping.
2847 *
2848 * This uses a state constant loaded in a user data SGPR and
2849 * an IF statement is added that clamps all colors if the constant
2850 * is true.
2851 */
2852 if (ctx->type == PIPE_SHADER_VERTEX) {
2853 struct lp_build_if_state if_ctx;
2854 LLVMValueRef cond = NULL;
2855 LLVMValueRef addr, val;
2856
2857 for (i = 0; i < info->num_outputs; i++) {
2858 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2859 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2860 continue;
2861
2862 /* We've found a color. */
2863 if (!cond) {
2864 /* The state is in the first bit of the user SGPR. */
2865 cond = LLVMGetParam(ctx->radeon_bld.main_fn,
2866 SI_PARAM_VS_STATE_BITS);
2867 cond = LLVMBuildTrunc(gallivm->builder, cond,
2868 ctx->i1, "");
2869 lp_build_if(&if_ctx, gallivm, cond);
2870 }
2871
2872 for (j = 0; j < 4; j++) {
2873 addr = ctx->radeon_bld.soa.outputs[i][j];
2874 val = LLVMBuildLoad(gallivm->builder, addr, "");
2875 val = radeon_llvm_saturate(bld_base, val);
2876 LLVMBuildStore(gallivm->builder, val, addr);
2877 }
2878 }
2879
2880 if (cond)
2881 lp_build_endif(&if_ctx);
2882 }
2883
2884 for (i = 0; i < info->num_outputs; i++) {
2885 outputs[i].name = info->output_semantic_name[i];
2886 outputs[i].sid = info->output_semantic_index[i];
2887
2888 for (j = 0; j < 4; j++)
2889 outputs[i].values[j] =
2890 LLVMBuildLoad(gallivm->builder,
2891 ctx->radeon_bld.soa.outputs[i][j],
2892 "");
2893 }
2894
2895 if (ctx->is_monolithic) {
2896 /* Export PrimitiveID when PS needs it. */
2897 if (si_vs_exports_prim_id(ctx->shader)) {
2898 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2899 outputs[i].sid = 0;
2900 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2901 get_primitive_id(bld_base, 0));
2902 outputs[i].values[1] = bld_base->base.undef;
2903 outputs[i].values[2] = bld_base->base.undef;
2904 outputs[i].values[3] = bld_base->base.undef;
2905 i++;
2906 }
2907 } else {
2908 /* Return the primitive ID from the LLVM function. */
2909 ctx->return_value =
2910 LLVMBuildInsertValue(gallivm->builder,
2911 ctx->return_value,
2912 bitcast(bld_base, TGSI_TYPE_FLOAT,
2913 get_primitive_id(bld_base, 0)),
2914 VS_EPILOG_PRIMID_LOC, "");
2915 }
2916
2917 si_llvm_export_vs(bld_base, outputs, i);
2918 FREE(outputs);
2919 }
2920
2921 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2922 LLVMValueRef depth, LLVMValueRef stencil,
2923 LLVMValueRef samplemask)
2924 {
2925 struct si_shader_context *ctx = si_shader_context(bld_base);
2926 struct lp_build_context *base = &bld_base->base;
2927 struct lp_build_context *uint = &bld_base->uint_bld;
2928 LLVMValueRef args[9];
2929 unsigned mask = 0;
2930
2931 assert(depth || stencil || samplemask);
2932
2933 args[1] = uint->one; /* whether the EXEC mask is valid */
2934 args[2] = uint->one; /* DONE bit */
2935
2936 /* Specify the target we are exporting */
2937 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2938
2939 args[4] = uint->zero; /* COMP flag */
2940 args[5] = base->undef; /* R, depth */
2941 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2942 args[7] = base->undef; /* B, sample mask */
2943 args[8] = base->undef; /* A, alpha to mask */
2944
2945 if (depth) {
2946 args[5] = depth;
2947 mask |= 0x1;
2948 }
2949
2950 if (stencil) {
2951 args[6] = stencil;
2952 mask |= 0x2;
2953 }
2954
2955 if (samplemask) {
2956 args[7] = samplemask;
2957 mask |= 0x4;
2958 }
2959
2960 /* SI (except OLAND) has a bug that it only looks
2961 * at the X writemask component. */
2962 if (ctx->screen->b.chip_class == SI &&
2963 ctx->screen->b.family != CHIP_OLAND)
2964 mask |= 0x1;
2965
2966 /* Specify which components to enable */
2967 args[0] = lp_build_const_int32(base->gallivm, mask);
2968
2969 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2970 ctx->voidt, args, 9, 0);
2971 }
2972
2973 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2974 LLVMValueRef *color, unsigned index,
2975 unsigned samplemask_param,
2976 bool is_last)
2977 {
2978 struct si_shader_context *ctx = si_shader_context(bld_base);
2979 struct lp_build_context *base = &bld_base->base;
2980 int i;
2981
2982 /* Clamp color */
2983 if (ctx->shader->key.ps.epilog.clamp_color)
2984 for (i = 0; i < 4; i++)
2985 color[i] = radeon_llvm_saturate(bld_base, color[i]);
2986
2987 /* Alpha to one */
2988 if (ctx->shader->key.ps.epilog.alpha_to_one)
2989 color[3] = base->one;
2990
2991 /* Alpha test */
2992 if (index == 0 &&
2993 ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2994 si_alpha_test(bld_base, color[3]);
2995
2996 /* Line & polygon smoothing */
2997 if (ctx->shader->key.ps.epilog.poly_line_smoothing)
2998 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
2999 samplemask_param);
3000
3001 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3002 if (ctx->shader->key.ps.epilog.last_cbuf > 0) {
3003 LLVMValueRef args[8][9];
3004 int c, last = -1;
3005
3006 /* Get the export arguments, also find out what the last one is. */
3007 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
3008 si_llvm_init_export_args(bld_base, color,
3009 V_008DFC_SQ_EXP_MRT + c, args[c]);
3010 if (args[c][0] != bld_base->uint_bld.zero)
3011 last = c;
3012 }
3013
3014 /* Emit all exports. */
3015 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
3016 if (is_last && last == c) {
3017 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3018 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
3019 } else if (args[c][0] == bld_base->uint_bld.zero)
3020 continue; /* unnecessary NULL export */
3021
3022 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
3023 ctx->voidt, args[c], 9, 0);
3024 }
3025 } else {
3026 LLVMValueRef args[9];
3027
3028 /* Export */
3029 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
3030 args);
3031 if (is_last) {
3032 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3033 args[2] = bld_base->uint_bld.one; /* DONE bit */
3034 } else if (args[0] == bld_base->uint_bld.zero)
3035 return; /* unnecessary NULL export */
3036
3037 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
3038 ctx->voidt, args, 9, 0);
3039 }
3040 }
3041
3042 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3043 {
3044 struct si_shader_context *ctx = si_shader_context(bld_base);
3045 struct lp_build_context *base = &bld_base->base;
3046 struct lp_build_context *uint = &bld_base->uint_bld;
3047 LLVMValueRef args[9];
3048
3049 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
3050 args[1] = uint->one; /* whether the EXEC mask is valid */
3051 args[2] = uint->one; /* DONE bit */
3052 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
3053 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
3054 args[5] = uint->undef; /* R */
3055 args[6] = uint->undef; /* G */
3056 args[7] = uint->undef; /* B */
3057 args[8] = uint->undef; /* A */
3058
3059 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
3060 ctx->voidt, args, 9, 0);
3061 }
3062
3063 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context *bld_base)
3064 {
3065 struct si_shader_context *ctx = si_shader_context(bld_base);
3066 struct si_shader *shader = ctx->shader;
3067 struct lp_build_context *base = &bld_base->base;
3068 struct tgsi_shader_info *info = &shader->selector->info;
3069 LLVMBuilderRef builder = base->gallivm->builder;
3070 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3071 int last_color_export = -1;
3072 int i;
3073
3074 /* Determine the last export. If MRTZ is present, it's always last.
3075 * Otherwise, find the last color export.
3076 */
3077 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask) {
3078 unsigned spi_format = shader->key.ps.epilog.spi_shader_col_format;
3079
3080 /* Don't export NULL and return if alpha-test is enabled. */
3081 if (shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS &&
3082 shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER &&
3083 (spi_format & 0xf) == 0)
3084 spi_format |= V_028714_SPI_SHADER_32_AR;
3085
3086 for (i = 0; i < info->num_outputs; i++) {
3087 unsigned index = info->output_semantic_index[i];
3088
3089 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR)
3090 continue;
3091
3092 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3093 if (shader->key.ps.epilog.last_cbuf > 0) {
3094 /* Just set this if any of the colorbuffers are enabled. */
3095 if (spi_format &
3096 ((1llu << (4 * (shader->key.ps.epilog.last_cbuf + 1))) - 1))
3097 last_color_export = i;
3098 continue;
3099 }
3100
3101 if ((spi_format >> (index * 4)) & 0xf)
3102 last_color_export = i;
3103 }
3104
3105 /* If there are no outputs, export NULL. */
3106 if (last_color_export == -1) {
3107 si_export_null(bld_base);
3108 return;
3109 }
3110 }
3111
3112 for (i = 0; i < info->num_outputs; i++) {
3113 unsigned semantic_name = info->output_semantic_name[i];
3114 unsigned semantic_index = info->output_semantic_index[i];
3115 unsigned j;
3116 LLVMValueRef color[4] = {};
3117
3118 /* Select the correct target */
3119 switch (semantic_name) {
3120 case TGSI_SEMANTIC_POSITION:
3121 depth = LLVMBuildLoad(builder,
3122 ctx->radeon_bld.soa.outputs[i][2], "");
3123 break;
3124 case TGSI_SEMANTIC_STENCIL:
3125 stencil = LLVMBuildLoad(builder,
3126 ctx->radeon_bld.soa.outputs[i][1], "");
3127 break;
3128 case TGSI_SEMANTIC_SAMPLEMASK:
3129 samplemask = LLVMBuildLoad(builder,
3130 ctx->radeon_bld.soa.outputs[i][0], "");
3131 break;
3132 case TGSI_SEMANTIC_COLOR:
3133 for (j = 0; j < 4; j++)
3134 color[j] = LLVMBuildLoad(builder,
3135 ctx->radeon_bld.soa.outputs[i][j], "");
3136
3137 si_export_mrt_color(bld_base, color, semantic_index,
3138 SI_PARAM_SAMPLE_COVERAGE,
3139 last_color_export == i);
3140 break;
3141 default:
3142 fprintf(stderr,
3143 "Warning: SI unhandled fs output type:%d\n",
3144 semantic_name);
3145 }
3146 }
3147
3148 if (depth || stencil || samplemask)
3149 si_export_mrt_z(bld_base, depth, stencil, samplemask);
3150 }
3151
3152 /**
3153 * Return PS outputs in this order:
3154 *
3155 * v[0:3] = color0.xyzw
3156 * v[4:7] = color1.xyzw
3157 * ...
3158 * vN+0 = Depth
3159 * vN+1 = Stencil
3160 * vN+2 = SampleMask
3161 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3162 *
3163 * The alpha-ref SGPR is returned via its original location.
3164 */
3165 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
3166 {
3167 struct si_shader_context *ctx = si_shader_context(bld_base);
3168 struct si_shader *shader = ctx->shader;
3169 struct lp_build_context *base = &bld_base->base;
3170 struct tgsi_shader_info *info = &shader->selector->info;
3171 LLVMBuilderRef builder = base->gallivm->builder;
3172 unsigned i, j, first_vgpr, vgpr;
3173
3174 LLVMValueRef color[8][4] = {};
3175 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3176 LLVMValueRef ret;
3177
3178 /* Read the output values. */
3179 for (i = 0; i < info->num_outputs; i++) {
3180 unsigned semantic_name = info->output_semantic_name[i];
3181 unsigned semantic_index = info->output_semantic_index[i];
3182
3183 switch (semantic_name) {
3184 case TGSI_SEMANTIC_COLOR:
3185 assert(semantic_index < 8);
3186 for (j = 0; j < 4; j++) {
3187 LLVMValueRef ptr = ctx->radeon_bld.soa.outputs[i][j];
3188 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3189 color[semantic_index][j] = result;
3190 }
3191 break;
3192 case TGSI_SEMANTIC_POSITION:
3193 depth = LLVMBuildLoad(builder,
3194 ctx->radeon_bld.soa.outputs[i][2], "");
3195 break;
3196 case TGSI_SEMANTIC_STENCIL:
3197 stencil = LLVMBuildLoad(builder,
3198 ctx->radeon_bld.soa.outputs[i][1], "");
3199 break;
3200 case TGSI_SEMANTIC_SAMPLEMASK:
3201 samplemask = LLVMBuildLoad(builder,
3202 ctx->radeon_bld.soa.outputs[i][0], "");
3203 break;
3204 default:
3205 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3206 semantic_name);
3207 }
3208 }
3209
3210 /* Fill the return structure. */
3211 ret = ctx->return_value;
3212
3213 /* Set SGPRs. */
3214 ret = LLVMBuildInsertValue(builder, ret,
3215 bitcast(bld_base, TGSI_TYPE_SIGNED,
3216 LLVMGetParam(ctx->radeon_bld.main_fn,
3217 SI_PARAM_ALPHA_REF)),
3218 SI_SGPR_ALPHA_REF, "");
3219
3220 /* Set VGPRs */
3221 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3222 for (i = 0; i < ARRAY_SIZE(color); i++) {
3223 if (!color[i][0])
3224 continue;
3225
3226 for (j = 0; j < 4; j++)
3227 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3228 }
3229 if (depth)
3230 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3231 if (stencil)
3232 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3233 if (samplemask)
3234 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3235
3236 /* Add the input sample mask for smoothing at the end. */
3237 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3238 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3239 ret = LLVMBuildInsertValue(builder, ret,
3240 LLVMGetParam(ctx->radeon_bld.main_fn,
3241 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3242
3243 ctx->return_value = ret;
3244 }
3245
3246 /**
3247 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3248 * buffer in number of elements and return it as an i32.
3249 */
3250 static LLVMValueRef get_buffer_size(
3251 struct lp_build_tgsi_context *bld_base,
3252 LLVMValueRef descriptor)
3253 {
3254 struct si_shader_context *ctx = si_shader_context(bld_base);
3255 struct gallivm_state *gallivm = bld_base->base.gallivm;
3256 LLVMBuilderRef builder = gallivm->builder;
3257 LLVMValueRef size =
3258 LLVMBuildExtractElement(builder, descriptor,
3259 lp_build_const_int32(gallivm, 6), "");
3260
3261 if (ctx->screen->b.chip_class >= VI) {
3262 /* On VI, the descriptor contains the size in bytes,
3263 * but TXQ must return the size in elements.
3264 * The stride is always non-zero for resources using TXQ.
3265 */
3266 LLVMValueRef stride =
3267 LLVMBuildExtractElement(builder, descriptor,
3268 lp_build_const_int32(gallivm, 5), "");
3269 stride = LLVMBuildLShr(builder, stride,
3270 lp_build_const_int32(gallivm, 16), "");
3271 stride = LLVMBuildAnd(builder, stride,
3272 lp_build_const_int32(gallivm, 0x3FFF), "");
3273
3274 size = LLVMBuildUDiv(builder, size, stride, "");
3275 }
3276
3277 return size;
3278 }
3279
3280 /**
3281 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
3282 * intrinsic names).
3283 */
3284 static void build_int_type_name(
3285 LLVMTypeRef type,
3286 char *buf, unsigned bufsize)
3287 {
3288 assert(bufsize >= 6);
3289
3290 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
3291 snprintf(buf, bufsize, "v%ui32",
3292 LLVMGetVectorSize(type));
3293 else
3294 strcpy(buf, "i32");
3295 }
3296
3297 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3298 struct lp_build_tgsi_context *bld_base,
3299 struct lp_build_emit_data *emit_data);
3300
3301 /* Prevent optimizations (at least of memory accesses) across the current
3302 * point in the program by emitting empty inline assembly that is marked as
3303 * having side effects.
3304 */
3305 static void emit_optimization_barrier(struct si_shader_context *ctx)
3306 {
3307 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
3308 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3309 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
3310 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3311 }
3312
3313 static void emit_waitcnt(struct si_shader_context *ctx)
3314 {
3315 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3316 LLVMBuilderRef builder = gallivm->builder;
3317 LLVMValueRef args[1] = {
3318 lp_build_const_int32(gallivm, 0xf70)
3319 };
3320 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3321 ctx->voidt, args, 1, 0);
3322 }
3323
3324 static void membar_emit(
3325 const struct lp_build_tgsi_action *action,
3326 struct lp_build_tgsi_context *bld_base,
3327 struct lp_build_emit_data *emit_data)
3328 {
3329 struct si_shader_context *ctx = si_shader_context(bld_base);
3330
3331 emit_waitcnt(ctx);
3332 }
3333
3334 static LLVMValueRef
3335 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3336 const struct tgsi_full_src_register *reg)
3337 {
3338 LLVMValueRef ind_index;
3339 LLVMValueRef rsrc_ptr;
3340
3341 if (!reg->Register.Indirect)
3342 return ctx->shader_buffers[reg->Register.Index];
3343
3344 ind_index = get_bounded_indirect_index(ctx, &reg->Indirect,
3345 reg->Register.Index,
3346 SI_NUM_SHADER_BUFFERS);
3347
3348 rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_SHADER_BUFFERS);
3349 return build_indexed_load_const(ctx, rsrc_ptr, ind_index);
3350 }
3351
3352 static bool tgsi_is_array_sampler(unsigned target)
3353 {
3354 return target == TGSI_TEXTURE_1D_ARRAY ||
3355 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3356 target == TGSI_TEXTURE_2D_ARRAY ||
3357 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3358 target == TGSI_TEXTURE_CUBE_ARRAY ||
3359 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3360 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3361 }
3362
3363 static bool tgsi_is_array_image(unsigned target)
3364 {
3365 return target == TGSI_TEXTURE_3D ||
3366 target == TGSI_TEXTURE_CUBE ||
3367 target == TGSI_TEXTURE_1D_ARRAY ||
3368 target == TGSI_TEXTURE_2D_ARRAY ||
3369 target == TGSI_TEXTURE_CUBE_ARRAY ||
3370 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3371 }
3372
3373 /**
3374 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3375 *
3376 * At least on Tonga, executing image stores on images with DCC enabled and
3377 * non-trivial can eventually lead to lockups. This can occur when an
3378 * application binds an image as read-only but then uses a shader that writes
3379 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3380 * program termination) in this case, but it doesn't cost much to be a bit
3381 * nicer: disabling DCC in the shader still leads to undefined results but
3382 * avoids the lockup.
3383 */
3384 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3385 LLVMValueRef rsrc)
3386 {
3387 if (ctx->screen->b.chip_class <= CIK) {
3388 return rsrc;
3389 } else {
3390 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
3391 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3392 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3393 LLVMValueRef tmp;
3394
3395 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3396 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3397 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3398 }
3399 }
3400
3401 /**
3402 * Load the resource descriptor for \p image.
3403 */
3404 static void
3405 image_fetch_rsrc(
3406 struct lp_build_tgsi_context *bld_base,
3407 const struct tgsi_full_src_register *image,
3408 bool dcc_off,
3409 LLVMValueRef *rsrc)
3410 {
3411 struct si_shader_context *ctx = si_shader_context(bld_base);
3412
3413 assert(image->Register.File == TGSI_FILE_IMAGE);
3414
3415 if (!image->Register.Indirect) {
3416 /* Fast path: use preloaded resources */
3417 *rsrc = ctx->images[image->Register.Index];
3418 } else {
3419 /* Indexing and manual load */
3420 LLVMValueRef ind_index;
3421 LLVMValueRef rsrc_ptr;
3422 LLVMValueRef tmp;
3423
3424 /* From the GL_ARB_shader_image_load_store extension spec:
3425 *
3426 * If a shader performs an image load, store, or atomic
3427 * operation using an image variable declared as an array,
3428 * and if the index used to select an individual element is
3429 * negative or greater than or equal to the size of the
3430 * array, the results of the operation are undefined but may
3431 * not lead to termination.
3432 */
3433 ind_index = get_bounded_indirect_index(ctx, &image->Indirect,
3434 image->Register.Index,
3435 SI_NUM_IMAGES);
3436
3437 rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
3438 tmp = build_indexed_load_const(ctx, rsrc_ptr, ind_index);
3439 if (dcc_off)
3440 tmp = force_dcc_off(ctx, tmp);
3441 *rsrc = tmp;
3442 }
3443 }
3444
3445 static LLVMValueRef image_fetch_coords(
3446 struct lp_build_tgsi_context *bld_base,
3447 const struct tgsi_full_instruction *inst,
3448 unsigned src)
3449 {
3450 struct gallivm_state *gallivm = bld_base->base.gallivm;
3451 LLVMBuilderRef builder = gallivm->builder;
3452 unsigned target = inst->Memory.Texture;
3453 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3454 LLVMValueRef coords[4];
3455 LLVMValueRef tmp;
3456 int chan;
3457
3458 for (chan = 0; chan < num_coords; ++chan) {
3459 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3460 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3461 coords[chan] = tmp;
3462 }
3463
3464 if (num_coords == 1)
3465 return coords[0];
3466
3467 if (num_coords == 3) {
3468 /* LLVM has difficulties lowering 3-element vectors. */
3469 coords[3] = bld_base->uint_bld.undef;
3470 num_coords = 4;
3471 }
3472
3473 return lp_build_gather_values(gallivm, coords, num_coords);
3474 }
3475
3476 /**
3477 * Append the extra mode bits that are used by image load and store.
3478 */
3479 static void image_append_args(
3480 struct si_shader_context *ctx,
3481 struct lp_build_emit_data * emit_data,
3482 unsigned target,
3483 bool atomic)
3484 {
3485 const struct tgsi_full_instruction *inst = emit_data->inst;
3486 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3487 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3488
3489 emit_data->args[emit_data->arg_count++] = i1false; /* r128 */
3490 emit_data->args[emit_data->arg_count++] =
3491 tgsi_is_array_image(target) ? i1true : i1false; /* da */
3492 if (!atomic) {
3493 emit_data->args[emit_data->arg_count++] =
3494 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3495 i1true : i1false; /* glc */
3496 }
3497 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3498 }
3499
3500 /**
3501 * Given a 256 bit resource, extract the top half (which stores the buffer
3502 * resource in the case of textures and images).
3503 */
3504 static LLVMValueRef extract_rsrc_top_half(
3505 struct si_shader_context *ctx,
3506 LLVMValueRef rsrc)
3507 {
3508 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3509 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
3510 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
3511
3512 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, v2i128, "");
3513 rsrc = LLVMBuildExtractElement(gallivm->builder, rsrc, bld_base->uint_bld.one, "");
3514 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, "");
3515
3516 return rsrc;
3517 }
3518
3519 /**
3520 * Append the resource and indexing arguments for buffer intrinsics.
3521 *
3522 * \param rsrc the v4i32 buffer resource
3523 * \param index index into the buffer (stride-based)
3524 * \param offset byte offset into the buffer
3525 */
3526 static void buffer_append_args(
3527 struct si_shader_context *ctx,
3528 struct lp_build_emit_data *emit_data,
3529 LLVMValueRef rsrc,
3530 LLVMValueRef index,
3531 LLVMValueRef offset,
3532 bool atomic)
3533 {
3534 const struct tgsi_full_instruction *inst = emit_data->inst;
3535 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3536 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3537
3538 emit_data->args[emit_data->arg_count++] = rsrc;
3539 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3540 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3541 if (!atomic) {
3542 emit_data->args[emit_data->arg_count++] =
3543 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3544 i1true : i1false; /* glc */
3545 }
3546 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3547 }
3548
3549 static void load_fetch_args(
3550 struct lp_build_tgsi_context * bld_base,
3551 struct lp_build_emit_data * emit_data)
3552 {
3553 struct si_shader_context *ctx = si_shader_context(bld_base);
3554 struct gallivm_state *gallivm = bld_base->base.gallivm;
3555 const struct tgsi_full_instruction * inst = emit_data->inst;
3556 unsigned target = inst->Memory.Texture;
3557 LLVMValueRef rsrc;
3558
3559 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3560
3561 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3562 LLVMBuilderRef builder = gallivm->builder;
3563 LLVMValueRef offset;
3564 LLVMValueRef tmp;
3565
3566 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3567
3568 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3569 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3570
3571 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3572 offset, false);
3573 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3574 LLVMValueRef coords;
3575
3576 image_fetch_rsrc(bld_base, &inst->Src[0], false, &rsrc);
3577 coords = image_fetch_coords(bld_base, inst, 1);
3578
3579 if (target == TGSI_TEXTURE_BUFFER) {
3580 rsrc = extract_rsrc_top_half(ctx, rsrc);
3581 buffer_append_args(ctx, emit_data, rsrc, coords,
3582 bld_base->uint_bld.zero, false);
3583 } else {
3584 emit_data->args[0] = coords;
3585 emit_data->args[1] = rsrc;
3586 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3587 emit_data->arg_count = 3;
3588
3589 image_append_args(ctx, emit_data, target, false);
3590 }
3591 }
3592 }
3593
3594 static void load_emit_buffer(struct si_shader_context *ctx,
3595 struct lp_build_emit_data *emit_data)
3596 {
3597 const struct tgsi_full_instruction *inst = emit_data->inst;
3598 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3599 LLVMBuilderRef builder = gallivm->builder;
3600 uint writemask = inst->Dst[0].Register.WriteMask;
3601 uint count = util_last_bit(writemask);
3602 const char *intrinsic_name;
3603 LLVMTypeRef dst_type;
3604
3605 switch (count) {
3606 case 1:
3607 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3608 dst_type = ctx->f32;
3609 break;
3610 case 2:
3611 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3612 dst_type = LLVMVectorType(ctx->f32, 2);
3613 break;
3614 default: // 3 & 4
3615 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3616 dst_type = ctx->v4f32;
3617 count = 4;
3618 }
3619
3620 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3621 builder, intrinsic_name, dst_type,
3622 emit_data->args, emit_data->arg_count,
3623 LLVMReadOnlyAttribute);
3624 }
3625
3626 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3627 const struct tgsi_full_instruction *inst,
3628 LLVMTypeRef type, int arg)
3629 {
3630 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3631 LLVMBuilderRef builder = gallivm->builder;
3632 LLVMValueRef offset, ptr;
3633 int addr_space;
3634
3635 offset = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, arg, 0);
3636 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3637
3638 ptr = ctx->shared_memory;
3639 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3640 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3641 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3642
3643 return ptr;
3644 }
3645
3646 static void load_emit_memory(
3647 struct si_shader_context *ctx,
3648 struct lp_build_emit_data *emit_data)
3649 {
3650 const struct tgsi_full_instruction *inst = emit_data->inst;
3651 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3652 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3653 LLVMBuilderRef builder = gallivm->builder;
3654 unsigned writemask = inst->Dst[0].Register.WriteMask;
3655 LLVMValueRef channels[4], ptr, derived_ptr, index;
3656 int chan;
3657
3658 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3659
3660 for (chan = 0; chan < 4; ++chan) {
3661 if (!(writemask & (1 << chan))) {
3662 channels[chan] = LLVMGetUndef(base->elem_type);
3663 continue;
3664 }
3665
3666 index = lp_build_const_int32(gallivm, chan);
3667 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3668 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3669 }
3670 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3671 }
3672
3673 static void load_emit(
3674 const struct lp_build_tgsi_action *action,
3675 struct lp_build_tgsi_context *bld_base,
3676 struct lp_build_emit_data *emit_data)
3677 {
3678 struct si_shader_context *ctx = si_shader_context(bld_base);
3679 struct gallivm_state *gallivm = bld_base->base.gallivm;
3680 LLVMBuilderRef builder = gallivm->builder;
3681 const struct tgsi_full_instruction * inst = emit_data->inst;
3682 char intrinsic_name[32];
3683 char coords_type[8];
3684
3685 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3686 load_emit_memory(ctx, emit_data);
3687 return;
3688 }
3689
3690 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3691 emit_waitcnt(ctx);
3692
3693 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3694 load_emit_buffer(ctx, emit_data);
3695 return;
3696 }
3697
3698 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3699 emit_data->output[emit_data->chan] =
3700 lp_build_intrinsic(
3701 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3702 emit_data->args, emit_data->arg_count,
3703 LLVMReadOnlyAttribute);
3704 } else {
3705 build_int_type_name(LLVMTypeOf(emit_data->args[0]),
3706 coords_type, sizeof(coords_type));
3707
3708 snprintf(intrinsic_name, sizeof(intrinsic_name),
3709 "llvm.amdgcn.image.load.%s", coords_type);
3710
3711 emit_data->output[emit_data->chan] =
3712 lp_build_intrinsic(
3713 builder, intrinsic_name, emit_data->dst_type,
3714 emit_data->args, emit_data->arg_count,
3715 LLVMReadOnlyAttribute);
3716 }
3717 }
3718
3719 static void store_fetch_args(
3720 struct lp_build_tgsi_context * bld_base,
3721 struct lp_build_emit_data * emit_data)
3722 {
3723 struct si_shader_context *ctx = si_shader_context(bld_base);
3724 struct gallivm_state *gallivm = bld_base->base.gallivm;
3725 LLVMBuilderRef builder = gallivm->builder;
3726 const struct tgsi_full_instruction * inst = emit_data->inst;
3727 struct tgsi_full_src_register memory;
3728 LLVMValueRef chans[4];
3729 LLVMValueRef data;
3730 LLVMValueRef rsrc;
3731 unsigned chan;
3732
3733 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3734
3735 for (chan = 0; chan < 4; ++chan) {
3736 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3737 }
3738 data = lp_build_gather_values(gallivm, chans, 4);
3739
3740 emit_data->args[emit_data->arg_count++] = data;
3741
3742 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3743
3744 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3745 LLVMValueRef offset;
3746 LLVMValueRef tmp;
3747
3748 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3749
3750 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3751 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3752
3753 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3754 offset, false);
3755 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3756 unsigned target = inst->Memory.Texture;
3757 LLVMValueRef coords;
3758
3759 coords = image_fetch_coords(bld_base, inst, 0);
3760
3761 if (target == TGSI_TEXTURE_BUFFER) {
3762 image_fetch_rsrc(bld_base, &memory, false, &rsrc);
3763
3764 rsrc = extract_rsrc_top_half(ctx, rsrc);
3765 buffer_append_args(ctx, emit_data, rsrc, coords,
3766 bld_base->uint_bld.zero, false);
3767 } else {
3768 emit_data->args[1] = coords;
3769 image_fetch_rsrc(bld_base, &memory, true, &emit_data->args[2]);
3770 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3771 emit_data->arg_count = 4;
3772
3773 image_append_args(ctx, emit_data, target, false);
3774 }
3775 }
3776 }
3777
3778 static void store_emit_buffer(
3779 struct si_shader_context *ctx,
3780 struct lp_build_emit_data *emit_data)
3781 {
3782 const struct tgsi_full_instruction *inst = emit_data->inst;
3783 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3784 LLVMBuilderRef builder = gallivm->builder;
3785 struct lp_build_context *uint_bld = &ctx->radeon_bld.soa.bld_base.uint_bld;
3786 LLVMValueRef base_data = emit_data->args[0];
3787 LLVMValueRef base_offset = emit_data->args[3];
3788 unsigned writemask = inst->Dst[0].Register.WriteMask;
3789
3790 while (writemask) {
3791 int start, count;
3792 const char *intrinsic_name;
3793 LLVMValueRef data;
3794 LLVMValueRef offset;
3795 LLVMValueRef tmp;
3796
3797 u_bit_scan_consecutive_range(&writemask, &start, &count);
3798
3799 /* Due to an LLVM limitation, split 3-element writes
3800 * into a 2-element and a 1-element write. */
3801 if (count == 3) {
3802 writemask |= 1 << (start + 2);
3803 count = 2;
3804 }
3805
3806 if (count == 4) {
3807 data = base_data;
3808 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3809 } else if (count == 2) {
3810 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3811
3812 tmp = LLVMBuildExtractElement(
3813 builder, base_data,
3814 lp_build_const_int32(gallivm, start), "");
3815 data = LLVMBuildInsertElement(
3816 builder, LLVMGetUndef(v2f32), tmp,
3817 uint_bld->zero, "");
3818
3819 tmp = LLVMBuildExtractElement(
3820 builder, base_data,
3821 lp_build_const_int32(gallivm, start + 1), "");
3822 data = LLVMBuildInsertElement(
3823 builder, data, tmp, uint_bld->one, "");
3824
3825 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3826 } else {
3827 assert(count == 1);
3828 data = LLVMBuildExtractElement(
3829 builder, base_data,
3830 lp_build_const_int32(gallivm, start), "");
3831 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3832 }
3833
3834 offset = base_offset;
3835 if (start != 0) {
3836 offset = LLVMBuildAdd(
3837 builder, offset,
3838 lp_build_const_int32(gallivm, start * 4), "");
3839 }
3840
3841 emit_data->args[0] = data;
3842 emit_data->args[3] = offset;
3843
3844 lp_build_intrinsic(
3845 builder, intrinsic_name, emit_data->dst_type,
3846 emit_data->args, emit_data->arg_count, 0);
3847 }
3848 }
3849
3850 static void store_emit_memory(
3851 struct si_shader_context *ctx,
3852 struct lp_build_emit_data *emit_data)
3853 {
3854 const struct tgsi_full_instruction *inst = emit_data->inst;
3855 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3856 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3857 LLVMBuilderRef builder = gallivm->builder;
3858 unsigned writemask = inst->Dst[0].Register.WriteMask;
3859 LLVMValueRef ptr, derived_ptr, data, index;
3860 int chan;
3861
3862 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3863
3864 for (chan = 0; chan < 4; ++chan) {
3865 if (!(writemask & (1 << chan))) {
3866 continue;
3867 }
3868 data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 1, chan);
3869 index = lp_build_const_int32(gallivm, chan);
3870 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3871 LLVMBuildStore(builder, data, derived_ptr);
3872 }
3873 }
3874
3875 static void store_emit(
3876 const struct lp_build_tgsi_action *action,
3877 struct lp_build_tgsi_context *bld_base,
3878 struct lp_build_emit_data *emit_data)
3879 {
3880 struct si_shader_context *ctx = si_shader_context(bld_base);
3881 struct gallivm_state *gallivm = bld_base->base.gallivm;
3882 LLVMBuilderRef builder = gallivm->builder;
3883 const struct tgsi_full_instruction * inst = emit_data->inst;
3884 unsigned target = inst->Memory.Texture;
3885 char intrinsic_name[32];
3886 char coords_type[8];
3887
3888 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3889 store_emit_memory(ctx, emit_data);
3890 return;
3891 }
3892
3893 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3894 emit_waitcnt(ctx);
3895
3896 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3897 store_emit_buffer(ctx, emit_data);
3898 return;
3899 }
3900
3901 if (target == TGSI_TEXTURE_BUFFER) {
3902 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3903 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3904 emit_data->dst_type, emit_data->args,
3905 emit_data->arg_count, 0);
3906 } else {
3907 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
3908 coords_type, sizeof(coords_type));
3909 snprintf(intrinsic_name, sizeof(intrinsic_name),
3910 "llvm.amdgcn.image.store.%s", coords_type);
3911
3912 emit_data->output[emit_data->chan] =
3913 lp_build_intrinsic(
3914 builder, intrinsic_name, emit_data->dst_type,
3915 emit_data->args, emit_data->arg_count, 0);
3916 }
3917 }
3918
3919 static void atomic_fetch_args(
3920 struct lp_build_tgsi_context * bld_base,
3921 struct lp_build_emit_data * emit_data)
3922 {
3923 struct si_shader_context *ctx = si_shader_context(bld_base);
3924 struct gallivm_state *gallivm = bld_base->base.gallivm;
3925 LLVMBuilderRef builder = gallivm->builder;
3926 const struct tgsi_full_instruction * inst = emit_data->inst;
3927 LLVMValueRef data1, data2;
3928 LLVMValueRef rsrc;
3929 LLVMValueRef tmp;
3930
3931 emit_data->dst_type = bld_base->base.elem_type;
3932
3933 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
3934 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3935
3936 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3937 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
3938 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3939 }
3940
3941 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3942 * of arguments, which is reversed relative to TGSI (and GLSL)
3943 */
3944 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3945 emit_data->args[emit_data->arg_count++] = data2;
3946 emit_data->args[emit_data->arg_count++] = data1;
3947
3948 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3949 LLVMValueRef offset;
3950
3951 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3952
3953 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3954 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3955
3956 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3957 offset, true);
3958 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3959 unsigned target = inst->Memory.Texture;
3960 LLVMValueRef coords;
3961
3962 image_fetch_rsrc(bld_base, &inst->Src[0],
3963 target != TGSI_TEXTURE_BUFFER, &rsrc);
3964 coords = image_fetch_coords(bld_base, inst, 1);
3965
3966 if (target == TGSI_TEXTURE_BUFFER) {
3967 rsrc = extract_rsrc_top_half(ctx, rsrc);
3968 buffer_append_args(ctx, emit_data, rsrc, coords,
3969 bld_base->uint_bld.zero, true);
3970 } else {
3971 emit_data->args[emit_data->arg_count++] = coords;
3972 emit_data->args[emit_data->arg_count++] = rsrc;
3973
3974 image_append_args(ctx, emit_data, target, true);
3975 }
3976 }
3977 }
3978
3979 static void atomic_emit_memory(struct si_shader_context *ctx,
3980 struct lp_build_emit_data *emit_data) {
3981 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3982 LLVMBuilderRef builder = gallivm->builder;
3983 const struct tgsi_full_instruction * inst = emit_data->inst;
3984 LLVMValueRef ptr, result, arg;
3985
3986 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
3987
3988 arg = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 2, 0);
3989 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
3990
3991 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3992 LLVMValueRef new_data;
3993 new_data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base,
3994 inst, 3, 0);
3995
3996 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
3997
3998 #if HAVE_LLVM >= 0x309
3999 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
4000 LLVMAtomicOrderingSequentiallyConsistent,
4001 LLVMAtomicOrderingSequentiallyConsistent,
4002 false);
4003 #endif
4004
4005 result = LLVMBuildExtractValue(builder, result, 0, "");
4006 } else {
4007 LLVMAtomicRMWBinOp op;
4008
4009 switch(inst->Instruction.Opcode) {
4010 case TGSI_OPCODE_ATOMUADD:
4011 op = LLVMAtomicRMWBinOpAdd;
4012 break;
4013 case TGSI_OPCODE_ATOMXCHG:
4014 op = LLVMAtomicRMWBinOpXchg;
4015 break;
4016 case TGSI_OPCODE_ATOMAND:
4017 op = LLVMAtomicRMWBinOpAnd;
4018 break;
4019 case TGSI_OPCODE_ATOMOR:
4020 op = LLVMAtomicRMWBinOpOr;
4021 break;
4022 case TGSI_OPCODE_ATOMXOR:
4023 op = LLVMAtomicRMWBinOpXor;
4024 break;
4025 case TGSI_OPCODE_ATOMUMIN:
4026 op = LLVMAtomicRMWBinOpUMin;
4027 break;
4028 case TGSI_OPCODE_ATOMUMAX:
4029 op = LLVMAtomicRMWBinOpUMax;
4030 break;
4031 case TGSI_OPCODE_ATOMIMIN:
4032 op = LLVMAtomicRMWBinOpMin;
4033 break;
4034 case TGSI_OPCODE_ATOMIMAX:
4035 op = LLVMAtomicRMWBinOpMax;
4036 break;
4037 default:
4038 unreachable("unknown atomic opcode");
4039 }
4040
4041 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
4042 LLVMAtomicOrderingSequentiallyConsistent,
4043 false);
4044 }
4045 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
4046 }
4047
4048 static void atomic_emit(
4049 const struct lp_build_tgsi_action *action,
4050 struct lp_build_tgsi_context *bld_base,
4051 struct lp_build_emit_data *emit_data)
4052 {
4053 struct si_shader_context *ctx = si_shader_context(bld_base);
4054 struct gallivm_state *gallivm = bld_base->base.gallivm;
4055 LLVMBuilderRef builder = gallivm->builder;
4056 const struct tgsi_full_instruction * inst = emit_data->inst;
4057 char intrinsic_name[40];
4058 LLVMValueRef tmp;
4059
4060 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
4061 atomic_emit_memory(ctx, emit_data);
4062 return;
4063 }
4064
4065 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
4066 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4067 snprintf(intrinsic_name, sizeof(intrinsic_name),
4068 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
4069 } else {
4070 char coords_type[8];
4071
4072 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
4073 coords_type, sizeof(coords_type));
4074 snprintf(intrinsic_name, sizeof(intrinsic_name),
4075 "llvm.amdgcn.image.atomic.%s.%s",
4076 action->intr_name, coords_type);
4077 }
4078
4079 tmp = lp_build_intrinsic(
4080 builder, intrinsic_name, bld_base->uint_bld.elem_type,
4081 emit_data->args, emit_data->arg_count, 0);
4082 emit_data->output[emit_data->chan] =
4083 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
4084 }
4085
4086 static void resq_fetch_args(
4087 struct lp_build_tgsi_context * bld_base,
4088 struct lp_build_emit_data * emit_data)
4089 {
4090 struct si_shader_context *ctx = si_shader_context(bld_base);
4091 struct gallivm_state *gallivm = bld_base->base.gallivm;
4092 const struct tgsi_full_instruction *inst = emit_data->inst;
4093 const struct tgsi_full_src_register *reg = &inst->Src[0];
4094
4095 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
4096
4097 if (reg->Register.File == TGSI_FILE_BUFFER) {
4098 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4099 emit_data->arg_count = 1;
4100 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4101 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[0]);
4102 emit_data->arg_count = 1;
4103 } else {
4104 emit_data->args[0] = bld_base->uint_bld.zero; /* mip level */
4105 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[1]);
4106 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
4107 emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
4108 emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
4109 emit_data->args[5] = tgsi_is_array_image(inst->Memory.Texture) ?
4110 bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da */
4111 emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
4112 emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
4113 emit_data->args[8] = bld_base->uint_bld.zero; /* tfe */
4114 emit_data->args[9] = bld_base->uint_bld.zero; /* lwe */
4115 emit_data->arg_count = 10;
4116 }
4117 }
4118
4119 static void resq_emit(
4120 const struct lp_build_tgsi_action *action,
4121 struct lp_build_tgsi_context *bld_base,
4122 struct lp_build_emit_data *emit_data)
4123 {
4124 struct gallivm_state *gallivm = bld_base->base.gallivm;
4125 LLVMBuilderRef builder = gallivm->builder;
4126 const struct tgsi_full_instruction *inst = emit_data->inst;
4127 LLVMValueRef out;
4128
4129 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4130 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4131 lp_build_const_int32(gallivm, 2), "");
4132 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4133 out = get_buffer_size(bld_base, emit_data->args[0]);
4134 } else {
4135 out = lp_build_intrinsic(
4136 builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
4137 emit_data->args, emit_data->arg_count,
4138 LLVMReadNoneAttribute);
4139
4140 /* Divide the number of layers by 6 to get the number of cubes. */
4141 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
4142 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
4143 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
4144
4145 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4146 z = LLVMBuildBitCast(builder, z, bld_base->uint_bld.elem_type, "");
4147 z = LLVMBuildSDiv(builder, z, imm6, "");
4148 z = LLVMBuildBitCast(builder, z, bld_base->base.elem_type, "");
4149 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4150 }
4151 }
4152
4153 emit_data->output[emit_data->chan] = out;
4154 }
4155
4156 static void set_tex_fetch_args(struct si_shader_context *ctx,
4157 struct lp_build_emit_data *emit_data,
4158 unsigned opcode, unsigned target,
4159 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4160 LLVMValueRef *param, unsigned count,
4161 unsigned dmask)
4162 {
4163 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4164 unsigned num_args;
4165 unsigned is_rect = target == TGSI_TEXTURE_RECT;
4166
4167 /* Pad to power of two vector */
4168 while (count < util_next_power_of_two(count))
4169 param[count++] = LLVMGetUndef(ctx->i32);
4170
4171 /* Texture coordinates. */
4172 if (count > 1)
4173 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
4174 else
4175 emit_data->args[0] = param[0];
4176
4177 /* Resource. */
4178 emit_data->args[1] = res_ptr;
4179 num_args = 2;
4180
4181 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
4182 emit_data->dst_type = ctx->v4i32;
4183 else {
4184 emit_data->dst_type = ctx->v4f32;
4185
4186 emit_data->args[num_args++] = samp_ptr;
4187 }
4188
4189 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
4190 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
4191 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
4192 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
4193 tgsi_is_array_sampler(target)); /* da */
4194 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
4195 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
4196 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
4197 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
4198
4199 emit_data->arg_count = num_args;
4200 }
4201
4202 static const struct lp_build_tgsi_action tex_action;
4203
4204 enum desc_type {
4205 DESC_IMAGE,
4206 DESC_FMASK,
4207 DESC_SAMPLER
4208 };
4209
4210 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
4211 {
4212 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
4213 CONST_ADDR_SPACE);
4214 }
4215
4216 /**
4217 * Load an image view, fmask view. or sampler state descriptor.
4218 */
4219 static LLVMValueRef get_sampler_desc_custom(struct si_shader_context *ctx,
4220 LLVMValueRef list, LLVMValueRef index,
4221 enum desc_type type)
4222 {
4223 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4224 LLVMBuilderRef builder = gallivm->builder;
4225
4226 switch (type) {
4227 case DESC_IMAGE:
4228 /* The image is at [0:7]. */
4229 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4230 break;
4231 case DESC_FMASK:
4232 /* The FMASK is at [8:15]. */
4233 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4234 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4235 break;
4236 case DESC_SAMPLER:
4237 /* The sampler state is at [12:15]. */
4238 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4239 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4240 list = LLVMBuildPointerCast(builder, list,
4241 const_array(ctx->v4i32, 0), "");
4242 break;
4243 }
4244
4245 return build_indexed_load_const(ctx, list, index);
4246 }
4247
4248 static LLVMValueRef get_sampler_desc(struct si_shader_context *ctx,
4249 LLVMValueRef index, enum desc_type type)
4250 {
4251 LLVMValueRef list = LLVMGetParam(ctx->radeon_bld.main_fn,
4252 SI_PARAM_SAMPLERS);
4253
4254 return get_sampler_desc_custom(ctx, list, index, type);
4255 }
4256
4257 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4258 *
4259 * SI-CI:
4260 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4261 * filtering manually. The driver sets img7 to a mask clearing
4262 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4263 * s_and_b32 samp0, samp0, img7
4264 *
4265 * VI:
4266 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4267 */
4268 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4269 LLVMValueRef res, LLVMValueRef samp)
4270 {
4271 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
4272 LLVMValueRef img7, samp0;
4273
4274 if (ctx->screen->b.chip_class >= VI)
4275 return samp;
4276
4277 img7 = LLVMBuildExtractElement(builder, res,
4278 LLVMConstInt(ctx->i32, 7, 0), "");
4279 samp0 = LLVMBuildExtractElement(builder, samp,
4280 LLVMConstInt(ctx->i32, 0, 0), "");
4281 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4282 return LLVMBuildInsertElement(builder, samp, samp0,
4283 LLVMConstInt(ctx->i32, 0, 0), "");
4284 }
4285
4286 static void tex_fetch_ptrs(
4287 struct lp_build_tgsi_context *bld_base,
4288 struct lp_build_emit_data *emit_data,
4289 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4290 {
4291 struct si_shader_context *ctx = si_shader_context(bld_base);
4292 const struct tgsi_full_instruction *inst = emit_data->inst;
4293 unsigned target = inst->Texture.Texture;
4294 unsigned sampler_src;
4295 unsigned sampler_index;
4296
4297 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4298 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
4299
4300 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
4301 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
4302 LLVMValueRef ind_index;
4303
4304 ind_index = get_bounded_indirect_index(ctx,
4305 &reg->Indirect,
4306 reg->Register.Index,
4307 SI_NUM_SAMPLERS);
4308
4309 *res_ptr = get_sampler_desc(ctx, ind_index, DESC_IMAGE);
4310
4311 if (target == TGSI_TEXTURE_2D_MSAA ||
4312 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4313 if (samp_ptr)
4314 *samp_ptr = NULL;
4315 if (fmask_ptr)
4316 *fmask_ptr = get_sampler_desc(ctx, ind_index, DESC_FMASK);
4317 } else {
4318 if (samp_ptr) {
4319 *samp_ptr = get_sampler_desc(ctx, ind_index, DESC_SAMPLER);
4320 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4321 }
4322 if (fmask_ptr)
4323 *fmask_ptr = NULL;
4324 }
4325 } else {
4326 *res_ptr = ctx->sampler_views[sampler_index];
4327 if (samp_ptr)
4328 *samp_ptr = ctx->sampler_states[sampler_index];
4329 if (fmask_ptr)
4330 *fmask_ptr = ctx->fmasks[sampler_index];
4331 }
4332 }
4333
4334 static void txq_fetch_args(
4335 struct lp_build_tgsi_context *bld_base,
4336 struct lp_build_emit_data *emit_data)
4337 {
4338 struct si_shader_context *ctx = si_shader_context(bld_base);
4339 struct gallivm_state *gallivm = bld_base->base.gallivm;
4340 LLVMBuilderRef builder = gallivm->builder;
4341 const struct tgsi_full_instruction *inst = emit_data->inst;
4342 unsigned target = inst->Texture.Texture;
4343 LLVMValueRef res_ptr;
4344 LLVMValueRef address;
4345
4346 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4347
4348 if (target == TGSI_TEXTURE_BUFFER) {
4349 /* Read the size from the buffer descriptor directly. */
4350 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4351 emit_data->args[0] = get_buffer_size(bld_base, res);
4352 return;
4353 }
4354
4355 /* Textures - set the mip level. */
4356 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4357
4358 set_tex_fetch_args(ctx, emit_data, TGSI_OPCODE_TXQ, target, res_ptr,
4359 NULL, &address, 1, 0xf);
4360 }
4361
4362 static void txq_emit(const struct lp_build_tgsi_action *action,
4363 struct lp_build_tgsi_context *bld_base,
4364 struct lp_build_emit_data *emit_data)
4365 {
4366 struct lp_build_context *base = &bld_base->base;
4367 unsigned target = emit_data->inst->Texture.Texture;
4368
4369 if (target == TGSI_TEXTURE_BUFFER) {
4370 /* Just return the buffer size. */
4371 emit_data->output[emit_data->chan] = emit_data->args[0];
4372 return;
4373 }
4374
4375 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4376 base->gallivm->builder, "llvm.SI.getresinfo.i32",
4377 emit_data->dst_type, emit_data->args, emit_data->arg_count,
4378 LLVMReadNoneAttribute);
4379
4380 /* Divide the number of layers by 6 to get the number of cubes. */
4381 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4382 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4383 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4384 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4385 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4386
4387 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4388 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4389 z = LLVMBuildSDiv(builder, z, six, "");
4390
4391 emit_data->output[emit_data->chan] =
4392 LLVMBuildInsertElement(builder, v4, z, two, "");
4393 }
4394 }
4395
4396 static void tex_fetch_args(
4397 struct lp_build_tgsi_context *bld_base,
4398 struct lp_build_emit_data *emit_data)
4399 {
4400 struct si_shader_context *ctx = si_shader_context(bld_base);
4401 struct gallivm_state *gallivm = bld_base->base.gallivm;
4402 const struct tgsi_full_instruction *inst = emit_data->inst;
4403 unsigned opcode = inst->Instruction.Opcode;
4404 unsigned target = inst->Texture.Texture;
4405 LLVMValueRef coords[5], derivs[6];
4406 LLVMValueRef address[16];
4407 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4408 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4409 unsigned count = 0;
4410 unsigned chan;
4411 unsigned num_deriv_channels = 0;
4412 bool has_offset = inst->Texture.NumOffsets > 0;
4413 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4414 unsigned dmask = 0xf;
4415
4416 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4417
4418 if (target == TGSI_TEXTURE_BUFFER) {
4419 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
4420
4421 /* Bitcast and truncate v8i32 to v16i8. */
4422 LLVMValueRef res = res_ptr;
4423 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
4424 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
4425 res = LLVMBuildBitCast(gallivm->builder, res, ctx->v16i8, "");
4426
4427 emit_data->dst_type = ctx->v4f32;
4428 emit_data->args[0] = res;
4429 emit_data->args[1] = bld_base->uint_bld.zero;
4430 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4431 emit_data->arg_count = 3;
4432 return;
4433 }
4434
4435 /* Fetch and project texture coordinates */
4436 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4437 for (chan = 0; chan < 3; chan++ ) {
4438 coords[chan] = lp_build_emit_fetch(bld_base,
4439 emit_data->inst, 0,
4440 chan);
4441 if (opcode == TGSI_OPCODE_TXP)
4442 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4443 TGSI_OPCODE_DIV,
4444 coords[chan],
4445 coords[3]);
4446 }
4447
4448 if (opcode == TGSI_OPCODE_TXP)
4449 coords[3] = bld_base->base.one;
4450
4451 /* Pack offsets. */
4452 if (has_offset && opcode != TGSI_OPCODE_TXF) {
4453 /* The offsets are six-bit signed integers packed like this:
4454 * X=[5:0], Y=[13:8], and Z=[21:16].
4455 */
4456 LLVMValueRef offset[3], pack;
4457
4458 assert(inst->Texture.NumOffsets == 1);
4459
4460 for (chan = 0; chan < 3; chan++) {
4461 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4462 emit_data->inst, 0, chan);
4463 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4464 lp_build_const_int32(gallivm, 0x3f), "");
4465 if (chan)
4466 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4467 lp_build_const_int32(gallivm, chan*8), "");
4468 }
4469
4470 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4471 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4472 address[count++] = pack;
4473 }
4474
4475 /* Pack LOD bias value */
4476 if (opcode == TGSI_OPCODE_TXB)
4477 address[count++] = coords[3];
4478 if (opcode == TGSI_OPCODE_TXB2)
4479 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4480
4481 /* Pack depth comparison value */
4482 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4483 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4484 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4485 } else {
4486 assert(ref_pos >= 0);
4487 address[count++] = coords[ref_pos];
4488 }
4489 }
4490
4491 /* Pack user derivatives */
4492 if (opcode == TGSI_OPCODE_TXD) {
4493 int param, num_src_deriv_channels;
4494
4495 switch (target) {
4496 case TGSI_TEXTURE_3D:
4497 num_src_deriv_channels = 3;
4498 num_deriv_channels = 3;
4499 break;
4500 case TGSI_TEXTURE_2D:
4501 case TGSI_TEXTURE_SHADOW2D:
4502 case TGSI_TEXTURE_RECT:
4503 case TGSI_TEXTURE_SHADOWRECT:
4504 case TGSI_TEXTURE_2D_ARRAY:
4505 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4506 num_src_deriv_channels = 2;
4507 num_deriv_channels = 2;
4508 break;
4509 case TGSI_TEXTURE_CUBE:
4510 case TGSI_TEXTURE_SHADOWCUBE:
4511 case TGSI_TEXTURE_CUBE_ARRAY:
4512 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4513 /* Cube derivatives will be converted to 2D. */
4514 num_src_deriv_channels = 3;
4515 num_deriv_channels = 2;
4516 break;
4517 case TGSI_TEXTURE_1D:
4518 case TGSI_TEXTURE_SHADOW1D:
4519 case TGSI_TEXTURE_1D_ARRAY:
4520 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4521 num_src_deriv_channels = 1;
4522 num_deriv_channels = 1;
4523 break;
4524 default:
4525 unreachable("invalid target");
4526 }
4527
4528 for (param = 0; param < 2; param++)
4529 for (chan = 0; chan < num_src_deriv_channels; chan++)
4530 derivs[param * num_src_deriv_channels + chan] =
4531 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4532 }
4533
4534 if (target == TGSI_TEXTURE_CUBE ||
4535 target == TGSI_TEXTURE_CUBE_ARRAY ||
4536 target == TGSI_TEXTURE_SHADOWCUBE ||
4537 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4538 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
4539
4540 if (opcode == TGSI_OPCODE_TXD)
4541 for (int i = 0; i < num_deriv_channels * 2; i++)
4542 address[count++] = derivs[i];
4543
4544 /* Pack texture coordinates */
4545 address[count++] = coords[0];
4546 if (num_coords > 1)
4547 address[count++] = coords[1];
4548 if (num_coords > 2)
4549 address[count++] = coords[2];
4550
4551 /* Pack LOD or sample index */
4552 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4553 address[count++] = coords[3];
4554 else if (opcode == TGSI_OPCODE_TXL2)
4555 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4556
4557 if (count > 16) {
4558 assert(!"Cannot handle more than 16 texture address parameters");
4559 count = 16;
4560 }
4561
4562 for (chan = 0; chan < count; chan++ ) {
4563 address[chan] = LLVMBuildBitCast(gallivm->builder,
4564 address[chan], ctx->i32, "");
4565 }
4566
4567 /* Adjust the sample index according to FMASK.
4568 *
4569 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4570 * which is the identity mapping. Each nibble says which physical sample
4571 * should be fetched to get that sample.
4572 *
4573 * For example, 0x11111100 means there are only 2 samples stored and
4574 * the second sample covers 3/4 of the pixel. When reading samples 0
4575 * and 1, return physical sample 0 (determined by the first two 0s
4576 * in FMASK), otherwise return physical sample 1.
4577 *
4578 * The sample index should be adjusted as follows:
4579 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4580 */
4581 if (target == TGSI_TEXTURE_2D_MSAA ||
4582 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4583 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4584 struct lp_build_emit_data txf_emit_data = *emit_data;
4585 LLVMValueRef txf_address[4];
4586 unsigned txf_count = count;
4587 struct tgsi_full_instruction inst = {};
4588
4589 memcpy(txf_address, address, sizeof(txf_address));
4590
4591 if (target == TGSI_TEXTURE_2D_MSAA) {
4592 txf_address[2] = bld_base->uint_bld.zero;
4593 }
4594 txf_address[3] = bld_base->uint_bld.zero;
4595
4596 /* Read FMASK using TXF. */
4597 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4598 inst.Texture.Texture = target;
4599 txf_emit_data.inst = &inst;
4600 txf_emit_data.chan = 0;
4601 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
4602 target, fmask_ptr, NULL,
4603 txf_address, txf_count, 0xf);
4604 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4605
4606 /* Initialize some constants. */
4607 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4608 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4609
4610 /* Apply the formula. */
4611 LLVMValueRef fmask =
4612 LLVMBuildExtractElement(gallivm->builder,
4613 txf_emit_data.output[0],
4614 uint_bld->zero, "");
4615
4616 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4617
4618 LLVMValueRef sample_index4 =
4619 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4620
4621 LLVMValueRef shifted_fmask =
4622 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4623
4624 LLVMValueRef final_sample =
4625 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4626
4627 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4628 * resource descriptor is 0 (invalid),
4629 */
4630 LLVMValueRef fmask_desc =
4631 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4632 ctx->v8i32, "");
4633
4634 LLVMValueRef fmask_word1 =
4635 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4636 uint_bld->one, "");
4637
4638 LLVMValueRef word1_is_nonzero =
4639 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4640 fmask_word1, uint_bld->zero, "");
4641
4642 /* Replace the MSAA sample index. */
4643 address[sample_chan] =
4644 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4645 final_sample, address[sample_chan], "");
4646 }
4647
4648 if (opcode == TGSI_OPCODE_TXF) {
4649 /* add tex offsets */
4650 if (inst->Texture.NumOffsets) {
4651 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4652 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
4653 const struct tgsi_texture_offset *off = inst->TexOffsets;
4654
4655 assert(inst->Texture.NumOffsets == 1);
4656
4657 switch (target) {
4658 case TGSI_TEXTURE_3D:
4659 address[2] = lp_build_add(uint_bld, address[2],
4660 bld->immediates[off->Index][off->SwizzleZ]);
4661 /* fall through */
4662 case TGSI_TEXTURE_2D:
4663 case TGSI_TEXTURE_SHADOW2D:
4664 case TGSI_TEXTURE_RECT:
4665 case TGSI_TEXTURE_SHADOWRECT:
4666 case TGSI_TEXTURE_2D_ARRAY:
4667 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4668 address[1] =
4669 lp_build_add(uint_bld, address[1],
4670 bld->immediates[off->Index][off->SwizzleY]);
4671 /* fall through */
4672 case TGSI_TEXTURE_1D:
4673 case TGSI_TEXTURE_SHADOW1D:
4674 case TGSI_TEXTURE_1D_ARRAY:
4675 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4676 address[0] =
4677 lp_build_add(uint_bld, address[0],
4678 bld->immediates[off->Index][off->SwizzleX]);
4679 break;
4680 /* texture offsets do not apply to other texture targets */
4681 }
4682 }
4683 }
4684
4685 if (opcode == TGSI_OPCODE_TG4) {
4686 unsigned gather_comp = 0;
4687
4688 /* DMASK was repurposed for GATHER4. 4 components are always
4689 * returned and DMASK works like a swizzle - it selects
4690 * the component to fetch. The only valid DMASK values are
4691 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4692 * (red,red,red,red) etc.) The ISA document doesn't mention
4693 * this.
4694 */
4695
4696 /* Get the component index from src1.x for Gather4. */
4697 if (!tgsi_is_shadow_target(target)) {
4698 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4699 LLVMValueRef comp_imm;
4700 struct tgsi_src_register src1 = inst->Src[1].Register;
4701
4702 assert(src1.File == TGSI_FILE_IMMEDIATE);
4703
4704 comp_imm = imms[src1.Index][src1.SwizzleX];
4705 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4706 gather_comp = CLAMP(gather_comp, 0, 3);
4707 }
4708
4709 dmask = 1 << gather_comp;
4710 }
4711
4712 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
4713 samp_ptr, address, count, dmask);
4714 }
4715
4716 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4717 struct lp_build_tgsi_context *bld_base,
4718 struct lp_build_emit_data *emit_data)
4719 {
4720 struct si_shader_context *ctx = si_shader_context(bld_base);
4721 struct lp_build_context *base = &bld_base->base;
4722 unsigned opcode = emit_data->inst->Instruction.Opcode;
4723 unsigned target = emit_data->inst->Texture.Texture;
4724 char intr_name[127];
4725 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
4726 bool is_shadow = tgsi_is_shadow_target(target);
4727 char type[64];
4728 const char *name = "llvm.SI.image.sample";
4729 const char *infix = "";
4730
4731 if (target == TGSI_TEXTURE_BUFFER) {
4732 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4733 base->gallivm->builder,
4734 "llvm.SI.vs.load.input", emit_data->dst_type,
4735 emit_data->args, emit_data->arg_count,
4736 LLVMReadNoneAttribute);
4737 return;
4738 }
4739
4740 switch (opcode) {
4741 case TGSI_OPCODE_TXF:
4742 name = target == TGSI_TEXTURE_2D_MSAA ||
4743 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4744 "llvm.SI.image.load" :
4745 "llvm.SI.image.load.mip";
4746 is_shadow = false;
4747 has_offset = false;
4748 break;
4749 case TGSI_OPCODE_LODQ:
4750 name = "llvm.SI.getlod";
4751 is_shadow = false;
4752 has_offset = false;
4753 break;
4754 case TGSI_OPCODE_TEX:
4755 case TGSI_OPCODE_TEX2:
4756 case TGSI_OPCODE_TXP:
4757 if (ctx->type != PIPE_SHADER_FRAGMENT)
4758 infix = ".lz";
4759 break;
4760 case TGSI_OPCODE_TXB:
4761 case TGSI_OPCODE_TXB2:
4762 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4763 infix = ".b";
4764 break;
4765 case TGSI_OPCODE_TXL:
4766 case TGSI_OPCODE_TXL2:
4767 infix = ".l";
4768 break;
4769 case TGSI_OPCODE_TXD:
4770 infix = ".d";
4771 break;
4772 case TGSI_OPCODE_TG4:
4773 name = "llvm.SI.gather4";
4774 infix = ".lz";
4775 break;
4776 default:
4777 assert(0);
4778 return;
4779 }
4780
4781 /* Add the type and suffixes .c, .o if needed. */
4782 build_int_type_name(LLVMTypeOf(emit_data->args[0]), type, sizeof(type));
4783 sprintf(intr_name, "%s%s%s%s.%s",
4784 name, is_shadow ? ".c" : "", infix,
4785 has_offset ? ".o" : "", type);
4786
4787 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4788 base->gallivm->builder, intr_name, emit_data->dst_type,
4789 emit_data->args, emit_data->arg_count,
4790 LLVMReadNoneAttribute);
4791 }
4792
4793 static void si_llvm_emit_txqs(
4794 const struct lp_build_tgsi_action *action,
4795 struct lp_build_tgsi_context *bld_base,
4796 struct lp_build_emit_data *emit_data)
4797 {
4798 struct si_shader_context *ctx = si_shader_context(bld_base);
4799 struct gallivm_state *gallivm = bld_base->base.gallivm;
4800 LLVMBuilderRef builder = gallivm->builder;
4801 LLVMValueRef res, samples;
4802 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4803
4804 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4805
4806
4807 /* Read the samples from the descriptor directly. */
4808 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4809 samples = LLVMBuildExtractElement(
4810 builder, res,
4811 lp_build_const_int32(gallivm, 3), "");
4812 samples = LLVMBuildLShr(builder, samples,
4813 lp_build_const_int32(gallivm, 16), "");
4814 samples = LLVMBuildAnd(builder, samples,
4815 lp_build_const_int32(gallivm, 0xf), "");
4816 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
4817 samples, "");
4818
4819 emit_data->output[emit_data->chan] = samples;
4820 }
4821
4822 /*
4823 * SI implements derivatives using the local data store (LDS)
4824 * All writes to the LDS happen in all executing threads at
4825 * the same time. TID is the Thread ID for the current
4826 * thread and is a value between 0 and 63, representing
4827 * the thread's position in the wavefront.
4828 *
4829 * For the pixel shader threads are grouped into quads of four pixels.
4830 * The TIDs of the pixels of a quad are:
4831 *
4832 * +------+------+
4833 * |4n + 0|4n + 1|
4834 * +------+------+
4835 * |4n + 2|4n + 3|
4836 * +------+------+
4837 *
4838 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
4839 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
4840 * the current pixel's column, and masking with 0xfffffffe yields the TID
4841 * of the left pixel of the current pixel's row.
4842 *
4843 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
4844 * adding 2 yields the TID of the pixel below the top pixel.
4845 */
4846 /* masks for thread ID. */
4847 #define TID_MASK_TOP_LEFT 0xfffffffc
4848 #define TID_MASK_TOP 0xfffffffd
4849 #define TID_MASK_LEFT 0xfffffffe
4850
4851 static void si_llvm_emit_ddxy(
4852 const struct lp_build_tgsi_action *action,
4853 struct lp_build_tgsi_context *bld_base,
4854 struct lp_build_emit_data *emit_data)
4855 {
4856 struct si_shader_context *ctx = si_shader_context(bld_base);
4857 struct gallivm_state *gallivm = bld_base->base.gallivm;
4858 const struct tgsi_full_instruction *inst = emit_data->inst;
4859 unsigned opcode = inst->Instruction.Opcode;
4860 LLVMValueRef indices[2];
4861 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
4862 LLVMValueRef tl, trbl, result[4];
4863 LLVMValueRef tl_tid, trbl_tid;
4864 unsigned swizzle[4];
4865 unsigned c;
4866 int idx;
4867 unsigned mask;
4868
4869 indices[0] = bld_base->uint_bld.zero;
4870 indices[1] = get_thread_id(ctx);
4871 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
4872 indices, 2, "");
4873
4874 if (opcode == TGSI_OPCODE_DDX_FINE)
4875 mask = TID_MASK_LEFT;
4876 else if (opcode == TGSI_OPCODE_DDY_FINE)
4877 mask = TID_MASK_TOP;
4878 else
4879 mask = TID_MASK_TOP_LEFT;
4880
4881 tl_tid = LLVMBuildAnd(gallivm->builder, indices[1],
4882 lp_build_const_int32(gallivm, mask), "");
4883 indices[1] = tl_tid;
4884 load_ptr0 = LLVMBuildGEP(gallivm->builder, ctx->lds,
4885 indices, 2, "");
4886
4887 /* for DDX we want to next X pixel, DDY next Y pixel. */
4888 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
4889 trbl_tid = LLVMBuildAdd(gallivm->builder, indices[1],
4890 lp_build_const_int32(gallivm, idx), "");
4891 indices[1] = trbl_tid;
4892 load_ptr1 = LLVMBuildGEP(gallivm->builder, ctx->lds,
4893 indices, 2, "");
4894
4895 for (c = 0; c < 4; ++c) {
4896 unsigned i;
4897 LLVMValueRef val;
4898 LLVMValueRef args[2];
4899
4900 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
4901 for (i = 0; i < c; ++i) {
4902 if (swizzle[i] == swizzle[c]) {
4903 result[c] = result[i];
4904 break;
4905 }
4906 }
4907 if (i != c)
4908 continue;
4909
4910 val = LLVMBuildBitCast(gallivm->builder,
4911 lp_build_emit_fetch(bld_base, inst, 0, c),
4912 ctx->i32, "");
4913
4914 if ((HAVE_LLVM >= 0x0309) && ctx->screen->b.family >= CHIP_TONGA) {
4915
4916 args[0] = LLVMBuildMul(gallivm->builder, tl_tid,
4917 lp_build_const_int32(gallivm, 4), "");
4918 args[1] = val;
4919 tl = lp_build_intrinsic(gallivm->builder,
4920 "llvm.amdgcn.ds.bpermute", ctx->i32,
4921 args, 2, LLVMReadNoneAttribute);
4922
4923 args[0] = LLVMBuildMul(gallivm->builder, trbl_tid,
4924 lp_build_const_int32(gallivm, 4), "");
4925 trbl = lp_build_intrinsic(gallivm->builder,
4926 "llvm.amdgcn.ds.bpermute", ctx->i32,
4927 args, 2, LLVMReadNoneAttribute);
4928 } else {
4929 LLVMBuildStore(gallivm->builder, val, store_ptr);
4930 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
4931 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
4932 }
4933 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
4934 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
4935 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
4936 }
4937
4938 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
4939 }
4940
4941 /*
4942 * this takes an I,J coordinate pair,
4943 * and works out the X and Y derivatives.
4944 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
4945 */
4946 static LLVMValueRef si_llvm_emit_ddxy_interp(
4947 struct lp_build_tgsi_context *bld_base,
4948 LLVMValueRef interp_ij)
4949 {
4950 struct si_shader_context *ctx = si_shader_context(bld_base);
4951 struct gallivm_state *gallivm = bld_base->base.gallivm;
4952 LLVMValueRef indices[2];
4953 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
4954 LLVMValueRef tl, tr, bl, result[4];
4955 unsigned c;
4956
4957 indices[0] = bld_base->uint_bld.zero;
4958 indices[1] = get_thread_id(ctx);
4959 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
4960 indices, 2, "");
4961
4962 temp = LLVMBuildAnd(gallivm->builder, indices[1],
4963 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
4964
4965 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
4966 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
4967
4968 indices[1] = temp;
4969 load_ptr_x = LLVMBuildGEP(gallivm->builder, ctx->lds,
4970 indices, 2, "");
4971
4972 indices[1] = temp2;
4973 load_ptr_y = LLVMBuildGEP(gallivm->builder, ctx->lds,
4974 indices, 2, "");
4975
4976 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
4977 lp_build_const_int32(gallivm, 1), "");
4978 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, ctx->lds,
4979 indices, 2, "");
4980
4981 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
4982 lp_build_const_int32(gallivm, 2), "");
4983 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, ctx->lds,
4984 indices, 2, "");
4985
4986 for (c = 0; c < 2; ++c) {
4987 LLVMValueRef store_val;
4988 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
4989
4990 store_val = LLVMBuildExtractElement(gallivm->builder,
4991 interp_ij, c_ll, "");
4992 LLVMBuildStore(gallivm->builder,
4993 store_val,
4994 store_ptr);
4995
4996 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
4997 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
4998
4999 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
5000 tr = LLVMBuildBitCast(gallivm->builder, tr, ctx->f32, "");
5001
5002 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
5003
5004 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
5005 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
5006
5007 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
5008 bl = LLVMBuildBitCast(gallivm->builder, bl, ctx->f32, "");
5009
5010 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
5011 }
5012
5013 return lp_build_gather_values(gallivm, result, 4);
5014 }
5015
5016 static void interp_fetch_args(
5017 struct lp_build_tgsi_context *bld_base,
5018 struct lp_build_emit_data *emit_data)
5019 {
5020 struct si_shader_context *ctx = si_shader_context(bld_base);
5021 struct gallivm_state *gallivm = bld_base->base.gallivm;
5022 const struct tgsi_full_instruction *inst = emit_data->inst;
5023
5024 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
5025 /* offset is in second src, first two channels */
5026 emit_data->args[0] = lp_build_emit_fetch(bld_base,
5027 emit_data->inst, 1,
5028 TGSI_CHAN_X);
5029 emit_data->args[1] = lp_build_emit_fetch(bld_base,
5030 emit_data->inst, 1,
5031 TGSI_CHAN_Y);
5032 emit_data->arg_count = 2;
5033 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5034 LLVMValueRef sample_position;
5035 LLVMValueRef sample_id;
5036 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
5037
5038 /* fetch sample ID, then fetch its sample position,
5039 * and place into first two channels.
5040 */
5041 sample_id = lp_build_emit_fetch(bld_base,
5042 emit_data->inst, 1, TGSI_CHAN_X);
5043 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
5044 ctx->i32, "");
5045 sample_position = load_sample_position(&ctx->radeon_bld, sample_id);
5046
5047 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
5048 sample_position,
5049 lp_build_const_int32(gallivm, 0), "");
5050
5051 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
5052 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
5053 sample_position,
5054 lp_build_const_int32(gallivm, 1), "");
5055 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
5056 emit_data->arg_count = 2;
5057 }
5058 }
5059
5060 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
5061 struct lp_build_tgsi_context *bld_base,
5062 struct lp_build_emit_data *emit_data)
5063 {
5064 struct si_shader_context *ctx = si_shader_context(bld_base);
5065 struct si_shader *shader = ctx->shader;
5066 struct gallivm_state *gallivm = bld_base->base.gallivm;
5067 LLVMValueRef interp_param;
5068 const struct tgsi_full_instruction *inst = emit_data->inst;
5069 const char *intr_name;
5070 int input_index = inst->Src[0].Register.Index;
5071 int chan;
5072 int i;
5073 LLVMValueRef attr_number;
5074 LLVMValueRef params = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
5075 int interp_param_idx;
5076 unsigned interp = shader->selector->info.input_interpolate[input_index];
5077 unsigned location;
5078
5079 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5080
5081 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5082 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
5083 location = TGSI_INTERPOLATE_LOC_CENTER;
5084 else
5085 location = TGSI_INTERPOLATE_LOC_CENTROID;
5086
5087 interp_param_idx = lookup_interp_param_index(interp, location);
5088 if (interp_param_idx == -1)
5089 return;
5090 else if (interp_param_idx)
5091 interp_param = get_interp_param(ctx, interp_param_idx);
5092 else
5093 interp_param = NULL;
5094
5095 attr_number = lp_build_const_int32(gallivm, input_index);
5096
5097 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5098 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5099 LLVMValueRef ij_out[2];
5100 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
5101
5102 /*
5103 * take the I then J parameters, and the DDX/Y for it, and
5104 * calculate the IJ inputs for the interpolator.
5105 * temp1 = ddx * offset/sample.x + I;
5106 * interp_param.I = ddy * offset/sample.y + temp1;
5107 * temp1 = ddx * offset/sample.x + J;
5108 * interp_param.J = ddy * offset/sample.y + temp1;
5109 */
5110 for (i = 0; i < 2; i++) {
5111 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
5112 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
5113 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
5114 ddxy_out, ix_ll, "");
5115 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
5116 ddxy_out, iy_ll, "");
5117 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5118 interp_param, ix_ll, "");
5119 LLVMValueRef temp1, temp2;
5120
5121 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5122 ctx->f32, "");
5123
5124 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5125
5126 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5127
5128 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5129
5130 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5131
5132 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
5133 temp2, ctx->i32, "");
5134 }
5135 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
5136 }
5137
5138 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
5139 for (chan = 0; chan < 2; chan++) {
5140 LLVMValueRef args[4];
5141 LLVMValueRef llvm_chan;
5142 unsigned schan;
5143
5144 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5145 llvm_chan = lp_build_const_int32(gallivm, schan);
5146
5147 args[0] = llvm_chan;
5148 args[1] = attr_number;
5149 args[2] = params;
5150 args[3] = interp_param;
5151
5152 emit_data->output[chan] =
5153 lp_build_intrinsic(gallivm->builder, intr_name,
5154 ctx->f32, args, args[3] ? 4 : 3,
5155 LLVMReadNoneAttribute);
5156 }
5157 }
5158
5159 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5160 struct lp_build_emit_data *emit_data)
5161 {
5162 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
5163 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5164 unsigned stream;
5165
5166 assert(src0.File == TGSI_FILE_IMMEDIATE);
5167
5168 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
5169 return stream;
5170 }
5171
5172 /* Emit one vertex from the geometry shader */
5173 static void si_llvm_emit_vertex(
5174 const struct lp_build_tgsi_action *action,
5175 struct lp_build_tgsi_context *bld_base,
5176 struct lp_build_emit_data *emit_data)
5177 {
5178 struct si_shader_context *ctx = si_shader_context(bld_base);
5179 struct lp_build_context *uint = &bld_base->uint_bld;
5180 struct si_shader *shader = ctx->shader;
5181 struct tgsi_shader_info *info = &shader->selector->info;
5182 struct gallivm_state *gallivm = bld_base->base.gallivm;
5183 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
5184 SI_PARAM_GS2VS_OFFSET);
5185 LLVMValueRef gs_next_vertex;
5186 LLVMValueRef can_emit, kill;
5187 LLVMValueRef args[2];
5188 unsigned chan;
5189 int i;
5190 unsigned stream;
5191
5192 stream = si_llvm_get_stream(bld_base, emit_data);
5193
5194 /* Write vertex attribute values to GSVS ring */
5195 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5196 ctx->gs_next_vertex[stream],
5197 "");
5198
5199 /* If this thread has already emitted the declared maximum number of
5200 * vertices, kill it: excessive vertex emissions are not supposed to
5201 * have any effect, and GS threads have no externally observable
5202 * effects other than emitting vertices.
5203 */
5204 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
5205 lp_build_const_int32(gallivm,
5206 shader->selector->gs_max_out_vertices), "");
5207 kill = lp_build_select(&bld_base->base, can_emit,
5208 lp_build_const_float(gallivm, 1.0f),
5209 lp_build_const_float(gallivm, -1.0f));
5210
5211 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
5212 ctx->voidt, &kill, 1, 0);
5213
5214 for (i = 0; i < info->num_outputs; i++) {
5215 LLVMValueRef *out_ptr =
5216 ctx->radeon_bld.soa.outputs[i];
5217
5218 for (chan = 0; chan < 4; chan++) {
5219 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5220 LLVMValueRef voffset =
5221 lp_build_const_int32(gallivm, (i * 4 + chan) *
5222 shader->selector->gs_max_out_vertices);
5223
5224 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5225 voffset = lp_build_mul_imm(uint, voffset, 4);
5226
5227 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5228
5229 build_tbuffer_store(ctx,
5230 ctx->gsvs_ring[stream],
5231 out_val, 1,
5232 voffset, soffset, 0,
5233 V_008F0C_BUF_DATA_FORMAT_32,
5234 V_008F0C_BUF_NUM_FORMAT_UINT,
5235 1, 0, 1, 1, 0);
5236 }
5237 }
5238 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5239 lp_build_const_int32(gallivm, 1));
5240
5241 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5242
5243 /* Signal vertex emission */
5244 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
5245 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
5246 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5247 ctx->voidt, args, 2, 0);
5248 }
5249
5250 /* Cut one primitive from the geometry shader */
5251 static void si_llvm_emit_primitive(
5252 const struct lp_build_tgsi_action *action,
5253 struct lp_build_tgsi_context *bld_base,
5254 struct lp_build_emit_data *emit_data)
5255 {
5256 struct si_shader_context *ctx = si_shader_context(bld_base);
5257 struct gallivm_state *gallivm = bld_base->base.gallivm;
5258 LLVMValueRef args[2];
5259 unsigned stream;
5260
5261 /* Signal primitive cut */
5262 stream = si_llvm_get_stream(bld_base, emit_data);
5263 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
5264 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
5265 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5266 ctx->voidt, args, 2, 0);
5267 }
5268
5269 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5270 struct lp_build_tgsi_context *bld_base,
5271 struct lp_build_emit_data *emit_data)
5272 {
5273 struct si_shader_context *ctx = si_shader_context(bld_base);
5274 struct gallivm_state *gallivm = bld_base->base.gallivm;
5275
5276 /* The real barrier instruction isn’t needed, because an entire patch
5277 * always fits into a single wave.
5278 */
5279 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
5280 emit_optimization_barrier(ctx);
5281 return;
5282 }
5283
5284 lp_build_intrinsic(gallivm->builder,
5285 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5286 : "llvm.AMDGPU.barrier.local",
5287 ctx->voidt, NULL, 0, 0);
5288 }
5289
5290 static const struct lp_build_tgsi_action tex_action = {
5291 .fetch_args = tex_fetch_args,
5292 .emit = build_tex_intrinsic,
5293 };
5294
5295 static const struct lp_build_tgsi_action interp_action = {
5296 .fetch_args = interp_fetch_args,
5297 .emit = build_interp_intrinsic,
5298 };
5299
5300 static void si_create_function(struct si_shader_context *ctx,
5301 LLVMTypeRef *returns, unsigned num_returns,
5302 LLVMTypeRef *params, unsigned num_params,
5303 int last_array_pointer, int last_sgpr)
5304 {
5305 int i;
5306
5307 radeon_llvm_create_func(&ctx->radeon_bld, returns, num_returns,
5308 params, num_params);
5309 radeon_llvm_shader_type(ctx->radeon_bld.main_fn, ctx->type);
5310 ctx->return_value = LLVMGetUndef(ctx->radeon_bld.return_type);
5311
5312 for (i = 0; i <= last_sgpr; ++i) {
5313 LLVMValueRef P = LLVMGetParam(ctx->radeon_bld.main_fn, i);
5314
5315 /* The combination of:
5316 * - ByVal
5317 * - dereferenceable
5318 * - tbaa
5319 * allows the optimization passes to move loads and reduces
5320 * SGPR spilling significantly.
5321 */
5322 if (i <= last_array_pointer) {
5323 LLVMAddAttribute(P, LLVMByValAttribute);
5324 lp_add_attr_dereferenceable(P, UINT64_MAX);
5325 } else
5326 LLVMAddAttribute(P, LLVMInRegAttribute);
5327 }
5328
5329 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5330 /* These were copied from some LLVM test. */
5331 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5332 "less-precise-fpmad",
5333 "true");
5334 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5335 "no-infs-fp-math",
5336 "true");
5337 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5338 "no-nans-fp-math",
5339 "true");
5340 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5341 "unsafe-fp-math",
5342 "true");
5343 }
5344 }
5345
5346 static void create_meta_data(struct si_shader_context *ctx)
5347 {
5348 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
5349 LLVMValueRef tbaa_const[3];
5350
5351 ctx->range_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5352 "range", 5);
5353 ctx->tbaa_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5354 "tbaa", 4);
5355 ctx->uniform_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5356 "amdgpu.uniform", 14);
5357
5358 ctx->empty_md = LLVMMDNodeInContext(gallivm->context, NULL, 0);
5359
5360 tbaa_const[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
5361 tbaa_const[1] = 0;
5362 tbaa_const[2] = lp_build_const_int32(gallivm, 1);
5363 ctx->tbaa_const_md = LLVMMDNodeInContext(gallivm->context, tbaa_const, 3);
5364 }
5365
5366 static void declare_streamout_params(struct si_shader_context *ctx,
5367 struct pipe_stream_output_info *so,
5368 LLVMTypeRef *params, LLVMTypeRef i32,
5369 unsigned *num_params)
5370 {
5371 int i;
5372
5373 /* Streamout SGPRs. */
5374 if (so->num_outputs) {
5375 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5376 params[ctx->param_streamout_config = (*num_params)++] = i32;
5377 else
5378 ctx->param_streamout_config = ctx->param_tess_offchip;
5379
5380 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5381 }
5382 /* A streamout buffer offset is loaded if the stride is non-zero. */
5383 for (i = 0; i < 4; i++) {
5384 if (!so->stride[i])
5385 continue;
5386
5387 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5388 }
5389 }
5390
5391 static unsigned llvm_get_type_size(LLVMTypeRef type)
5392 {
5393 LLVMTypeKind kind = LLVMGetTypeKind(type);
5394
5395 switch (kind) {
5396 case LLVMIntegerTypeKind:
5397 return LLVMGetIntTypeWidth(type) / 8;
5398 case LLVMFloatTypeKind:
5399 return 4;
5400 case LLVMPointerTypeKind:
5401 return 8;
5402 case LLVMVectorTypeKind:
5403 return LLVMGetVectorSize(type) *
5404 llvm_get_type_size(LLVMGetElementType(type));
5405 default:
5406 assert(0);
5407 return 0;
5408 }
5409 }
5410
5411 static void declare_tess_lds(struct si_shader_context *ctx)
5412 {
5413 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5414 LLVMTypeRef i32 = ctx->radeon_bld.soa.bld_base.uint_bld.elem_type;
5415 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5416
5417 /* The actual size is computed outside of the shader to reduce
5418 * the number of shader variants. */
5419 ctx->lds =
5420 LLVMAddGlobalInAddressSpace(gallivm->module,
5421 LLVMArrayType(i32, lds_size / 4),
5422 "tess_lds",
5423 LOCAL_ADDR_SPACE);
5424 }
5425
5426 static void create_function(struct si_shader_context *ctx)
5427 {
5428 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5429 struct gallivm_state *gallivm = bld_base->base.gallivm;
5430 struct si_shader *shader = ctx->shader;
5431 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
5432 LLVMTypeRef returns[16+32*4];
5433 unsigned i, last_array_pointer, last_sgpr, num_params, num_return_sgprs;
5434 unsigned num_returns = 0;
5435
5436 v3i32 = LLVMVectorType(ctx->i32, 3);
5437
5438 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5439 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5440 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5441 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5442 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5443 last_array_pointer = SI_PARAM_SHADER_BUFFERS;
5444
5445 switch (ctx->type) {
5446 case PIPE_SHADER_VERTEX:
5447 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
5448 last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
5449 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5450 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5451 num_params = SI_PARAM_START_INSTANCE+1;
5452
5453 if (shader->key.vs.as_es) {
5454 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5455 } else if (shader->key.vs.as_ls) {
5456 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
5457 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
5458 } else {
5459 if (ctx->is_gs_copy_shader) {
5460 last_array_pointer = SI_PARAM_RW_BUFFERS;
5461 num_params = SI_PARAM_RW_BUFFERS+1;
5462 } else {
5463 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5464 num_params = SI_PARAM_VS_STATE_BITS+1;
5465 }
5466
5467 /* The locations of the other parameters are assigned dynamically. */
5468 declare_streamout_params(ctx, &shader->selector->so,
5469 params, ctx->i32, &num_params);
5470 }
5471
5472 last_sgpr = num_params-1;
5473
5474 /* VGPRs */
5475 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5476 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5477 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5478 params[ctx->param_instance_id = num_params++] = ctx->i32;
5479
5480 if (!ctx->is_monolithic &&
5481 !ctx->is_gs_copy_shader) {
5482 /* Vertex load indices. */
5483 ctx->param_vertex_index0 = num_params;
5484
5485 for (i = 0; i < shader->selector->info.num_inputs; i++)
5486 params[num_params++] = ctx->i32;
5487
5488 /* PrimitiveID output. */
5489 if (!shader->key.vs.as_es && !shader->key.vs.as_ls)
5490 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5491 returns[num_returns++] = ctx->f32;
5492 }
5493 break;
5494
5495 case PIPE_SHADER_TESS_CTRL:
5496 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5497 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5498 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5499 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5500 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5501 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5502 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5503
5504 /* VGPRs */
5505 params[SI_PARAM_PATCH_ID] = ctx->i32;
5506 params[SI_PARAM_REL_IDS] = ctx->i32;
5507 num_params = SI_PARAM_REL_IDS+1;
5508
5509 if (!ctx->is_monolithic) {
5510 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5511 * placed after the user SGPRs.
5512 */
5513 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5514 returns[num_returns++] = ctx->i32; /* SGPRs */
5515
5516 for (i = 0; i < 3; i++)
5517 returns[num_returns++] = ctx->f32; /* VGPRs */
5518 }
5519 break;
5520
5521 case PIPE_SHADER_TESS_EVAL:
5522 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5523 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5524
5525 if (shader->key.tes.as_es) {
5526 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5527 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5528 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5529 } else {
5530 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5531 declare_streamout_params(ctx, &shader->selector->so,
5532 params, ctx->i32, &num_params);
5533 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5534 }
5535 last_sgpr = num_params - 1;
5536
5537 /* VGPRs */
5538 params[ctx->param_tes_u = num_params++] = ctx->f32;
5539 params[ctx->param_tes_v = num_params++] = ctx->f32;
5540 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5541 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5542
5543 /* PrimitiveID output. */
5544 if (!ctx->is_monolithic && !shader->key.tes.as_es)
5545 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5546 returns[num_returns++] = ctx->f32;
5547 break;
5548
5549 case PIPE_SHADER_GEOMETRY:
5550 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5551 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5552 last_sgpr = SI_PARAM_GS_WAVE_ID;
5553
5554 /* VGPRs */
5555 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5556 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5557 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5558 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5559 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5560 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5561 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5562 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5563 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5564 break;
5565
5566 case PIPE_SHADER_FRAGMENT:
5567 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5568 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5569 last_sgpr = SI_PARAM_PRIM_MASK;
5570 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5571 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5572 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5573 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5574 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5575 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5576 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5577 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5578 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5579 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5580 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5581 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5582 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5583 params[SI_PARAM_ANCILLARY] = ctx->i32;
5584 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5585 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5586 num_params = SI_PARAM_POS_FIXED_PT+1;
5587
5588 if (!ctx->is_monolithic) {
5589 /* Color inputs from the prolog. */
5590 if (shader->selector->info.colors_read) {
5591 unsigned num_color_elements =
5592 util_bitcount(shader->selector->info.colors_read);
5593
5594 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5595 for (i = 0; i < num_color_elements; i++)
5596 params[num_params++] = ctx->f32;
5597 }
5598
5599 /* Outputs for the epilog. */
5600 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5601 num_returns =
5602 num_return_sgprs +
5603 util_bitcount(shader->selector->info.colors_written) * 4 +
5604 shader->selector->info.writes_z +
5605 shader->selector->info.writes_stencil +
5606 shader->selector->info.writes_samplemask +
5607 1 /* SampleMaskIn */;
5608
5609 num_returns = MAX2(num_returns,
5610 num_return_sgprs +
5611 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5612
5613 for (i = 0; i < num_return_sgprs; i++)
5614 returns[i] = ctx->i32;
5615 for (; i < num_returns; i++)
5616 returns[i] = ctx->f32;
5617 }
5618 break;
5619
5620 case PIPE_SHADER_COMPUTE:
5621 params[SI_PARAM_GRID_SIZE] = v3i32;
5622 params[SI_PARAM_BLOCK_ID] = v3i32;
5623 last_sgpr = SI_PARAM_BLOCK_ID;
5624
5625 params[SI_PARAM_THREAD_ID] = v3i32;
5626 num_params = SI_PARAM_THREAD_ID + 1;
5627 break;
5628 default:
5629 assert(0 && "unimplemented shader");
5630 return;
5631 }
5632
5633 assert(num_params <= ARRAY_SIZE(params));
5634
5635 si_create_function(ctx, returns, num_returns, params,
5636 num_params, last_array_pointer, last_sgpr);
5637
5638 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5639 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5640 !ctx->is_monolithic) {
5641 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5642 "InitialPSInputAddr",
5643 S_0286D0_PERSP_SAMPLE_ENA(1) |
5644 S_0286D0_PERSP_CENTER_ENA(1) |
5645 S_0286D0_PERSP_CENTROID_ENA(1) |
5646 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5647 S_0286D0_LINEAR_CENTER_ENA(1) |
5648 S_0286D0_LINEAR_CENTROID_ENA(1) |
5649 S_0286D0_FRONT_FACE_ENA(1) |
5650 S_0286D0_POS_FIXED_PT_ENA(1));
5651 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5652 const unsigned *properties = shader->selector->info.properties;
5653 unsigned max_work_group_size =
5654 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5655 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5656 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5657
5658 assert(max_work_group_size);
5659
5660 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5661 "amdgpu-max-work-group-size",
5662 max_work_group_size);
5663 }
5664
5665 shader->info.num_input_sgprs = 0;
5666 shader->info.num_input_vgprs = 0;
5667
5668 for (i = 0; i <= last_sgpr; ++i)
5669 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5670
5671 /* Unused fragment shader inputs are eliminated by the compiler,
5672 * so we don't know yet how many there will be.
5673 */
5674 if (ctx->type != PIPE_SHADER_FRAGMENT)
5675 for (; i < num_params; ++i)
5676 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5677
5678 if (bld_base->info &&
5679 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5680 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5681 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5682 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5683 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5684 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5685 ctx->lds =
5686 LLVMAddGlobalInAddressSpace(gallivm->module,
5687 LLVMArrayType(ctx->i32, 64),
5688 "ddxy_lds",
5689 LOCAL_ADDR_SPACE);
5690
5691 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.vs.as_ls) ||
5692 ctx->type == PIPE_SHADER_TESS_CTRL ||
5693 ctx->type == PIPE_SHADER_TESS_EVAL)
5694 declare_tess_lds(ctx);
5695 }
5696
5697 static void preload_constants(struct si_shader_context *ctx)
5698 {
5699 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5700 struct gallivm_state *gallivm = bld_base->base.gallivm;
5701 const struct tgsi_shader_info *info = bld_base->info;
5702 unsigned buf;
5703 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
5704
5705 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
5706 unsigned i, num_const = info->const_file_max[buf] + 1;
5707
5708 if (num_const == 0)
5709 continue;
5710
5711 /* Allocate space for the constant values */
5712 ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
5713
5714 /* Load the resource descriptor */
5715 ctx->const_buffers[buf] =
5716 build_indexed_load_const(ctx, ptr, lp_build_const_int32(gallivm, buf));
5717
5718 /* Load the constants, we rely on the code sinking to do the rest */
5719 for (i = 0; i < num_const * 4; ++i) {
5720 ctx->constants[buf][i] =
5721 buffer_load_const(gallivm->builder,
5722 ctx->const_buffers[buf],
5723 lp_build_const_int32(gallivm, i * 4),
5724 ctx->f32);
5725 }
5726 }
5727 }
5728
5729 static void preload_shader_buffers(struct si_shader_context *ctx)
5730 {
5731 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5732 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_SHADER_BUFFERS);
5733 int buf, maxbuf;
5734
5735 maxbuf = MIN2(ctx->shader->selector->info.file_max[TGSI_FILE_BUFFER],
5736 SI_NUM_SHADER_BUFFERS - 1);
5737 for (buf = 0; buf <= maxbuf; ++buf) {
5738 ctx->shader_buffers[buf] =
5739 build_indexed_load_const(
5740 ctx, ptr, lp_build_const_int32(gallivm, buf));
5741 }
5742 }
5743
5744 static void preload_samplers(struct si_shader_context *ctx)
5745 {
5746 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5747 struct gallivm_state *gallivm = bld_base->base.gallivm;
5748 const struct tgsi_shader_info *info = bld_base->info;
5749 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
5750 LLVMValueRef offset;
5751
5752 if (num_samplers == 0)
5753 return;
5754
5755 /* Load the resources and samplers, we rely on the code sinking to do the rest */
5756 for (i = 0; i < num_samplers; ++i) {
5757 /* Resource */
5758 offset = lp_build_const_int32(gallivm, i);
5759 ctx->sampler_views[i] =
5760 get_sampler_desc(ctx, offset, DESC_IMAGE);
5761
5762 /* FMASK resource */
5763 if (info->is_msaa_sampler[i])
5764 ctx->fmasks[i] =
5765 get_sampler_desc(ctx, offset, DESC_FMASK);
5766 else {
5767 ctx->sampler_states[i] =
5768 get_sampler_desc(ctx, offset, DESC_SAMPLER);
5769 ctx->sampler_states[i] =
5770 sici_fix_sampler_aniso(ctx, ctx->sampler_views[i],
5771 ctx->sampler_states[i]);
5772 }
5773 }
5774 }
5775
5776 static void preload_images(struct si_shader_context *ctx)
5777 {
5778 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5779 struct tgsi_shader_info *info = &ctx->shader->selector->info;
5780 struct gallivm_state *gallivm = bld_base->base.gallivm;
5781 unsigned num_images = bld_base->info->file_max[TGSI_FILE_IMAGE] + 1;
5782 LLVMValueRef res_ptr;
5783 unsigned i;
5784
5785 if (num_images == 0)
5786 return;
5787
5788 res_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
5789
5790 for (i = 0; i < num_images; ++i) {
5791 /* Rely on LLVM to shrink the load for buffer resources. */
5792 LLVMValueRef rsrc =
5793 build_indexed_load_const(ctx, res_ptr,
5794 lp_build_const_int32(gallivm, i));
5795
5796 if (info->images_writemask & (1 << i) &&
5797 !(info->images_buffers & (1 << i)))
5798 rsrc = force_dcc_off(ctx, rsrc);
5799
5800 ctx->images[i] = rsrc;
5801 }
5802 }
5803
5804 static void preload_streamout_buffers(struct si_shader_context *ctx)
5805 {
5806 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5807 struct gallivm_state *gallivm = bld_base->base.gallivm;
5808 unsigned i;
5809
5810 /* Streamout can only be used if the shader is compiled as VS. */
5811 if (!ctx->shader->selector->so.num_outputs ||
5812 (ctx->type == PIPE_SHADER_VERTEX &&
5813 (ctx->shader->key.vs.as_es ||
5814 ctx->shader->key.vs.as_ls)) ||
5815 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5816 ctx->shader->key.tes.as_es))
5817 return;
5818
5819 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
5820 SI_PARAM_RW_BUFFERS);
5821
5822 /* Load the resources, we rely on the code sinking to do the rest */
5823 for (i = 0; i < 4; ++i) {
5824 if (ctx->shader->selector->so.stride[i]) {
5825 LLVMValueRef offset = lp_build_const_int32(gallivm,
5826 SI_VS_STREAMOUT_BUF0 + i);
5827
5828 ctx->so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
5829 }
5830 }
5831 }
5832
5833 /**
5834 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5835 * for later use.
5836 */
5837 static void preload_ring_buffers(struct si_shader_context *ctx)
5838 {
5839 struct gallivm_state *gallivm =
5840 ctx->radeon_bld.soa.bld_base.base.gallivm;
5841
5842 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
5843 SI_PARAM_RW_BUFFERS);
5844
5845 if ((ctx->type == PIPE_SHADER_VERTEX &&
5846 ctx->shader->key.vs.as_es) ||
5847 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5848 ctx->shader->key.tes.as_es) ||
5849 ctx->type == PIPE_SHADER_GEOMETRY) {
5850 unsigned ring =
5851 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5852 : SI_ES_RING_ESGS;
5853 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5854
5855 ctx->esgs_ring =
5856 build_indexed_load_const(ctx, buf_ptr, offset);
5857 }
5858
5859 if (ctx->is_gs_copy_shader) {
5860 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_VS_RING_GSVS);
5861
5862 ctx->gsvs_ring[0] =
5863 build_indexed_load_const(ctx, buf_ptr, offset);
5864 }
5865 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5866 int i;
5867 for (i = 0; i < 4; i++) {
5868 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_GS_RING_GSVS0 + i);
5869
5870 ctx->gsvs_ring[i] =
5871 build_indexed_load_const(ctx, buf_ptr, offset);
5872 }
5873 }
5874 }
5875
5876 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5877 LLVMValueRef param_rw_buffers,
5878 unsigned param_pos_fixed_pt)
5879 {
5880 struct lp_build_tgsi_context *bld_base =
5881 &ctx->radeon_bld.soa.bld_base;
5882 struct gallivm_state *gallivm = bld_base->base.gallivm;
5883 LLVMBuilderRef builder = gallivm->builder;
5884 LLVMValueRef slot, desc, offset, row, bit, address[2];
5885
5886 /* Use the fixed-point gl_FragCoord input.
5887 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5888 * per coordinate to get the repeating effect.
5889 */
5890 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5891 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5892
5893 /* Load the buffer descriptor. */
5894 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
5895 desc = build_indexed_load_const(ctx, param_rw_buffers, slot);
5896
5897 /* The stipple pattern is 32x32, each row has 32 bits. */
5898 offset = LLVMBuildMul(builder, address[1],
5899 LLVMConstInt(ctx->i32, 4, 0), "");
5900 row = buffer_load_const(builder, desc, offset, ctx->i32);
5901 bit = LLVMBuildLShr(builder, row, address[0], "");
5902 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5903
5904 /* The intrinsic kills the thread if arg < 0. */
5905 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
5906 LLVMConstReal(ctx->f32, -1), "");
5907 lp_build_intrinsic(builder, "llvm.AMDGPU.kill", ctx->voidt, &bit, 1, 0);
5908 }
5909
5910 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
5911 struct si_shader_config *conf,
5912 unsigned symbol_offset)
5913 {
5914 unsigned i;
5915 const unsigned char *config =
5916 radeon_shader_binary_config_start(binary, symbol_offset);
5917 bool really_needs_scratch = false;
5918
5919 /* LLVM adds SGPR spills to the scratch size.
5920 * Find out if we really need the scratch buffer.
5921 */
5922 for (i = 0; i < binary->reloc_count; i++) {
5923 const struct radeon_shader_reloc *reloc = &binary->relocs[i];
5924
5925 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5926 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5927 really_needs_scratch = true;
5928 break;
5929 }
5930 }
5931
5932 /* XXX: We may be able to emit some of these values directly rather than
5933 * extracting fields to be emitted later.
5934 */
5935
5936 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5937 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5938 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5939 switch (reg) {
5940 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5941 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5942 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5943 case R_00B848_COMPUTE_PGM_RSRC1:
5944 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5945 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5946 conf->float_mode = G_00B028_FLOAT_MODE(value);
5947 conf->rsrc1 = value;
5948 break;
5949 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5950 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5951 break;
5952 case R_00B84C_COMPUTE_PGM_RSRC2:
5953 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5954 conf->rsrc2 = value;
5955 break;
5956 case R_0286CC_SPI_PS_INPUT_ENA:
5957 conf->spi_ps_input_ena = value;
5958 break;
5959 case R_0286D0_SPI_PS_INPUT_ADDR:
5960 conf->spi_ps_input_addr = value;
5961 break;
5962 case R_0286E8_SPI_TMPRING_SIZE:
5963 case R_00B860_COMPUTE_TMPRING_SIZE:
5964 /* WAVESIZE is in units of 256 dwords. */
5965 if (really_needs_scratch)
5966 conf->scratch_bytes_per_wave =
5967 G_00B860_WAVESIZE(value) * 256 * 4;
5968 break;
5969 default:
5970 {
5971 static bool printed;
5972
5973 if (!printed) {
5974 fprintf(stderr, "Warning: LLVM emitted unknown "
5975 "config register: 0x%x\n", reg);
5976 printed = true;
5977 }
5978 }
5979 break;
5980 }
5981
5982 if (!conf->spi_ps_input_addr)
5983 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5984 }
5985 }
5986
5987 void si_shader_apply_scratch_relocs(struct si_context *sctx,
5988 struct si_shader *shader,
5989 struct si_shader_config *config,
5990 uint64_t scratch_va)
5991 {
5992 unsigned i;
5993 uint32_t scratch_rsrc_dword0 = scratch_va;
5994 uint32_t scratch_rsrc_dword1 =
5995 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5996
5997 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
5998 * correctly.
5999 */
6000 if (HAVE_LLVM >= 0x0309)
6001 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
6002 else
6003 scratch_rsrc_dword1 |=
6004 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
6005
6006 for (i = 0 ; i < shader->binary.reloc_count; i++) {
6007 const struct radeon_shader_reloc *reloc =
6008 &shader->binary.relocs[i];
6009 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
6010 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
6011 &scratch_rsrc_dword0, 4);
6012 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
6013 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
6014 &scratch_rsrc_dword1, 4);
6015 }
6016 }
6017 }
6018
6019 static unsigned si_get_shader_binary_size(struct si_shader *shader)
6020 {
6021 unsigned size = shader->binary.code_size;
6022
6023 if (shader->prolog)
6024 size += shader->prolog->binary.code_size;
6025 if (shader->epilog)
6026 size += shader->epilog->binary.code_size;
6027 return size;
6028 }
6029
6030 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
6031 {
6032 const struct radeon_shader_binary *prolog =
6033 shader->prolog ? &shader->prolog->binary : NULL;
6034 const struct radeon_shader_binary *epilog =
6035 shader->epilog ? &shader->epilog->binary : NULL;
6036 const struct radeon_shader_binary *mainb = &shader->binary;
6037 unsigned bo_size = si_get_shader_binary_size(shader) +
6038 (!epilog ? mainb->rodata_size : 0);
6039 unsigned char *ptr;
6040
6041 assert(!prolog || !prolog->rodata_size);
6042 assert((!prolog && !epilog) || !mainb->rodata_size);
6043 assert(!epilog || !epilog->rodata_size);
6044
6045 r600_resource_reference(&shader->bo, NULL);
6046 shader->bo = si_resource_create_custom(&sscreen->b.b,
6047 PIPE_USAGE_IMMUTABLE,
6048 bo_size);
6049 if (!shader->bo)
6050 return -ENOMEM;
6051
6052 /* Upload. */
6053 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
6054 PIPE_TRANSFER_READ_WRITE);
6055
6056 if (prolog) {
6057 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
6058 ptr += prolog->code_size;
6059 }
6060
6061 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
6062 ptr += mainb->code_size;
6063
6064 if (epilog)
6065 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
6066 else if (mainb->rodata_size > 0)
6067 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
6068
6069 sscreen->b.ws->buffer_unmap(shader->bo->buf);
6070 return 0;
6071 }
6072
6073 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
6074 struct pipe_debug_callback *debug,
6075 const char *name, FILE *file)
6076 {
6077 char *line, *p;
6078 unsigned i, count;
6079
6080 if (binary->disasm_string) {
6081 fprintf(file, "Shader %s disassembly:\n", name);
6082 fprintf(file, "%s", binary->disasm_string);
6083
6084 if (debug && debug->debug_message) {
6085 /* Very long debug messages are cut off, so send the
6086 * disassembly one line at a time. This causes more
6087 * overhead, but on the plus side it simplifies
6088 * parsing of resulting logs.
6089 */
6090 pipe_debug_message(debug, SHADER_INFO,
6091 "Shader Disassembly Begin");
6092
6093 line = binary->disasm_string;
6094 while (*line) {
6095 p = util_strchrnul(line, '\n');
6096 count = p - line;
6097
6098 if (count) {
6099 pipe_debug_message(debug, SHADER_INFO,
6100 "%.*s", count, line);
6101 }
6102
6103 if (!*p)
6104 break;
6105 line = p + 1;
6106 }
6107
6108 pipe_debug_message(debug, SHADER_INFO,
6109 "Shader Disassembly End");
6110 }
6111 } else {
6112 fprintf(file, "Shader %s binary:\n", name);
6113 for (i = 0; i < binary->code_size; i += 4) {
6114 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
6115 binary->code[i + 3], binary->code[i + 2],
6116 binary->code[i + 1], binary->code[i]);
6117 }
6118 }
6119 }
6120
6121 static void si_shader_dump_stats(struct si_screen *sscreen,
6122 struct si_shader_config *conf,
6123 unsigned num_inputs,
6124 unsigned code_size,
6125 struct pipe_debug_callback *debug,
6126 unsigned processor,
6127 FILE *file)
6128 {
6129 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
6130 unsigned lds_per_wave = 0;
6131 unsigned max_simd_waves = 10;
6132 /* Assuming SGPRs aren't spilled. */
6133 unsigned spilled_vgprs = conf->scratch_bytes_per_wave / 64 / 4;
6134
6135 /* Compute LDS usage for PS. */
6136 if (processor == PIPE_SHADER_FRAGMENT) {
6137 /* The minimum usage per wave is (num_inputs * 48). The maximum
6138 * usage is (num_inputs * 48 * 16).
6139 * We can get anything in between and it varies between waves.
6140 *
6141 * The 48 bytes per input for a single primitive is equal to
6142 * 4 bytes/component * 4 components/input * 3 points.
6143 *
6144 * Other stages don't know the size at compile time or don't
6145 * allocate LDS per wave, but instead they do it per thread group.
6146 */
6147 lds_per_wave = conf->lds_size * lds_increment +
6148 align(num_inputs * 48, lds_increment);
6149 }
6150
6151 /* Compute the per-SIMD wave counts. */
6152 if (conf->num_sgprs) {
6153 if (sscreen->b.chip_class >= VI)
6154 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
6155 else
6156 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
6157 }
6158
6159 if (conf->num_vgprs)
6160 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
6161
6162 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
6163 * that PS can use.
6164 */
6165 if (lds_per_wave)
6166 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
6167
6168 if (file != stderr ||
6169 r600_can_dump_shader(&sscreen->b, processor)) {
6170 if (processor == PIPE_SHADER_FRAGMENT) {
6171 fprintf(file, "*** SHADER CONFIG ***\n"
6172 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6173 "SPI_PS_INPUT_ENA = 0x%04x\n",
6174 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
6175 }
6176
6177 fprintf(file, "*** SHADER STATS ***\n"
6178 "SGPRS: %d\n"
6179 "VGPRS: %d\n"
6180 "Spilled VGPRs: %d\n"
6181 "Code Size: %d bytes\n"
6182 "LDS: %d blocks\n"
6183 "Scratch: %d bytes per wave\n"
6184 "Max Waves: %d\n"
6185 "********************\n",
6186 conf->num_sgprs, conf->num_vgprs, spilled_vgprs, code_size,
6187 conf->lds_size, conf->scratch_bytes_per_wave,
6188 max_simd_waves);
6189 }
6190
6191 pipe_debug_message(debug, SHADER_INFO,
6192 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6193 "LDS: %d Scratch: %d Max Waves: %d Spilled VGPRs: %d",
6194 conf->num_sgprs, conf->num_vgprs, code_size,
6195 conf->lds_size, conf->scratch_bytes_per_wave,
6196 max_simd_waves, spilled_vgprs);
6197 }
6198
6199 static const char *si_get_shader_name(struct si_shader *shader,
6200 unsigned processor)
6201 {
6202 switch (processor) {
6203 case PIPE_SHADER_VERTEX:
6204 if (shader->key.vs.as_es)
6205 return "Vertex Shader as ES";
6206 else if (shader->key.vs.as_ls)
6207 return "Vertex Shader as LS";
6208 else
6209 return "Vertex Shader as VS";
6210 case PIPE_SHADER_TESS_CTRL:
6211 return "Tessellation Control Shader";
6212 case PIPE_SHADER_TESS_EVAL:
6213 if (shader->key.tes.as_es)
6214 return "Tessellation Evaluation Shader as ES";
6215 else
6216 return "Tessellation Evaluation Shader as VS";
6217 case PIPE_SHADER_GEOMETRY:
6218 if (shader->gs_copy_shader == NULL)
6219 return "GS Copy Shader as VS";
6220 else
6221 return "Geometry Shader";
6222 case PIPE_SHADER_FRAGMENT:
6223 return "Pixel Shader";
6224 case PIPE_SHADER_COMPUTE:
6225 return "Compute Shader";
6226 default:
6227 return "Unknown Shader";
6228 }
6229 }
6230
6231 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6232 struct pipe_debug_callback *debug, unsigned processor,
6233 FILE *file)
6234 {
6235 if (file != stderr && shader->binary.llvm_ir_string) {
6236 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
6237 si_get_shader_name(shader, processor));
6238 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
6239 }
6240
6241 if (file != stderr ||
6242 (r600_can_dump_shader(&sscreen->b, processor) &&
6243 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6244 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6245
6246 if (shader->prolog)
6247 si_shader_dump_disassembly(&shader->prolog->binary,
6248 debug, "prolog", file);
6249
6250 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6251
6252 if (shader->epilog)
6253 si_shader_dump_disassembly(&shader->epilog->binary,
6254 debug, "epilog", file);
6255 fprintf(file, "\n");
6256 }
6257
6258 si_shader_dump_stats(sscreen, &shader->config,
6259 shader->selector ? shader->selector->info.num_inputs : 0,
6260 si_get_shader_binary_size(shader), debug, processor,
6261 file);
6262 }
6263
6264 int si_compile_llvm(struct si_screen *sscreen,
6265 struct radeon_shader_binary *binary,
6266 struct si_shader_config *conf,
6267 LLVMTargetMachineRef tm,
6268 LLVMModuleRef mod,
6269 struct pipe_debug_callback *debug,
6270 unsigned processor,
6271 const char *name)
6272 {
6273 int r = 0;
6274 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6275
6276 if (r600_can_dump_shader(&sscreen->b, processor)) {
6277 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6278
6279 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6280 fprintf(stderr, "%s LLVM IR:\n\n", name);
6281 LLVMDumpModule(mod);
6282 fprintf(stderr, "\n");
6283 }
6284 }
6285
6286 if (sscreen->record_llvm_ir) {
6287 char *ir = LLVMPrintModuleToString(mod);
6288 binary->llvm_ir_string = strdup(ir);
6289 LLVMDisposeMessage(ir);
6290 }
6291
6292 if (!si_replace_shader(count, binary)) {
6293 r = radeon_llvm_compile(mod, binary, tm, debug);
6294 if (r)
6295 return r;
6296 }
6297
6298 si_shader_binary_read_config(binary, conf, 0);
6299
6300 /* Enable 64-bit and 16-bit denormals, because there is no performance
6301 * cost.
6302 *
6303 * If denormals are enabled, all floating-point output modifiers are
6304 * ignored.
6305 *
6306 * Don't enable denormals for 32-bit floats, because:
6307 * - Floating-point output modifiers would be ignored by the hw.
6308 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6309 * have to stop using those.
6310 * - SI & CI would be very slow.
6311 */
6312 conf->float_mode |= V_00B028_FP_64_DENORMS;
6313
6314 FREE(binary->config);
6315 FREE(binary->global_symbol_offsets);
6316 binary->config = NULL;
6317 binary->global_symbol_offsets = NULL;
6318
6319 /* Some shaders can't have rodata because their binaries can be
6320 * concatenated.
6321 */
6322 if (binary->rodata_size &&
6323 (processor == PIPE_SHADER_VERTEX ||
6324 processor == PIPE_SHADER_TESS_CTRL ||
6325 processor == PIPE_SHADER_TESS_EVAL ||
6326 processor == PIPE_SHADER_FRAGMENT)) {
6327 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6328 return -EINVAL;
6329 }
6330
6331 return r;
6332 }
6333
6334 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6335 {
6336 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6337 LLVMBuildRetVoid(ctx->radeon_bld.gallivm.builder);
6338 else
6339 LLVMBuildRet(ctx->radeon_bld.gallivm.builder, ret);
6340 }
6341
6342 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6343 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
6344 struct si_shader_context *ctx,
6345 struct si_shader *gs,
6346 struct pipe_debug_callback *debug)
6347 {
6348 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
6349 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
6350 struct lp_build_context *uint = &bld_base->uint_bld;
6351 struct si_shader_output_values *outputs;
6352 struct tgsi_shader_info *gsinfo = &gs->selector->info;
6353 LLVMValueRef args[9];
6354 int i, r;
6355
6356 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6357
6358 si_init_shader_ctx(ctx, sscreen, ctx->shader, ctx->tm);
6359 ctx->type = PIPE_SHADER_VERTEX;
6360 ctx->is_gs_copy_shader = true;
6361
6362 create_meta_data(ctx);
6363 create_function(ctx);
6364 preload_streamout_buffers(ctx);
6365 preload_ring_buffers(ctx);
6366
6367 args[0] = ctx->gsvs_ring[0];
6368 args[1] = lp_build_mul_imm(uint,
6369 LLVMGetParam(ctx->radeon_bld.main_fn,
6370 ctx->param_vertex_id),
6371 4);
6372 args[3] = uint->zero;
6373 args[4] = uint->one; /* OFFEN */
6374 args[5] = uint->zero; /* IDXEN */
6375 args[6] = uint->one; /* GLC */
6376 args[7] = uint->one; /* SLC */
6377 args[8] = uint->zero; /* TFE */
6378
6379 /* Fetch vertex data from GSVS ring */
6380 for (i = 0; i < gsinfo->num_outputs; ++i) {
6381 unsigned chan;
6382
6383 outputs[i].name = gsinfo->output_semantic_name[i];
6384 outputs[i].sid = gsinfo->output_semantic_index[i];
6385
6386 for (chan = 0; chan < 4; chan++) {
6387 args[2] = lp_build_const_int32(gallivm,
6388 (i * 4 + chan) *
6389 gs->selector->gs_max_out_vertices * 16 * 4);
6390
6391 outputs[i].values[chan] =
6392 LLVMBuildBitCast(gallivm->builder,
6393 lp_build_intrinsic(gallivm->builder,
6394 "llvm.SI.buffer.load.dword.i32.i32",
6395 ctx->i32, args, 9,
6396 LLVMReadOnlyAttribute),
6397 ctx->f32, "");
6398 }
6399 }
6400
6401 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6402
6403 LLVMBuildRetVoid(gallivm->builder);
6404
6405 /* Dump LLVM IR before any optimization passes */
6406 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6407 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6408 LLVMDumpModule(bld_base->base.gallivm->module);
6409
6410 radeon_llvm_finalize_module(&ctx->radeon_bld);
6411
6412 r = si_compile_llvm(sscreen, &ctx->shader->binary,
6413 &ctx->shader->config, ctx->tm,
6414 bld_base->base.gallivm->module,
6415 debug, PIPE_SHADER_GEOMETRY,
6416 "GS Copy Shader");
6417 if (!r) {
6418 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6419 fprintf(stderr, "GS Copy Shader:\n");
6420 si_shader_dump(sscreen, ctx->shader, debug,
6421 PIPE_SHADER_GEOMETRY, stderr);
6422 r = si_shader_binary_upload(sscreen, ctx->shader);
6423 }
6424
6425 radeon_llvm_dispose(&ctx->radeon_bld);
6426
6427 FREE(outputs);
6428 return r;
6429 }
6430
6431 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
6432 {
6433 int i;
6434
6435 fprintf(f, "SHADER KEY\n");
6436
6437 switch (shader) {
6438 case PIPE_SHADER_VERTEX:
6439 fprintf(f, " instance_divisors = {");
6440 for (i = 0; i < ARRAY_SIZE(key->vs.prolog.instance_divisors); i++)
6441 fprintf(f, !i ? "%u" : ", %u",
6442 key->vs.prolog.instance_divisors[i]);
6443 fprintf(f, "}\n");
6444 fprintf(f, " as_es = %u\n", key->vs.as_es);
6445 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
6446 fprintf(f, " export_prim_id = %u\n", key->vs.epilog.export_prim_id);
6447 break;
6448
6449 case PIPE_SHADER_TESS_CTRL:
6450 fprintf(f, " prim_mode = %u\n", key->tcs.epilog.prim_mode);
6451 break;
6452
6453 case PIPE_SHADER_TESS_EVAL:
6454 fprintf(f, " as_es = %u\n", key->tes.as_es);
6455 fprintf(f, " export_prim_id = %u\n", key->tes.epilog.export_prim_id);
6456 break;
6457
6458 case PIPE_SHADER_GEOMETRY:
6459 case PIPE_SHADER_COMPUTE:
6460 break;
6461
6462 case PIPE_SHADER_FRAGMENT:
6463 fprintf(f, " prolog.color_two_side = %u\n", key->ps.prolog.color_two_side);
6464 fprintf(f, " prolog.flatshade_colors = %u\n", key->ps.prolog.flatshade_colors);
6465 fprintf(f, " prolog.poly_stipple = %u\n", key->ps.prolog.poly_stipple);
6466 fprintf(f, " prolog.force_persp_sample_interp = %u\n", key->ps.prolog.force_persp_sample_interp);
6467 fprintf(f, " prolog.force_linear_sample_interp = %u\n", key->ps.prolog.force_linear_sample_interp);
6468 fprintf(f, " prolog.force_persp_center_interp = %u\n", key->ps.prolog.force_persp_center_interp);
6469 fprintf(f, " prolog.force_linear_center_interp = %u\n", key->ps.prolog.force_linear_center_interp);
6470 fprintf(f, " prolog.bc_optimize_for_persp = %u\n", key->ps.prolog.bc_optimize_for_persp);
6471 fprintf(f, " prolog.bc_optimize_for_linear = %u\n", key->ps.prolog.bc_optimize_for_linear);
6472 fprintf(f, " epilog.spi_shader_col_format = 0x%x\n", key->ps.epilog.spi_shader_col_format);
6473 fprintf(f, " epilog.color_is_int8 = 0x%X\n", key->ps.epilog.color_is_int8);
6474 fprintf(f, " epilog.last_cbuf = %u\n", key->ps.epilog.last_cbuf);
6475 fprintf(f, " epilog.alpha_func = %u\n", key->ps.epilog.alpha_func);
6476 fprintf(f, " epilog.alpha_to_one = %u\n", key->ps.epilog.alpha_to_one);
6477 fprintf(f, " epilog.poly_line_smoothing = %u\n", key->ps.epilog.poly_line_smoothing);
6478 fprintf(f, " epilog.clamp_color = %u\n", key->ps.epilog.clamp_color);
6479 break;
6480
6481 default:
6482 assert(0);
6483 }
6484 }
6485
6486 static void si_init_shader_ctx(struct si_shader_context *ctx,
6487 struct si_screen *sscreen,
6488 struct si_shader *shader,
6489 LLVMTargetMachineRef tm)
6490 {
6491 struct lp_build_tgsi_context *bld_base;
6492 struct lp_build_tgsi_action tmpl = {};
6493
6494 memset(ctx, 0, sizeof(*ctx));
6495 radeon_llvm_context_init(&ctx->radeon_bld, "amdgcn--");
6496 ctx->tm = tm;
6497 ctx->screen = sscreen;
6498 if (shader && shader->selector)
6499 ctx->type = shader->selector->info.processor;
6500 else
6501 ctx->type = -1;
6502 ctx->shader = shader;
6503
6504 ctx->voidt = LLVMVoidTypeInContext(ctx->radeon_bld.gallivm.context);
6505 ctx->i1 = LLVMInt1TypeInContext(ctx->radeon_bld.gallivm.context);
6506 ctx->i8 = LLVMInt8TypeInContext(ctx->radeon_bld.gallivm.context);
6507 ctx->i32 = LLVMInt32TypeInContext(ctx->radeon_bld.gallivm.context);
6508 ctx->i64 = LLVMInt64TypeInContext(ctx->radeon_bld.gallivm.context);
6509 ctx->i128 = LLVMIntTypeInContext(ctx->radeon_bld.gallivm.context, 128);
6510 ctx->f32 = LLVMFloatTypeInContext(ctx->radeon_bld.gallivm.context);
6511 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
6512 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
6513 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
6514 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
6515 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
6516
6517 bld_base = &ctx->radeon_bld.soa.bld_base;
6518 if (shader && shader->selector)
6519 bld_base->info = &shader->selector->info;
6520 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6521
6522 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6523 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6524 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6525
6526 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6527 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6528 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6529 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6530 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6531 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6532 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6533 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6534 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6535 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6536 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6537 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6538 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6539 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6540
6541 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6542 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6543 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6544 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6545 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6546 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6547
6548 tmpl.fetch_args = atomic_fetch_args;
6549 tmpl.emit = atomic_emit;
6550 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6551 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6552 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6553 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6554 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6555 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6556 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6557 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6558 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6559 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6560 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6561 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6562 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6563 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6564 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6565 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6566 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6567 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6568 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6569 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6570
6571 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6572
6573 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6574 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6575 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6576 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6577
6578 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6579 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6580 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6581
6582 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
6583 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
6584 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
6585 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
6586 }
6587
6588 int si_compile_tgsi_shader(struct si_screen *sscreen,
6589 LLVMTargetMachineRef tm,
6590 struct si_shader *shader,
6591 bool is_monolithic,
6592 struct pipe_debug_callback *debug)
6593 {
6594 struct si_shader_selector *sel = shader->selector;
6595 struct si_shader_context ctx;
6596 struct lp_build_tgsi_context *bld_base;
6597 LLVMModuleRef mod;
6598 int r = 0;
6599
6600 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6601 * conversion fails. */
6602 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
6603 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
6604 if (is_monolithic)
6605 si_dump_shader_key(sel->type, &shader->key, stderr);
6606 tgsi_dump(sel->tokens, 0);
6607 si_dump_streamout(&sel->so);
6608 }
6609
6610 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6611 ctx.is_monolithic = is_monolithic;
6612
6613 shader->info.uses_instanceid = sel->info.uses_instanceid;
6614
6615 bld_base = &ctx.radeon_bld.soa.bld_base;
6616 ctx.radeon_bld.load_system_value = declare_system_value;
6617
6618 switch (ctx.type) {
6619 case PIPE_SHADER_VERTEX:
6620 ctx.radeon_bld.load_input = declare_input_vs;
6621 if (shader->key.vs.as_ls)
6622 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6623 else if (shader->key.vs.as_es)
6624 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6625 else
6626 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6627 break;
6628 case PIPE_SHADER_TESS_CTRL:
6629 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6630 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6631 bld_base->emit_store = store_output_tcs;
6632 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6633 break;
6634 case PIPE_SHADER_TESS_EVAL:
6635 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6636 if (shader->key.tes.as_es)
6637 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6638 else
6639 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6640 break;
6641 case PIPE_SHADER_GEOMETRY:
6642 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6643 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6644 break;
6645 case PIPE_SHADER_FRAGMENT:
6646 ctx.radeon_bld.load_input = declare_input_fs;
6647 if (is_monolithic)
6648 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
6649 else
6650 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6651 break;
6652 case PIPE_SHADER_COMPUTE:
6653 ctx.radeon_bld.declare_memory_region = declare_compute_memory;
6654 break;
6655 default:
6656 assert(!"Unsupported shader type");
6657 return -1;
6658 }
6659
6660 create_meta_data(&ctx);
6661 create_function(&ctx);
6662 preload_constants(&ctx);
6663 preload_shader_buffers(&ctx);
6664 preload_samplers(&ctx);
6665 preload_images(&ctx);
6666 preload_streamout_buffers(&ctx);
6667 preload_ring_buffers(&ctx);
6668
6669 if (ctx.is_monolithic && sel->type == PIPE_SHADER_FRAGMENT &&
6670 shader->key.ps.prolog.poly_stipple) {
6671 LLVMValueRef list = LLVMGetParam(ctx.radeon_bld.main_fn,
6672 SI_PARAM_RW_BUFFERS);
6673 si_llvm_emit_polygon_stipple(&ctx, list,
6674 SI_PARAM_POS_FIXED_PT);
6675 }
6676
6677 if (ctx.type == PIPE_SHADER_GEOMETRY) {
6678 int i;
6679 for (i = 0; i < 4; i++) {
6680 ctx.gs_next_vertex[i] =
6681 lp_build_alloca(bld_base->base.gallivm,
6682 ctx.i32, "");
6683 }
6684 }
6685
6686 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6687 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6688 goto out;
6689 }
6690
6691 si_llvm_build_ret(&ctx, ctx.return_value);
6692 mod = bld_base->base.gallivm->module;
6693
6694 /* Dump LLVM IR before any optimization passes */
6695 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6696 r600_can_dump_shader(&sscreen->b, ctx.type))
6697 LLVMDumpModule(mod);
6698
6699 radeon_llvm_finalize_module(&ctx.radeon_bld);
6700
6701 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6702 mod, debug, ctx.type, "TGSI shader");
6703 if (r) {
6704 fprintf(stderr, "LLVM failed to compile shader\n");
6705 goto out;
6706 }
6707
6708 radeon_llvm_dispose(&ctx.radeon_bld);
6709
6710 /* Add the scratch offset to input SGPRs. */
6711 if (shader->config.scratch_bytes_per_wave)
6712 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6713
6714 /* Calculate the number of fragment input VGPRs. */
6715 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6716 shader->info.num_input_vgprs = 0;
6717 shader->info.face_vgpr_index = -1;
6718
6719 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6720 shader->info.num_input_vgprs += 2;
6721 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6722 shader->info.num_input_vgprs += 2;
6723 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6724 shader->info.num_input_vgprs += 2;
6725 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6726 shader->info.num_input_vgprs += 3;
6727 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6728 shader->info.num_input_vgprs += 2;
6729 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6730 shader->info.num_input_vgprs += 2;
6731 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6732 shader->info.num_input_vgprs += 2;
6733 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6734 shader->info.num_input_vgprs += 1;
6735 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6736 shader->info.num_input_vgprs += 1;
6737 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6738 shader->info.num_input_vgprs += 1;
6739 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6740 shader->info.num_input_vgprs += 1;
6741 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6742 shader->info.num_input_vgprs += 1;
6743 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6744 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6745 shader->info.num_input_vgprs += 1;
6746 }
6747 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
6748 shader->info.num_input_vgprs += 1;
6749 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6750 shader->info.num_input_vgprs += 1;
6751 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6752 shader->info.num_input_vgprs += 1;
6753 }
6754
6755 if (ctx.type == PIPE_SHADER_GEOMETRY) {
6756 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
6757 shader->gs_copy_shader->selector = shader->selector;
6758 ctx.shader = shader->gs_copy_shader;
6759 if ((r = si_generate_gs_copy_shader(sscreen, &ctx,
6760 shader, debug))) {
6761 free(shader->gs_copy_shader);
6762 shader->gs_copy_shader = NULL;
6763 goto out;
6764 }
6765 }
6766
6767 out:
6768 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
6769 FREE(ctx.constants[i]);
6770 return r;
6771 }
6772
6773 /**
6774 * Create, compile and return a shader part (prolog or epilog).
6775 *
6776 * \param sscreen screen
6777 * \param list list of shader parts of the same category
6778 * \param key shader part key
6779 * \param tm LLVM target machine
6780 * \param debug debug callback
6781 * \param compile the callback responsible for compilation
6782 * \return non-NULL on success
6783 */
6784 static struct si_shader_part *
6785 si_get_shader_part(struct si_screen *sscreen,
6786 struct si_shader_part **list,
6787 union si_shader_part_key *key,
6788 LLVMTargetMachineRef tm,
6789 struct pipe_debug_callback *debug,
6790 bool (*compile)(struct si_screen *,
6791 LLVMTargetMachineRef,
6792 struct pipe_debug_callback *,
6793 struct si_shader_part *))
6794 {
6795 struct si_shader_part *result;
6796
6797 pipe_mutex_lock(sscreen->shader_parts_mutex);
6798
6799 /* Find existing. */
6800 for (result = *list; result; result = result->next) {
6801 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6802 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6803 return result;
6804 }
6805 }
6806
6807 /* Compile a new one. */
6808 result = CALLOC_STRUCT(si_shader_part);
6809 result->key = *key;
6810 if (!compile(sscreen, tm, debug, result)) {
6811 FREE(result);
6812 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6813 return NULL;
6814 }
6815
6816 result->next = *list;
6817 *list = result;
6818 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6819 return result;
6820 }
6821
6822 /**
6823 * Create a vertex shader prolog.
6824 *
6825 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6826 * All inputs are returned unmodified. The vertex load indices are
6827 * stored after them, which will used by the API VS for fetching inputs.
6828 *
6829 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6830 * input_v0,
6831 * input_v1,
6832 * input_v2,
6833 * input_v3,
6834 * (VertexID + BaseVertex),
6835 * (InstanceID + StartInstance),
6836 * (InstanceID / 2 + StartInstance)
6837 */
6838 static bool si_compile_vs_prolog(struct si_screen *sscreen,
6839 LLVMTargetMachineRef tm,
6840 struct pipe_debug_callback *debug,
6841 struct si_shader_part *out)
6842 {
6843 union si_shader_part_key *key = &out->key;
6844 struct si_shader shader = {};
6845 struct si_shader_context ctx;
6846 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6847 LLVMTypeRef *params, *returns;
6848 LLVMValueRef ret, func;
6849 int last_sgpr, num_params, num_returns, i;
6850 bool status = true;
6851
6852 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6853 ctx.type = PIPE_SHADER_VERTEX;
6854 ctx.param_vertex_id = key->vs_prolog.num_input_sgprs;
6855 ctx.param_instance_id = key->vs_prolog.num_input_sgprs + 3;
6856
6857 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6858 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
6859 sizeof(LLVMTypeRef));
6860 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
6861 key->vs_prolog.last_input + 1) *
6862 sizeof(LLVMTypeRef));
6863 num_params = 0;
6864 num_returns = 0;
6865
6866 /* Declare input and output SGPRs. */
6867 num_params = 0;
6868 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6869 params[num_params++] = ctx.i32;
6870 returns[num_returns++] = ctx.i32;
6871 }
6872 last_sgpr = num_params - 1;
6873
6874 /* 4 preloaded VGPRs (outputs must be floats) */
6875 for (i = 0; i < 4; i++) {
6876 params[num_params++] = ctx.i32;
6877 returns[num_returns++] = ctx.f32;
6878 }
6879
6880 /* Vertex load indices. */
6881 for (i = 0; i <= key->vs_prolog.last_input; i++)
6882 returns[num_returns++] = ctx.f32;
6883
6884 /* Create the function. */
6885 si_create_function(&ctx, returns, num_returns, params,
6886 num_params, -1, last_sgpr);
6887 func = ctx.radeon_bld.main_fn;
6888
6889 /* Copy inputs to outputs. This should be no-op, as the registers match,
6890 * but it will prevent the compiler from overwriting them unintentionally.
6891 */
6892 ret = ctx.return_value;
6893 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6894 LLVMValueRef p = LLVMGetParam(func, i);
6895 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6896 }
6897 for (i = num_params - 4; i < num_params; i++) {
6898 LLVMValueRef p = LLVMGetParam(func, i);
6899 p = LLVMBuildBitCast(gallivm->builder, p, ctx.f32, "");
6900 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6901 }
6902
6903 /* Compute vertex load indices from instance divisors. */
6904 for (i = 0; i <= key->vs_prolog.last_input; i++) {
6905 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
6906 LLVMValueRef index;
6907
6908 if (divisor) {
6909 /* InstanceID / Divisor + StartInstance */
6910 index = get_instance_index_for_fetch(&ctx.radeon_bld,
6911 SI_SGPR_START_INSTANCE,
6912 divisor);
6913 } else {
6914 /* VertexID + BaseVertex */
6915 index = LLVMBuildAdd(gallivm->builder,
6916 LLVMGetParam(func, ctx.param_vertex_id),
6917 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
6918 }
6919
6920 index = LLVMBuildBitCast(gallivm->builder, index, ctx.f32, "");
6921 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
6922 num_params++, "");
6923 }
6924
6925 /* Compile. */
6926 si_llvm_build_ret(&ctx, ret);
6927 radeon_llvm_finalize_module(&ctx.radeon_bld);
6928
6929 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6930 gallivm->module, debug, ctx.type,
6931 "Vertex Shader Prolog"))
6932 status = false;
6933
6934 radeon_llvm_dispose(&ctx.radeon_bld);
6935 return status;
6936 }
6937
6938 /**
6939 * Compile the vertex shader epilog. This is also used by the tessellation
6940 * evaluation shader compiled as VS.
6941 *
6942 * The input is PrimitiveID.
6943 *
6944 * If PrimitiveID is required by the pixel shader, export it.
6945 * Otherwise, do nothing.
6946 */
6947 static bool si_compile_vs_epilog(struct si_screen *sscreen,
6948 LLVMTargetMachineRef tm,
6949 struct pipe_debug_callback *debug,
6950 struct si_shader_part *out)
6951 {
6952 union si_shader_part_key *key = &out->key;
6953 struct si_shader_context ctx;
6954 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6955 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
6956 LLVMTypeRef params[5];
6957 int num_params, i;
6958 bool status = true;
6959
6960 si_init_shader_ctx(&ctx, sscreen, NULL, tm);
6961 ctx.type = PIPE_SHADER_VERTEX;
6962
6963 /* Declare input VGPRs. */
6964 num_params = key->vs_epilog.states.export_prim_id ?
6965 (VS_EPILOG_PRIMID_LOC + 1) : 0;
6966 assert(num_params <= ARRAY_SIZE(params));
6967
6968 for (i = 0; i < num_params; i++)
6969 params[i] = ctx.f32;
6970
6971 /* Create the function. */
6972 si_create_function(&ctx, NULL, 0, params, num_params,
6973 -1, -1);
6974
6975 /* Emit exports. */
6976 if (key->vs_epilog.states.export_prim_id) {
6977 struct lp_build_context *base = &bld_base->base;
6978 struct lp_build_context *uint = &bld_base->uint_bld;
6979 LLVMValueRef args[9];
6980
6981 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
6982 args[1] = uint->zero; /* whether the EXEC mask is valid */
6983 args[2] = uint->zero; /* DONE bit */
6984 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
6985 key->vs_epilog.prim_id_param_offset);
6986 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
6987 args[5] = LLVMGetParam(ctx.radeon_bld.main_fn,
6988 VS_EPILOG_PRIMID_LOC); /* X */
6989 args[6] = uint->undef; /* Y */
6990 args[7] = uint->undef; /* Z */
6991 args[8] = uint->undef; /* W */
6992
6993 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
6994 LLVMVoidTypeInContext(base->gallivm->context),
6995 args, 9, 0);
6996 }
6997
6998 /* Compile. */
6999 LLVMBuildRetVoid(gallivm->builder);
7000 radeon_llvm_finalize_module(&ctx.radeon_bld);
7001
7002 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7003 gallivm->module, debug, ctx.type,
7004 "Vertex Shader Epilog"))
7005 status = false;
7006
7007 radeon_llvm_dispose(&ctx.radeon_bld);
7008 return status;
7009 }
7010
7011 /**
7012 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7013 */
7014 static bool si_get_vs_epilog(struct si_screen *sscreen,
7015 LLVMTargetMachineRef tm,
7016 struct si_shader *shader,
7017 struct pipe_debug_callback *debug,
7018 struct si_vs_epilog_bits *states)
7019 {
7020 union si_shader_part_key epilog_key;
7021
7022 memset(&epilog_key, 0, sizeof(epilog_key));
7023 epilog_key.vs_epilog.states = *states;
7024
7025 /* Set up the PrimitiveID output. */
7026 if (shader->key.vs.epilog.export_prim_id) {
7027 unsigned index = shader->selector->info.num_outputs;
7028 unsigned offset = shader->info.nr_param_exports++;
7029
7030 epilog_key.vs_epilog.prim_id_param_offset = offset;
7031 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
7032 shader->info.vs_output_param_offset[index] = offset;
7033 }
7034
7035 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
7036 &epilog_key, tm, debug,
7037 si_compile_vs_epilog);
7038 return shader->epilog != NULL;
7039 }
7040
7041 /**
7042 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7043 */
7044 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7045 LLVMTargetMachineRef tm,
7046 struct si_shader *shader,
7047 struct pipe_debug_callback *debug)
7048 {
7049 struct tgsi_shader_info *info = &shader->selector->info;
7050 union si_shader_part_key prolog_key;
7051 unsigned i;
7052
7053 /* Get the prolog. */
7054 memset(&prolog_key, 0, sizeof(prolog_key));
7055 prolog_key.vs_prolog.states = shader->key.vs.prolog;
7056 prolog_key.vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7057 prolog_key.vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
7058
7059 /* The prolog is a no-op if there are no inputs. */
7060 if (info->num_inputs) {
7061 shader->prolog =
7062 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7063 &prolog_key, tm, debug,
7064 si_compile_vs_prolog);
7065 if (!shader->prolog)
7066 return false;
7067 }
7068
7069 /* Get the epilog. */
7070 if (!shader->key.vs.as_es && !shader->key.vs.as_ls &&
7071 !si_get_vs_epilog(sscreen, tm, shader, debug,
7072 &shader->key.vs.epilog))
7073 return false;
7074
7075 /* Set the instanceID flag. */
7076 for (i = 0; i < info->num_inputs; i++)
7077 if (prolog_key.vs_prolog.states.instance_divisors[i])
7078 shader->info.uses_instanceid = true;
7079
7080 return true;
7081 }
7082
7083 /**
7084 * Select and compile (or reuse) TES parts (epilog).
7085 */
7086 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
7087 LLVMTargetMachineRef tm,
7088 struct si_shader *shader,
7089 struct pipe_debug_callback *debug)
7090 {
7091 if (shader->key.tes.as_es)
7092 return true;
7093
7094 /* TES compiled as VS. */
7095 return si_get_vs_epilog(sscreen, tm, shader, debug,
7096 &shader->key.tes.epilog);
7097 }
7098
7099 /**
7100 * Compile the TCS epilog. This writes tesselation factors to memory based on
7101 * the output primitive type of the tesselator (determined by TES).
7102 */
7103 static bool si_compile_tcs_epilog(struct si_screen *sscreen,
7104 LLVMTargetMachineRef tm,
7105 struct pipe_debug_callback *debug,
7106 struct si_shader_part *out)
7107 {
7108 union si_shader_part_key *key = &out->key;
7109 struct si_shader shader = {};
7110 struct si_shader_context ctx;
7111 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7112 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
7113 LLVMTypeRef params[16];
7114 LLVMValueRef func;
7115 int last_array_pointer, last_sgpr, num_params;
7116 bool status = true;
7117
7118 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7119 ctx.type = PIPE_SHADER_TESS_CTRL;
7120 shader.key.tcs.epilog = key->tcs_epilog.states;
7121
7122 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
7123 params[SI_PARAM_RW_BUFFERS] = const_array(ctx.v16i8, SI_NUM_RW_BUFFERS);
7124 last_array_pointer = SI_PARAM_RW_BUFFERS;
7125 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
7126 params[SI_PARAM_SAMPLERS] = ctx.i64;
7127 params[SI_PARAM_IMAGES] = ctx.i64;
7128 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
7129 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx.i32;
7130 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx.i32;
7131 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx.i32;
7132 params[SI_PARAM_TCS_IN_LAYOUT] = ctx.i32;
7133 params[ctx.param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx.i32;
7134 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx.i32;
7135 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
7136 num_params = last_sgpr + 1;
7137
7138 params[num_params++] = ctx.i32; /* patch index within the wave (REL_PATCH_ID) */
7139 params[num_params++] = ctx.i32; /* invocation ID within the patch */
7140 params[num_params++] = ctx.i32; /* LDS offset where tess factors should be loaded from */
7141
7142 /* Create the function. */
7143 si_create_function(&ctx, NULL, 0, params, num_params,
7144 last_array_pointer, last_sgpr);
7145 declare_tess_lds(&ctx);
7146 func = ctx.radeon_bld.main_fn;
7147
7148 si_write_tess_factors(bld_base,
7149 LLVMGetParam(func, last_sgpr + 1),
7150 LLVMGetParam(func, last_sgpr + 2),
7151 LLVMGetParam(func, last_sgpr + 3));
7152
7153 /* Compile. */
7154 LLVMBuildRetVoid(gallivm->builder);
7155 radeon_llvm_finalize_module(&ctx.radeon_bld);
7156
7157 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7158 gallivm->module, debug, ctx.type,
7159 "Tessellation Control Shader Epilog"))
7160 status = false;
7161
7162 radeon_llvm_dispose(&ctx.radeon_bld);
7163 return status;
7164 }
7165
7166 /**
7167 * Select and compile (or reuse) TCS parts (epilog).
7168 */
7169 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7170 LLVMTargetMachineRef tm,
7171 struct si_shader *shader,
7172 struct pipe_debug_callback *debug)
7173 {
7174 union si_shader_part_key epilog_key;
7175
7176 /* Get the epilog. */
7177 memset(&epilog_key, 0, sizeof(epilog_key));
7178 epilog_key.tcs_epilog.states = shader->key.tcs.epilog;
7179
7180 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7181 &epilog_key, tm, debug,
7182 si_compile_tcs_epilog);
7183 return shader->epilog != NULL;
7184 }
7185
7186 /**
7187 * Compile the pixel shader prolog. This handles:
7188 * - two-side color selection and interpolation
7189 * - overriding interpolation parameters for the API PS
7190 * - polygon stippling
7191 *
7192 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7193 * overriden by other states. (e.g. per-sample interpolation)
7194 * Interpolated colors are stored after the preloaded VGPRs.
7195 */
7196 static bool si_compile_ps_prolog(struct si_screen *sscreen,
7197 LLVMTargetMachineRef tm,
7198 struct pipe_debug_callback *debug,
7199 struct si_shader_part *out)
7200 {
7201 union si_shader_part_key *key = &out->key;
7202 struct si_shader shader = {};
7203 struct si_shader_context ctx;
7204 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7205 LLVMTypeRef *params;
7206 LLVMValueRef ret, func;
7207 int last_sgpr, num_params, num_returns, i, num_color_channels;
7208 bool status = true;
7209
7210 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7211 ctx.type = PIPE_SHADER_FRAGMENT;
7212 shader.key.ps.prolog = key->ps_prolog.states;
7213
7214 /* Number of inputs + 8 color elements. */
7215 params = alloca((key->ps_prolog.num_input_sgprs +
7216 key->ps_prolog.num_input_vgprs + 8) *
7217 sizeof(LLVMTypeRef));
7218
7219 /* Declare inputs. */
7220 num_params = 0;
7221 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7222 params[num_params++] = ctx.i32;
7223 last_sgpr = num_params - 1;
7224
7225 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7226 params[num_params++] = ctx.f32;
7227
7228 /* Declare outputs (same as inputs + add colors if needed) */
7229 num_returns = num_params;
7230 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7231 for (i = 0; i < num_color_channels; i++)
7232 params[num_returns++] = ctx.f32;
7233
7234 /* Create the function. */
7235 si_create_function(&ctx, params, num_returns, params,
7236 num_params, -1, last_sgpr);
7237 func = ctx.radeon_bld.main_fn;
7238
7239 /* Copy inputs to outputs. This should be no-op, as the registers match,
7240 * but it will prevent the compiler from overwriting them unintentionally.
7241 */
7242 ret = ctx.return_value;
7243 for (i = 0; i < num_params; i++) {
7244 LLVMValueRef p = LLVMGetParam(func, i);
7245 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7246 }
7247
7248 /* Polygon stippling. */
7249 if (key->ps_prolog.states.poly_stipple) {
7250 /* POS_FIXED_PT is always last. */
7251 unsigned pos = key->ps_prolog.num_input_sgprs +
7252 key->ps_prolog.num_input_vgprs - 1;
7253 LLVMValueRef ptr[2], list;
7254
7255 /* Get the pointer to rw buffers. */
7256 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
7257 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
7258 list = lp_build_gather_values(gallivm, ptr, 2);
7259 list = LLVMBuildBitCast(gallivm->builder, list, ctx.i64, "");
7260 list = LLVMBuildIntToPtr(gallivm->builder, list,
7261 const_array(ctx.v16i8, SI_NUM_RW_BUFFERS), "");
7262
7263 si_llvm_emit_polygon_stipple(&ctx, list, pos);
7264 }
7265
7266 if (key->ps_prolog.states.bc_optimize_for_persp ||
7267 key->ps_prolog.states.bc_optimize_for_linear) {
7268 unsigned i, base = key->ps_prolog.num_input_sgprs;
7269 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7270
7271 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7272 * The hw doesn't compute CENTROID if the whole wave only
7273 * contains fully-covered quads.
7274 *
7275 * PRIM_MASK is after user SGPRs.
7276 */
7277 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7278 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
7279 LLVMConstInt(ctx.i32, 31, 0), "");
7280 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
7281 ctx.i1, "");
7282
7283 if (key->ps_prolog.states.bc_optimize_for_persp) {
7284 /* Read PERSP_CENTER. */
7285 for (i = 0; i < 2; i++)
7286 center[i] = LLVMGetParam(func, base + 2 + i);
7287 /* Read PERSP_CENTROID. */
7288 for (i = 0; i < 2; i++)
7289 centroid[i] = LLVMGetParam(func, base + 4 + i);
7290 /* Select PERSP_CENTROID. */
7291 for (i = 0; i < 2; i++) {
7292 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7293 center[i], centroid[i], "");
7294 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7295 tmp, base + 4 + i, "");
7296 }
7297 }
7298 if (key->ps_prolog.states.bc_optimize_for_linear) {
7299 /* Read LINEAR_CENTER. */
7300 for (i = 0; i < 2; i++)
7301 center[i] = LLVMGetParam(func, base + 8 + i);
7302 /* Read LINEAR_CENTROID. */
7303 for (i = 0; i < 2; i++)
7304 centroid[i] = LLVMGetParam(func, base + 10 + i);
7305 /* Select LINEAR_CENTROID. */
7306 for (i = 0; i < 2; i++) {
7307 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7308 center[i], centroid[i], "");
7309 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7310 tmp, base + 10 + i, "");
7311 }
7312 }
7313 }
7314
7315 /* Interpolate colors. */
7316 for (i = 0; i < 2; i++) {
7317 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7318 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7319 key->ps_prolog.face_vgpr_index;
7320 LLVMValueRef interp[2], color[4];
7321 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7322
7323 if (!writemask)
7324 continue;
7325
7326 /* If the interpolation qualifier is not CONSTANT (-1). */
7327 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7328 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7329 key->ps_prolog.color_interp_vgpr_index[i];
7330
7331 /* Get the (i,j) updated by bc_optimize handling. */
7332 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
7333 interp_vgpr, "");
7334 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
7335 interp_vgpr + 1, "");
7336 interp_ij = lp_build_gather_values(gallivm, interp, 2);
7337 interp_ij = LLVMBuildBitCast(gallivm->builder, interp_ij,
7338 ctx.v2i32, "");
7339 }
7340
7341 /* Use the absolute location of the input. */
7342 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7343
7344 if (key->ps_prolog.states.color_two_side) {
7345 face = LLVMGetParam(func, face_vgpr);
7346 face = LLVMBuildBitCast(gallivm->builder, face, ctx.i32, "");
7347 }
7348
7349 interp_fs_input(&ctx,
7350 key->ps_prolog.color_attr_index[i],
7351 TGSI_SEMANTIC_COLOR, i,
7352 key->ps_prolog.num_interp_inputs,
7353 key->ps_prolog.colors_read, interp_ij,
7354 prim_mask, face, color);
7355
7356 while (writemask) {
7357 unsigned chan = u_bit_scan(&writemask);
7358 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
7359 num_params++, "");
7360 }
7361 }
7362
7363 /* Force per-sample interpolation. */
7364 if (key->ps_prolog.states.force_persp_sample_interp) {
7365 unsigned i, base = key->ps_prolog.num_input_sgprs;
7366 LLVMValueRef persp_sample[2];
7367
7368 /* Read PERSP_SAMPLE. */
7369 for (i = 0; i < 2; i++)
7370 persp_sample[i] = LLVMGetParam(func, base + i);
7371 /* Overwrite PERSP_CENTER. */
7372 for (i = 0; i < 2; i++)
7373 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7374 persp_sample[i], base + 2 + i, "");
7375 /* Overwrite PERSP_CENTROID. */
7376 for (i = 0; i < 2; i++)
7377 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7378 persp_sample[i], base + 4 + i, "");
7379 }
7380 if (key->ps_prolog.states.force_linear_sample_interp) {
7381 unsigned i, base = key->ps_prolog.num_input_sgprs;
7382 LLVMValueRef linear_sample[2];
7383
7384 /* Read LINEAR_SAMPLE. */
7385 for (i = 0; i < 2; i++)
7386 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7387 /* Overwrite LINEAR_CENTER. */
7388 for (i = 0; i < 2; i++)
7389 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7390 linear_sample[i], base + 8 + i, "");
7391 /* Overwrite LINEAR_CENTROID. */
7392 for (i = 0; i < 2; i++)
7393 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7394 linear_sample[i], base + 10 + i, "");
7395 }
7396
7397 /* Force center interpolation. */
7398 if (key->ps_prolog.states.force_persp_center_interp) {
7399 unsigned i, base = key->ps_prolog.num_input_sgprs;
7400 LLVMValueRef persp_center[2];
7401
7402 /* Read PERSP_CENTER. */
7403 for (i = 0; i < 2; i++)
7404 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7405 /* Overwrite PERSP_SAMPLE. */
7406 for (i = 0; i < 2; i++)
7407 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7408 persp_center[i], base + i, "");
7409 /* Overwrite PERSP_CENTROID. */
7410 for (i = 0; i < 2; i++)
7411 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7412 persp_center[i], base + 4 + i, "");
7413 }
7414 if (key->ps_prolog.states.force_linear_center_interp) {
7415 unsigned i, base = key->ps_prolog.num_input_sgprs;
7416 LLVMValueRef linear_center[2];
7417
7418 /* Read LINEAR_CENTER. */
7419 for (i = 0; i < 2; i++)
7420 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7421 /* Overwrite LINEAR_SAMPLE. */
7422 for (i = 0; i < 2; i++)
7423 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7424 linear_center[i], base + 6 + i, "");
7425 /* Overwrite LINEAR_CENTROID. */
7426 for (i = 0; i < 2; i++)
7427 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7428 linear_center[i], base + 10 + i, "");
7429 }
7430
7431 /* Tell LLVM to insert WQM instruction sequence when needed. */
7432 if (key->ps_prolog.wqm) {
7433 LLVMAddTargetDependentFunctionAttr(func,
7434 "amdgpu-ps-wqm-outputs", "");
7435 }
7436
7437 /* Compile. */
7438 si_llvm_build_ret(&ctx, ret);
7439 radeon_llvm_finalize_module(&ctx.radeon_bld);
7440
7441 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7442 gallivm->module, debug, ctx.type,
7443 "Fragment Shader Prolog"))
7444 status = false;
7445
7446 radeon_llvm_dispose(&ctx.radeon_bld);
7447 return status;
7448 }
7449
7450 /**
7451 * Compile the pixel shader epilog. This handles everything that must be
7452 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7453 */
7454 static bool si_compile_ps_epilog(struct si_screen *sscreen,
7455 LLVMTargetMachineRef tm,
7456 struct pipe_debug_callback *debug,
7457 struct si_shader_part *out)
7458 {
7459 union si_shader_part_key *key = &out->key;
7460 struct si_shader shader = {};
7461 struct si_shader_context ctx;
7462 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7463 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
7464 LLVMTypeRef params[16+8*4+3];
7465 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7466 int last_array_pointer, last_sgpr, num_params, i;
7467 bool status = true;
7468
7469 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7470 ctx.type = PIPE_SHADER_FRAGMENT;
7471 shader.key.ps.epilog = key->ps_epilog.states;
7472
7473 /* Declare input SGPRs. */
7474 params[SI_PARAM_RW_BUFFERS] = ctx.i64;
7475 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
7476 params[SI_PARAM_SAMPLERS] = ctx.i64;
7477 params[SI_PARAM_IMAGES] = ctx.i64;
7478 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
7479 params[SI_PARAM_ALPHA_REF] = ctx.f32;
7480 last_array_pointer = -1;
7481 last_sgpr = SI_PARAM_ALPHA_REF;
7482
7483 /* Declare input VGPRs. */
7484 num_params = (last_sgpr + 1) +
7485 util_bitcount(key->ps_epilog.colors_written) * 4 +
7486 key->ps_epilog.writes_z +
7487 key->ps_epilog.writes_stencil +
7488 key->ps_epilog.writes_samplemask;
7489
7490 num_params = MAX2(num_params,
7491 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7492
7493 assert(num_params <= ARRAY_SIZE(params));
7494
7495 for (i = last_sgpr + 1; i < num_params; i++)
7496 params[i] = ctx.f32;
7497
7498 /* Create the function. */
7499 si_create_function(&ctx, NULL, 0, params, num_params,
7500 last_array_pointer, last_sgpr);
7501 /* Disable elimination of unused inputs. */
7502 radeon_llvm_add_attribute(ctx.radeon_bld.main_fn,
7503 "InitialPSInputAddr", 0xffffff);
7504
7505 /* Process colors. */
7506 unsigned vgpr = last_sgpr + 1;
7507 unsigned colors_written = key->ps_epilog.colors_written;
7508 int last_color_export = -1;
7509
7510 /* Find the last color export. */
7511 if (!key->ps_epilog.writes_z &&
7512 !key->ps_epilog.writes_stencil &&
7513 !key->ps_epilog.writes_samplemask) {
7514 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7515
7516 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7517 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7518 /* Just set this if any of the colorbuffers are enabled. */
7519 if (spi_format &
7520 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7521 last_color_export = 0;
7522 } else {
7523 for (i = 0; i < 8; i++)
7524 if (colors_written & (1 << i) &&
7525 (spi_format >> (i * 4)) & 0xf)
7526 last_color_export = i;
7527 }
7528 }
7529
7530 while (colors_written) {
7531 LLVMValueRef color[4];
7532 int mrt = u_bit_scan(&colors_written);
7533
7534 for (i = 0; i < 4; i++)
7535 color[i] = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7536
7537 si_export_mrt_color(bld_base, color, mrt,
7538 num_params - 1,
7539 mrt == last_color_export);
7540 }
7541
7542 /* Process depth, stencil, samplemask. */
7543 if (key->ps_epilog.writes_z)
7544 depth = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7545 if (key->ps_epilog.writes_stencil)
7546 stencil = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7547 if (key->ps_epilog.writes_samplemask)
7548 samplemask = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7549
7550 if (depth || stencil || samplemask)
7551 si_export_mrt_z(bld_base, depth, stencil, samplemask);
7552 else if (last_color_export == -1)
7553 si_export_null(bld_base);
7554
7555 /* Compile. */
7556 LLVMBuildRetVoid(gallivm->builder);
7557 radeon_llvm_finalize_module(&ctx.radeon_bld);
7558
7559 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7560 gallivm->module, debug, ctx.type,
7561 "Fragment Shader Epilog"))
7562 status = false;
7563
7564 radeon_llvm_dispose(&ctx.radeon_bld);
7565 return status;
7566 }
7567
7568 /**
7569 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7570 */
7571 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7572 LLVMTargetMachineRef tm,
7573 struct si_shader *shader,
7574 struct pipe_debug_callback *debug)
7575 {
7576 struct tgsi_shader_info *info = &shader->selector->info;
7577 union si_shader_part_key prolog_key;
7578 union si_shader_part_key epilog_key;
7579 unsigned i;
7580
7581 /* Get the prolog. */
7582 memset(&prolog_key, 0, sizeof(prolog_key));
7583 prolog_key.ps_prolog.states = shader->key.ps.prolog;
7584 prolog_key.ps_prolog.colors_read = info->colors_read;
7585 prolog_key.ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7586 prolog_key.ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
7587 prolog_key.ps_prolog.wqm = info->uses_derivatives &&
7588 (prolog_key.ps_prolog.colors_read ||
7589 prolog_key.ps_prolog.states.force_persp_sample_interp ||
7590 prolog_key.ps_prolog.states.force_linear_sample_interp ||
7591 prolog_key.ps_prolog.states.force_persp_center_interp ||
7592 prolog_key.ps_prolog.states.force_linear_center_interp ||
7593 prolog_key.ps_prolog.states.bc_optimize_for_persp ||
7594 prolog_key.ps_prolog.states.bc_optimize_for_linear);
7595
7596 if (info->colors_read) {
7597 unsigned *color = shader->selector->color_attr_index;
7598
7599 if (shader->key.ps.prolog.color_two_side) {
7600 /* BCOLORs are stored after the last input. */
7601 prolog_key.ps_prolog.num_interp_inputs = info->num_inputs;
7602 prolog_key.ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
7603 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
7604 }
7605
7606 for (i = 0; i < 2; i++) {
7607 unsigned interp = info->input_interpolate[color[i]];
7608 unsigned location = info->input_interpolate_loc[color[i]];
7609
7610 if (!(info->colors_read & (0xf << i*4)))
7611 continue;
7612
7613 prolog_key.ps_prolog.color_attr_index[i] = color[i];
7614
7615 if (shader->key.ps.prolog.flatshade_colors &&
7616 interp == TGSI_INTERPOLATE_COLOR)
7617 interp = TGSI_INTERPOLATE_CONSTANT;
7618
7619 switch (interp) {
7620 case TGSI_INTERPOLATE_CONSTANT:
7621 prolog_key.ps_prolog.color_interp_vgpr_index[i] = -1;
7622 break;
7623 case TGSI_INTERPOLATE_PERSPECTIVE:
7624 case TGSI_INTERPOLATE_COLOR:
7625 /* Force the interpolation location for colors here. */
7626 if (shader->key.ps.prolog.force_persp_sample_interp)
7627 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7628 if (shader->key.ps.prolog.force_persp_center_interp)
7629 location = TGSI_INTERPOLATE_LOC_CENTER;
7630
7631 switch (location) {
7632 case TGSI_INTERPOLATE_LOC_SAMPLE:
7633 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 0;
7634 shader->config.spi_ps_input_ena |=
7635 S_0286CC_PERSP_SAMPLE_ENA(1);
7636 break;
7637 case TGSI_INTERPOLATE_LOC_CENTER:
7638 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 2;
7639 shader->config.spi_ps_input_ena |=
7640 S_0286CC_PERSP_CENTER_ENA(1);
7641 break;
7642 case TGSI_INTERPOLATE_LOC_CENTROID:
7643 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 4;
7644 shader->config.spi_ps_input_ena |=
7645 S_0286CC_PERSP_CENTROID_ENA(1);
7646 break;
7647 default:
7648 assert(0);
7649 }
7650 break;
7651 case TGSI_INTERPOLATE_LINEAR:
7652 /* Force the interpolation location for colors here. */
7653 if (shader->key.ps.prolog.force_linear_sample_interp)
7654 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7655 if (shader->key.ps.prolog.force_linear_center_interp)
7656 location = TGSI_INTERPOLATE_LOC_CENTER;
7657
7658 switch (location) {
7659 case TGSI_INTERPOLATE_LOC_SAMPLE:
7660 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 6;
7661 shader->config.spi_ps_input_ena |=
7662 S_0286CC_LINEAR_SAMPLE_ENA(1);
7663 break;
7664 case TGSI_INTERPOLATE_LOC_CENTER:
7665 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 8;
7666 shader->config.spi_ps_input_ena |=
7667 S_0286CC_LINEAR_CENTER_ENA(1);
7668 break;
7669 case TGSI_INTERPOLATE_LOC_CENTROID:
7670 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 10;
7671 shader->config.spi_ps_input_ena |=
7672 S_0286CC_LINEAR_CENTROID_ENA(1);
7673 break;
7674 default:
7675 assert(0);
7676 }
7677 break;
7678 default:
7679 assert(0);
7680 }
7681 }
7682 }
7683
7684 /* The prolog is a no-op if these aren't set. */
7685 if (prolog_key.ps_prolog.colors_read ||
7686 prolog_key.ps_prolog.states.force_persp_sample_interp ||
7687 prolog_key.ps_prolog.states.force_linear_sample_interp ||
7688 prolog_key.ps_prolog.states.force_persp_center_interp ||
7689 prolog_key.ps_prolog.states.force_linear_center_interp ||
7690 prolog_key.ps_prolog.states.bc_optimize_for_persp ||
7691 prolog_key.ps_prolog.states.bc_optimize_for_linear ||
7692 prolog_key.ps_prolog.states.poly_stipple) {
7693 shader->prolog =
7694 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7695 &prolog_key, tm, debug,
7696 si_compile_ps_prolog);
7697 if (!shader->prolog)
7698 return false;
7699 }
7700
7701 /* Get the epilog. */
7702 memset(&epilog_key, 0, sizeof(epilog_key));
7703 epilog_key.ps_epilog.colors_written = info->colors_written;
7704 epilog_key.ps_epilog.writes_z = info->writes_z;
7705 epilog_key.ps_epilog.writes_stencil = info->writes_stencil;
7706 epilog_key.ps_epilog.writes_samplemask = info->writes_samplemask;
7707 epilog_key.ps_epilog.states = shader->key.ps.epilog;
7708
7709 shader->epilog =
7710 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7711 &epilog_key, tm, debug,
7712 si_compile_ps_epilog);
7713 if (!shader->epilog)
7714 return false;
7715
7716 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7717 if (shader->key.ps.prolog.poly_stipple) {
7718 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7719 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7720 }
7721
7722 /* Set up the enable bits for per-sample shading if needed. */
7723 if (shader->key.ps.prolog.force_persp_sample_interp &&
7724 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7725 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7726 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7727 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7728 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7729 }
7730 if (shader->key.ps.prolog.force_linear_sample_interp &&
7731 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7732 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7733 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7734 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7735 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7736 }
7737 if (shader->key.ps.prolog.force_persp_center_interp &&
7738 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7739 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7740 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7741 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7742 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7743 }
7744 if (shader->key.ps.prolog.force_linear_center_interp &&
7745 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7746 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7747 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7748 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7749 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7750 }
7751
7752 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7753 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7754 !(shader->config.spi_ps_input_ena & 0xf)) {
7755 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7756 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7757 }
7758
7759 /* At least one pair of interpolation weights must be enabled. */
7760 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7761 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7762 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7763 }
7764
7765 /* The sample mask input is always enabled, because the API shader always
7766 * passes it through to the epilog. Disable it here if it's unused.
7767 */
7768 if (!shader->key.ps.epilog.poly_line_smoothing &&
7769 !shader->selector->info.reads_samplemask)
7770 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7771
7772 return true;
7773 }
7774
7775 static void si_fix_num_sgprs(struct si_shader *shader)
7776 {
7777 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7778
7779 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7780 }
7781
7782 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7783 struct si_shader *shader,
7784 struct pipe_debug_callback *debug)
7785 {
7786 struct si_shader *mainp = shader->selector->main_shader_part;
7787 int r;
7788
7789 /* LS, ES, VS are compiled on demand if the main part hasn't been
7790 * compiled for that stage.
7791 */
7792 if (!mainp ||
7793 (shader->selector->type == PIPE_SHADER_VERTEX &&
7794 (shader->key.vs.as_es != mainp->key.vs.as_es ||
7795 shader->key.vs.as_ls != mainp->key.vs.as_ls)) ||
7796 (shader->selector->type == PIPE_SHADER_TESS_EVAL &&
7797 shader->key.tes.as_es != mainp->key.tes.as_es) ||
7798 (shader->selector->type == PIPE_SHADER_TESS_CTRL &&
7799 shader->key.tcs.epilog.inputs_to_copy) ||
7800 shader->selector->type == PIPE_SHADER_COMPUTE) {
7801 /* Monolithic shader (compiled as a whole, has many variants,
7802 * may take a long time to compile).
7803 */
7804 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7805 if (r)
7806 return r;
7807 } else {
7808 /* The shader consists of 2-3 parts:
7809 *
7810 * - the middle part is the user shader, it has 1 variant only
7811 * and it was compiled during the creation of the shader
7812 * selector
7813 * - the prolog part is inserted at the beginning
7814 * - the epilog part is inserted at the end
7815 *
7816 * The prolog and epilog have many (but simple) variants.
7817 */
7818
7819 /* Copy the compiled TGSI shader data over. */
7820 shader->is_binary_shared = true;
7821 shader->binary = mainp->binary;
7822 shader->config = mainp->config;
7823 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7824 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7825 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7826 memcpy(shader->info.vs_output_param_offset,
7827 mainp->info.vs_output_param_offset,
7828 sizeof(mainp->info.vs_output_param_offset));
7829 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7830 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7831 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7832
7833 /* Select prologs and/or epilogs. */
7834 switch (shader->selector->type) {
7835 case PIPE_SHADER_VERTEX:
7836 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7837 return -1;
7838 break;
7839 case PIPE_SHADER_TESS_CTRL:
7840 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7841 return -1;
7842 break;
7843 case PIPE_SHADER_TESS_EVAL:
7844 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
7845 return -1;
7846 break;
7847 case PIPE_SHADER_FRAGMENT:
7848 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7849 return -1;
7850
7851 /* Make sure we have at least as many VGPRs as there
7852 * are allocated inputs.
7853 */
7854 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7855 shader->info.num_input_vgprs);
7856 break;
7857 }
7858
7859 /* Update SGPR and VGPR counts. */
7860 if (shader->prolog) {
7861 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7862 shader->prolog->config.num_sgprs);
7863 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7864 shader->prolog->config.num_vgprs);
7865 }
7866 if (shader->epilog) {
7867 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7868 shader->epilog->config.num_sgprs);
7869 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7870 shader->epilog->config.num_vgprs);
7871 }
7872 }
7873
7874 si_fix_num_sgprs(shader);
7875 si_shader_dump(sscreen, shader, debug, shader->selector->info.processor,
7876 stderr);
7877
7878 /* Upload. */
7879 r = si_shader_binary_upload(sscreen, shader);
7880 if (r) {
7881 fprintf(stderr, "LLVM failed to upload shader\n");
7882 return r;
7883 }
7884
7885 return 0;
7886 }
7887
7888 void si_shader_destroy(struct si_shader *shader)
7889 {
7890 if (shader->gs_copy_shader) {
7891 si_shader_destroy(shader->gs_copy_shader);
7892 FREE(shader->gs_copy_shader);
7893 }
7894
7895 if (shader->scratch_bo)
7896 r600_resource_reference(&shader->scratch_bo, NULL);
7897
7898 r600_resource_reference(&shader->bo, NULL);
7899
7900 if (!shader->is_binary_shared)
7901 radeon_shader_binary_clean(&shader->binary);
7902 }