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[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "util/u_memory.h"
26 #include "util/u_string.h"
27 #include "tgsi/tgsi_build.h"
28 #include "tgsi/tgsi_strings.h"
29 #include "tgsi/tgsi_util.h"
30 #include "tgsi/tgsi_dump.h"
31
32 #include "ac_binary.h"
33 #include "ac_exp_param.h"
34 #include "ac_shader_util.h"
35 #include "ac_rtld.h"
36 #include "ac_llvm_util.h"
37 #include "si_shader_internal.h"
38 #include "si_pipe.h"
39 #include "sid.h"
40
41 #include "compiler/nir/nir.h"
42
43 static const char scratch_rsrc_dword0_symbol[] =
44 "SCRATCH_RSRC_DWORD0";
45
46 static const char scratch_rsrc_dword1_symbol[] =
47 "SCRATCH_RSRC_DWORD1";
48
49 struct si_shader_output_values
50 {
51 LLVMValueRef values[4];
52 unsigned semantic_name;
53 unsigned semantic_index;
54 ubyte vertex_stream[4];
55 };
56
57 static void si_init_shader_ctx(struct si_shader_context *ctx,
58 struct si_screen *sscreen,
59 struct ac_llvm_compiler *compiler);
60
61 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
62 struct lp_build_tgsi_context *bld_base,
63 struct lp_build_emit_data *emit_data);
64
65 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
66 FILE *f);
67
68 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
69 union si_shader_part_key *key);
70 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
71 union si_shader_part_key *key);
72 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
73 union si_shader_part_key *key);
74 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
75 union si_shader_part_key *key);
76 static void si_fix_resource_usage(struct si_screen *sscreen,
77 struct si_shader *shader);
78
79 /* Ideally pass the sample mask input to the PS epilog as v14, which
80 * is its usual location, so that the shader doesn't have to add v_mov.
81 */
82 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
83
84 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
85 LLVMTypeRef type)
86 {
87 if (type == ctx->ac.i64 || type == ctx->ac.f64)
88 return true;
89
90 return false;
91 }
92
93 static bool is_merged_shader(struct si_shader_context *ctx)
94 {
95 if (ctx->screen->info.chip_class <= GFX8)
96 return false;
97
98 return ctx->shader->key.as_ls ||
99 ctx->shader->key.as_es ||
100 ctx->type == PIPE_SHADER_TESS_CTRL ||
101 ctx->type == PIPE_SHADER_GEOMETRY;
102 }
103
104 void si_init_function_info(struct si_function_info *fninfo)
105 {
106 fninfo->num_params = 0;
107 fninfo->num_sgpr_params = 0;
108 }
109
110 unsigned add_arg_assign(struct si_function_info *fninfo,
111 enum si_arg_regfile regfile, LLVMTypeRef type,
112 LLVMValueRef *assign)
113 {
114 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
115
116 unsigned idx = fninfo->num_params++;
117 assert(idx < ARRAY_SIZE(fninfo->types));
118
119 if (regfile == ARG_SGPR)
120 fninfo->num_sgpr_params = fninfo->num_params;
121
122 fninfo->types[idx] = type;
123 fninfo->assign[idx] = assign;
124 return idx;
125 }
126
127 static unsigned add_arg(struct si_function_info *fninfo,
128 enum si_arg_regfile regfile, LLVMTypeRef type)
129 {
130 return add_arg_assign(fninfo, regfile, type, NULL);
131 }
132
133 static void add_arg_assign_checked(struct si_function_info *fninfo,
134 enum si_arg_regfile regfile, LLVMTypeRef type,
135 LLVMValueRef *assign, unsigned idx)
136 {
137 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
138 assert(actual == idx);
139 }
140
141 static void add_arg_checked(struct si_function_info *fninfo,
142 enum si_arg_regfile regfile, LLVMTypeRef type,
143 unsigned idx)
144 {
145 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
146 }
147
148 /**
149 * Returns a unique index for a per-patch semantic name and index. The index
150 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
151 * can be calculated.
152 */
153 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
154 {
155 switch (semantic_name) {
156 case TGSI_SEMANTIC_TESSOUTER:
157 return 0;
158 case TGSI_SEMANTIC_TESSINNER:
159 return 1;
160 case TGSI_SEMANTIC_PATCH:
161 assert(index < 30);
162 return 2 + index;
163
164 default:
165 assert(!"invalid semantic name");
166 return 0;
167 }
168 }
169
170 /**
171 * Returns a unique index for a semantic name and index. The index must be
172 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
173 * calculated.
174 */
175 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index,
176 unsigned is_varying)
177 {
178 switch (semantic_name) {
179 case TGSI_SEMANTIC_POSITION:
180 return 0;
181 case TGSI_SEMANTIC_GENERIC:
182 /* Since some shader stages use the the highest used IO index
183 * to determine the size to allocate for inputs/outputs
184 * (in LDS, tess and GS rings). GENERIC should be placed right
185 * after POSITION to make that size as small as possible.
186 */
187 if (index < SI_MAX_IO_GENERIC)
188 return 1 + index;
189
190 assert(!"invalid generic index");
191 return 0;
192 case TGSI_SEMANTIC_PSIZE:
193 return SI_MAX_IO_GENERIC + 1;
194 case TGSI_SEMANTIC_CLIPDIST:
195 assert(index <= 1);
196 return SI_MAX_IO_GENERIC + 2 + index;
197 case TGSI_SEMANTIC_FOG:
198 return SI_MAX_IO_GENERIC + 4;
199 case TGSI_SEMANTIC_LAYER:
200 return SI_MAX_IO_GENERIC + 5;
201 case TGSI_SEMANTIC_VIEWPORT_INDEX:
202 return SI_MAX_IO_GENERIC + 6;
203 case TGSI_SEMANTIC_PRIMID:
204 return SI_MAX_IO_GENERIC + 7;
205 case TGSI_SEMANTIC_COLOR:
206 assert(index < 2);
207 return SI_MAX_IO_GENERIC + 8 + index;
208 case TGSI_SEMANTIC_BCOLOR:
209 assert(index < 2);
210 /* If it's a varying, COLOR and BCOLOR alias. */
211 if (is_varying)
212 return SI_MAX_IO_GENERIC + 8 + index;
213 else
214 return SI_MAX_IO_GENERIC + 10 + index;
215 case TGSI_SEMANTIC_TEXCOORD:
216 assert(index < 8);
217 STATIC_ASSERT(SI_MAX_IO_GENERIC + 12 + 8 <= 63);
218 return SI_MAX_IO_GENERIC + 12 + index;
219 case TGSI_SEMANTIC_CLIPVERTEX:
220 return 63;
221 default:
222 fprintf(stderr, "invalid semantic name = %u\n", semantic_name);
223 assert(!"invalid semantic name");
224 return 0;
225 }
226 }
227
228 /**
229 * Get the value of a shader input parameter and extract a bitfield.
230 */
231 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
232 LLVMValueRef value, unsigned rshift,
233 unsigned bitwidth)
234 {
235 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
236 value = ac_to_integer(&ctx->ac, value);
237
238 if (rshift)
239 value = LLVMBuildLShr(ctx->ac.builder, value,
240 LLVMConstInt(ctx->i32, rshift, 0), "");
241
242 if (rshift + bitwidth < 32) {
243 unsigned mask = (1 << bitwidth) - 1;
244 value = LLVMBuildAnd(ctx->ac.builder, value,
245 LLVMConstInt(ctx->i32, mask, 0), "");
246 }
247
248 return value;
249 }
250
251 LLVMValueRef si_unpack_param(struct si_shader_context *ctx,
252 unsigned param, unsigned rshift,
253 unsigned bitwidth)
254 {
255 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
256
257 return unpack_llvm_param(ctx, value, rshift, bitwidth);
258 }
259
260 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
261 {
262 switch (ctx->type) {
263 case PIPE_SHADER_TESS_CTRL:
264 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
265
266 case PIPE_SHADER_TESS_EVAL:
267 return LLVMGetParam(ctx->main_fn,
268 ctx->param_tes_rel_patch_id);
269
270 default:
271 assert(0);
272 return NULL;
273 }
274 }
275
276 /* Tessellation shaders pass outputs to the next shader using LDS.
277 *
278 * LS outputs = TCS inputs
279 * TCS outputs = TES inputs
280 *
281 * The LDS layout is:
282 * - TCS inputs for patch 0
283 * - TCS inputs for patch 1
284 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
285 * - ...
286 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
287 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
288 * - TCS outputs for patch 1
289 * - Per-patch TCS outputs for patch 1
290 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
291 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
292 * - ...
293 *
294 * All three shaders VS(LS), TCS, TES share the same LDS space.
295 */
296
297 static LLVMValueRef
298 get_tcs_in_patch_stride(struct si_shader_context *ctx)
299 {
300 return si_unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
301 }
302
303 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
304 {
305 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
306
307 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
308 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
309
310 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
311 }
312
313 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
314 {
315 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
316
317 return LLVMConstInt(ctx->i32, stride, 0);
318 }
319
320 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
321 {
322 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
323 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
324
325 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
326 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
327 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
328 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
329 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
330 num_patch_outputs * 4;
331 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
332 }
333
334 static LLVMValueRef
335 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
336 {
337 return LLVMBuildMul(ctx->ac.builder,
338 si_unpack_param(ctx,
339 ctx->param_tcs_out_lds_offsets,
340 0, 16),
341 LLVMConstInt(ctx->i32, 4, 0), "");
342 }
343
344 static LLVMValueRef
345 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
346 {
347 return LLVMBuildMul(ctx->ac.builder,
348 si_unpack_param(ctx,
349 ctx->param_tcs_out_lds_offsets,
350 16, 16),
351 LLVMConstInt(ctx->i32, 4, 0), "");
352 }
353
354 static LLVMValueRef
355 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
356 {
357 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
358 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
359
360 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
361 }
362
363 static LLVMValueRef
364 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
365 {
366 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
367 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
368 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
369
370 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_offset);
371 }
372
373 static LLVMValueRef
374 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
375 {
376 LLVMValueRef patch0_patch_data_offset =
377 get_tcs_out_patch0_patch_data_offset(ctx);
378 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
379 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
380
381 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_patch_data_offset);
382 }
383
384 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
385 {
386 unsigned tcs_out_vertices =
387 ctx->shader->selector ?
388 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
389
390 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
391 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
392 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
393
394 return si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
395 }
396
397 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
398 {
399 unsigned stride;
400
401 switch (ctx->type) {
402 case PIPE_SHADER_VERTEX:
403 stride = ctx->shader->selector->lshs_vertex_stride / 4;
404 return LLVMConstInt(ctx->i32, stride, 0);
405
406 case PIPE_SHADER_TESS_CTRL:
407 if (ctx->screen->info.chip_class >= GFX9 &&
408 ctx->shader->is_monolithic) {
409 stride = ctx->shader->key.part.tcs.ls->lshs_vertex_stride / 4;
410 return LLVMConstInt(ctx->i32, stride, 0);
411 }
412 return si_unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
413
414 default:
415 assert(0);
416 return NULL;
417 }
418 }
419
420 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
421 LLVMValueRef i32, unsigned index)
422 {
423 assert(index <= 1);
424
425 if (index == 1)
426 return LLVMBuildAShr(ctx->ac.builder, i32,
427 LLVMConstInt(ctx->i32, 16, 0), "");
428
429 return LLVMBuildSExt(ctx->ac.builder,
430 LLVMBuildTrunc(ctx->ac.builder, i32,
431 ctx->ac.i16, ""),
432 ctx->i32, "");
433 }
434
435 void si_llvm_load_input_vs(
436 struct si_shader_context *ctx,
437 unsigned input_index,
438 LLVMValueRef out[4])
439 {
440 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
441 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
442
443 if (vs_blit_property) {
444 LLVMValueRef vertex_id = ctx->abi.vertex_id;
445 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
446 LLVMIntULE, vertex_id,
447 ctx->i32_1, "");
448 /* Use LLVMIntNE, because we have 3 vertices and only
449 * the middle one should use y2.
450 */
451 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
452 LLVMIntNE, vertex_id,
453 ctx->i32_1, "");
454
455 if (input_index == 0) {
456 /* Position: */
457 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
458 ctx->param_vs_blit_inputs);
459 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
460 ctx->param_vs_blit_inputs + 1);
461
462 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
463 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
464 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
465 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
466
467 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
468 x1, x2, "");
469 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
470 y1, y2, "");
471
472 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
473 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
474 out[2] = LLVMGetParam(ctx->main_fn,
475 ctx->param_vs_blit_inputs + 2);
476 out[3] = ctx->ac.f32_1;
477 return;
478 }
479
480 /* Color or texture coordinates: */
481 assert(input_index == 1);
482
483 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
484 for (int i = 0; i < 4; i++) {
485 out[i] = LLVMGetParam(ctx->main_fn,
486 ctx->param_vs_blit_inputs + 3 + i);
487 }
488 } else {
489 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
490 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
491 ctx->param_vs_blit_inputs + 3);
492 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
493 ctx->param_vs_blit_inputs + 4);
494 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
495 ctx->param_vs_blit_inputs + 5);
496 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
497 ctx->param_vs_blit_inputs + 6);
498
499 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
500 x1, x2, "");
501 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
502 y1, y2, "");
503 out[2] = LLVMGetParam(ctx->main_fn,
504 ctx->param_vs_blit_inputs + 7);
505 out[3] = LLVMGetParam(ctx->main_fn,
506 ctx->param_vs_blit_inputs + 8);
507 }
508 return;
509 }
510
511 union si_vs_fix_fetch fix_fetch;
512 LLVMValueRef t_list_ptr;
513 LLVMValueRef t_offset;
514 LLVMValueRef t_list;
515 LLVMValueRef vertex_index;
516 LLVMValueRef tmp;
517
518 /* Load the T list */
519 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
520
521 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
522
523 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
524
525 vertex_index = LLVMGetParam(ctx->main_fn,
526 ctx->param_vertex_index0 +
527 input_index);
528
529 /* Use the open-coded implementation for all loads of doubles and
530 * of dword-sized data that needs fixups. We need to insert conversion
531 * code anyway, and the amd/common code does it for us.
532 *
533 * Note: On LLVM <= 8, we can only open-code formats with
534 * channel size >= 4 bytes.
535 */
536 bool opencode = ctx->shader->key.mono.vs_fetch_opencode & (1 << input_index);
537 fix_fetch.bits = ctx->shader->key.mono.vs_fix_fetch[input_index].bits;
538 if (opencode ||
539 (fix_fetch.u.log_size == 3 && fix_fetch.u.format == AC_FETCH_FORMAT_FLOAT) ||
540 (fix_fetch.u.log_size == 2)) {
541 tmp = ac_build_opencoded_load_format(
542 &ctx->ac, fix_fetch.u.log_size, fix_fetch.u.num_channels_m1 + 1,
543 fix_fetch.u.format, fix_fetch.u.reverse, !opencode,
544 t_list, vertex_index, ctx->ac.i32_0, ctx->ac.i32_0,
545 false, false, true);
546 for (unsigned i = 0; i < 4; ++i)
547 out[i] = LLVMBuildExtractElement(ctx->ac.builder, tmp, LLVMConstInt(ctx->i32, i, false), "");
548 return;
549 }
550
551 /* Do multiple loads for special formats. */
552 unsigned required_channels = util_last_bit(info->input_usage_mask[input_index]);
553 LLVMValueRef fetches[4];
554 unsigned num_fetches;
555 unsigned fetch_stride;
556 unsigned channels_per_fetch;
557
558 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2) {
559 num_fetches = MIN2(required_channels, 3);
560 fetch_stride = 1 << fix_fetch.u.log_size;
561 channels_per_fetch = 1;
562 } else {
563 num_fetches = 1;
564 fetch_stride = 0;
565 channels_per_fetch = required_channels;
566 }
567
568 for (unsigned i = 0; i < num_fetches; ++i) {
569 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
570 fetches[i] = ac_build_buffer_load_format(&ctx->ac, t_list, vertex_index, voffset,
571 channels_per_fetch, false, true);
572 }
573
574 if (num_fetches == 1 && channels_per_fetch > 1) {
575 LLVMValueRef fetch = fetches[0];
576 for (unsigned i = 0; i < channels_per_fetch; ++i) {
577 tmp = LLVMConstInt(ctx->i32, i, false);
578 fetches[i] = LLVMBuildExtractElement(
579 ctx->ac.builder, fetch, tmp, "");
580 }
581 num_fetches = channels_per_fetch;
582 channels_per_fetch = 1;
583 }
584
585 for (unsigned i = num_fetches; i < 4; ++i)
586 fetches[i] = LLVMGetUndef(ctx->f32);
587
588 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2 &&
589 required_channels == 4) {
590 if (fix_fetch.u.format == AC_FETCH_FORMAT_UINT || fix_fetch.u.format == AC_FETCH_FORMAT_SINT)
591 fetches[3] = ctx->ac.i32_1;
592 else
593 fetches[3] = ctx->ac.f32_1;
594 } else if (fix_fetch.u.log_size == 3 &&
595 (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ||
596 fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED ||
597 fix_fetch.u.format == AC_FETCH_FORMAT_SINT) &&
598 required_channels == 4) {
599 /* For 2_10_10_10, the hardware returns an unsigned value;
600 * convert it to a signed one.
601 */
602 LLVMValueRef tmp = fetches[3];
603 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
604
605 /* First, recover the sign-extended signed integer value. */
606 if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED)
607 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
608 else
609 tmp = ac_to_integer(&ctx->ac, tmp);
610
611 /* For the integer-like cases, do a natural sign extension.
612 *
613 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
614 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
615 * exponent.
616 */
617 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
618 fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ?
619 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
620 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
621
622 /* Convert back to the right type. */
623 if (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM) {
624 LLVMValueRef clamp;
625 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
626 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
627 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
628 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
629 } else if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED) {
630 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
631 }
632
633 fetches[3] = tmp;
634 }
635
636 for (unsigned i = 0; i < 4; ++i)
637 out[i] = ac_to_float(&ctx->ac, fetches[i]);
638 }
639
640 static void declare_input_vs(
641 struct si_shader_context *ctx,
642 unsigned input_index,
643 const struct tgsi_full_declaration *decl,
644 LLVMValueRef out[4])
645 {
646 si_llvm_load_input_vs(ctx, input_index, out);
647 }
648
649 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
650 unsigned swizzle)
651 {
652 if (swizzle > 0)
653 return ctx->i32_0;
654
655 switch (ctx->type) {
656 case PIPE_SHADER_VERTEX:
657 return LLVMGetParam(ctx->main_fn,
658 ctx->param_vs_prim_id);
659 case PIPE_SHADER_TESS_CTRL:
660 return ctx->abi.tcs_patch_id;
661 case PIPE_SHADER_TESS_EVAL:
662 return ctx->abi.tes_patch_id;
663 case PIPE_SHADER_GEOMETRY:
664 return ctx->abi.gs_prim_id;
665 default:
666 assert(0);
667 return ctx->i32_0;
668 }
669 }
670
671 /**
672 * Return the value of tgsi_ind_register for indexing.
673 * This is the indirect index with the constant offset added to it.
674 */
675 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
676 const struct tgsi_ind_register *ind,
677 unsigned addr_mul,
678 int rel_index)
679 {
680 LLVMValueRef result;
681
682 if (ind->File == TGSI_FILE_ADDRESS) {
683 result = ctx->addrs[ind->Index][ind->Swizzle];
684 result = LLVMBuildLoad(ctx->ac.builder, result, "");
685 } else {
686 struct tgsi_full_src_register src = {};
687
688 src.Register.File = ind->File;
689 src.Register.Index = ind->Index;
690
691 /* Set the second index to 0 for constants. */
692 if (ind->File == TGSI_FILE_CONSTANT)
693 src.Register.Dimension = 1;
694
695 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
696 TGSI_TYPE_SIGNED,
697 ind->Swizzle);
698 result = ac_to_integer(&ctx->ac, result);
699 }
700
701 return ac_build_imad(&ctx->ac, result, LLVMConstInt(ctx->i32, addr_mul, 0),
702 LLVMConstInt(ctx->i32, rel_index, 0));
703 }
704
705 /**
706 * Like si_get_indirect_index, but restricts the return value to a (possibly
707 * undefined) value inside [0..num).
708 */
709 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
710 const struct tgsi_ind_register *ind,
711 int rel_index, unsigned num)
712 {
713 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
714
715 return si_llvm_bound_index(ctx, result, num);
716 }
717
718 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
719 LLVMValueRef vertex_dw_stride,
720 LLVMValueRef base_addr,
721 LLVMValueRef vertex_index,
722 LLVMValueRef param_index,
723 unsigned input_index,
724 ubyte *name,
725 ubyte *index,
726 bool is_patch)
727 {
728 if (vertex_dw_stride) {
729 base_addr = ac_build_imad(&ctx->ac, vertex_index,
730 vertex_dw_stride, base_addr);
731 }
732
733 if (param_index) {
734 base_addr = ac_build_imad(&ctx->ac, param_index,
735 LLVMConstInt(ctx->i32, 4, 0), base_addr);
736 }
737
738 int param = is_patch ?
739 si_shader_io_get_unique_index_patch(name[input_index],
740 index[input_index]) :
741 si_shader_io_get_unique_index(name[input_index],
742 index[input_index], false);
743
744 /* Add the base address of the element. */
745 return LLVMBuildAdd(ctx->ac.builder, base_addr,
746 LLVMConstInt(ctx->i32, param * 4, 0), "");
747 }
748
749 /**
750 * Calculate a dword address given an input or output register and a stride.
751 */
752 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
753 const struct tgsi_full_dst_register *dst,
754 const struct tgsi_full_src_register *src,
755 LLVMValueRef vertex_dw_stride,
756 LLVMValueRef base_addr)
757 {
758 struct tgsi_shader_info *info = &ctx->shader->selector->info;
759 ubyte *name, *index, *array_first;
760 int input_index;
761 struct tgsi_full_dst_register reg;
762 LLVMValueRef vertex_index = NULL;
763 LLVMValueRef ind_index = NULL;
764
765 /* Set the register description. The address computation is the same
766 * for sources and destinations. */
767 if (src) {
768 reg.Register.File = src->Register.File;
769 reg.Register.Index = src->Register.Index;
770 reg.Register.Indirect = src->Register.Indirect;
771 reg.Register.Dimension = src->Register.Dimension;
772 reg.Indirect = src->Indirect;
773 reg.Dimension = src->Dimension;
774 reg.DimIndirect = src->DimIndirect;
775 } else
776 reg = *dst;
777
778 /* If the register is 2-dimensional (e.g. an array of vertices
779 * in a primitive), calculate the base address of the vertex. */
780 if (reg.Register.Dimension) {
781 if (reg.Dimension.Indirect)
782 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
783 1, reg.Dimension.Index);
784 else
785 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
786 }
787
788 /* Get information about the register. */
789 if (reg.Register.File == TGSI_FILE_INPUT) {
790 name = info->input_semantic_name;
791 index = info->input_semantic_index;
792 array_first = info->input_array_first;
793 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
794 name = info->output_semantic_name;
795 index = info->output_semantic_index;
796 array_first = info->output_array_first;
797 } else {
798 assert(0);
799 return NULL;
800 }
801
802 if (reg.Register.Indirect) {
803 /* Add the relative address of the element. */
804 if (reg.Indirect.ArrayID)
805 input_index = array_first[reg.Indirect.ArrayID];
806 else
807 input_index = reg.Register.Index;
808
809 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
810 1, reg.Register.Index - input_index);
811 } else {
812 input_index = reg.Register.Index;
813 }
814
815 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
816 base_addr, vertex_index,
817 ind_index, input_index,
818 name, index,
819 !reg.Register.Dimension);
820 }
821
822 /* The offchip buffer layout for TCS->TES is
823 *
824 * - attribute 0 of patch 0 vertex 0
825 * - attribute 0 of patch 0 vertex 1
826 * - attribute 0 of patch 0 vertex 2
827 * ...
828 * - attribute 0 of patch 1 vertex 0
829 * - attribute 0 of patch 1 vertex 1
830 * ...
831 * - attribute 1 of patch 0 vertex 0
832 * - attribute 1 of patch 0 vertex 1
833 * ...
834 * - per patch attribute 0 of patch 0
835 * - per patch attribute 0 of patch 1
836 * ...
837 *
838 * Note that every attribute has 4 components.
839 */
840 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
841 LLVMValueRef rel_patch_id,
842 LLVMValueRef vertex_index,
843 LLVMValueRef param_index)
844 {
845 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
846 LLVMValueRef param_stride, constant16;
847
848 vertices_per_patch = get_num_tcs_out_vertices(ctx);
849 num_patches = si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
850 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
851 num_patches, "");
852
853 constant16 = LLVMConstInt(ctx->i32, 16, 0);
854 if (vertex_index) {
855 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
856 vertices_per_patch, vertex_index);
857 param_stride = total_vertices;
858 } else {
859 base_addr = rel_patch_id;
860 param_stride = num_patches;
861 }
862
863 base_addr = ac_build_imad(&ctx->ac, param_index, param_stride, base_addr);
864 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
865
866 if (!vertex_index) {
867 LLVMValueRef patch_data_offset =
868 si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
869
870 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
871 patch_data_offset, "");
872 }
873 return base_addr;
874 }
875
876 /* This is a generic helper that can be shared by the NIR and TGSI backends */
877 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
878 struct si_shader_context *ctx,
879 LLVMValueRef vertex_index,
880 LLVMValueRef param_index,
881 unsigned param_base,
882 ubyte *name,
883 ubyte *index,
884 bool is_patch)
885 {
886 unsigned param_index_base;
887
888 param_index_base = is_patch ?
889 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
890 si_shader_io_get_unique_index(name[param_base], index[param_base], false);
891
892 if (param_index) {
893 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
894 LLVMConstInt(ctx->i32, param_index_base, 0),
895 "");
896 } else {
897 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
898 }
899
900 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
901 vertex_index, param_index);
902 }
903
904 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
905 struct si_shader_context *ctx,
906 const struct tgsi_full_dst_register *dst,
907 const struct tgsi_full_src_register *src)
908 {
909 struct tgsi_shader_info *info = &ctx->shader->selector->info;
910 ubyte *name, *index, *array_first;
911 struct tgsi_full_src_register reg;
912 LLVMValueRef vertex_index = NULL;
913 LLVMValueRef param_index = NULL;
914 unsigned param_base;
915
916 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
917
918 if (reg.Register.Dimension) {
919
920 if (reg.Dimension.Indirect)
921 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
922 1, reg.Dimension.Index);
923 else
924 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
925 }
926
927 /* Get information about the register. */
928 if (reg.Register.File == TGSI_FILE_INPUT) {
929 name = info->input_semantic_name;
930 index = info->input_semantic_index;
931 array_first = info->input_array_first;
932 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
933 name = info->output_semantic_name;
934 index = info->output_semantic_index;
935 array_first = info->output_array_first;
936 } else {
937 assert(0);
938 return NULL;
939 }
940
941 if (reg.Register.Indirect) {
942 if (reg.Indirect.ArrayID)
943 param_base = array_first[reg.Indirect.ArrayID];
944 else
945 param_base = reg.Register.Index;
946
947 param_index = si_get_indirect_index(ctx, &reg.Indirect,
948 1, reg.Register.Index - param_base);
949
950 } else {
951 param_base = reg.Register.Index;
952 }
953
954 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
955 param_index, param_base,
956 name, index, !reg.Register.Dimension);
957 }
958
959 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
960 LLVMTypeRef type, unsigned swizzle,
961 LLVMValueRef buffer, LLVMValueRef offset,
962 LLVMValueRef base, bool can_speculate)
963 {
964 struct si_shader_context *ctx = si_shader_context(bld_base);
965 LLVMValueRef value, value2;
966 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
967
968 if (swizzle == ~0) {
969 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
970 0, 1, 0, can_speculate, false);
971
972 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
973 }
974
975 if (!llvm_type_is_64bit(ctx, type)) {
976 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
977 0, 1, 0, can_speculate, false);
978
979 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
980 return LLVMBuildExtractElement(ctx->ac.builder, value,
981 LLVMConstInt(ctx->i32, swizzle, 0), "");
982 }
983
984 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
985 swizzle * 4, 1, 0, can_speculate, false);
986
987 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
988 swizzle * 4 + 4, 1, 0, can_speculate, false);
989
990 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
991 }
992
993 /**
994 * Load from LSHS LDS storage.
995 *
996 * \param type output value type
997 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
998 * \param dw_addr address in dwords
999 */
1000 static LLVMValueRef lshs_lds_load(struct lp_build_tgsi_context *bld_base,
1001 LLVMTypeRef type, unsigned swizzle,
1002 LLVMValueRef dw_addr)
1003 {
1004 struct si_shader_context *ctx = si_shader_context(bld_base);
1005 LLVMValueRef value;
1006
1007 if (swizzle == ~0) {
1008 LLVMValueRef values[TGSI_NUM_CHANNELS];
1009
1010 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1011 values[chan] = lshs_lds_load(bld_base, type, chan, dw_addr);
1012
1013 return ac_build_gather_values(&ctx->ac, values,
1014 TGSI_NUM_CHANNELS);
1015 }
1016
1017 /* Split 64-bit loads. */
1018 if (llvm_type_is_64bit(ctx, type)) {
1019 LLVMValueRef lo, hi;
1020
1021 lo = lshs_lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1022 hi = lshs_lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1023 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1024 }
1025
1026 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1027 LLVMConstInt(ctx->i32, swizzle, 0), "");
1028
1029 value = ac_lds_load(&ctx->ac, dw_addr);
1030
1031 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1032 }
1033
1034 /**
1035 * Store to LSHS LDS storage.
1036 *
1037 * \param swizzle offset (typically 0..3)
1038 * \param dw_addr address in dwords
1039 * \param value value to store
1040 */
1041 static void lshs_lds_store(struct si_shader_context *ctx,
1042 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1043 LLVMValueRef value)
1044 {
1045 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1046 LLVMConstInt(ctx->i32, dw_offset_imm, 0), "");
1047
1048 ac_lds_store(&ctx->ac, dw_addr, value);
1049 }
1050
1051 enum si_tess_ring {
1052 TCS_FACTOR_RING,
1053 TESS_OFFCHIP_RING_TCS,
1054 TESS_OFFCHIP_RING_TES,
1055 };
1056
1057 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
1058 enum si_tess_ring ring)
1059 {
1060 LLVMBuilderRef builder = ctx->ac.builder;
1061 unsigned param = ring == TESS_OFFCHIP_RING_TES ? ctx->param_tes_offchip_addr :
1062 ctx->param_tcs_out_lds_layout;
1063 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1064
1065 /* TCS only receives high 13 bits of the address. */
1066 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
1067 addr = LLVMBuildAnd(builder, addr,
1068 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
1069 }
1070
1071 if (ring == TCS_FACTOR_RING) {
1072 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
1073 addr = LLVMBuildAdd(builder, addr,
1074 LLVMConstInt(ctx->i32, tf_offset, 0), "");
1075 }
1076
1077 LLVMValueRef desc[4];
1078 desc[0] = addr;
1079 desc[1] = LLVMConstInt(ctx->i32,
1080 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1081 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
1082 desc[3] = LLVMConstInt(ctx->i32,
1083 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1084 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1085 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1086 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1087 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1088 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0);
1089
1090 return ac_build_gather_values(&ctx->ac, desc, 4);
1091 }
1092
1093 static LLVMValueRef fetch_input_tcs(
1094 struct lp_build_tgsi_context *bld_base,
1095 const struct tgsi_full_src_register *reg,
1096 enum tgsi_opcode_type type, unsigned swizzle_in)
1097 {
1098 struct si_shader_context *ctx = si_shader_context(bld_base);
1099 LLVMValueRef dw_addr, stride;
1100 unsigned swizzle = swizzle_in & 0xffff;
1101 stride = get_tcs_in_vertex_dw_stride(ctx);
1102 dw_addr = get_tcs_in_current_patch_offset(ctx);
1103 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1104
1105 return lshs_lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1106 }
1107
1108 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1109 LLVMTypeRef type,
1110 LLVMValueRef vertex_index,
1111 LLVMValueRef param_index,
1112 unsigned const_index,
1113 unsigned location,
1114 unsigned driver_location,
1115 unsigned component,
1116 unsigned num_components,
1117 bool is_patch,
1118 bool is_compact,
1119 bool load_input)
1120 {
1121 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1122 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1123 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1124 LLVMValueRef dw_addr, stride;
1125
1126 driver_location = driver_location / 4;
1127
1128 if (load_input) {
1129 stride = get_tcs_in_vertex_dw_stride(ctx);
1130 dw_addr = get_tcs_in_current_patch_offset(ctx);
1131 } else {
1132 if (is_patch) {
1133 stride = NULL;
1134 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1135 } else {
1136 stride = get_tcs_out_vertex_dw_stride(ctx);
1137 dw_addr = get_tcs_out_current_patch_offset(ctx);
1138 }
1139 }
1140
1141 if (param_index) {
1142 /* Add the constant index to the indirect index */
1143 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1144 LLVMConstInt(ctx->i32, const_index, 0), "");
1145 } else {
1146 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1147 }
1148
1149 ubyte *names;
1150 ubyte *indices;
1151 if (load_input) {
1152 names = info->input_semantic_name;
1153 indices = info->input_semantic_index;
1154 } else {
1155 names = info->output_semantic_name;
1156 indices = info->output_semantic_index;
1157 }
1158
1159 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1160 vertex_index, param_index,
1161 driver_location,
1162 names, indices,
1163 is_patch);
1164
1165 LLVMValueRef value[4];
1166 for (unsigned i = 0; i < num_components; i++) {
1167 unsigned offset = i;
1168 if (llvm_type_is_64bit(ctx, type))
1169 offset *= 2;
1170
1171 offset += component;
1172 value[i + component] = lshs_lds_load(bld_base, type, offset, dw_addr);
1173 }
1174
1175 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1176 }
1177
1178 static LLVMValueRef fetch_output_tcs(
1179 struct lp_build_tgsi_context *bld_base,
1180 const struct tgsi_full_src_register *reg,
1181 enum tgsi_opcode_type type, unsigned swizzle_in)
1182 {
1183 struct si_shader_context *ctx = si_shader_context(bld_base);
1184 LLVMValueRef dw_addr, stride;
1185 unsigned swizzle = (swizzle_in & 0xffff);
1186
1187 if (reg->Register.Dimension) {
1188 stride = get_tcs_out_vertex_dw_stride(ctx);
1189 dw_addr = get_tcs_out_current_patch_offset(ctx);
1190 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1191 } else {
1192 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1193 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1194 }
1195
1196 return lshs_lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1197 }
1198
1199 static LLVMValueRef fetch_input_tes(
1200 struct lp_build_tgsi_context *bld_base,
1201 const struct tgsi_full_src_register *reg,
1202 enum tgsi_opcode_type type, unsigned swizzle_in)
1203 {
1204 struct si_shader_context *ctx = si_shader_context(bld_base);
1205 LLVMValueRef base, addr;
1206 unsigned swizzle = (swizzle_in & 0xffff);
1207
1208 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1209 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1210
1211 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1212 ctx->tess_offchip_ring, base, addr, true);
1213 }
1214
1215 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1216 LLVMTypeRef type,
1217 LLVMValueRef vertex_index,
1218 LLVMValueRef param_index,
1219 unsigned const_index,
1220 unsigned location,
1221 unsigned driver_location,
1222 unsigned component,
1223 unsigned num_components,
1224 bool is_patch,
1225 bool is_compact,
1226 bool load_input)
1227 {
1228 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1229 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1230 LLVMValueRef base, addr;
1231
1232 driver_location = driver_location / 4;
1233
1234 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1235
1236 if (param_index) {
1237 /* Add the constant index to the indirect index */
1238 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1239 LLVMConstInt(ctx->i32, const_index, 0), "");
1240 } else {
1241 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1242 }
1243
1244 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1245 param_index, driver_location,
1246 info->input_semantic_name,
1247 info->input_semantic_index,
1248 is_patch);
1249
1250 /* TODO: This will generate rather ordinary llvm code, although it
1251 * should be easy for the optimiser to fix up. In future we might want
1252 * to refactor buffer_load(), but for now this maximises code sharing
1253 * between the NIR and TGSI backends.
1254 */
1255 LLVMValueRef value[4];
1256 for (unsigned i = 0; i < num_components; i++) {
1257 unsigned offset = i;
1258 if (llvm_type_is_64bit(ctx, type)) {
1259 offset *= 2;
1260 if (offset == 4) {
1261 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1262 vertex_index,
1263 param_index,
1264 driver_location + 1,
1265 info->input_semantic_name,
1266 info->input_semantic_index,
1267 is_patch);
1268 }
1269
1270 offset = offset % 4;
1271 }
1272
1273 offset += component;
1274 value[i + component] = buffer_load(&ctx->bld_base, type, offset,
1275 ctx->tess_offchip_ring, base, addr, true);
1276 }
1277
1278 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1279 }
1280
1281 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1282 const struct tgsi_full_instruction *inst,
1283 const struct tgsi_opcode_info *info,
1284 unsigned index,
1285 LLVMValueRef dst[4])
1286 {
1287 struct si_shader_context *ctx = si_shader_context(bld_base);
1288 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1289 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1290 unsigned chan_index;
1291 LLVMValueRef dw_addr, stride;
1292 LLVMValueRef buffer, base, buf_addr;
1293 LLVMValueRef values[4];
1294 bool skip_lds_store;
1295 bool is_tess_factor = false, is_tess_inner = false;
1296
1297 /* Only handle per-patch and per-vertex outputs here.
1298 * Vectors will be lowered to scalars and this function will be called again.
1299 */
1300 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1301 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1302 si_llvm_emit_store(bld_base, inst, info, index, dst);
1303 return;
1304 }
1305
1306 if (reg->Register.Dimension) {
1307 stride = get_tcs_out_vertex_dw_stride(ctx);
1308 dw_addr = get_tcs_out_current_patch_offset(ctx);
1309 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1310 skip_lds_store = !sh_info->reads_pervertex_outputs;
1311 } else {
1312 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1313 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1314 skip_lds_store = !sh_info->reads_perpatch_outputs;
1315
1316 if (!reg->Register.Indirect) {
1317 int name = sh_info->output_semantic_name[reg->Register.Index];
1318
1319 /* Always write tess factors into LDS for the TCS epilog. */
1320 if (name == TGSI_SEMANTIC_TESSINNER ||
1321 name == TGSI_SEMANTIC_TESSOUTER) {
1322 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1323 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1324 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1325 is_tess_factor = true;
1326 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1327 }
1328 }
1329 }
1330
1331 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1332
1333 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1334 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1335
1336 uint32_t writemask = reg->Register.WriteMask;
1337 while (writemask) {
1338 chan_index = u_bit_scan(&writemask);
1339 LLVMValueRef value = dst[chan_index];
1340
1341 if (inst->Instruction.Saturate)
1342 value = ac_build_clamp(&ctx->ac, value);
1343
1344 /* Skip LDS stores if there is no LDS read of this output. */
1345 if (!skip_lds_store)
1346 lshs_lds_store(ctx, chan_index, dw_addr, value);
1347
1348 value = ac_to_integer(&ctx->ac, value);
1349 values[chan_index] = value;
1350
1351 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1352 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1353 buf_addr, base,
1354 4 * chan_index, 1, 0, false);
1355 }
1356
1357 /* Write tess factors into VGPRs for the epilog. */
1358 if (is_tess_factor &&
1359 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1360 if (!is_tess_inner) {
1361 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1362 ctx->invoc0_tess_factors[chan_index]);
1363 } else if (chan_index < 2) {
1364 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1365 ctx->invoc0_tess_factors[4 + chan_index]);
1366 }
1367 }
1368 }
1369
1370 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1371 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1372 values, 4);
1373 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1374 base, 0, 1, 0, false);
1375 }
1376 }
1377
1378 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1379 const struct nir_variable *var,
1380 LLVMValueRef vertex_index,
1381 LLVMValueRef param_index,
1382 unsigned const_index,
1383 LLVMValueRef src,
1384 unsigned writemask)
1385 {
1386 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1387 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1388 const unsigned component = var->data.location_frac;
1389 const bool is_patch = var->data.patch;
1390 unsigned driver_location = var->data.driver_location;
1391 LLVMValueRef dw_addr, stride;
1392 LLVMValueRef buffer, base, addr;
1393 LLVMValueRef values[8];
1394 bool skip_lds_store;
1395 bool is_tess_factor = false, is_tess_inner = false;
1396
1397 driver_location = driver_location / 4;
1398
1399 if (param_index) {
1400 /* Add the constant index to the indirect index */
1401 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1402 LLVMConstInt(ctx->i32, const_index, 0), "");
1403 } else {
1404 if (const_index != 0)
1405 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1406 }
1407
1408 if (!is_patch) {
1409 stride = get_tcs_out_vertex_dw_stride(ctx);
1410 dw_addr = get_tcs_out_current_patch_offset(ctx);
1411 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1412 vertex_index, param_index,
1413 driver_location,
1414 info->output_semantic_name,
1415 info->output_semantic_index,
1416 is_patch);
1417
1418 skip_lds_store = !info->reads_pervertex_outputs;
1419 } else {
1420 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1421 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1422 vertex_index, param_index,
1423 driver_location,
1424 info->output_semantic_name,
1425 info->output_semantic_index,
1426 is_patch);
1427
1428 skip_lds_store = !info->reads_perpatch_outputs;
1429
1430 if (!param_index) {
1431 int name = info->output_semantic_name[driver_location];
1432
1433 /* Always write tess factors into LDS for the TCS epilog. */
1434 if (name == TGSI_SEMANTIC_TESSINNER ||
1435 name == TGSI_SEMANTIC_TESSOUTER) {
1436 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1437 skip_lds_store = !info->reads_tessfactor_outputs &&
1438 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1439 is_tess_factor = true;
1440 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1441 }
1442 }
1443 }
1444
1445 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1446
1447 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1448
1449 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1450 param_index, driver_location,
1451 info->output_semantic_name,
1452 info->output_semantic_index,
1453 is_patch);
1454
1455 for (unsigned chan = 0; chan < 8; chan++) {
1456 if (!(writemask & (1 << chan)))
1457 continue;
1458 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1459
1460 unsigned buffer_store_offset = chan % 4;
1461 if (chan == 4) {
1462 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1463 vertex_index,
1464 param_index,
1465 driver_location + 1,
1466 info->output_semantic_name,
1467 info->output_semantic_index,
1468 is_patch);
1469 }
1470
1471 /* Skip LDS stores if there is no LDS read of this output. */
1472 if (!skip_lds_store)
1473 lshs_lds_store(ctx, chan, dw_addr, value);
1474
1475 value = ac_to_integer(&ctx->ac, value);
1476 values[chan] = value;
1477
1478 if (writemask != 0xF && !is_tess_factor) {
1479 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1480 addr, base,
1481 4 * buffer_store_offset,
1482 1, 0, false);
1483 }
1484
1485 /* Write tess factors into VGPRs for the epilog. */
1486 if (is_tess_factor &&
1487 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1488 if (!is_tess_inner) {
1489 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1490 ctx->invoc0_tess_factors[chan]);
1491 } else if (chan < 2) {
1492 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1493 ctx->invoc0_tess_factors[4 + chan]);
1494 }
1495 }
1496 }
1497
1498 if (writemask == 0xF && !is_tess_factor) {
1499 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1500 values, 4);
1501 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1502 base, 0, 1, 0, false);
1503 }
1504 }
1505
1506 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1507 unsigned input_index,
1508 unsigned vtx_offset_param,
1509 LLVMTypeRef type,
1510 unsigned swizzle)
1511 {
1512 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1513 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1514 struct si_shader *shader = ctx->shader;
1515 LLVMValueRef vtx_offset, soffset;
1516 struct tgsi_shader_info *info = &shader->selector->info;
1517 unsigned semantic_name = info->input_semantic_name[input_index];
1518 unsigned semantic_index = info->input_semantic_index[input_index];
1519 unsigned param;
1520 LLVMValueRef value;
1521
1522 param = si_shader_io_get_unique_index(semantic_name, semantic_index, false);
1523
1524 /* GFX9 has the ESGS ring in LDS. */
1525 if (ctx->screen->info.chip_class >= GFX9) {
1526 unsigned index = vtx_offset_param;
1527
1528 switch (index / 2) {
1529 case 0:
1530 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx01_offset,
1531 index % 2 ? 16 : 0, 16);
1532 break;
1533 case 1:
1534 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx23_offset,
1535 index % 2 ? 16 : 0, 16);
1536 break;
1537 case 2:
1538 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx45_offset,
1539 index % 2 ? 16 : 0, 16);
1540 break;
1541 default:
1542 assert(0);
1543 return NULL;
1544 }
1545
1546 unsigned offset = param * 4 + swizzle;
1547 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1548 LLVMConstInt(ctx->i32, offset, false), "");
1549
1550 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->esgs_ring, vtx_offset);
1551 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, ptr, "");
1552 if (llvm_type_is_64bit(ctx, type)) {
1553 ptr = LLVMBuildGEP(ctx->ac.builder, ptr,
1554 &ctx->ac.i32_1, 1, "");
1555 LLVMValueRef values[2] = {
1556 value,
1557 LLVMBuildLoad(ctx->ac.builder, ptr, "")
1558 };
1559 value = ac_build_gather_values(&ctx->ac, values, 2);
1560 }
1561 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1562 }
1563
1564 /* GFX6: input load from the ESGS ring in memory. */
1565 if (swizzle == ~0) {
1566 LLVMValueRef values[TGSI_NUM_CHANNELS];
1567 unsigned chan;
1568 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1569 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1570 type, chan);
1571 }
1572 return ac_build_gather_values(&ctx->ac, values,
1573 TGSI_NUM_CHANNELS);
1574 }
1575
1576 /* Get the vertex offset parameter on GFX6. */
1577 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1578
1579 vtx_offset = LLVMBuildMul(ctx->ac.builder, gs_vtx_offset,
1580 LLVMConstInt(ctx->i32, 4, 0), "");
1581
1582 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1583
1584 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1585 vtx_offset, soffset, 0, 1, 0, true, false);
1586 if (llvm_type_is_64bit(ctx, type)) {
1587 LLVMValueRef value2;
1588 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1589
1590 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1591 ctx->i32_0, vtx_offset, soffset,
1592 0, 1, 0, true, false);
1593 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1594 }
1595 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1596 }
1597
1598 static LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
1599 unsigned location,
1600 unsigned driver_location,
1601 unsigned component,
1602 unsigned num_components,
1603 unsigned vertex_index,
1604 unsigned const_index,
1605 LLVMTypeRef type)
1606 {
1607 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1608
1609 LLVMValueRef value[4];
1610 for (unsigned i = 0; i < num_components; i++) {
1611 unsigned offset = i;
1612 if (llvm_type_is_64bit(ctx, type))
1613 offset *= 2;
1614
1615 offset += component;
1616 value[i + component] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4,
1617 vertex_index, type, offset);
1618 }
1619
1620 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1621 }
1622
1623 static LLVMValueRef fetch_input_gs(
1624 struct lp_build_tgsi_context *bld_base,
1625 const struct tgsi_full_src_register *reg,
1626 enum tgsi_opcode_type type,
1627 unsigned swizzle_in)
1628 {
1629 struct si_shader_context *ctx = si_shader_context(bld_base);
1630 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1631 unsigned swizzle = swizzle_in & 0xffff;
1632
1633 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1634 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1635 return get_primitive_id(ctx, swizzle);
1636
1637 if (!reg->Register.Dimension)
1638 return NULL;
1639
1640 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1641 reg->Dimension.Index,
1642 tgsi2llvmtype(bld_base, type),
1643 swizzle);
1644 }
1645
1646 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1647 {
1648 switch (interpolate) {
1649 case TGSI_INTERPOLATE_CONSTANT:
1650 return 0;
1651
1652 case TGSI_INTERPOLATE_LINEAR:
1653 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1654 return SI_PARAM_LINEAR_SAMPLE;
1655 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1656 return SI_PARAM_LINEAR_CENTROID;
1657 else
1658 return SI_PARAM_LINEAR_CENTER;
1659 break;
1660 case TGSI_INTERPOLATE_COLOR:
1661 case TGSI_INTERPOLATE_PERSPECTIVE:
1662 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1663 return SI_PARAM_PERSP_SAMPLE;
1664 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1665 return SI_PARAM_PERSP_CENTROID;
1666 else
1667 return SI_PARAM_PERSP_CENTER;
1668 break;
1669 default:
1670 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1671 return -1;
1672 }
1673 }
1674
1675 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1676 unsigned attr_index, unsigned chan,
1677 LLVMValueRef prim_mask,
1678 LLVMValueRef i, LLVMValueRef j)
1679 {
1680 if (i || j) {
1681 return ac_build_fs_interp(&ctx->ac,
1682 LLVMConstInt(ctx->i32, chan, 0),
1683 LLVMConstInt(ctx->i32, attr_index, 0),
1684 prim_mask, i, j);
1685 }
1686 return ac_build_fs_interp_mov(&ctx->ac,
1687 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1688 LLVMConstInt(ctx->i32, chan, 0),
1689 LLVMConstInt(ctx->i32, attr_index, 0),
1690 prim_mask);
1691 }
1692
1693 /**
1694 * Interpolate a fragment shader input.
1695 *
1696 * @param ctx context
1697 * @param input_index index of the input in hardware
1698 * @param semantic_name TGSI_SEMANTIC_*
1699 * @param semantic_index semantic index
1700 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1701 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1702 * @param interp_param interpolation weights (i,j)
1703 * @param prim_mask SI_PARAM_PRIM_MASK
1704 * @param face SI_PARAM_FRONT_FACE
1705 * @param result the return value (4 components)
1706 */
1707 static void interp_fs_input(struct si_shader_context *ctx,
1708 unsigned input_index,
1709 unsigned semantic_name,
1710 unsigned semantic_index,
1711 unsigned num_interp_inputs,
1712 unsigned colors_read_mask,
1713 LLVMValueRef interp_param,
1714 LLVMValueRef prim_mask,
1715 LLVMValueRef face,
1716 LLVMValueRef result[4])
1717 {
1718 LLVMValueRef i = NULL, j = NULL;
1719 unsigned chan;
1720
1721 /* fs.constant returns the param from the middle vertex, so it's not
1722 * really useful for flat shading. It's meant to be used for custom
1723 * interpolation (but the intrinsic can't fetch from the other two
1724 * vertices).
1725 *
1726 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1727 * to do the right thing. The only reason we use fs.constant is that
1728 * fs.interp cannot be used on integers, because they can be equal
1729 * to NaN.
1730 *
1731 * When interp is false we will use fs.constant or for newer llvm,
1732 * amdgcn.interp.mov.
1733 */
1734 bool interp = interp_param != NULL;
1735
1736 if (interp) {
1737 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1738 LLVMVectorType(ctx->f32, 2), "");
1739
1740 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1741 ctx->i32_0, "");
1742 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1743 ctx->i32_1, "");
1744 }
1745
1746 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1747 ctx->shader->key.part.ps.prolog.color_two_side) {
1748 LLVMValueRef is_face_positive;
1749
1750 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1751 * otherwise it's at offset "num_inputs".
1752 */
1753 unsigned back_attr_offset = num_interp_inputs;
1754 if (semantic_index == 1 && colors_read_mask & 0xf)
1755 back_attr_offset += 1;
1756
1757 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1758 face, ctx->i32_0, "");
1759
1760 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1761 LLVMValueRef front, back;
1762
1763 front = si_build_fs_interp(ctx,
1764 input_index, chan,
1765 prim_mask, i, j);
1766 back = si_build_fs_interp(ctx,
1767 back_attr_offset, chan,
1768 prim_mask, i, j);
1769
1770 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1771 is_face_positive,
1772 front,
1773 back,
1774 "");
1775 }
1776 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1777 result[0] = si_build_fs_interp(ctx, input_index,
1778 0, prim_mask, i, j);
1779 result[1] =
1780 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1781 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1782 } else {
1783 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1784 result[chan] = si_build_fs_interp(ctx,
1785 input_index, chan,
1786 prim_mask, i, j);
1787 }
1788 }
1789 }
1790
1791 void si_llvm_load_input_fs(
1792 struct si_shader_context *ctx,
1793 unsigned input_index,
1794 LLVMValueRef out[4])
1795 {
1796 struct si_shader *shader = ctx->shader;
1797 struct tgsi_shader_info *info = &shader->selector->info;
1798 LLVMValueRef main_fn = ctx->main_fn;
1799 LLVMValueRef interp_param = NULL;
1800 int interp_param_idx;
1801 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1802 unsigned semantic_index = info->input_semantic_index[input_index];
1803 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1804 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1805
1806 /* Get colors from input VGPRs (set by the prolog). */
1807 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1808 unsigned colors_read = shader->selector->info.colors_read;
1809 unsigned mask = colors_read >> (semantic_index * 4);
1810 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1811 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1812 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1813
1814 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1815 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1816 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1817 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1818 return;
1819 }
1820
1821 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1822 if (interp_param_idx == -1)
1823 return;
1824 else if (interp_param_idx) {
1825 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1826 }
1827
1828 interp_fs_input(ctx, input_index, semantic_name,
1829 semantic_index, 0, /* this param is unused */
1830 shader->selector->info.colors_read, interp_param,
1831 ctx->abi.prim_mask,
1832 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1833 &out[0]);
1834 }
1835
1836 static void declare_input_fs(
1837 struct si_shader_context *ctx,
1838 unsigned input_index,
1839 const struct tgsi_full_declaration *decl,
1840 LLVMValueRef out[4])
1841 {
1842 si_llvm_load_input_fs(ctx, input_index, out);
1843 }
1844
1845 LLVMValueRef si_get_sample_id(struct si_shader_context *ctx)
1846 {
1847 return si_unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1848 }
1849
1850 static LLVMValueRef get_base_vertex(struct ac_shader_abi *abi)
1851 {
1852 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1853
1854 /* For non-indexed draws, the base vertex set by the driver
1855 * (for direct draws) or the CP (for indirect draws) is the
1856 * first vertex ID, but GLSL expects 0 to be returned.
1857 */
1858 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn,
1859 ctx->param_vs_state_bits);
1860 LLVMValueRef indexed;
1861
1862 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1863 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1864
1865 return LLVMBuildSelect(ctx->ac.builder, indexed, ctx->abi.base_vertex,
1866 ctx->i32_0, "");
1867 }
1868
1869 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1870 {
1871 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1872
1873 LLVMValueRef values[3];
1874 LLVMValueRef result;
1875 unsigned i;
1876 unsigned *properties = ctx->shader->selector->info.properties;
1877
1878 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1879 unsigned sizes[3] = {
1880 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1881 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1882 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1883 };
1884
1885 for (i = 0; i < 3; ++i)
1886 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1887
1888 result = ac_build_gather_values(&ctx->ac, values, 3);
1889 } else {
1890 result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1891 }
1892
1893 return result;
1894 }
1895
1896 /**
1897 * Load a dword from a constant buffer.
1898 */
1899 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1900 LLVMValueRef resource,
1901 LLVMValueRef offset)
1902 {
1903 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1904 0, 0, 0, true, true);
1905 }
1906
1907 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1908 {
1909 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1910 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1911 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1912 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1913
1914 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1915 LLVMValueRef offset0 = LLVMBuildMul(ctx->ac.builder, sample_id, LLVMConstInt(ctx->i32, 8, 0), "");
1916 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1917
1918 LLVMValueRef pos[4] = {
1919 buffer_load_const(ctx, resource, offset0),
1920 buffer_load_const(ctx, resource, offset1),
1921 LLVMConstReal(ctx->f32, 0),
1922 LLVMConstReal(ctx->f32, 0)
1923 };
1924
1925 return ac_build_gather_values(&ctx->ac, pos, 4);
1926 }
1927
1928 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1929 {
1930 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1931 return ac_to_integer(&ctx->ac, abi->sample_coverage);
1932 }
1933
1934 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
1935 {
1936 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1937 LLVMValueRef coord[4] = {
1938 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1939 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1940 ctx->ac.f32_0,
1941 ctx->ac.f32_0
1942 };
1943
1944 /* For triangles, the vector should be (u, v, 1-u-v). */
1945 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1946 PIPE_PRIM_TRIANGLES) {
1947 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1948 LLVMBuildFAdd(ctx->ac.builder,
1949 coord[0], coord[1], ""), "");
1950 }
1951 return ac_build_gather_values(&ctx->ac, coord, 4);
1952 }
1953
1954 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
1955 unsigned semantic_name)
1956 {
1957 LLVMValueRef base, addr;
1958
1959 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
1960
1961 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1962 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1963 LLVMConstInt(ctx->i32, param, 0));
1964
1965 return buffer_load(&ctx->bld_base, ctx->f32,
1966 ~0, ctx->tess_offchip_ring, base, addr, true);
1967
1968 }
1969
1970 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
1971 unsigned varying_id)
1972 {
1973 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1974 unsigned semantic_name;
1975
1976 switch (varying_id) {
1977 case VARYING_SLOT_TESS_LEVEL_INNER:
1978 semantic_name = TGSI_SEMANTIC_TESSINNER;
1979 break;
1980 case VARYING_SLOT_TESS_LEVEL_OUTER:
1981 semantic_name = TGSI_SEMANTIC_TESSOUTER;
1982 break;
1983 default:
1984 unreachable("unknown tess level");
1985 }
1986
1987 return load_tess_level(ctx, semantic_name);
1988
1989 }
1990
1991 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
1992 {
1993 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1994 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1995 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
1996 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1997 return get_num_tcs_out_vertices(ctx);
1998 else
1999 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2000 }
2001
2002 void si_load_system_value(struct si_shader_context *ctx,
2003 unsigned index,
2004 const struct tgsi_full_declaration *decl)
2005 {
2006 LLVMValueRef value = 0;
2007
2008 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
2009
2010 switch (decl->Semantic.Name) {
2011 case TGSI_SEMANTIC_INSTANCEID:
2012 value = ctx->abi.instance_id;
2013 break;
2014
2015 case TGSI_SEMANTIC_VERTEXID:
2016 value = LLVMBuildAdd(ctx->ac.builder,
2017 ctx->abi.vertex_id,
2018 ctx->abi.base_vertex, "");
2019 break;
2020
2021 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2022 /* Unused. Clarify the meaning in indexed vs. non-indexed
2023 * draws if this is ever used again. */
2024 assert(false);
2025 break;
2026
2027 case TGSI_SEMANTIC_BASEVERTEX:
2028 value = get_base_vertex(&ctx->abi);
2029 break;
2030
2031 case TGSI_SEMANTIC_BASEINSTANCE:
2032 value = ctx->abi.start_instance;
2033 break;
2034
2035 case TGSI_SEMANTIC_DRAWID:
2036 value = ctx->abi.draw_id;
2037 break;
2038
2039 case TGSI_SEMANTIC_INVOCATIONID:
2040 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2041 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2042 else if (ctx->type == PIPE_SHADER_GEOMETRY)
2043 value = ctx->abi.gs_invocation_id;
2044 else
2045 assert(!"INVOCATIONID not implemented");
2046 break;
2047
2048 case TGSI_SEMANTIC_POSITION:
2049 {
2050 LLVMValueRef pos[4] = {
2051 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2052 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2053 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2054 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2055 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT)),
2056 };
2057 value = ac_build_gather_values(&ctx->ac, pos, 4);
2058 break;
2059 }
2060
2061 case TGSI_SEMANTIC_FACE:
2062 value = ctx->abi.front_face;
2063 break;
2064
2065 case TGSI_SEMANTIC_SAMPLEID:
2066 value = si_get_sample_id(ctx);
2067 break;
2068
2069 case TGSI_SEMANTIC_SAMPLEPOS: {
2070 LLVMValueRef pos[4] = {
2071 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2072 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2073 LLVMConstReal(ctx->f32, 0),
2074 LLVMConstReal(ctx->f32, 0)
2075 };
2076 pos[0] = ac_build_fract(&ctx->ac, pos[0], 32);
2077 pos[1] = ac_build_fract(&ctx->ac, pos[1], 32);
2078 value = ac_build_gather_values(&ctx->ac, pos, 4);
2079 break;
2080 }
2081
2082 case TGSI_SEMANTIC_SAMPLEMASK:
2083 /* This can only occur with the OpenGL Core profile, which
2084 * doesn't support smoothing.
2085 */
2086 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2087 break;
2088
2089 case TGSI_SEMANTIC_TESSCOORD:
2090 value = si_load_tess_coord(&ctx->abi);
2091 break;
2092
2093 case TGSI_SEMANTIC_VERTICESIN:
2094 value = si_load_patch_vertices_in(&ctx->abi);
2095 break;
2096
2097 case TGSI_SEMANTIC_TESSINNER:
2098 case TGSI_SEMANTIC_TESSOUTER:
2099 value = load_tess_level(ctx, decl->Semantic.Name);
2100 break;
2101
2102 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
2103 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
2104 {
2105 LLVMValueRef buf, slot, val[4];
2106 int i, offset;
2107
2108 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
2109 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2110 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
2111 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
2112
2113 for (i = 0; i < 4; i++)
2114 val[i] = buffer_load_const(ctx, buf,
2115 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
2116 value = ac_build_gather_values(&ctx->ac, val, 4);
2117 break;
2118 }
2119
2120 case TGSI_SEMANTIC_PRIMID:
2121 value = get_primitive_id(ctx, 0);
2122 break;
2123
2124 case TGSI_SEMANTIC_GRID_SIZE:
2125 value = ctx->abi.num_work_groups;
2126 break;
2127
2128 case TGSI_SEMANTIC_BLOCK_SIZE:
2129 value = get_block_size(&ctx->abi);
2130 break;
2131
2132 case TGSI_SEMANTIC_BLOCK_ID:
2133 {
2134 LLVMValueRef values[3];
2135
2136 for (int i = 0; i < 3; i++) {
2137 values[i] = ctx->i32_0;
2138 if (ctx->abi.workgroup_ids[i]) {
2139 values[i] = ctx->abi.workgroup_ids[i];
2140 }
2141 }
2142 value = ac_build_gather_values(&ctx->ac, values, 3);
2143 break;
2144 }
2145
2146 case TGSI_SEMANTIC_THREAD_ID:
2147 value = ctx->abi.local_invocation_ids;
2148 break;
2149
2150 case TGSI_SEMANTIC_HELPER_INVOCATION:
2151 value = ac_build_load_helper_invocation(&ctx->ac);
2152 break;
2153
2154 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2155 value = LLVMConstInt(ctx->i32, 64, 0);
2156 break;
2157
2158 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2159 value = ac_get_thread_id(&ctx->ac);
2160 break;
2161
2162 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2163 {
2164 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2165 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2166 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
2167 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2168 break;
2169 }
2170
2171 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2172 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2173 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2174 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2175 {
2176 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2177 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2178 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2179 /* All bits set except LSB */
2180 value = LLVMConstInt(ctx->i64, -2, 0);
2181 } else {
2182 /* All bits set */
2183 value = LLVMConstInt(ctx->i64, -1, 0);
2184 }
2185 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2186 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2187 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2188 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2189 value = LLVMBuildNot(ctx->ac.builder, value, "");
2190 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2191 break;
2192 }
2193
2194 case TGSI_SEMANTIC_CS_USER_DATA:
2195 value = LLVMGetParam(ctx->main_fn, ctx->param_cs_user_data);
2196 break;
2197
2198 default:
2199 assert(!"unknown system value");
2200 return;
2201 }
2202
2203 ctx->system_values[index] = value;
2204 }
2205
2206 void si_declare_compute_memory(struct si_shader_context *ctx)
2207 {
2208 struct si_shader_selector *sel = ctx->shader->selector;
2209 unsigned lds_size = sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE];
2210
2211 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_ADDR_SPACE_LDS);
2212 LLVMValueRef var;
2213
2214 assert(!ctx->ac.lds);
2215
2216 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2217 LLVMArrayType(ctx->i8, lds_size),
2218 "compute_lds",
2219 AC_ADDR_SPACE_LDS);
2220 LLVMSetAlignment(var, 64 * 1024);
2221
2222 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2223 }
2224
2225 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
2226 const struct tgsi_full_declaration *decl)
2227 {
2228 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2229 assert(decl->Range.First == decl->Range.Last);
2230
2231 si_declare_compute_memory(ctx);
2232 }
2233
2234 static LLVMValueRef load_const_buffer_desc_fast_path(struct si_shader_context *ctx)
2235 {
2236 LLVMValueRef ptr =
2237 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2238 struct si_shader_selector *sel = ctx->shader->selector;
2239
2240 /* Do the bounds checking with a descriptor, because
2241 * doing computation and manual bounds checking of 64-bit
2242 * addresses generates horrible VALU code with very high
2243 * VGPR usage and very low SIMD occupancy.
2244 */
2245 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->ac.intptr, "");
2246
2247 LLVMValueRef desc0, desc1;
2248 desc0 = ptr;
2249 desc1 = LLVMConstInt(ctx->i32,
2250 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
2251
2252 LLVMValueRef desc_elems[] = {
2253 desc0,
2254 desc1,
2255 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2256 LLVMConstInt(ctx->i32,
2257 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2258 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2259 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2260 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2261 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2262 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2263 };
2264
2265 return ac_build_gather_values(&ctx->ac, desc_elems, 4);
2266 }
2267
2268 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2269 {
2270 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2271 ctx->param_const_and_shader_buffers);
2272
2273 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2274 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2275 }
2276
2277 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2278 {
2279 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2280 struct si_shader_selector *sel = ctx->shader->selector;
2281
2282 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2283
2284 if (sel->info.const_buffers_declared == 1 &&
2285 sel->info.shader_buffers_declared == 0) {
2286 return load_const_buffer_desc_fast_path(ctx);
2287 }
2288
2289 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2290 index = LLVMBuildAdd(ctx->ac.builder, index,
2291 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2292
2293 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2294 }
2295
2296 static LLVMValueRef
2297 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2298 {
2299 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2300 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2301 ctx->param_const_and_shader_buffers);
2302
2303 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2304 index = LLVMBuildSub(ctx->ac.builder,
2305 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2306 index, "");
2307
2308 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2309 }
2310
2311 static LLVMValueRef fetch_constant(
2312 struct lp_build_tgsi_context *bld_base,
2313 const struct tgsi_full_src_register *reg,
2314 enum tgsi_opcode_type type,
2315 unsigned swizzle_in)
2316 {
2317 struct si_shader_context *ctx = si_shader_context(bld_base);
2318 struct si_shader_selector *sel = ctx->shader->selector;
2319 const struct tgsi_ind_register *ireg = &reg->Indirect;
2320 unsigned buf, idx;
2321 unsigned swizzle = swizzle_in & 0xffff;
2322
2323 LLVMValueRef addr, bufp;
2324
2325 if (swizzle_in == LP_CHAN_ALL) {
2326 unsigned chan;
2327 LLVMValueRef values[4];
2328 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2329 values[chan] = fetch_constant(bld_base, reg, type, chan);
2330
2331 return ac_build_gather_values(&ctx->ac, values, 4);
2332 }
2333
2334 /* Split 64-bit loads. */
2335 if (tgsi_type_is_64bit(type)) {
2336 LLVMValueRef lo, hi;
2337
2338 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2339 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, (swizzle_in >> 16));
2340 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2341 lo, hi);
2342 }
2343
2344 idx = reg->Register.Index * 4 + swizzle;
2345 if (reg->Register.Indirect) {
2346 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2347 } else {
2348 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2349 }
2350
2351 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2352 if (sel->info.const_buffers_declared == 1 &&
2353 sel->info.shader_buffers_declared == 0) {
2354 LLVMValueRef desc = load_const_buffer_desc_fast_path(ctx);
2355 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2356 return bitcast(bld_base, type, result);
2357 }
2358
2359 assert(reg->Register.Dimension);
2360 buf = reg->Dimension.Index;
2361
2362 if (reg->Dimension.Indirect) {
2363 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2364 LLVMValueRef index;
2365 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2366 reg->Dimension.Index,
2367 ctx->num_const_buffers);
2368 index = LLVMBuildAdd(ctx->ac.builder, index,
2369 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2370 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2371 } else
2372 bufp = load_const_buffer_desc(ctx, buf);
2373
2374 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2375 }
2376
2377 /* Initialize arguments for the shader export intrinsic */
2378 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2379 LLVMValueRef *values,
2380 unsigned target,
2381 struct ac_export_args *args)
2382 {
2383 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2384 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2385 unsigned chan;
2386 bool is_int8, is_int10;
2387
2388 /* Default is 0xf. Adjusted below depending on the format. */
2389 args->enabled_channels = 0xf; /* writemask */
2390
2391 /* Specify whether the EXEC mask represents the valid mask */
2392 args->valid_mask = 0;
2393
2394 /* Specify whether this is the last export */
2395 args->done = 0;
2396
2397 /* Specify the target we are exporting */
2398 args->target = target;
2399
2400 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2401 const struct si_shader_key *key = &ctx->shader->key;
2402 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2403 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2404
2405 assert(cbuf >= 0 && cbuf < 8);
2406 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2407 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2408 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2409 }
2410
2411 args->compr = false;
2412 args->out[0] = f32undef;
2413 args->out[1] = f32undef;
2414 args->out[2] = f32undef;
2415 args->out[3] = f32undef;
2416
2417 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2418 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2419 unsigned bits, bool hi) = NULL;
2420
2421 switch (spi_shader_col_format) {
2422 case V_028714_SPI_SHADER_ZERO:
2423 args->enabled_channels = 0; /* writemask */
2424 args->target = V_008DFC_SQ_EXP_NULL;
2425 break;
2426
2427 case V_028714_SPI_SHADER_32_R:
2428 args->enabled_channels = 1; /* writemask */
2429 args->out[0] = values[0];
2430 break;
2431
2432 case V_028714_SPI_SHADER_32_GR:
2433 args->enabled_channels = 0x3; /* writemask */
2434 args->out[0] = values[0];
2435 args->out[1] = values[1];
2436 break;
2437
2438 case V_028714_SPI_SHADER_32_AR:
2439 args->enabled_channels = 0x9; /* writemask */
2440 args->out[0] = values[0];
2441 args->out[3] = values[3];
2442 break;
2443
2444 case V_028714_SPI_SHADER_FP16_ABGR:
2445 packf = ac_build_cvt_pkrtz_f16;
2446 break;
2447
2448 case V_028714_SPI_SHADER_UNORM16_ABGR:
2449 packf = ac_build_cvt_pknorm_u16;
2450 break;
2451
2452 case V_028714_SPI_SHADER_SNORM16_ABGR:
2453 packf = ac_build_cvt_pknorm_i16;
2454 break;
2455
2456 case V_028714_SPI_SHADER_UINT16_ABGR:
2457 packi = ac_build_cvt_pk_u16;
2458 break;
2459
2460 case V_028714_SPI_SHADER_SINT16_ABGR:
2461 packi = ac_build_cvt_pk_i16;
2462 break;
2463
2464 case V_028714_SPI_SHADER_32_ABGR:
2465 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2466 break;
2467 }
2468
2469 /* Pack f16 or norm_i16/u16. */
2470 if (packf) {
2471 for (chan = 0; chan < 2; chan++) {
2472 LLVMValueRef pack_args[2] = {
2473 values[2 * chan],
2474 values[2 * chan + 1]
2475 };
2476 LLVMValueRef packed;
2477
2478 packed = packf(&ctx->ac, pack_args);
2479 args->out[chan] = ac_to_float(&ctx->ac, packed);
2480 }
2481 args->compr = 1; /* COMPR flag */
2482 }
2483 /* Pack i16/u16. */
2484 if (packi) {
2485 for (chan = 0; chan < 2; chan++) {
2486 LLVMValueRef pack_args[2] = {
2487 ac_to_integer(&ctx->ac, values[2 * chan]),
2488 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2489 };
2490 LLVMValueRef packed;
2491
2492 packed = packi(&ctx->ac, pack_args,
2493 is_int8 ? 8 : is_int10 ? 10 : 16,
2494 chan == 1);
2495 args->out[chan] = ac_to_float(&ctx->ac, packed);
2496 }
2497 args->compr = 1; /* COMPR flag */
2498 }
2499 }
2500
2501 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2502 LLVMValueRef alpha)
2503 {
2504 struct si_shader_context *ctx = si_shader_context(bld_base);
2505
2506 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2507 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2508 [PIPE_FUNC_LESS] = LLVMRealOLT,
2509 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2510 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2511 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2512 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2513 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2514 };
2515 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2516 assert(cond);
2517
2518 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2519 SI_PARAM_ALPHA_REF);
2520 LLVMValueRef alpha_pass =
2521 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2522 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2523 } else {
2524 ac_build_kill_if_false(&ctx->ac, ctx->i1false);
2525 }
2526 }
2527
2528 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2529 LLVMValueRef alpha,
2530 unsigned samplemask_param)
2531 {
2532 struct si_shader_context *ctx = si_shader_context(bld_base);
2533 LLVMValueRef coverage;
2534
2535 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2536 coverage = LLVMGetParam(ctx->main_fn,
2537 samplemask_param);
2538 coverage = ac_to_integer(&ctx->ac, coverage);
2539
2540 coverage = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32",
2541 ctx->i32,
2542 &coverage, 1, AC_FUNC_ATTR_READNONE);
2543
2544 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2545 ctx->f32, "");
2546
2547 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2548 LLVMConstReal(ctx->f32,
2549 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2550
2551 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2552 }
2553
2554 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2555 struct ac_export_args *pos, LLVMValueRef *out_elts)
2556 {
2557 unsigned reg_index;
2558 unsigned chan;
2559 unsigned const_chan;
2560 LLVMValueRef base_elt;
2561 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2562 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2563 SI_VS_CONST_CLIP_PLANES, 0);
2564 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2565
2566 for (reg_index = 0; reg_index < 2; reg_index ++) {
2567 struct ac_export_args *args = &pos[2 + reg_index];
2568
2569 args->out[0] =
2570 args->out[1] =
2571 args->out[2] =
2572 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2573
2574 /* Compute dot products of position and user clip plane vectors */
2575 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2576 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2577 LLVMValueRef addr =
2578 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2579 const_chan) * 4, 0);
2580 base_elt = buffer_load_const(ctx, const_resource,
2581 addr);
2582 args->out[chan] = ac_build_fmad(&ctx->ac, base_elt,
2583 out_elts[const_chan], args->out[chan]);
2584 }
2585 }
2586
2587 args->enabled_channels = 0xf;
2588 args->valid_mask = 0;
2589 args->done = 0;
2590 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2591 args->compr = 0;
2592 }
2593 }
2594
2595 static void si_dump_streamout(struct pipe_stream_output_info *so)
2596 {
2597 unsigned i;
2598
2599 if (so->num_outputs)
2600 fprintf(stderr, "STREAMOUT\n");
2601
2602 for (i = 0; i < so->num_outputs; i++) {
2603 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2604 so->output[i].start_component;
2605 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2606 i, so->output[i].output_buffer,
2607 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2608 so->output[i].register_index,
2609 mask & 1 ? "x" : "",
2610 mask & 2 ? "y" : "",
2611 mask & 4 ? "z" : "",
2612 mask & 8 ? "w" : "");
2613 }
2614 }
2615
2616 static void emit_streamout_output(struct si_shader_context *ctx,
2617 LLVMValueRef const *so_buffers,
2618 LLVMValueRef const *so_write_offsets,
2619 struct pipe_stream_output *stream_out,
2620 struct si_shader_output_values *shader_out)
2621 {
2622 unsigned buf_idx = stream_out->output_buffer;
2623 unsigned start = stream_out->start_component;
2624 unsigned num_comps = stream_out->num_components;
2625 LLVMValueRef out[4];
2626
2627 assert(num_comps && num_comps <= 4);
2628 if (!num_comps || num_comps > 4)
2629 return;
2630
2631 /* Load the output as int. */
2632 for (int j = 0; j < num_comps; j++) {
2633 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2634
2635 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2636 }
2637
2638 /* Pack the output. */
2639 LLVMValueRef vdata = NULL;
2640
2641 switch (num_comps) {
2642 case 1: /* as i32 */
2643 vdata = out[0];
2644 break;
2645 case 2: /* as v2i32 */
2646 case 3: /* as v3i32 */
2647 if (ac_has_vec3_support(ctx->screen->info.chip_class, false)) {
2648 vdata = ac_build_gather_values(&ctx->ac, out, num_comps);
2649 break;
2650 }
2651 /* as v4i32 (aligned to 4) */
2652 out[3] = LLVMGetUndef(ctx->i32);
2653 /* fall through */
2654 case 4: /* as v4i32 */
2655 vdata = ac_build_gather_values(&ctx->ac, out, util_next_power_of_two(num_comps));
2656 break;
2657 }
2658
2659 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2660 vdata, num_comps,
2661 so_write_offsets[buf_idx],
2662 ctx->i32_0,
2663 stream_out->dst_offset * 4, 1, 1, false);
2664 }
2665
2666 /**
2667 * Write streamout data to buffers for vertex stream @p stream (different
2668 * vertex streams can occur for GS copy shaders).
2669 */
2670 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2671 struct si_shader_output_values *outputs,
2672 unsigned noutput, unsigned stream)
2673 {
2674 struct si_shader_selector *sel = ctx->shader->selector;
2675 struct pipe_stream_output_info *so = &sel->so;
2676 LLVMBuilderRef builder = ctx->ac.builder;
2677 int i;
2678 struct lp_build_if_state if_ctx;
2679
2680 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2681 LLVMValueRef so_vtx_count =
2682 si_unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2683
2684 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2685
2686 /* can_emit = tid < so_vtx_count; */
2687 LLVMValueRef can_emit =
2688 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2689
2690 /* Emit the streamout code conditionally. This actually avoids
2691 * out-of-bounds buffer access. The hw tells us via the SGPR
2692 * (so_vtx_count) which threads are allowed to emit streamout data. */
2693 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2694 {
2695 /* The buffer offset is computed as follows:
2696 * ByteOffset = streamout_offset[buffer_id]*4 +
2697 * (streamout_write_index + thread_id)*stride[buffer_id] +
2698 * attrib_offset
2699 */
2700
2701 LLVMValueRef so_write_index =
2702 LLVMGetParam(ctx->main_fn,
2703 ctx->param_streamout_write_index);
2704
2705 /* Compute (streamout_write_index + thread_id). */
2706 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2707
2708 /* Load the descriptor and compute the write offset for each
2709 * enabled buffer. */
2710 LLVMValueRef so_write_offset[4] = {};
2711 LLVMValueRef so_buffers[4];
2712 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2713 ctx->param_rw_buffers);
2714
2715 for (i = 0; i < 4; i++) {
2716 if (!so->stride[i])
2717 continue;
2718
2719 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2720 SI_VS_STREAMOUT_BUF0 + i, 0);
2721
2722 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2723
2724 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2725 ctx->param_streamout_offset[i]);
2726 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2727
2728 so_write_offset[i] = ac_build_imad(&ctx->ac, so_write_index,
2729 LLVMConstInt(ctx->i32, so->stride[i]*4, 0),
2730 so_offset);
2731 }
2732
2733 /* Write streamout data. */
2734 for (i = 0; i < so->num_outputs; i++) {
2735 unsigned reg = so->output[i].register_index;
2736
2737 if (reg >= noutput)
2738 continue;
2739
2740 if (stream != so->output[i].stream)
2741 continue;
2742
2743 emit_streamout_output(ctx, so_buffers, so_write_offset,
2744 &so->output[i], &outputs[reg]);
2745 }
2746 }
2747 lp_build_endif(&if_ctx);
2748 }
2749
2750 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2751 LLVMValueRef *values)
2752 {
2753 struct ac_export_args args;
2754
2755 si_llvm_init_export_args(ctx, values,
2756 V_008DFC_SQ_EXP_PARAM + index, &args);
2757 ac_build_export(&ctx->ac, &args);
2758 }
2759
2760 static void si_build_param_exports(struct si_shader_context *ctx,
2761 struct si_shader_output_values *outputs,
2762 unsigned noutput)
2763 {
2764 struct si_shader *shader = ctx->shader;
2765 unsigned param_count = 0;
2766
2767 for (unsigned i = 0; i < noutput; i++) {
2768 unsigned semantic_name = outputs[i].semantic_name;
2769 unsigned semantic_index = outputs[i].semantic_index;
2770
2771 if (outputs[i].vertex_stream[0] != 0 &&
2772 outputs[i].vertex_stream[1] != 0 &&
2773 outputs[i].vertex_stream[2] != 0 &&
2774 outputs[i].vertex_stream[3] != 0)
2775 continue;
2776
2777 switch (semantic_name) {
2778 case TGSI_SEMANTIC_LAYER:
2779 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2780 case TGSI_SEMANTIC_CLIPDIST:
2781 case TGSI_SEMANTIC_COLOR:
2782 case TGSI_SEMANTIC_BCOLOR:
2783 case TGSI_SEMANTIC_PRIMID:
2784 case TGSI_SEMANTIC_FOG:
2785 case TGSI_SEMANTIC_TEXCOORD:
2786 case TGSI_SEMANTIC_GENERIC:
2787 break;
2788 default:
2789 continue;
2790 }
2791
2792 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2793 semantic_index < SI_MAX_IO_GENERIC) &&
2794 shader->key.opt.kill_outputs &
2795 (1ull << si_shader_io_get_unique_index(semantic_name,
2796 semantic_index, true)))
2797 continue;
2798
2799 si_export_param(ctx, param_count, outputs[i].values);
2800
2801 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2802 shader->info.vs_output_param_offset[i] = param_count++;
2803 }
2804
2805 shader->info.nr_param_exports = param_count;
2806 }
2807
2808 /**
2809 * Vertex color clamping.
2810 *
2811 * This uses a state constant loaded in a user data SGPR and
2812 * an IF statement is added that clamps all colors if the constant
2813 * is true.
2814 */
2815 static void si_vertex_color_clamping(struct si_shader_context *ctx,
2816 struct si_shader_output_values *outputs,
2817 unsigned noutput)
2818 {
2819 LLVMValueRef addr[SI_MAX_VS_OUTPUTS][4];
2820 bool has_colors = false;
2821
2822 /* Store original colors to alloca variables. */
2823 for (unsigned i = 0; i < noutput; i++) {
2824 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2825 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2826 continue;
2827
2828 for (unsigned j = 0; j < 4; j++) {
2829 addr[i][j] = ac_build_alloca_undef(&ctx->ac, ctx->f32, "");
2830 LLVMBuildStore(ctx->ac.builder, outputs[i].values[j], addr[i][j]);
2831 }
2832 has_colors = true;
2833 }
2834
2835 if (!has_colors)
2836 return;
2837
2838 /* The state is in the first bit of the user SGPR. */
2839 LLVMValueRef cond = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
2840 cond = LLVMBuildTrunc(ctx->ac.builder, cond, ctx->i1, "");
2841
2842 struct lp_build_if_state if_ctx;
2843 lp_build_if(&if_ctx, &ctx->gallivm, cond);
2844
2845 /* Store clamped colors to alloca variables within the conditional block. */
2846 for (unsigned i = 0; i < noutput; i++) {
2847 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2848 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2849 continue;
2850
2851 for (unsigned j = 0; j < 4; j++) {
2852 LLVMBuildStore(ctx->ac.builder,
2853 ac_build_clamp(&ctx->ac, outputs[i].values[j]),
2854 addr[i][j]);
2855 }
2856 }
2857 lp_build_endif(&if_ctx);
2858
2859 /* Load clamped colors */
2860 for (unsigned i = 0; i < noutput; i++) {
2861 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2862 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2863 continue;
2864
2865 for (unsigned j = 0; j < 4; j++) {
2866 outputs[i].values[j] =
2867 LLVMBuildLoad(ctx->ac.builder, addr[i][j], "");
2868 }
2869 }
2870 }
2871
2872 /* Generate export instructions for hardware VS shader stage */
2873 static void si_llvm_export_vs(struct si_shader_context *ctx,
2874 struct si_shader_output_values *outputs,
2875 unsigned noutput)
2876 {
2877 struct si_shader *shader = ctx->shader;
2878 struct ac_export_args pos_args[4] = {};
2879 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2880 unsigned pos_idx;
2881 int i;
2882
2883 si_vertex_color_clamping(ctx, outputs, noutput);
2884
2885 /* Build position exports. */
2886 for (i = 0; i < noutput; i++) {
2887 switch (outputs[i].semantic_name) {
2888 case TGSI_SEMANTIC_POSITION:
2889 si_llvm_init_export_args(ctx, outputs[i].values,
2890 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2891 break;
2892 case TGSI_SEMANTIC_PSIZE:
2893 psize_value = outputs[i].values[0];
2894 break;
2895 case TGSI_SEMANTIC_LAYER:
2896 layer_value = outputs[i].values[0];
2897 break;
2898 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2899 viewport_index_value = outputs[i].values[0];
2900 break;
2901 case TGSI_SEMANTIC_EDGEFLAG:
2902 edgeflag_value = outputs[i].values[0];
2903 break;
2904 case TGSI_SEMANTIC_CLIPDIST:
2905 if (!shader->key.opt.clip_disable) {
2906 unsigned index = 2 + outputs[i].semantic_index;
2907 si_llvm_init_export_args(ctx, outputs[i].values,
2908 V_008DFC_SQ_EXP_POS + index,
2909 &pos_args[index]);
2910 }
2911 break;
2912 case TGSI_SEMANTIC_CLIPVERTEX:
2913 if (!shader->key.opt.clip_disable) {
2914 si_llvm_emit_clipvertex(ctx, pos_args,
2915 outputs[i].values);
2916 }
2917 break;
2918 }
2919 }
2920
2921 /* We need to add the position output manually if it's missing. */
2922 if (!pos_args[0].out[0]) {
2923 pos_args[0].enabled_channels = 0xf; /* writemask */
2924 pos_args[0].valid_mask = 0; /* EXEC mask */
2925 pos_args[0].done = 0; /* last export? */
2926 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2927 pos_args[0].compr = 0; /* COMPR flag */
2928 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2929 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2930 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2931 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2932 }
2933
2934 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2935 if (shader->selector->info.writes_psize ||
2936 shader->selector->info.writes_edgeflag ||
2937 shader->selector->info.writes_viewport_index ||
2938 shader->selector->info.writes_layer) {
2939 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2940 (shader->selector->info.writes_edgeflag << 1) |
2941 (shader->selector->info.writes_layer << 2);
2942
2943 pos_args[1].valid_mask = 0; /* EXEC mask */
2944 pos_args[1].done = 0; /* last export? */
2945 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2946 pos_args[1].compr = 0; /* COMPR flag */
2947 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2948 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2949 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2950 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2951
2952 if (shader->selector->info.writes_psize)
2953 pos_args[1].out[0] = psize_value;
2954
2955 if (shader->selector->info.writes_edgeflag) {
2956 /* The output is a float, but the hw expects an integer
2957 * with the first bit containing the edge flag. */
2958 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2959 edgeflag_value,
2960 ctx->i32, "");
2961 edgeflag_value = ac_build_umin(&ctx->ac,
2962 edgeflag_value,
2963 ctx->i32_1);
2964
2965 /* The LLVM intrinsic expects a float. */
2966 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2967 }
2968
2969 if (ctx->screen->info.chip_class >= GFX9) {
2970 /* GFX9 has the layer in out.z[10:0] and the viewport
2971 * index in out.z[19:16].
2972 */
2973 if (shader->selector->info.writes_layer)
2974 pos_args[1].out[2] = layer_value;
2975
2976 if (shader->selector->info.writes_viewport_index) {
2977 LLVMValueRef v = viewport_index_value;
2978
2979 v = ac_to_integer(&ctx->ac, v);
2980 v = LLVMBuildShl(ctx->ac.builder, v,
2981 LLVMConstInt(ctx->i32, 16, 0), "");
2982 v = LLVMBuildOr(ctx->ac.builder, v,
2983 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2984 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2985 pos_args[1].enabled_channels |= 1 << 2;
2986 }
2987 } else {
2988 if (shader->selector->info.writes_layer)
2989 pos_args[1].out[2] = layer_value;
2990
2991 if (shader->selector->info.writes_viewport_index) {
2992 pos_args[1].out[3] = viewport_index_value;
2993 pos_args[1].enabled_channels |= 1 << 3;
2994 }
2995 }
2996 }
2997
2998 for (i = 0; i < 4; i++)
2999 if (pos_args[i].out[0])
3000 shader->info.nr_pos_exports++;
3001
3002 pos_idx = 0;
3003 for (i = 0; i < 4; i++) {
3004 if (!pos_args[i].out[0])
3005 continue;
3006
3007 /* Specify the target we are exporting */
3008 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
3009
3010 if (pos_idx == shader->info.nr_pos_exports)
3011 /* Specify that this is the last export */
3012 pos_args[i].done = 1;
3013
3014 ac_build_export(&ctx->ac, &pos_args[i]);
3015 }
3016
3017 /* Build parameter exports. */
3018 si_build_param_exports(ctx, outputs, noutput);
3019 }
3020
3021 /**
3022 * Forward all outputs from the vertex shader to the TES. This is only used
3023 * for the fixed function TCS.
3024 */
3025 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
3026 {
3027 struct si_shader_context *ctx = si_shader_context(bld_base);
3028 LLVMValueRef invocation_id, buffer, buffer_offset;
3029 LLVMValueRef lds_vertex_stride, lds_base;
3030 uint64_t inputs;
3031
3032 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3033 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3034 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3035
3036 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
3037 lds_base = get_tcs_in_current_patch_offset(ctx);
3038 lds_base = ac_build_imad(&ctx->ac, invocation_id, lds_vertex_stride,
3039 lds_base);
3040
3041 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
3042 while (inputs) {
3043 unsigned i = u_bit_scan64(&inputs);
3044
3045 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
3046 LLVMConstInt(ctx->i32, 4 * i, 0),
3047 "");
3048
3049 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
3050 get_rel_patch_id(ctx),
3051 invocation_id,
3052 LLVMConstInt(ctx->i32, i, 0));
3053
3054 LLVMValueRef value = lshs_lds_load(bld_base, ctx->ac.i32, ~0, lds_ptr);
3055
3056 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
3057 buffer_offset, 0, 1, 0, false);
3058 }
3059 }
3060
3061 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
3062 LLVMValueRef rel_patch_id,
3063 LLVMValueRef invocation_id,
3064 LLVMValueRef tcs_out_current_patch_data_offset,
3065 LLVMValueRef invoc0_tf_outer[4],
3066 LLVMValueRef invoc0_tf_inner[2])
3067 {
3068 struct si_shader_context *ctx = si_shader_context(bld_base);
3069 struct si_shader *shader = ctx->shader;
3070 unsigned tess_inner_index, tess_outer_index;
3071 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
3072 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3073 unsigned stride, outer_comps, inner_comps, i, offset;
3074 struct lp_build_if_state if_ctx, inner_if_ctx;
3075
3076 /* Add a barrier before loading tess factors from LDS. */
3077 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
3078 si_llvm_emit_barrier(NULL, bld_base, NULL);
3079
3080 /* Do this only for invocation 0, because the tess levels are per-patch,
3081 * not per-vertex.
3082 *
3083 * This can't jump, because invocation 0 executes this. It should
3084 * at least mask out the loads and stores for other invocations.
3085 */
3086 lp_build_if(&if_ctx, &ctx->gallivm,
3087 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3088 invocation_id, ctx->i32_0, ""));
3089
3090 /* Determine the layout of one tess factor element in the buffer. */
3091 switch (shader->key.part.tcs.epilog.prim_mode) {
3092 case PIPE_PRIM_LINES:
3093 stride = 2; /* 2 dwords, 1 vec2 store */
3094 outer_comps = 2;
3095 inner_comps = 0;
3096 break;
3097 case PIPE_PRIM_TRIANGLES:
3098 stride = 4; /* 4 dwords, 1 vec4 store */
3099 outer_comps = 3;
3100 inner_comps = 1;
3101 break;
3102 case PIPE_PRIM_QUADS:
3103 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3104 outer_comps = 4;
3105 inner_comps = 2;
3106 break;
3107 default:
3108 assert(0);
3109 return;
3110 }
3111
3112 for (i = 0; i < 4; i++) {
3113 inner[i] = LLVMGetUndef(ctx->i32);
3114 outer[i] = LLVMGetUndef(ctx->i32);
3115 }
3116
3117 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3118 /* Tess factors are in VGPRs. */
3119 for (i = 0; i < outer_comps; i++)
3120 outer[i] = out[i] = invoc0_tf_outer[i];
3121 for (i = 0; i < inner_comps; i++)
3122 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3123 } else {
3124 /* Load tess_inner and tess_outer from LDS.
3125 * Any invocation can write them, so we can't get them from a temporary.
3126 */
3127 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3128 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3129
3130 lds_base = tcs_out_current_patch_data_offset;
3131 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3132 LLVMConstInt(ctx->i32,
3133 tess_inner_index * 4, 0), "");
3134 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3135 LLVMConstInt(ctx->i32,
3136 tess_outer_index * 4, 0), "");
3137
3138 for (i = 0; i < outer_comps; i++) {
3139 outer[i] = out[i] =
3140 lshs_lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3141 }
3142 for (i = 0; i < inner_comps; i++) {
3143 inner[i] = out[outer_comps+i] =
3144 lshs_lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3145 }
3146 }
3147
3148 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3149 /* For isolines, the hardware expects tess factors in the
3150 * reverse order from what GLSL / TGSI specify.
3151 */
3152 LLVMValueRef tmp = out[0];
3153 out[0] = out[1];
3154 out[1] = tmp;
3155 }
3156
3157 /* Convert the outputs to vectors for stores. */
3158 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3159 vec1 = NULL;
3160
3161 if (stride > 4)
3162 vec1 = ac_build_gather_values(&ctx->ac, out+4, stride - 4);
3163
3164 /* Get the buffer. */
3165 buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
3166
3167 /* Get the offset. */
3168 tf_base = LLVMGetParam(ctx->main_fn,
3169 ctx->param_tcs_factor_offset);
3170 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3171 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3172
3173 lp_build_if(&inner_if_ctx, &ctx->gallivm,
3174 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3175 rel_patch_id, ctx->i32_0, ""));
3176
3177 /* Store the dynamic HS control word. */
3178 offset = 0;
3179 if (ctx->screen->info.chip_class <= GFX8) {
3180 ac_build_buffer_store_dword(&ctx->ac, buffer,
3181 LLVMConstInt(ctx->i32, 0x80000000, 0),
3182 1, ctx->i32_0, tf_base,
3183 offset, 1, 0, false);
3184 offset += 4;
3185 }
3186
3187 lp_build_endif(&inner_if_ctx);
3188
3189 /* Store the tessellation factors. */
3190 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3191 MIN2(stride, 4), byteoffset, tf_base,
3192 offset, 1, 0, false);
3193 offset += 16;
3194 if (vec1)
3195 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3196 stride - 4, byteoffset, tf_base,
3197 offset, 1, 0, false);
3198
3199 /* Store the tess factors into the offchip buffer if TES reads them. */
3200 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3201 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3202 LLVMValueRef tf_inner_offset;
3203 unsigned param_outer, param_inner;
3204
3205 buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3206 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3207
3208 param_outer = si_shader_io_get_unique_index_patch(
3209 TGSI_SEMANTIC_TESSOUTER, 0);
3210 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3211 LLVMConstInt(ctx->i32, param_outer, 0));
3212
3213 unsigned outer_vec_size =
3214 ac_has_vec3_support(ctx->screen->info.chip_class, false) ?
3215 outer_comps : util_next_power_of_two(outer_comps);
3216 outer_vec = ac_build_gather_values(&ctx->ac, outer, outer_vec_size);
3217
3218 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3219 outer_comps, tf_outer_offset,
3220 base, 0, 1, 0, false);
3221 if (inner_comps) {
3222 param_inner = si_shader_io_get_unique_index_patch(
3223 TGSI_SEMANTIC_TESSINNER, 0);
3224 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3225 LLVMConstInt(ctx->i32, param_inner, 0));
3226
3227 inner_vec = inner_comps == 1 ? inner[0] :
3228 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3229 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3230 inner_comps, tf_inner_offset,
3231 base, 0, 1, 0, false);
3232 }
3233 }
3234
3235 lp_build_endif(&if_ctx);
3236 }
3237
3238 static LLVMValueRef
3239 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3240 unsigned param, unsigned return_index)
3241 {
3242 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3243 LLVMGetParam(ctx->main_fn, param),
3244 return_index, "");
3245 }
3246
3247 static LLVMValueRef
3248 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3249 unsigned param, unsigned return_index)
3250 {
3251 LLVMBuilderRef builder = ctx->ac.builder;
3252 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3253
3254 return LLVMBuildInsertValue(builder, ret,
3255 ac_to_float(&ctx->ac, p),
3256 return_index, "");
3257 }
3258
3259 static LLVMValueRef
3260 si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret,
3261 unsigned param, unsigned return_index)
3262 {
3263 LLVMBuilderRef builder = ctx->ac.builder;
3264 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, param);
3265 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i32, "");
3266 return LLVMBuildInsertValue(builder, ret, ptr, return_index, "");
3267 }
3268
3269 /* This only writes the tessellation factor levels. */
3270 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
3271 unsigned max_outputs,
3272 LLVMValueRef *addrs)
3273 {
3274 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3275 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
3276 LLVMBuilderRef builder = ctx->ac.builder;
3277 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3278
3279 si_copy_tcs_inputs(bld_base);
3280
3281 rel_patch_id = get_rel_patch_id(ctx);
3282 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3283 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3284
3285 if (ctx->screen->info.chip_class >= GFX9) {
3286 LLVMBasicBlockRef blocks[2] = {
3287 LLVMGetInsertBlock(builder),
3288 ctx->merged_wrap_if_state.entry_block
3289 };
3290 LLVMValueRef values[2];
3291
3292 lp_build_endif(&ctx->merged_wrap_if_state);
3293
3294 values[0] = rel_patch_id;
3295 values[1] = LLVMGetUndef(ctx->i32);
3296 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3297
3298 values[0] = tf_lds_offset;
3299 values[1] = LLVMGetUndef(ctx->i32);
3300 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3301
3302 values[0] = invocation_id;
3303 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3304 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3305 }
3306
3307 /* Return epilog parameters from this function. */
3308 LLVMValueRef ret = ctx->return_value;
3309 unsigned vgpr;
3310
3311 if (ctx->screen->info.chip_class >= GFX9) {
3312 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3313 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3314 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3315 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3316 /* Tess offchip and tess factor offsets are at the beginning. */
3317 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3318 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3319 vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
3320 } else {
3321 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3322 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3323 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3324 GFX6_SGPR_TCS_OUT_LAYOUT);
3325 /* Tess offchip and tess factor offsets are after user SGPRs. */
3326 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3327 GFX6_TCS_NUM_USER_SGPR);
3328 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3329 GFX6_TCS_NUM_USER_SGPR + 1);
3330 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3331 }
3332
3333 /* VGPRs */
3334 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3335 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3336 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3337
3338 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3339 * the invocation_id output does not alias the tcs_rel_ids input,
3340 * which saves a V_MOV on gfx9.
3341 */
3342 vgpr += 2;
3343
3344 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3345 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3346
3347 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3348 vgpr++; /* skip the tess factor LDS offset */
3349 for (unsigned i = 0; i < 6; i++) {
3350 LLVMValueRef value =
3351 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3352 value = ac_to_float(&ctx->ac, value);
3353 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3354 }
3355 } else {
3356 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3357 }
3358 ctx->return_value = ret;
3359 }
3360
3361 /* Pass TCS inputs from LS to TCS on GFX9. */
3362 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3363 {
3364 LLVMValueRef ret = ctx->return_value;
3365
3366 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3367 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3368 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3369 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3370 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3371 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3372
3373 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3374 8 + SI_SGPR_RW_BUFFERS);
3375 ret = si_insert_input_ptr(ctx, ret,
3376 ctx->param_bindless_samplers_and_images,
3377 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3378
3379 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3380 8 + SI_SGPR_VS_STATE_BITS);
3381
3382 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3383 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3384 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3385 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3386 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3387 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3388
3389 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3390 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3391 ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
3392 vgpr++, "");
3393 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3394 ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
3395 vgpr++, "");
3396 ctx->return_value = ret;
3397 }
3398
3399 /* Pass GS inputs from ES to GS on GFX9. */
3400 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3401 {
3402 LLVMValueRef ret = ctx->return_value;
3403
3404 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3405 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3406 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3407 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3408 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3409
3410 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3411 8 + SI_SGPR_RW_BUFFERS);
3412 ret = si_insert_input_ptr(ctx, ret,
3413 ctx->param_bindless_samplers_and_images,
3414 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3415
3416 unsigned vgpr;
3417 if (ctx->type == PIPE_SHADER_VERTEX)
3418 vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
3419 else
3420 vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
3421
3422 for (unsigned i = 0; i < 5; i++) {
3423 unsigned param = ctx->param_gs_vtx01_offset + i;
3424 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3425 }
3426 ctx->return_value = ret;
3427 }
3428
3429 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3430 unsigned max_outputs,
3431 LLVMValueRef *addrs)
3432 {
3433 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3434 struct si_shader *shader = ctx->shader;
3435 struct tgsi_shader_info *info = &shader->selector->info;
3436 unsigned i, chan;
3437 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3438 ctx->param_rel_auto_id);
3439 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3440 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3441 vertex_dw_stride, "");
3442
3443 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3444 * its inputs from it. */
3445 for (i = 0; i < info->num_outputs; i++) {
3446 unsigned name = info->output_semantic_name[i];
3447 unsigned index = info->output_semantic_index[i];
3448
3449 /* The ARB_shader_viewport_layer_array spec contains the
3450 * following issue:
3451 *
3452 * 2) What happens if gl_ViewportIndex or gl_Layer is
3453 * written in the vertex shader and a geometry shader is
3454 * present?
3455 *
3456 * RESOLVED: The value written by the last vertex processing
3457 * stage is used. If the last vertex processing stage
3458 * (vertex, tessellation evaluation or geometry) does not
3459 * statically assign to gl_ViewportIndex or gl_Layer, index
3460 * or layer zero is assumed.
3461 *
3462 * So writes to those outputs in VS-as-LS are simply ignored.
3463 */
3464 if (name == TGSI_SEMANTIC_LAYER ||
3465 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3466 continue;
3467
3468 int param = si_shader_io_get_unique_index(name, index, false);
3469 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3470 LLVMConstInt(ctx->i32, param * 4, 0), "");
3471
3472 for (chan = 0; chan < 4; chan++) {
3473 if (!(info->output_usagemask[i] & (1 << chan)))
3474 continue;
3475
3476 lshs_lds_store(ctx, chan, dw_addr,
3477 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3478 }
3479 }
3480
3481 if (ctx->screen->info.chip_class >= GFX9)
3482 si_set_ls_return_value_for_tcs(ctx);
3483 }
3484
3485 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3486 unsigned max_outputs,
3487 LLVMValueRef *addrs)
3488 {
3489 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3490 struct si_shader *es = ctx->shader;
3491 struct tgsi_shader_info *info = &es->selector->info;
3492 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3493 ctx->param_es2gs_offset);
3494 LLVMValueRef lds_base = NULL;
3495 unsigned chan;
3496 int i;
3497
3498 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3499 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3500 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3501 LLVMValueRef wave_idx = si_unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3502 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3503 LLVMBuildMul(ctx->ac.builder, wave_idx,
3504 LLVMConstInt(ctx->i32, 64, false), ""), "");
3505 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3506 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3507 }
3508
3509 for (i = 0; i < info->num_outputs; i++) {
3510 int param;
3511
3512 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3513 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3514 continue;
3515
3516 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3517 info->output_semantic_index[i], false);
3518
3519 for (chan = 0; chan < 4; chan++) {
3520 if (!(info->output_usagemask[i] & (1 << chan)))
3521 continue;
3522
3523 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3524 out_val = ac_to_integer(&ctx->ac, out_val);
3525
3526 /* GFX9 has the ESGS ring in LDS. */
3527 if (ctx->screen->info.chip_class >= GFX9) {
3528 LLVMValueRef idx = LLVMConstInt(ctx->i32, param * 4 + chan, false);
3529 idx = LLVMBuildAdd(ctx->ac.builder, lds_base, idx, "");
3530 ac_build_indexed_store(&ctx->ac, ctx->esgs_ring, idx, out_val);
3531 continue;
3532 }
3533
3534 ac_build_buffer_store_dword(&ctx->ac,
3535 ctx->esgs_ring,
3536 out_val, 1, NULL, soffset,
3537 (4 * param + chan) * 4,
3538 1, 1, true);
3539 }
3540 }
3541
3542 if (ctx->screen->info.chip_class >= GFX9)
3543 si_set_es_return_value_for_gs(ctx);
3544 }
3545
3546 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3547 {
3548 if (ctx->screen->info.chip_class >= GFX9)
3549 return si_unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3550 else
3551 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3552 }
3553
3554 static void emit_gs_epilogue(struct si_shader_context *ctx)
3555 {
3556 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3557 si_get_gs_wave_id(ctx));
3558
3559 if (ctx->screen->info.chip_class >= GFX9)
3560 lp_build_endif(&ctx->merged_wrap_if_state);
3561 }
3562
3563 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3564 unsigned max_outputs,
3565 LLVMValueRef *addrs)
3566 {
3567 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3568 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3569
3570 assert(info->num_outputs <= max_outputs);
3571
3572 emit_gs_epilogue(ctx);
3573 }
3574
3575 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3576 {
3577 struct si_shader_context *ctx = si_shader_context(bld_base);
3578 emit_gs_epilogue(ctx);
3579 }
3580
3581 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3582 unsigned max_outputs,
3583 LLVMValueRef *addrs)
3584 {
3585 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3586 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3587 struct si_shader_output_values *outputs = NULL;
3588 int i,j;
3589
3590 assert(!ctx->shader->is_gs_copy_shader);
3591 assert(info->num_outputs <= max_outputs);
3592
3593 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3594
3595 for (i = 0; i < info->num_outputs; i++) {
3596 outputs[i].semantic_name = info->output_semantic_name[i];
3597 outputs[i].semantic_index = info->output_semantic_index[i];
3598
3599 for (j = 0; j < 4; j++) {
3600 outputs[i].values[j] =
3601 LLVMBuildLoad(ctx->ac.builder,
3602 addrs[4 * i + j],
3603 "");
3604 outputs[i].vertex_stream[j] =
3605 (info->output_streams[i] >> (2 * j)) & 3;
3606 }
3607 }
3608
3609 if (ctx->shader->selector->so.num_outputs)
3610 si_llvm_emit_streamout(ctx, outputs, i, 0);
3611
3612 /* Export PrimitiveID. */
3613 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3614 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3615 outputs[i].semantic_index = 0;
3616 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3617 for (j = 1; j < 4; j++)
3618 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3619
3620 memset(outputs[i].vertex_stream, 0,
3621 sizeof(outputs[i].vertex_stream));
3622 i++;
3623 }
3624
3625 si_llvm_export_vs(ctx, outputs, i);
3626 FREE(outputs);
3627 }
3628
3629 static void si_llvm_emit_prim_discard_cs_epilogue(struct ac_shader_abi *abi,
3630 unsigned max_outputs,
3631 LLVMValueRef *addrs)
3632 {
3633 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3634 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3635 LLVMValueRef pos[4] = {};
3636
3637 assert(info->num_outputs <= max_outputs);
3638
3639 for (unsigned i = 0; i < info->num_outputs; i++) {
3640 if (info->output_semantic_name[i] != TGSI_SEMANTIC_POSITION)
3641 continue;
3642
3643 for (unsigned chan = 0; chan < 4; chan++)
3644 pos[chan] = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3645 break;
3646 }
3647 assert(pos[0] != NULL);
3648
3649 /* Return the position output. */
3650 LLVMValueRef ret = ctx->return_value;
3651 for (unsigned chan = 0; chan < 4; chan++)
3652 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, pos[chan], chan, "");
3653 ctx->return_value = ret;
3654 }
3655
3656 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3657 {
3658 struct si_shader_context *ctx = si_shader_context(bld_base);
3659
3660 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3661 &ctx->outputs[0][0]);
3662 }
3663
3664 struct si_ps_exports {
3665 unsigned num;
3666 struct ac_export_args args[10];
3667 };
3668
3669 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3670 LLVMValueRef depth, LLVMValueRef stencil,
3671 LLVMValueRef samplemask, struct si_ps_exports *exp)
3672 {
3673 struct si_shader_context *ctx = si_shader_context(bld_base);
3674 struct ac_export_args args;
3675
3676 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3677
3678 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3679 }
3680
3681 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3682 LLVMValueRef *color, unsigned index,
3683 unsigned samplemask_param,
3684 bool is_last, struct si_ps_exports *exp)
3685 {
3686 struct si_shader_context *ctx = si_shader_context(bld_base);
3687 int i;
3688
3689 /* Clamp color */
3690 if (ctx->shader->key.part.ps.epilog.clamp_color)
3691 for (i = 0; i < 4; i++)
3692 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3693
3694 /* Alpha to one */
3695 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3696 color[3] = ctx->ac.f32_1;
3697
3698 /* Alpha test */
3699 if (index == 0 &&
3700 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3701 si_alpha_test(bld_base, color[3]);
3702
3703 /* Line & polygon smoothing */
3704 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3705 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3706 samplemask_param);
3707
3708 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3709 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3710 struct ac_export_args args[8];
3711 int c, last = -1;
3712
3713 /* Get the export arguments, also find out what the last one is. */
3714 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3715 si_llvm_init_export_args(ctx, color,
3716 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3717 if (args[c].enabled_channels)
3718 last = c;
3719 }
3720
3721 /* Emit all exports. */
3722 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3723 if (is_last && last == c) {
3724 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3725 args[c].done = 1; /* DONE bit */
3726 } else if (!args[c].enabled_channels)
3727 continue; /* unnecessary NULL export */
3728
3729 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3730 }
3731 } else {
3732 struct ac_export_args args;
3733
3734 /* Export */
3735 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3736 &args);
3737 if (is_last) {
3738 args.valid_mask = 1; /* whether the EXEC mask is valid */
3739 args.done = 1; /* DONE bit */
3740 } else if (!args.enabled_channels)
3741 return; /* unnecessary NULL export */
3742
3743 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3744 }
3745 }
3746
3747 static void si_emit_ps_exports(struct si_shader_context *ctx,
3748 struct si_ps_exports *exp)
3749 {
3750 for (unsigned i = 0; i < exp->num; i++)
3751 ac_build_export(&ctx->ac, &exp->args[i]);
3752 }
3753
3754 /**
3755 * Return PS outputs in this order:
3756 *
3757 * v[0:3] = color0.xyzw
3758 * v[4:7] = color1.xyzw
3759 * ...
3760 * vN+0 = Depth
3761 * vN+1 = Stencil
3762 * vN+2 = SampleMask
3763 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3764 *
3765 * The alpha-ref SGPR is returned via its original location.
3766 */
3767 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3768 unsigned max_outputs,
3769 LLVMValueRef *addrs)
3770 {
3771 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3772 struct si_shader *shader = ctx->shader;
3773 struct tgsi_shader_info *info = &shader->selector->info;
3774 LLVMBuilderRef builder = ctx->ac.builder;
3775 unsigned i, j, first_vgpr, vgpr;
3776
3777 LLVMValueRef color[8][4] = {};
3778 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3779 LLVMValueRef ret;
3780
3781 if (ctx->postponed_kill)
3782 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3783
3784 /* Read the output values. */
3785 for (i = 0; i < info->num_outputs; i++) {
3786 unsigned semantic_name = info->output_semantic_name[i];
3787 unsigned semantic_index = info->output_semantic_index[i];
3788
3789 switch (semantic_name) {
3790 case TGSI_SEMANTIC_COLOR:
3791 assert(semantic_index < 8);
3792 for (j = 0; j < 4; j++) {
3793 LLVMValueRef ptr = addrs[4 * i + j];
3794 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3795 color[semantic_index][j] = result;
3796 }
3797 break;
3798 case TGSI_SEMANTIC_POSITION:
3799 depth = LLVMBuildLoad(builder,
3800 addrs[4 * i + 2], "");
3801 break;
3802 case TGSI_SEMANTIC_STENCIL:
3803 stencil = LLVMBuildLoad(builder,
3804 addrs[4 * i + 1], "");
3805 break;
3806 case TGSI_SEMANTIC_SAMPLEMASK:
3807 samplemask = LLVMBuildLoad(builder,
3808 addrs[4 * i + 0], "");
3809 break;
3810 default:
3811 fprintf(stderr, "Warning: GFX6 unhandled fs output type:%d\n",
3812 semantic_name);
3813 }
3814 }
3815
3816 /* Fill the return structure. */
3817 ret = ctx->return_value;
3818
3819 /* Set SGPRs. */
3820 ret = LLVMBuildInsertValue(builder, ret,
3821 ac_to_integer(&ctx->ac,
3822 LLVMGetParam(ctx->main_fn,
3823 SI_PARAM_ALPHA_REF)),
3824 SI_SGPR_ALPHA_REF, "");
3825
3826 /* Set VGPRs */
3827 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3828 for (i = 0; i < ARRAY_SIZE(color); i++) {
3829 if (!color[i][0])
3830 continue;
3831
3832 for (j = 0; j < 4; j++)
3833 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3834 }
3835 if (depth)
3836 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3837 if (stencil)
3838 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3839 if (samplemask)
3840 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3841
3842 /* Add the input sample mask for smoothing at the end. */
3843 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3844 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3845 ret = LLVMBuildInsertValue(builder, ret,
3846 LLVMGetParam(ctx->main_fn,
3847 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3848
3849 ctx->return_value = ret;
3850 }
3851
3852 static void membar_emit(
3853 const struct lp_build_tgsi_action *action,
3854 struct lp_build_tgsi_context *bld_base,
3855 struct lp_build_emit_data *emit_data)
3856 {
3857 struct si_shader_context *ctx = si_shader_context(bld_base);
3858 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3859 unsigned flags = LLVMConstIntGetZExtValue(src0);
3860 unsigned waitcnt = NOOP_WAITCNT;
3861
3862 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3863 waitcnt &= VM_CNT & LGKM_CNT;
3864
3865 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3866 TGSI_MEMBAR_SHADER_BUFFER |
3867 TGSI_MEMBAR_SHADER_IMAGE))
3868 waitcnt &= VM_CNT;
3869
3870 if (flags & TGSI_MEMBAR_SHARED)
3871 waitcnt &= LGKM_CNT;
3872
3873 if (waitcnt != NOOP_WAITCNT)
3874 ac_build_waitcnt(&ctx->ac, waitcnt);
3875 }
3876
3877 static void clock_emit(
3878 const struct lp_build_tgsi_action *action,
3879 struct lp_build_tgsi_context *bld_base,
3880 struct lp_build_emit_data *emit_data)
3881 {
3882 struct si_shader_context *ctx = si_shader_context(bld_base);
3883 LLVMValueRef tmp = ac_build_shader_clock(&ctx->ac);
3884
3885 emit_data->output[0] =
3886 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3887 emit_data->output[1] =
3888 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3889 }
3890
3891 static void si_llvm_emit_ddxy(
3892 const struct lp_build_tgsi_action *action,
3893 struct lp_build_tgsi_context *bld_base,
3894 struct lp_build_emit_data *emit_data)
3895 {
3896 struct si_shader_context *ctx = si_shader_context(bld_base);
3897 unsigned opcode = emit_data->info->opcode;
3898 LLVMValueRef val;
3899 int idx;
3900 unsigned mask;
3901
3902 if (opcode == TGSI_OPCODE_DDX_FINE)
3903 mask = AC_TID_MASK_LEFT;
3904 else if (opcode == TGSI_OPCODE_DDY_FINE)
3905 mask = AC_TID_MASK_TOP;
3906 else
3907 mask = AC_TID_MASK_TOP_LEFT;
3908
3909 /* for DDX we want to next X pixel, DDY next Y pixel. */
3910 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3911
3912 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3913 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3914 emit_data->output[emit_data->chan] = val;
3915 }
3916
3917 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3918 struct lp_build_tgsi_context *bld_base,
3919 struct lp_build_emit_data *emit_data)
3920 {
3921 struct si_shader_context *ctx = si_shader_context(bld_base);
3922 struct si_shader *shader = ctx->shader;
3923 const struct tgsi_shader_info *info = &shader->selector->info;
3924 LLVMValueRef interp_param;
3925 const struct tgsi_full_instruction *inst = emit_data->inst;
3926 const struct tgsi_full_src_register *input = &inst->Src[0];
3927 int input_base, input_array_size;
3928 int chan;
3929 int i;
3930 LLVMValueRef prim_mask = ctx->abi.prim_mask;
3931 LLVMValueRef array_idx, offset_x = NULL, offset_y = NULL;
3932 int interp_param_idx;
3933 unsigned interp;
3934 unsigned location;
3935
3936 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3937 /* offset is in second src, first two channels */
3938 offset_x = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
3939 TGSI_CHAN_X);
3940 offset_y = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
3941 TGSI_CHAN_Y);
3942 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3943 LLVMValueRef sample_position;
3944 LLVMValueRef sample_id;
3945 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3946
3947 /* fetch sample ID, then fetch its sample position,
3948 * and place into first two channels.
3949 */
3950 sample_id = lp_build_emit_fetch(bld_base,
3951 emit_data->inst, 1, TGSI_CHAN_X);
3952 sample_id = ac_to_integer(&ctx->ac, sample_id);
3953
3954 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
3955 * Language 4.50 spec says about interpolateAtSample:
3956 *
3957 * "Returns the value of the input interpolant variable at
3958 * the location of sample number sample. If multisample
3959 * buffers are not available, the input variable will be
3960 * evaluated at the center of the pixel. If sample sample
3961 * does not exist, the position used to interpolate the
3962 * input variable is undefined."
3963 *
3964 * This means that sample_id values outside of the valid are
3965 * in fact valid input, and the usual mechanism for loading the
3966 * sample position doesn't work.
3967 */
3968 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
3969 LLVMValueRef center[4] = {
3970 LLVMConstReal(ctx->f32, 0.5),
3971 LLVMConstReal(ctx->f32, 0.5),
3972 ctx->ac.f32_0,
3973 ctx->ac.f32_0,
3974 };
3975
3976 sample_position = ac_build_gather_values(&ctx->ac, center, 4);
3977 } else {
3978 sample_position = load_sample_position(&ctx->abi, sample_id);
3979 }
3980
3981 offset_x = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
3982 ctx->i32_0, "");
3983
3984 offset_x = LLVMBuildFSub(ctx->ac.builder, offset_x, halfval, "");
3985 offset_y = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
3986 ctx->i32_1, "");
3987 offset_y = LLVMBuildFSub(ctx->ac.builder, offset_y, halfval, "");
3988 }
3989
3990 assert(input->Register.File == TGSI_FILE_INPUT);
3991
3992 if (input->Register.Indirect) {
3993 unsigned array_id = input->Indirect.ArrayID;
3994
3995 if (array_id) {
3996 input_base = info->input_array_first[array_id];
3997 input_array_size = info->input_array_last[array_id] - input_base + 1;
3998 } else {
3999 input_base = inst->Src[0].Register.Index;
4000 input_array_size = info->num_inputs - input_base;
4001 }
4002
4003 array_idx = si_get_indirect_index(ctx, &input->Indirect,
4004 1, input->Register.Index - input_base);
4005 } else {
4006 input_base = inst->Src[0].Register.Index;
4007 input_array_size = 1;
4008 array_idx = ctx->i32_0;
4009 }
4010
4011 interp = shader->selector->info.input_interpolate[input_base];
4012
4013 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4014 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4015 location = TGSI_INTERPOLATE_LOC_CENTER;
4016 else
4017 location = TGSI_INTERPOLATE_LOC_CENTROID;
4018
4019 interp_param_idx = lookup_interp_param_index(interp, location);
4020 if (interp_param_idx == -1)
4021 return;
4022 else if (interp_param_idx)
4023 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4024 else
4025 interp_param = NULL;
4026
4027 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4028 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4029 LLVMValueRef ij_out[2];
4030 LLVMValueRef ddxy_out = ac_build_ddxy_interp(&ctx->ac, interp_param);
4031
4032 /*
4033 * take the I then J parameters, and the DDX/Y for it, and
4034 * calculate the IJ inputs for the interpolator.
4035 * temp1 = ddx * offset/sample.x + I;
4036 * interp_param.I = ddy * offset/sample.y + temp1;
4037 * temp1 = ddx * offset/sample.x + J;
4038 * interp_param.J = ddy * offset/sample.y + temp1;
4039 */
4040 for (i = 0; i < 2; i++) {
4041 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
4042 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
4043 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4044 ddxy_out, ix_ll, "");
4045 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4046 ddxy_out, iy_ll, "");
4047 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4048 interp_param, ix_ll, "");
4049 LLVMValueRef temp;
4050
4051 interp_el = ac_to_float(&ctx->ac, interp_el);
4052
4053 temp = ac_build_fmad(&ctx->ac, ddx_el, offset_x, interp_el);
4054 ij_out[i] = ac_build_fmad(&ctx->ac, ddy_el, offset_y, temp);
4055 }
4056 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4057 }
4058
4059 if (interp_param)
4060 interp_param = ac_to_float(&ctx->ac, interp_param);
4061
4062 for (chan = 0; chan < 4; chan++) {
4063 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
4064 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4065
4066 for (unsigned idx = 0; idx < input_array_size; ++idx) {
4067 LLVMValueRef v, i = NULL, j = NULL;
4068
4069 if (interp_param) {
4070 i = LLVMBuildExtractElement(
4071 ctx->ac.builder, interp_param, ctx->i32_0, "");
4072 j = LLVMBuildExtractElement(
4073 ctx->ac.builder, interp_param, ctx->i32_1, "");
4074 }
4075 v = si_build_fs_interp(ctx, input_base + idx, schan,
4076 prim_mask, i, j);
4077
4078 gather = LLVMBuildInsertElement(ctx->ac.builder,
4079 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
4080 }
4081
4082 emit_data->output[chan] = LLVMBuildExtractElement(
4083 ctx->ac.builder, gather, array_idx, "");
4084 }
4085 }
4086
4087 static void vote_all_emit(
4088 const struct lp_build_tgsi_action *action,
4089 struct lp_build_tgsi_context *bld_base,
4090 struct lp_build_emit_data *emit_data)
4091 {
4092 struct si_shader_context *ctx = si_shader_context(bld_base);
4093
4094 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
4095 emit_data->output[emit_data->chan] =
4096 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4097 }
4098
4099 static void vote_any_emit(
4100 const struct lp_build_tgsi_action *action,
4101 struct lp_build_tgsi_context *bld_base,
4102 struct lp_build_emit_data *emit_data)
4103 {
4104 struct si_shader_context *ctx = si_shader_context(bld_base);
4105
4106 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
4107 emit_data->output[emit_data->chan] =
4108 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4109 }
4110
4111 static void vote_eq_emit(
4112 const struct lp_build_tgsi_action *action,
4113 struct lp_build_tgsi_context *bld_base,
4114 struct lp_build_emit_data *emit_data)
4115 {
4116 struct si_shader_context *ctx = si_shader_context(bld_base);
4117
4118 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4119 emit_data->output[emit_data->chan] =
4120 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4121 }
4122
4123 static void ballot_emit(
4124 const struct lp_build_tgsi_action *action,
4125 struct lp_build_tgsi_context *bld_base,
4126 struct lp_build_emit_data *emit_data)
4127 {
4128 struct si_shader_context *ctx = si_shader_context(bld_base);
4129 LLVMBuilderRef builder = ctx->ac.builder;
4130 LLVMValueRef tmp;
4131
4132 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4133 tmp = ac_build_ballot(&ctx->ac, tmp);
4134 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4135
4136 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4137 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4138 }
4139
4140 static void read_lane_emit(
4141 const struct lp_build_tgsi_action *action,
4142 struct lp_build_tgsi_context *bld_base,
4143 struct lp_build_emit_data *emit_data)
4144 {
4145 struct si_shader_context *ctx = si_shader_context(bld_base);
4146
4147 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_READ_INVOC) {
4148 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4149 0, emit_data->src_chan);
4150
4151 /* Always read the source invocation (= lane) from the X channel. */
4152 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4153 1, TGSI_CHAN_X);
4154 emit_data->arg_count = 2;
4155 }
4156
4157 /* We currently have no other way to prevent LLVM from lifting the icmp
4158 * calls to a dominating basic block.
4159 */
4160 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4161
4162 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4163 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4164
4165 emit_data->output[emit_data->chan] =
4166 ac_build_intrinsic(&ctx->ac, action->intr_name,
4167 ctx->i32, emit_data->args, emit_data->arg_count,
4168 AC_FUNC_ATTR_READNONE |
4169 AC_FUNC_ATTR_CONVERGENT);
4170 }
4171
4172 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4173 struct lp_build_emit_data *emit_data)
4174 {
4175 struct si_shader_context *ctx = si_shader_context(bld_base);
4176 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4177 LLVMValueRef imm;
4178 unsigned stream;
4179
4180 assert(src0.File == TGSI_FILE_IMMEDIATE);
4181
4182 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4183 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4184 return stream;
4185 }
4186
4187 /* Emit one vertex from the geometry shader */
4188 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4189 unsigned stream,
4190 LLVMValueRef *addrs)
4191 {
4192 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4193 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4194 struct si_shader *shader = ctx->shader;
4195 struct lp_build_if_state if_state;
4196 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4197 ctx->param_gs2vs_offset);
4198 LLVMValueRef gs_next_vertex;
4199 LLVMValueRef can_emit;
4200 unsigned chan, offset;
4201 int i;
4202
4203 /* Write vertex attribute values to GSVS ring */
4204 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4205 ctx->gs_next_vertex[stream],
4206 "");
4207
4208 /* If this thread has already emitted the declared maximum number of
4209 * vertices, skip the write: excessive vertex emissions are not
4210 * supposed to have any effect.
4211 *
4212 * If the shader has no writes to memory, kill it instead. This skips
4213 * further memory loads and may allow LLVM to skip to the end
4214 * altogether.
4215 */
4216 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4217 LLVMConstInt(ctx->i32,
4218 shader->selector->gs_max_out_vertices, 0), "");
4219
4220 bool use_kill = !info->writes_memory;
4221 if (use_kill) {
4222 ac_build_kill_if_false(&ctx->ac, can_emit);
4223 } else {
4224 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4225 }
4226
4227 offset = 0;
4228 for (i = 0; i < info->num_outputs; i++) {
4229 for (chan = 0; chan < 4; chan++) {
4230 if (!(info->output_usagemask[i] & (1 << chan)) ||
4231 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4232 continue;
4233
4234 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4235 LLVMValueRef voffset =
4236 LLVMConstInt(ctx->i32, offset *
4237 shader->selector->gs_max_out_vertices, 0);
4238 offset++;
4239
4240 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4241 voffset = LLVMBuildMul(ctx->ac.builder, voffset,
4242 LLVMConstInt(ctx->i32, 4, 0), "");
4243
4244 out_val = ac_to_integer(&ctx->ac, out_val);
4245
4246 ac_build_buffer_store_dword(&ctx->ac,
4247 ctx->gsvs_ring[stream],
4248 out_val, 1,
4249 voffset, soffset, 0,
4250 1, 1, true);
4251 }
4252 }
4253
4254 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex, ctx->i32_1, "");
4255 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4256
4257 /* Signal vertex emission if vertex data was written. */
4258 if (offset) {
4259 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4260 si_get_gs_wave_id(ctx));
4261 }
4262
4263 if (!use_kill)
4264 lp_build_endif(&if_state);
4265 }
4266
4267 /* Emit one vertex from the geometry shader */
4268 static void si_tgsi_emit_vertex(
4269 const struct lp_build_tgsi_action *action,
4270 struct lp_build_tgsi_context *bld_base,
4271 struct lp_build_emit_data *emit_data)
4272 {
4273 struct si_shader_context *ctx = si_shader_context(bld_base);
4274 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4275
4276 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4277 }
4278
4279 /* Cut one primitive from the geometry shader */
4280 static void si_llvm_emit_primitive(struct ac_shader_abi *abi,
4281 unsigned stream)
4282 {
4283 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4284
4285 /* Signal primitive cut */
4286 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4287 si_get_gs_wave_id(ctx));
4288 }
4289
4290 /* Cut one primitive from the geometry shader */
4291 static void si_tgsi_emit_primitive(
4292 const struct lp_build_tgsi_action *action,
4293 struct lp_build_tgsi_context *bld_base,
4294 struct lp_build_emit_data *emit_data)
4295 {
4296 struct si_shader_context *ctx = si_shader_context(bld_base);
4297
4298 si_llvm_emit_primitive(&ctx->abi, si_llvm_get_stream(bld_base, emit_data));
4299 }
4300
4301 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4302 struct lp_build_tgsi_context *bld_base,
4303 struct lp_build_emit_data *emit_data)
4304 {
4305 struct si_shader_context *ctx = si_shader_context(bld_base);
4306
4307 /* GFX6 only (thanks to a hw bug workaround):
4308 * The real barrier instruction isn’t needed, because an entire patch
4309 * always fits into a single wave.
4310 */
4311 if (ctx->screen->info.chip_class == GFX6 &&
4312 ctx->type == PIPE_SHADER_TESS_CTRL) {
4313 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
4314 return;
4315 }
4316
4317 ac_build_s_barrier(&ctx->ac);
4318 }
4319
4320 void si_create_function(struct si_shader_context *ctx,
4321 const char *name,
4322 LLVMTypeRef *returns, unsigned num_returns,
4323 struct si_function_info *fninfo,
4324 unsigned max_workgroup_size)
4325 {
4326 int i;
4327
4328 si_llvm_create_func(ctx, name, returns, num_returns,
4329 fninfo->types, fninfo->num_params);
4330 ctx->return_value = LLVMGetUndef(ctx->return_type);
4331
4332 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4333 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4334
4335 /* The combination of:
4336 * - noalias
4337 * - dereferenceable
4338 * - invariant.load
4339 * allows the optimization passes to move loads and reduces
4340 * SGPR spilling significantly.
4341 */
4342 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4343 AC_FUNC_ATTR_INREG);
4344
4345 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4346 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4347 AC_FUNC_ATTR_NOALIAS);
4348 ac_add_attr_dereferenceable(P, UINT64_MAX);
4349 }
4350 }
4351
4352 for (i = 0; i < fninfo->num_params; ++i) {
4353 if (fninfo->assign[i])
4354 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4355 }
4356
4357 if (ctx->screen->info.address32_hi) {
4358 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4359 "amdgpu-32bit-address-high-bits",
4360 ctx->screen->info.address32_hi);
4361 }
4362
4363 ac_llvm_set_workgroup_size(ctx->main_fn, max_workgroup_size);
4364
4365 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4366 "no-signed-zeros-fp-math",
4367 "true");
4368
4369 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4370 /* These were copied from some LLVM test. */
4371 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4372 "less-precise-fpmad",
4373 "true");
4374 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4375 "no-infs-fp-math",
4376 "true");
4377 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4378 "no-nans-fp-math",
4379 "true");
4380 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4381 "unsafe-fp-math",
4382 "true");
4383 }
4384 }
4385
4386 static void declare_streamout_params(struct si_shader_context *ctx,
4387 struct pipe_stream_output_info *so,
4388 struct si_function_info *fninfo)
4389 {
4390 int i;
4391
4392 /* Streamout SGPRs. */
4393 if (so->num_outputs) {
4394 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4395 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4396 else
4397 ctx->param_streamout_config = fninfo->num_params - 1;
4398
4399 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4400 }
4401 /* A streamout buffer offset is loaded if the stride is non-zero. */
4402 for (i = 0; i < 4; i++) {
4403 if (!so->stride[i])
4404 continue;
4405
4406 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4407 }
4408 }
4409
4410 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4411 {
4412 switch (shader->selector->type) {
4413 case PIPE_SHADER_TESS_CTRL:
4414 /* Return this so that LLVM doesn't remove s_barrier
4415 * instructions on chips where we use s_barrier. */
4416 return shader->selector->screen->info.chip_class >= GFX7 ? 128 : 64;
4417
4418 case PIPE_SHADER_GEOMETRY:
4419 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4420
4421 case PIPE_SHADER_COMPUTE:
4422 break; /* see below */
4423
4424 default:
4425 return 0;
4426 }
4427
4428 const unsigned *properties = shader->selector->info.properties;
4429 unsigned max_work_group_size =
4430 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4431 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4432 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4433
4434 if (!max_work_group_size) {
4435 /* This is a variable group size compute shader,
4436 * compile it for the maximum possible group size.
4437 */
4438 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4439 }
4440 return max_work_group_size;
4441 }
4442
4443 static void declare_const_and_shader_buffers(struct si_shader_context *ctx,
4444 struct si_function_info *fninfo,
4445 bool assign_params)
4446 {
4447 LLVMTypeRef const_shader_buf_type;
4448
4449 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4450 ctx->shader->selector->info.shader_buffers_declared == 0)
4451 const_shader_buf_type = ctx->f32;
4452 else
4453 const_shader_buf_type = ctx->v4i32;
4454
4455 unsigned const_and_shader_buffers =
4456 add_arg(fninfo, ARG_SGPR,
4457 ac_array_in_const32_addr_space(const_shader_buf_type));
4458
4459 if (assign_params)
4460 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4461 }
4462
4463 static void declare_samplers_and_images(struct si_shader_context *ctx,
4464 struct si_function_info *fninfo,
4465 bool assign_params)
4466 {
4467 unsigned samplers_and_images =
4468 add_arg(fninfo, ARG_SGPR,
4469 ac_array_in_const32_addr_space(ctx->v8i32));
4470
4471 if (assign_params)
4472 ctx->param_samplers_and_images = samplers_and_images;
4473 }
4474
4475 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4476 struct si_function_info *fninfo,
4477 bool assign_params)
4478 {
4479 declare_const_and_shader_buffers(ctx, fninfo, assign_params);
4480 declare_samplers_and_images(ctx, fninfo, assign_params);
4481 }
4482
4483 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4484 struct si_function_info *fninfo)
4485 {
4486 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4487 ac_array_in_const32_addr_space(ctx->v4i32));
4488 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4489 ac_array_in_const32_addr_space(ctx->v8i32));
4490 }
4491
4492 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4493 struct si_function_info *fninfo)
4494 {
4495 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4496 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4497 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4498 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4499 }
4500
4501 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4502 struct si_function_info *fninfo,
4503 unsigned *num_prolog_vgprs)
4504 {
4505 struct si_shader *shader = ctx->shader;
4506
4507 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4508 if (shader->key.as_ls) {
4509 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4510 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4511 } else {
4512 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4513 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4514 }
4515 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4516
4517 if (!shader->is_gs_copy_shader) {
4518 /* Vertex load indices. */
4519 ctx->param_vertex_index0 = fninfo->num_params;
4520 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4521 add_arg(fninfo, ARG_VGPR, ctx->i32);
4522 *num_prolog_vgprs += shader->selector->info.num_inputs;
4523 }
4524 }
4525
4526 static void declare_vs_blit_inputs(struct si_shader_context *ctx,
4527 struct si_function_info *fninfo,
4528 unsigned vs_blit_property)
4529 {
4530 ctx->param_vs_blit_inputs = fninfo->num_params;
4531 add_arg(fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4532 add_arg(fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4533 add_arg(fninfo, ARG_SGPR, ctx->f32); /* depth */
4534
4535 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4536 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color0 */
4537 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color1 */
4538 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color2 */
4539 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color3 */
4540 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4541 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4542 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4543 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4544 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4545 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4546 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4547 }
4548 }
4549
4550 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4551 struct si_function_info *fninfo)
4552 {
4553 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4554 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4555 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4556 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
4557 }
4558
4559 enum {
4560 /* Convenient merged shader definitions. */
4561 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4562 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4563 };
4564
4565 static void create_function(struct si_shader_context *ctx)
4566 {
4567 struct si_shader *shader = ctx->shader;
4568 struct si_function_info fninfo;
4569 LLVMTypeRef returns[16+32*4];
4570 unsigned i, num_return_sgprs;
4571 unsigned num_returns = 0;
4572 unsigned num_prolog_vgprs = 0;
4573 unsigned type = ctx->type;
4574 unsigned vs_blit_property =
4575 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4576
4577 si_init_function_info(&fninfo);
4578
4579 /* Set MERGED shaders. */
4580 if (ctx->screen->info.chip_class >= GFX9) {
4581 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4582 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4583 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4584 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4585 }
4586
4587 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4588
4589 switch (type) {
4590 case PIPE_SHADER_VERTEX:
4591 declare_global_desc_pointers(ctx, &fninfo);
4592
4593 if (vs_blit_property) {
4594 declare_vs_blit_inputs(ctx, &fninfo, vs_blit_property);
4595
4596 /* VGPRs */
4597 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4598 break;
4599 }
4600
4601 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4602 declare_vs_specific_input_sgprs(ctx, &fninfo);
4603 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4604 ac_array_in_const32_addr_space(ctx->v4i32));
4605
4606 if (shader->key.as_es) {
4607 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4608 } else if (shader->key.as_ls) {
4609 /* no extra parameters */
4610 } else {
4611 if (shader->is_gs_copy_shader) {
4612 fninfo.num_params = ctx->param_vs_state_bits + 1;
4613 fninfo.num_sgpr_params = fninfo.num_params;
4614 }
4615
4616 /* The locations of the other parameters are assigned dynamically. */
4617 declare_streamout_params(ctx, &shader->selector->so,
4618 &fninfo);
4619 }
4620
4621 /* VGPRs */
4622 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4623
4624 /* Return values */
4625 if (shader->key.opt.vs_as_prim_discard_cs) {
4626 for (i = 0; i < 4; i++)
4627 returns[num_returns++] = ctx->f32; /* VGPRs */
4628 }
4629 break;
4630
4631 case PIPE_SHADER_TESS_CTRL: /* GFX6-GFX8 */
4632 declare_global_desc_pointers(ctx, &fninfo);
4633 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4634 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4635 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4636 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4637 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4638 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4639 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4640
4641 /* VGPRs */
4642 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4643 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4644
4645 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4646 * placed after the user SGPRs.
4647 */
4648 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4649 returns[num_returns++] = ctx->i32; /* SGPRs */
4650 for (i = 0; i < 11; i++)
4651 returns[num_returns++] = ctx->f32; /* VGPRs */
4652 break;
4653
4654 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4655 /* Merged stages have 8 system SGPRs at the beginning. */
4656 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
4657 declare_per_stage_desc_pointers(ctx, &fninfo,
4658 ctx->type == PIPE_SHADER_TESS_CTRL);
4659 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4660 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4661 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4662 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4663 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4664 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4665
4666 declare_global_desc_pointers(ctx, &fninfo);
4667 declare_per_stage_desc_pointers(ctx, &fninfo,
4668 ctx->type == PIPE_SHADER_VERTEX);
4669 declare_vs_specific_input_sgprs(ctx, &fninfo);
4670
4671 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4672 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4673 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4674 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4675 ac_array_in_const32_addr_space(ctx->v4i32));
4676
4677 /* VGPRs (first TCS, then VS) */
4678 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4679 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4680
4681 if (ctx->type == PIPE_SHADER_VERTEX) {
4682 declare_vs_input_vgprs(ctx, &fninfo,
4683 &num_prolog_vgprs);
4684
4685 /* LS return values are inputs to the TCS main shader part. */
4686 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4687 returns[num_returns++] = ctx->i32; /* SGPRs */
4688 for (i = 0; i < 2; i++)
4689 returns[num_returns++] = ctx->f32; /* VGPRs */
4690 } else {
4691 /* TCS return values are inputs to the TCS epilog.
4692 *
4693 * param_tcs_offchip_offset, param_tcs_factor_offset,
4694 * param_tcs_offchip_layout, and param_rw_buffers
4695 * should be passed to the epilog.
4696 */
4697 for (i = 0; i <= 8 + GFX9_SGPR_TCS_OUT_LAYOUT; i++)
4698 returns[num_returns++] = ctx->i32; /* SGPRs */
4699 for (i = 0; i < 11; i++)
4700 returns[num_returns++] = ctx->f32; /* VGPRs */
4701 }
4702 break;
4703
4704 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4705 /* Merged stages have 8 system SGPRs at the beginning. */
4706 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
4707 declare_per_stage_desc_pointers(ctx, &fninfo,
4708 ctx->type == PIPE_SHADER_GEOMETRY);
4709 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4710 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4711 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4712 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4713 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4714 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4715
4716 declare_global_desc_pointers(ctx, &fninfo);
4717 declare_per_stage_desc_pointers(ctx, &fninfo,
4718 (ctx->type == PIPE_SHADER_VERTEX ||
4719 ctx->type == PIPE_SHADER_TESS_EVAL));
4720 if (ctx->type == PIPE_SHADER_VERTEX) {
4721 declare_vs_specific_input_sgprs(ctx, &fninfo);
4722 } else {
4723 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4724 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4725 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4726 /* Declare as many input SGPRs as the VS has. */
4727 }
4728
4729 if (ctx->type == PIPE_SHADER_VERTEX) {
4730 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4731 ac_array_in_const32_addr_space(ctx->v4i32));
4732 }
4733
4734 /* VGPRs (first GS, then VS/TES) */
4735 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4736 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4737 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4738 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4739 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4740
4741 if (ctx->type == PIPE_SHADER_VERTEX) {
4742 declare_vs_input_vgprs(ctx, &fninfo,
4743 &num_prolog_vgprs);
4744 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4745 declare_tes_input_vgprs(ctx, &fninfo);
4746 }
4747
4748 if (ctx->type == PIPE_SHADER_VERTEX ||
4749 ctx->type == PIPE_SHADER_TESS_EVAL) {
4750 unsigned num_user_sgprs;
4751
4752 if (ctx->type == PIPE_SHADER_VERTEX)
4753 num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR;
4754 else
4755 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
4756
4757 /* ES return values are inputs to GS. */
4758 for (i = 0; i < 8 + num_user_sgprs; i++)
4759 returns[num_returns++] = ctx->i32; /* SGPRs */
4760 for (i = 0; i < 5; i++)
4761 returns[num_returns++] = ctx->f32; /* VGPRs */
4762 }
4763 break;
4764
4765 case PIPE_SHADER_TESS_EVAL:
4766 declare_global_desc_pointers(ctx, &fninfo);
4767 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4768 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4769 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4770 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4771
4772 if (shader->key.as_es) {
4773 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4774 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4775 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4776 } else {
4777 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4778 declare_streamout_params(ctx, &shader->selector->so,
4779 &fninfo);
4780 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4781 }
4782
4783 /* VGPRs */
4784 declare_tes_input_vgprs(ctx, &fninfo);
4785 break;
4786
4787 case PIPE_SHADER_GEOMETRY:
4788 declare_global_desc_pointers(ctx, &fninfo);
4789 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4790 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4791 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4792
4793 /* VGPRs */
4794 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4795 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4796 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4797 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4798 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4799 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4800 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4801 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4802 break;
4803
4804 case PIPE_SHADER_FRAGMENT:
4805 declare_global_desc_pointers(ctx, &fninfo);
4806 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4807 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4808 add_arg_assign_checked(&fninfo, ARG_SGPR, ctx->i32,
4809 &ctx->abi.prim_mask, SI_PARAM_PRIM_MASK);
4810
4811 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4812 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4813 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4814 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4815 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4816 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4817 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4818 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4819 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4820 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4821 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4822 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4823 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4824 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4825 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4826 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4827 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4828 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4829 shader->info.face_vgpr_index = 20;
4830 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4831 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4832 shader->info.ancillary_vgpr_index = 21;
4833 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4834 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4835 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4836
4837 /* Color inputs from the prolog. */
4838 if (shader->selector->info.colors_read) {
4839 unsigned num_color_elements =
4840 util_bitcount(shader->selector->info.colors_read);
4841
4842 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4843 for (i = 0; i < num_color_elements; i++)
4844 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4845
4846 num_prolog_vgprs += num_color_elements;
4847 }
4848
4849 /* Outputs for the epilog. */
4850 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4851 num_returns =
4852 num_return_sgprs +
4853 util_bitcount(shader->selector->info.colors_written) * 4 +
4854 shader->selector->info.writes_z +
4855 shader->selector->info.writes_stencil +
4856 shader->selector->info.writes_samplemask +
4857 1 /* SampleMaskIn */;
4858
4859 num_returns = MAX2(num_returns,
4860 num_return_sgprs +
4861 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4862
4863 for (i = 0; i < num_return_sgprs; i++)
4864 returns[i] = ctx->i32;
4865 for (; i < num_returns; i++)
4866 returns[i] = ctx->f32;
4867 break;
4868
4869 case PIPE_SHADER_COMPUTE:
4870 declare_global_desc_pointers(ctx, &fninfo);
4871 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4872 if (shader->selector->info.uses_grid_size)
4873 add_arg_assign(&fninfo, ARG_SGPR, v3i32, &ctx->abi.num_work_groups);
4874 if (shader->selector->info.uses_block_size &&
4875 shader->selector->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
4876 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4877
4878 unsigned cs_user_data_dwords =
4879 shader->selector->info.properties[TGSI_PROPERTY_CS_USER_DATA_DWORDS];
4880 if (cs_user_data_dwords) {
4881 ctx->param_cs_user_data = add_arg(&fninfo, ARG_SGPR,
4882 LLVMVectorType(ctx->i32, cs_user_data_dwords));
4883 }
4884
4885 for (i = 0; i < 3; i++) {
4886 ctx->abi.workgroup_ids[i] = NULL;
4887 if (shader->selector->info.uses_block_id[i])
4888 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->abi.workgroup_ids[i]);
4889 }
4890
4891 add_arg_assign(&fninfo, ARG_VGPR, v3i32, &ctx->abi.local_invocation_ids);
4892 break;
4893 default:
4894 assert(0 && "unimplemented shader");
4895 return;
4896 }
4897
4898 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4899 si_get_max_workgroup_size(shader));
4900
4901 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4902 if (ctx->type == PIPE_SHADER_FRAGMENT && !ctx->shader->is_monolithic) {
4903 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4904 "InitialPSInputAddr",
4905 S_0286D0_PERSP_SAMPLE_ENA(1) |
4906 S_0286D0_PERSP_CENTER_ENA(1) |
4907 S_0286D0_PERSP_CENTROID_ENA(1) |
4908 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4909 S_0286D0_LINEAR_CENTER_ENA(1) |
4910 S_0286D0_LINEAR_CENTROID_ENA(1) |
4911 S_0286D0_FRONT_FACE_ENA(1) |
4912 S_0286D0_ANCILLARY_ENA(1) |
4913 S_0286D0_POS_FIXED_PT_ENA(1));
4914 }
4915
4916 shader->info.num_input_sgprs = 0;
4917 shader->info.num_input_vgprs = 0;
4918
4919 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4920 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
4921
4922 for (; i < fninfo.num_params; ++i)
4923 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
4924
4925 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4926 shader->info.num_input_vgprs -= num_prolog_vgprs;
4927
4928 if (shader->key.as_ls || ctx->type == PIPE_SHADER_TESS_CTRL) {
4929 if (USE_LDS_SYMBOLS && HAVE_LLVM >= 0x0900) {
4930 /* The LSHS size is not known until draw time, so we append it
4931 * at the end of whatever LDS use there may be in the rest of
4932 * the shader (currently none, unless LLVM decides to do its
4933 * own LDS-based lowering).
4934 */
4935 ctx->ac.lds = LLVMAddGlobalInAddressSpace(
4936 ctx->ac.module, LLVMArrayType(ctx->i32, 0),
4937 "__lds_end", AC_ADDR_SPACE_LDS);
4938 LLVMSetAlignment(ctx->ac.lds, 256);
4939 } else {
4940 ac_declare_lds_as_pointer(&ctx->ac);
4941 }
4942 }
4943 }
4944
4945 /**
4946 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4947 * for later use.
4948 */
4949 static void preload_ring_buffers(struct si_shader_context *ctx)
4950 {
4951 LLVMBuilderRef builder = ctx->ac.builder;
4952
4953 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
4954 ctx->param_rw_buffers);
4955
4956 if (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY) {
4957 if (ctx->screen->info.chip_class <= GFX8) {
4958 unsigned ring =
4959 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
4960 : SI_ES_RING_ESGS;
4961 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
4962
4963 ctx->esgs_ring =
4964 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4965 } else {
4966 if (USE_LDS_SYMBOLS && HAVE_LLVM >= 0x0900) {
4967 /* Declare the ESGS ring as an explicit LDS symbol.
4968 * For monolithic shaders, we declare the ring only once.
4969 *
4970 * We declare it with 64KB alignment as a hint that the
4971 * pointer value will always be 0.
4972 */
4973 ctx->esgs_ring = LLVMAddGlobalInAddressSpace(
4974 ctx->ac.module, LLVMArrayType(ctx->i32, 0),
4975 "esgs_ring",
4976 AC_ADDR_SPACE_LDS);
4977 LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
4978 } else {
4979 ac_declare_lds_as_pointer(&ctx->ac);
4980 ctx->esgs_ring = ctx->ac.lds;
4981 }
4982 }
4983 }
4984
4985 if (ctx->shader->is_gs_copy_shader) {
4986 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4987
4988 ctx->gsvs_ring[0] =
4989 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4990 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
4991 const struct si_shader_selector *sel = ctx->shader->selector;
4992 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4993 LLVMValueRef base_ring;
4994
4995 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4996
4997 /* The conceptual layout of the GSVS ring is
4998 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4999 * but the real memory layout is swizzled across
5000 * threads:
5001 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5002 * t16v0c0 ..
5003 * Override the buffer descriptor accordingly.
5004 */
5005 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5006 uint64_t stream_offset = 0;
5007
5008 for (unsigned stream = 0; stream < 4; ++stream) {
5009 unsigned num_components;
5010 unsigned stride;
5011 unsigned num_records;
5012 LLVMValueRef ring, tmp;
5013
5014 num_components = sel->info.num_stream_output_components[stream];
5015 if (!num_components)
5016 continue;
5017
5018 stride = 4 * num_components * sel->gs_max_out_vertices;
5019
5020 /* Limit on the stride field for <= GFX7. */
5021 assert(stride < (1 << 14));
5022
5023 num_records = 64;
5024
5025 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5026 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
5027 tmp = LLVMBuildAdd(builder, tmp,
5028 LLVMConstInt(ctx->i64,
5029 stream_offset, 0), "");
5030 stream_offset += stride * 64;
5031
5032 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5033 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5034 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5035 tmp = LLVMBuildOr(builder, tmp,
5036 LLVMConstInt(ctx->i32,
5037 S_008F04_STRIDE(stride) |
5038 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5039 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5040 ring = LLVMBuildInsertElement(builder, ring,
5041 LLVMConstInt(ctx->i32, num_records, 0),
5042 LLVMConstInt(ctx->i32, 2, 0), "");
5043 ring = LLVMBuildInsertElement(builder, ring,
5044 LLVMConstInt(ctx->i32,
5045 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5046 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5047 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5048 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5049 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5050 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5051 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5052 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5053 S_008F0C_ADD_TID_ENABLE(1),
5054 0),
5055 LLVMConstInt(ctx->i32, 3, 0), "");
5056
5057 ctx->gsvs_ring[stream] = ring;
5058 }
5059 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
5060 ctx->tess_offchip_ring = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TES);
5061 }
5062 }
5063
5064 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5065 LLVMValueRef param_rw_buffers,
5066 unsigned param_pos_fixed_pt)
5067 {
5068 LLVMBuilderRef builder = ctx->ac.builder;
5069 LLVMValueRef slot, desc, offset, row, bit, address[2];
5070
5071 /* Use the fixed-point gl_FragCoord input.
5072 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5073 * per coordinate to get the repeating effect.
5074 */
5075 address[0] = si_unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5076 address[1] = si_unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5077
5078 /* Load the buffer descriptor. */
5079 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5080 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
5081
5082 /* The stipple pattern is 32x32, each row has 32 bits. */
5083 offset = LLVMBuildMul(builder, address[1],
5084 LLVMConstInt(ctx->i32, 4, 0), "");
5085 row = buffer_load_const(ctx, desc, offset);
5086 row = ac_to_integer(&ctx->ac, row);
5087 bit = LLVMBuildLShr(builder, row, address[0], "");
5088 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5089 ac_build_kill_if_false(&ctx->ac, bit);
5090 }
5091
5092 /* For the UMR disassembler. */
5093 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
5094 #define DEBUGGER_NUM_MARKERS 5
5095
5096 static bool si_shader_binary_open(struct si_screen *screen,
5097 struct si_shader *shader,
5098 struct ac_rtld_binary *rtld)
5099 {
5100 const struct si_shader_selector *sel = shader->selector;
5101 const char *part_elfs[5];
5102 size_t part_sizes[5];
5103 unsigned num_parts = 0;
5104
5105 #define add_part(shader_or_part) \
5106 if (shader_or_part) { \
5107 part_elfs[num_parts] = (shader_or_part)->binary.elf_buffer; \
5108 part_sizes[num_parts] = (shader_or_part)->binary.elf_size; \
5109 num_parts++; \
5110 }
5111
5112 add_part(shader->prolog);
5113 add_part(shader->previous_stage);
5114 add_part(shader->prolog2);
5115 add_part(shader);
5116 add_part(shader->epilog);
5117
5118 #undef add_part
5119
5120 struct ac_rtld_symbol lds_symbols[1];
5121 unsigned num_lds_symbols = 0;
5122
5123 if (sel && screen->info.chip_class >= GFX9 &&
5124 sel->type == PIPE_SHADER_GEOMETRY && !shader->is_gs_copy_shader) {
5125 /* We add this symbol even on LLVM <= 8 to ensure that
5126 * shader->config.lds_size is set correctly below.
5127 */
5128 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
5129 sym->name = "esgs_ring";
5130 sym->size = shader->gs_info.esgs_ring_size;
5131 sym->align = 64 * 1024;
5132 }
5133
5134 bool ok = ac_rtld_open(rtld, (struct ac_rtld_open_info){
5135 .info = &screen->info,
5136 .options = {
5137 .halt_at_entry = screen->options.halt_shaders,
5138 },
5139 .num_parts = num_parts,
5140 .elf_ptrs = part_elfs,
5141 .elf_sizes = part_sizes,
5142 .num_shared_lds_symbols = num_lds_symbols,
5143 .shared_lds_symbols = lds_symbols });
5144
5145 if (rtld->lds_size > 0) {
5146 unsigned alloc_granularity = screen->info.chip_class >= GFX7 ? 512 : 256;
5147 shader->config.lds_size =
5148 align(rtld->lds_size, alloc_granularity) / alloc_granularity;
5149 }
5150
5151 return ok;
5152 }
5153
5154 static unsigned si_get_shader_binary_size(struct si_screen *screen, struct si_shader *shader)
5155 {
5156 struct ac_rtld_binary rtld;
5157 si_shader_binary_open(screen, shader, &rtld);
5158 return rtld.rx_size;
5159 }
5160
5161
5162 static bool si_get_external_symbol(void *data, const char *name, uint64_t *value)
5163 {
5164 uint64_t *scratch_va = data;
5165
5166 if (!strcmp(scratch_rsrc_dword0_symbol, name)) {
5167 *value = (uint32_t)*scratch_va;
5168 return true;
5169 }
5170 if (!strcmp(scratch_rsrc_dword1_symbol, name)) {
5171 /* Enable scratch coalescing. */
5172 *value = S_008F04_BASE_ADDRESS_HI(*scratch_va >> 32) |
5173 S_008F04_SWIZZLE_ENABLE(1);
5174 if (HAVE_LLVM < 0x0800) {
5175 /* Old LLVM created an R_ABS32_HI relocation for
5176 * this symbol. */
5177 *value <<= 32;
5178 }
5179 return true;
5180 }
5181
5182 return false;
5183 }
5184
5185 bool si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader,
5186 uint64_t scratch_va)
5187 {
5188 struct ac_rtld_binary binary;
5189 if (!si_shader_binary_open(sscreen, shader, &binary))
5190 return false;
5191
5192 si_resource_reference(&shader->bo, NULL);
5193 shader->bo = si_aligned_buffer_create(&sscreen->b,
5194 sscreen->cpdma_prefetch_writes_memory ?
5195 0 : SI_RESOURCE_FLAG_READ_ONLY,
5196 PIPE_USAGE_IMMUTABLE,
5197 align(binary.rx_size, SI_CPDMA_ALIGNMENT),
5198 256);
5199 if (!shader->bo)
5200 return false;
5201
5202 /* Upload. */
5203 struct ac_rtld_upload_info u = {};
5204 u.binary = &binary;
5205 u.get_external_symbol = si_get_external_symbol;
5206 u.cb_data = &scratch_va;
5207 u.rx_va = shader->bo->gpu_address;
5208 u.rx_ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5209 PIPE_TRANSFER_READ_WRITE |
5210 PIPE_TRANSFER_UNSYNCHRONIZED |
5211 RADEON_TRANSFER_TEMPORARY);
5212 if (!u.rx_ptr)
5213 return false;
5214
5215 bool ok = ac_rtld_upload(&u);
5216
5217 sscreen->ws->buffer_unmap(shader->bo->buf);
5218 ac_rtld_close(&binary);
5219
5220 return ok;
5221 }
5222
5223 static void si_shader_dump_disassembly(struct si_screen *screen,
5224 const struct si_shader_binary *binary,
5225 struct pipe_debug_callback *debug,
5226 const char *name, FILE *file)
5227 {
5228 struct ac_rtld_binary rtld_binary;
5229
5230 if (!ac_rtld_open(&rtld_binary, (struct ac_rtld_open_info){
5231 .info = &screen->info,
5232 .num_parts = 1,
5233 .elf_ptrs = &binary->elf_buffer,
5234 .elf_sizes = &binary->elf_size }))
5235 return;
5236
5237 const char *disasm;
5238 size_t nbytes;
5239
5240 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm, &nbytes))
5241 goto out;
5242
5243 if (nbytes > INT_MAX)
5244 goto out;
5245
5246 if (debug && debug->debug_message) {
5247 /* Very long debug messages are cut off, so send the
5248 * disassembly one line at a time. This causes more
5249 * overhead, but on the plus side it simplifies
5250 * parsing of resulting logs.
5251 */
5252 pipe_debug_message(debug, SHADER_INFO,
5253 "Shader Disassembly Begin");
5254
5255 uint64_t line = 0;
5256 while (line < nbytes) {
5257 int count = nbytes - line;
5258 const char *nl = memchr(disasm + line, '\n', nbytes - line);
5259 if (nl)
5260 count = nl - (disasm + line);
5261
5262 if (count) {
5263 pipe_debug_message(debug, SHADER_INFO,
5264 "%.*s", count, disasm + line);
5265 }
5266
5267 line += count + 1;
5268 }
5269
5270 pipe_debug_message(debug, SHADER_INFO,
5271 "Shader Disassembly End");
5272 }
5273
5274 if (file) {
5275 fprintf(file, "Shader %s disassembly:\n", name);
5276 fprintf(file, "%*s", (int)nbytes, disasm);
5277 }
5278
5279 out:
5280 ac_rtld_close(&rtld_binary);
5281 }
5282
5283 static void si_calculate_max_simd_waves(struct si_shader *shader)
5284 {
5285 struct si_screen *sscreen = shader->selector->screen;
5286 struct ac_shader_config *conf = &shader->config;
5287 unsigned num_inputs = shader->selector->info.num_inputs;
5288 unsigned lds_increment = sscreen->info.chip_class >= GFX7 ? 512 : 256;
5289 unsigned lds_per_wave = 0;
5290 unsigned max_simd_waves;
5291
5292 max_simd_waves = ac_get_max_simd_waves(sscreen->info.family);
5293
5294 /* Compute LDS usage for PS. */
5295 switch (shader->selector->type) {
5296 case PIPE_SHADER_FRAGMENT:
5297 /* The minimum usage per wave is (num_inputs * 48). The maximum
5298 * usage is (num_inputs * 48 * 16).
5299 * We can get anything in between and it varies between waves.
5300 *
5301 * The 48 bytes per input for a single primitive is equal to
5302 * 4 bytes/component * 4 components/input * 3 points.
5303 *
5304 * Other stages don't know the size at compile time or don't
5305 * allocate LDS per wave, but instead they do it per thread group.
5306 */
5307 lds_per_wave = conf->lds_size * lds_increment +
5308 align(num_inputs * 48, lds_increment);
5309 break;
5310 case PIPE_SHADER_COMPUTE:
5311 if (shader->selector) {
5312 unsigned max_workgroup_size =
5313 si_get_max_workgroup_size(shader);
5314 lds_per_wave = (conf->lds_size * lds_increment) /
5315 DIV_ROUND_UP(max_workgroup_size, 64);
5316 }
5317 break;
5318 }
5319
5320 /* Compute the per-SIMD wave counts. */
5321 if (conf->num_sgprs) {
5322 max_simd_waves =
5323 MIN2(max_simd_waves,
5324 ac_get_num_physical_sgprs(sscreen->info.chip_class) / conf->num_sgprs);
5325 }
5326
5327 if (conf->num_vgprs)
5328 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5329
5330 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5331 * 16KB makes some SIMDs unoccupied). */
5332 if (lds_per_wave)
5333 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5334
5335 shader->info.max_simd_waves = max_simd_waves;
5336 }
5337
5338 void si_shader_dump_stats_for_shader_db(struct si_screen *screen,
5339 struct si_shader *shader,
5340 struct pipe_debug_callback *debug)
5341 {
5342 const struct ac_shader_config *conf = &shader->config;
5343
5344 if (screen->options.debug_disassembly)
5345 si_shader_dump_disassembly(screen, &shader->binary, debug, "main", NULL);
5346
5347 pipe_debug_message(debug, SHADER_INFO,
5348 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5349 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5350 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5351 conf->num_sgprs, conf->num_vgprs,
5352 si_get_shader_binary_size(screen, shader),
5353 conf->lds_size, conf->scratch_bytes_per_wave,
5354 shader->info.max_simd_waves, conf->spilled_sgprs,
5355 conf->spilled_vgprs, shader->info.private_mem_vgprs);
5356 }
5357
5358 static void si_shader_dump_stats(struct si_screen *sscreen,
5359 struct si_shader *shader,
5360 unsigned processor,
5361 FILE *file,
5362 bool check_debug_option)
5363 {
5364 const struct ac_shader_config *conf = &shader->config;
5365
5366 if (!check_debug_option ||
5367 si_can_dump_shader(sscreen, processor)) {
5368 if (processor == PIPE_SHADER_FRAGMENT) {
5369 fprintf(file, "*** SHADER CONFIG ***\n"
5370 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5371 "SPI_PS_INPUT_ENA = 0x%04x\n",
5372 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5373 }
5374
5375 fprintf(file, "*** SHADER STATS ***\n"
5376 "SGPRS: %d\n"
5377 "VGPRS: %d\n"
5378 "Spilled SGPRs: %d\n"
5379 "Spilled VGPRs: %d\n"
5380 "Private memory VGPRs: %d\n"
5381 "Code Size: %d bytes\n"
5382 "LDS: %d blocks\n"
5383 "Scratch: %d bytes per wave\n"
5384 "Max Waves: %d\n"
5385 "********************\n\n\n",
5386 conf->num_sgprs, conf->num_vgprs,
5387 conf->spilled_sgprs, conf->spilled_vgprs,
5388 shader->info.private_mem_vgprs,
5389 si_get_shader_binary_size(sscreen, shader),
5390 conf->lds_size, conf->scratch_bytes_per_wave,
5391 shader->info.max_simd_waves);
5392 }
5393 }
5394
5395 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5396 {
5397 switch (processor) {
5398 case PIPE_SHADER_VERTEX:
5399 if (shader->key.as_es)
5400 return "Vertex Shader as ES";
5401 else if (shader->key.as_ls)
5402 return "Vertex Shader as LS";
5403 else if (shader->key.opt.vs_as_prim_discard_cs)
5404 return "Vertex Shader as Primitive Discard CS";
5405 else
5406 return "Vertex Shader as VS";
5407 case PIPE_SHADER_TESS_CTRL:
5408 return "Tessellation Control Shader";
5409 case PIPE_SHADER_TESS_EVAL:
5410 if (shader->key.as_es)
5411 return "Tessellation Evaluation Shader as ES";
5412 else
5413 return "Tessellation Evaluation Shader as VS";
5414 case PIPE_SHADER_GEOMETRY:
5415 if (shader->is_gs_copy_shader)
5416 return "GS Copy Shader as VS";
5417 else
5418 return "Geometry Shader";
5419 case PIPE_SHADER_FRAGMENT:
5420 return "Pixel Shader";
5421 case PIPE_SHADER_COMPUTE:
5422 return "Compute Shader";
5423 default:
5424 return "Unknown Shader";
5425 }
5426 }
5427
5428 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
5429 struct pipe_debug_callback *debug, unsigned processor,
5430 FILE *file, bool check_debug_option)
5431 {
5432 if (!check_debug_option ||
5433 si_can_dump_shader(sscreen, processor))
5434 si_dump_shader_key(processor, shader, file);
5435
5436 if (!check_debug_option && shader->binary.llvm_ir_string) {
5437 if (shader->previous_stage &&
5438 shader->previous_stage->binary.llvm_ir_string) {
5439 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5440 si_get_shader_name(shader, processor));
5441 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5442 }
5443
5444 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5445 si_get_shader_name(shader, processor));
5446 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5447 }
5448
5449 if (!check_debug_option ||
5450 (si_can_dump_shader(sscreen, processor) &&
5451 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5452 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5453
5454 if (shader->prolog)
5455 si_shader_dump_disassembly(sscreen, &shader->prolog->binary,
5456 debug, "prolog", file);
5457 if (shader->previous_stage)
5458 si_shader_dump_disassembly(sscreen, &shader->previous_stage->binary,
5459 debug, "previous stage", file);
5460 if (shader->prolog2)
5461 si_shader_dump_disassembly(sscreen, &shader->prolog2->binary,
5462 debug, "prolog2", file);
5463
5464 si_shader_dump_disassembly(sscreen, &shader->binary, debug, "main", file);
5465
5466 if (shader->epilog)
5467 si_shader_dump_disassembly(sscreen, &shader->epilog->binary,
5468 debug, "epilog", file);
5469 fprintf(file, "\n");
5470 }
5471
5472 si_shader_dump_stats(sscreen, shader, processor, file,
5473 check_debug_option);
5474 }
5475
5476 static int si_compile_llvm(struct si_screen *sscreen,
5477 struct si_shader_binary *binary,
5478 struct ac_shader_config *conf,
5479 struct ac_llvm_compiler *compiler,
5480 LLVMModuleRef mod,
5481 struct pipe_debug_callback *debug,
5482 unsigned processor,
5483 const char *name,
5484 bool less_optimized)
5485 {
5486 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5487
5488 if (si_can_dump_shader(sscreen, processor)) {
5489 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5490
5491 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5492 fprintf(stderr, "%s LLVM IR:\n\n", name);
5493 ac_dump_module(mod);
5494 fprintf(stderr, "\n");
5495 }
5496 }
5497
5498 if (sscreen->record_llvm_ir) {
5499 char *ir = LLVMPrintModuleToString(mod);
5500 binary->llvm_ir_string = strdup(ir);
5501 LLVMDisposeMessage(ir);
5502 }
5503
5504 if (!si_replace_shader(count, binary)) {
5505 unsigned r = si_llvm_compile(mod, binary, compiler, debug,
5506 less_optimized);
5507 if (r)
5508 return r;
5509 }
5510
5511 struct ac_rtld_binary rtld;
5512 if (!ac_rtld_open(&rtld, (struct ac_rtld_open_info){
5513 .info = &sscreen->info,
5514 .num_parts = 1,
5515 .elf_ptrs = &binary->elf_buffer,
5516 .elf_sizes = &binary->elf_size }))
5517 return -1;
5518
5519 bool ok = ac_rtld_read_config(&rtld, conf);
5520 ac_rtld_close(&rtld);
5521 if (!ok)
5522 return -1;
5523
5524 /* Enable 64-bit and 16-bit denormals, because there is no performance
5525 * cost.
5526 *
5527 * If denormals are enabled, all floating-point output modifiers are
5528 * ignored.
5529 *
5530 * Don't enable denormals for 32-bit floats, because:
5531 * - Floating-point output modifiers would be ignored by the hw.
5532 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5533 * have to stop using those.
5534 * - GFX6 & GFX7 would be very slow.
5535 */
5536 conf->float_mode |= V_00B028_FP_64_DENORMS;
5537
5538 return 0;
5539 }
5540
5541 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5542 {
5543 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5544 LLVMBuildRetVoid(ctx->ac.builder);
5545 else
5546 LLVMBuildRet(ctx->ac.builder, ret);
5547 }
5548
5549 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5550 struct si_shader *
5551 si_generate_gs_copy_shader(struct si_screen *sscreen,
5552 struct ac_llvm_compiler *compiler,
5553 struct si_shader_selector *gs_selector,
5554 struct pipe_debug_callback *debug)
5555 {
5556 struct si_shader_context ctx;
5557 struct si_shader *shader;
5558 LLVMBuilderRef builder;
5559 struct si_shader_output_values outputs[SI_MAX_VS_OUTPUTS];
5560 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5561 int i;
5562
5563
5564 shader = CALLOC_STRUCT(si_shader);
5565 if (!shader)
5566 return NULL;
5567
5568 /* We can leave the fence as permanently signaled because the GS copy
5569 * shader only becomes visible globally after it has been compiled. */
5570 util_queue_fence_init(&shader->ready);
5571
5572 shader->selector = gs_selector;
5573 shader->is_gs_copy_shader = true;
5574
5575 si_init_shader_ctx(&ctx, sscreen, compiler);
5576 ctx.shader = shader;
5577 ctx.type = PIPE_SHADER_VERTEX;
5578
5579 builder = ctx.ac.builder;
5580
5581 create_function(&ctx);
5582 preload_ring_buffers(&ctx);
5583
5584 LLVMValueRef voffset =
5585 LLVMBuildMul(ctx.ac.builder, ctx.abi.vertex_id,
5586 LLVMConstInt(ctx.i32, 4, 0), "");
5587
5588 /* Fetch the vertex stream ID.*/
5589 LLVMValueRef stream_id;
5590
5591 if (gs_selector->so.num_outputs)
5592 stream_id = si_unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5593 else
5594 stream_id = ctx.i32_0;
5595
5596 /* Fill in output information. */
5597 for (i = 0; i < gsinfo->num_outputs; ++i) {
5598 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5599 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5600
5601 for (int chan = 0; chan < 4; chan++) {
5602 outputs[i].vertex_stream[chan] =
5603 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5604 }
5605 }
5606
5607 LLVMBasicBlockRef end_bb;
5608 LLVMValueRef switch_inst;
5609
5610 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5611 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5612
5613 for (int stream = 0; stream < 4; stream++) {
5614 LLVMBasicBlockRef bb;
5615 unsigned offset;
5616
5617 if (!gsinfo->num_stream_output_components[stream])
5618 continue;
5619
5620 if (stream > 0 && !gs_selector->so.num_outputs)
5621 continue;
5622
5623 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5624 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5625 LLVMPositionBuilderAtEnd(builder, bb);
5626
5627 /* Fetch vertex data from GSVS ring */
5628 offset = 0;
5629 for (i = 0; i < gsinfo->num_outputs; ++i) {
5630 for (unsigned chan = 0; chan < 4; chan++) {
5631 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5632 outputs[i].vertex_stream[chan] != stream) {
5633 outputs[i].values[chan] = LLVMGetUndef(ctx.f32);
5634 continue;
5635 }
5636
5637 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5638 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5639 offset++;
5640
5641 outputs[i].values[chan] =
5642 ac_build_buffer_load(&ctx.ac,
5643 ctx.gsvs_ring[0], 1,
5644 ctx.i32_0, voffset,
5645 soffset, 0, 1, 1,
5646 true, false);
5647 }
5648 }
5649
5650 /* Streamout and exports. */
5651 if (gs_selector->so.num_outputs) {
5652 si_llvm_emit_streamout(&ctx, outputs,
5653 gsinfo->num_outputs,
5654 stream);
5655 }
5656
5657 if (stream == 0)
5658 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5659
5660 LLVMBuildBr(builder, end_bb);
5661 }
5662
5663 LLVMPositionBuilderAtEnd(builder, end_bb);
5664
5665 LLVMBuildRetVoid(ctx.ac.builder);
5666
5667 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5668 si_llvm_optimize_module(&ctx);
5669
5670 bool ok = false;
5671 if (si_compile_llvm(sscreen, &ctx.shader->binary,
5672 &ctx.shader->config, ctx.compiler,
5673 ctx.ac.module,
5674 debug, PIPE_SHADER_GEOMETRY,
5675 "GS Copy Shader", false) == 0) {
5676 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5677 fprintf(stderr, "GS Copy Shader:\n");
5678 si_shader_dump(sscreen, ctx.shader, debug,
5679 PIPE_SHADER_GEOMETRY, stderr, true);
5680
5681 if (!ctx.shader->config.scratch_bytes_per_wave)
5682 ok = si_shader_binary_upload(sscreen, ctx.shader, 0);
5683 else
5684 ok = true;
5685 }
5686
5687 si_llvm_dispose(&ctx);
5688
5689 if (!ok) {
5690 FREE(shader);
5691 shader = NULL;
5692 } else {
5693 si_fix_resource_usage(sscreen, shader);
5694 }
5695 return shader;
5696 }
5697
5698 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5699 const struct si_vs_prolog_bits *prolog,
5700 const char *prefix, FILE *f)
5701 {
5702 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5703 prefix, prolog->instance_divisor_is_one);
5704 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5705 prefix, prolog->instance_divisor_is_fetched);
5706 fprintf(f, " %s.unpack_instance_id_from_vertex_id = %u\n",
5707 prefix, prolog->unpack_instance_id_from_vertex_id);
5708 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5709 prefix, prolog->ls_vgpr_fix);
5710
5711 fprintf(f, " mono.vs.fetch_opencode = %x\n", key->mono.vs_fetch_opencode);
5712 fprintf(f, " mono.vs.fix_fetch = {");
5713 for (int i = 0; i < SI_MAX_ATTRIBS; i++) {
5714 union si_vs_fix_fetch fix = key->mono.vs_fix_fetch[i];
5715 if (i)
5716 fprintf(f, ", ");
5717 if (!fix.bits)
5718 fprintf(f, "0");
5719 else
5720 fprintf(f, "%u.%u.%u.%u", fix.u.reverse, fix.u.log_size,
5721 fix.u.num_channels_m1, fix.u.format);
5722 }
5723 fprintf(f, "}\n");
5724 }
5725
5726 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5727 FILE *f)
5728 {
5729 const struct si_shader_key *key = &shader->key;
5730
5731 fprintf(f, "SHADER KEY\n");
5732
5733 switch (processor) {
5734 case PIPE_SHADER_VERTEX:
5735 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5736 "part.vs.prolog", f);
5737 fprintf(f, " as_es = %u\n", key->as_es);
5738 fprintf(f, " as_ls = %u\n", key->as_ls);
5739 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5740 key->mono.u.vs_export_prim_id);
5741 fprintf(f, " opt.vs_as_prim_discard_cs = %u\n",
5742 key->opt.vs_as_prim_discard_cs);
5743 fprintf(f, " opt.cs_prim_type = %s\n",
5744 tgsi_primitive_names[key->opt.cs_prim_type]);
5745 fprintf(f, " opt.cs_indexed = %u\n",
5746 key->opt.cs_indexed);
5747 fprintf(f, " opt.cs_instancing = %u\n",
5748 key->opt.cs_instancing);
5749 fprintf(f, " opt.cs_primitive_restart = %u\n",
5750 key->opt.cs_primitive_restart);
5751 fprintf(f, " opt.cs_provoking_vertex_first = %u\n",
5752 key->opt.cs_provoking_vertex_first);
5753 fprintf(f, " opt.cs_need_correct_orientation = %u\n",
5754 key->opt.cs_need_correct_orientation);
5755 fprintf(f, " opt.cs_cull_front = %u\n",
5756 key->opt.cs_cull_front);
5757 fprintf(f, " opt.cs_cull_back = %u\n",
5758 key->opt.cs_cull_back);
5759 fprintf(f, " opt.cs_cull_z = %u\n",
5760 key->opt.cs_cull_z);
5761 fprintf(f, " opt.cs_halfz_clip_space = %u\n",
5762 key->opt.cs_halfz_clip_space);
5763 break;
5764
5765 case PIPE_SHADER_TESS_CTRL:
5766 if (shader->selector->screen->info.chip_class >= GFX9) {
5767 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5768 "part.tcs.ls_prolog", f);
5769 }
5770 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5771 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5772 break;
5773
5774 case PIPE_SHADER_TESS_EVAL:
5775 fprintf(f, " as_es = %u\n", key->as_es);
5776 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5777 key->mono.u.vs_export_prim_id);
5778 break;
5779
5780 case PIPE_SHADER_GEOMETRY:
5781 if (shader->is_gs_copy_shader)
5782 break;
5783
5784 if (shader->selector->screen->info.chip_class >= GFX9 &&
5785 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5786 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5787 "part.gs.vs_prolog", f);
5788 }
5789 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5790 break;
5791
5792 case PIPE_SHADER_COMPUTE:
5793 break;
5794
5795 case PIPE_SHADER_FRAGMENT:
5796 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5797 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5798 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5799 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5800 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5801 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5802 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5803 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5804 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5805 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5806 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5807 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5808 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5809 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5810 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5811 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5812 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5813 break;
5814
5815 default:
5816 assert(0);
5817 }
5818
5819 if ((processor == PIPE_SHADER_GEOMETRY ||
5820 processor == PIPE_SHADER_TESS_EVAL ||
5821 processor == PIPE_SHADER_VERTEX) &&
5822 !key->as_es && !key->as_ls) {
5823 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5824 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5825 }
5826 }
5827
5828 static void si_init_shader_ctx(struct si_shader_context *ctx,
5829 struct si_screen *sscreen,
5830 struct ac_llvm_compiler *compiler)
5831 {
5832 struct lp_build_tgsi_context *bld_base;
5833
5834 si_llvm_context_init(ctx, sscreen, compiler);
5835
5836 bld_base = &ctx->bld_base;
5837 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5838
5839 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID].emit = build_interp_intrinsic;
5840 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE].emit = build_interp_intrinsic;
5841 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET].emit = build_interp_intrinsic;
5842
5843 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5844
5845 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5846
5847 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5848 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5849 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5850 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5851
5852 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5853 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5854 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5855 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5856 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5857 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5858 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5859 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5860
5861 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5862 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_tgsi_emit_primitive;
5863 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5864 }
5865
5866 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5867 {
5868 struct si_shader *shader = ctx->shader;
5869 struct tgsi_shader_info *info = &shader->selector->info;
5870
5871 if ((ctx->type != PIPE_SHADER_VERTEX &&
5872 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5873 shader->key.as_ls ||
5874 shader->key.as_es)
5875 return;
5876
5877 ac_optimize_vs_outputs(&ctx->ac,
5878 ctx->main_fn,
5879 shader->info.vs_output_param_offset,
5880 info->num_outputs,
5881 &shader->info.nr_param_exports);
5882 }
5883
5884 static void si_init_exec_from_input(struct si_shader_context *ctx,
5885 unsigned param, unsigned bitoffset)
5886 {
5887 LLVMValueRef args[] = {
5888 LLVMGetParam(ctx->main_fn, param),
5889 LLVMConstInt(ctx->i32, bitoffset, 0),
5890 };
5891 ac_build_intrinsic(&ctx->ac,
5892 "llvm.amdgcn.init.exec.from.input",
5893 ctx->voidt, args, 2, AC_FUNC_ATTR_CONVERGENT);
5894 }
5895
5896 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
5897 const struct si_vs_prolog_bits *key)
5898 {
5899 /* VGPR initialization fixup for Vega10 and Raven is always done in the
5900 * VS prolog. */
5901 return sel->vs_needs_prolog || key->ls_vgpr_fix;
5902 }
5903
5904 static bool si_compile_tgsi_main(struct si_shader_context *ctx)
5905 {
5906 struct si_shader *shader = ctx->shader;
5907 struct si_shader_selector *sel = shader->selector;
5908 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5909
5910 // TODO clean all this up!
5911 switch (ctx->type) {
5912 case PIPE_SHADER_VERTEX:
5913 ctx->load_input = declare_input_vs;
5914 if (shader->key.as_ls)
5915 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
5916 else if (shader->key.as_es)
5917 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5918 else if (shader->key.opt.vs_as_prim_discard_cs)
5919 ctx->abi.emit_outputs = si_llvm_emit_prim_discard_cs_epilogue;
5920 else
5921 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5922 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5923 ctx->abi.load_base_vertex = get_base_vertex;
5924 break;
5925 case PIPE_SHADER_TESS_CTRL:
5926 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5927 ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
5928 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5929 bld_base->emit_store = store_output_tcs;
5930 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
5931 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
5932 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
5933 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5934 break;
5935 case PIPE_SHADER_TESS_EVAL:
5936 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
5937 ctx->abi.load_tess_varyings = si_nir_load_input_tes;
5938 ctx->abi.load_tess_coord = si_load_tess_coord;
5939 ctx->abi.load_tess_level = si_load_tess_level;
5940 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
5941 if (shader->key.as_es)
5942 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5943 else
5944 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5945 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5946 break;
5947 case PIPE_SHADER_GEOMETRY:
5948 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
5949 ctx->abi.load_inputs = si_nir_load_input_gs;
5950 ctx->abi.emit_vertex = si_llvm_emit_vertex;
5951 ctx->abi.emit_primitive = si_llvm_emit_primitive;
5952 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
5953 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
5954 break;
5955 case PIPE_SHADER_FRAGMENT:
5956 ctx->load_input = declare_input_fs;
5957 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
5958 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5959 ctx->abi.lookup_interp_param = si_nir_lookup_interp_param;
5960 ctx->abi.load_sample_position = load_sample_position;
5961 ctx->abi.load_sample_mask_in = load_sample_mask_in;
5962 ctx->abi.emit_kill = si_llvm_emit_kill;
5963 break;
5964 case PIPE_SHADER_COMPUTE:
5965 ctx->abi.load_local_group_size = get_block_size;
5966 break;
5967 default:
5968 assert(!"Unsupported shader type");
5969 return false;
5970 }
5971
5972 ctx->abi.load_ubo = load_ubo;
5973 ctx->abi.load_ssbo = load_ssbo;
5974
5975 create_function(ctx);
5976 preload_ring_buffers(ctx);
5977
5978 /* For GFX9 merged shaders:
5979 * - Set EXEC for the first shader. If the prolog is present, set
5980 * EXEC there instead.
5981 * - Add a barrier before the second shader.
5982 * - In the second shader, reset EXEC to ~0 and wrap the main part in
5983 * an if-statement. This is required for correctness in geometry
5984 * shaders, to ensure that empty GS waves do not send GS_EMIT and
5985 * GS_CUT messages.
5986 *
5987 * For monolithic merged shaders, the first shader is wrapped in an
5988 * if-block together with its prolog in si_build_wrapper_function.
5989 */
5990 if (ctx->screen->info.chip_class >= GFX9) {
5991 if (!shader->is_monolithic &&
5992 sel->info.num_instructions > 1 && /* not empty shader */
5993 (shader->key.as_es || shader->key.as_ls) &&
5994 (ctx->type == PIPE_SHADER_TESS_EVAL ||
5995 (ctx->type == PIPE_SHADER_VERTEX &&
5996 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
5997 si_init_exec_from_input(ctx,
5998 ctx->param_merged_wave_info, 0);
5999 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6000 ctx->type == PIPE_SHADER_GEOMETRY) {
6001 if (!shader->is_monolithic)
6002 ac_init_exec_full_mask(&ctx->ac);
6003
6004 LLVMValueRef num_threads = si_unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
6005 LLVMValueRef ena =
6006 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
6007 ac_get_thread_id(&ctx->ac), num_threads, "");
6008 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
6009
6010 /* The barrier must execute for all shaders in a
6011 * threadgroup.
6012 *
6013 * Execute the barrier inside the conditional block,
6014 * so that empty waves can jump directly to s_endpgm,
6015 * which will also signal the barrier.
6016 *
6017 * If the shader is TCS and the TCS epilog is present
6018 * and contains a barrier, it will wait there and then
6019 * reach s_endpgm.
6020 */
6021 si_llvm_emit_barrier(NULL, bld_base, NULL);
6022 }
6023 }
6024
6025 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
6026 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
6027 for (unsigned i = 0; i < 6; i++) {
6028 ctx->invoc0_tess_factors[i] =
6029 ac_build_alloca_undef(&ctx->ac, ctx->i32, "");
6030 }
6031 }
6032
6033 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6034 int i;
6035 for (i = 0; i < 4; i++) {
6036 ctx->gs_next_vertex[i] =
6037 ac_build_alloca(&ctx->ac, ctx->i32, "");
6038 }
6039 }
6040
6041 if (sel->force_correct_derivs_after_kill) {
6042 ctx->postponed_kill = ac_build_alloca_undef(&ctx->ac, ctx->i1, "");
6043 /* true = don't kill. */
6044 LLVMBuildStore(ctx->ac.builder, ctx->i1true,
6045 ctx->postponed_kill);
6046 }
6047
6048 if (sel->tokens) {
6049 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6050 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6051 return false;
6052 }
6053 } else {
6054 if (!si_nir_build_llvm(ctx, sel->nir)) {
6055 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
6056 return false;
6057 }
6058 }
6059
6060 si_llvm_build_ret(ctx, ctx->return_value);
6061 return true;
6062 }
6063
6064 /**
6065 * Compute the VS prolog key, which contains all the information needed to
6066 * build the VS prolog function, and set shader->info bits where needed.
6067 *
6068 * \param info Shader info of the vertex shader.
6069 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6070 * \param prolog_key Key of the VS prolog
6071 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6072 * \param key Output shader part key.
6073 */
6074 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
6075 unsigned num_input_sgprs,
6076 const struct si_vs_prolog_bits *prolog_key,
6077 struct si_shader *shader_out,
6078 union si_shader_part_key *key)
6079 {
6080 memset(key, 0, sizeof(*key));
6081 key->vs_prolog.states = *prolog_key;
6082 key->vs_prolog.num_input_sgprs = num_input_sgprs;
6083 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6084 key->vs_prolog.as_ls = shader_out->key.as_ls;
6085 key->vs_prolog.as_es = shader_out->key.as_es;
6086
6087 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
6088 key->vs_prolog.as_ls = 1;
6089 key->vs_prolog.num_merged_next_stage_vgprs = 2;
6090 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
6091 key->vs_prolog.as_es = 1;
6092 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6093 }
6094
6095 /* Enable loading the InstanceID VGPR. */
6096 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
6097
6098 if ((key->vs_prolog.states.instance_divisor_is_one |
6099 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
6100 shader_out->info.uses_instanceid = true;
6101 }
6102
6103 /**
6104 * Compute the PS prolog key, which contains all the information needed to
6105 * build the PS prolog function, and set related bits in shader->config.
6106 */
6107 static void si_get_ps_prolog_key(struct si_shader *shader,
6108 union si_shader_part_key *key,
6109 bool separate_prolog)
6110 {
6111 struct tgsi_shader_info *info = &shader->selector->info;
6112
6113 memset(key, 0, sizeof(*key));
6114 key->ps_prolog.states = shader->key.part.ps.prolog;
6115 key->ps_prolog.colors_read = info->colors_read;
6116 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6117 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6118 key->ps_prolog.wqm = info->uses_derivatives &&
6119 (key->ps_prolog.colors_read ||
6120 key->ps_prolog.states.force_persp_sample_interp ||
6121 key->ps_prolog.states.force_linear_sample_interp ||
6122 key->ps_prolog.states.force_persp_center_interp ||
6123 key->ps_prolog.states.force_linear_center_interp ||
6124 key->ps_prolog.states.bc_optimize_for_persp ||
6125 key->ps_prolog.states.bc_optimize_for_linear);
6126 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
6127
6128 if (info->colors_read) {
6129 unsigned *color = shader->selector->color_attr_index;
6130
6131 if (shader->key.part.ps.prolog.color_two_side) {
6132 /* BCOLORs are stored after the last input. */
6133 key->ps_prolog.num_interp_inputs = info->num_inputs;
6134 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6135 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6136 }
6137
6138 for (unsigned i = 0; i < 2; i++) {
6139 unsigned interp = info->input_interpolate[color[i]];
6140 unsigned location = info->input_interpolate_loc[color[i]];
6141
6142 if (!(info->colors_read & (0xf << i*4)))
6143 continue;
6144
6145 key->ps_prolog.color_attr_index[i] = color[i];
6146
6147 if (shader->key.part.ps.prolog.flatshade_colors &&
6148 interp == TGSI_INTERPOLATE_COLOR)
6149 interp = TGSI_INTERPOLATE_CONSTANT;
6150
6151 switch (interp) {
6152 case TGSI_INTERPOLATE_CONSTANT:
6153 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6154 break;
6155 case TGSI_INTERPOLATE_PERSPECTIVE:
6156 case TGSI_INTERPOLATE_COLOR:
6157 /* Force the interpolation location for colors here. */
6158 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6159 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6160 if (shader->key.part.ps.prolog.force_persp_center_interp)
6161 location = TGSI_INTERPOLATE_LOC_CENTER;
6162
6163 switch (location) {
6164 case TGSI_INTERPOLATE_LOC_SAMPLE:
6165 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6166 shader->config.spi_ps_input_ena |=
6167 S_0286CC_PERSP_SAMPLE_ENA(1);
6168 break;
6169 case TGSI_INTERPOLATE_LOC_CENTER:
6170 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6171 shader->config.spi_ps_input_ena |=
6172 S_0286CC_PERSP_CENTER_ENA(1);
6173 break;
6174 case TGSI_INTERPOLATE_LOC_CENTROID:
6175 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6176 shader->config.spi_ps_input_ena |=
6177 S_0286CC_PERSP_CENTROID_ENA(1);
6178 break;
6179 default:
6180 assert(0);
6181 }
6182 break;
6183 case TGSI_INTERPOLATE_LINEAR:
6184 /* Force the interpolation location for colors here. */
6185 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6186 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6187 if (shader->key.part.ps.prolog.force_linear_center_interp)
6188 location = TGSI_INTERPOLATE_LOC_CENTER;
6189
6190 /* The VGPR assignment for non-monolithic shaders
6191 * works because InitialPSInputAddr is set on the
6192 * main shader and PERSP_PULL_MODEL is never used.
6193 */
6194 switch (location) {
6195 case TGSI_INTERPOLATE_LOC_SAMPLE:
6196 key->ps_prolog.color_interp_vgpr_index[i] =
6197 separate_prolog ? 6 : 9;
6198 shader->config.spi_ps_input_ena |=
6199 S_0286CC_LINEAR_SAMPLE_ENA(1);
6200 break;
6201 case TGSI_INTERPOLATE_LOC_CENTER:
6202 key->ps_prolog.color_interp_vgpr_index[i] =
6203 separate_prolog ? 8 : 11;
6204 shader->config.spi_ps_input_ena |=
6205 S_0286CC_LINEAR_CENTER_ENA(1);
6206 break;
6207 case TGSI_INTERPOLATE_LOC_CENTROID:
6208 key->ps_prolog.color_interp_vgpr_index[i] =
6209 separate_prolog ? 10 : 13;
6210 shader->config.spi_ps_input_ena |=
6211 S_0286CC_LINEAR_CENTROID_ENA(1);
6212 break;
6213 default:
6214 assert(0);
6215 }
6216 break;
6217 default:
6218 assert(0);
6219 }
6220 }
6221 }
6222 }
6223
6224 /**
6225 * Check whether a PS prolog is required based on the key.
6226 */
6227 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6228 {
6229 return key->ps_prolog.colors_read ||
6230 key->ps_prolog.states.force_persp_sample_interp ||
6231 key->ps_prolog.states.force_linear_sample_interp ||
6232 key->ps_prolog.states.force_persp_center_interp ||
6233 key->ps_prolog.states.force_linear_center_interp ||
6234 key->ps_prolog.states.bc_optimize_for_persp ||
6235 key->ps_prolog.states.bc_optimize_for_linear ||
6236 key->ps_prolog.states.poly_stipple ||
6237 key->ps_prolog.states.samplemask_log_ps_iter;
6238 }
6239
6240 /**
6241 * Compute the PS epilog key, which contains all the information needed to
6242 * build the PS epilog function.
6243 */
6244 static void si_get_ps_epilog_key(struct si_shader *shader,
6245 union si_shader_part_key *key)
6246 {
6247 struct tgsi_shader_info *info = &shader->selector->info;
6248 memset(key, 0, sizeof(*key));
6249 key->ps_epilog.colors_written = info->colors_written;
6250 key->ps_epilog.writes_z = info->writes_z;
6251 key->ps_epilog.writes_stencil = info->writes_stencil;
6252 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6253 key->ps_epilog.states = shader->key.part.ps.epilog;
6254 }
6255
6256 /**
6257 * Build the GS prolog function. Rotate the input vertices for triangle strips
6258 * with adjacency.
6259 */
6260 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6261 union si_shader_part_key *key)
6262 {
6263 unsigned num_sgprs, num_vgprs;
6264 struct si_function_info fninfo;
6265 LLVMBuilderRef builder = ctx->ac.builder;
6266 LLVMTypeRef returns[48];
6267 LLVMValueRef func, ret;
6268
6269 si_init_function_info(&fninfo);
6270
6271 if (ctx->screen->info.chip_class >= GFX9) {
6272 if (key->gs_prolog.states.gfx9_prev_is_vs)
6273 num_sgprs = 8 + GFX9_VSGS_NUM_USER_SGPR;
6274 else
6275 num_sgprs = 8 + GFX9_TESGS_NUM_USER_SGPR;
6276 num_vgprs = 5; /* ES inputs are not needed by GS */
6277 } else {
6278 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6279 num_vgprs = 8;
6280 }
6281
6282 for (unsigned i = 0; i < num_sgprs; ++i) {
6283 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6284 returns[i] = ctx->i32;
6285 }
6286
6287 for (unsigned i = 0; i < num_vgprs; ++i) {
6288 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6289 returns[num_sgprs + i] = ctx->f32;
6290 }
6291
6292 /* Create the function. */
6293 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6294 &fninfo, 0);
6295 func = ctx->main_fn;
6296
6297 /* Set the full EXEC mask for the prolog, because we are only fiddling
6298 * with registers here. The main shader part will set the correct EXEC
6299 * mask.
6300 */
6301 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6302 ac_init_exec_full_mask(&ctx->ac);
6303
6304 /* Copy inputs to outputs. This should be no-op, as the registers match,
6305 * but it will prevent the compiler from overwriting them unintentionally.
6306 */
6307 ret = ctx->return_value;
6308 for (unsigned i = 0; i < num_sgprs; i++) {
6309 LLVMValueRef p = LLVMGetParam(func, i);
6310 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6311 }
6312 for (unsigned i = 0; i < num_vgprs; i++) {
6313 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6314 p = ac_to_float(&ctx->ac, p);
6315 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6316 }
6317
6318 if (key->gs_prolog.states.tri_strip_adj_fix) {
6319 /* Remap the input vertices for every other primitive. */
6320 const unsigned gfx6_vtx_params[6] = {
6321 num_sgprs,
6322 num_sgprs + 1,
6323 num_sgprs + 3,
6324 num_sgprs + 4,
6325 num_sgprs + 5,
6326 num_sgprs + 6
6327 };
6328 const unsigned gfx9_vtx_params[3] = {
6329 num_sgprs,
6330 num_sgprs + 1,
6331 num_sgprs + 4,
6332 };
6333 LLVMValueRef vtx_in[6], vtx_out[6];
6334 LLVMValueRef prim_id, rotate;
6335
6336 if (ctx->screen->info.chip_class >= GFX9) {
6337 for (unsigned i = 0; i < 3; i++) {
6338 vtx_in[i*2] = si_unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6339 vtx_in[i*2+1] = si_unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6340 }
6341 } else {
6342 for (unsigned i = 0; i < 6; i++)
6343 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6344 }
6345
6346 prim_id = LLVMGetParam(func, num_sgprs + 2);
6347 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6348
6349 for (unsigned i = 0; i < 6; ++i) {
6350 LLVMValueRef base, rotated;
6351 base = vtx_in[i];
6352 rotated = vtx_in[(i + 4) % 6];
6353 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6354 }
6355
6356 if (ctx->screen->info.chip_class >= GFX9) {
6357 for (unsigned i = 0; i < 3; i++) {
6358 LLVMValueRef hi, out;
6359
6360 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6361 LLVMConstInt(ctx->i32, 16, 0), "");
6362 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6363 out = ac_to_float(&ctx->ac, out);
6364 ret = LLVMBuildInsertValue(builder, ret, out,
6365 gfx9_vtx_params[i], "");
6366 }
6367 } else {
6368 for (unsigned i = 0; i < 6; i++) {
6369 LLVMValueRef out;
6370
6371 out = ac_to_float(&ctx->ac, vtx_out[i]);
6372 ret = LLVMBuildInsertValue(builder, ret, out,
6373 gfx6_vtx_params[i], "");
6374 }
6375 }
6376 }
6377
6378 LLVMBuildRet(builder, ret);
6379 }
6380
6381 /**
6382 * Given a list of shader part functions, build a wrapper function that
6383 * runs them in sequence to form a monolithic shader.
6384 */
6385 static void si_build_wrapper_function(struct si_shader_context *ctx,
6386 LLVMValueRef *parts,
6387 unsigned num_parts,
6388 unsigned main_part,
6389 unsigned next_shader_first_part)
6390 {
6391 LLVMBuilderRef builder = ctx->ac.builder;
6392 /* PS epilog has one arg per color component; gfx9 merged shader
6393 * prologs need to forward 32 user SGPRs.
6394 */
6395 struct si_function_info fninfo;
6396 LLVMValueRef initial[64], out[64];
6397 LLVMTypeRef function_type;
6398 unsigned num_first_params;
6399 unsigned num_out, initial_num_out;
6400 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6401 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6402 unsigned num_sgprs, num_vgprs;
6403 unsigned gprs;
6404 struct lp_build_if_state if_state;
6405
6406 si_init_function_info(&fninfo);
6407
6408 for (unsigned i = 0; i < num_parts; ++i) {
6409 ac_add_function_attr(ctx->ac.context, parts[i], -1,
6410 AC_FUNC_ATTR_ALWAYSINLINE);
6411 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6412 }
6413
6414 /* The parameters of the wrapper function correspond to those of the
6415 * first part in terms of SGPRs and VGPRs, but we use the types of the
6416 * main part to get the right types. This is relevant for the
6417 * dereferenceable attribute on descriptor table pointers.
6418 */
6419 num_sgprs = 0;
6420 num_vgprs = 0;
6421
6422 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6423 num_first_params = LLVMCountParamTypes(function_type);
6424
6425 for (unsigned i = 0; i < num_first_params; ++i) {
6426 LLVMValueRef param = LLVMGetParam(parts[0], i);
6427
6428 if (ac_is_sgpr_param(param)) {
6429 assert(num_vgprs == 0);
6430 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6431 } else {
6432 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6433 }
6434 }
6435
6436 gprs = 0;
6437 while (gprs < num_sgprs + num_vgprs) {
6438 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6439 LLVMTypeRef type = LLVMTypeOf(param);
6440 unsigned size = ac_get_type_size(type) / 4;
6441
6442 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6443
6444 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6445 assert(gprs + size <= num_sgprs + num_vgprs &&
6446 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6447
6448 gprs += size;
6449 }
6450
6451 /* Prepare the return type. */
6452 unsigned num_returns = 0;
6453 LLVMTypeRef returns[32], last_func_type, return_type;
6454
6455 last_func_type = LLVMGetElementType(LLVMTypeOf(parts[num_parts - 1]));
6456 return_type = LLVMGetReturnType(last_func_type);
6457
6458 switch (LLVMGetTypeKind(return_type)) {
6459 case LLVMStructTypeKind:
6460 num_returns = LLVMCountStructElementTypes(return_type);
6461 assert(num_returns <= ARRAY_SIZE(returns));
6462 LLVMGetStructElementTypes(return_type, returns);
6463 break;
6464 case LLVMVoidTypeKind:
6465 break;
6466 default:
6467 unreachable("unexpected type");
6468 }
6469
6470 si_create_function(ctx, "wrapper", returns, num_returns, &fninfo,
6471 si_get_max_workgroup_size(ctx->shader));
6472
6473 if (is_merged_shader(ctx))
6474 ac_init_exec_full_mask(&ctx->ac);
6475
6476 /* Record the arguments of the function as if they were an output of
6477 * a previous part.
6478 */
6479 num_out = 0;
6480 num_out_sgpr = 0;
6481
6482 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6483 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6484 LLVMTypeRef param_type = LLVMTypeOf(param);
6485 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6486 unsigned size = ac_get_type_size(param_type) / 4;
6487
6488 if (size == 1) {
6489 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6490 param = LLVMBuildPtrToInt(builder, param, ctx->i32, "");
6491 param_type = ctx->i32;
6492 }
6493
6494 if (param_type != out_type)
6495 param = LLVMBuildBitCast(builder, param, out_type, "");
6496 out[num_out++] = param;
6497 } else {
6498 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6499
6500 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6501 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6502 param_type = ctx->i64;
6503 }
6504
6505 if (param_type != vector_type)
6506 param = LLVMBuildBitCast(builder, param, vector_type, "");
6507
6508 for (unsigned j = 0; j < size; ++j)
6509 out[num_out++] = LLVMBuildExtractElement(
6510 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6511 }
6512
6513 if (i < fninfo.num_sgpr_params)
6514 num_out_sgpr = num_out;
6515 }
6516
6517 memcpy(initial, out, sizeof(out));
6518 initial_num_out = num_out;
6519 initial_num_out_sgpr = num_out_sgpr;
6520
6521 /* Now chain the parts. */
6522 LLVMValueRef ret;
6523 for (unsigned part = 0; part < num_parts; ++part) {
6524 LLVMValueRef in[48];
6525 LLVMTypeRef ret_type;
6526 unsigned out_idx = 0;
6527 unsigned num_params = LLVMCountParams(parts[part]);
6528
6529 /* Merged shaders are executed conditionally depending
6530 * on the number of enabled threads passed in the input SGPRs. */
6531 if (is_merged_shader(ctx) && part == 0) {
6532 LLVMValueRef ena, count = initial[3];
6533
6534 count = LLVMBuildAnd(builder, count,
6535 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6536 ena = LLVMBuildICmp(builder, LLVMIntULT,
6537 ac_get_thread_id(&ctx->ac), count, "");
6538 lp_build_if(&if_state, &ctx->gallivm, ena);
6539 }
6540
6541 /* Derive arguments for the next part from outputs of the
6542 * previous one.
6543 */
6544 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6545 LLVMValueRef param;
6546 LLVMTypeRef param_type;
6547 bool is_sgpr;
6548 unsigned param_size;
6549 LLVMValueRef arg = NULL;
6550
6551 param = LLVMGetParam(parts[part], param_idx);
6552 param_type = LLVMTypeOf(param);
6553 param_size = ac_get_type_size(param_type) / 4;
6554 is_sgpr = ac_is_sgpr_param(param);
6555
6556 if (is_sgpr) {
6557 ac_add_function_attr(ctx->ac.context, parts[part],
6558 param_idx + 1, AC_FUNC_ATTR_INREG);
6559 } else if (out_idx < num_out_sgpr) {
6560 /* Skip returned SGPRs the current part doesn't
6561 * declare on the input. */
6562 out_idx = num_out_sgpr;
6563 }
6564
6565 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6566
6567 if (param_size == 1)
6568 arg = out[out_idx];
6569 else
6570 arg = ac_build_gather_values(&ctx->ac, &out[out_idx], param_size);
6571
6572 if (LLVMTypeOf(arg) != param_type) {
6573 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6574 if (LLVMGetPointerAddressSpace(param_type) ==
6575 AC_ADDR_SPACE_CONST_32BIT) {
6576 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
6577 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6578 } else {
6579 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6580 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6581 }
6582 } else {
6583 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6584 }
6585 }
6586
6587 in[param_idx] = arg;
6588 out_idx += param_size;
6589 }
6590
6591 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6592
6593 if (is_merged_shader(ctx) &&
6594 part + 1 == next_shader_first_part) {
6595 lp_build_endif(&if_state);
6596
6597 /* The second half of the merged shader should use
6598 * the inputs from the toplevel (wrapper) function,
6599 * not the return value from the last call.
6600 *
6601 * That's because the last call was executed condi-
6602 * tionally, so we can't consume it in the main
6603 * block.
6604 */
6605 memcpy(out, initial, sizeof(initial));
6606 num_out = initial_num_out;
6607 num_out_sgpr = initial_num_out_sgpr;
6608 continue;
6609 }
6610
6611 /* Extract the returned GPRs. */
6612 ret_type = LLVMTypeOf(ret);
6613 num_out = 0;
6614 num_out_sgpr = 0;
6615
6616 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6617 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6618
6619 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6620
6621 for (unsigned i = 0; i < ret_size; ++i) {
6622 LLVMValueRef val =
6623 LLVMBuildExtractValue(builder, ret, i, "");
6624
6625 assert(num_out < ARRAY_SIZE(out));
6626 out[num_out++] = val;
6627
6628 if (LLVMTypeOf(val) == ctx->i32) {
6629 assert(num_out_sgpr + 1 == num_out);
6630 num_out_sgpr = num_out;
6631 }
6632 }
6633 }
6634 }
6635
6636 /* Return the value from the last part. */
6637 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6638 LLVMBuildRetVoid(builder);
6639 else
6640 LLVMBuildRet(builder, ret);
6641 }
6642
6643 static bool si_should_optimize_less(struct ac_llvm_compiler *compiler,
6644 struct si_shader_selector *sel)
6645 {
6646 if (!compiler->low_opt_passes)
6647 return false;
6648
6649 /* Assume a slow CPU. */
6650 assert(!sel->screen->info.has_dedicated_vram &&
6651 sel->screen->info.chip_class <= GFX8);
6652
6653 /* For a crazy dEQP test containing 2597 memory opcodes, mostly
6654 * buffer stores. */
6655 return sel->type == PIPE_SHADER_COMPUTE &&
6656 sel->info.num_memory_instructions > 1000;
6657 }
6658
6659 int si_compile_tgsi_shader(struct si_screen *sscreen,
6660 struct ac_llvm_compiler *compiler,
6661 struct si_shader *shader,
6662 struct pipe_debug_callback *debug)
6663 {
6664 struct si_shader_selector *sel = shader->selector;
6665 struct si_shader_context ctx;
6666 int r = -1;
6667
6668 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6669 * conversion fails. */
6670 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6671 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6672 if (sel->tokens)
6673 tgsi_dump(sel->tokens, 0);
6674 else
6675 nir_print_shader(sel->nir, stderr);
6676 si_dump_streamout(&sel->so);
6677 }
6678
6679 si_init_shader_ctx(&ctx, sscreen, compiler);
6680 si_llvm_context_set_tgsi(&ctx, shader);
6681
6682 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6683 sizeof(shader->info.vs_output_param_offset));
6684
6685 shader->info.uses_instanceid = sel->info.uses_instanceid;
6686
6687 if (!si_compile_tgsi_main(&ctx)) {
6688 si_llvm_dispose(&ctx);
6689 return -1;
6690 }
6691
6692 if (shader->is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6693 LLVMValueRef parts[2];
6694 bool need_prolog = sel->vs_needs_prolog;
6695
6696 parts[1] = ctx.main_fn;
6697
6698 if (need_prolog) {
6699 union si_shader_part_key prolog_key;
6700 si_get_vs_prolog_key(&sel->info,
6701 shader->info.num_input_sgprs,
6702 &shader->key.part.vs.prolog,
6703 shader, &prolog_key);
6704 si_build_vs_prolog_function(&ctx, &prolog_key);
6705 parts[0] = ctx.main_fn;
6706 }
6707
6708 si_build_wrapper_function(&ctx, parts + !need_prolog,
6709 1 + need_prolog, need_prolog, 0);
6710
6711 if (ctx.shader->key.opt.vs_as_prim_discard_cs)
6712 si_build_prim_discard_compute_shader(&ctx);
6713 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6714 if (sscreen->info.chip_class >= GFX9) {
6715 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6716 LLVMValueRef parts[4];
6717 bool vs_needs_prolog =
6718 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6719
6720 /* TCS main part */
6721 parts[2] = ctx.main_fn;
6722
6723 /* TCS epilog */
6724 union si_shader_part_key tcs_epilog_key;
6725 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6726 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6727 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6728 parts[3] = ctx.main_fn;
6729
6730 /* VS as LS main part */
6731 struct si_shader shader_ls = {};
6732 shader_ls.selector = ls;
6733 shader_ls.key.as_ls = 1;
6734 shader_ls.key.mono = shader->key.mono;
6735 shader_ls.key.opt = shader->key.opt;
6736 shader_ls.is_monolithic = true;
6737 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6738
6739 if (!si_compile_tgsi_main(&ctx)) {
6740 si_llvm_dispose(&ctx);
6741 return -1;
6742 }
6743 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6744 parts[1] = ctx.main_fn;
6745
6746 /* LS prolog */
6747 if (vs_needs_prolog) {
6748 union si_shader_part_key vs_prolog_key;
6749 si_get_vs_prolog_key(&ls->info,
6750 shader_ls.info.num_input_sgprs,
6751 &shader->key.part.tcs.ls_prolog,
6752 shader, &vs_prolog_key);
6753 vs_prolog_key.vs_prolog.is_monolithic = true;
6754 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6755 parts[0] = ctx.main_fn;
6756 }
6757
6758 /* Reset the shader context. */
6759 ctx.shader = shader;
6760 ctx.type = PIPE_SHADER_TESS_CTRL;
6761
6762 si_build_wrapper_function(&ctx,
6763 parts + !vs_needs_prolog,
6764 4 - !vs_needs_prolog, vs_needs_prolog,
6765 vs_needs_prolog ? 2 : 1);
6766 } else {
6767 LLVMValueRef parts[2];
6768 union si_shader_part_key epilog_key;
6769
6770 parts[0] = ctx.main_fn;
6771
6772 memset(&epilog_key, 0, sizeof(epilog_key));
6773 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6774 si_build_tcs_epilog_function(&ctx, &epilog_key);
6775 parts[1] = ctx.main_fn;
6776
6777 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6778 }
6779 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6780 if (ctx.screen->info.chip_class >= GFX9) {
6781 struct si_shader_selector *es = shader->key.part.gs.es;
6782 LLVMValueRef es_prolog = NULL;
6783 LLVMValueRef es_main = NULL;
6784 LLVMValueRef gs_prolog = NULL;
6785 LLVMValueRef gs_main = ctx.main_fn;
6786
6787 /* GS prolog */
6788 union si_shader_part_key gs_prolog_key;
6789 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6790 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6791 gs_prolog_key.gs_prolog.is_monolithic = true;
6792 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6793 gs_prolog = ctx.main_fn;
6794
6795 /* ES main part */
6796 struct si_shader shader_es = {};
6797 shader_es.selector = es;
6798 shader_es.key.as_es = 1;
6799 shader_es.key.mono = shader->key.mono;
6800 shader_es.key.opt = shader->key.opt;
6801 shader_es.is_monolithic = true;
6802 si_llvm_context_set_tgsi(&ctx, &shader_es);
6803
6804 if (!si_compile_tgsi_main(&ctx)) {
6805 si_llvm_dispose(&ctx);
6806 return -1;
6807 }
6808 shader->info.uses_instanceid |= es->info.uses_instanceid;
6809 es_main = ctx.main_fn;
6810
6811 /* ES prolog */
6812 if (es->vs_needs_prolog) {
6813 union si_shader_part_key vs_prolog_key;
6814 si_get_vs_prolog_key(&es->info,
6815 shader_es.info.num_input_sgprs,
6816 &shader->key.part.gs.vs_prolog,
6817 shader, &vs_prolog_key);
6818 vs_prolog_key.vs_prolog.is_monolithic = true;
6819 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6820 es_prolog = ctx.main_fn;
6821 }
6822
6823 /* Reset the shader context. */
6824 ctx.shader = shader;
6825 ctx.type = PIPE_SHADER_GEOMETRY;
6826
6827 /* Prepare the array of shader parts. */
6828 LLVMValueRef parts[4];
6829 unsigned num_parts = 0, main_part, next_first_part;
6830
6831 if (es_prolog)
6832 parts[num_parts++] = es_prolog;
6833
6834 parts[main_part = num_parts++] = es_main;
6835 parts[next_first_part = num_parts++] = gs_prolog;
6836 parts[num_parts++] = gs_main;
6837
6838 si_build_wrapper_function(&ctx, parts, num_parts,
6839 main_part, next_first_part);
6840 } else {
6841 LLVMValueRef parts[2];
6842 union si_shader_part_key prolog_key;
6843
6844 parts[1] = ctx.main_fn;
6845
6846 memset(&prolog_key, 0, sizeof(prolog_key));
6847 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6848 si_build_gs_prolog_function(&ctx, &prolog_key);
6849 parts[0] = ctx.main_fn;
6850
6851 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6852 }
6853 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6854 LLVMValueRef parts[3];
6855 union si_shader_part_key prolog_key;
6856 union si_shader_part_key epilog_key;
6857 bool need_prolog;
6858
6859 si_get_ps_prolog_key(shader, &prolog_key, false);
6860 need_prolog = si_need_ps_prolog(&prolog_key);
6861
6862 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6863
6864 if (need_prolog) {
6865 si_build_ps_prolog_function(&ctx, &prolog_key);
6866 parts[0] = ctx.main_fn;
6867 }
6868
6869 si_get_ps_epilog_key(shader, &epilog_key);
6870 si_build_ps_epilog_function(&ctx, &epilog_key);
6871 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6872
6873 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6874 need_prolog ? 1 : 0, 0);
6875 }
6876
6877 si_llvm_optimize_module(&ctx);
6878
6879 /* Post-optimization transformations and analysis. */
6880 si_optimize_vs_outputs(&ctx);
6881
6882 if ((debug && debug->debug_message) ||
6883 si_can_dump_shader(sscreen, ctx.type)) {
6884 ctx.shader->info.private_mem_vgprs =
6885 ac_count_scratch_private_memory(ctx.main_fn);
6886 }
6887
6888 /* Make sure the input is a pointer and not integer followed by inttoptr. */
6889 assert(LLVMGetTypeKind(LLVMTypeOf(LLVMGetParam(ctx.main_fn, 0))) ==
6890 LLVMPointerTypeKind);
6891
6892 /* Compile to bytecode. */
6893 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, compiler,
6894 ctx.ac.module, debug, ctx.type,
6895 si_get_shader_name(shader, ctx.type),
6896 si_should_optimize_less(compiler, shader->selector));
6897 si_llvm_dispose(&ctx);
6898 if (r) {
6899 fprintf(stderr, "LLVM failed to compile shader\n");
6900 return r;
6901 }
6902
6903 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6904 * LLVM 3.9svn has this bug.
6905 */
6906 if (sel->type == PIPE_SHADER_COMPUTE) {
6907 unsigned wave_size = 64;
6908 unsigned max_vgprs = 256;
6909 unsigned max_sgprs = sscreen->info.chip_class >= GFX8 ? 800 : 512;
6910 unsigned max_sgprs_per_wave = 128;
6911 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6912 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6913 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6914
6915 max_vgprs = max_vgprs / min_waves_per_simd;
6916 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6917
6918 if (shader->config.num_sgprs > max_sgprs ||
6919 shader->config.num_vgprs > max_vgprs) {
6920 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6921 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6922 shader->config.num_sgprs, shader->config.num_vgprs,
6923 max_sgprs, max_vgprs);
6924
6925 /* Just terminate the process, because dependent
6926 * shaders can hang due to bad input data, but use
6927 * the env var to allow shader-db to work.
6928 */
6929 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6930 abort();
6931 }
6932 }
6933
6934 /* Add the scratch offset to input SGPRs. */
6935 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(&ctx))
6936 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6937
6938 /* Calculate the number of fragment input VGPRs. */
6939 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6940 shader->info.num_input_vgprs = 0;
6941 shader->info.face_vgpr_index = -1;
6942 shader->info.ancillary_vgpr_index = -1;
6943
6944 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6945 shader->info.num_input_vgprs += 2;
6946 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6947 shader->info.num_input_vgprs += 2;
6948 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6949 shader->info.num_input_vgprs += 2;
6950 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6951 shader->info.num_input_vgprs += 3;
6952 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6953 shader->info.num_input_vgprs += 2;
6954 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6955 shader->info.num_input_vgprs += 2;
6956 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6957 shader->info.num_input_vgprs += 2;
6958 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6959 shader->info.num_input_vgprs += 1;
6960 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6961 shader->info.num_input_vgprs += 1;
6962 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6963 shader->info.num_input_vgprs += 1;
6964 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6965 shader->info.num_input_vgprs += 1;
6966 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6967 shader->info.num_input_vgprs += 1;
6968 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6969 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6970 shader->info.num_input_vgprs += 1;
6971 }
6972 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
6973 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
6974 shader->info.num_input_vgprs += 1;
6975 }
6976 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6977 shader->info.num_input_vgprs += 1;
6978 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6979 shader->info.num_input_vgprs += 1;
6980 }
6981
6982 si_calculate_max_simd_waves(shader);
6983 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
6984 return 0;
6985 }
6986
6987 /**
6988 * Create, compile and return a shader part (prolog or epilog).
6989 *
6990 * \param sscreen screen
6991 * \param list list of shader parts of the same category
6992 * \param type shader type
6993 * \param key shader part key
6994 * \param prolog whether the part being requested is a prolog
6995 * \param tm LLVM target machine
6996 * \param debug debug callback
6997 * \param build the callback responsible for building the main function
6998 * \return non-NULL on success
6999 */
7000 static struct si_shader_part *
7001 si_get_shader_part(struct si_screen *sscreen,
7002 struct si_shader_part **list,
7003 enum pipe_shader_type type,
7004 bool prolog,
7005 union si_shader_part_key *key,
7006 struct ac_llvm_compiler *compiler,
7007 struct pipe_debug_callback *debug,
7008 void (*build)(struct si_shader_context *,
7009 union si_shader_part_key *),
7010 const char *name)
7011 {
7012 struct si_shader_part *result;
7013
7014 mtx_lock(&sscreen->shader_parts_mutex);
7015
7016 /* Find existing. */
7017 for (result = *list; result; result = result->next) {
7018 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7019 mtx_unlock(&sscreen->shader_parts_mutex);
7020 return result;
7021 }
7022 }
7023
7024 /* Compile a new one. */
7025 result = CALLOC_STRUCT(si_shader_part);
7026 result->key = *key;
7027
7028 struct si_shader shader = {};
7029 struct si_shader_context ctx;
7030
7031 si_init_shader_ctx(&ctx, sscreen, compiler);
7032 ctx.shader = &shader;
7033 ctx.type = type;
7034
7035 switch (type) {
7036 case PIPE_SHADER_VERTEX:
7037 shader.key.as_ls = key->vs_prolog.as_ls;
7038 shader.key.as_es = key->vs_prolog.as_es;
7039 break;
7040 case PIPE_SHADER_TESS_CTRL:
7041 assert(!prolog);
7042 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7043 break;
7044 case PIPE_SHADER_GEOMETRY:
7045 assert(prolog);
7046 break;
7047 case PIPE_SHADER_FRAGMENT:
7048 if (prolog)
7049 shader.key.part.ps.prolog = key->ps_prolog.states;
7050 else
7051 shader.key.part.ps.epilog = key->ps_epilog.states;
7052 break;
7053 default:
7054 unreachable("bad shader part");
7055 }
7056
7057 build(&ctx, key);
7058
7059 /* Compile. */
7060 si_llvm_optimize_module(&ctx);
7061
7062 if (si_compile_llvm(sscreen, &result->binary, &result->config, compiler,
7063 ctx.ac.module, debug, ctx.type, name, false)) {
7064 FREE(result);
7065 result = NULL;
7066 goto out;
7067 }
7068
7069 result->next = *list;
7070 *list = result;
7071
7072 out:
7073 si_llvm_dispose(&ctx);
7074 mtx_unlock(&sscreen->shader_parts_mutex);
7075 return result;
7076 }
7077
7078 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
7079 {
7080 LLVMValueRef ptr[2], list;
7081 bool merged_shader = is_merged_shader(ctx);
7082
7083 ptr[0] = LLVMGetParam(ctx->main_fn, (merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7084 list = LLVMBuildIntToPtr(ctx->ac.builder, ptr[0],
7085 ac_array_in_const32_addr_space(ctx->v4i32), "");
7086 return list;
7087 }
7088
7089 /**
7090 * Build the vertex shader prolog function.
7091 *
7092 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7093 * All inputs are returned unmodified. The vertex load indices are
7094 * stored after them, which will be used by the API VS for fetching inputs.
7095 *
7096 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7097 * input_v0,
7098 * input_v1,
7099 * input_v2,
7100 * input_v3,
7101 * (VertexID + BaseVertex),
7102 * (InstanceID + StartInstance),
7103 * (InstanceID / 2 + StartInstance)
7104 */
7105 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7106 union si_shader_part_key *key)
7107 {
7108 struct si_function_info fninfo;
7109 LLVMTypeRef *returns;
7110 LLVMValueRef ret, func;
7111 int num_returns, i;
7112 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
7113 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
7114 LLVMValueRef input_vgprs[9];
7115 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
7116 num_input_vgprs;
7117 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
7118
7119 si_init_function_info(&fninfo);
7120
7121 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7122 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
7123 sizeof(LLVMTypeRef));
7124 num_returns = 0;
7125
7126 /* Declare input and output SGPRs. */
7127 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7128 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7129 returns[num_returns++] = ctx->i32;
7130 }
7131
7132 /* Preloaded VGPRs (outputs must be floats) */
7133 for (i = 0; i < num_input_vgprs; i++) {
7134 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
7135 returns[num_returns++] = ctx->f32;
7136 }
7137
7138 /* Vertex load indices. */
7139 for (i = 0; i <= key->vs_prolog.last_input; i++)
7140 returns[num_returns++] = ctx->f32;
7141
7142 /* Create the function. */
7143 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
7144 func = ctx->main_fn;
7145
7146 if (key->vs_prolog.num_merged_next_stage_vgprs) {
7147 if (!key->vs_prolog.is_monolithic)
7148 si_init_exec_from_input(ctx, 3, 0);
7149
7150 if (key->vs_prolog.as_ls &&
7151 ctx->screen->has_ls_vgpr_init_bug) {
7152 /* If there are no HS threads, SPI loads the LS VGPRs
7153 * starting at VGPR 0. Shift them back to where they
7154 * belong.
7155 */
7156 LLVMValueRef has_hs_threads =
7157 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
7158 si_unpack_param(ctx, 3, 8, 8),
7159 ctx->i32_0, "");
7160
7161 for (i = 4; i > 0; --i) {
7162 input_vgprs[i + 1] =
7163 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
7164 input_vgprs[i + 1],
7165 input_vgprs[i - 1], "");
7166 }
7167 }
7168 }
7169
7170 unsigned vertex_id_vgpr = first_vs_vgpr;
7171 unsigned instance_id_vgpr = first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1);
7172
7173 ctx->abi.vertex_id = input_vgprs[vertex_id_vgpr];
7174 ctx->abi.instance_id = input_vgprs[instance_id_vgpr];
7175
7176 /* InstanceID = VertexID >> 16;
7177 * VertexID = VertexID & 0xffff;
7178 */
7179 if (key->vs_prolog.states.unpack_instance_id_from_vertex_id) {
7180 ctx->abi.instance_id = LLVMBuildLShr(ctx->ac.builder, ctx->abi.vertex_id,
7181 LLVMConstInt(ctx->i32, 16, 0), "");
7182 ctx->abi.vertex_id = LLVMBuildAnd(ctx->ac.builder, ctx->abi.vertex_id,
7183 LLVMConstInt(ctx->i32, 0xffff, 0), "");
7184 }
7185
7186 /* Copy inputs to outputs. This should be no-op, as the registers match,
7187 * but it will prevent the compiler from overwriting them unintentionally.
7188 */
7189 ret = ctx->return_value;
7190 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7191 LLVMValueRef p = LLVMGetParam(func, i);
7192 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7193 }
7194 for (i = 0; i < num_input_vgprs; i++) {
7195 LLVMValueRef p = input_vgprs[i];
7196
7197 if (i == vertex_id_vgpr)
7198 p = ctx->abi.vertex_id;
7199 else if (i == instance_id_vgpr)
7200 p = ctx->abi.instance_id;
7201
7202 p = ac_to_float(&ctx->ac, p);
7203 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
7204 key->vs_prolog.num_input_sgprs + i, "");
7205 }
7206
7207 /* Compute vertex load indices from instance divisors. */
7208 LLVMValueRef instance_divisor_constbuf = NULL;
7209
7210 if (key->vs_prolog.states.instance_divisor_is_fetched) {
7211 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7212 LLVMValueRef buf_index =
7213 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
7214 instance_divisor_constbuf =
7215 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
7216 }
7217
7218 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7219 bool divisor_is_one =
7220 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
7221 bool divisor_is_fetched =
7222 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
7223 LLVMValueRef index = NULL;
7224
7225 if (divisor_is_one) {
7226 index = ctx->abi.instance_id;
7227 } else if (divisor_is_fetched) {
7228 LLVMValueRef udiv_factors[4];
7229
7230 for (unsigned j = 0; j < 4; j++) {
7231 udiv_factors[j] =
7232 buffer_load_const(ctx, instance_divisor_constbuf,
7233 LLVMConstInt(ctx->i32, i*16 + j*4, 0));
7234 udiv_factors[j] = ac_to_integer(&ctx->ac, udiv_factors[j]);
7235 }
7236 /* The faster NUW version doesn't work when InstanceID == UINT_MAX.
7237 * Such InstanceID might not be achievable in a reasonable time though.
7238 */
7239 index = ac_build_fast_udiv_nuw(&ctx->ac, ctx->abi.instance_id,
7240 udiv_factors[0], udiv_factors[1],
7241 udiv_factors[2], udiv_factors[3]);
7242 }
7243
7244 if (divisor_is_one || divisor_is_fetched) {
7245 /* Add StartInstance. */
7246 index = LLVMBuildAdd(ctx->ac.builder, index,
7247 LLVMGetParam(ctx->main_fn, user_sgpr_base +
7248 SI_SGPR_START_INSTANCE), "");
7249 } else {
7250 /* VertexID + BaseVertex */
7251 index = LLVMBuildAdd(ctx->ac.builder,
7252 ctx->abi.vertex_id,
7253 LLVMGetParam(func, user_sgpr_base +
7254 SI_SGPR_BASE_VERTEX), "");
7255 }
7256
7257 index = ac_to_float(&ctx->ac, index);
7258 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7259 fninfo.num_params + i, "");
7260 }
7261
7262 si_llvm_build_ret(ctx, ret);
7263 }
7264
7265 static bool si_get_vs_prolog(struct si_screen *sscreen,
7266 struct ac_llvm_compiler *compiler,
7267 struct si_shader *shader,
7268 struct pipe_debug_callback *debug,
7269 struct si_shader *main_part,
7270 const struct si_vs_prolog_bits *key)
7271 {
7272 struct si_shader_selector *vs = main_part->selector;
7273
7274 if (!si_vs_needs_prolog(vs, key))
7275 return true;
7276
7277 /* Get the prolog. */
7278 union si_shader_part_key prolog_key;
7279 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7280 key, shader, &prolog_key);
7281
7282 shader->prolog =
7283 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7284 PIPE_SHADER_VERTEX, true, &prolog_key, compiler,
7285 debug, si_build_vs_prolog_function,
7286 "Vertex Shader Prolog");
7287 return shader->prolog != NULL;
7288 }
7289
7290 /**
7291 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7292 */
7293 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7294 struct ac_llvm_compiler *compiler,
7295 struct si_shader *shader,
7296 struct pipe_debug_callback *debug)
7297 {
7298 return si_get_vs_prolog(sscreen, compiler, shader, debug, shader,
7299 &shader->key.part.vs.prolog);
7300 }
7301
7302 /**
7303 * Compile the TCS epilog function. This writes tesselation factors to memory
7304 * based on the output primitive type of the tesselator (determined by TES).
7305 */
7306 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7307 union si_shader_part_key *key)
7308 {
7309 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7310 struct si_function_info fninfo;
7311 LLVMValueRef func;
7312
7313 si_init_function_info(&fninfo);
7314
7315 if (ctx->screen->info.chip_class >= GFX9) {
7316 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7317 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7318 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7319 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7320 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7321 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7322 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7323 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7324 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7325 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7326 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7327 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7328 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7329 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7330 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7331 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7332 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7333 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7334 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7335 } else {
7336 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7337 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7338 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7339 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7340 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7341 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7342 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7343 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7344 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7345 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7346 }
7347
7348 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7349 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7350 unsigned tess_factors_idx =
7351 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7352 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7353 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7354
7355 for (unsigned i = 0; i < 6; i++)
7356 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7357
7358 /* Create the function. */
7359 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7360 ctx->screen->info.chip_class >= GFX7 ? 128 : 64);
7361 ac_declare_lds_as_pointer(&ctx->ac);
7362 func = ctx->main_fn;
7363
7364 LLVMValueRef invoc0_tess_factors[6];
7365 for (unsigned i = 0; i < 6; i++)
7366 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7367
7368 si_write_tess_factors(bld_base,
7369 LLVMGetParam(func, tess_factors_idx),
7370 LLVMGetParam(func, tess_factors_idx + 1),
7371 LLVMGetParam(func, tess_factors_idx + 2),
7372 invoc0_tess_factors, invoc0_tess_factors + 4);
7373
7374 LLVMBuildRetVoid(ctx->ac.builder);
7375 }
7376
7377 /**
7378 * Select and compile (or reuse) TCS parts (epilog).
7379 */
7380 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7381 struct ac_llvm_compiler *compiler,
7382 struct si_shader *shader,
7383 struct pipe_debug_callback *debug)
7384 {
7385 if (sscreen->info.chip_class >= GFX9) {
7386 struct si_shader *ls_main_part =
7387 shader->key.part.tcs.ls->main_shader_part_ls;
7388
7389 if (!si_get_vs_prolog(sscreen, compiler, shader, debug, ls_main_part,
7390 &shader->key.part.tcs.ls_prolog))
7391 return false;
7392
7393 shader->previous_stage = ls_main_part;
7394 }
7395
7396 /* Get the epilog. */
7397 union si_shader_part_key epilog_key;
7398 memset(&epilog_key, 0, sizeof(epilog_key));
7399 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7400
7401 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7402 PIPE_SHADER_TESS_CTRL, false,
7403 &epilog_key, compiler, debug,
7404 si_build_tcs_epilog_function,
7405 "Tessellation Control Shader Epilog");
7406 return shader->epilog != NULL;
7407 }
7408
7409 /**
7410 * Select and compile (or reuse) GS parts (prolog).
7411 */
7412 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7413 struct ac_llvm_compiler *compiler,
7414 struct si_shader *shader,
7415 struct pipe_debug_callback *debug)
7416 {
7417 if (sscreen->info.chip_class >= GFX9) {
7418 struct si_shader *es_main_part =
7419 shader->key.part.gs.es->main_shader_part_es;
7420
7421 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7422 !si_get_vs_prolog(sscreen, compiler, shader, debug, es_main_part,
7423 &shader->key.part.gs.vs_prolog))
7424 return false;
7425
7426 shader->previous_stage = es_main_part;
7427 }
7428
7429 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7430 return true;
7431
7432 union si_shader_part_key prolog_key;
7433 memset(&prolog_key, 0, sizeof(prolog_key));
7434 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7435
7436 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7437 PIPE_SHADER_GEOMETRY, true,
7438 &prolog_key, compiler, debug,
7439 si_build_gs_prolog_function,
7440 "Geometry Shader Prolog");
7441 return shader->prolog2 != NULL;
7442 }
7443
7444 /**
7445 * Build the pixel shader prolog function. This handles:
7446 * - two-side color selection and interpolation
7447 * - overriding interpolation parameters for the API PS
7448 * - polygon stippling
7449 *
7450 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7451 * overriden by other states. (e.g. per-sample interpolation)
7452 * Interpolated colors are stored after the preloaded VGPRs.
7453 */
7454 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7455 union si_shader_part_key *key)
7456 {
7457 struct si_function_info fninfo;
7458 LLVMValueRef ret, func;
7459 int num_returns, i, num_color_channels;
7460
7461 assert(si_need_ps_prolog(key));
7462
7463 si_init_function_info(&fninfo);
7464
7465 /* Declare inputs. */
7466 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7467 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7468
7469 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7470 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7471
7472 /* Declare outputs (same as inputs + add colors if needed) */
7473 num_returns = fninfo.num_params;
7474 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7475 for (i = 0; i < num_color_channels; i++)
7476 fninfo.types[num_returns++] = ctx->f32;
7477
7478 /* Create the function. */
7479 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7480 &fninfo, 0);
7481 func = ctx->main_fn;
7482
7483 /* Copy inputs to outputs. This should be no-op, as the registers match,
7484 * but it will prevent the compiler from overwriting them unintentionally.
7485 */
7486 ret = ctx->return_value;
7487 for (i = 0; i < fninfo.num_params; i++) {
7488 LLVMValueRef p = LLVMGetParam(func, i);
7489 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7490 }
7491
7492 /* Polygon stippling. */
7493 if (key->ps_prolog.states.poly_stipple) {
7494 /* POS_FIXED_PT is always last. */
7495 unsigned pos = key->ps_prolog.num_input_sgprs +
7496 key->ps_prolog.num_input_vgprs - 1;
7497 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7498
7499 si_llvm_emit_polygon_stipple(ctx, list, pos);
7500 }
7501
7502 if (key->ps_prolog.states.bc_optimize_for_persp ||
7503 key->ps_prolog.states.bc_optimize_for_linear) {
7504 unsigned i, base = key->ps_prolog.num_input_sgprs;
7505 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7506
7507 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7508 * The hw doesn't compute CENTROID if the whole wave only
7509 * contains fully-covered quads.
7510 *
7511 * PRIM_MASK is after user SGPRs.
7512 */
7513 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7514 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7515 LLVMConstInt(ctx->i32, 31, 0), "");
7516 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7517 ctx->i1, "");
7518
7519 if (key->ps_prolog.states.bc_optimize_for_persp) {
7520 /* Read PERSP_CENTER. */
7521 for (i = 0; i < 2; i++)
7522 center[i] = LLVMGetParam(func, base + 2 + i);
7523 /* Read PERSP_CENTROID. */
7524 for (i = 0; i < 2; i++)
7525 centroid[i] = LLVMGetParam(func, base + 4 + i);
7526 /* Select PERSP_CENTROID. */
7527 for (i = 0; i < 2; i++) {
7528 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7529 center[i], centroid[i], "");
7530 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7531 tmp, base + 4 + i, "");
7532 }
7533 }
7534 if (key->ps_prolog.states.bc_optimize_for_linear) {
7535 /* Read LINEAR_CENTER. */
7536 for (i = 0; i < 2; i++)
7537 center[i] = LLVMGetParam(func, base + 8 + i);
7538 /* Read LINEAR_CENTROID. */
7539 for (i = 0; i < 2; i++)
7540 centroid[i] = LLVMGetParam(func, base + 10 + i);
7541 /* Select LINEAR_CENTROID. */
7542 for (i = 0; i < 2; i++) {
7543 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7544 center[i], centroid[i], "");
7545 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7546 tmp, base + 10 + i, "");
7547 }
7548 }
7549 }
7550
7551 /* Force per-sample interpolation. */
7552 if (key->ps_prolog.states.force_persp_sample_interp) {
7553 unsigned i, base = key->ps_prolog.num_input_sgprs;
7554 LLVMValueRef persp_sample[2];
7555
7556 /* Read PERSP_SAMPLE. */
7557 for (i = 0; i < 2; i++)
7558 persp_sample[i] = LLVMGetParam(func, base + i);
7559 /* Overwrite PERSP_CENTER. */
7560 for (i = 0; i < 2; i++)
7561 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7562 persp_sample[i], base + 2 + i, "");
7563 /* Overwrite PERSP_CENTROID. */
7564 for (i = 0; i < 2; i++)
7565 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7566 persp_sample[i], base + 4 + i, "");
7567 }
7568 if (key->ps_prolog.states.force_linear_sample_interp) {
7569 unsigned i, base = key->ps_prolog.num_input_sgprs;
7570 LLVMValueRef linear_sample[2];
7571
7572 /* Read LINEAR_SAMPLE. */
7573 for (i = 0; i < 2; i++)
7574 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7575 /* Overwrite LINEAR_CENTER. */
7576 for (i = 0; i < 2; i++)
7577 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7578 linear_sample[i], base + 8 + i, "");
7579 /* Overwrite LINEAR_CENTROID. */
7580 for (i = 0; i < 2; i++)
7581 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7582 linear_sample[i], base + 10 + i, "");
7583 }
7584
7585 /* Force center interpolation. */
7586 if (key->ps_prolog.states.force_persp_center_interp) {
7587 unsigned i, base = key->ps_prolog.num_input_sgprs;
7588 LLVMValueRef persp_center[2];
7589
7590 /* Read PERSP_CENTER. */
7591 for (i = 0; i < 2; i++)
7592 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7593 /* Overwrite PERSP_SAMPLE. */
7594 for (i = 0; i < 2; i++)
7595 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7596 persp_center[i], base + i, "");
7597 /* Overwrite PERSP_CENTROID. */
7598 for (i = 0; i < 2; i++)
7599 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7600 persp_center[i], base + 4 + i, "");
7601 }
7602 if (key->ps_prolog.states.force_linear_center_interp) {
7603 unsigned i, base = key->ps_prolog.num_input_sgprs;
7604 LLVMValueRef linear_center[2];
7605
7606 /* Read LINEAR_CENTER. */
7607 for (i = 0; i < 2; i++)
7608 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7609 /* Overwrite LINEAR_SAMPLE. */
7610 for (i = 0; i < 2; i++)
7611 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7612 linear_center[i], base + 6 + i, "");
7613 /* Overwrite LINEAR_CENTROID. */
7614 for (i = 0; i < 2; i++)
7615 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7616 linear_center[i], base + 10 + i, "");
7617 }
7618
7619 /* Interpolate colors. */
7620 unsigned color_out_idx = 0;
7621 for (i = 0; i < 2; i++) {
7622 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7623 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7624 key->ps_prolog.face_vgpr_index;
7625 LLVMValueRef interp[2], color[4];
7626 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7627
7628 if (!writemask)
7629 continue;
7630
7631 /* If the interpolation qualifier is not CONSTANT (-1). */
7632 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7633 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7634 key->ps_prolog.color_interp_vgpr_index[i];
7635
7636 /* Get the (i,j) updated by bc_optimize handling. */
7637 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7638 interp_vgpr, "");
7639 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7640 interp_vgpr + 1, "");
7641 interp_ij = ac_build_gather_values(&ctx->ac, interp, 2);
7642 }
7643
7644 /* Use the absolute location of the input. */
7645 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7646
7647 if (key->ps_prolog.states.color_two_side) {
7648 face = LLVMGetParam(func, face_vgpr);
7649 face = ac_to_integer(&ctx->ac, face);
7650 }
7651
7652 interp_fs_input(ctx,
7653 key->ps_prolog.color_attr_index[i],
7654 TGSI_SEMANTIC_COLOR, i,
7655 key->ps_prolog.num_interp_inputs,
7656 key->ps_prolog.colors_read, interp_ij,
7657 prim_mask, face, color);
7658
7659 while (writemask) {
7660 unsigned chan = u_bit_scan(&writemask);
7661 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7662 fninfo.num_params + color_out_idx++, "");
7663 }
7664 }
7665
7666 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7667 * says:
7668 *
7669 * "When per-sample shading is active due to the use of a fragment
7670 * input qualified by sample or due to the use of the gl_SampleID
7671 * or gl_SamplePosition variables, only the bit for the current
7672 * sample is set in gl_SampleMaskIn. When state specifies multiple
7673 * fragment shader invocations for a given fragment, the sample
7674 * mask for any single fragment shader invocation may specify a
7675 * subset of the covered samples for the fragment. In this case,
7676 * the bit corresponding to each covered sample will be set in
7677 * exactly one fragment shader invocation."
7678 *
7679 * The samplemask loaded by hardware is always the coverage of the
7680 * entire pixel/fragment, so mask bits out based on the sample ID.
7681 */
7682 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7683 /* The bit pattern matches that used by fixed function fragment
7684 * processing. */
7685 static const uint16_t ps_iter_masks[] = {
7686 0xffff, /* not used */
7687 0x5555,
7688 0x1111,
7689 0x0101,
7690 0x0001,
7691 };
7692 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7693
7694 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7695 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7696 key->ps_prolog.ancillary_vgpr_index;
7697 LLVMValueRef sampleid = si_unpack_param(ctx, ancillary_vgpr, 8, 4);
7698 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7699
7700 samplemask = ac_to_integer(&ctx->ac, samplemask);
7701 samplemask = LLVMBuildAnd(
7702 ctx->ac.builder,
7703 samplemask,
7704 LLVMBuildShl(ctx->ac.builder,
7705 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7706 sampleid, ""),
7707 "");
7708 samplemask = ac_to_float(&ctx->ac, samplemask);
7709
7710 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7711 ancillary_vgpr + 1, "");
7712 }
7713
7714 /* Tell LLVM to insert WQM instruction sequence when needed. */
7715 if (key->ps_prolog.wqm) {
7716 LLVMAddTargetDependentFunctionAttr(func,
7717 "amdgpu-ps-wqm-outputs", "");
7718 }
7719
7720 si_llvm_build_ret(ctx, ret);
7721 }
7722
7723 /**
7724 * Build the pixel shader epilog function. This handles everything that must be
7725 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7726 */
7727 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7728 union si_shader_part_key *key)
7729 {
7730 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7731 struct si_function_info fninfo;
7732 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7733 int i;
7734 struct si_ps_exports exp = {};
7735
7736 si_init_function_info(&fninfo);
7737
7738 /* Declare input SGPRs. */
7739 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7740 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7741 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7742 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7743 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7744
7745 /* Declare input VGPRs. */
7746 unsigned required_num_params =
7747 fninfo.num_sgpr_params +
7748 util_bitcount(key->ps_epilog.colors_written) * 4 +
7749 key->ps_epilog.writes_z +
7750 key->ps_epilog.writes_stencil +
7751 key->ps_epilog.writes_samplemask;
7752
7753 required_num_params = MAX2(required_num_params,
7754 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7755
7756 while (fninfo.num_params < required_num_params)
7757 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7758
7759 /* Create the function. */
7760 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7761 /* Disable elimination of unused inputs. */
7762 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
7763 "InitialPSInputAddr", 0xffffff);
7764
7765 /* Process colors. */
7766 unsigned vgpr = fninfo.num_sgpr_params;
7767 unsigned colors_written = key->ps_epilog.colors_written;
7768 int last_color_export = -1;
7769
7770 /* Find the last color export. */
7771 if (!key->ps_epilog.writes_z &&
7772 !key->ps_epilog.writes_stencil &&
7773 !key->ps_epilog.writes_samplemask) {
7774 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7775
7776 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7777 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7778 /* Just set this if any of the colorbuffers are enabled. */
7779 if (spi_format &
7780 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7781 last_color_export = 0;
7782 } else {
7783 for (i = 0; i < 8; i++)
7784 if (colors_written & (1 << i) &&
7785 (spi_format >> (i * 4)) & 0xf)
7786 last_color_export = i;
7787 }
7788 }
7789
7790 while (colors_written) {
7791 LLVMValueRef color[4];
7792 int mrt = u_bit_scan(&colors_written);
7793
7794 for (i = 0; i < 4; i++)
7795 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7796
7797 si_export_mrt_color(bld_base, color, mrt,
7798 fninfo.num_params - 1,
7799 mrt == last_color_export, &exp);
7800 }
7801
7802 /* Process depth, stencil, samplemask. */
7803 if (key->ps_epilog.writes_z)
7804 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7805 if (key->ps_epilog.writes_stencil)
7806 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7807 if (key->ps_epilog.writes_samplemask)
7808 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7809
7810 if (depth || stencil || samplemask)
7811 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7812 else if (last_color_export == -1)
7813 ac_build_export_null(&ctx->ac);
7814
7815 if (exp.num)
7816 si_emit_ps_exports(ctx, &exp);
7817
7818 /* Compile. */
7819 LLVMBuildRetVoid(ctx->ac.builder);
7820 }
7821
7822 /**
7823 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7824 */
7825 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7826 struct ac_llvm_compiler *compiler,
7827 struct si_shader *shader,
7828 struct pipe_debug_callback *debug)
7829 {
7830 union si_shader_part_key prolog_key;
7831 union si_shader_part_key epilog_key;
7832
7833 /* Get the prolog. */
7834 si_get_ps_prolog_key(shader, &prolog_key, true);
7835
7836 /* The prolog is a no-op if these aren't set. */
7837 if (si_need_ps_prolog(&prolog_key)) {
7838 shader->prolog =
7839 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7840 PIPE_SHADER_FRAGMENT, true,
7841 &prolog_key, compiler, debug,
7842 si_build_ps_prolog_function,
7843 "Fragment Shader Prolog");
7844 if (!shader->prolog)
7845 return false;
7846 }
7847
7848 /* Get the epilog. */
7849 si_get_ps_epilog_key(shader, &epilog_key);
7850
7851 shader->epilog =
7852 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7853 PIPE_SHADER_FRAGMENT, false,
7854 &epilog_key, compiler, debug,
7855 si_build_ps_epilog_function,
7856 "Fragment Shader Epilog");
7857 if (!shader->epilog)
7858 return false;
7859
7860 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7861 if (shader->key.part.ps.prolog.poly_stipple) {
7862 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7863 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7864 }
7865
7866 /* Set up the enable bits for per-sample shading if needed. */
7867 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7868 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7869 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7870 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7871 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7872 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7873 }
7874 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7875 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7876 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7877 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7878 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7879 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7880 }
7881 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7882 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7883 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7884 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7885 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7886 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7887 }
7888 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7889 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7890 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7891 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7892 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7893 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7894 }
7895
7896 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7897 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7898 !(shader->config.spi_ps_input_ena & 0xf)) {
7899 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7900 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7901 }
7902
7903 /* At least one pair of interpolation weights must be enabled. */
7904 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7905 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7906 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7907 }
7908
7909 /* Samplemask fixup requires the sample ID. */
7910 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7911 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7912 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7913 }
7914
7915 /* The sample mask input is always enabled, because the API shader always
7916 * passes it through to the epilog. Disable it here if it's unused.
7917 */
7918 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7919 !shader->selector->info.reads_samplemask)
7920 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7921
7922 return true;
7923 }
7924
7925 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7926 unsigned *lds_size)
7927 {
7928 /* If tessellation is all offchip and on-chip GS isn't used, this
7929 * workaround is not needed.
7930 */
7931 return;
7932
7933 /* SPI barrier management bug:
7934 * Make sure we have at least 4k of LDS in use to avoid the bug.
7935 * It applies to workgroup sizes of more than one wavefront.
7936 */
7937 if (sscreen->info.family == CHIP_BONAIRE ||
7938 sscreen->info.family == CHIP_KABINI)
7939 *lds_size = MAX2(*lds_size, 8);
7940 }
7941
7942 static void si_fix_resource_usage(struct si_screen *sscreen,
7943 struct si_shader *shader)
7944 {
7945 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7946
7947 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7948
7949 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7950 si_get_max_workgroup_size(shader) > 64) {
7951 si_multiwave_lds_size_workaround(sscreen,
7952 &shader->config.lds_size);
7953 }
7954 }
7955
7956 bool si_shader_create(struct si_screen *sscreen, struct ac_llvm_compiler *compiler,
7957 struct si_shader *shader,
7958 struct pipe_debug_callback *debug)
7959 {
7960 struct si_shader_selector *sel = shader->selector;
7961 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7962 int r;
7963
7964 /* LS, ES, VS are compiled on demand if the main part hasn't been
7965 * compiled for that stage.
7966 *
7967 * Vertex shaders are compiled on demand when a vertex fetch
7968 * workaround must be applied.
7969 */
7970 if (shader->is_monolithic) {
7971 /* Monolithic shader (compiled as a whole, has many variants,
7972 * may take a long time to compile).
7973 */
7974 r = si_compile_tgsi_shader(sscreen, compiler, shader, debug);
7975 if (r)
7976 return false;
7977 } else {
7978 /* The shader consists of several parts:
7979 *
7980 * - the middle part is the user shader, it has 1 variant only
7981 * and it was compiled during the creation of the shader
7982 * selector
7983 * - the prolog part is inserted at the beginning
7984 * - the epilog part is inserted at the end
7985 *
7986 * The prolog and epilog have many (but simple) variants.
7987 *
7988 * Starting with gfx9, geometry and tessellation control
7989 * shaders also contain the prolog and user shader parts of
7990 * the previous shader stage.
7991 */
7992
7993 if (!mainp)
7994 return false;
7995
7996 /* Copy the compiled TGSI shader data over. */
7997 shader->is_binary_shared = true;
7998 shader->binary = mainp->binary;
7999 shader->config = mainp->config;
8000 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8001 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8002 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8003 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
8004 memcpy(shader->info.vs_output_param_offset,
8005 mainp->info.vs_output_param_offset,
8006 sizeof(mainp->info.vs_output_param_offset));
8007 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8008 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8009 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8010
8011 /* Select prologs and/or epilogs. */
8012 switch (sel->type) {
8013 case PIPE_SHADER_VERTEX:
8014 if (!si_shader_select_vs_parts(sscreen, compiler, shader, debug))
8015 return false;
8016 break;
8017 case PIPE_SHADER_TESS_CTRL:
8018 if (!si_shader_select_tcs_parts(sscreen, compiler, shader, debug))
8019 return false;
8020 break;
8021 case PIPE_SHADER_TESS_EVAL:
8022 break;
8023 case PIPE_SHADER_GEOMETRY:
8024 if (!si_shader_select_gs_parts(sscreen, compiler, shader, debug))
8025 return false;
8026 break;
8027 case PIPE_SHADER_FRAGMENT:
8028 if (!si_shader_select_ps_parts(sscreen, compiler, shader, debug))
8029 return false;
8030
8031 /* Make sure we have at least as many VGPRs as there
8032 * are allocated inputs.
8033 */
8034 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8035 shader->info.num_input_vgprs);
8036 break;
8037 }
8038
8039 /* Update SGPR and VGPR counts. */
8040 if (shader->prolog) {
8041 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8042 shader->prolog->config.num_sgprs);
8043 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8044 shader->prolog->config.num_vgprs);
8045 }
8046 if (shader->previous_stage) {
8047 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8048 shader->previous_stage->config.num_sgprs);
8049 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8050 shader->previous_stage->config.num_vgprs);
8051 shader->config.spilled_sgprs =
8052 MAX2(shader->config.spilled_sgprs,
8053 shader->previous_stage->config.spilled_sgprs);
8054 shader->config.spilled_vgprs =
8055 MAX2(shader->config.spilled_vgprs,
8056 shader->previous_stage->config.spilled_vgprs);
8057 shader->info.private_mem_vgprs =
8058 MAX2(shader->info.private_mem_vgprs,
8059 shader->previous_stage->info.private_mem_vgprs);
8060 shader->config.scratch_bytes_per_wave =
8061 MAX2(shader->config.scratch_bytes_per_wave,
8062 shader->previous_stage->config.scratch_bytes_per_wave);
8063 shader->info.uses_instanceid |=
8064 shader->previous_stage->info.uses_instanceid;
8065 }
8066 if (shader->prolog2) {
8067 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8068 shader->prolog2->config.num_sgprs);
8069 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8070 shader->prolog2->config.num_vgprs);
8071 }
8072 if (shader->epilog) {
8073 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8074 shader->epilog->config.num_sgprs);
8075 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8076 shader->epilog->config.num_vgprs);
8077 }
8078 si_calculate_max_simd_waves(shader);
8079 }
8080
8081 if (sscreen->info.chip_class >= GFX9 && sel->type == PIPE_SHADER_GEOMETRY)
8082 gfx9_get_gs_info(shader->previous_stage_sel, sel, &shader->gs_info);
8083
8084 si_fix_resource_usage(sscreen, shader);
8085 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8086 stderr, true);
8087
8088 /* Upload. */
8089 if (!si_shader_binary_upload(sscreen, shader, 0)) {
8090 fprintf(stderr, "LLVM failed to upload shader\n");
8091 return false;
8092 }
8093
8094 return true;
8095 }
8096
8097 void si_shader_destroy(struct si_shader *shader)
8098 {
8099 if (shader->scratch_bo)
8100 si_resource_reference(&shader->scratch_bo, NULL);
8101
8102 si_resource_reference(&shader->bo, NULL);
8103
8104 if (!shader->is_binary_shared)
8105 si_shader_binary_clean(&shader->binary);
8106
8107 free(shader->shader_log);
8108 }