2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "util/u_string.h"
43 #include "tgsi/tgsi_parse.h"
44 #include "tgsi/tgsi_build.h"
45 #include "tgsi/tgsi_util.h"
46 #include "tgsi/tgsi_dump.h"
49 #include "si_shader.h"
54 static const char *scratch_rsrc_dword0_symbol
=
55 "SCRATCH_RSRC_DWORD0";
57 static const char *scratch_rsrc_dword1_symbol
=
58 "SCRATCH_RSRC_DWORD1";
60 struct si_shader_output_values
62 LLVMValueRef values
[4];
67 struct si_shader_context
69 struct radeon_llvm_context radeon_bld
;
70 struct si_shader
*shader
;
71 struct si_screen
*screen
;
73 unsigned type
; /* PIPE_SHADER_* specifies the type of shader. */
74 bool is_gs_copy_shader
;
76 /* Whether to generate the optimized shader variant compiled as a whole
77 * (without a prolog and epilog)
81 int param_streamout_config
;
82 int param_streamout_write_index
;
83 int param_streamout_offset
[4];
85 int param_rel_auto_id
;
87 int param_instance_id
;
88 int param_vertex_index0
;
91 int param_tes_rel_patch_id
;
92 int param_tes_patch_id
;
93 int param_es2gs_offset
;
96 /* Sets a bit if the dynamic HS control word was 0x80000000. The bit is
97 * 0x800000 for VS, 0x1 for ES.
99 int param_tess_offchip
;
101 LLVMTargetMachineRef tm
;
103 unsigned uniform_md_kind
;
104 LLVMValueRef const_md
;
105 LLVMValueRef empty_md
;
106 LLVMValueRef const_buffers
[SI_NUM_CONST_BUFFERS
];
108 LLVMValueRef
*constants
[SI_NUM_CONST_BUFFERS
];
109 LLVMValueRef shader_buffers
[SI_NUM_SHADER_BUFFERS
];
110 LLVMValueRef sampler_views
[SI_NUM_SAMPLERS
];
111 LLVMValueRef sampler_states
[SI_NUM_SAMPLERS
];
112 LLVMValueRef fmasks
[SI_NUM_SAMPLERS
];
113 LLVMValueRef images
[SI_NUM_IMAGES
];
114 LLVMValueRef so_buffers
[4];
115 LLVMValueRef esgs_ring
;
116 LLVMValueRef gsvs_ring
[4];
117 LLVMValueRef gs_next_vertex
[4];
118 LLVMValueRef return_value
;
133 LLVMValueRef shared_memory
;
136 static struct si_shader_context
*si_shader_context(
137 struct lp_build_tgsi_context
*bld_base
)
139 return (struct si_shader_context
*)bld_base
;
142 static void si_init_shader_ctx(struct si_shader_context
*ctx
,
143 struct si_screen
*sscreen
,
144 struct si_shader
*shader
,
145 LLVMTargetMachineRef tm
);
147 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action
*action
,
148 struct lp_build_tgsi_context
*bld_base
,
149 struct lp_build_emit_data
*emit_data
);
151 /* Ideally pass the sample mask input to the PS epilog as v13, which
152 * is its usual location, so that the shader doesn't have to add v_mov.
154 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
156 /* The VS location of the PrimitiveID input is the same in the epilog,
157 * so that the main shader part doesn't have to move it.
159 #define VS_EPILOG_PRIMID_LOC 2
161 #define PERSPECTIVE_BASE 0
162 #define LINEAR_BASE 9
164 #define SAMPLE_OFFSET 0
165 #define CENTER_OFFSET 2
166 #define CENTROID_OFSET 4
168 #define USE_SGPR_MAX_SUFFIX_LEN 5
169 #define CONST_ADDR_SPACE 2
170 #define LOCAL_ADDR_SPACE 3
171 #define USER_SGPR_ADDR_SPACE 8
175 #define SENDMSG_GS_DONE 3
177 #define SENDMSG_GS_OP_NOP (0 << 4)
178 #define SENDMSG_GS_OP_CUT (1 << 4)
179 #define SENDMSG_GS_OP_EMIT (2 << 4)
180 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
183 * Returns a unique index for a semantic name and index. The index must be
184 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
187 unsigned si_shader_io_get_unique_index(unsigned semantic_name
, unsigned index
)
189 switch (semantic_name
) {
190 case TGSI_SEMANTIC_POSITION
:
192 case TGSI_SEMANTIC_PSIZE
:
194 case TGSI_SEMANTIC_CLIPDIST
:
197 case TGSI_SEMANTIC_GENERIC
:
201 /* same explanation as in the default statement,
202 * the only user hitting this is st/nine.
206 /* patch indices are completely separate and thus start from 0 */
207 case TGSI_SEMANTIC_TESSOUTER
:
209 case TGSI_SEMANTIC_TESSINNER
:
211 case TGSI_SEMANTIC_PATCH
:
215 /* Don't fail here. The result of this function is only used
216 * for LS, TCS, TES, and GS, where legacy GL semantics can't
217 * occur, but this function is called for all vertex shaders
218 * before it's known whether LS will be compiled or not.
225 * Get the value of a shader input parameter and extract a bitfield.
227 static LLVMValueRef
unpack_param(struct si_shader_context
*ctx
,
228 unsigned param
, unsigned rshift
,
231 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
232 LLVMValueRef value
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
235 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMFloatTypeKind
)
236 value
= bitcast(&ctx
->radeon_bld
.soa
.bld_base
,
237 TGSI_TYPE_UNSIGNED
, value
);
240 value
= LLVMBuildLShr(gallivm
->builder
, value
,
241 lp_build_const_int32(gallivm
, rshift
), "");
243 if (rshift
+ bitwidth
< 32) {
244 unsigned mask
= (1 << bitwidth
) - 1;
245 value
= LLVMBuildAnd(gallivm
->builder
, value
,
246 lp_build_const_int32(gallivm
, mask
), "");
252 static LLVMValueRef
get_rel_patch_id(struct si_shader_context
*ctx
)
255 case PIPE_SHADER_TESS_CTRL
:
256 return unpack_param(ctx
, SI_PARAM_REL_IDS
, 0, 8);
258 case PIPE_SHADER_TESS_EVAL
:
259 return LLVMGetParam(ctx
->radeon_bld
.main_fn
,
260 ctx
->param_tes_rel_patch_id
);
268 /* Tessellation shaders pass outputs to the next shader using LDS.
270 * LS outputs = TCS inputs
271 * TCS outputs = TES inputs
274 * - TCS inputs for patch 0
275 * - TCS inputs for patch 1
276 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
278 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
279 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
280 * - TCS outputs for patch 1
281 * - Per-patch TCS outputs for patch 1
282 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
283 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
286 * All three shaders VS(LS), TCS, TES share the same LDS space.
290 get_tcs_in_patch_stride(struct si_shader_context
*ctx
)
292 if (ctx
->type
== PIPE_SHADER_VERTEX
)
293 return unpack_param(ctx
, SI_PARAM_LS_OUT_LAYOUT
, 0, 13);
294 else if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
295 return unpack_param(ctx
, SI_PARAM_TCS_IN_LAYOUT
, 0, 13);
303 get_tcs_out_patch_stride(struct si_shader_context
*ctx
)
305 return unpack_param(ctx
, SI_PARAM_TCS_OUT_LAYOUT
, 0, 13);
309 get_tcs_out_patch0_offset(struct si_shader_context
*ctx
)
311 return lp_build_mul_imm(&ctx
->radeon_bld
.soa
.bld_base
.uint_bld
,
313 SI_PARAM_TCS_OUT_OFFSETS
,
319 get_tcs_out_patch0_patch_data_offset(struct si_shader_context
*ctx
)
321 return lp_build_mul_imm(&ctx
->radeon_bld
.soa
.bld_base
.uint_bld
,
323 SI_PARAM_TCS_OUT_OFFSETS
,
329 get_tcs_in_current_patch_offset(struct si_shader_context
*ctx
)
331 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
332 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
333 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
335 return LLVMBuildMul(gallivm
->builder
, patch_stride
, rel_patch_id
, "");
339 get_tcs_out_current_patch_offset(struct si_shader_context
*ctx
)
341 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
342 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
343 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
344 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
346 return LLVMBuildAdd(gallivm
->builder
, patch0_offset
,
347 LLVMBuildMul(gallivm
->builder
, patch_stride
,
353 get_tcs_out_current_patch_data_offset(struct si_shader_context
*ctx
)
355 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
356 LLVMValueRef patch0_patch_data_offset
=
357 get_tcs_out_patch0_patch_data_offset(ctx
);
358 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
359 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
361 return LLVMBuildAdd(gallivm
->builder
, patch0_patch_data_offset
,
362 LLVMBuildMul(gallivm
->builder
, patch_stride
,
367 static void build_indexed_store(struct si_shader_context
*ctx
,
368 LLVMValueRef base_ptr
, LLVMValueRef index
,
371 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
372 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
373 LLVMValueRef indices
[2], pointer
;
375 indices
[0] = bld_base
->uint_bld
.zero
;
378 pointer
= LLVMBuildGEP(gallivm
->builder
, base_ptr
, indices
, 2, "");
379 LLVMBuildStore(gallivm
->builder
, value
, pointer
);
383 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
384 * It's equivalent to doing a load from &base_ptr[index].
386 * \param base_ptr Where the array starts.
387 * \param index The element index into the array.
388 * \param uniform Whether the base_ptr and index can be assumed to be
389 * dynamically uniform
391 static LLVMValueRef
build_indexed_load(struct si_shader_context
*ctx
,
392 LLVMValueRef base_ptr
, LLVMValueRef index
,
395 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
396 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
397 LLVMValueRef indices
[2], pointer
;
399 indices
[0] = bld_base
->uint_bld
.zero
;
402 pointer
= LLVMBuildGEP(gallivm
->builder
, base_ptr
, indices
, 2, "");
404 LLVMSetMetadata(pointer
, ctx
->uniform_md_kind
, ctx
->empty_md
);
405 return LLVMBuildLoad(gallivm
->builder
, pointer
, "");
409 * Do a load from &base_ptr[index], but also add a flag that it's loading
410 * a constant from a dynamically uniform index.
412 static LLVMValueRef
build_indexed_load_const(
413 struct si_shader_context
*ctx
,
414 LLVMValueRef base_ptr
, LLVMValueRef index
)
416 LLVMValueRef result
= build_indexed_load(ctx
, base_ptr
, index
, true);
417 LLVMSetMetadata(result
, 1, ctx
->const_md
);
421 static LLVMValueRef
get_instance_index_for_fetch(
422 struct radeon_llvm_context
*radeon_bld
,
423 unsigned param_start_instance
, unsigned divisor
)
425 struct si_shader_context
*ctx
=
426 si_shader_context(&radeon_bld
->soa
.bld_base
);
427 struct gallivm_state
*gallivm
= radeon_bld
->soa
.bld_base
.base
.gallivm
;
429 LLVMValueRef result
= LLVMGetParam(radeon_bld
->main_fn
,
430 ctx
->param_instance_id
);
432 /* The division must be done before START_INSTANCE is added. */
434 result
= LLVMBuildUDiv(gallivm
->builder
, result
,
435 lp_build_const_int32(gallivm
, divisor
), "");
437 return LLVMBuildAdd(gallivm
->builder
, result
,
438 LLVMGetParam(radeon_bld
->main_fn
, param_start_instance
), "");
441 static void declare_input_vs(
442 struct radeon_llvm_context
*radeon_bld
,
443 unsigned input_index
,
444 const struct tgsi_full_declaration
*decl
)
446 struct lp_build_context
*base
= &radeon_bld
->soa
.bld_base
.base
;
447 struct gallivm_state
*gallivm
= base
->gallivm
;
448 struct si_shader_context
*ctx
=
449 si_shader_context(&radeon_bld
->soa
.bld_base
);
451 ctx
->shader
->key
.vs
.prolog
.instance_divisors
[input_index
];
455 LLVMValueRef t_list_ptr
;
456 LLVMValueRef t_offset
;
458 LLVMValueRef attribute_offset
;
459 LLVMValueRef buffer_index
;
460 LLVMValueRef args
[3];
463 /* Load the T list */
464 t_list_ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_VERTEX_BUFFERS
);
466 t_offset
= lp_build_const_int32(gallivm
, input_index
);
468 t_list
= build_indexed_load_const(ctx
, t_list_ptr
, t_offset
);
470 /* Build the attribute offset */
471 attribute_offset
= lp_build_const_int32(gallivm
, 0);
473 if (!ctx
->is_monolithic
) {
474 buffer_index
= LLVMGetParam(radeon_bld
->main_fn
,
475 ctx
->param_vertex_index0
+
477 } else if (divisor
) {
478 /* Build index from instance ID, start instance and divisor */
479 ctx
->shader
->info
.uses_instanceid
= true;
480 buffer_index
= get_instance_index_for_fetch(&ctx
->radeon_bld
,
481 SI_PARAM_START_INSTANCE
,
484 /* Load the buffer index for vertices. */
485 LLVMValueRef vertex_id
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
486 ctx
->param_vertex_id
);
487 LLVMValueRef base_vertex
= LLVMGetParam(radeon_bld
->main_fn
,
488 SI_PARAM_BASE_VERTEX
);
489 buffer_index
= LLVMBuildAdd(gallivm
->builder
, base_vertex
, vertex_id
, "");
493 args
[1] = attribute_offset
;
494 args
[2] = buffer_index
;
495 input
= lp_build_intrinsic(gallivm
->builder
,
496 "llvm.SI.vs.load.input", ctx
->v4f32
, args
, 3,
497 LLVMReadNoneAttribute
);
499 /* Break up the vec4 into individual components */
500 for (chan
= 0; chan
< 4; chan
++) {
501 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
502 /* XXX: Use a helper function for this. There is one in
504 ctx
->radeon_bld
.inputs
[radeon_llvm_reg_index_soa(input_index
, chan
)] =
505 LLVMBuildExtractElement(gallivm
->builder
,
506 input
, llvm_chan
, "");
510 static LLVMValueRef
get_primitive_id(struct lp_build_tgsi_context
*bld_base
,
513 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
516 return bld_base
->uint_bld
.zero
;
519 case PIPE_SHADER_VERTEX
:
520 return LLVMGetParam(ctx
->radeon_bld
.main_fn
,
521 ctx
->param_vs_prim_id
);
522 case PIPE_SHADER_TESS_CTRL
:
523 return LLVMGetParam(ctx
->radeon_bld
.main_fn
,
525 case PIPE_SHADER_TESS_EVAL
:
526 return LLVMGetParam(ctx
->radeon_bld
.main_fn
,
527 ctx
->param_tes_patch_id
);
528 case PIPE_SHADER_GEOMETRY
:
529 return LLVMGetParam(ctx
->radeon_bld
.main_fn
,
530 SI_PARAM_PRIMITIVE_ID
);
533 return bld_base
->uint_bld
.zero
;
538 * Return the value of tgsi_ind_register for indexing.
539 * This is the indirect index with the constant offset added to it.
541 static LLVMValueRef
get_indirect_index(struct si_shader_context
*ctx
,
542 const struct tgsi_ind_register
*ind
,
545 struct gallivm_state
*gallivm
= ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
548 result
= ctx
->radeon_bld
.soa
.addr
[ind
->Index
][ind
->Swizzle
];
549 result
= LLVMBuildLoad(gallivm
->builder
, result
, "");
550 result
= LLVMBuildAdd(gallivm
->builder
, result
,
551 lp_build_const_int32(gallivm
, rel_index
), "");
556 * Like get_indirect_index, but restricts the return value to a (possibly
557 * undefined) value inside [0..num).
559 static LLVMValueRef
get_bounded_indirect_index(struct si_shader_context
*ctx
,
560 const struct tgsi_ind_register
*ind
,
561 int rel_index
, unsigned num
)
563 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
564 LLVMBuilderRef builder
= gallivm
->builder
;
565 LLVMValueRef result
= get_indirect_index(ctx
, ind
, rel_index
);
566 LLVMValueRef c_max
= LLVMConstInt(ctx
->i32
, num
- 1, 0);
569 /* LLVM 3.8: If indirect resource indexing is used:
573 if (HAVE_LLVM
<= 0x0308)
574 return LLVMGetUndef(ctx
->i32
);
576 if (util_is_power_of_two(num
)) {
577 result
= LLVMBuildAnd(builder
, result
, c_max
, "");
579 /* In theory, this MAX pattern should result in code that is
580 * as good as the bit-wise AND above.
582 * In practice, LLVM generates worse code (at the time of
583 * writing), because its value tracking is not strong enough.
585 cc
= LLVMBuildICmp(builder
, LLVMIntULE
, result
, c_max
, "");
586 result
= LLVMBuildSelect(builder
, cc
, result
, c_max
, "");
594 * Calculate a dword address given an input or output register and a stride.
596 static LLVMValueRef
get_dw_address(struct si_shader_context
*ctx
,
597 const struct tgsi_full_dst_register
*dst
,
598 const struct tgsi_full_src_register
*src
,
599 LLVMValueRef vertex_dw_stride
,
600 LLVMValueRef base_addr
)
602 struct gallivm_state
*gallivm
= ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
603 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
604 ubyte
*name
, *index
, *array_first
;
606 struct tgsi_full_dst_register reg
;
608 /* Set the register description. The address computation is the same
609 * for sources and destinations. */
611 reg
.Register
.File
= src
->Register
.File
;
612 reg
.Register
.Index
= src
->Register
.Index
;
613 reg
.Register
.Indirect
= src
->Register
.Indirect
;
614 reg
.Register
.Dimension
= src
->Register
.Dimension
;
615 reg
.Indirect
= src
->Indirect
;
616 reg
.Dimension
= src
->Dimension
;
617 reg
.DimIndirect
= src
->DimIndirect
;
621 /* If the register is 2-dimensional (e.g. an array of vertices
622 * in a primitive), calculate the base address of the vertex. */
623 if (reg
.Register
.Dimension
) {
626 if (reg
.Dimension
.Indirect
)
627 index
= get_indirect_index(ctx
, ®
.DimIndirect
,
628 reg
.Dimension
.Index
);
630 index
= lp_build_const_int32(gallivm
, reg
.Dimension
.Index
);
632 base_addr
= LLVMBuildAdd(gallivm
->builder
, base_addr
,
633 LLVMBuildMul(gallivm
->builder
, index
,
634 vertex_dw_stride
, ""), "");
637 /* Get information about the register. */
638 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
639 name
= info
->input_semantic_name
;
640 index
= info
->input_semantic_index
;
641 array_first
= info
->input_array_first
;
642 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
643 name
= info
->output_semantic_name
;
644 index
= info
->output_semantic_index
;
645 array_first
= info
->output_array_first
;
651 if (reg
.Register
.Indirect
) {
652 /* Add the relative address of the element. */
653 LLVMValueRef ind_index
;
655 if (reg
.Indirect
.ArrayID
)
656 first
= array_first
[reg
.Indirect
.ArrayID
];
658 first
= reg
.Register
.Index
;
660 ind_index
= get_indirect_index(ctx
, ®
.Indirect
,
661 reg
.Register
.Index
- first
);
663 base_addr
= LLVMBuildAdd(gallivm
->builder
, base_addr
,
664 LLVMBuildMul(gallivm
->builder
, ind_index
,
665 lp_build_const_int32(gallivm
, 4), ""), "");
667 param
= si_shader_io_get_unique_index(name
[first
], index
[first
]);
669 param
= si_shader_io_get_unique_index(name
[reg
.Register
.Index
],
670 index
[reg
.Register
.Index
]);
673 /* Add the base address of the element. */
674 return LLVMBuildAdd(gallivm
->builder
, base_addr
,
675 lp_build_const_int32(gallivm
, param
* 4), "");
678 /* The offchip buffer layout for TCS->TES is
680 * - attribute 0 of patch 0 vertex 0
681 * - attribute 0 of patch 0 vertex 1
682 * - attribute 0 of patch 0 vertex 2
684 * - attribute 0 of patch 1 vertex 0
685 * - attribute 0 of patch 1 vertex 1
687 * - attribute 1 of patch 0 vertex 0
688 * - attribute 1 of patch 0 vertex 1
690 * - per patch attribute 0 of patch 0
691 * - per patch attribute 0 of patch 1
694 * Note that every attribute has 4 components.
696 static LLVMValueRef
get_tcs_tes_buffer_address(struct si_shader_context
*ctx
,
697 LLVMValueRef vertex_index
,
698 LLVMValueRef param_index
)
700 struct gallivm_state
*gallivm
= ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
701 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
, total_vertices
;
702 LLVMValueRef param_stride
, constant16
;
704 vertices_per_patch
= unpack_param(ctx
, SI_PARAM_TCS_OFFCHIP_LAYOUT
, 9, 6);
705 num_patches
= unpack_param(ctx
, SI_PARAM_TCS_OFFCHIP_LAYOUT
, 0, 9);
706 total_vertices
= LLVMBuildMul(gallivm
->builder
, vertices_per_patch
,
709 constant16
= lp_build_const_int32(gallivm
, 16);
711 base_addr
= LLVMBuildMul(gallivm
->builder
, get_rel_patch_id(ctx
),
712 vertices_per_patch
, "");
714 base_addr
= LLVMBuildAdd(gallivm
->builder
, base_addr
,
717 param_stride
= total_vertices
;
719 base_addr
= get_rel_patch_id(ctx
);
720 param_stride
= num_patches
;
723 base_addr
= LLVMBuildAdd(gallivm
->builder
, base_addr
,
724 LLVMBuildMul(gallivm
->builder
, param_index
,
725 param_stride
, ""), "");
727 base_addr
= LLVMBuildMul(gallivm
->builder
, base_addr
, constant16
, "");
730 LLVMValueRef patch_data_offset
=
731 unpack_param(ctx
, SI_PARAM_TCS_OFFCHIP_LAYOUT
, 16, 16);
733 base_addr
= LLVMBuildAdd(gallivm
->builder
, base_addr
,
734 patch_data_offset
, "");
739 static LLVMValueRef
get_tcs_tes_buffer_address_from_reg(
740 struct si_shader_context
*ctx
,
741 const struct tgsi_full_dst_register
*dst
,
742 const struct tgsi_full_src_register
*src
)
744 struct gallivm_state
*gallivm
= ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
745 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
746 ubyte
*name
, *index
, *array_first
;
747 struct tgsi_full_src_register reg
;
748 LLVMValueRef vertex_index
= NULL
;
749 LLVMValueRef param_index
= NULL
;
750 unsigned param_index_base
, param_base
;
752 reg
= src
? *src
: tgsi_full_src_register_from_dst(dst
);
754 if (reg
.Register
.Dimension
) {
756 if (reg
.Dimension
.Indirect
)
757 vertex_index
= get_indirect_index(ctx
, ®
.DimIndirect
,
758 reg
.Dimension
.Index
);
760 vertex_index
= lp_build_const_int32(gallivm
,
761 reg
.Dimension
.Index
);
764 /* Get information about the register. */
765 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
766 name
= info
->input_semantic_name
;
767 index
= info
->input_semantic_index
;
768 array_first
= info
->input_array_first
;
769 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
770 name
= info
->output_semantic_name
;
771 index
= info
->output_semantic_index
;
772 array_first
= info
->output_array_first
;
778 if (reg
.Register
.Indirect
) {
779 if (reg
.Indirect
.ArrayID
)
780 param_base
= array_first
[reg
.Indirect
.ArrayID
];
782 param_base
= reg
.Register
.Index
;
784 param_index
= get_indirect_index(ctx
, ®
.Indirect
,
785 reg
.Register
.Index
- param_base
);
788 param_base
= reg
.Register
.Index
;
789 param_index
= lp_build_const_int32(gallivm
, 0);
792 param_index_base
= si_shader_io_get_unique_index(name
[param_base
],
795 param_index
= LLVMBuildAdd(gallivm
->builder
, param_index
,
796 lp_build_const_int32(gallivm
, param_index_base
),
799 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
802 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
803 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
804 * or v4i32 (num_channels=3,4). */
805 static void build_tbuffer_store(struct si_shader_context
*ctx
,
808 unsigned num_channels
,
810 LLVMValueRef soffset
,
811 unsigned inst_offset
,
820 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
821 LLVMValueRef args
[] = {
824 LLVMConstInt(ctx
->i32
, num_channels
, 0),
827 LLVMConstInt(ctx
->i32
, inst_offset
, 0),
828 LLVMConstInt(ctx
->i32
, dfmt
, 0),
829 LLVMConstInt(ctx
->i32
, nfmt
, 0),
830 LLVMConstInt(ctx
->i32
, offen
, 0),
831 LLVMConstInt(ctx
->i32
, idxen
, 0),
832 LLVMConstInt(ctx
->i32
, glc
, 0),
833 LLVMConstInt(ctx
->i32
, slc
, 0),
834 LLVMConstInt(ctx
->i32
, tfe
, 0)
837 /* The instruction offset field has 12 bits */
838 assert(offen
|| inst_offset
< (1 << 12));
840 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
841 unsigned func
= CLAMP(num_channels
, 1, 3) - 1;
842 const char *types
[] = {"i32", "v2i32", "v4i32"};
844 snprintf(name
, sizeof(name
), "llvm.SI.tbuffer.store.%s", types
[func
]);
846 lp_build_intrinsic(gallivm
->builder
, name
, ctx
->voidt
,
847 args
, ARRAY_SIZE(args
), 0);
850 static void build_tbuffer_store_dwords(struct si_shader_context
*ctx
,
853 unsigned num_channels
,
855 LLVMValueRef soffset
,
856 unsigned inst_offset
)
858 static unsigned dfmt
[] = {
859 V_008F0C_BUF_DATA_FORMAT_32
,
860 V_008F0C_BUF_DATA_FORMAT_32_32
,
861 V_008F0C_BUF_DATA_FORMAT_32_32_32
,
862 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
864 assert(num_channels
>= 1 && num_channels
<= 4);
866 build_tbuffer_store(ctx
, rsrc
, vdata
, num_channels
, vaddr
, soffset
,
867 inst_offset
, dfmt
[num_channels
-1],
868 V_008F0C_BUF_NUM_FORMAT_UINT
, 1, 0, 1, 1, 0);
871 static LLVMValueRef
build_buffer_load(struct si_shader_context
*ctx
,
875 LLVMValueRef voffset
,
876 LLVMValueRef soffset
,
877 unsigned inst_offset
,
881 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
882 unsigned func
= CLAMP(num_channels
, 1, 3) - 1;
884 if (HAVE_LLVM
>= 0x309) {
885 LLVMValueRef args
[] = {
886 LLVMBuildBitCast(gallivm
->builder
, rsrc
, ctx
->v4i32
, ""),
887 vindex
? vindex
: LLVMConstInt(ctx
->i32
, 0, 0),
888 LLVMConstInt(ctx
->i32
, inst_offset
, 0),
889 LLVMConstInt(ctx
->i1
, glc
, 0),
890 LLVMConstInt(ctx
->i1
, slc
, 0)
893 LLVMTypeRef types
[] = {ctx
->f32
, LLVMVectorType(ctx
->f32
, 2),
895 const char *type_names
[] = {"f32", "v2f32", "v4f32"};
899 args
[2] = LLVMBuildAdd(gallivm
->builder
, args
[2], voffset
,
904 args
[2] = LLVMBuildAdd(gallivm
->builder
, args
[2], soffset
,
908 snprintf(name
, sizeof(name
), "llvm.amdgcn.buffer.load.%s",
911 return lp_build_intrinsic(gallivm
->builder
, name
, types
[func
], args
,
912 ARRAY_SIZE(args
), LLVMReadOnlyAttribute
);
914 LLVMValueRef args
[] = {
915 LLVMBuildBitCast(gallivm
->builder
, rsrc
, ctx
->v16i8
, ""),
916 voffset
? voffset
: vindex
,
918 LLVMConstInt(ctx
->i32
, inst_offset
, 0),
919 LLVMConstInt(ctx
->i32
, voffset
? 1 : 0, 0), // offen
920 LLVMConstInt(ctx
->i32
, vindex
? 1 : 0, 0), //idxen
921 LLVMConstInt(ctx
->i32
, glc
, 0),
922 LLVMConstInt(ctx
->i32
, slc
, 0),
923 LLVMConstInt(ctx
->i32
, 0, 0), // TFE
926 LLVMTypeRef types
[] = {ctx
->i32
, LLVMVectorType(ctx
->i32
, 2),
928 const char *type_names
[] = {"i32", "v2i32", "v4i32"};
929 const char *arg_type
= "i32";
932 if (voffset
&& vindex
) {
933 LLVMValueRef vaddr
[] = {vindex
, voffset
};
936 args
[1] = lp_build_gather_values(gallivm
, vaddr
, 2);
939 snprintf(name
, sizeof(name
), "llvm.SI.buffer.load.dword.%s.%s",
940 type_names
[func
], arg_type
);
942 return lp_build_intrinsic(gallivm
->builder
, name
, types
[func
], args
,
943 ARRAY_SIZE(args
), LLVMReadOnlyAttribute
);
947 static LLVMValueRef
buffer_load(struct lp_build_tgsi_context
*bld_base
,
948 enum tgsi_opcode_type type
, unsigned swizzle
,
949 LLVMValueRef buffer
, LLVMValueRef offset
,
952 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
953 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
954 LLVMValueRef value
, value2
;
955 LLVMTypeRef llvm_type
= tgsi2llvmtype(bld_base
, type
);
956 LLVMTypeRef vec_type
= LLVMVectorType(llvm_type
, 4);
959 value
= build_buffer_load(ctx
, buffer
, 4, NULL
, base
, offset
,
962 return LLVMBuildBitCast(gallivm
->builder
, value
, vec_type
, "");
965 if (!tgsi_type_is_64bit(type
)) {
966 value
= build_buffer_load(ctx
, buffer
, 4, NULL
, base
, offset
,
969 value
= LLVMBuildBitCast(gallivm
->builder
, value
, vec_type
, "");
970 return LLVMBuildExtractElement(gallivm
->builder
, value
,
971 lp_build_const_int32(gallivm
, swizzle
), "");
974 value
= build_buffer_load(ctx
, buffer
, 1, NULL
, base
, offset
,
977 value2
= build_buffer_load(ctx
, buffer
, 1, NULL
, base
, offset
,
978 swizzle
* 4 + 4, 1, 0);
980 return radeon_llvm_emit_fetch_64bit(bld_base
, type
, value
, value2
);
986 * \param type output value type
987 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
988 * \param dw_addr address in dwords
990 static LLVMValueRef
lds_load(struct lp_build_tgsi_context
*bld_base
,
991 enum tgsi_opcode_type type
, unsigned swizzle
,
992 LLVMValueRef dw_addr
)
994 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
995 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
999 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
1001 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++)
1002 values
[chan
] = lds_load(bld_base
, type
, chan
, dw_addr
);
1004 return lp_build_gather_values(bld_base
->base
.gallivm
, values
,
1008 dw_addr
= lp_build_add(&bld_base
->uint_bld
, dw_addr
,
1009 lp_build_const_int32(gallivm
, swizzle
));
1011 value
= build_indexed_load(ctx
, ctx
->lds
, dw_addr
, false);
1012 if (tgsi_type_is_64bit(type
)) {
1013 LLVMValueRef value2
;
1014 dw_addr
= lp_build_add(&bld_base
->uint_bld
, dw_addr
,
1015 lp_build_const_int32(gallivm
, swizzle
+ 1));
1016 value2
= build_indexed_load(ctx
, ctx
->lds
, dw_addr
, false);
1017 return radeon_llvm_emit_fetch_64bit(bld_base
, type
, value
, value2
);
1020 return LLVMBuildBitCast(gallivm
->builder
, value
,
1021 tgsi2llvmtype(bld_base
, type
), "");
1027 * \param swizzle offset (typically 0..3)
1028 * \param dw_addr address in dwords
1029 * \param value value to store
1031 static void lds_store(struct lp_build_tgsi_context
*bld_base
,
1032 unsigned swizzle
, LLVMValueRef dw_addr
,
1035 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1036 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1038 dw_addr
= lp_build_add(&bld_base
->uint_bld
, dw_addr
,
1039 lp_build_const_int32(gallivm
, swizzle
));
1041 value
= LLVMBuildBitCast(gallivm
->builder
, value
, ctx
->i32
, "");
1042 build_indexed_store(ctx
, ctx
->lds
,
1046 static LLVMValueRef
fetch_input_tcs(
1047 struct lp_build_tgsi_context
*bld_base
,
1048 const struct tgsi_full_src_register
*reg
,
1049 enum tgsi_opcode_type type
, unsigned swizzle
)
1051 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1052 LLVMValueRef dw_addr
, stride
;
1054 stride
= unpack_param(ctx
, SI_PARAM_TCS_IN_LAYOUT
, 13, 8);
1055 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1056 dw_addr
= get_dw_address(ctx
, NULL
, reg
, stride
, dw_addr
);
1058 return lds_load(bld_base
, type
, swizzle
, dw_addr
);
1061 static LLVMValueRef
fetch_output_tcs(
1062 struct lp_build_tgsi_context
*bld_base
,
1063 const struct tgsi_full_src_register
*reg
,
1064 enum tgsi_opcode_type type
, unsigned swizzle
)
1066 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1067 LLVMValueRef dw_addr
, stride
;
1069 if (reg
->Register
.Dimension
) {
1070 stride
= unpack_param(ctx
, SI_PARAM_TCS_OUT_LAYOUT
, 13, 8);
1071 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1072 dw_addr
= get_dw_address(ctx
, NULL
, reg
, stride
, dw_addr
);
1074 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1075 dw_addr
= get_dw_address(ctx
, NULL
, reg
, NULL
, dw_addr
);
1078 return lds_load(bld_base
, type
, swizzle
, dw_addr
);
1081 static LLVMValueRef
fetch_input_tes(
1082 struct lp_build_tgsi_context
*bld_base
,
1083 const struct tgsi_full_src_register
*reg
,
1084 enum tgsi_opcode_type type
, unsigned swizzle
)
1086 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1087 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1088 LLVMValueRef rw_buffers
, buffer
, base
, addr
;
1090 rw_buffers
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
1091 SI_PARAM_RW_BUFFERS
);
1092 buffer
= build_indexed_load_const(ctx
, rw_buffers
,
1093 lp_build_const_int32(gallivm
, SI_HS_RING_TESS_OFFCHIP
));
1095 base
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, ctx
->param_oc_lds
);
1096 addr
= get_tcs_tes_buffer_address_from_reg(ctx
, NULL
, reg
);
1098 return buffer_load(bld_base
, type
, swizzle
, buffer
, base
, addr
);
1101 static void store_output_tcs(struct lp_build_tgsi_context
*bld_base
,
1102 const struct tgsi_full_instruction
*inst
,
1103 const struct tgsi_opcode_info
*info
,
1104 LLVMValueRef dst
[4])
1106 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1107 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1108 const struct tgsi_full_dst_register
*reg
= &inst
->Dst
[0];
1109 unsigned chan_index
;
1110 LLVMValueRef dw_addr
, stride
;
1111 LLVMValueRef rw_buffers
, buffer
, base
, buf_addr
;
1112 LLVMValueRef values
[4];
1114 /* Only handle per-patch and per-vertex outputs here.
1115 * Vectors will be lowered to scalars and this function will be called again.
1117 if (reg
->Register
.File
!= TGSI_FILE_OUTPUT
||
1118 (dst
[0] && LLVMGetTypeKind(LLVMTypeOf(dst
[0])) == LLVMVectorTypeKind
)) {
1119 radeon_llvm_emit_store(bld_base
, inst
, info
, dst
);
1123 if (reg
->Register
.Dimension
) {
1124 stride
= unpack_param(ctx
, SI_PARAM_TCS_OUT_LAYOUT
, 13, 8);
1125 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1126 dw_addr
= get_dw_address(ctx
, reg
, NULL
, stride
, dw_addr
);
1128 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1129 dw_addr
= get_dw_address(ctx
, reg
, NULL
, NULL
, dw_addr
);
1132 rw_buffers
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
1133 SI_PARAM_RW_BUFFERS
);
1134 buffer
= build_indexed_load_const(ctx
, rw_buffers
,
1135 lp_build_const_int32(gallivm
, SI_HS_RING_TESS_OFFCHIP
));
1137 base
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, ctx
->param_oc_lds
);
1138 buf_addr
= get_tcs_tes_buffer_address_from_reg(ctx
, reg
, NULL
);
1141 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst
, chan_index
) {
1142 LLVMValueRef value
= dst
[chan_index
];
1144 if (inst
->Instruction
.Saturate
)
1145 value
= radeon_llvm_saturate(bld_base
, value
);
1147 lds_store(bld_base
, chan_index
, dw_addr
, value
);
1149 value
= LLVMBuildBitCast(gallivm
->builder
, value
, ctx
->i32
, "");
1150 values
[chan_index
] = value
;
1152 if (inst
->Dst
[0].Register
.WriteMask
!= 0xF) {
1153 build_tbuffer_store_dwords(ctx
, buffer
, value
, 1,
1159 if (inst
->Dst
[0].Register
.WriteMask
== 0xF) {
1160 LLVMValueRef value
= lp_build_gather_values(bld_base
->base
.gallivm
,
1162 build_tbuffer_store_dwords(ctx
, buffer
, value
, 4, buf_addr
,
1167 static LLVMValueRef
fetch_input_gs(
1168 struct lp_build_tgsi_context
*bld_base
,
1169 const struct tgsi_full_src_register
*reg
,
1170 enum tgsi_opcode_type type
,
1173 struct lp_build_context
*base
= &bld_base
->base
;
1174 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1175 struct si_shader
*shader
= ctx
->shader
;
1176 struct lp_build_context
*uint
= &ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
1177 struct gallivm_state
*gallivm
= base
->gallivm
;
1178 LLVMValueRef vtx_offset
;
1179 LLVMValueRef args
[9];
1180 unsigned vtx_offset_param
;
1181 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1182 unsigned semantic_name
= info
->input_semantic_name
[reg
->Register
.Index
];
1183 unsigned semantic_index
= info
->input_semantic_index
[reg
->Register
.Index
];
1187 if (swizzle
!= ~0 && semantic_name
== TGSI_SEMANTIC_PRIMID
)
1188 return get_primitive_id(bld_base
, swizzle
);
1190 if (!reg
->Register
.Dimension
)
1193 if (swizzle
== ~0) {
1194 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
1196 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1197 values
[chan
] = fetch_input_gs(bld_base
, reg
, type
, chan
);
1199 return lp_build_gather_values(bld_base
->base
.gallivm
, values
,
1203 /* Get the vertex offset parameter */
1204 vtx_offset_param
= reg
->Dimension
.Index
;
1205 if (vtx_offset_param
< 2) {
1206 vtx_offset_param
+= SI_PARAM_VTX0_OFFSET
;
1208 assert(vtx_offset_param
< 6);
1209 vtx_offset_param
+= SI_PARAM_VTX2_OFFSET
- 2;
1211 vtx_offset
= lp_build_mul_imm(uint
,
1212 LLVMGetParam(ctx
->radeon_bld
.main_fn
,
1216 param
= si_shader_io_get_unique_index(semantic_name
, semantic_index
);
1217 args
[0] = ctx
->esgs_ring
;
1218 args
[1] = vtx_offset
;
1219 args
[2] = lp_build_const_int32(gallivm
, (param
* 4 + swizzle
) * 256);
1220 args
[3] = uint
->zero
;
1221 args
[4] = uint
->one
; /* OFFEN */
1222 args
[5] = uint
->zero
; /* IDXEN */
1223 args
[6] = uint
->one
; /* GLC */
1224 args
[7] = uint
->zero
; /* SLC */
1225 args
[8] = uint
->zero
; /* TFE */
1227 value
= lp_build_intrinsic(gallivm
->builder
,
1228 "llvm.SI.buffer.load.dword.i32.i32",
1230 LLVMReadOnlyAttribute
);
1231 if (tgsi_type_is_64bit(type
)) {
1232 LLVMValueRef value2
;
1233 args
[2] = lp_build_const_int32(gallivm
, (param
* 4 + swizzle
+ 1) * 256);
1234 value2
= lp_build_intrinsic(gallivm
->builder
,
1235 "llvm.SI.buffer.load.dword.i32.i32",
1237 LLVMReadOnlyAttribute
);
1238 return radeon_llvm_emit_fetch_64bit(bld_base
, type
,
1241 return LLVMBuildBitCast(gallivm
->builder
,
1243 tgsi2llvmtype(bld_base
, type
), "");
1246 static int lookup_interp_param_index(unsigned interpolate
, unsigned location
)
1248 switch (interpolate
) {
1249 case TGSI_INTERPOLATE_CONSTANT
:
1252 case TGSI_INTERPOLATE_LINEAR
:
1253 if (location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
1254 return SI_PARAM_LINEAR_SAMPLE
;
1255 else if (location
== TGSI_INTERPOLATE_LOC_CENTROID
)
1256 return SI_PARAM_LINEAR_CENTROID
;
1258 return SI_PARAM_LINEAR_CENTER
;
1260 case TGSI_INTERPOLATE_COLOR
:
1261 case TGSI_INTERPOLATE_PERSPECTIVE
:
1262 if (location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
1263 return SI_PARAM_PERSP_SAMPLE
;
1264 else if (location
== TGSI_INTERPOLATE_LOC_CENTROID
)
1265 return SI_PARAM_PERSP_CENTROID
;
1267 return SI_PARAM_PERSP_CENTER
;
1270 fprintf(stderr
, "Warning: Unhandled interpolation mode.\n");
1275 /* This shouldn't be used by explicit INTERP opcodes. */
1276 static unsigned select_interp_param(struct si_shader_context
*ctx
,
1279 if (!ctx
->is_monolithic
)
1282 if (ctx
->shader
->key
.ps
.prolog
.force_persp_sample_interp
) {
1284 case SI_PARAM_PERSP_CENTROID
:
1285 case SI_PARAM_PERSP_CENTER
:
1286 return SI_PARAM_PERSP_SAMPLE
;
1289 if (ctx
->shader
->key
.ps
.prolog
.force_linear_sample_interp
) {
1291 case SI_PARAM_LINEAR_CENTROID
:
1292 case SI_PARAM_LINEAR_CENTER
:
1293 return SI_PARAM_LINEAR_SAMPLE
;
1296 if (ctx
->shader
->key
.ps
.prolog
.force_persp_center_interp
) {
1298 case SI_PARAM_PERSP_CENTROID
:
1299 case SI_PARAM_PERSP_SAMPLE
:
1300 return SI_PARAM_PERSP_CENTER
;
1303 if (ctx
->shader
->key
.ps
.prolog
.force_linear_center_interp
) {
1305 case SI_PARAM_LINEAR_CENTROID
:
1306 case SI_PARAM_LINEAR_SAMPLE
:
1307 return SI_PARAM_LINEAR_CENTER
;
1315 * Interpolate a fragment shader input.
1317 * @param ctx context
1318 * @param input_index index of the input in hardware
1319 * @param semantic_name TGSI_SEMANTIC_*
1320 * @param semantic_index semantic index
1321 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1322 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1323 * @param interp_param interpolation weights (i,j)
1324 * @param prim_mask SI_PARAM_PRIM_MASK
1325 * @param face SI_PARAM_FRONT_FACE
1326 * @param result the return value (4 components)
1328 static void interp_fs_input(struct si_shader_context
*ctx
,
1329 unsigned input_index
,
1330 unsigned semantic_name
,
1331 unsigned semantic_index
,
1332 unsigned num_interp_inputs
,
1333 unsigned colors_read_mask
,
1334 LLVMValueRef interp_param
,
1335 LLVMValueRef prim_mask
,
1337 LLVMValueRef result
[4])
1339 struct lp_build_context
*base
= &ctx
->radeon_bld
.soa
.bld_base
.base
;
1340 struct lp_build_context
*uint
= &ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
1341 struct gallivm_state
*gallivm
= base
->gallivm
;
1342 const char *intr_name
;
1343 LLVMValueRef attr_number
;
1347 attr_number
= lp_build_const_int32(gallivm
, input_index
);
1349 /* fs.constant returns the param from the middle vertex, so it's not
1350 * really useful for flat shading. It's meant to be used for custom
1351 * interpolation (but the intrinsic can't fetch from the other two
1354 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1355 * to do the right thing. The only reason we use fs.constant is that
1356 * fs.interp cannot be used on integers, because they can be equal
1359 intr_name
= interp_param
? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
1361 if (semantic_name
== TGSI_SEMANTIC_COLOR
&&
1362 ctx
->shader
->key
.ps
.prolog
.color_two_side
) {
1363 LLVMValueRef args
[4];
1364 LLVMValueRef is_face_positive
;
1365 LLVMValueRef back_attr_number
;
1367 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1368 * otherwise it's at offset "num_inputs".
1370 unsigned back_attr_offset
= num_interp_inputs
;
1371 if (semantic_index
== 1 && colors_read_mask
& 0xf)
1372 back_attr_offset
+= 1;
1374 back_attr_number
= lp_build_const_int32(gallivm
, back_attr_offset
);
1376 is_face_positive
= LLVMBuildICmp(gallivm
->builder
, LLVMIntNE
,
1377 face
, uint
->zero
, "");
1379 args
[2] = prim_mask
;
1380 args
[3] = interp_param
;
1381 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1382 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
1383 LLVMValueRef front
, back
;
1385 args
[0] = llvm_chan
;
1386 args
[1] = attr_number
;
1387 front
= lp_build_intrinsic(gallivm
->builder
, intr_name
,
1388 ctx
->f32
, args
, args
[3] ? 4 : 3,
1389 LLVMReadNoneAttribute
);
1391 args
[1] = back_attr_number
;
1392 back
= lp_build_intrinsic(gallivm
->builder
, intr_name
,
1393 ctx
->f32
, args
, args
[3] ? 4 : 3,
1394 LLVMReadNoneAttribute
);
1396 result
[chan
] = LLVMBuildSelect(gallivm
->builder
,
1402 } else if (semantic_name
== TGSI_SEMANTIC_FOG
) {
1403 LLVMValueRef args
[4];
1405 args
[0] = uint
->zero
;
1406 args
[1] = attr_number
;
1407 args
[2] = prim_mask
;
1408 args
[3] = interp_param
;
1409 result
[0] = lp_build_intrinsic(gallivm
->builder
, intr_name
,
1410 ctx
->f32
, args
, args
[3] ? 4 : 3,
1411 LLVMReadNoneAttribute
);
1413 result
[2] = lp_build_const_float(gallivm
, 0.0f
);
1414 result
[3] = lp_build_const_float(gallivm
, 1.0f
);
1416 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1417 LLVMValueRef args
[4];
1418 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
1420 args
[0] = llvm_chan
;
1421 args
[1] = attr_number
;
1422 args
[2] = prim_mask
;
1423 args
[3] = interp_param
;
1424 result
[chan
] = lp_build_intrinsic(gallivm
->builder
, intr_name
,
1425 ctx
->f32
, args
, args
[3] ? 4 : 3,
1426 LLVMReadNoneAttribute
);
1431 /* LLVMGetParam with bc_optimize resolved. */
1432 static LLVMValueRef
get_interp_param(struct si_shader_context
*ctx
,
1433 int interp_param_idx
)
1435 LLVMBuilderRef builder
= ctx
->radeon_bld
.gallivm
.builder
;
1436 LLVMValueRef main_fn
= ctx
->radeon_bld
.main_fn
;
1437 LLVMValueRef param
= NULL
;
1439 /* Handle PRIM_MASK[31] (bc_optimize). */
1440 if (ctx
->is_monolithic
&&
1441 ((ctx
->shader
->key
.ps
.prolog
.bc_optimize_for_persp
&&
1442 interp_param_idx
== SI_PARAM_PERSP_CENTROID
) ||
1443 (ctx
->shader
->key
.ps
.prolog
.bc_optimize_for_linear
&&
1444 interp_param_idx
== SI_PARAM_LINEAR_CENTROID
))) {
1445 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
1446 * The hw doesn't compute CENTROID if the whole wave only
1447 * contains fully-covered quads.
1449 LLVMValueRef bc_optimize
=
1450 LLVMGetParam(main_fn
, SI_PARAM_PRIM_MASK
);
1451 bc_optimize
= LLVMBuildLShr(builder
,
1453 LLVMConstInt(ctx
->i32
, 31, 0), "");
1454 bc_optimize
= LLVMBuildTrunc(builder
, bc_optimize
, ctx
->i1
, "");
1456 if (ctx
->shader
->key
.ps
.prolog
.bc_optimize_for_persp
&&
1457 interp_param_idx
== SI_PARAM_PERSP_CENTROID
) {
1458 param
= LLVMBuildSelect(builder
, bc_optimize
,
1459 LLVMGetParam(main_fn
,
1460 SI_PARAM_PERSP_CENTER
),
1461 LLVMGetParam(main_fn
,
1462 SI_PARAM_PERSP_CENTROID
),
1465 if (ctx
->shader
->key
.ps
.prolog
.bc_optimize_for_linear
&&
1466 interp_param_idx
== SI_PARAM_LINEAR_CENTROID
) {
1467 param
= LLVMBuildSelect(builder
, bc_optimize
,
1468 LLVMGetParam(main_fn
,
1469 SI_PARAM_LINEAR_CENTER
),
1470 LLVMGetParam(main_fn
,
1471 SI_PARAM_LINEAR_CENTROID
),
1477 param
= LLVMGetParam(main_fn
, interp_param_idx
);
1481 static void declare_input_fs(
1482 struct radeon_llvm_context
*radeon_bld
,
1483 unsigned input_index
,
1484 const struct tgsi_full_declaration
*decl
)
1486 struct lp_build_context
*base
= &radeon_bld
->soa
.bld_base
.base
;
1487 struct si_shader_context
*ctx
=
1488 si_shader_context(&radeon_bld
->soa
.bld_base
);
1489 struct si_shader
*shader
= ctx
->shader
;
1490 LLVMValueRef main_fn
= radeon_bld
->main_fn
;
1491 LLVMValueRef interp_param
= NULL
;
1492 int interp_param_idx
;
1494 /* Get colors from input VGPRs (set by the prolog). */
1495 if (!ctx
->is_monolithic
&&
1496 decl
->Semantic
.Name
== TGSI_SEMANTIC_COLOR
) {
1497 unsigned i
= decl
->Semantic
.Index
;
1498 unsigned colors_read
= shader
->selector
->info
.colors_read
;
1499 unsigned mask
= colors_read
>> (i
* 4);
1500 unsigned offset
= SI_PARAM_POS_FIXED_PT
+ 1 +
1501 (i
? util_bitcount(colors_read
& 0xf) : 0);
1503 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 0)] =
1504 mask
& 0x1 ? LLVMGetParam(main_fn
, offset
++) : base
->undef
;
1505 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 1)] =
1506 mask
& 0x2 ? LLVMGetParam(main_fn
, offset
++) : base
->undef
;
1507 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 2)] =
1508 mask
& 0x4 ? LLVMGetParam(main_fn
, offset
++) : base
->undef
;
1509 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 3)] =
1510 mask
& 0x8 ? LLVMGetParam(main_fn
, offset
++) : base
->undef
;
1514 interp_param_idx
= lookup_interp_param_index(decl
->Interp
.Interpolate
,
1515 decl
->Interp
.Location
);
1516 if (interp_param_idx
== -1)
1518 else if (interp_param_idx
) {
1519 interp_param_idx
= select_interp_param(ctx
,
1521 interp_param
= get_interp_param(ctx
, interp_param_idx
);
1524 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_COLOR
&&
1525 decl
->Interp
.Interpolate
== TGSI_INTERPOLATE_COLOR
&&
1526 ctx
->shader
->key
.ps
.prolog
.flatshade_colors
)
1527 interp_param
= NULL
; /* load the constant color */
1529 interp_fs_input(ctx
, input_index
, decl
->Semantic
.Name
,
1530 decl
->Semantic
.Index
, shader
->selector
->info
.num_inputs
,
1531 shader
->selector
->info
.colors_read
, interp_param
,
1532 LLVMGetParam(main_fn
, SI_PARAM_PRIM_MASK
),
1533 LLVMGetParam(main_fn
, SI_PARAM_FRONT_FACE
),
1534 &radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 0)]);
1537 static LLVMValueRef
get_sample_id(struct radeon_llvm_context
*radeon_bld
)
1539 return unpack_param(si_shader_context(&radeon_bld
->soa
.bld_base
),
1540 SI_PARAM_ANCILLARY
, 8, 4);
1544 * Set range metadata on an instruction. This can only be used on load and
1545 * call instructions. If you know an instruction can only produce the values
1546 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1547 * \p lo is the minimum value inclusive.
1548 * \p hi is the maximum value exclusive.
1550 static void set_range_metadata(LLVMValueRef value
, unsigned lo
, unsigned hi
)
1552 const char *range_md_string
= "range";
1553 LLVMValueRef range_md
, md_args
[2];
1554 LLVMTypeRef type
= LLVMTypeOf(value
);
1555 LLVMContextRef context
= LLVMGetTypeContext(type
);
1556 unsigned md_range_id
= LLVMGetMDKindIDInContext(context
,
1557 range_md_string
, strlen(range_md_string
));
1559 md_args
[0] = LLVMConstInt(type
, lo
, false);
1560 md_args
[1] = LLVMConstInt(type
, hi
, false);
1561 range_md
= LLVMMDNodeInContext(context
, md_args
, 2);
1562 LLVMSetMetadata(value
, md_range_id
, range_md
);
1565 static LLVMValueRef
get_thread_id(struct si_shader_context
*ctx
)
1567 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
1570 if (HAVE_LLVM
< 0x0308) {
1571 tid
= lp_build_intrinsic(gallivm
->builder
, "llvm.SI.tid",
1572 ctx
->i32
, NULL
, 0, LLVMReadNoneAttribute
);
1574 LLVMValueRef tid_args
[2];
1575 tid_args
[0] = lp_build_const_int32(gallivm
, 0xffffffff);
1576 tid_args
[1] = lp_build_const_int32(gallivm
, 0);
1577 tid_args
[1] = lp_build_intrinsic(gallivm
->builder
,
1578 "llvm.amdgcn.mbcnt.lo", ctx
->i32
,
1579 tid_args
, 2, LLVMReadNoneAttribute
);
1581 tid
= lp_build_intrinsic(gallivm
->builder
,
1582 "llvm.amdgcn.mbcnt.hi", ctx
->i32
,
1583 tid_args
, 2, LLVMReadNoneAttribute
);
1585 set_range_metadata(tid
, 0, 64);
1590 * Load a dword from a constant buffer.
1592 static LLVMValueRef
buffer_load_const(LLVMBuilderRef builder
, LLVMValueRef resource
,
1593 LLVMValueRef offset
, LLVMTypeRef return_type
)
1595 LLVMValueRef args
[2] = {resource
, offset
};
1597 return lp_build_intrinsic(builder
, "llvm.SI.load.const", return_type
, args
, 2,
1598 LLVMReadNoneAttribute
);
1601 static LLVMValueRef
load_sample_position(struct radeon_llvm_context
*radeon_bld
, LLVMValueRef sample_id
)
1603 struct si_shader_context
*ctx
=
1604 si_shader_context(&radeon_bld
->soa
.bld_base
);
1605 struct lp_build_context
*uint_bld
= &radeon_bld
->soa
.bld_base
.uint_bld
;
1606 struct gallivm_state
*gallivm
= &radeon_bld
->gallivm
;
1607 LLVMBuilderRef builder
= gallivm
->builder
;
1608 LLVMValueRef desc
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_RW_BUFFERS
);
1609 LLVMValueRef buf_index
= lp_build_const_int32(gallivm
, SI_PS_CONST_SAMPLE_POSITIONS
);
1610 LLVMValueRef resource
= build_indexed_load_const(ctx
, desc
, buf_index
);
1612 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1613 LLVMValueRef offset0
= lp_build_mul_imm(uint_bld
, sample_id
, 8);
1614 LLVMValueRef offset1
= LLVMBuildAdd(builder
, offset0
, lp_build_const_int32(gallivm
, 4), "");
1616 LLVMValueRef pos
[4] = {
1617 buffer_load_const(builder
, resource
, offset0
, ctx
->f32
),
1618 buffer_load_const(builder
, resource
, offset1
, ctx
->f32
),
1619 lp_build_const_float(gallivm
, 0),
1620 lp_build_const_float(gallivm
, 0)
1623 return lp_build_gather_values(gallivm
, pos
, 4);
1626 static void declare_system_value(
1627 struct radeon_llvm_context
*radeon_bld
,
1629 const struct tgsi_full_declaration
*decl
)
1631 struct si_shader_context
*ctx
=
1632 si_shader_context(&radeon_bld
->soa
.bld_base
);
1633 struct lp_build_context
*bld
= &radeon_bld
->soa
.bld_base
.base
;
1634 struct gallivm_state
*gallivm
= &radeon_bld
->gallivm
;
1635 LLVMValueRef value
= 0;
1637 switch (decl
->Semantic
.Name
) {
1638 case TGSI_SEMANTIC_INSTANCEID
:
1639 value
= LLVMGetParam(radeon_bld
->main_fn
,
1640 ctx
->param_instance_id
);
1643 case TGSI_SEMANTIC_VERTEXID
:
1644 value
= LLVMBuildAdd(gallivm
->builder
,
1645 LLVMGetParam(radeon_bld
->main_fn
,
1646 ctx
->param_vertex_id
),
1647 LLVMGetParam(radeon_bld
->main_fn
,
1648 SI_PARAM_BASE_VERTEX
), "");
1651 case TGSI_SEMANTIC_VERTEXID_NOBASE
:
1652 value
= LLVMGetParam(radeon_bld
->main_fn
,
1653 ctx
->param_vertex_id
);
1656 case TGSI_SEMANTIC_BASEVERTEX
:
1657 value
= LLVMGetParam(radeon_bld
->main_fn
,
1658 SI_PARAM_BASE_VERTEX
);
1661 case TGSI_SEMANTIC_INVOCATIONID
:
1662 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
1663 value
= unpack_param(ctx
, SI_PARAM_REL_IDS
, 8, 5);
1664 else if (ctx
->type
== PIPE_SHADER_GEOMETRY
)
1665 value
= LLVMGetParam(radeon_bld
->main_fn
,
1666 SI_PARAM_GS_INSTANCE_ID
);
1668 assert(!"INVOCATIONID not implemented");
1671 case TGSI_SEMANTIC_POSITION
:
1673 LLVMValueRef pos
[4] = {
1674 LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_POS_X_FLOAT
),
1675 LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_POS_Y_FLOAT
),
1676 LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_POS_Z_FLOAT
),
1677 lp_build_emit_llvm_unary(&radeon_bld
->soa
.bld_base
, TGSI_OPCODE_RCP
,
1678 LLVMGetParam(radeon_bld
->main_fn
,
1679 SI_PARAM_POS_W_FLOAT
)),
1681 value
= lp_build_gather_values(gallivm
, pos
, 4);
1685 case TGSI_SEMANTIC_FACE
:
1686 value
= LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_FRONT_FACE
);
1689 case TGSI_SEMANTIC_SAMPLEID
:
1690 value
= get_sample_id(radeon_bld
);
1693 case TGSI_SEMANTIC_SAMPLEPOS
: {
1694 LLVMValueRef pos
[4] = {
1695 LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_POS_X_FLOAT
),
1696 LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_POS_Y_FLOAT
),
1697 lp_build_const_float(gallivm
, 0),
1698 lp_build_const_float(gallivm
, 0)
1700 pos
[0] = lp_build_emit_llvm_unary(&radeon_bld
->soa
.bld_base
,
1701 TGSI_OPCODE_FRC
, pos
[0]);
1702 pos
[1] = lp_build_emit_llvm_unary(&radeon_bld
->soa
.bld_base
,
1703 TGSI_OPCODE_FRC
, pos
[1]);
1704 value
= lp_build_gather_values(gallivm
, pos
, 4);
1708 case TGSI_SEMANTIC_SAMPLEMASK
:
1709 /* This can only occur with the OpenGL Core profile, which
1710 * doesn't support smoothing.
1712 value
= LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_SAMPLE_COVERAGE
);
1715 case TGSI_SEMANTIC_TESSCOORD
:
1717 LLVMValueRef coord
[4] = {
1718 LLVMGetParam(radeon_bld
->main_fn
, ctx
->param_tes_u
),
1719 LLVMGetParam(radeon_bld
->main_fn
, ctx
->param_tes_v
),
1724 /* For triangles, the vector should be (u, v, 1-u-v). */
1725 if (ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] ==
1726 PIPE_PRIM_TRIANGLES
)
1727 coord
[2] = lp_build_sub(bld
, bld
->one
,
1728 lp_build_add(bld
, coord
[0], coord
[1]));
1730 value
= lp_build_gather_values(gallivm
, coord
, 4);
1734 case TGSI_SEMANTIC_VERTICESIN
:
1735 value
= unpack_param(ctx
, SI_PARAM_TCS_OUT_LAYOUT
, 26, 6);
1738 case TGSI_SEMANTIC_TESSINNER
:
1739 case TGSI_SEMANTIC_TESSOUTER
:
1741 LLVMValueRef rw_buffers
, buffer
, base
, addr
;
1742 int param
= si_shader_io_get_unique_index(decl
->Semantic
.Name
, 0);
1744 rw_buffers
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
1745 SI_PARAM_RW_BUFFERS
);
1746 buffer
= build_indexed_load_const(ctx
, rw_buffers
,
1747 lp_build_const_int32(gallivm
, SI_HS_RING_TESS_OFFCHIP
));
1749 base
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, ctx
->param_oc_lds
);
1750 addr
= get_tcs_tes_buffer_address(ctx
, NULL
,
1751 lp_build_const_int32(gallivm
, param
));
1753 value
= buffer_load(&radeon_bld
->soa
.bld_base
, TGSI_TYPE_FLOAT
,
1754 ~0, buffer
, base
, addr
);
1759 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
:
1760 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
:
1762 LLVMValueRef buf
, slot
, val
[4];
1765 slot
= lp_build_const_int32(gallivm
, SI_HS_CONST_DEFAULT_TESS_LEVELS
);
1766 buf
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_RW_BUFFERS
);
1767 buf
= build_indexed_load_const(ctx
, buf
, slot
);
1768 offset
= decl
->Semantic
.Name
== TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
? 4 : 0;
1770 for (i
= 0; i
< 4; i
++)
1771 val
[i
] = buffer_load_const(gallivm
->builder
, buf
,
1772 lp_build_const_int32(gallivm
, (offset
+ i
) * 4),
1774 value
= lp_build_gather_values(gallivm
, val
, 4);
1778 case TGSI_SEMANTIC_PRIMID
:
1779 value
= get_primitive_id(&radeon_bld
->soa
.bld_base
, 0);
1782 case TGSI_SEMANTIC_GRID_SIZE
:
1783 value
= LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_GRID_SIZE
);
1786 case TGSI_SEMANTIC_BLOCK_SIZE
:
1788 LLVMValueRef values
[3];
1790 unsigned *properties
= ctx
->shader
->selector
->info
.properties
;
1791 unsigned sizes
[3] = {
1792 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
],
1793 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
],
1794 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
]
1797 for (i
= 0; i
< 3; ++i
)
1798 values
[i
] = lp_build_const_int32(gallivm
, sizes
[i
]);
1800 value
= lp_build_gather_values(gallivm
, values
, 3);
1804 case TGSI_SEMANTIC_BLOCK_ID
:
1805 value
= LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_BLOCK_ID
);
1808 case TGSI_SEMANTIC_THREAD_ID
:
1809 value
= LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_THREAD_ID
);
1812 #if HAVE_LLVM >= 0x0309
1813 case TGSI_SEMANTIC_HELPER_INVOCATION
:
1814 value
= lp_build_intrinsic(gallivm
->builder
,
1815 "llvm.amdgcn.ps.live",
1817 LLVMReadNoneAttribute
);
1818 value
= LLVMBuildNot(gallivm
->builder
, value
, "");
1819 value
= LLVMBuildSExt(gallivm
->builder
, value
, ctx
->i32
, "");
1824 assert(!"unknown system value");
1828 radeon_bld
->system_values
[index
] = value
;
1831 static void declare_compute_memory(struct radeon_llvm_context
*radeon_bld
,
1832 const struct tgsi_full_declaration
*decl
)
1834 struct si_shader_context
*ctx
=
1835 si_shader_context(&radeon_bld
->soa
.bld_base
);
1836 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
1837 struct gallivm_state
*gallivm
= &radeon_bld
->gallivm
;
1839 LLVMTypeRef i8p
= LLVMPointerType(ctx
->i8
, LOCAL_ADDR_SPACE
);
1842 assert(decl
->Declaration
.MemType
== TGSI_MEMORY_TYPE_SHARED
);
1843 assert(decl
->Range
.First
== decl
->Range
.Last
);
1844 assert(!ctx
->shared_memory
);
1846 var
= LLVMAddGlobalInAddressSpace(gallivm
->module
,
1847 LLVMArrayType(ctx
->i8
, sel
->local_size
),
1850 LLVMSetAlignment(var
, 4);
1852 ctx
->shared_memory
= LLVMBuildBitCast(gallivm
->builder
, var
, i8p
, "");
1855 static LLVMValueRef
fetch_constant(
1856 struct lp_build_tgsi_context
*bld_base
,
1857 const struct tgsi_full_src_register
*reg
,
1858 enum tgsi_opcode_type type
,
1861 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1862 struct lp_build_context
*base
= &bld_base
->base
;
1863 const struct tgsi_ind_register
*ireg
= ®
->Indirect
;
1866 LLVMValueRef addr
, bufp
;
1867 LLVMValueRef result
;
1869 if (swizzle
== LP_CHAN_ALL
) {
1871 LLVMValueRef values
[4];
1872 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; ++chan
)
1873 values
[chan
] = fetch_constant(bld_base
, reg
, type
, chan
);
1875 return lp_build_gather_values(bld_base
->base
.gallivm
, values
, 4);
1878 buf
= reg
->Register
.Dimension
? reg
->Dimension
.Index
: 0;
1879 idx
= reg
->Register
.Index
* 4 + swizzle
;
1881 if (!reg
->Register
.Indirect
&& !reg
->Dimension
.Indirect
) {
1882 if (!tgsi_type_is_64bit(type
))
1883 return bitcast(bld_base
, type
, ctx
->constants
[buf
][idx
]);
1885 return radeon_llvm_emit_fetch_64bit(bld_base
, type
,
1886 ctx
->constants
[buf
][idx
],
1887 ctx
->constants
[buf
][idx
+ 1]);
1891 if (reg
->Register
.Dimension
&& reg
->Dimension
.Indirect
) {
1892 LLVMValueRef ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_CONST_BUFFERS
);
1894 index
= get_bounded_indirect_index(ctx
, ®
->DimIndirect
,
1895 reg
->Dimension
.Index
,
1896 SI_NUM_CONST_BUFFERS
);
1897 bufp
= build_indexed_load_const(ctx
, ptr
, index
);
1899 bufp
= ctx
->const_buffers
[buf
];
1901 addr
= ctx
->radeon_bld
.soa
.addr
[ireg
->Index
][ireg
->Swizzle
];
1902 addr
= LLVMBuildLoad(base
->gallivm
->builder
, addr
, "load addr reg");
1903 addr
= lp_build_mul_imm(&bld_base
->uint_bld
, addr
, 16);
1904 addr
= lp_build_add(&bld_base
->uint_bld
, addr
,
1905 lp_build_const_int32(base
->gallivm
, idx
* 4));
1907 result
= buffer_load_const(base
->gallivm
->builder
, bufp
,
1910 if (!tgsi_type_is_64bit(type
))
1911 result
= bitcast(bld_base
, type
, result
);
1913 LLVMValueRef addr2
, result2
;
1914 addr2
= ctx
->radeon_bld
.soa
.addr
[ireg
->Index
][ireg
->Swizzle
+ 1];
1915 addr2
= LLVMBuildLoad(base
->gallivm
->builder
, addr2
, "load addr reg2");
1916 addr2
= lp_build_mul_imm(&bld_base
->uint_bld
, addr2
, 16);
1917 addr2
= lp_build_add(&bld_base
->uint_bld
, addr2
,
1918 lp_build_const_int32(base
->gallivm
, idx
* 4));
1920 result2
= buffer_load_const(base
->gallivm
->builder
, ctx
->const_buffers
[buf
],
1923 result
= radeon_llvm_emit_fetch_64bit(bld_base
, type
,
1929 /* Upper 16 bits must be zero. */
1930 static LLVMValueRef
si_llvm_pack_two_int16(struct gallivm_state
*gallivm
,
1931 LLVMValueRef val
[2])
1933 return LLVMBuildOr(gallivm
->builder
, val
[0],
1934 LLVMBuildShl(gallivm
->builder
, val
[1],
1935 lp_build_const_int32(gallivm
, 16),
1939 /* Upper 16 bits are ignored and will be dropped. */
1940 static LLVMValueRef
si_llvm_pack_two_int32_as_int16(struct gallivm_state
*gallivm
,
1941 LLVMValueRef val
[2])
1943 LLVMValueRef v
[2] = {
1944 LLVMBuildAnd(gallivm
->builder
, val
[0],
1945 lp_build_const_int32(gallivm
, 0xffff), ""),
1948 return si_llvm_pack_two_int16(gallivm
, v
);
1951 /* Initialize arguments for the shader export intrinsic */
1952 static void si_llvm_init_export_args(struct lp_build_tgsi_context
*bld_base
,
1953 LLVMValueRef
*values
,
1957 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1958 struct lp_build_context
*uint
=
1959 &ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
1960 struct lp_build_context
*base
= &bld_base
->base
;
1961 struct gallivm_state
*gallivm
= base
->gallivm
;
1962 LLVMBuilderRef builder
= base
->gallivm
->builder
;
1963 LLVMValueRef val
[4];
1964 unsigned spi_shader_col_format
= V_028714_SPI_SHADER_32_ABGR
;
1968 /* Default is 0xf. Adjusted below depending on the format. */
1969 args
[0] = lp_build_const_int32(base
->gallivm
, 0xf); /* writemask */
1971 /* Specify whether the EXEC mask represents the valid mask */
1972 args
[1] = uint
->zero
;
1974 /* Specify whether this is the last export */
1975 args
[2] = uint
->zero
;
1977 /* Specify the target we are exporting */
1978 args
[3] = lp_build_const_int32(base
->gallivm
, target
);
1980 if (ctx
->type
== PIPE_SHADER_FRAGMENT
) {
1981 const union si_shader_key
*key
= &ctx
->shader
->key
;
1982 unsigned col_formats
= key
->ps
.epilog
.spi_shader_col_format
;
1983 int cbuf
= target
- V_008DFC_SQ_EXP_MRT
;
1985 assert(cbuf
>= 0 && cbuf
< 8);
1986 spi_shader_col_format
= (col_formats
>> (cbuf
* 4)) & 0xf;
1987 is_int8
= (key
->ps
.epilog
.color_is_int8
>> cbuf
) & 0x1;
1990 args
[4] = uint
->zero
; /* COMPR flag */
1991 args
[5] = base
->undef
;
1992 args
[6] = base
->undef
;
1993 args
[7] = base
->undef
;
1994 args
[8] = base
->undef
;
1996 switch (spi_shader_col_format
) {
1997 case V_028714_SPI_SHADER_ZERO
:
1998 args
[0] = uint
->zero
; /* writemask */
1999 args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_NULL
);
2002 case V_028714_SPI_SHADER_32_R
:
2003 args
[0] = uint
->one
; /* writemask */
2004 args
[5] = values
[0];
2007 case V_028714_SPI_SHADER_32_GR
:
2008 args
[0] = lp_build_const_int32(base
->gallivm
, 0x3); /* writemask */
2009 args
[5] = values
[0];
2010 args
[6] = values
[1];
2013 case V_028714_SPI_SHADER_32_AR
:
2014 args
[0] = lp_build_const_int32(base
->gallivm
, 0x9); /* writemask */
2015 args
[5] = values
[0];
2016 args
[8] = values
[3];
2019 case V_028714_SPI_SHADER_FP16_ABGR
:
2020 args
[4] = uint
->one
; /* COMPR flag */
2022 for (chan
= 0; chan
< 2; chan
++) {
2023 LLVMValueRef pack_args
[2] = {
2025 values
[2 * chan
+ 1]
2027 LLVMValueRef packed
;
2029 packed
= lp_build_intrinsic(base
->gallivm
->builder
,
2031 ctx
->i32
, pack_args
, 2,
2032 LLVMReadNoneAttribute
);
2034 LLVMBuildBitCast(base
->gallivm
->builder
,
2035 packed
, ctx
->f32
, "");
2039 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2040 for (chan
= 0; chan
< 4; chan
++) {
2041 val
[chan
] = radeon_llvm_saturate(bld_base
, values
[chan
]);
2042 val
[chan
] = LLVMBuildFMul(builder
, val
[chan
],
2043 lp_build_const_float(gallivm
, 65535), "");
2044 val
[chan
] = LLVMBuildFAdd(builder
, val
[chan
],
2045 lp_build_const_float(gallivm
, 0.5), "");
2046 val
[chan
] = LLVMBuildFPToUI(builder
, val
[chan
],
2050 args
[4] = uint
->one
; /* COMPR flag */
2051 args
[5] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2052 si_llvm_pack_two_int16(gallivm
, val
));
2053 args
[6] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2054 si_llvm_pack_two_int16(gallivm
, val
+2));
2057 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2058 for (chan
= 0; chan
< 4; chan
++) {
2059 /* Clamp between [-1, 1]. */
2060 val
[chan
] = lp_build_emit_llvm_binary(bld_base
, TGSI_OPCODE_MIN
,
2062 lp_build_const_float(gallivm
, 1));
2063 val
[chan
] = lp_build_emit_llvm_binary(bld_base
, TGSI_OPCODE_MAX
,
2065 lp_build_const_float(gallivm
, -1));
2066 /* Convert to a signed integer in [-32767, 32767]. */
2067 val
[chan
] = LLVMBuildFMul(builder
, val
[chan
],
2068 lp_build_const_float(gallivm
, 32767), "");
2069 /* If positive, add 0.5, else add -0.5. */
2070 val
[chan
] = LLVMBuildFAdd(builder
, val
[chan
],
2071 LLVMBuildSelect(builder
,
2072 LLVMBuildFCmp(builder
, LLVMRealOGE
,
2073 val
[chan
], base
->zero
, ""),
2074 lp_build_const_float(gallivm
, 0.5),
2075 lp_build_const_float(gallivm
, -0.5), ""), "");
2076 val
[chan
] = LLVMBuildFPToSI(builder
, val
[chan
], ctx
->i32
, "");
2079 args
[4] = uint
->one
; /* COMPR flag */
2080 args
[5] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2081 si_llvm_pack_two_int32_as_int16(gallivm
, val
));
2082 args
[6] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2083 si_llvm_pack_two_int32_as_int16(gallivm
, val
+2));
2086 case V_028714_SPI_SHADER_UINT16_ABGR
: {
2087 LLVMValueRef max
= lp_build_const_int32(gallivm
, is_int8
?
2090 for (chan
= 0; chan
< 4; chan
++) {
2091 val
[chan
] = bitcast(bld_base
, TGSI_TYPE_UNSIGNED
, values
[chan
]);
2092 val
[chan
] = lp_build_emit_llvm_binary(bld_base
, TGSI_OPCODE_UMIN
,
2096 args
[4] = uint
->one
; /* COMPR flag */
2097 args
[5] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2098 si_llvm_pack_two_int16(gallivm
, val
));
2099 args
[6] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2100 si_llvm_pack_two_int16(gallivm
, val
+2));
2104 case V_028714_SPI_SHADER_SINT16_ABGR
: {
2105 LLVMValueRef max
= lp_build_const_int32(gallivm
, is_int8
?
2107 LLVMValueRef min
= lp_build_const_int32(gallivm
, is_int8
?
2110 for (chan
= 0; chan
< 4; chan
++) {
2111 val
[chan
] = bitcast(bld_base
, TGSI_TYPE_UNSIGNED
, values
[chan
]);
2112 val
[chan
] = lp_build_emit_llvm_binary(bld_base
,
2115 val
[chan
] = lp_build_emit_llvm_binary(bld_base
,
2120 args
[4] = uint
->one
; /* COMPR flag */
2121 args
[5] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2122 si_llvm_pack_two_int32_as_int16(gallivm
, val
));
2123 args
[6] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2124 si_llvm_pack_two_int32_as_int16(gallivm
, val
+2));
2128 case V_028714_SPI_SHADER_32_ABGR
:
2129 memcpy(&args
[5], values
, sizeof(values
[0]) * 4);
2134 static void si_alpha_test(struct lp_build_tgsi_context
*bld_base
,
2137 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2138 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2140 if (ctx
->shader
->key
.ps
.epilog
.alpha_func
!= PIPE_FUNC_NEVER
) {
2141 LLVMValueRef alpha_ref
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2142 SI_PARAM_ALPHA_REF
);
2144 LLVMValueRef alpha_pass
=
2145 lp_build_cmp(&bld_base
->base
,
2146 ctx
->shader
->key
.ps
.epilog
.alpha_func
,
2149 lp_build_select(&bld_base
->base
,
2151 lp_build_const_float(gallivm
, 1.0f
),
2152 lp_build_const_float(gallivm
, -1.0f
));
2154 lp_build_intrinsic(gallivm
->builder
, "llvm.AMDGPU.kill",
2155 ctx
->voidt
, &arg
, 1, 0);
2157 lp_build_intrinsic(gallivm
->builder
, "llvm.AMDGPU.kilp",
2158 ctx
->voidt
, NULL
, 0, 0);
2162 static LLVMValueRef
si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context
*bld_base
,
2164 unsigned samplemask_param
)
2166 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2167 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2168 LLVMValueRef coverage
;
2170 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2171 coverage
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2173 coverage
= bitcast(bld_base
, TGSI_TYPE_SIGNED
, coverage
);
2175 coverage
= lp_build_intrinsic(gallivm
->builder
, "llvm.ctpop.i32",
2177 &coverage
, 1, LLVMReadNoneAttribute
);
2179 coverage
= LLVMBuildUIToFP(gallivm
->builder
, coverage
,
2182 coverage
= LLVMBuildFMul(gallivm
->builder
, coverage
,
2183 lp_build_const_float(gallivm
,
2184 1.0 / SI_NUM_SMOOTH_AA_SAMPLES
), "");
2186 return LLVMBuildFMul(gallivm
->builder
, alpha
, coverage
, "");
2189 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context
*bld_base
,
2190 LLVMValueRef (*pos
)[9], LLVMValueRef
*out_elts
)
2192 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2193 struct lp_build_context
*base
= &bld_base
->base
;
2194 struct lp_build_context
*uint
= &ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
2197 unsigned const_chan
;
2198 LLVMValueRef base_elt
;
2199 LLVMValueRef ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_RW_BUFFERS
);
2200 LLVMValueRef constbuf_index
= lp_build_const_int32(base
->gallivm
,
2201 SI_VS_CONST_CLIP_PLANES
);
2202 LLVMValueRef const_resource
= build_indexed_load_const(ctx
, ptr
, constbuf_index
);
2204 for (reg_index
= 0; reg_index
< 2; reg_index
++) {
2205 LLVMValueRef
*args
= pos
[2 + reg_index
];
2210 args
[8] = lp_build_const_float(base
->gallivm
, 0.0f
);
2212 /* Compute dot products of position and user clip plane vectors */
2213 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2214 for (const_chan
= 0; const_chan
< TGSI_NUM_CHANNELS
; const_chan
++) {
2215 args
[1] = lp_build_const_int32(base
->gallivm
,
2216 ((reg_index
* 4 + chan
) * 4 +
2218 base_elt
= buffer_load_const(base
->gallivm
->builder
, const_resource
,
2221 lp_build_add(base
, args
[5 + chan
],
2222 lp_build_mul(base
, base_elt
,
2223 out_elts
[const_chan
]));
2227 args
[0] = lp_build_const_int32(base
->gallivm
, 0xf);
2228 args
[1] = uint
->zero
;
2229 args
[2] = uint
->zero
;
2230 args
[3] = lp_build_const_int32(base
->gallivm
,
2231 V_008DFC_SQ_EXP_POS
+ 2 + reg_index
);
2232 args
[4] = uint
->zero
;
2236 static void si_dump_streamout(struct pipe_stream_output_info
*so
)
2240 if (so
->num_outputs
)
2241 fprintf(stderr
, "STREAMOUT\n");
2243 for (i
= 0; i
< so
->num_outputs
; i
++) {
2244 unsigned mask
= ((1 << so
->output
[i
].num_components
) - 1) <<
2245 so
->output
[i
].start_component
;
2246 fprintf(stderr
, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2247 i
, so
->output
[i
].output_buffer
,
2248 so
->output
[i
].dst_offset
, so
->output
[i
].dst_offset
+ so
->output
[i
].num_components
- 1,
2249 so
->output
[i
].register_index
,
2250 mask
& 1 ? "x" : "",
2251 mask
& 2 ? "y" : "",
2252 mask
& 4 ? "z" : "",
2253 mask
& 8 ? "w" : "");
2257 /* On SI, the vertex shader is responsible for writing streamout data
2259 static void si_llvm_emit_streamout(struct si_shader_context
*ctx
,
2260 struct si_shader_output_values
*outputs
,
2263 struct pipe_stream_output_info
*so
= &ctx
->shader
->selector
->so
;
2264 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
2265 LLVMBuilderRef builder
= gallivm
->builder
;
2267 struct lp_build_if_state if_ctx
;
2269 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2270 LLVMValueRef so_vtx_count
=
2271 unpack_param(ctx
, ctx
->param_streamout_config
, 16, 7);
2273 LLVMValueRef tid
= get_thread_id(ctx
);
2275 /* can_emit = tid < so_vtx_count; */
2276 LLVMValueRef can_emit
=
2277 LLVMBuildICmp(builder
, LLVMIntULT
, tid
, so_vtx_count
, "");
2279 LLVMValueRef stream_id
=
2280 unpack_param(ctx
, ctx
->param_streamout_config
, 24, 2);
2282 /* Emit the streamout code conditionally. This actually avoids
2283 * out-of-bounds buffer access. The hw tells us via the SGPR
2284 * (so_vtx_count) which threads are allowed to emit streamout data. */
2285 lp_build_if(&if_ctx
, gallivm
, can_emit
);
2287 /* The buffer offset is computed as follows:
2288 * ByteOffset = streamout_offset[buffer_id]*4 +
2289 * (streamout_write_index + thread_id)*stride[buffer_id] +
2293 LLVMValueRef so_write_index
=
2294 LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2295 ctx
->param_streamout_write_index
);
2297 /* Compute (streamout_write_index + thread_id). */
2298 so_write_index
= LLVMBuildAdd(builder
, so_write_index
, tid
, "");
2300 /* Compute the write offset for each enabled buffer. */
2301 LLVMValueRef so_write_offset
[4] = {};
2302 for (i
= 0; i
< 4; i
++) {
2306 LLVMValueRef so_offset
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2307 ctx
->param_streamout_offset
[i
]);
2308 so_offset
= LLVMBuildMul(builder
, so_offset
, LLVMConstInt(ctx
->i32
, 4, 0), "");
2310 so_write_offset
[i
] = LLVMBuildMul(builder
, so_write_index
,
2311 LLVMConstInt(ctx
->i32
, so
->stride
[i
]*4, 0), "");
2312 so_write_offset
[i
] = LLVMBuildAdd(builder
, so_write_offset
[i
], so_offset
, "");
2315 /* Write streamout data. */
2316 for (i
= 0; i
< so
->num_outputs
; i
++) {
2317 unsigned buf_idx
= so
->output
[i
].output_buffer
;
2318 unsigned reg
= so
->output
[i
].register_index
;
2319 unsigned start
= so
->output
[i
].start_component
;
2320 unsigned num_comps
= so
->output
[i
].num_components
;
2321 unsigned stream
= so
->output
[i
].stream
;
2322 LLVMValueRef out
[4];
2323 struct lp_build_if_state if_ctx_stream
;
2325 assert(num_comps
&& num_comps
<= 4);
2326 if (!num_comps
|| num_comps
> 4)
2332 /* Load the output as int. */
2333 for (j
= 0; j
< num_comps
; j
++) {
2334 out
[j
] = LLVMBuildBitCast(builder
,
2335 outputs
[reg
].values
[start
+j
],
2339 /* Pack the output. */
2340 LLVMValueRef vdata
= NULL
;
2342 switch (num_comps
) {
2343 case 1: /* as i32 */
2346 case 2: /* as v2i32 */
2347 case 3: /* as v4i32 (aligned to 4) */
2348 case 4: /* as v4i32 */
2349 vdata
= LLVMGetUndef(LLVMVectorType(ctx
->i32
, util_next_power_of_two(num_comps
)));
2350 for (j
= 0; j
< num_comps
; j
++) {
2351 vdata
= LLVMBuildInsertElement(builder
, vdata
, out
[j
],
2352 LLVMConstInt(ctx
->i32
, j
, 0), "");
2357 LLVMValueRef can_emit_stream
=
2358 LLVMBuildICmp(builder
, LLVMIntEQ
,
2360 lp_build_const_int32(gallivm
, stream
), "");
2362 lp_build_if(&if_ctx_stream
, gallivm
, can_emit_stream
);
2363 build_tbuffer_store_dwords(ctx
, ctx
->so_buffers
[buf_idx
],
2365 so_write_offset
[buf_idx
],
2366 LLVMConstInt(ctx
->i32
, 0, 0),
2367 so
->output
[i
].dst_offset
*4);
2368 lp_build_endif(&if_ctx_stream
);
2371 lp_build_endif(&if_ctx
);
2375 /* Generate export instructions for hardware VS shader stage */
2376 static void si_llvm_export_vs(struct lp_build_tgsi_context
*bld_base
,
2377 struct si_shader_output_values
*outputs
,
2380 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2381 struct si_shader
*shader
= ctx
->shader
;
2382 struct lp_build_context
*base
= &bld_base
->base
;
2383 struct lp_build_context
*uint
=
2384 &ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
2385 LLVMValueRef args
[9];
2386 LLVMValueRef pos_args
[4][9] = { { 0 } };
2387 LLVMValueRef psize_value
= NULL
, edgeflag_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
2388 unsigned semantic_name
, semantic_index
;
2390 unsigned param_count
= 0;
2394 if (outputs
&& ctx
->shader
->selector
->so
.num_outputs
) {
2395 si_llvm_emit_streamout(ctx
, outputs
, noutput
);
2398 for (i
= 0; i
< noutput
; i
++) {
2399 semantic_name
= outputs
[i
].name
;
2400 semantic_index
= outputs
[i
].sid
;
2403 /* Select the correct target */
2404 switch(semantic_name
) {
2405 case TGSI_SEMANTIC_PSIZE
:
2406 psize_value
= outputs
[i
].values
[0];
2408 case TGSI_SEMANTIC_EDGEFLAG
:
2409 edgeflag_value
= outputs
[i
].values
[0];
2411 case TGSI_SEMANTIC_LAYER
:
2412 layer_value
= outputs
[i
].values
[0];
2413 semantic_name
= TGSI_SEMANTIC_GENERIC
;
2414 goto handle_semantic
;
2415 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
2416 viewport_index_value
= outputs
[i
].values
[0];
2417 semantic_name
= TGSI_SEMANTIC_GENERIC
;
2418 goto handle_semantic
;
2419 case TGSI_SEMANTIC_POSITION
:
2420 target
= V_008DFC_SQ_EXP_POS
;
2422 case TGSI_SEMANTIC_COLOR
:
2423 case TGSI_SEMANTIC_BCOLOR
:
2424 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
2425 assert(i
< ARRAY_SIZE(shader
->info
.vs_output_param_offset
));
2426 shader
->info
.vs_output_param_offset
[i
] = param_count
;
2429 case TGSI_SEMANTIC_CLIPDIST
:
2430 target
= V_008DFC_SQ_EXP_POS
+ 2 + semantic_index
;
2432 case TGSI_SEMANTIC_CLIPVERTEX
:
2433 si_llvm_emit_clipvertex(bld_base
, pos_args
, outputs
[i
].values
);
2435 case TGSI_SEMANTIC_PRIMID
:
2436 case TGSI_SEMANTIC_FOG
:
2437 case TGSI_SEMANTIC_TEXCOORD
:
2438 case TGSI_SEMANTIC_GENERIC
:
2439 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
2440 assert(i
< ARRAY_SIZE(shader
->info
.vs_output_param_offset
));
2441 shader
->info
.vs_output_param_offset
[i
] = param_count
;
2447 "Warning: SI unhandled vs output type:%d\n",
2451 si_llvm_init_export_args(bld_base
, outputs
[i
].values
, target
, args
);
2453 if (target
>= V_008DFC_SQ_EXP_POS
&&
2454 target
<= (V_008DFC_SQ_EXP_POS
+ 3)) {
2455 memcpy(pos_args
[target
- V_008DFC_SQ_EXP_POS
],
2456 args
, sizeof(args
));
2458 lp_build_intrinsic(base
->gallivm
->builder
,
2459 "llvm.SI.export", ctx
->voidt
,
2463 if (semantic_name
== TGSI_SEMANTIC_CLIPDIST
) {
2464 semantic_name
= TGSI_SEMANTIC_GENERIC
;
2465 goto handle_semantic
;
2469 shader
->info
.nr_param_exports
= param_count
;
2471 /* We need to add the position output manually if it's missing. */
2472 if (!pos_args
[0][0]) {
2473 pos_args
[0][0] = lp_build_const_int32(base
->gallivm
, 0xf); /* writemask */
2474 pos_args
[0][1] = uint
->zero
; /* EXEC mask */
2475 pos_args
[0][2] = uint
->zero
; /* last export? */
2476 pos_args
[0][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
);
2477 pos_args
[0][4] = uint
->zero
; /* COMPR flag */
2478 pos_args
[0][5] = base
->zero
; /* X */
2479 pos_args
[0][6] = base
->zero
; /* Y */
2480 pos_args
[0][7] = base
->zero
; /* Z */
2481 pos_args
[0][8] = base
->one
; /* W */
2484 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2485 if (shader
->selector
->info
.writes_psize
||
2486 shader
->selector
->info
.writes_edgeflag
||
2487 shader
->selector
->info
.writes_viewport_index
||
2488 shader
->selector
->info
.writes_layer
) {
2489 pos_args
[1][0] = lp_build_const_int32(base
->gallivm
, /* writemask */
2490 shader
->selector
->info
.writes_psize
|
2491 (shader
->selector
->info
.writes_edgeflag
<< 1) |
2492 (shader
->selector
->info
.writes_layer
<< 2) |
2493 (shader
->selector
->info
.writes_viewport_index
<< 3));
2494 pos_args
[1][1] = uint
->zero
; /* EXEC mask */
2495 pos_args
[1][2] = uint
->zero
; /* last export? */
2496 pos_args
[1][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
+ 1);
2497 pos_args
[1][4] = uint
->zero
; /* COMPR flag */
2498 pos_args
[1][5] = base
->zero
; /* X */
2499 pos_args
[1][6] = base
->zero
; /* Y */
2500 pos_args
[1][7] = base
->zero
; /* Z */
2501 pos_args
[1][8] = base
->zero
; /* W */
2503 if (shader
->selector
->info
.writes_psize
)
2504 pos_args
[1][5] = psize_value
;
2506 if (shader
->selector
->info
.writes_edgeflag
) {
2507 /* The output is a float, but the hw expects an integer
2508 * with the first bit containing the edge flag. */
2509 edgeflag_value
= LLVMBuildFPToUI(base
->gallivm
->builder
,
2512 edgeflag_value
= lp_build_min(&bld_base
->int_bld
,
2514 bld_base
->int_bld
.one
);
2516 /* The LLVM intrinsic expects a float. */
2517 pos_args
[1][6] = LLVMBuildBitCast(base
->gallivm
->builder
,
2522 if (shader
->selector
->info
.writes_layer
)
2523 pos_args
[1][7] = layer_value
;
2525 if (shader
->selector
->info
.writes_viewport_index
)
2526 pos_args
[1][8] = viewport_index_value
;
2529 for (i
= 0; i
< 4; i
++)
2531 shader
->info
.nr_pos_exports
++;
2534 for (i
= 0; i
< 4; i
++) {
2535 if (!pos_args
[i
][0])
2538 /* Specify the target we are exporting */
2539 pos_args
[i
][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
+ pos_idx
++);
2541 if (pos_idx
== shader
->info
.nr_pos_exports
)
2542 /* Specify that this is the last export */
2543 pos_args
[i
][2] = uint
->one
;
2545 lp_build_intrinsic(base
->gallivm
->builder
, "llvm.SI.export",
2546 ctx
->voidt
, pos_args
[i
], 9, 0);
2550 static void si_copy_tcs_inputs(struct lp_build_tgsi_context
*bld_base
)
2552 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2553 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2554 LLVMValueRef invocation_id
, rw_buffers
, buffer
, buffer_offset
;
2555 LLVMValueRef lds_vertex_stride
, lds_vertex_offset
, lds_base
;
2558 invocation_id
= unpack_param(ctx
, SI_PARAM_REL_IDS
, 8, 5);
2560 rw_buffers
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_RW_BUFFERS
);
2561 buffer
= build_indexed_load_const(ctx
, rw_buffers
,
2562 lp_build_const_int32(gallivm
, SI_HS_RING_TESS_OFFCHIP
));
2564 buffer_offset
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, ctx
->param_oc_lds
);
2566 lds_vertex_stride
= unpack_param(ctx
, SI_PARAM_TCS_IN_LAYOUT
, 13, 8);
2567 lds_vertex_offset
= LLVMBuildMul(gallivm
->builder
, invocation_id
,
2568 lds_vertex_stride
, "");
2569 lds_base
= get_tcs_in_current_patch_offset(ctx
);
2570 lds_base
= LLVMBuildAdd(gallivm
->builder
, lds_base
, lds_vertex_offset
, "");
2572 inputs
= ctx
->shader
->key
.tcs
.epilog
.inputs_to_copy
;
2574 unsigned i
= u_bit_scan64(&inputs
);
2576 LLVMValueRef lds_ptr
= LLVMBuildAdd(gallivm
->builder
, lds_base
,
2577 lp_build_const_int32(gallivm
, 4 * i
),
2580 LLVMValueRef buffer_addr
= get_tcs_tes_buffer_address(ctx
,
2582 lp_build_const_int32(gallivm
, i
));
2584 LLVMValueRef value
= lds_load(bld_base
, TGSI_TYPE_SIGNED
, ~0,
2587 build_tbuffer_store_dwords(ctx
, buffer
, value
, 4, buffer_addr
,
2592 static void si_write_tess_factors(struct lp_build_tgsi_context
*bld_base
,
2593 LLVMValueRef rel_patch_id
,
2594 LLVMValueRef invocation_id
,
2595 LLVMValueRef tcs_out_current_patch_data_offset
)
2597 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2598 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2599 struct si_shader
*shader
= ctx
->shader
;
2600 unsigned tess_inner_index
, tess_outer_index
;
2601 LLVMValueRef lds_base
, lds_inner
, lds_outer
, byteoffset
, buffer
;
2602 LLVMValueRef out
[6], vec0
, vec1
, rw_buffers
, tf_base
;
2603 unsigned stride
, outer_comps
, inner_comps
, i
;
2604 struct lp_build_if_state if_ctx
, inner_if_ctx
;
2606 si_llvm_emit_barrier(NULL
, bld_base
, NULL
);
2608 /* Do this only for invocation 0, because the tess levels are per-patch,
2611 * This can't jump, because invocation 0 executes this. It should
2612 * at least mask out the loads and stores for other invocations.
2614 lp_build_if(&if_ctx
, gallivm
,
2615 LLVMBuildICmp(gallivm
->builder
, LLVMIntEQ
,
2616 invocation_id
, bld_base
->uint_bld
.zero
, ""));
2618 /* Determine the layout of one tess factor element in the buffer. */
2619 switch (shader
->key
.tcs
.epilog
.prim_mode
) {
2620 case PIPE_PRIM_LINES
:
2621 stride
= 2; /* 2 dwords, 1 vec2 store */
2625 case PIPE_PRIM_TRIANGLES
:
2626 stride
= 4; /* 4 dwords, 1 vec4 store */
2630 case PIPE_PRIM_QUADS
:
2631 stride
= 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2640 /* Load tess_inner and tess_outer from LDS.
2641 * Any invocation can write them, so we can't get them from a temporary.
2643 tess_inner_index
= si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER
, 0);
2644 tess_outer_index
= si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER
, 0);
2646 lds_base
= tcs_out_current_patch_data_offset
;
2647 lds_inner
= LLVMBuildAdd(gallivm
->builder
, lds_base
,
2648 lp_build_const_int32(gallivm
,
2649 tess_inner_index
* 4), "");
2650 lds_outer
= LLVMBuildAdd(gallivm
->builder
, lds_base
,
2651 lp_build_const_int32(gallivm
,
2652 tess_outer_index
* 4), "");
2654 for (i
= 0; i
< outer_comps
; i
++)
2655 out
[i
] = lds_load(bld_base
, TGSI_TYPE_SIGNED
, i
, lds_outer
);
2656 for (i
= 0; i
< inner_comps
; i
++)
2657 out
[outer_comps
+i
] = lds_load(bld_base
, TGSI_TYPE_SIGNED
, i
, lds_inner
);
2659 /* Convert the outputs to vectors for stores. */
2660 vec0
= lp_build_gather_values(gallivm
, out
, MIN2(stride
, 4));
2664 vec1
= lp_build_gather_values(gallivm
, out
+4, stride
- 4);
2666 /* Get the buffer. */
2667 rw_buffers
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2668 SI_PARAM_RW_BUFFERS
);
2669 buffer
= build_indexed_load_const(ctx
, rw_buffers
,
2670 lp_build_const_int32(gallivm
, SI_HS_RING_TESS_FACTOR
));
2672 /* Get the offset. */
2673 tf_base
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2674 SI_PARAM_TESS_FACTOR_OFFSET
);
2675 byteoffset
= LLVMBuildMul(gallivm
->builder
, rel_patch_id
,
2676 lp_build_const_int32(gallivm
, 4 * stride
), "");
2678 lp_build_if(&inner_if_ctx
, gallivm
,
2679 LLVMBuildICmp(gallivm
->builder
, LLVMIntEQ
,
2680 rel_patch_id
, bld_base
->uint_bld
.zero
, ""));
2682 /* Store the dynamic HS control word. */
2683 build_tbuffer_store_dwords(ctx
, buffer
,
2684 lp_build_const_int32(gallivm
, 0x80000000),
2685 1, lp_build_const_int32(gallivm
, 0), tf_base
, 0);
2687 lp_build_endif(&inner_if_ctx
);
2689 /* Store the tessellation factors. */
2690 build_tbuffer_store_dwords(ctx
, buffer
, vec0
,
2691 MIN2(stride
, 4), byteoffset
, tf_base
, 4);
2693 build_tbuffer_store_dwords(ctx
, buffer
, vec1
,
2694 stride
- 4, byteoffset
, tf_base
, 20);
2695 lp_build_endif(&if_ctx
);
2698 /* This only writes the tessellation factor levels. */
2699 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context
*bld_base
)
2701 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2702 LLVMValueRef rel_patch_id
, invocation_id
, tf_lds_offset
;
2704 rel_patch_id
= get_rel_patch_id(ctx
);
2705 invocation_id
= unpack_param(ctx
, SI_PARAM_REL_IDS
, 8, 5);
2706 tf_lds_offset
= get_tcs_out_current_patch_data_offset(ctx
);
2708 if (!ctx
->is_monolithic
) {
2709 /* Return epilog parameters from this function. */
2710 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
2711 LLVMValueRef ret
= ctx
->return_value
;
2712 LLVMValueRef rw_buffers
, rw0
, rw1
, tf_soffset
;
2715 /* RW_BUFFERS pointer */
2716 rw_buffers
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2717 SI_PARAM_RW_BUFFERS
);
2718 rw_buffers
= LLVMBuildPtrToInt(builder
, rw_buffers
, ctx
->i64
, "");
2719 rw_buffers
= LLVMBuildBitCast(builder
, rw_buffers
, ctx
->v2i32
, "");
2720 rw0
= LLVMBuildExtractElement(builder
, rw_buffers
,
2721 bld_base
->uint_bld
.zero
, "");
2722 rw1
= LLVMBuildExtractElement(builder
, rw_buffers
,
2723 bld_base
->uint_bld
.one
, "");
2724 ret
= LLVMBuildInsertValue(builder
, ret
, rw0
, 0, "");
2725 ret
= LLVMBuildInsertValue(builder
, ret
, rw1
, 1, "");
2727 /* Tess factor buffer soffset is after user SGPRs. */
2728 tf_soffset
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2729 SI_PARAM_TESS_FACTOR_OFFSET
);
2730 ret
= LLVMBuildInsertValue(builder
, ret
, tf_soffset
,
2731 SI_TCS_NUM_USER_SGPR
+ 1, "");
2734 rel_patch_id
= bitcast(bld_base
, TGSI_TYPE_FLOAT
, rel_patch_id
);
2735 invocation_id
= bitcast(bld_base
, TGSI_TYPE_FLOAT
, invocation_id
);
2736 tf_lds_offset
= bitcast(bld_base
, TGSI_TYPE_FLOAT
, tf_lds_offset
);
2738 vgpr
= SI_TCS_NUM_USER_SGPR
+ 2;
2739 ret
= LLVMBuildInsertValue(builder
, ret
, rel_patch_id
, vgpr
++, "");
2740 ret
= LLVMBuildInsertValue(builder
, ret
, invocation_id
, vgpr
++, "");
2741 ret
= LLVMBuildInsertValue(builder
, ret
, tf_lds_offset
, vgpr
++, "");
2742 ctx
->return_value
= ret
;
2746 si_copy_tcs_inputs(bld_base
);
2747 si_write_tess_factors(bld_base
, rel_patch_id
, invocation_id
, tf_lds_offset
);
2750 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context
*bld_base
)
2752 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2753 struct si_shader
*shader
= ctx
->shader
;
2754 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
2755 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2757 LLVMValueRef vertex_id
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2758 ctx
->param_rel_auto_id
);
2759 LLVMValueRef vertex_dw_stride
=
2760 unpack_param(ctx
, SI_PARAM_LS_OUT_LAYOUT
, 13, 8);
2761 LLVMValueRef base_dw_addr
= LLVMBuildMul(gallivm
->builder
, vertex_id
,
2762 vertex_dw_stride
, "");
2764 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2765 * its inputs from it. */
2766 for (i
= 0; i
< info
->num_outputs
; i
++) {
2767 LLVMValueRef
*out_ptr
= ctx
->radeon_bld
.soa
.outputs
[i
];
2768 unsigned name
= info
->output_semantic_name
[i
];
2769 unsigned index
= info
->output_semantic_index
[i
];
2770 int param
= si_shader_io_get_unique_index(name
, index
);
2771 LLVMValueRef dw_addr
= LLVMBuildAdd(gallivm
->builder
, base_dw_addr
,
2772 lp_build_const_int32(gallivm
, param
* 4), "");
2774 for (chan
= 0; chan
< 4; chan
++) {
2775 lds_store(bld_base
, chan
, dw_addr
,
2776 LLVMBuildLoad(gallivm
->builder
, out_ptr
[chan
], ""));
2781 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context
*bld_base
)
2783 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2784 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2785 struct si_shader
*es
= ctx
->shader
;
2786 struct tgsi_shader_info
*info
= &es
->selector
->info
;
2787 LLVMValueRef soffset
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2788 ctx
->param_es2gs_offset
);
2792 for (i
= 0; i
< info
->num_outputs
; i
++) {
2793 LLVMValueRef
*out_ptr
=
2794 ctx
->radeon_bld
.soa
.outputs
[i
];
2797 if (info
->output_semantic_name
[i
] == TGSI_SEMANTIC_VIEWPORT_INDEX
||
2798 info
->output_semantic_name
[i
] == TGSI_SEMANTIC_LAYER
)
2801 param_index
= si_shader_io_get_unique_index(info
->output_semantic_name
[i
],
2802 info
->output_semantic_index
[i
]);
2804 for (chan
= 0; chan
< 4; chan
++) {
2805 LLVMValueRef out_val
= LLVMBuildLoad(gallivm
->builder
, out_ptr
[chan
], "");
2806 out_val
= LLVMBuildBitCast(gallivm
->builder
, out_val
, ctx
->i32
, "");
2808 build_tbuffer_store(ctx
,
2811 LLVMGetUndef(ctx
->i32
), soffset
,
2812 (4 * param_index
+ chan
) * 4,
2813 V_008F0C_BUF_DATA_FORMAT_32
,
2814 V_008F0C_BUF_NUM_FORMAT_UINT
,
2820 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context
*bld_base
)
2822 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2823 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2824 LLVMValueRef args
[2];
2826 args
[0] = lp_build_const_int32(gallivm
, SENDMSG_GS_OP_NOP
| SENDMSG_GS_DONE
);
2827 args
[1] = LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_GS_WAVE_ID
);
2828 lp_build_intrinsic(gallivm
->builder
, "llvm.SI.sendmsg",
2829 ctx
->voidt
, args
, 2, 0);
2832 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context
*bld_base
)
2834 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2835 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2836 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
2837 struct si_shader_output_values
*outputs
= NULL
;
2840 assert(!ctx
->is_gs_copy_shader
);
2842 outputs
= MALLOC((info
->num_outputs
+ 1) * sizeof(outputs
[0]));
2844 /* Vertex color clamping.
2846 * This uses a state constant loaded in a user data SGPR and
2847 * an IF statement is added that clamps all colors if the constant
2850 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
2851 struct lp_build_if_state if_ctx
;
2852 LLVMValueRef cond
= NULL
;
2853 LLVMValueRef addr
, val
;
2855 for (i
= 0; i
< info
->num_outputs
; i
++) {
2856 if (info
->output_semantic_name
[i
] != TGSI_SEMANTIC_COLOR
&&
2857 info
->output_semantic_name
[i
] != TGSI_SEMANTIC_BCOLOR
)
2860 /* We've found a color. */
2862 /* The state is in the first bit of the user SGPR. */
2863 cond
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2864 SI_PARAM_VS_STATE_BITS
);
2865 cond
= LLVMBuildTrunc(gallivm
->builder
, cond
,
2867 lp_build_if(&if_ctx
, gallivm
, cond
);
2870 for (j
= 0; j
< 4; j
++) {
2871 addr
= ctx
->radeon_bld
.soa
.outputs
[i
][j
];
2872 val
= LLVMBuildLoad(gallivm
->builder
, addr
, "");
2873 val
= radeon_llvm_saturate(bld_base
, val
);
2874 LLVMBuildStore(gallivm
->builder
, val
, addr
);
2879 lp_build_endif(&if_ctx
);
2882 for (i
= 0; i
< info
->num_outputs
; i
++) {
2883 outputs
[i
].name
= info
->output_semantic_name
[i
];
2884 outputs
[i
].sid
= info
->output_semantic_index
[i
];
2886 for (j
= 0; j
< 4; j
++)
2887 outputs
[i
].values
[j
] =
2888 LLVMBuildLoad(gallivm
->builder
,
2889 ctx
->radeon_bld
.soa
.outputs
[i
][j
],
2893 if (ctx
->is_monolithic
) {
2894 /* Export PrimitiveID when PS needs it. */
2895 if (si_vs_exports_prim_id(ctx
->shader
)) {
2896 outputs
[i
].name
= TGSI_SEMANTIC_PRIMID
;
2898 outputs
[i
].values
[0] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2899 get_primitive_id(bld_base
, 0));
2900 outputs
[i
].values
[1] = bld_base
->base
.undef
;
2901 outputs
[i
].values
[2] = bld_base
->base
.undef
;
2902 outputs
[i
].values
[3] = bld_base
->base
.undef
;
2906 /* Return the primitive ID from the LLVM function. */
2908 LLVMBuildInsertValue(gallivm
->builder
,
2910 bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2911 get_primitive_id(bld_base
, 0)),
2912 VS_EPILOG_PRIMID_LOC
, "");
2915 si_llvm_export_vs(bld_base
, outputs
, i
);
2919 static void si_export_mrt_z(struct lp_build_tgsi_context
*bld_base
,
2920 LLVMValueRef depth
, LLVMValueRef stencil
,
2921 LLVMValueRef samplemask
)
2923 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2924 struct lp_build_context
*base
= &bld_base
->base
;
2925 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
2926 LLVMValueRef args
[9];
2929 assert(depth
|| stencil
|| samplemask
);
2931 args
[1] = uint
->one
; /* whether the EXEC mask is valid */
2932 args
[2] = uint
->one
; /* DONE bit */
2934 /* Specify the target we are exporting */
2935 args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_MRTZ
);
2937 args
[4] = uint
->zero
; /* COMP flag */
2938 args
[5] = base
->undef
; /* R, depth */
2939 args
[6] = base
->undef
; /* G, stencil test value[0:7], stencil op value[8:15] */
2940 args
[7] = base
->undef
; /* B, sample mask */
2941 args
[8] = base
->undef
; /* A, alpha to mask */
2954 args
[7] = samplemask
;
2958 /* SI (except OLAND) has a bug that it only looks
2959 * at the X writemask component. */
2960 if (ctx
->screen
->b
.chip_class
== SI
&&
2961 ctx
->screen
->b
.family
!= CHIP_OLAND
)
2964 /* Specify which components to enable */
2965 args
[0] = lp_build_const_int32(base
->gallivm
, mask
);
2967 lp_build_intrinsic(base
->gallivm
->builder
, "llvm.SI.export",
2968 ctx
->voidt
, args
, 9, 0);
2971 static void si_export_mrt_color(struct lp_build_tgsi_context
*bld_base
,
2972 LLVMValueRef
*color
, unsigned index
,
2973 unsigned samplemask_param
,
2976 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2977 struct lp_build_context
*base
= &bld_base
->base
;
2981 if (ctx
->shader
->key
.ps
.epilog
.clamp_color
)
2982 for (i
= 0; i
< 4; i
++)
2983 color
[i
] = radeon_llvm_saturate(bld_base
, color
[i
]);
2986 if (ctx
->shader
->key
.ps
.epilog
.alpha_to_one
)
2987 color
[3] = base
->one
;
2991 ctx
->shader
->key
.ps
.epilog
.alpha_func
!= PIPE_FUNC_ALWAYS
)
2992 si_alpha_test(bld_base
, color
[3]);
2994 /* Line & polygon smoothing */
2995 if (ctx
->shader
->key
.ps
.epilog
.poly_line_smoothing
)
2996 color
[3] = si_scale_alpha_by_sample_mask(bld_base
, color
[3],
2999 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3000 if (ctx
->shader
->key
.ps
.epilog
.last_cbuf
> 0) {
3001 LLVMValueRef args
[8][9];
3004 /* Get the export arguments, also find out what the last one is. */
3005 for (c
= 0; c
<= ctx
->shader
->key
.ps
.epilog
.last_cbuf
; c
++) {
3006 si_llvm_init_export_args(bld_base
, color
,
3007 V_008DFC_SQ_EXP_MRT
+ c
, args
[c
]);
3008 if (args
[c
][0] != bld_base
->uint_bld
.zero
)
3012 /* Emit all exports. */
3013 for (c
= 0; c
<= ctx
->shader
->key
.ps
.epilog
.last_cbuf
; c
++) {
3014 if (is_last
&& last
== c
) {
3015 args
[c
][1] = bld_base
->uint_bld
.one
; /* whether the EXEC mask is valid */
3016 args
[c
][2] = bld_base
->uint_bld
.one
; /* DONE bit */
3017 } else if (args
[c
][0] == bld_base
->uint_bld
.zero
)
3018 continue; /* unnecessary NULL export */
3020 lp_build_intrinsic(base
->gallivm
->builder
, "llvm.SI.export",
3021 ctx
->voidt
, args
[c
], 9, 0);
3024 LLVMValueRef args
[9];
3027 si_llvm_init_export_args(bld_base
, color
, V_008DFC_SQ_EXP_MRT
+ index
,
3030 args
[1] = bld_base
->uint_bld
.one
; /* whether the EXEC mask is valid */
3031 args
[2] = bld_base
->uint_bld
.one
; /* DONE bit */
3032 } else if (args
[0] == bld_base
->uint_bld
.zero
)
3033 return; /* unnecessary NULL export */
3035 lp_build_intrinsic(base
->gallivm
->builder
, "llvm.SI.export",
3036 ctx
->voidt
, args
, 9, 0);
3040 static void si_export_null(struct lp_build_tgsi_context
*bld_base
)
3042 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3043 struct lp_build_context
*base
= &bld_base
->base
;
3044 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
3045 LLVMValueRef args
[9];
3047 args
[0] = lp_build_const_int32(base
->gallivm
, 0x0); /* enabled channels */
3048 args
[1] = uint
->one
; /* whether the EXEC mask is valid */
3049 args
[2] = uint
->one
; /* DONE bit */
3050 args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_NULL
);
3051 args
[4] = uint
->zero
; /* COMPR flag (0 = 32-bit export) */
3052 args
[5] = uint
->undef
; /* R */
3053 args
[6] = uint
->undef
; /* G */
3054 args
[7] = uint
->undef
; /* B */
3055 args
[8] = uint
->undef
; /* A */
3057 lp_build_intrinsic(base
->gallivm
->builder
, "llvm.SI.export",
3058 ctx
->voidt
, args
, 9, 0);
3061 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context
*bld_base
)
3063 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3064 struct si_shader
*shader
= ctx
->shader
;
3065 struct lp_build_context
*base
= &bld_base
->base
;
3066 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
3067 LLVMBuilderRef builder
= base
->gallivm
->builder
;
3068 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3069 int last_color_export
= -1;
3072 /* Determine the last export. If MRTZ is present, it's always last.
3073 * Otherwise, find the last color export.
3075 if (!info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
) {
3076 unsigned spi_format
= shader
->key
.ps
.epilog
.spi_shader_col_format
;
3078 /* Don't export NULL and return if alpha-test is enabled. */
3079 if (shader
->key
.ps
.epilog
.alpha_func
!= PIPE_FUNC_ALWAYS
&&
3080 shader
->key
.ps
.epilog
.alpha_func
!= PIPE_FUNC_NEVER
&&
3081 (spi_format
& 0xf) == 0)
3082 spi_format
|= V_028714_SPI_SHADER_32_AR
;
3084 for (i
= 0; i
< info
->num_outputs
; i
++) {
3085 unsigned index
= info
->output_semantic_index
[i
];
3087 if (info
->output_semantic_name
[i
] != TGSI_SEMANTIC_COLOR
)
3090 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3091 if (shader
->key
.ps
.epilog
.last_cbuf
> 0) {
3092 /* Just set this if any of the colorbuffers are enabled. */
3094 ((1llu << (4 * (shader
->key
.ps
.epilog
.last_cbuf
+ 1))) - 1))
3095 last_color_export
= i
;
3099 if ((spi_format
>> (index
* 4)) & 0xf)
3100 last_color_export
= i
;
3103 /* If there are no outputs, export NULL. */
3104 if (last_color_export
== -1) {
3105 si_export_null(bld_base
);
3110 for (i
= 0; i
< info
->num_outputs
; i
++) {
3111 unsigned semantic_name
= info
->output_semantic_name
[i
];
3112 unsigned semantic_index
= info
->output_semantic_index
[i
];
3114 LLVMValueRef color
[4] = {};
3116 /* Select the correct target */
3117 switch (semantic_name
) {
3118 case TGSI_SEMANTIC_POSITION
:
3119 depth
= LLVMBuildLoad(builder
,
3120 ctx
->radeon_bld
.soa
.outputs
[i
][2], "");
3122 case TGSI_SEMANTIC_STENCIL
:
3123 stencil
= LLVMBuildLoad(builder
,
3124 ctx
->radeon_bld
.soa
.outputs
[i
][1], "");
3126 case TGSI_SEMANTIC_SAMPLEMASK
:
3127 samplemask
= LLVMBuildLoad(builder
,
3128 ctx
->radeon_bld
.soa
.outputs
[i
][0], "");
3130 case TGSI_SEMANTIC_COLOR
:
3131 for (j
= 0; j
< 4; j
++)
3132 color
[j
] = LLVMBuildLoad(builder
,
3133 ctx
->radeon_bld
.soa
.outputs
[i
][j
], "");
3135 si_export_mrt_color(bld_base
, color
, semantic_index
,
3136 SI_PARAM_SAMPLE_COVERAGE
,
3137 last_color_export
== i
);
3141 "Warning: SI unhandled fs output type:%d\n",
3146 if (depth
|| stencil
|| samplemask
)
3147 si_export_mrt_z(bld_base
, depth
, stencil
, samplemask
);
3151 * Return PS outputs in this order:
3153 * v[0:3] = color0.xyzw
3154 * v[4:7] = color1.xyzw
3159 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3161 * The alpha-ref SGPR is returned via its original location.
3163 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context
*bld_base
)
3165 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3166 struct si_shader
*shader
= ctx
->shader
;
3167 struct lp_build_context
*base
= &bld_base
->base
;
3168 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
3169 LLVMBuilderRef builder
= base
->gallivm
->builder
;
3170 unsigned i
, j
, first_vgpr
, vgpr
;
3172 LLVMValueRef color
[8][4] = {};
3173 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3176 /* Read the output values. */
3177 for (i
= 0; i
< info
->num_outputs
; i
++) {
3178 unsigned semantic_name
= info
->output_semantic_name
[i
];
3179 unsigned semantic_index
= info
->output_semantic_index
[i
];
3181 switch (semantic_name
) {
3182 case TGSI_SEMANTIC_COLOR
:
3183 assert(semantic_index
< 8);
3184 for (j
= 0; j
< 4; j
++) {
3185 LLVMValueRef ptr
= ctx
->radeon_bld
.soa
.outputs
[i
][j
];
3186 LLVMValueRef result
= LLVMBuildLoad(builder
, ptr
, "");
3187 color
[semantic_index
][j
] = result
;
3190 case TGSI_SEMANTIC_POSITION
:
3191 depth
= LLVMBuildLoad(builder
,
3192 ctx
->radeon_bld
.soa
.outputs
[i
][2], "");
3194 case TGSI_SEMANTIC_STENCIL
:
3195 stencil
= LLVMBuildLoad(builder
,
3196 ctx
->radeon_bld
.soa
.outputs
[i
][1], "");
3198 case TGSI_SEMANTIC_SAMPLEMASK
:
3199 samplemask
= LLVMBuildLoad(builder
,
3200 ctx
->radeon_bld
.soa
.outputs
[i
][0], "");
3203 fprintf(stderr
, "Warning: SI unhandled fs output type:%d\n",
3208 /* Fill the return structure. */
3209 ret
= ctx
->return_value
;
3212 ret
= LLVMBuildInsertValue(builder
, ret
,
3213 bitcast(bld_base
, TGSI_TYPE_SIGNED
,
3214 LLVMGetParam(ctx
->radeon_bld
.main_fn
,
3215 SI_PARAM_ALPHA_REF
)),
3216 SI_SGPR_ALPHA_REF
, "");
3219 first_vgpr
= vgpr
= SI_SGPR_ALPHA_REF
+ 1;
3220 for (i
= 0; i
< ARRAY_SIZE(color
); i
++) {
3224 for (j
= 0; j
< 4; j
++)
3225 ret
= LLVMBuildInsertValue(builder
, ret
, color
[i
][j
], vgpr
++, "");
3228 ret
= LLVMBuildInsertValue(builder
, ret
, depth
, vgpr
++, "");
3230 ret
= LLVMBuildInsertValue(builder
, ret
, stencil
, vgpr
++, "");
3232 ret
= LLVMBuildInsertValue(builder
, ret
, samplemask
, vgpr
++, "");
3234 /* Add the input sample mask for smoothing at the end. */
3235 if (vgpr
< first_vgpr
+ PS_EPILOG_SAMPLEMASK_MIN_LOC
)
3236 vgpr
= first_vgpr
+ PS_EPILOG_SAMPLEMASK_MIN_LOC
;
3237 ret
= LLVMBuildInsertValue(builder
, ret
,
3238 LLVMGetParam(ctx
->radeon_bld
.main_fn
,
3239 SI_PARAM_SAMPLE_COVERAGE
), vgpr
++, "");
3241 ctx
->return_value
= ret
;
3245 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3246 * buffer in number of elements and return it as an i32.
3248 static LLVMValueRef
get_buffer_size(
3249 struct lp_build_tgsi_context
*bld_base
,
3250 LLVMValueRef descriptor
)
3252 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3253 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3254 LLVMBuilderRef builder
= gallivm
->builder
;
3256 LLVMBuildExtractElement(builder
, descriptor
,
3257 lp_build_const_int32(gallivm
, 6), "");
3259 if (ctx
->screen
->b
.chip_class
>= VI
) {
3260 /* On VI, the descriptor contains the size in bytes,
3261 * but TXQ must return the size in elements.
3262 * The stride is always non-zero for resources using TXQ.
3264 LLVMValueRef stride
=
3265 LLVMBuildExtractElement(builder
, descriptor
,
3266 lp_build_const_int32(gallivm
, 5), "");
3267 stride
= LLVMBuildLShr(builder
, stride
,
3268 lp_build_const_int32(gallivm
, 16), "");
3269 stride
= LLVMBuildAnd(builder
, stride
,
3270 lp_build_const_int32(gallivm
, 0x3FFF), "");
3272 size
= LLVMBuildUDiv(builder
, size
, stride
, "");
3279 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
3282 static void build_int_type_name(
3284 char *buf
, unsigned bufsize
)
3286 assert(bufsize
>= 6);
3288 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
3289 snprintf(buf
, bufsize
, "v%ui32",
3290 LLVMGetVectorSize(type
));
3295 static void build_tex_intrinsic(const struct lp_build_tgsi_action
*action
,
3296 struct lp_build_tgsi_context
*bld_base
,
3297 struct lp_build_emit_data
*emit_data
);
3299 /* Prevent optimizations (at least of memory accesses) across the current
3300 * point in the program by emitting empty inline assembly that is marked as
3301 * having side effects.
3303 static void emit_optimization_barrier(struct si_shader_context
*ctx
)
3305 LLVMBuilderRef builder
= ctx
->radeon_bld
.gallivm
.builder
;
3306 LLVMTypeRef ftype
= LLVMFunctionType(ctx
->voidt
, NULL
, 0, false);
3307 LLVMValueRef inlineasm
= LLVMConstInlineAsm(ftype
, "", "", true, false);
3308 LLVMBuildCall(builder
, inlineasm
, NULL
, 0, "");
3311 static void emit_waitcnt(struct si_shader_context
*ctx
)
3313 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3314 LLVMBuilderRef builder
= gallivm
->builder
;
3315 LLVMValueRef args
[1] = {
3316 lp_build_const_int32(gallivm
, 0xf70)
3318 lp_build_intrinsic(builder
, "llvm.amdgcn.s.waitcnt",
3319 ctx
->voidt
, args
, 1, 0);
3322 static void membar_emit(
3323 const struct lp_build_tgsi_action
*action
,
3324 struct lp_build_tgsi_context
*bld_base
,
3325 struct lp_build_emit_data
*emit_data
)
3327 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3333 shader_buffer_fetch_rsrc(struct si_shader_context
*ctx
,
3334 const struct tgsi_full_src_register
*reg
)
3336 LLVMValueRef ind_index
;
3337 LLVMValueRef rsrc_ptr
;
3339 if (!reg
->Register
.Indirect
)
3340 return ctx
->shader_buffers
[reg
->Register
.Index
];
3342 ind_index
= get_bounded_indirect_index(ctx
, ®
->Indirect
,
3343 reg
->Register
.Index
,
3344 SI_NUM_SHADER_BUFFERS
);
3346 rsrc_ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_SHADER_BUFFERS
);
3347 return build_indexed_load_const(ctx
, rsrc_ptr
, ind_index
);
3350 static bool tgsi_is_array_sampler(unsigned target
)
3352 return target
== TGSI_TEXTURE_1D_ARRAY
||
3353 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
3354 target
== TGSI_TEXTURE_2D_ARRAY
||
3355 target
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
3356 target
== TGSI_TEXTURE_CUBE_ARRAY
||
3357 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
||
3358 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
;
3361 static bool tgsi_is_array_image(unsigned target
)
3363 return target
== TGSI_TEXTURE_3D
||
3364 target
== TGSI_TEXTURE_CUBE
||
3365 target
== TGSI_TEXTURE_1D_ARRAY
||
3366 target
== TGSI_TEXTURE_2D_ARRAY
||
3367 target
== TGSI_TEXTURE_CUBE_ARRAY
||
3368 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
;
3372 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3374 * At least on Tonga, executing image stores on images with DCC enabled and
3375 * non-trivial can eventually lead to lockups. This can occur when an
3376 * application binds an image as read-only but then uses a shader that writes
3377 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3378 * program termination) in this case, but it doesn't cost much to be a bit
3379 * nicer: disabling DCC in the shader still leads to undefined results but
3380 * avoids the lockup.
3382 static LLVMValueRef
force_dcc_off(struct si_shader_context
*ctx
,
3385 if (ctx
->screen
->b
.chip_class
<= CIK
) {
3388 LLVMBuilderRef builder
= ctx
->radeon_bld
.gallivm
.builder
;
3389 LLVMValueRef i32_6
= LLVMConstInt(ctx
->i32
, 6, 0);
3390 LLVMValueRef i32_C
= LLVMConstInt(ctx
->i32
, C_008F28_COMPRESSION_EN
, 0);
3393 tmp
= LLVMBuildExtractElement(builder
, rsrc
, i32_6
, "");
3394 tmp
= LLVMBuildAnd(builder
, tmp
, i32_C
, "");
3395 return LLVMBuildInsertElement(builder
, rsrc
, tmp
, i32_6
, "");
3400 * Load the resource descriptor for \p image.
3404 struct lp_build_tgsi_context
*bld_base
,
3405 const struct tgsi_full_src_register
*image
,
3409 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3411 assert(image
->Register
.File
== TGSI_FILE_IMAGE
);
3413 if (!image
->Register
.Indirect
) {
3414 /* Fast path: use preloaded resources */
3415 *rsrc
= ctx
->images
[image
->Register
.Index
];
3417 /* Indexing and manual load */
3418 LLVMValueRef ind_index
;
3419 LLVMValueRef rsrc_ptr
;
3422 /* From the GL_ARB_shader_image_load_store extension spec:
3424 * If a shader performs an image load, store, or atomic
3425 * operation using an image variable declared as an array,
3426 * and if the index used to select an individual element is
3427 * negative or greater than or equal to the size of the
3428 * array, the results of the operation are undefined but may
3429 * not lead to termination.
3431 ind_index
= get_bounded_indirect_index(ctx
, &image
->Indirect
,
3432 image
->Register
.Index
,
3435 rsrc_ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_IMAGES
);
3436 tmp
= build_indexed_load_const(ctx
, rsrc_ptr
, ind_index
);
3438 tmp
= force_dcc_off(ctx
, tmp
);
3443 static LLVMValueRef
image_fetch_coords(
3444 struct lp_build_tgsi_context
*bld_base
,
3445 const struct tgsi_full_instruction
*inst
,
3448 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3449 LLVMBuilderRef builder
= gallivm
->builder
;
3450 unsigned target
= inst
->Memory
.Texture
;
3451 unsigned num_coords
= tgsi_util_get_texture_coord_dim(target
);
3452 LLVMValueRef coords
[4];
3456 for (chan
= 0; chan
< num_coords
; ++chan
) {
3457 tmp
= lp_build_emit_fetch(bld_base
, inst
, src
, chan
);
3458 tmp
= LLVMBuildBitCast(builder
, tmp
, bld_base
->uint_bld
.elem_type
, "");
3462 if (num_coords
== 1)
3465 if (num_coords
== 3) {
3466 /* LLVM has difficulties lowering 3-element vectors. */
3467 coords
[3] = bld_base
->uint_bld
.undef
;
3471 return lp_build_gather_values(gallivm
, coords
, num_coords
);
3475 * Append the extra mode bits that are used by image load and store.
3477 static void image_append_args(
3478 struct si_shader_context
*ctx
,
3479 struct lp_build_emit_data
* emit_data
,
3483 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3484 LLVMValueRef i1false
= LLVMConstInt(ctx
->i1
, 0, 0);
3485 LLVMValueRef i1true
= LLVMConstInt(ctx
->i1
, 1, 0);
3487 emit_data
->args
[emit_data
->arg_count
++] = i1false
; /* r128 */
3488 emit_data
->args
[emit_data
->arg_count
++] =
3489 tgsi_is_array_image(target
) ? i1true
: i1false
; /* da */
3491 emit_data
->args
[emit_data
->arg_count
++] =
3492 inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
) ?
3493 i1true
: i1false
; /* glc */
3495 emit_data
->args
[emit_data
->arg_count
++] = i1false
; /* slc */
3499 * Given a 256 bit resource, extract the top half (which stores the buffer
3500 * resource in the case of textures and images).
3502 static LLVMValueRef
extract_rsrc_top_half(
3503 struct si_shader_context
*ctx
,
3506 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3507 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
3508 LLVMTypeRef v2i128
= LLVMVectorType(ctx
->i128
, 2);
3510 rsrc
= LLVMBuildBitCast(gallivm
->builder
, rsrc
, v2i128
, "");
3511 rsrc
= LLVMBuildExtractElement(gallivm
->builder
, rsrc
, bld_base
->uint_bld
.one
, "");
3512 rsrc
= LLVMBuildBitCast(gallivm
->builder
, rsrc
, ctx
->v4i32
, "");
3518 * Append the resource and indexing arguments for buffer intrinsics.
3520 * \param rsrc the v4i32 buffer resource
3521 * \param index index into the buffer (stride-based)
3522 * \param offset byte offset into the buffer
3524 static void buffer_append_args(
3525 struct si_shader_context
*ctx
,
3526 struct lp_build_emit_data
*emit_data
,
3529 LLVMValueRef offset
,
3532 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3533 LLVMValueRef i1false
= LLVMConstInt(ctx
->i1
, 0, 0);
3534 LLVMValueRef i1true
= LLVMConstInt(ctx
->i1
, 1, 0);
3536 emit_data
->args
[emit_data
->arg_count
++] = rsrc
;
3537 emit_data
->args
[emit_data
->arg_count
++] = index
; /* vindex */
3538 emit_data
->args
[emit_data
->arg_count
++] = offset
; /* voffset */
3540 emit_data
->args
[emit_data
->arg_count
++] =
3541 inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
) ?
3542 i1true
: i1false
; /* glc */
3544 emit_data
->args
[emit_data
->arg_count
++] = i1false
; /* slc */
3547 static void load_fetch_args(
3548 struct lp_build_tgsi_context
* bld_base
,
3549 struct lp_build_emit_data
* emit_data
)
3551 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3552 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3553 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
3554 unsigned target
= inst
->Memory
.Texture
;
3557 emit_data
->dst_type
= LLVMVectorType(bld_base
->base
.elem_type
, 4);
3559 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
3560 LLVMBuilderRef builder
= gallivm
->builder
;
3561 LLVMValueRef offset
;
3564 rsrc
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0]);
3566 tmp
= lp_build_emit_fetch(bld_base
, inst
, 1, 0);
3567 offset
= LLVMBuildBitCast(builder
, tmp
, bld_base
->uint_bld
.elem_type
, "");
3569 buffer_append_args(ctx
, emit_data
, rsrc
, bld_base
->uint_bld
.zero
,
3571 } else if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
) {
3572 LLVMValueRef coords
;
3574 image_fetch_rsrc(bld_base
, &inst
->Src
[0], false, &rsrc
);
3575 coords
= image_fetch_coords(bld_base
, inst
, 1);
3577 if (target
== TGSI_TEXTURE_BUFFER
) {
3578 rsrc
= extract_rsrc_top_half(ctx
, rsrc
);
3579 buffer_append_args(ctx
, emit_data
, rsrc
, coords
,
3580 bld_base
->uint_bld
.zero
, false);
3582 emit_data
->args
[0] = coords
;
3583 emit_data
->args
[1] = rsrc
;
3584 emit_data
->args
[2] = lp_build_const_int32(gallivm
, 15); /* dmask */
3585 emit_data
->arg_count
= 3;
3587 image_append_args(ctx
, emit_data
, target
, false);
3592 static void load_emit_buffer(struct si_shader_context
*ctx
,
3593 struct lp_build_emit_data
*emit_data
)
3595 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3596 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3597 LLVMBuilderRef builder
= gallivm
->builder
;
3598 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
3599 uint count
= util_last_bit(writemask
);
3600 const char *intrinsic_name
;
3601 LLVMTypeRef dst_type
;
3605 intrinsic_name
= "llvm.amdgcn.buffer.load.f32";
3606 dst_type
= ctx
->f32
;
3609 intrinsic_name
= "llvm.amdgcn.buffer.load.v2f32";
3610 dst_type
= LLVMVectorType(ctx
->f32
, 2);
3613 intrinsic_name
= "llvm.amdgcn.buffer.load.v4f32";
3614 dst_type
= ctx
->v4f32
;
3618 emit_data
->output
[emit_data
->chan
] = lp_build_intrinsic(
3619 builder
, intrinsic_name
, dst_type
,
3620 emit_data
->args
, emit_data
->arg_count
,
3621 LLVMReadOnlyAttribute
);
3624 static LLVMValueRef
get_memory_ptr(struct si_shader_context
*ctx
,
3625 const struct tgsi_full_instruction
*inst
,
3626 LLVMTypeRef type
, int arg
)
3628 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3629 LLVMBuilderRef builder
= gallivm
->builder
;
3630 LLVMValueRef offset
, ptr
;
3633 offset
= lp_build_emit_fetch(&ctx
->radeon_bld
.soa
.bld_base
, inst
, arg
, 0);
3634 offset
= LLVMBuildBitCast(builder
, offset
, ctx
->i32
, "");
3636 ptr
= ctx
->shared_memory
;
3637 ptr
= LLVMBuildGEP(builder
, ptr
, &offset
, 1, "");
3638 addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
3639 ptr
= LLVMBuildBitCast(builder
, ptr
, LLVMPointerType(type
, addr_space
), "");
3644 static void load_emit_memory(
3645 struct si_shader_context
*ctx
,
3646 struct lp_build_emit_data
*emit_data
)
3648 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3649 struct lp_build_context
*base
= &ctx
->radeon_bld
.soa
.bld_base
.base
;
3650 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3651 LLVMBuilderRef builder
= gallivm
->builder
;
3652 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
3653 LLVMValueRef channels
[4], ptr
, derived_ptr
, index
;
3656 ptr
= get_memory_ptr(ctx
, inst
, base
->elem_type
, 1);
3658 for (chan
= 0; chan
< 4; ++chan
) {
3659 if (!(writemask
& (1 << chan
))) {
3660 channels
[chan
] = LLVMGetUndef(base
->elem_type
);
3664 index
= lp_build_const_int32(gallivm
, chan
);
3665 derived_ptr
= LLVMBuildGEP(builder
, ptr
, &index
, 1, "");
3666 channels
[chan
] = LLVMBuildLoad(builder
, derived_ptr
, "");
3668 emit_data
->output
[emit_data
->chan
] = lp_build_gather_values(gallivm
, channels
, 4);
3671 static void load_emit(
3672 const struct lp_build_tgsi_action
*action
,
3673 struct lp_build_tgsi_context
*bld_base
,
3674 struct lp_build_emit_data
*emit_data
)
3676 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3677 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3678 LLVMBuilderRef builder
= gallivm
->builder
;
3679 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
3680 char intrinsic_name
[32];
3681 char coords_type
[8];
3683 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
3684 load_emit_memory(ctx
, emit_data
);
3688 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
3691 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
3692 load_emit_buffer(ctx
, emit_data
);
3696 if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
3697 emit_data
->output
[emit_data
->chan
] =
3699 builder
, "llvm.amdgcn.buffer.load.format.v4f32", emit_data
->dst_type
,
3700 emit_data
->args
, emit_data
->arg_count
,
3701 LLVMReadOnlyAttribute
);
3703 build_int_type_name(LLVMTypeOf(emit_data
->args
[0]),
3704 coords_type
, sizeof(coords_type
));
3706 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3707 "llvm.amdgcn.image.load.%s", coords_type
);
3709 emit_data
->output
[emit_data
->chan
] =
3711 builder
, intrinsic_name
, emit_data
->dst_type
,
3712 emit_data
->args
, emit_data
->arg_count
,
3713 LLVMReadOnlyAttribute
);
3717 static void store_fetch_args(
3718 struct lp_build_tgsi_context
* bld_base
,
3719 struct lp_build_emit_data
* emit_data
)
3721 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3722 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3723 LLVMBuilderRef builder
= gallivm
->builder
;
3724 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
3725 struct tgsi_full_src_register memory
;
3726 LLVMValueRef chans
[4];
3731 emit_data
->dst_type
= LLVMVoidTypeInContext(gallivm
->context
);
3733 for (chan
= 0; chan
< 4; ++chan
) {
3734 chans
[chan
] = lp_build_emit_fetch(bld_base
, inst
, 1, chan
);
3736 data
= lp_build_gather_values(gallivm
, chans
, 4);
3738 emit_data
->args
[emit_data
->arg_count
++] = data
;
3740 memory
= tgsi_full_src_register_from_dst(&inst
->Dst
[0]);
3742 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
3743 LLVMValueRef offset
;
3746 rsrc
= shader_buffer_fetch_rsrc(ctx
, &memory
);
3748 tmp
= lp_build_emit_fetch(bld_base
, inst
, 0, 0);
3749 offset
= LLVMBuildBitCast(builder
, tmp
, bld_base
->uint_bld
.elem_type
, "");
3751 buffer_append_args(ctx
, emit_data
, rsrc
, bld_base
->uint_bld
.zero
,
3753 } else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_IMAGE
) {
3754 unsigned target
= inst
->Memory
.Texture
;
3755 LLVMValueRef coords
;
3757 coords
= image_fetch_coords(bld_base
, inst
, 0);
3759 if (target
== TGSI_TEXTURE_BUFFER
) {
3760 image_fetch_rsrc(bld_base
, &memory
, false, &rsrc
);
3762 rsrc
= extract_rsrc_top_half(ctx
, rsrc
);
3763 buffer_append_args(ctx
, emit_data
, rsrc
, coords
,
3764 bld_base
->uint_bld
.zero
, false);
3766 emit_data
->args
[1] = coords
;
3767 image_fetch_rsrc(bld_base
, &memory
, true, &emit_data
->args
[2]);
3768 emit_data
->args
[3] = lp_build_const_int32(gallivm
, 15); /* dmask */
3769 emit_data
->arg_count
= 4;
3771 image_append_args(ctx
, emit_data
, target
, false);
3776 static void store_emit_buffer(
3777 struct si_shader_context
*ctx
,
3778 struct lp_build_emit_data
*emit_data
)
3780 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3781 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3782 LLVMBuilderRef builder
= gallivm
->builder
;
3783 struct lp_build_context
*uint_bld
= &ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
3784 LLVMValueRef base_data
= emit_data
->args
[0];
3785 LLVMValueRef base_offset
= emit_data
->args
[3];
3786 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
3790 const char *intrinsic_name
;
3792 LLVMValueRef offset
;
3795 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
3797 /* Due to an LLVM limitation, split 3-element writes
3798 * into a 2-element and a 1-element write. */
3800 writemask
|= 1 << (start
+ 2);
3806 intrinsic_name
= "llvm.amdgcn.buffer.store.v4f32";
3807 } else if (count
== 2) {
3808 LLVMTypeRef v2f32
= LLVMVectorType(ctx
->f32
, 2);
3810 tmp
= LLVMBuildExtractElement(
3812 lp_build_const_int32(gallivm
, start
), "");
3813 data
= LLVMBuildInsertElement(
3814 builder
, LLVMGetUndef(v2f32
), tmp
,
3815 uint_bld
->zero
, "");
3817 tmp
= LLVMBuildExtractElement(
3819 lp_build_const_int32(gallivm
, start
+ 1), "");
3820 data
= LLVMBuildInsertElement(
3821 builder
, data
, tmp
, uint_bld
->one
, "");
3823 intrinsic_name
= "llvm.amdgcn.buffer.store.v2f32";
3826 data
= LLVMBuildExtractElement(
3828 lp_build_const_int32(gallivm
, start
), "");
3829 intrinsic_name
= "llvm.amdgcn.buffer.store.f32";
3832 offset
= base_offset
;
3834 offset
= LLVMBuildAdd(
3836 lp_build_const_int32(gallivm
, start
* 4), "");
3839 emit_data
->args
[0] = data
;
3840 emit_data
->args
[3] = offset
;
3843 builder
, intrinsic_name
, emit_data
->dst_type
,
3844 emit_data
->args
, emit_data
->arg_count
, 0);
3848 static void store_emit_memory(
3849 struct si_shader_context
*ctx
,
3850 struct lp_build_emit_data
*emit_data
)
3852 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3853 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3854 struct lp_build_context
*base
= &ctx
->radeon_bld
.soa
.bld_base
.base
;
3855 LLVMBuilderRef builder
= gallivm
->builder
;
3856 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
3857 LLVMValueRef ptr
, derived_ptr
, data
, index
;
3860 ptr
= get_memory_ptr(ctx
, inst
, base
->elem_type
, 0);
3862 for (chan
= 0; chan
< 4; ++chan
) {
3863 if (!(writemask
& (1 << chan
))) {
3866 data
= lp_build_emit_fetch(&ctx
->radeon_bld
.soa
.bld_base
, inst
, 1, chan
);
3867 index
= lp_build_const_int32(gallivm
, chan
);
3868 derived_ptr
= LLVMBuildGEP(builder
, ptr
, &index
, 1, "");
3869 LLVMBuildStore(builder
, data
, derived_ptr
);
3873 static void store_emit(
3874 const struct lp_build_tgsi_action
*action
,
3875 struct lp_build_tgsi_context
*bld_base
,
3876 struct lp_build_emit_data
*emit_data
)
3878 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3879 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3880 LLVMBuilderRef builder
= gallivm
->builder
;
3881 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
3882 unsigned target
= inst
->Memory
.Texture
;
3883 char intrinsic_name
[32];
3884 char coords_type
[8];
3886 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
) {
3887 store_emit_memory(ctx
, emit_data
);
3891 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
3894 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
3895 store_emit_buffer(ctx
, emit_data
);
3899 if (target
== TGSI_TEXTURE_BUFFER
) {
3900 emit_data
->output
[emit_data
->chan
] = lp_build_intrinsic(
3901 builder
, "llvm.amdgcn.buffer.store.format.v4f32",
3902 emit_data
->dst_type
, emit_data
->args
,
3903 emit_data
->arg_count
, 0);
3905 build_int_type_name(LLVMTypeOf(emit_data
->args
[1]),
3906 coords_type
, sizeof(coords_type
));
3907 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3908 "llvm.amdgcn.image.store.%s", coords_type
);
3910 emit_data
->output
[emit_data
->chan
] =
3912 builder
, intrinsic_name
, emit_data
->dst_type
,
3913 emit_data
->args
, emit_data
->arg_count
, 0);
3917 static void atomic_fetch_args(
3918 struct lp_build_tgsi_context
* bld_base
,
3919 struct lp_build_emit_data
* emit_data
)
3921 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3922 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3923 LLVMBuilderRef builder
= gallivm
->builder
;
3924 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
3925 LLVMValueRef data1
, data2
;
3929 emit_data
->dst_type
= bld_base
->base
.elem_type
;
3931 tmp
= lp_build_emit_fetch(bld_base
, inst
, 2, 0);
3932 data1
= LLVMBuildBitCast(builder
, tmp
, bld_base
->uint_bld
.elem_type
, "");
3934 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
3935 tmp
= lp_build_emit_fetch(bld_base
, inst
, 3, 0);
3936 data2
= LLVMBuildBitCast(builder
, tmp
, bld_base
->uint_bld
.elem_type
, "");
3939 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3940 * of arguments, which is reversed relative to TGSI (and GLSL)
3942 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
3943 emit_data
->args
[emit_data
->arg_count
++] = data2
;
3944 emit_data
->args
[emit_data
->arg_count
++] = data1
;
3946 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
3947 LLVMValueRef offset
;
3949 rsrc
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0]);
3951 tmp
= lp_build_emit_fetch(bld_base
, inst
, 1, 0);
3952 offset
= LLVMBuildBitCast(builder
, tmp
, bld_base
->uint_bld
.elem_type
, "");
3954 buffer_append_args(ctx
, emit_data
, rsrc
, bld_base
->uint_bld
.zero
,
3956 } else if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
) {
3957 unsigned target
= inst
->Memory
.Texture
;
3958 LLVMValueRef coords
;
3960 image_fetch_rsrc(bld_base
, &inst
->Src
[0],
3961 target
!= TGSI_TEXTURE_BUFFER
, &rsrc
);
3962 coords
= image_fetch_coords(bld_base
, inst
, 1);
3964 if (target
== TGSI_TEXTURE_BUFFER
) {
3965 rsrc
= extract_rsrc_top_half(ctx
, rsrc
);
3966 buffer_append_args(ctx
, emit_data
, rsrc
, coords
,
3967 bld_base
->uint_bld
.zero
, true);
3969 emit_data
->args
[emit_data
->arg_count
++] = coords
;
3970 emit_data
->args
[emit_data
->arg_count
++] = rsrc
;
3972 image_append_args(ctx
, emit_data
, target
, true);
3977 static void atomic_emit_memory(struct si_shader_context
*ctx
,
3978 struct lp_build_emit_data
*emit_data
) {
3979 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3980 LLVMBuilderRef builder
= gallivm
->builder
;
3981 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
3982 LLVMValueRef ptr
, result
, arg
;
3984 ptr
= get_memory_ptr(ctx
, inst
, ctx
->i32
, 1);
3986 arg
= lp_build_emit_fetch(&ctx
->radeon_bld
.soa
.bld_base
, inst
, 2, 0);
3987 arg
= LLVMBuildBitCast(builder
, arg
, ctx
->i32
, "");
3989 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
3990 LLVMValueRef new_data
;
3991 new_data
= lp_build_emit_fetch(&ctx
->radeon_bld
.soa
.bld_base
,
3994 new_data
= LLVMBuildBitCast(builder
, new_data
, ctx
->i32
, "");
3996 #if HAVE_LLVM >= 0x309
3997 result
= LLVMBuildAtomicCmpXchg(builder
, ptr
, arg
, new_data
,
3998 LLVMAtomicOrderingSequentiallyConsistent
,
3999 LLVMAtomicOrderingSequentiallyConsistent
,
4003 result
= LLVMBuildExtractValue(builder
, result
, 0, "");
4005 LLVMAtomicRMWBinOp op
;
4007 switch(inst
->Instruction
.Opcode
) {
4008 case TGSI_OPCODE_ATOMUADD
:
4009 op
= LLVMAtomicRMWBinOpAdd
;
4011 case TGSI_OPCODE_ATOMXCHG
:
4012 op
= LLVMAtomicRMWBinOpXchg
;
4014 case TGSI_OPCODE_ATOMAND
:
4015 op
= LLVMAtomicRMWBinOpAnd
;
4017 case TGSI_OPCODE_ATOMOR
:
4018 op
= LLVMAtomicRMWBinOpOr
;
4020 case TGSI_OPCODE_ATOMXOR
:
4021 op
= LLVMAtomicRMWBinOpXor
;
4023 case TGSI_OPCODE_ATOMUMIN
:
4024 op
= LLVMAtomicRMWBinOpUMin
;
4026 case TGSI_OPCODE_ATOMUMAX
:
4027 op
= LLVMAtomicRMWBinOpUMax
;
4029 case TGSI_OPCODE_ATOMIMIN
:
4030 op
= LLVMAtomicRMWBinOpMin
;
4032 case TGSI_OPCODE_ATOMIMAX
:
4033 op
= LLVMAtomicRMWBinOpMax
;
4036 unreachable("unknown atomic opcode");
4039 result
= LLVMBuildAtomicRMW(builder
, op
, ptr
, arg
,
4040 LLVMAtomicOrderingSequentiallyConsistent
,
4043 emit_data
->output
[emit_data
->chan
] = LLVMBuildBitCast(builder
, result
, emit_data
->dst_type
, "");
4046 static void atomic_emit(
4047 const struct lp_build_tgsi_action
*action
,
4048 struct lp_build_tgsi_context
*bld_base
,
4049 struct lp_build_emit_data
*emit_data
)
4051 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4052 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4053 LLVMBuilderRef builder
= gallivm
->builder
;
4054 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
4055 char intrinsic_name
[40];
4058 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
4059 atomic_emit_memory(ctx
, emit_data
);
4063 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
4064 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
4065 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
4066 "llvm.amdgcn.buffer.atomic.%s", action
->intr_name
);
4068 char coords_type
[8];
4070 build_int_type_name(LLVMTypeOf(emit_data
->args
[1]),
4071 coords_type
, sizeof(coords_type
));
4072 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
4073 "llvm.amdgcn.image.atomic.%s.%s",
4074 action
->intr_name
, coords_type
);
4077 tmp
= lp_build_intrinsic(
4078 builder
, intrinsic_name
, bld_base
->uint_bld
.elem_type
,
4079 emit_data
->args
, emit_data
->arg_count
, 0);
4080 emit_data
->output
[emit_data
->chan
] =
4081 LLVMBuildBitCast(builder
, tmp
, bld_base
->base
.elem_type
, "");
4084 static void resq_fetch_args(
4085 struct lp_build_tgsi_context
* bld_base
,
4086 struct lp_build_emit_data
* emit_data
)
4088 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4089 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4090 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4091 const struct tgsi_full_src_register
*reg
= &inst
->Src
[0];
4093 emit_data
->dst_type
= LLVMVectorType(bld_base
->base
.elem_type
, 4);
4095 if (reg
->Register
.File
== TGSI_FILE_BUFFER
) {
4096 emit_data
->args
[0] = shader_buffer_fetch_rsrc(ctx
, reg
);
4097 emit_data
->arg_count
= 1;
4098 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
4099 image_fetch_rsrc(bld_base
, reg
, false, &emit_data
->args
[0]);
4100 emit_data
->arg_count
= 1;
4102 emit_data
->args
[0] = bld_base
->uint_bld
.zero
; /* mip level */
4103 image_fetch_rsrc(bld_base
, reg
, false, &emit_data
->args
[1]);
4104 emit_data
->args
[2] = lp_build_const_int32(gallivm
, 15); /* dmask */
4105 emit_data
->args
[3] = bld_base
->uint_bld
.zero
; /* unorm */
4106 emit_data
->args
[4] = bld_base
->uint_bld
.zero
; /* r128 */
4107 emit_data
->args
[5] = tgsi_is_array_image(inst
->Memory
.Texture
) ?
4108 bld_base
->uint_bld
.one
: bld_base
->uint_bld
.zero
; /* da */
4109 emit_data
->args
[6] = bld_base
->uint_bld
.zero
; /* glc */
4110 emit_data
->args
[7] = bld_base
->uint_bld
.zero
; /* slc */
4111 emit_data
->args
[8] = bld_base
->uint_bld
.zero
; /* tfe */
4112 emit_data
->args
[9] = bld_base
->uint_bld
.zero
; /* lwe */
4113 emit_data
->arg_count
= 10;
4117 static void resq_emit(
4118 const struct lp_build_tgsi_action
*action
,
4119 struct lp_build_tgsi_context
*bld_base
,
4120 struct lp_build_emit_data
*emit_data
)
4122 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4123 LLVMBuilderRef builder
= gallivm
->builder
;
4124 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4127 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
4128 out
= LLVMBuildExtractElement(builder
, emit_data
->args
[0],
4129 lp_build_const_int32(gallivm
, 2), "");
4130 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
4131 out
= get_buffer_size(bld_base
, emit_data
->args
[0]);
4133 out
= lp_build_intrinsic(
4134 builder
, "llvm.SI.getresinfo.i32", emit_data
->dst_type
,
4135 emit_data
->args
, emit_data
->arg_count
,
4136 LLVMReadNoneAttribute
);
4138 /* Divide the number of layers by 6 to get the number of cubes. */
4139 if (inst
->Memory
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
) {
4140 LLVMValueRef imm2
= lp_build_const_int32(gallivm
, 2);
4141 LLVMValueRef imm6
= lp_build_const_int32(gallivm
, 6);
4143 LLVMValueRef z
= LLVMBuildExtractElement(builder
, out
, imm2
, "");
4144 z
= LLVMBuildBitCast(builder
, z
, bld_base
->uint_bld
.elem_type
, "");
4145 z
= LLVMBuildSDiv(builder
, z
, imm6
, "");
4146 z
= LLVMBuildBitCast(builder
, z
, bld_base
->base
.elem_type
, "");
4147 out
= LLVMBuildInsertElement(builder
, out
, z
, imm2
, "");
4151 emit_data
->output
[emit_data
->chan
] = out
;
4154 static void set_tex_fetch_args(struct si_shader_context
*ctx
,
4155 struct lp_build_emit_data
*emit_data
,
4156 unsigned opcode
, unsigned target
,
4157 LLVMValueRef res_ptr
, LLVMValueRef samp_ptr
,
4158 LLVMValueRef
*param
, unsigned count
,
4161 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
4163 unsigned is_rect
= target
== TGSI_TEXTURE_RECT
;
4165 /* Pad to power of two vector */
4166 while (count
< util_next_power_of_two(count
))
4167 param
[count
++] = LLVMGetUndef(ctx
->i32
);
4169 /* Texture coordinates. */
4171 emit_data
->args
[0] = lp_build_gather_values(gallivm
, param
, count
);
4173 emit_data
->args
[0] = param
[0];
4176 emit_data
->args
[1] = res_ptr
;
4179 if (opcode
== TGSI_OPCODE_TXF
|| opcode
== TGSI_OPCODE_TXQ
)
4180 emit_data
->dst_type
= ctx
->v4i32
;
4182 emit_data
->dst_type
= ctx
->v4f32
;
4184 emit_data
->args
[num_args
++] = samp_ptr
;
4187 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, dmask
);
4188 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, is_rect
); /* unorm */
4189 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, 0); /* r128 */
4190 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
,
4191 tgsi_is_array_sampler(target
)); /* da */
4192 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, 0); /* glc */
4193 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, 0); /* slc */
4194 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, 0); /* tfe */
4195 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, 0); /* lwe */
4197 emit_data
->arg_count
= num_args
;
4200 static const struct lp_build_tgsi_action tex_action
;
4208 static LLVMTypeRef
const_array(LLVMTypeRef elem_type
, int num_elements
)
4210 return LLVMPointerType(LLVMArrayType(elem_type
, num_elements
),
4215 * Load an image view, fmask view. or sampler state descriptor.
4217 static LLVMValueRef
get_sampler_desc_custom(struct si_shader_context
*ctx
,
4218 LLVMValueRef list
, LLVMValueRef index
,
4219 enum desc_type type
)
4221 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
4222 LLVMBuilderRef builder
= gallivm
->builder
;
4226 /* The image is at [0:7]. */
4227 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
4230 /* The FMASK is at [8:15]. */
4231 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
4232 index
= LLVMBuildAdd(builder
, index
, LLVMConstInt(ctx
->i32
, 1, 0), "");
4235 /* The sampler state is at [12:15]. */
4236 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 4, 0), "");
4237 index
= LLVMBuildAdd(builder
, index
, LLVMConstInt(ctx
->i32
, 3, 0), "");
4238 list
= LLVMBuildPointerCast(builder
, list
,
4239 const_array(ctx
->v4i32
, 0), "");
4243 return build_indexed_load_const(ctx
, list
, index
);
4246 static LLVMValueRef
get_sampler_desc(struct si_shader_context
*ctx
,
4247 LLVMValueRef index
, enum desc_type type
)
4249 LLVMValueRef list
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
4252 return get_sampler_desc_custom(ctx
, list
, index
, type
);
4255 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4258 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4259 * filtering manually. The driver sets img7 to a mask clearing
4260 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4261 * s_and_b32 samp0, samp0, img7
4264 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4266 static LLVMValueRef
sici_fix_sampler_aniso(struct si_shader_context
*ctx
,
4267 LLVMValueRef res
, LLVMValueRef samp
)
4269 LLVMBuilderRef builder
= ctx
->radeon_bld
.gallivm
.builder
;
4270 LLVMValueRef img7
, samp0
;
4272 if (ctx
->screen
->b
.chip_class
>= VI
)
4275 img7
= LLVMBuildExtractElement(builder
, res
,
4276 LLVMConstInt(ctx
->i32
, 7, 0), "");
4277 samp0
= LLVMBuildExtractElement(builder
, samp
,
4278 LLVMConstInt(ctx
->i32
, 0, 0), "");
4279 samp0
= LLVMBuildAnd(builder
, samp0
, img7
, "");
4280 return LLVMBuildInsertElement(builder
, samp
, samp0
,
4281 LLVMConstInt(ctx
->i32
, 0, 0), "");
4284 static void tex_fetch_ptrs(
4285 struct lp_build_tgsi_context
*bld_base
,
4286 struct lp_build_emit_data
*emit_data
,
4287 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
, LLVMValueRef
*fmask_ptr
)
4289 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4290 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4291 unsigned target
= inst
->Texture
.Texture
;
4292 unsigned sampler_src
;
4293 unsigned sampler_index
;
4295 sampler_src
= emit_data
->inst
->Instruction
.NumSrcRegs
- 1;
4296 sampler_index
= emit_data
->inst
->Src
[sampler_src
].Register
.Index
;
4298 if (emit_data
->inst
->Src
[sampler_src
].Register
.Indirect
) {
4299 const struct tgsi_full_src_register
*reg
= &emit_data
->inst
->Src
[sampler_src
];
4300 LLVMValueRef ind_index
;
4302 ind_index
= get_bounded_indirect_index(ctx
,
4304 reg
->Register
.Index
,
4307 *res_ptr
= get_sampler_desc(ctx
, ind_index
, DESC_IMAGE
);
4309 if (target
== TGSI_TEXTURE_2D_MSAA
||
4310 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
4314 *fmask_ptr
= get_sampler_desc(ctx
, ind_index
, DESC_FMASK
);
4317 *samp_ptr
= get_sampler_desc(ctx
, ind_index
, DESC_SAMPLER
);
4318 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
4324 *res_ptr
= ctx
->sampler_views
[sampler_index
];
4326 *samp_ptr
= ctx
->sampler_states
[sampler_index
];
4328 *fmask_ptr
= ctx
->fmasks
[sampler_index
];
4332 static void txq_fetch_args(
4333 struct lp_build_tgsi_context
*bld_base
,
4334 struct lp_build_emit_data
*emit_data
)
4336 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4337 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4338 LLVMBuilderRef builder
= gallivm
->builder
;
4339 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4340 unsigned target
= inst
->Texture
.Texture
;
4341 LLVMValueRef res_ptr
;
4342 LLVMValueRef address
;
4344 tex_fetch_ptrs(bld_base
, emit_data
, &res_ptr
, NULL
, NULL
);
4346 if (target
== TGSI_TEXTURE_BUFFER
) {
4347 /* Read the size from the buffer descriptor directly. */
4348 LLVMValueRef res
= LLVMBuildBitCast(builder
, res_ptr
, ctx
->v8i32
, "");
4349 emit_data
->args
[0] = get_buffer_size(bld_base
, res
);
4353 /* Textures - set the mip level. */
4354 address
= lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_X
);
4356 set_tex_fetch_args(ctx
, emit_data
, TGSI_OPCODE_TXQ
, target
, res_ptr
,
4357 NULL
, &address
, 1, 0xf);
4360 static void txq_emit(const struct lp_build_tgsi_action
*action
,
4361 struct lp_build_tgsi_context
*bld_base
,
4362 struct lp_build_emit_data
*emit_data
)
4364 struct lp_build_context
*base
= &bld_base
->base
;
4365 unsigned target
= emit_data
->inst
->Texture
.Texture
;
4367 if (target
== TGSI_TEXTURE_BUFFER
) {
4368 /* Just return the buffer size. */
4369 emit_data
->output
[emit_data
->chan
] = emit_data
->args
[0];
4373 emit_data
->output
[emit_data
->chan
] = lp_build_intrinsic(
4374 base
->gallivm
->builder
, "llvm.SI.getresinfo.i32",
4375 emit_data
->dst_type
, emit_data
->args
, emit_data
->arg_count
,
4376 LLVMReadNoneAttribute
);
4378 /* Divide the number of layers by 6 to get the number of cubes. */
4379 if (target
== TGSI_TEXTURE_CUBE_ARRAY
||
4380 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
4381 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
4382 LLVMValueRef two
= lp_build_const_int32(bld_base
->base
.gallivm
, 2);
4383 LLVMValueRef six
= lp_build_const_int32(bld_base
->base
.gallivm
, 6);
4385 LLVMValueRef v4
= emit_data
->output
[emit_data
->chan
];
4386 LLVMValueRef z
= LLVMBuildExtractElement(builder
, v4
, two
, "");
4387 z
= LLVMBuildSDiv(builder
, z
, six
, "");
4389 emit_data
->output
[emit_data
->chan
] =
4390 LLVMBuildInsertElement(builder
, v4
, z
, two
, "");
4394 static void tex_fetch_args(
4395 struct lp_build_tgsi_context
*bld_base
,
4396 struct lp_build_emit_data
*emit_data
)
4398 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4399 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4400 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4401 unsigned opcode
= inst
->Instruction
.Opcode
;
4402 unsigned target
= inst
->Texture
.Texture
;
4403 LLVMValueRef coords
[5], derivs
[6];
4404 LLVMValueRef address
[16];
4405 unsigned num_coords
= tgsi_util_get_texture_coord_dim(target
);
4406 int ref_pos
= tgsi_util_get_shadow_ref_src_index(target
);
4409 unsigned num_deriv_channels
= 0;
4410 bool has_offset
= inst
->Texture
.NumOffsets
> 0;
4411 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
;
4412 unsigned dmask
= 0xf;
4414 tex_fetch_ptrs(bld_base
, emit_data
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
4416 if (target
== TGSI_TEXTURE_BUFFER
) {
4417 LLVMTypeRef v2i128
= LLVMVectorType(ctx
->i128
, 2);
4419 /* Bitcast and truncate v8i32 to v16i8. */
4420 LLVMValueRef res
= res_ptr
;
4421 res
= LLVMBuildBitCast(gallivm
->builder
, res
, v2i128
, "");
4422 res
= LLVMBuildExtractElement(gallivm
->builder
, res
, bld_base
->uint_bld
.one
, "");
4423 res
= LLVMBuildBitCast(gallivm
->builder
, res
, ctx
->v16i8
, "");
4425 emit_data
->dst_type
= ctx
->v4f32
;
4426 emit_data
->args
[0] = res
;
4427 emit_data
->args
[1] = bld_base
->uint_bld
.zero
;
4428 emit_data
->args
[2] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_X
);
4429 emit_data
->arg_count
= 3;
4433 /* Fetch and project texture coordinates */
4434 coords
[3] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_W
);
4435 for (chan
= 0; chan
< 3; chan
++ ) {
4436 coords
[chan
] = lp_build_emit_fetch(bld_base
,
4439 if (opcode
== TGSI_OPCODE_TXP
)
4440 coords
[chan
] = lp_build_emit_llvm_binary(bld_base
,
4446 if (opcode
== TGSI_OPCODE_TXP
)
4447 coords
[3] = bld_base
->base
.one
;
4450 if (has_offset
&& opcode
!= TGSI_OPCODE_TXF
) {
4451 /* The offsets are six-bit signed integers packed like this:
4452 * X=[5:0], Y=[13:8], and Z=[21:16].
4454 LLVMValueRef offset
[3], pack
;
4456 assert(inst
->Texture
.NumOffsets
== 1);
4458 for (chan
= 0; chan
< 3; chan
++) {
4459 offset
[chan
] = lp_build_emit_fetch_texoffset(bld_base
,
4460 emit_data
->inst
, 0, chan
);
4461 offset
[chan
] = LLVMBuildAnd(gallivm
->builder
, offset
[chan
],
4462 lp_build_const_int32(gallivm
, 0x3f), "");
4464 offset
[chan
] = LLVMBuildShl(gallivm
->builder
, offset
[chan
],
4465 lp_build_const_int32(gallivm
, chan
*8), "");
4468 pack
= LLVMBuildOr(gallivm
->builder
, offset
[0], offset
[1], "");
4469 pack
= LLVMBuildOr(gallivm
->builder
, pack
, offset
[2], "");
4470 address
[count
++] = pack
;
4473 /* Pack LOD bias value */
4474 if (opcode
== TGSI_OPCODE_TXB
)
4475 address
[count
++] = coords
[3];
4476 if (opcode
== TGSI_OPCODE_TXB2
)
4477 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
4479 /* Pack depth comparison value */
4480 if (tgsi_is_shadow_target(target
) && opcode
!= TGSI_OPCODE_LODQ
) {
4481 if (target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
4482 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
4484 assert(ref_pos
>= 0);
4485 address
[count
++] = coords
[ref_pos
];
4489 /* Pack user derivatives */
4490 if (opcode
== TGSI_OPCODE_TXD
) {
4491 int param
, num_src_deriv_channels
;
4494 case TGSI_TEXTURE_3D
:
4495 num_src_deriv_channels
= 3;
4496 num_deriv_channels
= 3;
4498 case TGSI_TEXTURE_2D
:
4499 case TGSI_TEXTURE_SHADOW2D
:
4500 case TGSI_TEXTURE_RECT
:
4501 case TGSI_TEXTURE_SHADOWRECT
:
4502 case TGSI_TEXTURE_2D_ARRAY
:
4503 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
4504 num_src_deriv_channels
= 2;
4505 num_deriv_channels
= 2;
4507 case TGSI_TEXTURE_CUBE
:
4508 case TGSI_TEXTURE_SHADOWCUBE
:
4509 case TGSI_TEXTURE_CUBE_ARRAY
:
4510 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
4511 /* Cube derivatives will be converted to 2D. */
4512 num_src_deriv_channels
= 3;
4513 num_deriv_channels
= 2;
4515 case TGSI_TEXTURE_1D
:
4516 case TGSI_TEXTURE_SHADOW1D
:
4517 case TGSI_TEXTURE_1D_ARRAY
:
4518 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
4519 num_src_deriv_channels
= 1;
4520 num_deriv_channels
= 1;
4523 unreachable("invalid target");
4526 for (param
= 0; param
< 2; param
++)
4527 for (chan
= 0; chan
< num_src_deriv_channels
; chan
++)
4528 derivs
[param
* num_src_deriv_channels
+ chan
] =
4529 lp_build_emit_fetch(bld_base
, inst
, param
+1, chan
);
4532 if (target
== TGSI_TEXTURE_CUBE
||
4533 target
== TGSI_TEXTURE_CUBE_ARRAY
||
4534 target
== TGSI_TEXTURE_SHADOWCUBE
||
4535 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)
4536 radeon_llvm_emit_prepare_cube_coords(bld_base
, emit_data
, coords
, derivs
);
4538 if (opcode
== TGSI_OPCODE_TXD
)
4539 for (int i
= 0; i
< num_deriv_channels
* 2; i
++)
4540 address
[count
++] = derivs
[i
];
4542 /* Pack texture coordinates */
4543 address
[count
++] = coords
[0];
4545 address
[count
++] = coords
[1];
4547 address
[count
++] = coords
[2];
4549 /* Pack LOD or sample index */
4550 if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXF
)
4551 address
[count
++] = coords
[3];
4552 else if (opcode
== TGSI_OPCODE_TXL2
)
4553 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
4556 assert(!"Cannot handle more than 16 texture address parameters");
4560 for (chan
= 0; chan
< count
; chan
++ ) {
4561 address
[chan
] = LLVMBuildBitCast(gallivm
->builder
,
4562 address
[chan
], ctx
->i32
, "");
4565 /* Adjust the sample index according to FMASK.
4567 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4568 * which is the identity mapping. Each nibble says which physical sample
4569 * should be fetched to get that sample.
4571 * For example, 0x11111100 means there are only 2 samples stored and
4572 * the second sample covers 3/4 of the pixel. When reading samples 0
4573 * and 1, return physical sample 0 (determined by the first two 0s
4574 * in FMASK), otherwise return physical sample 1.
4576 * The sample index should be adjusted as follows:
4577 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4579 if (target
== TGSI_TEXTURE_2D_MSAA
||
4580 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
4581 struct lp_build_context
*uint_bld
= &bld_base
->uint_bld
;
4582 struct lp_build_emit_data txf_emit_data
= *emit_data
;
4583 LLVMValueRef txf_address
[4];
4584 unsigned txf_count
= count
;
4585 struct tgsi_full_instruction inst
= {};
4587 memcpy(txf_address
, address
, sizeof(txf_address
));
4589 if (target
== TGSI_TEXTURE_2D_MSAA
) {
4590 txf_address
[2] = bld_base
->uint_bld
.zero
;
4592 txf_address
[3] = bld_base
->uint_bld
.zero
;
4594 /* Read FMASK using TXF. */
4595 inst
.Instruction
.Opcode
= TGSI_OPCODE_TXF
;
4596 inst
.Texture
.Texture
= target
;
4597 txf_emit_data
.inst
= &inst
;
4598 txf_emit_data
.chan
= 0;
4599 set_tex_fetch_args(ctx
, &txf_emit_data
, TGSI_OPCODE_TXF
,
4600 target
, fmask_ptr
, NULL
,
4601 txf_address
, txf_count
, 0xf);
4602 build_tex_intrinsic(&tex_action
, bld_base
, &txf_emit_data
);
4604 /* Initialize some constants. */
4605 LLVMValueRef four
= LLVMConstInt(ctx
->i32
, 4, 0);
4606 LLVMValueRef F
= LLVMConstInt(ctx
->i32
, 0xF, 0);
4608 /* Apply the formula. */
4609 LLVMValueRef fmask
=
4610 LLVMBuildExtractElement(gallivm
->builder
,
4611 txf_emit_data
.output
[0],
4612 uint_bld
->zero
, "");
4614 unsigned sample_chan
= target
== TGSI_TEXTURE_2D_MSAA
? 2 : 3;
4616 LLVMValueRef sample_index4
=
4617 LLVMBuildMul(gallivm
->builder
, address
[sample_chan
], four
, "");
4619 LLVMValueRef shifted_fmask
=
4620 LLVMBuildLShr(gallivm
->builder
, fmask
, sample_index4
, "");
4622 LLVMValueRef final_sample
=
4623 LLVMBuildAnd(gallivm
->builder
, shifted_fmask
, F
, "");
4625 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4626 * resource descriptor is 0 (invalid),
4628 LLVMValueRef fmask_desc
=
4629 LLVMBuildBitCast(gallivm
->builder
, fmask_ptr
,
4632 LLVMValueRef fmask_word1
=
4633 LLVMBuildExtractElement(gallivm
->builder
, fmask_desc
,
4636 LLVMValueRef word1_is_nonzero
=
4637 LLVMBuildICmp(gallivm
->builder
, LLVMIntNE
,
4638 fmask_word1
, uint_bld
->zero
, "");
4640 /* Replace the MSAA sample index. */
4641 address
[sample_chan
] =
4642 LLVMBuildSelect(gallivm
->builder
, word1_is_nonzero
,
4643 final_sample
, address
[sample_chan
], "");
4646 if (opcode
== TGSI_OPCODE_TXF
) {
4647 /* add tex offsets */
4648 if (inst
->Texture
.NumOffsets
) {
4649 struct lp_build_context
*uint_bld
= &bld_base
->uint_bld
;
4650 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
4651 const struct tgsi_texture_offset
*off
= inst
->TexOffsets
;
4653 assert(inst
->Texture
.NumOffsets
== 1);
4656 case TGSI_TEXTURE_3D
:
4657 address
[2] = lp_build_add(uint_bld
, address
[2],
4658 bld
->immediates
[off
->Index
][off
->SwizzleZ
]);
4660 case TGSI_TEXTURE_2D
:
4661 case TGSI_TEXTURE_SHADOW2D
:
4662 case TGSI_TEXTURE_RECT
:
4663 case TGSI_TEXTURE_SHADOWRECT
:
4664 case TGSI_TEXTURE_2D_ARRAY
:
4665 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
4667 lp_build_add(uint_bld
, address
[1],
4668 bld
->immediates
[off
->Index
][off
->SwizzleY
]);
4670 case TGSI_TEXTURE_1D
:
4671 case TGSI_TEXTURE_SHADOW1D
:
4672 case TGSI_TEXTURE_1D_ARRAY
:
4673 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
4675 lp_build_add(uint_bld
, address
[0],
4676 bld
->immediates
[off
->Index
][off
->SwizzleX
]);
4678 /* texture offsets do not apply to other texture targets */
4683 if (opcode
== TGSI_OPCODE_TG4
) {
4684 unsigned gather_comp
= 0;
4686 /* DMASK was repurposed for GATHER4. 4 components are always
4687 * returned and DMASK works like a swizzle - it selects
4688 * the component to fetch. The only valid DMASK values are
4689 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4690 * (red,red,red,red) etc.) The ISA document doesn't mention
4694 /* Get the component index from src1.x for Gather4. */
4695 if (!tgsi_is_shadow_target(target
)) {
4696 LLVMValueRef (*imms
)[4] = lp_soa_context(bld_base
)->immediates
;
4697 LLVMValueRef comp_imm
;
4698 struct tgsi_src_register src1
= inst
->Src
[1].Register
;
4700 assert(src1
.File
== TGSI_FILE_IMMEDIATE
);
4702 comp_imm
= imms
[src1
.Index
][src1
.SwizzleX
];
4703 gather_comp
= LLVMConstIntGetZExtValue(comp_imm
);
4704 gather_comp
= CLAMP(gather_comp
, 0, 3);
4707 dmask
= 1 << gather_comp
;
4710 set_tex_fetch_args(ctx
, emit_data
, opcode
, target
, res_ptr
,
4711 samp_ptr
, address
, count
, dmask
);
4714 static void build_tex_intrinsic(const struct lp_build_tgsi_action
*action
,
4715 struct lp_build_tgsi_context
*bld_base
,
4716 struct lp_build_emit_data
*emit_data
)
4718 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4719 struct lp_build_context
*base
= &bld_base
->base
;
4720 unsigned opcode
= emit_data
->inst
->Instruction
.Opcode
;
4721 unsigned target
= emit_data
->inst
->Texture
.Texture
;
4722 char intr_name
[127];
4723 bool has_offset
= emit_data
->inst
->Texture
.NumOffsets
> 0;
4724 bool is_shadow
= tgsi_is_shadow_target(target
);
4726 const char *name
= "llvm.SI.image.sample";
4727 const char *infix
= "";
4729 if (target
== TGSI_TEXTURE_BUFFER
) {
4730 emit_data
->output
[emit_data
->chan
] = lp_build_intrinsic(
4731 base
->gallivm
->builder
,
4732 "llvm.SI.vs.load.input", emit_data
->dst_type
,
4733 emit_data
->args
, emit_data
->arg_count
,
4734 LLVMReadNoneAttribute
);
4739 case TGSI_OPCODE_TXF
:
4740 name
= target
== TGSI_TEXTURE_2D_MSAA
||
4741 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
?
4742 "llvm.SI.image.load" :
4743 "llvm.SI.image.load.mip";
4747 case TGSI_OPCODE_LODQ
:
4748 name
= "llvm.SI.getlod";
4752 case TGSI_OPCODE_TEX
:
4753 case TGSI_OPCODE_TEX2
:
4754 case TGSI_OPCODE_TXP
:
4755 if (ctx
->type
!= PIPE_SHADER_FRAGMENT
)
4758 case TGSI_OPCODE_TXB
:
4759 case TGSI_OPCODE_TXB2
:
4760 assert(ctx
->type
== PIPE_SHADER_FRAGMENT
);
4763 case TGSI_OPCODE_TXL
:
4764 case TGSI_OPCODE_TXL2
:
4767 case TGSI_OPCODE_TXD
:
4770 case TGSI_OPCODE_TG4
:
4771 name
= "llvm.SI.gather4";
4779 /* Add the type and suffixes .c, .o if needed. */
4780 build_int_type_name(LLVMTypeOf(emit_data
->args
[0]), type
, sizeof(type
));
4781 sprintf(intr_name
, "%s%s%s%s.%s",
4782 name
, is_shadow
? ".c" : "", infix
,
4783 has_offset
? ".o" : "", type
);
4785 emit_data
->output
[emit_data
->chan
] = lp_build_intrinsic(
4786 base
->gallivm
->builder
, intr_name
, emit_data
->dst_type
,
4787 emit_data
->args
, emit_data
->arg_count
,
4788 LLVMReadNoneAttribute
);
4791 static void si_llvm_emit_txqs(
4792 const struct lp_build_tgsi_action
*action
,
4793 struct lp_build_tgsi_context
*bld_base
,
4794 struct lp_build_emit_data
*emit_data
)
4796 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4797 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4798 LLVMBuilderRef builder
= gallivm
->builder
;
4799 LLVMValueRef res
, samples
;
4800 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
;
4802 tex_fetch_ptrs(bld_base
, emit_data
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
4805 /* Read the samples from the descriptor directly. */
4806 res
= LLVMBuildBitCast(builder
, res_ptr
, ctx
->v8i32
, "");
4807 samples
= LLVMBuildExtractElement(
4809 lp_build_const_int32(gallivm
, 3), "");
4810 samples
= LLVMBuildLShr(builder
, samples
,
4811 lp_build_const_int32(gallivm
, 16), "");
4812 samples
= LLVMBuildAnd(builder
, samples
,
4813 lp_build_const_int32(gallivm
, 0xf), "");
4814 samples
= LLVMBuildShl(builder
, lp_build_const_int32(gallivm
, 1),
4817 emit_data
->output
[emit_data
->chan
] = samples
;
4821 * SI implements derivatives using the local data store (LDS)
4822 * All writes to the LDS happen in all executing threads at
4823 * the same time. TID is the Thread ID for the current
4824 * thread and is a value between 0 and 63, representing
4825 * the thread's position in the wavefront.
4827 * For the pixel shader threads are grouped into quads of four pixels.
4828 * The TIDs of the pixels of a quad are:
4836 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
4837 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
4838 * the current pixel's column, and masking with 0xfffffffe yields the TID
4839 * of the left pixel of the current pixel's row.
4841 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
4842 * adding 2 yields the TID of the pixel below the top pixel.
4844 /* masks for thread ID. */
4845 #define TID_MASK_TOP_LEFT 0xfffffffc
4846 #define TID_MASK_TOP 0xfffffffd
4847 #define TID_MASK_LEFT 0xfffffffe
4849 static void si_llvm_emit_ddxy(
4850 const struct lp_build_tgsi_action
*action
,
4851 struct lp_build_tgsi_context
*bld_base
,
4852 struct lp_build_emit_data
*emit_data
)
4854 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4855 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4856 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4857 unsigned opcode
= inst
->Instruction
.Opcode
;
4858 LLVMValueRef indices
[2];
4859 LLVMValueRef store_ptr
, load_ptr0
, load_ptr1
;
4860 LLVMValueRef tl
, trbl
, result
[4];
4861 LLVMValueRef tl_tid
, trbl_tid
;
4862 unsigned swizzle
[4];
4867 indices
[0] = bld_base
->uint_bld
.zero
;
4868 indices
[1] = get_thread_id(ctx
);
4869 store_ptr
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4872 if (opcode
== TGSI_OPCODE_DDX_FINE
)
4873 mask
= TID_MASK_LEFT
;
4874 else if (opcode
== TGSI_OPCODE_DDY_FINE
)
4875 mask
= TID_MASK_TOP
;
4877 mask
= TID_MASK_TOP_LEFT
;
4879 tl_tid
= LLVMBuildAnd(gallivm
->builder
, indices
[1],
4880 lp_build_const_int32(gallivm
, mask
), "");
4881 indices
[1] = tl_tid
;
4882 load_ptr0
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4885 /* for DDX we want to next X pixel, DDY next Y pixel. */
4886 idx
= (opcode
== TGSI_OPCODE_DDX
|| opcode
== TGSI_OPCODE_DDX_FINE
) ? 1 : 2;
4887 trbl_tid
= LLVMBuildAdd(gallivm
->builder
, indices
[1],
4888 lp_build_const_int32(gallivm
, idx
), "");
4889 indices
[1] = trbl_tid
;
4890 load_ptr1
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4893 for (c
= 0; c
< 4; ++c
) {
4896 LLVMValueRef args
[2];
4898 swizzle
[c
] = tgsi_util_get_full_src_register_swizzle(&inst
->Src
[0], c
);
4899 for (i
= 0; i
< c
; ++i
) {
4900 if (swizzle
[i
] == swizzle
[c
]) {
4901 result
[c
] = result
[i
];
4908 val
= LLVMBuildBitCast(gallivm
->builder
,
4909 lp_build_emit_fetch(bld_base
, inst
, 0, c
),
4912 if ((HAVE_LLVM
>= 0x0309) && ctx
->screen
->b
.family
>= CHIP_TONGA
) {
4914 args
[0] = LLVMBuildMul(gallivm
->builder
, tl_tid
,
4915 lp_build_const_int32(gallivm
, 4), "");
4917 tl
= lp_build_intrinsic(gallivm
->builder
,
4918 "llvm.amdgcn.ds.bpermute", ctx
->i32
,
4919 args
, 2, LLVMReadNoneAttribute
);
4921 args
[0] = LLVMBuildMul(gallivm
->builder
, trbl_tid
,
4922 lp_build_const_int32(gallivm
, 4), "");
4923 trbl
= lp_build_intrinsic(gallivm
->builder
,
4924 "llvm.amdgcn.ds.bpermute", ctx
->i32
,
4925 args
, 2, LLVMReadNoneAttribute
);
4927 LLVMBuildStore(gallivm
->builder
, val
, store_ptr
);
4928 tl
= LLVMBuildLoad(gallivm
->builder
, load_ptr0
, "");
4929 trbl
= LLVMBuildLoad(gallivm
->builder
, load_ptr1
, "");
4931 tl
= LLVMBuildBitCast(gallivm
->builder
, tl
, ctx
->f32
, "");
4932 trbl
= LLVMBuildBitCast(gallivm
->builder
, trbl
, ctx
->f32
, "");
4933 result
[c
] = LLVMBuildFSub(gallivm
->builder
, trbl
, tl
, "");
4936 emit_data
->output
[0] = lp_build_gather_values(gallivm
, result
, 4);
4940 * this takes an I,J coordinate pair,
4941 * and works out the X and Y derivatives.
4942 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
4944 static LLVMValueRef
si_llvm_emit_ddxy_interp(
4945 struct lp_build_tgsi_context
*bld_base
,
4946 LLVMValueRef interp_ij
)
4948 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4949 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4950 LLVMValueRef indices
[2];
4951 LLVMValueRef store_ptr
, load_ptr_x
, load_ptr_y
, load_ptr_ddx
, load_ptr_ddy
, temp
, temp2
;
4952 LLVMValueRef tl
, tr
, bl
, result
[4];
4955 indices
[0] = bld_base
->uint_bld
.zero
;
4956 indices
[1] = get_thread_id(ctx
);
4957 store_ptr
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4960 temp
= LLVMBuildAnd(gallivm
->builder
, indices
[1],
4961 lp_build_const_int32(gallivm
, TID_MASK_LEFT
), "");
4963 temp2
= LLVMBuildAnd(gallivm
->builder
, indices
[1],
4964 lp_build_const_int32(gallivm
, TID_MASK_TOP
), "");
4967 load_ptr_x
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4971 load_ptr_y
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4974 indices
[1] = LLVMBuildAdd(gallivm
->builder
, temp
,
4975 lp_build_const_int32(gallivm
, 1), "");
4976 load_ptr_ddx
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4979 indices
[1] = LLVMBuildAdd(gallivm
->builder
, temp2
,
4980 lp_build_const_int32(gallivm
, 2), "");
4981 load_ptr_ddy
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4984 for (c
= 0; c
< 2; ++c
) {
4985 LLVMValueRef store_val
;
4986 LLVMValueRef c_ll
= lp_build_const_int32(gallivm
, c
);
4988 store_val
= LLVMBuildExtractElement(gallivm
->builder
,
4989 interp_ij
, c_ll
, "");
4990 LLVMBuildStore(gallivm
->builder
,
4994 tl
= LLVMBuildLoad(gallivm
->builder
, load_ptr_x
, "");
4995 tl
= LLVMBuildBitCast(gallivm
->builder
, tl
, ctx
->f32
, "");
4997 tr
= LLVMBuildLoad(gallivm
->builder
, load_ptr_ddx
, "");
4998 tr
= LLVMBuildBitCast(gallivm
->builder
, tr
, ctx
->f32
, "");
5000 result
[c
] = LLVMBuildFSub(gallivm
->builder
, tr
, tl
, "");
5002 tl
= LLVMBuildLoad(gallivm
->builder
, load_ptr_y
, "");
5003 tl
= LLVMBuildBitCast(gallivm
->builder
, tl
, ctx
->f32
, "");
5005 bl
= LLVMBuildLoad(gallivm
->builder
, load_ptr_ddy
, "");
5006 bl
= LLVMBuildBitCast(gallivm
->builder
, bl
, ctx
->f32
, "");
5008 result
[c
+ 2] = LLVMBuildFSub(gallivm
->builder
, bl
, tl
, "");
5011 return lp_build_gather_values(gallivm
, result
, 4);
5014 static void interp_fetch_args(
5015 struct lp_build_tgsi_context
*bld_base
,
5016 struct lp_build_emit_data
*emit_data
)
5018 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
5019 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5020 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
5022 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
5023 /* offset is in second src, first two channels */
5024 emit_data
->args
[0] = lp_build_emit_fetch(bld_base
,
5027 emit_data
->args
[1] = lp_build_emit_fetch(bld_base
,
5030 emit_data
->arg_count
= 2;
5031 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
5032 LLVMValueRef sample_position
;
5033 LLVMValueRef sample_id
;
5034 LLVMValueRef halfval
= lp_build_const_float(gallivm
, 0.5f
);
5036 /* fetch sample ID, then fetch its sample position,
5037 * and place into first two channels.
5039 sample_id
= lp_build_emit_fetch(bld_base
,
5040 emit_data
->inst
, 1, TGSI_CHAN_X
);
5041 sample_id
= LLVMBuildBitCast(gallivm
->builder
, sample_id
,
5043 sample_position
= load_sample_position(&ctx
->radeon_bld
, sample_id
);
5045 emit_data
->args
[0] = LLVMBuildExtractElement(gallivm
->builder
,
5047 lp_build_const_int32(gallivm
, 0), "");
5049 emit_data
->args
[0] = LLVMBuildFSub(gallivm
->builder
, emit_data
->args
[0], halfval
, "");
5050 emit_data
->args
[1] = LLVMBuildExtractElement(gallivm
->builder
,
5052 lp_build_const_int32(gallivm
, 1), "");
5053 emit_data
->args
[1] = LLVMBuildFSub(gallivm
->builder
, emit_data
->args
[1], halfval
, "");
5054 emit_data
->arg_count
= 2;
5058 static void build_interp_intrinsic(const struct lp_build_tgsi_action
*action
,
5059 struct lp_build_tgsi_context
*bld_base
,
5060 struct lp_build_emit_data
*emit_data
)
5062 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
5063 struct si_shader
*shader
= ctx
->shader
;
5064 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5065 LLVMValueRef interp_param
;
5066 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
5067 const char *intr_name
;
5068 int input_index
= inst
->Src
[0].Register
.Index
;
5071 LLVMValueRef attr_number
;
5072 LLVMValueRef params
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_PRIM_MASK
);
5073 int interp_param_idx
;
5074 unsigned interp
= shader
->selector
->info
.input_interpolate
[input_index
];
5077 assert(inst
->Src
[0].Register
.File
== TGSI_FILE_INPUT
);
5079 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
5080 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
)
5081 location
= TGSI_INTERPOLATE_LOC_CENTER
;
5083 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
5085 interp_param_idx
= lookup_interp_param_index(interp
, location
);
5086 if (interp_param_idx
== -1)
5088 else if (interp_param_idx
)
5089 interp_param
= get_interp_param(ctx
, interp_param_idx
);
5091 interp_param
= NULL
;
5093 attr_number
= lp_build_const_int32(gallivm
, input_index
);
5095 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
5096 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
5097 LLVMValueRef ij_out
[2];
5098 LLVMValueRef ddxy_out
= si_llvm_emit_ddxy_interp(bld_base
, interp_param
);
5101 * take the I then J parameters, and the DDX/Y for it, and
5102 * calculate the IJ inputs for the interpolator.
5103 * temp1 = ddx * offset/sample.x + I;
5104 * interp_param.I = ddy * offset/sample.y + temp1;
5105 * temp1 = ddx * offset/sample.x + J;
5106 * interp_param.J = ddy * offset/sample.y + temp1;
5108 for (i
= 0; i
< 2; i
++) {
5109 LLVMValueRef ix_ll
= lp_build_const_int32(gallivm
, i
);
5110 LLVMValueRef iy_ll
= lp_build_const_int32(gallivm
, i
+ 2);
5111 LLVMValueRef ddx_el
= LLVMBuildExtractElement(gallivm
->builder
,
5112 ddxy_out
, ix_ll
, "");
5113 LLVMValueRef ddy_el
= LLVMBuildExtractElement(gallivm
->builder
,
5114 ddxy_out
, iy_ll
, "");
5115 LLVMValueRef interp_el
= LLVMBuildExtractElement(gallivm
->builder
,
5116 interp_param
, ix_ll
, "");
5117 LLVMValueRef temp1
, temp2
;
5119 interp_el
= LLVMBuildBitCast(gallivm
->builder
, interp_el
,
5122 temp1
= LLVMBuildFMul(gallivm
->builder
, ddx_el
, emit_data
->args
[0], "");
5124 temp1
= LLVMBuildFAdd(gallivm
->builder
, temp1
, interp_el
, "");
5126 temp2
= LLVMBuildFMul(gallivm
->builder
, ddy_el
, emit_data
->args
[1], "");
5128 temp2
= LLVMBuildFAdd(gallivm
->builder
, temp2
, temp1
, "");
5130 ij_out
[i
] = LLVMBuildBitCast(gallivm
->builder
,
5131 temp2
, ctx
->i32
, "");
5133 interp_param
= lp_build_gather_values(bld_base
->base
.gallivm
, ij_out
, 2);
5136 intr_name
= interp_param
? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
5137 for (chan
= 0; chan
< 2; chan
++) {
5138 LLVMValueRef args
[4];
5139 LLVMValueRef llvm_chan
;
5142 schan
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[0], chan
);
5143 llvm_chan
= lp_build_const_int32(gallivm
, schan
);
5145 args
[0] = llvm_chan
;
5146 args
[1] = attr_number
;
5148 args
[3] = interp_param
;
5150 emit_data
->output
[chan
] =
5151 lp_build_intrinsic(gallivm
->builder
, intr_name
,
5152 ctx
->f32
, args
, args
[3] ? 4 : 3,
5153 LLVMReadNoneAttribute
);
5157 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context
*bld_base
,
5158 struct lp_build_emit_data
*emit_data
)
5160 LLVMValueRef (*imms
)[4] = lp_soa_context(bld_base
)->immediates
;
5161 struct tgsi_src_register src0
= emit_data
->inst
->Src
[0].Register
;
5164 assert(src0
.File
== TGSI_FILE_IMMEDIATE
);
5166 stream
= LLVMConstIntGetZExtValue(imms
[src0
.Index
][src0
.SwizzleX
]) & 0x3;
5170 /* Emit one vertex from the geometry shader */
5171 static void si_llvm_emit_vertex(
5172 const struct lp_build_tgsi_action
*action
,
5173 struct lp_build_tgsi_context
*bld_base
,
5174 struct lp_build_emit_data
*emit_data
)
5176 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
5177 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
5178 struct si_shader
*shader
= ctx
->shader
;
5179 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
5180 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5181 LLVMValueRef soffset
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
5182 SI_PARAM_GS2VS_OFFSET
);
5183 LLVMValueRef gs_next_vertex
;
5184 LLVMValueRef can_emit
, kill
;
5185 LLVMValueRef args
[2];
5190 stream
= si_llvm_get_stream(bld_base
, emit_data
);
5192 /* Write vertex attribute values to GSVS ring */
5193 gs_next_vertex
= LLVMBuildLoad(gallivm
->builder
,
5194 ctx
->gs_next_vertex
[stream
],
5197 /* If this thread has already emitted the declared maximum number of
5198 * vertices, kill it: excessive vertex emissions are not supposed to
5199 * have any effect, and GS threads have no externally observable
5200 * effects other than emitting vertices.
5202 can_emit
= LLVMBuildICmp(gallivm
->builder
, LLVMIntULE
, gs_next_vertex
,
5203 lp_build_const_int32(gallivm
,
5204 shader
->selector
->gs_max_out_vertices
), "");
5205 kill
= lp_build_select(&bld_base
->base
, can_emit
,
5206 lp_build_const_float(gallivm
, 1.0f
),
5207 lp_build_const_float(gallivm
, -1.0f
));
5209 lp_build_intrinsic(gallivm
->builder
, "llvm.AMDGPU.kill",
5210 ctx
->voidt
, &kill
, 1, 0);
5212 for (i
= 0; i
< info
->num_outputs
; i
++) {
5213 LLVMValueRef
*out_ptr
=
5214 ctx
->radeon_bld
.soa
.outputs
[i
];
5216 for (chan
= 0; chan
< 4; chan
++) {
5217 LLVMValueRef out_val
= LLVMBuildLoad(gallivm
->builder
, out_ptr
[chan
], "");
5218 LLVMValueRef voffset
=
5219 lp_build_const_int32(gallivm
, (i
* 4 + chan
) *
5220 shader
->selector
->gs_max_out_vertices
);
5222 voffset
= lp_build_add(uint
, voffset
, gs_next_vertex
);
5223 voffset
= lp_build_mul_imm(uint
, voffset
, 4);
5225 out_val
= LLVMBuildBitCast(gallivm
->builder
, out_val
, ctx
->i32
, "");
5227 build_tbuffer_store(ctx
,
5228 ctx
->gsvs_ring
[stream
],
5230 voffset
, soffset
, 0,
5231 V_008F0C_BUF_DATA_FORMAT_32
,
5232 V_008F0C_BUF_NUM_FORMAT_UINT
,
5236 gs_next_vertex
= lp_build_add(uint
, gs_next_vertex
,
5237 lp_build_const_int32(gallivm
, 1));
5239 LLVMBuildStore(gallivm
->builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
5241 /* Signal vertex emission */
5242 args
[0] = lp_build_const_int32(gallivm
, SENDMSG_GS_OP_EMIT
| SENDMSG_GS
| (stream
<< 8));
5243 args
[1] = LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_GS_WAVE_ID
);
5244 lp_build_intrinsic(gallivm
->builder
, "llvm.SI.sendmsg",
5245 ctx
->voidt
, args
, 2, 0);
5248 /* Cut one primitive from the geometry shader */
5249 static void si_llvm_emit_primitive(
5250 const struct lp_build_tgsi_action
*action
,
5251 struct lp_build_tgsi_context
*bld_base
,
5252 struct lp_build_emit_data
*emit_data
)
5254 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
5255 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5256 LLVMValueRef args
[2];
5259 /* Signal primitive cut */
5260 stream
= si_llvm_get_stream(bld_base
, emit_data
);
5261 args
[0] = lp_build_const_int32(gallivm
, SENDMSG_GS_OP_CUT
| SENDMSG_GS
| (stream
<< 8));
5262 args
[1] = LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_GS_WAVE_ID
);
5263 lp_build_intrinsic(gallivm
->builder
, "llvm.SI.sendmsg",
5264 ctx
->voidt
, args
, 2, 0);
5267 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action
*action
,
5268 struct lp_build_tgsi_context
*bld_base
,
5269 struct lp_build_emit_data
*emit_data
)
5271 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
5272 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5274 /* The real barrier instruction isn’t needed, because an entire patch
5275 * always fits into a single wave.
5277 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
) {
5278 emit_optimization_barrier(ctx
);
5282 lp_build_intrinsic(gallivm
->builder
,
5283 HAVE_LLVM
>= 0x0309 ? "llvm.amdgcn.s.barrier"
5284 : "llvm.AMDGPU.barrier.local",
5285 ctx
->voidt
, NULL
, 0, 0);
5288 static const struct lp_build_tgsi_action tex_action
= {
5289 .fetch_args
= tex_fetch_args
,
5290 .emit
= build_tex_intrinsic
,
5293 static const struct lp_build_tgsi_action interp_action
= {
5294 .fetch_args
= interp_fetch_args
,
5295 .emit
= build_interp_intrinsic
,
5298 static void si_create_function(struct si_shader_context
*ctx
,
5299 LLVMTypeRef
*returns
, unsigned num_returns
,
5300 LLVMTypeRef
*params
, unsigned num_params
,
5301 int last_array_pointer
, int last_sgpr
)
5305 radeon_llvm_create_func(&ctx
->radeon_bld
, returns
, num_returns
,
5306 params
, num_params
);
5307 radeon_llvm_shader_type(ctx
->radeon_bld
.main_fn
, ctx
->type
);
5308 ctx
->return_value
= LLVMGetUndef(ctx
->radeon_bld
.return_type
);
5310 for (i
= 0; i
<= last_sgpr
; ++i
) {
5311 LLVMValueRef P
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, i
);
5313 /* We tell llvm that array inputs are passed by value to allow Sinking pass
5314 * to move load. Inputs are constant so this is fine. */
5315 if (i
<= last_array_pointer
)
5316 LLVMAddAttribute(P
, LLVMByValAttribute
);
5318 LLVMAddAttribute(P
, LLVMInRegAttribute
);
5321 if (ctx
->screen
->b
.debug_flags
& DBG_UNSAFE_MATH
) {
5322 /* These were copied from some LLVM test. */
5323 LLVMAddTargetDependentFunctionAttr(ctx
->radeon_bld
.main_fn
,
5324 "less-precise-fpmad",
5326 LLVMAddTargetDependentFunctionAttr(ctx
->radeon_bld
.main_fn
,
5329 LLVMAddTargetDependentFunctionAttr(ctx
->radeon_bld
.main_fn
,
5332 LLVMAddTargetDependentFunctionAttr(ctx
->radeon_bld
.main_fn
,
5338 static void create_meta_data(struct si_shader_context
*ctx
)
5340 struct gallivm_state
*gallivm
= ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
5341 LLVMValueRef args
[3];
5343 args
[0] = LLVMMDStringInContext(gallivm
->context
, "const", 5);
5345 args
[2] = lp_build_const_int32(gallivm
, 1);
5347 ctx
->const_md
= LLVMMDNodeInContext(gallivm
->context
, args
, 3);
5349 ctx
->uniform_md_kind
= LLVMGetMDKindIDInContext(gallivm
->context
,
5350 "amdgpu.uniform", 14);
5352 ctx
->empty_md
= LLVMMDNodeInContext(gallivm
->context
, NULL
, 0);
5355 static void declare_streamout_params(struct si_shader_context
*ctx
,
5356 struct pipe_stream_output_info
*so
,
5357 LLVMTypeRef
*params
, LLVMTypeRef i32
,
5358 unsigned *num_params
)
5362 /* Streamout SGPRs. */
5363 if (so
->num_outputs
) {
5364 if (ctx
->type
!= PIPE_SHADER_TESS_EVAL
)
5365 params
[ctx
->param_streamout_config
= (*num_params
)++] = i32
;
5367 ctx
->param_streamout_config
= ctx
->param_tess_offchip
;
5369 params
[ctx
->param_streamout_write_index
= (*num_params
)++] = i32
;
5371 /* A streamout buffer offset is loaded if the stride is non-zero. */
5372 for (i
= 0; i
< 4; i
++) {
5376 params
[ctx
->param_streamout_offset
[i
] = (*num_params
)++] = i32
;
5380 static unsigned llvm_get_type_size(LLVMTypeRef type
)
5382 LLVMTypeKind kind
= LLVMGetTypeKind(type
);
5385 case LLVMIntegerTypeKind
:
5386 return LLVMGetIntTypeWidth(type
) / 8;
5387 case LLVMFloatTypeKind
:
5389 case LLVMPointerTypeKind
:
5391 case LLVMVectorTypeKind
:
5392 return LLVMGetVectorSize(type
) *
5393 llvm_get_type_size(LLVMGetElementType(type
));
5400 static void declare_tess_lds(struct si_shader_context
*ctx
)
5402 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
5403 LLVMTypeRef i32
= ctx
->radeon_bld
.soa
.bld_base
.uint_bld
.elem_type
;
5404 unsigned lds_size
= ctx
->screen
->b
.chip_class
>= CIK
? 65536 : 32768;
5406 /* The actual size is computed outside of the shader to reduce
5407 * the number of shader variants. */
5409 LLVMAddGlobalInAddressSpace(gallivm
->module
,
5410 LLVMArrayType(i32
, lds_size
/ 4),
5415 static void create_function(struct si_shader_context
*ctx
)
5417 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
5418 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5419 struct si_shader
*shader
= ctx
->shader
;
5420 LLVMTypeRef params
[SI_NUM_PARAMS
+ SI_NUM_VERTEX_BUFFERS
], v3i32
;
5421 LLVMTypeRef returns
[16+32*4];
5422 unsigned i
, last_array_pointer
, last_sgpr
, num_params
, num_return_sgprs
;
5423 unsigned num_returns
= 0;
5425 v3i32
= LLVMVectorType(ctx
->i32
, 3);
5427 params
[SI_PARAM_RW_BUFFERS
] = const_array(ctx
->v16i8
, SI_NUM_RW_BUFFERS
);
5428 params
[SI_PARAM_CONST_BUFFERS
] = const_array(ctx
->v16i8
, SI_NUM_CONST_BUFFERS
);
5429 params
[SI_PARAM_SAMPLERS
] = const_array(ctx
->v8i32
, SI_NUM_SAMPLERS
);
5430 params
[SI_PARAM_IMAGES
] = const_array(ctx
->v8i32
, SI_NUM_IMAGES
);
5431 params
[SI_PARAM_SHADER_BUFFERS
] = const_array(ctx
->v4i32
, SI_NUM_SHADER_BUFFERS
);
5432 last_array_pointer
= SI_PARAM_SHADER_BUFFERS
;
5434 switch (ctx
->type
) {
5435 case PIPE_SHADER_VERTEX
:
5436 params
[SI_PARAM_VERTEX_BUFFERS
] = const_array(ctx
->v16i8
, SI_NUM_VERTEX_BUFFERS
);
5437 last_array_pointer
= SI_PARAM_VERTEX_BUFFERS
;
5438 params
[SI_PARAM_BASE_VERTEX
] = ctx
->i32
;
5439 params
[SI_PARAM_START_INSTANCE
] = ctx
->i32
;
5440 num_params
= SI_PARAM_START_INSTANCE
+1;
5442 if (shader
->key
.vs
.as_es
) {
5443 params
[ctx
->param_es2gs_offset
= num_params
++] = ctx
->i32
;
5444 } else if (shader
->key
.vs
.as_ls
) {
5445 params
[SI_PARAM_LS_OUT_LAYOUT
] = ctx
->i32
;
5446 num_params
= SI_PARAM_LS_OUT_LAYOUT
+1;
5448 if (ctx
->is_gs_copy_shader
) {
5449 last_array_pointer
= SI_PARAM_RW_BUFFERS
;
5450 num_params
= SI_PARAM_RW_BUFFERS
+1;
5452 params
[SI_PARAM_VS_STATE_BITS
] = ctx
->i32
;
5453 num_params
= SI_PARAM_VS_STATE_BITS
+1;
5456 /* The locations of the other parameters are assigned dynamically. */
5457 declare_streamout_params(ctx
, &shader
->selector
->so
,
5458 params
, ctx
->i32
, &num_params
);
5461 last_sgpr
= num_params
-1;
5464 params
[ctx
->param_vertex_id
= num_params
++] = ctx
->i32
;
5465 params
[ctx
->param_rel_auto_id
= num_params
++] = ctx
->i32
;
5466 params
[ctx
->param_vs_prim_id
= num_params
++] = ctx
->i32
;
5467 params
[ctx
->param_instance_id
= num_params
++] = ctx
->i32
;
5469 if (!ctx
->is_monolithic
&&
5470 !ctx
->is_gs_copy_shader
) {
5471 /* Vertex load indices. */
5472 ctx
->param_vertex_index0
= num_params
;
5474 for (i
= 0; i
< shader
->selector
->info
.num_inputs
; i
++)
5475 params
[num_params
++] = ctx
->i32
;
5477 /* PrimitiveID output. */
5478 if (!shader
->key
.vs
.as_es
&& !shader
->key
.vs
.as_ls
)
5479 for (i
= 0; i
<= VS_EPILOG_PRIMID_LOC
; i
++)
5480 returns
[num_returns
++] = ctx
->f32
;
5484 case PIPE_SHADER_TESS_CTRL
:
5485 params
[SI_PARAM_TCS_OFFCHIP_LAYOUT
] = ctx
->i32
;
5486 params
[SI_PARAM_TCS_OUT_OFFSETS
] = ctx
->i32
;
5487 params
[SI_PARAM_TCS_OUT_LAYOUT
] = ctx
->i32
;
5488 params
[SI_PARAM_TCS_IN_LAYOUT
] = ctx
->i32
;
5489 params
[ctx
->param_oc_lds
= SI_PARAM_TCS_OC_LDS
] = ctx
->i32
;
5490 params
[SI_PARAM_TESS_FACTOR_OFFSET
] = ctx
->i32
;
5491 last_sgpr
= SI_PARAM_TESS_FACTOR_OFFSET
;
5494 params
[SI_PARAM_PATCH_ID
] = ctx
->i32
;
5495 params
[SI_PARAM_REL_IDS
] = ctx
->i32
;
5496 num_params
= SI_PARAM_REL_IDS
+1;
5498 if (!ctx
->is_monolithic
) {
5499 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5500 * placed after the user SGPRs.
5502 for (i
= 0; i
< SI_TCS_NUM_USER_SGPR
+ 2; i
++)
5503 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
5505 for (i
= 0; i
< 3; i
++)
5506 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
5510 case PIPE_SHADER_TESS_EVAL
:
5511 params
[SI_PARAM_TCS_OFFCHIP_LAYOUT
] = ctx
->i32
;
5512 num_params
= SI_PARAM_TCS_OFFCHIP_LAYOUT
+1;
5514 if (shader
->key
.tes
.as_es
) {
5515 params
[ctx
->param_oc_lds
= num_params
++] = ctx
->i32
;
5516 params
[ctx
->param_tess_offchip
= num_params
++] = ctx
->i32
;
5517 params
[ctx
->param_es2gs_offset
= num_params
++] = ctx
->i32
;
5519 params
[ctx
->param_tess_offchip
= num_params
++] = ctx
->i32
;
5520 declare_streamout_params(ctx
, &shader
->selector
->so
,
5521 params
, ctx
->i32
, &num_params
);
5522 params
[ctx
->param_oc_lds
= num_params
++] = ctx
->i32
;
5524 last_sgpr
= num_params
- 1;
5527 params
[ctx
->param_tes_u
= num_params
++] = ctx
->f32
;
5528 params
[ctx
->param_tes_v
= num_params
++] = ctx
->f32
;
5529 params
[ctx
->param_tes_rel_patch_id
= num_params
++] = ctx
->i32
;
5530 params
[ctx
->param_tes_patch_id
= num_params
++] = ctx
->i32
;
5532 /* PrimitiveID output. */
5533 if (!ctx
->is_monolithic
&& !shader
->key
.tes
.as_es
)
5534 for (i
= 0; i
<= VS_EPILOG_PRIMID_LOC
; i
++)
5535 returns
[num_returns
++] = ctx
->f32
;
5538 case PIPE_SHADER_GEOMETRY
:
5539 params
[SI_PARAM_GS2VS_OFFSET
] = ctx
->i32
;
5540 params
[SI_PARAM_GS_WAVE_ID
] = ctx
->i32
;
5541 last_sgpr
= SI_PARAM_GS_WAVE_ID
;
5544 params
[SI_PARAM_VTX0_OFFSET
] = ctx
->i32
;
5545 params
[SI_PARAM_VTX1_OFFSET
] = ctx
->i32
;
5546 params
[SI_PARAM_PRIMITIVE_ID
] = ctx
->i32
;
5547 params
[SI_PARAM_VTX2_OFFSET
] = ctx
->i32
;
5548 params
[SI_PARAM_VTX3_OFFSET
] = ctx
->i32
;
5549 params
[SI_PARAM_VTX4_OFFSET
] = ctx
->i32
;
5550 params
[SI_PARAM_VTX5_OFFSET
] = ctx
->i32
;
5551 params
[SI_PARAM_GS_INSTANCE_ID
] = ctx
->i32
;
5552 num_params
= SI_PARAM_GS_INSTANCE_ID
+1;
5555 case PIPE_SHADER_FRAGMENT
:
5556 params
[SI_PARAM_ALPHA_REF
] = ctx
->f32
;
5557 params
[SI_PARAM_PRIM_MASK
] = ctx
->i32
;
5558 last_sgpr
= SI_PARAM_PRIM_MASK
;
5559 params
[SI_PARAM_PERSP_SAMPLE
] = ctx
->v2i32
;
5560 params
[SI_PARAM_PERSP_CENTER
] = ctx
->v2i32
;
5561 params
[SI_PARAM_PERSP_CENTROID
] = ctx
->v2i32
;
5562 params
[SI_PARAM_PERSP_PULL_MODEL
] = v3i32
;
5563 params
[SI_PARAM_LINEAR_SAMPLE
] = ctx
->v2i32
;
5564 params
[SI_PARAM_LINEAR_CENTER
] = ctx
->v2i32
;
5565 params
[SI_PARAM_LINEAR_CENTROID
] = ctx
->v2i32
;
5566 params
[SI_PARAM_LINE_STIPPLE_TEX
] = ctx
->f32
;
5567 params
[SI_PARAM_POS_X_FLOAT
] = ctx
->f32
;
5568 params
[SI_PARAM_POS_Y_FLOAT
] = ctx
->f32
;
5569 params
[SI_PARAM_POS_Z_FLOAT
] = ctx
->f32
;
5570 params
[SI_PARAM_POS_W_FLOAT
] = ctx
->f32
;
5571 params
[SI_PARAM_FRONT_FACE
] = ctx
->i32
;
5572 params
[SI_PARAM_ANCILLARY
] = ctx
->i32
;
5573 params
[SI_PARAM_SAMPLE_COVERAGE
] = ctx
->f32
;
5574 params
[SI_PARAM_POS_FIXED_PT
] = ctx
->i32
;
5575 num_params
= SI_PARAM_POS_FIXED_PT
+1;
5577 if (!ctx
->is_monolithic
) {
5578 /* Color inputs from the prolog. */
5579 if (shader
->selector
->info
.colors_read
) {
5580 unsigned num_color_elements
=
5581 util_bitcount(shader
->selector
->info
.colors_read
);
5583 assert(num_params
+ num_color_elements
<= ARRAY_SIZE(params
));
5584 for (i
= 0; i
< num_color_elements
; i
++)
5585 params
[num_params
++] = ctx
->f32
;
5588 /* Outputs for the epilog. */
5589 num_return_sgprs
= SI_SGPR_ALPHA_REF
+ 1;
5592 util_bitcount(shader
->selector
->info
.colors_written
) * 4 +
5593 shader
->selector
->info
.writes_z
+
5594 shader
->selector
->info
.writes_stencil
+
5595 shader
->selector
->info
.writes_samplemask
+
5596 1 /* SampleMaskIn */;
5598 num_returns
= MAX2(num_returns
,
5600 PS_EPILOG_SAMPLEMASK_MIN_LOC
+ 1);
5602 for (i
= 0; i
< num_return_sgprs
; i
++)
5603 returns
[i
] = ctx
->i32
;
5604 for (; i
< num_returns
; i
++)
5605 returns
[i
] = ctx
->f32
;
5609 case PIPE_SHADER_COMPUTE
:
5610 params
[SI_PARAM_GRID_SIZE
] = v3i32
;
5611 params
[SI_PARAM_BLOCK_ID
] = v3i32
;
5612 last_sgpr
= SI_PARAM_BLOCK_ID
;
5614 params
[SI_PARAM_THREAD_ID
] = v3i32
;
5615 num_params
= SI_PARAM_THREAD_ID
+ 1;
5618 assert(0 && "unimplemented shader");
5622 assert(num_params
<= ARRAY_SIZE(params
));
5624 si_create_function(ctx
, returns
, num_returns
, params
,
5625 num_params
, last_array_pointer
, last_sgpr
);
5627 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5628 if (ctx
->type
== PIPE_SHADER_FRAGMENT
&&
5629 !ctx
->is_monolithic
) {
5630 radeon_llvm_add_attribute(ctx
->radeon_bld
.main_fn
,
5631 "InitialPSInputAddr",
5632 S_0286D0_PERSP_SAMPLE_ENA(1) |
5633 S_0286D0_PERSP_CENTER_ENA(1) |
5634 S_0286D0_PERSP_CENTROID_ENA(1) |
5635 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5636 S_0286D0_LINEAR_CENTER_ENA(1) |
5637 S_0286D0_LINEAR_CENTROID_ENA(1) |
5638 S_0286D0_FRONT_FACE_ENA(1) |
5639 S_0286D0_POS_FIXED_PT_ENA(1));
5640 } else if (ctx
->type
== PIPE_SHADER_COMPUTE
) {
5641 const unsigned *properties
= shader
->selector
->info
.properties
;
5642 unsigned max_work_group_size
=
5643 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] *
5644 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
] *
5645 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
];
5647 assert(max_work_group_size
);
5649 radeon_llvm_add_attribute(ctx
->radeon_bld
.main_fn
,
5650 "amdgpu-max-work-group-size",
5651 max_work_group_size
);
5654 shader
->info
.num_input_sgprs
= 0;
5655 shader
->info
.num_input_vgprs
= 0;
5657 for (i
= 0; i
<= last_sgpr
; ++i
)
5658 shader
->info
.num_input_sgprs
+= llvm_get_type_size(params
[i
]) / 4;
5660 /* Unused fragment shader inputs are eliminated by the compiler,
5661 * so we don't know yet how many there will be.
5663 if (ctx
->type
!= PIPE_SHADER_FRAGMENT
)
5664 for (; i
< num_params
; ++i
)
5665 shader
->info
.num_input_vgprs
+= llvm_get_type_size(params
[i
]) / 4;
5667 if (bld_base
->info
&&
5668 (bld_base
->info
->opcode_count
[TGSI_OPCODE_DDX
] > 0 ||
5669 bld_base
->info
->opcode_count
[TGSI_OPCODE_DDY
] > 0 ||
5670 bld_base
->info
->opcode_count
[TGSI_OPCODE_DDX_FINE
] > 0 ||
5671 bld_base
->info
->opcode_count
[TGSI_OPCODE_DDY_FINE
] > 0 ||
5672 bld_base
->info
->opcode_count
[TGSI_OPCODE_INTERP_OFFSET
] > 0 ||
5673 bld_base
->info
->opcode_count
[TGSI_OPCODE_INTERP_SAMPLE
] > 0))
5675 LLVMAddGlobalInAddressSpace(gallivm
->module
,
5676 LLVMArrayType(ctx
->i32
, 64),
5680 if ((ctx
->type
== PIPE_SHADER_VERTEX
&& shader
->key
.vs
.as_ls
) ||
5681 ctx
->type
== PIPE_SHADER_TESS_CTRL
||
5682 ctx
->type
== PIPE_SHADER_TESS_EVAL
)
5683 declare_tess_lds(ctx
);
5686 static void preload_constants(struct si_shader_context
*ctx
)
5688 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
5689 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5690 const struct tgsi_shader_info
*info
= bld_base
->info
;
5692 LLVMValueRef ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_CONST_BUFFERS
);
5694 for (buf
= 0; buf
< SI_NUM_CONST_BUFFERS
; buf
++) {
5695 unsigned i
, num_const
= info
->const_file_max
[buf
] + 1;
5700 /* Allocate space for the constant values */
5701 ctx
->constants
[buf
] = CALLOC(num_const
* 4, sizeof(LLVMValueRef
));
5703 /* Load the resource descriptor */
5704 ctx
->const_buffers
[buf
] =
5705 build_indexed_load_const(ctx
, ptr
, lp_build_const_int32(gallivm
, buf
));
5707 /* Load the constants, we rely on the code sinking to do the rest */
5708 for (i
= 0; i
< num_const
* 4; ++i
) {
5709 ctx
->constants
[buf
][i
] =
5710 buffer_load_const(gallivm
->builder
,
5711 ctx
->const_buffers
[buf
],
5712 lp_build_const_int32(gallivm
, i
* 4),
5718 static void preload_shader_buffers(struct si_shader_context
*ctx
)
5720 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
5721 LLVMValueRef ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_SHADER_BUFFERS
);
5724 maxbuf
= MIN2(ctx
->shader
->selector
->info
.file_max
[TGSI_FILE_BUFFER
],
5725 SI_NUM_SHADER_BUFFERS
- 1);
5726 for (buf
= 0; buf
<= maxbuf
; ++buf
) {
5727 ctx
->shader_buffers
[buf
] =
5728 build_indexed_load_const(
5729 ctx
, ptr
, lp_build_const_int32(gallivm
, buf
));
5733 static void preload_samplers(struct si_shader_context
*ctx
)
5735 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
5736 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5737 const struct tgsi_shader_info
*info
= bld_base
->info
;
5738 unsigned i
, num_samplers
= info
->file_max
[TGSI_FILE_SAMPLER
] + 1;
5739 LLVMValueRef offset
;
5741 if (num_samplers
== 0)
5744 /* Load the resources and samplers, we rely on the code sinking to do the rest */
5745 for (i
= 0; i
< num_samplers
; ++i
) {
5747 offset
= lp_build_const_int32(gallivm
, i
);
5748 ctx
->sampler_views
[i
] =
5749 get_sampler_desc(ctx
, offset
, DESC_IMAGE
);
5751 /* FMASK resource */
5752 if (info
->is_msaa_sampler
[i
])
5754 get_sampler_desc(ctx
, offset
, DESC_FMASK
);
5756 ctx
->sampler_states
[i
] =
5757 get_sampler_desc(ctx
, offset
, DESC_SAMPLER
);
5758 ctx
->sampler_states
[i
] =
5759 sici_fix_sampler_aniso(ctx
, ctx
->sampler_views
[i
],
5760 ctx
->sampler_states
[i
]);
5765 static void preload_images(struct si_shader_context
*ctx
)
5767 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
5768 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
5769 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5770 unsigned num_images
= bld_base
->info
->file_max
[TGSI_FILE_IMAGE
] + 1;
5771 LLVMValueRef res_ptr
;
5774 if (num_images
== 0)
5777 res_ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_IMAGES
);
5779 for (i
= 0; i
< num_images
; ++i
) {
5780 /* Rely on LLVM to shrink the load for buffer resources. */
5782 build_indexed_load_const(ctx
, res_ptr
,
5783 lp_build_const_int32(gallivm
, i
));
5785 if (info
->images_writemask
& (1 << i
) &&
5786 !(info
->images_buffers
& (1 << i
)))
5787 rsrc
= force_dcc_off(ctx
, rsrc
);
5789 ctx
->images
[i
] = rsrc
;
5793 static void preload_streamout_buffers(struct si_shader_context
*ctx
)
5795 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
5796 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5799 /* Streamout can only be used if the shader is compiled as VS. */
5800 if (!ctx
->shader
->selector
->so
.num_outputs
||
5801 (ctx
->type
== PIPE_SHADER_VERTEX
&&
5802 (ctx
->shader
->key
.vs
.as_es
||
5803 ctx
->shader
->key
.vs
.as_ls
)) ||
5804 (ctx
->type
== PIPE_SHADER_TESS_EVAL
&&
5805 ctx
->shader
->key
.tes
.as_es
))
5808 LLVMValueRef buf_ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
5809 SI_PARAM_RW_BUFFERS
);
5811 /* Load the resources, we rely on the code sinking to do the rest */
5812 for (i
= 0; i
< 4; ++i
) {
5813 if (ctx
->shader
->selector
->so
.stride
[i
]) {
5814 LLVMValueRef offset
= lp_build_const_int32(gallivm
,
5815 SI_VS_STREAMOUT_BUF0
+ i
);
5817 ctx
->so_buffers
[i
] = build_indexed_load_const(ctx
, buf_ptr
, offset
);
5823 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5826 static void preload_ring_buffers(struct si_shader_context
*ctx
)
5828 struct gallivm_state
*gallivm
=
5829 ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
5831 LLVMValueRef buf_ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
5832 SI_PARAM_RW_BUFFERS
);
5834 if ((ctx
->type
== PIPE_SHADER_VERTEX
&&
5835 ctx
->shader
->key
.vs
.as_es
) ||
5836 (ctx
->type
== PIPE_SHADER_TESS_EVAL
&&
5837 ctx
->shader
->key
.tes
.as_es
) ||
5838 ctx
->type
== PIPE_SHADER_GEOMETRY
) {
5840 ctx
->type
== PIPE_SHADER_GEOMETRY
? SI_GS_RING_ESGS
5842 LLVMValueRef offset
= lp_build_const_int32(gallivm
, ring
);
5845 build_indexed_load_const(ctx
, buf_ptr
, offset
);
5848 if (ctx
->is_gs_copy_shader
) {
5849 LLVMValueRef offset
= lp_build_const_int32(gallivm
, SI_VS_RING_GSVS
);
5852 build_indexed_load_const(ctx
, buf_ptr
, offset
);
5854 if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
5856 for (i
= 0; i
< 4; i
++) {
5857 LLVMValueRef offset
= lp_build_const_int32(gallivm
, SI_GS_RING_GSVS0
+ i
);
5860 build_indexed_load_const(ctx
, buf_ptr
, offset
);
5865 static void si_llvm_emit_polygon_stipple(struct si_shader_context
*ctx
,
5866 LLVMValueRef param_rw_buffers
,
5867 unsigned param_pos_fixed_pt
)
5869 struct lp_build_tgsi_context
*bld_base
=
5870 &ctx
->radeon_bld
.soa
.bld_base
;
5871 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5872 LLVMBuilderRef builder
= gallivm
->builder
;
5873 LLVMValueRef slot
, desc
, offset
, row
, bit
, address
[2];
5875 /* Use the fixed-point gl_FragCoord input.
5876 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5877 * per coordinate to get the repeating effect.
5879 address
[0] = unpack_param(ctx
, param_pos_fixed_pt
, 0, 5);
5880 address
[1] = unpack_param(ctx
, param_pos_fixed_pt
, 16, 5);
5882 /* Load the buffer descriptor. */
5883 slot
= lp_build_const_int32(gallivm
, SI_PS_CONST_POLY_STIPPLE
);
5884 desc
= build_indexed_load_const(ctx
, param_rw_buffers
, slot
);
5886 /* The stipple pattern is 32x32, each row has 32 bits. */
5887 offset
= LLVMBuildMul(builder
, address
[1],
5888 LLVMConstInt(ctx
->i32
, 4, 0), "");
5889 row
= buffer_load_const(builder
, desc
, offset
, ctx
->i32
);
5890 bit
= LLVMBuildLShr(builder
, row
, address
[0], "");
5891 bit
= LLVMBuildTrunc(builder
, bit
, ctx
->i1
, "");
5893 /* The intrinsic kills the thread if arg < 0. */
5894 bit
= LLVMBuildSelect(builder
, bit
, LLVMConstReal(ctx
->f32
, 0),
5895 LLVMConstReal(ctx
->f32
, -1), "");
5896 lp_build_intrinsic(builder
, "llvm.AMDGPU.kill", ctx
->voidt
, &bit
, 1, 0);
5899 void si_shader_binary_read_config(struct radeon_shader_binary
*binary
,
5900 struct si_shader_config
*conf
,
5901 unsigned symbol_offset
)
5904 const unsigned char *config
=
5905 radeon_shader_binary_config_start(binary
, symbol_offset
);
5906 bool really_needs_scratch
= false;
5908 /* LLVM adds SGPR spills to the scratch size.
5909 * Find out if we really need the scratch buffer.
5911 for (i
= 0; i
< binary
->reloc_count
; i
++) {
5912 const struct radeon_shader_reloc
*reloc
= &binary
->relocs
[i
];
5914 if (!strcmp(scratch_rsrc_dword0_symbol
, reloc
->name
) ||
5915 !strcmp(scratch_rsrc_dword1_symbol
, reloc
->name
)) {
5916 really_needs_scratch
= true;
5921 /* XXX: We may be able to emit some of these values directly rather than
5922 * extracting fields to be emitted later.
5925 for (i
= 0; i
< binary
->config_size_per_symbol
; i
+= 8) {
5926 unsigned reg
= util_le32_to_cpu(*(uint32_t*)(config
+ i
));
5927 unsigned value
= util_le32_to_cpu(*(uint32_t*)(config
+ i
+ 4));
5929 case R_00B028_SPI_SHADER_PGM_RSRC1_PS
:
5930 case R_00B128_SPI_SHADER_PGM_RSRC1_VS
:
5931 case R_00B228_SPI_SHADER_PGM_RSRC1_GS
:
5932 case R_00B848_COMPUTE_PGM_RSRC1
:
5933 conf
->num_sgprs
= MAX2(conf
->num_sgprs
, (G_00B028_SGPRS(value
) + 1) * 8);
5934 conf
->num_vgprs
= MAX2(conf
->num_vgprs
, (G_00B028_VGPRS(value
) + 1) * 4);
5935 conf
->float_mode
= G_00B028_FLOAT_MODE(value
);
5936 conf
->rsrc1
= value
;
5938 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS
:
5939 conf
->lds_size
= MAX2(conf
->lds_size
, G_00B02C_EXTRA_LDS_SIZE(value
));
5941 case R_00B84C_COMPUTE_PGM_RSRC2
:
5942 conf
->lds_size
= MAX2(conf
->lds_size
, G_00B84C_LDS_SIZE(value
));
5943 conf
->rsrc2
= value
;
5945 case R_0286CC_SPI_PS_INPUT_ENA
:
5946 conf
->spi_ps_input_ena
= value
;
5948 case R_0286D0_SPI_PS_INPUT_ADDR
:
5949 conf
->spi_ps_input_addr
= value
;
5951 case R_0286E8_SPI_TMPRING_SIZE
:
5952 case R_00B860_COMPUTE_TMPRING_SIZE
:
5953 /* WAVESIZE is in units of 256 dwords. */
5954 if (really_needs_scratch
)
5955 conf
->scratch_bytes_per_wave
=
5956 G_00B860_WAVESIZE(value
) * 256 * 4;
5960 static bool printed
;
5963 fprintf(stderr
, "Warning: LLVM emitted unknown "
5964 "config register: 0x%x\n", reg
);
5971 if (!conf
->spi_ps_input_addr
)
5972 conf
->spi_ps_input_addr
= conf
->spi_ps_input_ena
;
5976 void si_shader_apply_scratch_relocs(struct si_context
*sctx
,
5977 struct si_shader
*shader
,
5978 struct si_shader_config
*config
,
5979 uint64_t scratch_va
)
5982 uint32_t scratch_rsrc_dword0
= scratch_va
;
5983 uint32_t scratch_rsrc_dword1
=
5984 S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32);
5986 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
5989 if (HAVE_LLVM
>= 0x0309)
5990 scratch_rsrc_dword1
|= S_008F04_SWIZZLE_ENABLE(1);
5992 scratch_rsrc_dword1
|=
5993 S_008F04_STRIDE(config
->scratch_bytes_per_wave
/ 64);
5995 for (i
= 0 ; i
< shader
->binary
.reloc_count
; i
++) {
5996 const struct radeon_shader_reloc
*reloc
=
5997 &shader
->binary
.relocs
[i
];
5998 if (!strcmp(scratch_rsrc_dword0_symbol
, reloc
->name
)) {
5999 util_memcpy_cpu_to_le32(shader
->binary
.code
+ reloc
->offset
,
6000 &scratch_rsrc_dword0
, 4);
6001 } else if (!strcmp(scratch_rsrc_dword1_symbol
, reloc
->name
)) {
6002 util_memcpy_cpu_to_le32(shader
->binary
.code
+ reloc
->offset
,
6003 &scratch_rsrc_dword1
, 4);
6008 static unsigned si_get_shader_binary_size(struct si_shader
*shader
)
6010 unsigned size
= shader
->binary
.code_size
;
6013 size
+= shader
->prolog
->binary
.code_size
;
6015 size
+= shader
->epilog
->binary
.code_size
;
6019 int si_shader_binary_upload(struct si_screen
*sscreen
, struct si_shader
*shader
)
6021 const struct radeon_shader_binary
*prolog
=
6022 shader
->prolog
? &shader
->prolog
->binary
: NULL
;
6023 const struct radeon_shader_binary
*epilog
=
6024 shader
->epilog
? &shader
->epilog
->binary
: NULL
;
6025 const struct radeon_shader_binary
*mainb
= &shader
->binary
;
6026 unsigned bo_size
= si_get_shader_binary_size(shader
) +
6027 (!epilog
? mainb
->rodata_size
: 0);
6030 assert(!prolog
|| !prolog
->rodata_size
);
6031 assert((!prolog
&& !epilog
) || !mainb
->rodata_size
);
6032 assert(!epilog
|| !epilog
->rodata_size
);
6034 r600_resource_reference(&shader
->bo
, NULL
);
6035 shader
->bo
= si_resource_create_custom(&sscreen
->b
.b
,
6036 PIPE_USAGE_IMMUTABLE
,
6042 ptr
= sscreen
->b
.ws
->buffer_map(shader
->bo
->buf
, NULL
,
6043 PIPE_TRANSFER_READ_WRITE
);
6046 util_memcpy_cpu_to_le32(ptr
, prolog
->code
, prolog
->code_size
);
6047 ptr
+= prolog
->code_size
;
6050 util_memcpy_cpu_to_le32(ptr
, mainb
->code
, mainb
->code_size
);
6051 ptr
+= mainb
->code_size
;
6054 util_memcpy_cpu_to_le32(ptr
, epilog
->code
, epilog
->code_size
);
6055 else if (mainb
->rodata_size
> 0)
6056 util_memcpy_cpu_to_le32(ptr
, mainb
->rodata
, mainb
->rodata_size
);
6058 sscreen
->b
.ws
->buffer_unmap(shader
->bo
->buf
);
6062 static void si_shader_dump_disassembly(const struct radeon_shader_binary
*binary
,
6063 struct pipe_debug_callback
*debug
,
6064 const char *name
, FILE *file
)
6069 if (binary
->disasm_string
) {
6070 fprintf(file
, "Shader %s disassembly:\n", name
);
6071 fprintf(file
, "%s", binary
->disasm_string
);
6073 if (debug
&& debug
->debug_message
) {
6074 /* Very long debug messages are cut off, so send the
6075 * disassembly one line at a time. This causes more
6076 * overhead, but on the plus side it simplifies
6077 * parsing of resulting logs.
6079 pipe_debug_message(debug
, SHADER_INFO
,
6080 "Shader Disassembly Begin");
6082 line
= binary
->disasm_string
;
6084 p
= util_strchrnul(line
, '\n');
6088 pipe_debug_message(debug
, SHADER_INFO
,
6089 "%.*s", count
, line
);
6097 pipe_debug_message(debug
, SHADER_INFO
,
6098 "Shader Disassembly End");
6101 fprintf(file
, "Shader %s binary:\n", name
);
6102 for (i
= 0; i
< binary
->code_size
; i
+= 4) {
6103 fprintf(file
, "@0x%x: %02x%02x%02x%02x\n", i
,
6104 binary
->code
[i
+ 3], binary
->code
[i
+ 2],
6105 binary
->code
[i
+ 1], binary
->code
[i
]);
6110 static void si_shader_dump_stats(struct si_screen
*sscreen
,
6111 struct si_shader_config
*conf
,
6112 unsigned num_inputs
,
6114 struct pipe_debug_callback
*debug
,
6118 unsigned lds_increment
= sscreen
->b
.chip_class
>= CIK
? 512 : 256;
6119 unsigned lds_per_wave
= 0;
6120 unsigned max_simd_waves
= 10;
6121 /* Assuming SGPRs aren't spilled. */
6122 unsigned spilled_vgprs
= conf
->scratch_bytes_per_wave
/ 64 / 4;
6124 /* Compute LDS usage for PS. */
6125 if (processor
== PIPE_SHADER_FRAGMENT
) {
6126 /* The minimum usage per wave is (num_inputs * 48). The maximum
6127 * usage is (num_inputs * 48 * 16).
6128 * We can get anything in between and it varies between waves.
6130 * The 48 bytes per input for a single primitive is equal to
6131 * 4 bytes/component * 4 components/input * 3 points.
6133 * Other stages don't know the size at compile time or don't
6134 * allocate LDS per wave, but instead they do it per thread group.
6136 lds_per_wave
= conf
->lds_size
* lds_increment
+
6137 align(num_inputs
* 48, lds_increment
);
6140 /* Compute the per-SIMD wave counts. */
6141 if (conf
->num_sgprs
) {
6142 if (sscreen
->b
.chip_class
>= VI
)
6143 max_simd_waves
= MIN2(max_simd_waves
, 800 / conf
->num_sgprs
);
6145 max_simd_waves
= MIN2(max_simd_waves
, 512 / conf
->num_sgprs
);
6148 if (conf
->num_vgprs
)
6149 max_simd_waves
= MIN2(max_simd_waves
, 256 / conf
->num_vgprs
);
6151 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
6155 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
6157 if (file
!= stderr
||
6158 r600_can_dump_shader(&sscreen
->b
, processor
)) {
6159 if (processor
== PIPE_SHADER_FRAGMENT
) {
6160 fprintf(file
, "*** SHADER CONFIG ***\n"
6161 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6162 "SPI_PS_INPUT_ENA = 0x%04x\n",
6163 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
6166 fprintf(file
, "*** SHADER STATS ***\n"
6169 "Spilled VGPRs: %d\n"
6170 "Code Size: %d bytes\n"
6172 "Scratch: %d bytes per wave\n"
6174 "********************\n",
6175 conf
->num_sgprs
, conf
->num_vgprs
, spilled_vgprs
, code_size
,
6176 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
6180 pipe_debug_message(debug
, SHADER_INFO
,
6181 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6182 "LDS: %d Scratch: %d Max Waves: %d Spilled VGPRs: %d",
6183 conf
->num_sgprs
, conf
->num_vgprs
, code_size
,
6184 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
6185 max_simd_waves
, spilled_vgprs
);
6188 static const char *si_get_shader_name(struct si_shader
*shader
,
6191 switch (processor
) {
6192 case PIPE_SHADER_VERTEX
:
6193 if (shader
->key
.vs
.as_es
)
6194 return "Vertex Shader as ES";
6195 else if (shader
->key
.vs
.as_ls
)
6196 return "Vertex Shader as LS";
6198 return "Vertex Shader as VS";
6199 case PIPE_SHADER_TESS_CTRL
:
6200 return "Tessellation Control Shader";
6201 case PIPE_SHADER_TESS_EVAL
:
6202 if (shader
->key
.tes
.as_es
)
6203 return "Tessellation Evaluation Shader as ES";
6205 return "Tessellation Evaluation Shader as VS";
6206 case PIPE_SHADER_GEOMETRY
:
6207 if (shader
->gs_copy_shader
== NULL
)
6208 return "GS Copy Shader as VS";
6210 return "Geometry Shader";
6211 case PIPE_SHADER_FRAGMENT
:
6212 return "Pixel Shader";
6213 case PIPE_SHADER_COMPUTE
:
6214 return "Compute Shader";
6216 return "Unknown Shader";
6220 void si_shader_dump(struct si_screen
*sscreen
, struct si_shader
*shader
,
6221 struct pipe_debug_callback
*debug
, unsigned processor
,
6224 if (file
!= stderr
&& shader
->binary
.llvm_ir_string
) {
6225 fprintf(file
, "\n%s - main shader part - LLVM IR:\n\n",
6226 si_get_shader_name(shader
, processor
));
6227 fprintf(file
, "%s\n", shader
->binary
.llvm_ir_string
);
6230 if (file
!= stderr
||
6231 (r600_can_dump_shader(&sscreen
->b
, processor
) &&
6232 !(sscreen
->b
.debug_flags
& DBG_NO_ASM
))) {
6233 fprintf(file
, "\n%s:\n", si_get_shader_name(shader
, processor
));
6236 si_shader_dump_disassembly(&shader
->prolog
->binary
,
6237 debug
, "prolog", file
);
6239 si_shader_dump_disassembly(&shader
->binary
, debug
, "main", file
);
6242 si_shader_dump_disassembly(&shader
->epilog
->binary
,
6243 debug
, "epilog", file
);
6244 fprintf(file
, "\n");
6247 si_shader_dump_stats(sscreen
, &shader
->config
,
6248 shader
->selector
? shader
->selector
->info
.num_inputs
: 0,
6249 si_get_shader_binary_size(shader
), debug
, processor
,
6253 int si_compile_llvm(struct si_screen
*sscreen
,
6254 struct radeon_shader_binary
*binary
,
6255 struct si_shader_config
*conf
,
6256 LLVMTargetMachineRef tm
,
6258 struct pipe_debug_callback
*debug
,
6263 unsigned count
= p_atomic_inc_return(&sscreen
->b
.num_compilations
);
6265 if (r600_can_dump_shader(&sscreen
->b
, processor
)) {
6266 fprintf(stderr
, "radeonsi: Compiling shader %d\n", count
);
6268 if (!(sscreen
->b
.debug_flags
& (DBG_NO_IR
| DBG_PREOPT_IR
))) {
6269 fprintf(stderr
, "%s LLVM IR:\n\n", name
);
6270 LLVMDumpModule(mod
);
6271 fprintf(stderr
, "\n");
6275 if (sscreen
->record_llvm_ir
) {
6276 char *ir
= LLVMPrintModuleToString(mod
);
6277 binary
->llvm_ir_string
= strdup(ir
);
6278 LLVMDisposeMessage(ir
);
6281 if (!si_replace_shader(count
, binary
)) {
6282 r
= radeon_llvm_compile(mod
, binary
, tm
, debug
);
6287 si_shader_binary_read_config(binary
, conf
, 0);
6289 /* Enable 64-bit and 16-bit denormals, because there is no performance
6292 * If denormals are enabled, all floating-point output modifiers are
6295 * Don't enable denormals for 32-bit floats, because:
6296 * - Floating-point output modifiers would be ignored by the hw.
6297 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6298 * have to stop using those.
6299 * - SI & CI would be very slow.
6301 conf
->float_mode
|= V_00B028_FP_64_DENORMS
;
6303 FREE(binary
->config
);
6304 FREE(binary
->global_symbol_offsets
);
6305 binary
->config
= NULL
;
6306 binary
->global_symbol_offsets
= NULL
;
6308 /* Some shaders can't have rodata because their binaries can be
6311 if (binary
->rodata_size
&&
6312 (processor
== PIPE_SHADER_VERTEX
||
6313 processor
== PIPE_SHADER_TESS_CTRL
||
6314 processor
== PIPE_SHADER_TESS_EVAL
||
6315 processor
== PIPE_SHADER_FRAGMENT
)) {
6316 fprintf(stderr
, "radeonsi: The shader can't have rodata.");
6323 static void si_llvm_build_ret(struct si_shader_context
*ctx
, LLVMValueRef ret
)
6325 if (LLVMGetTypeKind(LLVMTypeOf(ret
)) == LLVMVoidTypeKind
)
6326 LLVMBuildRetVoid(ctx
->radeon_bld
.gallivm
.builder
);
6328 LLVMBuildRet(ctx
->radeon_bld
.gallivm
.builder
, ret
);
6331 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6332 static int si_generate_gs_copy_shader(struct si_screen
*sscreen
,
6333 struct si_shader_context
*ctx
,
6334 struct si_shader
*gs
,
6335 struct pipe_debug_callback
*debug
)
6337 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
6338 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
6339 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
6340 struct si_shader_output_values
*outputs
;
6341 struct tgsi_shader_info
*gsinfo
= &gs
->selector
->info
;
6342 LLVMValueRef args
[9];
6345 outputs
= MALLOC(gsinfo
->num_outputs
* sizeof(outputs
[0]));
6347 si_init_shader_ctx(ctx
, sscreen
, ctx
->shader
, ctx
->tm
);
6348 ctx
->type
= PIPE_SHADER_VERTEX
;
6349 ctx
->is_gs_copy_shader
= true;
6351 create_meta_data(ctx
);
6352 create_function(ctx
);
6353 preload_streamout_buffers(ctx
);
6354 preload_ring_buffers(ctx
);
6356 args
[0] = ctx
->gsvs_ring
[0];
6357 args
[1] = lp_build_mul_imm(uint
,
6358 LLVMGetParam(ctx
->radeon_bld
.main_fn
,
6359 ctx
->param_vertex_id
),
6361 args
[3] = uint
->zero
;
6362 args
[4] = uint
->one
; /* OFFEN */
6363 args
[5] = uint
->zero
; /* IDXEN */
6364 args
[6] = uint
->one
; /* GLC */
6365 args
[7] = uint
->one
; /* SLC */
6366 args
[8] = uint
->zero
; /* TFE */
6368 /* Fetch vertex data from GSVS ring */
6369 for (i
= 0; i
< gsinfo
->num_outputs
; ++i
) {
6372 outputs
[i
].name
= gsinfo
->output_semantic_name
[i
];
6373 outputs
[i
].sid
= gsinfo
->output_semantic_index
[i
];
6375 for (chan
= 0; chan
< 4; chan
++) {
6376 args
[2] = lp_build_const_int32(gallivm
,
6378 gs
->selector
->gs_max_out_vertices
* 16 * 4);
6380 outputs
[i
].values
[chan
] =
6381 LLVMBuildBitCast(gallivm
->builder
,
6382 lp_build_intrinsic(gallivm
->builder
,
6383 "llvm.SI.buffer.load.dword.i32.i32",
6385 LLVMReadOnlyAttribute
),
6390 si_llvm_export_vs(bld_base
, outputs
, gsinfo
->num_outputs
);
6392 LLVMBuildRetVoid(gallivm
->builder
);
6394 /* Dump LLVM IR before any optimization passes */
6395 if (sscreen
->b
.debug_flags
& DBG_PREOPT_IR
&&
6396 r600_can_dump_shader(&sscreen
->b
, PIPE_SHADER_GEOMETRY
))
6397 LLVMDumpModule(bld_base
->base
.gallivm
->module
);
6399 radeon_llvm_finalize_module(&ctx
->radeon_bld
);
6401 r
= si_compile_llvm(sscreen
, &ctx
->shader
->binary
,
6402 &ctx
->shader
->config
, ctx
->tm
,
6403 bld_base
->base
.gallivm
->module
,
6404 debug
, PIPE_SHADER_GEOMETRY
,
6407 if (r600_can_dump_shader(&sscreen
->b
, PIPE_SHADER_GEOMETRY
))
6408 fprintf(stderr
, "GS Copy Shader:\n");
6409 si_shader_dump(sscreen
, ctx
->shader
, debug
,
6410 PIPE_SHADER_GEOMETRY
, stderr
);
6411 r
= si_shader_binary_upload(sscreen
, ctx
->shader
);
6414 radeon_llvm_dispose(&ctx
->radeon_bld
);
6420 void si_dump_shader_key(unsigned shader
, union si_shader_key
*key
, FILE *f
)
6424 fprintf(f
, "SHADER KEY\n");
6427 case PIPE_SHADER_VERTEX
:
6428 fprintf(f
, " instance_divisors = {");
6429 for (i
= 0; i
< ARRAY_SIZE(key
->vs
.prolog
.instance_divisors
); i
++)
6430 fprintf(f
, !i
? "%u" : ", %u",
6431 key
->vs
.prolog
.instance_divisors
[i
]);
6433 fprintf(f
, " as_es = %u\n", key
->vs
.as_es
);
6434 fprintf(f
, " as_ls = %u\n", key
->vs
.as_ls
);
6435 fprintf(f
, " export_prim_id = %u\n", key
->vs
.epilog
.export_prim_id
);
6438 case PIPE_SHADER_TESS_CTRL
:
6439 fprintf(f
, " prim_mode = %u\n", key
->tcs
.epilog
.prim_mode
);
6442 case PIPE_SHADER_TESS_EVAL
:
6443 fprintf(f
, " as_es = %u\n", key
->tes
.as_es
);
6444 fprintf(f
, " export_prim_id = %u\n", key
->tes
.epilog
.export_prim_id
);
6447 case PIPE_SHADER_GEOMETRY
:
6448 case PIPE_SHADER_COMPUTE
:
6451 case PIPE_SHADER_FRAGMENT
:
6452 fprintf(f
, " prolog.color_two_side = %u\n", key
->ps
.prolog
.color_two_side
);
6453 fprintf(f
, " prolog.flatshade_colors = %u\n", key
->ps
.prolog
.flatshade_colors
);
6454 fprintf(f
, " prolog.poly_stipple = %u\n", key
->ps
.prolog
.poly_stipple
);
6455 fprintf(f
, " prolog.force_persp_sample_interp = %u\n", key
->ps
.prolog
.force_persp_sample_interp
);
6456 fprintf(f
, " prolog.force_linear_sample_interp = %u\n", key
->ps
.prolog
.force_linear_sample_interp
);
6457 fprintf(f
, " prolog.force_persp_center_interp = %u\n", key
->ps
.prolog
.force_persp_center_interp
);
6458 fprintf(f
, " prolog.force_linear_center_interp = %u\n", key
->ps
.prolog
.force_linear_center_interp
);
6459 fprintf(f
, " prolog.bc_optimize_for_persp = %u\n", key
->ps
.prolog
.bc_optimize_for_persp
);
6460 fprintf(f
, " prolog.bc_optimize_for_linear = %u\n", key
->ps
.prolog
.bc_optimize_for_linear
);
6461 fprintf(f
, " epilog.spi_shader_col_format = 0x%x\n", key
->ps
.epilog
.spi_shader_col_format
);
6462 fprintf(f
, " epilog.color_is_int8 = 0x%X\n", key
->ps
.epilog
.color_is_int8
);
6463 fprintf(f
, " epilog.last_cbuf = %u\n", key
->ps
.epilog
.last_cbuf
);
6464 fprintf(f
, " epilog.alpha_func = %u\n", key
->ps
.epilog
.alpha_func
);
6465 fprintf(f
, " epilog.alpha_to_one = %u\n", key
->ps
.epilog
.alpha_to_one
);
6466 fprintf(f
, " epilog.poly_line_smoothing = %u\n", key
->ps
.epilog
.poly_line_smoothing
);
6467 fprintf(f
, " epilog.clamp_color = %u\n", key
->ps
.epilog
.clamp_color
);
6475 static void si_init_shader_ctx(struct si_shader_context
*ctx
,
6476 struct si_screen
*sscreen
,
6477 struct si_shader
*shader
,
6478 LLVMTargetMachineRef tm
)
6480 struct lp_build_tgsi_context
*bld_base
;
6481 struct lp_build_tgsi_action tmpl
= {};
6483 memset(ctx
, 0, sizeof(*ctx
));
6484 radeon_llvm_context_init(&ctx
->radeon_bld
, "amdgcn--");
6486 ctx
->screen
= sscreen
;
6487 if (shader
&& shader
->selector
)
6488 ctx
->type
= shader
->selector
->info
.processor
;
6491 ctx
->shader
= shader
;
6493 ctx
->voidt
= LLVMVoidTypeInContext(ctx
->radeon_bld
.gallivm
.context
);
6494 ctx
->i1
= LLVMInt1TypeInContext(ctx
->radeon_bld
.gallivm
.context
);
6495 ctx
->i8
= LLVMInt8TypeInContext(ctx
->radeon_bld
.gallivm
.context
);
6496 ctx
->i32
= LLVMInt32TypeInContext(ctx
->radeon_bld
.gallivm
.context
);
6497 ctx
->i64
= LLVMInt64TypeInContext(ctx
->radeon_bld
.gallivm
.context
);
6498 ctx
->i128
= LLVMIntTypeInContext(ctx
->radeon_bld
.gallivm
.context
, 128);
6499 ctx
->f32
= LLVMFloatTypeInContext(ctx
->radeon_bld
.gallivm
.context
);
6500 ctx
->v16i8
= LLVMVectorType(ctx
->i8
, 16);
6501 ctx
->v2i32
= LLVMVectorType(ctx
->i32
, 2);
6502 ctx
->v4i32
= LLVMVectorType(ctx
->i32
, 4);
6503 ctx
->v4f32
= LLVMVectorType(ctx
->f32
, 4);
6504 ctx
->v8i32
= LLVMVectorType(ctx
->i32
, 8);
6506 bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
6507 if (shader
&& shader
->selector
)
6508 bld_base
->info
= &shader
->selector
->info
;
6509 bld_base
->emit_fetch_funcs
[TGSI_FILE_CONSTANT
] = fetch_constant
;
6511 bld_base
->op_actions
[TGSI_OPCODE_INTERP_CENTROID
] = interp_action
;
6512 bld_base
->op_actions
[TGSI_OPCODE_INTERP_SAMPLE
] = interp_action
;
6513 bld_base
->op_actions
[TGSI_OPCODE_INTERP_OFFSET
] = interp_action
;
6515 bld_base
->op_actions
[TGSI_OPCODE_TEX
] = tex_action
;
6516 bld_base
->op_actions
[TGSI_OPCODE_TEX2
] = tex_action
;
6517 bld_base
->op_actions
[TGSI_OPCODE_TXB
] = tex_action
;
6518 bld_base
->op_actions
[TGSI_OPCODE_TXB2
] = tex_action
;
6519 bld_base
->op_actions
[TGSI_OPCODE_TXD
] = tex_action
;
6520 bld_base
->op_actions
[TGSI_OPCODE_TXF
] = tex_action
;
6521 bld_base
->op_actions
[TGSI_OPCODE_TXL
] = tex_action
;
6522 bld_base
->op_actions
[TGSI_OPCODE_TXL2
] = tex_action
;
6523 bld_base
->op_actions
[TGSI_OPCODE_TXP
] = tex_action
;
6524 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].fetch_args
= txq_fetch_args
;
6525 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].emit
= txq_emit
;
6526 bld_base
->op_actions
[TGSI_OPCODE_TG4
] = tex_action
;
6527 bld_base
->op_actions
[TGSI_OPCODE_LODQ
] = tex_action
;
6528 bld_base
->op_actions
[TGSI_OPCODE_TXQS
].emit
= si_llvm_emit_txqs
;
6530 bld_base
->op_actions
[TGSI_OPCODE_LOAD
].fetch_args
= load_fetch_args
;
6531 bld_base
->op_actions
[TGSI_OPCODE_LOAD
].emit
= load_emit
;
6532 bld_base
->op_actions
[TGSI_OPCODE_STORE
].fetch_args
= store_fetch_args
;
6533 bld_base
->op_actions
[TGSI_OPCODE_STORE
].emit
= store_emit
;
6534 bld_base
->op_actions
[TGSI_OPCODE_RESQ
].fetch_args
= resq_fetch_args
;
6535 bld_base
->op_actions
[TGSI_OPCODE_RESQ
].emit
= resq_emit
;
6537 tmpl
.fetch_args
= atomic_fetch_args
;
6538 tmpl
.emit
= atomic_emit
;
6539 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
] = tmpl
;
6540 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
].intr_name
= "add";
6541 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
] = tmpl
;
6542 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
].intr_name
= "swap";
6543 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
] = tmpl
;
6544 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
].intr_name
= "cmpswap";
6545 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
] = tmpl
;
6546 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
].intr_name
= "and";
6547 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
] = tmpl
;
6548 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
].intr_name
= "or";
6549 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
] = tmpl
;
6550 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
].intr_name
= "xor";
6551 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
] = tmpl
;
6552 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
].intr_name
= "umin";
6553 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
] = tmpl
;
6554 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
].intr_name
= "umax";
6555 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
] = tmpl
;
6556 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
].intr_name
= "smin";
6557 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
] = tmpl
;
6558 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
].intr_name
= "smax";
6560 bld_base
->op_actions
[TGSI_OPCODE_MEMBAR
].emit
= membar_emit
;
6562 bld_base
->op_actions
[TGSI_OPCODE_DDX
].emit
= si_llvm_emit_ddxy
;
6563 bld_base
->op_actions
[TGSI_OPCODE_DDY
].emit
= si_llvm_emit_ddxy
;
6564 bld_base
->op_actions
[TGSI_OPCODE_DDX_FINE
].emit
= si_llvm_emit_ddxy
;
6565 bld_base
->op_actions
[TGSI_OPCODE_DDY_FINE
].emit
= si_llvm_emit_ddxy
;
6567 bld_base
->op_actions
[TGSI_OPCODE_EMIT
].emit
= si_llvm_emit_vertex
;
6568 bld_base
->op_actions
[TGSI_OPCODE_ENDPRIM
].emit
= si_llvm_emit_primitive
;
6569 bld_base
->op_actions
[TGSI_OPCODE_BARRIER
].emit
= si_llvm_emit_barrier
;
6571 bld_base
->op_actions
[TGSI_OPCODE_MAX
].emit
= build_tgsi_intrinsic_nomem
;
6572 bld_base
->op_actions
[TGSI_OPCODE_MAX
].intr_name
= "llvm.maxnum.f32";
6573 bld_base
->op_actions
[TGSI_OPCODE_MIN
].emit
= build_tgsi_intrinsic_nomem
;
6574 bld_base
->op_actions
[TGSI_OPCODE_MIN
].intr_name
= "llvm.minnum.f32";
6577 int si_compile_tgsi_shader(struct si_screen
*sscreen
,
6578 LLVMTargetMachineRef tm
,
6579 struct si_shader
*shader
,
6581 struct pipe_debug_callback
*debug
)
6583 struct si_shader_selector
*sel
= shader
->selector
;
6584 struct si_shader_context ctx
;
6585 struct lp_build_tgsi_context
*bld_base
;
6589 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6590 * conversion fails. */
6591 if (r600_can_dump_shader(&sscreen
->b
, sel
->info
.processor
) &&
6592 !(sscreen
->b
.debug_flags
& DBG_NO_TGSI
)) {
6594 si_dump_shader_key(sel
->type
, &shader
->key
, stderr
);
6595 tgsi_dump(sel
->tokens
, 0);
6596 si_dump_streamout(&sel
->so
);
6599 si_init_shader_ctx(&ctx
, sscreen
, shader
, tm
);
6600 ctx
.is_monolithic
= is_monolithic
;
6602 shader
->info
.uses_instanceid
= sel
->info
.uses_instanceid
;
6604 bld_base
= &ctx
.radeon_bld
.soa
.bld_base
;
6605 ctx
.radeon_bld
.load_system_value
= declare_system_value
;
6608 case PIPE_SHADER_VERTEX
:
6609 ctx
.radeon_bld
.load_input
= declare_input_vs
;
6610 if (shader
->key
.vs
.as_ls
)
6611 bld_base
->emit_epilogue
= si_llvm_emit_ls_epilogue
;
6612 else if (shader
->key
.vs
.as_es
)
6613 bld_base
->emit_epilogue
= si_llvm_emit_es_epilogue
;
6615 bld_base
->emit_epilogue
= si_llvm_emit_vs_epilogue
;
6617 case PIPE_SHADER_TESS_CTRL
:
6618 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_tcs
;
6619 bld_base
->emit_fetch_funcs
[TGSI_FILE_OUTPUT
] = fetch_output_tcs
;
6620 bld_base
->emit_store
= store_output_tcs
;
6621 bld_base
->emit_epilogue
= si_llvm_emit_tcs_epilogue
;
6623 case PIPE_SHADER_TESS_EVAL
:
6624 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_tes
;
6625 if (shader
->key
.tes
.as_es
)
6626 bld_base
->emit_epilogue
= si_llvm_emit_es_epilogue
;
6628 bld_base
->emit_epilogue
= si_llvm_emit_vs_epilogue
;
6630 case PIPE_SHADER_GEOMETRY
:
6631 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_gs
;
6632 bld_base
->emit_epilogue
= si_llvm_emit_gs_epilogue
;
6634 case PIPE_SHADER_FRAGMENT
:
6635 ctx
.radeon_bld
.load_input
= declare_input_fs
;
6637 bld_base
->emit_epilogue
= si_llvm_emit_fs_epilogue
;
6639 bld_base
->emit_epilogue
= si_llvm_return_fs_outputs
;
6641 case PIPE_SHADER_COMPUTE
:
6642 ctx
.radeon_bld
.declare_memory_region
= declare_compute_memory
;
6645 assert(!"Unsupported shader type");
6649 create_meta_data(&ctx
);
6650 create_function(&ctx
);
6651 preload_constants(&ctx
);
6652 preload_shader_buffers(&ctx
);
6653 preload_samplers(&ctx
);
6654 preload_images(&ctx
);
6655 preload_streamout_buffers(&ctx
);
6656 preload_ring_buffers(&ctx
);
6658 if (ctx
.is_monolithic
&& sel
->type
== PIPE_SHADER_FRAGMENT
&&
6659 shader
->key
.ps
.prolog
.poly_stipple
) {
6660 LLVMValueRef list
= LLVMGetParam(ctx
.radeon_bld
.main_fn
,
6661 SI_PARAM_RW_BUFFERS
);
6662 si_llvm_emit_polygon_stipple(&ctx
, list
,
6663 SI_PARAM_POS_FIXED_PT
);
6666 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
6668 for (i
= 0; i
< 4; i
++) {
6669 ctx
.gs_next_vertex
[i
] =
6670 lp_build_alloca(bld_base
->base
.gallivm
,
6675 if (!lp_build_tgsi_llvm(bld_base
, sel
->tokens
)) {
6676 fprintf(stderr
, "Failed to translate shader from TGSI to LLVM\n");
6680 si_llvm_build_ret(&ctx
, ctx
.return_value
);
6681 mod
= bld_base
->base
.gallivm
->module
;
6683 /* Dump LLVM IR before any optimization passes */
6684 if (sscreen
->b
.debug_flags
& DBG_PREOPT_IR
&&
6685 r600_can_dump_shader(&sscreen
->b
, ctx
.type
))
6686 LLVMDumpModule(mod
);
6688 radeon_llvm_finalize_module(&ctx
.radeon_bld
);
6690 r
= si_compile_llvm(sscreen
, &shader
->binary
, &shader
->config
, tm
,
6691 mod
, debug
, ctx
.type
, "TGSI shader");
6693 fprintf(stderr
, "LLVM failed to compile shader\n");
6697 radeon_llvm_dispose(&ctx
.radeon_bld
);
6699 /* Add the scratch offset to input SGPRs. */
6700 if (shader
->config
.scratch_bytes_per_wave
)
6701 shader
->info
.num_input_sgprs
+= 1; /* scratch byte offset */
6703 /* Calculate the number of fragment input VGPRs. */
6704 if (ctx
.type
== PIPE_SHADER_FRAGMENT
) {
6705 shader
->info
.num_input_vgprs
= 0;
6706 shader
->info
.face_vgpr_index
= -1;
6708 if (G_0286CC_PERSP_SAMPLE_ENA(shader
->config
.spi_ps_input_addr
))
6709 shader
->info
.num_input_vgprs
+= 2;
6710 if (G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_addr
))
6711 shader
->info
.num_input_vgprs
+= 2;
6712 if (G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_addr
))
6713 shader
->info
.num_input_vgprs
+= 2;
6714 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader
->config
.spi_ps_input_addr
))
6715 shader
->info
.num_input_vgprs
+= 3;
6716 if (G_0286CC_LINEAR_SAMPLE_ENA(shader
->config
.spi_ps_input_addr
))
6717 shader
->info
.num_input_vgprs
+= 2;
6718 if (G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_addr
))
6719 shader
->info
.num_input_vgprs
+= 2;
6720 if (G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_addr
))
6721 shader
->info
.num_input_vgprs
+= 2;
6722 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader
->config
.spi_ps_input_addr
))
6723 shader
->info
.num_input_vgprs
+= 1;
6724 if (G_0286CC_POS_X_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
6725 shader
->info
.num_input_vgprs
+= 1;
6726 if (G_0286CC_POS_Y_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
6727 shader
->info
.num_input_vgprs
+= 1;
6728 if (G_0286CC_POS_Z_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
6729 shader
->info
.num_input_vgprs
+= 1;
6730 if (G_0286CC_POS_W_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
6731 shader
->info
.num_input_vgprs
+= 1;
6732 if (G_0286CC_FRONT_FACE_ENA(shader
->config
.spi_ps_input_addr
)) {
6733 shader
->info
.face_vgpr_index
= shader
->info
.num_input_vgprs
;
6734 shader
->info
.num_input_vgprs
+= 1;
6736 if (G_0286CC_ANCILLARY_ENA(shader
->config
.spi_ps_input_addr
))
6737 shader
->info
.num_input_vgprs
+= 1;
6738 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader
->config
.spi_ps_input_addr
))
6739 shader
->info
.num_input_vgprs
+= 1;
6740 if (G_0286CC_POS_FIXED_PT_ENA(shader
->config
.spi_ps_input_addr
))
6741 shader
->info
.num_input_vgprs
+= 1;
6744 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
6745 shader
->gs_copy_shader
= CALLOC_STRUCT(si_shader
);
6746 shader
->gs_copy_shader
->selector
= shader
->selector
;
6747 ctx
.shader
= shader
->gs_copy_shader
;
6748 if ((r
= si_generate_gs_copy_shader(sscreen
, &ctx
,
6750 free(shader
->gs_copy_shader
);
6751 shader
->gs_copy_shader
= NULL
;
6757 for (int i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++)
6758 FREE(ctx
.constants
[i
]);
6763 * Create, compile and return a shader part (prolog or epilog).
6765 * \param sscreen screen
6766 * \param list list of shader parts of the same category
6767 * \param key shader part key
6768 * \param tm LLVM target machine
6769 * \param debug debug callback
6770 * \param compile the callback responsible for compilation
6771 * \return non-NULL on success
6773 static struct si_shader_part
*
6774 si_get_shader_part(struct si_screen
*sscreen
,
6775 struct si_shader_part
**list
,
6776 union si_shader_part_key
*key
,
6777 LLVMTargetMachineRef tm
,
6778 struct pipe_debug_callback
*debug
,
6779 bool (*compile
)(struct si_screen
*,
6780 LLVMTargetMachineRef
,
6781 struct pipe_debug_callback
*,
6782 struct si_shader_part
*))
6784 struct si_shader_part
*result
;
6786 pipe_mutex_lock(sscreen
->shader_parts_mutex
);
6788 /* Find existing. */
6789 for (result
= *list
; result
; result
= result
->next
) {
6790 if (memcmp(&result
->key
, key
, sizeof(*key
)) == 0) {
6791 pipe_mutex_unlock(sscreen
->shader_parts_mutex
);
6796 /* Compile a new one. */
6797 result
= CALLOC_STRUCT(si_shader_part
);
6799 if (!compile(sscreen
, tm
, debug
, result
)) {
6801 pipe_mutex_unlock(sscreen
->shader_parts_mutex
);
6805 result
->next
= *list
;
6807 pipe_mutex_unlock(sscreen
->shader_parts_mutex
);
6812 * Create a vertex shader prolog.
6814 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6815 * All inputs are returned unmodified. The vertex load indices are
6816 * stored after them, which will used by the API VS for fetching inputs.
6818 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6823 * (VertexID + BaseVertex),
6824 * (InstanceID + StartInstance),
6825 * (InstanceID / 2 + StartInstance)
6827 static bool si_compile_vs_prolog(struct si_screen
*sscreen
,
6828 LLVMTargetMachineRef tm
,
6829 struct pipe_debug_callback
*debug
,
6830 struct si_shader_part
*out
)
6832 union si_shader_part_key
*key
= &out
->key
;
6833 struct si_shader shader
= {};
6834 struct si_shader_context ctx
;
6835 struct gallivm_state
*gallivm
= &ctx
.radeon_bld
.gallivm
;
6836 LLVMTypeRef
*params
, *returns
;
6837 LLVMValueRef ret
, func
;
6838 int last_sgpr
, num_params
, num_returns
, i
;
6841 si_init_shader_ctx(&ctx
, sscreen
, &shader
, tm
);
6842 ctx
.type
= PIPE_SHADER_VERTEX
;
6843 ctx
.param_vertex_id
= key
->vs_prolog
.num_input_sgprs
;
6844 ctx
.param_instance_id
= key
->vs_prolog
.num_input_sgprs
+ 3;
6846 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6847 params
= alloca((key
->vs_prolog
.num_input_sgprs
+ 4) *
6848 sizeof(LLVMTypeRef
));
6849 returns
= alloca((key
->vs_prolog
.num_input_sgprs
+ 4 +
6850 key
->vs_prolog
.last_input
+ 1) *
6851 sizeof(LLVMTypeRef
));
6855 /* Declare input and output SGPRs. */
6857 for (i
= 0; i
< key
->vs_prolog
.num_input_sgprs
; i
++) {
6858 params
[num_params
++] = ctx
.i32
;
6859 returns
[num_returns
++] = ctx
.i32
;
6861 last_sgpr
= num_params
- 1;
6863 /* 4 preloaded VGPRs (outputs must be floats) */
6864 for (i
= 0; i
< 4; i
++) {
6865 params
[num_params
++] = ctx
.i32
;
6866 returns
[num_returns
++] = ctx
.f32
;
6869 /* Vertex load indices. */
6870 for (i
= 0; i
<= key
->vs_prolog
.last_input
; i
++)
6871 returns
[num_returns
++] = ctx
.f32
;
6873 /* Create the function. */
6874 si_create_function(&ctx
, returns
, num_returns
, params
,
6875 num_params
, -1, last_sgpr
);
6876 func
= ctx
.radeon_bld
.main_fn
;
6878 /* Copy inputs to outputs. This should be no-op, as the registers match,
6879 * but it will prevent the compiler from overwriting them unintentionally.
6881 ret
= ctx
.return_value
;
6882 for (i
= 0; i
< key
->vs_prolog
.num_input_sgprs
; i
++) {
6883 LLVMValueRef p
= LLVMGetParam(func
, i
);
6884 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
, p
, i
, "");
6886 for (i
= num_params
- 4; i
< num_params
; i
++) {
6887 LLVMValueRef p
= LLVMGetParam(func
, i
);
6888 p
= LLVMBuildBitCast(gallivm
->builder
, p
, ctx
.f32
, "");
6889 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
, p
, i
, "");
6892 /* Compute vertex load indices from instance divisors. */
6893 for (i
= 0; i
<= key
->vs_prolog
.last_input
; i
++) {
6894 unsigned divisor
= key
->vs_prolog
.states
.instance_divisors
[i
];
6898 /* InstanceID / Divisor + StartInstance */
6899 index
= get_instance_index_for_fetch(&ctx
.radeon_bld
,
6900 SI_SGPR_START_INSTANCE
,
6903 /* VertexID + BaseVertex */
6904 index
= LLVMBuildAdd(gallivm
->builder
,
6905 LLVMGetParam(func
, ctx
.param_vertex_id
),
6906 LLVMGetParam(func
, SI_SGPR_BASE_VERTEX
), "");
6909 index
= LLVMBuildBitCast(gallivm
->builder
, index
, ctx
.f32
, "");
6910 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
, index
,
6915 si_llvm_build_ret(&ctx
, ret
);
6916 radeon_llvm_finalize_module(&ctx
.radeon_bld
);
6918 if (si_compile_llvm(sscreen
, &out
->binary
, &out
->config
, tm
,
6919 gallivm
->module
, debug
, ctx
.type
,
6920 "Vertex Shader Prolog"))
6923 radeon_llvm_dispose(&ctx
.radeon_bld
);
6928 * Compile the vertex shader epilog. This is also used by the tessellation
6929 * evaluation shader compiled as VS.
6931 * The input is PrimitiveID.
6933 * If PrimitiveID is required by the pixel shader, export it.
6934 * Otherwise, do nothing.
6936 static bool si_compile_vs_epilog(struct si_screen
*sscreen
,
6937 LLVMTargetMachineRef tm
,
6938 struct pipe_debug_callback
*debug
,
6939 struct si_shader_part
*out
)
6941 union si_shader_part_key
*key
= &out
->key
;
6942 struct si_shader_context ctx
;
6943 struct gallivm_state
*gallivm
= &ctx
.radeon_bld
.gallivm
;
6944 struct lp_build_tgsi_context
*bld_base
= &ctx
.radeon_bld
.soa
.bld_base
;
6945 LLVMTypeRef params
[5];
6949 si_init_shader_ctx(&ctx
, sscreen
, NULL
, tm
);
6950 ctx
.type
= PIPE_SHADER_VERTEX
;
6952 /* Declare input VGPRs. */
6953 num_params
= key
->vs_epilog
.states
.export_prim_id
?
6954 (VS_EPILOG_PRIMID_LOC
+ 1) : 0;
6955 assert(num_params
<= ARRAY_SIZE(params
));
6957 for (i
= 0; i
< num_params
; i
++)
6958 params
[i
] = ctx
.f32
;
6960 /* Create the function. */
6961 si_create_function(&ctx
, NULL
, 0, params
, num_params
,
6965 if (key
->vs_epilog
.states
.export_prim_id
) {
6966 struct lp_build_context
*base
= &bld_base
->base
;
6967 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
6968 LLVMValueRef args
[9];
6970 args
[0] = lp_build_const_int32(base
->gallivm
, 0x0); /* enabled channels */
6971 args
[1] = uint
->zero
; /* whether the EXEC mask is valid */
6972 args
[2] = uint
->zero
; /* DONE bit */
6973 args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_PARAM
+
6974 key
->vs_epilog
.prim_id_param_offset
);
6975 args
[4] = uint
->zero
; /* COMPR flag (0 = 32-bit export) */
6976 args
[5] = LLVMGetParam(ctx
.radeon_bld
.main_fn
,
6977 VS_EPILOG_PRIMID_LOC
); /* X */
6978 args
[6] = uint
->undef
; /* Y */
6979 args
[7] = uint
->undef
; /* Z */
6980 args
[8] = uint
->undef
; /* W */
6982 lp_build_intrinsic(base
->gallivm
->builder
, "llvm.SI.export",
6983 LLVMVoidTypeInContext(base
->gallivm
->context
),
6988 LLVMBuildRetVoid(gallivm
->builder
);
6989 radeon_llvm_finalize_module(&ctx
.radeon_bld
);
6991 if (si_compile_llvm(sscreen
, &out
->binary
, &out
->config
, tm
,
6992 gallivm
->module
, debug
, ctx
.type
,
6993 "Vertex Shader Epilog"))
6996 radeon_llvm_dispose(&ctx
.radeon_bld
);
7001 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7003 static bool si_get_vs_epilog(struct si_screen
*sscreen
,
7004 LLVMTargetMachineRef tm
,
7005 struct si_shader
*shader
,
7006 struct pipe_debug_callback
*debug
,
7007 struct si_vs_epilog_bits
*states
)
7009 union si_shader_part_key epilog_key
;
7011 memset(&epilog_key
, 0, sizeof(epilog_key
));
7012 epilog_key
.vs_epilog
.states
= *states
;
7014 /* Set up the PrimitiveID output. */
7015 if (shader
->key
.vs
.epilog
.export_prim_id
) {
7016 unsigned index
= shader
->selector
->info
.num_outputs
;
7017 unsigned offset
= shader
->info
.nr_param_exports
++;
7019 epilog_key
.vs_epilog
.prim_id_param_offset
= offset
;
7020 assert(index
< ARRAY_SIZE(shader
->info
.vs_output_param_offset
));
7021 shader
->info
.vs_output_param_offset
[index
] = offset
;
7024 shader
->epilog
= si_get_shader_part(sscreen
, &sscreen
->vs_epilogs
,
7025 &epilog_key
, tm
, debug
,
7026 si_compile_vs_epilog
);
7027 return shader
->epilog
!= NULL
;
7031 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7033 static bool si_shader_select_vs_parts(struct si_screen
*sscreen
,
7034 LLVMTargetMachineRef tm
,
7035 struct si_shader
*shader
,
7036 struct pipe_debug_callback
*debug
)
7038 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
7039 union si_shader_part_key prolog_key
;
7042 /* Get the prolog. */
7043 memset(&prolog_key
, 0, sizeof(prolog_key
));
7044 prolog_key
.vs_prolog
.states
= shader
->key
.vs
.prolog
;
7045 prolog_key
.vs_prolog
.num_input_sgprs
= shader
->info
.num_input_sgprs
;
7046 prolog_key
.vs_prolog
.last_input
= MAX2(1, info
->num_inputs
) - 1;
7048 /* The prolog is a no-op if there are no inputs. */
7049 if (info
->num_inputs
) {
7051 si_get_shader_part(sscreen
, &sscreen
->vs_prologs
,
7052 &prolog_key
, tm
, debug
,
7053 si_compile_vs_prolog
);
7054 if (!shader
->prolog
)
7058 /* Get the epilog. */
7059 if (!shader
->key
.vs
.as_es
&& !shader
->key
.vs
.as_ls
&&
7060 !si_get_vs_epilog(sscreen
, tm
, shader
, debug
,
7061 &shader
->key
.vs
.epilog
))
7064 /* Set the instanceID flag. */
7065 for (i
= 0; i
< info
->num_inputs
; i
++)
7066 if (prolog_key
.vs_prolog
.states
.instance_divisors
[i
])
7067 shader
->info
.uses_instanceid
= true;
7073 * Select and compile (or reuse) TES parts (epilog).
7075 static bool si_shader_select_tes_parts(struct si_screen
*sscreen
,
7076 LLVMTargetMachineRef tm
,
7077 struct si_shader
*shader
,
7078 struct pipe_debug_callback
*debug
)
7080 if (shader
->key
.tes
.as_es
)
7083 /* TES compiled as VS. */
7084 return si_get_vs_epilog(sscreen
, tm
, shader
, debug
,
7085 &shader
->key
.tes
.epilog
);
7089 * Compile the TCS epilog. This writes tesselation factors to memory based on
7090 * the output primitive type of the tesselator (determined by TES).
7092 static bool si_compile_tcs_epilog(struct si_screen
*sscreen
,
7093 LLVMTargetMachineRef tm
,
7094 struct pipe_debug_callback
*debug
,
7095 struct si_shader_part
*out
)
7097 union si_shader_part_key
*key
= &out
->key
;
7098 struct si_shader shader
= {};
7099 struct si_shader_context ctx
;
7100 struct gallivm_state
*gallivm
= &ctx
.radeon_bld
.gallivm
;
7101 struct lp_build_tgsi_context
*bld_base
= &ctx
.radeon_bld
.soa
.bld_base
;
7102 LLVMTypeRef params
[16];
7104 int last_array_pointer
, last_sgpr
, num_params
;
7107 si_init_shader_ctx(&ctx
, sscreen
, &shader
, tm
);
7108 ctx
.type
= PIPE_SHADER_TESS_CTRL
;
7109 shader
.key
.tcs
.epilog
= key
->tcs_epilog
.states
;
7111 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
7112 params
[SI_PARAM_RW_BUFFERS
] = const_array(ctx
.v16i8
, SI_NUM_RW_BUFFERS
);
7113 last_array_pointer
= SI_PARAM_RW_BUFFERS
;
7114 params
[SI_PARAM_CONST_BUFFERS
] = ctx
.i64
;
7115 params
[SI_PARAM_SAMPLERS
] = ctx
.i64
;
7116 params
[SI_PARAM_IMAGES
] = ctx
.i64
;
7117 params
[SI_PARAM_SHADER_BUFFERS
] = ctx
.i64
;
7118 params
[SI_PARAM_TCS_OFFCHIP_LAYOUT
] = ctx
.i32
;
7119 params
[SI_PARAM_TCS_OUT_OFFSETS
] = ctx
.i32
;
7120 params
[SI_PARAM_TCS_OUT_LAYOUT
] = ctx
.i32
;
7121 params
[SI_PARAM_TCS_IN_LAYOUT
] = ctx
.i32
;
7122 params
[ctx
.param_oc_lds
= SI_PARAM_TCS_OC_LDS
] = ctx
.i32
;
7123 params
[SI_PARAM_TESS_FACTOR_OFFSET
] = ctx
.i32
;
7124 last_sgpr
= SI_PARAM_TESS_FACTOR_OFFSET
;
7125 num_params
= last_sgpr
+ 1;
7127 params
[num_params
++] = ctx
.i32
; /* patch index within the wave (REL_PATCH_ID) */
7128 params
[num_params
++] = ctx
.i32
; /* invocation ID within the patch */
7129 params
[num_params
++] = ctx
.i32
; /* LDS offset where tess factors should be loaded from */
7131 /* Create the function. */
7132 si_create_function(&ctx
, NULL
, 0, params
, num_params
,
7133 last_array_pointer
, last_sgpr
);
7134 declare_tess_lds(&ctx
);
7135 func
= ctx
.radeon_bld
.main_fn
;
7137 si_write_tess_factors(bld_base
,
7138 LLVMGetParam(func
, last_sgpr
+ 1),
7139 LLVMGetParam(func
, last_sgpr
+ 2),
7140 LLVMGetParam(func
, last_sgpr
+ 3));
7143 LLVMBuildRetVoid(gallivm
->builder
);
7144 radeon_llvm_finalize_module(&ctx
.radeon_bld
);
7146 if (si_compile_llvm(sscreen
, &out
->binary
, &out
->config
, tm
,
7147 gallivm
->module
, debug
, ctx
.type
,
7148 "Tessellation Control Shader Epilog"))
7151 radeon_llvm_dispose(&ctx
.radeon_bld
);
7156 * Select and compile (or reuse) TCS parts (epilog).
7158 static bool si_shader_select_tcs_parts(struct si_screen
*sscreen
,
7159 LLVMTargetMachineRef tm
,
7160 struct si_shader
*shader
,
7161 struct pipe_debug_callback
*debug
)
7163 union si_shader_part_key epilog_key
;
7165 /* Get the epilog. */
7166 memset(&epilog_key
, 0, sizeof(epilog_key
));
7167 epilog_key
.tcs_epilog
.states
= shader
->key
.tcs
.epilog
;
7169 shader
->epilog
= si_get_shader_part(sscreen
, &sscreen
->tcs_epilogs
,
7170 &epilog_key
, tm
, debug
,
7171 si_compile_tcs_epilog
);
7172 return shader
->epilog
!= NULL
;
7176 * Compile the pixel shader prolog. This handles:
7177 * - two-side color selection and interpolation
7178 * - overriding interpolation parameters for the API PS
7179 * - polygon stippling
7181 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7182 * overriden by other states. (e.g. per-sample interpolation)
7183 * Interpolated colors are stored after the preloaded VGPRs.
7185 static bool si_compile_ps_prolog(struct si_screen
*sscreen
,
7186 LLVMTargetMachineRef tm
,
7187 struct pipe_debug_callback
*debug
,
7188 struct si_shader_part
*out
)
7190 union si_shader_part_key
*key
= &out
->key
;
7191 struct si_shader shader
= {};
7192 struct si_shader_context ctx
;
7193 struct gallivm_state
*gallivm
= &ctx
.radeon_bld
.gallivm
;
7194 LLVMTypeRef
*params
;
7195 LLVMValueRef ret
, func
;
7196 int last_sgpr
, num_params
, num_returns
, i
, num_color_channels
;
7199 si_init_shader_ctx(&ctx
, sscreen
, &shader
, tm
);
7200 ctx
.type
= PIPE_SHADER_FRAGMENT
;
7201 shader
.key
.ps
.prolog
= key
->ps_prolog
.states
;
7203 /* Number of inputs + 8 color elements. */
7204 params
= alloca((key
->ps_prolog
.num_input_sgprs
+
7205 key
->ps_prolog
.num_input_vgprs
+ 8) *
7206 sizeof(LLVMTypeRef
));
7208 /* Declare inputs. */
7210 for (i
= 0; i
< key
->ps_prolog
.num_input_sgprs
; i
++)
7211 params
[num_params
++] = ctx
.i32
;
7212 last_sgpr
= num_params
- 1;
7214 for (i
= 0; i
< key
->ps_prolog
.num_input_vgprs
; i
++)
7215 params
[num_params
++] = ctx
.f32
;
7217 /* Declare outputs (same as inputs + add colors if needed) */
7218 num_returns
= num_params
;
7219 num_color_channels
= util_bitcount(key
->ps_prolog
.colors_read
);
7220 for (i
= 0; i
< num_color_channels
; i
++)
7221 params
[num_returns
++] = ctx
.f32
;
7223 /* Create the function. */
7224 si_create_function(&ctx
, params
, num_returns
, params
,
7225 num_params
, -1, last_sgpr
);
7226 func
= ctx
.radeon_bld
.main_fn
;
7228 /* Copy inputs to outputs. This should be no-op, as the registers match,
7229 * but it will prevent the compiler from overwriting them unintentionally.
7231 ret
= ctx
.return_value
;
7232 for (i
= 0; i
< num_params
; i
++) {
7233 LLVMValueRef p
= LLVMGetParam(func
, i
);
7234 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
, p
, i
, "");
7237 /* Polygon stippling. */
7238 if (key
->ps_prolog
.states
.poly_stipple
) {
7239 /* POS_FIXED_PT is always last. */
7240 unsigned pos
= key
->ps_prolog
.num_input_sgprs
+
7241 key
->ps_prolog
.num_input_vgprs
- 1;
7242 LLVMValueRef ptr
[2], list
;
7244 /* Get the pointer to rw buffers. */
7245 ptr
[0] = LLVMGetParam(func
, SI_SGPR_RW_BUFFERS
);
7246 ptr
[1] = LLVMGetParam(func
, SI_SGPR_RW_BUFFERS_HI
);
7247 list
= lp_build_gather_values(gallivm
, ptr
, 2);
7248 list
= LLVMBuildBitCast(gallivm
->builder
, list
, ctx
.i64
, "");
7249 list
= LLVMBuildIntToPtr(gallivm
->builder
, list
,
7250 const_array(ctx
.v16i8
, SI_NUM_RW_BUFFERS
), "");
7252 si_llvm_emit_polygon_stipple(&ctx
, list
, pos
);
7255 if (key
->ps_prolog
.states
.bc_optimize_for_persp
||
7256 key
->ps_prolog
.states
.bc_optimize_for_linear
) {
7257 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7258 LLVMValueRef center
[2], centroid
[2], tmp
, bc_optimize
;
7260 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7261 * The hw doesn't compute CENTROID if the whole wave only
7262 * contains fully-covered quads.
7264 * PRIM_MASK is after user SGPRs.
7266 bc_optimize
= LLVMGetParam(func
, SI_PS_NUM_USER_SGPR
);
7267 bc_optimize
= LLVMBuildLShr(gallivm
->builder
, bc_optimize
,
7268 LLVMConstInt(ctx
.i32
, 31, 0), "");
7269 bc_optimize
= LLVMBuildTrunc(gallivm
->builder
, bc_optimize
,
7272 if (key
->ps_prolog
.states
.bc_optimize_for_persp
) {
7273 /* Read PERSP_CENTER. */
7274 for (i
= 0; i
< 2; i
++)
7275 center
[i
] = LLVMGetParam(func
, base
+ 2 + i
);
7276 /* Read PERSP_CENTROID. */
7277 for (i
= 0; i
< 2; i
++)
7278 centroid
[i
] = LLVMGetParam(func
, base
+ 4 + i
);
7279 /* Select PERSP_CENTROID. */
7280 for (i
= 0; i
< 2; i
++) {
7281 tmp
= LLVMBuildSelect(gallivm
->builder
, bc_optimize
,
7282 center
[i
], centroid
[i
], "");
7283 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7284 tmp
, base
+ 4 + i
, "");
7287 if (key
->ps_prolog
.states
.bc_optimize_for_linear
) {
7288 /* Read LINEAR_CENTER. */
7289 for (i
= 0; i
< 2; i
++)
7290 center
[i
] = LLVMGetParam(func
, base
+ 8 + i
);
7291 /* Read LINEAR_CENTROID. */
7292 for (i
= 0; i
< 2; i
++)
7293 centroid
[i
] = LLVMGetParam(func
, base
+ 10 + i
);
7294 /* Select LINEAR_CENTROID. */
7295 for (i
= 0; i
< 2; i
++) {
7296 tmp
= LLVMBuildSelect(gallivm
->builder
, bc_optimize
,
7297 center
[i
], centroid
[i
], "");
7298 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7299 tmp
, base
+ 10 + i
, "");
7304 /* Interpolate colors. */
7305 for (i
= 0; i
< 2; i
++) {
7306 unsigned writemask
= (key
->ps_prolog
.colors_read
>> (i
* 4)) & 0xf;
7307 unsigned face_vgpr
= key
->ps_prolog
.num_input_sgprs
+
7308 key
->ps_prolog
.face_vgpr_index
;
7309 LLVMValueRef interp
[2], color
[4];
7310 LLVMValueRef interp_ij
= NULL
, prim_mask
= NULL
, face
= NULL
;
7315 /* If the interpolation qualifier is not CONSTANT (-1). */
7316 if (key
->ps_prolog
.color_interp_vgpr_index
[i
] != -1) {
7317 unsigned interp_vgpr
= key
->ps_prolog
.num_input_sgprs
+
7318 key
->ps_prolog
.color_interp_vgpr_index
[i
];
7320 /* Get the (i,j) updated by bc_optimize handling. */
7321 interp
[0] = LLVMBuildExtractValue(gallivm
->builder
, ret
,
7323 interp
[1] = LLVMBuildExtractValue(gallivm
->builder
, ret
,
7324 interp_vgpr
+ 1, "");
7325 interp_ij
= lp_build_gather_values(gallivm
, interp
, 2);
7326 interp_ij
= LLVMBuildBitCast(gallivm
->builder
, interp_ij
,
7330 /* Use the absolute location of the input. */
7331 prim_mask
= LLVMGetParam(func
, SI_PS_NUM_USER_SGPR
);
7333 if (key
->ps_prolog
.states
.color_two_side
) {
7334 face
= LLVMGetParam(func
, face_vgpr
);
7335 face
= LLVMBuildBitCast(gallivm
->builder
, face
, ctx
.i32
, "");
7338 interp_fs_input(&ctx
,
7339 key
->ps_prolog
.color_attr_index
[i
],
7340 TGSI_SEMANTIC_COLOR
, i
,
7341 key
->ps_prolog
.num_interp_inputs
,
7342 key
->ps_prolog
.colors_read
, interp_ij
,
7343 prim_mask
, face
, color
);
7346 unsigned chan
= u_bit_scan(&writemask
);
7347 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
, color
[chan
],
7352 /* Force per-sample interpolation. */
7353 if (key
->ps_prolog
.states
.force_persp_sample_interp
) {
7354 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7355 LLVMValueRef persp_sample
[2];
7357 /* Read PERSP_SAMPLE. */
7358 for (i
= 0; i
< 2; i
++)
7359 persp_sample
[i
] = LLVMGetParam(func
, base
+ i
);
7360 /* Overwrite PERSP_CENTER. */
7361 for (i
= 0; i
< 2; i
++)
7362 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7363 persp_sample
[i
], base
+ 2 + i
, "");
7364 /* Overwrite PERSP_CENTROID. */
7365 for (i
= 0; i
< 2; i
++)
7366 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7367 persp_sample
[i
], base
+ 4 + i
, "");
7369 if (key
->ps_prolog
.states
.force_linear_sample_interp
) {
7370 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7371 LLVMValueRef linear_sample
[2];
7373 /* Read LINEAR_SAMPLE. */
7374 for (i
= 0; i
< 2; i
++)
7375 linear_sample
[i
] = LLVMGetParam(func
, base
+ 6 + i
);
7376 /* Overwrite LINEAR_CENTER. */
7377 for (i
= 0; i
< 2; i
++)
7378 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7379 linear_sample
[i
], base
+ 8 + i
, "");
7380 /* Overwrite LINEAR_CENTROID. */
7381 for (i
= 0; i
< 2; i
++)
7382 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7383 linear_sample
[i
], base
+ 10 + i
, "");
7386 /* Force center interpolation. */
7387 if (key
->ps_prolog
.states
.force_persp_center_interp
) {
7388 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7389 LLVMValueRef persp_center
[2];
7391 /* Read PERSP_CENTER. */
7392 for (i
= 0; i
< 2; i
++)
7393 persp_center
[i
] = LLVMGetParam(func
, base
+ 2 + i
);
7394 /* Overwrite PERSP_SAMPLE. */
7395 for (i
= 0; i
< 2; i
++)
7396 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7397 persp_center
[i
], base
+ i
, "");
7398 /* Overwrite PERSP_CENTROID. */
7399 for (i
= 0; i
< 2; i
++)
7400 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7401 persp_center
[i
], base
+ 4 + i
, "");
7403 if (key
->ps_prolog
.states
.force_linear_center_interp
) {
7404 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7405 LLVMValueRef linear_center
[2];
7407 /* Read LINEAR_CENTER. */
7408 for (i
= 0; i
< 2; i
++)
7409 linear_center
[i
] = LLVMGetParam(func
, base
+ 8 + i
);
7410 /* Overwrite LINEAR_SAMPLE. */
7411 for (i
= 0; i
< 2; i
++)
7412 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7413 linear_center
[i
], base
+ 6 + i
, "");
7414 /* Overwrite LINEAR_CENTROID. */
7415 for (i
= 0; i
< 2; i
++)
7416 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7417 linear_center
[i
], base
+ 10 + i
, "");
7420 /* Tell LLVM to insert WQM instruction sequence when needed. */
7421 if (key
->ps_prolog
.wqm
) {
7422 LLVMAddTargetDependentFunctionAttr(func
,
7423 "amdgpu-ps-wqm-outputs", "");
7427 si_llvm_build_ret(&ctx
, ret
);
7428 radeon_llvm_finalize_module(&ctx
.radeon_bld
);
7430 if (si_compile_llvm(sscreen
, &out
->binary
, &out
->config
, tm
,
7431 gallivm
->module
, debug
, ctx
.type
,
7432 "Fragment Shader Prolog"))
7435 radeon_llvm_dispose(&ctx
.radeon_bld
);
7440 * Compile the pixel shader epilog. This handles everything that must be
7441 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7443 static bool si_compile_ps_epilog(struct si_screen
*sscreen
,
7444 LLVMTargetMachineRef tm
,
7445 struct pipe_debug_callback
*debug
,
7446 struct si_shader_part
*out
)
7448 union si_shader_part_key
*key
= &out
->key
;
7449 struct si_shader shader
= {};
7450 struct si_shader_context ctx
;
7451 struct gallivm_state
*gallivm
= &ctx
.radeon_bld
.gallivm
;
7452 struct lp_build_tgsi_context
*bld_base
= &ctx
.radeon_bld
.soa
.bld_base
;
7453 LLVMTypeRef params
[16+8*4+3];
7454 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
7455 int last_array_pointer
, last_sgpr
, num_params
, i
;
7458 si_init_shader_ctx(&ctx
, sscreen
, &shader
, tm
);
7459 ctx
.type
= PIPE_SHADER_FRAGMENT
;
7460 shader
.key
.ps
.epilog
= key
->ps_epilog
.states
;
7462 /* Declare input SGPRs. */
7463 params
[SI_PARAM_RW_BUFFERS
] = ctx
.i64
;
7464 params
[SI_PARAM_CONST_BUFFERS
] = ctx
.i64
;
7465 params
[SI_PARAM_SAMPLERS
] = ctx
.i64
;
7466 params
[SI_PARAM_IMAGES
] = ctx
.i64
;
7467 params
[SI_PARAM_SHADER_BUFFERS
] = ctx
.i64
;
7468 params
[SI_PARAM_ALPHA_REF
] = ctx
.f32
;
7469 last_array_pointer
= -1;
7470 last_sgpr
= SI_PARAM_ALPHA_REF
;
7472 /* Declare input VGPRs. */
7473 num_params
= (last_sgpr
+ 1) +
7474 util_bitcount(key
->ps_epilog
.colors_written
) * 4 +
7475 key
->ps_epilog
.writes_z
+
7476 key
->ps_epilog
.writes_stencil
+
7477 key
->ps_epilog
.writes_samplemask
;
7479 num_params
= MAX2(num_params
,
7480 last_sgpr
+ 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC
+ 1);
7482 assert(num_params
<= ARRAY_SIZE(params
));
7484 for (i
= last_sgpr
+ 1; i
< num_params
; i
++)
7485 params
[i
] = ctx
.f32
;
7487 /* Create the function. */
7488 si_create_function(&ctx
, NULL
, 0, params
, num_params
,
7489 last_array_pointer
, last_sgpr
);
7490 /* Disable elimination of unused inputs. */
7491 radeon_llvm_add_attribute(ctx
.radeon_bld
.main_fn
,
7492 "InitialPSInputAddr", 0xffffff);
7494 /* Process colors. */
7495 unsigned vgpr
= last_sgpr
+ 1;
7496 unsigned colors_written
= key
->ps_epilog
.colors_written
;
7497 int last_color_export
= -1;
7499 /* Find the last color export. */
7500 if (!key
->ps_epilog
.writes_z
&&
7501 !key
->ps_epilog
.writes_stencil
&&
7502 !key
->ps_epilog
.writes_samplemask
) {
7503 unsigned spi_format
= key
->ps_epilog
.states
.spi_shader_col_format
;
7505 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7506 if (colors_written
== 0x1 && key
->ps_epilog
.states
.last_cbuf
> 0) {
7507 /* Just set this if any of the colorbuffers are enabled. */
7509 ((1llu << (4 * (key
->ps_epilog
.states
.last_cbuf
+ 1))) - 1))
7510 last_color_export
= 0;
7512 for (i
= 0; i
< 8; i
++)
7513 if (colors_written
& (1 << i
) &&
7514 (spi_format
>> (i
* 4)) & 0xf)
7515 last_color_export
= i
;
7519 while (colors_written
) {
7520 LLVMValueRef color
[4];
7521 int mrt
= u_bit_scan(&colors_written
);
7523 for (i
= 0; i
< 4; i
++)
7524 color
[i
] = LLVMGetParam(ctx
.radeon_bld
.main_fn
, vgpr
++);
7526 si_export_mrt_color(bld_base
, color
, mrt
,
7528 mrt
== last_color_export
);
7531 /* Process depth, stencil, samplemask. */
7532 if (key
->ps_epilog
.writes_z
)
7533 depth
= LLVMGetParam(ctx
.radeon_bld
.main_fn
, vgpr
++);
7534 if (key
->ps_epilog
.writes_stencil
)
7535 stencil
= LLVMGetParam(ctx
.radeon_bld
.main_fn
, vgpr
++);
7536 if (key
->ps_epilog
.writes_samplemask
)
7537 samplemask
= LLVMGetParam(ctx
.radeon_bld
.main_fn
, vgpr
++);
7539 if (depth
|| stencil
|| samplemask
)
7540 si_export_mrt_z(bld_base
, depth
, stencil
, samplemask
);
7541 else if (last_color_export
== -1)
7542 si_export_null(bld_base
);
7545 LLVMBuildRetVoid(gallivm
->builder
);
7546 radeon_llvm_finalize_module(&ctx
.radeon_bld
);
7548 if (si_compile_llvm(sscreen
, &out
->binary
, &out
->config
, tm
,
7549 gallivm
->module
, debug
, ctx
.type
,
7550 "Fragment Shader Epilog"))
7553 radeon_llvm_dispose(&ctx
.radeon_bld
);
7558 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7560 static bool si_shader_select_ps_parts(struct si_screen
*sscreen
,
7561 LLVMTargetMachineRef tm
,
7562 struct si_shader
*shader
,
7563 struct pipe_debug_callback
*debug
)
7565 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
7566 union si_shader_part_key prolog_key
;
7567 union si_shader_part_key epilog_key
;
7570 /* Get the prolog. */
7571 memset(&prolog_key
, 0, sizeof(prolog_key
));
7572 prolog_key
.ps_prolog
.states
= shader
->key
.ps
.prolog
;
7573 prolog_key
.ps_prolog
.colors_read
= info
->colors_read
;
7574 prolog_key
.ps_prolog
.num_input_sgprs
= shader
->info
.num_input_sgprs
;
7575 prolog_key
.ps_prolog
.num_input_vgprs
= shader
->info
.num_input_vgprs
;
7576 prolog_key
.ps_prolog
.wqm
= info
->uses_derivatives
&&
7577 (prolog_key
.ps_prolog
.colors_read
||
7578 prolog_key
.ps_prolog
.states
.force_persp_sample_interp
||
7579 prolog_key
.ps_prolog
.states
.force_linear_sample_interp
||
7580 prolog_key
.ps_prolog
.states
.force_persp_center_interp
||
7581 prolog_key
.ps_prolog
.states
.force_linear_center_interp
||
7582 prolog_key
.ps_prolog
.states
.bc_optimize_for_persp
||
7583 prolog_key
.ps_prolog
.states
.bc_optimize_for_linear
);
7585 if (info
->colors_read
) {
7586 unsigned *color
= shader
->selector
->color_attr_index
;
7588 if (shader
->key
.ps
.prolog
.color_two_side
) {
7589 /* BCOLORs are stored after the last input. */
7590 prolog_key
.ps_prolog
.num_interp_inputs
= info
->num_inputs
;
7591 prolog_key
.ps_prolog
.face_vgpr_index
= shader
->info
.face_vgpr_index
;
7592 shader
->config
.spi_ps_input_ena
|= S_0286CC_FRONT_FACE_ENA(1);
7595 for (i
= 0; i
< 2; i
++) {
7596 unsigned interp
= info
->input_interpolate
[color
[i
]];
7597 unsigned location
= info
->input_interpolate_loc
[color
[i
]];
7599 if (!(info
->colors_read
& (0xf << i
*4)))
7602 prolog_key
.ps_prolog
.color_attr_index
[i
] = color
[i
];
7604 if (shader
->key
.ps
.prolog
.flatshade_colors
&&
7605 interp
== TGSI_INTERPOLATE_COLOR
)
7606 interp
= TGSI_INTERPOLATE_CONSTANT
;
7609 case TGSI_INTERPOLATE_CONSTANT
:
7610 prolog_key
.ps_prolog
.color_interp_vgpr_index
[i
] = -1;
7612 case TGSI_INTERPOLATE_PERSPECTIVE
:
7613 case TGSI_INTERPOLATE_COLOR
:
7614 /* Force the interpolation location for colors here. */
7615 if (shader
->key
.ps
.prolog
.force_persp_sample_interp
)
7616 location
= TGSI_INTERPOLATE_LOC_SAMPLE
;
7617 if (shader
->key
.ps
.prolog
.force_persp_center_interp
)
7618 location
= TGSI_INTERPOLATE_LOC_CENTER
;
7621 case TGSI_INTERPOLATE_LOC_SAMPLE
:
7622 prolog_key
.ps_prolog
.color_interp_vgpr_index
[i
] = 0;
7623 shader
->config
.spi_ps_input_ena
|=
7624 S_0286CC_PERSP_SAMPLE_ENA(1);
7626 case TGSI_INTERPOLATE_LOC_CENTER
:
7627 prolog_key
.ps_prolog
.color_interp_vgpr_index
[i
] = 2;
7628 shader
->config
.spi_ps_input_ena
|=
7629 S_0286CC_PERSP_CENTER_ENA(1);
7631 case TGSI_INTERPOLATE_LOC_CENTROID
:
7632 prolog_key
.ps_prolog
.color_interp_vgpr_index
[i
] = 4;
7633 shader
->config
.spi_ps_input_ena
|=
7634 S_0286CC_PERSP_CENTROID_ENA(1);
7640 case TGSI_INTERPOLATE_LINEAR
:
7641 /* Force the interpolation location for colors here. */
7642 if (shader
->key
.ps
.prolog
.force_linear_sample_interp
)
7643 location
= TGSI_INTERPOLATE_LOC_SAMPLE
;
7644 if (shader
->key
.ps
.prolog
.force_linear_center_interp
)
7645 location
= TGSI_INTERPOLATE_LOC_CENTER
;
7648 case TGSI_INTERPOLATE_LOC_SAMPLE
:
7649 prolog_key
.ps_prolog
.color_interp_vgpr_index
[i
] = 6;
7650 shader
->config
.spi_ps_input_ena
|=
7651 S_0286CC_LINEAR_SAMPLE_ENA(1);
7653 case TGSI_INTERPOLATE_LOC_CENTER
:
7654 prolog_key
.ps_prolog
.color_interp_vgpr_index
[i
] = 8;
7655 shader
->config
.spi_ps_input_ena
|=
7656 S_0286CC_LINEAR_CENTER_ENA(1);
7658 case TGSI_INTERPOLATE_LOC_CENTROID
:
7659 prolog_key
.ps_prolog
.color_interp_vgpr_index
[i
] = 10;
7660 shader
->config
.spi_ps_input_ena
|=
7661 S_0286CC_LINEAR_CENTROID_ENA(1);
7673 /* The prolog is a no-op if these aren't set. */
7674 if (prolog_key
.ps_prolog
.colors_read
||
7675 prolog_key
.ps_prolog
.states
.force_persp_sample_interp
||
7676 prolog_key
.ps_prolog
.states
.force_linear_sample_interp
||
7677 prolog_key
.ps_prolog
.states
.force_persp_center_interp
||
7678 prolog_key
.ps_prolog
.states
.force_linear_center_interp
||
7679 prolog_key
.ps_prolog
.states
.bc_optimize_for_persp
||
7680 prolog_key
.ps_prolog
.states
.bc_optimize_for_linear
||
7681 prolog_key
.ps_prolog
.states
.poly_stipple
) {
7683 si_get_shader_part(sscreen
, &sscreen
->ps_prologs
,
7684 &prolog_key
, tm
, debug
,
7685 si_compile_ps_prolog
);
7686 if (!shader
->prolog
)
7690 /* Get the epilog. */
7691 memset(&epilog_key
, 0, sizeof(epilog_key
));
7692 epilog_key
.ps_epilog
.colors_written
= info
->colors_written
;
7693 epilog_key
.ps_epilog
.writes_z
= info
->writes_z
;
7694 epilog_key
.ps_epilog
.writes_stencil
= info
->writes_stencil
;
7695 epilog_key
.ps_epilog
.writes_samplemask
= info
->writes_samplemask
;
7696 epilog_key
.ps_epilog
.states
= shader
->key
.ps
.epilog
;
7699 si_get_shader_part(sscreen
, &sscreen
->ps_epilogs
,
7700 &epilog_key
, tm
, debug
,
7701 si_compile_ps_epilog
);
7702 if (!shader
->epilog
)
7705 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7706 if (shader
->key
.ps
.prolog
.poly_stipple
) {
7707 shader
->config
.spi_ps_input_ena
|= S_0286CC_POS_FIXED_PT_ENA(1);
7708 assert(G_0286CC_POS_FIXED_PT_ENA(shader
->config
.spi_ps_input_addr
));
7711 /* Set up the enable bits for per-sample shading if needed. */
7712 if (shader
->key
.ps
.prolog
.force_persp_sample_interp
&&
7713 (G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_ena
) ||
7714 G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7715 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTER_ENA
;
7716 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTROID_ENA
;
7717 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_SAMPLE_ENA(1);
7719 if (shader
->key
.ps
.prolog
.force_linear_sample_interp
&&
7720 (G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_ena
) ||
7721 G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7722 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTER_ENA
;
7723 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTROID_ENA
;
7724 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_SAMPLE_ENA(1);
7726 if (shader
->key
.ps
.prolog
.force_persp_center_interp
&&
7727 (G_0286CC_PERSP_SAMPLE_ENA(shader
->config
.spi_ps_input_ena
) ||
7728 G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7729 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_SAMPLE_ENA
;
7730 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTROID_ENA
;
7731 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_CENTER_ENA(1);
7733 if (shader
->key
.ps
.prolog
.force_linear_center_interp
&&
7734 (G_0286CC_LINEAR_SAMPLE_ENA(shader
->config
.spi_ps_input_ena
) ||
7735 G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7736 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_SAMPLE_ENA
;
7737 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTROID_ENA
;
7738 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_CENTER_ENA(1);
7741 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7742 if (G_0286CC_POS_W_FLOAT_ENA(shader
->config
.spi_ps_input_ena
) &&
7743 !(shader
->config
.spi_ps_input_ena
& 0xf)) {
7744 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_CENTER_ENA(1);
7745 assert(G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_addr
));
7748 /* At least one pair of interpolation weights must be enabled. */
7749 if (!(shader
->config
.spi_ps_input_ena
& 0x7f)) {
7750 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_CENTER_ENA(1);
7751 assert(G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_addr
));
7754 /* The sample mask input is always enabled, because the API shader always
7755 * passes it through to the epilog. Disable it here if it's unused.
7757 if (!shader
->key
.ps
.epilog
.poly_line_smoothing
&&
7758 !shader
->selector
->info
.reads_samplemask
)
7759 shader
->config
.spi_ps_input_ena
&= C_0286CC_SAMPLE_COVERAGE_ENA
;
7764 static void si_fix_num_sgprs(struct si_shader
*shader
)
7766 unsigned min_sgprs
= shader
->info
.num_input_sgprs
+ 2; /* VCC */
7768 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
, min_sgprs
);
7771 int si_shader_create(struct si_screen
*sscreen
, LLVMTargetMachineRef tm
,
7772 struct si_shader
*shader
,
7773 struct pipe_debug_callback
*debug
)
7775 struct si_shader
*mainp
= shader
->selector
->main_shader_part
;
7778 /* LS, ES, VS are compiled on demand if the main part hasn't been
7779 * compiled for that stage.
7782 (shader
->selector
->type
== PIPE_SHADER_VERTEX
&&
7783 (shader
->key
.vs
.as_es
!= mainp
->key
.vs
.as_es
||
7784 shader
->key
.vs
.as_ls
!= mainp
->key
.vs
.as_ls
)) ||
7785 (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
&&
7786 shader
->key
.tes
.as_es
!= mainp
->key
.tes
.as_es
) ||
7787 (shader
->selector
->type
== PIPE_SHADER_TESS_CTRL
&&
7788 shader
->key
.tcs
.epilog
.inputs_to_copy
) ||
7789 shader
->selector
->type
== PIPE_SHADER_COMPUTE
) {
7790 /* Monolithic shader (compiled as a whole, has many variants,
7791 * may take a long time to compile).
7793 r
= si_compile_tgsi_shader(sscreen
, tm
, shader
, true, debug
);
7797 /* The shader consists of 2-3 parts:
7799 * - the middle part is the user shader, it has 1 variant only
7800 * and it was compiled during the creation of the shader
7802 * - the prolog part is inserted at the beginning
7803 * - the epilog part is inserted at the end
7805 * The prolog and epilog have many (but simple) variants.
7808 /* Copy the compiled TGSI shader data over. */
7809 shader
->is_binary_shared
= true;
7810 shader
->binary
= mainp
->binary
;
7811 shader
->config
= mainp
->config
;
7812 shader
->info
.num_input_sgprs
= mainp
->info
.num_input_sgprs
;
7813 shader
->info
.num_input_vgprs
= mainp
->info
.num_input_vgprs
;
7814 shader
->info
.face_vgpr_index
= mainp
->info
.face_vgpr_index
;
7815 memcpy(shader
->info
.vs_output_param_offset
,
7816 mainp
->info
.vs_output_param_offset
,
7817 sizeof(mainp
->info
.vs_output_param_offset
));
7818 shader
->info
.uses_instanceid
= mainp
->info
.uses_instanceid
;
7819 shader
->info
.nr_pos_exports
= mainp
->info
.nr_pos_exports
;
7820 shader
->info
.nr_param_exports
= mainp
->info
.nr_param_exports
;
7822 /* Select prologs and/or epilogs. */
7823 switch (shader
->selector
->type
) {
7824 case PIPE_SHADER_VERTEX
:
7825 if (!si_shader_select_vs_parts(sscreen
, tm
, shader
, debug
))
7828 case PIPE_SHADER_TESS_CTRL
:
7829 if (!si_shader_select_tcs_parts(sscreen
, tm
, shader
, debug
))
7832 case PIPE_SHADER_TESS_EVAL
:
7833 if (!si_shader_select_tes_parts(sscreen
, tm
, shader
, debug
))
7836 case PIPE_SHADER_FRAGMENT
:
7837 if (!si_shader_select_ps_parts(sscreen
, tm
, shader
, debug
))
7840 /* Make sure we have at least as many VGPRs as there
7841 * are allocated inputs.
7843 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
7844 shader
->info
.num_input_vgprs
);
7848 /* Update SGPR and VGPR counts. */
7849 if (shader
->prolog
) {
7850 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
7851 shader
->prolog
->config
.num_sgprs
);
7852 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
7853 shader
->prolog
->config
.num_vgprs
);
7855 if (shader
->epilog
) {
7856 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
7857 shader
->epilog
->config
.num_sgprs
);
7858 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
7859 shader
->epilog
->config
.num_vgprs
);
7863 si_fix_num_sgprs(shader
);
7864 si_shader_dump(sscreen
, shader
, debug
, shader
->selector
->info
.processor
,
7868 r
= si_shader_binary_upload(sscreen
, shader
);
7870 fprintf(stderr
, "LLVM failed to upload shader\n");
7877 void si_shader_destroy(struct si_shader
*shader
)
7879 if (shader
->gs_copy_shader
) {
7880 si_shader_destroy(shader
->gs_copy_shader
);
7881 FREE(shader
->gs_copy_shader
);
7884 if (shader
->scratch_bo
)
7885 r600_resource_reference(&shader
->scratch_bo
, NULL
);
7887 r600_resource_reference(&shader
->bo
, NULL
);
7889 if (!shader
->is_binary_shared
)
7890 radeon_shader_binary_clean(&shader
->binary
);