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2ca53dec70abf4869a6f73ad65fdade1a230684f
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "util/u_memory.h"
37 #include "util/u_string.h"
38 #include "tgsi/tgsi_build.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "si_shader_internal.h"
45 #include "si_pipe.h"
46 #include "sid.h"
47
48
49 static const char *scratch_rsrc_dword0_symbol =
50 "SCRATCH_RSRC_DWORD0";
51
52 static const char *scratch_rsrc_dword1_symbol =
53 "SCRATCH_RSRC_DWORD1";
54
55 struct si_shader_output_values
56 {
57 LLVMValueRef values[4];
58 unsigned semantic_name;
59 unsigned semantic_index;
60 ubyte vertex_stream[4];
61 };
62
63 static void si_init_shader_ctx(struct si_shader_context *ctx,
64 struct si_screen *sscreen,
65 struct si_shader *shader,
66 LLVMTargetMachineRef tm);
67
68 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
69 struct lp_build_tgsi_context *bld_base,
70 struct lp_build_emit_data *emit_data);
71
72 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
73 FILE *f);
74
75 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
76 union si_shader_part_key *key);
77 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
78 union si_shader_part_key *key);
79 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
80 union si_shader_part_key *key);
81 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
82 union si_shader_part_key *key);
83 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
84 union si_shader_part_key *key);
85
86 /* Ideally pass the sample mask input to the PS epilog as v13, which
87 * is its usual location, so that the shader doesn't have to add v_mov.
88 */
89 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
90
91 /* The VS location of the PrimitiveID input is the same in the epilog,
92 * so that the main shader part doesn't have to move it.
93 */
94 #define VS_EPILOG_PRIMID_LOC 2
95
96 enum {
97 CONST_ADDR_SPACE = 2,
98 LOCAL_ADDR_SPACE = 3,
99 };
100
101 /**
102 * Returns a unique index for a semantic name and index. The index must be
103 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
104 * calculated.
105 */
106 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
107 {
108 switch (semantic_name) {
109 case TGSI_SEMANTIC_POSITION:
110 return 0;
111 case TGSI_SEMANTIC_PSIZE:
112 return 1;
113 case TGSI_SEMANTIC_CLIPDIST:
114 assert(index <= 1);
115 return 2 + index;
116 case TGSI_SEMANTIC_GENERIC:
117 if (index <= 63-4)
118 return 4 + index;
119
120 assert(!"invalid generic index");
121 return 0;
122
123 /* patch indices are completely separate and thus start from 0 */
124 case TGSI_SEMANTIC_TESSOUTER:
125 return 0;
126 case TGSI_SEMANTIC_TESSINNER:
127 return 1;
128 case TGSI_SEMANTIC_PATCH:
129 return 2 + index;
130
131 default:
132 assert(!"invalid semantic name");
133 return 0;
134 }
135 }
136
137 unsigned si_shader_io_get_unique_index2(unsigned name, unsigned index)
138 {
139 switch (name) {
140 case TGSI_SEMANTIC_FOG:
141 return 0;
142 case TGSI_SEMANTIC_LAYER:
143 return 1;
144 case TGSI_SEMANTIC_VIEWPORT_INDEX:
145 return 2;
146 case TGSI_SEMANTIC_PRIMID:
147 return 3;
148 case TGSI_SEMANTIC_COLOR: /* these alias */
149 case TGSI_SEMANTIC_BCOLOR:
150 return 4 + index;
151 case TGSI_SEMANTIC_TEXCOORD:
152 return 6 + index;
153 default:
154 assert(!"invalid semantic name");
155 return 0;
156 }
157 }
158
159 /**
160 * Get the value of a shader input parameter and extract a bitfield.
161 */
162 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
163 unsigned param, unsigned rshift,
164 unsigned bitwidth)
165 {
166 struct gallivm_state *gallivm = &ctx->gallivm;
167 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
168 param);
169
170 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
171 value = bitcast(&ctx->bld_base,
172 TGSI_TYPE_UNSIGNED, value);
173
174 if (rshift)
175 value = LLVMBuildLShr(gallivm->builder, value,
176 lp_build_const_int32(gallivm, rshift), "");
177
178 if (rshift + bitwidth < 32) {
179 unsigned mask = (1 << bitwidth) - 1;
180 value = LLVMBuildAnd(gallivm->builder, value,
181 lp_build_const_int32(gallivm, mask), "");
182 }
183
184 return value;
185 }
186
187 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
188 {
189 switch (ctx->type) {
190 case PIPE_SHADER_TESS_CTRL:
191 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
192
193 case PIPE_SHADER_TESS_EVAL:
194 return LLVMGetParam(ctx->main_fn,
195 ctx->param_tes_rel_patch_id);
196
197 default:
198 assert(0);
199 return NULL;
200 }
201 }
202
203 /* Tessellation shaders pass outputs to the next shader using LDS.
204 *
205 * LS outputs = TCS inputs
206 * TCS outputs = TES inputs
207 *
208 * The LDS layout is:
209 * - TCS inputs for patch 0
210 * - TCS inputs for patch 1
211 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
212 * - ...
213 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
214 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
215 * - TCS outputs for patch 1
216 * - Per-patch TCS outputs for patch 1
217 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
218 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
219 * - ...
220 *
221 * All three shaders VS(LS), TCS, TES share the same LDS space.
222 */
223
224 static LLVMValueRef
225 get_tcs_in_patch_stride(struct si_shader_context *ctx)
226 {
227 if (ctx->type == PIPE_SHADER_VERTEX)
228 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
229 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
230 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
231 else {
232 assert(0);
233 return NULL;
234 }
235 }
236
237 static LLVMValueRef
238 get_tcs_out_patch_stride(struct si_shader_context *ctx)
239 {
240 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
241 }
242
243 static LLVMValueRef
244 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
245 {
246 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
247 unpack_param(ctx,
248 SI_PARAM_TCS_OUT_OFFSETS,
249 0, 16),
250 4);
251 }
252
253 static LLVMValueRef
254 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
255 {
256 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
257 unpack_param(ctx,
258 SI_PARAM_TCS_OUT_OFFSETS,
259 16, 16),
260 4);
261 }
262
263 static LLVMValueRef
264 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
265 {
266 struct gallivm_state *gallivm = &ctx->gallivm;
267 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
268 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
269
270 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
271 }
272
273 static LLVMValueRef
274 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
275 {
276 struct gallivm_state *gallivm = &ctx->gallivm;
277 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
278 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
279 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
280
281 return LLVMBuildAdd(gallivm->builder, patch0_offset,
282 LLVMBuildMul(gallivm->builder, patch_stride,
283 rel_patch_id, ""),
284 "");
285 }
286
287 static LLVMValueRef
288 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
289 {
290 struct gallivm_state *gallivm = &ctx->gallivm;
291 LLVMValueRef patch0_patch_data_offset =
292 get_tcs_out_patch0_patch_data_offset(ctx);
293 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
294 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
295
296 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
297 LLVMBuildMul(gallivm->builder, patch_stride,
298 rel_patch_id, ""),
299 "");
300 }
301
302 static LLVMValueRef get_instance_index_for_fetch(
303 struct si_shader_context *radeon_bld,
304 unsigned param_start_instance, unsigned divisor)
305 {
306 struct si_shader_context *ctx =
307 si_shader_context(&radeon_bld->bld_base);
308 struct gallivm_state *gallivm = radeon_bld->bld_base.base.gallivm;
309
310 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
311 ctx->param_instance_id);
312
313 /* The division must be done before START_INSTANCE is added. */
314 if (divisor > 1)
315 result = LLVMBuildUDiv(gallivm->builder, result,
316 lp_build_const_int32(gallivm, divisor), "");
317
318 return LLVMBuildAdd(gallivm->builder, result,
319 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
320 }
321
322 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
323 * to float. */
324 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
325 LLVMValueRef vec4,
326 unsigned double_index)
327 {
328 LLVMBuilderRef builder = ctx->gallivm.builder;
329 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->gallivm.context);
330 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
331 LLVMVectorType(f64, 2), "");
332 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
333 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
334 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
335 }
336
337 static void declare_input_vs(
338 struct si_shader_context *ctx,
339 unsigned input_index,
340 const struct tgsi_full_declaration *decl,
341 LLVMValueRef out[4])
342 {
343 struct lp_build_context *base = &ctx->bld_base.base;
344 struct gallivm_state *gallivm = base->gallivm;
345
346 unsigned chan;
347 unsigned fix_fetch;
348 unsigned num_fetches;
349 unsigned fetch_stride;
350
351 LLVMValueRef t_list_ptr;
352 LLVMValueRef t_offset;
353 LLVMValueRef t_list;
354 LLVMValueRef vertex_index;
355 LLVMValueRef input[3];
356
357 /* Load the T list */
358 t_list_ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_VERTEX_BUFFERS);
359
360 t_offset = lp_build_const_int32(gallivm, input_index);
361
362 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
363
364 vertex_index = LLVMGetParam(ctx->main_fn,
365 ctx->param_vertex_index0 +
366 input_index);
367
368 fix_fetch = ctx->shader->key.mono.vs.fix_fetch[input_index];
369
370 /* Do multiple loads for special formats. */
371 switch (fix_fetch) {
372 case SI_FIX_FETCH_RGB_64_FLOAT:
373 num_fetches = 3; /* 3 2-dword loads */
374 fetch_stride = 8;
375 break;
376 case SI_FIX_FETCH_RGBA_64_FLOAT:
377 num_fetches = 2; /* 2 4-dword loads */
378 fetch_stride = 16;
379 break;
380 case SI_FIX_FETCH_RGB_8:
381 case SI_FIX_FETCH_RGB_8_INT:
382 num_fetches = 3;
383 fetch_stride = 1;
384 break;
385 case SI_FIX_FETCH_RGB_16:
386 case SI_FIX_FETCH_RGB_16_INT:
387 num_fetches = 3;
388 fetch_stride = 2;
389 break;
390 default:
391 num_fetches = 1;
392 fetch_stride = 0;
393 }
394
395 for (unsigned i = 0; i < num_fetches; i++) {
396 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
397
398 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
399 vertex_index, voffset,
400 true);
401 }
402
403 /* Break up the vec4 into individual components */
404 for (chan = 0; chan < 4; chan++) {
405 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
406 out[chan] = LLVMBuildExtractElement(gallivm->builder,
407 input[0], llvm_chan, "");
408 }
409
410 switch (fix_fetch) {
411 case SI_FIX_FETCH_A2_SNORM:
412 case SI_FIX_FETCH_A2_SSCALED:
413 case SI_FIX_FETCH_A2_SINT: {
414 /* The hardware returns an unsigned value; convert it to a
415 * signed one.
416 */
417 LLVMValueRef tmp = out[3];
418 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
419
420 /* First, recover the sign-extended signed integer value. */
421 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
422 tmp = LLVMBuildFPToUI(gallivm->builder, tmp, ctx->i32, "");
423 else
424 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->i32, "");
425
426 /* For the integer-like cases, do a natural sign extension.
427 *
428 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
429 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
430 * exponent.
431 */
432 tmp = LLVMBuildShl(gallivm->builder, tmp,
433 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
434 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
435 tmp = LLVMBuildAShr(gallivm->builder, tmp, c30, "");
436
437 /* Convert back to the right type. */
438 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
439 LLVMValueRef clamp;
440 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
441 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
442 clamp = LLVMBuildFCmp(gallivm->builder, LLVMRealULT, tmp, neg_one, "");
443 tmp = LLVMBuildSelect(gallivm->builder, clamp, neg_one, tmp, "");
444 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
445 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
446 }
447
448 out[3] = tmp;
449 break;
450 }
451 case SI_FIX_FETCH_RGBA_32_UNORM:
452 case SI_FIX_FETCH_RGBX_32_UNORM:
453 for (chan = 0; chan < 4; chan++) {
454 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
455 ctx->i32, "");
456 out[chan] = LLVMBuildUIToFP(gallivm->builder,
457 out[chan], ctx->f32, "");
458 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
459 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
460 }
461 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
462 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
463 out[3] = LLVMConstReal(ctx->f32, 1);
464 break;
465 case SI_FIX_FETCH_RGBA_32_SNORM:
466 case SI_FIX_FETCH_RGBX_32_SNORM:
467 case SI_FIX_FETCH_RGBA_32_FIXED:
468 case SI_FIX_FETCH_RGBX_32_FIXED: {
469 double scale;
470 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
471 scale = 1.0 / 0x10000;
472 else
473 scale = 1.0 / INT_MAX;
474
475 for (chan = 0; chan < 4; chan++) {
476 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
477 ctx->i32, "");
478 out[chan] = LLVMBuildSIToFP(gallivm->builder,
479 out[chan], ctx->f32, "");
480 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
481 LLVMConstReal(ctx->f32, scale), "");
482 }
483 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
484 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
485 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
486 out[3] = LLVMConstReal(ctx->f32, 1);
487 break;
488 }
489 case SI_FIX_FETCH_RGBA_32_USCALED:
490 for (chan = 0; chan < 4; chan++) {
491 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
492 ctx->i32, "");
493 out[chan] = LLVMBuildUIToFP(gallivm->builder,
494 out[chan], ctx->f32, "");
495 }
496 break;
497 case SI_FIX_FETCH_RGBA_32_SSCALED:
498 for (chan = 0; chan < 4; chan++) {
499 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
500 ctx->i32, "");
501 out[chan] = LLVMBuildSIToFP(gallivm->builder,
502 out[chan], ctx->f32, "");
503 }
504 break;
505 case SI_FIX_FETCH_RG_64_FLOAT:
506 for (chan = 0; chan < 2; chan++)
507 out[chan] = extract_double_to_float(ctx, input[0], chan);
508
509 out[2] = LLVMConstReal(ctx->f32, 0);
510 out[3] = LLVMConstReal(ctx->f32, 1);
511 break;
512 case SI_FIX_FETCH_RGB_64_FLOAT:
513 for (chan = 0; chan < 3; chan++)
514 out[chan] = extract_double_to_float(ctx, input[chan], 0);
515
516 out[3] = LLVMConstReal(ctx->f32, 1);
517 break;
518 case SI_FIX_FETCH_RGBA_64_FLOAT:
519 for (chan = 0; chan < 4; chan++) {
520 out[chan] = extract_double_to_float(ctx, input[chan / 2],
521 chan % 2);
522 }
523 break;
524 case SI_FIX_FETCH_RGB_8:
525 case SI_FIX_FETCH_RGB_8_INT:
526 case SI_FIX_FETCH_RGB_16:
527 case SI_FIX_FETCH_RGB_16_INT:
528 for (chan = 0; chan < 3; chan++) {
529 out[chan] = LLVMBuildExtractElement(gallivm->builder,
530 input[chan],
531 ctx->i32_0, "");
532 }
533 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
534 fix_fetch == SI_FIX_FETCH_RGB_16) {
535 out[3] = LLVMConstReal(ctx->f32, 1);
536 } else {
537 out[3] = LLVMBuildBitCast(gallivm->builder, ctx->i32_1,
538 ctx->f32, "");
539 }
540 break;
541 }
542 }
543
544 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
545 unsigned swizzle)
546 {
547 struct si_shader_context *ctx = si_shader_context(bld_base);
548
549 if (swizzle > 0)
550 return bld_base->uint_bld.zero;
551
552 switch (ctx->type) {
553 case PIPE_SHADER_VERTEX:
554 return LLVMGetParam(ctx->main_fn,
555 ctx->param_vs_prim_id);
556 case PIPE_SHADER_TESS_CTRL:
557 return LLVMGetParam(ctx->main_fn,
558 SI_PARAM_PATCH_ID);
559 case PIPE_SHADER_TESS_EVAL:
560 return LLVMGetParam(ctx->main_fn,
561 ctx->param_tes_patch_id);
562 case PIPE_SHADER_GEOMETRY:
563 return LLVMGetParam(ctx->main_fn,
564 SI_PARAM_PRIMITIVE_ID);
565 default:
566 assert(0);
567 return bld_base->uint_bld.zero;
568 }
569 }
570
571 /**
572 * Return the value of tgsi_ind_register for indexing.
573 * This is the indirect index with the constant offset added to it.
574 */
575 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
576 const struct tgsi_ind_register *ind,
577 int rel_index)
578 {
579 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
580 LLVMValueRef result;
581
582 result = ctx->addrs[ind->Index][ind->Swizzle];
583 result = LLVMBuildLoad(gallivm->builder, result, "");
584 result = LLVMBuildAdd(gallivm->builder, result,
585 lp_build_const_int32(gallivm, rel_index), "");
586 return result;
587 }
588
589 /**
590 * Like get_indirect_index, but restricts the return value to a (possibly
591 * undefined) value inside [0..num).
592 */
593 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
594 const struct tgsi_ind_register *ind,
595 int rel_index, unsigned num)
596 {
597 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
598
599 /* LLVM 3.8: If indirect resource indexing is used:
600 * - SI & CIK hang
601 * - VI crashes
602 */
603 if (HAVE_LLVM == 0x0308)
604 return LLVMGetUndef(ctx->i32);
605
606 return si_llvm_bound_index(ctx, result, num);
607 }
608
609
610 /**
611 * Calculate a dword address given an input or output register and a stride.
612 */
613 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
614 const struct tgsi_full_dst_register *dst,
615 const struct tgsi_full_src_register *src,
616 LLVMValueRef vertex_dw_stride,
617 LLVMValueRef base_addr)
618 {
619 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
620 struct tgsi_shader_info *info = &ctx->shader->selector->info;
621 ubyte *name, *index, *array_first;
622 int first, param;
623 struct tgsi_full_dst_register reg;
624
625 /* Set the register description. The address computation is the same
626 * for sources and destinations. */
627 if (src) {
628 reg.Register.File = src->Register.File;
629 reg.Register.Index = src->Register.Index;
630 reg.Register.Indirect = src->Register.Indirect;
631 reg.Register.Dimension = src->Register.Dimension;
632 reg.Indirect = src->Indirect;
633 reg.Dimension = src->Dimension;
634 reg.DimIndirect = src->DimIndirect;
635 } else
636 reg = *dst;
637
638 /* If the register is 2-dimensional (e.g. an array of vertices
639 * in a primitive), calculate the base address of the vertex. */
640 if (reg.Register.Dimension) {
641 LLVMValueRef index;
642
643 if (reg.Dimension.Indirect)
644 index = get_indirect_index(ctx, &reg.DimIndirect,
645 reg.Dimension.Index);
646 else
647 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
648
649 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
650 LLVMBuildMul(gallivm->builder, index,
651 vertex_dw_stride, ""), "");
652 }
653
654 /* Get information about the register. */
655 if (reg.Register.File == TGSI_FILE_INPUT) {
656 name = info->input_semantic_name;
657 index = info->input_semantic_index;
658 array_first = info->input_array_first;
659 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
660 name = info->output_semantic_name;
661 index = info->output_semantic_index;
662 array_first = info->output_array_first;
663 } else {
664 assert(0);
665 return NULL;
666 }
667
668 if (reg.Register.Indirect) {
669 /* Add the relative address of the element. */
670 LLVMValueRef ind_index;
671
672 if (reg.Indirect.ArrayID)
673 first = array_first[reg.Indirect.ArrayID];
674 else
675 first = reg.Register.Index;
676
677 ind_index = get_indirect_index(ctx, &reg.Indirect,
678 reg.Register.Index - first);
679
680 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
681 LLVMBuildMul(gallivm->builder, ind_index,
682 lp_build_const_int32(gallivm, 4), ""), "");
683
684 param = si_shader_io_get_unique_index(name[first], index[first]);
685 } else {
686 param = si_shader_io_get_unique_index(name[reg.Register.Index],
687 index[reg.Register.Index]);
688 }
689
690 /* Add the base address of the element. */
691 return LLVMBuildAdd(gallivm->builder, base_addr,
692 lp_build_const_int32(gallivm, param * 4), "");
693 }
694
695 /* The offchip buffer layout for TCS->TES is
696 *
697 * - attribute 0 of patch 0 vertex 0
698 * - attribute 0 of patch 0 vertex 1
699 * - attribute 0 of patch 0 vertex 2
700 * ...
701 * - attribute 0 of patch 1 vertex 0
702 * - attribute 0 of patch 1 vertex 1
703 * ...
704 * - attribute 1 of patch 0 vertex 0
705 * - attribute 1 of patch 0 vertex 1
706 * ...
707 * - per patch attribute 0 of patch 0
708 * - per patch attribute 0 of patch 1
709 * ...
710 *
711 * Note that every attribute has 4 components.
712 */
713 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
714 LLVMValueRef rel_patch_id,
715 LLVMValueRef vertex_index,
716 LLVMValueRef param_index)
717 {
718 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
719 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
720 LLVMValueRef param_stride, constant16;
721
722 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
723 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
724 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
725 num_patches, "");
726
727 constant16 = lp_build_const_int32(gallivm, 16);
728 if (vertex_index) {
729 base_addr = LLVMBuildMul(gallivm->builder, rel_patch_id,
730 vertices_per_patch, "");
731
732 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
733 vertex_index, "");
734
735 param_stride = total_vertices;
736 } else {
737 base_addr = rel_patch_id;
738 param_stride = num_patches;
739 }
740
741 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
742 LLVMBuildMul(gallivm->builder, param_index,
743 param_stride, ""), "");
744
745 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
746
747 if (!vertex_index) {
748 LLVMValueRef patch_data_offset =
749 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
750
751 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
752 patch_data_offset, "");
753 }
754 return base_addr;
755 }
756
757 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
758 struct si_shader_context *ctx,
759 const struct tgsi_full_dst_register *dst,
760 const struct tgsi_full_src_register *src)
761 {
762 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
763 struct tgsi_shader_info *info = &ctx->shader->selector->info;
764 ubyte *name, *index, *array_first;
765 struct tgsi_full_src_register reg;
766 LLVMValueRef vertex_index = NULL;
767 LLVMValueRef param_index = NULL;
768 unsigned param_index_base, param_base;
769
770 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
771
772 if (reg.Register.Dimension) {
773
774 if (reg.Dimension.Indirect)
775 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
776 reg.Dimension.Index);
777 else
778 vertex_index = lp_build_const_int32(gallivm,
779 reg.Dimension.Index);
780 }
781
782 /* Get information about the register. */
783 if (reg.Register.File == TGSI_FILE_INPUT) {
784 name = info->input_semantic_name;
785 index = info->input_semantic_index;
786 array_first = info->input_array_first;
787 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
788 name = info->output_semantic_name;
789 index = info->output_semantic_index;
790 array_first = info->output_array_first;
791 } else {
792 assert(0);
793 return NULL;
794 }
795
796 if (reg.Register.Indirect) {
797 if (reg.Indirect.ArrayID)
798 param_base = array_first[reg.Indirect.ArrayID];
799 else
800 param_base = reg.Register.Index;
801
802 param_index = get_indirect_index(ctx, &reg.Indirect,
803 reg.Register.Index - param_base);
804
805 } else {
806 param_base = reg.Register.Index;
807 param_index = lp_build_const_int32(gallivm, 0);
808 }
809
810 param_index_base = si_shader_io_get_unique_index(name[param_base],
811 index[param_base]);
812
813 param_index = LLVMBuildAdd(gallivm->builder, param_index,
814 lp_build_const_int32(gallivm, param_index_base),
815 "");
816
817 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
818 vertex_index, param_index);
819 }
820
821 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
822 enum tgsi_opcode_type type, unsigned swizzle,
823 LLVMValueRef buffer, LLVMValueRef offset,
824 LLVMValueRef base, bool readonly_memory)
825 {
826 struct si_shader_context *ctx = si_shader_context(bld_base);
827 struct gallivm_state *gallivm = bld_base->base.gallivm;
828 LLVMValueRef value, value2;
829 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
830 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
831
832 if (swizzle == ~0) {
833 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
834 0, 1, 0, readonly_memory);
835
836 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
837 }
838
839 if (!tgsi_type_is_64bit(type)) {
840 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
841 0, 1, 0, readonly_memory);
842
843 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
844 return LLVMBuildExtractElement(gallivm->builder, value,
845 lp_build_const_int32(gallivm, swizzle), "");
846 }
847
848 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
849 swizzle * 4, 1, 0, readonly_memory);
850
851 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
852 swizzle * 4 + 4, 1, 0, readonly_memory);
853
854 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
855 }
856
857 /**
858 * Load from LDS.
859 *
860 * \param type output value type
861 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
862 * \param dw_addr address in dwords
863 */
864 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
865 enum tgsi_opcode_type type, unsigned swizzle,
866 LLVMValueRef dw_addr)
867 {
868 struct si_shader_context *ctx = si_shader_context(bld_base);
869 struct gallivm_state *gallivm = bld_base->base.gallivm;
870 LLVMValueRef value;
871
872 if (swizzle == ~0) {
873 LLVMValueRef values[TGSI_NUM_CHANNELS];
874
875 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
876 values[chan] = lds_load(bld_base, type, chan, dw_addr);
877
878 return lp_build_gather_values(bld_base->base.gallivm, values,
879 TGSI_NUM_CHANNELS);
880 }
881
882 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
883 lp_build_const_int32(gallivm, swizzle));
884
885 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
886 if (tgsi_type_is_64bit(type)) {
887 LLVMValueRef value2;
888 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
889 lp_build_const_int32(gallivm, 1));
890 value2 = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
891 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
892 }
893
894 return LLVMBuildBitCast(gallivm->builder, value,
895 tgsi2llvmtype(bld_base, type), "");
896 }
897
898 /**
899 * Store to LDS.
900 *
901 * \param swizzle offset (typically 0..3)
902 * \param dw_addr address in dwords
903 * \param value value to store
904 */
905 static void lds_store(struct lp_build_tgsi_context *bld_base,
906 unsigned swizzle, LLVMValueRef dw_addr,
907 LLVMValueRef value)
908 {
909 struct si_shader_context *ctx = si_shader_context(bld_base);
910 struct gallivm_state *gallivm = bld_base->base.gallivm;
911
912 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
913 lp_build_const_int32(gallivm, swizzle));
914
915 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
916 ac_build_indexed_store(&ctx->ac, ctx->lds,
917 dw_addr, value);
918 }
919
920 static LLVMValueRef fetch_input_tcs(
921 struct lp_build_tgsi_context *bld_base,
922 const struct tgsi_full_src_register *reg,
923 enum tgsi_opcode_type type, unsigned swizzle)
924 {
925 struct si_shader_context *ctx = si_shader_context(bld_base);
926 LLVMValueRef dw_addr, stride;
927
928 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
929 dw_addr = get_tcs_in_current_patch_offset(ctx);
930 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
931
932 return lds_load(bld_base, type, swizzle, dw_addr);
933 }
934
935 static LLVMValueRef fetch_output_tcs(
936 struct lp_build_tgsi_context *bld_base,
937 const struct tgsi_full_src_register *reg,
938 enum tgsi_opcode_type type, unsigned swizzle)
939 {
940 struct si_shader_context *ctx = si_shader_context(bld_base);
941 LLVMValueRef dw_addr, stride;
942
943 if (reg->Register.Dimension) {
944 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
945 dw_addr = get_tcs_out_current_patch_offset(ctx);
946 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
947 } else {
948 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
949 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
950 }
951
952 return lds_load(bld_base, type, swizzle, dw_addr);
953 }
954
955 static LLVMValueRef fetch_input_tes(
956 struct lp_build_tgsi_context *bld_base,
957 const struct tgsi_full_src_register *reg,
958 enum tgsi_opcode_type type, unsigned swizzle)
959 {
960 struct si_shader_context *ctx = si_shader_context(bld_base);
961 struct gallivm_state *gallivm = bld_base->base.gallivm;
962 LLVMValueRef rw_buffers, buffer, base, addr;
963
964 rw_buffers = LLVMGetParam(ctx->main_fn,
965 SI_PARAM_RW_BUFFERS);
966 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
967 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
968
969 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
970 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
971
972 return buffer_load(bld_base, type, swizzle, buffer, base, addr, true);
973 }
974
975 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
976 const struct tgsi_full_instruction *inst,
977 const struct tgsi_opcode_info *info,
978 LLVMValueRef dst[4])
979 {
980 struct si_shader_context *ctx = si_shader_context(bld_base);
981 struct gallivm_state *gallivm = bld_base->base.gallivm;
982 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
983 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
984 unsigned chan_index;
985 LLVMValueRef dw_addr, stride;
986 LLVMValueRef rw_buffers, buffer, base, buf_addr;
987 LLVMValueRef values[4];
988 bool skip_lds_store;
989 bool is_tess_factor = false;
990
991 /* Only handle per-patch and per-vertex outputs here.
992 * Vectors will be lowered to scalars and this function will be called again.
993 */
994 if (reg->Register.File != TGSI_FILE_OUTPUT ||
995 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
996 si_llvm_emit_store(bld_base, inst, info, dst);
997 return;
998 }
999
1000 if (reg->Register.Dimension) {
1001 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1002 dw_addr = get_tcs_out_current_patch_offset(ctx);
1003 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1004 skip_lds_store = !sh_info->reads_pervertex_outputs;
1005 } else {
1006 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1007 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1008 skip_lds_store = !sh_info->reads_perpatch_outputs;
1009
1010 if (!reg->Register.Indirect) {
1011 int name = sh_info->output_semantic_name[reg->Register.Index];
1012
1013 /* Always write tess factors into LDS for the TCS epilog. */
1014 if (name == TGSI_SEMANTIC_TESSINNER ||
1015 name == TGSI_SEMANTIC_TESSOUTER) {
1016 skip_lds_store = false;
1017 is_tess_factor = true;
1018 }
1019 }
1020 }
1021
1022 rw_buffers = LLVMGetParam(ctx->main_fn,
1023 SI_PARAM_RW_BUFFERS);
1024 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
1025 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1026
1027 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1028 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1029
1030
1031 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1032 LLVMValueRef value = dst[chan_index];
1033
1034 if (inst->Instruction.Saturate)
1035 value = ac_build_clamp(&ctx->ac, value);
1036
1037 /* Skip LDS stores if there is no LDS read of this output. */
1038 if (!skip_lds_store)
1039 lds_store(bld_base, chan_index, dw_addr, value);
1040
1041 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1042 values[chan_index] = value;
1043
1044 if (inst->Dst[0].Register.WriteMask != 0xF && !is_tess_factor) {
1045 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1046 buf_addr, base,
1047 4 * chan_index, 1, 0, true, false);
1048 }
1049 }
1050
1051 if (inst->Dst[0].Register.WriteMask == 0xF && !is_tess_factor) {
1052 LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
1053 values, 4);
1054 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1055 base, 0, 1, 0, true, false);
1056 }
1057 }
1058
1059 static LLVMValueRef fetch_input_gs(
1060 struct lp_build_tgsi_context *bld_base,
1061 const struct tgsi_full_src_register *reg,
1062 enum tgsi_opcode_type type,
1063 unsigned swizzle)
1064 {
1065 struct lp_build_context *base = &bld_base->base;
1066 struct si_shader_context *ctx = si_shader_context(bld_base);
1067 struct si_shader *shader = ctx->shader;
1068 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1069 struct gallivm_state *gallivm = base->gallivm;
1070 LLVMValueRef vtx_offset, soffset;
1071 unsigned vtx_offset_param;
1072 struct tgsi_shader_info *info = &shader->selector->info;
1073 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1074 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1075 unsigned param;
1076 LLVMValueRef value;
1077
1078 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1079 return get_primitive_id(bld_base, swizzle);
1080
1081 if (!reg->Register.Dimension)
1082 return NULL;
1083
1084 if (swizzle == ~0) {
1085 LLVMValueRef values[TGSI_NUM_CHANNELS];
1086 unsigned chan;
1087 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1088 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1089 }
1090 return lp_build_gather_values(bld_base->base.gallivm, values,
1091 TGSI_NUM_CHANNELS);
1092 }
1093
1094 /* Get the vertex offset parameter */
1095 vtx_offset_param = reg->Dimension.Index;
1096 if (vtx_offset_param < 2) {
1097 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1098 } else {
1099 assert(vtx_offset_param < 6);
1100 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1101 }
1102 vtx_offset = lp_build_mul_imm(uint,
1103 LLVMGetParam(ctx->main_fn,
1104 vtx_offset_param),
1105 4);
1106
1107 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1108 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1109
1110 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, uint->zero,
1111 vtx_offset, soffset, 0, 1, 0, true);
1112 if (tgsi_type_is_64bit(type)) {
1113 LLVMValueRef value2;
1114 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1115
1116 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1117 uint->zero, vtx_offset, soffset,
1118 0, 1, 0, true);
1119 return si_llvm_emit_fetch_64bit(bld_base, type,
1120 value, value2);
1121 }
1122 return LLVMBuildBitCast(gallivm->builder,
1123 value,
1124 tgsi2llvmtype(bld_base, type), "");
1125 }
1126
1127 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1128 {
1129 switch (interpolate) {
1130 case TGSI_INTERPOLATE_CONSTANT:
1131 return 0;
1132
1133 case TGSI_INTERPOLATE_LINEAR:
1134 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1135 return SI_PARAM_LINEAR_SAMPLE;
1136 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1137 return SI_PARAM_LINEAR_CENTROID;
1138 else
1139 return SI_PARAM_LINEAR_CENTER;
1140 break;
1141 case TGSI_INTERPOLATE_COLOR:
1142 case TGSI_INTERPOLATE_PERSPECTIVE:
1143 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1144 return SI_PARAM_PERSP_SAMPLE;
1145 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1146 return SI_PARAM_PERSP_CENTROID;
1147 else
1148 return SI_PARAM_PERSP_CENTER;
1149 break;
1150 default:
1151 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1152 return -1;
1153 }
1154 }
1155
1156 /**
1157 * Interpolate a fragment shader input.
1158 *
1159 * @param ctx context
1160 * @param input_index index of the input in hardware
1161 * @param semantic_name TGSI_SEMANTIC_*
1162 * @param semantic_index semantic index
1163 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1164 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1165 * @param interp_param interpolation weights (i,j)
1166 * @param prim_mask SI_PARAM_PRIM_MASK
1167 * @param face SI_PARAM_FRONT_FACE
1168 * @param result the return value (4 components)
1169 */
1170 static void interp_fs_input(struct si_shader_context *ctx,
1171 unsigned input_index,
1172 unsigned semantic_name,
1173 unsigned semantic_index,
1174 unsigned num_interp_inputs,
1175 unsigned colors_read_mask,
1176 LLVMValueRef interp_param,
1177 LLVMValueRef prim_mask,
1178 LLVMValueRef face,
1179 LLVMValueRef result[4])
1180 {
1181 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1182 struct lp_build_context *base = &bld_base->base;
1183 struct lp_build_context *uint = &bld_base->uint_bld;
1184 struct gallivm_state *gallivm = base->gallivm;
1185 LLVMValueRef attr_number;
1186 LLVMValueRef i, j;
1187
1188 unsigned chan;
1189
1190 /* fs.constant returns the param from the middle vertex, so it's not
1191 * really useful for flat shading. It's meant to be used for custom
1192 * interpolation (but the intrinsic can't fetch from the other two
1193 * vertices).
1194 *
1195 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1196 * to do the right thing. The only reason we use fs.constant is that
1197 * fs.interp cannot be used on integers, because they can be equal
1198 * to NaN.
1199 *
1200 * When interp is false we will use fs.constant or for newer llvm,
1201 * amdgcn.interp.mov.
1202 */
1203 bool interp = interp_param != NULL;
1204
1205 attr_number = lp_build_const_int32(gallivm, input_index);
1206
1207 if (interp) {
1208 interp_param = LLVMBuildBitCast(gallivm->builder, interp_param,
1209 LLVMVectorType(ctx->f32, 2), "");
1210
1211 i = LLVMBuildExtractElement(gallivm->builder, interp_param,
1212 uint->zero, "");
1213 j = LLVMBuildExtractElement(gallivm->builder, interp_param,
1214 uint->one, "");
1215 }
1216
1217 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1218 ctx->shader->key.part.ps.prolog.color_two_side) {
1219 LLVMValueRef is_face_positive;
1220 LLVMValueRef back_attr_number;
1221
1222 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1223 * otherwise it's at offset "num_inputs".
1224 */
1225 unsigned back_attr_offset = num_interp_inputs;
1226 if (semantic_index == 1 && colors_read_mask & 0xf)
1227 back_attr_offset += 1;
1228
1229 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1230
1231 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1232 face, uint->zero, "");
1233
1234 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1235 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1236 LLVMValueRef front, back;
1237
1238 if (interp) {
1239 front = ac_build_fs_interp(&ctx->ac, llvm_chan,
1240 attr_number, prim_mask,
1241 i, j);
1242 back = ac_build_fs_interp(&ctx->ac, llvm_chan,
1243 back_attr_number, prim_mask,
1244 i, j);
1245 } else {
1246 front = ac_build_fs_interp_mov(&ctx->ac,
1247 lp_build_const_int32(gallivm, 2), /* P0 */
1248 llvm_chan, attr_number, prim_mask);
1249 back = ac_build_fs_interp_mov(&ctx->ac,
1250 lp_build_const_int32(gallivm, 2), /* P0 */
1251 llvm_chan, back_attr_number, prim_mask);
1252 }
1253
1254 result[chan] = LLVMBuildSelect(gallivm->builder,
1255 is_face_positive,
1256 front,
1257 back,
1258 "");
1259 }
1260 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1261 if (interp) {
1262 result[0] = ac_build_fs_interp(&ctx->ac, uint->zero,
1263 attr_number, prim_mask, i, j);
1264 } else {
1265 result[0] = ac_build_fs_interp_mov(&ctx->ac, uint->zero,
1266 lp_build_const_int32(gallivm, 2), /* P0 */
1267 attr_number, prim_mask);
1268 }
1269 result[1] =
1270 result[2] = lp_build_const_float(gallivm, 0.0f);
1271 result[3] = lp_build_const_float(gallivm, 1.0f);
1272 } else {
1273 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1274 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1275
1276 if (interp) {
1277 result[chan] = ac_build_fs_interp(&ctx->ac,
1278 llvm_chan, attr_number, prim_mask, i, j);
1279 } else {
1280 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
1281 lp_build_const_int32(gallivm, 2), /* P0 */
1282 llvm_chan, attr_number, prim_mask);
1283 }
1284 }
1285 }
1286 }
1287
1288 static void declare_input_fs(
1289 struct si_shader_context *radeon_bld,
1290 unsigned input_index,
1291 const struct tgsi_full_declaration *decl,
1292 LLVMValueRef out[4])
1293 {
1294 struct lp_build_context *base = &radeon_bld->bld_base.base;
1295 struct si_shader_context *ctx =
1296 si_shader_context(&radeon_bld->bld_base);
1297 struct si_shader *shader = ctx->shader;
1298 LLVMValueRef main_fn = radeon_bld->main_fn;
1299 LLVMValueRef interp_param = NULL;
1300 int interp_param_idx;
1301
1302 /* Get colors from input VGPRs (set by the prolog). */
1303 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1304 unsigned i = decl->Semantic.Index;
1305 unsigned colors_read = shader->selector->info.colors_read;
1306 unsigned mask = colors_read >> (i * 4);
1307 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1308 (i ? util_bitcount(colors_read & 0xf) : 0);
1309
1310 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1311 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1312 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1313 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1314 return;
1315 }
1316
1317 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1318 decl->Interp.Location);
1319 if (interp_param_idx == -1)
1320 return;
1321 else if (interp_param_idx) {
1322 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1323 }
1324
1325 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
1326 decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR &&
1327 ctx->shader->key.part.ps.prolog.flatshade_colors)
1328 interp_param = NULL; /* load the constant color */
1329
1330 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1331 decl->Semantic.Index, shader->selector->info.num_inputs,
1332 shader->selector->info.colors_read, interp_param,
1333 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1334 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1335 &out[0]);
1336 }
1337
1338 static LLVMValueRef get_sample_id(struct si_shader_context *radeon_bld)
1339 {
1340 return unpack_param(si_shader_context(&radeon_bld->bld_base),
1341 SI_PARAM_ANCILLARY, 8, 4);
1342 }
1343
1344
1345 /**
1346 * Load a dword from a constant buffer.
1347 */
1348 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1349 LLVMValueRef resource,
1350 LLVMValueRef offset)
1351 {
1352 LLVMBuilderRef builder = ctx->gallivm.builder;
1353 LLVMValueRef args[2] = {resource, offset};
1354
1355 return lp_build_intrinsic(builder, "llvm.SI.load.const", ctx->f32, args, 2,
1356 LP_FUNC_ATTR_READNONE |
1357 LP_FUNC_ATTR_LEGACY);
1358 }
1359
1360 static LLVMValueRef load_sample_position(struct si_shader_context *radeon_bld, LLVMValueRef sample_id)
1361 {
1362 struct si_shader_context *ctx =
1363 si_shader_context(&radeon_bld->bld_base);
1364 struct lp_build_context *uint_bld = &radeon_bld->bld_base.uint_bld;
1365 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1366 LLVMBuilderRef builder = gallivm->builder;
1367 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1368 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1369 LLVMValueRef resource = ac_build_indexed_load_const(&ctx->ac, desc, buf_index);
1370
1371 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1372 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1373 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1374
1375 LLVMValueRef pos[4] = {
1376 buffer_load_const(ctx, resource, offset0),
1377 buffer_load_const(ctx, resource, offset1),
1378 lp_build_const_float(gallivm, 0),
1379 lp_build_const_float(gallivm, 0)
1380 };
1381
1382 return lp_build_gather_values(gallivm, pos, 4);
1383 }
1384
1385 static void declare_system_value(
1386 struct si_shader_context *radeon_bld,
1387 unsigned index,
1388 const struct tgsi_full_declaration *decl)
1389 {
1390 struct si_shader_context *ctx =
1391 si_shader_context(&radeon_bld->bld_base);
1392 struct lp_build_context *bld = &radeon_bld->bld_base.base;
1393 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1394 LLVMValueRef value = 0;
1395
1396 switch (decl->Semantic.Name) {
1397 case TGSI_SEMANTIC_INSTANCEID:
1398 value = LLVMGetParam(radeon_bld->main_fn,
1399 ctx->param_instance_id);
1400 break;
1401
1402 case TGSI_SEMANTIC_VERTEXID:
1403 value = LLVMBuildAdd(gallivm->builder,
1404 LLVMGetParam(radeon_bld->main_fn,
1405 ctx->param_vertex_id),
1406 LLVMGetParam(radeon_bld->main_fn,
1407 SI_PARAM_BASE_VERTEX), "");
1408 break;
1409
1410 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1411 value = LLVMGetParam(radeon_bld->main_fn,
1412 ctx->param_vertex_id);
1413 break;
1414
1415 case TGSI_SEMANTIC_BASEVERTEX:
1416 value = LLVMGetParam(radeon_bld->main_fn,
1417 SI_PARAM_BASE_VERTEX);
1418 break;
1419
1420 case TGSI_SEMANTIC_BASEINSTANCE:
1421 value = LLVMGetParam(radeon_bld->main_fn,
1422 SI_PARAM_START_INSTANCE);
1423 break;
1424
1425 case TGSI_SEMANTIC_DRAWID:
1426 value = LLVMGetParam(radeon_bld->main_fn,
1427 SI_PARAM_DRAWID);
1428 break;
1429
1430 case TGSI_SEMANTIC_INVOCATIONID:
1431 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1432 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1433 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1434 value = LLVMGetParam(radeon_bld->main_fn,
1435 SI_PARAM_GS_INSTANCE_ID);
1436 else
1437 assert(!"INVOCATIONID not implemented");
1438 break;
1439
1440 case TGSI_SEMANTIC_POSITION:
1441 {
1442 LLVMValueRef pos[4] = {
1443 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1444 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1445 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1446 lp_build_emit_llvm_unary(&radeon_bld->bld_base, TGSI_OPCODE_RCP,
1447 LLVMGetParam(radeon_bld->main_fn,
1448 SI_PARAM_POS_W_FLOAT)),
1449 };
1450 value = lp_build_gather_values(gallivm, pos, 4);
1451 break;
1452 }
1453
1454 case TGSI_SEMANTIC_FACE:
1455 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1456 break;
1457
1458 case TGSI_SEMANTIC_SAMPLEID:
1459 value = get_sample_id(radeon_bld);
1460 break;
1461
1462 case TGSI_SEMANTIC_SAMPLEPOS: {
1463 LLVMValueRef pos[4] = {
1464 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1465 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1466 lp_build_const_float(gallivm, 0),
1467 lp_build_const_float(gallivm, 0)
1468 };
1469 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->bld_base,
1470 TGSI_OPCODE_FRC, pos[0]);
1471 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->bld_base,
1472 TGSI_OPCODE_FRC, pos[1]);
1473 value = lp_build_gather_values(gallivm, pos, 4);
1474 break;
1475 }
1476
1477 case TGSI_SEMANTIC_SAMPLEMASK:
1478 /* This can only occur with the OpenGL Core profile, which
1479 * doesn't support smoothing.
1480 */
1481 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1482 break;
1483
1484 case TGSI_SEMANTIC_TESSCOORD:
1485 {
1486 LLVMValueRef coord[4] = {
1487 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1488 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1489 bld->zero,
1490 bld->zero
1491 };
1492
1493 /* For triangles, the vector should be (u, v, 1-u-v). */
1494 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1495 PIPE_PRIM_TRIANGLES)
1496 coord[2] = lp_build_sub(bld, bld->one,
1497 lp_build_add(bld, coord[0], coord[1]));
1498
1499 value = lp_build_gather_values(gallivm, coord, 4);
1500 break;
1501 }
1502
1503 case TGSI_SEMANTIC_VERTICESIN:
1504 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1505 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1506 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1507 value = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 7);
1508 else
1509 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1510 break;
1511
1512 case TGSI_SEMANTIC_TESSINNER:
1513 case TGSI_SEMANTIC_TESSOUTER:
1514 {
1515 LLVMValueRef rw_buffers, buffer, base, addr;
1516 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1517
1518 rw_buffers = LLVMGetParam(ctx->main_fn,
1519 SI_PARAM_RW_BUFFERS);
1520 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
1521 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1522
1523 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1524 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1525 lp_build_const_int32(gallivm, param));
1526
1527 value = buffer_load(&radeon_bld->bld_base, TGSI_TYPE_FLOAT,
1528 ~0, buffer, base, addr, true);
1529
1530 break;
1531 }
1532
1533 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1534 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1535 {
1536 LLVMValueRef buf, slot, val[4];
1537 int i, offset;
1538
1539 slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
1540 buf = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1541 buf = ac_build_indexed_load_const(&ctx->ac, buf, slot);
1542 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1543
1544 for (i = 0; i < 4; i++)
1545 val[i] = buffer_load_const(ctx, buf,
1546 lp_build_const_int32(gallivm, (offset + i) * 4));
1547 value = lp_build_gather_values(gallivm, val, 4);
1548 break;
1549 }
1550
1551 case TGSI_SEMANTIC_PRIMID:
1552 value = get_primitive_id(&radeon_bld->bld_base, 0);
1553 break;
1554
1555 case TGSI_SEMANTIC_GRID_SIZE:
1556 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1557 break;
1558
1559 case TGSI_SEMANTIC_BLOCK_SIZE:
1560 {
1561 LLVMValueRef values[3];
1562 unsigned i;
1563 unsigned *properties = ctx->shader->selector->info.properties;
1564
1565 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1566 unsigned sizes[3] = {
1567 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1568 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1569 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1570 };
1571
1572 for (i = 0; i < 3; ++i)
1573 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1574
1575 value = lp_build_gather_values(gallivm, values, 3);
1576 } else {
1577 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_SIZE);
1578 }
1579 break;
1580 }
1581
1582 case TGSI_SEMANTIC_BLOCK_ID:
1583 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1584 break;
1585
1586 case TGSI_SEMANTIC_THREAD_ID:
1587 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1588 break;
1589
1590 case TGSI_SEMANTIC_HELPER_INVOCATION:
1591 if (HAVE_LLVM >= 0x0309) {
1592 value = lp_build_intrinsic(gallivm->builder,
1593 "llvm.amdgcn.ps.live",
1594 ctx->i1, NULL, 0,
1595 LP_FUNC_ATTR_READNONE);
1596 value = LLVMBuildNot(gallivm->builder, value, "");
1597 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1598 } else {
1599 assert(!"TGSI_SEMANTIC_HELPER_INVOCATION unsupported");
1600 return;
1601 }
1602 break;
1603
1604 default:
1605 assert(!"unknown system value");
1606 return;
1607 }
1608
1609 radeon_bld->system_values[index] = value;
1610 }
1611
1612 static void declare_compute_memory(struct si_shader_context *radeon_bld,
1613 const struct tgsi_full_declaration *decl)
1614 {
1615 struct si_shader_context *ctx =
1616 si_shader_context(&radeon_bld->bld_base);
1617 struct si_shader_selector *sel = ctx->shader->selector;
1618 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1619
1620 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1621 LLVMValueRef var;
1622
1623 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1624 assert(decl->Range.First == decl->Range.Last);
1625 assert(!ctx->shared_memory);
1626
1627 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1628 LLVMArrayType(ctx->i8, sel->local_size),
1629 "compute_lds",
1630 LOCAL_ADDR_SPACE);
1631 LLVMSetAlignment(var, 4);
1632
1633 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1634 }
1635
1636 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1637 {
1638 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1639 SI_PARAM_CONST_BUFFERS);
1640
1641 return ac_build_indexed_load_const(&ctx->ac, list_ptr,
1642 LLVMConstInt(ctx->i32, i, 0));
1643 }
1644
1645 static LLVMValueRef fetch_constant(
1646 struct lp_build_tgsi_context *bld_base,
1647 const struct tgsi_full_src_register *reg,
1648 enum tgsi_opcode_type type,
1649 unsigned swizzle)
1650 {
1651 struct si_shader_context *ctx = si_shader_context(bld_base);
1652 struct lp_build_context *base = &bld_base->base;
1653 const struct tgsi_ind_register *ireg = &reg->Indirect;
1654 unsigned buf, idx;
1655
1656 LLVMValueRef addr, bufp;
1657 LLVMValueRef result;
1658
1659 if (swizzle == LP_CHAN_ALL) {
1660 unsigned chan;
1661 LLVMValueRef values[4];
1662 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1663 values[chan] = fetch_constant(bld_base, reg, type, chan);
1664
1665 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1666 }
1667
1668 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1669 idx = reg->Register.Index * 4 + swizzle;
1670
1671 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1672 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_CONST_BUFFERS);
1673 LLVMValueRef index;
1674 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1675 reg->Dimension.Index,
1676 SI_NUM_CONST_BUFFERS);
1677 bufp = ac_build_indexed_load_const(&ctx->ac, ptr, index);
1678 } else
1679 bufp = load_const_buffer_desc(ctx, buf);
1680
1681 if (reg->Register.Indirect) {
1682 addr = ctx->addrs[ireg->Index][ireg->Swizzle];
1683 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1684 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1685 addr = lp_build_add(&bld_base->uint_bld, addr,
1686 lp_build_const_int32(base->gallivm, idx * 4));
1687 } else {
1688 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
1689 }
1690
1691 result = buffer_load_const(ctx, bufp, addr);
1692
1693 if (!tgsi_type_is_64bit(type))
1694 result = bitcast(bld_base, type, result);
1695 else {
1696 LLVMValueRef addr2, result2;
1697
1698 addr2 = lp_build_add(&bld_base->uint_bld, addr,
1699 LLVMConstInt(ctx->i32, 4, 0));
1700 result2 = buffer_load_const(ctx, bufp, addr2);
1701
1702 result = si_llvm_emit_fetch_64bit(bld_base, type,
1703 result, result2);
1704 }
1705 return result;
1706 }
1707
1708 /* Upper 16 bits must be zero. */
1709 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1710 LLVMValueRef val[2])
1711 {
1712 return LLVMBuildOr(gallivm->builder, val[0],
1713 LLVMBuildShl(gallivm->builder, val[1],
1714 lp_build_const_int32(gallivm, 16),
1715 ""), "");
1716 }
1717
1718 /* Upper 16 bits are ignored and will be dropped. */
1719 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1720 LLVMValueRef val[2])
1721 {
1722 LLVMValueRef v[2] = {
1723 LLVMBuildAnd(gallivm->builder, val[0],
1724 lp_build_const_int32(gallivm, 0xffff), ""),
1725 val[1],
1726 };
1727 return si_llvm_pack_two_int16(gallivm, v);
1728 }
1729
1730 /* Initialize arguments for the shader export intrinsic */
1731 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1732 LLVMValueRef *values,
1733 unsigned target,
1734 struct ac_export_args *args)
1735 {
1736 struct si_shader_context *ctx = si_shader_context(bld_base);
1737 struct lp_build_context *base = &bld_base->base;
1738 struct gallivm_state *gallivm = base->gallivm;
1739 LLVMBuilderRef builder = base->gallivm->builder;
1740 LLVMValueRef val[4];
1741 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1742 unsigned chan;
1743 bool is_int8, is_int10;
1744
1745 /* Default is 0xf. Adjusted below depending on the format. */
1746 args->enabled_channels = 0xf; /* writemask */
1747
1748 /* Specify whether the EXEC mask represents the valid mask */
1749 args->valid_mask = 0;
1750
1751 /* Specify whether this is the last export */
1752 args->done = 0;
1753
1754 /* Specify the target we are exporting */
1755 args->target = target;
1756
1757 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1758 const struct si_shader_key *key = &ctx->shader->key;
1759 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
1760 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1761
1762 assert(cbuf >= 0 && cbuf < 8);
1763 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1764 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
1765 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
1766 }
1767
1768 args->compr = false;
1769 args->out[0] = base->undef;
1770 args->out[1] = base->undef;
1771 args->out[2] = base->undef;
1772 args->out[3] = base->undef;
1773
1774 switch (spi_shader_col_format) {
1775 case V_028714_SPI_SHADER_ZERO:
1776 args->enabled_channels = 0; /* writemask */
1777 args->target = V_008DFC_SQ_EXP_NULL;
1778 break;
1779
1780 case V_028714_SPI_SHADER_32_R:
1781 args->enabled_channels = 1; /* writemask */
1782 args->out[0] = values[0];
1783 break;
1784
1785 case V_028714_SPI_SHADER_32_GR:
1786 args->enabled_channels = 0x3; /* writemask */
1787 args->out[0] = values[0];
1788 args->out[1] = values[1];
1789 break;
1790
1791 case V_028714_SPI_SHADER_32_AR:
1792 args->enabled_channels = 0x9; /* writemask */
1793 args->out[0] = values[0];
1794 args->out[3] = values[3];
1795 break;
1796
1797 case V_028714_SPI_SHADER_FP16_ABGR:
1798 args->compr = 1; /* COMPR flag */
1799
1800 for (chan = 0; chan < 2; chan++) {
1801 LLVMValueRef pack_args[2] = {
1802 values[2 * chan],
1803 values[2 * chan + 1]
1804 };
1805 LLVMValueRef packed;
1806
1807 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
1808 args->out[chan] =
1809 LLVMBuildBitCast(base->gallivm->builder,
1810 packed, ctx->f32, "");
1811 }
1812 break;
1813
1814 case V_028714_SPI_SHADER_UNORM16_ABGR:
1815 for (chan = 0; chan < 4; chan++) {
1816 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
1817 val[chan] = LLVMBuildFMul(builder, val[chan],
1818 lp_build_const_float(gallivm, 65535), "");
1819 val[chan] = LLVMBuildFAdd(builder, val[chan],
1820 lp_build_const_float(gallivm, 0.5), "");
1821 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1822 ctx->i32, "");
1823 }
1824
1825 args->compr = 1; /* COMPR flag */
1826 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1827 si_llvm_pack_two_int16(gallivm, val));
1828 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1829 si_llvm_pack_two_int16(gallivm, val+2));
1830 break;
1831
1832 case V_028714_SPI_SHADER_SNORM16_ABGR:
1833 for (chan = 0; chan < 4; chan++) {
1834 /* Clamp between [-1, 1]. */
1835 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1836 values[chan],
1837 lp_build_const_float(gallivm, 1));
1838 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1839 val[chan],
1840 lp_build_const_float(gallivm, -1));
1841 /* Convert to a signed integer in [-32767, 32767]. */
1842 val[chan] = LLVMBuildFMul(builder, val[chan],
1843 lp_build_const_float(gallivm, 32767), "");
1844 /* If positive, add 0.5, else add -0.5. */
1845 val[chan] = LLVMBuildFAdd(builder, val[chan],
1846 LLVMBuildSelect(builder,
1847 LLVMBuildFCmp(builder, LLVMRealOGE,
1848 val[chan], base->zero, ""),
1849 lp_build_const_float(gallivm, 0.5),
1850 lp_build_const_float(gallivm, -0.5), ""), "");
1851 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
1852 }
1853
1854 args->compr = 1; /* COMPR flag */
1855 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1856 si_llvm_pack_two_int32_as_int16(gallivm, val));
1857 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1858 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1859 break;
1860
1861 case V_028714_SPI_SHADER_UINT16_ABGR: {
1862 LLVMValueRef max_rgb = lp_build_const_int32(gallivm,
1863 is_int8 ? 255 : is_int10 ? 1023 : 65535);
1864 LLVMValueRef max_alpha =
1865 !is_int10 ? max_rgb : lp_build_const_int32(gallivm, 3);
1866
1867 /* Clamp. */
1868 for (chan = 0; chan < 4; chan++) {
1869 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1870 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1871 val[chan],
1872 chan == 3 ? max_alpha : max_rgb);
1873 }
1874
1875 args->compr = 1; /* COMPR flag */
1876 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1877 si_llvm_pack_two_int16(gallivm, val));
1878 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1879 si_llvm_pack_two_int16(gallivm, val+2));
1880 break;
1881 }
1882
1883 case V_028714_SPI_SHADER_SINT16_ABGR: {
1884 LLVMValueRef max_rgb = lp_build_const_int32(gallivm,
1885 is_int8 ? 127 : is_int10 ? 511 : 32767);
1886 LLVMValueRef min_rgb = lp_build_const_int32(gallivm,
1887 is_int8 ? -128 : is_int10 ? -512 : -32768);
1888 LLVMValueRef max_alpha =
1889 !is_int10 ? max_rgb : lp_build_const_int32(gallivm, 1);
1890 LLVMValueRef min_alpha =
1891 !is_int10 ? min_rgb : lp_build_const_int32(gallivm, -2);
1892
1893 /* Clamp. */
1894 for (chan = 0; chan < 4; chan++) {
1895 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1896 val[chan] = lp_build_emit_llvm_binary(bld_base,
1897 TGSI_OPCODE_IMIN,
1898 val[chan], chan == 3 ? max_alpha : max_rgb);
1899 val[chan] = lp_build_emit_llvm_binary(bld_base,
1900 TGSI_OPCODE_IMAX,
1901 val[chan], chan == 3 ? min_alpha : min_rgb);
1902 }
1903
1904 args->compr = 1; /* COMPR flag */
1905 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1906 si_llvm_pack_two_int32_as_int16(gallivm, val));
1907 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1908 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1909 break;
1910 }
1911
1912 case V_028714_SPI_SHADER_32_ABGR:
1913 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1914 break;
1915 }
1916 }
1917
1918 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1919 LLVMValueRef alpha)
1920 {
1921 struct si_shader_context *ctx = si_shader_context(bld_base);
1922 struct gallivm_state *gallivm = bld_base->base.gallivm;
1923
1924 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
1925 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
1926 SI_PARAM_ALPHA_REF);
1927
1928 LLVMValueRef alpha_pass =
1929 lp_build_cmp(&bld_base->base,
1930 ctx->shader->key.part.ps.epilog.alpha_func,
1931 alpha, alpha_ref);
1932 LLVMValueRef arg =
1933 lp_build_select(&bld_base->base,
1934 alpha_pass,
1935 lp_build_const_float(gallivm, 1.0f),
1936 lp_build_const_float(gallivm, -1.0f));
1937
1938 ac_build_kill(&ctx->ac, arg);
1939 } else {
1940 ac_build_kill(&ctx->ac, NULL);
1941 }
1942 }
1943
1944 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1945 LLVMValueRef alpha,
1946 unsigned samplemask_param)
1947 {
1948 struct si_shader_context *ctx = si_shader_context(bld_base);
1949 struct gallivm_state *gallivm = bld_base->base.gallivm;
1950 LLVMValueRef coverage;
1951
1952 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1953 coverage = LLVMGetParam(ctx->main_fn,
1954 samplemask_param);
1955 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1956
1957 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1958 ctx->i32,
1959 &coverage, 1, LP_FUNC_ATTR_READNONE);
1960
1961 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1962 ctx->f32, "");
1963
1964 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1965 lp_build_const_float(gallivm,
1966 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1967
1968 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1969 }
1970
1971 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
1972 struct ac_export_args *pos, LLVMValueRef *out_elts)
1973 {
1974 struct si_shader_context *ctx = si_shader_context(bld_base);
1975 struct lp_build_context *base = &bld_base->base;
1976 unsigned reg_index;
1977 unsigned chan;
1978 unsigned const_chan;
1979 LLVMValueRef base_elt;
1980 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1981 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
1982 SI_VS_CONST_CLIP_PLANES);
1983 LLVMValueRef const_resource = ac_build_indexed_load_const(&ctx->ac, ptr, constbuf_index);
1984
1985 for (reg_index = 0; reg_index < 2; reg_index ++) {
1986 struct ac_export_args *args = &pos[2 + reg_index];
1987
1988 args->out[0] =
1989 args->out[1] =
1990 args->out[2] =
1991 args->out[3] = lp_build_const_float(base->gallivm, 0.0f);
1992
1993 /* Compute dot products of position and user clip plane vectors */
1994 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1995 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1996 LLVMValueRef addr =
1997 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
1998 const_chan) * 4, 0);
1999 base_elt = buffer_load_const(ctx, const_resource,
2000 addr);
2001 args->out[chan] =
2002 lp_build_add(base, args->out[chan],
2003 lp_build_mul(base, base_elt,
2004 out_elts[const_chan]));
2005 }
2006 }
2007
2008 args->enabled_channels = 0xf;
2009 args->valid_mask = 0;
2010 args->done = 0;
2011 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2012 args->compr = 0;
2013 }
2014 }
2015
2016 static void si_dump_streamout(struct pipe_stream_output_info *so)
2017 {
2018 unsigned i;
2019
2020 if (so->num_outputs)
2021 fprintf(stderr, "STREAMOUT\n");
2022
2023 for (i = 0; i < so->num_outputs; i++) {
2024 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2025 so->output[i].start_component;
2026 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2027 i, so->output[i].output_buffer,
2028 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2029 so->output[i].register_index,
2030 mask & 1 ? "x" : "",
2031 mask & 2 ? "y" : "",
2032 mask & 4 ? "z" : "",
2033 mask & 8 ? "w" : "");
2034 }
2035 }
2036
2037 static void emit_streamout_output(struct si_shader_context *ctx,
2038 LLVMValueRef const *so_buffers,
2039 LLVMValueRef const *so_write_offsets,
2040 struct pipe_stream_output *stream_out,
2041 struct si_shader_output_values *shader_out)
2042 {
2043 struct gallivm_state *gallivm = &ctx->gallivm;
2044 LLVMBuilderRef builder = gallivm->builder;
2045 unsigned buf_idx = stream_out->output_buffer;
2046 unsigned start = stream_out->start_component;
2047 unsigned num_comps = stream_out->num_components;
2048 LLVMValueRef out[4];
2049
2050 assert(num_comps && num_comps <= 4);
2051 if (!num_comps || num_comps > 4)
2052 return;
2053
2054 /* Load the output as int. */
2055 for (int j = 0; j < num_comps; j++) {
2056 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2057
2058 out[j] = LLVMBuildBitCast(builder,
2059 shader_out->values[start + j],
2060 ctx->i32, "");
2061 }
2062
2063 /* Pack the output. */
2064 LLVMValueRef vdata = NULL;
2065
2066 switch (num_comps) {
2067 case 1: /* as i32 */
2068 vdata = out[0];
2069 break;
2070 case 2: /* as v2i32 */
2071 case 3: /* as v4i32 (aligned to 4) */
2072 case 4: /* as v4i32 */
2073 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2074 for (int j = 0; j < num_comps; j++) {
2075 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2076 LLVMConstInt(ctx->i32, j, 0), "");
2077 }
2078 break;
2079 }
2080
2081 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2082 vdata, num_comps,
2083 so_write_offsets[buf_idx],
2084 LLVMConstInt(ctx->i32, 0, 0),
2085 stream_out->dst_offset * 4, 1, 1, true, false);
2086 }
2087
2088 /**
2089 * Write streamout data to buffers for vertex stream @p stream (different
2090 * vertex streams can occur for GS copy shaders).
2091 */
2092 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2093 struct si_shader_output_values *outputs,
2094 unsigned noutput, unsigned stream)
2095 {
2096 struct si_shader_selector *sel = ctx->shader->selector;
2097 struct pipe_stream_output_info *so = &sel->so;
2098 struct gallivm_state *gallivm = &ctx->gallivm;
2099 LLVMBuilderRef builder = gallivm->builder;
2100 int i;
2101 struct lp_build_if_state if_ctx;
2102
2103 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2104 LLVMValueRef so_vtx_count =
2105 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2106
2107 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2108
2109 /* can_emit = tid < so_vtx_count; */
2110 LLVMValueRef can_emit =
2111 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2112
2113 /* Emit the streamout code conditionally. This actually avoids
2114 * out-of-bounds buffer access. The hw tells us via the SGPR
2115 * (so_vtx_count) which threads are allowed to emit streamout data. */
2116 lp_build_if(&if_ctx, gallivm, can_emit);
2117 {
2118 /* The buffer offset is computed as follows:
2119 * ByteOffset = streamout_offset[buffer_id]*4 +
2120 * (streamout_write_index + thread_id)*stride[buffer_id] +
2121 * attrib_offset
2122 */
2123
2124 LLVMValueRef so_write_index =
2125 LLVMGetParam(ctx->main_fn,
2126 ctx->param_streamout_write_index);
2127
2128 /* Compute (streamout_write_index + thread_id). */
2129 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2130
2131 /* Load the descriptor and compute the write offset for each
2132 * enabled buffer. */
2133 LLVMValueRef so_write_offset[4] = {};
2134 LLVMValueRef so_buffers[4];
2135 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2136 SI_PARAM_RW_BUFFERS);
2137
2138 for (i = 0; i < 4; i++) {
2139 if (!so->stride[i])
2140 continue;
2141
2142 LLVMValueRef offset = lp_build_const_int32(gallivm,
2143 SI_VS_STREAMOUT_BUF0 + i);
2144
2145 so_buffers[i] = ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
2146
2147 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2148 ctx->param_streamout_offset[i]);
2149 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2150
2151 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2152 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2153 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2154 }
2155
2156 /* Write streamout data. */
2157 for (i = 0; i < so->num_outputs; i++) {
2158 unsigned reg = so->output[i].register_index;
2159
2160 if (reg >= noutput)
2161 continue;
2162
2163 if (stream != so->output[i].stream)
2164 continue;
2165
2166 emit_streamout_output(ctx, so_buffers, so_write_offset,
2167 &so->output[i], &outputs[reg]);
2168 }
2169 }
2170 lp_build_endif(&if_ctx);
2171 }
2172
2173
2174 /* Generate export instructions for hardware VS shader stage */
2175 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2176 struct si_shader_output_values *outputs,
2177 unsigned noutput)
2178 {
2179 struct si_shader_context *ctx = si_shader_context(bld_base);
2180 struct si_shader *shader = ctx->shader;
2181 struct lp_build_context *base = &bld_base->base;
2182 struct ac_export_args args, pos_args[4] = {};
2183 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2184 unsigned semantic_name, semantic_index;
2185 unsigned target;
2186 unsigned param_count = 0;
2187 unsigned pos_idx;
2188 int i;
2189
2190 for (i = 0; i < noutput; i++) {
2191 semantic_name = outputs[i].semantic_name;
2192 semantic_index = outputs[i].semantic_index;
2193 bool export_param = true;
2194
2195 switch (semantic_name) {
2196 case TGSI_SEMANTIC_POSITION: /* ignore these */
2197 case TGSI_SEMANTIC_PSIZE:
2198 case TGSI_SEMANTIC_CLIPVERTEX:
2199 case TGSI_SEMANTIC_EDGEFLAG:
2200 break;
2201 case TGSI_SEMANTIC_GENERIC:
2202 case TGSI_SEMANTIC_CLIPDIST:
2203 if (shader->key.opt.hw_vs.kill_outputs &
2204 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2205 export_param = false;
2206 break;
2207 default:
2208 if (shader->key.opt.hw_vs.kill_outputs2 &
2209 (1u << si_shader_io_get_unique_index2(semantic_name, semantic_index)))
2210 export_param = false;
2211 break;
2212 }
2213
2214 if (outputs[i].vertex_stream[0] != 0 &&
2215 outputs[i].vertex_stream[1] != 0 &&
2216 outputs[i].vertex_stream[2] != 0 &&
2217 outputs[i].vertex_stream[3] != 0)
2218 export_param = false;
2219
2220 handle_semantic:
2221 /* Select the correct target */
2222 switch(semantic_name) {
2223 case TGSI_SEMANTIC_PSIZE:
2224 psize_value = outputs[i].values[0];
2225 continue;
2226 case TGSI_SEMANTIC_EDGEFLAG:
2227 edgeflag_value = outputs[i].values[0];
2228 continue;
2229 case TGSI_SEMANTIC_LAYER:
2230 layer_value = outputs[i].values[0];
2231 semantic_name = TGSI_SEMANTIC_GENERIC;
2232 goto handle_semantic;
2233 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2234 viewport_index_value = outputs[i].values[0];
2235 semantic_name = TGSI_SEMANTIC_GENERIC;
2236 goto handle_semantic;
2237 case TGSI_SEMANTIC_POSITION:
2238 target = V_008DFC_SQ_EXP_POS;
2239 break;
2240 case TGSI_SEMANTIC_CLIPDIST:
2241 if (shader->key.opt.hw_vs.clip_disable) {
2242 semantic_name = TGSI_SEMANTIC_GENERIC;
2243 goto handle_semantic;
2244 }
2245 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2246 break;
2247 case TGSI_SEMANTIC_CLIPVERTEX:
2248 if (shader->key.opt.hw_vs.clip_disable)
2249 continue;
2250 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2251 continue;
2252 case TGSI_SEMANTIC_COLOR:
2253 case TGSI_SEMANTIC_BCOLOR:
2254 case TGSI_SEMANTIC_PRIMID:
2255 case TGSI_SEMANTIC_FOG:
2256 case TGSI_SEMANTIC_TEXCOORD:
2257 case TGSI_SEMANTIC_GENERIC:
2258 if (!export_param)
2259 continue;
2260 target = V_008DFC_SQ_EXP_PARAM + param_count;
2261 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2262 shader->info.vs_output_param_offset[i] = param_count;
2263 param_count++;
2264 break;
2265 default:
2266 target = 0;
2267 fprintf(stderr,
2268 "Warning: SI unhandled vs output type:%d\n",
2269 semantic_name);
2270 }
2271
2272 si_llvm_init_export_args(bld_base, outputs[i].values, target, &args);
2273
2274 if (target >= V_008DFC_SQ_EXP_POS &&
2275 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2276 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2277 &args, sizeof(args));
2278 } else {
2279 ac_build_export(&ctx->ac, &args);
2280 }
2281
2282 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2283 semantic_name = TGSI_SEMANTIC_GENERIC;
2284 goto handle_semantic;
2285 }
2286 }
2287
2288 shader->info.nr_param_exports = param_count;
2289
2290 /* We need to add the position output manually if it's missing. */
2291 if (!pos_args[0].out[0]) {
2292 pos_args[0].enabled_channels = 0xf; /* writemask */
2293 pos_args[0].valid_mask = 0; /* EXEC mask */
2294 pos_args[0].done = 0; /* last export? */
2295 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2296 pos_args[0].compr = 0; /* COMPR flag */
2297 pos_args[0].out[0] = base->zero; /* X */
2298 pos_args[0].out[1] = base->zero; /* Y */
2299 pos_args[0].out[2] = base->zero; /* Z */
2300 pos_args[0].out[3] = base->one; /* W */
2301 }
2302
2303 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2304 if (shader->selector->info.writes_psize ||
2305 shader->selector->info.writes_edgeflag ||
2306 shader->selector->info.writes_viewport_index ||
2307 shader->selector->info.writes_layer) {
2308 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2309 (shader->selector->info.writes_edgeflag << 1) |
2310 (shader->selector->info.writes_layer << 2) |
2311 (shader->selector->info.writes_viewport_index << 3);
2312 pos_args[1].valid_mask = 0; /* EXEC mask */
2313 pos_args[1].done = 0; /* last export? */
2314 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2315 pos_args[1].compr = 0; /* COMPR flag */
2316 pos_args[1].out[0] = base->zero; /* X */
2317 pos_args[1].out[1] = base->zero; /* Y */
2318 pos_args[1].out[2] = base->zero; /* Z */
2319 pos_args[1].out[3] = base->zero; /* W */
2320
2321 if (shader->selector->info.writes_psize)
2322 pos_args[1].out[0] = psize_value;
2323
2324 if (shader->selector->info.writes_edgeflag) {
2325 /* The output is a float, but the hw expects an integer
2326 * with the first bit containing the edge flag. */
2327 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2328 edgeflag_value,
2329 ctx->i32, "");
2330 edgeflag_value = lp_build_min(&bld_base->int_bld,
2331 edgeflag_value,
2332 bld_base->int_bld.one);
2333
2334 /* The LLVM intrinsic expects a float. */
2335 pos_args[1].out[1] = LLVMBuildBitCast(base->gallivm->builder,
2336 edgeflag_value,
2337 ctx->f32, "");
2338 }
2339
2340 if (shader->selector->info.writes_layer)
2341 pos_args[1].out[2] = layer_value;
2342
2343 if (shader->selector->info.writes_viewport_index)
2344 pos_args[1].out[3] = viewport_index_value;
2345 }
2346
2347 for (i = 0; i < 4; i++)
2348 if (pos_args[i].out[0])
2349 shader->info.nr_pos_exports++;
2350
2351 pos_idx = 0;
2352 for (i = 0; i < 4; i++) {
2353 if (!pos_args[i].out[0])
2354 continue;
2355
2356 /* Specify the target we are exporting */
2357 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2358
2359 if (pos_idx == shader->info.nr_pos_exports)
2360 /* Specify that this is the last export */
2361 pos_args[i].done = 1;
2362
2363 ac_build_export(&ctx->ac, &pos_args[i]);
2364 }
2365 }
2366
2367 /**
2368 * Forward all outputs from the vertex shader to the TES. This is only used
2369 * for the fixed function TCS.
2370 */
2371 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2372 {
2373 struct si_shader_context *ctx = si_shader_context(bld_base);
2374 struct gallivm_state *gallivm = bld_base->base.gallivm;
2375 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2376 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2377 uint64_t inputs;
2378
2379 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2380
2381 rw_buffers = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2382 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
2383 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
2384
2385 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2386
2387 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
2388 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2389 lds_vertex_stride, "");
2390 lds_base = get_tcs_in_current_patch_offset(ctx);
2391 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2392
2393 inputs = ctx->shader->key.mono.tcs.inputs_to_copy;
2394 while (inputs) {
2395 unsigned i = u_bit_scan64(&inputs);
2396
2397 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2398 lp_build_const_int32(gallivm, 4 * i),
2399 "");
2400
2401 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2402 get_rel_patch_id(ctx),
2403 invocation_id,
2404 lp_build_const_int32(gallivm, i));
2405
2406 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2407 lds_ptr);
2408
2409 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
2410 buffer_offset, 0, 1, 0, true, false);
2411 }
2412 }
2413
2414 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2415 LLVMValueRef rel_patch_id,
2416 LLVMValueRef invocation_id,
2417 LLVMValueRef tcs_out_current_patch_data_offset)
2418 {
2419 struct si_shader_context *ctx = si_shader_context(bld_base);
2420 struct gallivm_state *gallivm = bld_base->base.gallivm;
2421 struct si_shader *shader = ctx->shader;
2422 unsigned tess_inner_index, tess_outer_index;
2423 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2424 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base, inner[4], outer[4];
2425 unsigned stride, outer_comps, inner_comps, i;
2426 struct lp_build_if_state if_ctx, inner_if_ctx;
2427
2428 si_llvm_emit_barrier(NULL, bld_base, NULL);
2429
2430 /* Do this only for invocation 0, because the tess levels are per-patch,
2431 * not per-vertex.
2432 *
2433 * This can't jump, because invocation 0 executes this. It should
2434 * at least mask out the loads and stores for other invocations.
2435 */
2436 lp_build_if(&if_ctx, gallivm,
2437 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2438 invocation_id, bld_base->uint_bld.zero, ""));
2439
2440 /* Determine the layout of one tess factor element in the buffer. */
2441 switch (shader->key.part.tcs.epilog.prim_mode) {
2442 case PIPE_PRIM_LINES:
2443 stride = 2; /* 2 dwords, 1 vec2 store */
2444 outer_comps = 2;
2445 inner_comps = 0;
2446 break;
2447 case PIPE_PRIM_TRIANGLES:
2448 stride = 4; /* 4 dwords, 1 vec4 store */
2449 outer_comps = 3;
2450 inner_comps = 1;
2451 break;
2452 case PIPE_PRIM_QUADS:
2453 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2454 outer_comps = 4;
2455 inner_comps = 2;
2456 break;
2457 default:
2458 assert(0);
2459 return;
2460 }
2461
2462 /* Load tess_inner and tess_outer from LDS.
2463 * Any invocation can write them, so we can't get them from a temporary.
2464 */
2465 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2466 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2467
2468 lds_base = tcs_out_current_patch_data_offset;
2469 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2470 lp_build_const_int32(gallivm,
2471 tess_inner_index * 4), "");
2472 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2473 lp_build_const_int32(gallivm,
2474 tess_outer_index * 4), "");
2475
2476 for (i = 0; i < 4; i++) {
2477 inner[i] = LLVMGetUndef(ctx->i32);
2478 outer[i] = LLVMGetUndef(ctx->i32);
2479 }
2480
2481 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2482 /* For isolines, the hardware expects tess factors in the
2483 * reverse order from what GLSL / TGSI specify.
2484 */
2485 outer[0] = out[1] = lds_load(bld_base, TGSI_TYPE_SIGNED, 0, lds_outer);
2486 outer[1] = out[0] = lds_load(bld_base, TGSI_TYPE_SIGNED, 1, lds_outer);
2487 } else {
2488 for (i = 0; i < outer_comps; i++) {
2489 outer[i] = out[i] =
2490 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2491 }
2492 for (i = 0; i < inner_comps; i++) {
2493 inner[i] = out[outer_comps+i] =
2494 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2495 }
2496 }
2497
2498 /* Convert the outputs to vectors for stores. */
2499 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2500 vec1 = NULL;
2501
2502 if (stride > 4)
2503 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2504
2505 /* Get the buffer. */
2506 rw_buffers = LLVMGetParam(ctx->main_fn,
2507 SI_PARAM_RW_BUFFERS);
2508 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
2509 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2510
2511 /* Get the offset. */
2512 tf_base = LLVMGetParam(ctx->main_fn,
2513 SI_PARAM_TESS_FACTOR_OFFSET);
2514 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2515 lp_build_const_int32(gallivm, 4 * stride), "");
2516
2517 lp_build_if(&inner_if_ctx, gallivm,
2518 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2519 rel_patch_id, bld_base->uint_bld.zero, ""));
2520
2521 /* Store the dynamic HS control word. */
2522 ac_build_buffer_store_dword(&ctx->ac, buffer,
2523 lp_build_const_int32(gallivm, 0x80000000),
2524 1, lp_build_const_int32(gallivm, 0), tf_base,
2525 0, 1, 0, true, false);
2526
2527 lp_build_endif(&inner_if_ctx);
2528
2529 /* Store the tessellation factors. */
2530 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2531 MIN2(stride, 4), byteoffset, tf_base,
2532 4, 1, 0, true, false);
2533 if (vec1)
2534 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2535 stride - 4, byteoffset, tf_base,
2536 20, 1, 0, true, false);
2537
2538 /* Store the tess factors into the offchip buffer if TES reads them. */
2539 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
2540 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
2541 LLVMValueRef tf_inner_offset;
2542 unsigned param_outer, param_inner;
2543
2544 buf = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
2545 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
2546 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2547
2548 param_outer = si_shader_io_get_unique_index(
2549 TGSI_SEMANTIC_TESSOUTER, 0);
2550 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2551 LLVMConstInt(ctx->i32, param_outer, 0));
2552
2553 outer_vec = lp_build_gather_values(gallivm, outer,
2554 util_next_power_of_two(outer_comps));
2555
2556 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
2557 outer_comps, tf_outer_offset,
2558 base, 0, 1, 0, true, false);
2559 if (inner_comps) {
2560 param_inner = si_shader_io_get_unique_index(
2561 TGSI_SEMANTIC_TESSINNER, 0);
2562 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2563 LLVMConstInt(ctx->i32, param_inner, 0));
2564
2565 inner_vec = inner_comps == 1 ? inner[0] :
2566 lp_build_gather_values(gallivm, inner, inner_comps);
2567 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
2568 inner_comps, tf_inner_offset,
2569 base, 0, 1, 0, true, false);
2570 }
2571 }
2572
2573 lp_build_endif(&if_ctx);
2574 }
2575
2576 /* This only writes the tessellation factor levels. */
2577 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2578 {
2579 struct si_shader_context *ctx = si_shader_context(bld_base);
2580 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2581 LLVMValueRef offchip_soffset, offchip_layout;
2582
2583 si_copy_tcs_inputs(bld_base);
2584
2585 rel_patch_id = get_rel_patch_id(ctx);
2586 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2587 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2588
2589 /* Return epilog parameters from this function. */
2590 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2591 LLVMValueRef ret = ctx->return_value;
2592 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2593 unsigned vgpr;
2594
2595 /* RW_BUFFERS pointer */
2596 rw_buffers = LLVMGetParam(ctx->main_fn,
2597 SI_PARAM_RW_BUFFERS);
2598 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2599 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2600 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2601 bld_base->uint_bld.zero, "");
2602 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2603 bld_base->uint_bld.one, "");
2604 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2605 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2606
2607 /* Tess offchip and factor buffer soffset are after user SGPRs. */
2608 offchip_layout = LLVMGetParam(ctx->main_fn,
2609 SI_PARAM_TCS_OFFCHIP_LAYOUT);
2610 offchip_soffset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2611 tf_soffset = LLVMGetParam(ctx->main_fn,
2612 SI_PARAM_TESS_FACTOR_OFFSET);
2613 ret = LLVMBuildInsertValue(builder, ret, offchip_layout,
2614 SI_SGPR_TCS_OFFCHIP_LAYOUT, "");
2615 ret = LLVMBuildInsertValue(builder, ret, offchip_soffset,
2616 SI_TCS_NUM_USER_SGPR, "");
2617 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2618 SI_TCS_NUM_USER_SGPR + 1, "");
2619
2620 /* VGPRs */
2621 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2622 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2623 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2624
2625 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2626 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2627 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2628 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2629 ctx->return_value = ret;
2630 }
2631
2632 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2633 {
2634 struct si_shader_context *ctx = si_shader_context(bld_base);
2635 struct si_shader *shader = ctx->shader;
2636 struct tgsi_shader_info *info = &shader->selector->info;
2637 struct gallivm_state *gallivm = bld_base->base.gallivm;
2638 unsigned i, chan;
2639 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
2640 ctx->param_rel_auto_id);
2641 LLVMValueRef vertex_dw_stride =
2642 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2643 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2644 vertex_dw_stride, "");
2645
2646 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2647 * its inputs from it. */
2648 for (i = 0; i < info->num_outputs; i++) {
2649 LLVMValueRef *out_ptr = ctx->outputs[i];
2650 unsigned name = info->output_semantic_name[i];
2651 unsigned index = info->output_semantic_index[i];
2652 int param = si_shader_io_get_unique_index(name, index);
2653 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2654 lp_build_const_int32(gallivm, param * 4), "");
2655
2656 for (chan = 0; chan < 4; chan++) {
2657 lds_store(bld_base, chan, dw_addr,
2658 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2659 }
2660 }
2661 }
2662
2663 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2664 {
2665 struct si_shader_context *ctx = si_shader_context(bld_base);
2666 struct gallivm_state *gallivm = bld_base->base.gallivm;
2667 struct si_shader *es = ctx->shader;
2668 struct tgsi_shader_info *info = &es->selector->info;
2669 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
2670 ctx->param_es2gs_offset);
2671 unsigned chan;
2672 int i;
2673
2674 for (i = 0; i < info->num_outputs; i++) {
2675 LLVMValueRef *out_ptr = ctx->outputs[i];
2676 int param_index;
2677
2678 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2679 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2680 continue;
2681
2682 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2683 info->output_semantic_index[i]);
2684
2685 for (chan = 0; chan < 4; chan++) {
2686 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2687 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2688
2689 ac_build_buffer_store_dword(&ctx->ac,
2690 ctx->esgs_ring,
2691 out_val, 1, NULL, soffset,
2692 (4 * param_index + chan) * 4,
2693 1, 1, true, true);
2694 }
2695 }
2696 }
2697
2698 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2699 {
2700 struct si_shader_context *ctx = si_shader_context(bld_base);
2701
2702 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
2703 LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID));
2704 }
2705
2706 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2707 {
2708 struct si_shader_context *ctx = si_shader_context(bld_base);
2709 struct gallivm_state *gallivm = bld_base->base.gallivm;
2710 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2711 struct si_shader_output_values *outputs = NULL;
2712 int i,j;
2713
2714 assert(!ctx->shader->is_gs_copy_shader);
2715
2716 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2717
2718 /* Vertex color clamping.
2719 *
2720 * This uses a state constant loaded in a user data SGPR and
2721 * an IF statement is added that clamps all colors if the constant
2722 * is true.
2723 */
2724 if (ctx->type == PIPE_SHADER_VERTEX) {
2725 struct lp_build_if_state if_ctx;
2726 LLVMValueRef cond = NULL;
2727 LLVMValueRef addr, val;
2728
2729 for (i = 0; i < info->num_outputs; i++) {
2730 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2731 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2732 continue;
2733
2734 /* We've found a color. */
2735 if (!cond) {
2736 /* The state is in the first bit of the user SGPR. */
2737 cond = LLVMGetParam(ctx->main_fn,
2738 SI_PARAM_VS_STATE_BITS);
2739 cond = LLVMBuildTrunc(gallivm->builder, cond,
2740 ctx->i1, "");
2741 lp_build_if(&if_ctx, gallivm, cond);
2742 }
2743
2744 for (j = 0; j < 4; j++) {
2745 addr = ctx->outputs[i][j];
2746 val = LLVMBuildLoad(gallivm->builder, addr, "");
2747 val = ac_build_clamp(&ctx->ac, val);
2748 LLVMBuildStore(gallivm->builder, val, addr);
2749 }
2750 }
2751
2752 if (cond)
2753 lp_build_endif(&if_ctx);
2754 }
2755
2756 for (i = 0; i < info->num_outputs; i++) {
2757 outputs[i].semantic_name = info->output_semantic_name[i];
2758 outputs[i].semantic_index = info->output_semantic_index[i];
2759
2760 for (j = 0; j < 4; j++) {
2761 outputs[i].values[j] =
2762 LLVMBuildLoad(gallivm->builder,
2763 ctx->outputs[i][j],
2764 "");
2765 outputs[i].vertex_stream[j] =
2766 (info->output_streams[i] >> (2 * j)) & 3;
2767 }
2768
2769 }
2770
2771 /* Return the primitive ID from the LLVM function. */
2772 ctx->return_value =
2773 LLVMBuildInsertValue(gallivm->builder,
2774 ctx->return_value,
2775 bitcast(bld_base, TGSI_TYPE_FLOAT,
2776 get_primitive_id(bld_base, 0)),
2777 VS_EPILOG_PRIMID_LOC, "");
2778
2779 if (ctx->shader->selector->so.num_outputs)
2780 si_llvm_emit_streamout(ctx, outputs, i, 0);
2781 si_llvm_export_vs(bld_base, outputs, i);
2782 FREE(outputs);
2783 }
2784
2785 struct si_ps_exports {
2786 unsigned num;
2787 struct ac_export_args args[10];
2788 };
2789
2790 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
2791 bool writes_samplemask)
2792 {
2793 if (writes_z) {
2794 /* Z needs 32 bits. */
2795 if (writes_samplemask)
2796 return V_028710_SPI_SHADER_32_ABGR;
2797 else if (writes_stencil)
2798 return V_028710_SPI_SHADER_32_GR;
2799 else
2800 return V_028710_SPI_SHADER_32_R;
2801 } else if (writes_stencil || writes_samplemask) {
2802 /* Both stencil and sample mask need only 16 bits. */
2803 return V_028710_SPI_SHADER_UINT16_ABGR;
2804 } else {
2805 return V_028710_SPI_SHADER_ZERO;
2806 }
2807 }
2808
2809 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2810 LLVMValueRef depth, LLVMValueRef stencil,
2811 LLVMValueRef samplemask, struct si_ps_exports *exp)
2812 {
2813 struct si_shader_context *ctx = si_shader_context(bld_base);
2814 struct lp_build_context *base = &bld_base->base;
2815 struct ac_export_args args;
2816 unsigned mask = 0;
2817 unsigned format = si_get_spi_shader_z_format(depth != NULL,
2818 stencil != NULL,
2819 samplemask != NULL);
2820
2821 assert(depth || stencil || samplemask);
2822
2823 args.valid_mask = 1; /* whether the EXEC mask is valid */
2824 args.done = 1; /* DONE bit */
2825
2826 /* Specify the target we are exporting */
2827 args.target = V_008DFC_SQ_EXP_MRTZ;
2828
2829 args.compr = 0; /* COMP flag */
2830 args.out[0] = base->undef; /* R, depth */
2831 args.out[1] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2832 args.out[2] = base->undef; /* B, sample mask */
2833 args.out[3] = base->undef; /* A, alpha to mask */
2834
2835 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
2836 assert(!depth);
2837 args.compr = 1; /* COMPR flag */
2838
2839 if (stencil) {
2840 /* Stencil should be in X[23:16]. */
2841 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
2842 stencil = LLVMBuildShl(base->gallivm->builder, stencil,
2843 LLVMConstInt(ctx->i32, 16, 0), "");
2844 args.out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
2845 mask |= 0x3;
2846 }
2847 if (samplemask) {
2848 /* SampleMask should be in Y[15:0]. */
2849 args.out[1] = samplemask;
2850 mask |= 0xc;
2851 }
2852 } else {
2853 if (depth) {
2854 args.out[0] = depth;
2855 mask |= 0x1;
2856 }
2857 if (stencil) {
2858 args.out[1] = stencil;
2859 mask |= 0x2;
2860 }
2861 if (samplemask) {
2862 args.out[2] = samplemask;
2863 mask |= 0x4;
2864 }
2865 }
2866
2867 /* SI (except OLAND and HAINAN) has a bug that it only looks
2868 * at the X writemask component. */
2869 if (ctx->screen->b.chip_class == SI &&
2870 ctx->screen->b.family != CHIP_OLAND &&
2871 ctx->screen->b.family != CHIP_HAINAN)
2872 mask |= 0x1;
2873
2874 /* Specify which components to enable */
2875 args.enabled_channels = mask;
2876
2877 memcpy(&exp->args[exp->num++], &args, sizeof(args));
2878 }
2879
2880 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2881 LLVMValueRef *color, unsigned index,
2882 unsigned samplemask_param,
2883 bool is_last, struct si_ps_exports *exp)
2884 {
2885 struct si_shader_context *ctx = si_shader_context(bld_base);
2886 struct lp_build_context *base = &bld_base->base;
2887 int i;
2888
2889 /* Clamp color */
2890 if (ctx->shader->key.part.ps.epilog.clamp_color)
2891 for (i = 0; i < 4; i++)
2892 color[i] = ac_build_clamp(&ctx->ac, color[i]);
2893
2894 /* Alpha to one */
2895 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
2896 color[3] = base->one;
2897
2898 /* Alpha test */
2899 if (index == 0 &&
2900 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2901 si_alpha_test(bld_base, color[3]);
2902
2903 /* Line & polygon smoothing */
2904 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
2905 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
2906 samplemask_param);
2907
2908 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2909 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
2910 struct ac_export_args args[8];
2911 int c, last = -1;
2912
2913 /* Get the export arguments, also find out what the last one is. */
2914 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2915 si_llvm_init_export_args(bld_base, color,
2916 V_008DFC_SQ_EXP_MRT + c, &args[c]);
2917 if (args[c].enabled_channels)
2918 last = c;
2919 }
2920
2921 /* Emit all exports. */
2922 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2923 if (is_last && last == c) {
2924 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
2925 args[c].done = 1; /* DONE bit */
2926 } else if (!args[c].enabled_channels)
2927 continue; /* unnecessary NULL export */
2928
2929 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
2930 }
2931 } else {
2932 struct ac_export_args args;
2933
2934 /* Export */
2935 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2936 &args);
2937 if (is_last) {
2938 args.valid_mask = 1; /* whether the EXEC mask is valid */
2939 args.done = 1; /* DONE bit */
2940 } else if (!args.enabled_channels)
2941 return; /* unnecessary NULL export */
2942
2943 memcpy(&exp->args[exp->num++], &args, sizeof(args));
2944 }
2945 }
2946
2947 static void si_emit_ps_exports(struct si_shader_context *ctx,
2948 struct si_ps_exports *exp)
2949 {
2950 for (unsigned i = 0; i < exp->num; i++)
2951 ac_build_export(&ctx->ac, &exp->args[i]);
2952 }
2953
2954 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2955 {
2956 struct si_shader_context *ctx = si_shader_context(bld_base);
2957 struct lp_build_context *base = &bld_base->base;
2958 struct ac_export_args args;
2959
2960 args.enabled_channels = 0x0; /* enabled channels */
2961 args.valid_mask = 1; /* whether the EXEC mask is valid */
2962 args.done = 1; /* DONE bit */
2963 args.target = V_008DFC_SQ_EXP_NULL;
2964 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
2965 args.out[0] = base->undef; /* R */
2966 args.out[1] = base->undef; /* G */
2967 args.out[2] = base->undef; /* B */
2968 args.out[3] = base->undef; /* A */
2969
2970 ac_build_export(&ctx->ac, &args);
2971 }
2972
2973 /**
2974 * Return PS outputs in this order:
2975 *
2976 * v[0:3] = color0.xyzw
2977 * v[4:7] = color1.xyzw
2978 * ...
2979 * vN+0 = Depth
2980 * vN+1 = Stencil
2981 * vN+2 = SampleMask
2982 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
2983 *
2984 * The alpha-ref SGPR is returned via its original location.
2985 */
2986 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
2987 {
2988 struct si_shader_context *ctx = si_shader_context(bld_base);
2989 struct si_shader *shader = ctx->shader;
2990 struct lp_build_context *base = &bld_base->base;
2991 struct tgsi_shader_info *info = &shader->selector->info;
2992 LLVMBuilderRef builder = base->gallivm->builder;
2993 unsigned i, j, first_vgpr, vgpr;
2994
2995 LLVMValueRef color[8][4] = {};
2996 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2997 LLVMValueRef ret;
2998
2999 /* Read the output values. */
3000 for (i = 0; i < info->num_outputs; i++) {
3001 unsigned semantic_name = info->output_semantic_name[i];
3002 unsigned semantic_index = info->output_semantic_index[i];
3003
3004 switch (semantic_name) {
3005 case TGSI_SEMANTIC_COLOR:
3006 assert(semantic_index < 8);
3007 for (j = 0; j < 4; j++) {
3008 LLVMValueRef ptr = ctx->outputs[i][j];
3009 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3010 color[semantic_index][j] = result;
3011 }
3012 break;
3013 case TGSI_SEMANTIC_POSITION:
3014 depth = LLVMBuildLoad(builder,
3015 ctx->outputs[i][2], "");
3016 break;
3017 case TGSI_SEMANTIC_STENCIL:
3018 stencil = LLVMBuildLoad(builder,
3019 ctx->outputs[i][1], "");
3020 break;
3021 case TGSI_SEMANTIC_SAMPLEMASK:
3022 samplemask = LLVMBuildLoad(builder,
3023 ctx->outputs[i][0], "");
3024 break;
3025 default:
3026 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3027 semantic_name);
3028 }
3029 }
3030
3031 /* Fill the return structure. */
3032 ret = ctx->return_value;
3033
3034 /* Set SGPRs. */
3035 ret = LLVMBuildInsertValue(builder, ret,
3036 bitcast(bld_base, TGSI_TYPE_SIGNED,
3037 LLVMGetParam(ctx->main_fn,
3038 SI_PARAM_ALPHA_REF)),
3039 SI_SGPR_ALPHA_REF, "");
3040
3041 /* Set VGPRs */
3042 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3043 for (i = 0; i < ARRAY_SIZE(color); i++) {
3044 if (!color[i][0])
3045 continue;
3046
3047 for (j = 0; j < 4; j++)
3048 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3049 }
3050 if (depth)
3051 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3052 if (stencil)
3053 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3054 if (samplemask)
3055 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3056
3057 /* Add the input sample mask for smoothing at the end. */
3058 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3059 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3060 ret = LLVMBuildInsertValue(builder, ret,
3061 LLVMGetParam(ctx->main_fn,
3062 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3063
3064 ctx->return_value = ret;
3065 }
3066
3067 /**
3068 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3069 * buffer in number of elements and return it as an i32.
3070 */
3071 static LLVMValueRef get_buffer_size(
3072 struct lp_build_tgsi_context *bld_base,
3073 LLVMValueRef descriptor)
3074 {
3075 struct si_shader_context *ctx = si_shader_context(bld_base);
3076 struct gallivm_state *gallivm = bld_base->base.gallivm;
3077 LLVMBuilderRef builder = gallivm->builder;
3078 LLVMValueRef size =
3079 LLVMBuildExtractElement(builder, descriptor,
3080 lp_build_const_int32(gallivm, 2), "");
3081
3082 if (ctx->screen->b.chip_class == VI) {
3083 /* On VI, the descriptor contains the size in bytes,
3084 * but TXQ must return the size in elements.
3085 * The stride is always non-zero for resources using TXQ.
3086 */
3087 LLVMValueRef stride =
3088 LLVMBuildExtractElement(builder, descriptor,
3089 lp_build_const_int32(gallivm, 1), "");
3090 stride = LLVMBuildLShr(builder, stride,
3091 lp_build_const_int32(gallivm, 16), "");
3092 stride = LLVMBuildAnd(builder, stride,
3093 lp_build_const_int32(gallivm, 0x3FFF), "");
3094
3095 size = LLVMBuildUDiv(builder, size, stride, "");
3096 }
3097
3098 return size;
3099 }
3100
3101 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3102 struct lp_build_tgsi_context *bld_base,
3103 struct lp_build_emit_data *emit_data);
3104
3105 /* Prevent optimizations (at least of memory accesses) across the current
3106 * point in the program by emitting empty inline assembly that is marked as
3107 * having side effects.
3108 */
3109 #if 0 /* unused currently */
3110 static void emit_optimization_barrier(struct si_shader_context *ctx)
3111 {
3112 LLVMBuilderRef builder = ctx->gallivm.builder;
3113 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3114 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
3115 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3116 }
3117 #endif
3118
3119 /* Combine these with & instead of |. */
3120 #define NOOP_WAITCNT 0xf7f
3121 #define LGKM_CNT 0x07f
3122 #define VM_CNT 0xf70
3123
3124 static void emit_waitcnt(struct si_shader_context *ctx, unsigned simm16)
3125 {
3126 struct gallivm_state *gallivm = &ctx->gallivm;
3127 LLVMBuilderRef builder = gallivm->builder;
3128 LLVMValueRef args[1] = {
3129 lp_build_const_int32(gallivm, simm16)
3130 };
3131 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3132 ctx->voidt, args, 1, 0);
3133 }
3134
3135 static void membar_emit(
3136 const struct lp_build_tgsi_action *action,
3137 struct lp_build_tgsi_context *bld_base,
3138 struct lp_build_emit_data *emit_data)
3139 {
3140 struct si_shader_context *ctx = si_shader_context(bld_base);
3141 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3142 unsigned flags = LLVMConstIntGetZExtValue(src0);
3143 unsigned waitcnt = NOOP_WAITCNT;
3144
3145 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3146 waitcnt &= VM_CNT & LGKM_CNT;
3147
3148 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3149 TGSI_MEMBAR_SHADER_BUFFER |
3150 TGSI_MEMBAR_SHADER_IMAGE))
3151 waitcnt &= VM_CNT;
3152
3153 if (flags & TGSI_MEMBAR_SHARED)
3154 waitcnt &= LGKM_CNT;
3155
3156 if (waitcnt != NOOP_WAITCNT)
3157 emit_waitcnt(ctx, waitcnt);
3158 }
3159
3160 static void clock_emit(
3161 const struct lp_build_tgsi_action *action,
3162 struct lp_build_tgsi_context *bld_base,
3163 struct lp_build_emit_data *emit_data)
3164 {
3165 struct si_shader_context *ctx = si_shader_context(bld_base);
3166 struct gallivm_state *gallivm = &ctx->gallivm;
3167 LLVMValueRef tmp;
3168
3169 tmp = lp_build_intrinsic(gallivm->builder, "llvm.readcyclecounter",
3170 ctx->i64, NULL, 0, 0);
3171 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->v2i32, "");
3172
3173 emit_data->output[0] =
3174 LLVMBuildExtractElement(gallivm->builder, tmp, ctx->i32_0, "");
3175 emit_data->output[1] =
3176 LLVMBuildExtractElement(gallivm->builder, tmp, ctx->i32_1, "");
3177 }
3178
3179 static LLVMValueRef
3180 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3181 const struct tgsi_full_src_register *reg)
3182 {
3183 LLVMValueRef index;
3184 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3185 SI_PARAM_SHADER_BUFFERS);
3186
3187 if (!reg->Register.Indirect)
3188 index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
3189 else
3190 index = get_bounded_indirect_index(ctx, &reg->Indirect,
3191 reg->Register.Index,
3192 SI_NUM_SHADER_BUFFERS);
3193
3194 return ac_build_indexed_load_const(&ctx->ac, rsrc_ptr, index);
3195 }
3196
3197 static bool tgsi_is_array_sampler(unsigned target)
3198 {
3199 return target == TGSI_TEXTURE_1D_ARRAY ||
3200 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3201 target == TGSI_TEXTURE_2D_ARRAY ||
3202 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3203 target == TGSI_TEXTURE_CUBE_ARRAY ||
3204 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3205 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3206 }
3207
3208 static bool tgsi_is_array_image(unsigned target)
3209 {
3210 return target == TGSI_TEXTURE_3D ||
3211 target == TGSI_TEXTURE_CUBE ||
3212 target == TGSI_TEXTURE_1D_ARRAY ||
3213 target == TGSI_TEXTURE_2D_ARRAY ||
3214 target == TGSI_TEXTURE_CUBE_ARRAY ||
3215 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3216 }
3217
3218 /**
3219 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3220 *
3221 * At least on Tonga, executing image stores on images with DCC enabled and
3222 * non-trivial can eventually lead to lockups. This can occur when an
3223 * application binds an image as read-only but then uses a shader that writes
3224 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3225 * program termination) in this case, but it doesn't cost much to be a bit
3226 * nicer: disabling DCC in the shader still leads to undefined results but
3227 * avoids the lockup.
3228 */
3229 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3230 LLVMValueRef rsrc)
3231 {
3232 if (ctx->screen->b.chip_class <= CIK) {
3233 return rsrc;
3234 } else {
3235 LLVMBuilderRef builder = ctx->gallivm.builder;
3236 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3237 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3238 LLVMValueRef tmp;
3239
3240 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3241 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3242 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3243 }
3244 }
3245
3246 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3247 {
3248 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3249 CONST_ADDR_SPACE);
3250 }
3251
3252 /**
3253 * Load the resource descriptor for \p image.
3254 */
3255 static void
3256 image_fetch_rsrc(
3257 struct lp_build_tgsi_context *bld_base,
3258 const struct tgsi_full_src_register *image,
3259 bool is_store, unsigned target,
3260 LLVMValueRef *rsrc)
3261 {
3262 struct si_shader_context *ctx = si_shader_context(bld_base);
3263 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3264 SI_PARAM_IMAGES);
3265 LLVMValueRef index, tmp;
3266 bool dcc_off = target != TGSI_TEXTURE_BUFFER && is_store;
3267
3268 assert(image->Register.File == TGSI_FILE_IMAGE);
3269
3270 if (!image->Register.Indirect) {
3271 const struct tgsi_shader_info *info = bld_base->info;
3272 unsigned images_writemask = info->images_store |
3273 info->images_atomic;
3274
3275 index = LLVMConstInt(ctx->i32, image->Register.Index, 0);
3276
3277 if (images_writemask & (1 << image->Register.Index) &&
3278 target != TGSI_TEXTURE_BUFFER)
3279 dcc_off = true;
3280 } else {
3281 /* From the GL_ARB_shader_image_load_store extension spec:
3282 *
3283 * If a shader performs an image load, store, or atomic
3284 * operation using an image variable declared as an array,
3285 * and if the index used to select an individual element is
3286 * negative or greater than or equal to the size of the
3287 * array, the results of the operation are undefined but may
3288 * not lead to termination.
3289 */
3290 index = get_bounded_indirect_index(ctx, &image->Indirect,
3291 image->Register.Index,
3292 SI_NUM_IMAGES);
3293 }
3294
3295 if (target == TGSI_TEXTURE_BUFFER) {
3296 LLVMBuilderRef builder = ctx->gallivm.builder;
3297
3298 rsrc_ptr = LLVMBuildPointerCast(builder, rsrc_ptr,
3299 const_array(ctx->v4i32, 0), "");
3300 index = LLVMBuildMul(builder, index,
3301 LLVMConstInt(ctx->i32, 2, 0), "");
3302 index = LLVMBuildAdd(builder, index,
3303 LLVMConstInt(ctx->i32, 1, 0), "");
3304 *rsrc = ac_build_indexed_load_const(&ctx->ac, rsrc_ptr, index);
3305 return;
3306 }
3307
3308 tmp = ac_build_indexed_load_const(&ctx->ac, rsrc_ptr, index);
3309 if (dcc_off)
3310 tmp = force_dcc_off(ctx, tmp);
3311 *rsrc = tmp;
3312 }
3313
3314 static LLVMValueRef image_fetch_coords(
3315 struct lp_build_tgsi_context *bld_base,
3316 const struct tgsi_full_instruction *inst,
3317 unsigned src)
3318 {
3319 struct si_shader_context *ctx = si_shader_context(bld_base);
3320 struct gallivm_state *gallivm = bld_base->base.gallivm;
3321 LLVMBuilderRef builder = gallivm->builder;
3322 unsigned target = inst->Memory.Texture;
3323 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3324 LLVMValueRef coords[4];
3325 LLVMValueRef tmp;
3326 int chan;
3327
3328 for (chan = 0; chan < num_coords; ++chan) {
3329 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3330 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3331 coords[chan] = tmp;
3332 }
3333
3334 /* 1D textures are allocated and used as 2D on GFX9. */
3335 if (ctx->screen->b.chip_class >= GFX9) {
3336 if (target == TGSI_TEXTURE_1D) {
3337 coords[1] = bld_base->uint_bld.zero;
3338 num_coords++;
3339 } else if (target == TGSI_TEXTURE_1D_ARRAY) {
3340 coords[2] = coords[1];
3341 coords[1] = bld_base->uint_bld.zero;
3342 }
3343 }
3344
3345 if (num_coords == 1)
3346 return coords[0];
3347
3348 if (num_coords == 3) {
3349 /* LLVM has difficulties lowering 3-element vectors. */
3350 coords[3] = bld_base->uint_bld.undef;
3351 num_coords = 4;
3352 }
3353
3354 return lp_build_gather_values(gallivm, coords, num_coords);
3355 }
3356
3357 /**
3358 * Append the extra mode bits that are used by image load and store.
3359 */
3360 static void image_append_args(
3361 struct si_shader_context *ctx,
3362 struct lp_build_emit_data * emit_data,
3363 unsigned target,
3364 bool atomic,
3365 bool force_glc)
3366 {
3367 const struct tgsi_full_instruction *inst = emit_data->inst;
3368 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3369 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3370 LLVMValueRef r128 = i1false;
3371 LLVMValueRef da = tgsi_is_array_image(target) ? i1true : i1false;
3372 LLVMValueRef glc =
3373 force_glc ||
3374 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3375 i1true : i1false;
3376 LLVMValueRef slc = i1false;
3377 LLVMValueRef lwe = i1false;
3378
3379 if (atomic || (HAVE_LLVM <= 0x0309)) {
3380 emit_data->args[emit_data->arg_count++] = r128;
3381 emit_data->args[emit_data->arg_count++] = da;
3382 if (!atomic) {
3383 emit_data->args[emit_data->arg_count++] = glc;
3384 }
3385 emit_data->args[emit_data->arg_count++] = slc;
3386 return;
3387 }
3388
3389 /* HAVE_LLVM >= 0x0400 */
3390 emit_data->args[emit_data->arg_count++] = glc;
3391 emit_data->args[emit_data->arg_count++] = slc;
3392 emit_data->args[emit_data->arg_count++] = lwe;
3393 emit_data->args[emit_data->arg_count++] = da;
3394 }
3395
3396 /**
3397 * Append the resource and indexing arguments for buffer intrinsics.
3398 *
3399 * \param rsrc the v4i32 buffer resource
3400 * \param index index into the buffer (stride-based)
3401 * \param offset byte offset into the buffer
3402 */
3403 static void buffer_append_args(
3404 struct si_shader_context *ctx,
3405 struct lp_build_emit_data *emit_data,
3406 LLVMValueRef rsrc,
3407 LLVMValueRef index,
3408 LLVMValueRef offset,
3409 bool atomic,
3410 bool force_glc)
3411 {
3412 const struct tgsi_full_instruction *inst = emit_data->inst;
3413 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3414 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3415
3416 emit_data->args[emit_data->arg_count++] = rsrc;
3417 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3418 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3419 if (!atomic) {
3420 emit_data->args[emit_data->arg_count++] =
3421 force_glc ||
3422 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3423 i1true : i1false; /* glc */
3424 }
3425 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3426 }
3427
3428 static void load_fetch_args(
3429 struct lp_build_tgsi_context * bld_base,
3430 struct lp_build_emit_data * emit_data)
3431 {
3432 struct si_shader_context *ctx = si_shader_context(bld_base);
3433 struct gallivm_state *gallivm = bld_base->base.gallivm;
3434 const struct tgsi_full_instruction * inst = emit_data->inst;
3435 unsigned target = inst->Memory.Texture;
3436 LLVMValueRef rsrc;
3437
3438 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3439
3440 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3441 LLVMBuilderRef builder = gallivm->builder;
3442 LLVMValueRef offset;
3443 LLVMValueRef tmp;
3444
3445 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3446
3447 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3448 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3449
3450 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3451 offset, false, false);
3452 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3453 LLVMValueRef coords;
3454
3455 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
3456 coords = image_fetch_coords(bld_base, inst, 1);
3457
3458 if (target == TGSI_TEXTURE_BUFFER) {
3459 buffer_append_args(ctx, emit_data, rsrc, coords,
3460 bld_base->uint_bld.zero, false, false);
3461 } else {
3462 emit_data->args[0] = coords;
3463 emit_data->args[1] = rsrc;
3464 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3465 emit_data->arg_count = 3;
3466
3467 image_append_args(ctx, emit_data, target, false, false);
3468 }
3469 }
3470 }
3471
3472 static unsigned get_load_intr_attribs(bool readonly_memory)
3473 {
3474 /* READNONE means writes can't affect it, while READONLY means that
3475 * writes can affect it. */
3476 return readonly_memory && HAVE_LLVM >= 0x0400 ?
3477 LP_FUNC_ATTR_READNONE :
3478 LP_FUNC_ATTR_READONLY;
3479 }
3480
3481 static unsigned get_store_intr_attribs(bool writeonly_memory)
3482 {
3483 return writeonly_memory && HAVE_LLVM >= 0x0400 ?
3484 LP_FUNC_ATTR_INACCESSIBLE_MEM_ONLY :
3485 LP_FUNC_ATTR_WRITEONLY;
3486 }
3487
3488 static void load_emit_buffer(struct si_shader_context *ctx,
3489 struct lp_build_emit_data *emit_data,
3490 bool readonly_memory)
3491 {
3492 const struct tgsi_full_instruction *inst = emit_data->inst;
3493 struct gallivm_state *gallivm = &ctx->gallivm;
3494 LLVMBuilderRef builder = gallivm->builder;
3495 uint writemask = inst->Dst[0].Register.WriteMask;
3496 uint count = util_last_bit(writemask);
3497 const char *intrinsic_name;
3498 LLVMTypeRef dst_type;
3499
3500 switch (count) {
3501 case 1:
3502 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3503 dst_type = ctx->f32;
3504 break;
3505 case 2:
3506 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3507 dst_type = LLVMVectorType(ctx->f32, 2);
3508 break;
3509 default: // 3 & 4
3510 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3511 dst_type = ctx->v4f32;
3512 count = 4;
3513 }
3514
3515 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3516 builder, intrinsic_name, dst_type,
3517 emit_data->args, emit_data->arg_count,
3518 get_load_intr_attribs(readonly_memory));
3519 }
3520
3521 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3522 const struct tgsi_full_instruction *inst,
3523 LLVMTypeRef type, int arg)
3524 {
3525 struct gallivm_state *gallivm = &ctx->gallivm;
3526 LLVMBuilderRef builder = gallivm->builder;
3527 LLVMValueRef offset, ptr;
3528 int addr_space;
3529
3530 offset = lp_build_emit_fetch(&ctx->bld_base, inst, arg, 0);
3531 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3532
3533 ptr = ctx->shared_memory;
3534 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3535 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3536 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3537
3538 return ptr;
3539 }
3540
3541 static void load_emit_memory(
3542 struct si_shader_context *ctx,
3543 struct lp_build_emit_data *emit_data)
3544 {
3545 const struct tgsi_full_instruction *inst = emit_data->inst;
3546 struct lp_build_context *base = &ctx->bld_base.base;
3547 struct gallivm_state *gallivm = &ctx->gallivm;
3548 LLVMBuilderRef builder = gallivm->builder;
3549 unsigned writemask = inst->Dst[0].Register.WriteMask;
3550 LLVMValueRef channels[4], ptr, derived_ptr, index;
3551 int chan;
3552
3553 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3554
3555 for (chan = 0; chan < 4; ++chan) {
3556 if (!(writemask & (1 << chan))) {
3557 channels[chan] = LLVMGetUndef(base->elem_type);
3558 continue;
3559 }
3560
3561 index = lp_build_const_int32(gallivm, chan);
3562 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3563 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3564 }
3565 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3566 }
3567
3568 /**
3569 * Return true if the memory accessed by a LOAD or STORE instruction is
3570 * read-only or write-only, respectively.
3571 *
3572 * \param shader_buffers_reverse_access_mask
3573 * For LOAD, set this to (store | atomic) slot usage in the shader.
3574 * For STORE, set this to (load | atomic) slot usage in the shader.
3575 * \param images_reverse_access_mask Same as above, but for images.
3576 */
3577 static bool is_oneway_access_only(const struct tgsi_full_instruction *inst,
3578 const struct tgsi_shader_info *info,
3579 unsigned shader_buffers_reverse_access_mask,
3580 unsigned images_reverse_access_mask)
3581 {
3582 /* RESTRICT means NOALIAS.
3583 * If there are no writes, we can assume the accessed memory is read-only.
3584 * If there are no reads, we can assume the accessed memory is write-only.
3585 */
3586 if (inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT) {
3587 unsigned reverse_access_mask;
3588
3589 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3590 reverse_access_mask = shader_buffers_reverse_access_mask;
3591 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3592 reverse_access_mask = info->images_buffers &
3593 images_reverse_access_mask;
3594 } else {
3595 reverse_access_mask = ~info->images_buffers &
3596 images_reverse_access_mask;
3597 }
3598
3599 if (inst->Src[0].Register.Indirect) {
3600 if (!reverse_access_mask)
3601 return true;
3602 } else {
3603 if (!(reverse_access_mask &
3604 (1u << inst->Src[0].Register.Index)))
3605 return true;
3606 }
3607 }
3608
3609 /* If there are no buffer writes (for both shader buffers & image
3610 * buffers), it implies that buffer memory is read-only.
3611 * If there are no buffer reads (for both shader buffers & image
3612 * buffers), it implies that buffer memory is write-only.
3613 *
3614 * Same for the case when there are no writes/reads for non-buffer
3615 * images.
3616 */
3617 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
3618 (inst->Src[0].Register.File == TGSI_FILE_IMAGE &&
3619 inst->Memory.Texture == TGSI_TEXTURE_BUFFER)) {
3620 if (!shader_buffers_reverse_access_mask &&
3621 !(info->images_buffers & images_reverse_access_mask))
3622 return true;
3623 } else {
3624 if (!(~info->images_buffers & images_reverse_access_mask))
3625 return true;
3626 }
3627 return false;
3628 }
3629
3630 static void load_emit(
3631 const struct lp_build_tgsi_action *action,
3632 struct lp_build_tgsi_context *bld_base,
3633 struct lp_build_emit_data *emit_data)
3634 {
3635 struct si_shader_context *ctx = si_shader_context(bld_base);
3636 struct gallivm_state *gallivm = bld_base->base.gallivm;
3637 LLVMBuilderRef builder = gallivm->builder;
3638 const struct tgsi_full_instruction * inst = emit_data->inst;
3639 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
3640 char intrinsic_name[64];
3641 bool readonly_memory = false;
3642
3643 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3644 load_emit_memory(ctx, emit_data);
3645 return;
3646 }
3647
3648 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3649 emit_waitcnt(ctx, VM_CNT);
3650
3651 readonly_memory = !(inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE) &&
3652 is_oneway_access_only(inst, info,
3653 info->shader_buffers_store |
3654 info->shader_buffers_atomic,
3655 info->images_store |
3656 info->images_atomic);
3657
3658 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3659 load_emit_buffer(ctx, emit_data, readonly_memory);
3660 return;
3661 }
3662
3663 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3664 emit_data->output[emit_data->chan] =
3665 lp_build_intrinsic(
3666 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3667 emit_data->args, emit_data->arg_count,
3668 get_load_intr_attribs(readonly_memory));
3669 } else {
3670 ac_get_image_intr_name("llvm.amdgcn.image.load",
3671 emit_data->dst_type, /* vdata */
3672 LLVMTypeOf(emit_data->args[0]), /* coords */
3673 LLVMTypeOf(emit_data->args[1]), /* rsrc */
3674 intrinsic_name, sizeof(intrinsic_name));
3675
3676 emit_data->output[emit_data->chan] =
3677 lp_build_intrinsic(
3678 builder, intrinsic_name, emit_data->dst_type,
3679 emit_data->args, emit_data->arg_count,
3680 get_load_intr_attribs(readonly_memory));
3681 }
3682 }
3683
3684 static void store_fetch_args(
3685 struct lp_build_tgsi_context * bld_base,
3686 struct lp_build_emit_data * emit_data)
3687 {
3688 struct si_shader_context *ctx = si_shader_context(bld_base);
3689 struct gallivm_state *gallivm = bld_base->base.gallivm;
3690 LLVMBuilderRef builder = gallivm->builder;
3691 const struct tgsi_full_instruction * inst = emit_data->inst;
3692 struct tgsi_full_src_register memory;
3693 LLVMValueRef chans[4];
3694 LLVMValueRef data;
3695 LLVMValueRef rsrc;
3696 unsigned chan;
3697
3698 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3699
3700 for (chan = 0; chan < 4; ++chan) {
3701 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3702 }
3703 data = lp_build_gather_values(gallivm, chans, 4);
3704
3705 emit_data->args[emit_data->arg_count++] = data;
3706
3707 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3708
3709 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3710 LLVMValueRef offset;
3711 LLVMValueRef tmp;
3712
3713 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3714
3715 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3716 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3717
3718 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3719 offset, false, false);
3720 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3721 unsigned target = inst->Memory.Texture;
3722 LLVMValueRef coords;
3723
3724 /* 8bit/16bit TC L1 write corruption bug on SI.
3725 * All store opcodes not aligned to a dword are affected.
3726 *
3727 * The only way to get unaligned stores in radeonsi is through
3728 * shader images.
3729 */
3730 bool force_glc = ctx->screen->b.chip_class == SI;
3731
3732 coords = image_fetch_coords(bld_base, inst, 0);
3733
3734 if (target == TGSI_TEXTURE_BUFFER) {
3735 image_fetch_rsrc(bld_base, &memory, true, target, &rsrc);
3736 buffer_append_args(ctx, emit_data, rsrc, coords,
3737 bld_base->uint_bld.zero, false, force_glc);
3738 } else {
3739 emit_data->args[1] = coords;
3740 image_fetch_rsrc(bld_base, &memory, true, target,
3741 &emit_data->args[2]);
3742 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3743 emit_data->arg_count = 4;
3744
3745 image_append_args(ctx, emit_data, target, false, force_glc);
3746 }
3747 }
3748 }
3749
3750 static void store_emit_buffer(
3751 struct si_shader_context *ctx,
3752 struct lp_build_emit_data *emit_data,
3753 bool writeonly_memory)
3754 {
3755 const struct tgsi_full_instruction *inst = emit_data->inst;
3756 struct gallivm_state *gallivm = &ctx->gallivm;
3757 LLVMBuilderRef builder = gallivm->builder;
3758 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
3759 LLVMValueRef base_data = emit_data->args[0];
3760 LLVMValueRef base_offset = emit_data->args[3];
3761 unsigned writemask = inst->Dst[0].Register.WriteMask;
3762
3763 while (writemask) {
3764 int start, count;
3765 const char *intrinsic_name;
3766 LLVMValueRef data;
3767 LLVMValueRef offset;
3768 LLVMValueRef tmp;
3769
3770 u_bit_scan_consecutive_range(&writemask, &start, &count);
3771
3772 /* Due to an LLVM limitation, split 3-element writes
3773 * into a 2-element and a 1-element write. */
3774 if (count == 3) {
3775 writemask |= 1 << (start + 2);
3776 count = 2;
3777 }
3778
3779 if (count == 4) {
3780 data = base_data;
3781 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3782 } else if (count == 2) {
3783 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3784
3785 tmp = LLVMBuildExtractElement(
3786 builder, base_data,
3787 lp_build_const_int32(gallivm, start), "");
3788 data = LLVMBuildInsertElement(
3789 builder, LLVMGetUndef(v2f32), tmp,
3790 uint_bld->zero, "");
3791
3792 tmp = LLVMBuildExtractElement(
3793 builder, base_data,
3794 lp_build_const_int32(gallivm, start + 1), "");
3795 data = LLVMBuildInsertElement(
3796 builder, data, tmp, uint_bld->one, "");
3797
3798 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3799 } else {
3800 assert(count == 1);
3801 data = LLVMBuildExtractElement(
3802 builder, base_data,
3803 lp_build_const_int32(gallivm, start), "");
3804 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3805 }
3806
3807 offset = base_offset;
3808 if (start != 0) {
3809 offset = LLVMBuildAdd(
3810 builder, offset,
3811 lp_build_const_int32(gallivm, start * 4), "");
3812 }
3813
3814 emit_data->args[0] = data;
3815 emit_data->args[3] = offset;
3816
3817 lp_build_intrinsic(
3818 builder, intrinsic_name, emit_data->dst_type,
3819 emit_data->args, emit_data->arg_count,
3820 get_store_intr_attribs(writeonly_memory));
3821 }
3822 }
3823
3824 static void store_emit_memory(
3825 struct si_shader_context *ctx,
3826 struct lp_build_emit_data *emit_data)
3827 {
3828 const struct tgsi_full_instruction *inst = emit_data->inst;
3829 struct gallivm_state *gallivm = &ctx->gallivm;
3830 struct lp_build_context *base = &ctx->bld_base.base;
3831 LLVMBuilderRef builder = gallivm->builder;
3832 unsigned writemask = inst->Dst[0].Register.WriteMask;
3833 LLVMValueRef ptr, derived_ptr, data, index;
3834 int chan;
3835
3836 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3837
3838 for (chan = 0; chan < 4; ++chan) {
3839 if (!(writemask & (1 << chan))) {
3840 continue;
3841 }
3842 data = lp_build_emit_fetch(&ctx->bld_base, inst, 1, chan);
3843 index = lp_build_const_int32(gallivm, chan);
3844 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3845 LLVMBuildStore(builder, data, derived_ptr);
3846 }
3847 }
3848
3849 static void store_emit(
3850 const struct lp_build_tgsi_action *action,
3851 struct lp_build_tgsi_context *bld_base,
3852 struct lp_build_emit_data *emit_data)
3853 {
3854 struct si_shader_context *ctx = si_shader_context(bld_base);
3855 struct gallivm_state *gallivm = bld_base->base.gallivm;
3856 LLVMBuilderRef builder = gallivm->builder;
3857 const struct tgsi_full_instruction * inst = emit_data->inst;
3858 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
3859 unsigned target = inst->Memory.Texture;
3860 char intrinsic_name[64];
3861 bool writeonly_memory = false;
3862
3863 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3864 store_emit_memory(ctx, emit_data);
3865 return;
3866 }
3867
3868 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3869 emit_waitcnt(ctx, VM_CNT);
3870
3871 writeonly_memory = is_oneway_access_only(inst, info,
3872 info->shader_buffers_load |
3873 info->shader_buffers_atomic,
3874 info->images_load |
3875 info->images_atomic);
3876
3877 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3878 store_emit_buffer(ctx, emit_data, writeonly_memory);
3879 return;
3880 }
3881
3882 if (target == TGSI_TEXTURE_BUFFER) {
3883 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3884 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3885 emit_data->dst_type, emit_data->args,
3886 emit_data->arg_count,
3887 get_store_intr_attribs(writeonly_memory));
3888 } else {
3889 ac_get_image_intr_name("llvm.amdgcn.image.store",
3890 LLVMTypeOf(emit_data->args[0]), /* vdata */
3891 LLVMTypeOf(emit_data->args[1]), /* coords */
3892 LLVMTypeOf(emit_data->args[2]), /* rsrc */
3893 intrinsic_name, sizeof(intrinsic_name));
3894
3895 emit_data->output[emit_data->chan] =
3896 lp_build_intrinsic(
3897 builder, intrinsic_name, emit_data->dst_type,
3898 emit_data->args, emit_data->arg_count,
3899 get_store_intr_attribs(writeonly_memory));
3900 }
3901 }
3902
3903 static void atomic_fetch_args(
3904 struct lp_build_tgsi_context * bld_base,
3905 struct lp_build_emit_data * emit_data)
3906 {
3907 struct si_shader_context *ctx = si_shader_context(bld_base);
3908 struct gallivm_state *gallivm = bld_base->base.gallivm;
3909 LLVMBuilderRef builder = gallivm->builder;
3910 const struct tgsi_full_instruction * inst = emit_data->inst;
3911 LLVMValueRef data1, data2;
3912 LLVMValueRef rsrc;
3913 LLVMValueRef tmp;
3914
3915 emit_data->dst_type = bld_base->base.elem_type;
3916
3917 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
3918 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3919
3920 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3921 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
3922 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3923 }
3924
3925 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3926 * of arguments, which is reversed relative to TGSI (and GLSL)
3927 */
3928 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3929 emit_data->args[emit_data->arg_count++] = data2;
3930 emit_data->args[emit_data->arg_count++] = data1;
3931
3932 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3933 LLVMValueRef offset;
3934
3935 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3936
3937 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3938 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3939
3940 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3941 offset, true, false);
3942 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3943 unsigned target = inst->Memory.Texture;
3944 LLVMValueRef coords;
3945
3946 image_fetch_rsrc(bld_base, &inst->Src[0], true, target, &rsrc);
3947 coords = image_fetch_coords(bld_base, inst, 1);
3948
3949 if (target == TGSI_TEXTURE_BUFFER) {
3950 buffer_append_args(ctx, emit_data, rsrc, coords,
3951 bld_base->uint_bld.zero, true, false);
3952 } else {
3953 emit_data->args[emit_data->arg_count++] = coords;
3954 emit_data->args[emit_data->arg_count++] = rsrc;
3955
3956 image_append_args(ctx, emit_data, target, true, false);
3957 }
3958 }
3959 }
3960
3961 static void atomic_emit_memory(struct si_shader_context *ctx,
3962 struct lp_build_emit_data *emit_data) {
3963 struct gallivm_state *gallivm = &ctx->gallivm;
3964 LLVMBuilderRef builder = gallivm->builder;
3965 const struct tgsi_full_instruction * inst = emit_data->inst;
3966 LLVMValueRef ptr, result, arg;
3967
3968 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
3969
3970 arg = lp_build_emit_fetch(&ctx->bld_base, inst, 2, 0);
3971 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
3972
3973 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3974 LLVMValueRef new_data;
3975 new_data = lp_build_emit_fetch(&ctx->bld_base,
3976 inst, 3, 0);
3977
3978 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
3979
3980 #if HAVE_LLVM >= 0x309
3981 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
3982 LLVMAtomicOrderingSequentiallyConsistent,
3983 LLVMAtomicOrderingSequentiallyConsistent,
3984 false);
3985 #endif
3986
3987 result = LLVMBuildExtractValue(builder, result, 0, "");
3988 } else {
3989 LLVMAtomicRMWBinOp op;
3990
3991 switch(inst->Instruction.Opcode) {
3992 case TGSI_OPCODE_ATOMUADD:
3993 op = LLVMAtomicRMWBinOpAdd;
3994 break;
3995 case TGSI_OPCODE_ATOMXCHG:
3996 op = LLVMAtomicRMWBinOpXchg;
3997 break;
3998 case TGSI_OPCODE_ATOMAND:
3999 op = LLVMAtomicRMWBinOpAnd;
4000 break;
4001 case TGSI_OPCODE_ATOMOR:
4002 op = LLVMAtomicRMWBinOpOr;
4003 break;
4004 case TGSI_OPCODE_ATOMXOR:
4005 op = LLVMAtomicRMWBinOpXor;
4006 break;
4007 case TGSI_OPCODE_ATOMUMIN:
4008 op = LLVMAtomicRMWBinOpUMin;
4009 break;
4010 case TGSI_OPCODE_ATOMUMAX:
4011 op = LLVMAtomicRMWBinOpUMax;
4012 break;
4013 case TGSI_OPCODE_ATOMIMIN:
4014 op = LLVMAtomicRMWBinOpMin;
4015 break;
4016 case TGSI_OPCODE_ATOMIMAX:
4017 op = LLVMAtomicRMWBinOpMax;
4018 break;
4019 default:
4020 unreachable("unknown atomic opcode");
4021 }
4022
4023 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
4024 LLVMAtomicOrderingSequentiallyConsistent,
4025 false);
4026 }
4027 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
4028 }
4029
4030 static void atomic_emit(
4031 const struct lp_build_tgsi_action *action,
4032 struct lp_build_tgsi_context *bld_base,
4033 struct lp_build_emit_data *emit_data)
4034 {
4035 struct si_shader_context *ctx = si_shader_context(bld_base);
4036 struct gallivm_state *gallivm = bld_base->base.gallivm;
4037 LLVMBuilderRef builder = gallivm->builder;
4038 const struct tgsi_full_instruction * inst = emit_data->inst;
4039 char intrinsic_name[40];
4040 LLVMValueRef tmp;
4041
4042 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
4043 atomic_emit_memory(ctx, emit_data);
4044 return;
4045 }
4046
4047 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
4048 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4049 snprintf(intrinsic_name, sizeof(intrinsic_name),
4050 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
4051 } else {
4052 LLVMValueRef coords;
4053 char coords_type[8];
4054
4055 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4056 coords = emit_data->args[2];
4057 else
4058 coords = emit_data->args[1];
4059
4060 ac_build_type_name_for_intr(LLVMTypeOf(coords), coords_type, sizeof(coords_type));
4061 snprintf(intrinsic_name, sizeof(intrinsic_name),
4062 "llvm.amdgcn.image.atomic.%s.%s",
4063 action->intr_name, coords_type);
4064 }
4065
4066 tmp = lp_build_intrinsic(
4067 builder, intrinsic_name, bld_base->uint_bld.elem_type,
4068 emit_data->args, emit_data->arg_count, 0);
4069 emit_data->output[emit_data->chan] =
4070 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
4071 }
4072
4073 static void set_tex_fetch_args(struct si_shader_context *ctx,
4074 struct lp_build_emit_data *emit_data,
4075 unsigned target,
4076 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4077 LLVMValueRef *param, unsigned count,
4078 unsigned dmask)
4079 {
4080 struct gallivm_state *gallivm = &ctx->gallivm;
4081 struct ac_image_args args = {};
4082
4083 /* Pad to power of two vector */
4084 while (count < util_next_power_of_two(count))
4085 param[count++] = LLVMGetUndef(ctx->i32);
4086
4087 if (count > 1)
4088 args.addr = lp_build_gather_values(gallivm, param, count);
4089 else
4090 args.addr = param[0];
4091
4092 args.resource = res_ptr;
4093 args.sampler = samp_ptr;
4094 args.dmask = dmask;
4095 args.unorm = target == TGSI_TEXTURE_RECT ||
4096 target == TGSI_TEXTURE_SHADOWRECT;
4097 args.da = tgsi_is_array_sampler(target);
4098
4099 /* Ugly, but we seem to have no other choice right now. */
4100 STATIC_ASSERT(sizeof(args) <= sizeof(emit_data->args));
4101 memcpy(emit_data->args, &args, sizeof(args));
4102 }
4103
4104 static LLVMValueRef fix_resinfo(struct si_shader_context *ctx,
4105 unsigned target, LLVMValueRef out)
4106 {
4107 LLVMBuilderRef builder = ctx->gallivm.builder;
4108
4109 /* 1D textures are allocated and used as 2D on GFX9. */
4110 if (ctx->screen->b.chip_class >= GFX9 &&
4111 (target == TGSI_TEXTURE_1D_ARRAY ||
4112 target == TGSI_TEXTURE_SHADOW1D_ARRAY)) {
4113 LLVMValueRef layers =
4114 LLVMBuildExtractElement(builder, out,
4115 LLVMConstInt(ctx->i32, 2, 0), "");
4116 out = LLVMBuildInsertElement(builder, out, layers,
4117 LLVMConstInt(ctx->i32, 1, 0), "");
4118 }
4119
4120 /* Divide the number of layers by 6 to get the number of cubes. */
4121 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4122 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4123 LLVMValueRef imm2 = LLVMConstInt(ctx->i32, 2, 0);
4124
4125 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4126 z = LLVMBuildSDiv(builder, z, LLVMConstInt(ctx->i32, 6, 0), "");
4127
4128 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4129 }
4130 return out;
4131 }
4132
4133 static void resq_fetch_args(
4134 struct lp_build_tgsi_context * bld_base,
4135 struct lp_build_emit_data * emit_data)
4136 {
4137 struct si_shader_context *ctx = si_shader_context(bld_base);
4138 const struct tgsi_full_instruction *inst = emit_data->inst;
4139 const struct tgsi_full_src_register *reg = &inst->Src[0];
4140
4141 emit_data->dst_type = ctx->v4i32;
4142
4143 if (reg->Register.File == TGSI_FILE_BUFFER) {
4144 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4145 emit_data->arg_count = 1;
4146 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4147 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4148 &emit_data->args[0]);
4149 emit_data->arg_count = 1;
4150 } else {
4151 LLVMValueRef res_ptr;
4152 unsigned image_target;
4153
4154 if (inst->Memory.Texture == TGSI_TEXTURE_3D)
4155 image_target = TGSI_TEXTURE_2D_ARRAY;
4156 else
4157 image_target = inst->Memory.Texture;
4158
4159 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4160 &res_ptr);
4161 set_tex_fetch_args(ctx, emit_data, image_target,
4162 res_ptr, NULL, &bld_base->uint_bld.zero, 1,
4163 0xf);
4164 }
4165 }
4166
4167 static void resq_emit(
4168 const struct lp_build_tgsi_action *action,
4169 struct lp_build_tgsi_context *bld_base,
4170 struct lp_build_emit_data *emit_data)
4171 {
4172 struct si_shader_context *ctx = si_shader_context(bld_base);
4173 struct gallivm_state *gallivm = bld_base->base.gallivm;
4174 LLVMBuilderRef builder = gallivm->builder;
4175 const struct tgsi_full_instruction *inst = emit_data->inst;
4176 LLVMValueRef out;
4177
4178 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4179 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4180 lp_build_const_int32(gallivm, 2), "");
4181 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4182 out = get_buffer_size(bld_base, emit_data->args[0]);
4183 } else {
4184 struct ac_image_args args;
4185
4186 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
4187 args.opcode = ac_image_get_resinfo;
4188 out = ac_build_image_opcode(&ctx->ac, &args);
4189
4190 out = fix_resinfo(ctx, inst->Memory.Texture, out);
4191 }
4192
4193 emit_data->output[emit_data->chan] = out;
4194 }
4195
4196 static const struct lp_build_tgsi_action tex_action;
4197
4198 enum desc_type {
4199 DESC_IMAGE,
4200 DESC_BUFFER,
4201 DESC_FMASK,
4202 DESC_SAMPLER,
4203 };
4204
4205 /**
4206 * Load an image view, fmask view. or sampler state descriptor.
4207 */
4208 static LLVMValueRef load_sampler_desc(struct si_shader_context *ctx,
4209 LLVMValueRef list, LLVMValueRef index,
4210 enum desc_type type)
4211 {
4212 struct gallivm_state *gallivm = &ctx->gallivm;
4213 LLVMBuilderRef builder = gallivm->builder;
4214
4215 switch (type) {
4216 case DESC_IMAGE:
4217 /* The image is at [0:7]. */
4218 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4219 break;
4220 case DESC_BUFFER:
4221 /* The buffer is in [4:7]. */
4222 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4223 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4224 list = LLVMBuildPointerCast(builder, list,
4225 const_array(ctx->v4i32, 0), "");
4226 break;
4227 case DESC_FMASK:
4228 /* The FMASK is at [8:15]. */
4229 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4230 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4231 break;
4232 case DESC_SAMPLER:
4233 /* The sampler state is at [12:15]. */
4234 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4235 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4236 list = LLVMBuildPointerCast(builder, list,
4237 const_array(ctx->v4i32, 0), "");
4238 break;
4239 }
4240
4241 return ac_build_indexed_load_const(&ctx->ac, list, index);
4242 }
4243
4244 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4245 *
4246 * SI-CI:
4247 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4248 * filtering manually. The driver sets img7 to a mask clearing
4249 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4250 * s_and_b32 samp0, samp0, img7
4251 *
4252 * VI:
4253 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4254 */
4255 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4256 LLVMValueRef res, LLVMValueRef samp)
4257 {
4258 LLVMBuilderRef builder = ctx->gallivm.builder;
4259 LLVMValueRef img7, samp0;
4260
4261 if (ctx->screen->b.chip_class >= VI)
4262 return samp;
4263
4264 img7 = LLVMBuildExtractElement(builder, res,
4265 LLVMConstInt(ctx->i32, 7, 0), "");
4266 samp0 = LLVMBuildExtractElement(builder, samp,
4267 LLVMConstInt(ctx->i32, 0, 0), "");
4268 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4269 return LLVMBuildInsertElement(builder, samp, samp0,
4270 LLVMConstInt(ctx->i32, 0, 0), "");
4271 }
4272
4273 static void tex_fetch_ptrs(
4274 struct lp_build_tgsi_context *bld_base,
4275 struct lp_build_emit_data *emit_data,
4276 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4277 {
4278 struct si_shader_context *ctx = si_shader_context(bld_base);
4279 LLVMValueRef list = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLERS);
4280 const struct tgsi_full_instruction *inst = emit_data->inst;
4281 const struct tgsi_full_src_register *reg;
4282 unsigned target = inst->Texture.Texture;
4283 unsigned sampler_src;
4284 LLVMValueRef index;
4285
4286 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4287 reg = &emit_data->inst->Src[sampler_src];
4288
4289 if (reg->Register.Indirect) {
4290 index = get_bounded_indirect_index(ctx,
4291 &reg->Indirect,
4292 reg->Register.Index,
4293 SI_NUM_SAMPLERS);
4294 } else {
4295 index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
4296 }
4297
4298 if (target == TGSI_TEXTURE_BUFFER)
4299 *res_ptr = load_sampler_desc(ctx, list, index, DESC_BUFFER);
4300 else
4301 *res_ptr = load_sampler_desc(ctx, list, index, DESC_IMAGE);
4302
4303 if (samp_ptr)
4304 *samp_ptr = NULL;
4305 if (fmask_ptr)
4306 *fmask_ptr = NULL;
4307
4308 if (target == TGSI_TEXTURE_2D_MSAA ||
4309 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4310 if (fmask_ptr)
4311 *fmask_ptr = load_sampler_desc(ctx, list, index,
4312 DESC_FMASK);
4313 } else if (target != TGSI_TEXTURE_BUFFER) {
4314 if (samp_ptr) {
4315 *samp_ptr = load_sampler_desc(ctx, list, index,
4316 DESC_SAMPLER);
4317 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4318 }
4319 }
4320 }
4321
4322 static void txq_fetch_args(
4323 struct lp_build_tgsi_context *bld_base,
4324 struct lp_build_emit_data *emit_data)
4325 {
4326 struct si_shader_context *ctx = si_shader_context(bld_base);
4327 const struct tgsi_full_instruction *inst = emit_data->inst;
4328 unsigned target = inst->Texture.Texture;
4329 LLVMValueRef res_ptr;
4330 LLVMValueRef address;
4331
4332 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4333
4334 if (target == TGSI_TEXTURE_BUFFER) {
4335 /* Read the size from the buffer descriptor directly. */
4336 emit_data->args[0] = get_buffer_size(bld_base, res_ptr);
4337 return;
4338 }
4339
4340 /* Textures - set the mip level. */
4341 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4342
4343 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
4344 NULL, &address, 1, 0xf);
4345 }
4346
4347 static void txq_emit(const struct lp_build_tgsi_action *action,
4348 struct lp_build_tgsi_context *bld_base,
4349 struct lp_build_emit_data *emit_data)
4350 {
4351 struct si_shader_context *ctx = si_shader_context(bld_base);
4352 struct ac_image_args args;
4353 unsigned target = emit_data->inst->Texture.Texture;
4354
4355 if (target == TGSI_TEXTURE_BUFFER) {
4356 /* Just return the buffer size. */
4357 emit_data->output[emit_data->chan] = emit_data->args[0];
4358 return;
4359 }
4360
4361 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
4362
4363 args.opcode = ac_image_get_resinfo;
4364 LLVMValueRef result = ac_build_image_opcode(&ctx->ac, &args);
4365
4366 emit_data->output[emit_data->chan] = fix_resinfo(ctx, target, result);
4367 }
4368
4369 static void tex_fetch_args(
4370 struct lp_build_tgsi_context *bld_base,
4371 struct lp_build_emit_data *emit_data)
4372 {
4373 struct si_shader_context *ctx = si_shader_context(bld_base);
4374 struct gallivm_state *gallivm = bld_base->base.gallivm;
4375 const struct tgsi_full_instruction *inst = emit_data->inst;
4376 unsigned opcode = inst->Instruction.Opcode;
4377 unsigned target = inst->Texture.Texture;
4378 LLVMValueRef coords[5], derivs[6];
4379 LLVMValueRef address[16];
4380 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4381 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4382 unsigned count = 0;
4383 unsigned chan;
4384 unsigned num_deriv_channels = 0;
4385 bool has_offset = inst->Texture.NumOffsets > 0;
4386 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4387 unsigned dmask = 0xf;
4388
4389 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4390
4391 if (target == TGSI_TEXTURE_BUFFER) {
4392 emit_data->dst_type = ctx->v4f32;
4393 emit_data->args[0] = LLVMBuildBitCast(gallivm->builder, res_ptr,
4394 ctx->v16i8, "");
4395 emit_data->args[1] = bld_base->uint_bld.zero;
4396 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4397 emit_data->arg_count = 3;
4398 return;
4399 }
4400
4401 /* Fetch and project texture coordinates */
4402 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4403 for (chan = 0; chan < 3; chan++ ) {
4404 coords[chan] = lp_build_emit_fetch(bld_base,
4405 emit_data->inst, 0,
4406 chan);
4407 if (opcode == TGSI_OPCODE_TXP)
4408 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4409 TGSI_OPCODE_DIV,
4410 coords[chan],
4411 coords[3]);
4412 }
4413
4414 if (opcode == TGSI_OPCODE_TXP)
4415 coords[3] = bld_base->base.one;
4416
4417 /* Pack offsets. */
4418 if (has_offset &&
4419 opcode != TGSI_OPCODE_TXF &&
4420 opcode != TGSI_OPCODE_TXF_LZ) {
4421 /* The offsets are six-bit signed integers packed like this:
4422 * X=[5:0], Y=[13:8], and Z=[21:16].
4423 */
4424 LLVMValueRef offset[3], pack;
4425
4426 assert(inst->Texture.NumOffsets == 1);
4427
4428 for (chan = 0; chan < 3; chan++) {
4429 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4430 emit_data->inst, 0, chan);
4431 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4432 lp_build_const_int32(gallivm, 0x3f), "");
4433 if (chan)
4434 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4435 lp_build_const_int32(gallivm, chan*8), "");
4436 }
4437
4438 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4439 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4440 address[count++] = pack;
4441 }
4442
4443 /* Pack LOD bias value */
4444 if (opcode == TGSI_OPCODE_TXB)
4445 address[count++] = coords[3];
4446 if (opcode == TGSI_OPCODE_TXB2)
4447 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4448
4449 /* Pack depth comparison value */
4450 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4451 LLVMValueRef z;
4452
4453 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4454 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4455 } else {
4456 assert(ref_pos >= 0);
4457 z = coords[ref_pos];
4458 }
4459
4460 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4461 * so the depth comparison value isn't clamped for Z16 and
4462 * Z24 anymore. Do it manually here.
4463 *
4464 * It's unnecessary if the original texture format was
4465 * Z32_FLOAT, but we don't know that here.
4466 */
4467 if (ctx->screen->b.chip_class == VI)
4468 z = ac_build_clamp(&ctx->ac, z);
4469
4470 address[count++] = z;
4471 }
4472
4473 /* Pack user derivatives */
4474 if (opcode == TGSI_OPCODE_TXD) {
4475 int param, num_src_deriv_channels, num_dst_deriv_channels;
4476
4477 switch (target) {
4478 case TGSI_TEXTURE_3D:
4479 num_src_deriv_channels = 3;
4480 num_dst_deriv_channels = 3;
4481 num_deriv_channels = 3;
4482 break;
4483 case TGSI_TEXTURE_2D:
4484 case TGSI_TEXTURE_SHADOW2D:
4485 case TGSI_TEXTURE_RECT:
4486 case TGSI_TEXTURE_SHADOWRECT:
4487 case TGSI_TEXTURE_2D_ARRAY:
4488 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4489 num_src_deriv_channels = 2;
4490 num_dst_deriv_channels = 2;
4491 num_deriv_channels = 2;
4492 break;
4493 case TGSI_TEXTURE_CUBE:
4494 case TGSI_TEXTURE_SHADOWCUBE:
4495 case TGSI_TEXTURE_CUBE_ARRAY:
4496 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4497 /* Cube derivatives will be converted to 2D. */
4498 num_src_deriv_channels = 3;
4499 num_dst_deriv_channels = 3;
4500 num_deriv_channels = 2;
4501 break;
4502 case TGSI_TEXTURE_1D:
4503 case TGSI_TEXTURE_SHADOW1D:
4504 case TGSI_TEXTURE_1D_ARRAY:
4505 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4506 num_src_deriv_channels = 1;
4507
4508 /* 1D textures are allocated and used as 2D on GFX9. */
4509 if (ctx->screen->b.chip_class >= GFX9) {
4510 num_dst_deriv_channels = 2;
4511 num_deriv_channels = 2;
4512 } else {
4513 num_dst_deriv_channels = 1;
4514 num_deriv_channels = 1;
4515 }
4516 break;
4517 default:
4518 unreachable("invalid target");
4519 }
4520
4521 for (param = 0; param < 2; param++) {
4522 for (chan = 0; chan < num_src_deriv_channels; chan++)
4523 derivs[param * num_dst_deriv_channels + chan] =
4524 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4525
4526 /* Fill in the rest with zeros. */
4527 for (chan = num_src_deriv_channels;
4528 chan < num_dst_deriv_channels; chan++)
4529 derivs[param * num_dst_deriv_channels + chan] =
4530 bld_base->base.zero;
4531 }
4532 }
4533
4534 if (target == TGSI_TEXTURE_CUBE ||
4535 target == TGSI_TEXTURE_CUBE_ARRAY ||
4536 target == TGSI_TEXTURE_SHADOWCUBE ||
4537 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4538 ac_prepare_cube_coords(&ctx->ac,
4539 opcode == TGSI_OPCODE_TXD,
4540 target == TGSI_TEXTURE_CUBE_ARRAY ||
4541 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
4542 coords, derivs);
4543
4544 if (opcode == TGSI_OPCODE_TXD)
4545 for (int i = 0; i < num_deriv_channels * 2; i++)
4546 address[count++] = derivs[i];
4547
4548 /* Pack texture coordinates */
4549 address[count++] = coords[0];
4550 if (num_coords > 1)
4551 address[count++] = coords[1];
4552 if (num_coords > 2)
4553 address[count++] = coords[2];
4554
4555 /* 1D textures are allocated and used as 2D on GFX9. */
4556 if (ctx->screen->b.chip_class >= GFX9) {
4557 LLVMValueRef filler;
4558
4559 /* Use 0.5, so that we don't sample the border color. */
4560 if (opcode == TGSI_OPCODE_TXF)
4561 filler = bld_base->uint_bld.zero;
4562 else
4563 filler = LLVMConstReal(ctx->f32, 0.5);
4564
4565 if (target == TGSI_TEXTURE_1D ||
4566 target == TGSI_TEXTURE_SHADOW1D) {
4567 address[count++] = filler;
4568 } else if (target == TGSI_TEXTURE_1D_ARRAY ||
4569 target == TGSI_TEXTURE_SHADOW1D_ARRAY) {
4570 address[count] = address[count - 1];
4571 address[count - 1] = filler;
4572 count++;
4573 }
4574 }
4575
4576 /* Pack LOD or sample index */
4577 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4578 address[count++] = coords[3];
4579 else if (opcode == TGSI_OPCODE_TXL2)
4580 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4581
4582 if (count > 16) {
4583 assert(!"Cannot handle more than 16 texture address parameters");
4584 count = 16;
4585 }
4586
4587 for (chan = 0; chan < count; chan++ ) {
4588 address[chan] = LLVMBuildBitCast(gallivm->builder,
4589 address[chan], ctx->i32, "");
4590 }
4591
4592 /* Adjust the sample index according to FMASK.
4593 *
4594 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4595 * which is the identity mapping. Each nibble says which physical sample
4596 * should be fetched to get that sample.
4597 *
4598 * For example, 0x11111100 means there are only 2 samples stored and
4599 * the second sample covers 3/4 of the pixel. When reading samples 0
4600 * and 1, return physical sample 0 (determined by the first two 0s
4601 * in FMASK), otherwise return physical sample 1.
4602 *
4603 * The sample index should be adjusted as follows:
4604 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4605 */
4606 if (target == TGSI_TEXTURE_2D_MSAA ||
4607 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4608 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4609 struct lp_build_emit_data txf_emit_data = *emit_data;
4610 LLVMValueRef txf_address[4];
4611 /* We only need .xy for non-arrays, and .xyz for arrays. */
4612 unsigned txf_count = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4613 struct tgsi_full_instruction inst = {};
4614
4615 memcpy(txf_address, address, sizeof(txf_address));
4616
4617 /* Read FMASK using TXF_LZ. */
4618 inst.Instruction.Opcode = TGSI_OPCODE_TXF_LZ;
4619 inst.Texture.Texture = target;
4620 txf_emit_data.inst = &inst;
4621 txf_emit_data.chan = 0;
4622 set_tex_fetch_args(ctx, &txf_emit_data,
4623 target, fmask_ptr, NULL,
4624 txf_address, txf_count, 0xf);
4625 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4626
4627 /* Initialize some constants. */
4628 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4629 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4630
4631 /* Apply the formula. */
4632 LLVMValueRef fmask =
4633 LLVMBuildExtractElement(gallivm->builder,
4634 txf_emit_data.output[0],
4635 uint_bld->zero, "");
4636
4637 unsigned sample_chan = txf_count; /* the sample index is last */
4638
4639 LLVMValueRef sample_index4 =
4640 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4641
4642 LLVMValueRef shifted_fmask =
4643 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4644
4645 LLVMValueRef final_sample =
4646 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4647
4648 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4649 * resource descriptor is 0 (invalid),
4650 */
4651 LLVMValueRef fmask_desc =
4652 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4653 ctx->v8i32, "");
4654
4655 LLVMValueRef fmask_word1 =
4656 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4657 uint_bld->one, "");
4658
4659 LLVMValueRef word1_is_nonzero =
4660 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4661 fmask_word1, uint_bld->zero, "");
4662
4663 /* Replace the MSAA sample index. */
4664 address[sample_chan] =
4665 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4666 final_sample, address[sample_chan], "");
4667 }
4668
4669 if (opcode == TGSI_OPCODE_TXF ||
4670 opcode == TGSI_OPCODE_TXF_LZ) {
4671 /* add tex offsets */
4672 if (inst->Texture.NumOffsets) {
4673 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4674 const struct tgsi_texture_offset *off = inst->TexOffsets;
4675
4676 assert(inst->Texture.NumOffsets == 1);
4677
4678 switch (target) {
4679 case TGSI_TEXTURE_3D:
4680 address[2] = lp_build_add(uint_bld, address[2],
4681 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ]);
4682 /* fall through */
4683 case TGSI_TEXTURE_2D:
4684 case TGSI_TEXTURE_SHADOW2D:
4685 case TGSI_TEXTURE_RECT:
4686 case TGSI_TEXTURE_SHADOWRECT:
4687 case TGSI_TEXTURE_2D_ARRAY:
4688 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4689 address[1] =
4690 lp_build_add(uint_bld, address[1],
4691 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY]);
4692 /* fall through */
4693 case TGSI_TEXTURE_1D:
4694 case TGSI_TEXTURE_SHADOW1D:
4695 case TGSI_TEXTURE_1D_ARRAY:
4696 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4697 address[0] =
4698 lp_build_add(uint_bld, address[0],
4699 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX]);
4700 break;
4701 /* texture offsets do not apply to other texture targets */
4702 }
4703 }
4704 }
4705
4706 if (opcode == TGSI_OPCODE_TG4) {
4707 unsigned gather_comp = 0;
4708
4709 /* DMASK was repurposed for GATHER4. 4 components are always
4710 * returned and DMASK works like a swizzle - it selects
4711 * the component to fetch. The only valid DMASK values are
4712 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4713 * (red,red,red,red) etc.) The ISA document doesn't mention
4714 * this.
4715 */
4716
4717 /* Get the component index from src1.x for Gather4. */
4718 if (!tgsi_is_shadow_target(target)) {
4719 LLVMValueRef comp_imm;
4720 struct tgsi_src_register src1 = inst->Src[1].Register;
4721
4722 assert(src1.File == TGSI_FILE_IMMEDIATE);
4723
4724 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX];
4725 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4726 gather_comp = CLAMP(gather_comp, 0, 3);
4727 }
4728
4729 dmask = 1 << gather_comp;
4730 }
4731
4732 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
4733 samp_ptr, address, count, dmask);
4734 }
4735
4736 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
4737 * incorrectly forces nearest filtering if the texture format is integer.
4738 * The only effect it has on Gather4, which always returns 4 texels for
4739 * bilinear filtering, is that the final coordinates are off by 0.5 of
4740 * the texel size.
4741 *
4742 * The workaround is to subtract 0.5 from the unnormalized coordinates,
4743 * or (0.5 / size) from the normalized coordinates.
4744 */
4745 static void si_lower_gather4_integer(struct si_shader_context *ctx,
4746 struct ac_image_args *args,
4747 unsigned target)
4748 {
4749 LLVMBuilderRef builder = ctx->gallivm.builder;
4750 LLVMValueRef coord = args->addr;
4751 LLVMValueRef half_texel[2];
4752 /* Texture coordinates start after:
4753 * {offset, bias, z-compare, derivatives}
4754 * Only the offset and z-compare can occur here.
4755 */
4756 unsigned coord_vgpr_index = (int)args->offset + (int)args->compare;
4757 int c;
4758
4759 if (target == TGSI_TEXTURE_RECT ||
4760 target == TGSI_TEXTURE_SHADOWRECT) {
4761 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
4762 } else {
4763 struct tgsi_full_instruction txq_inst = {};
4764 struct lp_build_emit_data txq_emit_data = {};
4765
4766 /* Query the texture size. */
4767 txq_inst.Texture.Texture = target;
4768 txq_emit_data.inst = &txq_inst;
4769 txq_emit_data.dst_type = ctx->v4i32;
4770 set_tex_fetch_args(ctx, &txq_emit_data, target,
4771 args->resource, NULL,
4772 &ctx->bld_base.uint_bld.zero,
4773 1, 0xf);
4774 txq_emit(NULL, &ctx->bld_base, &txq_emit_data);
4775
4776 /* Compute -0.5 / size. */
4777 for (c = 0; c < 2; c++) {
4778 half_texel[c] =
4779 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
4780 LLVMConstInt(ctx->i32, c, 0), "");
4781 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
4782 half_texel[c] =
4783 lp_build_emit_llvm_unary(&ctx->bld_base,
4784 TGSI_OPCODE_RCP, half_texel[c]);
4785 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
4786 LLVMConstReal(ctx->f32, -0.5), "");
4787 }
4788 }
4789
4790 for (c = 0; c < 2; c++) {
4791 LLVMValueRef tmp;
4792 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
4793
4794 tmp = LLVMBuildExtractElement(builder, coord, index, "");
4795 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4796 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
4797 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4798 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
4799 }
4800
4801 args->addr = coord;
4802 }
4803
4804 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4805 struct lp_build_tgsi_context *bld_base,
4806 struct lp_build_emit_data *emit_data)
4807 {
4808 struct si_shader_context *ctx = si_shader_context(bld_base);
4809 const struct tgsi_full_instruction *inst = emit_data->inst;
4810 struct ac_image_args args;
4811 unsigned opcode = inst->Instruction.Opcode;
4812 unsigned target = inst->Texture.Texture;
4813
4814 if (target == TGSI_TEXTURE_BUFFER) {
4815 emit_data->output[emit_data->chan] =
4816 ac_build_buffer_load_format(&ctx->ac,
4817 emit_data->args[0],
4818 emit_data->args[2],
4819 emit_data->args[1],
4820 true);
4821 return;
4822 }
4823
4824 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
4825
4826 args.opcode = ac_image_sample;
4827 args.compare = tgsi_is_shadow_target(target);
4828 args.offset = inst->Texture.NumOffsets > 0;
4829
4830 switch (opcode) {
4831 case TGSI_OPCODE_TXF:
4832 case TGSI_OPCODE_TXF_LZ:
4833 args.opcode = opcode == TGSI_OPCODE_TXF_LZ ||
4834 target == TGSI_TEXTURE_2D_MSAA ||
4835 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4836 ac_image_load : ac_image_load_mip;
4837 args.compare = false;
4838 args.offset = false;
4839 break;
4840 case TGSI_OPCODE_LODQ:
4841 args.opcode = ac_image_get_lod;
4842 args.compare = false;
4843 args.offset = false;
4844 break;
4845 case TGSI_OPCODE_TEX:
4846 case TGSI_OPCODE_TEX2:
4847 case TGSI_OPCODE_TXP:
4848 if (ctx->type != PIPE_SHADER_FRAGMENT)
4849 args.level_zero = true;
4850 break;
4851 case TGSI_OPCODE_TEX_LZ:
4852 args.level_zero = true;
4853 break;
4854 case TGSI_OPCODE_TXB:
4855 case TGSI_OPCODE_TXB2:
4856 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4857 args.bias = true;
4858 break;
4859 case TGSI_OPCODE_TXL:
4860 case TGSI_OPCODE_TXL2:
4861 args.lod = true;
4862 break;
4863 case TGSI_OPCODE_TXD:
4864 args.deriv = true;
4865 break;
4866 case TGSI_OPCODE_TG4:
4867 args.opcode = ac_image_gather4;
4868 args.level_zero = true;
4869 break;
4870 default:
4871 assert(0);
4872 return;
4873 }
4874
4875 /* The hardware needs special lowering for Gather4 with integer formats. */
4876 if (ctx->screen->b.chip_class <= VI &&
4877 opcode == TGSI_OPCODE_TG4) {
4878 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4879 /* This will also work with non-constant indexing because of how
4880 * glsl_to_tgsi works and we intent to preserve that behavior.
4881 */
4882 const unsigned src_idx = 2;
4883 unsigned sampler = inst->Src[src_idx].Register.Index;
4884
4885 assert(inst->Src[src_idx].Register.File == TGSI_FILE_SAMPLER);
4886
4887 if (info->sampler_type[sampler] == TGSI_RETURN_TYPE_SINT ||
4888 info->sampler_type[sampler] == TGSI_RETURN_TYPE_UINT)
4889 si_lower_gather4_integer(ctx, &args, target);
4890 }
4891
4892 emit_data->output[emit_data->chan] =
4893 ac_build_image_opcode(&ctx->ac, &args);
4894 }
4895
4896 static void si_llvm_emit_txqs(
4897 const struct lp_build_tgsi_action *action,
4898 struct lp_build_tgsi_context *bld_base,
4899 struct lp_build_emit_data *emit_data)
4900 {
4901 struct si_shader_context *ctx = si_shader_context(bld_base);
4902 struct gallivm_state *gallivm = bld_base->base.gallivm;
4903 LLVMBuilderRef builder = gallivm->builder;
4904 LLVMValueRef res, samples;
4905 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4906
4907 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4908
4909
4910 /* Read the samples from the descriptor directly. */
4911 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4912 samples = LLVMBuildExtractElement(
4913 builder, res,
4914 lp_build_const_int32(gallivm, 3), "");
4915 samples = LLVMBuildLShr(builder, samples,
4916 lp_build_const_int32(gallivm, 16), "");
4917 samples = LLVMBuildAnd(builder, samples,
4918 lp_build_const_int32(gallivm, 0xf), "");
4919 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
4920 samples, "");
4921
4922 emit_data->output[emit_data->chan] = samples;
4923 }
4924
4925 static void si_llvm_emit_ddxy(
4926 const struct lp_build_tgsi_action *action,
4927 struct lp_build_tgsi_context *bld_base,
4928 struct lp_build_emit_data *emit_data)
4929 {
4930 struct si_shader_context *ctx = si_shader_context(bld_base);
4931 struct gallivm_state *gallivm = bld_base->base.gallivm;
4932 unsigned opcode = emit_data->info->opcode;
4933 LLVMValueRef val;
4934 int idx;
4935 unsigned mask;
4936
4937 if (opcode == TGSI_OPCODE_DDX_FINE)
4938 mask = AC_TID_MASK_LEFT;
4939 else if (opcode == TGSI_OPCODE_DDY_FINE)
4940 mask = AC_TID_MASK_TOP;
4941 else
4942 mask = AC_TID_MASK_TOP_LEFT;
4943
4944 /* for DDX we want to next X pixel, DDY next Y pixel. */
4945 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
4946
4947 val = LLVMBuildBitCast(gallivm->builder, emit_data->args[0], ctx->i32, "");
4948 val = ac_build_ddxy(&ctx->ac, ctx->screen->has_ds_bpermute,
4949 mask, idx, ctx->lds, val);
4950 emit_data->output[emit_data->chan] = val;
4951 }
4952
4953 /*
4954 * this takes an I,J coordinate pair,
4955 * and works out the X and Y derivatives.
4956 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
4957 */
4958 static LLVMValueRef si_llvm_emit_ddxy_interp(
4959 struct lp_build_tgsi_context *bld_base,
4960 LLVMValueRef interp_ij)
4961 {
4962 struct si_shader_context *ctx = si_shader_context(bld_base);
4963 struct gallivm_state *gallivm = bld_base->base.gallivm;
4964 LLVMValueRef result[4], a;
4965 unsigned i;
4966
4967 for (i = 0; i < 2; i++) {
4968 a = LLVMBuildExtractElement(gallivm->builder, interp_ij,
4969 LLVMConstInt(ctx->i32, i, 0), "");
4970 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
4971 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
4972 }
4973
4974 return lp_build_gather_values(gallivm, result, 4);
4975 }
4976
4977 static void interp_fetch_args(
4978 struct lp_build_tgsi_context *bld_base,
4979 struct lp_build_emit_data *emit_data)
4980 {
4981 struct si_shader_context *ctx = si_shader_context(bld_base);
4982 struct gallivm_state *gallivm = bld_base->base.gallivm;
4983 const struct tgsi_full_instruction *inst = emit_data->inst;
4984
4985 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
4986 /* offset is in second src, first two channels */
4987 emit_data->args[0] = lp_build_emit_fetch(bld_base,
4988 emit_data->inst, 1,
4989 TGSI_CHAN_X);
4990 emit_data->args[1] = lp_build_emit_fetch(bld_base,
4991 emit_data->inst, 1,
4992 TGSI_CHAN_Y);
4993 emit_data->arg_count = 2;
4994 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4995 LLVMValueRef sample_position;
4996 LLVMValueRef sample_id;
4997 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
4998
4999 /* fetch sample ID, then fetch its sample position,
5000 * and place into first two channels.
5001 */
5002 sample_id = lp_build_emit_fetch(bld_base,
5003 emit_data->inst, 1, TGSI_CHAN_X);
5004 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
5005 ctx->i32, "");
5006 sample_position = load_sample_position(ctx, sample_id);
5007
5008 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
5009 sample_position,
5010 lp_build_const_int32(gallivm, 0), "");
5011
5012 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
5013 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
5014 sample_position,
5015 lp_build_const_int32(gallivm, 1), "");
5016 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
5017 emit_data->arg_count = 2;
5018 }
5019 }
5020
5021 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
5022 struct lp_build_tgsi_context *bld_base,
5023 struct lp_build_emit_data *emit_data)
5024 {
5025 struct si_shader_context *ctx = si_shader_context(bld_base);
5026 struct si_shader *shader = ctx->shader;
5027 struct gallivm_state *gallivm = bld_base->base.gallivm;
5028 struct lp_build_context *uint = &bld_base->uint_bld;
5029 LLVMValueRef interp_param;
5030 const struct tgsi_full_instruction *inst = emit_data->inst;
5031 int input_index = inst->Src[0].Register.Index;
5032 int chan;
5033 int i;
5034 LLVMValueRef attr_number;
5035 LLVMValueRef params = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
5036 int interp_param_idx;
5037 unsigned interp = shader->selector->info.input_interpolate[input_index];
5038 unsigned location;
5039
5040 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5041
5042 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5043 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
5044 location = TGSI_INTERPOLATE_LOC_CENTER;
5045 else
5046 location = TGSI_INTERPOLATE_LOC_CENTROID;
5047
5048 interp_param_idx = lookup_interp_param_index(interp, location);
5049 if (interp_param_idx == -1)
5050 return;
5051 else if (interp_param_idx)
5052 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
5053 else
5054 interp_param = NULL;
5055
5056 attr_number = lp_build_const_int32(gallivm, input_index);
5057
5058 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5059 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5060 LLVMValueRef ij_out[2];
5061 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
5062
5063 /*
5064 * take the I then J parameters, and the DDX/Y for it, and
5065 * calculate the IJ inputs for the interpolator.
5066 * temp1 = ddx * offset/sample.x + I;
5067 * interp_param.I = ddy * offset/sample.y + temp1;
5068 * temp1 = ddx * offset/sample.x + J;
5069 * interp_param.J = ddy * offset/sample.y + temp1;
5070 */
5071 for (i = 0; i < 2; i++) {
5072 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
5073 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
5074 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
5075 ddxy_out, ix_ll, "");
5076 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
5077 ddxy_out, iy_ll, "");
5078 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5079 interp_param, ix_ll, "");
5080 LLVMValueRef temp1, temp2;
5081
5082 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5083 ctx->f32, "");
5084
5085 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5086
5087 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5088
5089 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5090
5091 ij_out[i] = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5092 }
5093 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
5094 }
5095
5096 for (chan = 0; chan < 4; chan++) {
5097 LLVMValueRef llvm_chan;
5098 unsigned schan;
5099
5100 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5101 llvm_chan = lp_build_const_int32(gallivm, schan);
5102
5103 if (interp_param) {
5104 interp_param = LLVMBuildBitCast(gallivm->builder,
5105 interp_param, LLVMVectorType(ctx->f32, 2), "");
5106 LLVMValueRef i = LLVMBuildExtractElement(
5107 gallivm->builder, interp_param, uint->zero, "");
5108 LLVMValueRef j = LLVMBuildExtractElement(
5109 gallivm->builder, interp_param, uint->one, "");
5110 emit_data->output[chan] = ac_build_fs_interp(&ctx->ac,
5111 llvm_chan, attr_number, params,
5112 i, j);
5113 } else {
5114 emit_data->output[chan] = ac_build_fs_interp_mov(&ctx->ac,
5115 lp_build_const_int32(gallivm, 2), /* P0 */
5116 llvm_chan, attr_number, params);
5117 }
5118 }
5119 }
5120
5121 static LLVMValueRef si_emit_ballot(struct si_shader_context *ctx,
5122 LLVMValueRef value)
5123 {
5124 struct gallivm_state *gallivm = &ctx->gallivm;
5125 LLVMValueRef args[3] = {
5126 value,
5127 ctx->i32_0,
5128 LLVMConstInt(ctx->i32, LLVMIntNE, 0)
5129 };
5130
5131 if (LLVMTypeOf(value) != ctx->i32)
5132 args[0] = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
5133
5134 return lp_build_intrinsic(gallivm->builder,
5135 "llvm.amdgcn.icmp.i32",
5136 ctx->i64, args, 3,
5137 LP_FUNC_ATTR_NOUNWIND |
5138 LP_FUNC_ATTR_READNONE |
5139 LP_FUNC_ATTR_CONVERGENT);
5140 }
5141
5142 static void vote_all_emit(
5143 const struct lp_build_tgsi_action *action,
5144 struct lp_build_tgsi_context *bld_base,
5145 struct lp_build_emit_data *emit_data)
5146 {
5147 struct si_shader_context *ctx = si_shader_context(bld_base);
5148 struct gallivm_state *gallivm = &ctx->gallivm;
5149 LLVMValueRef active_set, vote_set;
5150 LLVMValueRef tmp;
5151
5152 active_set = si_emit_ballot(ctx, ctx->i32_1);
5153 vote_set = si_emit_ballot(ctx, emit_data->args[0]);
5154
5155 tmp = LLVMBuildICmp(gallivm->builder, LLVMIntEQ, vote_set, active_set, "");
5156 emit_data->output[emit_data->chan] =
5157 LLVMBuildSExt(gallivm->builder, tmp, ctx->i32, "");
5158 }
5159
5160 static void vote_any_emit(
5161 const struct lp_build_tgsi_action *action,
5162 struct lp_build_tgsi_context *bld_base,
5163 struct lp_build_emit_data *emit_data)
5164 {
5165 struct si_shader_context *ctx = si_shader_context(bld_base);
5166 struct gallivm_state *gallivm = &ctx->gallivm;
5167 LLVMValueRef vote_set;
5168 LLVMValueRef tmp;
5169
5170 vote_set = si_emit_ballot(ctx, emit_data->args[0]);
5171
5172 tmp = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
5173 vote_set, LLVMConstInt(ctx->i64, 0, 0), "");
5174 emit_data->output[emit_data->chan] =
5175 LLVMBuildSExt(gallivm->builder, tmp, ctx->i32, "");
5176 }
5177
5178 static void vote_eq_emit(
5179 const struct lp_build_tgsi_action *action,
5180 struct lp_build_tgsi_context *bld_base,
5181 struct lp_build_emit_data *emit_data)
5182 {
5183 struct si_shader_context *ctx = si_shader_context(bld_base);
5184 struct gallivm_state *gallivm = &ctx->gallivm;
5185 LLVMValueRef active_set, vote_set;
5186 LLVMValueRef all, none, tmp;
5187
5188 active_set = si_emit_ballot(ctx, ctx->i32_1);
5189 vote_set = si_emit_ballot(ctx, emit_data->args[0]);
5190
5191 all = LLVMBuildICmp(gallivm->builder, LLVMIntEQ, vote_set, active_set, "");
5192 none = LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
5193 vote_set, LLVMConstInt(ctx->i64, 0, 0), "");
5194 tmp = LLVMBuildOr(gallivm->builder, all, none, "");
5195 emit_data->output[emit_data->chan] =
5196 LLVMBuildSExt(gallivm->builder, tmp, ctx->i32, "");
5197 }
5198
5199 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5200 struct lp_build_emit_data *emit_data)
5201 {
5202 struct si_shader_context *ctx = si_shader_context(bld_base);
5203 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5204 LLVMValueRef imm;
5205 unsigned stream;
5206
5207 assert(src0.File == TGSI_FILE_IMMEDIATE);
5208
5209 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
5210 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
5211 return stream;
5212 }
5213
5214 /* Emit one vertex from the geometry shader */
5215 static void si_llvm_emit_vertex(
5216 const struct lp_build_tgsi_action *action,
5217 struct lp_build_tgsi_context *bld_base,
5218 struct lp_build_emit_data *emit_data)
5219 {
5220 struct si_shader_context *ctx = si_shader_context(bld_base);
5221 struct lp_build_context *uint = &bld_base->uint_bld;
5222 struct si_shader *shader = ctx->shader;
5223 struct tgsi_shader_info *info = &shader->selector->info;
5224 struct gallivm_state *gallivm = bld_base->base.gallivm;
5225 struct lp_build_if_state if_state;
5226 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
5227 SI_PARAM_GS2VS_OFFSET);
5228 LLVMValueRef gs_next_vertex;
5229 LLVMValueRef can_emit, kill;
5230 unsigned chan, offset;
5231 int i;
5232 unsigned stream;
5233
5234 stream = si_llvm_get_stream(bld_base, emit_data);
5235
5236 /* Write vertex attribute values to GSVS ring */
5237 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5238 ctx->gs_next_vertex[stream],
5239 "");
5240
5241 /* If this thread has already emitted the declared maximum number of
5242 * vertices, skip the write: excessive vertex emissions are not
5243 * supposed to have any effect.
5244 *
5245 * If the shader has no writes to memory, kill it instead. This skips
5246 * further memory loads and may allow LLVM to skip to the end
5247 * altogether.
5248 */
5249 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULT, gs_next_vertex,
5250 lp_build_const_int32(gallivm,
5251 shader->selector->gs_max_out_vertices), "");
5252
5253 bool use_kill = !info->writes_memory;
5254 if (use_kill) {
5255 kill = lp_build_select(&bld_base->base, can_emit,
5256 lp_build_const_float(gallivm, 1.0f),
5257 lp_build_const_float(gallivm, -1.0f));
5258
5259 ac_build_kill(&ctx->ac, kill);
5260 } else {
5261 lp_build_if(&if_state, gallivm, can_emit);
5262 }
5263
5264 offset = 0;
5265 for (i = 0; i < info->num_outputs; i++) {
5266 LLVMValueRef *out_ptr = ctx->outputs[i];
5267
5268 for (chan = 0; chan < 4; chan++) {
5269 if (!(info->output_usagemask[i] & (1 << chan)) ||
5270 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
5271 continue;
5272
5273 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5274 LLVMValueRef voffset =
5275 lp_build_const_int32(gallivm, offset *
5276 shader->selector->gs_max_out_vertices);
5277 offset++;
5278
5279 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5280 voffset = lp_build_mul_imm(uint, voffset, 4);
5281
5282 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5283
5284 ac_build_buffer_store_dword(&ctx->ac,
5285 ctx->gsvs_ring[stream],
5286 out_val, 1,
5287 voffset, soffset, 0,
5288 1, 1, true, true);
5289 }
5290 }
5291
5292 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5293 lp_build_const_int32(gallivm, 1));
5294
5295 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5296
5297 /* Signal vertex emission */
5298 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
5299 LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID));
5300 if (!use_kill)
5301 lp_build_endif(&if_state);
5302 }
5303
5304 /* Cut one primitive from the geometry shader */
5305 static void si_llvm_emit_primitive(
5306 const struct lp_build_tgsi_action *action,
5307 struct lp_build_tgsi_context *bld_base,
5308 struct lp_build_emit_data *emit_data)
5309 {
5310 struct si_shader_context *ctx = si_shader_context(bld_base);
5311 unsigned stream;
5312
5313 /* Signal primitive cut */
5314 stream = si_llvm_get_stream(bld_base, emit_data);
5315 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
5316 LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID));
5317 }
5318
5319 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5320 struct lp_build_tgsi_context *bld_base,
5321 struct lp_build_emit_data *emit_data)
5322 {
5323 struct si_shader_context *ctx = si_shader_context(bld_base);
5324 struct gallivm_state *gallivm = bld_base->base.gallivm;
5325
5326 /* SI only (thanks to a hw bug workaround):
5327 * The real barrier instruction isn’t needed, because an entire patch
5328 * always fits into a single wave.
5329 */
5330 if (HAVE_LLVM >= 0x0309 &&
5331 ctx->screen->b.chip_class == SI &&
5332 ctx->type == PIPE_SHADER_TESS_CTRL) {
5333 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
5334 return;
5335 }
5336
5337 lp_build_intrinsic(gallivm->builder,
5338 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5339 : "llvm.AMDGPU.barrier.local",
5340 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
5341 }
5342
5343 static const struct lp_build_tgsi_action tex_action = {
5344 .fetch_args = tex_fetch_args,
5345 .emit = build_tex_intrinsic,
5346 };
5347
5348 static const struct lp_build_tgsi_action interp_action = {
5349 .fetch_args = interp_fetch_args,
5350 .emit = build_interp_intrinsic,
5351 };
5352
5353 static void si_create_function(struct si_shader_context *ctx,
5354 const char *name,
5355 LLVMTypeRef *returns, unsigned num_returns,
5356 LLVMTypeRef *params, unsigned num_params,
5357 int last_sgpr)
5358 {
5359 int i;
5360
5361 si_llvm_create_func(ctx, name, returns, num_returns,
5362 params, num_params);
5363 si_llvm_shader_type(ctx->main_fn, ctx->type);
5364 ctx->return_value = LLVMGetUndef(ctx->return_type);
5365
5366 for (i = 0; i <= last_sgpr; ++i) {
5367 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
5368
5369 /* The combination of:
5370 * - ByVal
5371 * - dereferenceable
5372 * - invariant.load
5373 * allows the optimization passes to move loads and reduces
5374 * SGPR spilling significantly.
5375 */
5376 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
5377 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
5378 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
5379 ac_add_attr_dereferenceable(P, UINT64_MAX);
5380 } else
5381 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
5382 }
5383
5384 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5385 "no-signed-zeros-fp-math",
5386 "true");
5387
5388 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5389 /* These were copied from some LLVM test. */
5390 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5391 "less-precise-fpmad",
5392 "true");
5393 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5394 "no-infs-fp-math",
5395 "true");
5396 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5397 "no-nans-fp-math",
5398 "true");
5399 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5400 "unsafe-fp-math",
5401 "true");
5402 }
5403 }
5404
5405 static void declare_streamout_params(struct si_shader_context *ctx,
5406 struct pipe_stream_output_info *so,
5407 LLVMTypeRef *params, LLVMTypeRef i32,
5408 unsigned *num_params)
5409 {
5410 int i;
5411
5412 /* Streamout SGPRs. */
5413 if (so->num_outputs) {
5414 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5415 params[ctx->param_streamout_config = (*num_params)++] = i32;
5416 else
5417 ctx->param_streamout_config = *num_params - 1;
5418
5419 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5420 }
5421 /* A streamout buffer offset is loaded if the stride is non-zero. */
5422 for (i = 0; i < 4; i++) {
5423 if (!so->stride[i])
5424 continue;
5425
5426 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5427 }
5428 }
5429
5430 static unsigned llvm_get_type_size(LLVMTypeRef type)
5431 {
5432 LLVMTypeKind kind = LLVMGetTypeKind(type);
5433
5434 switch (kind) {
5435 case LLVMIntegerTypeKind:
5436 return LLVMGetIntTypeWidth(type) / 8;
5437 case LLVMFloatTypeKind:
5438 return 4;
5439 case LLVMPointerTypeKind:
5440 return 8;
5441 case LLVMVectorTypeKind:
5442 return LLVMGetVectorSize(type) *
5443 llvm_get_type_size(LLVMGetElementType(type));
5444 case LLVMArrayTypeKind:
5445 return LLVMGetArrayLength(type) *
5446 llvm_get_type_size(LLVMGetElementType(type));
5447 default:
5448 assert(0);
5449 return 0;
5450 }
5451 }
5452
5453 static void declare_tess_lds(struct si_shader_context *ctx)
5454 {
5455 struct gallivm_state *gallivm = &ctx->gallivm;
5456 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5457 struct lp_build_context *uint = &bld_base->uint_bld;
5458
5459 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5460 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, uint->zero,
5461 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
5462 "tess_lds");
5463 }
5464
5465 static unsigned si_get_max_workgroup_size(struct si_shader *shader)
5466 {
5467 const unsigned *properties = shader->selector->info.properties;
5468 unsigned max_work_group_size =
5469 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5470 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5471 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5472
5473 if (!max_work_group_size) {
5474 /* This is a variable group size compute shader,
5475 * compile it for the maximum possible group size.
5476 */
5477 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
5478 }
5479 return max_work_group_size;
5480 }
5481
5482 static void create_function(struct si_shader_context *ctx)
5483 {
5484 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5485 struct gallivm_state *gallivm = bld_base->base.gallivm;
5486 struct si_shader *shader = ctx->shader;
5487 LLVMTypeRef params[SI_NUM_PARAMS + SI_MAX_ATTRIBS], v3i32;
5488 LLVMTypeRef returns[16+32*4];
5489 unsigned i, last_sgpr, num_params, num_return_sgprs;
5490 unsigned num_returns = 0;
5491 unsigned num_prolog_vgprs = 0;
5492
5493 v3i32 = LLVMVectorType(ctx->i32, 3);
5494
5495 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5496 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5497 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5498 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5499 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5500
5501 switch (ctx->type) {
5502 case PIPE_SHADER_VERTEX:
5503 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_MAX_ATTRIBS);
5504 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5505 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5506 params[SI_PARAM_DRAWID] = ctx->i32;
5507 num_params = SI_PARAM_DRAWID+1;
5508
5509 if (shader->key.as_es) {
5510 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5511 } else if (shader->key.as_ls) {
5512 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
5513 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
5514 } else {
5515 if (shader->is_gs_copy_shader) {
5516 num_params = SI_PARAM_RW_BUFFERS+1;
5517 } else {
5518 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5519 num_params = SI_PARAM_VS_STATE_BITS+1;
5520 }
5521
5522 /* The locations of the other parameters are assigned dynamically. */
5523 declare_streamout_params(ctx, &shader->selector->so,
5524 params, ctx->i32, &num_params);
5525 }
5526
5527 last_sgpr = num_params-1;
5528
5529 /* VGPRs */
5530 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5531 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5532 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5533 params[ctx->param_instance_id = num_params++] = ctx->i32;
5534
5535 if (!shader->is_gs_copy_shader) {
5536 /* Vertex load indices. */
5537 ctx->param_vertex_index0 = num_params;
5538
5539 for (i = 0; i < shader->selector->info.num_inputs; i++)
5540 params[num_params++] = ctx->i32;
5541
5542 num_prolog_vgprs += shader->selector->info.num_inputs;
5543
5544 /* PrimitiveID output. */
5545 if (!shader->key.as_es && !shader->key.as_ls)
5546 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5547 returns[num_returns++] = ctx->f32;
5548 }
5549 break;
5550
5551 case PIPE_SHADER_TESS_CTRL:
5552 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5553 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5554 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5555 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5556 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5557 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5558 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5559
5560 /* VGPRs */
5561 params[SI_PARAM_PATCH_ID] = ctx->i32;
5562 params[SI_PARAM_REL_IDS] = ctx->i32;
5563 num_params = SI_PARAM_REL_IDS+1;
5564
5565 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5566 * placed after the user SGPRs.
5567 */
5568 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5569 returns[num_returns++] = ctx->i32; /* SGPRs */
5570
5571 for (i = 0; i < 3; i++)
5572 returns[num_returns++] = ctx->f32; /* VGPRs */
5573 break;
5574
5575 case PIPE_SHADER_TESS_EVAL:
5576 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5577 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5578
5579 if (shader->key.as_es) {
5580 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5581 params[num_params++] = ctx->i32;
5582 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5583 } else {
5584 params[num_params++] = ctx->i32;
5585 declare_streamout_params(ctx, &shader->selector->so,
5586 params, ctx->i32, &num_params);
5587 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5588 }
5589 last_sgpr = num_params - 1;
5590
5591 /* VGPRs */
5592 params[ctx->param_tes_u = num_params++] = ctx->f32;
5593 params[ctx->param_tes_v = num_params++] = ctx->f32;
5594 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5595 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5596
5597 /* PrimitiveID output. */
5598 if (!shader->key.as_es)
5599 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5600 returns[num_returns++] = ctx->f32;
5601 break;
5602
5603 case PIPE_SHADER_GEOMETRY:
5604 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5605 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5606 last_sgpr = SI_PARAM_GS_WAVE_ID;
5607
5608 /* VGPRs */
5609 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5610 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5611 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5612 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5613 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5614 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5615 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5616 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5617 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5618 break;
5619
5620 case PIPE_SHADER_FRAGMENT:
5621 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5622 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5623 last_sgpr = SI_PARAM_PRIM_MASK;
5624 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5625 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5626 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5627 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5628 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5629 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5630 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5631 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5632 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5633 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5634 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5635 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5636 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5637 shader->info.face_vgpr_index = 20;
5638 params[SI_PARAM_ANCILLARY] = ctx->i32;
5639 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5640 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5641 num_params = SI_PARAM_POS_FIXED_PT+1;
5642
5643 /* Color inputs from the prolog. */
5644 if (shader->selector->info.colors_read) {
5645 unsigned num_color_elements =
5646 util_bitcount(shader->selector->info.colors_read);
5647
5648 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5649 for (i = 0; i < num_color_elements; i++)
5650 params[num_params++] = ctx->f32;
5651
5652 num_prolog_vgprs += num_color_elements;
5653 }
5654
5655 /* Outputs for the epilog. */
5656 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5657 num_returns =
5658 num_return_sgprs +
5659 util_bitcount(shader->selector->info.colors_written) * 4 +
5660 shader->selector->info.writes_z +
5661 shader->selector->info.writes_stencil +
5662 shader->selector->info.writes_samplemask +
5663 1 /* SampleMaskIn */;
5664
5665 num_returns = MAX2(num_returns,
5666 num_return_sgprs +
5667 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5668
5669 for (i = 0; i < num_return_sgprs; i++)
5670 returns[i] = ctx->i32;
5671 for (; i < num_returns; i++)
5672 returns[i] = ctx->f32;
5673 break;
5674
5675 case PIPE_SHADER_COMPUTE:
5676 params[SI_PARAM_GRID_SIZE] = v3i32;
5677 params[SI_PARAM_BLOCK_SIZE] = v3i32;
5678 params[SI_PARAM_BLOCK_ID] = v3i32;
5679 last_sgpr = SI_PARAM_BLOCK_ID;
5680
5681 params[SI_PARAM_THREAD_ID] = v3i32;
5682 num_params = SI_PARAM_THREAD_ID + 1;
5683 break;
5684 default:
5685 assert(0 && "unimplemented shader");
5686 return;
5687 }
5688
5689 assert(num_params <= ARRAY_SIZE(params));
5690
5691 si_create_function(ctx, "main", returns, num_returns, params,
5692 num_params, last_sgpr);
5693
5694 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5695 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5696 ctx->separate_prolog) {
5697 si_llvm_add_attribute(ctx->main_fn,
5698 "InitialPSInputAddr",
5699 S_0286D0_PERSP_SAMPLE_ENA(1) |
5700 S_0286D0_PERSP_CENTER_ENA(1) |
5701 S_0286D0_PERSP_CENTROID_ENA(1) |
5702 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5703 S_0286D0_LINEAR_CENTER_ENA(1) |
5704 S_0286D0_LINEAR_CENTROID_ENA(1) |
5705 S_0286D0_FRONT_FACE_ENA(1) |
5706 S_0286D0_POS_FIXED_PT_ENA(1));
5707 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5708 si_llvm_add_attribute(ctx->main_fn,
5709 "amdgpu-max-work-group-size",
5710 si_get_max_workgroup_size(shader));
5711 }
5712
5713 shader->info.num_input_sgprs = 0;
5714 shader->info.num_input_vgprs = 0;
5715
5716 for (i = 0; i <= last_sgpr; ++i)
5717 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5718
5719 for (; i < num_params; ++i)
5720 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5721
5722 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5723 shader->info.num_input_vgprs -= num_prolog_vgprs;
5724
5725 if (!ctx->screen->has_ds_bpermute &&
5726 bld_base->info &&
5727 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5728 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5729 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5730 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5731 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5732 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5733 ctx->lds =
5734 LLVMAddGlobalInAddressSpace(gallivm->module,
5735 LLVMArrayType(ctx->i32, 64),
5736 "ddxy_lds",
5737 LOCAL_ADDR_SPACE);
5738
5739 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.as_ls) ||
5740 ctx->type == PIPE_SHADER_TESS_CTRL)
5741 declare_tess_lds(ctx);
5742 }
5743
5744 /**
5745 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5746 * for later use.
5747 */
5748 static void preload_ring_buffers(struct si_shader_context *ctx)
5749 {
5750 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
5751 LLVMBuilderRef builder = gallivm->builder;
5752
5753 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5754 SI_PARAM_RW_BUFFERS);
5755
5756 if ((ctx->type == PIPE_SHADER_VERTEX &&
5757 ctx->shader->key.as_es) ||
5758 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5759 ctx->shader->key.as_es) ||
5760 ctx->type == PIPE_SHADER_GEOMETRY) {
5761 unsigned ring =
5762 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5763 : SI_ES_RING_ESGS;
5764 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5765
5766 ctx->esgs_ring =
5767 ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
5768 }
5769
5770 if (ctx->shader->is_gs_copy_shader) {
5771 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
5772
5773 ctx->gsvs_ring[0] =
5774 ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
5775 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5776 const struct si_shader_selector *sel = ctx->shader->selector;
5777 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
5778 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
5779 LLVMValueRef base_ring;
5780
5781 base_ring = ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
5782
5783 /* The conceptual layout of the GSVS ring is
5784 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5785 * but the real memory layout is swizzled across
5786 * threads:
5787 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5788 * t16v0c0 ..
5789 * Override the buffer descriptor accordingly.
5790 */
5791 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5792 uint64_t stream_offset = 0;
5793
5794 for (unsigned stream = 0; stream < 4; ++stream) {
5795 unsigned num_components;
5796 unsigned stride;
5797 unsigned num_records;
5798 LLVMValueRef ring, tmp;
5799
5800 num_components = sel->info.num_stream_output_components[stream];
5801 if (!num_components)
5802 continue;
5803
5804 stride = 4 * num_components * sel->gs_max_out_vertices;
5805
5806 /* Limit on the stride field for <= CIK. */
5807 assert(stride < (1 << 14));
5808
5809 num_records = 64;
5810
5811 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5812 tmp = LLVMBuildExtractElement(builder, ring, uint->zero, "");
5813 tmp = LLVMBuildAdd(builder, tmp,
5814 LLVMConstInt(ctx->i64,
5815 stream_offset, 0), "");
5816 stream_offset += stride * 64;
5817
5818 ring = LLVMBuildInsertElement(builder, ring, tmp, uint->zero, "");
5819 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5820 tmp = LLVMBuildExtractElement(builder, ring, uint->one, "");
5821 tmp = LLVMBuildOr(builder, tmp,
5822 LLVMConstInt(ctx->i32,
5823 S_008F04_STRIDE(stride) |
5824 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5825 ring = LLVMBuildInsertElement(builder, ring, tmp, uint->one, "");
5826 ring = LLVMBuildInsertElement(builder, ring,
5827 LLVMConstInt(ctx->i32, num_records, 0),
5828 LLVMConstInt(ctx->i32, 2, 0), "");
5829 ring = LLVMBuildInsertElement(builder, ring,
5830 LLVMConstInt(ctx->i32,
5831 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5832 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5833 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5834 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5835 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5836 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5837 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5838 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5839 S_008F0C_ADD_TID_ENABLE(1),
5840 0),
5841 LLVMConstInt(ctx->i32, 3, 0), "");
5842 ring = LLVMBuildBitCast(builder, ring, ctx->v16i8, "");
5843
5844 ctx->gsvs_ring[stream] = ring;
5845 }
5846 }
5847 }
5848
5849 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5850 LLVMValueRef param_rw_buffers,
5851 unsigned param_pos_fixed_pt)
5852 {
5853 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5854 struct gallivm_state *gallivm = bld_base->base.gallivm;
5855 LLVMBuilderRef builder = gallivm->builder;
5856 LLVMValueRef slot, desc, offset, row, bit, address[2];
5857
5858 /* Use the fixed-point gl_FragCoord input.
5859 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5860 * per coordinate to get the repeating effect.
5861 */
5862 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5863 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5864
5865 /* Load the buffer descriptor. */
5866 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
5867 desc = ac_build_indexed_load_const(&ctx->ac, param_rw_buffers, slot);
5868
5869 /* The stipple pattern is 32x32, each row has 32 bits. */
5870 offset = LLVMBuildMul(builder, address[1],
5871 LLVMConstInt(ctx->i32, 4, 0), "");
5872 row = buffer_load_const(ctx, desc, offset);
5873 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
5874 bit = LLVMBuildLShr(builder, row, address[0], "");
5875 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5876
5877 /* The intrinsic kills the thread if arg < 0. */
5878 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
5879 LLVMConstReal(ctx->f32, -1), "");
5880 ac_build_kill(&ctx->ac, bit);
5881 }
5882
5883 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5884 struct si_shader_config *conf,
5885 unsigned symbol_offset)
5886 {
5887 unsigned i;
5888 const unsigned char *config =
5889 ac_shader_binary_config_start(binary, symbol_offset);
5890 bool really_needs_scratch = false;
5891
5892 /* LLVM adds SGPR spills to the scratch size.
5893 * Find out if we really need the scratch buffer.
5894 */
5895 for (i = 0; i < binary->reloc_count; i++) {
5896 const struct ac_shader_reloc *reloc = &binary->relocs[i];
5897
5898 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5899 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5900 really_needs_scratch = true;
5901 break;
5902 }
5903 }
5904
5905 /* XXX: We may be able to emit some of these values directly rather than
5906 * extracting fields to be emitted later.
5907 */
5908
5909 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5910 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5911 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5912 switch (reg) {
5913 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5914 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5915 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5916 case R_00B848_COMPUTE_PGM_RSRC1:
5917 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5918 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5919 conf->float_mode = G_00B028_FLOAT_MODE(value);
5920 conf->rsrc1 = value;
5921 break;
5922 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5923 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5924 break;
5925 case R_00B84C_COMPUTE_PGM_RSRC2:
5926 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5927 conf->rsrc2 = value;
5928 break;
5929 case R_0286CC_SPI_PS_INPUT_ENA:
5930 conf->spi_ps_input_ena = value;
5931 break;
5932 case R_0286D0_SPI_PS_INPUT_ADDR:
5933 conf->spi_ps_input_addr = value;
5934 break;
5935 case R_0286E8_SPI_TMPRING_SIZE:
5936 case R_00B860_COMPUTE_TMPRING_SIZE:
5937 /* WAVESIZE is in units of 256 dwords. */
5938 if (really_needs_scratch)
5939 conf->scratch_bytes_per_wave =
5940 G_00B860_WAVESIZE(value) * 256 * 4;
5941 break;
5942 case 0x4: /* SPILLED_SGPRS */
5943 conf->spilled_sgprs = value;
5944 break;
5945 case 0x8: /* SPILLED_VGPRS */
5946 conf->spilled_vgprs = value;
5947 break;
5948 default:
5949 {
5950 static bool printed;
5951
5952 if (!printed) {
5953 fprintf(stderr, "Warning: LLVM emitted unknown "
5954 "config register: 0x%x\n", reg);
5955 printed = true;
5956 }
5957 }
5958 break;
5959 }
5960 }
5961
5962 if (!conf->spi_ps_input_addr)
5963 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5964 }
5965
5966 void si_shader_apply_scratch_relocs(struct si_context *sctx,
5967 struct si_shader *shader,
5968 struct si_shader_config *config,
5969 uint64_t scratch_va)
5970 {
5971 unsigned i;
5972 uint32_t scratch_rsrc_dword0 = scratch_va;
5973 uint32_t scratch_rsrc_dword1 =
5974 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5975
5976 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
5977 * correctly.
5978 */
5979 if (HAVE_LLVM >= 0x0309)
5980 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5981 else
5982 scratch_rsrc_dword1 |=
5983 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
5984
5985 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5986 const struct ac_shader_reloc *reloc =
5987 &shader->binary.relocs[i];
5988 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5989 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5990 &scratch_rsrc_dword0, 4);
5991 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5992 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5993 &scratch_rsrc_dword1, 4);
5994 }
5995 }
5996 }
5997
5998 static unsigned si_get_shader_binary_size(struct si_shader *shader)
5999 {
6000 unsigned size = shader->binary.code_size;
6001
6002 if (shader->prolog)
6003 size += shader->prolog->binary.code_size;
6004 if (shader->epilog)
6005 size += shader->epilog->binary.code_size;
6006 return size;
6007 }
6008
6009 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
6010 {
6011 const struct ac_shader_binary *prolog =
6012 shader->prolog ? &shader->prolog->binary : NULL;
6013 const struct ac_shader_binary *epilog =
6014 shader->epilog ? &shader->epilog->binary : NULL;
6015 const struct ac_shader_binary *mainb = &shader->binary;
6016 unsigned bo_size = si_get_shader_binary_size(shader) +
6017 (!epilog ? mainb->rodata_size : 0);
6018 unsigned char *ptr;
6019
6020 assert(!prolog || !prolog->rodata_size);
6021 assert((!prolog && !epilog) || !mainb->rodata_size);
6022 assert(!epilog || !epilog->rodata_size);
6023
6024 /* GFX9 can fetch at most 128 bytes past the end of the shader.
6025 * Prevent VM faults.
6026 */
6027 if (sscreen->b.chip_class >= GFX9)
6028 bo_size += 128;
6029
6030 r600_resource_reference(&shader->bo, NULL);
6031 shader->bo = (struct r600_resource*)
6032 pipe_buffer_create(&sscreen->b.b, 0,
6033 PIPE_USAGE_IMMUTABLE,
6034 align(bo_size, SI_CPDMA_ALIGNMENT));
6035 if (!shader->bo)
6036 return -ENOMEM;
6037
6038 /* Upload. */
6039 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
6040 PIPE_TRANSFER_READ_WRITE);
6041
6042 if (prolog) {
6043 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
6044 ptr += prolog->code_size;
6045 }
6046
6047 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
6048 ptr += mainb->code_size;
6049
6050 if (epilog)
6051 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
6052 else if (mainb->rodata_size > 0)
6053 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
6054
6055 sscreen->b.ws->buffer_unmap(shader->bo->buf);
6056 return 0;
6057 }
6058
6059 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
6060 struct pipe_debug_callback *debug,
6061 const char *name, FILE *file)
6062 {
6063 char *line, *p;
6064 unsigned i, count;
6065
6066 if (binary->disasm_string) {
6067 fprintf(file, "Shader %s disassembly:\n", name);
6068 fprintf(file, "%s", binary->disasm_string);
6069
6070 if (debug && debug->debug_message) {
6071 /* Very long debug messages are cut off, so send the
6072 * disassembly one line at a time. This causes more
6073 * overhead, but on the plus side it simplifies
6074 * parsing of resulting logs.
6075 */
6076 pipe_debug_message(debug, SHADER_INFO,
6077 "Shader Disassembly Begin");
6078
6079 line = binary->disasm_string;
6080 while (*line) {
6081 p = util_strchrnul(line, '\n');
6082 count = p - line;
6083
6084 if (count) {
6085 pipe_debug_message(debug, SHADER_INFO,
6086 "%.*s", count, line);
6087 }
6088
6089 if (!*p)
6090 break;
6091 line = p + 1;
6092 }
6093
6094 pipe_debug_message(debug, SHADER_INFO,
6095 "Shader Disassembly End");
6096 }
6097 } else {
6098 fprintf(file, "Shader %s binary:\n", name);
6099 for (i = 0; i < binary->code_size; i += 4) {
6100 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
6101 binary->code[i + 3], binary->code[i + 2],
6102 binary->code[i + 1], binary->code[i]);
6103 }
6104 }
6105 }
6106
6107 static void si_shader_dump_stats(struct si_screen *sscreen,
6108 struct si_shader *shader,
6109 struct pipe_debug_callback *debug,
6110 unsigned processor,
6111 FILE *file,
6112 bool check_debug_option)
6113 {
6114 struct si_shader_config *conf = &shader->config;
6115 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
6116 unsigned code_size = si_get_shader_binary_size(shader);
6117 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
6118 unsigned lds_per_wave = 0;
6119 unsigned max_simd_waves = 10;
6120
6121 /* Compute LDS usage for PS. */
6122 switch (processor) {
6123 case PIPE_SHADER_FRAGMENT:
6124 /* The minimum usage per wave is (num_inputs * 48). The maximum
6125 * usage is (num_inputs * 48 * 16).
6126 * We can get anything in between and it varies between waves.
6127 *
6128 * The 48 bytes per input for a single primitive is equal to
6129 * 4 bytes/component * 4 components/input * 3 points.
6130 *
6131 * Other stages don't know the size at compile time or don't
6132 * allocate LDS per wave, but instead they do it per thread group.
6133 */
6134 lds_per_wave = conf->lds_size * lds_increment +
6135 align(num_inputs * 48, lds_increment);
6136 break;
6137 case PIPE_SHADER_COMPUTE:
6138 if (shader->selector) {
6139 unsigned max_workgroup_size =
6140 si_get_max_workgroup_size(shader);
6141 lds_per_wave = (conf->lds_size * lds_increment) /
6142 DIV_ROUND_UP(max_workgroup_size, 64);
6143 }
6144 break;
6145 }
6146
6147 /* Compute the per-SIMD wave counts. */
6148 if (conf->num_sgprs) {
6149 if (sscreen->b.chip_class >= VI)
6150 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
6151 else
6152 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
6153 }
6154
6155 if (conf->num_vgprs)
6156 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
6157
6158 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
6159 * 16KB makes some SIMDs unoccupied). */
6160 if (lds_per_wave)
6161 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
6162
6163 if (!check_debug_option ||
6164 r600_can_dump_shader(&sscreen->b, processor)) {
6165 if (processor == PIPE_SHADER_FRAGMENT) {
6166 fprintf(file, "*** SHADER CONFIG ***\n"
6167 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6168 "SPI_PS_INPUT_ENA = 0x%04x\n",
6169 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
6170 }
6171
6172 fprintf(file, "*** SHADER STATS ***\n"
6173 "SGPRS: %d\n"
6174 "VGPRS: %d\n"
6175 "Spilled SGPRs: %d\n"
6176 "Spilled VGPRs: %d\n"
6177 "Private memory VGPRs: %d\n"
6178 "Code Size: %d bytes\n"
6179 "LDS: %d blocks\n"
6180 "Scratch: %d bytes per wave\n"
6181 "Max Waves: %d\n"
6182 "********************\n\n\n",
6183 conf->num_sgprs, conf->num_vgprs,
6184 conf->spilled_sgprs, conf->spilled_vgprs,
6185 conf->private_mem_vgprs, code_size,
6186 conf->lds_size, conf->scratch_bytes_per_wave,
6187 max_simd_waves);
6188 }
6189
6190 pipe_debug_message(debug, SHADER_INFO,
6191 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6192 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
6193 "Spilled VGPRs: %d PrivMem VGPRs: %d",
6194 conf->num_sgprs, conf->num_vgprs, code_size,
6195 conf->lds_size, conf->scratch_bytes_per_wave,
6196 max_simd_waves, conf->spilled_sgprs,
6197 conf->spilled_vgprs, conf->private_mem_vgprs);
6198 }
6199
6200 const char *si_get_shader_name(struct si_shader *shader, unsigned processor)
6201 {
6202 switch (processor) {
6203 case PIPE_SHADER_VERTEX:
6204 if (shader->key.as_es)
6205 return "Vertex Shader as ES";
6206 else if (shader->key.as_ls)
6207 return "Vertex Shader as LS";
6208 else
6209 return "Vertex Shader as VS";
6210 case PIPE_SHADER_TESS_CTRL:
6211 return "Tessellation Control Shader";
6212 case PIPE_SHADER_TESS_EVAL:
6213 if (shader->key.as_es)
6214 return "Tessellation Evaluation Shader as ES";
6215 else
6216 return "Tessellation Evaluation Shader as VS";
6217 case PIPE_SHADER_GEOMETRY:
6218 if (shader->is_gs_copy_shader)
6219 return "GS Copy Shader as VS";
6220 else
6221 return "Geometry Shader";
6222 case PIPE_SHADER_FRAGMENT:
6223 return "Pixel Shader";
6224 case PIPE_SHADER_COMPUTE:
6225 return "Compute Shader";
6226 default:
6227 return "Unknown Shader";
6228 }
6229 }
6230
6231 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6232 struct pipe_debug_callback *debug, unsigned processor,
6233 FILE *file, bool check_debug_option)
6234 {
6235 if (!check_debug_option ||
6236 r600_can_dump_shader(&sscreen->b, processor))
6237 si_dump_shader_key(processor, &shader->key, file);
6238
6239 if (!check_debug_option && shader->binary.llvm_ir_string) {
6240 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
6241 si_get_shader_name(shader, processor));
6242 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
6243 }
6244
6245 if (!check_debug_option ||
6246 (r600_can_dump_shader(&sscreen->b, processor) &&
6247 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6248 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6249
6250 if (shader->prolog)
6251 si_shader_dump_disassembly(&shader->prolog->binary,
6252 debug, "prolog", file);
6253
6254 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6255
6256 if (shader->epilog)
6257 si_shader_dump_disassembly(&shader->epilog->binary,
6258 debug, "epilog", file);
6259 fprintf(file, "\n");
6260 }
6261
6262 si_shader_dump_stats(sscreen, shader, debug, processor, file,
6263 check_debug_option);
6264 }
6265
6266 int si_compile_llvm(struct si_screen *sscreen,
6267 struct ac_shader_binary *binary,
6268 struct si_shader_config *conf,
6269 LLVMTargetMachineRef tm,
6270 LLVMModuleRef mod,
6271 struct pipe_debug_callback *debug,
6272 unsigned processor,
6273 const char *name)
6274 {
6275 int r = 0;
6276 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6277
6278 if (r600_can_dump_shader(&sscreen->b, processor)) {
6279 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6280
6281 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6282 fprintf(stderr, "%s LLVM IR:\n\n", name);
6283 ac_dump_module(mod);
6284 fprintf(stderr, "\n");
6285 }
6286 }
6287
6288 if (sscreen->record_llvm_ir) {
6289 char *ir = LLVMPrintModuleToString(mod);
6290 binary->llvm_ir_string = strdup(ir);
6291 LLVMDisposeMessage(ir);
6292 }
6293
6294 if (!si_replace_shader(count, binary)) {
6295 r = si_llvm_compile(mod, binary, tm, debug);
6296 if (r)
6297 return r;
6298 }
6299
6300 si_shader_binary_read_config(binary, conf, 0);
6301
6302 /* Enable 64-bit and 16-bit denormals, because there is no performance
6303 * cost.
6304 *
6305 * If denormals are enabled, all floating-point output modifiers are
6306 * ignored.
6307 *
6308 * Don't enable denormals for 32-bit floats, because:
6309 * - Floating-point output modifiers would be ignored by the hw.
6310 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6311 * have to stop using those.
6312 * - SI & CI would be very slow.
6313 */
6314 conf->float_mode |= V_00B028_FP_64_DENORMS;
6315
6316 FREE(binary->config);
6317 FREE(binary->global_symbol_offsets);
6318 binary->config = NULL;
6319 binary->global_symbol_offsets = NULL;
6320
6321 /* Some shaders can't have rodata because their binaries can be
6322 * concatenated.
6323 */
6324 if (binary->rodata_size &&
6325 (processor == PIPE_SHADER_VERTEX ||
6326 processor == PIPE_SHADER_TESS_CTRL ||
6327 processor == PIPE_SHADER_TESS_EVAL ||
6328 processor == PIPE_SHADER_FRAGMENT)) {
6329 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6330 return -EINVAL;
6331 }
6332
6333 return r;
6334 }
6335
6336 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6337 {
6338 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6339 LLVMBuildRetVoid(ctx->gallivm.builder);
6340 else
6341 LLVMBuildRet(ctx->gallivm.builder, ret);
6342 }
6343
6344 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6345 struct si_shader *
6346 si_generate_gs_copy_shader(struct si_screen *sscreen,
6347 LLVMTargetMachineRef tm,
6348 struct si_shader_selector *gs_selector,
6349 struct pipe_debug_callback *debug)
6350 {
6351 struct si_shader_context ctx;
6352 struct si_shader *shader;
6353 struct gallivm_state *gallivm = &ctx.gallivm;
6354 LLVMBuilderRef builder;
6355 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
6356 struct lp_build_context *uint = &bld_base->uint_bld;
6357 struct si_shader_output_values *outputs;
6358 struct tgsi_shader_info *gsinfo = &gs_selector->info;
6359 int i, r;
6360
6361 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6362
6363 if (!outputs)
6364 return NULL;
6365
6366 shader = CALLOC_STRUCT(si_shader);
6367 if (!shader) {
6368 FREE(outputs);
6369 return NULL;
6370 }
6371
6372
6373 shader->selector = gs_selector;
6374 shader->is_gs_copy_shader = true;
6375
6376 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6377 ctx.type = PIPE_SHADER_VERTEX;
6378
6379 builder = gallivm->builder;
6380
6381 create_function(&ctx);
6382 preload_ring_buffers(&ctx);
6383
6384 LLVMValueRef voffset =
6385 lp_build_mul_imm(uint, LLVMGetParam(ctx.main_fn,
6386 ctx.param_vertex_id), 4);
6387
6388 /* Fetch the vertex stream ID.*/
6389 LLVMValueRef stream_id;
6390
6391 if (gs_selector->so.num_outputs)
6392 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
6393 else
6394 stream_id = uint->zero;
6395
6396 /* Fill in output information. */
6397 for (i = 0; i < gsinfo->num_outputs; ++i) {
6398 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
6399 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
6400
6401 for (int chan = 0; chan < 4; chan++) {
6402 outputs[i].vertex_stream[chan] =
6403 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
6404 }
6405 }
6406
6407 LLVMBasicBlockRef end_bb;
6408 LLVMValueRef switch_inst;
6409
6410 end_bb = LLVMAppendBasicBlockInContext(gallivm->context, ctx.main_fn, "end");
6411 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
6412
6413 for (int stream = 0; stream < 4; stream++) {
6414 LLVMBasicBlockRef bb;
6415 unsigned offset;
6416
6417 if (!gsinfo->num_stream_output_components[stream])
6418 continue;
6419
6420 if (stream > 0 && !gs_selector->so.num_outputs)
6421 continue;
6422
6423 bb = LLVMInsertBasicBlockInContext(gallivm->context, end_bb, "out");
6424 LLVMAddCase(switch_inst, lp_build_const_int32(gallivm, stream), bb);
6425 LLVMPositionBuilderAtEnd(builder, bb);
6426
6427 /* Fetch vertex data from GSVS ring */
6428 offset = 0;
6429 for (i = 0; i < gsinfo->num_outputs; ++i) {
6430 for (unsigned chan = 0; chan < 4; chan++) {
6431 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
6432 outputs[i].vertex_stream[chan] != stream) {
6433 outputs[i].values[chan] = ctx.bld_base.base.undef;
6434 continue;
6435 }
6436
6437 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
6438 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
6439 offset++;
6440
6441 outputs[i].values[chan] =
6442 ac_build_buffer_load(&ctx.ac,
6443 ctx.gsvs_ring[0], 1,
6444 uint->zero, voffset,
6445 soffset, 0, 1, 1, true);
6446 }
6447 }
6448
6449 /* Streamout and exports. */
6450 if (gs_selector->so.num_outputs) {
6451 si_llvm_emit_streamout(&ctx, outputs,
6452 gsinfo->num_outputs,
6453 stream);
6454 }
6455
6456 if (stream == 0)
6457 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6458
6459 LLVMBuildBr(builder, end_bb);
6460 }
6461
6462 LLVMPositionBuilderAtEnd(builder, end_bb);
6463
6464 LLVMBuildRetVoid(gallivm->builder);
6465
6466 /* Dump LLVM IR before any optimization passes */
6467 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6468 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6469 ac_dump_module(bld_base->base.gallivm->module);
6470
6471 si_llvm_finalize_module(&ctx,
6472 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_GEOMETRY));
6473
6474 r = si_compile_llvm(sscreen, &ctx.shader->binary,
6475 &ctx.shader->config, ctx.tm,
6476 bld_base->base.gallivm->module,
6477 debug, PIPE_SHADER_GEOMETRY,
6478 "GS Copy Shader");
6479 if (!r) {
6480 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6481 fprintf(stderr, "GS Copy Shader:\n");
6482 si_shader_dump(sscreen, ctx.shader, debug,
6483 PIPE_SHADER_GEOMETRY, stderr, true);
6484 r = si_shader_binary_upload(sscreen, ctx.shader);
6485 }
6486
6487 si_llvm_dispose(&ctx);
6488
6489 FREE(outputs);
6490
6491 if (r != 0) {
6492 FREE(shader);
6493 shader = NULL;
6494 }
6495 return shader;
6496 }
6497
6498 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
6499 FILE *f)
6500 {
6501 int i;
6502
6503 fprintf(f, "SHADER KEY\n");
6504
6505 switch (shader) {
6506 case PIPE_SHADER_VERTEX:
6507 fprintf(f, " part.vs.prolog.instance_divisors = {");
6508 for (i = 0; i < ARRAY_SIZE(key->part.vs.prolog.instance_divisors); i++)
6509 fprintf(f, !i ? "%u" : ", %u",
6510 key->part.vs.prolog.instance_divisors[i]);
6511 fprintf(f, "}\n");
6512 fprintf(f, " part.vs.epilog.export_prim_id = %u\n", key->part.vs.epilog.export_prim_id);
6513 fprintf(f, " as_es = %u\n", key->as_es);
6514 fprintf(f, " as_ls = %u\n", key->as_ls);
6515
6516 fprintf(f, " mono.vs.fix_fetch = {");
6517 for (i = 0; i < SI_MAX_ATTRIBS; i++)
6518 fprintf(f, !i ? "%u" : ", %u", key->mono.vs.fix_fetch[i]);
6519 fprintf(f, "}\n");
6520 break;
6521
6522 case PIPE_SHADER_TESS_CTRL:
6523 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
6524 fprintf(f, " mono.tcs.inputs_to_copy = 0x%"PRIx64"\n", key->mono.tcs.inputs_to_copy);
6525 break;
6526
6527 case PIPE_SHADER_TESS_EVAL:
6528 fprintf(f, " part.tes.epilog.export_prim_id = %u\n", key->part.tes.epilog.export_prim_id);
6529 fprintf(f, " as_es = %u\n", key->as_es);
6530 break;
6531
6532 case PIPE_SHADER_GEOMETRY:
6533 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
6534 break;
6535
6536 case PIPE_SHADER_COMPUTE:
6537 break;
6538
6539 case PIPE_SHADER_FRAGMENT:
6540 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
6541 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
6542 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
6543 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
6544 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
6545 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
6546 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
6547 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
6548 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
6549 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
6550 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
6551 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
6552 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
6553 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
6554 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
6555 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
6556 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
6557 break;
6558
6559 default:
6560 assert(0);
6561 }
6562
6563 if ((shader == PIPE_SHADER_GEOMETRY ||
6564 shader == PIPE_SHADER_TESS_EVAL ||
6565 shader == PIPE_SHADER_VERTEX) &&
6566 !key->as_es && !key->as_ls) {
6567 fprintf(f, " opt.hw_vs.kill_outputs = 0x%"PRIx64"\n", key->opt.hw_vs.kill_outputs);
6568 fprintf(f, " opt.hw_vs.kill_outputs2 = 0x%x\n", key->opt.hw_vs.kill_outputs2);
6569 fprintf(f, " opt.hw_vs.clip_disable = %u\n", key->opt.hw_vs.clip_disable);
6570 }
6571 }
6572
6573 static void si_init_shader_ctx(struct si_shader_context *ctx,
6574 struct si_screen *sscreen,
6575 struct si_shader *shader,
6576 LLVMTargetMachineRef tm)
6577 {
6578 struct lp_build_tgsi_context *bld_base;
6579 struct lp_build_tgsi_action tmpl = {};
6580
6581 si_llvm_context_init(ctx, sscreen, shader, tm,
6582 (shader && shader->selector) ? &shader->selector->info : NULL,
6583 (shader && shader->selector) ? shader->selector->tokens : NULL);
6584
6585 bld_base = &ctx->bld_base;
6586 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6587
6588 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6589 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6590 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6591
6592 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6593 bld_base->op_actions[TGSI_OPCODE_TEX_LZ] = tex_action;
6594 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6595 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6596 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6597 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6598 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6599 bld_base->op_actions[TGSI_OPCODE_TXF_LZ] = tex_action;
6600 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6601 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6602 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6603 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6604 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6605 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6606 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6607 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6608
6609 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6610 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6611 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6612 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6613 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6614 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6615
6616 tmpl.fetch_args = atomic_fetch_args;
6617 tmpl.emit = atomic_emit;
6618 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6619 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6620 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6621 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6622 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6623 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6624 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6625 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6626 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6627 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6628 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6629 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6630 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6631 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6632 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6633 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6634 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6635 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6636 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6637 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6638
6639 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6640
6641 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
6642
6643 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6644 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6645 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6646 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6647
6648 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
6649 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
6650 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
6651
6652 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6653 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6654 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6655 }
6656
6657 #define EXP_TARGET (HAVE_LLVM >= 0x0500 ? 0 : 3)
6658 #define EXP_OUT0 (HAVE_LLVM >= 0x0500 ? 2 : 5)
6659
6660 /* Return true if the PARAM export has been eliminated. */
6661 static bool si_eliminate_const_output(struct si_shader_context *ctx,
6662 LLVMValueRef inst, unsigned offset)
6663 {
6664 struct si_shader *shader = ctx->shader;
6665 unsigned num_outputs = shader->selector->info.num_outputs;
6666 unsigned i, default_val; /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL */
6667 bool is_zero[4] = {}, is_one[4] = {};
6668
6669 for (i = 0; i < 4; i++) {
6670 LLVMBool loses_info;
6671 LLVMValueRef p = LLVMGetOperand(inst, EXP_OUT0 + i);
6672
6673 /* It's a constant expression. Undef outputs are eliminated too. */
6674 if (LLVMIsUndef(p)) {
6675 is_zero[i] = true;
6676 is_one[i] = true;
6677 } else if (LLVMIsAConstantFP(p)) {
6678 double a = LLVMConstRealGetDouble(p, &loses_info);
6679
6680 if (a == 0)
6681 is_zero[i] = true;
6682 else if (a == 1)
6683 is_one[i] = true;
6684 else
6685 return false; /* other constant */
6686 } else
6687 return false;
6688 }
6689
6690 /* Only certain combinations of 0 and 1 can be eliminated. */
6691 if (is_zero[0] && is_zero[1] && is_zero[2])
6692 default_val = is_zero[3] ? 0 : 1;
6693 else if (is_one[0] && is_one[1] && is_one[2])
6694 default_val = is_zero[3] ? 2 : 3;
6695 else
6696 return false;
6697
6698 /* The PARAM export can be represented as DEFAULT_VAL. Kill it. */
6699 LLVMInstructionEraseFromParent(inst);
6700
6701 /* Change OFFSET to DEFAULT_VAL. */
6702 for (i = 0; i < num_outputs; i++) {
6703 if (shader->info.vs_output_param_offset[i] == offset) {
6704 shader->info.vs_output_param_offset[i] =
6705 EXP_PARAM_DEFAULT_VAL_0000 + default_val;
6706 break;
6707 }
6708 }
6709 return true;
6710 }
6711
6712 struct si_vs_exports {
6713 unsigned num;
6714 unsigned offset[SI_MAX_VS_OUTPUTS];
6715 LLVMValueRef inst[SI_MAX_VS_OUTPUTS];
6716 };
6717
6718 static void si_eliminate_const_vs_outputs(struct si_shader_context *ctx)
6719 {
6720 struct si_shader *shader = ctx->shader;
6721 struct tgsi_shader_info *info = &shader->selector->info;
6722 LLVMBasicBlockRef bb;
6723 struct si_vs_exports exports;
6724 bool removed_any = false;
6725
6726 exports.num = 0;
6727
6728 if (ctx->type == PIPE_SHADER_FRAGMENT ||
6729 ctx->type == PIPE_SHADER_COMPUTE ||
6730 shader->key.as_es ||
6731 shader->key.as_ls)
6732 return;
6733
6734 /* Process all LLVM instructions. */
6735 bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6736 while (bb) {
6737 LLVMValueRef inst = LLVMGetFirstInstruction(bb);
6738
6739 while (inst) {
6740 LLVMValueRef cur = inst;
6741 inst = LLVMGetNextInstruction(inst);
6742
6743 if (LLVMGetInstructionOpcode(cur) != LLVMCall)
6744 continue;
6745
6746 LLVMValueRef callee = lp_get_called_value(cur);
6747
6748 if (!lp_is_function(callee))
6749 continue;
6750
6751 const char *name = LLVMGetValueName(callee);
6752 unsigned num_args = LLVMCountParams(callee);
6753
6754 /* Check if this is an export instruction. */
6755 if ((num_args != 9 && num_args != 8) ||
6756 (strcmp(name, "llvm.SI.export") &&
6757 strcmp(name, "llvm.amdgcn.exp.f32")))
6758 continue;
6759
6760 LLVMValueRef arg = LLVMGetOperand(cur, EXP_TARGET);
6761 unsigned target = LLVMConstIntGetZExtValue(arg);
6762
6763 if (target < V_008DFC_SQ_EXP_PARAM)
6764 continue;
6765
6766 target -= V_008DFC_SQ_EXP_PARAM;
6767
6768 /* Eliminate constant value PARAM exports. */
6769 if (si_eliminate_const_output(ctx, cur, target)) {
6770 removed_any = true;
6771 } else {
6772 exports.offset[exports.num] = target;
6773 exports.inst[exports.num] = cur;
6774 exports.num++;
6775 }
6776 }
6777 bb = LLVMGetNextBasicBlock(bb);
6778 }
6779
6780 /* Remove holes in export memory due to removed PARAM exports.
6781 * This is done by renumbering all PARAM exports.
6782 */
6783 if (removed_any) {
6784 ubyte current_offset[SI_MAX_VS_OUTPUTS];
6785 unsigned new_count = 0;
6786 unsigned out, i;
6787
6788 /* Make a copy of the offsets. We need the old version while
6789 * we are modifying some of them. */
6790 assert(sizeof(current_offset) ==
6791 sizeof(shader->info.vs_output_param_offset));
6792 memcpy(current_offset, shader->info.vs_output_param_offset,
6793 sizeof(current_offset));
6794
6795 for (i = 0; i < exports.num; i++) {
6796 unsigned offset = exports.offset[i];
6797
6798 for (out = 0; out < info->num_outputs; out++) {
6799 if (current_offset[out] != offset)
6800 continue;
6801
6802 LLVMSetOperand(exports.inst[i], EXP_TARGET,
6803 LLVMConstInt(ctx->i32,
6804 V_008DFC_SQ_EXP_PARAM + new_count, 0));
6805 shader->info.vs_output_param_offset[out] = new_count;
6806 new_count++;
6807 break;
6808 }
6809 }
6810 shader->info.nr_param_exports = new_count;
6811 }
6812 }
6813
6814 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
6815 {
6816 ctx->shader->config.private_mem_vgprs = 0;
6817
6818 /* Process all LLVM instructions. */
6819 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6820 while (bb) {
6821 LLVMValueRef next = LLVMGetFirstInstruction(bb);
6822
6823 while (next) {
6824 LLVMValueRef inst = next;
6825 next = LLVMGetNextInstruction(next);
6826
6827 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
6828 continue;
6829
6830 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
6831 /* No idea why LLVM aligns allocas to 4 elements. */
6832 unsigned alignment = LLVMGetAlignment(inst);
6833 unsigned dw_size = align(llvm_get_type_size(type) / 4, alignment);
6834 ctx->shader->config.private_mem_vgprs += dw_size;
6835 }
6836 bb = LLVMGetNextBasicBlock(bb);
6837 }
6838 }
6839
6840 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
6841 struct si_shader *shader)
6842 {
6843 struct si_shader_selector *sel = shader->selector;
6844 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6845
6846 switch (ctx->type) {
6847 case PIPE_SHADER_VERTEX:
6848 ctx->load_input = declare_input_vs;
6849 if (shader->key.as_ls)
6850 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6851 else if (shader->key.as_es)
6852 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6853 else
6854 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6855 break;
6856 case PIPE_SHADER_TESS_CTRL:
6857 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6858 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6859 bld_base->emit_store = store_output_tcs;
6860 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6861 break;
6862 case PIPE_SHADER_TESS_EVAL:
6863 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6864 if (shader->key.as_es)
6865 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6866 else
6867 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6868 break;
6869 case PIPE_SHADER_GEOMETRY:
6870 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6871 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6872 break;
6873 case PIPE_SHADER_FRAGMENT:
6874 ctx->load_input = declare_input_fs;
6875 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6876 break;
6877 case PIPE_SHADER_COMPUTE:
6878 ctx->declare_memory_region = declare_compute_memory;
6879 break;
6880 default:
6881 assert(!"Unsupported shader type");
6882 return false;
6883 }
6884
6885 create_function(ctx);
6886 preload_ring_buffers(ctx);
6887
6888 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6889 int i;
6890 for (i = 0; i < 4; i++) {
6891 ctx->gs_next_vertex[i] =
6892 lp_build_alloca(bld_base->base.gallivm,
6893 ctx->i32, "");
6894 }
6895 }
6896
6897 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6898 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6899 return false;
6900 }
6901
6902 si_llvm_build_ret(ctx, ctx->return_value);
6903 return true;
6904 }
6905
6906 /**
6907 * Compute the VS prolog key, which contains all the information needed to
6908 * build the VS prolog function, and set shader->info bits where needed.
6909 */
6910 static void si_get_vs_prolog_key(struct si_shader *shader,
6911 union si_shader_part_key *key)
6912 {
6913 struct tgsi_shader_info *info = &shader->selector->info;
6914
6915 memset(key, 0, sizeof(*key));
6916 key->vs_prolog.states = shader->key.part.vs.prolog;
6917 key->vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6918 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6919
6920 /* Set the instanceID flag. */
6921 for (unsigned i = 0; i < info->num_inputs; i++)
6922 if (key->vs_prolog.states.instance_divisors[i])
6923 shader->info.uses_instanceid = true;
6924 }
6925
6926 /**
6927 * Compute the VS epilog key, which contains all the information needed to
6928 * build the VS epilog function, and set the PrimitiveID output offset.
6929 */
6930 static void si_get_vs_epilog_key(struct si_shader *shader,
6931 struct si_vs_epilog_bits *states,
6932 union si_shader_part_key *key)
6933 {
6934 memset(key, 0, sizeof(*key));
6935 key->vs_epilog.states = *states;
6936
6937 /* Set up the PrimitiveID output. */
6938 if (shader->key.part.vs.epilog.export_prim_id) {
6939 unsigned index = shader->selector->info.num_outputs;
6940 unsigned offset = shader->info.nr_param_exports++;
6941
6942 key->vs_epilog.prim_id_param_offset = offset;
6943 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
6944 shader->info.vs_output_param_offset[index] = offset;
6945 }
6946 }
6947
6948 /**
6949 * Compute the PS prolog key, which contains all the information needed to
6950 * build the PS prolog function, and set related bits in shader->config.
6951 */
6952 static void si_get_ps_prolog_key(struct si_shader *shader,
6953 union si_shader_part_key *key,
6954 bool separate_prolog)
6955 {
6956 struct tgsi_shader_info *info = &shader->selector->info;
6957
6958 memset(key, 0, sizeof(*key));
6959 key->ps_prolog.states = shader->key.part.ps.prolog;
6960 key->ps_prolog.colors_read = info->colors_read;
6961 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6962 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6963 key->ps_prolog.wqm = info->uses_derivatives &&
6964 (key->ps_prolog.colors_read ||
6965 key->ps_prolog.states.force_persp_sample_interp ||
6966 key->ps_prolog.states.force_linear_sample_interp ||
6967 key->ps_prolog.states.force_persp_center_interp ||
6968 key->ps_prolog.states.force_linear_center_interp ||
6969 key->ps_prolog.states.bc_optimize_for_persp ||
6970 key->ps_prolog.states.bc_optimize_for_linear);
6971
6972 if (info->colors_read) {
6973 unsigned *color = shader->selector->color_attr_index;
6974
6975 if (shader->key.part.ps.prolog.color_two_side) {
6976 /* BCOLORs are stored after the last input. */
6977 key->ps_prolog.num_interp_inputs = info->num_inputs;
6978 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6979 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6980 }
6981
6982 for (unsigned i = 0; i < 2; i++) {
6983 unsigned interp = info->input_interpolate[color[i]];
6984 unsigned location = info->input_interpolate_loc[color[i]];
6985
6986 if (!(info->colors_read & (0xf << i*4)))
6987 continue;
6988
6989 key->ps_prolog.color_attr_index[i] = color[i];
6990
6991 if (shader->key.part.ps.prolog.flatshade_colors &&
6992 interp == TGSI_INTERPOLATE_COLOR)
6993 interp = TGSI_INTERPOLATE_CONSTANT;
6994
6995 switch (interp) {
6996 case TGSI_INTERPOLATE_CONSTANT:
6997 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6998 break;
6999 case TGSI_INTERPOLATE_PERSPECTIVE:
7000 case TGSI_INTERPOLATE_COLOR:
7001 /* Force the interpolation location for colors here. */
7002 if (shader->key.part.ps.prolog.force_persp_sample_interp)
7003 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7004 if (shader->key.part.ps.prolog.force_persp_center_interp)
7005 location = TGSI_INTERPOLATE_LOC_CENTER;
7006
7007 switch (location) {
7008 case TGSI_INTERPOLATE_LOC_SAMPLE:
7009 key->ps_prolog.color_interp_vgpr_index[i] = 0;
7010 shader->config.spi_ps_input_ena |=
7011 S_0286CC_PERSP_SAMPLE_ENA(1);
7012 break;
7013 case TGSI_INTERPOLATE_LOC_CENTER:
7014 key->ps_prolog.color_interp_vgpr_index[i] = 2;
7015 shader->config.spi_ps_input_ena |=
7016 S_0286CC_PERSP_CENTER_ENA(1);
7017 break;
7018 case TGSI_INTERPOLATE_LOC_CENTROID:
7019 key->ps_prolog.color_interp_vgpr_index[i] = 4;
7020 shader->config.spi_ps_input_ena |=
7021 S_0286CC_PERSP_CENTROID_ENA(1);
7022 break;
7023 default:
7024 assert(0);
7025 }
7026 break;
7027 case TGSI_INTERPOLATE_LINEAR:
7028 /* Force the interpolation location for colors here. */
7029 if (shader->key.part.ps.prolog.force_linear_sample_interp)
7030 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7031 if (shader->key.part.ps.prolog.force_linear_center_interp)
7032 location = TGSI_INTERPOLATE_LOC_CENTER;
7033
7034 /* The VGPR assignment for non-monolithic shaders
7035 * works because InitialPSInputAddr is set on the
7036 * main shader and PERSP_PULL_MODEL is never used.
7037 */
7038 switch (location) {
7039 case TGSI_INTERPOLATE_LOC_SAMPLE:
7040 key->ps_prolog.color_interp_vgpr_index[i] =
7041 separate_prolog ? 6 : 9;
7042 shader->config.spi_ps_input_ena |=
7043 S_0286CC_LINEAR_SAMPLE_ENA(1);
7044 break;
7045 case TGSI_INTERPOLATE_LOC_CENTER:
7046 key->ps_prolog.color_interp_vgpr_index[i] =
7047 separate_prolog ? 8 : 11;
7048 shader->config.spi_ps_input_ena |=
7049 S_0286CC_LINEAR_CENTER_ENA(1);
7050 break;
7051 case TGSI_INTERPOLATE_LOC_CENTROID:
7052 key->ps_prolog.color_interp_vgpr_index[i] =
7053 separate_prolog ? 10 : 13;
7054 shader->config.spi_ps_input_ena |=
7055 S_0286CC_LINEAR_CENTROID_ENA(1);
7056 break;
7057 default:
7058 assert(0);
7059 }
7060 break;
7061 default:
7062 assert(0);
7063 }
7064 }
7065 }
7066 }
7067
7068 /**
7069 * Check whether a PS prolog is required based on the key.
7070 */
7071 static bool si_need_ps_prolog(const union si_shader_part_key *key)
7072 {
7073 return key->ps_prolog.colors_read ||
7074 key->ps_prolog.states.force_persp_sample_interp ||
7075 key->ps_prolog.states.force_linear_sample_interp ||
7076 key->ps_prolog.states.force_persp_center_interp ||
7077 key->ps_prolog.states.force_linear_center_interp ||
7078 key->ps_prolog.states.bc_optimize_for_persp ||
7079 key->ps_prolog.states.bc_optimize_for_linear ||
7080 key->ps_prolog.states.poly_stipple;
7081 }
7082
7083 /**
7084 * Compute the PS epilog key, which contains all the information needed to
7085 * build the PS epilog function.
7086 */
7087 static void si_get_ps_epilog_key(struct si_shader *shader,
7088 union si_shader_part_key *key)
7089 {
7090 struct tgsi_shader_info *info = &shader->selector->info;
7091 memset(key, 0, sizeof(*key));
7092 key->ps_epilog.colors_written = info->colors_written;
7093 key->ps_epilog.writes_z = info->writes_z;
7094 key->ps_epilog.writes_stencil = info->writes_stencil;
7095 key->ps_epilog.writes_samplemask = info->writes_samplemask;
7096 key->ps_epilog.states = shader->key.part.ps.epilog;
7097 }
7098
7099 /**
7100 * Build the GS prolog function. Rotate the input vertices for triangle strips
7101 * with adjacency.
7102 */
7103 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
7104 union si_shader_part_key *key)
7105 {
7106 const unsigned num_sgprs = SI_GS_NUM_USER_SGPR + 2;
7107 const unsigned num_vgprs = 8;
7108 struct gallivm_state *gallivm = &ctx->gallivm;
7109 LLVMBuilderRef builder = gallivm->builder;
7110 LLVMTypeRef params[32];
7111 LLVMTypeRef returns[32];
7112 LLVMValueRef func, ret;
7113
7114 for (unsigned i = 0; i < num_sgprs; ++i) {
7115 params[i] = ctx->i32;
7116 returns[i] = ctx->i32;
7117 }
7118
7119 for (unsigned i = 0; i < num_vgprs; ++i) {
7120 params[num_sgprs + i] = ctx->i32;
7121 returns[num_sgprs + i] = ctx->f32;
7122 }
7123
7124 /* Create the function. */
7125 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
7126 params, num_sgprs + num_vgprs, num_sgprs - 1);
7127 func = ctx->main_fn;
7128
7129 /* Copy inputs to outputs. This should be no-op, as the registers match,
7130 * but it will prevent the compiler from overwriting them unintentionally.
7131 */
7132 ret = ctx->return_value;
7133 for (unsigned i = 0; i < num_sgprs; i++) {
7134 LLVMValueRef p = LLVMGetParam(func, i);
7135 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
7136 }
7137 for (unsigned i = 0; i < num_vgprs; i++) {
7138 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
7139 p = LLVMBuildBitCast(builder, p, ctx->f32, "");
7140 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
7141 }
7142
7143 if (key->gs_prolog.states.tri_strip_adj_fix) {
7144 /* Remap the input vertices for every other primitive. */
7145 const unsigned vtx_params[6] = {
7146 num_sgprs,
7147 num_sgprs + 1,
7148 num_sgprs + 3,
7149 num_sgprs + 4,
7150 num_sgprs + 5,
7151 num_sgprs + 6
7152 };
7153 LLVMValueRef prim_id, rotate;
7154
7155 prim_id = LLVMGetParam(func, num_sgprs + 2);
7156 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
7157
7158 for (unsigned i = 0; i < 6; ++i) {
7159 LLVMValueRef base, rotated, actual;
7160 base = LLVMGetParam(func, vtx_params[i]);
7161 rotated = LLVMGetParam(func, vtx_params[(i + 4) % 6]);
7162 actual = LLVMBuildSelect(builder, rotate, rotated, base, "");
7163 actual = LLVMBuildBitCast(builder, actual, ctx->f32, "");
7164 ret = LLVMBuildInsertValue(builder, ret, actual, vtx_params[i], "");
7165 }
7166 }
7167
7168 LLVMBuildRet(builder, ret);
7169 }
7170
7171 /**
7172 * Given a list of shader part functions, build a wrapper function that
7173 * runs them in sequence to form a monolithic shader.
7174 */
7175 static void si_build_wrapper_function(struct si_shader_context *ctx,
7176 LLVMValueRef *parts,
7177 unsigned num_parts,
7178 unsigned main_part)
7179 {
7180 struct gallivm_state *gallivm = &ctx->gallivm;
7181 LLVMBuilderRef builder = ctx->gallivm.builder;
7182 /* PS epilog has one arg per color component */
7183 LLVMTypeRef param_types[48];
7184 LLVMValueRef out[48];
7185 LLVMTypeRef function_type;
7186 unsigned num_params;
7187 unsigned num_out;
7188 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
7189 unsigned num_sgprs, num_vgprs;
7190 unsigned last_sgpr_param;
7191 unsigned gprs;
7192
7193 for (unsigned i = 0; i < num_parts; ++i) {
7194 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
7195 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
7196 }
7197
7198 /* The parameters of the wrapper function correspond to those of the
7199 * first part in terms of SGPRs and VGPRs, but we use the types of the
7200 * main part to get the right types. This is relevant for the
7201 * dereferenceable attribute on descriptor table pointers.
7202 */
7203 num_sgprs = 0;
7204 num_vgprs = 0;
7205
7206 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
7207 num_params = LLVMCountParamTypes(function_type);
7208
7209 for (unsigned i = 0; i < num_params; ++i) {
7210 LLVMValueRef param = LLVMGetParam(parts[0], i);
7211
7212 if (ac_is_sgpr_param(param)) {
7213 assert(num_vgprs == 0);
7214 num_sgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
7215 } else {
7216 num_vgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
7217 }
7218 }
7219 assert(num_vgprs + num_sgprs <= ARRAY_SIZE(param_types));
7220
7221 num_params = 0;
7222 last_sgpr_param = 0;
7223 gprs = 0;
7224 while (gprs < num_sgprs + num_vgprs) {
7225 LLVMValueRef param = LLVMGetParam(parts[main_part], num_params);
7226 unsigned size;
7227
7228 param_types[num_params] = LLVMTypeOf(param);
7229 if (gprs < num_sgprs)
7230 last_sgpr_param = num_params;
7231 size = llvm_get_type_size(param_types[num_params]) / 4;
7232 num_params++;
7233
7234 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
7235 assert(gprs + size <= num_sgprs + num_vgprs &&
7236 (gprs >= num_sgprs || gprs + size <= num_sgprs));
7237
7238 gprs += size;
7239 }
7240
7241 si_create_function(ctx, "wrapper", NULL, 0, param_types, num_params, last_sgpr_param);
7242
7243 /* Record the arguments of the function as if they were an output of
7244 * a previous part.
7245 */
7246 num_out = 0;
7247 num_out_sgpr = 0;
7248
7249 for (unsigned i = 0; i < num_params; ++i) {
7250 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
7251 LLVMTypeRef param_type = LLVMTypeOf(param);
7252 LLVMTypeRef out_type = i <= last_sgpr_param ? ctx->i32 : ctx->f32;
7253 unsigned size = llvm_get_type_size(param_type) / 4;
7254
7255 if (size == 1) {
7256 if (param_type != out_type)
7257 param = LLVMBuildBitCast(builder, param, out_type, "");
7258 out[num_out++] = param;
7259 } else {
7260 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
7261
7262 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7263 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
7264 param_type = ctx->i64;
7265 }
7266
7267 if (param_type != vector_type)
7268 param = LLVMBuildBitCast(builder, param, vector_type, "");
7269
7270 for (unsigned j = 0; j < size; ++j)
7271 out[num_out++] = LLVMBuildExtractElement(
7272 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
7273 }
7274
7275 if (i <= last_sgpr_param)
7276 num_out_sgpr = num_out;
7277 }
7278
7279 /* Now chain the parts. */
7280 for (unsigned part = 0; part < num_parts; ++part) {
7281 LLVMValueRef in[48];
7282 LLVMValueRef ret;
7283 LLVMTypeRef ret_type;
7284 unsigned out_idx = 0;
7285
7286 num_params = LLVMCountParams(parts[part]);
7287 assert(num_params <= ARRAY_SIZE(param_types));
7288
7289 /* Derive arguments for the next part from outputs of the
7290 * previous one.
7291 */
7292 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
7293 LLVMValueRef param;
7294 LLVMTypeRef param_type;
7295 bool is_sgpr;
7296 unsigned param_size;
7297 LLVMValueRef arg = NULL;
7298
7299 param = LLVMGetParam(parts[part], param_idx);
7300 param_type = LLVMTypeOf(param);
7301 param_size = llvm_get_type_size(param_type) / 4;
7302 is_sgpr = ac_is_sgpr_param(param);
7303
7304 if (is_sgpr) {
7305 #if HAVE_LLVM < 0x0400
7306 LLVMRemoveAttribute(param, LLVMByValAttribute);
7307 #else
7308 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
7309 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
7310 #endif
7311 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
7312 }
7313
7314 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
7315 assert(is_sgpr || out_idx >= num_out_sgpr);
7316
7317 if (param_size == 1)
7318 arg = out[out_idx];
7319 else
7320 arg = lp_build_gather_values(gallivm, &out[out_idx], param_size);
7321
7322 if (LLVMTypeOf(arg) != param_type) {
7323 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7324 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
7325 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
7326 } else {
7327 arg = LLVMBuildBitCast(builder, arg, param_type, "");
7328 }
7329 }
7330
7331 in[param_idx] = arg;
7332 out_idx += param_size;
7333 }
7334
7335 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
7336 ret_type = LLVMTypeOf(ret);
7337
7338 /* Extract the returned GPRs. */
7339 num_out = 0;
7340 num_out_sgpr = 0;
7341
7342 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
7343 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
7344
7345 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
7346
7347 for (unsigned i = 0; i < ret_size; ++i) {
7348 LLVMValueRef val =
7349 LLVMBuildExtractValue(builder, ret, i, "");
7350
7351 out[num_out++] = val;
7352
7353 if (LLVMTypeOf(val) == ctx->i32) {
7354 assert(num_out_sgpr + 1 == num_out);
7355 num_out_sgpr = num_out;
7356 }
7357 }
7358 }
7359 }
7360
7361 LLVMBuildRetVoid(builder);
7362 }
7363
7364 int si_compile_tgsi_shader(struct si_screen *sscreen,
7365 LLVMTargetMachineRef tm,
7366 struct si_shader *shader,
7367 bool is_monolithic,
7368 struct pipe_debug_callback *debug)
7369 {
7370 struct si_shader_selector *sel = shader->selector;
7371 struct si_shader_context ctx;
7372 struct lp_build_tgsi_context *bld_base;
7373 LLVMModuleRef mod;
7374 int r = -1;
7375
7376 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
7377 * conversion fails. */
7378 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
7379 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
7380 tgsi_dump(sel->tokens, 0);
7381 si_dump_streamout(&sel->so);
7382 }
7383
7384 si_init_shader_ctx(&ctx, sscreen, shader, tm);
7385 ctx.separate_prolog = !is_monolithic;
7386
7387 memset(shader->info.vs_output_param_offset, EXP_PARAM_UNDEFINED,
7388 sizeof(shader->info.vs_output_param_offset));
7389
7390 shader->info.uses_instanceid = sel->info.uses_instanceid;
7391
7392 bld_base = &ctx.bld_base;
7393 ctx.load_system_value = declare_system_value;
7394
7395 if (!si_compile_tgsi_main(&ctx, shader)) {
7396 si_llvm_dispose(&ctx);
7397 return -1;
7398 }
7399
7400 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
7401 LLVMValueRef parts[3];
7402 bool need_prolog;
7403 bool need_epilog;
7404
7405 need_prolog = sel->info.num_inputs;
7406 need_epilog = !shader->key.as_es && !shader->key.as_ls;
7407
7408 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7409
7410 if (need_prolog) {
7411 union si_shader_part_key prolog_key;
7412 si_get_vs_prolog_key(shader, &prolog_key);
7413 si_build_vs_prolog_function(&ctx, &prolog_key);
7414 parts[0] = ctx.main_fn;
7415 }
7416
7417 if (need_epilog) {
7418 union si_shader_part_key epilog_key;
7419 si_get_vs_epilog_key(shader, &shader->key.part.vs.epilog, &epilog_key);
7420 si_build_vs_epilog_function(&ctx, &epilog_key);
7421 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7422 }
7423
7424 si_build_wrapper_function(&ctx, parts, 1 + need_prolog + need_epilog,
7425 need_prolog ? 1 : 0);
7426 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
7427 LLVMValueRef parts[2];
7428 union si_shader_part_key epilog_key;
7429
7430 parts[0] = ctx.main_fn;
7431
7432 memset(&epilog_key, 0, sizeof(epilog_key));
7433 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7434 si_build_tcs_epilog_function(&ctx, &epilog_key);
7435 parts[1] = ctx.main_fn;
7436
7437 si_build_wrapper_function(&ctx, parts, 2, 0);
7438 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_EVAL &&
7439 !shader->key.as_es) {
7440 LLVMValueRef parts[2];
7441 union si_shader_part_key epilog_key;
7442
7443 parts[0] = ctx.main_fn;
7444
7445 si_get_vs_epilog_key(shader, &shader->key.part.tes.epilog, &epilog_key);
7446 si_build_vs_epilog_function(&ctx, &epilog_key);
7447 parts[1] = ctx.main_fn;
7448
7449 si_build_wrapper_function(&ctx, parts, 2, 0);
7450 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
7451 LLVMValueRef parts[2];
7452 union si_shader_part_key prolog_key;
7453
7454 parts[1] = ctx.main_fn;
7455
7456 memset(&prolog_key, 0, sizeof(prolog_key));
7457 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7458 si_build_gs_prolog_function(&ctx, &prolog_key);
7459 parts[0] = ctx.main_fn;
7460
7461 si_build_wrapper_function(&ctx, parts, 2, 1);
7462 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
7463 LLVMValueRef parts[3];
7464 union si_shader_part_key prolog_key;
7465 union si_shader_part_key epilog_key;
7466 bool need_prolog;
7467
7468 si_get_ps_prolog_key(shader, &prolog_key, false);
7469 need_prolog = si_need_ps_prolog(&prolog_key);
7470
7471 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7472
7473 if (need_prolog) {
7474 si_build_ps_prolog_function(&ctx, &prolog_key);
7475 parts[0] = ctx.main_fn;
7476 }
7477
7478 si_get_ps_epilog_key(shader, &epilog_key);
7479 si_build_ps_epilog_function(&ctx, &epilog_key);
7480 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7481
7482 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2, need_prolog ? 1 : 0);
7483 }
7484
7485 mod = bld_base->base.gallivm->module;
7486
7487 /* Dump LLVM IR before any optimization passes */
7488 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
7489 r600_can_dump_shader(&sscreen->b, ctx.type))
7490 ac_dump_module(mod);
7491
7492 si_llvm_finalize_module(&ctx,
7493 r600_extra_shader_checks(&sscreen->b, ctx.type));
7494
7495 /* Post-optimization transformations and analysis. */
7496 si_eliminate_const_vs_outputs(&ctx);
7497
7498 if ((debug && debug->debug_message) ||
7499 r600_can_dump_shader(&sscreen->b, ctx.type))
7500 si_count_scratch_private_memory(&ctx);
7501
7502 /* Compile to bytecode. */
7503 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
7504 mod, debug, ctx.type, "TGSI shader");
7505 si_llvm_dispose(&ctx);
7506 if (r) {
7507 fprintf(stderr, "LLVM failed to compile shader\n");
7508 return r;
7509 }
7510
7511 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
7512 * LLVM 3.9svn has this bug.
7513 */
7514 if (sel->type == PIPE_SHADER_COMPUTE) {
7515 unsigned wave_size = 64;
7516 unsigned max_vgprs = 256;
7517 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
7518 unsigned max_sgprs_per_wave = 128;
7519 unsigned max_block_threads = si_get_max_workgroup_size(shader);
7520 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
7521 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
7522
7523 max_vgprs = max_vgprs / min_waves_per_simd;
7524 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
7525
7526 if (shader->config.num_sgprs > max_sgprs ||
7527 shader->config.num_vgprs > max_vgprs) {
7528 fprintf(stderr, "LLVM failed to compile a shader correctly: "
7529 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7530 shader->config.num_sgprs, shader->config.num_vgprs,
7531 max_sgprs, max_vgprs);
7532
7533 /* Just terminate the process, because dependent
7534 * shaders can hang due to bad input data, but use
7535 * the env var to allow shader-db to work.
7536 */
7537 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7538 abort();
7539 }
7540 }
7541
7542 /* Add the scratch offset to input SGPRs. */
7543 if (shader->config.scratch_bytes_per_wave)
7544 shader->info.num_input_sgprs += 1; /* scratch byte offset */
7545
7546 /* Calculate the number of fragment input VGPRs. */
7547 if (ctx.type == PIPE_SHADER_FRAGMENT) {
7548 shader->info.num_input_vgprs = 0;
7549 shader->info.face_vgpr_index = -1;
7550
7551 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7552 shader->info.num_input_vgprs += 2;
7553 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
7554 shader->info.num_input_vgprs += 2;
7555 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
7556 shader->info.num_input_vgprs += 2;
7557 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
7558 shader->info.num_input_vgprs += 3;
7559 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7560 shader->info.num_input_vgprs += 2;
7561 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7562 shader->info.num_input_vgprs += 2;
7563 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7564 shader->info.num_input_vgprs += 2;
7565 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7566 shader->info.num_input_vgprs += 1;
7567 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7568 shader->info.num_input_vgprs += 1;
7569 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7570 shader->info.num_input_vgprs += 1;
7571 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7572 shader->info.num_input_vgprs += 1;
7573 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7574 shader->info.num_input_vgprs += 1;
7575 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7576 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7577 shader->info.num_input_vgprs += 1;
7578 }
7579 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
7580 shader->info.num_input_vgprs += 1;
7581 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7582 shader->info.num_input_vgprs += 1;
7583 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7584 shader->info.num_input_vgprs += 1;
7585 }
7586
7587 return 0;
7588 }
7589
7590 /**
7591 * Create, compile and return a shader part (prolog or epilog).
7592 *
7593 * \param sscreen screen
7594 * \param list list of shader parts of the same category
7595 * \param type shader type
7596 * \param key shader part key
7597 * \param prolog whether the part being requested is a prolog
7598 * \param tm LLVM target machine
7599 * \param debug debug callback
7600 * \param build the callback responsible for building the main function
7601 * \return non-NULL on success
7602 */
7603 static struct si_shader_part *
7604 si_get_shader_part(struct si_screen *sscreen,
7605 struct si_shader_part **list,
7606 enum pipe_shader_type type,
7607 bool prolog,
7608 union si_shader_part_key *key,
7609 LLVMTargetMachineRef tm,
7610 struct pipe_debug_callback *debug,
7611 void (*build)(struct si_shader_context *,
7612 union si_shader_part_key *),
7613 const char *name)
7614 {
7615 struct si_shader_part *result;
7616
7617 mtx_lock(&sscreen->shader_parts_mutex);
7618
7619 /* Find existing. */
7620 for (result = *list; result; result = result->next) {
7621 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7622 mtx_unlock(&sscreen->shader_parts_mutex);
7623 return result;
7624 }
7625 }
7626
7627 /* Compile a new one. */
7628 result = CALLOC_STRUCT(si_shader_part);
7629 result->key = *key;
7630
7631 struct si_shader shader = {};
7632 struct si_shader_context ctx;
7633 struct gallivm_state *gallivm = &ctx.gallivm;
7634
7635 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7636 ctx.type = type;
7637
7638 switch (type) {
7639 case PIPE_SHADER_VERTEX:
7640 break;
7641 case PIPE_SHADER_TESS_CTRL:
7642 assert(!prolog);
7643 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7644 break;
7645 case PIPE_SHADER_GEOMETRY:
7646 assert(prolog);
7647 break;
7648 case PIPE_SHADER_FRAGMENT:
7649 if (prolog)
7650 shader.key.part.ps.prolog = key->ps_prolog.states;
7651 else
7652 shader.key.part.ps.epilog = key->ps_epilog.states;
7653 break;
7654 default:
7655 unreachable("bad shader part");
7656 }
7657
7658 build(&ctx, key);
7659
7660 /* Compile. */
7661 si_llvm_finalize_module(&ctx,
7662 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT));
7663
7664 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7665 gallivm->module, debug, ctx.type, name)) {
7666 FREE(result);
7667 result = NULL;
7668 goto out;
7669 }
7670
7671 result->next = *list;
7672 *list = result;
7673
7674 out:
7675 si_llvm_dispose(&ctx);
7676 mtx_unlock(&sscreen->shader_parts_mutex);
7677 return result;
7678 }
7679
7680 /**
7681 * Build the vertex shader prolog function.
7682 *
7683 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7684 * All inputs are returned unmodified. The vertex load indices are
7685 * stored after them, which will be used by the API VS for fetching inputs.
7686 *
7687 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7688 * input_v0,
7689 * input_v1,
7690 * input_v2,
7691 * input_v3,
7692 * (VertexID + BaseVertex),
7693 * (InstanceID + StartInstance),
7694 * (InstanceID / 2 + StartInstance)
7695 */
7696 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7697 union si_shader_part_key *key)
7698 {
7699 struct gallivm_state *gallivm = &ctx->gallivm;
7700 LLVMTypeRef *params, *returns;
7701 LLVMValueRef ret, func;
7702 int last_sgpr, num_params, num_returns, i;
7703
7704 ctx->param_vertex_id = key->vs_prolog.num_input_sgprs;
7705 ctx->param_instance_id = key->vs_prolog.num_input_sgprs + 3;
7706
7707 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7708 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
7709 sizeof(LLVMTypeRef));
7710 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
7711 key->vs_prolog.last_input + 1) *
7712 sizeof(LLVMTypeRef));
7713 num_params = 0;
7714 num_returns = 0;
7715
7716 /* Declare input and output SGPRs. */
7717 num_params = 0;
7718 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7719 params[num_params++] = ctx->i32;
7720 returns[num_returns++] = ctx->i32;
7721 }
7722 last_sgpr = num_params - 1;
7723
7724 /* 4 preloaded VGPRs (outputs must be floats) */
7725 for (i = 0; i < 4; i++) {
7726 params[num_params++] = ctx->i32;
7727 returns[num_returns++] = ctx->f32;
7728 }
7729
7730 /* Vertex load indices. */
7731 for (i = 0; i <= key->vs_prolog.last_input; i++)
7732 returns[num_returns++] = ctx->f32;
7733
7734 /* Create the function. */
7735 si_create_function(ctx, "vs_prolog", returns, num_returns, params,
7736 num_params, last_sgpr);
7737 func = ctx->main_fn;
7738
7739 /* Copy inputs to outputs. This should be no-op, as the registers match,
7740 * but it will prevent the compiler from overwriting them unintentionally.
7741 */
7742 ret = ctx->return_value;
7743 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7744 LLVMValueRef p = LLVMGetParam(func, i);
7745 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7746 }
7747 for (i = num_params - 4; i < num_params; i++) {
7748 LLVMValueRef p = LLVMGetParam(func, i);
7749 p = LLVMBuildBitCast(gallivm->builder, p, ctx->f32, "");
7750 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7751 }
7752
7753 /* Compute vertex load indices from instance divisors. */
7754 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7755 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
7756 LLVMValueRef index;
7757
7758 if (divisor) {
7759 /* InstanceID / Divisor + StartInstance */
7760 index = get_instance_index_for_fetch(ctx,
7761 SI_SGPR_START_INSTANCE,
7762 divisor);
7763 } else {
7764 /* VertexID + BaseVertex */
7765 index = LLVMBuildAdd(gallivm->builder,
7766 LLVMGetParam(func, ctx->param_vertex_id),
7767 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
7768 }
7769
7770 index = LLVMBuildBitCast(gallivm->builder, index, ctx->f32, "");
7771 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
7772 num_params++, "");
7773 }
7774
7775 si_llvm_build_ret(ctx, ret);
7776 }
7777
7778 /**
7779 * Build the vertex shader epilog function. This is also used by the tessellation
7780 * evaluation shader compiled as VS.
7781 *
7782 * The input is PrimitiveID.
7783 *
7784 * If PrimitiveID is required by the pixel shader, export it.
7785 * Otherwise, do nothing.
7786 */
7787 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
7788 union si_shader_part_key *key)
7789 {
7790 struct gallivm_state *gallivm = &ctx->gallivm;
7791 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7792 LLVMTypeRef params[5];
7793 int num_params, i;
7794
7795 /* Declare input VGPRs. */
7796 num_params = key->vs_epilog.states.export_prim_id ?
7797 (VS_EPILOG_PRIMID_LOC + 1) : 0;
7798 assert(num_params <= ARRAY_SIZE(params));
7799
7800 for (i = 0; i < num_params; i++)
7801 params[i] = ctx->f32;
7802
7803 /* Create the function. */
7804 si_create_function(ctx, "vs_epilog", NULL, 0, params, num_params, -1);
7805
7806 /* Emit exports. */
7807 if (key->vs_epilog.states.export_prim_id) {
7808 struct lp_build_context *base = &bld_base->base;
7809 struct ac_export_args args;
7810
7811 args.enabled_channels = 0x1; /* enabled channels */
7812 args.valid_mask = 0; /* whether the EXEC mask is valid */
7813 args.done = 0; /* DONE bit */
7814 args.target = V_008DFC_SQ_EXP_PARAM +
7815 key->vs_epilog.prim_id_param_offset;
7816 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
7817 args.out[0] = LLVMGetParam(ctx->main_fn,
7818 VS_EPILOG_PRIMID_LOC); /* X */
7819 args.out[1] = base->undef; /* Y */
7820 args.out[2] = base->undef; /* Z */
7821 args.out[3] = base->undef; /* W */
7822
7823 ac_build_export(&ctx->ac, &args);
7824 }
7825
7826 LLVMBuildRetVoid(gallivm->builder);
7827 }
7828
7829 /**
7830 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7831 */
7832 static bool si_get_vs_epilog(struct si_screen *sscreen,
7833 LLVMTargetMachineRef tm,
7834 struct si_shader *shader,
7835 struct pipe_debug_callback *debug,
7836 struct si_vs_epilog_bits *states)
7837 {
7838 union si_shader_part_key epilog_key;
7839
7840 si_get_vs_epilog_key(shader, states, &epilog_key);
7841
7842 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
7843 PIPE_SHADER_VERTEX, true,
7844 &epilog_key, tm, debug,
7845 si_build_vs_epilog_function,
7846 "Vertex Shader Epilog");
7847 return shader->epilog != NULL;
7848 }
7849
7850 /**
7851 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7852 */
7853 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7854 LLVMTargetMachineRef tm,
7855 struct si_shader *shader,
7856 struct pipe_debug_callback *debug)
7857 {
7858 struct tgsi_shader_info *info = &shader->selector->info;
7859 union si_shader_part_key prolog_key;
7860
7861 /* Get the prolog. */
7862 si_get_vs_prolog_key(shader, &prolog_key);
7863
7864 /* The prolog is a no-op if there are no inputs. */
7865 if (info->num_inputs) {
7866 shader->prolog =
7867 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7868 PIPE_SHADER_VERTEX, true,
7869 &prolog_key, tm, debug,
7870 si_build_vs_prolog_function,
7871 "Vertex Shader Prolog");
7872 if (!shader->prolog)
7873 return false;
7874 }
7875
7876 /* Get the epilog. */
7877 if (!shader->key.as_es && !shader->key.as_ls &&
7878 !si_get_vs_epilog(sscreen, tm, shader, debug,
7879 &shader->key.part.vs.epilog))
7880 return false;
7881
7882 return true;
7883 }
7884
7885 /**
7886 * Select and compile (or reuse) TES parts (epilog).
7887 */
7888 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
7889 LLVMTargetMachineRef tm,
7890 struct si_shader *shader,
7891 struct pipe_debug_callback *debug)
7892 {
7893 if (shader->key.as_es)
7894 return true;
7895
7896 /* TES compiled as VS. */
7897 return si_get_vs_epilog(sscreen, tm, shader, debug,
7898 &shader->key.part.tes.epilog);
7899 }
7900
7901 /**
7902 * Compile the TCS epilog function. This writes tesselation factors to memory
7903 * based on the output primitive type of the tesselator (determined by TES).
7904 */
7905 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7906 union si_shader_part_key *key)
7907 {
7908 struct gallivm_state *gallivm = &ctx->gallivm;
7909 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7910 LLVMTypeRef params[16];
7911 LLVMValueRef func;
7912 int last_sgpr, num_params;
7913
7914 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
7915 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
7916 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
7917 params[SI_PARAM_SAMPLERS] = ctx->i64;
7918 params[SI_PARAM_IMAGES] = ctx->i64;
7919 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
7920 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
7921 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
7922 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
7923 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
7924 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
7925 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
7926 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
7927 num_params = last_sgpr + 1;
7928
7929 params[num_params++] = ctx->i32; /* patch index within the wave (REL_PATCH_ID) */
7930 params[num_params++] = ctx->i32; /* invocation ID within the patch */
7931 params[num_params++] = ctx->i32; /* LDS offset where tess factors should be loaded from */
7932
7933 /* Create the function. */
7934 si_create_function(ctx, "tcs_epilog", NULL, 0, params, num_params, last_sgpr);
7935 declare_tess_lds(ctx);
7936 func = ctx->main_fn;
7937
7938 si_write_tess_factors(bld_base,
7939 LLVMGetParam(func, last_sgpr + 1),
7940 LLVMGetParam(func, last_sgpr + 2),
7941 LLVMGetParam(func, last_sgpr + 3));
7942
7943 LLVMBuildRetVoid(gallivm->builder);
7944 }
7945
7946 /**
7947 * Select and compile (or reuse) TCS parts (epilog).
7948 */
7949 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7950 LLVMTargetMachineRef tm,
7951 struct si_shader *shader,
7952 struct pipe_debug_callback *debug)
7953 {
7954 union si_shader_part_key epilog_key;
7955
7956 /* Get the epilog. */
7957 memset(&epilog_key, 0, sizeof(epilog_key));
7958 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7959
7960 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7961 PIPE_SHADER_TESS_CTRL, false,
7962 &epilog_key, tm, debug,
7963 si_build_tcs_epilog_function,
7964 "Tessellation Control Shader Epilog");
7965 return shader->epilog != NULL;
7966 }
7967
7968 /**
7969 * Select and compile (or reuse) GS parts (prolog).
7970 */
7971 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7972 LLVMTargetMachineRef tm,
7973 struct si_shader *shader,
7974 struct pipe_debug_callback *debug)
7975 {
7976 union si_shader_part_key prolog_key;
7977
7978 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7979 return true;
7980
7981 memset(&prolog_key, 0, sizeof(prolog_key));
7982 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7983
7984 shader->prolog = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7985 PIPE_SHADER_GEOMETRY, true,
7986 &prolog_key, tm, debug,
7987 si_build_gs_prolog_function,
7988 "Geometry Shader Prolog");
7989 return shader->prolog != NULL;
7990 }
7991
7992 /**
7993 * Build the pixel shader prolog function. This handles:
7994 * - two-side color selection and interpolation
7995 * - overriding interpolation parameters for the API PS
7996 * - polygon stippling
7997 *
7998 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7999 * overriden by other states. (e.g. per-sample interpolation)
8000 * Interpolated colors are stored after the preloaded VGPRs.
8001 */
8002 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
8003 union si_shader_part_key *key)
8004 {
8005 struct gallivm_state *gallivm = &ctx->gallivm;
8006 LLVMTypeRef *params;
8007 LLVMValueRef ret, func;
8008 int last_sgpr, num_params, num_returns, i, num_color_channels;
8009
8010 assert(si_need_ps_prolog(key));
8011
8012 /* Number of inputs + 8 color elements. */
8013 params = alloca((key->ps_prolog.num_input_sgprs +
8014 key->ps_prolog.num_input_vgprs + 8) *
8015 sizeof(LLVMTypeRef));
8016
8017 /* Declare inputs. */
8018 num_params = 0;
8019 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
8020 params[num_params++] = ctx->i32;
8021 last_sgpr = num_params - 1;
8022
8023 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
8024 params[num_params++] = ctx->f32;
8025
8026 /* Declare outputs (same as inputs + add colors if needed) */
8027 num_returns = num_params;
8028 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
8029 for (i = 0; i < num_color_channels; i++)
8030 params[num_returns++] = ctx->f32;
8031
8032 /* Create the function. */
8033 si_create_function(ctx, "ps_prolog", params, num_returns, params,
8034 num_params, last_sgpr);
8035 func = ctx->main_fn;
8036
8037 /* Copy inputs to outputs. This should be no-op, as the registers match,
8038 * but it will prevent the compiler from overwriting them unintentionally.
8039 */
8040 ret = ctx->return_value;
8041 for (i = 0; i < num_params; i++) {
8042 LLVMValueRef p = LLVMGetParam(func, i);
8043 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
8044 }
8045
8046 /* Polygon stippling. */
8047 if (key->ps_prolog.states.poly_stipple) {
8048 /* POS_FIXED_PT is always last. */
8049 unsigned pos = key->ps_prolog.num_input_sgprs +
8050 key->ps_prolog.num_input_vgprs - 1;
8051 LLVMValueRef ptr[2], list;
8052
8053 /* Get the pointer to rw buffers. */
8054 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
8055 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
8056 list = lp_build_gather_values(gallivm, ptr, 2);
8057 list = LLVMBuildBitCast(gallivm->builder, list, ctx->i64, "");
8058 list = LLVMBuildIntToPtr(gallivm->builder, list,
8059 const_array(ctx->v16i8, SI_NUM_RW_BUFFERS), "");
8060
8061 si_llvm_emit_polygon_stipple(ctx, list, pos);
8062 }
8063
8064 if (key->ps_prolog.states.bc_optimize_for_persp ||
8065 key->ps_prolog.states.bc_optimize_for_linear) {
8066 unsigned i, base = key->ps_prolog.num_input_sgprs;
8067 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
8068
8069 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
8070 * The hw doesn't compute CENTROID if the whole wave only
8071 * contains fully-covered quads.
8072 *
8073 * PRIM_MASK is after user SGPRs.
8074 */
8075 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
8076 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
8077 LLVMConstInt(ctx->i32, 31, 0), "");
8078 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
8079 ctx->i1, "");
8080
8081 if (key->ps_prolog.states.bc_optimize_for_persp) {
8082 /* Read PERSP_CENTER. */
8083 for (i = 0; i < 2; i++)
8084 center[i] = LLVMGetParam(func, base + 2 + i);
8085 /* Read PERSP_CENTROID. */
8086 for (i = 0; i < 2; i++)
8087 centroid[i] = LLVMGetParam(func, base + 4 + i);
8088 /* Select PERSP_CENTROID. */
8089 for (i = 0; i < 2; i++) {
8090 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
8091 center[i], centroid[i], "");
8092 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8093 tmp, base + 4 + i, "");
8094 }
8095 }
8096 if (key->ps_prolog.states.bc_optimize_for_linear) {
8097 /* Read LINEAR_CENTER. */
8098 for (i = 0; i < 2; i++)
8099 center[i] = LLVMGetParam(func, base + 8 + i);
8100 /* Read LINEAR_CENTROID. */
8101 for (i = 0; i < 2; i++)
8102 centroid[i] = LLVMGetParam(func, base + 10 + i);
8103 /* Select LINEAR_CENTROID. */
8104 for (i = 0; i < 2; i++) {
8105 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
8106 center[i], centroid[i], "");
8107 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8108 tmp, base + 10 + i, "");
8109 }
8110 }
8111 }
8112
8113 /* Force per-sample interpolation. */
8114 if (key->ps_prolog.states.force_persp_sample_interp) {
8115 unsigned i, base = key->ps_prolog.num_input_sgprs;
8116 LLVMValueRef persp_sample[2];
8117
8118 /* Read PERSP_SAMPLE. */
8119 for (i = 0; i < 2; i++)
8120 persp_sample[i] = LLVMGetParam(func, base + i);
8121 /* Overwrite PERSP_CENTER. */
8122 for (i = 0; i < 2; i++)
8123 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8124 persp_sample[i], base + 2 + i, "");
8125 /* Overwrite PERSP_CENTROID. */
8126 for (i = 0; i < 2; i++)
8127 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8128 persp_sample[i], base + 4 + i, "");
8129 }
8130 if (key->ps_prolog.states.force_linear_sample_interp) {
8131 unsigned i, base = key->ps_prolog.num_input_sgprs;
8132 LLVMValueRef linear_sample[2];
8133
8134 /* Read LINEAR_SAMPLE. */
8135 for (i = 0; i < 2; i++)
8136 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
8137 /* Overwrite LINEAR_CENTER. */
8138 for (i = 0; i < 2; i++)
8139 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8140 linear_sample[i], base + 8 + i, "");
8141 /* Overwrite LINEAR_CENTROID. */
8142 for (i = 0; i < 2; i++)
8143 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8144 linear_sample[i], base + 10 + i, "");
8145 }
8146
8147 /* Force center interpolation. */
8148 if (key->ps_prolog.states.force_persp_center_interp) {
8149 unsigned i, base = key->ps_prolog.num_input_sgprs;
8150 LLVMValueRef persp_center[2];
8151
8152 /* Read PERSP_CENTER. */
8153 for (i = 0; i < 2; i++)
8154 persp_center[i] = LLVMGetParam(func, base + 2 + i);
8155 /* Overwrite PERSP_SAMPLE. */
8156 for (i = 0; i < 2; i++)
8157 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8158 persp_center[i], base + i, "");
8159 /* Overwrite PERSP_CENTROID. */
8160 for (i = 0; i < 2; i++)
8161 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8162 persp_center[i], base + 4 + i, "");
8163 }
8164 if (key->ps_prolog.states.force_linear_center_interp) {
8165 unsigned i, base = key->ps_prolog.num_input_sgprs;
8166 LLVMValueRef linear_center[2];
8167
8168 /* Read LINEAR_CENTER. */
8169 for (i = 0; i < 2; i++)
8170 linear_center[i] = LLVMGetParam(func, base + 8 + i);
8171 /* Overwrite LINEAR_SAMPLE. */
8172 for (i = 0; i < 2; i++)
8173 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8174 linear_center[i], base + 6 + i, "");
8175 /* Overwrite LINEAR_CENTROID. */
8176 for (i = 0; i < 2; i++)
8177 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8178 linear_center[i], base + 10 + i, "");
8179 }
8180
8181 /* Interpolate colors. */
8182 for (i = 0; i < 2; i++) {
8183 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
8184 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
8185 key->ps_prolog.face_vgpr_index;
8186 LLVMValueRef interp[2], color[4];
8187 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
8188
8189 if (!writemask)
8190 continue;
8191
8192 /* If the interpolation qualifier is not CONSTANT (-1). */
8193 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
8194 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
8195 key->ps_prolog.color_interp_vgpr_index[i];
8196
8197 /* Get the (i,j) updated by bc_optimize handling. */
8198 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
8199 interp_vgpr, "");
8200 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
8201 interp_vgpr + 1, "");
8202 interp_ij = lp_build_gather_values(gallivm, interp, 2);
8203 }
8204
8205 /* Use the absolute location of the input. */
8206 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
8207
8208 if (key->ps_prolog.states.color_two_side) {
8209 face = LLVMGetParam(func, face_vgpr);
8210 face = LLVMBuildBitCast(gallivm->builder, face, ctx->i32, "");
8211 }
8212
8213 interp_fs_input(ctx,
8214 key->ps_prolog.color_attr_index[i],
8215 TGSI_SEMANTIC_COLOR, i,
8216 key->ps_prolog.num_interp_inputs,
8217 key->ps_prolog.colors_read, interp_ij,
8218 prim_mask, face, color);
8219
8220 while (writemask) {
8221 unsigned chan = u_bit_scan(&writemask);
8222 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
8223 num_params++, "");
8224 }
8225 }
8226
8227 /* Tell LLVM to insert WQM instruction sequence when needed. */
8228 if (key->ps_prolog.wqm) {
8229 LLVMAddTargetDependentFunctionAttr(func,
8230 "amdgpu-ps-wqm-outputs", "");
8231 }
8232
8233 si_llvm_build_ret(ctx, ret);
8234 }
8235
8236 /**
8237 * Build the pixel shader epilog function. This handles everything that must be
8238 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
8239 */
8240 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
8241 union si_shader_part_key *key)
8242 {
8243 struct gallivm_state *gallivm = &ctx->gallivm;
8244 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
8245 LLVMTypeRef params[16+8*4+3];
8246 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
8247 int last_sgpr, num_params, i;
8248 struct si_ps_exports exp = {};
8249
8250 /* Declare input SGPRs. */
8251 params[SI_PARAM_RW_BUFFERS] = ctx->i64;
8252 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
8253 params[SI_PARAM_SAMPLERS] = ctx->i64;
8254 params[SI_PARAM_IMAGES] = ctx->i64;
8255 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
8256 params[SI_PARAM_ALPHA_REF] = ctx->f32;
8257 last_sgpr = SI_PARAM_ALPHA_REF;
8258
8259 /* Declare input VGPRs. */
8260 num_params = (last_sgpr + 1) +
8261 util_bitcount(key->ps_epilog.colors_written) * 4 +
8262 key->ps_epilog.writes_z +
8263 key->ps_epilog.writes_stencil +
8264 key->ps_epilog.writes_samplemask;
8265
8266 num_params = MAX2(num_params,
8267 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
8268
8269 assert(num_params <= ARRAY_SIZE(params));
8270
8271 for (i = last_sgpr + 1; i < num_params; i++)
8272 params[i] = ctx->f32;
8273
8274 /* Create the function. */
8275 si_create_function(ctx, "ps_epilog", NULL, 0, params, num_params, last_sgpr);
8276 /* Disable elimination of unused inputs. */
8277 si_llvm_add_attribute(ctx->main_fn,
8278 "InitialPSInputAddr", 0xffffff);
8279
8280 /* Process colors. */
8281 unsigned vgpr = last_sgpr + 1;
8282 unsigned colors_written = key->ps_epilog.colors_written;
8283 int last_color_export = -1;
8284
8285 /* Find the last color export. */
8286 if (!key->ps_epilog.writes_z &&
8287 !key->ps_epilog.writes_stencil &&
8288 !key->ps_epilog.writes_samplemask) {
8289 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
8290
8291 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
8292 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
8293 /* Just set this if any of the colorbuffers are enabled. */
8294 if (spi_format &
8295 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
8296 last_color_export = 0;
8297 } else {
8298 for (i = 0; i < 8; i++)
8299 if (colors_written & (1 << i) &&
8300 (spi_format >> (i * 4)) & 0xf)
8301 last_color_export = i;
8302 }
8303 }
8304
8305 while (colors_written) {
8306 LLVMValueRef color[4];
8307 int mrt = u_bit_scan(&colors_written);
8308
8309 for (i = 0; i < 4; i++)
8310 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
8311
8312 si_export_mrt_color(bld_base, color, mrt,
8313 num_params - 1,
8314 mrt == last_color_export, &exp);
8315 }
8316
8317 /* Process depth, stencil, samplemask. */
8318 if (key->ps_epilog.writes_z)
8319 depth = LLVMGetParam(ctx->main_fn, vgpr++);
8320 if (key->ps_epilog.writes_stencil)
8321 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
8322 if (key->ps_epilog.writes_samplemask)
8323 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
8324
8325 if (depth || stencil || samplemask)
8326 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
8327 else if (last_color_export == -1)
8328 si_export_null(bld_base);
8329
8330 if (exp.num)
8331 si_emit_ps_exports(ctx, &exp);
8332
8333 /* Compile. */
8334 LLVMBuildRetVoid(gallivm->builder);
8335 }
8336
8337 /**
8338 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
8339 */
8340 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
8341 LLVMTargetMachineRef tm,
8342 struct si_shader *shader,
8343 struct pipe_debug_callback *debug)
8344 {
8345 union si_shader_part_key prolog_key;
8346 union si_shader_part_key epilog_key;
8347
8348 /* Get the prolog. */
8349 si_get_ps_prolog_key(shader, &prolog_key, true);
8350
8351 /* The prolog is a no-op if these aren't set. */
8352 if (si_need_ps_prolog(&prolog_key)) {
8353 shader->prolog =
8354 si_get_shader_part(sscreen, &sscreen->ps_prologs,
8355 PIPE_SHADER_FRAGMENT, true,
8356 &prolog_key, tm, debug,
8357 si_build_ps_prolog_function,
8358 "Fragment Shader Prolog");
8359 if (!shader->prolog)
8360 return false;
8361 }
8362
8363 /* Get the epilog. */
8364 si_get_ps_epilog_key(shader, &epilog_key);
8365
8366 shader->epilog =
8367 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
8368 PIPE_SHADER_FRAGMENT, false,
8369 &epilog_key, tm, debug,
8370 si_build_ps_epilog_function,
8371 "Fragment Shader Epilog");
8372 if (!shader->epilog)
8373 return false;
8374
8375 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
8376 if (shader->key.part.ps.prolog.poly_stipple) {
8377 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
8378 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
8379 }
8380
8381 /* Set up the enable bits for per-sample shading if needed. */
8382 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
8383 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8384 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8385 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
8386 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8387 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
8388 }
8389 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
8390 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8391 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8392 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
8393 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8394 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
8395 }
8396 if (shader->key.part.ps.prolog.force_persp_center_interp &&
8397 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8398 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8399 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
8400 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8401 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8402 }
8403 if (shader->key.part.ps.prolog.force_linear_center_interp &&
8404 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8405 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8406 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
8407 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8408 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8409 }
8410
8411 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
8412 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
8413 !(shader->config.spi_ps_input_ena & 0xf)) {
8414 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8415 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
8416 }
8417
8418 /* At least one pair of interpolation weights must be enabled. */
8419 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
8420 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8421 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
8422 }
8423
8424 /* The sample mask input is always enabled, because the API shader always
8425 * passes it through to the epilog. Disable it here if it's unused.
8426 */
8427 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
8428 !shader->selector->info.reads_samplemask)
8429 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
8430
8431 return true;
8432 }
8433
8434 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
8435 unsigned *lds_size)
8436 {
8437 /* SPI barrier management bug:
8438 * Make sure we have at least 4k of LDS in use to avoid the bug.
8439 * It applies to workgroup sizes of more than one wavefront.
8440 */
8441 if (sscreen->b.family == CHIP_BONAIRE ||
8442 sscreen->b.family == CHIP_KABINI ||
8443 sscreen->b.family == CHIP_MULLINS)
8444 *lds_size = MAX2(*lds_size, 8);
8445 }
8446
8447 static void si_fix_resource_usage(struct si_screen *sscreen,
8448 struct si_shader *shader)
8449 {
8450 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
8451
8452 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
8453
8454 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
8455 si_get_max_workgroup_size(shader) > 64) {
8456 si_multiwave_lds_size_workaround(sscreen,
8457 &shader->config.lds_size);
8458 }
8459 }
8460
8461 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
8462 struct si_shader *shader,
8463 struct pipe_debug_callback *debug)
8464 {
8465 struct si_shader_selector *sel = shader->selector;
8466 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
8467 int r;
8468
8469 /* LS, ES, VS are compiled on demand if the main part hasn't been
8470 * compiled for that stage.
8471 *
8472 * Vertex shaders are compiled on demand when a vertex fetch
8473 * workaround must be applied.
8474 */
8475 if (shader->is_monolithic) {
8476 /* Monolithic shader (compiled as a whole, has many variants,
8477 * may take a long time to compile).
8478 */
8479 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
8480 if (r)
8481 return r;
8482 } else {
8483 /* The shader consists of 2-3 parts:
8484 *
8485 * - the middle part is the user shader, it has 1 variant only
8486 * and it was compiled during the creation of the shader
8487 * selector
8488 * - the prolog part is inserted at the beginning
8489 * - the epilog part is inserted at the end
8490 *
8491 * The prolog and epilog have many (but simple) variants.
8492 */
8493
8494 /* Copy the compiled TGSI shader data over. */
8495 shader->is_binary_shared = true;
8496 shader->binary = mainp->binary;
8497 shader->config = mainp->config;
8498 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8499 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8500 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8501 memcpy(shader->info.vs_output_param_offset,
8502 mainp->info.vs_output_param_offset,
8503 sizeof(mainp->info.vs_output_param_offset));
8504 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8505 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8506 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8507
8508 /* Select prologs and/or epilogs. */
8509 switch (sel->type) {
8510 case PIPE_SHADER_VERTEX:
8511 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
8512 return -1;
8513 break;
8514 case PIPE_SHADER_TESS_CTRL:
8515 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
8516 return -1;
8517 break;
8518 case PIPE_SHADER_TESS_EVAL:
8519 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
8520 return -1;
8521 break;
8522 case PIPE_SHADER_GEOMETRY:
8523 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
8524 return -1;
8525 break;
8526 case PIPE_SHADER_FRAGMENT:
8527 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8528 return -1;
8529
8530 /* Make sure we have at least as many VGPRs as there
8531 * are allocated inputs.
8532 */
8533 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8534 shader->info.num_input_vgprs);
8535 break;
8536 }
8537
8538 /* Update SGPR and VGPR counts. */
8539 if (shader->prolog) {
8540 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8541 shader->prolog->config.num_sgprs);
8542 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8543 shader->prolog->config.num_vgprs);
8544 }
8545 if (shader->epilog) {
8546 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8547 shader->epilog->config.num_sgprs);
8548 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8549 shader->epilog->config.num_vgprs);
8550 }
8551 }
8552
8553 si_fix_resource_usage(sscreen, shader);
8554 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8555 stderr, true);
8556
8557 /* Upload. */
8558 r = si_shader_binary_upload(sscreen, shader);
8559 if (r) {
8560 fprintf(stderr, "LLVM failed to upload shader\n");
8561 return r;
8562 }
8563
8564 return 0;
8565 }
8566
8567 void si_shader_destroy(struct si_shader *shader)
8568 {
8569 if (shader->scratch_bo)
8570 r600_resource_reference(&shader->scratch_bo, NULL);
8571
8572 r600_resource_reference(&shader->bo, NULL);
8573
8574 if (!shader->is_binary_shared)
8575 radeon_shader_binary_clean(&shader->binary);
8576
8577 free(shader->shader_log);
8578 }