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radeonsi: Pass VS resource descriptors to the HW ES shader stage as well
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "radeon_llvm.h"
36 #include "radeon_llvm_emit.h"
37 #include "util/u_memory.h"
38 #include "tgsi/tgsi_parse.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "si_pipe.h"
43 #include "si_shader.h"
44 #include "sid.h"
45
46 #include <errno.h>
47
48 struct si_shader_output_values
49 {
50 LLVMValueRef values[4];
51 unsigned name;
52 unsigned index;
53 unsigned sid;
54 unsigned usage;
55 };
56
57 struct si_shader_context
58 {
59 struct radeon_llvm_context radeon_bld;
60 struct tgsi_parse_context parse;
61 struct tgsi_token * tokens;
62 struct si_pipe_shader *shader;
63 struct si_shader *gs_for_vs;
64 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
65 int param_streamout_config;
66 int param_streamout_write_index;
67 int param_streamout_offset[4];
68 int param_vertex_id;
69 int param_instance_id;
70 LLVMValueRef const_md;
71 LLVMValueRef const_resource[NUM_CONST_BUFFERS];
72 #if HAVE_LLVM >= 0x0304
73 LLVMValueRef ddxy_lds;
74 #endif
75 LLVMValueRef *constants[NUM_CONST_BUFFERS];
76 LLVMValueRef *resources;
77 LLVMValueRef *samplers;
78 LLVMValueRef so_buffers[4];
79 LLVMValueRef gs_next_vertex;
80 };
81
82 static struct si_shader_context * si_shader_context(
83 struct lp_build_tgsi_context * bld_base)
84 {
85 return (struct si_shader_context *)bld_base;
86 }
87
88
89 #define PERSPECTIVE_BASE 0
90 #define LINEAR_BASE 9
91
92 #define SAMPLE_OFFSET 0
93 #define CENTER_OFFSET 2
94 #define CENTROID_OFSET 4
95
96 #define USE_SGPR_MAX_SUFFIX_LEN 5
97 #define CONST_ADDR_SPACE 2
98 #define LOCAL_ADDR_SPACE 3
99 #define USER_SGPR_ADDR_SPACE 8
100
101
102 #define SENDMSG_GS 2
103 #define SENDMSG_GS_DONE 3
104
105 #define SENDMSG_GS_OP_NOP (0 << 4)
106 #define SENDMSG_GS_OP_CUT (1 << 4)
107 #define SENDMSG_GS_OP_EMIT (2 << 4)
108 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
109
110
111 /**
112 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
113 *
114 * @param offset The offset parameter specifies the number of
115 * elements to offset, not the number of bytes or dwords. An element is the
116 * the type pointed to by the base_ptr parameter (e.g. int is the element of
117 * an int* pointer)
118 *
119 * When LLVM lowers the load instruction, it will convert the element offset
120 * into a dword offset automatically.
121 *
122 */
123 static LLVMValueRef build_indexed_load(
124 struct si_shader_context * si_shader_ctx,
125 LLVMValueRef base_ptr,
126 LLVMValueRef offset)
127 {
128 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
129
130 LLVMValueRef indices[2] = {
131 LLVMConstInt(LLVMInt64TypeInContext(base->gallivm->context), 0, false),
132 offset
133 };
134 LLVMValueRef computed_ptr = LLVMBuildGEP(
135 base->gallivm->builder, base_ptr, indices, 2, "");
136
137 LLVMValueRef result = LLVMBuildLoad(base->gallivm->builder, computed_ptr, "");
138 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
139 return result;
140 }
141
142 static LLVMValueRef get_instance_index_for_fetch(
143 struct radeon_llvm_context * radeon_bld,
144 unsigned divisor)
145 {
146 struct si_shader_context *si_shader_ctx =
147 si_shader_context(&radeon_bld->soa.bld_base);
148 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
149
150 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
151 si_shader_ctx->param_instance_id);
152 result = LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
153 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
154
155 if (divisor > 1)
156 result = LLVMBuildUDiv(gallivm->builder, result,
157 lp_build_const_int32(gallivm, divisor), "");
158
159 return result;
160 }
161
162 static int si_store_shader_io_attribs(struct si_shader *shader,
163 const struct tgsi_full_declaration *d)
164 {
165 int i = -1;
166
167 switch (d->Declaration.File) {
168 case TGSI_FILE_INPUT:
169 i = shader->ninput++;
170 assert(i < Elements(shader->input));
171 shader->input[i].name = d->Semantic.Name;
172 shader->input[i].sid = d->Semantic.Index;
173 shader->input[i].index = d->Range.First;
174 shader->input[i].interpolate = d->Interp.Interpolate;
175 shader->input[i].centroid = d->Interp.Centroid;
176 return -1;
177
178 case TGSI_FILE_OUTPUT:
179 i = shader->noutput++;
180 assert(i < Elements(shader->output));
181 shader->output[i].name = d->Semantic.Name;
182 shader->output[i].sid = d->Semantic.Index;
183 shader->output[i].index = d->Range.First;
184 shader->output[i].usage = d->Declaration.UsageMask;
185 break;
186 }
187
188 return i;
189 }
190
191 static void declare_input_vs(
192 struct radeon_llvm_context *radeon_bld,
193 unsigned input_index,
194 const struct tgsi_full_declaration *decl)
195 {
196 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
197 struct gallivm_state *gallivm = base->gallivm;
198 struct si_shader_context *si_shader_ctx =
199 si_shader_context(&radeon_bld->soa.bld_base);
200 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
201
202 unsigned chan;
203
204 LLVMValueRef t_list_ptr;
205 LLVMValueRef t_offset;
206 LLVMValueRef t_list;
207 LLVMValueRef attribute_offset;
208 LLVMValueRef buffer_index;
209 LLVMValueRef args[3];
210 LLVMTypeRef vec4_type;
211 LLVMValueRef input;
212
213 /* Load the T list */
214 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
215
216 t_offset = lp_build_const_int32(gallivm, input_index);
217
218 t_list = build_indexed_load(si_shader_ctx, t_list_ptr, t_offset);
219
220 /* Build the attribute offset */
221 attribute_offset = lp_build_const_int32(gallivm, 0);
222
223 if (divisor) {
224 /* Build index from instance ID, start instance and divisor */
225 si_shader_ctx->shader->shader.uses_instanceid = true;
226 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
227 } else {
228 /* Load the buffer index, which is always stored in VGPR0
229 * for Vertex Shaders */
230 buffer_index = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
231 si_shader_ctx->param_vertex_id);
232 }
233
234 vec4_type = LLVMVectorType(base->elem_type, 4);
235 args[0] = t_list;
236 args[1] = attribute_offset;
237 args[2] = buffer_index;
238 input = build_intrinsic(gallivm->builder,
239 "llvm.SI.vs.load.input", vec4_type, args, 3,
240 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
241
242 /* Break up the vec4 into individual components */
243 for (chan = 0; chan < 4; chan++) {
244 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
245 /* XXX: Use a helper function for this. There is one in
246 * tgsi_llvm.c. */
247 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
248 LLVMBuildExtractElement(gallivm->builder,
249 input, llvm_chan, "");
250 }
251 }
252
253 static void declare_input_gs(
254 struct radeon_llvm_context *radeon_bld,
255 unsigned input_index,
256 const struct tgsi_full_declaration *decl)
257 {
258 struct si_shader_context *si_shader_ctx =
259 si_shader_context(&radeon_bld->soa.bld_base);
260 struct si_shader *shader = &si_shader_ctx->shader->shader;
261
262 si_store_shader_io_attribs(shader, decl);
263
264 if (decl->Semantic.Name != TGSI_SEMANTIC_PRIMID)
265 shader->input[input_index].param_offset = shader->nparam++;
266 }
267
268 static LLVMValueRef fetch_input_gs(
269 struct lp_build_tgsi_context *bld_base,
270 const struct tgsi_full_src_register *reg,
271 enum tgsi_opcode_type type,
272 unsigned swizzle)
273 {
274 struct lp_build_context *base = &bld_base->base;
275 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
276 struct si_shader *shader = &si_shader_ctx->shader->shader;
277 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
278 struct gallivm_state *gallivm = base->gallivm;
279 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
280 LLVMValueRef vtx_offset;
281 LLVMValueRef t_list_ptr;
282 LLVMValueRef t_list;
283 LLVMValueRef args[9];
284 unsigned vtx_offset_param;
285
286 if (swizzle != ~0 &&
287 shader->input[reg->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
288 if (swizzle == 0)
289 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
290 SI_PARAM_PRIMITIVE_ID);
291 else
292 return uint->zero;
293 }
294
295 if (!reg->Register.Dimension)
296 return NULL;
297
298 if (swizzle == ~0) {
299 LLVMValueRef values[TGSI_NUM_CHANNELS];
300 unsigned chan;
301 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
302 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
303 }
304 return lp_build_gather_values(bld_base->base.gallivm, values,
305 TGSI_NUM_CHANNELS);
306 }
307
308 /* Get the vertex offset parameter */
309 vtx_offset_param = reg->Dimension.Index;
310 if (vtx_offset_param < 2) {
311 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
312 } else {
313 assert(vtx_offset_param < 6);
314 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
315 }
316 vtx_offset = lp_build_mul_imm(uint,
317 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
318 vtx_offset_param),
319 4);
320
321 /* Load the ESGS ring resource descriptor */
322 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
323 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
324 lp_build_const_int32(gallivm, SI_RING_ESGS));
325
326 args[0] = t_list;
327 args[1] = vtx_offset;
328 args[2] = lp_build_const_int32(gallivm,
329 ((shader->input[reg->Register.Index].param_offset * 4) +
330 swizzle) * 256);
331 args[3] = uint->zero;
332 args[4] = uint->one; /* OFFEN */
333 args[5] = uint->zero; /* IDXEN */
334 args[6] = uint->one; /* GLC */
335 args[7] = uint->zero; /* SLC */
336 args[8] = uint->zero; /* TFE */
337
338 return LLVMBuildBitCast(gallivm->builder,
339 build_intrinsic(gallivm->builder,
340 "llvm.SI.buffer.load.dword.i32.i32",
341 i32, args, 9,
342 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
343 tgsi2llvmtype(bld_base, type), "");
344 }
345
346 static void declare_input_fs(
347 struct radeon_llvm_context *radeon_bld,
348 unsigned input_index,
349 const struct tgsi_full_declaration *decl)
350 {
351 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
352 struct si_shader_context *si_shader_ctx =
353 si_shader_context(&radeon_bld->soa.bld_base);
354 struct si_shader *shader = &si_shader_ctx->shader->shader;
355 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
356 struct gallivm_state *gallivm = base->gallivm;
357 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
358 LLVMValueRef main_fn = radeon_bld->main_fn;
359
360 LLVMValueRef interp_param;
361 const char * intr_name;
362
363 /* This value is:
364 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
365 * quad begins a new primitive. Bit 0 always needs
366 * to be unset)
367 * [32:16] ParamOffset
368 *
369 */
370 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
371 LLVMValueRef attr_number;
372
373 unsigned chan;
374
375 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
376 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
377 unsigned soa_index =
378 radeon_llvm_reg_index_soa(input_index, chan);
379 radeon_bld->inputs[soa_index] =
380 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
381
382 if (chan == 3)
383 /* RCP for fragcoord.w */
384 radeon_bld->inputs[soa_index] =
385 LLVMBuildFDiv(gallivm->builder,
386 lp_build_const_float(gallivm, 1.0f),
387 radeon_bld->inputs[soa_index],
388 "");
389 }
390 return;
391 }
392
393 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
394 LLVMValueRef face, is_face_positive;
395
396 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
397
398 is_face_positive = LLVMBuildFCmp(gallivm->builder,
399 LLVMRealUGT, face,
400 lp_build_const_float(gallivm, 0.0f),
401 "");
402
403 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
404 LLVMBuildSelect(gallivm->builder,
405 is_face_positive,
406 lp_build_const_float(gallivm, 1.0f),
407 lp_build_const_float(gallivm, 0.0f),
408 "");
409 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
410 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
411 lp_build_const_float(gallivm, 0.0f);
412 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
413 lp_build_const_float(gallivm, 1.0f);
414
415 return;
416 }
417
418 shader->input[input_index].param_offset = shader->nparam++;
419 attr_number = lp_build_const_int32(gallivm,
420 shader->input[input_index].param_offset);
421
422 switch (decl->Interp.Interpolate) {
423 case TGSI_INTERPOLATE_COLOR:
424 if (si_shader_ctx->shader->key.ps.flatshade) {
425 interp_param = 0;
426 } else {
427 if (decl->Interp.Centroid)
428 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
429 else
430 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
431 }
432 break;
433 case TGSI_INTERPOLATE_CONSTANT:
434 interp_param = 0;
435 break;
436 case TGSI_INTERPOLATE_LINEAR:
437 if (decl->Interp.Centroid)
438 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
439 else
440 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
441 break;
442 case TGSI_INTERPOLATE_PERSPECTIVE:
443 if (decl->Interp.Centroid)
444 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
445 else
446 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
447 break;
448 default:
449 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
450 return;
451 }
452
453 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
454
455 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
456 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
457 si_shader_ctx->shader->key.ps.color_two_side) {
458 LLVMValueRef args[4];
459 LLVMValueRef face, is_face_positive;
460 LLVMValueRef back_attr_number =
461 lp_build_const_int32(gallivm,
462 shader->input[input_index].param_offset + 1);
463
464 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
465
466 is_face_positive = LLVMBuildFCmp(gallivm->builder,
467 LLVMRealUGT, face,
468 lp_build_const_float(gallivm, 0.0f),
469 "");
470
471 args[2] = params;
472 args[3] = interp_param;
473 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
474 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
475 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
476 LLVMValueRef front, back;
477
478 args[0] = llvm_chan;
479 args[1] = attr_number;
480 front = build_intrinsic(gallivm->builder, intr_name,
481 input_type, args, args[3] ? 4 : 3,
482 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
483
484 args[1] = back_attr_number;
485 back = build_intrinsic(gallivm->builder, intr_name,
486 input_type, args, args[3] ? 4 : 3,
487 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
488
489 radeon_bld->inputs[soa_index] =
490 LLVMBuildSelect(gallivm->builder,
491 is_face_positive,
492 front,
493 back,
494 "");
495 }
496
497 shader->nparam++;
498 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
499 LLVMValueRef args[4];
500
501 args[0] = uint->zero;
502 args[1] = attr_number;
503 args[2] = params;
504 args[3] = interp_param;
505 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
506 build_intrinsic(gallivm->builder, intr_name,
507 input_type, args, args[3] ? 4 : 3,
508 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
509 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
510 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
511 lp_build_const_float(gallivm, 0.0f);
512 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
513 lp_build_const_float(gallivm, 1.0f);
514 } else {
515 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
516 LLVMValueRef args[4];
517 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
518 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
519 args[0] = llvm_chan;
520 args[1] = attr_number;
521 args[2] = params;
522 args[3] = interp_param;
523 radeon_bld->inputs[soa_index] =
524 build_intrinsic(gallivm->builder, intr_name,
525 input_type, args, args[3] ? 4 : 3,
526 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
527 }
528 }
529 }
530
531 static void declare_system_value(
532 struct radeon_llvm_context * radeon_bld,
533 unsigned index,
534 const struct tgsi_full_declaration *decl)
535 {
536 struct si_shader_context *si_shader_ctx =
537 si_shader_context(&radeon_bld->soa.bld_base);
538 LLVMValueRef value = 0;
539
540 switch (decl->Semantic.Name) {
541 case TGSI_SEMANTIC_INSTANCEID:
542 value = LLVMGetParam(radeon_bld->main_fn,
543 si_shader_ctx->param_instance_id);
544 break;
545
546 case TGSI_SEMANTIC_VERTEXID:
547 value = LLVMGetParam(radeon_bld->main_fn,
548 si_shader_ctx->param_vertex_id);
549 break;
550
551 default:
552 assert(!"unknown system value");
553 return;
554 }
555
556 radeon_bld->system_values[index] = value;
557 }
558
559 static LLVMValueRef fetch_constant(
560 struct lp_build_tgsi_context * bld_base,
561 const struct tgsi_full_src_register *reg,
562 enum tgsi_opcode_type type,
563 unsigned swizzle)
564 {
565 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
566 struct lp_build_context * base = &bld_base->base;
567 const struct tgsi_ind_register *ireg = &reg->Indirect;
568 unsigned buf, idx;
569
570 LLVMValueRef args[2];
571 LLVMValueRef addr;
572 LLVMValueRef result;
573
574 if (swizzle == LP_CHAN_ALL) {
575 unsigned chan;
576 LLVMValueRef values[4];
577 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
578 values[chan] = fetch_constant(bld_base, reg, type, chan);
579
580 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
581 }
582
583 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
584 idx = reg->Register.Index * 4 + swizzle;
585
586 if (!reg->Register.Indirect)
587 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
588
589 args[0] = si_shader_ctx->const_resource[buf];
590 args[1] = lp_build_const_int32(base->gallivm, idx * 4);
591 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
592 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
593 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
594 args[1] = lp_build_add(&bld_base->uint_bld, addr, args[1]);
595
596 result = build_intrinsic(base->gallivm->builder, "llvm.SI.load.const", base->elem_type,
597 args, 2, LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
598
599 return bitcast(bld_base, type, result);
600 }
601
602 /* Initialize arguments for the shader export intrinsic */
603 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
604 LLVMValueRef *values,
605 unsigned target,
606 LLVMValueRef *args)
607 {
608 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
609 struct lp_build_context *uint =
610 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
611 struct lp_build_context *base = &bld_base->base;
612 unsigned compressed = 0;
613 unsigned chan;
614
615 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
616 int cbuf = target - V_008DFC_SQ_EXP_MRT;
617
618 if (cbuf >= 0 && cbuf < 8) {
619 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
620
621 if (compressed)
622 si_shader_ctx->shader->spi_shader_col_format |=
623 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
624 else
625 si_shader_ctx->shader->spi_shader_col_format |=
626 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
627
628 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
629 }
630 }
631
632 if (compressed) {
633 /* Pixel shader needs to pack output values before export */
634 for (chan = 0; chan < 2; chan++ ) {
635 args[0] = values[2 * chan];
636 args[1] = values[2 * chan + 1];
637 args[chan + 5] =
638 build_intrinsic(base->gallivm->builder,
639 "llvm.SI.packf16",
640 LLVMInt32TypeInContext(base->gallivm->context),
641 args, 2,
642 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
643 args[chan + 7] = args[chan + 5] =
644 LLVMBuildBitCast(base->gallivm->builder,
645 args[chan + 5],
646 LLVMFloatTypeInContext(base->gallivm->context),
647 "");
648 }
649
650 /* Set COMPR flag */
651 args[4] = uint->one;
652 } else {
653 for (chan = 0; chan < 4; chan++ )
654 /* +5 because the first output value will be
655 * the 6th argument to the intrinsic. */
656 args[chan + 5] = values[chan];
657
658 /* Clear COMPR flag */
659 args[4] = uint->zero;
660 }
661
662 /* XXX: This controls which components of the output
663 * registers actually get exported. (e.g bit 0 means export
664 * X component, bit 1 means export Y component, etc.) I'm
665 * hard coding this to 0xf for now. In the future, we might
666 * want to do something else. */
667 args[0] = lp_build_const_int32(base->gallivm, 0xf);
668
669 /* Specify whether the EXEC mask represents the valid mask */
670 args[1] = uint->zero;
671
672 /* Specify whether this is the last export */
673 args[2] = uint->zero;
674
675 /* Specify the target we are exporting */
676 args[3] = lp_build_const_int32(base->gallivm, target);
677
678 /* XXX: We probably need to keep track of the output
679 * values, so we know what we are passing to the next
680 * stage. */
681 }
682
683 /* Load from output pointers and initialize arguments for the shader export intrinsic */
684 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
685 LLVMValueRef *out_ptr,
686 unsigned target,
687 LLVMValueRef *args)
688 {
689 struct gallivm_state *gallivm = bld_base->base.gallivm;
690 LLVMValueRef values[4];
691 int i;
692
693 for (i = 0; i < 4; i++)
694 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
695
696 si_llvm_init_export_args(bld_base, values, target, args);
697 }
698
699 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
700 LLVMValueRef *out_ptr)
701 {
702 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
703 struct gallivm_state *gallivm = bld_base->base.gallivm;
704
705 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
706 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
707 SI_PARAM_ALPHA_REF);
708
709 LLVMValueRef alpha_pass =
710 lp_build_cmp(&bld_base->base,
711 si_shader_ctx->shader->key.ps.alpha_func,
712 LLVMBuildLoad(gallivm->builder, out_ptr[3], ""),
713 alpha_ref);
714 LLVMValueRef arg =
715 lp_build_select(&bld_base->base,
716 alpha_pass,
717 lp_build_const_float(gallivm, 1.0f),
718 lp_build_const_float(gallivm, -1.0f));
719
720 build_intrinsic(gallivm->builder,
721 "llvm.AMDGPU.kill",
722 LLVMVoidTypeInContext(gallivm->context),
723 &arg, 1, 0);
724 } else {
725 build_intrinsic(gallivm->builder,
726 "llvm.AMDGPU.kilp",
727 LLVMVoidTypeInContext(gallivm->context),
728 NULL, 0, 0);
729 }
730 }
731
732 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
733 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
734 {
735 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
736 struct si_pipe_shader *shader = si_shader_ctx->shader;
737 struct lp_build_context *base = &bld_base->base;
738 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
739 unsigned reg_index;
740 unsigned chan;
741 unsigned const_chan;
742 LLVMValueRef base_elt;
743 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
744 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, NUM_PIPE_CONST_BUFFERS);
745 LLVMValueRef const_resource = build_indexed_load(si_shader_ctx, ptr, constbuf_index);
746
747 for (reg_index = 0; reg_index < 2; reg_index ++) {
748 LLVMValueRef *args = pos[2 + reg_index];
749
750 if (!(shader->key.vs.ucps_enabled & (1 << reg_index)))
751 continue;
752
753 shader->shader.clip_dist_write |= 0xf << (4 * reg_index);
754
755 args[5] =
756 args[6] =
757 args[7] =
758 args[8] = lp_build_const_float(base->gallivm, 0.0f);
759
760 /* Compute dot products of position and user clip plane vectors */
761 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
762 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
763 args[0] = const_resource;
764 args[1] = lp_build_const_int32(base->gallivm,
765 ((reg_index * 4 + chan) * 4 +
766 const_chan) * 4);
767 base_elt = build_intrinsic(base->gallivm->builder,
768 "llvm.SI.load.const",
769 base->elem_type,
770 args, 2,
771 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
772 args[5 + chan] =
773 lp_build_add(base, args[5 + chan],
774 lp_build_mul(base, base_elt,
775 out_elts[const_chan]));
776 }
777 }
778
779 args[0] = lp_build_const_int32(base->gallivm, 0xf);
780 args[1] = uint->zero;
781 args[2] = uint->zero;
782 args[3] = lp_build_const_int32(base->gallivm,
783 V_008DFC_SQ_EXP_POS + 2 + reg_index);
784 args[4] = uint->zero;
785 }
786 }
787
788 static void si_dump_streamout(struct pipe_stream_output_info *so)
789 {
790 unsigned i;
791
792 if (so->num_outputs)
793 fprintf(stderr, "STREAMOUT\n");
794
795 for (i = 0; i < so->num_outputs; i++) {
796 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
797 so->output[i].start_component;
798 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
799 i, so->output[i].output_buffer,
800 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
801 so->output[i].register_index,
802 mask & 1 ? "x" : "",
803 mask & 2 ? "y" : "",
804 mask & 4 ? "z" : "",
805 mask & 8 ? "w" : "");
806 }
807 }
808
809 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
810 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
811 * or v4i32 (num_channels=3,4). */
812 static void build_tbuffer_store(struct si_shader_context *shader,
813 LLVMValueRef rsrc,
814 LLVMValueRef vdata,
815 unsigned num_channels,
816 LLVMValueRef vaddr,
817 LLVMValueRef soffset,
818 unsigned inst_offset,
819 unsigned dfmt,
820 unsigned nfmt,
821 unsigned offen,
822 unsigned idxen,
823 unsigned glc,
824 unsigned slc,
825 unsigned tfe)
826 {
827 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
828 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
829 LLVMValueRef args[] = {
830 rsrc,
831 vdata,
832 LLVMConstInt(i32, num_channels, 0),
833 vaddr,
834 soffset,
835 LLVMConstInt(i32, inst_offset, 0),
836 LLVMConstInt(i32, dfmt, 0),
837 LLVMConstInt(i32, nfmt, 0),
838 LLVMConstInt(i32, offen, 0),
839 LLVMConstInt(i32, idxen, 0),
840 LLVMConstInt(i32, glc, 0),
841 LLVMConstInt(i32, slc, 0),
842 LLVMConstInt(i32, tfe, 0)
843 };
844
845 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
846 unsigned func = CLAMP(num_channels, 1, 3) - 1;
847 const char *types[] = {"i32", "v2i32", "v4i32"};
848 char name[256];
849 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
850
851 lp_build_intrinsic(gallivm->builder, name,
852 LLVMVoidTypeInContext(gallivm->context),
853 args, Elements(args));
854 }
855
856 static void build_streamout_store(struct si_shader_context *shader,
857 LLVMValueRef rsrc,
858 LLVMValueRef vdata,
859 unsigned num_channels,
860 LLVMValueRef vaddr,
861 LLVMValueRef soffset,
862 unsigned inst_offset)
863 {
864 static unsigned dfmt[] = {
865 V_008F0C_BUF_DATA_FORMAT_32,
866 V_008F0C_BUF_DATA_FORMAT_32_32,
867 V_008F0C_BUF_DATA_FORMAT_32_32_32,
868 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
869 };
870 assert(num_channels >= 1 && num_channels <= 4);
871
872 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
873 inst_offset, dfmt[num_channels-1],
874 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
875 }
876
877 /* On SI, the vertex shader is responsible for writing streamout data
878 * to buffers. */
879 static void si_llvm_emit_streamout(struct si_shader_context *shader,
880 struct si_shader_output_values *outputs,
881 unsigned noutput)
882 {
883 struct pipe_stream_output_info *so = &shader->shader->selector->so;
884 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
885 LLVMBuilderRef builder = gallivm->builder;
886 int i, j;
887 struct lp_build_if_state if_ctx;
888
889 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
890
891 LLVMValueRef so_param =
892 LLVMGetParam(shader->radeon_bld.main_fn,
893 shader->param_streamout_config);
894
895 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
896 LLVMValueRef so_vtx_count =
897 LLVMBuildAnd(builder,
898 LLVMBuildLShr(builder, so_param,
899 LLVMConstInt(i32, 16, 0), ""),
900 LLVMConstInt(i32, 127, 0), "");
901
902 LLVMValueRef tid = build_intrinsic(builder, "llvm.SI.tid", i32,
903 NULL, 0, LLVMReadNoneAttribute);
904
905 /* can_emit = tid < so_vtx_count; */
906 LLVMValueRef can_emit =
907 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
908
909 /* Emit the streamout code conditionally. This actually avoids
910 * out-of-bounds buffer access. The hw tells us via the SGPR
911 * (so_vtx_count) which threads are allowed to emit streamout data. */
912 lp_build_if(&if_ctx, gallivm, can_emit);
913 {
914 /* The buffer offset is computed as follows:
915 * ByteOffset = streamout_offset[buffer_id]*4 +
916 * (streamout_write_index + thread_id)*stride[buffer_id] +
917 * attrib_offset
918 */
919
920 LLVMValueRef so_write_index =
921 LLVMGetParam(shader->radeon_bld.main_fn,
922 shader->param_streamout_write_index);
923
924 /* Compute (streamout_write_index + thread_id). */
925 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
926
927 /* Compute the write offset for each enabled buffer. */
928 LLVMValueRef so_write_offset[4] = {};
929 for (i = 0; i < 4; i++) {
930 if (!so->stride[i])
931 continue;
932
933 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
934 shader->param_streamout_offset[i]);
935 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
936
937 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
938 LLVMConstInt(i32, so->stride[i]*4, 0), "");
939 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
940 }
941
942 /* Write streamout data. */
943 for (i = 0; i < so->num_outputs; i++) {
944 unsigned buf_idx = so->output[i].output_buffer;
945 unsigned reg = so->output[i].register_index;
946 unsigned start = so->output[i].start_component;
947 unsigned num_comps = so->output[i].num_components;
948 LLVMValueRef out[4];
949
950 assert(num_comps && num_comps <= 4);
951 if (!num_comps || num_comps > 4)
952 continue;
953
954 /* Load the output as int. */
955 for (j = 0; j < num_comps; j++) {
956 unsigned outidx = 0;
957
958 while (outidx < noutput && outputs[outidx].index != reg)
959 outidx++;
960
961 if (outidx < noutput)
962 out[j] = LLVMBuildBitCast(builder,
963 outputs[outidx].values[start+j],
964 i32, "");
965 else
966 out[j] = NULL;
967 }
968
969 if (!out[0])
970 continue;
971
972 /* Pack the output. */
973 LLVMValueRef vdata = NULL;
974
975 switch (num_comps) {
976 case 1: /* as i32 */
977 vdata = out[0];
978 break;
979 case 2: /* as v2i32 */
980 case 3: /* as v4i32 (aligned to 4) */
981 case 4: /* as v4i32 */
982 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
983 for (j = 0; j < num_comps; j++) {
984 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
985 LLVMConstInt(i32, j, 0), "");
986 }
987 break;
988 }
989
990 build_streamout_store(shader, shader->so_buffers[buf_idx],
991 vdata, num_comps,
992 so_write_offset[buf_idx],
993 LLVMConstInt(i32, 0, 0),
994 so->output[i].dst_offset*4);
995 }
996 }
997 lp_build_endif(&if_ctx);
998 }
999
1000
1001 /* Generate export instructions for hardware VS shader stage */
1002 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1003 struct si_shader_output_values *outputs,
1004 unsigned noutput)
1005 {
1006 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1007 struct si_shader * shader = &si_shader_ctx->shader->shader;
1008 struct lp_build_context * base = &bld_base->base;
1009 struct lp_build_context * uint =
1010 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1011 LLVMValueRef args[9];
1012 LLVMValueRef pos_args[4][9] = { { 0 } };
1013 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL;
1014 unsigned semantic_name, semantic_index, semantic_usage;
1015 unsigned target;
1016 unsigned param_count = 0;
1017 unsigned pos_idx;
1018 int i;
1019
1020 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1021 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1022 }
1023
1024 for (i = 0; i < noutput; i++) {
1025 semantic_name = outputs[i].name;
1026 semantic_index = outputs[i].sid;
1027 semantic_usage = outputs[i].usage;
1028
1029 handle_semantic:
1030 /* Select the correct target */
1031 switch(semantic_name) {
1032 case TGSI_SEMANTIC_PSIZE:
1033 shader->vs_out_misc_write = true;
1034 shader->vs_out_point_size = true;
1035 psize_value = outputs[i].values[0];
1036 continue;
1037 case TGSI_SEMANTIC_EDGEFLAG:
1038 shader->vs_out_misc_write = true;
1039 shader->vs_out_edgeflag = true;
1040 edgeflag_value = outputs[i].values[0];
1041 continue;
1042 case TGSI_SEMANTIC_LAYER:
1043 shader->vs_out_misc_write = true;
1044 shader->vs_out_layer = true;
1045 layer_value = outputs[i].values[0];
1046 continue;
1047 case TGSI_SEMANTIC_POSITION:
1048 target = V_008DFC_SQ_EXP_POS;
1049 break;
1050 case TGSI_SEMANTIC_COLOR:
1051 case TGSI_SEMANTIC_BCOLOR:
1052 target = V_008DFC_SQ_EXP_PARAM + param_count;
1053 shader->output[i].param_offset = param_count;
1054 param_count++;
1055 break;
1056 case TGSI_SEMANTIC_CLIPDIST:
1057 if (!(si_shader_ctx->shader->key.vs.ucps_enabled &
1058 (1 << semantic_index)))
1059 continue;
1060 shader->clip_dist_write |=
1061 semantic_usage << (semantic_index << 2);
1062 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1063 break;
1064 case TGSI_SEMANTIC_CLIPVERTEX:
1065 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1066 continue;
1067 case TGSI_SEMANTIC_PRIMID:
1068 case TGSI_SEMANTIC_FOG:
1069 case TGSI_SEMANTIC_GENERIC:
1070 target = V_008DFC_SQ_EXP_PARAM + param_count;
1071 shader->output[i].param_offset = param_count;
1072 param_count++;
1073 break;
1074 default:
1075 target = 0;
1076 fprintf(stderr,
1077 "Warning: SI unhandled vs output type:%d\n",
1078 semantic_name);
1079 }
1080
1081 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1082
1083 if (target >= V_008DFC_SQ_EXP_POS &&
1084 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1085 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1086 args, sizeof(args));
1087 } else {
1088 lp_build_intrinsic(base->gallivm->builder,
1089 "llvm.SI.export",
1090 LLVMVoidTypeInContext(base->gallivm->context),
1091 args, 9);
1092 }
1093
1094 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1095 semantic_name = TGSI_SEMANTIC_GENERIC;
1096 goto handle_semantic;
1097 }
1098 }
1099
1100 /* We need to add the position output manually if it's missing. */
1101 if (!pos_args[0][0]) {
1102 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1103 pos_args[0][1] = uint->zero; /* EXEC mask */
1104 pos_args[0][2] = uint->zero; /* last export? */
1105 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1106 pos_args[0][4] = uint->zero; /* COMPR flag */
1107 pos_args[0][5] = base->zero; /* X */
1108 pos_args[0][6] = base->zero; /* Y */
1109 pos_args[0][7] = base->zero; /* Z */
1110 pos_args[0][8] = base->one; /* W */
1111 }
1112
1113 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1114 if (shader->vs_out_misc_write) {
1115 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1116 shader->vs_out_point_size |
1117 (shader->vs_out_edgeflag << 1) |
1118 (shader->vs_out_layer << 2));
1119 pos_args[1][1] = uint->zero; /* EXEC mask */
1120 pos_args[1][2] = uint->zero; /* last export? */
1121 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1122 pos_args[1][4] = uint->zero; /* COMPR flag */
1123 pos_args[1][5] = base->zero; /* X */
1124 pos_args[1][6] = base->zero; /* Y */
1125 pos_args[1][7] = base->zero; /* Z */
1126 pos_args[1][8] = base->zero; /* W */
1127
1128 if (shader->vs_out_point_size)
1129 pos_args[1][5] = psize_value;
1130
1131 if (shader->vs_out_edgeflag) {
1132 /* The output is a float, but the hw expects an integer
1133 * with the first bit containing the edge flag. */
1134 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1135 edgeflag_value,
1136 bld_base->uint_bld.elem_type, "");
1137 edgeflag_value = lp_build_min(&bld_base->int_bld,
1138 edgeflag_value,
1139 bld_base->int_bld.one);
1140
1141 /* The LLVM intrinsic expects a float. */
1142 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1143 edgeflag_value,
1144 base->elem_type, "");
1145 }
1146
1147 if (shader->vs_out_layer)
1148 pos_args[1][7] = layer_value;
1149 }
1150
1151 for (i = 0; i < 4; i++)
1152 if (pos_args[i][0])
1153 shader->nr_pos_exports++;
1154
1155 pos_idx = 0;
1156 for (i = 0; i < 4; i++) {
1157 if (!pos_args[i][0])
1158 continue;
1159
1160 /* Specify the target we are exporting */
1161 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1162
1163 if (pos_idx == shader->nr_pos_exports)
1164 /* Specify that this is the last export */
1165 pos_args[i][2] = uint->one;
1166
1167 lp_build_intrinsic(base->gallivm->builder,
1168 "llvm.SI.export",
1169 LLVMVoidTypeInContext(base->gallivm->context),
1170 pos_args[i], 9);
1171 }
1172 }
1173
1174 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1175 {
1176 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1177 struct gallivm_state *gallivm = bld_base->base.gallivm;
1178 struct si_shader *es = &si_shader_ctx->shader->shader;
1179 struct si_shader *gs = si_shader_ctx->gs_for_vs;
1180 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1181 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1182 LLVMValueRef t_list_ptr;
1183 LLVMValueRef t_list;
1184 unsigned chan;
1185 int i;
1186
1187 while (!tgsi_parse_end_of_tokens(parse)) {
1188 struct tgsi_full_declaration *d =
1189 &parse->FullToken.FullDeclaration;
1190
1191 tgsi_parse_token(parse);
1192
1193 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1194 continue;
1195
1196 si_store_shader_io_attribs(es, d);
1197 }
1198
1199 /* Load the ESGS ring resource descriptor */
1200 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1201 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
1202 lp_build_const_int32(gallivm, SI_RING_ESGS));
1203
1204 for (i = 0; i < es->noutput; i++) {
1205 LLVMValueRef *out_ptr =
1206 si_shader_ctx->radeon_bld.soa.outputs[es->output[i].index];
1207 int j;
1208
1209 for (j = 0; j < gs->ninput; j++) {
1210 if (gs->input[j].name == es->output[i].name &&
1211 gs->input[j].sid == es->output[i].sid)
1212 break;
1213 }
1214 if (j == gs->ninput)
1215 continue;
1216
1217 for (chan = 0; chan < 4; chan++) {
1218 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1219 LLVMValueRef voffset =
1220 lp_build_const_int32(gallivm,
1221 (4 * gs->input[j].param_offset + chan) * 4);
1222 LLVMValueRef soffset =
1223 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1224 SI_PARAM_ES2GS_OFFSET);
1225
1226 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1227
1228 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
1229 voffset, soffset, 0,
1230 V_008F0C_BUF_DATA_FORMAT_32,
1231 V_008F0C_BUF_NUM_FORMAT_UINT,
1232 1, 0, 1, 1, 0);
1233 }
1234 }
1235 }
1236
1237 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
1238 {
1239 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1240 struct gallivm_state *gallivm = bld_base->base.gallivm;
1241 LLVMValueRef args[2];
1242
1243 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
1244 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1245 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1246 LLVMVoidTypeInContext(gallivm->context), args, 2,
1247 LLVMNoUnwindAttribute);
1248 }
1249
1250 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
1251 {
1252 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1253 struct gallivm_state *gallivm = bld_base->base.gallivm;
1254 struct si_pipe_shader *shader = si_shader_ctx->shader;
1255 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1256 struct si_shader_output_values *outputs = NULL;
1257 unsigned noutput = 0;
1258 int i;
1259
1260 while (!tgsi_parse_end_of_tokens(parse)) {
1261 struct tgsi_full_declaration *d =
1262 &parse->FullToken.FullDeclaration;
1263 unsigned index;
1264
1265 tgsi_parse_token(parse);
1266
1267 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1268 continue;
1269
1270 i = si_store_shader_io_attribs(&shader->shader, d);
1271 if (i < 0)
1272 continue;
1273
1274 outputs = REALLOC(outputs, noutput * sizeof(outputs[0]),
1275 (noutput + 1) * sizeof(outputs[0]));
1276 for (index = d->Range.First; index <= d->Range.Last; index++) {
1277 outputs[noutput].index = index;
1278 outputs[noutput].name = d->Semantic.Name;
1279 outputs[noutput].sid = d->Semantic.Index;
1280 outputs[noutput].usage = d->Declaration.UsageMask;
1281
1282 for (i = 0; i < 4; i++)
1283 outputs[noutput].values[i] =
1284 LLVMBuildLoad(gallivm->builder,
1285 si_shader_ctx->radeon_bld.soa.outputs[index][i],
1286 "");
1287 }
1288 noutput++;
1289 }
1290
1291 si_llvm_export_vs(bld_base, outputs, noutput);
1292 FREE(outputs);
1293 }
1294
1295 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
1296 {
1297 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1298 struct si_shader * shader = &si_shader_ctx->shader->shader;
1299 struct lp_build_context * base = &bld_base->base;
1300 struct lp_build_context * uint =
1301 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1302 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1303 LLVMValueRef args[9];
1304 LLVMValueRef last_args[9] = { 0 };
1305 unsigned semantic_name;
1306 int depth_index = -1, stencil_index = -1;
1307 int i;
1308
1309 while (!tgsi_parse_end_of_tokens(parse)) {
1310 struct tgsi_full_declaration *d =
1311 &parse->FullToken.FullDeclaration;
1312 unsigned target;
1313 unsigned index;
1314
1315 tgsi_parse_token(parse);
1316
1317 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_PROPERTY &&
1318 parse->FullToken.FullProperty.Property.PropertyName ==
1319 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS)
1320 shader->fs_write_all = TRUE;
1321
1322 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1323 continue;
1324
1325 i = si_store_shader_io_attribs(shader, d);
1326 if (i < 0)
1327 continue;
1328
1329 semantic_name = d->Semantic.Name;
1330 for (index = d->Range.First; index <= d->Range.Last; index++) {
1331 /* Select the correct target */
1332 switch(semantic_name) {
1333 case TGSI_SEMANTIC_POSITION:
1334 depth_index = index;
1335 continue;
1336 case TGSI_SEMANTIC_STENCIL:
1337 stencil_index = index;
1338 continue;
1339 case TGSI_SEMANTIC_COLOR:
1340 target = V_008DFC_SQ_EXP_MRT + d->Semantic.Index;
1341 if (si_shader_ctx->shader->key.ps.alpha_to_one)
1342 LLVMBuildStore(bld_base->base.gallivm->builder,
1343 bld_base->base.one,
1344 si_shader_ctx->radeon_bld.soa.outputs[index][3]);
1345
1346 if (d->Semantic.Index == 0 &&
1347 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
1348 si_alpha_test(bld_base,
1349 si_shader_ctx->radeon_bld.soa.outputs[index]);
1350 break;
1351 default:
1352 target = 0;
1353 fprintf(stderr,
1354 "Warning: SI unhandled fs output type:%d\n",
1355 semantic_name);
1356 }
1357
1358 si_llvm_init_export_args_load(bld_base,
1359 si_shader_ctx->radeon_bld.soa.outputs[index],
1360 target, args);
1361
1362 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1363 /* If there is an export instruction waiting to be emitted, do so now. */
1364 if (last_args[0]) {
1365 lp_build_intrinsic(base->gallivm->builder,
1366 "llvm.SI.export",
1367 LLVMVoidTypeInContext(base->gallivm->context),
1368 last_args, 9);
1369 }
1370
1371 /* This instruction will be emitted at the end of the shader. */
1372 memcpy(last_args, args, sizeof(args));
1373
1374 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
1375 if (shader->fs_write_all && shader->output[i].sid == 0 &&
1376 si_shader_ctx->shader->key.ps.nr_cbufs > 1) {
1377 for (int c = 1; c < si_shader_ctx->shader->key.ps.nr_cbufs; c++) {
1378 si_llvm_init_export_args_load(bld_base,
1379 si_shader_ctx->radeon_bld.soa.outputs[index],
1380 V_008DFC_SQ_EXP_MRT + c, args);
1381 lp_build_intrinsic(base->gallivm->builder,
1382 "llvm.SI.export",
1383 LLVMVoidTypeInContext(base->gallivm->context),
1384 args, 9);
1385 }
1386 }
1387 } else {
1388 lp_build_intrinsic(base->gallivm->builder,
1389 "llvm.SI.export",
1390 LLVMVoidTypeInContext(base->gallivm->context),
1391 args, 9);
1392 }
1393 }
1394 }
1395
1396 if (depth_index >= 0 || stencil_index >= 0) {
1397 LLVMValueRef out_ptr;
1398 unsigned mask = 0;
1399
1400 /* Specify the target we are exporting */
1401 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
1402
1403 if (depth_index >= 0) {
1404 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
1405 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1406 mask |= 0x1;
1407
1408 if (stencil_index < 0) {
1409 args[6] =
1410 args[7] =
1411 args[8] = args[5];
1412 }
1413 }
1414
1415 if (stencil_index >= 0) {
1416 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
1417 args[7] =
1418 args[8] =
1419 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1420 /* Only setting the stencil component bit (0x2) here
1421 * breaks some stencil piglit tests
1422 */
1423 mask |= 0x3;
1424
1425 if (depth_index < 0)
1426 args[5] = args[6];
1427 }
1428
1429 /* Specify which components to enable */
1430 args[0] = lp_build_const_int32(base->gallivm, mask);
1431
1432 args[1] =
1433 args[2] =
1434 args[4] = uint->zero;
1435
1436 if (last_args[0])
1437 lp_build_intrinsic(base->gallivm->builder,
1438 "llvm.SI.export",
1439 LLVMVoidTypeInContext(base->gallivm->context),
1440 args, 9);
1441 else
1442 memcpy(last_args, args, sizeof(args));
1443 }
1444
1445 if (!last_args[0]) {
1446 /* Specify which components to enable */
1447 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
1448
1449 /* Specify the target we are exporting */
1450 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
1451
1452 /* Set COMPR flag to zero to export data as 32-bit */
1453 last_args[4] = uint->zero;
1454
1455 /* dummy bits */
1456 last_args[5]= uint->zero;
1457 last_args[6]= uint->zero;
1458 last_args[7]= uint->zero;
1459 last_args[8]= uint->zero;
1460
1461 si_shader_ctx->shader->spi_shader_col_format |=
1462 V_028714_SPI_SHADER_32_ABGR;
1463 si_shader_ctx->shader->cb_shader_mask |= S_02823C_OUTPUT0_ENABLE(0xf);
1464 }
1465
1466 /* Specify whether the EXEC mask represents the valid mask */
1467 last_args[1] = uint->one;
1468
1469 /* Specify that this is the last export */
1470 last_args[2] = lp_build_const_int32(base->gallivm, 1);
1471
1472 lp_build_intrinsic(base->gallivm->builder,
1473 "llvm.SI.export",
1474 LLVMVoidTypeInContext(base->gallivm->context),
1475 last_args, 9);
1476 }
1477
1478 static const struct lp_build_tgsi_action txf_action;
1479
1480 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1481 struct lp_build_tgsi_context * bld_base,
1482 struct lp_build_emit_data * emit_data);
1483
1484 static void tex_fetch_args(
1485 struct lp_build_tgsi_context * bld_base,
1486 struct lp_build_emit_data * emit_data)
1487 {
1488 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1489 struct gallivm_state *gallivm = bld_base->base.gallivm;
1490 const struct tgsi_full_instruction * inst = emit_data->inst;
1491 unsigned opcode = inst->Instruction.Opcode;
1492 unsigned target = inst->Texture.Texture;
1493 LLVMValueRef coords[4];
1494 LLVMValueRef address[16];
1495 int ref_pos;
1496 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
1497 unsigned count = 0;
1498 unsigned chan;
1499 unsigned sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1500 unsigned sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
1501
1502 if (target == TGSI_TEXTURE_BUFFER) {
1503 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
1504 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
1505 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
1506 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
1507
1508 /* Truncate v32i8 to v16i8. */
1509 LLVMValueRef res = si_shader_ctx->resources[sampler_index];
1510 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
1511 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.zero, "");
1512 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
1513
1514 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
1515 emit_data->args[0] = res;
1516 emit_data->args[1] = bld_base->uint_bld.zero;
1517 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
1518 emit_data->arg_count = 3;
1519 return;
1520 }
1521
1522 /* Fetch and project texture coordinates */
1523 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1524 for (chan = 0; chan < 3; chan++ ) {
1525 coords[chan] = lp_build_emit_fetch(bld_base,
1526 emit_data->inst, 0,
1527 chan);
1528 if (opcode == TGSI_OPCODE_TXP)
1529 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1530 TGSI_OPCODE_DIV,
1531 coords[chan],
1532 coords[3]);
1533 }
1534
1535 if (opcode == TGSI_OPCODE_TXP)
1536 coords[3] = bld_base->base.one;
1537
1538 /* Pack LOD bias value */
1539 if (opcode == TGSI_OPCODE_TXB)
1540 address[count++] = coords[3];
1541
1542 if (target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE)
1543 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
1544
1545 /* Pack depth comparison value */
1546 switch (target) {
1547 case TGSI_TEXTURE_SHADOW1D:
1548 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1549 case TGSI_TEXTURE_SHADOW2D:
1550 case TGSI_TEXTURE_SHADOWRECT:
1551 case TGSI_TEXTURE_SHADOWCUBE:
1552 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1553 assert(ref_pos >= 0);
1554 address[count++] = coords[ref_pos];
1555 break;
1556 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1557 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1558 }
1559
1560 /* Pack user derivatives */
1561 if (opcode == TGSI_OPCODE_TXD) {
1562 for (chan = 0; chan < 2; chan++) {
1563 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, chan);
1564 if (num_coords > 1)
1565 address[count++] = lp_build_emit_fetch(bld_base, inst, 2, chan);
1566 }
1567 }
1568
1569 /* Pack texture coordinates */
1570 address[count++] = coords[0];
1571 if (num_coords > 1)
1572 address[count++] = coords[1];
1573 if (num_coords > 2)
1574 address[count++] = coords[2];
1575
1576 /* Pack LOD or sample index */
1577 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1578 address[count++] = coords[3];
1579
1580 if (count > 16) {
1581 assert(!"Cannot handle more than 16 texture address parameters");
1582 count = 16;
1583 }
1584
1585 for (chan = 0; chan < count; chan++ ) {
1586 address[chan] = LLVMBuildBitCast(gallivm->builder,
1587 address[chan],
1588 LLVMInt32TypeInContext(gallivm->context),
1589 "");
1590 }
1591
1592 /* Adjust the sample index according to FMASK.
1593 *
1594 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1595 * which is the identity mapping. Each nibble says which physical sample
1596 * should be fetched to get that sample.
1597 *
1598 * For example, 0x11111100 means there are only 2 samples stored and
1599 * the second sample covers 3/4 of the pixel. When reading samples 0
1600 * and 1, return physical sample 0 (determined by the first two 0s
1601 * in FMASK), otherwise return physical sample 1.
1602 *
1603 * The sample index should be adjusted as follows:
1604 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1605 */
1606 if (target == TGSI_TEXTURE_2D_MSAA ||
1607 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1608 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1609 struct lp_build_emit_data txf_emit_data = *emit_data;
1610 LLVMValueRef txf_address[4];
1611 unsigned txf_count = count;
1612
1613 memcpy(txf_address, address, sizeof(txf_address));
1614
1615 if (target == TGSI_TEXTURE_2D_MSAA) {
1616 txf_address[2] = bld_base->uint_bld.zero;
1617 }
1618 txf_address[3] = bld_base->uint_bld.zero;
1619
1620 /* Pad to a power-of-two size. */
1621 while (txf_count < util_next_power_of_two(txf_count))
1622 txf_address[txf_count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1623
1624 /* Read FMASK using TXF. */
1625 txf_emit_data.chan = 0;
1626 txf_emit_data.dst_type = LLVMVectorType(
1627 LLVMInt32TypeInContext(bld_base->base.gallivm->context), 4);
1628 txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
1629 txf_emit_data.args[1] = si_shader_ctx->resources[FMASK_TEX_OFFSET + sampler_index];
1630 txf_emit_data.args[2] = lp_build_const_int32(bld_base->base.gallivm,
1631 target == TGSI_TEXTURE_2D_MSAA ? TGSI_TEXTURE_2D : TGSI_TEXTURE_2D_ARRAY);
1632 txf_emit_data.arg_count = 3;
1633
1634 build_tex_intrinsic(&txf_action, bld_base, &txf_emit_data);
1635
1636 /* Initialize some constants. */
1637 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
1638 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
1639
1640 /* Apply the formula. */
1641 LLVMValueRef fmask =
1642 LLVMBuildExtractElement(gallivm->builder,
1643 txf_emit_data.output[0],
1644 uint_bld->zero, "");
1645
1646 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1647
1648 LLVMValueRef sample_index4 =
1649 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1650
1651 LLVMValueRef shifted_fmask =
1652 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1653
1654 LLVMValueRef final_sample =
1655 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1656
1657 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1658 * resource descriptor is 0 (invalid),
1659 */
1660 LLVMValueRef fmask_desc =
1661 LLVMBuildBitCast(gallivm->builder,
1662 si_shader_ctx->resources[FMASK_TEX_OFFSET + sampler_index],
1663 LLVMVectorType(uint_bld->elem_type, 8), "");
1664
1665 LLVMValueRef fmask_word1 =
1666 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1667 uint_bld->one, "");
1668
1669 LLVMValueRef word1_is_nonzero =
1670 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1671 fmask_word1, uint_bld->zero, "");
1672
1673 /* Replace the MSAA sample index. */
1674 address[sample_chan] =
1675 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1676 final_sample, address[sample_chan], "");
1677 }
1678
1679 /* Resource */
1680 emit_data->args[1] = si_shader_ctx->resources[sampler_index];
1681
1682 if (opcode == TGSI_OPCODE_TXF) {
1683 /* add tex offsets */
1684 if (inst->Texture.NumOffsets) {
1685 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1686 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
1687 const struct tgsi_texture_offset * off = inst->TexOffsets;
1688
1689 assert(inst->Texture.NumOffsets == 1);
1690
1691 switch (target) {
1692 case TGSI_TEXTURE_3D:
1693 address[2] = lp_build_add(uint_bld, address[2],
1694 bld->immediates[off->Index][off->SwizzleZ]);
1695 /* fall through */
1696 case TGSI_TEXTURE_2D:
1697 case TGSI_TEXTURE_SHADOW2D:
1698 case TGSI_TEXTURE_RECT:
1699 case TGSI_TEXTURE_SHADOWRECT:
1700 case TGSI_TEXTURE_2D_ARRAY:
1701 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1702 address[1] =
1703 lp_build_add(uint_bld, address[1],
1704 bld->immediates[off->Index][off->SwizzleY]);
1705 /* fall through */
1706 case TGSI_TEXTURE_1D:
1707 case TGSI_TEXTURE_SHADOW1D:
1708 case TGSI_TEXTURE_1D_ARRAY:
1709 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1710 address[0] =
1711 lp_build_add(uint_bld, address[0],
1712 bld->immediates[off->Index][off->SwizzleX]);
1713 break;
1714 /* texture offsets do not apply to other texture targets */
1715 }
1716 }
1717
1718 emit_data->dst_type = LLVMVectorType(
1719 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
1720 4);
1721
1722 emit_data->arg_count = 3;
1723 } else {
1724 /* Sampler */
1725 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1726
1727 emit_data->dst_type = LLVMVectorType(
1728 LLVMFloatTypeInContext(bld_base->base.gallivm->context),
1729 4);
1730
1731 emit_data->arg_count = 4;
1732 }
1733
1734 /* Dimensions */
1735 emit_data->args[emit_data->arg_count - 1] =
1736 lp_build_const_int32(bld_base->base.gallivm, target);
1737
1738 /* Pad to power of two vector */
1739 while (count < util_next_power_of_two(count))
1740 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1741
1742 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
1743 }
1744
1745 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1746 struct lp_build_tgsi_context * bld_base,
1747 struct lp_build_emit_data * emit_data)
1748 {
1749 struct lp_build_context * base = &bld_base->base;
1750 char intr_name[127];
1751
1752 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1753 emit_data->output[emit_data->chan] = build_intrinsic(
1754 base->gallivm->builder,
1755 "llvm.SI.vs.load.input", emit_data->dst_type,
1756 emit_data->args, emit_data->arg_count,
1757 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1758 return;
1759 }
1760
1761 sprintf(intr_name, "%sv%ui32", action->intr_name,
1762 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
1763
1764 emit_data->output[emit_data->chan] = build_intrinsic(
1765 base->gallivm->builder, intr_name, emit_data->dst_type,
1766 emit_data->args, emit_data->arg_count,
1767 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1768 }
1769
1770 static void txq_fetch_args(
1771 struct lp_build_tgsi_context * bld_base,
1772 struct lp_build_emit_data * emit_data)
1773 {
1774 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1775 const struct tgsi_full_instruction *inst = emit_data->inst;
1776 struct gallivm_state *gallivm = bld_base->base.gallivm;
1777
1778 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1779 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1780 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
1781
1782 /* Read the size from the buffer descriptor directly. */
1783 LLVMValueRef size = si_shader_ctx->resources[inst->Src[1].Register.Index];
1784 size = LLVMBuildBitCast(gallivm->builder, size, v8i32, "");
1785 size = LLVMBuildExtractElement(gallivm->builder, size,
1786 lp_build_const_int32(gallivm, 2), "");
1787 emit_data->args[0] = size;
1788 return;
1789 }
1790
1791 /* Mip level */
1792 emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1793
1794 /* Resource */
1795 emit_data->args[1] = si_shader_ctx->resources[inst->Src[1].Register.Index];
1796
1797 /* Dimensions */
1798 emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
1799 inst->Texture.Texture);
1800
1801 emit_data->arg_count = 3;
1802
1803 emit_data->dst_type = LLVMVectorType(
1804 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
1805 4);
1806 }
1807
1808 static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
1809 struct lp_build_tgsi_context * bld_base,
1810 struct lp_build_emit_data * emit_data)
1811 {
1812 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1813 /* Just return the buffer size. */
1814 emit_data->output[emit_data->chan] = emit_data->args[0];
1815 return;
1816 }
1817
1818 build_tgsi_intrinsic_nomem(action, bld_base, emit_data);
1819 }
1820
1821 #if HAVE_LLVM >= 0x0304
1822
1823 static void si_llvm_emit_ddxy(
1824 const struct lp_build_tgsi_action * action,
1825 struct lp_build_tgsi_context * bld_base,
1826 struct lp_build_emit_data * emit_data)
1827 {
1828 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1829 struct gallivm_state *gallivm = bld_base->base.gallivm;
1830 struct lp_build_context * base = &bld_base->base;
1831 const struct tgsi_full_instruction *inst = emit_data->inst;
1832 unsigned opcode = inst->Instruction.Opcode;
1833 LLVMValueRef indices[2];
1834 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
1835 LLVMValueRef tl, trbl, result[4];
1836 LLVMTypeRef i32;
1837 unsigned swizzle[4];
1838 unsigned c;
1839
1840 i32 = LLVMInt32TypeInContext(gallivm->context);
1841
1842 indices[0] = bld_base->uint_bld.zero;
1843 indices[1] = build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
1844 NULL, 0, LLVMReadNoneAttribute);
1845 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
1846 indices, 2, "");
1847
1848 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
1849 lp_build_const_int32(gallivm, 0xfffffffc), "");
1850 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
1851 indices, 2, "");
1852
1853 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
1854 lp_build_const_int32(gallivm,
1855 opcode == TGSI_OPCODE_DDX ? 1 : 2),
1856 "");
1857 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
1858 indices, 2, "");
1859
1860 for (c = 0; c < 4; ++c) {
1861 unsigned i;
1862
1863 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
1864 for (i = 0; i < c; ++i) {
1865 if (swizzle[i] == swizzle[c]) {
1866 result[c] = result[i];
1867 break;
1868 }
1869 }
1870 if (i != c)
1871 continue;
1872
1873 LLVMBuildStore(gallivm->builder,
1874 LLVMBuildBitCast(gallivm->builder,
1875 lp_build_emit_fetch(bld_base, inst, 0, c),
1876 i32, ""),
1877 store_ptr);
1878
1879 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
1880 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
1881
1882 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
1883 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
1884
1885 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
1886 }
1887
1888 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
1889 }
1890
1891 #endif /* HAVE_LLVM >= 0x0304 */
1892
1893 /* Emit one vertex from the geometry shader */
1894 static void si_llvm_emit_vertex(
1895 const struct lp_build_tgsi_action *action,
1896 struct lp_build_tgsi_context *bld_base,
1897 struct lp_build_emit_data *emit_data)
1898 {
1899 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1900 struct lp_build_context *uint = &bld_base->uint_bld;
1901 struct si_shader *shader = &si_shader_ctx->shader->shader;
1902 struct gallivm_state *gallivm = bld_base->base.gallivm;
1903 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1904 LLVMValueRef gs_next_vertex;
1905 LLVMValueRef t_list_ptr;
1906 LLVMValueRef t_list;
1907 LLVMValueRef args[2];
1908 unsigned chan;
1909 int i;
1910
1911 /* Load the GSVS ring resource descriptor */
1912 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1913 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
1914 lp_build_const_int32(gallivm, SI_RING_GSVS));
1915
1916 if (shader->noutput == 0) {
1917 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1918
1919 while (!tgsi_parse_end_of_tokens(parse)) {
1920 tgsi_parse_token(parse);
1921
1922 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1923 struct tgsi_full_declaration *d = &parse->FullToken.FullDeclaration;
1924
1925 if (d->Declaration.File == TGSI_FILE_OUTPUT)
1926 si_store_shader_io_attribs(shader, d);
1927 }
1928 }
1929 }
1930
1931 /* Write vertex attribute values to GSVS ring */
1932 gs_next_vertex = LLVMBuildLoad(gallivm->builder, si_shader_ctx->gs_next_vertex, "");
1933 for (i = 0; i < shader->noutput; i++) {
1934 LLVMValueRef *out_ptr =
1935 si_shader_ctx->radeon_bld.soa.outputs[shader->output[i].index];
1936
1937 for (chan = 0; chan < 4; chan++) {
1938 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1939 LLVMValueRef soffset =
1940 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1941 SI_PARAM_GS2VS_OFFSET);
1942 LLVMValueRef voffset =
1943 lp_build_const_int32(gallivm, (i * 4 + chan) *
1944 shader->gs_max_out_vertices);
1945
1946 voffset = lp_build_add(uint, voffset, gs_next_vertex);
1947 voffset = lp_build_mul_imm(uint, voffset, 4);
1948
1949 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1950
1951 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
1952 voffset, soffset, 0,
1953 V_008F0C_BUF_DATA_FORMAT_32,
1954 V_008F0C_BUF_NUM_FORMAT_UINT,
1955 1, 0, 1, 1, 0);
1956 }
1957 }
1958 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
1959 lp_build_const_int32(gallivm, 1));
1960 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex);
1961
1962 /* Signal vertex emission */
1963 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS);
1964 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1965 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1966 LLVMVoidTypeInContext(gallivm->context), args, 2,
1967 LLVMNoUnwindAttribute);
1968 }
1969
1970 /* Cut one primitive from the geometry shader */
1971 static void si_llvm_emit_primitive(
1972 const struct lp_build_tgsi_action *action,
1973 struct lp_build_tgsi_context *bld_base,
1974 struct lp_build_emit_data *emit_data)
1975 {
1976 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1977 struct gallivm_state *gallivm = bld_base->base.gallivm;
1978 LLVMValueRef args[2];
1979
1980 /* Signal primitive cut */
1981 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS);
1982 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1983 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1984 LLVMVoidTypeInContext(gallivm->context), args, 2,
1985 LLVMNoUnwindAttribute);
1986 }
1987
1988 static const struct lp_build_tgsi_action tex_action = {
1989 .fetch_args = tex_fetch_args,
1990 .emit = build_tex_intrinsic,
1991 .intr_name = "llvm.SI.sample."
1992 };
1993
1994 static const struct lp_build_tgsi_action txb_action = {
1995 .fetch_args = tex_fetch_args,
1996 .emit = build_tex_intrinsic,
1997 .intr_name = "llvm.SI.sampleb."
1998 };
1999
2000 #if HAVE_LLVM >= 0x0304
2001 static const struct lp_build_tgsi_action txd_action = {
2002 .fetch_args = tex_fetch_args,
2003 .emit = build_tex_intrinsic,
2004 .intr_name = "llvm.SI.sampled."
2005 };
2006 #endif
2007
2008 static const struct lp_build_tgsi_action txf_action = {
2009 .fetch_args = tex_fetch_args,
2010 .emit = build_tex_intrinsic,
2011 .intr_name = "llvm.SI.imageload."
2012 };
2013
2014 static const struct lp_build_tgsi_action txl_action = {
2015 .fetch_args = tex_fetch_args,
2016 .emit = build_tex_intrinsic,
2017 .intr_name = "llvm.SI.samplel."
2018 };
2019
2020 static const struct lp_build_tgsi_action txq_action = {
2021 .fetch_args = txq_fetch_args,
2022 .emit = build_txq_intrinsic,
2023 .intr_name = "llvm.SI.resinfo"
2024 };
2025
2026 static void create_meta_data(struct si_shader_context *si_shader_ctx)
2027 {
2028 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2029 LLVMValueRef args[3];
2030
2031 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
2032 args[1] = 0;
2033 args[2] = lp_build_const_int32(gallivm, 1);
2034
2035 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
2036 }
2037
2038 static void create_function(struct si_shader_context *si_shader_ctx)
2039 {
2040 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2041 struct gallivm_state *gallivm = bld_base->base.gallivm;
2042 struct si_pipe_shader *shader = si_shader_ctx->shader;
2043 LLVMTypeRef params[21], f32, i8, i32, v2i32, v3i32;
2044 unsigned i, last_sgpr, num_params;
2045
2046 i8 = LLVMInt8TypeInContext(gallivm->context);
2047 i32 = LLVMInt32TypeInContext(gallivm->context);
2048 f32 = LLVMFloatTypeInContext(gallivm->context);
2049 v2i32 = LLVMVectorType(i32, 2);
2050 v3i32 = LLVMVectorType(i32, 3);
2051
2052 params[SI_PARAM_CONST] = LLVMPointerType(
2053 LLVMArrayType(LLVMVectorType(i8, 16), NUM_CONST_BUFFERS), CONST_ADDR_SPACE);
2054 /* We assume at most 16 textures per program at the moment.
2055 * This need probably need to be changed to support bindless textures */
2056 params[SI_PARAM_SAMPLER] = LLVMPointerType(
2057 LLVMArrayType(LLVMVectorType(i8, 16), NUM_SAMPLER_VIEWS), CONST_ADDR_SPACE);
2058 params[SI_PARAM_RESOURCE] = LLVMPointerType(
2059 LLVMArrayType(LLVMVectorType(i8, 32), NUM_SAMPLER_STATES), CONST_ADDR_SPACE);
2060
2061 switch (si_shader_ctx->type) {
2062 case TGSI_PROCESSOR_VERTEX:
2063 params[SI_PARAM_VERTEX_BUFFER] = params[SI_PARAM_CONST];
2064 params[SI_PARAM_SO_BUFFER] = params[SI_PARAM_CONST];
2065 params[SI_PARAM_START_INSTANCE] = i32;
2066 num_params = SI_PARAM_START_INSTANCE+1;
2067 if (shader->key.vs.as_es) {
2068 params[SI_PARAM_ES2GS_OFFSET] = i32;
2069 num_params++;
2070 } else {
2071 /* The locations of the other parameters are assigned dynamically. */
2072
2073 /* Streamout SGPRs. */
2074 if (shader->selector->so.num_outputs) {
2075 params[si_shader_ctx->param_streamout_config = num_params++] = i32;
2076 params[si_shader_ctx->param_streamout_write_index = num_params++] = i32;
2077 }
2078 /* A streamout buffer offset is loaded if the stride is non-zero. */
2079 for (i = 0; i < 4; i++) {
2080 if (!shader->selector->so.stride[i])
2081 continue;
2082
2083 params[si_shader_ctx->param_streamout_offset[i] = num_params++] = i32;
2084 }
2085 }
2086
2087 last_sgpr = num_params-1;
2088
2089 /* VGPRs */
2090 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
2091 params[num_params++] = i32; /* unused*/
2092 params[num_params++] = i32; /* unused */
2093 params[si_shader_ctx->param_instance_id = num_params++] = i32;
2094 break;
2095
2096 case TGSI_PROCESSOR_GEOMETRY:
2097 params[SI_PARAM_GS2VS_OFFSET] = i32;
2098 params[SI_PARAM_GS_WAVE_ID] = i32;
2099 last_sgpr = SI_PARAM_GS_WAVE_ID;
2100
2101 /* VGPRs */
2102 params[SI_PARAM_VTX0_OFFSET] = i32;
2103 params[SI_PARAM_VTX1_OFFSET] = i32;
2104 params[SI_PARAM_PRIMITIVE_ID] = i32;
2105 params[SI_PARAM_VTX2_OFFSET] = i32;
2106 params[SI_PARAM_VTX3_OFFSET] = i32;
2107 params[SI_PARAM_VTX4_OFFSET] = i32;
2108 params[SI_PARAM_VTX5_OFFSET] = i32;
2109 params[SI_PARAM_GS_INSTANCE_ID] = i32;
2110 num_params = SI_PARAM_GS_INSTANCE_ID+1;
2111 break;
2112
2113 case TGSI_PROCESSOR_FRAGMENT:
2114 params[SI_PARAM_ALPHA_REF] = f32;
2115 params[SI_PARAM_PRIM_MASK] = i32;
2116 last_sgpr = SI_PARAM_PRIM_MASK;
2117 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
2118 params[SI_PARAM_PERSP_CENTER] = v2i32;
2119 params[SI_PARAM_PERSP_CENTROID] = v2i32;
2120 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
2121 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
2122 params[SI_PARAM_LINEAR_CENTER] = v2i32;
2123 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
2124 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
2125 params[SI_PARAM_POS_X_FLOAT] = f32;
2126 params[SI_PARAM_POS_Y_FLOAT] = f32;
2127 params[SI_PARAM_POS_Z_FLOAT] = f32;
2128 params[SI_PARAM_POS_W_FLOAT] = f32;
2129 params[SI_PARAM_FRONT_FACE] = f32;
2130 params[SI_PARAM_ANCILLARY] = f32;
2131 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
2132 params[SI_PARAM_POS_FIXED_PT] = f32;
2133 num_params = SI_PARAM_POS_FIXED_PT+1;
2134 break;
2135
2136 default:
2137 assert(0 && "unimplemented shader");
2138 return;
2139 }
2140
2141 assert(num_params <= Elements(params));
2142 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
2143 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
2144
2145 for (i = 0; i <= last_sgpr; ++i) {
2146 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
2147 switch (i) {
2148 default:
2149 LLVMAddAttribute(P, LLVMInRegAttribute);
2150 break;
2151 #if HAVE_LLVM >= 0x0304
2152 /* We tell llvm that array inputs are passed by value to allow Sinking pass
2153 * to move load. Inputs are constant so this is fine. */
2154 case SI_PARAM_CONST:
2155 case SI_PARAM_SAMPLER:
2156 case SI_PARAM_RESOURCE:
2157 LLVMAddAttribute(P, LLVMByValAttribute);
2158 break;
2159 #endif
2160 }
2161 }
2162
2163 #if HAVE_LLVM >= 0x0304
2164 if (bld_base->info &&
2165 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
2166 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0))
2167 si_shader_ctx->ddxy_lds =
2168 LLVMAddGlobalInAddressSpace(gallivm->module,
2169 LLVMArrayType(i32, 64),
2170 "ddxy_lds",
2171 LOCAL_ADDR_SPACE);
2172 #endif
2173 }
2174
2175 static void preload_constants(struct si_shader_context *si_shader_ctx)
2176 {
2177 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2178 struct gallivm_state * gallivm = bld_base->base.gallivm;
2179 const struct tgsi_shader_info * info = bld_base->info;
2180 unsigned buf;
2181 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
2182
2183 for (buf = 0; buf < NUM_CONST_BUFFERS; buf++) {
2184 unsigned i, num_const = info->const_file_max[buf] + 1;
2185
2186 if (num_const == 0)
2187 continue;
2188
2189 /* Allocate space for the constant values */
2190 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
2191
2192 /* Load the resource descriptor */
2193 si_shader_ctx->const_resource[buf] =
2194 build_indexed_load(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
2195
2196 /* Load the constants, we rely on the code sinking to do the rest */
2197 for (i = 0; i < num_const * 4; ++i) {
2198 LLVMValueRef args[2] = {
2199 si_shader_ctx->const_resource[buf],
2200 lp_build_const_int32(gallivm, i * 4)
2201 };
2202 si_shader_ctx->constants[buf][i] =
2203 build_intrinsic(gallivm->builder, "llvm.SI.load.const",
2204 bld_base->base.elem_type, args, 2,
2205 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2206 }
2207 }
2208 }
2209
2210 static void preload_samplers(struct si_shader_context *si_shader_ctx)
2211 {
2212 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2213 struct gallivm_state * gallivm = bld_base->base.gallivm;
2214 const struct tgsi_shader_info * info = bld_base->info;
2215
2216 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
2217
2218 LLVMValueRef res_ptr, samp_ptr;
2219 LLVMValueRef offset;
2220
2221 if (num_samplers == 0)
2222 return;
2223
2224 /* Allocate space for the values */
2225 si_shader_ctx->resources = CALLOC(NUM_SAMPLER_VIEWS, sizeof(LLVMValueRef));
2226 si_shader_ctx->samplers = CALLOC(num_samplers, sizeof(LLVMValueRef));
2227
2228 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2229 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2230
2231 /* Load the resources and samplers, we rely on the code sinking to do the rest */
2232 for (i = 0; i < num_samplers; ++i) {
2233 /* Resource */
2234 offset = lp_build_const_int32(gallivm, i);
2235 si_shader_ctx->resources[i] = build_indexed_load(si_shader_ctx, res_ptr, offset);
2236
2237 /* Sampler */
2238 offset = lp_build_const_int32(gallivm, i);
2239 si_shader_ctx->samplers[i] = build_indexed_load(si_shader_ctx, samp_ptr, offset);
2240
2241 /* FMASK resource */
2242 if (info->is_msaa_sampler[i]) {
2243 offset = lp_build_const_int32(gallivm, FMASK_TEX_OFFSET + i);
2244 si_shader_ctx->resources[FMASK_TEX_OFFSET + i] =
2245 build_indexed_load(si_shader_ctx, res_ptr, offset);
2246 }
2247 }
2248 }
2249
2250 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
2251 {
2252 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2253 struct gallivm_state * gallivm = bld_base->base.gallivm;
2254 unsigned i;
2255
2256 if (si_shader_ctx->type != TGSI_PROCESSOR_VERTEX ||
2257 si_shader_ctx->shader->key.vs.as_es ||
2258 !si_shader_ctx->shader->selector->so.num_outputs)
2259 return;
2260
2261 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2262 SI_PARAM_SO_BUFFER);
2263
2264 /* Load the resources, we rely on the code sinking to do the rest */
2265 for (i = 0; i < 4; ++i) {
2266 if (si_shader_ctx->shader->selector->so.stride[i]) {
2267 LLVMValueRef offset = lp_build_const_int32(gallivm, i);
2268
2269 si_shader_ctx->so_buffers[i] = build_indexed_load(si_shader_ctx, buf_ptr, offset);
2270 }
2271 }
2272 }
2273
2274 int si_compile_llvm(struct si_context *sctx, struct si_pipe_shader *shader,
2275 LLVMModuleRef mod)
2276 {
2277 unsigned i;
2278 uint32_t *ptr;
2279 struct radeon_llvm_binary binary;
2280 bool dump = r600_can_dump_shader(&sctx->screen->b,
2281 shader->selector ? shader->selector->tokens : NULL);
2282 memset(&binary, 0, sizeof(binary));
2283 radeon_llvm_compile(mod, &binary,
2284 r600_get_llvm_processor_name(sctx->screen->b.family), dump);
2285 if (dump && ! binary.disassembled) {
2286 fprintf(stderr, "SI CODE:\n");
2287 for (i = 0; i < binary.code_size; i+=4 ) {
2288 fprintf(stderr, "%02x%02x%02x%02x\n", binary.code[i + 3],
2289 binary.code[i + 2], binary.code[i + 1],
2290 binary.code[i]);
2291 }
2292 }
2293
2294 /* XXX: We may be able to emit some of these values directly rather than
2295 * extracting fields to be emitted later.
2296 */
2297 for (i = 0; i < binary.config_size; i+= 8) {
2298 unsigned reg = util_le32_to_cpu(*(uint32_t*)(binary.config + i));
2299 unsigned value = util_le32_to_cpu(*(uint32_t*)(binary.config + i + 4));
2300 switch (reg) {
2301 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
2302 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
2303 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
2304 case R_00B848_COMPUTE_PGM_RSRC1:
2305 shader->num_sgprs = (G_00B028_SGPRS(value) + 1) * 8;
2306 shader->num_vgprs = (G_00B028_VGPRS(value) + 1) * 4;
2307 break;
2308 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
2309 shader->lds_size = G_00B02C_EXTRA_LDS_SIZE(value);
2310 break;
2311 case R_00B84C_COMPUTE_PGM_RSRC2:
2312 shader->lds_size = G_00B84C_LDS_SIZE(value);
2313 break;
2314 case R_0286CC_SPI_PS_INPUT_ENA:
2315 shader->spi_ps_input_ena = value;
2316 break;
2317 default:
2318 fprintf(stderr, "Warning: Compiler emitted unknown "
2319 "config register: 0x%x\n", reg);
2320 break;
2321 }
2322 }
2323
2324 /* copy new shader */
2325 r600_resource_reference(&shader->bo, NULL);
2326 shader->bo = si_resource_create_custom(sctx->b.b.screen, PIPE_USAGE_IMMUTABLE,
2327 binary.code_size);
2328 if (shader->bo == NULL) {
2329 return -ENOMEM;
2330 }
2331
2332 ptr = (uint32_t*)sctx->b.ws->buffer_map(shader->bo->cs_buf, sctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE);
2333 if (0 /*SI_BIG_ENDIAN*/) {
2334 for (i = 0; i < binary.code_size / 4; ++i) {
2335 ptr[i] = util_bswap32(*(uint32_t*)(binary.code + i*4));
2336 }
2337 } else {
2338 memcpy(ptr, binary.code, binary.code_size);
2339 }
2340 sctx->b.ws->buffer_unmap(shader->bo->cs_buf);
2341
2342 free(binary.code);
2343 free(binary.config);
2344
2345 return 0;
2346 }
2347
2348 /* Generate code for the hardware VS shader stage to go with a geometry shader */
2349 static int si_generate_gs_copy_shader(struct si_context *sctx,
2350 struct si_shader_context *si_shader_ctx,
2351 bool dump)
2352 {
2353 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
2354 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2355 struct lp_build_context *base = &bld_base->base;
2356 struct lp_build_context *uint = &bld_base->uint_bld;
2357 struct si_shader *shader = &si_shader_ctx->shader->shader;
2358 struct si_shader *gs = &si_shader_ctx->shader->selector->current->shader;
2359 struct si_shader_output_values *outputs;
2360 LLVMValueRef t_list_ptr, t_list;
2361 LLVMValueRef args[9];
2362 int i, r;
2363
2364 outputs = MALLOC(gs->noutput * sizeof(outputs[0]));
2365
2366 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
2367 si_shader_ctx->gs_for_vs = gs;
2368
2369 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
2370
2371 create_meta_data(si_shader_ctx);
2372 create_function(si_shader_ctx);
2373 preload_streamout_buffers(si_shader_ctx);
2374
2375 /* Load the GSVS ring resource descriptor */
2376 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
2377 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
2378 lp_build_const_int32(gallivm, SI_RING_GSVS));
2379
2380 args[0] = t_list;
2381 args[1] = lp_build_mul_imm(uint,
2382 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2383 si_shader_ctx->param_vertex_id),
2384 4);
2385 args[3] = uint->zero;
2386 args[4] = uint->one; /* OFFEN */
2387 args[5] = uint->zero; /* IDXEN */
2388 args[6] = uint->one; /* GLC */
2389 args[7] = uint->one; /* SLC */
2390 args[8] = uint->zero; /* TFE */
2391
2392 /* Fetch vertex data from GSVS ring */
2393 for (i = 0; i < gs->noutput; ++i) {
2394 struct si_shader_output *out = gs->output + i;
2395 unsigned chan;
2396
2397 shader->output[i] = *out;
2398
2399 outputs[i].name = out->name;
2400 outputs[i].index = out->index;
2401 outputs[i].sid = out->sid;
2402 outputs[i].usage = out->usage;
2403
2404 for (chan = 0; chan < 4; chan++) {
2405 args[2] = lp_build_const_int32(gallivm,
2406 (i * 4 + chan) *
2407 gs->gs_max_out_vertices * 16 * 4);
2408
2409 outputs[i].values[chan] =
2410 LLVMBuildBitCast(gallivm->builder,
2411 build_intrinsic(gallivm->builder,
2412 "llvm.SI.buffer.load.dword.i32.i32",
2413 LLVMInt32TypeInContext(gallivm->context),
2414 args, 9,
2415 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
2416 base->elem_type, "");
2417 }
2418 }
2419 shader->noutput = gs->noutput;
2420
2421 si_llvm_export_vs(bld_base, outputs, gs->noutput);
2422
2423 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
2424
2425 if (dump)
2426 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
2427
2428 r = si_compile_llvm(sctx, si_shader_ctx->shader,
2429 bld_base->base.gallivm->module);
2430
2431 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
2432
2433 FREE(outputs);
2434 return r;
2435 }
2436
2437 int si_pipe_shader_create(
2438 struct pipe_context *ctx,
2439 struct si_pipe_shader *shader)
2440 {
2441 struct si_context *sctx = (struct si_context*)ctx;
2442 struct si_pipe_shader_selector *sel = shader->selector;
2443 struct si_shader_context si_shader_ctx;
2444 struct tgsi_shader_info shader_info;
2445 struct lp_build_tgsi_context * bld_base;
2446 LLVMModuleRef mod;
2447 int r = 0;
2448 bool dump = r600_can_dump_shader(&sctx->screen->b, sel->tokens);
2449
2450 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2451 * conversion fails. */
2452 if (dump) {
2453 tgsi_dump(sel->tokens, 0);
2454 si_dump_streamout(&sel->so);
2455 }
2456
2457 assert(shader->shader.noutput == 0);
2458 assert(shader->shader.nparam == 0);
2459 assert(shader->shader.ninput == 0);
2460
2461 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
2462 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
2463 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
2464
2465 tgsi_scan_shader(sel->tokens, &shader_info);
2466
2467 shader->shader.uses_kill = shader_info.uses_kill;
2468 shader->shader.uses_instanceid = shader_info.uses_instanceid;
2469 bld_base->info = &shader_info;
2470 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
2471
2472 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
2473 bld_base->op_actions[TGSI_OPCODE_TXB] = txb_action;
2474 #if HAVE_LLVM >= 0x0304
2475 bld_base->op_actions[TGSI_OPCODE_TXD] = txd_action;
2476 #endif
2477 bld_base->op_actions[TGSI_OPCODE_TXF] = txf_action;
2478 bld_base->op_actions[TGSI_OPCODE_TXL] = txl_action;
2479 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
2480 bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
2481
2482 #if HAVE_LLVM >= 0x0304
2483 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
2484 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
2485 #endif
2486
2487 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
2488 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
2489
2490 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
2491 si_shader_ctx.tokens = sel->tokens;
2492 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
2493 si_shader_ctx.shader = shader;
2494 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
2495
2496 switch (si_shader_ctx.type) {
2497 case TGSI_PROCESSOR_VERTEX:
2498 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
2499 if (shader->key.vs.as_es) {
2500 si_shader_ctx.gs_for_vs = &sctx->gs_shader->current->shader;
2501 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
2502 } else {
2503 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
2504 }
2505 break;
2506 case TGSI_PROCESSOR_GEOMETRY: {
2507 int i;
2508
2509 si_shader_ctx.radeon_bld.load_input = declare_input_gs;
2510 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
2511 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
2512
2513 for (i = 0; i < shader_info.num_properties; i++) {
2514 switch (shader_info.properties[i].name) {
2515 case TGSI_PROPERTY_GS_INPUT_PRIM:
2516 shader->shader.gs_input_prim = shader_info.properties[i].data[0];
2517 break;
2518 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
2519 shader->shader.gs_output_prim = shader_info.properties[i].data[0];
2520 break;
2521 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
2522 shader->shader.gs_max_out_vertices = shader_info.properties[i].data[0];
2523 break;
2524 }
2525 }
2526 break;
2527 }
2528 case TGSI_PROCESSOR_FRAGMENT:
2529 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
2530 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
2531 break;
2532 default:
2533 assert(!"Unsupported shader type");
2534 return -1;
2535 }
2536
2537 create_meta_data(&si_shader_ctx);
2538 create_function(&si_shader_ctx);
2539 preload_constants(&si_shader_ctx);
2540 preload_samplers(&si_shader_ctx);
2541 preload_streamout_buffers(&si_shader_ctx);
2542
2543 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2544 si_shader_ctx.gs_next_vertex =
2545 lp_build_alloca(bld_base->base.gallivm,
2546 bld_base->uint_bld.elem_type, "");
2547 }
2548
2549 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
2550 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
2551 goto out;
2552 }
2553
2554 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
2555
2556 mod = bld_base->base.gallivm->module;
2557 r = si_compile_llvm(sctx, shader, mod);
2558 if (r) {
2559 fprintf(stderr, "LLVM failed to compile shader\n");
2560 goto out;
2561 }
2562
2563 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
2564
2565 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2566 shader->gs_copy_shader = CALLOC_STRUCT(si_pipe_shader);
2567 shader->gs_copy_shader->selector = shader->selector;
2568 shader->gs_copy_shader->key = shader->key;
2569 si_shader_ctx.shader = shader->gs_copy_shader;
2570 if ((r = si_generate_gs_copy_shader(sctx, &si_shader_ctx, dump))) {
2571 free(shader->gs_copy_shader);
2572 shader->gs_copy_shader = NULL;
2573 goto out;
2574 }
2575 }
2576
2577 tgsi_parse_free(&si_shader_ctx.parse);
2578
2579 out:
2580 for (int i = 0; i < NUM_CONST_BUFFERS; i++)
2581 FREE(si_shader_ctx.constants[i]);
2582 FREE(si_shader_ctx.resources);
2583 FREE(si_shader_ctx.samplers);
2584
2585 return r;
2586 }
2587
2588 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
2589 {
2590 r600_resource_reference(&shader->bo, NULL);
2591 }