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ac: import lp_create_builder() from gallivm
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "gallivm/lp_bld_const.h"
25 #include "gallivm/lp_bld_gather.h"
26 #include "gallivm/lp_bld_intr.h"
27 #include "gallivm/lp_bld_logic.h"
28 #include "gallivm/lp_bld_arit.h"
29 #include "gallivm/lp_bld_flow.h"
30 #include "gallivm/lp_bld_misc.h"
31 #include "util/u_memory.h"
32 #include "util/u_string.h"
33 #include "tgsi/tgsi_build.h"
34 #include "tgsi/tgsi_util.h"
35 #include "tgsi/tgsi_dump.h"
36
37 #include "ac_binary.h"
38 #include "ac_llvm_util.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41 #include "si_shader_internal.h"
42 #include "si_pipe.h"
43 #include "sid.h"
44
45 #include "compiler/nir/nir.h"
46
47 static const char *scratch_rsrc_dword0_symbol =
48 "SCRATCH_RSRC_DWORD0";
49
50 static const char *scratch_rsrc_dword1_symbol =
51 "SCRATCH_RSRC_DWORD1";
52
53 struct si_shader_output_values
54 {
55 LLVMValueRef values[4];
56 unsigned semantic_name;
57 unsigned semantic_index;
58 ubyte vertex_stream[4];
59 };
60
61 /**
62 * Used to collect types and other info about arguments of the LLVM function
63 * before the function is created.
64 */
65 struct si_function_info {
66 LLVMTypeRef types[100];
67 LLVMValueRef *assign[100];
68 unsigned num_sgpr_params;
69 unsigned num_params;
70 };
71
72 enum si_arg_regfile {
73 ARG_SGPR,
74 ARG_VGPR
75 };
76
77 static void si_init_shader_ctx(struct si_shader_context *ctx,
78 struct si_screen *sscreen,
79 LLVMTargetMachineRef tm);
80
81 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
82 struct lp_build_tgsi_context *bld_base,
83 struct lp_build_emit_data *emit_data);
84
85 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
86 FILE *f);
87
88 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
89 union si_shader_part_key *key);
90 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
91 union si_shader_part_key *key);
92 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
93 union si_shader_part_key *key);
94 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
95 union si_shader_part_key *key);
96
97 /* Ideally pass the sample mask input to the PS epilog as v14, which
98 * is its usual location, so that the shader doesn't have to add v_mov.
99 */
100 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
101
102 enum {
103 CONST_ADDR_SPACE = 2,
104 LOCAL_ADDR_SPACE = 3,
105 };
106
107 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
108 LLVMTypeRef type)
109 {
110 if (type == ctx->ac.i64 || type == ctx->ac.f64)
111 return true;
112
113 return false;
114 }
115
116 static bool is_merged_shader(struct si_shader *shader)
117 {
118 if (shader->selector->screen->info.chip_class <= VI)
119 return false;
120
121 return shader->key.as_ls ||
122 shader->key.as_es ||
123 shader->selector->type == PIPE_SHADER_TESS_CTRL ||
124 shader->selector->type == PIPE_SHADER_GEOMETRY;
125 }
126
127 static void si_init_function_info(struct si_function_info *fninfo)
128 {
129 fninfo->num_params = 0;
130 fninfo->num_sgpr_params = 0;
131 }
132
133 static unsigned add_arg_assign(struct si_function_info *fninfo,
134 enum si_arg_regfile regfile, LLVMTypeRef type,
135 LLVMValueRef *assign)
136 {
137 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
138
139 unsigned idx = fninfo->num_params++;
140 assert(idx < ARRAY_SIZE(fninfo->types));
141
142 if (regfile == ARG_SGPR)
143 fninfo->num_sgpr_params = fninfo->num_params;
144
145 fninfo->types[idx] = type;
146 fninfo->assign[idx] = assign;
147 return idx;
148 }
149
150 static unsigned add_arg(struct si_function_info *fninfo,
151 enum si_arg_regfile regfile, LLVMTypeRef type)
152 {
153 return add_arg_assign(fninfo, regfile, type, NULL);
154 }
155
156 static void add_arg_assign_checked(struct si_function_info *fninfo,
157 enum si_arg_regfile regfile, LLVMTypeRef type,
158 LLVMValueRef *assign, unsigned idx)
159 {
160 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
161 assert(actual == idx);
162 }
163
164 static void add_arg_checked(struct si_function_info *fninfo,
165 enum si_arg_regfile regfile, LLVMTypeRef type,
166 unsigned idx)
167 {
168 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
169 }
170
171 /**
172 * Returns a unique index for a per-patch semantic name and index. The index
173 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
174 * can be calculated.
175 */
176 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
177 {
178 switch (semantic_name) {
179 case TGSI_SEMANTIC_TESSOUTER:
180 return 0;
181 case TGSI_SEMANTIC_TESSINNER:
182 return 1;
183 case TGSI_SEMANTIC_PATCH:
184 assert(index < 30);
185 return 2 + index;
186
187 default:
188 assert(!"invalid semantic name");
189 return 0;
190 }
191 }
192
193 /**
194 * Returns a unique index for a semantic name and index. The index must be
195 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
196 * calculated.
197 */
198 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
199 {
200 switch (semantic_name) {
201 case TGSI_SEMANTIC_POSITION:
202 return 0;
203 case TGSI_SEMANTIC_GENERIC:
204 /* Since some shader stages use the the highest used IO index
205 * to determine the size to allocate for inputs/outputs
206 * (in LDS, tess and GS rings). GENERIC should be placed right
207 * after POSITION to make that size as small as possible.
208 */
209 if (index < SI_MAX_IO_GENERIC)
210 return 1 + index;
211
212 assert(!"invalid generic index");
213 return 0;
214 case TGSI_SEMANTIC_PSIZE:
215 return SI_MAX_IO_GENERIC + 1;
216 case TGSI_SEMANTIC_CLIPDIST:
217 assert(index <= 1);
218 return SI_MAX_IO_GENERIC + 2 + index;
219 case TGSI_SEMANTIC_FOG:
220 return SI_MAX_IO_GENERIC + 4;
221 case TGSI_SEMANTIC_LAYER:
222 return SI_MAX_IO_GENERIC + 5;
223 case TGSI_SEMANTIC_VIEWPORT_INDEX:
224 return SI_MAX_IO_GENERIC + 6;
225 case TGSI_SEMANTIC_PRIMID:
226 return SI_MAX_IO_GENERIC + 7;
227 case TGSI_SEMANTIC_COLOR: /* these alias */
228 case TGSI_SEMANTIC_BCOLOR:
229 assert(index < 2);
230 return SI_MAX_IO_GENERIC + 8 + index;
231 case TGSI_SEMANTIC_TEXCOORD:
232 assert(index < 8);
233 assert(SI_MAX_IO_GENERIC + 10 + index < 64);
234 return SI_MAX_IO_GENERIC + 10 + index;
235 default:
236 assert(!"invalid semantic name");
237 return 0;
238 }
239 }
240
241 /**
242 * Get the value of a shader input parameter and extract a bitfield.
243 */
244 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
245 LLVMValueRef value, unsigned rshift,
246 unsigned bitwidth)
247 {
248 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
249 value = ac_to_integer(&ctx->ac, value);
250
251 if (rshift)
252 value = LLVMBuildLShr(ctx->ac.builder, value,
253 LLVMConstInt(ctx->i32, rshift, 0), "");
254
255 if (rshift + bitwidth < 32) {
256 unsigned mask = (1 << bitwidth) - 1;
257 value = LLVMBuildAnd(ctx->ac.builder, value,
258 LLVMConstInt(ctx->i32, mask, 0), "");
259 }
260
261 return value;
262 }
263
264 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
265 unsigned param, unsigned rshift,
266 unsigned bitwidth)
267 {
268 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
269
270 return unpack_llvm_param(ctx, value, rshift, bitwidth);
271 }
272
273 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
274 {
275 switch (ctx->type) {
276 case PIPE_SHADER_TESS_CTRL:
277 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
278
279 case PIPE_SHADER_TESS_EVAL:
280 return LLVMGetParam(ctx->main_fn,
281 ctx->param_tes_rel_patch_id);
282
283 default:
284 assert(0);
285 return NULL;
286 }
287 }
288
289 /* Tessellation shaders pass outputs to the next shader using LDS.
290 *
291 * LS outputs = TCS inputs
292 * TCS outputs = TES inputs
293 *
294 * The LDS layout is:
295 * - TCS inputs for patch 0
296 * - TCS inputs for patch 1
297 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
298 * - ...
299 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
300 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
301 * - TCS outputs for patch 1
302 * - Per-patch TCS outputs for patch 1
303 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
304 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
305 * - ...
306 *
307 * All three shaders VS(LS), TCS, TES share the same LDS space.
308 */
309
310 static LLVMValueRef
311 get_tcs_in_patch_stride(struct si_shader_context *ctx)
312 {
313 return unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
314 }
315
316 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
317 {
318 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
319
320 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
321 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
322
323 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
324 }
325
326 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
327 {
328 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
329
330 return LLVMConstInt(ctx->i32, stride, 0);
331 }
332
333 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
334 {
335 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
336 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
337
338 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
339 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
340 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
341 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
342 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
343 num_patch_outputs * 4;
344 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
345 }
346
347 static LLVMValueRef
348 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
349 {
350 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
351 unpack_param(ctx,
352 ctx->param_tcs_out_lds_offsets,
353 0, 16),
354 4);
355 }
356
357 static LLVMValueRef
358 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
359 {
360 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
361 unpack_param(ctx,
362 ctx->param_tcs_out_lds_offsets,
363 16, 16),
364 4);
365 }
366
367 static LLVMValueRef
368 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
369 {
370 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
371 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
372
373 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
374 }
375
376 static LLVMValueRef
377 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
378 {
379 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
380 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
381 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
382
383 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
384 LLVMBuildMul(ctx->ac.builder, patch_stride,
385 rel_patch_id, ""),
386 "");
387 }
388
389 static LLVMValueRef
390 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
391 {
392 LLVMValueRef patch0_patch_data_offset =
393 get_tcs_out_patch0_patch_data_offset(ctx);
394 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
395 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
396
397 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
398 LLVMBuildMul(ctx->ac.builder, patch_stride,
399 rel_patch_id, ""),
400 "");
401 }
402
403 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
404 {
405 unsigned tcs_out_vertices =
406 ctx->shader->selector ?
407 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
408
409 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
410 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
411 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
412
413 return unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
414 }
415
416 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
417 {
418 unsigned stride;
419
420 switch (ctx->type) {
421 case PIPE_SHADER_VERTEX:
422 stride = util_last_bit64(ctx->shader->selector->outputs_written);
423 return LLVMConstInt(ctx->i32, stride * 4, 0);
424
425 case PIPE_SHADER_TESS_CTRL:
426 if (ctx->screen->info.chip_class >= GFX9 &&
427 ctx->shader->is_monolithic) {
428 stride = util_last_bit64(ctx->shader->key.part.tcs.ls->outputs_written);
429 return LLVMConstInt(ctx->i32, stride * 4, 0);
430 }
431 return unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
432
433 default:
434 assert(0);
435 return NULL;
436 }
437 }
438
439 static LLVMValueRef get_instance_index_for_fetch(
440 struct si_shader_context *ctx,
441 unsigned param_start_instance, LLVMValueRef divisor)
442 {
443 LLVMValueRef result = ctx->abi.instance_id;
444
445 /* The division must be done before START_INSTANCE is added. */
446 if (divisor != ctx->i32_1)
447 result = LLVMBuildUDiv(ctx->ac.builder, result, divisor, "");
448
449 return LLVMBuildAdd(ctx->ac.builder, result,
450 LLVMGetParam(ctx->main_fn, param_start_instance), "");
451 }
452
453 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
454 * to float. */
455 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
456 LLVMValueRef vec4,
457 unsigned double_index)
458 {
459 LLVMBuilderRef builder = ctx->ac.builder;
460 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->ac.context);
461 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
462 LLVMVectorType(f64, 2), "");
463 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
464 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
465 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
466 }
467
468 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
469 LLVMValueRef i32, unsigned index)
470 {
471 assert(index <= 1);
472
473 if (index == 1)
474 return LLVMBuildAShr(ctx->ac.builder, i32,
475 LLVMConstInt(ctx->i32, 16, 0), "");
476
477 return LLVMBuildSExt(ctx->ac.builder,
478 LLVMBuildTrunc(ctx->ac.builder, i32,
479 ctx->ac.i16, ""),
480 ctx->i32, "");
481 }
482
483 void si_llvm_load_input_vs(
484 struct si_shader_context *ctx,
485 unsigned input_index,
486 LLVMValueRef out[4])
487 {
488 unsigned vs_blit_property =
489 ctx->shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
490
491 if (vs_blit_property) {
492 LLVMValueRef vertex_id = ctx->abi.vertex_id;
493 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
494 LLVMIntULE, vertex_id,
495 ctx->i32_1, "");
496 /* Use LLVMIntNE, because we have 3 vertices and only
497 * the middle one should use y2.
498 */
499 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
500 LLVMIntNE, vertex_id,
501 ctx->i32_1, "");
502
503 if (input_index == 0) {
504 /* Position: */
505 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
506 ctx->param_vs_blit_inputs);
507 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
508 ctx->param_vs_blit_inputs + 1);
509
510 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
511 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
512 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
513 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
514
515 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
516 x1, x2, "");
517 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
518 y1, y2, "");
519
520 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
521 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
522 out[2] = LLVMGetParam(ctx->main_fn,
523 ctx->param_vs_blit_inputs + 2);
524 out[3] = ctx->ac.f32_1;
525 return;
526 }
527
528 /* Color or texture coordinates: */
529 assert(input_index == 1);
530
531 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
532 for (int i = 0; i < 4; i++) {
533 out[i] = LLVMGetParam(ctx->main_fn,
534 ctx->param_vs_blit_inputs + 3 + i);
535 }
536 } else {
537 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
538 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
539 ctx->param_vs_blit_inputs + 3);
540 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
541 ctx->param_vs_blit_inputs + 4);
542 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
543 ctx->param_vs_blit_inputs + 5);
544 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
545 ctx->param_vs_blit_inputs + 6);
546
547 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
548 x1, x2, "");
549 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
550 y1, y2, "");
551 out[2] = LLVMGetParam(ctx->main_fn,
552 ctx->param_vs_blit_inputs + 7);
553 out[3] = LLVMGetParam(ctx->main_fn,
554 ctx->param_vs_blit_inputs + 8);
555 }
556 return;
557 }
558
559 unsigned chan;
560 unsigned fix_fetch;
561 unsigned num_fetches;
562 unsigned fetch_stride;
563
564 LLVMValueRef t_list_ptr;
565 LLVMValueRef t_offset;
566 LLVMValueRef t_list;
567 LLVMValueRef vertex_index;
568 LLVMValueRef input[3];
569
570 /* Load the T list */
571 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
572
573 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
574
575 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
576
577 vertex_index = LLVMGetParam(ctx->main_fn,
578 ctx->param_vertex_index0 +
579 input_index);
580
581 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
582
583 /* Do multiple loads for special formats. */
584 switch (fix_fetch) {
585 case SI_FIX_FETCH_RGB_64_FLOAT:
586 num_fetches = 3; /* 3 2-dword loads */
587 fetch_stride = 8;
588 break;
589 case SI_FIX_FETCH_RGBA_64_FLOAT:
590 num_fetches = 2; /* 2 4-dword loads */
591 fetch_stride = 16;
592 break;
593 case SI_FIX_FETCH_RGB_8:
594 case SI_FIX_FETCH_RGB_8_INT:
595 num_fetches = 3;
596 fetch_stride = 1;
597 break;
598 case SI_FIX_FETCH_RGB_16:
599 case SI_FIX_FETCH_RGB_16_INT:
600 num_fetches = 3;
601 fetch_stride = 2;
602 break;
603 default:
604 num_fetches = 1;
605 fetch_stride = 0;
606 }
607
608 for (unsigned i = 0; i < num_fetches; i++) {
609 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
610
611 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
612 vertex_index, voffset,
613 true);
614 }
615
616 /* Break up the vec4 into individual components */
617 for (chan = 0; chan < 4; chan++) {
618 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
619 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
620 input[0], llvm_chan, "");
621 }
622
623 switch (fix_fetch) {
624 case SI_FIX_FETCH_A2_SNORM:
625 case SI_FIX_FETCH_A2_SSCALED:
626 case SI_FIX_FETCH_A2_SINT: {
627 /* The hardware returns an unsigned value; convert it to a
628 * signed one.
629 */
630 LLVMValueRef tmp = out[3];
631 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
632
633 /* First, recover the sign-extended signed integer value. */
634 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
635 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
636 else
637 tmp = ac_to_integer(&ctx->ac, tmp);
638
639 /* For the integer-like cases, do a natural sign extension.
640 *
641 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
642 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
643 * exponent.
644 */
645 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
646 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
647 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
648 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
649
650 /* Convert back to the right type. */
651 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
652 LLVMValueRef clamp;
653 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
654 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
655 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
656 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
657 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
658 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
659 }
660
661 out[3] = tmp;
662 break;
663 }
664 case SI_FIX_FETCH_RGBA_32_UNORM:
665 case SI_FIX_FETCH_RGBX_32_UNORM:
666 for (chan = 0; chan < 4; chan++) {
667 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
668 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
669 out[chan], ctx->f32, "");
670 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
671 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
672 }
673 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
674 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
675 out[3] = LLVMConstReal(ctx->f32, 1);
676 break;
677 case SI_FIX_FETCH_RGBA_32_SNORM:
678 case SI_FIX_FETCH_RGBX_32_SNORM:
679 case SI_FIX_FETCH_RGBA_32_FIXED:
680 case SI_FIX_FETCH_RGBX_32_FIXED: {
681 double scale;
682 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
683 scale = 1.0 / 0x10000;
684 else
685 scale = 1.0 / INT_MAX;
686
687 for (chan = 0; chan < 4; chan++) {
688 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
689 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
690 out[chan], ctx->f32, "");
691 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
692 LLVMConstReal(ctx->f32, scale), "");
693 }
694 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
695 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
696 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
697 out[3] = LLVMConstReal(ctx->f32, 1);
698 break;
699 }
700 case SI_FIX_FETCH_RGBA_32_USCALED:
701 for (chan = 0; chan < 4; chan++) {
702 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
703 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
704 out[chan], ctx->f32, "");
705 }
706 break;
707 case SI_FIX_FETCH_RGBA_32_SSCALED:
708 for (chan = 0; chan < 4; chan++) {
709 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
710 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
711 out[chan], ctx->f32, "");
712 }
713 break;
714 case SI_FIX_FETCH_RG_64_FLOAT:
715 for (chan = 0; chan < 2; chan++)
716 out[chan] = extract_double_to_float(ctx, input[0], chan);
717
718 out[2] = LLVMConstReal(ctx->f32, 0);
719 out[3] = LLVMConstReal(ctx->f32, 1);
720 break;
721 case SI_FIX_FETCH_RGB_64_FLOAT:
722 for (chan = 0; chan < 3; chan++)
723 out[chan] = extract_double_to_float(ctx, input[chan], 0);
724
725 out[3] = LLVMConstReal(ctx->f32, 1);
726 break;
727 case SI_FIX_FETCH_RGBA_64_FLOAT:
728 for (chan = 0; chan < 4; chan++) {
729 out[chan] = extract_double_to_float(ctx, input[chan / 2],
730 chan % 2);
731 }
732 break;
733 case SI_FIX_FETCH_RGB_8:
734 case SI_FIX_FETCH_RGB_8_INT:
735 case SI_FIX_FETCH_RGB_16:
736 case SI_FIX_FETCH_RGB_16_INT:
737 for (chan = 0; chan < 3; chan++) {
738 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
739 input[chan],
740 ctx->i32_0, "");
741 }
742 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
743 fix_fetch == SI_FIX_FETCH_RGB_16) {
744 out[3] = LLVMConstReal(ctx->f32, 1);
745 } else {
746 out[3] = ac_to_float(&ctx->ac, ctx->i32_1);
747 }
748 break;
749 }
750 }
751
752 static void declare_input_vs(
753 struct si_shader_context *ctx,
754 unsigned input_index,
755 const struct tgsi_full_declaration *decl,
756 LLVMValueRef out[4])
757 {
758 si_llvm_load_input_vs(ctx, input_index, out);
759 }
760
761 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
762 unsigned swizzle)
763 {
764 if (swizzle > 0)
765 return ctx->i32_0;
766
767 switch (ctx->type) {
768 case PIPE_SHADER_VERTEX:
769 return LLVMGetParam(ctx->main_fn,
770 ctx->param_vs_prim_id);
771 case PIPE_SHADER_TESS_CTRL:
772 return ctx->abi.tcs_patch_id;
773 case PIPE_SHADER_TESS_EVAL:
774 return ctx->abi.tes_patch_id;
775 case PIPE_SHADER_GEOMETRY:
776 return ctx->abi.gs_prim_id;
777 default:
778 assert(0);
779 return ctx->i32_0;
780 }
781 }
782
783 /**
784 * Return the value of tgsi_ind_register for indexing.
785 * This is the indirect index with the constant offset added to it.
786 */
787 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
788 const struct tgsi_ind_register *ind,
789 unsigned addr_mul,
790 int rel_index)
791 {
792 LLVMValueRef result;
793
794 if (ind->File == TGSI_FILE_ADDRESS) {
795 result = ctx->addrs[ind->Index][ind->Swizzle];
796 result = LLVMBuildLoad(ctx->ac.builder, result, "");
797 } else {
798 struct tgsi_full_src_register src = {};
799
800 src.Register.File = ind->File;
801 src.Register.Index = ind->Index;
802
803 /* Set the second index to 0 for constants. */
804 if (ind->File == TGSI_FILE_CONSTANT)
805 src.Register.Dimension = 1;
806
807 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
808 TGSI_TYPE_SIGNED,
809 ind->Swizzle);
810 result = ac_to_integer(&ctx->ac, result);
811 }
812
813 if (addr_mul != 1)
814 result = LLVMBuildMul(ctx->ac.builder, result,
815 LLVMConstInt(ctx->i32, addr_mul, 0), "");
816 result = LLVMBuildAdd(ctx->ac.builder, result,
817 LLVMConstInt(ctx->i32, rel_index, 0), "");
818 return result;
819 }
820
821 /**
822 * Like si_get_indirect_index, but restricts the return value to a (possibly
823 * undefined) value inside [0..num).
824 */
825 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
826 const struct tgsi_ind_register *ind,
827 int rel_index, unsigned num)
828 {
829 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
830
831 return si_llvm_bound_index(ctx, result, num);
832 }
833
834 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
835 LLVMValueRef vertex_dw_stride,
836 LLVMValueRef base_addr,
837 LLVMValueRef vertex_index,
838 LLVMValueRef param_index,
839 unsigned input_index,
840 ubyte *name,
841 ubyte *index,
842 bool is_patch)
843 {
844 if (vertex_dw_stride) {
845 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
846 LLVMBuildMul(ctx->ac.builder, vertex_index,
847 vertex_dw_stride, ""), "");
848 }
849
850 if (param_index) {
851 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
852 LLVMBuildMul(ctx->ac.builder, param_index,
853 LLVMConstInt(ctx->i32, 4, 0), ""), "");
854 }
855
856 int param = is_patch ?
857 si_shader_io_get_unique_index_patch(name[input_index],
858 index[input_index]) :
859 si_shader_io_get_unique_index(name[input_index],
860 index[input_index]);
861
862 /* Add the base address of the element. */
863 return LLVMBuildAdd(ctx->ac.builder, base_addr,
864 LLVMConstInt(ctx->i32, param * 4, 0), "");
865 }
866
867 /**
868 * Calculate a dword address given an input or output register and a stride.
869 */
870 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
871 const struct tgsi_full_dst_register *dst,
872 const struct tgsi_full_src_register *src,
873 LLVMValueRef vertex_dw_stride,
874 LLVMValueRef base_addr)
875 {
876 struct tgsi_shader_info *info = &ctx->shader->selector->info;
877 ubyte *name, *index, *array_first;
878 int input_index;
879 struct tgsi_full_dst_register reg;
880 LLVMValueRef vertex_index = NULL;
881 LLVMValueRef ind_index = NULL;
882
883 /* Set the register description. The address computation is the same
884 * for sources and destinations. */
885 if (src) {
886 reg.Register.File = src->Register.File;
887 reg.Register.Index = src->Register.Index;
888 reg.Register.Indirect = src->Register.Indirect;
889 reg.Register.Dimension = src->Register.Dimension;
890 reg.Indirect = src->Indirect;
891 reg.Dimension = src->Dimension;
892 reg.DimIndirect = src->DimIndirect;
893 } else
894 reg = *dst;
895
896 /* If the register is 2-dimensional (e.g. an array of vertices
897 * in a primitive), calculate the base address of the vertex. */
898 if (reg.Register.Dimension) {
899 if (reg.Dimension.Indirect)
900 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
901 1, reg.Dimension.Index);
902 else
903 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
904 }
905
906 /* Get information about the register. */
907 if (reg.Register.File == TGSI_FILE_INPUT) {
908 name = info->input_semantic_name;
909 index = info->input_semantic_index;
910 array_first = info->input_array_first;
911 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
912 name = info->output_semantic_name;
913 index = info->output_semantic_index;
914 array_first = info->output_array_first;
915 } else {
916 assert(0);
917 return NULL;
918 }
919
920 if (reg.Register.Indirect) {
921 /* Add the relative address of the element. */
922 if (reg.Indirect.ArrayID)
923 input_index = array_first[reg.Indirect.ArrayID];
924 else
925 input_index = reg.Register.Index;
926
927 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
928 1, reg.Register.Index - input_index);
929 } else {
930 input_index = reg.Register.Index;
931 }
932
933 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
934 base_addr, vertex_index,
935 ind_index, input_index,
936 name, index,
937 !reg.Register.Dimension);
938 }
939
940 /* The offchip buffer layout for TCS->TES is
941 *
942 * - attribute 0 of patch 0 vertex 0
943 * - attribute 0 of patch 0 vertex 1
944 * - attribute 0 of patch 0 vertex 2
945 * ...
946 * - attribute 0 of patch 1 vertex 0
947 * - attribute 0 of patch 1 vertex 1
948 * ...
949 * - attribute 1 of patch 0 vertex 0
950 * - attribute 1 of patch 0 vertex 1
951 * ...
952 * - per patch attribute 0 of patch 0
953 * - per patch attribute 0 of patch 1
954 * ...
955 *
956 * Note that every attribute has 4 components.
957 */
958 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
959 LLVMValueRef rel_patch_id,
960 LLVMValueRef vertex_index,
961 LLVMValueRef param_index)
962 {
963 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
964 LLVMValueRef param_stride, constant16;
965
966 vertices_per_patch = get_num_tcs_out_vertices(ctx);
967 num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
968 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
969 num_patches, "");
970
971 constant16 = LLVMConstInt(ctx->i32, 16, 0);
972 if (vertex_index) {
973 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
974 vertices_per_patch, "");
975
976 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
977 vertex_index, "");
978
979 param_stride = total_vertices;
980 } else {
981 base_addr = rel_patch_id;
982 param_stride = num_patches;
983 }
984
985 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
986 LLVMBuildMul(ctx->ac.builder, param_index,
987 param_stride, ""), "");
988
989 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
990
991 if (!vertex_index) {
992 LLVMValueRef patch_data_offset =
993 unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
994
995 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
996 patch_data_offset, "");
997 }
998 return base_addr;
999 }
1000
1001 /* This is a generic helper that can be shared by the NIR and TGSI backends */
1002 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
1003 struct si_shader_context *ctx,
1004 LLVMValueRef vertex_index,
1005 LLVMValueRef param_index,
1006 unsigned param_base,
1007 ubyte *name,
1008 ubyte *index,
1009 bool is_patch)
1010 {
1011 unsigned param_index_base;
1012
1013 param_index_base = is_patch ?
1014 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
1015 si_shader_io_get_unique_index(name[param_base], index[param_base]);
1016
1017 if (param_index) {
1018 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1019 LLVMConstInt(ctx->i32, param_index_base, 0),
1020 "");
1021 } else {
1022 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
1023 }
1024
1025 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
1026 vertex_index, param_index);
1027 }
1028
1029 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
1030 struct si_shader_context *ctx,
1031 const struct tgsi_full_dst_register *dst,
1032 const struct tgsi_full_src_register *src)
1033 {
1034 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1035 ubyte *name, *index, *array_first;
1036 struct tgsi_full_src_register reg;
1037 LLVMValueRef vertex_index = NULL;
1038 LLVMValueRef param_index = NULL;
1039 unsigned param_base;
1040
1041 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
1042
1043 if (reg.Register.Dimension) {
1044
1045 if (reg.Dimension.Indirect)
1046 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
1047 1, reg.Dimension.Index);
1048 else
1049 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
1050 }
1051
1052 /* Get information about the register. */
1053 if (reg.Register.File == TGSI_FILE_INPUT) {
1054 name = info->input_semantic_name;
1055 index = info->input_semantic_index;
1056 array_first = info->input_array_first;
1057 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1058 name = info->output_semantic_name;
1059 index = info->output_semantic_index;
1060 array_first = info->output_array_first;
1061 } else {
1062 assert(0);
1063 return NULL;
1064 }
1065
1066 if (reg.Register.Indirect) {
1067 if (reg.Indirect.ArrayID)
1068 param_base = array_first[reg.Indirect.ArrayID];
1069 else
1070 param_base = reg.Register.Index;
1071
1072 param_index = si_get_indirect_index(ctx, &reg.Indirect,
1073 1, reg.Register.Index - param_base);
1074
1075 } else {
1076 param_base = reg.Register.Index;
1077 }
1078
1079 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1080 param_index, param_base,
1081 name, index, !reg.Register.Dimension);
1082 }
1083
1084 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
1085 LLVMTypeRef type, unsigned swizzle,
1086 LLVMValueRef buffer, LLVMValueRef offset,
1087 LLVMValueRef base, bool can_speculate)
1088 {
1089 struct si_shader_context *ctx = si_shader_context(bld_base);
1090 LLVMValueRef value, value2;
1091 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
1092
1093 if (swizzle == ~0) {
1094 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1095 0, 1, 0, can_speculate, false);
1096
1097 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1098 }
1099
1100 if (!llvm_type_is_64bit(ctx, type)) {
1101 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1102 0, 1, 0, can_speculate, false);
1103
1104 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1105 return LLVMBuildExtractElement(ctx->ac.builder, value,
1106 LLVMConstInt(ctx->i32, swizzle, 0), "");
1107 }
1108
1109 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1110 swizzle * 4, 1, 0, can_speculate, false);
1111
1112 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1113 swizzle * 4 + 4, 1, 0, can_speculate, false);
1114
1115 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1116 }
1117
1118 /**
1119 * Load from LDS.
1120 *
1121 * \param type output value type
1122 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1123 * \param dw_addr address in dwords
1124 */
1125 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1126 LLVMTypeRef type, unsigned swizzle,
1127 LLVMValueRef dw_addr)
1128 {
1129 struct si_shader_context *ctx = si_shader_context(bld_base);
1130 LLVMValueRef value;
1131
1132 if (swizzle == ~0) {
1133 LLVMValueRef values[TGSI_NUM_CHANNELS];
1134
1135 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1136 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1137
1138 return lp_build_gather_values(&ctx->gallivm, values,
1139 TGSI_NUM_CHANNELS);
1140 }
1141
1142 /* Split 64-bit loads. */
1143 if (llvm_type_is_64bit(ctx, type)) {
1144 LLVMValueRef lo, hi;
1145
1146 lo = lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1147 hi = lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1148 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1149 }
1150
1151 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1152 LLVMConstInt(ctx->i32, swizzle, 0));
1153
1154 value = ac_lds_load(&ctx->ac, dw_addr);
1155
1156 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1157 }
1158
1159 /**
1160 * Store to LDS.
1161 *
1162 * \param swizzle offset (typically 0..3)
1163 * \param dw_addr address in dwords
1164 * \param value value to store
1165 */
1166 static void lds_store(struct si_shader_context *ctx,
1167 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1168 LLVMValueRef value)
1169 {
1170 dw_addr = lp_build_add(&ctx->bld_base.uint_bld, dw_addr,
1171 LLVMConstInt(ctx->i32, dw_offset_imm, 0));
1172
1173 ac_lds_store(&ctx->ac, dw_addr, value);
1174 }
1175
1176 static LLVMValueRef desc_from_addr_base64k(struct si_shader_context *ctx,
1177 unsigned param)
1178 {
1179 LLVMBuilderRef builder = ctx->ac.builder;
1180
1181 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1182 addr = LLVMBuildZExt(builder, addr, ctx->i64, "");
1183 addr = LLVMBuildShl(builder, addr, LLVMConstInt(ctx->i64, 16, 0), "");
1184
1185 uint64_t desc2 = 0xffffffff;
1186 uint64_t desc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1187 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1188 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1189 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1190 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1191 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1192 LLVMValueRef hi = LLVMConstInt(ctx->i64, desc2 | (desc3 << 32), 0);
1193
1194 LLVMValueRef desc = LLVMGetUndef(LLVMVectorType(ctx->i64, 2));
1195 desc = LLVMBuildInsertElement(builder, desc, addr, ctx->i32_0, "");
1196 desc = LLVMBuildInsertElement(builder, desc, hi, ctx->i32_1, "");
1197 return LLVMBuildBitCast(builder, desc, ctx->v4i32, "");
1198 }
1199
1200 static LLVMValueRef fetch_input_tcs(
1201 struct lp_build_tgsi_context *bld_base,
1202 const struct tgsi_full_src_register *reg,
1203 enum tgsi_opcode_type type, unsigned swizzle)
1204 {
1205 struct si_shader_context *ctx = si_shader_context(bld_base);
1206 LLVMValueRef dw_addr, stride;
1207
1208 stride = get_tcs_in_vertex_dw_stride(ctx);
1209 dw_addr = get_tcs_in_current_patch_offset(ctx);
1210 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1211
1212 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1213 }
1214
1215 static LLVMValueRef si_nir_load_input_tcs(struct ac_shader_abi *abi,
1216 LLVMValueRef vertex_index,
1217 LLVMValueRef param_index,
1218 unsigned const_index,
1219 unsigned location,
1220 unsigned driver_location,
1221 unsigned component,
1222 unsigned num_components,
1223 bool is_patch,
1224 bool is_compact)
1225 {
1226 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1227 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1228 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1229 LLVMValueRef dw_addr, stride;
1230
1231 driver_location = driver_location / 4;
1232
1233 stride = get_tcs_in_vertex_dw_stride(ctx);
1234 dw_addr = get_tcs_in_current_patch_offset(ctx);
1235
1236 if (param_index) {
1237 /* Add the constant index to the indirect index */
1238 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1239 LLVMConstInt(ctx->i32, const_index, 0), "");
1240 } else {
1241 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1242 }
1243
1244 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1245 vertex_index, param_index,
1246 driver_location,
1247 info->input_semantic_name,
1248 info->input_semantic_index,
1249 is_patch);
1250
1251 LLVMValueRef value[4];
1252 for (unsigned i = 0; i < num_components + component; i++) {
1253 value[i] = lds_load(bld_base, ctx->i32, i, dw_addr);
1254 }
1255
1256 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1257 }
1258
1259 static LLVMValueRef fetch_output_tcs(
1260 struct lp_build_tgsi_context *bld_base,
1261 const struct tgsi_full_src_register *reg,
1262 enum tgsi_opcode_type type, unsigned swizzle)
1263 {
1264 struct si_shader_context *ctx = si_shader_context(bld_base);
1265 LLVMValueRef dw_addr, stride;
1266
1267 if (reg->Register.Dimension) {
1268 stride = get_tcs_out_vertex_dw_stride(ctx);
1269 dw_addr = get_tcs_out_current_patch_offset(ctx);
1270 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1271 } else {
1272 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1273 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1274 }
1275
1276 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1277 }
1278
1279 static LLVMValueRef fetch_input_tes(
1280 struct lp_build_tgsi_context *bld_base,
1281 const struct tgsi_full_src_register *reg,
1282 enum tgsi_opcode_type type, unsigned swizzle)
1283 {
1284 struct si_shader_context *ctx = si_shader_context(bld_base);
1285 LLVMValueRef buffer, base, addr;
1286
1287 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1288
1289 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1290 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1291
1292 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1293 buffer, base, addr, true);
1294 }
1295
1296 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1297 LLVMValueRef vertex_index,
1298 LLVMValueRef param_index,
1299 unsigned const_index,
1300 unsigned location,
1301 unsigned driver_location,
1302 unsigned component,
1303 unsigned num_components,
1304 bool is_patch,
1305 bool is_compact)
1306 {
1307 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1308 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1309 LLVMValueRef buffer, base, addr;
1310
1311 driver_location = driver_location / 4;
1312
1313 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1314
1315 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1316
1317 if (param_index) {
1318 /* Add the constant index to the indirect index */
1319 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1320 LLVMConstInt(ctx->i32, const_index, 0), "");
1321 } else {
1322 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1323 }
1324
1325 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1326 param_index, driver_location,
1327 info->input_semantic_name,
1328 info->input_semantic_index,
1329 is_patch);
1330
1331 /* TODO: This will generate rather ordinary llvm code, although it
1332 * should be easy for the optimiser to fix up. In future we might want
1333 * to refactor buffer_load(), but for now this maximises code sharing
1334 * between the NIR and TGSI backends.
1335 */
1336 LLVMValueRef value[4];
1337 for (unsigned i = component; i < num_components + component; i++) {
1338 value[i] = buffer_load(&ctx->bld_base, ctx->i32, i, buffer, base, addr, true);
1339 }
1340
1341 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1342 }
1343
1344 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1345 const struct tgsi_full_instruction *inst,
1346 const struct tgsi_opcode_info *info,
1347 unsigned index,
1348 LLVMValueRef dst[4])
1349 {
1350 struct si_shader_context *ctx = si_shader_context(bld_base);
1351 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1352 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1353 unsigned chan_index;
1354 LLVMValueRef dw_addr, stride;
1355 LLVMValueRef buffer, base, buf_addr;
1356 LLVMValueRef values[4];
1357 bool skip_lds_store;
1358 bool is_tess_factor = false, is_tess_inner = false;
1359
1360 /* Only handle per-patch and per-vertex outputs here.
1361 * Vectors will be lowered to scalars and this function will be called again.
1362 */
1363 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1364 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1365 si_llvm_emit_store(bld_base, inst, info, index, dst);
1366 return;
1367 }
1368
1369 if (reg->Register.Dimension) {
1370 stride = get_tcs_out_vertex_dw_stride(ctx);
1371 dw_addr = get_tcs_out_current_patch_offset(ctx);
1372 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1373 skip_lds_store = !sh_info->reads_pervertex_outputs;
1374 } else {
1375 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1376 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1377 skip_lds_store = !sh_info->reads_perpatch_outputs;
1378
1379 if (!reg->Register.Indirect) {
1380 int name = sh_info->output_semantic_name[reg->Register.Index];
1381
1382 /* Always write tess factors into LDS for the TCS epilog. */
1383 if (name == TGSI_SEMANTIC_TESSINNER ||
1384 name == TGSI_SEMANTIC_TESSOUTER) {
1385 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1386 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1387 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1388 is_tess_factor = true;
1389 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1390 }
1391 }
1392 }
1393
1394 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1395
1396 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1397 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1398
1399 uint32_t writemask = reg->Register.WriteMask;
1400 while (writemask) {
1401 chan_index = u_bit_scan(&writemask);
1402 LLVMValueRef value = dst[chan_index];
1403
1404 if (inst->Instruction.Saturate)
1405 value = ac_build_clamp(&ctx->ac, value);
1406
1407 /* Skip LDS stores if there is no LDS read of this output. */
1408 if (!skip_lds_store)
1409 lds_store(ctx, chan_index, dw_addr, value);
1410
1411 value = ac_to_integer(&ctx->ac, value);
1412 values[chan_index] = value;
1413
1414 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1415 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1416 buf_addr, base,
1417 4 * chan_index, 1, 0, true, false);
1418 }
1419
1420 /* Write tess factors into VGPRs for the epilog. */
1421 if (is_tess_factor &&
1422 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1423 if (!is_tess_inner) {
1424 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1425 ctx->invoc0_tess_factors[chan_index]);
1426 } else if (chan_index < 2) {
1427 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1428 ctx->invoc0_tess_factors[4 + chan_index]);
1429 }
1430 }
1431 }
1432
1433 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1434 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1435 values, 4);
1436 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1437 base, 0, 1, 0, true, false);
1438 }
1439 }
1440
1441 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1442 LLVMValueRef vertex_index,
1443 LLVMValueRef param_index,
1444 unsigned const_index,
1445 unsigned location,
1446 unsigned driver_location,
1447 LLVMValueRef src,
1448 unsigned component,
1449 bool is_patch,
1450 bool is_compact,
1451 unsigned writemask)
1452 {
1453 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1454 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1455 LLVMValueRef dw_addr, stride;
1456 LLVMValueRef buffer, base, addr;
1457 LLVMValueRef values[4];
1458 bool skip_lds_store;
1459 bool is_tess_factor = false, is_tess_inner = false;
1460
1461 driver_location = driver_location / 4;
1462
1463 if (param_index) {
1464 /* Add the constant index to the indirect index */
1465 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1466 LLVMConstInt(ctx->i32, const_index, 0), "");
1467 } else {
1468 if (const_index != 0)
1469 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1470 }
1471
1472 if (!is_patch) {
1473 stride = get_tcs_out_vertex_dw_stride(ctx);
1474 dw_addr = get_tcs_out_current_patch_offset(ctx);
1475 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1476 vertex_index, param_index,
1477 driver_location,
1478 info->output_semantic_name,
1479 info->output_semantic_index,
1480 is_patch);
1481
1482 skip_lds_store = !info->reads_pervertex_outputs;
1483 } else {
1484 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1485 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1486 vertex_index, param_index,
1487 driver_location,
1488 info->output_semantic_name,
1489 info->output_semantic_index,
1490 is_patch);
1491
1492 skip_lds_store = !info->reads_perpatch_outputs;
1493
1494 if (!param_index) {
1495 int name = info->output_semantic_name[driver_location];
1496
1497 /* Always write tess factors into LDS for the TCS epilog. */
1498 if (name == TGSI_SEMANTIC_TESSINNER ||
1499 name == TGSI_SEMANTIC_TESSOUTER) {
1500 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1501 skip_lds_store = !info->reads_tessfactor_outputs &&
1502 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1503 is_tess_factor = true;
1504 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1505 }
1506 }
1507 }
1508
1509 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1510
1511 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1512
1513 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1514 param_index, driver_location,
1515 info->output_semantic_name,
1516 info->output_semantic_index,
1517 is_patch);
1518
1519 for (unsigned chan = 0; chan < 4; chan++) {
1520 if (!(writemask & (1 << chan)))
1521 continue;
1522 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1523
1524 /* Skip LDS stores if there is no LDS read of this output. */
1525 if (!skip_lds_store)
1526 ac_lds_store(&ctx->ac, dw_addr, value);
1527
1528 value = ac_to_integer(&ctx->ac, value);
1529 values[chan] = value;
1530
1531 if (writemask != 0xF && !is_tess_factor) {
1532 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1533 addr, base,
1534 4 * chan, 1, 0, true, false);
1535 }
1536
1537 /* Write tess factors into VGPRs for the epilog. */
1538 if (is_tess_factor &&
1539 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1540 if (!is_tess_inner) {
1541 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1542 ctx->invoc0_tess_factors[chan]);
1543 } else if (chan < 2) {
1544 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1545 ctx->invoc0_tess_factors[4 + chan]);
1546 }
1547 }
1548 }
1549
1550 if (writemask == 0xF && !is_tess_factor) {
1551 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1552 values, 4);
1553 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1554 base, 0, 1, 0, true, false);
1555 }
1556 }
1557
1558 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1559 unsigned input_index,
1560 unsigned vtx_offset_param,
1561 LLVMTypeRef type,
1562 unsigned swizzle)
1563 {
1564 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1565 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1566 struct si_shader *shader = ctx->shader;
1567 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1568 LLVMValueRef vtx_offset, soffset;
1569 struct tgsi_shader_info *info = &shader->selector->info;
1570 unsigned semantic_name = info->input_semantic_name[input_index];
1571 unsigned semantic_index = info->input_semantic_index[input_index];
1572 unsigned param;
1573 LLVMValueRef value;
1574
1575 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1576
1577 /* GFX9 has the ESGS ring in LDS. */
1578 if (ctx->screen->info.chip_class >= GFX9) {
1579 unsigned index = vtx_offset_param;
1580
1581 switch (index / 2) {
1582 case 0:
1583 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx01_offset,
1584 index % 2 ? 16 : 0, 16);
1585 break;
1586 case 1:
1587 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx23_offset,
1588 index % 2 ? 16 : 0, 16);
1589 break;
1590 case 2:
1591 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx45_offset,
1592 index % 2 ? 16 : 0, 16);
1593 break;
1594 default:
1595 assert(0);
1596 return NULL;
1597 }
1598
1599 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1600 LLVMConstInt(ctx->i32, param * 4, 0), "");
1601 return lds_load(bld_base, type, swizzle, vtx_offset);
1602 }
1603
1604 /* GFX6: input load from the ESGS ring in memory. */
1605 if (swizzle == ~0) {
1606 LLVMValueRef values[TGSI_NUM_CHANNELS];
1607 unsigned chan;
1608 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1609 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1610 type, chan);
1611 }
1612 return lp_build_gather_values(&ctx->gallivm, values,
1613 TGSI_NUM_CHANNELS);
1614 }
1615
1616 /* Get the vertex offset parameter on GFX6. */
1617 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1618
1619 vtx_offset = lp_build_mul_imm(uint, gs_vtx_offset, 4);
1620
1621 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1622
1623 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1624 vtx_offset, soffset, 0, 1, 0, true, false);
1625 if (llvm_type_is_64bit(ctx, type)) {
1626 LLVMValueRef value2;
1627 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1628
1629 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1630 ctx->i32_0, vtx_offset, soffset,
1631 0, 1, 0, true, false);
1632 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1633 }
1634 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1635 }
1636
1637 static LLVMValueRef fetch_input_gs(
1638 struct lp_build_tgsi_context *bld_base,
1639 const struct tgsi_full_src_register *reg,
1640 enum tgsi_opcode_type type,
1641 unsigned swizzle)
1642 {
1643 struct si_shader_context *ctx = si_shader_context(bld_base);
1644 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1645
1646 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1647 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1648 return get_primitive_id(ctx, swizzle);
1649
1650 if (!reg->Register.Dimension)
1651 return NULL;
1652
1653 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1654 reg->Dimension.Index,
1655 tgsi2llvmtype(bld_base, type),
1656 swizzle);
1657 }
1658
1659 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1660 {
1661 switch (interpolate) {
1662 case TGSI_INTERPOLATE_CONSTANT:
1663 return 0;
1664
1665 case TGSI_INTERPOLATE_LINEAR:
1666 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1667 return SI_PARAM_LINEAR_SAMPLE;
1668 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1669 return SI_PARAM_LINEAR_CENTROID;
1670 else
1671 return SI_PARAM_LINEAR_CENTER;
1672 break;
1673 case TGSI_INTERPOLATE_COLOR:
1674 case TGSI_INTERPOLATE_PERSPECTIVE:
1675 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1676 return SI_PARAM_PERSP_SAMPLE;
1677 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1678 return SI_PARAM_PERSP_CENTROID;
1679 else
1680 return SI_PARAM_PERSP_CENTER;
1681 break;
1682 default:
1683 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1684 return -1;
1685 }
1686 }
1687
1688 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1689 unsigned attr_index, unsigned chan,
1690 LLVMValueRef prim_mask,
1691 LLVMValueRef i, LLVMValueRef j)
1692 {
1693 if (i || j) {
1694 return ac_build_fs_interp(&ctx->ac,
1695 LLVMConstInt(ctx->i32, chan, 0),
1696 LLVMConstInt(ctx->i32, attr_index, 0),
1697 prim_mask, i, j);
1698 }
1699 return ac_build_fs_interp_mov(&ctx->ac,
1700 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1701 LLVMConstInt(ctx->i32, chan, 0),
1702 LLVMConstInt(ctx->i32, attr_index, 0),
1703 prim_mask);
1704 }
1705
1706 /**
1707 * Interpolate a fragment shader input.
1708 *
1709 * @param ctx context
1710 * @param input_index index of the input in hardware
1711 * @param semantic_name TGSI_SEMANTIC_*
1712 * @param semantic_index semantic index
1713 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1714 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1715 * @param interp_param interpolation weights (i,j)
1716 * @param prim_mask SI_PARAM_PRIM_MASK
1717 * @param face SI_PARAM_FRONT_FACE
1718 * @param result the return value (4 components)
1719 */
1720 static void interp_fs_input(struct si_shader_context *ctx,
1721 unsigned input_index,
1722 unsigned semantic_name,
1723 unsigned semantic_index,
1724 unsigned num_interp_inputs,
1725 unsigned colors_read_mask,
1726 LLVMValueRef interp_param,
1727 LLVMValueRef prim_mask,
1728 LLVMValueRef face,
1729 LLVMValueRef result[4])
1730 {
1731 LLVMValueRef i = NULL, j = NULL;
1732 unsigned chan;
1733
1734 /* fs.constant returns the param from the middle vertex, so it's not
1735 * really useful for flat shading. It's meant to be used for custom
1736 * interpolation (but the intrinsic can't fetch from the other two
1737 * vertices).
1738 *
1739 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1740 * to do the right thing. The only reason we use fs.constant is that
1741 * fs.interp cannot be used on integers, because they can be equal
1742 * to NaN.
1743 *
1744 * When interp is false we will use fs.constant or for newer llvm,
1745 * amdgcn.interp.mov.
1746 */
1747 bool interp = interp_param != NULL;
1748
1749 if (interp) {
1750 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1751 LLVMVectorType(ctx->f32, 2), "");
1752
1753 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1754 ctx->i32_0, "");
1755 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1756 ctx->i32_1, "");
1757 }
1758
1759 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1760 ctx->shader->key.part.ps.prolog.color_two_side) {
1761 LLVMValueRef is_face_positive;
1762
1763 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1764 * otherwise it's at offset "num_inputs".
1765 */
1766 unsigned back_attr_offset = num_interp_inputs;
1767 if (semantic_index == 1 && colors_read_mask & 0xf)
1768 back_attr_offset += 1;
1769
1770 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1771 face, ctx->i32_0, "");
1772
1773 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1774 LLVMValueRef front, back;
1775
1776 front = si_build_fs_interp(ctx,
1777 input_index, chan,
1778 prim_mask, i, j);
1779 back = si_build_fs_interp(ctx,
1780 back_attr_offset, chan,
1781 prim_mask, i, j);
1782
1783 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1784 is_face_positive,
1785 front,
1786 back,
1787 "");
1788 }
1789 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1790 result[0] = si_build_fs_interp(ctx, input_index,
1791 0, prim_mask, i, j);
1792 result[1] =
1793 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1794 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1795 } else {
1796 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1797 result[chan] = si_build_fs_interp(ctx,
1798 input_index, chan,
1799 prim_mask, i, j);
1800 }
1801 }
1802 }
1803
1804 void si_llvm_load_input_fs(
1805 struct si_shader_context *ctx,
1806 unsigned input_index,
1807 LLVMValueRef out[4])
1808 {
1809 struct lp_build_context *base = &ctx->bld_base.base;
1810 struct si_shader *shader = ctx->shader;
1811 struct tgsi_shader_info *info = &shader->selector->info;
1812 LLVMValueRef main_fn = ctx->main_fn;
1813 LLVMValueRef interp_param = NULL;
1814 int interp_param_idx;
1815 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1816 unsigned semantic_index = info->input_semantic_index[input_index];
1817 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1818 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1819
1820 /* Get colors from input VGPRs (set by the prolog). */
1821 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1822 unsigned colors_read = shader->selector->info.colors_read;
1823 unsigned mask = colors_read >> (semantic_index * 4);
1824 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1825 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1826
1827 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1828 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1829 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1830 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1831 return;
1832 }
1833
1834 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1835 if (interp_param_idx == -1)
1836 return;
1837 else if (interp_param_idx) {
1838 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1839 }
1840
1841 interp_fs_input(ctx, input_index, semantic_name,
1842 semantic_index, 0, /* this param is unused */
1843 shader->selector->info.colors_read, interp_param,
1844 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1845 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1846 &out[0]);
1847 }
1848
1849 static void declare_input_fs(
1850 struct si_shader_context *ctx,
1851 unsigned input_index,
1852 const struct tgsi_full_declaration *decl,
1853 LLVMValueRef out[4])
1854 {
1855 si_llvm_load_input_fs(ctx, input_index, out);
1856 }
1857
1858 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1859 {
1860 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1861 }
1862
1863
1864 /**
1865 * Load a dword from a constant buffer.
1866 */
1867 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1868 LLVMValueRef resource,
1869 LLVMValueRef offset)
1870 {
1871 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1872 0, 0, 0, true, true);
1873 }
1874
1875 static LLVMValueRef load_sample_position(struct si_shader_context *ctx, LLVMValueRef sample_id)
1876 {
1877 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1878 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1879 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1880 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1881
1882 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1883 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1884 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1885
1886 LLVMValueRef pos[4] = {
1887 buffer_load_const(ctx, resource, offset0),
1888 buffer_load_const(ctx, resource, offset1),
1889 LLVMConstReal(ctx->f32, 0),
1890 LLVMConstReal(ctx->f32, 0)
1891 };
1892
1893 return lp_build_gather_values(&ctx->gallivm, pos, 4);
1894 }
1895
1896 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi,
1897 LLVMTypeRef type,
1898 unsigned num_components)
1899 {
1900 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1901 struct lp_build_context *bld = &ctx->bld_base.base;
1902
1903 LLVMValueRef coord[4] = {
1904 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1905 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1906 ctx->ac.f32_0,
1907 ctx->ac.f32_0
1908 };
1909
1910 /* For triangles, the vector should be (u, v, 1-u-v). */
1911 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1912 PIPE_PRIM_TRIANGLES)
1913 coord[2] = lp_build_sub(bld, ctx->ac.f32_1,
1914 lp_build_add(bld, coord[0], coord[1]));
1915
1916 return lp_build_gather_values(&ctx->gallivm, coord, 4);
1917 }
1918
1919 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
1920 unsigned semantic_name)
1921 {
1922 LLVMValueRef buffer, base, addr;
1923
1924 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
1925
1926 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1927
1928 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1929 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1930 LLVMConstInt(ctx->i32, param, 0));
1931
1932 return buffer_load(&ctx->bld_base, ctx->f32,
1933 ~0, buffer, base, addr, true);
1934
1935 }
1936
1937 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
1938 unsigned varying_id)
1939 {
1940 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1941 unsigned semantic_name;
1942
1943 switch (varying_id) {
1944 case VARYING_SLOT_TESS_LEVEL_INNER:
1945 semantic_name = TGSI_SEMANTIC_TESSINNER;
1946 break;
1947 case VARYING_SLOT_TESS_LEVEL_OUTER:
1948 semantic_name = TGSI_SEMANTIC_TESSOUTER;
1949 break;
1950 default:
1951 unreachable("unknown tess level");
1952 }
1953
1954 return load_tess_level(ctx, semantic_name);
1955
1956 }
1957
1958 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
1959 {
1960 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1961 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1962 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6);
1963 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1964 return get_num_tcs_out_vertices(ctx);
1965 else
1966 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1967 }
1968
1969 void si_load_system_value(struct si_shader_context *ctx,
1970 unsigned index,
1971 const struct tgsi_full_declaration *decl)
1972 {
1973 LLVMValueRef value = 0;
1974
1975 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
1976
1977 switch (decl->Semantic.Name) {
1978 case TGSI_SEMANTIC_INSTANCEID:
1979 value = ctx->abi.instance_id;
1980 break;
1981
1982 case TGSI_SEMANTIC_VERTEXID:
1983 value = LLVMBuildAdd(ctx->ac.builder,
1984 ctx->abi.vertex_id,
1985 ctx->abi.base_vertex, "");
1986 break;
1987
1988 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1989 /* Unused. Clarify the meaning in indexed vs. non-indexed
1990 * draws if this is ever used again. */
1991 assert(false);
1992 break;
1993
1994 case TGSI_SEMANTIC_BASEVERTEX:
1995 {
1996 /* For non-indexed draws, the base vertex set by the driver
1997 * (for direct draws) or the CP (for indirect draws) is the
1998 * first vertex ID, but GLSL expects 0 to be returned.
1999 */
2000 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
2001 LLVMValueRef indexed;
2002
2003 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
2004 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
2005
2006 value = LLVMBuildSelect(ctx->ac.builder, indexed,
2007 ctx->abi.base_vertex, ctx->i32_0, "");
2008 break;
2009 }
2010
2011 case TGSI_SEMANTIC_BASEINSTANCE:
2012 value = ctx->abi.start_instance;
2013 break;
2014
2015 case TGSI_SEMANTIC_DRAWID:
2016 value = ctx->abi.draw_id;
2017 break;
2018
2019 case TGSI_SEMANTIC_INVOCATIONID:
2020 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2021 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2022 else if (ctx->type == PIPE_SHADER_GEOMETRY)
2023 value = ctx->abi.gs_invocation_id;
2024 else
2025 assert(!"INVOCATIONID not implemented");
2026 break;
2027
2028 case TGSI_SEMANTIC_POSITION:
2029 {
2030 LLVMValueRef pos[4] = {
2031 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2032 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2033 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2034 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
2035 LLVMGetParam(ctx->main_fn,
2036 SI_PARAM_POS_W_FLOAT)),
2037 };
2038 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
2039 break;
2040 }
2041
2042 case TGSI_SEMANTIC_FACE:
2043 value = ctx->abi.front_face;
2044 break;
2045
2046 case TGSI_SEMANTIC_SAMPLEID:
2047 value = get_sample_id(ctx);
2048 break;
2049
2050 case TGSI_SEMANTIC_SAMPLEPOS: {
2051 LLVMValueRef pos[4] = {
2052 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2053 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2054 LLVMConstReal(ctx->f32, 0),
2055 LLVMConstReal(ctx->f32, 0)
2056 };
2057 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
2058 TGSI_OPCODE_FRC, pos[0]);
2059 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
2060 TGSI_OPCODE_FRC, pos[1]);
2061 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
2062 break;
2063 }
2064
2065 case TGSI_SEMANTIC_SAMPLEMASK:
2066 /* This can only occur with the OpenGL Core profile, which
2067 * doesn't support smoothing.
2068 */
2069 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2070 break;
2071
2072 case TGSI_SEMANTIC_TESSCOORD:
2073 value = si_load_tess_coord(&ctx->abi, NULL, 4);
2074 break;
2075
2076 case TGSI_SEMANTIC_VERTICESIN:
2077 value = si_load_patch_vertices_in(&ctx->abi);
2078 break;
2079
2080 case TGSI_SEMANTIC_TESSINNER:
2081 case TGSI_SEMANTIC_TESSOUTER:
2082 value = load_tess_level(ctx, decl->Semantic.Name);
2083 break;
2084
2085 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
2086 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
2087 {
2088 LLVMValueRef buf, slot, val[4];
2089 int i, offset;
2090
2091 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
2092 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2093 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
2094 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
2095
2096 for (i = 0; i < 4; i++)
2097 val[i] = buffer_load_const(ctx, buf,
2098 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
2099 value = lp_build_gather_values(&ctx->gallivm, val, 4);
2100 break;
2101 }
2102
2103 case TGSI_SEMANTIC_PRIMID:
2104 value = get_primitive_id(ctx, 0);
2105 break;
2106
2107 case TGSI_SEMANTIC_GRID_SIZE:
2108 value = LLVMGetParam(ctx->main_fn, ctx->param_grid_size);
2109 break;
2110
2111 case TGSI_SEMANTIC_BLOCK_SIZE:
2112 {
2113 LLVMValueRef values[3];
2114 unsigned i;
2115 unsigned *properties = ctx->shader->selector->info.properties;
2116
2117 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
2118 unsigned sizes[3] = {
2119 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
2120 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
2121 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
2122 };
2123
2124 for (i = 0; i < 3; ++i)
2125 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
2126
2127 value = lp_build_gather_values(&ctx->gallivm, values, 3);
2128 } else {
2129 value = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
2130 }
2131 break;
2132 }
2133
2134 case TGSI_SEMANTIC_BLOCK_ID:
2135 {
2136 LLVMValueRef values[3];
2137
2138 for (int i = 0; i < 3; i++) {
2139 values[i] = ctx->i32_0;
2140 if (ctx->param_block_id[i] >= 0) {
2141 values[i] = LLVMGetParam(ctx->main_fn,
2142 ctx->param_block_id[i]);
2143 }
2144 }
2145 value = lp_build_gather_values(&ctx->gallivm, values, 3);
2146 break;
2147 }
2148
2149 case TGSI_SEMANTIC_THREAD_ID:
2150 value = LLVMGetParam(ctx->main_fn, ctx->param_thread_id);
2151 break;
2152
2153 case TGSI_SEMANTIC_HELPER_INVOCATION:
2154 value = lp_build_intrinsic(ctx->ac.builder,
2155 "llvm.amdgcn.ps.live",
2156 ctx->i1, NULL, 0,
2157 LP_FUNC_ATTR_READNONE);
2158 value = LLVMBuildNot(ctx->ac.builder, value, "");
2159 value = LLVMBuildSExt(ctx->ac.builder, value, ctx->i32, "");
2160 break;
2161
2162 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2163 value = LLVMConstInt(ctx->i32, 64, 0);
2164 break;
2165
2166 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2167 value = ac_get_thread_id(&ctx->ac);
2168 break;
2169
2170 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2171 {
2172 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2173 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2174 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
2175 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2176 break;
2177 }
2178
2179 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2180 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2181 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2182 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2183 {
2184 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2185 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2186 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2187 /* All bits set except LSB */
2188 value = LLVMConstInt(ctx->i64, -2, 0);
2189 } else {
2190 /* All bits set */
2191 value = LLVMConstInt(ctx->i64, -1, 0);
2192 }
2193 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2194 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2195 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2196 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2197 value = LLVMBuildNot(ctx->ac.builder, value, "");
2198 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2199 break;
2200 }
2201
2202 default:
2203 assert(!"unknown system value");
2204 return;
2205 }
2206
2207 ctx->system_values[index] = value;
2208 }
2209
2210 void si_declare_compute_memory(struct si_shader_context *ctx,
2211 const struct tgsi_full_declaration *decl)
2212 {
2213 struct si_shader_selector *sel = ctx->shader->selector;
2214
2215 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
2216 LLVMValueRef var;
2217
2218 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2219 assert(decl->Range.First == decl->Range.Last);
2220 assert(!ctx->ac.lds);
2221
2222 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2223 LLVMArrayType(ctx->i8, sel->local_size),
2224 "compute_lds",
2225 LOCAL_ADDR_SPACE);
2226 LLVMSetAlignment(var, 4);
2227
2228 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2229 }
2230
2231 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2232 {
2233 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2234 ctx->param_const_and_shader_buffers);
2235
2236 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2237 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2238 }
2239
2240 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2241 {
2242 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2243 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2244
2245 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2246 index = LLVMBuildAdd(ctx->ac.builder, index,
2247 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2248
2249 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2250 }
2251
2252 static LLVMValueRef
2253 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2254 {
2255 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2256 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2257 ctx->param_const_and_shader_buffers);
2258
2259 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2260 index = LLVMBuildSub(ctx->ac.builder,
2261 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2262 index, "");
2263
2264 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2265 }
2266
2267 static LLVMValueRef fetch_constant(
2268 struct lp_build_tgsi_context *bld_base,
2269 const struct tgsi_full_src_register *reg,
2270 enum tgsi_opcode_type type,
2271 unsigned swizzle)
2272 {
2273 struct si_shader_context *ctx = si_shader_context(bld_base);
2274 struct si_shader_selector *sel = ctx->shader->selector;
2275 const struct tgsi_ind_register *ireg = &reg->Indirect;
2276 unsigned buf, idx;
2277
2278 LLVMValueRef addr, bufp;
2279
2280 if (swizzle == LP_CHAN_ALL) {
2281 unsigned chan;
2282 LLVMValueRef values[4];
2283 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2284 values[chan] = fetch_constant(bld_base, reg, type, chan);
2285
2286 return lp_build_gather_values(&ctx->gallivm, values, 4);
2287 }
2288
2289 /* Split 64-bit loads. */
2290 if (tgsi_type_is_64bit(type)) {
2291 LLVMValueRef lo, hi;
2292
2293 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2294 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle + 1);
2295 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2296 lo, hi);
2297 }
2298
2299 idx = reg->Register.Index * 4 + swizzle;
2300 if (reg->Register.Indirect) {
2301 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2302 } else {
2303 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2304 }
2305
2306 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2307 if (sel->info.const_buffers_declared == 1 &&
2308 sel->info.shader_buffers_declared == 0) {
2309 LLVMValueRef ptr =
2310 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2311
2312 /* This enables use of s_load_dword and flat_load_dword for const buffer 0
2313 * loads, and up to x4 load opcode merging. However, it leads to horrible
2314 * code reducing SIMD wave occupancy from 8 to 2 in many cases.
2315 *
2316 * Using s_buffer_load_dword (x1) seems to be the best option right now.
2317 *
2318 * LLVM 5.0 on SI doesn't insert a required s_nop between SALU setting
2319 * a descriptor and s_buffer_load_dword using it, so we can't expand
2320 * the pointer into a full descriptor like below. We have to use
2321 * s_load_dword instead. The only case when LLVM 5.0 would select
2322 * s_buffer_load_dword (that we have to prevent) is when we use use
2323 * a literal offset where we don't need bounds checking.
2324 */
2325 if (ctx->screen->info.chip_class == SI &&
2326 HAVE_LLVM < 0x0600 &&
2327 !reg->Register.Indirect) {
2328 addr = LLVMBuildLShr(ctx->ac.builder, addr, LLVMConstInt(ctx->i32, 2, 0), "");
2329 LLVMValueRef result = ac_build_load_invariant(&ctx->ac, ptr, addr);
2330 return bitcast(bld_base, type, result);
2331 }
2332
2333 /* Do the bounds checking with a descriptor, because
2334 * doing computation and manual bounds checking of 64-bit
2335 * addresses generates horrible VALU code with very high
2336 * VGPR usage and very low SIMD occupancy.
2337 */
2338 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->i64, "");
2339 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ctx->v2i32, "");
2340
2341 LLVMValueRef desc_elems[] = {
2342 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_0, ""),
2343 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_1, ""),
2344 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2345 LLVMConstInt(ctx->i32,
2346 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2347 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2348 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2349 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2350 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2351 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2352 };
2353 LLVMValueRef desc = ac_build_gather_values(&ctx->ac, desc_elems, 4);
2354 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2355 return bitcast(bld_base, type, result);
2356 }
2357
2358 assert(reg->Register.Dimension);
2359 buf = reg->Dimension.Index;
2360
2361 if (reg->Dimension.Indirect) {
2362 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2363 LLVMValueRef index;
2364 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2365 reg->Dimension.Index,
2366 ctx->num_const_buffers);
2367 index = LLVMBuildAdd(ctx->ac.builder, index,
2368 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2369 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2370 } else
2371 bufp = load_const_buffer_desc(ctx, buf);
2372
2373 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2374 }
2375
2376 /* Upper 16 bits must be zero. */
2377 static LLVMValueRef si_llvm_pack_two_int16(struct si_shader_context *ctx,
2378 LLVMValueRef val[2])
2379 {
2380 return LLVMBuildOr(ctx->ac.builder, val[0],
2381 LLVMBuildShl(ctx->ac.builder, val[1],
2382 LLVMConstInt(ctx->i32, 16, 0),
2383 ""), "");
2384 }
2385
2386 /* Upper 16 bits are ignored and will be dropped. */
2387 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct si_shader_context *ctx,
2388 LLVMValueRef val[2])
2389 {
2390 LLVMValueRef v[2] = {
2391 LLVMBuildAnd(ctx->ac.builder, val[0],
2392 LLVMConstInt(ctx->i32, 0xffff, 0), ""),
2393 val[1],
2394 };
2395 return si_llvm_pack_two_int16(ctx, v);
2396 }
2397
2398 /* Initialize arguments for the shader export intrinsic */
2399 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2400 LLVMValueRef *values,
2401 unsigned target,
2402 struct ac_export_args *args)
2403 {
2404 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2405 LLVMBuilderRef builder = ctx->ac.builder;
2406 LLVMValueRef val[4];
2407 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2408 unsigned chan;
2409 bool is_int8, is_int10;
2410
2411 /* Default is 0xf. Adjusted below depending on the format. */
2412 args->enabled_channels = 0xf; /* writemask */
2413
2414 /* Specify whether the EXEC mask represents the valid mask */
2415 args->valid_mask = 0;
2416
2417 /* Specify whether this is the last export */
2418 args->done = 0;
2419
2420 /* Specify the target we are exporting */
2421 args->target = target;
2422
2423 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2424 const struct si_shader_key *key = &ctx->shader->key;
2425 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2426 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2427
2428 assert(cbuf >= 0 && cbuf < 8);
2429 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2430 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2431 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2432 }
2433
2434 args->compr = false;
2435 args->out[0] = f32undef;
2436 args->out[1] = f32undef;
2437 args->out[2] = f32undef;
2438 args->out[3] = f32undef;
2439
2440 switch (spi_shader_col_format) {
2441 case V_028714_SPI_SHADER_ZERO:
2442 args->enabled_channels = 0; /* writemask */
2443 args->target = V_008DFC_SQ_EXP_NULL;
2444 break;
2445
2446 case V_028714_SPI_SHADER_32_R:
2447 args->enabled_channels = 1; /* writemask */
2448 args->out[0] = values[0];
2449 break;
2450
2451 case V_028714_SPI_SHADER_32_GR:
2452 args->enabled_channels = 0x3; /* writemask */
2453 args->out[0] = values[0];
2454 args->out[1] = values[1];
2455 break;
2456
2457 case V_028714_SPI_SHADER_32_AR:
2458 args->enabled_channels = 0x9; /* writemask */
2459 args->out[0] = values[0];
2460 args->out[3] = values[3];
2461 break;
2462
2463 case V_028714_SPI_SHADER_FP16_ABGR:
2464 args->compr = 1; /* COMPR flag */
2465
2466 for (chan = 0; chan < 2; chan++) {
2467 LLVMValueRef pack_args[2] = {
2468 values[2 * chan],
2469 values[2 * chan + 1]
2470 };
2471 LLVMValueRef packed;
2472
2473 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
2474 args->out[chan] = ac_to_float(&ctx->ac, packed);
2475 }
2476 break;
2477
2478 case V_028714_SPI_SHADER_UNORM16_ABGR:
2479 for (chan = 0; chan < 4; chan++) {
2480 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
2481 val[chan] = LLVMBuildFMul(builder, val[chan],
2482 LLVMConstReal(ctx->f32, 65535), "");
2483 val[chan] = LLVMBuildFAdd(builder, val[chan],
2484 LLVMConstReal(ctx->f32, 0.5), "");
2485 val[chan] = LLVMBuildFPToUI(builder, val[chan],
2486 ctx->i32, "");
2487 }
2488
2489 args->compr = 1; /* COMPR flag */
2490 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val));
2491 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val+2));
2492 break;
2493
2494 case V_028714_SPI_SHADER_SNORM16_ABGR:
2495 for (chan = 0; chan < 4; chan++) {
2496 /* Clamp between [-1, 1]. */
2497 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base, TGSI_OPCODE_MIN,
2498 values[chan],
2499 LLVMConstReal(ctx->f32, 1));
2500 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base, TGSI_OPCODE_MAX,
2501 val[chan],
2502 LLVMConstReal(ctx->f32, -1));
2503 /* Convert to a signed integer in [-32767, 32767]. */
2504 val[chan] = LLVMBuildFMul(builder, val[chan],
2505 LLVMConstReal(ctx->f32, 32767), "");
2506 /* If positive, add 0.5, else add -0.5. */
2507 val[chan] = LLVMBuildFAdd(builder, val[chan],
2508 LLVMBuildSelect(builder,
2509 LLVMBuildFCmp(builder, LLVMRealOGE,
2510 val[chan], ctx->ac.f32_0, ""),
2511 LLVMConstReal(ctx->f32, 0.5),
2512 LLVMConstReal(ctx->f32, -0.5), ""), "");
2513 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2514 }
2515
2516 args->compr = 1; /* COMPR flag */
2517 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val));
2518 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val+2));
2519 break;
2520
2521 case V_028714_SPI_SHADER_UINT16_ABGR: {
2522 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2523 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
2524 LLVMValueRef max_alpha =
2525 !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
2526
2527 /* Clamp. */
2528 for (chan = 0; chan < 4; chan++) {
2529 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
2530 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base, TGSI_OPCODE_UMIN,
2531 val[chan],
2532 chan == 3 ? max_alpha : max_rgb);
2533 }
2534
2535 args->compr = 1; /* COMPR flag */
2536 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val));
2537 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val+2));
2538 break;
2539 }
2540
2541 case V_028714_SPI_SHADER_SINT16_ABGR: {
2542 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2543 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
2544 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
2545 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
2546 LLVMValueRef max_alpha =
2547 !is_int10 ? max_rgb : ctx->i32_1;
2548 LLVMValueRef min_alpha =
2549 !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
2550
2551 /* Clamp. */
2552 for (chan = 0; chan < 4; chan++) {
2553 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
2554 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base,
2555 TGSI_OPCODE_IMIN,
2556 val[chan], chan == 3 ? max_alpha : max_rgb);
2557 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base,
2558 TGSI_OPCODE_IMAX,
2559 val[chan], chan == 3 ? min_alpha : min_rgb);
2560 }
2561
2562 args->compr = 1; /* COMPR flag */
2563 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val));
2564 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val+2));
2565 break;
2566 }
2567
2568 case V_028714_SPI_SHADER_32_ABGR:
2569 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2570 break;
2571 }
2572 }
2573
2574 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2575 LLVMValueRef alpha)
2576 {
2577 struct si_shader_context *ctx = si_shader_context(bld_base);
2578
2579 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2580 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2581 [PIPE_FUNC_LESS] = LLVMRealOLT,
2582 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2583 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2584 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2585 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2586 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2587 };
2588 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2589 assert(cond);
2590
2591 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2592 SI_PARAM_ALPHA_REF);
2593 LLVMValueRef alpha_pass =
2594 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2595 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2596 } else {
2597 ac_build_kill_if_false(&ctx->ac, LLVMConstInt(ctx->i1, 0, 0));
2598 }
2599 }
2600
2601 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2602 LLVMValueRef alpha,
2603 unsigned samplemask_param)
2604 {
2605 struct si_shader_context *ctx = si_shader_context(bld_base);
2606 LLVMValueRef coverage;
2607
2608 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2609 coverage = LLVMGetParam(ctx->main_fn,
2610 samplemask_param);
2611 coverage = ac_to_integer(&ctx->ac, coverage);
2612
2613 coverage = lp_build_intrinsic(ctx->ac.builder, "llvm.ctpop.i32",
2614 ctx->i32,
2615 &coverage, 1, LP_FUNC_ATTR_READNONE);
2616
2617 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2618 ctx->f32, "");
2619
2620 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2621 LLVMConstReal(ctx->f32,
2622 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2623
2624 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2625 }
2626
2627 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2628 struct ac_export_args *pos, LLVMValueRef *out_elts)
2629 {
2630 unsigned reg_index;
2631 unsigned chan;
2632 unsigned const_chan;
2633 LLVMValueRef base_elt;
2634 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2635 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2636 SI_VS_CONST_CLIP_PLANES, 0);
2637 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2638
2639 for (reg_index = 0; reg_index < 2; reg_index ++) {
2640 struct ac_export_args *args = &pos[2 + reg_index];
2641
2642 args->out[0] =
2643 args->out[1] =
2644 args->out[2] =
2645 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2646
2647 /* Compute dot products of position and user clip plane vectors */
2648 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2649 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2650 LLVMValueRef addr =
2651 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2652 const_chan) * 4, 0);
2653 base_elt = buffer_load_const(ctx, const_resource,
2654 addr);
2655 args->out[chan] =
2656 lp_build_add(&ctx->bld_base.base, args->out[chan],
2657 lp_build_mul(&ctx->bld_base.base, base_elt,
2658 out_elts[const_chan]));
2659 }
2660 }
2661
2662 args->enabled_channels = 0xf;
2663 args->valid_mask = 0;
2664 args->done = 0;
2665 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2666 args->compr = 0;
2667 }
2668 }
2669
2670 static void si_dump_streamout(struct pipe_stream_output_info *so)
2671 {
2672 unsigned i;
2673
2674 if (so->num_outputs)
2675 fprintf(stderr, "STREAMOUT\n");
2676
2677 for (i = 0; i < so->num_outputs; i++) {
2678 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2679 so->output[i].start_component;
2680 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2681 i, so->output[i].output_buffer,
2682 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2683 so->output[i].register_index,
2684 mask & 1 ? "x" : "",
2685 mask & 2 ? "y" : "",
2686 mask & 4 ? "z" : "",
2687 mask & 8 ? "w" : "");
2688 }
2689 }
2690
2691 static void emit_streamout_output(struct si_shader_context *ctx,
2692 LLVMValueRef const *so_buffers,
2693 LLVMValueRef const *so_write_offsets,
2694 struct pipe_stream_output *stream_out,
2695 struct si_shader_output_values *shader_out)
2696 {
2697 unsigned buf_idx = stream_out->output_buffer;
2698 unsigned start = stream_out->start_component;
2699 unsigned num_comps = stream_out->num_components;
2700 LLVMValueRef out[4];
2701
2702 assert(num_comps && num_comps <= 4);
2703 if (!num_comps || num_comps > 4)
2704 return;
2705
2706 /* Load the output as int. */
2707 for (int j = 0; j < num_comps; j++) {
2708 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2709
2710 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2711 }
2712
2713 /* Pack the output. */
2714 LLVMValueRef vdata = NULL;
2715
2716 switch (num_comps) {
2717 case 1: /* as i32 */
2718 vdata = out[0];
2719 break;
2720 case 2: /* as v2i32 */
2721 case 3: /* as v4i32 (aligned to 4) */
2722 case 4: /* as v4i32 */
2723 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2724 for (int j = 0; j < num_comps; j++) {
2725 vdata = LLVMBuildInsertElement(ctx->ac.builder, vdata, out[j],
2726 LLVMConstInt(ctx->i32, j, 0), "");
2727 }
2728 break;
2729 }
2730
2731 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2732 vdata, num_comps,
2733 so_write_offsets[buf_idx],
2734 ctx->i32_0,
2735 stream_out->dst_offset * 4, 1, 1, true, false);
2736 }
2737
2738 /**
2739 * Write streamout data to buffers for vertex stream @p stream (different
2740 * vertex streams can occur for GS copy shaders).
2741 */
2742 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2743 struct si_shader_output_values *outputs,
2744 unsigned noutput, unsigned stream)
2745 {
2746 struct si_shader_selector *sel = ctx->shader->selector;
2747 struct pipe_stream_output_info *so = &sel->so;
2748 LLVMBuilderRef builder = ctx->ac.builder;
2749 int i;
2750 struct lp_build_if_state if_ctx;
2751
2752 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2753 LLVMValueRef so_vtx_count =
2754 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2755
2756 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2757
2758 /* can_emit = tid < so_vtx_count; */
2759 LLVMValueRef can_emit =
2760 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2761
2762 /* Emit the streamout code conditionally. This actually avoids
2763 * out-of-bounds buffer access. The hw tells us via the SGPR
2764 * (so_vtx_count) which threads are allowed to emit streamout data. */
2765 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2766 {
2767 /* The buffer offset is computed as follows:
2768 * ByteOffset = streamout_offset[buffer_id]*4 +
2769 * (streamout_write_index + thread_id)*stride[buffer_id] +
2770 * attrib_offset
2771 */
2772
2773 LLVMValueRef so_write_index =
2774 LLVMGetParam(ctx->main_fn,
2775 ctx->param_streamout_write_index);
2776
2777 /* Compute (streamout_write_index + thread_id). */
2778 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2779
2780 /* Load the descriptor and compute the write offset for each
2781 * enabled buffer. */
2782 LLVMValueRef so_write_offset[4] = {};
2783 LLVMValueRef so_buffers[4];
2784 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2785 ctx->param_rw_buffers);
2786
2787 for (i = 0; i < 4; i++) {
2788 if (!so->stride[i])
2789 continue;
2790
2791 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2792 SI_VS_STREAMOUT_BUF0 + i, 0);
2793
2794 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2795
2796 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2797 ctx->param_streamout_offset[i]);
2798 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2799
2800 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2801 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2802 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2803 }
2804
2805 /* Write streamout data. */
2806 for (i = 0; i < so->num_outputs; i++) {
2807 unsigned reg = so->output[i].register_index;
2808
2809 if (reg >= noutput)
2810 continue;
2811
2812 if (stream != so->output[i].stream)
2813 continue;
2814
2815 emit_streamout_output(ctx, so_buffers, so_write_offset,
2816 &so->output[i], &outputs[reg]);
2817 }
2818 }
2819 lp_build_endif(&if_ctx);
2820 }
2821
2822 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2823 LLVMValueRef *values)
2824 {
2825 struct ac_export_args args;
2826
2827 si_llvm_init_export_args(ctx, values,
2828 V_008DFC_SQ_EXP_PARAM + index, &args);
2829 ac_build_export(&ctx->ac, &args);
2830 }
2831
2832 static void si_build_param_exports(struct si_shader_context *ctx,
2833 struct si_shader_output_values *outputs,
2834 unsigned noutput)
2835 {
2836 struct si_shader *shader = ctx->shader;
2837 unsigned param_count = 0;
2838
2839 for (unsigned i = 0; i < noutput; i++) {
2840 unsigned semantic_name = outputs[i].semantic_name;
2841 unsigned semantic_index = outputs[i].semantic_index;
2842
2843 if (outputs[i].vertex_stream[0] != 0 &&
2844 outputs[i].vertex_stream[1] != 0 &&
2845 outputs[i].vertex_stream[2] != 0 &&
2846 outputs[i].vertex_stream[3] != 0)
2847 continue;
2848
2849 switch (semantic_name) {
2850 case TGSI_SEMANTIC_LAYER:
2851 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2852 case TGSI_SEMANTIC_CLIPDIST:
2853 case TGSI_SEMANTIC_COLOR:
2854 case TGSI_SEMANTIC_BCOLOR:
2855 case TGSI_SEMANTIC_PRIMID:
2856 case TGSI_SEMANTIC_FOG:
2857 case TGSI_SEMANTIC_TEXCOORD:
2858 case TGSI_SEMANTIC_GENERIC:
2859 break;
2860 default:
2861 continue;
2862 }
2863
2864 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2865 semantic_index < SI_MAX_IO_GENERIC) &&
2866 shader->key.opt.kill_outputs &
2867 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2868 continue;
2869
2870 si_export_param(ctx, param_count, outputs[i].values);
2871
2872 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2873 shader->info.vs_output_param_offset[i] = param_count++;
2874 }
2875
2876 shader->info.nr_param_exports = param_count;
2877 }
2878
2879 /* Generate export instructions for hardware VS shader stage */
2880 static void si_llvm_export_vs(struct si_shader_context *ctx,
2881 struct si_shader_output_values *outputs,
2882 unsigned noutput)
2883 {
2884 struct si_shader *shader = ctx->shader;
2885 struct ac_export_args pos_args[4] = {};
2886 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2887 unsigned pos_idx;
2888 int i;
2889
2890 /* Build position exports. */
2891 for (i = 0; i < noutput; i++) {
2892 switch (outputs[i].semantic_name) {
2893 case TGSI_SEMANTIC_POSITION:
2894 si_llvm_init_export_args(ctx, outputs[i].values,
2895 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2896 break;
2897 case TGSI_SEMANTIC_PSIZE:
2898 psize_value = outputs[i].values[0];
2899 break;
2900 case TGSI_SEMANTIC_LAYER:
2901 layer_value = outputs[i].values[0];
2902 break;
2903 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2904 viewport_index_value = outputs[i].values[0];
2905 break;
2906 case TGSI_SEMANTIC_EDGEFLAG:
2907 edgeflag_value = outputs[i].values[0];
2908 break;
2909 case TGSI_SEMANTIC_CLIPDIST:
2910 if (!shader->key.opt.clip_disable) {
2911 unsigned index = 2 + outputs[i].semantic_index;
2912 si_llvm_init_export_args(ctx, outputs[i].values,
2913 V_008DFC_SQ_EXP_POS + index,
2914 &pos_args[index]);
2915 }
2916 break;
2917 case TGSI_SEMANTIC_CLIPVERTEX:
2918 if (!shader->key.opt.clip_disable) {
2919 si_llvm_emit_clipvertex(ctx, pos_args,
2920 outputs[i].values);
2921 }
2922 break;
2923 }
2924 }
2925
2926 /* We need to add the position output manually if it's missing. */
2927 if (!pos_args[0].out[0]) {
2928 pos_args[0].enabled_channels = 0xf; /* writemask */
2929 pos_args[0].valid_mask = 0; /* EXEC mask */
2930 pos_args[0].done = 0; /* last export? */
2931 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2932 pos_args[0].compr = 0; /* COMPR flag */
2933 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2934 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2935 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2936 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2937 }
2938
2939 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2940 if (shader->selector->info.writes_psize ||
2941 shader->selector->info.writes_edgeflag ||
2942 shader->selector->info.writes_viewport_index ||
2943 shader->selector->info.writes_layer) {
2944 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2945 (shader->selector->info.writes_edgeflag << 1) |
2946 (shader->selector->info.writes_layer << 2);
2947
2948 pos_args[1].valid_mask = 0; /* EXEC mask */
2949 pos_args[1].done = 0; /* last export? */
2950 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2951 pos_args[1].compr = 0; /* COMPR flag */
2952 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2953 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2954 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2955 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2956
2957 if (shader->selector->info.writes_psize)
2958 pos_args[1].out[0] = psize_value;
2959
2960 if (shader->selector->info.writes_edgeflag) {
2961 /* The output is a float, but the hw expects an integer
2962 * with the first bit containing the edge flag. */
2963 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2964 edgeflag_value,
2965 ctx->i32, "");
2966 edgeflag_value = ac_build_umin(&ctx->ac,
2967 edgeflag_value,
2968 ctx->i32_1);
2969
2970 /* The LLVM intrinsic expects a float. */
2971 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2972 }
2973
2974 if (ctx->screen->info.chip_class >= GFX9) {
2975 /* GFX9 has the layer in out.z[10:0] and the viewport
2976 * index in out.z[19:16].
2977 */
2978 if (shader->selector->info.writes_layer)
2979 pos_args[1].out[2] = layer_value;
2980
2981 if (shader->selector->info.writes_viewport_index) {
2982 LLVMValueRef v = viewport_index_value;
2983
2984 v = ac_to_integer(&ctx->ac, v);
2985 v = LLVMBuildShl(ctx->ac.builder, v,
2986 LLVMConstInt(ctx->i32, 16, 0), "");
2987 v = LLVMBuildOr(ctx->ac.builder, v,
2988 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2989 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2990 pos_args[1].enabled_channels |= 1 << 2;
2991 }
2992 } else {
2993 if (shader->selector->info.writes_layer)
2994 pos_args[1].out[2] = layer_value;
2995
2996 if (shader->selector->info.writes_viewport_index) {
2997 pos_args[1].out[3] = viewport_index_value;
2998 pos_args[1].enabled_channels |= 1 << 3;
2999 }
3000 }
3001 }
3002
3003 for (i = 0; i < 4; i++)
3004 if (pos_args[i].out[0])
3005 shader->info.nr_pos_exports++;
3006
3007 pos_idx = 0;
3008 for (i = 0; i < 4; i++) {
3009 if (!pos_args[i].out[0])
3010 continue;
3011
3012 /* Specify the target we are exporting */
3013 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
3014
3015 if (pos_idx == shader->info.nr_pos_exports)
3016 /* Specify that this is the last export */
3017 pos_args[i].done = 1;
3018
3019 ac_build_export(&ctx->ac, &pos_args[i]);
3020 }
3021
3022 /* Build parameter exports. */
3023 si_build_param_exports(ctx, outputs, noutput);
3024 }
3025
3026 /**
3027 * Forward all outputs from the vertex shader to the TES. This is only used
3028 * for the fixed function TCS.
3029 */
3030 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
3031 {
3032 struct si_shader_context *ctx = si_shader_context(bld_base);
3033 LLVMValueRef invocation_id, buffer, buffer_offset;
3034 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
3035 uint64_t inputs;
3036
3037 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3038 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
3039 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3040
3041 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
3042 lds_vertex_offset = LLVMBuildMul(ctx->ac.builder, invocation_id,
3043 lds_vertex_stride, "");
3044 lds_base = get_tcs_in_current_patch_offset(ctx);
3045 lds_base = LLVMBuildAdd(ctx->ac.builder, lds_base, lds_vertex_offset, "");
3046
3047 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
3048 while (inputs) {
3049 unsigned i = u_bit_scan64(&inputs);
3050
3051 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
3052 LLVMConstInt(ctx->i32, 4 * i, 0),
3053 "");
3054
3055 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
3056 get_rel_patch_id(ctx),
3057 invocation_id,
3058 LLVMConstInt(ctx->i32, i, 0));
3059
3060 LLVMValueRef value = lds_load(bld_base, ctx->ac.i32, ~0,
3061 lds_ptr);
3062
3063 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
3064 buffer_offset, 0, 1, 0, true, false);
3065 }
3066 }
3067
3068 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
3069 LLVMValueRef rel_patch_id,
3070 LLVMValueRef invocation_id,
3071 LLVMValueRef tcs_out_current_patch_data_offset,
3072 LLVMValueRef invoc0_tf_outer[4],
3073 LLVMValueRef invoc0_tf_inner[2])
3074 {
3075 struct si_shader_context *ctx = si_shader_context(bld_base);
3076 struct si_shader *shader = ctx->shader;
3077 unsigned tess_inner_index, tess_outer_index;
3078 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
3079 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3080 unsigned stride, outer_comps, inner_comps, i, offset;
3081 struct lp_build_if_state if_ctx, inner_if_ctx;
3082
3083 /* Add a barrier before loading tess factors from LDS. */
3084 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
3085 si_llvm_emit_barrier(NULL, bld_base, NULL);
3086
3087 /* Do this only for invocation 0, because the tess levels are per-patch,
3088 * not per-vertex.
3089 *
3090 * This can't jump, because invocation 0 executes this. It should
3091 * at least mask out the loads and stores for other invocations.
3092 */
3093 lp_build_if(&if_ctx, &ctx->gallivm,
3094 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3095 invocation_id, ctx->i32_0, ""));
3096
3097 /* Determine the layout of one tess factor element in the buffer. */
3098 switch (shader->key.part.tcs.epilog.prim_mode) {
3099 case PIPE_PRIM_LINES:
3100 stride = 2; /* 2 dwords, 1 vec2 store */
3101 outer_comps = 2;
3102 inner_comps = 0;
3103 break;
3104 case PIPE_PRIM_TRIANGLES:
3105 stride = 4; /* 4 dwords, 1 vec4 store */
3106 outer_comps = 3;
3107 inner_comps = 1;
3108 break;
3109 case PIPE_PRIM_QUADS:
3110 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3111 outer_comps = 4;
3112 inner_comps = 2;
3113 break;
3114 default:
3115 assert(0);
3116 return;
3117 }
3118
3119 for (i = 0; i < 4; i++) {
3120 inner[i] = LLVMGetUndef(ctx->i32);
3121 outer[i] = LLVMGetUndef(ctx->i32);
3122 }
3123
3124 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3125 /* Tess factors are in VGPRs. */
3126 for (i = 0; i < outer_comps; i++)
3127 outer[i] = out[i] = invoc0_tf_outer[i];
3128 for (i = 0; i < inner_comps; i++)
3129 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3130 } else {
3131 /* Load tess_inner and tess_outer from LDS.
3132 * Any invocation can write them, so we can't get them from a temporary.
3133 */
3134 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3135 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3136
3137 lds_base = tcs_out_current_patch_data_offset;
3138 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3139 LLVMConstInt(ctx->i32,
3140 tess_inner_index * 4, 0), "");
3141 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3142 LLVMConstInt(ctx->i32,
3143 tess_outer_index * 4, 0), "");
3144
3145 for (i = 0; i < outer_comps; i++) {
3146 outer[i] = out[i] =
3147 lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3148 }
3149 for (i = 0; i < inner_comps; i++) {
3150 inner[i] = out[outer_comps+i] =
3151 lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3152 }
3153 }
3154
3155 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3156 /* For isolines, the hardware expects tess factors in the
3157 * reverse order from what GLSL / TGSI specify.
3158 */
3159 LLVMValueRef tmp = out[0];
3160 out[0] = out[1];
3161 out[1] = tmp;
3162 }
3163
3164 /* Convert the outputs to vectors for stores. */
3165 vec0 = lp_build_gather_values(&ctx->gallivm, out, MIN2(stride, 4));
3166 vec1 = NULL;
3167
3168 if (stride > 4)
3169 vec1 = lp_build_gather_values(&ctx->gallivm, out+4, stride - 4);
3170
3171 /* Get the buffer. */
3172 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_factor_addr_base64k);
3173
3174 /* Get the offset. */
3175 tf_base = LLVMGetParam(ctx->main_fn,
3176 ctx->param_tcs_factor_offset);
3177 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3178 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3179
3180 lp_build_if(&inner_if_ctx, &ctx->gallivm,
3181 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3182 rel_patch_id, ctx->i32_0, ""));
3183
3184 /* Store the dynamic HS control word. */
3185 offset = 0;
3186 if (ctx->screen->info.chip_class <= VI) {
3187 ac_build_buffer_store_dword(&ctx->ac, buffer,
3188 LLVMConstInt(ctx->i32, 0x80000000, 0),
3189 1, ctx->i32_0, tf_base,
3190 offset, 1, 0, true, false);
3191 offset += 4;
3192 }
3193
3194 lp_build_endif(&inner_if_ctx);
3195
3196 /* Store the tessellation factors. */
3197 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3198 MIN2(stride, 4), byteoffset, tf_base,
3199 offset, 1, 0, true, false);
3200 offset += 16;
3201 if (vec1)
3202 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3203 stride - 4, byteoffset, tf_base,
3204 offset, 1, 0, true, false);
3205
3206 /* Store the tess factors into the offchip buffer if TES reads them. */
3207 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3208 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3209 LLVMValueRef tf_inner_offset;
3210 unsigned param_outer, param_inner;
3211
3212 buf = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
3213 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3214
3215 param_outer = si_shader_io_get_unique_index_patch(
3216 TGSI_SEMANTIC_TESSOUTER, 0);
3217 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3218 LLVMConstInt(ctx->i32, param_outer, 0));
3219
3220 outer_vec = lp_build_gather_values(&ctx->gallivm, outer,
3221 util_next_power_of_two(outer_comps));
3222
3223 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3224 outer_comps, tf_outer_offset,
3225 base, 0, 1, 0, true, false);
3226 if (inner_comps) {
3227 param_inner = si_shader_io_get_unique_index_patch(
3228 TGSI_SEMANTIC_TESSINNER, 0);
3229 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3230 LLVMConstInt(ctx->i32, param_inner, 0));
3231
3232 inner_vec = inner_comps == 1 ? inner[0] :
3233 lp_build_gather_values(&ctx->gallivm, inner, inner_comps);
3234 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3235 inner_comps, tf_inner_offset,
3236 base, 0, 1, 0, true, false);
3237 }
3238 }
3239
3240 lp_build_endif(&if_ctx);
3241 }
3242
3243 static LLVMValueRef
3244 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3245 unsigned param, unsigned return_index)
3246 {
3247 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3248 LLVMGetParam(ctx->main_fn, param),
3249 return_index, "");
3250 }
3251
3252 static LLVMValueRef
3253 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3254 unsigned param, unsigned return_index)
3255 {
3256 LLVMBuilderRef builder = ctx->ac.builder;
3257 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3258
3259 return LLVMBuildInsertValue(builder, ret,
3260 ac_to_float(&ctx->ac, p),
3261 return_index, "");
3262 }
3263
3264 static LLVMValueRef
3265 si_insert_input_ptr_as_2xi32(struct si_shader_context *ctx, LLVMValueRef ret,
3266 unsigned param, unsigned return_index)
3267 {
3268 LLVMBuilderRef builder = ctx->ac.builder;
3269 LLVMValueRef ptr, lo, hi;
3270
3271 ptr = LLVMGetParam(ctx->main_fn, param);
3272 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
3273 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
3274 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
3275 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
3276 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
3277 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
3278 }
3279
3280 /* This only writes the tessellation factor levels. */
3281 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
3282 unsigned max_outputs,
3283 LLVMValueRef *addrs)
3284 {
3285 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3286 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
3287 LLVMBuilderRef builder = ctx->ac.builder;
3288 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3289
3290 si_copy_tcs_inputs(bld_base);
3291
3292 rel_patch_id = get_rel_patch_id(ctx);
3293 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3294 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3295
3296 if (ctx->screen->info.chip_class >= GFX9) {
3297 LLVMBasicBlockRef blocks[2] = {
3298 LLVMGetInsertBlock(builder),
3299 ctx->merged_wrap_if_state.entry_block
3300 };
3301 LLVMValueRef values[2];
3302
3303 lp_build_endif(&ctx->merged_wrap_if_state);
3304
3305 values[0] = rel_patch_id;
3306 values[1] = LLVMGetUndef(ctx->i32);
3307 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3308
3309 values[0] = tf_lds_offset;
3310 values[1] = LLVMGetUndef(ctx->i32);
3311 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3312
3313 values[0] = invocation_id;
3314 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3315 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3316 }
3317
3318 /* Return epilog parameters from this function. */
3319 LLVMValueRef ret = ctx->return_value;
3320 unsigned vgpr;
3321
3322 if (ctx->screen->info.chip_class >= GFX9) {
3323 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3324 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3325 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3326 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3327 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3328 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
3329 /* Tess offchip and tess factor offsets are at the beginning. */
3330 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3331 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3332 vgpr = 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K + 1;
3333 } else {
3334 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3335 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3336 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3337 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3338 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3339 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K);
3340 /* Tess offchip and tess factor offsets are after user SGPRs. */
3341 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3342 GFX6_TCS_NUM_USER_SGPR);
3343 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3344 GFX6_TCS_NUM_USER_SGPR + 1);
3345 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3346 }
3347
3348 /* VGPRs */
3349 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3350 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3351 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3352
3353 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3354 * the invocation_id output does not alias the tcs_rel_ids input,
3355 * which saves a V_MOV on gfx9.
3356 */
3357 vgpr += 2;
3358
3359 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3360 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3361
3362 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3363 vgpr++; /* skip the tess factor LDS offset */
3364 for (unsigned i = 0; i < 6; i++) {
3365 LLVMValueRef value =
3366 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3367 value = ac_to_float(&ctx->ac, value);
3368 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3369 }
3370 } else {
3371 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3372 }
3373 ctx->return_value = ret;
3374 }
3375
3376 /* Pass TCS inputs from LS to TCS on GFX9. */
3377 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3378 {
3379 LLVMValueRef ret = ctx->return_value;
3380
3381 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3382 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3383 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3384 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3385
3386 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
3387 8 + SI_SGPR_RW_BUFFERS);
3388 ret = si_insert_input_ptr_as_2xi32(ctx, ret,
3389 ctx->param_bindless_samplers_and_images,
3390 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3391
3392 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3393 8 + SI_SGPR_VS_STATE_BITS);
3394 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3395 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3396 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3397 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3398 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3399 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3400 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3401 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3402 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3403 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
3404
3405 unsigned desc_param = ctx->param_tcs_factor_addr_base64k + 2;
3406 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
3407 8 + GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS);
3408 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
3409 8 + GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES);
3410
3411 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3412 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3413 ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
3414 vgpr++, "");
3415 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3416 ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
3417 vgpr++, "");
3418 ctx->return_value = ret;
3419 }
3420
3421 /* Pass GS inputs from ES to GS on GFX9. */
3422 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3423 {
3424 LLVMValueRef ret = ctx->return_value;
3425
3426 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3427 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3428 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3429
3430 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
3431 8 + SI_SGPR_RW_BUFFERS);
3432 ret = si_insert_input_ptr_as_2xi32(ctx, ret,
3433 ctx->param_bindless_samplers_and_images,
3434 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3435
3436 unsigned desc_param = ctx->param_vs_state_bits + 1;
3437 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
3438 8 + GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS);
3439 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
3440 8 + GFX9_SGPR_GS_SAMPLERS_AND_IMAGES);
3441
3442 unsigned vgpr = 8 + GFX9_GS_NUM_USER_SGPR;
3443 for (unsigned i = 0; i < 5; i++) {
3444 unsigned param = ctx->param_gs_vtx01_offset + i;
3445 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3446 }
3447 ctx->return_value = ret;
3448 }
3449
3450 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3451 unsigned max_outputs,
3452 LLVMValueRef *addrs)
3453 {
3454 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3455 struct si_shader *shader = ctx->shader;
3456 struct tgsi_shader_info *info = &shader->selector->info;
3457 unsigned i, chan;
3458 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3459 ctx->param_rel_auto_id);
3460 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3461 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3462 vertex_dw_stride, "");
3463
3464 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3465 * its inputs from it. */
3466 for (i = 0; i < info->num_outputs; i++) {
3467 unsigned name = info->output_semantic_name[i];
3468 unsigned index = info->output_semantic_index[i];
3469
3470 /* The ARB_shader_viewport_layer_array spec contains the
3471 * following issue:
3472 *
3473 * 2) What happens if gl_ViewportIndex or gl_Layer is
3474 * written in the vertex shader and a geometry shader is
3475 * present?
3476 *
3477 * RESOLVED: The value written by the last vertex processing
3478 * stage is used. If the last vertex processing stage
3479 * (vertex, tessellation evaluation or geometry) does not
3480 * statically assign to gl_ViewportIndex or gl_Layer, index
3481 * or layer zero is assumed.
3482 *
3483 * So writes to those outputs in VS-as-LS are simply ignored.
3484 */
3485 if (name == TGSI_SEMANTIC_LAYER ||
3486 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3487 continue;
3488
3489 int param = si_shader_io_get_unique_index(name, index);
3490 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3491 LLVMConstInt(ctx->i32, param * 4, 0), "");
3492
3493 for (chan = 0; chan < 4; chan++) {
3494 if (!(info->output_usagemask[i] & (1 << chan)))
3495 continue;
3496
3497 lds_store(ctx, chan, dw_addr,
3498 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3499 }
3500 }
3501
3502 if (ctx->screen->info.chip_class >= GFX9)
3503 si_set_ls_return_value_for_tcs(ctx);
3504 }
3505
3506 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3507 unsigned max_outputs,
3508 LLVMValueRef *addrs)
3509 {
3510 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3511 struct si_shader *es = ctx->shader;
3512 struct tgsi_shader_info *info = &es->selector->info;
3513 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3514 ctx->param_es2gs_offset);
3515 LLVMValueRef lds_base = NULL;
3516 unsigned chan;
3517 int i;
3518
3519 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3520 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3521 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3522 LLVMValueRef wave_idx = unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3523 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3524 LLVMBuildMul(ctx->ac.builder, wave_idx,
3525 LLVMConstInt(ctx->i32, 64, false), ""), "");
3526 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3527 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3528 }
3529
3530 for (i = 0; i < info->num_outputs; i++) {
3531 int param;
3532
3533 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3534 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3535 continue;
3536
3537 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3538 info->output_semantic_index[i]);
3539
3540 for (chan = 0; chan < 4; chan++) {
3541 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3542 out_val = ac_to_integer(&ctx->ac, out_val);
3543
3544 /* GFX9 has the ESGS ring in LDS. */
3545 if (ctx->screen->info.chip_class >= GFX9) {
3546 lds_store(ctx, param * 4 + chan, lds_base, out_val);
3547 continue;
3548 }
3549
3550 ac_build_buffer_store_dword(&ctx->ac,
3551 ctx->esgs_ring,
3552 out_val, 1, NULL, soffset,
3553 (4 * param + chan) * 4,
3554 1, 1, true, true);
3555 }
3556 }
3557
3558 if (ctx->screen->info.chip_class >= GFX9)
3559 si_set_es_return_value_for_gs(ctx);
3560 }
3561
3562 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3563 {
3564 if (ctx->screen->info.chip_class >= GFX9)
3565 return unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3566 else
3567 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3568 }
3569
3570 static void emit_gs_epilogue(struct si_shader_context *ctx)
3571 {
3572 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3573 si_get_gs_wave_id(ctx));
3574
3575 if (ctx->screen->info.chip_class >= GFX9)
3576 lp_build_endif(&ctx->merged_wrap_if_state);
3577 }
3578
3579 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3580 unsigned max_outputs,
3581 LLVMValueRef *addrs)
3582 {
3583 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3584 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3585
3586 assert(info->num_outputs <= max_outputs);
3587
3588 emit_gs_epilogue(ctx);
3589 }
3590
3591 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3592 {
3593 struct si_shader_context *ctx = si_shader_context(bld_base);
3594 emit_gs_epilogue(ctx);
3595 }
3596
3597 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3598 unsigned max_outputs,
3599 LLVMValueRef *addrs)
3600 {
3601 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3602 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3603 struct si_shader_output_values *outputs = NULL;
3604 int i,j;
3605
3606 assert(!ctx->shader->is_gs_copy_shader);
3607 assert(info->num_outputs <= max_outputs);
3608
3609 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3610
3611 /* Vertex color clamping.
3612 *
3613 * This uses a state constant loaded in a user data SGPR and
3614 * an IF statement is added that clamps all colors if the constant
3615 * is true.
3616 */
3617 if (ctx->type == PIPE_SHADER_VERTEX) {
3618 struct lp_build_if_state if_ctx;
3619 LLVMValueRef cond = NULL;
3620 LLVMValueRef addr, val;
3621
3622 for (i = 0; i < info->num_outputs; i++) {
3623 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3624 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3625 continue;
3626
3627 /* We've found a color. */
3628 if (!cond) {
3629 /* The state is in the first bit of the user SGPR. */
3630 cond = LLVMGetParam(ctx->main_fn,
3631 ctx->param_vs_state_bits);
3632 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3633 ctx->i1, "");
3634 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3635 }
3636
3637 for (j = 0; j < 4; j++) {
3638 addr = addrs[4 * i + j];
3639 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3640 val = ac_build_clamp(&ctx->ac, val);
3641 LLVMBuildStore(ctx->ac.builder, val, addr);
3642 }
3643 }
3644
3645 if (cond)
3646 lp_build_endif(&if_ctx);
3647 }
3648
3649 for (i = 0; i < info->num_outputs; i++) {
3650 outputs[i].semantic_name = info->output_semantic_name[i];
3651 outputs[i].semantic_index = info->output_semantic_index[i];
3652
3653 for (j = 0; j < 4; j++) {
3654 outputs[i].values[j] =
3655 LLVMBuildLoad(ctx->ac.builder,
3656 addrs[4 * i + j],
3657 "");
3658 outputs[i].vertex_stream[j] =
3659 (info->output_streams[i] >> (2 * j)) & 3;
3660 }
3661 }
3662
3663 if (ctx->shader->selector->so.num_outputs)
3664 si_llvm_emit_streamout(ctx, outputs, i, 0);
3665
3666 /* Export PrimitiveID. */
3667 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3668 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3669 outputs[i].semantic_index = 0;
3670 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3671 for (j = 1; j < 4; j++)
3672 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3673
3674 memset(outputs[i].vertex_stream, 0,
3675 sizeof(outputs[i].vertex_stream));
3676 i++;
3677 }
3678
3679 si_llvm_export_vs(ctx, outputs, i);
3680 FREE(outputs);
3681 }
3682
3683 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3684 {
3685 struct si_shader_context *ctx = si_shader_context(bld_base);
3686
3687 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3688 &ctx->outputs[0][0]);
3689 }
3690
3691 struct si_ps_exports {
3692 unsigned num;
3693 struct ac_export_args args[10];
3694 };
3695
3696 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3697 LLVMValueRef depth, LLVMValueRef stencil,
3698 LLVMValueRef samplemask, struct si_ps_exports *exp)
3699 {
3700 struct si_shader_context *ctx = si_shader_context(bld_base);
3701 struct ac_export_args args;
3702
3703 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3704
3705 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3706 }
3707
3708 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3709 LLVMValueRef *color, unsigned index,
3710 unsigned samplemask_param,
3711 bool is_last, struct si_ps_exports *exp)
3712 {
3713 struct si_shader_context *ctx = si_shader_context(bld_base);
3714 int i;
3715
3716 /* Clamp color */
3717 if (ctx->shader->key.part.ps.epilog.clamp_color)
3718 for (i = 0; i < 4; i++)
3719 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3720
3721 /* Alpha to one */
3722 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3723 color[3] = ctx->ac.f32_1;
3724
3725 /* Alpha test */
3726 if (index == 0 &&
3727 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3728 si_alpha_test(bld_base, color[3]);
3729
3730 /* Line & polygon smoothing */
3731 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3732 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3733 samplemask_param);
3734
3735 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3736 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3737 struct ac_export_args args[8];
3738 int c, last = -1;
3739
3740 /* Get the export arguments, also find out what the last one is. */
3741 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3742 si_llvm_init_export_args(ctx, color,
3743 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3744 if (args[c].enabled_channels)
3745 last = c;
3746 }
3747
3748 /* Emit all exports. */
3749 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3750 if (is_last && last == c) {
3751 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3752 args[c].done = 1; /* DONE bit */
3753 } else if (!args[c].enabled_channels)
3754 continue; /* unnecessary NULL export */
3755
3756 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3757 }
3758 } else {
3759 struct ac_export_args args;
3760
3761 /* Export */
3762 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3763 &args);
3764 if (is_last) {
3765 args.valid_mask = 1; /* whether the EXEC mask is valid */
3766 args.done = 1; /* DONE bit */
3767 } else if (!args.enabled_channels)
3768 return; /* unnecessary NULL export */
3769
3770 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3771 }
3772 }
3773
3774 static void si_emit_ps_exports(struct si_shader_context *ctx,
3775 struct si_ps_exports *exp)
3776 {
3777 for (unsigned i = 0; i < exp->num; i++)
3778 ac_build_export(&ctx->ac, &exp->args[i]);
3779 }
3780
3781 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3782 {
3783 struct si_shader_context *ctx = si_shader_context(bld_base);
3784 struct lp_build_context *base = &bld_base->base;
3785 struct ac_export_args args;
3786
3787 args.enabled_channels = 0x0; /* enabled channels */
3788 args.valid_mask = 1; /* whether the EXEC mask is valid */
3789 args.done = 1; /* DONE bit */
3790 args.target = V_008DFC_SQ_EXP_NULL;
3791 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
3792 args.out[0] = base->undef; /* R */
3793 args.out[1] = base->undef; /* G */
3794 args.out[2] = base->undef; /* B */
3795 args.out[3] = base->undef; /* A */
3796
3797 ac_build_export(&ctx->ac, &args);
3798 }
3799
3800 /**
3801 * Return PS outputs in this order:
3802 *
3803 * v[0:3] = color0.xyzw
3804 * v[4:7] = color1.xyzw
3805 * ...
3806 * vN+0 = Depth
3807 * vN+1 = Stencil
3808 * vN+2 = SampleMask
3809 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3810 *
3811 * The alpha-ref SGPR is returned via its original location.
3812 */
3813 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3814 unsigned max_outputs,
3815 LLVMValueRef *addrs)
3816 {
3817 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3818 struct si_shader *shader = ctx->shader;
3819 struct tgsi_shader_info *info = &shader->selector->info;
3820 LLVMBuilderRef builder = ctx->ac.builder;
3821 unsigned i, j, first_vgpr, vgpr;
3822
3823 LLVMValueRef color[8][4] = {};
3824 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3825 LLVMValueRef ret;
3826
3827 if (ctx->postponed_kill)
3828 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3829
3830 /* Read the output values. */
3831 for (i = 0; i < info->num_outputs; i++) {
3832 unsigned semantic_name = info->output_semantic_name[i];
3833 unsigned semantic_index = info->output_semantic_index[i];
3834
3835 switch (semantic_name) {
3836 case TGSI_SEMANTIC_COLOR:
3837 assert(semantic_index < 8);
3838 for (j = 0; j < 4; j++) {
3839 LLVMValueRef ptr = addrs[4 * i + j];
3840 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3841 color[semantic_index][j] = result;
3842 }
3843 break;
3844 case TGSI_SEMANTIC_POSITION:
3845 depth = LLVMBuildLoad(builder,
3846 addrs[4 * i + 2], "");
3847 break;
3848 case TGSI_SEMANTIC_STENCIL:
3849 stencil = LLVMBuildLoad(builder,
3850 addrs[4 * i + 1], "");
3851 break;
3852 case TGSI_SEMANTIC_SAMPLEMASK:
3853 samplemask = LLVMBuildLoad(builder,
3854 addrs[4 * i + 0], "");
3855 break;
3856 default:
3857 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3858 semantic_name);
3859 }
3860 }
3861
3862 /* Fill the return structure. */
3863 ret = ctx->return_value;
3864
3865 /* Set SGPRs. */
3866 ret = LLVMBuildInsertValue(builder, ret,
3867 ac_to_integer(&ctx->ac,
3868 LLVMGetParam(ctx->main_fn,
3869 SI_PARAM_ALPHA_REF)),
3870 SI_SGPR_ALPHA_REF, "");
3871
3872 /* Set VGPRs */
3873 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3874 for (i = 0; i < ARRAY_SIZE(color); i++) {
3875 if (!color[i][0])
3876 continue;
3877
3878 for (j = 0; j < 4; j++)
3879 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3880 }
3881 if (depth)
3882 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3883 if (stencil)
3884 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3885 if (samplemask)
3886 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3887
3888 /* Add the input sample mask for smoothing at the end. */
3889 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3890 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3891 ret = LLVMBuildInsertValue(builder, ret,
3892 LLVMGetParam(ctx->main_fn,
3893 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3894
3895 ctx->return_value = ret;
3896 }
3897
3898 static void membar_emit(
3899 const struct lp_build_tgsi_action *action,
3900 struct lp_build_tgsi_context *bld_base,
3901 struct lp_build_emit_data *emit_data)
3902 {
3903 struct si_shader_context *ctx = si_shader_context(bld_base);
3904 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3905 unsigned flags = LLVMConstIntGetZExtValue(src0);
3906 unsigned waitcnt = NOOP_WAITCNT;
3907
3908 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3909 waitcnt &= VM_CNT & LGKM_CNT;
3910
3911 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3912 TGSI_MEMBAR_SHADER_BUFFER |
3913 TGSI_MEMBAR_SHADER_IMAGE))
3914 waitcnt &= VM_CNT;
3915
3916 if (flags & TGSI_MEMBAR_SHARED)
3917 waitcnt &= LGKM_CNT;
3918
3919 if (waitcnt != NOOP_WAITCNT)
3920 ac_build_waitcnt(&ctx->ac, waitcnt);
3921 }
3922
3923 static void clock_emit(
3924 const struct lp_build_tgsi_action *action,
3925 struct lp_build_tgsi_context *bld_base,
3926 struct lp_build_emit_data *emit_data)
3927 {
3928 struct si_shader_context *ctx = si_shader_context(bld_base);
3929 LLVMValueRef tmp;
3930
3931 tmp = lp_build_intrinsic(ctx->ac.builder, "llvm.readcyclecounter",
3932 ctx->i64, NULL, 0, 0);
3933 tmp = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->v2i32, "");
3934
3935 emit_data->output[0] =
3936 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3937 emit_data->output[1] =
3938 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3939 }
3940
3941 LLVMTypeRef si_const_array(LLVMTypeRef elem_type, int num_elements)
3942 {
3943 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3944 CONST_ADDR_SPACE);
3945 }
3946
3947 static void si_llvm_emit_ddxy(
3948 const struct lp_build_tgsi_action *action,
3949 struct lp_build_tgsi_context *bld_base,
3950 struct lp_build_emit_data *emit_data)
3951 {
3952 struct si_shader_context *ctx = si_shader_context(bld_base);
3953 unsigned opcode = emit_data->info->opcode;
3954 LLVMValueRef val;
3955 int idx;
3956 unsigned mask;
3957
3958 if (opcode == TGSI_OPCODE_DDX_FINE)
3959 mask = AC_TID_MASK_LEFT;
3960 else if (opcode == TGSI_OPCODE_DDY_FINE)
3961 mask = AC_TID_MASK_TOP;
3962 else
3963 mask = AC_TID_MASK_TOP_LEFT;
3964
3965 /* for DDX we want to next X pixel, DDY next Y pixel. */
3966 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3967
3968 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3969 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3970 emit_data->output[emit_data->chan] = val;
3971 }
3972
3973 /*
3974 * this takes an I,J coordinate pair,
3975 * and works out the X and Y derivatives.
3976 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3977 */
3978 static LLVMValueRef si_llvm_emit_ddxy_interp(
3979 struct lp_build_tgsi_context *bld_base,
3980 LLVMValueRef interp_ij)
3981 {
3982 struct si_shader_context *ctx = si_shader_context(bld_base);
3983 LLVMValueRef result[4], a;
3984 unsigned i;
3985
3986 for (i = 0; i < 2; i++) {
3987 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
3988 LLVMConstInt(ctx->i32, i, 0), "");
3989 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
3990 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
3991 }
3992
3993 return lp_build_gather_values(&ctx->gallivm, result, 4);
3994 }
3995
3996 static void interp_fetch_args(
3997 struct lp_build_tgsi_context *bld_base,
3998 struct lp_build_emit_data *emit_data)
3999 {
4000 struct si_shader_context *ctx = si_shader_context(bld_base);
4001 const struct tgsi_full_instruction *inst = emit_data->inst;
4002
4003 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
4004 /* offset is in second src, first two channels */
4005 emit_data->args[0] = lp_build_emit_fetch(bld_base,
4006 emit_data->inst, 1,
4007 TGSI_CHAN_X);
4008 emit_data->args[1] = lp_build_emit_fetch(bld_base,
4009 emit_data->inst, 1,
4010 TGSI_CHAN_Y);
4011 emit_data->arg_count = 2;
4012 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4013 LLVMValueRef sample_position;
4014 LLVMValueRef sample_id;
4015 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
4016
4017 /* fetch sample ID, then fetch its sample position,
4018 * and place into first two channels.
4019 */
4020 sample_id = lp_build_emit_fetch(bld_base,
4021 emit_data->inst, 1, TGSI_CHAN_X);
4022 sample_id = ac_to_integer(&ctx->ac, sample_id);
4023
4024 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
4025 * Language 4.50 spec says about interpolateAtSample:
4026 *
4027 * "Returns the value of the input interpolant variable at
4028 * the location of sample number sample. If multisample
4029 * buffers are not available, the input variable will be
4030 * evaluated at the center of the pixel. If sample sample
4031 * does not exist, the position used to interpolate the
4032 * input variable is undefined."
4033 *
4034 * This means that sample_id values outside of the valid are
4035 * in fact valid input, and the usual mechanism for loading the
4036 * sample position doesn't work.
4037 */
4038 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
4039 LLVMValueRef center[4] = {
4040 LLVMConstReal(ctx->f32, 0.5),
4041 LLVMConstReal(ctx->f32, 0.5),
4042 ctx->ac.f32_0,
4043 ctx->ac.f32_0,
4044 };
4045
4046 sample_position = lp_build_gather_values(&ctx->gallivm, center, 4);
4047 } else {
4048 sample_position = load_sample_position(ctx, sample_id);
4049 }
4050
4051 emit_data->args[0] = LLVMBuildExtractElement(ctx->ac.builder,
4052 sample_position,
4053 ctx->i32_0, "");
4054
4055 emit_data->args[0] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[0], halfval, "");
4056 emit_data->args[1] = LLVMBuildExtractElement(ctx->ac.builder,
4057 sample_position,
4058 ctx->i32_1, "");
4059 emit_data->args[1] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[1], halfval, "");
4060 emit_data->arg_count = 2;
4061 }
4062 }
4063
4064 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
4065 struct lp_build_tgsi_context *bld_base,
4066 struct lp_build_emit_data *emit_data)
4067 {
4068 struct si_shader_context *ctx = si_shader_context(bld_base);
4069 struct si_shader *shader = ctx->shader;
4070 const struct tgsi_shader_info *info = &shader->selector->info;
4071 LLVMValueRef interp_param;
4072 const struct tgsi_full_instruction *inst = emit_data->inst;
4073 const struct tgsi_full_src_register *input = &inst->Src[0];
4074 int input_base, input_array_size;
4075 int chan;
4076 int i;
4077 LLVMValueRef prim_mask = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
4078 LLVMValueRef array_idx;
4079 int interp_param_idx;
4080 unsigned interp;
4081 unsigned location;
4082
4083 assert(input->Register.File == TGSI_FILE_INPUT);
4084
4085 if (input->Register.Indirect) {
4086 unsigned array_id = input->Indirect.ArrayID;
4087
4088 if (array_id) {
4089 input_base = info->input_array_first[array_id];
4090 input_array_size = info->input_array_last[array_id] - input_base + 1;
4091 } else {
4092 input_base = inst->Src[0].Register.Index;
4093 input_array_size = info->num_inputs - input_base;
4094 }
4095
4096 array_idx = si_get_indirect_index(ctx, &input->Indirect,
4097 1, input->Register.Index - input_base);
4098 } else {
4099 input_base = inst->Src[0].Register.Index;
4100 input_array_size = 1;
4101 array_idx = ctx->i32_0;
4102 }
4103
4104 interp = shader->selector->info.input_interpolate[input_base];
4105
4106 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4107 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4108 location = TGSI_INTERPOLATE_LOC_CENTER;
4109 else
4110 location = TGSI_INTERPOLATE_LOC_CENTROID;
4111
4112 interp_param_idx = lookup_interp_param_index(interp, location);
4113 if (interp_param_idx == -1)
4114 return;
4115 else if (interp_param_idx)
4116 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4117 else
4118 interp_param = NULL;
4119
4120 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4121 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4122 LLVMValueRef ij_out[2];
4123 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
4124
4125 /*
4126 * take the I then J parameters, and the DDX/Y for it, and
4127 * calculate the IJ inputs for the interpolator.
4128 * temp1 = ddx * offset/sample.x + I;
4129 * interp_param.I = ddy * offset/sample.y + temp1;
4130 * temp1 = ddx * offset/sample.x + J;
4131 * interp_param.J = ddy * offset/sample.y + temp1;
4132 */
4133 for (i = 0; i < 2; i++) {
4134 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
4135 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
4136 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4137 ddxy_out, ix_ll, "");
4138 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4139 ddxy_out, iy_ll, "");
4140 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4141 interp_param, ix_ll, "");
4142 LLVMValueRef temp1, temp2;
4143
4144 interp_el = ac_to_float(&ctx->ac, interp_el);
4145
4146 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, emit_data->args[0], "");
4147
4148 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4149
4150 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, emit_data->args[1], "");
4151
4152 ij_out[i] = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4153 }
4154 interp_param = lp_build_gather_values(&ctx->gallivm, ij_out, 2);
4155 }
4156
4157 if (interp_param)
4158 interp_param = ac_to_float(&ctx->ac, interp_param);
4159
4160 for (chan = 0; chan < 4; chan++) {
4161 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
4162 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4163
4164 for (unsigned idx = 0; idx < input_array_size; ++idx) {
4165 LLVMValueRef v, i = NULL, j = NULL;
4166
4167 if (interp_param) {
4168 i = LLVMBuildExtractElement(
4169 ctx->ac.builder, interp_param, ctx->i32_0, "");
4170 j = LLVMBuildExtractElement(
4171 ctx->ac.builder, interp_param, ctx->i32_1, "");
4172 }
4173 v = si_build_fs_interp(ctx, input_base + idx, schan,
4174 prim_mask, i, j);
4175
4176 gather = LLVMBuildInsertElement(ctx->ac.builder,
4177 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
4178 }
4179
4180 emit_data->output[chan] = LLVMBuildExtractElement(
4181 ctx->ac.builder, gather, array_idx, "");
4182 }
4183 }
4184
4185 static void vote_all_emit(
4186 const struct lp_build_tgsi_action *action,
4187 struct lp_build_tgsi_context *bld_base,
4188 struct lp_build_emit_data *emit_data)
4189 {
4190 struct si_shader_context *ctx = si_shader_context(bld_base);
4191
4192 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
4193 emit_data->output[emit_data->chan] =
4194 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4195 }
4196
4197 static void vote_any_emit(
4198 const struct lp_build_tgsi_action *action,
4199 struct lp_build_tgsi_context *bld_base,
4200 struct lp_build_emit_data *emit_data)
4201 {
4202 struct si_shader_context *ctx = si_shader_context(bld_base);
4203
4204 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
4205 emit_data->output[emit_data->chan] =
4206 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4207 }
4208
4209 static void vote_eq_emit(
4210 const struct lp_build_tgsi_action *action,
4211 struct lp_build_tgsi_context *bld_base,
4212 struct lp_build_emit_data *emit_data)
4213 {
4214 struct si_shader_context *ctx = si_shader_context(bld_base);
4215
4216 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4217 emit_data->output[emit_data->chan] =
4218 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4219 }
4220
4221 static void ballot_emit(
4222 const struct lp_build_tgsi_action *action,
4223 struct lp_build_tgsi_context *bld_base,
4224 struct lp_build_emit_data *emit_data)
4225 {
4226 struct si_shader_context *ctx = si_shader_context(bld_base);
4227 LLVMBuilderRef builder = ctx->ac.builder;
4228 LLVMValueRef tmp;
4229
4230 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4231 tmp = ac_build_ballot(&ctx->ac, tmp);
4232 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4233
4234 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4235 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4236 }
4237
4238 static void read_invoc_fetch_args(
4239 struct lp_build_tgsi_context *bld_base,
4240 struct lp_build_emit_data *emit_data)
4241 {
4242 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4243 0, emit_data->src_chan);
4244
4245 /* Always read the source invocation (= lane) from the X channel. */
4246 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4247 1, TGSI_CHAN_X);
4248 emit_data->arg_count = 2;
4249 }
4250
4251 static void read_lane_emit(
4252 const struct lp_build_tgsi_action *action,
4253 struct lp_build_tgsi_context *bld_base,
4254 struct lp_build_emit_data *emit_data)
4255 {
4256 struct si_shader_context *ctx = si_shader_context(bld_base);
4257
4258 /* We currently have no other way to prevent LLVM from lifting the icmp
4259 * calls to a dominating basic block.
4260 */
4261 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4262
4263 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4264 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4265
4266 emit_data->output[emit_data->chan] =
4267 ac_build_intrinsic(&ctx->ac, action->intr_name,
4268 ctx->i32, emit_data->args, emit_data->arg_count,
4269 AC_FUNC_ATTR_READNONE |
4270 AC_FUNC_ATTR_CONVERGENT);
4271 }
4272
4273 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4274 struct lp_build_emit_data *emit_data)
4275 {
4276 struct si_shader_context *ctx = si_shader_context(bld_base);
4277 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4278 LLVMValueRef imm;
4279 unsigned stream;
4280
4281 assert(src0.File == TGSI_FILE_IMMEDIATE);
4282
4283 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4284 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4285 return stream;
4286 }
4287
4288 /* Emit one vertex from the geometry shader */
4289 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4290 unsigned stream,
4291 LLVMValueRef *addrs)
4292 {
4293 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4294 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4295 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
4296 struct si_shader *shader = ctx->shader;
4297 struct lp_build_if_state if_state;
4298 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4299 ctx->param_gs2vs_offset);
4300 LLVMValueRef gs_next_vertex;
4301 LLVMValueRef can_emit;
4302 unsigned chan, offset;
4303 int i;
4304
4305 /* Write vertex attribute values to GSVS ring */
4306 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4307 ctx->gs_next_vertex[stream],
4308 "");
4309
4310 /* If this thread has already emitted the declared maximum number of
4311 * vertices, skip the write: excessive vertex emissions are not
4312 * supposed to have any effect.
4313 *
4314 * If the shader has no writes to memory, kill it instead. This skips
4315 * further memory loads and may allow LLVM to skip to the end
4316 * altogether.
4317 */
4318 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4319 LLVMConstInt(ctx->i32,
4320 shader->selector->gs_max_out_vertices, 0), "");
4321
4322 bool use_kill = !info->writes_memory;
4323 if (use_kill) {
4324 ac_build_kill_if_false(&ctx->ac, can_emit);
4325 } else {
4326 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4327 }
4328
4329 offset = 0;
4330 for (i = 0; i < info->num_outputs; i++) {
4331 for (chan = 0; chan < 4; chan++) {
4332 if (!(info->output_usagemask[i] & (1 << chan)) ||
4333 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4334 continue;
4335
4336 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4337 LLVMValueRef voffset =
4338 LLVMConstInt(ctx->i32, offset *
4339 shader->selector->gs_max_out_vertices, 0);
4340 offset++;
4341
4342 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4343 voffset = lp_build_mul_imm(uint, voffset, 4);
4344
4345 out_val = ac_to_integer(&ctx->ac, out_val);
4346
4347 ac_build_buffer_store_dword(&ctx->ac,
4348 ctx->gsvs_ring[stream],
4349 out_val, 1,
4350 voffset, soffset, 0,
4351 1, 1, true, true);
4352 }
4353 }
4354
4355 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4356 ctx->i32_1);
4357
4358 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4359
4360 /* Signal vertex emission */
4361 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4362 si_get_gs_wave_id(ctx));
4363 if (!use_kill)
4364 lp_build_endif(&if_state);
4365 }
4366
4367 /* Emit one vertex from the geometry shader */
4368 static void si_tgsi_emit_vertex(
4369 const struct lp_build_tgsi_action *action,
4370 struct lp_build_tgsi_context *bld_base,
4371 struct lp_build_emit_data *emit_data)
4372 {
4373 struct si_shader_context *ctx = si_shader_context(bld_base);
4374 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4375
4376 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4377 }
4378
4379 /* Cut one primitive from the geometry shader */
4380 static void si_llvm_emit_primitive(
4381 const struct lp_build_tgsi_action *action,
4382 struct lp_build_tgsi_context *bld_base,
4383 struct lp_build_emit_data *emit_data)
4384 {
4385 struct si_shader_context *ctx = si_shader_context(bld_base);
4386 unsigned stream;
4387
4388 /* Signal primitive cut */
4389 stream = si_llvm_get_stream(bld_base, emit_data);
4390 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4391 si_get_gs_wave_id(ctx));
4392 }
4393
4394 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4395 struct lp_build_tgsi_context *bld_base,
4396 struct lp_build_emit_data *emit_data)
4397 {
4398 struct si_shader_context *ctx = si_shader_context(bld_base);
4399
4400 /* SI only (thanks to a hw bug workaround):
4401 * The real barrier instruction isn’t needed, because an entire patch
4402 * always fits into a single wave.
4403 */
4404 if (ctx->screen->info.chip_class == SI &&
4405 ctx->type == PIPE_SHADER_TESS_CTRL) {
4406 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
4407 return;
4408 }
4409
4410 lp_build_intrinsic(ctx->ac.builder,
4411 "llvm.amdgcn.s.barrier",
4412 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
4413 }
4414
4415 static const struct lp_build_tgsi_action interp_action = {
4416 .fetch_args = interp_fetch_args,
4417 .emit = build_interp_intrinsic,
4418 };
4419
4420 static void si_create_function(struct si_shader_context *ctx,
4421 const char *name,
4422 LLVMTypeRef *returns, unsigned num_returns,
4423 struct si_function_info *fninfo,
4424 unsigned max_workgroup_size)
4425 {
4426 int i;
4427
4428 si_llvm_create_func(ctx, name, returns, num_returns,
4429 fninfo->types, fninfo->num_params);
4430 ctx->return_value = LLVMGetUndef(ctx->return_type);
4431
4432 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4433 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4434
4435 /* The combination of:
4436 * - ByVal
4437 * - dereferenceable
4438 * - invariant.load
4439 * allows the optimization passes to move loads and reduces
4440 * SGPR spilling significantly.
4441 */
4442 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4443 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
4444 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
4445 ac_add_attr_dereferenceable(P, UINT64_MAX);
4446 } else
4447 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
4448 }
4449
4450 for (i = 0; i < fninfo->num_params; ++i) {
4451 if (fninfo->assign[i])
4452 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4453 }
4454
4455 if (max_workgroup_size) {
4456 si_llvm_add_attribute(ctx->main_fn, "amdgpu-max-work-group-size",
4457 max_workgroup_size);
4458 }
4459 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4460 "no-signed-zeros-fp-math",
4461 "true");
4462
4463 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4464 /* These were copied from some LLVM test. */
4465 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4466 "less-precise-fpmad",
4467 "true");
4468 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4469 "no-infs-fp-math",
4470 "true");
4471 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4472 "no-nans-fp-math",
4473 "true");
4474 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4475 "unsafe-fp-math",
4476 "true");
4477 }
4478 }
4479
4480 static void declare_streamout_params(struct si_shader_context *ctx,
4481 struct pipe_stream_output_info *so,
4482 struct si_function_info *fninfo)
4483 {
4484 int i;
4485
4486 /* Streamout SGPRs. */
4487 if (so->num_outputs) {
4488 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4489 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4490 else
4491 ctx->param_streamout_config = fninfo->num_params - 1;
4492
4493 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4494 }
4495 /* A streamout buffer offset is loaded if the stride is non-zero. */
4496 for (i = 0; i < 4; i++) {
4497 if (!so->stride[i])
4498 continue;
4499
4500 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4501 }
4502 }
4503
4504 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4505 {
4506 switch (shader->selector->type) {
4507 case PIPE_SHADER_TESS_CTRL:
4508 /* Return this so that LLVM doesn't remove s_barrier
4509 * instructions on chips where we use s_barrier. */
4510 return shader->selector->screen->info.chip_class >= CIK ? 128 : 64;
4511
4512 case PIPE_SHADER_GEOMETRY:
4513 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4514
4515 case PIPE_SHADER_COMPUTE:
4516 break; /* see below */
4517
4518 default:
4519 return 0;
4520 }
4521
4522 const unsigned *properties = shader->selector->info.properties;
4523 unsigned max_work_group_size =
4524 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4525 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4526 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4527
4528 if (!max_work_group_size) {
4529 /* This is a variable group size compute shader,
4530 * compile it for the maximum possible group size.
4531 */
4532 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4533 }
4534 return max_work_group_size;
4535 }
4536
4537 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4538 struct si_function_info *fninfo,
4539 bool assign_params)
4540 {
4541 LLVMTypeRef const_shader_buf_type;
4542
4543 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4544 ctx->shader->selector->info.shader_buffers_declared == 0)
4545 const_shader_buf_type = ctx->f32;
4546 else
4547 const_shader_buf_type = ctx->v4i32;
4548
4549 unsigned const_and_shader_buffers =
4550 add_arg(fninfo, ARG_SGPR,
4551 si_const_array(const_shader_buf_type, 0));
4552
4553 unsigned samplers_and_images =
4554 add_arg(fninfo, ARG_SGPR,
4555 si_const_array(ctx->v8i32,
4556 SI_NUM_IMAGES + SI_NUM_SAMPLERS * 2));
4557
4558 if (assign_params) {
4559 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4560 ctx->param_samplers_and_images = samplers_and_images;
4561 }
4562 }
4563
4564 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4565 struct si_function_info *fninfo)
4566 {
4567 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4568 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS));
4569 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4570 si_const_array(ctx->v8i32, 0));
4571 }
4572
4573 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4574 struct si_function_info *fninfo)
4575 {
4576 ctx->param_vertex_buffers = add_arg(fninfo, ARG_SGPR,
4577 si_const_array(ctx->v4i32, SI_NUM_VERTEX_BUFFERS));
4578 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4579 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4580 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4581 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4582 }
4583
4584 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4585 struct si_function_info *fninfo,
4586 unsigned *num_prolog_vgprs)
4587 {
4588 struct si_shader *shader = ctx->shader;
4589
4590 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4591 if (shader->key.as_ls) {
4592 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4593 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4594 } else {
4595 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4596 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4597 }
4598 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4599
4600 if (!shader->is_gs_copy_shader) {
4601 /* Vertex load indices. */
4602 ctx->param_vertex_index0 = fninfo->num_params;
4603 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4604 add_arg(fninfo, ARG_VGPR, ctx->i32);
4605 *num_prolog_vgprs += shader->selector->info.num_inputs;
4606 }
4607 }
4608
4609 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4610 struct si_function_info *fninfo)
4611 {
4612 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4613 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4614 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4615 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
4616 }
4617
4618 enum {
4619 /* Convenient merged shader definitions. */
4620 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4621 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4622 };
4623
4624 static void create_function(struct si_shader_context *ctx)
4625 {
4626 struct si_shader *shader = ctx->shader;
4627 struct si_function_info fninfo;
4628 LLVMTypeRef returns[16+32*4];
4629 unsigned i, num_return_sgprs;
4630 unsigned num_returns = 0;
4631 unsigned num_prolog_vgprs = 0;
4632 unsigned type = ctx->type;
4633 unsigned vs_blit_property =
4634 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4635
4636 si_init_function_info(&fninfo);
4637
4638 /* Set MERGED shaders. */
4639 if (ctx->screen->info.chip_class >= GFX9) {
4640 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4641 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4642 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4643 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4644 }
4645
4646 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4647
4648 switch (type) {
4649 case PIPE_SHADER_VERTEX:
4650 declare_global_desc_pointers(ctx, &fninfo);
4651
4652 if (vs_blit_property) {
4653 ctx->param_vs_blit_inputs = fninfo.num_params;
4654 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4655 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4656 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* depth */
4657
4658 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4659 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color0 */
4660 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color1 */
4661 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color2 */
4662 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color3 */
4663 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4664 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4665 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4666 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4667 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4668 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4669 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4670 }
4671
4672 /* VGPRs */
4673 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4674 break;
4675 }
4676
4677 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4678 declare_vs_specific_input_sgprs(ctx, &fninfo);
4679
4680 if (shader->key.as_es) {
4681 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4682 } else if (shader->key.as_ls) {
4683 /* no extra parameters */
4684 } else {
4685 if (shader->is_gs_copy_shader) {
4686 fninfo.num_params = ctx->param_rw_buffers + 1;
4687 fninfo.num_sgpr_params = fninfo.num_params;
4688 }
4689
4690 /* The locations of the other parameters are assigned dynamically. */
4691 declare_streamout_params(ctx, &shader->selector->so,
4692 &fninfo);
4693 }
4694
4695 /* VGPRs */
4696 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4697 break;
4698
4699 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4700 declare_global_desc_pointers(ctx, &fninfo);
4701 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4702 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4703 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4704 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4705 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4706 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4707 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4708 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4709 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4710
4711 /* VGPRs */
4712 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4713 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4714
4715 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4716 * placed after the user SGPRs.
4717 */
4718 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4719 returns[num_returns++] = ctx->i32; /* SGPRs */
4720 for (i = 0; i < 11; i++)
4721 returns[num_returns++] = ctx->f32; /* VGPRs */
4722 break;
4723
4724 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4725 /* Merged stages have 8 system SGPRs at the beginning. */
4726 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_LO_HS */
4727 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_HI_HS */
4728 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4729 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4730 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4731 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4732 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4733 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4734
4735 declare_global_desc_pointers(ctx, &fninfo);
4736 declare_per_stage_desc_pointers(ctx, &fninfo,
4737 ctx->type == PIPE_SHADER_VERTEX);
4738 declare_vs_specific_input_sgprs(ctx, &fninfo);
4739
4740 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4741 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4742 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4743 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4744 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4745 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4746
4747 declare_per_stage_desc_pointers(ctx, &fninfo,
4748 ctx->type == PIPE_SHADER_TESS_CTRL);
4749
4750 /* VGPRs (first TCS, then VS) */
4751 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4752 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4753
4754 if (ctx->type == PIPE_SHADER_VERTEX) {
4755 declare_vs_input_vgprs(ctx, &fninfo,
4756 &num_prolog_vgprs);
4757
4758 /* LS return values are inputs to the TCS main shader part. */
4759 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4760 returns[num_returns++] = ctx->i32; /* SGPRs */
4761 for (i = 0; i < 2; i++)
4762 returns[num_returns++] = ctx->f32; /* VGPRs */
4763 } else {
4764 /* TCS return values are inputs to the TCS epilog.
4765 *
4766 * param_tcs_offchip_offset, param_tcs_factor_offset,
4767 * param_tcs_offchip_layout, and param_rw_buffers
4768 * should be passed to the epilog.
4769 */
4770 for (i = 0; i <= 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K; i++)
4771 returns[num_returns++] = ctx->i32; /* SGPRs */
4772 for (i = 0; i < 11; i++)
4773 returns[num_returns++] = ctx->f32; /* VGPRs */
4774 }
4775 break;
4776
4777 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4778 /* Merged stages have 8 system SGPRs at the beginning. */
4779 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_LO_GS) */
4780 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_HI_GS) */
4781 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4782 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4783 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4784 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4785 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4786 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4787
4788 declare_global_desc_pointers(ctx, &fninfo);
4789 declare_per_stage_desc_pointers(ctx, &fninfo,
4790 (ctx->type == PIPE_SHADER_VERTEX ||
4791 ctx->type == PIPE_SHADER_TESS_EVAL));
4792 if (ctx->type == PIPE_SHADER_VERTEX) {
4793 declare_vs_specific_input_sgprs(ctx, &fninfo);
4794 } else {
4795 /* TESS_EVAL (and also GEOMETRY):
4796 * Declare as many input SGPRs as the VS has. */
4797 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4798 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4799 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4800 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4801 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4802 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4803 }
4804
4805 declare_per_stage_desc_pointers(ctx, &fninfo,
4806 ctx->type == PIPE_SHADER_GEOMETRY);
4807
4808 /* VGPRs (first GS, then VS/TES) */
4809 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4810 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4811 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4812 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4813 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4814
4815 if (ctx->type == PIPE_SHADER_VERTEX) {
4816 declare_vs_input_vgprs(ctx, &fninfo,
4817 &num_prolog_vgprs);
4818 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4819 declare_tes_input_vgprs(ctx, &fninfo);
4820 }
4821
4822 if (ctx->type == PIPE_SHADER_VERTEX ||
4823 ctx->type == PIPE_SHADER_TESS_EVAL) {
4824 /* ES return values are inputs to GS. */
4825 for (i = 0; i < 8 + GFX9_GS_NUM_USER_SGPR; i++)
4826 returns[num_returns++] = ctx->i32; /* SGPRs */
4827 for (i = 0; i < 5; i++)
4828 returns[num_returns++] = ctx->f32; /* VGPRs */
4829 }
4830 break;
4831
4832 case PIPE_SHADER_TESS_EVAL:
4833 declare_global_desc_pointers(ctx, &fninfo);
4834 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4835 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4836 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4837
4838 if (shader->key.as_es) {
4839 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4840 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4841 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4842 } else {
4843 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4844 declare_streamout_params(ctx, &shader->selector->so,
4845 &fninfo);
4846 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4847 }
4848
4849 /* VGPRs */
4850 declare_tes_input_vgprs(ctx, &fninfo);
4851 break;
4852
4853 case PIPE_SHADER_GEOMETRY:
4854 declare_global_desc_pointers(ctx, &fninfo);
4855 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4856 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4857 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4858
4859 /* VGPRs */
4860 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4861 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4862 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4863 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4864 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4865 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4866 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4867 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4868 break;
4869
4870 case PIPE_SHADER_FRAGMENT:
4871 declare_global_desc_pointers(ctx, &fninfo);
4872 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4873 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4874 add_arg_checked(&fninfo, ARG_SGPR, ctx->i32, SI_PARAM_PRIM_MASK);
4875
4876 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4877 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4878 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4879 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4880 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4881 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4882 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4883 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4884 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4885 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4886 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4887 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4888 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4889 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4890 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4891 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4892 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4893 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4894 shader->info.face_vgpr_index = 20;
4895 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4896 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4897 shader->info.ancillary_vgpr_index = 21;
4898 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4899 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4900 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4901
4902 /* Color inputs from the prolog. */
4903 if (shader->selector->info.colors_read) {
4904 unsigned num_color_elements =
4905 util_bitcount(shader->selector->info.colors_read);
4906
4907 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4908 for (i = 0; i < num_color_elements; i++)
4909 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4910
4911 num_prolog_vgprs += num_color_elements;
4912 }
4913
4914 /* Outputs for the epilog. */
4915 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4916 num_returns =
4917 num_return_sgprs +
4918 util_bitcount(shader->selector->info.colors_written) * 4 +
4919 shader->selector->info.writes_z +
4920 shader->selector->info.writes_stencil +
4921 shader->selector->info.writes_samplemask +
4922 1 /* SampleMaskIn */;
4923
4924 num_returns = MAX2(num_returns,
4925 num_return_sgprs +
4926 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4927
4928 for (i = 0; i < num_return_sgprs; i++)
4929 returns[i] = ctx->i32;
4930 for (; i < num_returns; i++)
4931 returns[i] = ctx->f32;
4932 break;
4933
4934 case PIPE_SHADER_COMPUTE:
4935 declare_global_desc_pointers(ctx, &fninfo);
4936 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4937 if (shader->selector->info.uses_grid_size)
4938 ctx->param_grid_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4939 if (shader->selector->info.uses_block_size)
4940 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4941
4942 for (i = 0; i < 3; i++) {
4943 ctx->param_block_id[i] = -1;
4944 if (shader->selector->info.uses_block_id[i])
4945 ctx->param_block_id[i] = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4946 }
4947
4948 ctx->param_thread_id = add_arg(&fninfo, ARG_VGPR, v3i32);
4949 break;
4950 default:
4951 assert(0 && "unimplemented shader");
4952 return;
4953 }
4954
4955 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4956 si_get_max_workgroup_size(shader));
4957
4958 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4959 if (ctx->type == PIPE_SHADER_FRAGMENT &&
4960 ctx->separate_prolog) {
4961 si_llvm_add_attribute(ctx->main_fn,
4962 "InitialPSInputAddr",
4963 S_0286D0_PERSP_SAMPLE_ENA(1) |
4964 S_0286D0_PERSP_CENTER_ENA(1) |
4965 S_0286D0_PERSP_CENTROID_ENA(1) |
4966 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4967 S_0286D0_LINEAR_CENTER_ENA(1) |
4968 S_0286D0_LINEAR_CENTROID_ENA(1) |
4969 S_0286D0_FRONT_FACE_ENA(1) |
4970 S_0286D0_ANCILLARY_ENA(1) |
4971 S_0286D0_POS_FIXED_PT_ENA(1));
4972 }
4973
4974 shader->info.num_input_sgprs = 0;
4975 shader->info.num_input_vgprs = 0;
4976
4977 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4978 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
4979
4980 for (; i < fninfo.num_params; ++i)
4981 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
4982
4983 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4984 shader->info.num_input_vgprs -= num_prolog_vgprs;
4985
4986 if (shader->key.as_ls ||
4987 ctx->type == PIPE_SHADER_TESS_CTRL ||
4988 /* GFX9 has the ESGS ring buffer in LDS. */
4989 type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY)
4990 ac_declare_lds_as_pointer(&ctx->ac);
4991 }
4992
4993 /**
4994 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4995 * for later use.
4996 */
4997 static void preload_ring_buffers(struct si_shader_context *ctx)
4998 {
4999 LLVMBuilderRef builder = ctx->ac.builder;
5000
5001 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5002 ctx->param_rw_buffers);
5003
5004 if (ctx->screen->info.chip_class <= VI &&
5005 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
5006 unsigned ring =
5007 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5008 : SI_ES_RING_ESGS;
5009 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
5010
5011 ctx->esgs_ring =
5012 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5013 }
5014
5015 if (ctx->shader->is_gs_copy_shader) {
5016 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5017
5018 ctx->gsvs_ring[0] =
5019 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5020 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5021 const struct si_shader_selector *sel = ctx->shader->selector;
5022 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5023 LLVMValueRef base_ring;
5024
5025 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5026
5027 /* The conceptual layout of the GSVS ring is
5028 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5029 * but the real memory layout is swizzled across
5030 * threads:
5031 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5032 * t16v0c0 ..
5033 * Override the buffer descriptor accordingly.
5034 */
5035 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5036 uint64_t stream_offset = 0;
5037
5038 for (unsigned stream = 0; stream < 4; ++stream) {
5039 unsigned num_components;
5040 unsigned stride;
5041 unsigned num_records;
5042 LLVMValueRef ring, tmp;
5043
5044 num_components = sel->info.num_stream_output_components[stream];
5045 if (!num_components)
5046 continue;
5047
5048 stride = 4 * num_components * sel->gs_max_out_vertices;
5049
5050 /* Limit on the stride field for <= CIK. */
5051 assert(stride < (1 << 14));
5052
5053 num_records = 64;
5054
5055 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5056 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
5057 tmp = LLVMBuildAdd(builder, tmp,
5058 LLVMConstInt(ctx->i64,
5059 stream_offset, 0), "");
5060 stream_offset += stride * 64;
5061
5062 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5063 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5064 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5065 tmp = LLVMBuildOr(builder, tmp,
5066 LLVMConstInt(ctx->i32,
5067 S_008F04_STRIDE(stride) |
5068 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5069 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5070 ring = LLVMBuildInsertElement(builder, ring,
5071 LLVMConstInt(ctx->i32, num_records, 0),
5072 LLVMConstInt(ctx->i32, 2, 0), "");
5073 ring = LLVMBuildInsertElement(builder, ring,
5074 LLVMConstInt(ctx->i32,
5075 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5076 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5077 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5078 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5079 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5080 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5081 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5082 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5083 S_008F0C_ADD_TID_ENABLE(1),
5084 0),
5085 LLVMConstInt(ctx->i32, 3, 0), "");
5086
5087 ctx->gsvs_ring[stream] = ring;
5088 }
5089 }
5090 }
5091
5092 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5093 LLVMValueRef param_rw_buffers,
5094 unsigned param_pos_fixed_pt)
5095 {
5096 LLVMBuilderRef builder = ctx->ac.builder;
5097 LLVMValueRef slot, desc, offset, row, bit, address[2];
5098
5099 /* Use the fixed-point gl_FragCoord input.
5100 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5101 * per coordinate to get the repeating effect.
5102 */
5103 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5104 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5105
5106 /* Load the buffer descriptor. */
5107 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5108 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
5109
5110 /* The stipple pattern is 32x32, each row has 32 bits. */
5111 offset = LLVMBuildMul(builder, address[1],
5112 LLVMConstInt(ctx->i32, 4, 0), "");
5113 row = buffer_load_const(ctx, desc, offset);
5114 row = ac_to_integer(&ctx->ac, row);
5115 bit = LLVMBuildLShr(builder, row, address[0], "");
5116 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5117 ac_build_kill_if_false(&ctx->ac, bit);
5118 }
5119
5120 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5121 struct si_shader_config *conf,
5122 unsigned symbol_offset)
5123 {
5124 unsigned i;
5125 const unsigned char *config =
5126 ac_shader_binary_config_start(binary, symbol_offset);
5127 bool really_needs_scratch = false;
5128
5129 /* LLVM adds SGPR spills to the scratch size.
5130 * Find out if we really need the scratch buffer.
5131 */
5132 for (i = 0; i < binary->reloc_count; i++) {
5133 const struct ac_shader_reloc *reloc = &binary->relocs[i];
5134
5135 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5136 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5137 really_needs_scratch = true;
5138 break;
5139 }
5140 }
5141
5142 /* XXX: We may be able to emit some of these values directly rather than
5143 * extracting fields to be emitted later.
5144 */
5145
5146 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5147 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5148 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5149 switch (reg) {
5150 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5151 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5152 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5153 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
5154 case R_00B848_COMPUTE_PGM_RSRC1:
5155 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5156 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5157 conf->float_mode = G_00B028_FLOAT_MODE(value);
5158 conf->rsrc1 = value;
5159 break;
5160 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5161 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5162 break;
5163 case R_00B84C_COMPUTE_PGM_RSRC2:
5164 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5165 conf->rsrc2 = value;
5166 break;
5167 case R_0286CC_SPI_PS_INPUT_ENA:
5168 conf->spi_ps_input_ena = value;
5169 break;
5170 case R_0286D0_SPI_PS_INPUT_ADDR:
5171 conf->spi_ps_input_addr = value;
5172 break;
5173 case R_0286E8_SPI_TMPRING_SIZE:
5174 case R_00B860_COMPUTE_TMPRING_SIZE:
5175 /* WAVESIZE is in units of 256 dwords. */
5176 if (really_needs_scratch)
5177 conf->scratch_bytes_per_wave =
5178 G_00B860_WAVESIZE(value) * 256 * 4;
5179 break;
5180 case 0x4: /* SPILLED_SGPRS */
5181 conf->spilled_sgprs = value;
5182 break;
5183 case 0x8: /* SPILLED_VGPRS */
5184 conf->spilled_vgprs = value;
5185 break;
5186 default:
5187 {
5188 static bool printed;
5189
5190 if (!printed) {
5191 fprintf(stderr, "Warning: LLVM emitted unknown "
5192 "config register: 0x%x\n", reg);
5193 printed = true;
5194 }
5195 }
5196 break;
5197 }
5198 }
5199
5200 if (!conf->spi_ps_input_addr)
5201 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5202 }
5203
5204 void si_shader_apply_scratch_relocs(struct si_shader *shader,
5205 uint64_t scratch_va)
5206 {
5207 unsigned i;
5208 uint32_t scratch_rsrc_dword0 = scratch_va;
5209 uint32_t scratch_rsrc_dword1 =
5210 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5211
5212 /* Enable scratch coalescing. */
5213 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5214
5215 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5216 const struct ac_shader_reloc *reloc =
5217 &shader->binary.relocs[i];
5218 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5219 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5220 &scratch_rsrc_dword0, 4);
5221 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5222 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5223 &scratch_rsrc_dword1, 4);
5224 }
5225 }
5226 }
5227
5228 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
5229 {
5230 unsigned size = shader->binary.code_size;
5231
5232 if (shader->prolog)
5233 size += shader->prolog->binary.code_size;
5234 if (shader->previous_stage)
5235 size += shader->previous_stage->binary.code_size;
5236 if (shader->prolog2)
5237 size += shader->prolog2->binary.code_size;
5238 if (shader->epilog)
5239 size += shader->epilog->binary.code_size;
5240 return size;
5241 }
5242
5243 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5244 {
5245 const struct ac_shader_binary *prolog =
5246 shader->prolog ? &shader->prolog->binary : NULL;
5247 const struct ac_shader_binary *previous_stage =
5248 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5249 const struct ac_shader_binary *prolog2 =
5250 shader->prolog2 ? &shader->prolog2->binary : NULL;
5251 const struct ac_shader_binary *epilog =
5252 shader->epilog ? &shader->epilog->binary : NULL;
5253 const struct ac_shader_binary *mainb = &shader->binary;
5254 unsigned bo_size = si_get_shader_binary_size(shader) +
5255 (!epilog ? mainb->rodata_size : 0);
5256 unsigned char *ptr;
5257
5258 assert(!prolog || !prolog->rodata_size);
5259 assert(!previous_stage || !previous_stage->rodata_size);
5260 assert(!prolog2 || !prolog2->rodata_size);
5261 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5262 !mainb->rodata_size);
5263 assert(!epilog || !epilog->rodata_size);
5264
5265 r600_resource_reference(&shader->bo, NULL);
5266 shader->bo = (struct r600_resource*)
5267 si_aligned_buffer_create(&sscreen->b,
5268 sscreen->cpdma_prefetch_writes_memory ?
5269 0 : R600_RESOURCE_FLAG_READ_ONLY,
5270 PIPE_USAGE_IMMUTABLE,
5271 align(bo_size, SI_CPDMA_ALIGNMENT),
5272 256);
5273 if (!shader->bo)
5274 return -ENOMEM;
5275
5276 /* Upload. */
5277 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5278 PIPE_TRANSFER_READ_WRITE |
5279 PIPE_TRANSFER_UNSYNCHRONIZED);
5280
5281 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5282 * endian-independent. */
5283 if (prolog) {
5284 memcpy(ptr, prolog->code, prolog->code_size);
5285 ptr += prolog->code_size;
5286 }
5287 if (previous_stage) {
5288 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5289 ptr += previous_stage->code_size;
5290 }
5291 if (prolog2) {
5292 memcpy(ptr, prolog2->code, prolog2->code_size);
5293 ptr += prolog2->code_size;
5294 }
5295
5296 memcpy(ptr, mainb->code, mainb->code_size);
5297 ptr += mainb->code_size;
5298
5299 if (epilog)
5300 memcpy(ptr, epilog->code, epilog->code_size);
5301 else if (mainb->rodata_size > 0)
5302 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5303
5304 sscreen->ws->buffer_unmap(shader->bo->buf);
5305 return 0;
5306 }
5307
5308 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5309 struct pipe_debug_callback *debug,
5310 const char *name, FILE *file)
5311 {
5312 char *line, *p;
5313 unsigned i, count;
5314
5315 if (binary->disasm_string) {
5316 fprintf(file, "Shader %s disassembly:\n", name);
5317 fprintf(file, "%s", binary->disasm_string);
5318
5319 if (debug && debug->debug_message) {
5320 /* Very long debug messages are cut off, so send the
5321 * disassembly one line at a time. This causes more
5322 * overhead, but on the plus side it simplifies
5323 * parsing of resulting logs.
5324 */
5325 pipe_debug_message(debug, SHADER_INFO,
5326 "Shader Disassembly Begin");
5327
5328 line = binary->disasm_string;
5329 while (*line) {
5330 p = util_strchrnul(line, '\n');
5331 count = p - line;
5332
5333 if (count) {
5334 pipe_debug_message(debug, SHADER_INFO,
5335 "%.*s", count, line);
5336 }
5337
5338 if (!*p)
5339 break;
5340 line = p + 1;
5341 }
5342
5343 pipe_debug_message(debug, SHADER_INFO,
5344 "Shader Disassembly End");
5345 }
5346 } else {
5347 fprintf(file, "Shader %s binary:\n", name);
5348 for (i = 0; i < binary->code_size; i += 4) {
5349 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5350 binary->code[i + 3], binary->code[i + 2],
5351 binary->code[i + 1], binary->code[i]);
5352 }
5353 }
5354 }
5355
5356 static void si_shader_dump_stats(struct si_screen *sscreen,
5357 const struct si_shader *shader,
5358 struct pipe_debug_callback *debug,
5359 unsigned processor,
5360 FILE *file,
5361 bool check_debug_option)
5362 {
5363 const struct si_shader_config *conf = &shader->config;
5364 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
5365 unsigned code_size = si_get_shader_binary_size(shader);
5366 unsigned lds_increment = sscreen->info.chip_class >= CIK ? 512 : 256;
5367 unsigned lds_per_wave = 0;
5368 unsigned max_simd_waves;
5369
5370 switch (sscreen->info.family) {
5371 /* These always have 8 waves: */
5372 case CHIP_POLARIS10:
5373 case CHIP_POLARIS11:
5374 case CHIP_POLARIS12:
5375 max_simd_waves = 8;
5376 break;
5377 default:
5378 max_simd_waves = 10;
5379 }
5380
5381 /* Compute LDS usage for PS. */
5382 switch (processor) {
5383 case PIPE_SHADER_FRAGMENT:
5384 /* The minimum usage per wave is (num_inputs * 48). The maximum
5385 * usage is (num_inputs * 48 * 16).
5386 * We can get anything in between and it varies between waves.
5387 *
5388 * The 48 bytes per input for a single primitive is equal to
5389 * 4 bytes/component * 4 components/input * 3 points.
5390 *
5391 * Other stages don't know the size at compile time or don't
5392 * allocate LDS per wave, but instead they do it per thread group.
5393 */
5394 lds_per_wave = conf->lds_size * lds_increment +
5395 align(num_inputs * 48, lds_increment);
5396 break;
5397 case PIPE_SHADER_COMPUTE:
5398 if (shader->selector) {
5399 unsigned max_workgroup_size =
5400 si_get_max_workgroup_size(shader);
5401 lds_per_wave = (conf->lds_size * lds_increment) /
5402 DIV_ROUND_UP(max_workgroup_size, 64);
5403 }
5404 break;
5405 }
5406
5407 /* Compute the per-SIMD wave counts. */
5408 if (conf->num_sgprs) {
5409 if (sscreen->info.chip_class >= VI)
5410 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5411 else
5412 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5413 }
5414
5415 if (conf->num_vgprs)
5416 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5417
5418 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5419 * 16KB makes some SIMDs unoccupied). */
5420 if (lds_per_wave)
5421 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5422
5423 if (!check_debug_option ||
5424 si_can_dump_shader(sscreen, processor)) {
5425 if (processor == PIPE_SHADER_FRAGMENT) {
5426 fprintf(file, "*** SHADER CONFIG ***\n"
5427 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5428 "SPI_PS_INPUT_ENA = 0x%04x\n",
5429 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5430 }
5431
5432 fprintf(file, "*** SHADER STATS ***\n"
5433 "SGPRS: %d\n"
5434 "VGPRS: %d\n"
5435 "Spilled SGPRs: %d\n"
5436 "Spilled VGPRs: %d\n"
5437 "Private memory VGPRs: %d\n"
5438 "Code Size: %d bytes\n"
5439 "LDS: %d blocks\n"
5440 "Scratch: %d bytes per wave\n"
5441 "Max Waves: %d\n"
5442 "********************\n\n\n",
5443 conf->num_sgprs, conf->num_vgprs,
5444 conf->spilled_sgprs, conf->spilled_vgprs,
5445 conf->private_mem_vgprs, code_size,
5446 conf->lds_size, conf->scratch_bytes_per_wave,
5447 max_simd_waves);
5448 }
5449
5450 pipe_debug_message(debug, SHADER_INFO,
5451 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5452 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5453 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5454 conf->num_sgprs, conf->num_vgprs, code_size,
5455 conf->lds_size, conf->scratch_bytes_per_wave,
5456 max_simd_waves, conf->spilled_sgprs,
5457 conf->spilled_vgprs, conf->private_mem_vgprs);
5458 }
5459
5460 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5461 {
5462 switch (processor) {
5463 case PIPE_SHADER_VERTEX:
5464 if (shader->key.as_es)
5465 return "Vertex Shader as ES";
5466 else if (shader->key.as_ls)
5467 return "Vertex Shader as LS";
5468 else
5469 return "Vertex Shader as VS";
5470 case PIPE_SHADER_TESS_CTRL:
5471 return "Tessellation Control Shader";
5472 case PIPE_SHADER_TESS_EVAL:
5473 if (shader->key.as_es)
5474 return "Tessellation Evaluation Shader as ES";
5475 else
5476 return "Tessellation Evaluation Shader as VS";
5477 case PIPE_SHADER_GEOMETRY:
5478 if (shader->is_gs_copy_shader)
5479 return "GS Copy Shader as VS";
5480 else
5481 return "Geometry Shader";
5482 case PIPE_SHADER_FRAGMENT:
5483 return "Pixel Shader";
5484 case PIPE_SHADER_COMPUTE:
5485 return "Compute Shader";
5486 default:
5487 return "Unknown Shader";
5488 }
5489 }
5490
5491 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5492 struct pipe_debug_callback *debug, unsigned processor,
5493 FILE *file, bool check_debug_option)
5494 {
5495 if (!check_debug_option ||
5496 si_can_dump_shader(sscreen, processor))
5497 si_dump_shader_key(processor, shader, file);
5498
5499 if (!check_debug_option && shader->binary.llvm_ir_string) {
5500 if (shader->previous_stage &&
5501 shader->previous_stage->binary.llvm_ir_string) {
5502 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5503 si_get_shader_name(shader, processor));
5504 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5505 }
5506
5507 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5508 si_get_shader_name(shader, processor));
5509 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5510 }
5511
5512 if (!check_debug_option ||
5513 (si_can_dump_shader(sscreen, processor) &&
5514 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5515 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5516
5517 if (shader->prolog)
5518 si_shader_dump_disassembly(&shader->prolog->binary,
5519 debug, "prolog", file);
5520 if (shader->previous_stage)
5521 si_shader_dump_disassembly(&shader->previous_stage->binary,
5522 debug, "previous stage", file);
5523 if (shader->prolog2)
5524 si_shader_dump_disassembly(&shader->prolog2->binary,
5525 debug, "prolog2", file);
5526
5527 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5528
5529 if (shader->epilog)
5530 si_shader_dump_disassembly(&shader->epilog->binary,
5531 debug, "epilog", file);
5532 fprintf(file, "\n");
5533 }
5534
5535 si_shader_dump_stats(sscreen, shader, debug, processor, file,
5536 check_debug_option);
5537 }
5538
5539 static int si_compile_llvm(struct si_screen *sscreen,
5540 struct ac_shader_binary *binary,
5541 struct si_shader_config *conf,
5542 LLVMTargetMachineRef tm,
5543 LLVMModuleRef mod,
5544 struct pipe_debug_callback *debug,
5545 unsigned processor,
5546 const char *name)
5547 {
5548 int r = 0;
5549 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5550
5551 if (si_can_dump_shader(sscreen, processor)) {
5552 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5553
5554 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5555 fprintf(stderr, "%s LLVM IR:\n\n", name);
5556 ac_dump_module(mod);
5557 fprintf(stderr, "\n");
5558 }
5559 }
5560
5561 if (sscreen->record_llvm_ir) {
5562 char *ir = LLVMPrintModuleToString(mod);
5563 binary->llvm_ir_string = strdup(ir);
5564 LLVMDisposeMessage(ir);
5565 }
5566
5567 if (!si_replace_shader(count, binary)) {
5568 r = si_llvm_compile(mod, binary, tm, debug);
5569 if (r)
5570 return r;
5571 }
5572
5573 si_shader_binary_read_config(binary, conf, 0);
5574
5575 /* Enable 64-bit and 16-bit denormals, because there is no performance
5576 * cost.
5577 *
5578 * If denormals are enabled, all floating-point output modifiers are
5579 * ignored.
5580 *
5581 * Don't enable denormals for 32-bit floats, because:
5582 * - Floating-point output modifiers would be ignored by the hw.
5583 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5584 * have to stop using those.
5585 * - SI & CI would be very slow.
5586 */
5587 conf->float_mode |= V_00B028_FP_64_DENORMS;
5588
5589 FREE(binary->config);
5590 FREE(binary->global_symbol_offsets);
5591 binary->config = NULL;
5592 binary->global_symbol_offsets = NULL;
5593
5594 /* Some shaders can't have rodata because their binaries can be
5595 * concatenated.
5596 */
5597 if (binary->rodata_size &&
5598 (processor == PIPE_SHADER_VERTEX ||
5599 processor == PIPE_SHADER_TESS_CTRL ||
5600 processor == PIPE_SHADER_TESS_EVAL ||
5601 processor == PIPE_SHADER_FRAGMENT)) {
5602 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5603 return -EINVAL;
5604 }
5605
5606 return r;
5607 }
5608
5609 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5610 {
5611 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5612 LLVMBuildRetVoid(ctx->ac.builder);
5613 else
5614 LLVMBuildRet(ctx->ac.builder, ret);
5615 }
5616
5617 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5618 struct si_shader *
5619 si_generate_gs_copy_shader(struct si_screen *sscreen,
5620 LLVMTargetMachineRef tm,
5621 struct si_shader_selector *gs_selector,
5622 struct pipe_debug_callback *debug)
5623 {
5624 struct si_shader_context ctx;
5625 struct si_shader *shader;
5626 LLVMBuilderRef builder;
5627 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
5628 struct lp_build_context *uint = &bld_base->uint_bld;
5629 struct si_shader_output_values *outputs;
5630 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5631 int i, r;
5632
5633 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5634
5635 if (!outputs)
5636 return NULL;
5637
5638 shader = CALLOC_STRUCT(si_shader);
5639 if (!shader) {
5640 FREE(outputs);
5641 return NULL;
5642 }
5643
5644 /* We can leave the fence as permanently signaled because the GS copy
5645 * shader only becomes visible globally after it has been compiled. */
5646 util_queue_fence_init(&shader->ready);
5647
5648 shader->selector = gs_selector;
5649 shader->is_gs_copy_shader = true;
5650
5651 si_init_shader_ctx(&ctx, sscreen, tm);
5652 ctx.shader = shader;
5653 ctx.type = PIPE_SHADER_VERTEX;
5654
5655 builder = ctx.ac.builder;
5656
5657 create_function(&ctx);
5658 preload_ring_buffers(&ctx);
5659
5660 LLVMValueRef voffset =
5661 lp_build_mul_imm(uint, ctx.abi.vertex_id, 4);
5662
5663 /* Fetch the vertex stream ID.*/
5664 LLVMValueRef stream_id;
5665
5666 if (gs_selector->so.num_outputs)
5667 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5668 else
5669 stream_id = ctx.i32_0;
5670
5671 /* Fill in output information. */
5672 for (i = 0; i < gsinfo->num_outputs; ++i) {
5673 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5674 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5675
5676 for (int chan = 0; chan < 4; chan++) {
5677 outputs[i].vertex_stream[chan] =
5678 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5679 }
5680 }
5681
5682 LLVMBasicBlockRef end_bb;
5683 LLVMValueRef switch_inst;
5684
5685 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5686 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5687
5688 for (int stream = 0; stream < 4; stream++) {
5689 LLVMBasicBlockRef bb;
5690 unsigned offset;
5691
5692 if (!gsinfo->num_stream_output_components[stream])
5693 continue;
5694
5695 if (stream > 0 && !gs_selector->so.num_outputs)
5696 continue;
5697
5698 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5699 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5700 LLVMPositionBuilderAtEnd(builder, bb);
5701
5702 /* Fetch vertex data from GSVS ring */
5703 offset = 0;
5704 for (i = 0; i < gsinfo->num_outputs; ++i) {
5705 for (unsigned chan = 0; chan < 4; chan++) {
5706 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5707 outputs[i].vertex_stream[chan] != stream) {
5708 outputs[i].values[chan] = ctx.bld_base.base.undef;
5709 continue;
5710 }
5711
5712 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5713 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5714 offset++;
5715
5716 outputs[i].values[chan] =
5717 ac_build_buffer_load(&ctx.ac,
5718 ctx.gsvs_ring[0], 1,
5719 ctx.i32_0, voffset,
5720 soffset, 0, 1, 1,
5721 true, false);
5722 }
5723 }
5724
5725 /* Streamout and exports. */
5726 if (gs_selector->so.num_outputs) {
5727 si_llvm_emit_streamout(&ctx, outputs,
5728 gsinfo->num_outputs,
5729 stream);
5730 }
5731
5732 if (stream == 0)
5733 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5734
5735 LLVMBuildBr(builder, end_bb);
5736 }
5737
5738 LLVMPositionBuilderAtEnd(builder, end_bb);
5739
5740 LLVMBuildRetVoid(ctx.ac.builder);
5741
5742 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5743 si_llvm_optimize_module(&ctx);
5744
5745 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5746 &ctx.shader->config, ctx.tm,
5747 ctx.gallivm.module,
5748 debug, PIPE_SHADER_GEOMETRY,
5749 "GS Copy Shader");
5750 if (!r) {
5751 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5752 fprintf(stderr, "GS Copy Shader:\n");
5753 si_shader_dump(sscreen, ctx.shader, debug,
5754 PIPE_SHADER_GEOMETRY, stderr, true);
5755 r = si_shader_binary_upload(sscreen, ctx.shader);
5756 }
5757
5758 si_llvm_dispose(&ctx);
5759
5760 FREE(outputs);
5761
5762 if (r != 0) {
5763 FREE(shader);
5764 shader = NULL;
5765 }
5766 return shader;
5767 }
5768
5769 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5770 const struct si_vs_prolog_bits *prolog,
5771 const char *prefix, FILE *f)
5772 {
5773 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5774 prefix, prolog->instance_divisor_is_one);
5775 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5776 prefix, prolog->instance_divisor_is_fetched);
5777 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5778 prefix, prolog->ls_vgpr_fix);
5779
5780 fprintf(f, " mono.vs.fix_fetch = {");
5781 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5782 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5783 fprintf(f, "}\n");
5784 }
5785
5786 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5787 FILE *f)
5788 {
5789 const struct si_shader_key *key = &shader->key;
5790
5791 fprintf(f, "SHADER KEY\n");
5792
5793 switch (processor) {
5794 case PIPE_SHADER_VERTEX:
5795 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5796 "part.vs.prolog", f);
5797 fprintf(f, " as_es = %u\n", key->as_es);
5798 fprintf(f, " as_ls = %u\n", key->as_ls);
5799 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5800 key->mono.u.vs_export_prim_id);
5801 break;
5802
5803 case PIPE_SHADER_TESS_CTRL:
5804 if (shader->selector->screen->info.chip_class >= GFX9) {
5805 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5806 "part.tcs.ls_prolog", f);
5807 }
5808 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5809 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5810 break;
5811
5812 case PIPE_SHADER_TESS_EVAL:
5813 fprintf(f, " as_es = %u\n", key->as_es);
5814 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5815 key->mono.u.vs_export_prim_id);
5816 break;
5817
5818 case PIPE_SHADER_GEOMETRY:
5819 if (shader->is_gs_copy_shader)
5820 break;
5821
5822 if (shader->selector->screen->info.chip_class >= GFX9 &&
5823 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5824 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5825 "part.gs.vs_prolog", f);
5826 }
5827 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5828 break;
5829
5830 case PIPE_SHADER_COMPUTE:
5831 break;
5832
5833 case PIPE_SHADER_FRAGMENT:
5834 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5835 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5836 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5837 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5838 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5839 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5840 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5841 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5842 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5843 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5844 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5845 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5846 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5847 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5848 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5849 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5850 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5851 break;
5852
5853 default:
5854 assert(0);
5855 }
5856
5857 if ((processor == PIPE_SHADER_GEOMETRY ||
5858 processor == PIPE_SHADER_TESS_EVAL ||
5859 processor == PIPE_SHADER_VERTEX) &&
5860 !key->as_es && !key->as_ls) {
5861 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5862 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5863 }
5864 }
5865
5866 static void si_init_shader_ctx(struct si_shader_context *ctx,
5867 struct si_screen *sscreen,
5868 LLVMTargetMachineRef tm)
5869 {
5870 struct lp_build_tgsi_context *bld_base;
5871
5872 si_llvm_context_init(ctx, sscreen, tm);
5873
5874 bld_base = &ctx->bld_base;
5875 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5876
5877 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5878 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5879 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5880
5881 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5882
5883 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5884
5885 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5886 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5887 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5888 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5889
5890 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5891 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5892 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5893 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5894 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5895 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5896 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5897 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
5898 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5899
5900 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5901 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
5902 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5903 }
5904
5905 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5906 {
5907 struct si_shader *shader = ctx->shader;
5908 struct tgsi_shader_info *info = &shader->selector->info;
5909
5910 if ((ctx->type != PIPE_SHADER_VERTEX &&
5911 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5912 shader->key.as_ls ||
5913 shader->key.as_es)
5914 return;
5915
5916 ac_optimize_vs_outputs(&ctx->ac,
5917 ctx->main_fn,
5918 shader->info.vs_output_param_offset,
5919 info->num_outputs,
5920 &shader->info.nr_param_exports);
5921 }
5922
5923 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
5924 {
5925 ctx->shader->config.private_mem_vgprs = 0;
5926
5927 /* Process all LLVM instructions. */
5928 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
5929 while (bb) {
5930 LLVMValueRef next = LLVMGetFirstInstruction(bb);
5931
5932 while (next) {
5933 LLVMValueRef inst = next;
5934 next = LLVMGetNextInstruction(next);
5935
5936 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
5937 continue;
5938
5939 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
5940 /* No idea why LLVM aligns allocas to 4 elements. */
5941 unsigned alignment = LLVMGetAlignment(inst);
5942 unsigned dw_size = align(ac_get_type_size(type) / 4, alignment);
5943 ctx->shader->config.private_mem_vgprs += dw_size;
5944 }
5945 bb = LLVMGetNextBasicBlock(bb);
5946 }
5947 }
5948
5949 static void si_init_exec_from_input(struct si_shader_context *ctx,
5950 unsigned param, unsigned bitoffset)
5951 {
5952 LLVMValueRef args[] = {
5953 LLVMGetParam(ctx->main_fn, param),
5954 LLVMConstInt(ctx->i32, bitoffset, 0),
5955 };
5956 lp_build_intrinsic(ctx->ac.builder,
5957 "llvm.amdgcn.init.exec.from.input",
5958 ctx->voidt, args, 2, LP_FUNC_ATTR_CONVERGENT);
5959 }
5960
5961 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
5962 const struct si_vs_prolog_bits *key)
5963 {
5964 /* VGPR initialization fixup for Vega10 and Raven is always done in the
5965 * VS prolog. */
5966 return sel->vs_needs_prolog || key->ls_vgpr_fix;
5967 }
5968
5969 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
5970 bool is_monolithic)
5971 {
5972 struct si_shader *shader = ctx->shader;
5973 struct si_shader_selector *sel = shader->selector;
5974 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5975
5976 // TODO clean all this up!
5977 switch (ctx->type) {
5978 case PIPE_SHADER_VERTEX:
5979 ctx->load_input = declare_input_vs;
5980 if (shader->key.as_ls)
5981 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
5982 else if (shader->key.as_es)
5983 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5984 else
5985 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5986 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5987 break;
5988 case PIPE_SHADER_TESS_CTRL:
5989 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5990 ctx->abi.load_tess_inputs = si_nir_load_input_tcs;
5991 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5992 bld_base->emit_store = store_output_tcs;
5993 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
5994 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
5995 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
5996 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5997 break;
5998 case PIPE_SHADER_TESS_EVAL:
5999 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6000 ctx->abi.load_tess_inputs = si_nir_load_input_tes;
6001 ctx->abi.load_tess_coord = si_load_tess_coord;
6002 ctx->abi.load_tess_level = si_load_tess_level;
6003 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6004 if (shader->key.as_es)
6005 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6006 else
6007 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6008 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6009 break;
6010 case PIPE_SHADER_GEOMETRY:
6011 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6012 ctx->abi.load_inputs = si_nir_load_input_gs;
6013 ctx->abi.emit_vertex = si_llvm_emit_vertex;
6014 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
6015 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
6016 break;
6017 case PIPE_SHADER_FRAGMENT:
6018 ctx->load_input = declare_input_fs;
6019 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
6020 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6021 break;
6022 case PIPE_SHADER_COMPUTE:
6023 break;
6024 default:
6025 assert(!"Unsupported shader type");
6026 return false;
6027 }
6028
6029 ctx->abi.load_ubo = load_ubo;
6030 ctx->abi.load_ssbo = load_ssbo;
6031
6032 create_function(ctx);
6033 preload_ring_buffers(ctx);
6034
6035 /* For GFX9 merged shaders:
6036 * - Set EXEC for the first shader. If the prolog is present, set
6037 * EXEC there instead.
6038 * - Add a barrier before the second shader.
6039 * - In the second shader, reset EXEC to ~0 and wrap the main part in
6040 * an if-statement. This is required for correctness in geometry
6041 * shaders, to ensure that empty GS waves do not send GS_EMIT and
6042 * GS_CUT messages.
6043 *
6044 * For monolithic merged shaders, the first shader is wrapped in an
6045 * if-block together with its prolog in si_build_wrapper_function.
6046 */
6047 if (ctx->screen->info.chip_class >= GFX9) {
6048 if (!is_monolithic &&
6049 sel->info.num_instructions > 1 && /* not empty shader */
6050 (shader->key.as_es || shader->key.as_ls) &&
6051 (ctx->type == PIPE_SHADER_TESS_EVAL ||
6052 (ctx->type == PIPE_SHADER_VERTEX &&
6053 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
6054 si_init_exec_from_input(ctx,
6055 ctx->param_merged_wave_info, 0);
6056 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6057 ctx->type == PIPE_SHADER_GEOMETRY) {
6058 if (!is_monolithic)
6059 ac_init_exec_full_mask(&ctx->ac);
6060
6061 /* The barrier must execute for all shaders in a
6062 * threadgroup.
6063 */
6064 si_llvm_emit_barrier(NULL, bld_base, NULL);
6065
6066 LLVMValueRef num_threads = unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
6067 LLVMValueRef ena =
6068 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
6069 ac_get_thread_id(&ctx->ac), num_threads, "");
6070 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
6071 }
6072 }
6073
6074 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
6075 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
6076 for (unsigned i = 0; i < 6; i++) {
6077 ctx->invoc0_tess_factors[i] =
6078 lp_build_alloca_undef(&ctx->gallivm, ctx->i32, "");
6079 }
6080 }
6081
6082 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6083 int i;
6084 for (i = 0; i < 4; i++) {
6085 ctx->gs_next_vertex[i] =
6086 lp_build_alloca(&ctx->gallivm,
6087 ctx->i32, "");
6088 }
6089 }
6090
6091 if (sel->force_correct_derivs_after_kill) {
6092 ctx->postponed_kill = lp_build_alloca_undef(&ctx->gallivm, ctx->i1, "");
6093 /* true = don't kill. */
6094 LLVMBuildStore(ctx->ac.builder, LLVMConstInt(ctx->i1, 1, 0),
6095 ctx->postponed_kill);
6096 }
6097
6098 if (sel->tokens) {
6099 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6100 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6101 return false;
6102 }
6103 } else {
6104 if (!si_nir_build_llvm(ctx, sel->nir)) {
6105 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
6106 return false;
6107 }
6108 }
6109
6110 si_llvm_build_ret(ctx, ctx->return_value);
6111 return true;
6112 }
6113
6114 /**
6115 * Compute the VS prolog key, which contains all the information needed to
6116 * build the VS prolog function, and set shader->info bits where needed.
6117 *
6118 * \param info Shader info of the vertex shader.
6119 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6120 * \param prolog_key Key of the VS prolog
6121 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6122 * \param key Output shader part key.
6123 */
6124 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
6125 unsigned num_input_sgprs,
6126 const struct si_vs_prolog_bits *prolog_key,
6127 struct si_shader *shader_out,
6128 union si_shader_part_key *key)
6129 {
6130 memset(key, 0, sizeof(*key));
6131 key->vs_prolog.states = *prolog_key;
6132 key->vs_prolog.num_input_sgprs = num_input_sgprs;
6133 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6134 key->vs_prolog.as_ls = shader_out->key.as_ls;
6135 key->vs_prolog.as_es = shader_out->key.as_es;
6136
6137 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
6138 key->vs_prolog.as_ls = 1;
6139 key->vs_prolog.num_merged_next_stage_vgprs = 2;
6140 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
6141 key->vs_prolog.as_es = 1;
6142 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6143 }
6144
6145 /* Enable loading the InstanceID VGPR. */
6146 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
6147
6148 if ((key->vs_prolog.states.instance_divisor_is_one |
6149 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
6150 shader_out->info.uses_instanceid = true;
6151 }
6152
6153 /**
6154 * Compute the PS prolog key, which contains all the information needed to
6155 * build the PS prolog function, and set related bits in shader->config.
6156 */
6157 static void si_get_ps_prolog_key(struct si_shader *shader,
6158 union si_shader_part_key *key,
6159 bool separate_prolog)
6160 {
6161 struct tgsi_shader_info *info = &shader->selector->info;
6162
6163 memset(key, 0, sizeof(*key));
6164 key->ps_prolog.states = shader->key.part.ps.prolog;
6165 key->ps_prolog.colors_read = info->colors_read;
6166 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6167 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6168 key->ps_prolog.wqm = info->uses_derivatives &&
6169 (key->ps_prolog.colors_read ||
6170 key->ps_prolog.states.force_persp_sample_interp ||
6171 key->ps_prolog.states.force_linear_sample_interp ||
6172 key->ps_prolog.states.force_persp_center_interp ||
6173 key->ps_prolog.states.force_linear_center_interp ||
6174 key->ps_prolog.states.bc_optimize_for_persp ||
6175 key->ps_prolog.states.bc_optimize_for_linear);
6176 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
6177
6178 if (info->colors_read) {
6179 unsigned *color = shader->selector->color_attr_index;
6180
6181 if (shader->key.part.ps.prolog.color_two_side) {
6182 /* BCOLORs are stored after the last input. */
6183 key->ps_prolog.num_interp_inputs = info->num_inputs;
6184 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6185 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6186 }
6187
6188 for (unsigned i = 0; i < 2; i++) {
6189 unsigned interp = info->input_interpolate[color[i]];
6190 unsigned location = info->input_interpolate_loc[color[i]];
6191
6192 if (!(info->colors_read & (0xf << i*4)))
6193 continue;
6194
6195 key->ps_prolog.color_attr_index[i] = color[i];
6196
6197 if (shader->key.part.ps.prolog.flatshade_colors &&
6198 interp == TGSI_INTERPOLATE_COLOR)
6199 interp = TGSI_INTERPOLATE_CONSTANT;
6200
6201 switch (interp) {
6202 case TGSI_INTERPOLATE_CONSTANT:
6203 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6204 break;
6205 case TGSI_INTERPOLATE_PERSPECTIVE:
6206 case TGSI_INTERPOLATE_COLOR:
6207 /* Force the interpolation location for colors here. */
6208 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6209 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6210 if (shader->key.part.ps.prolog.force_persp_center_interp)
6211 location = TGSI_INTERPOLATE_LOC_CENTER;
6212
6213 switch (location) {
6214 case TGSI_INTERPOLATE_LOC_SAMPLE:
6215 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6216 shader->config.spi_ps_input_ena |=
6217 S_0286CC_PERSP_SAMPLE_ENA(1);
6218 break;
6219 case TGSI_INTERPOLATE_LOC_CENTER:
6220 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6221 shader->config.spi_ps_input_ena |=
6222 S_0286CC_PERSP_CENTER_ENA(1);
6223 break;
6224 case TGSI_INTERPOLATE_LOC_CENTROID:
6225 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6226 shader->config.spi_ps_input_ena |=
6227 S_0286CC_PERSP_CENTROID_ENA(1);
6228 break;
6229 default:
6230 assert(0);
6231 }
6232 break;
6233 case TGSI_INTERPOLATE_LINEAR:
6234 /* Force the interpolation location for colors here. */
6235 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6236 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6237 if (shader->key.part.ps.prolog.force_linear_center_interp)
6238 location = TGSI_INTERPOLATE_LOC_CENTER;
6239
6240 /* The VGPR assignment for non-monolithic shaders
6241 * works because InitialPSInputAddr is set on the
6242 * main shader and PERSP_PULL_MODEL is never used.
6243 */
6244 switch (location) {
6245 case TGSI_INTERPOLATE_LOC_SAMPLE:
6246 key->ps_prolog.color_interp_vgpr_index[i] =
6247 separate_prolog ? 6 : 9;
6248 shader->config.spi_ps_input_ena |=
6249 S_0286CC_LINEAR_SAMPLE_ENA(1);
6250 break;
6251 case TGSI_INTERPOLATE_LOC_CENTER:
6252 key->ps_prolog.color_interp_vgpr_index[i] =
6253 separate_prolog ? 8 : 11;
6254 shader->config.spi_ps_input_ena |=
6255 S_0286CC_LINEAR_CENTER_ENA(1);
6256 break;
6257 case TGSI_INTERPOLATE_LOC_CENTROID:
6258 key->ps_prolog.color_interp_vgpr_index[i] =
6259 separate_prolog ? 10 : 13;
6260 shader->config.spi_ps_input_ena |=
6261 S_0286CC_LINEAR_CENTROID_ENA(1);
6262 break;
6263 default:
6264 assert(0);
6265 }
6266 break;
6267 default:
6268 assert(0);
6269 }
6270 }
6271 }
6272 }
6273
6274 /**
6275 * Check whether a PS prolog is required based on the key.
6276 */
6277 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6278 {
6279 return key->ps_prolog.colors_read ||
6280 key->ps_prolog.states.force_persp_sample_interp ||
6281 key->ps_prolog.states.force_linear_sample_interp ||
6282 key->ps_prolog.states.force_persp_center_interp ||
6283 key->ps_prolog.states.force_linear_center_interp ||
6284 key->ps_prolog.states.bc_optimize_for_persp ||
6285 key->ps_prolog.states.bc_optimize_for_linear ||
6286 key->ps_prolog.states.poly_stipple ||
6287 key->ps_prolog.states.samplemask_log_ps_iter;
6288 }
6289
6290 /**
6291 * Compute the PS epilog key, which contains all the information needed to
6292 * build the PS epilog function.
6293 */
6294 static void si_get_ps_epilog_key(struct si_shader *shader,
6295 union si_shader_part_key *key)
6296 {
6297 struct tgsi_shader_info *info = &shader->selector->info;
6298 memset(key, 0, sizeof(*key));
6299 key->ps_epilog.colors_written = info->colors_written;
6300 key->ps_epilog.writes_z = info->writes_z;
6301 key->ps_epilog.writes_stencil = info->writes_stencil;
6302 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6303 key->ps_epilog.states = shader->key.part.ps.epilog;
6304 }
6305
6306 /**
6307 * Build the GS prolog function. Rotate the input vertices for triangle strips
6308 * with adjacency.
6309 */
6310 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6311 union si_shader_part_key *key)
6312 {
6313 unsigned num_sgprs, num_vgprs;
6314 struct si_function_info fninfo;
6315 LLVMBuilderRef builder = ctx->ac.builder;
6316 LLVMTypeRef returns[48];
6317 LLVMValueRef func, ret;
6318
6319 si_init_function_info(&fninfo);
6320
6321 if (ctx->screen->info.chip_class >= GFX9) {
6322 num_sgprs = 8 + GFX9_GS_NUM_USER_SGPR;
6323 num_vgprs = 5; /* ES inputs are not needed by GS */
6324 } else {
6325 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6326 num_vgprs = 8;
6327 }
6328
6329 for (unsigned i = 0; i < num_sgprs; ++i) {
6330 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6331 returns[i] = ctx->i32;
6332 }
6333
6334 for (unsigned i = 0; i < num_vgprs; ++i) {
6335 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6336 returns[num_sgprs + i] = ctx->f32;
6337 }
6338
6339 /* Create the function. */
6340 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6341 &fninfo, 0);
6342 func = ctx->main_fn;
6343
6344 /* Set the full EXEC mask for the prolog, because we are only fiddling
6345 * with registers here. The main shader part will set the correct EXEC
6346 * mask.
6347 */
6348 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6349 ac_init_exec_full_mask(&ctx->ac);
6350
6351 /* Copy inputs to outputs. This should be no-op, as the registers match,
6352 * but it will prevent the compiler from overwriting them unintentionally.
6353 */
6354 ret = ctx->return_value;
6355 for (unsigned i = 0; i < num_sgprs; i++) {
6356 LLVMValueRef p = LLVMGetParam(func, i);
6357 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6358 }
6359 for (unsigned i = 0; i < num_vgprs; i++) {
6360 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6361 p = ac_to_float(&ctx->ac, p);
6362 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6363 }
6364
6365 if (key->gs_prolog.states.tri_strip_adj_fix) {
6366 /* Remap the input vertices for every other primitive. */
6367 const unsigned gfx6_vtx_params[6] = {
6368 num_sgprs,
6369 num_sgprs + 1,
6370 num_sgprs + 3,
6371 num_sgprs + 4,
6372 num_sgprs + 5,
6373 num_sgprs + 6
6374 };
6375 const unsigned gfx9_vtx_params[3] = {
6376 num_sgprs,
6377 num_sgprs + 1,
6378 num_sgprs + 4,
6379 };
6380 LLVMValueRef vtx_in[6], vtx_out[6];
6381 LLVMValueRef prim_id, rotate;
6382
6383 if (ctx->screen->info.chip_class >= GFX9) {
6384 for (unsigned i = 0; i < 3; i++) {
6385 vtx_in[i*2] = unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6386 vtx_in[i*2+1] = unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6387 }
6388 } else {
6389 for (unsigned i = 0; i < 6; i++)
6390 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6391 }
6392
6393 prim_id = LLVMGetParam(func, num_sgprs + 2);
6394 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6395
6396 for (unsigned i = 0; i < 6; ++i) {
6397 LLVMValueRef base, rotated;
6398 base = vtx_in[i];
6399 rotated = vtx_in[(i + 4) % 6];
6400 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6401 }
6402
6403 if (ctx->screen->info.chip_class >= GFX9) {
6404 for (unsigned i = 0; i < 3; i++) {
6405 LLVMValueRef hi, out;
6406
6407 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6408 LLVMConstInt(ctx->i32, 16, 0), "");
6409 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6410 out = ac_to_float(&ctx->ac, out);
6411 ret = LLVMBuildInsertValue(builder, ret, out,
6412 gfx9_vtx_params[i], "");
6413 }
6414 } else {
6415 for (unsigned i = 0; i < 6; i++) {
6416 LLVMValueRef out;
6417
6418 out = ac_to_float(&ctx->ac, vtx_out[i]);
6419 ret = LLVMBuildInsertValue(builder, ret, out,
6420 gfx6_vtx_params[i], "");
6421 }
6422 }
6423 }
6424
6425 LLVMBuildRet(builder, ret);
6426 }
6427
6428 /**
6429 * Given a list of shader part functions, build a wrapper function that
6430 * runs them in sequence to form a monolithic shader.
6431 */
6432 static void si_build_wrapper_function(struct si_shader_context *ctx,
6433 LLVMValueRef *parts,
6434 unsigned num_parts,
6435 unsigned main_part,
6436 unsigned next_shader_first_part)
6437 {
6438 LLVMBuilderRef builder = ctx->ac.builder;
6439 /* PS epilog has one arg per color component; gfx9 merged shader
6440 * prologs need to forward 32 user SGPRs.
6441 */
6442 struct si_function_info fninfo;
6443 LLVMValueRef initial[64], out[64];
6444 LLVMTypeRef function_type;
6445 unsigned num_first_params;
6446 unsigned num_out, initial_num_out;
6447 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6448 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6449 unsigned num_sgprs, num_vgprs;
6450 unsigned gprs;
6451 struct lp_build_if_state if_state;
6452
6453 si_init_function_info(&fninfo);
6454
6455 for (unsigned i = 0; i < num_parts; ++i) {
6456 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6457 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6458 }
6459
6460 /* The parameters of the wrapper function correspond to those of the
6461 * first part in terms of SGPRs and VGPRs, but we use the types of the
6462 * main part to get the right types. This is relevant for the
6463 * dereferenceable attribute on descriptor table pointers.
6464 */
6465 num_sgprs = 0;
6466 num_vgprs = 0;
6467
6468 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6469 num_first_params = LLVMCountParamTypes(function_type);
6470
6471 for (unsigned i = 0; i < num_first_params; ++i) {
6472 LLVMValueRef param = LLVMGetParam(parts[0], i);
6473
6474 if (ac_is_sgpr_param(param)) {
6475 assert(num_vgprs == 0);
6476 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6477 } else {
6478 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6479 }
6480 }
6481
6482 gprs = 0;
6483 while (gprs < num_sgprs + num_vgprs) {
6484 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6485 LLVMTypeRef type = LLVMTypeOf(param);
6486 unsigned size = ac_get_type_size(type) / 4;
6487
6488 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6489
6490 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6491 assert(gprs + size <= num_sgprs + num_vgprs &&
6492 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6493
6494 gprs += size;
6495 }
6496
6497 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6498 si_get_max_workgroup_size(ctx->shader));
6499
6500 if (is_merged_shader(ctx->shader))
6501 ac_init_exec_full_mask(&ctx->ac);
6502
6503 /* Record the arguments of the function as if they were an output of
6504 * a previous part.
6505 */
6506 num_out = 0;
6507 num_out_sgpr = 0;
6508
6509 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6510 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6511 LLVMTypeRef param_type = LLVMTypeOf(param);
6512 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6513 unsigned size = ac_get_type_size(param_type) / 4;
6514
6515 if (size == 1) {
6516 if (param_type != out_type)
6517 param = LLVMBuildBitCast(builder, param, out_type, "");
6518 out[num_out++] = param;
6519 } else {
6520 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6521
6522 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6523 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6524 param_type = ctx->i64;
6525 }
6526
6527 if (param_type != vector_type)
6528 param = LLVMBuildBitCast(builder, param, vector_type, "");
6529
6530 for (unsigned j = 0; j < size; ++j)
6531 out[num_out++] = LLVMBuildExtractElement(
6532 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6533 }
6534
6535 if (i < fninfo.num_sgpr_params)
6536 num_out_sgpr = num_out;
6537 }
6538
6539 memcpy(initial, out, sizeof(out));
6540 initial_num_out = num_out;
6541 initial_num_out_sgpr = num_out_sgpr;
6542
6543 /* Now chain the parts. */
6544 for (unsigned part = 0; part < num_parts; ++part) {
6545 LLVMValueRef in[48];
6546 LLVMValueRef ret;
6547 LLVMTypeRef ret_type;
6548 unsigned out_idx = 0;
6549 unsigned num_params = LLVMCountParams(parts[part]);
6550
6551 /* Merged shaders are executed conditionally depending
6552 * on the number of enabled threads passed in the input SGPRs. */
6553 if (is_merged_shader(ctx->shader) && part == 0) {
6554 LLVMValueRef ena, count = initial[3];
6555
6556 count = LLVMBuildAnd(builder, count,
6557 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6558 ena = LLVMBuildICmp(builder, LLVMIntULT,
6559 ac_get_thread_id(&ctx->ac), count, "");
6560 lp_build_if(&if_state, &ctx->gallivm, ena);
6561 }
6562
6563 /* Derive arguments for the next part from outputs of the
6564 * previous one.
6565 */
6566 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6567 LLVMValueRef param;
6568 LLVMTypeRef param_type;
6569 bool is_sgpr;
6570 unsigned param_size;
6571 LLVMValueRef arg = NULL;
6572
6573 param = LLVMGetParam(parts[part], param_idx);
6574 param_type = LLVMTypeOf(param);
6575 param_size = ac_get_type_size(param_type) / 4;
6576 is_sgpr = ac_is_sgpr_param(param);
6577
6578 if (is_sgpr) {
6579 #if HAVE_LLVM < 0x0400
6580 LLVMRemoveAttribute(param, LLVMByValAttribute);
6581 #else
6582 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
6583 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
6584 #endif
6585 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
6586 }
6587
6588 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6589 assert(is_sgpr || out_idx >= num_out_sgpr);
6590
6591 if (param_size == 1)
6592 arg = out[out_idx];
6593 else
6594 arg = lp_build_gather_values(&ctx->gallivm, &out[out_idx], param_size);
6595
6596 if (LLVMTypeOf(arg) != param_type) {
6597 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6598 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6599 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6600 } else {
6601 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6602 }
6603 }
6604
6605 in[param_idx] = arg;
6606 out_idx += param_size;
6607 }
6608
6609 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6610
6611 if (is_merged_shader(ctx->shader) &&
6612 part + 1 == next_shader_first_part) {
6613 lp_build_endif(&if_state);
6614
6615 /* The second half of the merged shader should use
6616 * the inputs from the toplevel (wrapper) function,
6617 * not the return value from the last call.
6618 *
6619 * That's because the last call was executed condi-
6620 * tionally, so we can't consume it in the main
6621 * block.
6622 */
6623 memcpy(out, initial, sizeof(initial));
6624 num_out = initial_num_out;
6625 num_out_sgpr = initial_num_out_sgpr;
6626 continue;
6627 }
6628
6629 /* Extract the returned GPRs. */
6630 ret_type = LLVMTypeOf(ret);
6631 num_out = 0;
6632 num_out_sgpr = 0;
6633
6634 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6635 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6636
6637 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6638
6639 for (unsigned i = 0; i < ret_size; ++i) {
6640 LLVMValueRef val =
6641 LLVMBuildExtractValue(builder, ret, i, "");
6642
6643 assert(num_out < ARRAY_SIZE(out));
6644 out[num_out++] = val;
6645
6646 if (LLVMTypeOf(val) == ctx->i32) {
6647 assert(num_out_sgpr + 1 == num_out);
6648 num_out_sgpr = num_out;
6649 }
6650 }
6651 }
6652 }
6653
6654 LLVMBuildRetVoid(builder);
6655 }
6656
6657 int si_compile_tgsi_shader(struct si_screen *sscreen,
6658 LLVMTargetMachineRef tm,
6659 struct si_shader *shader,
6660 bool is_monolithic,
6661 struct pipe_debug_callback *debug)
6662 {
6663 struct si_shader_selector *sel = shader->selector;
6664 struct si_shader_context ctx;
6665 int r = -1;
6666
6667 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6668 * conversion fails. */
6669 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6670 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6671 if (sel->tokens)
6672 tgsi_dump(sel->tokens, 0);
6673 else
6674 nir_print_shader(sel->nir, stderr);
6675 si_dump_streamout(&sel->so);
6676 }
6677
6678 si_init_shader_ctx(&ctx, sscreen, tm);
6679 si_llvm_context_set_tgsi(&ctx, shader);
6680 ctx.separate_prolog = !is_monolithic;
6681
6682 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6683 sizeof(shader->info.vs_output_param_offset));
6684
6685 shader->info.uses_instanceid = sel->info.uses_instanceid;
6686
6687 if (!si_compile_tgsi_main(&ctx, is_monolithic)) {
6688 si_llvm_dispose(&ctx);
6689 return -1;
6690 }
6691
6692 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6693 LLVMValueRef parts[2];
6694 bool need_prolog = sel->vs_needs_prolog;
6695
6696 parts[1] = ctx.main_fn;
6697
6698 if (need_prolog) {
6699 union si_shader_part_key prolog_key;
6700 si_get_vs_prolog_key(&sel->info,
6701 shader->info.num_input_sgprs,
6702 &shader->key.part.vs.prolog,
6703 shader, &prolog_key);
6704 si_build_vs_prolog_function(&ctx, &prolog_key);
6705 parts[0] = ctx.main_fn;
6706 }
6707
6708 si_build_wrapper_function(&ctx, parts + !need_prolog,
6709 1 + need_prolog, need_prolog, 0);
6710 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6711 if (sscreen->info.chip_class >= GFX9) {
6712 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6713 LLVMValueRef parts[4];
6714 bool vs_needs_prolog =
6715 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6716
6717 /* TCS main part */
6718 parts[2] = ctx.main_fn;
6719
6720 /* TCS epilog */
6721 union si_shader_part_key tcs_epilog_key;
6722 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6723 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6724 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6725 parts[3] = ctx.main_fn;
6726
6727 /* VS prolog */
6728 if (vs_needs_prolog) {
6729 union si_shader_part_key vs_prolog_key;
6730 si_get_vs_prolog_key(&ls->info,
6731 shader->info.num_input_sgprs,
6732 &shader->key.part.tcs.ls_prolog,
6733 shader, &vs_prolog_key);
6734 vs_prolog_key.vs_prolog.is_monolithic = true;
6735 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6736 parts[0] = ctx.main_fn;
6737 }
6738
6739 /* VS as LS main part */
6740 struct si_shader shader_ls = {};
6741 shader_ls.selector = ls;
6742 shader_ls.key.as_ls = 1;
6743 shader_ls.key.mono = shader->key.mono;
6744 shader_ls.key.opt = shader->key.opt;
6745 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6746
6747 if (!si_compile_tgsi_main(&ctx, true)) {
6748 si_llvm_dispose(&ctx);
6749 return -1;
6750 }
6751 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6752 parts[1] = ctx.main_fn;
6753
6754 /* Reset the shader context. */
6755 ctx.shader = shader;
6756 ctx.type = PIPE_SHADER_TESS_CTRL;
6757
6758 si_build_wrapper_function(&ctx,
6759 parts + !vs_needs_prolog,
6760 4 - !vs_needs_prolog, 0,
6761 vs_needs_prolog ? 2 : 1);
6762 } else {
6763 LLVMValueRef parts[2];
6764 union si_shader_part_key epilog_key;
6765
6766 parts[0] = ctx.main_fn;
6767
6768 memset(&epilog_key, 0, sizeof(epilog_key));
6769 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6770 si_build_tcs_epilog_function(&ctx, &epilog_key);
6771 parts[1] = ctx.main_fn;
6772
6773 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6774 }
6775 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6776 if (ctx.screen->info.chip_class >= GFX9) {
6777 struct si_shader_selector *es = shader->key.part.gs.es;
6778 LLVMValueRef es_prolog = NULL;
6779 LLVMValueRef es_main = NULL;
6780 LLVMValueRef gs_prolog = NULL;
6781 LLVMValueRef gs_main = ctx.main_fn;
6782
6783 /* GS prolog */
6784 union si_shader_part_key gs_prolog_key;
6785 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6786 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6787 gs_prolog_key.gs_prolog.is_monolithic = true;
6788 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6789 gs_prolog = ctx.main_fn;
6790
6791 /* ES prolog */
6792 if (es->vs_needs_prolog) {
6793 union si_shader_part_key vs_prolog_key;
6794 si_get_vs_prolog_key(&es->info,
6795 shader->info.num_input_sgprs,
6796 &shader->key.part.gs.vs_prolog,
6797 shader, &vs_prolog_key);
6798 vs_prolog_key.vs_prolog.is_monolithic = true;
6799 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6800 es_prolog = ctx.main_fn;
6801 }
6802
6803 /* ES main part */
6804 struct si_shader shader_es = {};
6805 shader_es.selector = es;
6806 shader_es.key.as_es = 1;
6807 shader_es.key.mono = shader->key.mono;
6808 shader_es.key.opt = shader->key.opt;
6809 si_llvm_context_set_tgsi(&ctx, &shader_es);
6810
6811 if (!si_compile_tgsi_main(&ctx, true)) {
6812 si_llvm_dispose(&ctx);
6813 return -1;
6814 }
6815 shader->info.uses_instanceid |= es->info.uses_instanceid;
6816 es_main = ctx.main_fn;
6817
6818 /* Reset the shader context. */
6819 ctx.shader = shader;
6820 ctx.type = PIPE_SHADER_GEOMETRY;
6821
6822 /* Prepare the array of shader parts. */
6823 LLVMValueRef parts[4];
6824 unsigned num_parts = 0, main_part, next_first_part;
6825
6826 if (es_prolog)
6827 parts[num_parts++] = es_prolog;
6828
6829 parts[main_part = num_parts++] = es_main;
6830 parts[next_first_part = num_parts++] = gs_prolog;
6831 parts[num_parts++] = gs_main;
6832
6833 si_build_wrapper_function(&ctx, parts, num_parts,
6834 main_part, next_first_part);
6835 } else {
6836 LLVMValueRef parts[2];
6837 union si_shader_part_key prolog_key;
6838
6839 parts[1] = ctx.main_fn;
6840
6841 memset(&prolog_key, 0, sizeof(prolog_key));
6842 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6843 si_build_gs_prolog_function(&ctx, &prolog_key);
6844 parts[0] = ctx.main_fn;
6845
6846 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6847 }
6848 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6849 LLVMValueRef parts[3];
6850 union si_shader_part_key prolog_key;
6851 union si_shader_part_key epilog_key;
6852 bool need_prolog;
6853
6854 si_get_ps_prolog_key(shader, &prolog_key, false);
6855 need_prolog = si_need_ps_prolog(&prolog_key);
6856
6857 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6858
6859 if (need_prolog) {
6860 si_build_ps_prolog_function(&ctx, &prolog_key);
6861 parts[0] = ctx.main_fn;
6862 }
6863
6864 si_get_ps_epilog_key(shader, &epilog_key);
6865 si_build_ps_epilog_function(&ctx, &epilog_key);
6866 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6867
6868 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6869 need_prolog ? 1 : 0, 0);
6870 }
6871
6872 si_llvm_optimize_module(&ctx);
6873
6874 /* Post-optimization transformations and analysis. */
6875 si_optimize_vs_outputs(&ctx);
6876
6877 if ((debug && debug->debug_message) ||
6878 si_can_dump_shader(sscreen, ctx.type))
6879 si_count_scratch_private_memory(&ctx);
6880
6881 /* Compile to bytecode. */
6882 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6883 ctx.gallivm.module, debug, ctx.type, "TGSI shader");
6884 si_llvm_dispose(&ctx);
6885 if (r) {
6886 fprintf(stderr, "LLVM failed to compile shader\n");
6887 return r;
6888 }
6889
6890 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6891 * LLVM 3.9svn has this bug.
6892 */
6893 if (sel->type == PIPE_SHADER_COMPUTE) {
6894 unsigned wave_size = 64;
6895 unsigned max_vgprs = 256;
6896 unsigned max_sgprs = sscreen->info.chip_class >= VI ? 800 : 512;
6897 unsigned max_sgprs_per_wave = 128;
6898 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6899 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6900 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6901
6902 max_vgprs = max_vgprs / min_waves_per_simd;
6903 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6904
6905 if (shader->config.num_sgprs > max_sgprs ||
6906 shader->config.num_vgprs > max_vgprs) {
6907 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6908 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6909 shader->config.num_sgprs, shader->config.num_vgprs,
6910 max_sgprs, max_vgprs);
6911
6912 /* Just terminate the process, because dependent
6913 * shaders can hang due to bad input data, but use
6914 * the env var to allow shader-db to work.
6915 */
6916 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6917 abort();
6918 }
6919 }
6920
6921 /* Add the scratch offset to input SGPRs. */
6922 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(shader))
6923 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6924
6925 /* Calculate the number of fragment input VGPRs. */
6926 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6927 shader->info.num_input_vgprs = 0;
6928 shader->info.face_vgpr_index = -1;
6929 shader->info.ancillary_vgpr_index = -1;
6930
6931 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6932 shader->info.num_input_vgprs += 2;
6933 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6934 shader->info.num_input_vgprs += 2;
6935 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6936 shader->info.num_input_vgprs += 2;
6937 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6938 shader->info.num_input_vgprs += 3;
6939 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6940 shader->info.num_input_vgprs += 2;
6941 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6942 shader->info.num_input_vgprs += 2;
6943 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6944 shader->info.num_input_vgprs += 2;
6945 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6946 shader->info.num_input_vgprs += 1;
6947 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6948 shader->info.num_input_vgprs += 1;
6949 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6950 shader->info.num_input_vgprs += 1;
6951 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6952 shader->info.num_input_vgprs += 1;
6953 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6954 shader->info.num_input_vgprs += 1;
6955 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6956 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6957 shader->info.num_input_vgprs += 1;
6958 }
6959 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
6960 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
6961 shader->info.num_input_vgprs += 1;
6962 }
6963 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6964 shader->info.num_input_vgprs += 1;
6965 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6966 shader->info.num_input_vgprs += 1;
6967 }
6968
6969 return 0;
6970 }
6971
6972 /**
6973 * Create, compile and return a shader part (prolog or epilog).
6974 *
6975 * \param sscreen screen
6976 * \param list list of shader parts of the same category
6977 * \param type shader type
6978 * \param key shader part key
6979 * \param prolog whether the part being requested is a prolog
6980 * \param tm LLVM target machine
6981 * \param debug debug callback
6982 * \param build the callback responsible for building the main function
6983 * \return non-NULL on success
6984 */
6985 static struct si_shader_part *
6986 si_get_shader_part(struct si_screen *sscreen,
6987 struct si_shader_part **list,
6988 enum pipe_shader_type type,
6989 bool prolog,
6990 union si_shader_part_key *key,
6991 LLVMTargetMachineRef tm,
6992 struct pipe_debug_callback *debug,
6993 void (*build)(struct si_shader_context *,
6994 union si_shader_part_key *),
6995 const char *name)
6996 {
6997 struct si_shader_part *result;
6998
6999 mtx_lock(&sscreen->shader_parts_mutex);
7000
7001 /* Find existing. */
7002 for (result = *list; result; result = result->next) {
7003 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7004 mtx_unlock(&sscreen->shader_parts_mutex);
7005 return result;
7006 }
7007 }
7008
7009 /* Compile a new one. */
7010 result = CALLOC_STRUCT(si_shader_part);
7011 result->key = *key;
7012
7013 struct si_shader shader = {};
7014 struct si_shader_context ctx;
7015
7016 si_init_shader_ctx(&ctx, sscreen, tm);
7017 ctx.shader = &shader;
7018 ctx.type = type;
7019
7020 switch (type) {
7021 case PIPE_SHADER_VERTEX:
7022 shader.key.as_ls = key->vs_prolog.as_ls;
7023 shader.key.as_es = key->vs_prolog.as_es;
7024 break;
7025 case PIPE_SHADER_TESS_CTRL:
7026 assert(!prolog);
7027 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7028 break;
7029 case PIPE_SHADER_GEOMETRY:
7030 assert(prolog);
7031 break;
7032 case PIPE_SHADER_FRAGMENT:
7033 if (prolog)
7034 shader.key.part.ps.prolog = key->ps_prolog.states;
7035 else
7036 shader.key.part.ps.epilog = key->ps_epilog.states;
7037 break;
7038 default:
7039 unreachable("bad shader part");
7040 }
7041
7042 build(&ctx, key);
7043
7044 /* Compile. */
7045 si_llvm_optimize_module(&ctx);
7046
7047 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7048 ctx.ac.module, debug, ctx.type, name)) {
7049 FREE(result);
7050 result = NULL;
7051 goto out;
7052 }
7053
7054 result->next = *list;
7055 *list = result;
7056
7057 out:
7058 si_llvm_dispose(&ctx);
7059 mtx_unlock(&sscreen->shader_parts_mutex);
7060 return result;
7061 }
7062
7063 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
7064 {
7065 LLVMValueRef ptr[2], list;
7066 bool is_merged_shader =
7067 ctx->screen->info.chip_class >= GFX9 &&
7068 (ctx->type == PIPE_SHADER_TESS_CTRL ||
7069 ctx->type == PIPE_SHADER_GEOMETRY ||
7070 ctx->shader->key.as_ls || ctx->shader->key.as_es);
7071
7072 /* Get the pointer to rw buffers. */
7073 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7074 ptr[1] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS_HI);
7075 list = lp_build_gather_values(&ctx->gallivm, ptr, 2);
7076 list = LLVMBuildBitCast(ctx->ac.builder, list, ctx->i64, "");
7077 list = LLVMBuildIntToPtr(ctx->ac.builder, list,
7078 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS), "");
7079 return list;
7080 }
7081
7082 /**
7083 * Build the vertex shader prolog function.
7084 *
7085 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7086 * All inputs are returned unmodified. The vertex load indices are
7087 * stored after them, which will be used by the API VS for fetching inputs.
7088 *
7089 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7090 * input_v0,
7091 * input_v1,
7092 * input_v2,
7093 * input_v3,
7094 * (VertexID + BaseVertex),
7095 * (InstanceID + StartInstance),
7096 * (InstanceID / 2 + StartInstance)
7097 */
7098 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7099 union si_shader_part_key *key)
7100 {
7101 struct si_function_info fninfo;
7102 LLVMTypeRef *returns;
7103 LLVMValueRef ret, func;
7104 int num_returns, i;
7105 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
7106 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
7107 LLVMValueRef input_vgprs[9];
7108 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
7109 num_input_vgprs;
7110 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
7111
7112 si_init_function_info(&fninfo);
7113
7114 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7115 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
7116 sizeof(LLVMTypeRef));
7117 num_returns = 0;
7118
7119 /* Declare input and output SGPRs. */
7120 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7121 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7122 returns[num_returns++] = ctx->i32;
7123 }
7124
7125 /* Preloaded VGPRs (outputs must be floats) */
7126 for (i = 0; i < num_input_vgprs; i++) {
7127 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
7128 returns[num_returns++] = ctx->f32;
7129 }
7130
7131 /* Vertex load indices. */
7132 for (i = 0; i <= key->vs_prolog.last_input; i++)
7133 returns[num_returns++] = ctx->f32;
7134
7135 /* Create the function. */
7136 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
7137 func = ctx->main_fn;
7138
7139 if (key->vs_prolog.num_merged_next_stage_vgprs) {
7140 if (!key->vs_prolog.is_monolithic)
7141 si_init_exec_from_input(ctx, 3, 0);
7142
7143 if (key->vs_prolog.as_ls &&
7144 ctx->screen->has_ls_vgpr_init_bug) {
7145 /* If there are no HS threads, SPI loads the LS VGPRs
7146 * starting at VGPR 0. Shift them back to where they
7147 * belong.
7148 */
7149 LLVMValueRef has_hs_threads =
7150 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
7151 unpack_param(ctx, 3, 8, 8),
7152 ctx->i32_0, "");
7153
7154 for (i = 4; i > 0; --i) {
7155 input_vgprs[i + 1] =
7156 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
7157 input_vgprs[i + 1],
7158 input_vgprs[i - 1], "");
7159 }
7160 }
7161 }
7162
7163 ctx->abi.vertex_id = input_vgprs[first_vs_vgpr];
7164 ctx->abi.instance_id = input_vgprs[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)];
7165
7166 /* Copy inputs to outputs. This should be no-op, as the registers match,
7167 * but it will prevent the compiler from overwriting them unintentionally.
7168 */
7169 ret = ctx->return_value;
7170 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7171 LLVMValueRef p = LLVMGetParam(func, i);
7172 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7173 }
7174 for (i = 0; i < num_input_vgprs; i++) {
7175 LLVMValueRef p = input_vgprs[i];
7176 p = ac_to_float(&ctx->ac, p);
7177 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
7178 key->vs_prolog.num_input_sgprs + i, "");
7179 }
7180
7181 /* Compute vertex load indices from instance divisors. */
7182 LLVMValueRef instance_divisor_constbuf = NULL;
7183
7184 if (key->vs_prolog.states.instance_divisor_is_fetched) {
7185 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7186 LLVMValueRef buf_index =
7187 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
7188 instance_divisor_constbuf =
7189 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
7190 }
7191
7192 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7193 bool divisor_is_one =
7194 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
7195 bool divisor_is_fetched =
7196 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
7197 LLVMValueRef index;
7198
7199 if (divisor_is_one || divisor_is_fetched) {
7200 LLVMValueRef divisor = ctx->i32_1;
7201
7202 if (divisor_is_fetched) {
7203 divisor = buffer_load_const(ctx, instance_divisor_constbuf,
7204 LLVMConstInt(ctx->i32, i * 4, 0));
7205 divisor = ac_to_integer(&ctx->ac, divisor);
7206 }
7207
7208 /* InstanceID / Divisor + StartInstance */
7209 index = get_instance_index_for_fetch(ctx,
7210 user_sgpr_base +
7211 SI_SGPR_START_INSTANCE,
7212 divisor);
7213 } else {
7214 /* VertexID + BaseVertex */
7215 index = LLVMBuildAdd(ctx->ac.builder,
7216 ctx->abi.vertex_id,
7217 LLVMGetParam(func, user_sgpr_base +
7218 SI_SGPR_BASE_VERTEX), "");
7219 }
7220
7221 index = ac_to_float(&ctx->ac, index);
7222 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7223 fninfo.num_params + i, "");
7224 }
7225
7226 si_llvm_build_ret(ctx, ret);
7227 }
7228
7229 static bool si_get_vs_prolog(struct si_screen *sscreen,
7230 LLVMTargetMachineRef tm,
7231 struct si_shader *shader,
7232 struct pipe_debug_callback *debug,
7233 struct si_shader *main_part,
7234 const struct si_vs_prolog_bits *key)
7235 {
7236 struct si_shader_selector *vs = main_part->selector;
7237
7238 if (!si_vs_needs_prolog(vs, key))
7239 return true;
7240
7241 /* Get the prolog. */
7242 union si_shader_part_key prolog_key;
7243 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7244 key, shader, &prolog_key);
7245
7246 shader->prolog =
7247 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7248 PIPE_SHADER_VERTEX, true, &prolog_key, tm,
7249 debug, si_build_vs_prolog_function,
7250 "Vertex Shader Prolog");
7251 return shader->prolog != NULL;
7252 }
7253
7254 /**
7255 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7256 */
7257 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7258 LLVMTargetMachineRef tm,
7259 struct si_shader *shader,
7260 struct pipe_debug_callback *debug)
7261 {
7262 return si_get_vs_prolog(sscreen, tm, shader, debug, shader,
7263 &shader->key.part.vs.prolog);
7264 }
7265
7266 /**
7267 * Compile the TCS epilog function. This writes tesselation factors to memory
7268 * based on the output primitive type of the tesselator (determined by TES).
7269 */
7270 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7271 union si_shader_part_key *key)
7272 {
7273 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7274 struct si_function_info fninfo;
7275 LLVMValueRef func;
7276
7277 si_init_function_info(&fninfo);
7278
7279 if (ctx->screen->info.chip_class >= GFX9) {
7280 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7281 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7282 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7283 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7284 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7285 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7286 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7287 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7288 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7289 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7290 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7291 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7292 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7293 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7294 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7295 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7296 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7297 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7298 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7299 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7300 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7301 } else {
7302 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7303 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7304 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7305 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7306 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7307 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7308 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7309 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7310 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7311 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7312 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7313 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7314 }
7315
7316 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7317 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7318 unsigned tess_factors_idx =
7319 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7320 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7321 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7322
7323 for (unsigned i = 0; i < 6; i++)
7324 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7325
7326 /* Create the function. */
7327 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7328 ctx->screen->info.chip_class >= CIK ? 128 : 64);
7329 ac_declare_lds_as_pointer(&ctx->ac);
7330 func = ctx->main_fn;
7331
7332 LLVMValueRef invoc0_tess_factors[6];
7333 for (unsigned i = 0; i < 6; i++)
7334 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7335
7336 si_write_tess_factors(bld_base,
7337 LLVMGetParam(func, tess_factors_idx),
7338 LLVMGetParam(func, tess_factors_idx + 1),
7339 LLVMGetParam(func, tess_factors_idx + 2),
7340 invoc0_tess_factors, invoc0_tess_factors + 4);
7341
7342 LLVMBuildRetVoid(ctx->ac.builder);
7343 }
7344
7345 /**
7346 * Select and compile (or reuse) TCS parts (epilog).
7347 */
7348 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7349 LLVMTargetMachineRef tm,
7350 struct si_shader *shader,
7351 struct pipe_debug_callback *debug)
7352 {
7353 if (sscreen->info.chip_class >= GFX9) {
7354 struct si_shader *ls_main_part =
7355 shader->key.part.tcs.ls->main_shader_part_ls;
7356
7357 if (!si_get_vs_prolog(sscreen, tm, shader, debug, ls_main_part,
7358 &shader->key.part.tcs.ls_prolog))
7359 return false;
7360
7361 shader->previous_stage = ls_main_part;
7362 }
7363
7364 /* Get the epilog. */
7365 union si_shader_part_key epilog_key;
7366 memset(&epilog_key, 0, sizeof(epilog_key));
7367 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7368
7369 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7370 PIPE_SHADER_TESS_CTRL, false,
7371 &epilog_key, tm, debug,
7372 si_build_tcs_epilog_function,
7373 "Tessellation Control Shader Epilog");
7374 return shader->epilog != NULL;
7375 }
7376
7377 /**
7378 * Select and compile (or reuse) GS parts (prolog).
7379 */
7380 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7381 LLVMTargetMachineRef tm,
7382 struct si_shader *shader,
7383 struct pipe_debug_callback *debug)
7384 {
7385 if (sscreen->info.chip_class >= GFX9) {
7386 struct si_shader *es_main_part =
7387 shader->key.part.gs.es->main_shader_part_es;
7388
7389 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7390 !si_get_vs_prolog(sscreen, tm, shader, debug, es_main_part,
7391 &shader->key.part.gs.vs_prolog))
7392 return false;
7393
7394 shader->previous_stage = es_main_part;
7395 }
7396
7397 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7398 return true;
7399
7400 union si_shader_part_key prolog_key;
7401 memset(&prolog_key, 0, sizeof(prolog_key));
7402 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7403
7404 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7405 PIPE_SHADER_GEOMETRY, true,
7406 &prolog_key, tm, debug,
7407 si_build_gs_prolog_function,
7408 "Geometry Shader Prolog");
7409 return shader->prolog2 != NULL;
7410 }
7411
7412 /**
7413 * Build the pixel shader prolog function. This handles:
7414 * - two-side color selection and interpolation
7415 * - overriding interpolation parameters for the API PS
7416 * - polygon stippling
7417 *
7418 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7419 * overriden by other states. (e.g. per-sample interpolation)
7420 * Interpolated colors are stored after the preloaded VGPRs.
7421 */
7422 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7423 union si_shader_part_key *key)
7424 {
7425 struct si_function_info fninfo;
7426 LLVMValueRef ret, func;
7427 int num_returns, i, num_color_channels;
7428
7429 assert(si_need_ps_prolog(key));
7430
7431 si_init_function_info(&fninfo);
7432
7433 /* Declare inputs. */
7434 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7435 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7436
7437 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7438 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7439
7440 /* Declare outputs (same as inputs + add colors if needed) */
7441 num_returns = fninfo.num_params;
7442 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7443 for (i = 0; i < num_color_channels; i++)
7444 fninfo.types[num_returns++] = ctx->f32;
7445
7446 /* Create the function. */
7447 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7448 &fninfo, 0);
7449 func = ctx->main_fn;
7450
7451 /* Copy inputs to outputs. This should be no-op, as the registers match,
7452 * but it will prevent the compiler from overwriting them unintentionally.
7453 */
7454 ret = ctx->return_value;
7455 for (i = 0; i < fninfo.num_params; i++) {
7456 LLVMValueRef p = LLVMGetParam(func, i);
7457 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7458 }
7459
7460 /* Polygon stippling. */
7461 if (key->ps_prolog.states.poly_stipple) {
7462 /* POS_FIXED_PT is always last. */
7463 unsigned pos = key->ps_prolog.num_input_sgprs +
7464 key->ps_prolog.num_input_vgprs - 1;
7465 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7466
7467 si_llvm_emit_polygon_stipple(ctx, list, pos);
7468 }
7469
7470 if (key->ps_prolog.states.bc_optimize_for_persp ||
7471 key->ps_prolog.states.bc_optimize_for_linear) {
7472 unsigned i, base = key->ps_prolog.num_input_sgprs;
7473 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7474
7475 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7476 * The hw doesn't compute CENTROID if the whole wave only
7477 * contains fully-covered quads.
7478 *
7479 * PRIM_MASK is after user SGPRs.
7480 */
7481 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7482 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7483 LLVMConstInt(ctx->i32, 31, 0), "");
7484 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7485 ctx->i1, "");
7486
7487 if (key->ps_prolog.states.bc_optimize_for_persp) {
7488 /* Read PERSP_CENTER. */
7489 for (i = 0; i < 2; i++)
7490 center[i] = LLVMGetParam(func, base + 2 + i);
7491 /* Read PERSP_CENTROID. */
7492 for (i = 0; i < 2; i++)
7493 centroid[i] = LLVMGetParam(func, base + 4 + i);
7494 /* Select PERSP_CENTROID. */
7495 for (i = 0; i < 2; i++) {
7496 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7497 center[i], centroid[i], "");
7498 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7499 tmp, base + 4 + i, "");
7500 }
7501 }
7502 if (key->ps_prolog.states.bc_optimize_for_linear) {
7503 /* Read LINEAR_CENTER. */
7504 for (i = 0; i < 2; i++)
7505 center[i] = LLVMGetParam(func, base + 8 + i);
7506 /* Read LINEAR_CENTROID. */
7507 for (i = 0; i < 2; i++)
7508 centroid[i] = LLVMGetParam(func, base + 10 + i);
7509 /* Select LINEAR_CENTROID. */
7510 for (i = 0; i < 2; i++) {
7511 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7512 center[i], centroid[i], "");
7513 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7514 tmp, base + 10 + i, "");
7515 }
7516 }
7517 }
7518
7519 /* Force per-sample interpolation. */
7520 if (key->ps_prolog.states.force_persp_sample_interp) {
7521 unsigned i, base = key->ps_prolog.num_input_sgprs;
7522 LLVMValueRef persp_sample[2];
7523
7524 /* Read PERSP_SAMPLE. */
7525 for (i = 0; i < 2; i++)
7526 persp_sample[i] = LLVMGetParam(func, base + i);
7527 /* Overwrite PERSP_CENTER. */
7528 for (i = 0; i < 2; i++)
7529 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7530 persp_sample[i], base + 2 + i, "");
7531 /* Overwrite PERSP_CENTROID. */
7532 for (i = 0; i < 2; i++)
7533 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7534 persp_sample[i], base + 4 + i, "");
7535 }
7536 if (key->ps_prolog.states.force_linear_sample_interp) {
7537 unsigned i, base = key->ps_prolog.num_input_sgprs;
7538 LLVMValueRef linear_sample[2];
7539
7540 /* Read LINEAR_SAMPLE. */
7541 for (i = 0; i < 2; i++)
7542 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7543 /* Overwrite LINEAR_CENTER. */
7544 for (i = 0; i < 2; i++)
7545 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7546 linear_sample[i], base + 8 + i, "");
7547 /* Overwrite LINEAR_CENTROID. */
7548 for (i = 0; i < 2; i++)
7549 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7550 linear_sample[i], base + 10 + i, "");
7551 }
7552
7553 /* Force center interpolation. */
7554 if (key->ps_prolog.states.force_persp_center_interp) {
7555 unsigned i, base = key->ps_prolog.num_input_sgprs;
7556 LLVMValueRef persp_center[2];
7557
7558 /* Read PERSP_CENTER. */
7559 for (i = 0; i < 2; i++)
7560 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7561 /* Overwrite PERSP_SAMPLE. */
7562 for (i = 0; i < 2; i++)
7563 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7564 persp_center[i], base + i, "");
7565 /* Overwrite PERSP_CENTROID. */
7566 for (i = 0; i < 2; i++)
7567 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7568 persp_center[i], base + 4 + i, "");
7569 }
7570 if (key->ps_prolog.states.force_linear_center_interp) {
7571 unsigned i, base = key->ps_prolog.num_input_sgprs;
7572 LLVMValueRef linear_center[2];
7573
7574 /* Read LINEAR_CENTER. */
7575 for (i = 0; i < 2; i++)
7576 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7577 /* Overwrite LINEAR_SAMPLE. */
7578 for (i = 0; i < 2; i++)
7579 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7580 linear_center[i], base + 6 + i, "");
7581 /* Overwrite LINEAR_CENTROID. */
7582 for (i = 0; i < 2; i++)
7583 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7584 linear_center[i], base + 10 + i, "");
7585 }
7586
7587 /* Interpolate colors. */
7588 unsigned color_out_idx = 0;
7589 for (i = 0; i < 2; i++) {
7590 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7591 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7592 key->ps_prolog.face_vgpr_index;
7593 LLVMValueRef interp[2], color[4];
7594 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7595
7596 if (!writemask)
7597 continue;
7598
7599 /* If the interpolation qualifier is not CONSTANT (-1). */
7600 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7601 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7602 key->ps_prolog.color_interp_vgpr_index[i];
7603
7604 /* Get the (i,j) updated by bc_optimize handling. */
7605 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7606 interp_vgpr, "");
7607 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7608 interp_vgpr + 1, "");
7609 interp_ij = lp_build_gather_values(&ctx->gallivm, interp, 2);
7610 }
7611
7612 /* Use the absolute location of the input. */
7613 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7614
7615 if (key->ps_prolog.states.color_two_side) {
7616 face = LLVMGetParam(func, face_vgpr);
7617 face = ac_to_integer(&ctx->ac, face);
7618 }
7619
7620 interp_fs_input(ctx,
7621 key->ps_prolog.color_attr_index[i],
7622 TGSI_SEMANTIC_COLOR, i,
7623 key->ps_prolog.num_interp_inputs,
7624 key->ps_prolog.colors_read, interp_ij,
7625 prim_mask, face, color);
7626
7627 while (writemask) {
7628 unsigned chan = u_bit_scan(&writemask);
7629 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7630 fninfo.num_params + color_out_idx++, "");
7631 }
7632 }
7633
7634 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7635 * says:
7636 *
7637 * "When per-sample shading is active due to the use of a fragment
7638 * input qualified by sample or due to the use of the gl_SampleID
7639 * or gl_SamplePosition variables, only the bit for the current
7640 * sample is set in gl_SampleMaskIn. When state specifies multiple
7641 * fragment shader invocations for a given fragment, the sample
7642 * mask for any single fragment shader invocation may specify a
7643 * subset of the covered samples for the fragment. In this case,
7644 * the bit corresponding to each covered sample will be set in
7645 * exactly one fragment shader invocation."
7646 *
7647 * The samplemask loaded by hardware is always the coverage of the
7648 * entire pixel/fragment, so mask bits out based on the sample ID.
7649 */
7650 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7651 /* The bit pattern matches that used by fixed function fragment
7652 * processing. */
7653 static const uint16_t ps_iter_masks[] = {
7654 0xffff, /* not used */
7655 0x5555,
7656 0x1111,
7657 0x0101,
7658 0x0001,
7659 };
7660 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7661
7662 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7663 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7664 key->ps_prolog.ancillary_vgpr_index;
7665 LLVMValueRef sampleid = unpack_param(ctx, ancillary_vgpr, 8, 4);
7666 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7667
7668 samplemask = ac_to_integer(&ctx->ac, samplemask);
7669 samplemask = LLVMBuildAnd(
7670 ctx->ac.builder,
7671 samplemask,
7672 LLVMBuildShl(ctx->ac.builder,
7673 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7674 sampleid, ""),
7675 "");
7676 samplemask = ac_to_float(&ctx->ac, samplemask);
7677
7678 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7679 ancillary_vgpr + 1, "");
7680 }
7681
7682 /* Tell LLVM to insert WQM instruction sequence when needed. */
7683 if (key->ps_prolog.wqm) {
7684 LLVMAddTargetDependentFunctionAttr(func,
7685 "amdgpu-ps-wqm-outputs", "");
7686 }
7687
7688 si_llvm_build_ret(ctx, ret);
7689 }
7690
7691 /**
7692 * Build the pixel shader epilog function. This handles everything that must be
7693 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7694 */
7695 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7696 union si_shader_part_key *key)
7697 {
7698 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7699 struct si_function_info fninfo;
7700 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7701 int i;
7702 struct si_ps_exports exp = {};
7703
7704 si_init_function_info(&fninfo);
7705
7706 /* Declare input SGPRs. */
7707 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7708 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7709 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7710 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7711 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7712
7713 /* Declare input VGPRs. */
7714 unsigned required_num_params =
7715 fninfo.num_sgpr_params +
7716 util_bitcount(key->ps_epilog.colors_written) * 4 +
7717 key->ps_epilog.writes_z +
7718 key->ps_epilog.writes_stencil +
7719 key->ps_epilog.writes_samplemask;
7720
7721 required_num_params = MAX2(required_num_params,
7722 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7723
7724 while (fninfo.num_params < required_num_params)
7725 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7726
7727 /* Create the function. */
7728 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7729 /* Disable elimination of unused inputs. */
7730 si_llvm_add_attribute(ctx->main_fn,
7731 "InitialPSInputAddr", 0xffffff);
7732
7733 /* Process colors. */
7734 unsigned vgpr = fninfo.num_sgpr_params;
7735 unsigned colors_written = key->ps_epilog.colors_written;
7736 int last_color_export = -1;
7737
7738 /* Find the last color export. */
7739 if (!key->ps_epilog.writes_z &&
7740 !key->ps_epilog.writes_stencil &&
7741 !key->ps_epilog.writes_samplemask) {
7742 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7743
7744 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7745 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7746 /* Just set this if any of the colorbuffers are enabled. */
7747 if (spi_format &
7748 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7749 last_color_export = 0;
7750 } else {
7751 for (i = 0; i < 8; i++)
7752 if (colors_written & (1 << i) &&
7753 (spi_format >> (i * 4)) & 0xf)
7754 last_color_export = i;
7755 }
7756 }
7757
7758 while (colors_written) {
7759 LLVMValueRef color[4];
7760 int mrt = u_bit_scan(&colors_written);
7761
7762 for (i = 0; i < 4; i++)
7763 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7764
7765 si_export_mrt_color(bld_base, color, mrt,
7766 fninfo.num_params - 1,
7767 mrt == last_color_export, &exp);
7768 }
7769
7770 /* Process depth, stencil, samplemask. */
7771 if (key->ps_epilog.writes_z)
7772 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7773 if (key->ps_epilog.writes_stencil)
7774 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7775 if (key->ps_epilog.writes_samplemask)
7776 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7777
7778 if (depth || stencil || samplemask)
7779 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7780 else if (last_color_export == -1)
7781 si_export_null(bld_base);
7782
7783 if (exp.num)
7784 si_emit_ps_exports(ctx, &exp);
7785
7786 /* Compile. */
7787 LLVMBuildRetVoid(ctx->ac.builder);
7788 }
7789
7790 /**
7791 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7792 */
7793 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7794 LLVMTargetMachineRef tm,
7795 struct si_shader *shader,
7796 struct pipe_debug_callback *debug)
7797 {
7798 union si_shader_part_key prolog_key;
7799 union si_shader_part_key epilog_key;
7800
7801 /* Get the prolog. */
7802 si_get_ps_prolog_key(shader, &prolog_key, true);
7803
7804 /* The prolog is a no-op if these aren't set. */
7805 if (si_need_ps_prolog(&prolog_key)) {
7806 shader->prolog =
7807 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7808 PIPE_SHADER_FRAGMENT, true,
7809 &prolog_key, tm, debug,
7810 si_build_ps_prolog_function,
7811 "Fragment Shader Prolog");
7812 if (!shader->prolog)
7813 return false;
7814 }
7815
7816 /* Get the epilog. */
7817 si_get_ps_epilog_key(shader, &epilog_key);
7818
7819 shader->epilog =
7820 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7821 PIPE_SHADER_FRAGMENT, false,
7822 &epilog_key, tm, debug,
7823 si_build_ps_epilog_function,
7824 "Fragment Shader Epilog");
7825 if (!shader->epilog)
7826 return false;
7827
7828 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7829 if (shader->key.part.ps.prolog.poly_stipple) {
7830 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7831 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7832 }
7833
7834 /* Set up the enable bits for per-sample shading if needed. */
7835 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7836 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7837 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7838 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7839 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7840 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7841 }
7842 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7843 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7844 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7845 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7846 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7847 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7848 }
7849 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7850 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7851 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7852 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7853 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7854 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7855 }
7856 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7857 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7858 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7859 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7860 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7861 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7862 }
7863
7864 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7865 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7866 !(shader->config.spi_ps_input_ena & 0xf)) {
7867 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7868 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7869 }
7870
7871 /* At least one pair of interpolation weights must be enabled. */
7872 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7873 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7874 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7875 }
7876
7877 /* Samplemask fixup requires the sample ID. */
7878 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7879 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7880 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7881 }
7882
7883 /* The sample mask input is always enabled, because the API shader always
7884 * passes it through to the epilog. Disable it here if it's unused.
7885 */
7886 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7887 !shader->selector->info.reads_samplemask)
7888 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7889
7890 return true;
7891 }
7892
7893 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7894 unsigned *lds_size)
7895 {
7896 /* SPI barrier management bug:
7897 * Make sure we have at least 4k of LDS in use to avoid the bug.
7898 * It applies to workgroup sizes of more than one wavefront.
7899 */
7900 if (sscreen->info.family == CHIP_BONAIRE ||
7901 sscreen->info.family == CHIP_KABINI ||
7902 sscreen->info.family == CHIP_MULLINS)
7903 *lds_size = MAX2(*lds_size, 8);
7904 }
7905
7906 static void si_fix_resource_usage(struct si_screen *sscreen,
7907 struct si_shader *shader)
7908 {
7909 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7910
7911 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7912
7913 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7914 si_get_max_workgroup_size(shader) > 64) {
7915 si_multiwave_lds_size_workaround(sscreen,
7916 &shader->config.lds_size);
7917 }
7918 }
7919
7920 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7921 struct si_shader *shader,
7922 struct pipe_debug_callback *debug)
7923 {
7924 struct si_shader_selector *sel = shader->selector;
7925 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7926 int r;
7927
7928 /* LS, ES, VS are compiled on demand if the main part hasn't been
7929 * compiled for that stage.
7930 *
7931 * Vertex shaders are compiled on demand when a vertex fetch
7932 * workaround must be applied.
7933 */
7934 if (shader->is_monolithic) {
7935 /* Monolithic shader (compiled as a whole, has many variants,
7936 * may take a long time to compile).
7937 */
7938 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7939 if (r)
7940 return r;
7941 } else {
7942 /* The shader consists of several parts:
7943 *
7944 * - the middle part is the user shader, it has 1 variant only
7945 * and it was compiled during the creation of the shader
7946 * selector
7947 * - the prolog part is inserted at the beginning
7948 * - the epilog part is inserted at the end
7949 *
7950 * The prolog and epilog have many (but simple) variants.
7951 *
7952 * Starting with gfx9, geometry and tessellation control
7953 * shaders also contain the prolog and user shader parts of
7954 * the previous shader stage.
7955 */
7956
7957 if (!mainp)
7958 return -1;
7959
7960 /* Copy the compiled TGSI shader data over. */
7961 shader->is_binary_shared = true;
7962 shader->binary = mainp->binary;
7963 shader->config = mainp->config;
7964 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7965 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7966 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7967 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
7968 memcpy(shader->info.vs_output_param_offset,
7969 mainp->info.vs_output_param_offset,
7970 sizeof(mainp->info.vs_output_param_offset));
7971 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7972 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7973 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7974
7975 /* Select prologs and/or epilogs. */
7976 switch (sel->type) {
7977 case PIPE_SHADER_VERTEX:
7978 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7979 return -1;
7980 break;
7981 case PIPE_SHADER_TESS_CTRL:
7982 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7983 return -1;
7984 break;
7985 case PIPE_SHADER_TESS_EVAL:
7986 break;
7987 case PIPE_SHADER_GEOMETRY:
7988 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
7989 return -1;
7990 break;
7991 case PIPE_SHADER_FRAGMENT:
7992 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7993 return -1;
7994
7995 /* Make sure we have at least as many VGPRs as there
7996 * are allocated inputs.
7997 */
7998 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7999 shader->info.num_input_vgprs);
8000 break;
8001 }
8002
8003 /* Update SGPR and VGPR counts. */
8004 if (shader->prolog) {
8005 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8006 shader->prolog->config.num_sgprs);
8007 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8008 shader->prolog->config.num_vgprs);
8009 }
8010 if (shader->previous_stage) {
8011 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8012 shader->previous_stage->config.num_sgprs);
8013 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8014 shader->previous_stage->config.num_vgprs);
8015 shader->config.spilled_sgprs =
8016 MAX2(shader->config.spilled_sgprs,
8017 shader->previous_stage->config.spilled_sgprs);
8018 shader->config.spilled_vgprs =
8019 MAX2(shader->config.spilled_vgprs,
8020 shader->previous_stage->config.spilled_vgprs);
8021 shader->config.private_mem_vgprs =
8022 MAX2(shader->config.private_mem_vgprs,
8023 shader->previous_stage->config.private_mem_vgprs);
8024 shader->config.scratch_bytes_per_wave =
8025 MAX2(shader->config.scratch_bytes_per_wave,
8026 shader->previous_stage->config.scratch_bytes_per_wave);
8027 shader->info.uses_instanceid |=
8028 shader->previous_stage->info.uses_instanceid;
8029 }
8030 if (shader->prolog2) {
8031 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8032 shader->prolog2->config.num_sgprs);
8033 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8034 shader->prolog2->config.num_vgprs);
8035 }
8036 if (shader->epilog) {
8037 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8038 shader->epilog->config.num_sgprs);
8039 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8040 shader->epilog->config.num_vgprs);
8041 }
8042 }
8043
8044 si_fix_resource_usage(sscreen, shader);
8045 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8046 stderr, true);
8047
8048 /* Upload. */
8049 r = si_shader_binary_upload(sscreen, shader);
8050 if (r) {
8051 fprintf(stderr, "LLVM failed to upload shader\n");
8052 return r;
8053 }
8054
8055 return 0;
8056 }
8057
8058 void si_shader_destroy(struct si_shader *shader)
8059 {
8060 if (shader->scratch_bo)
8061 r600_resource_reference(&shader->scratch_bo, NULL);
8062
8063 r600_resource_reference(&shader->bo, NULL);
8064
8065 if (!shader->is_binary_shared)
8066 ac_shader_binary_clean(&shader->binary);
8067
8068 free(shader->shader_log);
8069 }