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radeonsi: turn si_shader_key::mono into a non-union
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "util/u_memory.h"
37 #include "util/u_string.h"
38 #include "tgsi/tgsi_build.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "si_shader_internal.h"
45 #include "si_pipe.h"
46 #include "sid.h"
47
48
49 static const char *scratch_rsrc_dword0_symbol =
50 "SCRATCH_RSRC_DWORD0";
51
52 static const char *scratch_rsrc_dword1_symbol =
53 "SCRATCH_RSRC_DWORD1";
54
55 struct si_shader_output_values
56 {
57 LLVMValueRef values[4];
58 unsigned semantic_name;
59 unsigned semantic_index;
60 ubyte vertex_stream[4];
61 };
62
63 static void si_init_shader_ctx(struct si_shader_context *ctx,
64 struct si_screen *sscreen,
65 struct si_shader *shader,
66 LLVMTargetMachineRef tm);
67
68 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
69 struct lp_build_tgsi_context *bld_base,
70 struct lp_build_emit_data *emit_data);
71
72 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
73 FILE *f);
74
75 static unsigned llvm_get_type_size(LLVMTypeRef type);
76
77 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
78 union si_shader_part_key *key);
79 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
80 union si_shader_part_key *key);
81 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
82 union si_shader_part_key *key);
83 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
84 union si_shader_part_key *key);
85 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
86 union si_shader_part_key *key);
87
88 /* Ideally pass the sample mask input to the PS epilog as v13, which
89 * is its usual location, so that the shader doesn't have to add v_mov.
90 */
91 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
92
93 /* The VS location of the PrimitiveID input is the same in the epilog,
94 * so that the main shader part doesn't have to move it.
95 */
96 #define VS_EPILOG_PRIMID_LOC 2
97
98 enum {
99 CONST_ADDR_SPACE = 2,
100 LOCAL_ADDR_SPACE = 3,
101 };
102
103 /**
104 * Returns a unique index for a semantic name and index. The index must be
105 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
106 * calculated.
107 */
108 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
109 {
110 switch (semantic_name) {
111 case TGSI_SEMANTIC_POSITION:
112 return 0;
113 case TGSI_SEMANTIC_PSIZE:
114 return 1;
115 case TGSI_SEMANTIC_CLIPDIST:
116 assert(index <= 1);
117 return 2 + index;
118 case TGSI_SEMANTIC_GENERIC:
119 if (index <= 63-4)
120 return 4 + index;
121
122 assert(!"invalid generic index");
123 return 0;
124
125 /* patch indices are completely separate and thus start from 0 */
126 case TGSI_SEMANTIC_TESSOUTER:
127 return 0;
128 case TGSI_SEMANTIC_TESSINNER:
129 return 1;
130 case TGSI_SEMANTIC_PATCH:
131 return 2 + index;
132
133 default:
134 assert(!"invalid semantic name");
135 return 0;
136 }
137 }
138
139 unsigned si_shader_io_get_unique_index2(unsigned name, unsigned index)
140 {
141 switch (name) {
142 case TGSI_SEMANTIC_FOG:
143 return 0;
144 case TGSI_SEMANTIC_LAYER:
145 return 1;
146 case TGSI_SEMANTIC_VIEWPORT_INDEX:
147 return 2;
148 case TGSI_SEMANTIC_PRIMID:
149 return 3;
150 case TGSI_SEMANTIC_COLOR: /* these alias */
151 case TGSI_SEMANTIC_BCOLOR:
152 return 4 + index;
153 case TGSI_SEMANTIC_TEXCOORD:
154 return 6 + index;
155 default:
156 assert(!"invalid semantic name");
157 return 0;
158 }
159 }
160
161 /**
162 * Get the value of a shader input parameter and extract a bitfield.
163 */
164 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
165 unsigned param, unsigned rshift,
166 unsigned bitwidth)
167 {
168 struct gallivm_state *gallivm = &ctx->gallivm;
169 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
170 param);
171
172 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
173 value = bitcast(&ctx->bld_base,
174 TGSI_TYPE_UNSIGNED, value);
175
176 if (rshift)
177 value = LLVMBuildLShr(gallivm->builder, value,
178 LLVMConstInt(ctx->i32, rshift, 0), "");
179
180 if (rshift + bitwidth < 32) {
181 unsigned mask = (1 << bitwidth) - 1;
182 value = LLVMBuildAnd(gallivm->builder, value,
183 LLVMConstInt(ctx->i32, mask, 0), "");
184 }
185
186 return value;
187 }
188
189 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
190 {
191 switch (ctx->type) {
192 case PIPE_SHADER_TESS_CTRL:
193 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
194
195 case PIPE_SHADER_TESS_EVAL:
196 return LLVMGetParam(ctx->main_fn,
197 ctx->param_tes_rel_patch_id);
198
199 default:
200 assert(0);
201 return NULL;
202 }
203 }
204
205 /* Tessellation shaders pass outputs to the next shader using LDS.
206 *
207 * LS outputs = TCS inputs
208 * TCS outputs = TES inputs
209 *
210 * The LDS layout is:
211 * - TCS inputs for patch 0
212 * - TCS inputs for patch 1
213 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
214 * - ...
215 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
216 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
217 * - TCS outputs for patch 1
218 * - Per-patch TCS outputs for patch 1
219 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
220 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
221 * - ...
222 *
223 * All three shaders VS(LS), TCS, TES share the same LDS space.
224 */
225
226 static LLVMValueRef
227 get_tcs_in_patch_stride(struct si_shader_context *ctx)
228 {
229 if (ctx->type == PIPE_SHADER_VERTEX)
230 return unpack_param(ctx, SI_PARAM_VS_STATE_BITS, 8, 13);
231 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
232 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 8, 13);
233 else {
234 assert(0);
235 return NULL;
236 }
237 }
238
239 static LLVMValueRef
240 get_tcs_out_patch_stride(struct si_shader_context *ctx)
241 {
242 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
243 }
244
245 static LLVMValueRef
246 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
247 {
248 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
249 unpack_param(ctx,
250 SI_PARAM_TCS_OUT_OFFSETS,
251 0, 16),
252 4);
253 }
254
255 static LLVMValueRef
256 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
257 {
258 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
259 unpack_param(ctx,
260 SI_PARAM_TCS_OUT_OFFSETS,
261 16, 16),
262 4);
263 }
264
265 static LLVMValueRef
266 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
267 {
268 struct gallivm_state *gallivm = &ctx->gallivm;
269 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
270 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
271
272 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
273 }
274
275 static LLVMValueRef
276 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
277 {
278 struct gallivm_state *gallivm = &ctx->gallivm;
279 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
280 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
281 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
282
283 return LLVMBuildAdd(gallivm->builder, patch0_offset,
284 LLVMBuildMul(gallivm->builder, patch_stride,
285 rel_patch_id, ""),
286 "");
287 }
288
289 static LLVMValueRef
290 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
291 {
292 struct gallivm_state *gallivm = &ctx->gallivm;
293 LLVMValueRef patch0_patch_data_offset =
294 get_tcs_out_patch0_patch_data_offset(ctx);
295 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
296 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
297
298 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
299 LLVMBuildMul(gallivm->builder, patch_stride,
300 rel_patch_id, ""),
301 "");
302 }
303
304 static LLVMValueRef get_instance_index_for_fetch(
305 struct si_shader_context *ctx,
306 unsigned param_start_instance, unsigned divisor)
307 {
308 struct gallivm_state *gallivm = &ctx->gallivm;
309
310 LLVMValueRef result = LLVMGetParam(ctx->main_fn,
311 ctx->param_instance_id);
312
313 /* The division must be done before START_INSTANCE is added. */
314 if (divisor > 1)
315 result = LLVMBuildUDiv(gallivm->builder, result,
316 LLVMConstInt(ctx->i32, divisor, 0), "");
317
318 return LLVMBuildAdd(gallivm->builder, result,
319 LLVMGetParam(ctx->main_fn, param_start_instance), "");
320 }
321
322 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
323 * to float. */
324 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
325 LLVMValueRef vec4,
326 unsigned double_index)
327 {
328 LLVMBuilderRef builder = ctx->gallivm.builder;
329 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->gallivm.context);
330 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
331 LLVMVectorType(f64, 2), "");
332 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
333 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
334 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
335 }
336
337 static void declare_input_vs(
338 struct si_shader_context *ctx,
339 unsigned input_index,
340 const struct tgsi_full_declaration *decl,
341 LLVMValueRef out[4])
342 {
343 struct gallivm_state *gallivm = &ctx->gallivm;
344
345 unsigned chan;
346 unsigned fix_fetch;
347 unsigned num_fetches;
348 unsigned fetch_stride;
349
350 LLVMValueRef t_list_ptr;
351 LLVMValueRef t_offset;
352 LLVMValueRef t_list;
353 LLVMValueRef vertex_index;
354 LLVMValueRef input[3];
355
356 /* Load the T list */
357 t_list_ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_VERTEX_BUFFERS);
358
359 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
360
361 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
362
363 vertex_index = LLVMGetParam(ctx->main_fn,
364 ctx->param_vertex_index0 +
365 input_index);
366
367 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
368
369 /* Do multiple loads for special formats. */
370 switch (fix_fetch) {
371 case SI_FIX_FETCH_RGB_64_FLOAT:
372 num_fetches = 3; /* 3 2-dword loads */
373 fetch_stride = 8;
374 break;
375 case SI_FIX_FETCH_RGBA_64_FLOAT:
376 num_fetches = 2; /* 2 4-dword loads */
377 fetch_stride = 16;
378 break;
379 case SI_FIX_FETCH_RGB_8:
380 case SI_FIX_FETCH_RGB_8_INT:
381 num_fetches = 3;
382 fetch_stride = 1;
383 break;
384 case SI_FIX_FETCH_RGB_16:
385 case SI_FIX_FETCH_RGB_16_INT:
386 num_fetches = 3;
387 fetch_stride = 2;
388 break;
389 default:
390 num_fetches = 1;
391 fetch_stride = 0;
392 }
393
394 for (unsigned i = 0; i < num_fetches; i++) {
395 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
396
397 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
398 vertex_index, voffset,
399 true);
400 }
401
402 /* Break up the vec4 into individual components */
403 for (chan = 0; chan < 4; chan++) {
404 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
405 out[chan] = LLVMBuildExtractElement(gallivm->builder,
406 input[0], llvm_chan, "");
407 }
408
409 switch (fix_fetch) {
410 case SI_FIX_FETCH_A2_SNORM:
411 case SI_FIX_FETCH_A2_SSCALED:
412 case SI_FIX_FETCH_A2_SINT: {
413 /* The hardware returns an unsigned value; convert it to a
414 * signed one.
415 */
416 LLVMValueRef tmp = out[3];
417 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
418
419 /* First, recover the sign-extended signed integer value. */
420 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
421 tmp = LLVMBuildFPToUI(gallivm->builder, tmp, ctx->i32, "");
422 else
423 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->i32, "");
424
425 /* For the integer-like cases, do a natural sign extension.
426 *
427 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
428 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
429 * exponent.
430 */
431 tmp = LLVMBuildShl(gallivm->builder, tmp,
432 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
433 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
434 tmp = LLVMBuildAShr(gallivm->builder, tmp, c30, "");
435
436 /* Convert back to the right type. */
437 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
438 LLVMValueRef clamp;
439 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
440 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
441 clamp = LLVMBuildFCmp(gallivm->builder, LLVMRealULT, tmp, neg_one, "");
442 tmp = LLVMBuildSelect(gallivm->builder, clamp, neg_one, tmp, "");
443 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
444 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
445 }
446
447 out[3] = tmp;
448 break;
449 }
450 case SI_FIX_FETCH_RGBA_32_UNORM:
451 case SI_FIX_FETCH_RGBX_32_UNORM:
452 for (chan = 0; chan < 4; chan++) {
453 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
454 ctx->i32, "");
455 out[chan] = LLVMBuildUIToFP(gallivm->builder,
456 out[chan], ctx->f32, "");
457 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
458 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
459 }
460 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
461 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
462 out[3] = LLVMConstReal(ctx->f32, 1);
463 break;
464 case SI_FIX_FETCH_RGBA_32_SNORM:
465 case SI_FIX_FETCH_RGBX_32_SNORM:
466 case SI_FIX_FETCH_RGBA_32_FIXED:
467 case SI_FIX_FETCH_RGBX_32_FIXED: {
468 double scale;
469 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
470 scale = 1.0 / 0x10000;
471 else
472 scale = 1.0 / INT_MAX;
473
474 for (chan = 0; chan < 4; chan++) {
475 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
476 ctx->i32, "");
477 out[chan] = LLVMBuildSIToFP(gallivm->builder,
478 out[chan], ctx->f32, "");
479 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
480 LLVMConstReal(ctx->f32, scale), "");
481 }
482 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
483 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
484 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
485 out[3] = LLVMConstReal(ctx->f32, 1);
486 break;
487 }
488 case SI_FIX_FETCH_RGBA_32_USCALED:
489 for (chan = 0; chan < 4; chan++) {
490 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
491 ctx->i32, "");
492 out[chan] = LLVMBuildUIToFP(gallivm->builder,
493 out[chan], ctx->f32, "");
494 }
495 break;
496 case SI_FIX_FETCH_RGBA_32_SSCALED:
497 for (chan = 0; chan < 4; chan++) {
498 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
499 ctx->i32, "");
500 out[chan] = LLVMBuildSIToFP(gallivm->builder,
501 out[chan], ctx->f32, "");
502 }
503 break;
504 case SI_FIX_FETCH_RG_64_FLOAT:
505 for (chan = 0; chan < 2; chan++)
506 out[chan] = extract_double_to_float(ctx, input[0], chan);
507
508 out[2] = LLVMConstReal(ctx->f32, 0);
509 out[3] = LLVMConstReal(ctx->f32, 1);
510 break;
511 case SI_FIX_FETCH_RGB_64_FLOAT:
512 for (chan = 0; chan < 3; chan++)
513 out[chan] = extract_double_to_float(ctx, input[chan], 0);
514
515 out[3] = LLVMConstReal(ctx->f32, 1);
516 break;
517 case SI_FIX_FETCH_RGBA_64_FLOAT:
518 for (chan = 0; chan < 4; chan++) {
519 out[chan] = extract_double_to_float(ctx, input[chan / 2],
520 chan % 2);
521 }
522 break;
523 case SI_FIX_FETCH_RGB_8:
524 case SI_FIX_FETCH_RGB_8_INT:
525 case SI_FIX_FETCH_RGB_16:
526 case SI_FIX_FETCH_RGB_16_INT:
527 for (chan = 0; chan < 3; chan++) {
528 out[chan] = LLVMBuildExtractElement(gallivm->builder,
529 input[chan],
530 ctx->i32_0, "");
531 }
532 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
533 fix_fetch == SI_FIX_FETCH_RGB_16) {
534 out[3] = LLVMConstReal(ctx->f32, 1);
535 } else {
536 out[3] = LLVMBuildBitCast(gallivm->builder, ctx->i32_1,
537 ctx->f32, "");
538 }
539 break;
540 }
541 }
542
543 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
544 unsigned swizzle)
545 {
546 struct si_shader_context *ctx = si_shader_context(bld_base);
547
548 if (swizzle > 0)
549 return ctx->i32_0;
550
551 switch (ctx->type) {
552 case PIPE_SHADER_VERTEX:
553 return LLVMGetParam(ctx->main_fn,
554 ctx->param_vs_prim_id);
555 case PIPE_SHADER_TESS_CTRL:
556 return LLVMGetParam(ctx->main_fn,
557 SI_PARAM_PATCH_ID);
558 case PIPE_SHADER_TESS_EVAL:
559 return LLVMGetParam(ctx->main_fn,
560 ctx->param_tes_patch_id);
561 case PIPE_SHADER_GEOMETRY:
562 return LLVMGetParam(ctx->main_fn,
563 SI_PARAM_PRIMITIVE_ID);
564 default:
565 assert(0);
566 return ctx->i32_0;
567 }
568 }
569
570 /**
571 * Return the value of tgsi_ind_register for indexing.
572 * This is the indirect index with the constant offset added to it.
573 */
574 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
575 const struct tgsi_ind_register *ind,
576 int rel_index)
577 {
578 struct gallivm_state *gallivm = &ctx->gallivm;
579 LLVMValueRef result;
580
581 result = ctx->addrs[ind->Index][ind->Swizzle];
582 result = LLVMBuildLoad(gallivm->builder, result, "");
583 result = LLVMBuildAdd(gallivm->builder, result,
584 LLVMConstInt(ctx->i32, rel_index, 0), "");
585 return result;
586 }
587
588 /**
589 * Like get_indirect_index, but restricts the return value to a (possibly
590 * undefined) value inside [0..num).
591 */
592 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
593 const struct tgsi_ind_register *ind,
594 int rel_index, unsigned num)
595 {
596 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
597
598 /* LLVM 3.8: If indirect resource indexing is used:
599 * - SI & CIK hang
600 * - VI crashes
601 */
602 if (HAVE_LLVM == 0x0308)
603 return LLVMGetUndef(ctx->i32);
604
605 return si_llvm_bound_index(ctx, result, num);
606 }
607
608
609 /**
610 * Calculate a dword address given an input or output register and a stride.
611 */
612 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
613 const struct tgsi_full_dst_register *dst,
614 const struct tgsi_full_src_register *src,
615 LLVMValueRef vertex_dw_stride,
616 LLVMValueRef base_addr)
617 {
618 struct gallivm_state *gallivm = &ctx->gallivm;
619 struct tgsi_shader_info *info = &ctx->shader->selector->info;
620 ubyte *name, *index, *array_first;
621 int first, param;
622 struct tgsi_full_dst_register reg;
623
624 /* Set the register description. The address computation is the same
625 * for sources and destinations. */
626 if (src) {
627 reg.Register.File = src->Register.File;
628 reg.Register.Index = src->Register.Index;
629 reg.Register.Indirect = src->Register.Indirect;
630 reg.Register.Dimension = src->Register.Dimension;
631 reg.Indirect = src->Indirect;
632 reg.Dimension = src->Dimension;
633 reg.DimIndirect = src->DimIndirect;
634 } else
635 reg = *dst;
636
637 /* If the register is 2-dimensional (e.g. an array of vertices
638 * in a primitive), calculate the base address of the vertex. */
639 if (reg.Register.Dimension) {
640 LLVMValueRef index;
641
642 if (reg.Dimension.Indirect)
643 index = get_indirect_index(ctx, &reg.DimIndirect,
644 reg.Dimension.Index);
645 else
646 index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
647
648 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
649 LLVMBuildMul(gallivm->builder, index,
650 vertex_dw_stride, ""), "");
651 }
652
653 /* Get information about the register. */
654 if (reg.Register.File == TGSI_FILE_INPUT) {
655 name = info->input_semantic_name;
656 index = info->input_semantic_index;
657 array_first = info->input_array_first;
658 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
659 name = info->output_semantic_name;
660 index = info->output_semantic_index;
661 array_first = info->output_array_first;
662 } else {
663 assert(0);
664 return NULL;
665 }
666
667 if (reg.Register.Indirect) {
668 /* Add the relative address of the element. */
669 LLVMValueRef ind_index;
670
671 if (reg.Indirect.ArrayID)
672 first = array_first[reg.Indirect.ArrayID];
673 else
674 first = reg.Register.Index;
675
676 ind_index = get_indirect_index(ctx, &reg.Indirect,
677 reg.Register.Index - first);
678
679 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
680 LLVMBuildMul(gallivm->builder, ind_index,
681 LLVMConstInt(ctx->i32, 4, 0), ""), "");
682
683 param = si_shader_io_get_unique_index(name[first], index[first]);
684 } else {
685 param = si_shader_io_get_unique_index(name[reg.Register.Index],
686 index[reg.Register.Index]);
687 }
688
689 /* Add the base address of the element. */
690 return LLVMBuildAdd(gallivm->builder, base_addr,
691 LLVMConstInt(ctx->i32, param * 4, 0), "");
692 }
693
694 /* The offchip buffer layout for TCS->TES is
695 *
696 * - attribute 0 of patch 0 vertex 0
697 * - attribute 0 of patch 0 vertex 1
698 * - attribute 0 of patch 0 vertex 2
699 * ...
700 * - attribute 0 of patch 1 vertex 0
701 * - attribute 0 of patch 1 vertex 1
702 * ...
703 * - attribute 1 of patch 0 vertex 0
704 * - attribute 1 of patch 0 vertex 1
705 * ...
706 * - per patch attribute 0 of patch 0
707 * - per patch attribute 0 of patch 1
708 * ...
709 *
710 * Note that every attribute has 4 components.
711 */
712 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
713 LLVMValueRef rel_patch_id,
714 LLVMValueRef vertex_index,
715 LLVMValueRef param_index)
716 {
717 struct gallivm_state *gallivm = &ctx->gallivm;
718 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
719 LLVMValueRef param_stride, constant16;
720
721 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
722 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
723 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
724 num_patches, "");
725
726 constant16 = LLVMConstInt(ctx->i32, 16, 0);
727 if (vertex_index) {
728 base_addr = LLVMBuildMul(gallivm->builder, rel_patch_id,
729 vertices_per_patch, "");
730
731 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
732 vertex_index, "");
733
734 param_stride = total_vertices;
735 } else {
736 base_addr = rel_patch_id;
737 param_stride = num_patches;
738 }
739
740 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
741 LLVMBuildMul(gallivm->builder, param_index,
742 param_stride, ""), "");
743
744 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
745
746 if (!vertex_index) {
747 LLVMValueRef patch_data_offset =
748 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
749
750 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
751 patch_data_offset, "");
752 }
753 return base_addr;
754 }
755
756 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
757 struct si_shader_context *ctx,
758 const struct tgsi_full_dst_register *dst,
759 const struct tgsi_full_src_register *src)
760 {
761 struct gallivm_state *gallivm = &ctx->gallivm;
762 struct tgsi_shader_info *info = &ctx->shader->selector->info;
763 ubyte *name, *index, *array_first;
764 struct tgsi_full_src_register reg;
765 LLVMValueRef vertex_index = NULL;
766 LLVMValueRef param_index = NULL;
767 unsigned param_index_base, param_base;
768
769 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
770
771 if (reg.Register.Dimension) {
772
773 if (reg.Dimension.Indirect)
774 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
775 reg.Dimension.Index);
776 else
777 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
778 }
779
780 /* Get information about the register. */
781 if (reg.Register.File == TGSI_FILE_INPUT) {
782 name = info->input_semantic_name;
783 index = info->input_semantic_index;
784 array_first = info->input_array_first;
785 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
786 name = info->output_semantic_name;
787 index = info->output_semantic_index;
788 array_first = info->output_array_first;
789 } else {
790 assert(0);
791 return NULL;
792 }
793
794 if (reg.Register.Indirect) {
795 if (reg.Indirect.ArrayID)
796 param_base = array_first[reg.Indirect.ArrayID];
797 else
798 param_base = reg.Register.Index;
799
800 param_index = get_indirect_index(ctx, &reg.Indirect,
801 reg.Register.Index - param_base);
802
803 } else {
804 param_base = reg.Register.Index;
805 param_index = ctx->i32_0;
806 }
807
808 param_index_base = si_shader_io_get_unique_index(name[param_base],
809 index[param_base]);
810
811 param_index = LLVMBuildAdd(gallivm->builder, param_index,
812 LLVMConstInt(ctx->i32, param_index_base, 0),
813 "");
814
815 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
816 vertex_index, param_index);
817 }
818
819 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
820 enum tgsi_opcode_type type, unsigned swizzle,
821 LLVMValueRef buffer, LLVMValueRef offset,
822 LLVMValueRef base, bool readonly_memory)
823 {
824 struct si_shader_context *ctx = si_shader_context(bld_base);
825 struct gallivm_state *gallivm = &ctx->gallivm;
826 LLVMValueRef value, value2;
827 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
828 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
829
830 if (swizzle == ~0) {
831 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
832 0, 1, 0, readonly_memory);
833
834 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
835 }
836
837 if (!tgsi_type_is_64bit(type)) {
838 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
839 0, 1, 0, readonly_memory);
840
841 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
842 return LLVMBuildExtractElement(gallivm->builder, value,
843 LLVMConstInt(ctx->i32, swizzle, 0), "");
844 }
845
846 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
847 swizzle * 4, 1, 0, readonly_memory);
848
849 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
850 swizzle * 4 + 4, 1, 0, readonly_memory);
851
852 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
853 }
854
855 /**
856 * Load from LDS.
857 *
858 * \param type output value type
859 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
860 * \param dw_addr address in dwords
861 */
862 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
863 enum tgsi_opcode_type type, unsigned swizzle,
864 LLVMValueRef dw_addr)
865 {
866 struct si_shader_context *ctx = si_shader_context(bld_base);
867 struct gallivm_state *gallivm = &ctx->gallivm;
868 LLVMValueRef value;
869
870 if (swizzle == ~0) {
871 LLVMValueRef values[TGSI_NUM_CHANNELS];
872
873 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
874 values[chan] = lds_load(bld_base, type, chan, dw_addr);
875
876 return lp_build_gather_values(gallivm, values,
877 TGSI_NUM_CHANNELS);
878 }
879
880 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
881 LLVMConstInt(ctx->i32, swizzle, 0));
882
883 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
884 if (tgsi_type_is_64bit(type)) {
885 LLVMValueRef value2;
886 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
887 ctx->i32_1);
888 value2 = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
889 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
890 }
891
892 return LLVMBuildBitCast(gallivm->builder, value,
893 tgsi2llvmtype(bld_base, type), "");
894 }
895
896 /**
897 * Store to LDS.
898 *
899 * \param swizzle offset (typically 0..3)
900 * \param dw_addr address in dwords
901 * \param value value to store
902 */
903 static void lds_store(struct lp_build_tgsi_context *bld_base,
904 unsigned swizzle, LLVMValueRef dw_addr,
905 LLVMValueRef value)
906 {
907 struct si_shader_context *ctx = si_shader_context(bld_base);
908 struct gallivm_state *gallivm = &ctx->gallivm;
909
910 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
911 LLVMConstInt(ctx->i32, swizzle, 0));
912
913 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
914 ac_build_indexed_store(&ctx->ac, ctx->lds,
915 dw_addr, value);
916 }
917
918 static LLVMValueRef fetch_input_tcs(
919 struct lp_build_tgsi_context *bld_base,
920 const struct tgsi_full_src_register *reg,
921 enum tgsi_opcode_type type, unsigned swizzle)
922 {
923 struct si_shader_context *ctx = si_shader_context(bld_base);
924 LLVMValueRef dw_addr, stride;
925
926 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 24, 8);
927 dw_addr = get_tcs_in_current_patch_offset(ctx);
928 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
929
930 return lds_load(bld_base, type, swizzle, dw_addr);
931 }
932
933 static LLVMValueRef fetch_output_tcs(
934 struct lp_build_tgsi_context *bld_base,
935 const struct tgsi_full_src_register *reg,
936 enum tgsi_opcode_type type, unsigned swizzle)
937 {
938 struct si_shader_context *ctx = si_shader_context(bld_base);
939 LLVMValueRef dw_addr, stride;
940
941 if (reg->Register.Dimension) {
942 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
943 dw_addr = get_tcs_out_current_patch_offset(ctx);
944 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
945 } else {
946 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
947 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
948 }
949
950 return lds_load(bld_base, type, swizzle, dw_addr);
951 }
952
953 static LLVMValueRef fetch_input_tes(
954 struct lp_build_tgsi_context *bld_base,
955 const struct tgsi_full_src_register *reg,
956 enum tgsi_opcode_type type, unsigned swizzle)
957 {
958 struct si_shader_context *ctx = si_shader_context(bld_base);
959 LLVMValueRef rw_buffers, buffer, base, addr;
960
961 rw_buffers = LLVMGetParam(ctx->main_fn,
962 SI_PARAM_RW_BUFFERS);
963 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
964 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
965
966 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
967 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
968
969 return buffer_load(bld_base, type, swizzle, buffer, base, addr, true);
970 }
971
972 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
973 const struct tgsi_full_instruction *inst,
974 const struct tgsi_opcode_info *info,
975 LLVMValueRef dst[4])
976 {
977 struct si_shader_context *ctx = si_shader_context(bld_base);
978 struct gallivm_state *gallivm = &ctx->gallivm;
979 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
980 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
981 unsigned chan_index;
982 LLVMValueRef dw_addr, stride;
983 LLVMValueRef rw_buffers, buffer, base, buf_addr;
984 LLVMValueRef values[4];
985 bool skip_lds_store;
986 bool is_tess_factor = false;
987
988 /* Only handle per-patch and per-vertex outputs here.
989 * Vectors will be lowered to scalars and this function will be called again.
990 */
991 if (reg->Register.File != TGSI_FILE_OUTPUT ||
992 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
993 si_llvm_emit_store(bld_base, inst, info, dst);
994 return;
995 }
996
997 if (reg->Register.Dimension) {
998 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
999 dw_addr = get_tcs_out_current_patch_offset(ctx);
1000 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1001 skip_lds_store = !sh_info->reads_pervertex_outputs;
1002 } else {
1003 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1004 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1005 skip_lds_store = !sh_info->reads_perpatch_outputs;
1006
1007 if (!reg->Register.Indirect) {
1008 int name = sh_info->output_semantic_name[reg->Register.Index];
1009
1010 /* Always write tess factors into LDS for the TCS epilog. */
1011 if (name == TGSI_SEMANTIC_TESSINNER ||
1012 name == TGSI_SEMANTIC_TESSOUTER) {
1013 skip_lds_store = false;
1014 is_tess_factor = true;
1015 }
1016 }
1017 }
1018
1019 rw_buffers = LLVMGetParam(ctx->main_fn,
1020 SI_PARAM_RW_BUFFERS);
1021 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
1022 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
1023
1024 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1025 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1026
1027
1028 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1029 LLVMValueRef value = dst[chan_index];
1030
1031 if (inst->Instruction.Saturate)
1032 value = ac_build_clamp(&ctx->ac, value);
1033
1034 /* Skip LDS stores if there is no LDS read of this output. */
1035 if (!skip_lds_store)
1036 lds_store(bld_base, chan_index, dw_addr, value);
1037
1038 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1039 values[chan_index] = value;
1040
1041 if (inst->Dst[0].Register.WriteMask != 0xF && !is_tess_factor) {
1042 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1043 buf_addr, base,
1044 4 * chan_index, 1, 0, true, false);
1045 }
1046 }
1047
1048 if (inst->Dst[0].Register.WriteMask == 0xF && !is_tess_factor) {
1049 LLVMValueRef value = lp_build_gather_values(gallivm,
1050 values, 4);
1051 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1052 base, 0, 1, 0, true, false);
1053 }
1054 }
1055
1056 static LLVMValueRef fetch_input_gs(
1057 struct lp_build_tgsi_context *bld_base,
1058 const struct tgsi_full_src_register *reg,
1059 enum tgsi_opcode_type type,
1060 unsigned swizzle)
1061 {
1062 struct si_shader_context *ctx = si_shader_context(bld_base);
1063 struct si_shader *shader = ctx->shader;
1064 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1065 struct gallivm_state *gallivm = &ctx->gallivm;
1066 LLVMValueRef vtx_offset, soffset;
1067 unsigned vtx_offset_param;
1068 struct tgsi_shader_info *info = &shader->selector->info;
1069 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1070 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1071 unsigned param;
1072 LLVMValueRef value;
1073
1074 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1075 return get_primitive_id(bld_base, swizzle);
1076
1077 if (!reg->Register.Dimension)
1078 return NULL;
1079
1080 if (swizzle == ~0) {
1081 LLVMValueRef values[TGSI_NUM_CHANNELS];
1082 unsigned chan;
1083 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1084 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1085 }
1086 return lp_build_gather_values(gallivm, values,
1087 TGSI_NUM_CHANNELS);
1088 }
1089
1090 /* Get the vertex offset parameter */
1091 vtx_offset_param = reg->Dimension.Index;
1092 if (vtx_offset_param < 2) {
1093 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1094 } else {
1095 assert(vtx_offset_param < 6);
1096 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1097 }
1098 vtx_offset = lp_build_mul_imm(uint,
1099 LLVMGetParam(ctx->main_fn,
1100 vtx_offset_param),
1101 4);
1102
1103 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1104 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1105
1106 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1107 vtx_offset, soffset, 0, 1, 0, true);
1108 if (tgsi_type_is_64bit(type)) {
1109 LLVMValueRef value2;
1110 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1111
1112 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1113 ctx->i32_0, vtx_offset, soffset,
1114 0, 1, 0, true);
1115 return si_llvm_emit_fetch_64bit(bld_base, type,
1116 value, value2);
1117 }
1118 return LLVMBuildBitCast(gallivm->builder,
1119 value,
1120 tgsi2llvmtype(bld_base, type), "");
1121 }
1122
1123 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1124 {
1125 switch (interpolate) {
1126 case TGSI_INTERPOLATE_CONSTANT:
1127 return 0;
1128
1129 case TGSI_INTERPOLATE_LINEAR:
1130 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1131 return SI_PARAM_LINEAR_SAMPLE;
1132 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1133 return SI_PARAM_LINEAR_CENTROID;
1134 else
1135 return SI_PARAM_LINEAR_CENTER;
1136 break;
1137 case TGSI_INTERPOLATE_COLOR:
1138 case TGSI_INTERPOLATE_PERSPECTIVE:
1139 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1140 return SI_PARAM_PERSP_SAMPLE;
1141 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1142 return SI_PARAM_PERSP_CENTROID;
1143 else
1144 return SI_PARAM_PERSP_CENTER;
1145 break;
1146 default:
1147 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1148 return -1;
1149 }
1150 }
1151
1152 /**
1153 * Interpolate a fragment shader input.
1154 *
1155 * @param ctx context
1156 * @param input_index index of the input in hardware
1157 * @param semantic_name TGSI_SEMANTIC_*
1158 * @param semantic_index semantic index
1159 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1160 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1161 * @param interp_param interpolation weights (i,j)
1162 * @param prim_mask SI_PARAM_PRIM_MASK
1163 * @param face SI_PARAM_FRONT_FACE
1164 * @param result the return value (4 components)
1165 */
1166 static void interp_fs_input(struct si_shader_context *ctx,
1167 unsigned input_index,
1168 unsigned semantic_name,
1169 unsigned semantic_index,
1170 unsigned num_interp_inputs,
1171 unsigned colors_read_mask,
1172 LLVMValueRef interp_param,
1173 LLVMValueRef prim_mask,
1174 LLVMValueRef face,
1175 LLVMValueRef result[4])
1176 {
1177 struct gallivm_state *gallivm = &ctx->gallivm;
1178 LLVMValueRef attr_number;
1179 LLVMValueRef i, j;
1180
1181 unsigned chan;
1182
1183 /* fs.constant returns the param from the middle vertex, so it's not
1184 * really useful for flat shading. It's meant to be used for custom
1185 * interpolation (but the intrinsic can't fetch from the other two
1186 * vertices).
1187 *
1188 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1189 * to do the right thing. The only reason we use fs.constant is that
1190 * fs.interp cannot be used on integers, because they can be equal
1191 * to NaN.
1192 *
1193 * When interp is false we will use fs.constant or for newer llvm,
1194 * amdgcn.interp.mov.
1195 */
1196 bool interp = interp_param != NULL;
1197
1198 attr_number = LLVMConstInt(ctx->i32, input_index, 0);
1199
1200 if (interp) {
1201 interp_param = LLVMBuildBitCast(gallivm->builder, interp_param,
1202 LLVMVectorType(ctx->f32, 2), "");
1203
1204 i = LLVMBuildExtractElement(gallivm->builder, interp_param,
1205 ctx->i32_0, "");
1206 j = LLVMBuildExtractElement(gallivm->builder, interp_param,
1207 ctx->i32_1, "");
1208 }
1209
1210 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1211 ctx->shader->key.part.ps.prolog.color_two_side) {
1212 LLVMValueRef is_face_positive;
1213 LLVMValueRef back_attr_number;
1214
1215 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1216 * otherwise it's at offset "num_inputs".
1217 */
1218 unsigned back_attr_offset = num_interp_inputs;
1219 if (semantic_index == 1 && colors_read_mask & 0xf)
1220 back_attr_offset += 1;
1221
1222 back_attr_number = LLVMConstInt(ctx->i32, back_attr_offset, 0);
1223
1224 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1225 face, ctx->i32_0, "");
1226
1227 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1228 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
1229 LLVMValueRef front, back;
1230
1231 if (interp) {
1232 front = ac_build_fs_interp(&ctx->ac, llvm_chan,
1233 attr_number, prim_mask,
1234 i, j);
1235 back = ac_build_fs_interp(&ctx->ac, llvm_chan,
1236 back_attr_number, prim_mask,
1237 i, j);
1238 } else {
1239 front = ac_build_fs_interp_mov(&ctx->ac,
1240 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1241 llvm_chan, attr_number, prim_mask);
1242 back = ac_build_fs_interp_mov(&ctx->ac,
1243 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1244 llvm_chan, back_attr_number, prim_mask);
1245 }
1246
1247 result[chan] = LLVMBuildSelect(gallivm->builder,
1248 is_face_positive,
1249 front,
1250 back,
1251 "");
1252 }
1253 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1254 if (interp) {
1255 result[0] = ac_build_fs_interp(&ctx->ac, ctx->i32_0,
1256 attr_number, prim_mask, i, j);
1257 } else {
1258 result[0] = ac_build_fs_interp_mov(&ctx->ac, ctx->i32_0,
1259 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1260 attr_number, prim_mask);
1261 }
1262 result[1] =
1263 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1264 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1265 } else {
1266 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1267 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
1268
1269 if (interp) {
1270 result[chan] = ac_build_fs_interp(&ctx->ac,
1271 llvm_chan, attr_number, prim_mask, i, j);
1272 } else {
1273 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
1274 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1275 llvm_chan, attr_number, prim_mask);
1276 }
1277 }
1278 }
1279 }
1280
1281 static void declare_input_fs(
1282 struct si_shader_context *ctx,
1283 unsigned input_index,
1284 const struct tgsi_full_declaration *decl,
1285 LLVMValueRef out[4])
1286 {
1287 struct lp_build_context *base = &ctx->bld_base.base;
1288 struct si_shader *shader = ctx->shader;
1289 LLVMValueRef main_fn = ctx->main_fn;
1290 LLVMValueRef interp_param = NULL;
1291 int interp_param_idx;
1292
1293 /* Get colors from input VGPRs (set by the prolog). */
1294 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1295 unsigned i = decl->Semantic.Index;
1296 unsigned colors_read = shader->selector->info.colors_read;
1297 unsigned mask = colors_read >> (i * 4);
1298 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1299 (i ? util_bitcount(colors_read & 0xf) : 0);
1300
1301 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1302 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1303 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1304 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1305 return;
1306 }
1307
1308 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1309 decl->Interp.Location);
1310 if (interp_param_idx == -1)
1311 return;
1312 else if (interp_param_idx) {
1313 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1314 }
1315
1316 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
1317 decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR &&
1318 ctx->shader->key.part.ps.prolog.flatshade_colors)
1319 interp_param = NULL; /* load the constant color */
1320
1321 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1322 decl->Semantic.Index, shader->selector->info.num_inputs,
1323 shader->selector->info.colors_read, interp_param,
1324 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1325 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1326 &out[0]);
1327 }
1328
1329 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1330 {
1331 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1332 }
1333
1334
1335 /**
1336 * Load a dword from a constant buffer.
1337 */
1338 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1339 LLVMValueRef resource,
1340 LLVMValueRef offset)
1341 {
1342 LLVMBuilderRef builder = ctx->gallivm.builder;
1343 LLVMValueRef args[2] = {resource, offset};
1344
1345 return lp_build_intrinsic(builder, "llvm.SI.load.const", ctx->f32, args, 2,
1346 LP_FUNC_ATTR_READNONE |
1347 LP_FUNC_ATTR_LEGACY);
1348 }
1349
1350 static LLVMValueRef load_sample_position(struct si_shader_context *ctx, LLVMValueRef sample_id)
1351 {
1352 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1353 struct gallivm_state *gallivm = &ctx->gallivm;
1354 LLVMBuilderRef builder = gallivm->builder;
1355 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1356 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1357 LLVMValueRef resource = ac_build_indexed_load_const(&ctx->ac, desc, buf_index);
1358
1359 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1360 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1361 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1362
1363 LLVMValueRef pos[4] = {
1364 buffer_load_const(ctx, resource, offset0),
1365 buffer_load_const(ctx, resource, offset1),
1366 LLVMConstReal(ctx->f32, 0),
1367 LLVMConstReal(ctx->f32, 0)
1368 };
1369
1370 return lp_build_gather_values(gallivm, pos, 4);
1371 }
1372
1373 static void declare_system_value(struct si_shader_context *ctx,
1374 unsigned index,
1375 const struct tgsi_full_declaration *decl)
1376 {
1377 struct lp_build_context *bld = &ctx->bld_base.base;
1378 struct gallivm_state *gallivm = &ctx->gallivm;
1379 LLVMValueRef value = 0;
1380
1381 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
1382
1383 switch (decl->Semantic.Name) {
1384 case TGSI_SEMANTIC_INSTANCEID:
1385 value = LLVMGetParam(ctx->main_fn,
1386 ctx->param_instance_id);
1387 break;
1388
1389 case TGSI_SEMANTIC_VERTEXID:
1390 value = LLVMBuildAdd(gallivm->builder,
1391 LLVMGetParam(ctx->main_fn,
1392 ctx->param_vertex_id),
1393 LLVMGetParam(ctx->main_fn,
1394 SI_PARAM_BASE_VERTEX), "");
1395 break;
1396
1397 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1398 /* Unused. Clarify the meaning in indexed vs. non-indexed
1399 * draws if this is ever used again. */
1400 assert(false);
1401 break;
1402
1403 case TGSI_SEMANTIC_BASEVERTEX:
1404 {
1405 /* For non-indexed draws, the base vertex set by the driver
1406 * (for direct draws) or the CP (for indirect draws) is the
1407 * first vertex ID, but GLSL expects 0 to be returned.
1408 */
1409 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn, SI_PARAM_VS_STATE_BITS);
1410 LLVMValueRef indexed;
1411
1412 indexed = LLVMBuildLShr(gallivm->builder, vs_state, ctx->i32_1, "");
1413 indexed = LLVMBuildTrunc(gallivm->builder, indexed, ctx->i1, "");
1414
1415 value = LLVMBuildSelect(gallivm->builder, indexed,
1416 LLVMGetParam(ctx->main_fn, SI_PARAM_BASE_VERTEX),
1417 ctx->i32_0, "");
1418 break;
1419 }
1420
1421 case TGSI_SEMANTIC_BASEINSTANCE:
1422 value = LLVMGetParam(ctx->main_fn,
1423 SI_PARAM_START_INSTANCE);
1424 break;
1425
1426 case TGSI_SEMANTIC_DRAWID:
1427 value = LLVMGetParam(ctx->main_fn,
1428 SI_PARAM_DRAWID);
1429 break;
1430
1431 case TGSI_SEMANTIC_INVOCATIONID:
1432 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1433 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1434 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1435 value = LLVMGetParam(ctx->main_fn,
1436 SI_PARAM_GS_INSTANCE_ID);
1437 else
1438 assert(!"INVOCATIONID not implemented");
1439 break;
1440
1441 case TGSI_SEMANTIC_POSITION:
1442 {
1443 LLVMValueRef pos[4] = {
1444 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1445 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1446 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
1447 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
1448 LLVMGetParam(ctx->main_fn,
1449 SI_PARAM_POS_W_FLOAT)),
1450 };
1451 value = lp_build_gather_values(gallivm, pos, 4);
1452 break;
1453 }
1454
1455 case TGSI_SEMANTIC_FACE:
1456 value = LLVMGetParam(ctx->main_fn, SI_PARAM_FRONT_FACE);
1457 break;
1458
1459 case TGSI_SEMANTIC_SAMPLEID:
1460 value = get_sample_id(ctx);
1461 break;
1462
1463 case TGSI_SEMANTIC_SAMPLEPOS: {
1464 LLVMValueRef pos[4] = {
1465 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1466 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1467 LLVMConstReal(ctx->f32, 0),
1468 LLVMConstReal(ctx->f32, 0)
1469 };
1470 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
1471 TGSI_OPCODE_FRC, pos[0]);
1472 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
1473 TGSI_OPCODE_FRC, pos[1]);
1474 value = lp_build_gather_values(gallivm, pos, 4);
1475 break;
1476 }
1477
1478 case TGSI_SEMANTIC_SAMPLEMASK:
1479 /* This can only occur with the OpenGL Core profile, which
1480 * doesn't support smoothing.
1481 */
1482 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1483 break;
1484
1485 case TGSI_SEMANTIC_TESSCOORD:
1486 {
1487 LLVMValueRef coord[4] = {
1488 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1489 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1490 bld->zero,
1491 bld->zero
1492 };
1493
1494 /* For triangles, the vector should be (u, v, 1-u-v). */
1495 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1496 PIPE_PRIM_TRIANGLES)
1497 coord[2] = lp_build_sub(bld, bld->one,
1498 lp_build_add(bld, coord[0], coord[1]));
1499
1500 value = lp_build_gather_values(gallivm, coord, 4);
1501 break;
1502 }
1503
1504 case TGSI_SEMANTIC_VERTICESIN:
1505 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1506 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1507 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1508 value = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 7);
1509 else
1510 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1511 break;
1512
1513 case TGSI_SEMANTIC_TESSINNER:
1514 case TGSI_SEMANTIC_TESSOUTER:
1515 {
1516 LLVMValueRef rw_buffers, buffer, base, addr;
1517 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1518
1519 rw_buffers = LLVMGetParam(ctx->main_fn,
1520 SI_PARAM_RW_BUFFERS);
1521 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
1522 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
1523
1524 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1525 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1526 LLVMConstInt(ctx->i32, param, 0));
1527
1528 value = buffer_load(&ctx->bld_base, TGSI_TYPE_FLOAT,
1529 ~0, buffer, base, addr, true);
1530
1531 break;
1532 }
1533
1534 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1535 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1536 {
1537 LLVMValueRef buf, slot, val[4];
1538 int i, offset;
1539
1540 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
1541 buf = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1542 buf = ac_build_indexed_load_const(&ctx->ac, buf, slot);
1543 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1544
1545 for (i = 0; i < 4; i++)
1546 val[i] = buffer_load_const(ctx, buf,
1547 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
1548 value = lp_build_gather_values(gallivm, val, 4);
1549 break;
1550 }
1551
1552 case TGSI_SEMANTIC_PRIMID:
1553 value = get_primitive_id(&ctx->bld_base, 0);
1554 break;
1555
1556 case TGSI_SEMANTIC_GRID_SIZE:
1557 value = LLVMGetParam(ctx->main_fn, SI_PARAM_GRID_SIZE);
1558 break;
1559
1560 case TGSI_SEMANTIC_BLOCK_SIZE:
1561 {
1562 LLVMValueRef values[3];
1563 unsigned i;
1564 unsigned *properties = ctx->shader->selector->info.properties;
1565
1566 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1567 unsigned sizes[3] = {
1568 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1569 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1570 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1571 };
1572
1573 for (i = 0; i < 3; ++i)
1574 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1575
1576 value = lp_build_gather_values(gallivm, values, 3);
1577 } else {
1578 value = LLVMGetParam(ctx->main_fn, SI_PARAM_BLOCK_SIZE);
1579 }
1580 break;
1581 }
1582
1583 case TGSI_SEMANTIC_BLOCK_ID:
1584 value = LLVMGetParam(ctx->main_fn, SI_PARAM_BLOCK_ID);
1585 break;
1586
1587 case TGSI_SEMANTIC_THREAD_ID:
1588 value = LLVMGetParam(ctx->main_fn, SI_PARAM_THREAD_ID);
1589 break;
1590
1591 case TGSI_SEMANTIC_HELPER_INVOCATION:
1592 if (HAVE_LLVM >= 0x0309) {
1593 value = lp_build_intrinsic(gallivm->builder,
1594 "llvm.amdgcn.ps.live",
1595 ctx->i1, NULL, 0,
1596 LP_FUNC_ATTR_READNONE);
1597 value = LLVMBuildNot(gallivm->builder, value, "");
1598 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1599 } else {
1600 assert(!"TGSI_SEMANTIC_HELPER_INVOCATION unsupported");
1601 return;
1602 }
1603 break;
1604
1605 case TGSI_SEMANTIC_SUBGROUP_SIZE:
1606 value = LLVMConstInt(ctx->i32, 64, 0);
1607 break;
1608
1609 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
1610 value = ac_get_thread_id(&ctx->ac);
1611 break;
1612
1613 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
1614 {
1615 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1616 id = LLVMBuildZExt(gallivm->builder, id, ctx->i64, "");
1617 value = LLVMBuildShl(gallivm->builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
1618 value = LLVMBuildBitCast(gallivm->builder, value, ctx->v2i32, "");
1619 break;
1620 }
1621
1622 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
1623 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
1624 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
1625 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
1626 {
1627 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1628 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
1629 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
1630 /* All bits set except LSB */
1631 value = LLVMConstInt(ctx->i64, -2, 0);
1632 } else {
1633 /* All bits set */
1634 value = LLVMConstInt(ctx->i64, -1, 0);
1635 }
1636 id = LLVMBuildZExt(gallivm->builder, id, ctx->i64, "");
1637 value = LLVMBuildShl(gallivm->builder, value, id, "");
1638 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
1639 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
1640 value = LLVMBuildNot(gallivm->builder, value, "");
1641 value = LLVMBuildBitCast(gallivm->builder, value, ctx->v2i32, "");
1642 break;
1643 }
1644
1645 default:
1646 assert(!"unknown system value");
1647 return;
1648 }
1649
1650 ctx->system_values[index] = value;
1651 }
1652
1653 static void declare_compute_memory(struct si_shader_context *ctx,
1654 const struct tgsi_full_declaration *decl)
1655 {
1656 struct si_shader_selector *sel = ctx->shader->selector;
1657 struct gallivm_state *gallivm = &ctx->gallivm;
1658
1659 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1660 LLVMValueRef var;
1661
1662 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1663 assert(decl->Range.First == decl->Range.Last);
1664 assert(!ctx->shared_memory);
1665
1666 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1667 LLVMArrayType(ctx->i8, sel->local_size),
1668 "compute_lds",
1669 LOCAL_ADDR_SPACE);
1670 LLVMSetAlignment(var, 4);
1671
1672 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1673 }
1674
1675 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1676 {
1677 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1678 SI_PARAM_CONST_BUFFERS);
1679
1680 return ac_build_indexed_load_const(&ctx->ac, list_ptr,
1681 LLVMConstInt(ctx->i32, i, 0));
1682 }
1683
1684 static LLVMValueRef fetch_constant(
1685 struct lp_build_tgsi_context *bld_base,
1686 const struct tgsi_full_src_register *reg,
1687 enum tgsi_opcode_type type,
1688 unsigned swizzle)
1689 {
1690 struct si_shader_context *ctx = si_shader_context(bld_base);
1691 struct lp_build_context *base = &bld_base->base;
1692 const struct tgsi_ind_register *ireg = &reg->Indirect;
1693 unsigned buf, idx;
1694
1695 LLVMValueRef addr, bufp;
1696 LLVMValueRef result;
1697
1698 if (swizzle == LP_CHAN_ALL) {
1699 unsigned chan;
1700 LLVMValueRef values[4];
1701 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1702 values[chan] = fetch_constant(bld_base, reg, type, chan);
1703
1704 return lp_build_gather_values(&ctx->gallivm, values, 4);
1705 }
1706
1707 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1708 idx = reg->Register.Index * 4 + swizzle;
1709
1710 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1711 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_CONST_BUFFERS);
1712 LLVMValueRef index;
1713 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1714 reg->Dimension.Index,
1715 SI_NUM_CONST_BUFFERS);
1716 bufp = ac_build_indexed_load_const(&ctx->ac, ptr, index);
1717 } else
1718 bufp = load_const_buffer_desc(ctx, buf);
1719
1720 if (reg->Register.Indirect) {
1721 addr = ctx->addrs[ireg->Index][ireg->Swizzle];
1722 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1723 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1724 addr = lp_build_add(&bld_base->uint_bld, addr,
1725 LLVMConstInt(ctx->i32, idx * 4, 0));
1726 } else {
1727 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
1728 }
1729
1730 result = buffer_load_const(ctx, bufp, addr);
1731
1732 if (!tgsi_type_is_64bit(type))
1733 result = bitcast(bld_base, type, result);
1734 else {
1735 LLVMValueRef addr2, result2;
1736
1737 addr2 = lp_build_add(&bld_base->uint_bld, addr,
1738 LLVMConstInt(ctx->i32, 4, 0));
1739 result2 = buffer_load_const(ctx, bufp, addr2);
1740
1741 result = si_llvm_emit_fetch_64bit(bld_base, type,
1742 result, result2);
1743 }
1744 return result;
1745 }
1746
1747 /* Upper 16 bits must be zero. */
1748 static LLVMValueRef si_llvm_pack_two_int16(struct si_shader_context *ctx,
1749 LLVMValueRef val[2])
1750 {
1751 return LLVMBuildOr(ctx->gallivm.builder, val[0],
1752 LLVMBuildShl(ctx->gallivm.builder, val[1],
1753 LLVMConstInt(ctx->i32, 16, 0),
1754 ""), "");
1755 }
1756
1757 /* Upper 16 bits are ignored and will be dropped. */
1758 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct si_shader_context *ctx,
1759 LLVMValueRef val[2])
1760 {
1761 LLVMValueRef v[2] = {
1762 LLVMBuildAnd(ctx->gallivm.builder, val[0],
1763 LLVMConstInt(ctx->i32, 0xffff, 0), ""),
1764 val[1],
1765 };
1766 return si_llvm_pack_two_int16(ctx, v);
1767 }
1768
1769 /* Initialize arguments for the shader export intrinsic */
1770 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1771 LLVMValueRef *values,
1772 unsigned target,
1773 struct ac_export_args *args)
1774 {
1775 struct si_shader_context *ctx = si_shader_context(bld_base);
1776 struct lp_build_context *base = &bld_base->base;
1777 LLVMBuilderRef builder = ctx->gallivm.builder;
1778 LLVMValueRef val[4];
1779 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1780 unsigned chan;
1781 bool is_int8, is_int10;
1782
1783 /* Default is 0xf. Adjusted below depending on the format. */
1784 args->enabled_channels = 0xf; /* writemask */
1785
1786 /* Specify whether the EXEC mask represents the valid mask */
1787 args->valid_mask = 0;
1788
1789 /* Specify whether this is the last export */
1790 args->done = 0;
1791
1792 /* Specify the target we are exporting */
1793 args->target = target;
1794
1795 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1796 const struct si_shader_key *key = &ctx->shader->key;
1797 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
1798 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1799
1800 assert(cbuf >= 0 && cbuf < 8);
1801 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1802 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
1803 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
1804 }
1805
1806 args->compr = false;
1807 args->out[0] = base->undef;
1808 args->out[1] = base->undef;
1809 args->out[2] = base->undef;
1810 args->out[3] = base->undef;
1811
1812 switch (spi_shader_col_format) {
1813 case V_028714_SPI_SHADER_ZERO:
1814 args->enabled_channels = 0; /* writemask */
1815 args->target = V_008DFC_SQ_EXP_NULL;
1816 break;
1817
1818 case V_028714_SPI_SHADER_32_R:
1819 args->enabled_channels = 1; /* writemask */
1820 args->out[0] = values[0];
1821 break;
1822
1823 case V_028714_SPI_SHADER_32_GR:
1824 args->enabled_channels = 0x3; /* writemask */
1825 args->out[0] = values[0];
1826 args->out[1] = values[1];
1827 break;
1828
1829 case V_028714_SPI_SHADER_32_AR:
1830 args->enabled_channels = 0x9; /* writemask */
1831 args->out[0] = values[0];
1832 args->out[3] = values[3];
1833 break;
1834
1835 case V_028714_SPI_SHADER_FP16_ABGR:
1836 args->compr = 1; /* COMPR flag */
1837
1838 for (chan = 0; chan < 2; chan++) {
1839 LLVMValueRef pack_args[2] = {
1840 values[2 * chan],
1841 values[2 * chan + 1]
1842 };
1843 LLVMValueRef packed;
1844
1845 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
1846 args->out[chan] =
1847 LLVMBuildBitCast(ctx->gallivm.builder,
1848 packed, ctx->f32, "");
1849 }
1850 break;
1851
1852 case V_028714_SPI_SHADER_UNORM16_ABGR:
1853 for (chan = 0; chan < 4; chan++) {
1854 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
1855 val[chan] = LLVMBuildFMul(builder, val[chan],
1856 LLVMConstReal(ctx->f32, 65535), "");
1857 val[chan] = LLVMBuildFAdd(builder, val[chan],
1858 LLVMConstReal(ctx->f32, 0.5), "");
1859 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1860 ctx->i32, "");
1861 }
1862
1863 args->compr = 1; /* COMPR flag */
1864 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1865 si_llvm_pack_two_int16(ctx, val));
1866 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1867 si_llvm_pack_two_int16(ctx, val+2));
1868 break;
1869
1870 case V_028714_SPI_SHADER_SNORM16_ABGR:
1871 for (chan = 0; chan < 4; chan++) {
1872 /* Clamp between [-1, 1]. */
1873 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1874 values[chan],
1875 LLVMConstReal(ctx->f32, 1));
1876 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1877 val[chan],
1878 LLVMConstReal(ctx->f32, -1));
1879 /* Convert to a signed integer in [-32767, 32767]. */
1880 val[chan] = LLVMBuildFMul(builder, val[chan],
1881 LLVMConstReal(ctx->f32, 32767), "");
1882 /* If positive, add 0.5, else add -0.5. */
1883 val[chan] = LLVMBuildFAdd(builder, val[chan],
1884 LLVMBuildSelect(builder,
1885 LLVMBuildFCmp(builder, LLVMRealOGE,
1886 val[chan], base->zero, ""),
1887 LLVMConstReal(ctx->f32, 0.5),
1888 LLVMConstReal(ctx->f32, -0.5), ""), "");
1889 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
1890 }
1891
1892 args->compr = 1; /* COMPR flag */
1893 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1894 si_llvm_pack_two_int32_as_int16(ctx, val));
1895 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1896 si_llvm_pack_two_int32_as_int16(ctx, val+2));
1897 break;
1898
1899 case V_028714_SPI_SHADER_UINT16_ABGR: {
1900 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
1901 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
1902 LLVMValueRef max_alpha =
1903 !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
1904
1905 /* Clamp. */
1906 for (chan = 0; chan < 4; chan++) {
1907 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1908 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1909 val[chan],
1910 chan == 3 ? max_alpha : max_rgb);
1911 }
1912
1913 args->compr = 1; /* COMPR flag */
1914 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1915 si_llvm_pack_two_int16(ctx, val));
1916 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1917 si_llvm_pack_two_int16(ctx, val+2));
1918 break;
1919 }
1920
1921 case V_028714_SPI_SHADER_SINT16_ABGR: {
1922 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
1923 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
1924 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
1925 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
1926 LLVMValueRef max_alpha =
1927 !is_int10 ? max_rgb : ctx->i32_1;
1928 LLVMValueRef min_alpha =
1929 !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
1930
1931 /* Clamp. */
1932 for (chan = 0; chan < 4; chan++) {
1933 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1934 val[chan] = lp_build_emit_llvm_binary(bld_base,
1935 TGSI_OPCODE_IMIN,
1936 val[chan], chan == 3 ? max_alpha : max_rgb);
1937 val[chan] = lp_build_emit_llvm_binary(bld_base,
1938 TGSI_OPCODE_IMAX,
1939 val[chan], chan == 3 ? min_alpha : min_rgb);
1940 }
1941
1942 args->compr = 1; /* COMPR flag */
1943 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1944 si_llvm_pack_two_int32_as_int16(ctx, val));
1945 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1946 si_llvm_pack_two_int32_as_int16(ctx, val+2));
1947 break;
1948 }
1949
1950 case V_028714_SPI_SHADER_32_ABGR:
1951 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1952 break;
1953 }
1954 }
1955
1956 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1957 LLVMValueRef alpha)
1958 {
1959 struct si_shader_context *ctx = si_shader_context(bld_base);
1960
1961 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
1962 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
1963 SI_PARAM_ALPHA_REF);
1964
1965 LLVMValueRef alpha_pass =
1966 lp_build_cmp(&bld_base->base,
1967 ctx->shader->key.part.ps.epilog.alpha_func,
1968 alpha, alpha_ref);
1969 LLVMValueRef arg =
1970 lp_build_select(&bld_base->base,
1971 alpha_pass,
1972 LLVMConstReal(ctx->f32, 1.0f),
1973 LLVMConstReal(ctx->f32, -1.0f));
1974
1975 ac_build_kill(&ctx->ac, arg);
1976 } else {
1977 ac_build_kill(&ctx->ac, NULL);
1978 }
1979 }
1980
1981 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1982 LLVMValueRef alpha,
1983 unsigned samplemask_param)
1984 {
1985 struct si_shader_context *ctx = si_shader_context(bld_base);
1986 struct gallivm_state *gallivm = &ctx->gallivm;
1987 LLVMValueRef coverage;
1988
1989 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1990 coverage = LLVMGetParam(ctx->main_fn,
1991 samplemask_param);
1992 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1993
1994 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1995 ctx->i32,
1996 &coverage, 1, LP_FUNC_ATTR_READNONE);
1997
1998 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1999 ctx->f32, "");
2000
2001 coverage = LLVMBuildFMul(gallivm->builder, coverage,
2002 LLVMConstReal(ctx->f32,
2003 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2004
2005 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
2006 }
2007
2008 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2009 struct ac_export_args *pos, LLVMValueRef *out_elts)
2010 {
2011 struct si_shader_context *ctx = si_shader_context(bld_base);
2012 struct lp_build_context *base = &bld_base->base;
2013 unsigned reg_index;
2014 unsigned chan;
2015 unsigned const_chan;
2016 LLVMValueRef base_elt;
2017 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2018 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2019 SI_VS_CONST_CLIP_PLANES, 0);
2020 LLVMValueRef const_resource = ac_build_indexed_load_const(&ctx->ac, ptr, constbuf_index);
2021
2022 for (reg_index = 0; reg_index < 2; reg_index ++) {
2023 struct ac_export_args *args = &pos[2 + reg_index];
2024
2025 args->out[0] =
2026 args->out[1] =
2027 args->out[2] =
2028 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2029
2030 /* Compute dot products of position and user clip plane vectors */
2031 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2032 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2033 LLVMValueRef addr =
2034 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2035 const_chan) * 4, 0);
2036 base_elt = buffer_load_const(ctx, const_resource,
2037 addr);
2038 args->out[chan] =
2039 lp_build_add(base, args->out[chan],
2040 lp_build_mul(base, base_elt,
2041 out_elts[const_chan]));
2042 }
2043 }
2044
2045 args->enabled_channels = 0xf;
2046 args->valid_mask = 0;
2047 args->done = 0;
2048 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2049 args->compr = 0;
2050 }
2051 }
2052
2053 static void si_dump_streamout(struct pipe_stream_output_info *so)
2054 {
2055 unsigned i;
2056
2057 if (so->num_outputs)
2058 fprintf(stderr, "STREAMOUT\n");
2059
2060 for (i = 0; i < so->num_outputs; i++) {
2061 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2062 so->output[i].start_component;
2063 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2064 i, so->output[i].output_buffer,
2065 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2066 so->output[i].register_index,
2067 mask & 1 ? "x" : "",
2068 mask & 2 ? "y" : "",
2069 mask & 4 ? "z" : "",
2070 mask & 8 ? "w" : "");
2071 }
2072 }
2073
2074 static void emit_streamout_output(struct si_shader_context *ctx,
2075 LLVMValueRef const *so_buffers,
2076 LLVMValueRef const *so_write_offsets,
2077 struct pipe_stream_output *stream_out,
2078 struct si_shader_output_values *shader_out)
2079 {
2080 struct gallivm_state *gallivm = &ctx->gallivm;
2081 LLVMBuilderRef builder = gallivm->builder;
2082 unsigned buf_idx = stream_out->output_buffer;
2083 unsigned start = stream_out->start_component;
2084 unsigned num_comps = stream_out->num_components;
2085 LLVMValueRef out[4];
2086
2087 assert(num_comps && num_comps <= 4);
2088 if (!num_comps || num_comps > 4)
2089 return;
2090
2091 /* Load the output as int. */
2092 for (int j = 0; j < num_comps; j++) {
2093 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2094
2095 out[j] = LLVMBuildBitCast(builder,
2096 shader_out->values[start + j],
2097 ctx->i32, "");
2098 }
2099
2100 /* Pack the output. */
2101 LLVMValueRef vdata = NULL;
2102
2103 switch (num_comps) {
2104 case 1: /* as i32 */
2105 vdata = out[0];
2106 break;
2107 case 2: /* as v2i32 */
2108 case 3: /* as v4i32 (aligned to 4) */
2109 case 4: /* as v4i32 */
2110 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2111 for (int j = 0; j < num_comps; j++) {
2112 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2113 LLVMConstInt(ctx->i32, j, 0), "");
2114 }
2115 break;
2116 }
2117
2118 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2119 vdata, num_comps,
2120 so_write_offsets[buf_idx],
2121 ctx->i32_0,
2122 stream_out->dst_offset * 4, 1, 1, true, false);
2123 }
2124
2125 /**
2126 * Write streamout data to buffers for vertex stream @p stream (different
2127 * vertex streams can occur for GS copy shaders).
2128 */
2129 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2130 struct si_shader_output_values *outputs,
2131 unsigned noutput, unsigned stream)
2132 {
2133 struct si_shader_selector *sel = ctx->shader->selector;
2134 struct pipe_stream_output_info *so = &sel->so;
2135 struct gallivm_state *gallivm = &ctx->gallivm;
2136 LLVMBuilderRef builder = gallivm->builder;
2137 int i;
2138 struct lp_build_if_state if_ctx;
2139
2140 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2141 LLVMValueRef so_vtx_count =
2142 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2143
2144 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2145
2146 /* can_emit = tid < so_vtx_count; */
2147 LLVMValueRef can_emit =
2148 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2149
2150 /* Emit the streamout code conditionally. This actually avoids
2151 * out-of-bounds buffer access. The hw tells us via the SGPR
2152 * (so_vtx_count) which threads are allowed to emit streamout data. */
2153 lp_build_if(&if_ctx, gallivm, can_emit);
2154 {
2155 /* The buffer offset is computed as follows:
2156 * ByteOffset = streamout_offset[buffer_id]*4 +
2157 * (streamout_write_index + thread_id)*stride[buffer_id] +
2158 * attrib_offset
2159 */
2160
2161 LLVMValueRef so_write_index =
2162 LLVMGetParam(ctx->main_fn,
2163 ctx->param_streamout_write_index);
2164
2165 /* Compute (streamout_write_index + thread_id). */
2166 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2167
2168 /* Load the descriptor and compute the write offset for each
2169 * enabled buffer. */
2170 LLVMValueRef so_write_offset[4] = {};
2171 LLVMValueRef so_buffers[4];
2172 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2173 SI_PARAM_RW_BUFFERS);
2174
2175 for (i = 0; i < 4; i++) {
2176 if (!so->stride[i])
2177 continue;
2178
2179 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2180 SI_VS_STREAMOUT_BUF0 + i, 0);
2181
2182 so_buffers[i] = ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
2183
2184 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2185 ctx->param_streamout_offset[i]);
2186 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2187
2188 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2189 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2190 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2191 }
2192
2193 /* Write streamout data. */
2194 for (i = 0; i < so->num_outputs; i++) {
2195 unsigned reg = so->output[i].register_index;
2196
2197 if (reg >= noutput)
2198 continue;
2199
2200 if (stream != so->output[i].stream)
2201 continue;
2202
2203 emit_streamout_output(ctx, so_buffers, so_write_offset,
2204 &so->output[i], &outputs[reg]);
2205 }
2206 }
2207 lp_build_endif(&if_ctx);
2208 }
2209
2210
2211 /* Generate export instructions for hardware VS shader stage */
2212 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2213 struct si_shader_output_values *outputs,
2214 unsigned noutput)
2215 {
2216 struct si_shader_context *ctx = si_shader_context(bld_base);
2217 struct si_shader *shader = ctx->shader;
2218 struct lp_build_context *base = &bld_base->base;
2219 struct ac_export_args args, pos_args[4] = {};
2220 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2221 unsigned semantic_name, semantic_index;
2222 unsigned target;
2223 unsigned param_count = 0;
2224 unsigned pos_idx;
2225 int i;
2226
2227 for (i = 0; i < noutput; i++) {
2228 semantic_name = outputs[i].semantic_name;
2229 semantic_index = outputs[i].semantic_index;
2230 bool export_param = true;
2231
2232 switch (semantic_name) {
2233 case TGSI_SEMANTIC_POSITION: /* ignore these */
2234 case TGSI_SEMANTIC_PSIZE:
2235 case TGSI_SEMANTIC_CLIPVERTEX:
2236 case TGSI_SEMANTIC_EDGEFLAG:
2237 break;
2238 case TGSI_SEMANTIC_GENERIC:
2239 case TGSI_SEMANTIC_CLIPDIST:
2240 if (shader->key.opt.hw_vs.kill_outputs &
2241 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2242 export_param = false;
2243 break;
2244 default:
2245 if (shader->key.opt.hw_vs.kill_outputs2 &
2246 (1u << si_shader_io_get_unique_index2(semantic_name, semantic_index)))
2247 export_param = false;
2248 break;
2249 }
2250
2251 if (outputs[i].vertex_stream[0] != 0 &&
2252 outputs[i].vertex_stream[1] != 0 &&
2253 outputs[i].vertex_stream[2] != 0 &&
2254 outputs[i].vertex_stream[3] != 0)
2255 export_param = false;
2256
2257 handle_semantic:
2258 /* Select the correct target */
2259 switch(semantic_name) {
2260 case TGSI_SEMANTIC_PSIZE:
2261 psize_value = outputs[i].values[0];
2262 continue;
2263 case TGSI_SEMANTIC_EDGEFLAG:
2264 edgeflag_value = outputs[i].values[0];
2265 continue;
2266 case TGSI_SEMANTIC_LAYER:
2267 layer_value = outputs[i].values[0];
2268 semantic_name = TGSI_SEMANTIC_GENERIC;
2269 goto handle_semantic;
2270 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2271 viewport_index_value = outputs[i].values[0];
2272 semantic_name = TGSI_SEMANTIC_GENERIC;
2273 goto handle_semantic;
2274 case TGSI_SEMANTIC_POSITION:
2275 target = V_008DFC_SQ_EXP_POS;
2276 break;
2277 case TGSI_SEMANTIC_CLIPDIST:
2278 if (shader->key.opt.hw_vs.clip_disable) {
2279 semantic_name = TGSI_SEMANTIC_GENERIC;
2280 goto handle_semantic;
2281 }
2282 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2283 break;
2284 case TGSI_SEMANTIC_CLIPVERTEX:
2285 if (shader->key.opt.hw_vs.clip_disable)
2286 continue;
2287 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2288 continue;
2289 case TGSI_SEMANTIC_COLOR:
2290 case TGSI_SEMANTIC_BCOLOR:
2291 case TGSI_SEMANTIC_PRIMID:
2292 case TGSI_SEMANTIC_FOG:
2293 case TGSI_SEMANTIC_TEXCOORD:
2294 case TGSI_SEMANTIC_GENERIC:
2295 if (!export_param)
2296 continue;
2297 target = V_008DFC_SQ_EXP_PARAM + param_count;
2298 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2299 shader->info.vs_output_param_offset[i] = param_count;
2300 param_count++;
2301 break;
2302 default:
2303 target = 0;
2304 fprintf(stderr,
2305 "Warning: SI unhandled vs output type:%d\n",
2306 semantic_name);
2307 }
2308
2309 si_llvm_init_export_args(bld_base, outputs[i].values, target, &args);
2310
2311 if (target >= V_008DFC_SQ_EXP_POS &&
2312 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2313 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2314 &args, sizeof(args));
2315 } else {
2316 ac_build_export(&ctx->ac, &args);
2317 }
2318
2319 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2320 semantic_name = TGSI_SEMANTIC_GENERIC;
2321 goto handle_semantic;
2322 }
2323 }
2324
2325 shader->info.nr_param_exports = param_count;
2326
2327 /* We need to add the position output manually if it's missing. */
2328 if (!pos_args[0].out[0]) {
2329 pos_args[0].enabled_channels = 0xf; /* writemask */
2330 pos_args[0].valid_mask = 0; /* EXEC mask */
2331 pos_args[0].done = 0; /* last export? */
2332 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2333 pos_args[0].compr = 0; /* COMPR flag */
2334 pos_args[0].out[0] = base->zero; /* X */
2335 pos_args[0].out[1] = base->zero; /* Y */
2336 pos_args[0].out[2] = base->zero; /* Z */
2337 pos_args[0].out[3] = base->one; /* W */
2338 }
2339
2340 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2341 if (shader->selector->info.writes_psize ||
2342 shader->selector->info.writes_edgeflag ||
2343 shader->selector->info.writes_viewport_index ||
2344 shader->selector->info.writes_layer) {
2345 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2346 (shader->selector->info.writes_edgeflag << 1) |
2347 (shader->selector->info.writes_layer << 2) |
2348 (shader->selector->info.writes_viewport_index << 3);
2349 pos_args[1].valid_mask = 0; /* EXEC mask */
2350 pos_args[1].done = 0; /* last export? */
2351 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2352 pos_args[1].compr = 0; /* COMPR flag */
2353 pos_args[1].out[0] = base->zero; /* X */
2354 pos_args[1].out[1] = base->zero; /* Y */
2355 pos_args[1].out[2] = base->zero; /* Z */
2356 pos_args[1].out[3] = base->zero; /* W */
2357
2358 if (shader->selector->info.writes_psize)
2359 pos_args[1].out[0] = psize_value;
2360
2361 if (shader->selector->info.writes_edgeflag) {
2362 /* The output is a float, but the hw expects an integer
2363 * with the first bit containing the edge flag. */
2364 edgeflag_value = LLVMBuildFPToUI(ctx->gallivm.builder,
2365 edgeflag_value,
2366 ctx->i32, "");
2367 edgeflag_value = lp_build_min(&bld_base->int_bld,
2368 edgeflag_value,
2369 ctx->i32_1);
2370
2371 /* The LLVM intrinsic expects a float. */
2372 pos_args[1].out[1] = LLVMBuildBitCast(ctx->gallivm.builder,
2373 edgeflag_value,
2374 ctx->f32, "");
2375 }
2376
2377 if (shader->selector->info.writes_layer)
2378 pos_args[1].out[2] = layer_value;
2379
2380 if (shader->selector->info.writes_viewport_index)
2381 pos_args[1].out[3] = viewport_index_value;
2382 }
2383
2384 for (i = 0; i < 4; i++)
2385 if (pos_args[i].out[0])
2386 shader->info.nr_pos_exports++;
2387
2388 pos_idx = 0;
2389 for (i = 0; i < 4; i++) {
2390 if (!pos_args[i].out[0])
2391 continue;
2392
2393 /* Specify the target we are exporting */
2394 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2395
2396 if (pos_idx == shader->info.nr_pos_exports)
2397 /* Specify that this is the last export */
2398 pos_args[i].done = 1;
2399
2400 ac_build_export(&ctx->ac, &pos_args[i]);
2401 }
2402 }
2403
2404 /**
2405 * Forward all outputs from the vertex shader to the TES. This is only used
2406 * for the fixed function TCS.
2407 */
2408 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2409 {
2410 struct si_shader_context *ctx = si_shader_context(bld_base);
2411 struct gallivm_state *gallivm = &ctx->gallivm;
2412 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2413 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2414 uint64_t inputs;
2415
2416 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2417
2418 rw_buffers = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2419 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
2420 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
2421
2422 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2423
2424 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 24, 8);
2425 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2426 lds_vertex_stride, "");
2427 lds_base = get_tcs_in_current_patch_offset(ctx);
2428 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2429
2430 inputs = ctx->shader->key.mono.ff_tcs_inputs_to_copy;
2431 while (inputs) {
2432 unsigned i = u_bit_scan64(&inputs);
2433
2434 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2435 LLVMConstInt(ctx->i32, 4 * i, 0),
2436 "");
2437
2438 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2439 get_rel_patch_id(ctx),
2440 invocation_id,
2441 LLVMConstInt(ctx->i32, i, 0));
2442
2443 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2444 lds_ptr);
2445
2446 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
2447 buffer_offset, 0, 1, 0, true, false);
2448 }
2449 }
2450
2451 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2452 LLVMValueRef rel_patch_id,
2453 LLVMValueRef invocation_id,
2454 LLVMValueRef tcs_out_current_patch_data_offset)
2455 {
2456 struct si_shader_context *ctx = si_shader_context(bld_base);
2457 struct gallivm_state *gallivm = &ctx->gallivm;
2458 struct si_shader *shader = ctx->shader;
2459 unsigned tess_inner_index, tess_outer_index;
2460 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2461 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base, inner[4], outer[4];
2462 unsigned stride, outer_comps, inner_comps, i;
2463 struct lp_build_if_state if_ctx, inner_if_ctx;
2464
2465 si_llvm_emit_barrier(NULL, bld_base, NULL);
2466
2467 /* Do this only for invocation 0, because the tess levels are per-patch,
2468 * not per-vertex.
2469 *
2470 * This can't jump, because invocation 0 executes this. It should
2471 * at least mask out the loads and stores for other invocations.
2472 */
2473 lp_build_if(&if_ctx, gallivm,
2474 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2475 invocation_id, ctx->i32_0, ""));
2476
2477 /* Determine the layout of one tess factor element in the buffer. */
2478 switch (shader->key.part.tcs.epilog.prim_mode) {
2479 case PIPE_PRIM_LINES:
2480 stride = 2; /* 2 dwords, 1 vec2 store */
2481 outer_comps = 2;
2482 inner_comps = 0;
2483 break;
2484 case PIPE_PRIM_TRIANGLES:
2485 stride = 4; /* 4 dwords, 1 vec4 store */
2486 outer_comps = 3;
2487 inner_comps = 1;
2488 break;
2489 case PIPE_PRIM_QUADS:
2490 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2491 outer_comps = 4;
2492 inner_comps = 2;
2493 break;
2494 default:
2495 assert(0);
2496 return;
2497 }
2498
2499 /* Load tess_inner and tess_outer from LDS.
2500 * Any invocation can write them, so we can't get them from a temporary.
2501 */
2502 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2503 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2504
2505 lds_base = tcs_out_current_patch_data_offset;
2506 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2507 LLVMConstInt(ctx->i32,
2508 tess_inner_index * 4, 0), "");
2509 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2510 LLVMConstInt(ctx->i32,
2511 tess_outer_index * 4, 0), "");
2512
2513 for (i = 0; i < 4; i++) {
2514 inner[i] = LLVMGetUndef(ctx->i32);
2515 outer[i] = LLVMGetUndef(ctx->i32);
2516 }
2517
2518 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2519 /* For isolines, the hardware expects tess factors in the
2520 * reverse order from what GLSL / TGSI specify.
2521 */
2522 outer[0] = out[1] = lds_load(bld_base, TGSI_TYPE_SIGNED, 0, lds_outer);
2523 outer[1] = out[0] = lds_load(bld_base, TGSI_TYPE_SIGNED, 1, lds_outer);
2524 } else {
2525 for (i = 0; i < outer_comps; i++) {
2526 outer[i] = out[i] =
2527 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2528 }
2529 for (i = 0; i < inner_comps; i++) {
2530 inner[i] = out[outer_comps+i] =
2531 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2532 }
2533 }
2534
2535 /* Convert the outputs to vectors for stores. */
2536 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2537 vec1 = NULL;
2538
2539 if (stride > 4)
2540 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2541
2542 /* Get the buffer. */
2543 rw_buffers = LLVMGetParam(ctx->main_fn,
2544 SI_PARAM_RW_BUFFERS);
2545 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
2546 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_FACTOR, 0));
2547
2548 /* Get the offset. */
2549 tf_base = LLVMGetParam(ctx->main_fn,
2550 SI_PARAM_TESS_FACTOR_OFFSET);
2551 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2552 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
2553
2554 lp_build_if(&inner_if_ctx, gallivm,
2555 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2556 rel_patch_id, ctx->i32_0, ""));
2557
2558 /* Store the dynamic HS control word. */
2559 ac_build_buffer_store_dword(&ctx->ac, buffer,
2560 LLVMConstInt(ctx->i32, 0x80000000, 0),
2561 1, ctx->i32_0, tf_base,
2562 0, 1, 0, true, false);
2563
2564 lp_build_endif(&inner_if_ctx);
2565
2566 /* Store the tessellation factors. */
2567 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2568 MIN2(stride, 4), byteoffset, tf_base,
2569 4, 1, 0, true, false);
2570 if (vec1)
2571 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2572 stride - 4, byteoffset, tf_base,
2573 20, 1, 0, true, false);
2574
2575 /* Store the tess factors into the offchip buffer if TES reads them. */
2576 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
2577 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
2578 LLVMValueRef tf_inner_offset;
2579 unsigned param_outer, param_inner;
2580
2581 buf = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
2582 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
2583 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2584
2585 param_outer = si_shader_io_get_unique_index(
2586 TGSI_SEMANTIC_TESSOUTER, 0);
2587 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2588 LLVMConstInt(ctx->i32, param_outer, 0));
2589
2590 outer_vec = lp_build_gather_values(gallivm, outer,
2591 util_next_power_of_two(outer_comps));
2592
2593 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
2594 outer_comps, tf_outer_offset,
2595 base, 0, 1, 0, true, false);
2596 if (inner_comps) {
2597 param_inner = si_shader_io_get_unique_index(
2598 TGSI_SEMANTIC_TESSINNER, 0);
2599 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2600 LLVMConstInt(ctx->i32, param_inner, 0));
2601
2602 inner_vec = inner_comps == 1 ? inner[0] :
2603 lp_build_gather_values(gallivm, inner, inner_comps);
2604 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
2605 inner_comps, tf_inner_offset,
2606 base, 0, 1, 0, true, false);
2607 }
2608 }
2609
2610 lp_build_endif(&if_ctx);
2611 }
2612
2613 /* This only writes the tessellation factor levels. */
2614 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2615 {
2616 struct si_shader_context *ctx = si_shader_context(bld_base);
2617 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2618 LLVMValueRef offchip_soffset, offchip_layout;
2619
2620 si_copy_tcs_inputs(bld_base);
2621
2622 rel_patch_id = get_rel_patch_id(ctx);
2623 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2624 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2625
2626 /* Return epilog parameters from this function. */
2627 LLVMBuilderRef builder = ctx->gallivm.builder;
2628 LLVMValueRef ret = ctx->return_value;
2629 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2630 unsigned vgpr;
2631
2632 /* RW_BUFFERS pointer */
2633 rw_buffers = LLVMGetParam(ctx->main_fn,
2634 SI_PARAM_RW_BUFFERS);
2635 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2636 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2637 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2638 ctx->i32_0, "");
2639 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2640 ctx->i32_1, "");
2641 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2642 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2643
2644 /* Tess offchip and factor buffer soffset are after user SGPRs. */
2645 offchip_layout = LLVMGetParam(ctx->main_fn,
2646 SI_PARAM_TCS_OFFCHIP_LAYOUT);
2647 offchip_soffset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2648 tf_soffset = LLVMGetParam(ctx->main_fn,
2649 SI_PARAM_TESS_FACTOR_OFFSET);
2650 ret = LLVMBuildInsertValue(builder, ret, offchip_layout,
2651 SI_SGPR_TCS_OFFCHIP_LAYOUT, "");
2652 ret = LLVMBuildInsertValue(builder, ret, offchip_soffset,
2653 SI_TCS_NUM_USER_SGPR, "");
2654 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2655 SI_TCS_NUM_USER_SGPR + 1, "");
2656
2657 /* VGPRs */
2658 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2659 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2660 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2661
2662 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2663 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2664 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2665 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2666 ctx->return_value = ret;
2667 }
2668
2669 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2670 {
2671 struct si_shader_context *ctx = si_shader_context(bld_base);
2672 struct si_shader *shader = ctx->shader;
2673 struct tgsi_shader_info *info = &shader->selector->info;
2674 struct gallivm_state *gallivm = &ctx->gallivm;
2675 unsigned i, chan;
2676 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
2677 ctx->param_rel_auto_id);
2678 LLVMValueRef vertex_dw_stride =
2679 unpack_param(ctx, SI_PARAM_VS_STATE_BITS, 24, 8);
2680 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2681 vertex_dw_stride, "");
2682
2683 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2684 * its inputs from it. */
2685 for (i = 0; i < info->num_outputs; i++) {
2686 LLVMValueRef *out_ptr = ctx->outputs[i];
2687 unsigned name = info->output_semantic_name[i];
2688 unsigned index = info->output_semantic_index[i];
2689
2690 /* The ARB_shader_viewport_layer_array spec contains the
2691 * following issue:
2692 *
2693 * 2) What happens if gl_ViewportIndex or gl_Layer is
2694 * written in the vertex shader and a geometry shader is
2695 * present?
2696 *
2697 * RESOLVED: The value written by the last vertex processing
2698 * stage is used. If the last vertex processing stage
2699 * (vertex, tessellation evaluation or geometry) does not
2700 * statically assign to gl_ViewportIndex or gl_Layer, index
2701 * or layer zero is assumed.
2702 *
2703 * So writes to those outputs in VS-as-LS are simply ignored.
2704 */
2705 if (name == TGSI_SEMANTIC_LAYER ||
2706 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
2707 continue;
2708
2709 int param = si_shader_io_get_unique_index(name, index);
2710 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2711 LLVMConstInt(ctx->i32, param * 4, 0), "");
2712
2713 for (chan = 0; chan < 4; chan++) {
2714 lds_store(bld_base, chan, dw_addr,
2715 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2716 }
2717 }
2718 }
2719
2720 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2721 {
2722 struct si_shader_context *ctx = si_shader_context(bld_base);
2723 struct gallivm_state *gallivm = &ctx->gallivm;
2724 struct si_shader *es = ctx->shader;
2725 struct tgsi_shader_info *info = &es->selector->info;
2726 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
2727 ctx->param_es2gs_offset);
2728 unsigned chan;
2729 int i;
2730
2731 for (i = 0; i < info->num_outputs; i++) {
2732 LLVMValueRef *out_ptr = ctx->outputs[i];
2733 int param_index;
2734
2735 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2736 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2737 continue;
2738
2739 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2740 info->output_semantic_index[i]);
2741
2742 for (chan = 0; chan < 4; chan++) {
2743 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2744 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2745
2746 ac_build_buffer_store_dword(&ctx->ac,
2747 ctx->esgs_ring,
2748 out_val, 1, NULL, soffset,
2749 (4 * param_index + chan) * 4,
2750 1, 1, true, true);
2751 }
2752 }
2753 }
2754
2755 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2756 {
2757 struct si_shader_context *ctx = si_shader_context(bld_base);
2758
2759 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
2760 LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID));
2761 }
2762
2763 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2764 {
2765 struct si_shader_context *ctx = si_shader_context(bld_base);
2766 struct gallivm_state *gallivm = &ctx->gallivm;
2767 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2768 struct si_shader_output_values *outputs = NULL;
2769 int i,j;
2770
2771 assert(!ctx->shader->is_gs_copy_shader);
2772
2773 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2774
2775 /* Vertex color clamping.
2776 *
2777 * This uses a state constant loaded in a user data SGPR and
2778 * an IF statement is added that clamps all colors if the constant
2779 * is true.
2780 */
2781 if (ctx->type == PIPE_SHADER_VERTEX) {
2782 struct lp_build_if_state if_ctx;
2783 LLVMValueRef cond = NULL;
2784 LLVMValueRef addr, val;
2785
2786 for (i = 0; i < info->num_outputs; i++) {
2787 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2788 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2789 continue;
2790
2791 /* We've found a color. */
2792 if (!cond) {
2793 /* The state is in the first bit of the user SGPR. */
2794 cond = LLVMGetParam(ctx->main_fn,
2795 SI_PARAM_VS_STATE_BITS);
2796 cond = LLVMBuildTrunc(gallivm->builder, cond,
2797 ctx->i1, "");
2798 lp_build_if(&if_ctx, gallivm, cond);
2799 }
2800
2801 for (j = 0; j < 4; j++) {
2802 addr = ctx->outputs[i][j];
2803 val = LLVMBuildLoad(gallivm->builder, addr, "");
2804 val = ac_build_clamp(&ctx->ac, val);
2805 LLVMBuildStore(gallivm->builder, val, addr);
2806 }
2807 }
2808
2809 if (cond)
2810 lp_build_endif(&if_ctx);
2811 }
2812
2813 for (i = 0; i < info->num_outputs; i++) {
2814 outputs[i].semantic_name = info->output_semantic_name[i];
2815 outputs[i].semantic_index = info->output_semantic_index[i];
2816
2817 for (j = 0; j < 4; j++) {
2818 outputs[i].values[j] =
2819 LLVMBuildLoad(gallivm->builder,
2820 ctx->outputs[i][j],
2821 "");
2822 outputs[i].vertex_stream[j] =
2823 (info->output_streams[i] >> (2 * j)) & 3;
2824 }
2825
2826 }
2827
2828 /* Return the primitive ID from the LLVM function. */
2829 ctx->return_value =
2830 LLVMBuildInsertValue(gallivm->builder,
2831 ctx->return_value,
2832 bitcast(bld_base, TGSI_TYPE_FLOAT,
2833 get_primitive_id(bld_base, 0)),
2834 VS_EPILOG_PRIMID_LOC, "");
2835
2836 if (ctx->shader->selector->so.num_outputs)
2837 si_llvm_emit_streamout(ctx, outputs, i, 0);
2838 si_llvm_export_vs(bld_base, outputs, i);
2839 FREE(outputs);
2840 }
2841
2842 struct si_ps_exports {
2843 unsigned num;
2844 struct ac_export_args args[10];
2845 };
2846
2847 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
2848 bool writes_samplemask)
2849 {
2850 if (writes_z) {
2851 /* Z needs 32 bits. */
2852 if (writes_samplemask)
2853 return V_028710_SPI_SHADER_32_ABGR;
2854 else if (writes_stencil)
2855 return V_028710_SPI_SHADER_32_GR;
2856 else
2857 return V_028710_SPI_SHADER_32_R;
2858 } else if (writes_stencil || writes_samplemask) {
2859 /* Both stencil and sample mask need only 16 bits. */
2860 return V_028710_SPI_SHADER_UINT16_ABGR;
2861 } else {
2862 return V_028710_SPI_SHADER_ZERO;
2863 }
2864 }
2865
2866 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2867 LLVMValueRef depth, LLVMValueRef stencil,
2868 LLVMValueRef samplemask, struct si_ps_exports *exp)
2869 {
2870 struct si_shader_context *ctx = si_shader_context(bld_base);
2871 struct lp_build_context *base = &bld_base->base;
2872 struct ac_export_args args;
2873 unsigned mask = 0;
2874 unsigned format = si_get_spi_shader_z_format(depth != NULL,
2875 stencil != NULL,
2876 samplemask != NULL);
2877
2878 assert(depth || stencil || samplemask);
2879
2880 args.valid_mask = 1; /* whether the EXEC mask is valid */
2881 args.done = 1; /* DONE bit */
2882
2883 /* Specify the target we are exporting */
2884 args.target = V_008DFC_SQ_EXP_MRTZ;
2885
2886 args.compr = 0; /* COMP flag */
2887 args.out[0] = base->undef; /* R, depth */
2888 args.out[1] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2889 args.out[2] = base->undef; /* B, sample mask */
2890 args.out[3] = base->undef; /* A, alpha to mask */
2891
2892 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
2893 assert(!depth);
2894 args.compr = 1; /* COMPR flag */
2895
2896 if (stencil) {
2897 /* Stencil should be in X[23:16]. */
2898 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
2899 stencil = LLVMBuildShl(ctx->gallivm.builder, stencil,
2900 LLVMConstInt(ctx->i32, 16, 0), "");
2901 args.out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
2902 mask |= 0x3;
2903 }
2904 if (samplemask) {
2905 /* SampleMask should be in Y[15:0]. */
2906 args.out[1] = samplemask;
2907 mask |= 0xc;
2908 }
2909 } else {
2910 if (depth) {
2911 args.out[0] = depth;
2912 mask |= 0x1;
2913 }
2914 if (stencil) {
2915 args.out[1] = stencil;
2916 mask |= 0x2;
2917 }
2918 if (samplemask) {
2919 args.out[2] = samplemask;
2920 mask |= 0x4;
2921 }
2922 }
2923
2924 /* SI (except OLAND and HAINAN) has a bug that it only looks
2925 * at the X writemask component. */
2926 if (ctx->screen->b.chip_class == SI &&
2927 ctx->screen->b.family != CHIP_OLAND &&
2928 ctx->screen->b.family != CHIP_HAINAN)
2929 mask |= 0x1;
2930
2931 /* Specify which components to enable */
2932 args.enabled_channels = mask;
2933
2934 memcpy(&exp->args[exp->num++], &args, sizeof(args));
2935 }
2936
2937 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2938 LLVMValueRef *color, unsigned index,
2939 unsigned samplemask_param,
2940 bool is_last, struct si_ps_exports *exp)
2941 {
2942 struct si_shader_context *ctx = si_shader_context(bld_base);
2943 struct lp_build_context *base = &bld_base->base;
2944 int i;
2945
2946 /* Clamp color */
2947 if (ctx->shader->key.part.ps.epilog.clamp_color)
2948 for (i = 0; i < 4; i++)
2949 color[i] = ac_build_clamp(&ctx->ac, color[i]);
2950
2951 /* Alpha to one */
2952 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
2953 color[3] = base->one;
2954
2955 /* Alpha test */
2956 if (index == 0 &&
2957 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2958 si_alpha_test(bld_base, color[3]);
2959
2960 /* Line & polygon smoothing */
2961 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
2962 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
2963 samplemask_param);
2964
2965 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2966 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
2967 struct ac_export_args args[8];
2968 int c, last = -1;
2969
2970 /* Get the export arguments, also find out what the last one is. */
2971 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2972 si_llvm_init_export_args(bld_base, color,
2973 V_008DFC_SQ_EXP_MRT + c, &args[c]);
2974 if (args[c].enabled_channels)
2975 last = c;
2976 }
2977
2978 /* Emit all exports. */
2979 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2980 if (is_last && last == c) {
2981 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
2982 args[c].done = 1; /* DONE bit */
2983 } else if (!args[c].enabled_channels)
2984 continue; /* unnecessary NULL export */
2985
2986 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
2987 }
2988 } else {
2989 struct ac_export_args args;
2990
2991 /* Export */
2992 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2993 &args);
2994 if (is_last) {
2995 args.valid_mask = 1; /* whether the EXEC mask is valid */
2996 args.done = 1; /* DONE bit */
2997 } else if (!args.enabled_channels)
2998 return; /* unnecessary NULL export */
2999
3000 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3001 }
3002 }
3003
3004 static void si_emit_ps_exports(struct si_shader_context *ctx,
3005 struct si_ps_exports *exp)
3006 {
3007 for (unsigned i = 0; i < exp->num; i++)
3008 ac_build_export(&ctx->ac, &exp->args[i]);
3009 }
3010
3011 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3012 {
3013 struct si_shader_context *ctx = si_shader_context(bld_base);
3014 struct lp_build_context *base = &bld_base->base;
3015 struct ac_export_args args;
3016
3017 args.enabled_channels = 0x0; /* enabled channels */
3018 args.valid_mask = 1; /* whether the EXEC mask is valid */
3019 args.done = 1; /* DONE bit */
3020 args.target = V_008DFC_SQ_EXP_NULL;
3021 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
3022 args.out[0] = base->undef; /* R */
3023 args.out[1] = base->undef; /* G */
3024 args.out[2] = base->undef; /* B */
3025 args.out[3] = base->undef; /* A */
3026
3027 ac_build_export(&ctx->ac, &args);
3028 }
3029
3030 /**
3031 * Return PS outputs in this order:
3032 *
3033 * v[0:3] = color0.xyzw
3034 * v[4:7] = color1.xyzw
3035 * ...
3036 * vN+0 = Depth
3037 * vN+1 = Stencil
3038 * vN+2 = SampleMask
3039 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3040 *
3041 * The alpha-ref SGPR is returned via its original location.
3042 */
3043 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
3044 {
3045 struct si_shader_context *ctx = si_shader_context(bld_base);
3046 struct si_shader *shader = ctx->shader;
3047 struct tgsi_shader_info *info = &shader->selector->info;
3048 LLVMBuilderRef builder = ctx->gallivm.builder;
3049 unsigned i, j, first_vgpr, vgpr;
3050
3051 LLVMValueRef color[8][4] = {};
3052 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3053 LLVMValueRef ret;
3054
3055 /* Read the output values. */
3056 for (i = 0; i < info->num_outputs; i++) {
3057 unsigned semantic_name = info->output_semantic_name[i];
3058 unsigned semantic_index = info->output_semantic_index[i];
3059
3060 switch (semantic_name) {
3061 case TGSI_SEMANTIC_COLOR:
3062 assert(semantic_index < 8);
3063 for (j = 0; j < 4; j++) {
3064 LLVMValueRef ptr = ctx->outputs[i][j];
3065 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3066 color[semantic_index][j] = result;
3067 }
3068 break;
3069 case TGSI_SEMANTIC_POSITION:
3070 depth = LLVMBuildLoad(builder,
3071 ctx->outputs[i][2], "");
3072 break;
3073 case TGSI_SEMANTIC_STENCIL:
3074 stencil = LLVMBuildLoad(builder,
3075 ctx->outputs[i][1], "");
3076 break;
3077 case TGSI_SEMANTIC_SAMPLEMASK:
3078 samplemask = LLVMBuildLoad(builder,
3079 ctx->outputs[i][0], "");
3080 break;
3081 default:
3082 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3083 semantic_name);
3084 }
3085 }
3086
3087 /* Fill the return structure. */
3088 ret = ctx->return_value;
3089
3090 /* Set SGPRs. */
3091 ret = LLVMBuildInsertValue(builder, ret,
3092 bitcast(bld_base, TGSI_TYPE_SIGNED,
3093 LLVMGetParam(ctx->main_fn,
3094 SI_PARAM_ALPHA_REF)),
3095 SI_SGPR_ALPHA_REF, "");
3096
3097 /* Set VGPRs */
3098 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3099 for (i = 0; i < ARRAY_SIZE(color); i++) {
3100 if (!color[i][0])
3101 continue;
3102
3103 for (j = 0; j < 4; j++)
3104 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3105 }
3106 if (depth)
3107 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3108 if (stencil)
3109 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3110 if (samplemask)
3111 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3112
3113 /* Add the input sample mask for smoothing at the end. */
3114 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3115 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3116 ret = LLVMBuildInsertValue(builder, ret,
3117 LLVMGetParam(ctx->main_fn,
3118 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3119
3120 ctx->return_value = ret;
3121 }
3122
3123 /**
3124 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3125 * buffer in number of elements and return it as an i32.
3126 */
3127 static LLVMValueRef get_buffer_size(
3128 struct lp_build_tgsi_context *bld_base,
3129 LLVMValueRef descriptor)
3130 {
3131 struct si_shader_context *ctx = si_shader_context(bld_base);
3132 struct gallivm_state *gallivm = &ctx->gallivm;
3133 LLVMBuilderRef builder = gallivm->builder;
3134 LLVMValueRef size =
3135 LLVMBuildExtractElement(builder, descriptor,
3136 LLVMConstInt(ctx->i32, 2, 0), "");
3137
3138 if (ctx->screen->b.chip_class == VI) {
3139 /* On VI, the descriptor contains the size in bytes,
3140 * but TXQ must return the size in elements.
3141 * The stride is always non-zero for resources using TXQ.
3142 */
3143 LLVMValueRef stride =
3144 LLVMBuildExtractElement(builder, descriptor,
3145 ctx->i32_1, "");
3146 stride = LLVMBuildLShr(builder, stride,
3147 LLVMConstInt(ctx->i32, 16, 0), "");
3148 stride = LLVMBuildAnd(builder, stride,
3149 LLVMConstInt(ctx->i32, 0x3FFF, 0), "");
3150
3151 size = LLVMBuildUDiv(builder, size, stride, "");
3152 }
3153
3154 return size;
3155 }
3156
3157 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3158 struct lp_build_tgsi_context *bld_base,
3159 struct lp_build_emit_data *emit_data);
3160
3161 /* Prevent optimizations (at least of memory accesses) across the current
3162 * point in the program by emitting empty inline assembly that is marked as
3163 * having side effects.
3164 *
3165 * Optionally, a value can be passed through the inline assembly to prevent
3166 * LLVM from hoisting calls to ReadNone functions.
3167 */
3168 static void emit_optimization_barrier(struct si_shader_context *ctx,
3169 LLVMValueRef *pvgpr)
3170 {
3171 static int counter = 0;
3172
3173 LLVMBuilderRef builder = ctx->gallivm.builder;
3174 char code[16];
3175
3176 snprintf(code, sizeof(code), "; %d", p_atomic_inc_return(&counter));
3177
3178 if (!pvgpr) {
3179 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3180 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, code, "", true, false);
3181 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3182 } else {
3183 LLVMTypeRef ftype = LLVMFunctionType(ctx->i32, &ctx->i32, 1, false);
3184 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, code, "=v,0", true, false);
3185 LLVMValueRef vgpr = *pvgpr;
3186 LLVMTypeRef vgpr_type = LLVMTypeOf(vgpr);
3187 unsigned vgpr_size = llvm_get_type_size(vgpr_type);
3188 LLVMValueRef vgpr0;
3189
3190 assert(vgpr_size % 4 == 0);
3191
3192 vgpr = LLVMBuildBitCast(builder, vgpr, LLVMVectorType(ctx->i32, vgpr_size / 4), "");
3193 vgpr0 = LLVMBuildExtractElement(builder, vgpr, ctx->i32_0, "");
3194 vgpr0 = LLVMBuildCall(builder, inlineasm, &vgpr0, 1, "");
3195 vgpr = LLVMBuildInsertElement(builder, vgpr, vgpr0, ctx->i32_0, "");
3196 vgpr = LLVMBuildBitCast(builder, vgpr, vgpr_type, "");
3197
3198 *pvgpr = vgpr;
3199 }
3200 }
3201
3202 /* Combine these with & instead of |. */
3203 #define NOOP_WAITCNT 0xf7f
3204 #define LGKM_CNT 0x07f
3205 #define VM_CNT 0xf70
3206
3207 static void emit_waitcnt(struct si_shader_context *ctx, unsigned simm16)
3208 {
3209 struct gallivm_state *gallivm = &ctx->gallivm;
3210 LLVMBuilderRef builder = gallivm->builder;
3211 LLVMValueRef args[1] = {
3212 LLVMConstInt(ctx->i32, simm16, 0)
3213 };
3214 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3215 ctx->voidt, args, 1, 0);
3216 }
3217
3218 static void membar_emit(
3219 const struct lp_build_tgsi_action *action,
3220 struct lp_build_tgsi_context *bld_base,
3221 struct lp_build_emit_data *emit_data)
3222 {
3223 struct si_shader_context *ctx = si_shader_context(bld_base);
3224 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3225 unsigned flags = LLVMConstIntGetZExtValue(src0);
3226 unsigned waitcnt = NOOP_WAITCNT;
3227
3228 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3229 waitcnt &= VM_CNT & LGKM_CNT;
3230
3231 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3232 TGSI_MEMBAR_SHADER_BUFFER |
3233 TGSI_MEMBAR_SHADER_IMAGE))
3234 waitcnt &= VM_CNT;
3235
3236 if (flags & TGSI_MEMBAR_SHARED)
3237 waitcnt &= LGKM_CNT;
3238
3239 if (waitcnt != NOOP_WAITCNT)
3240 emit_waitcnt(ctx, waitcnt);
3241 }
3242
3243 static void clock_emit(
3244 const struct lp_build_tgsi_action *action,
3245 struct lp_build_tgsi_context *bld_base,
3246 struct lp_build_emit_data *emit_data)
3247 {
3248 struct si_shader_context *ctx = si_shader_context(bld_base);
3249 struct gallivm_state *gallivm = &ctx->gallivm;
3250 LLVMValueRef tmp;
3251
3252 tmp = lp_build_intrinsic(gallivm->builder, "llvm.readcyclecounter",
3253 ctx->i64, NULL, 0, 0);
3254 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->v2i32, "");
3255
3256 emit_data->output[0] =
3257 LLVMBuildExtractElement(gallivm->builder, tmp, ctx->i32_0, "");
3258 emit_data->output[1] =
3259 LLVMBuildExtractElement(gallivm->builder, tmp, ctx->i32_1, "");
3260 }
3261
3262 static LLVMValueRef
3263 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3264 const struct tgsi_full_src_register *reg)
3265 {
3266 LLVMValueRef index;
3267 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3268 SI_PARAM_SHADER_BUFFERS);
3269
3270 if (!reg->Register.Indirect)
3271 index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
3272 else
3273 index = get_bounded_indirect_index(ctx, &reg->Indirect,
3274 reg->Register.Index,
3275 SI_NUM_SHADER_BUFFERS);
3276
3277 return ac_build_indexed_load_const(&ctx->ac, rsrc_ptr, index);
3278 }
3279
3280 static bool tgsi_is_array_sampler(unsigned target)
3281 {
3282 return target == TGSI_TEXTURE_1D_ARRAY ||
3283 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3284 target == TGSI_TEXTURE_2D_ARRAY ||
3285 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3286 target == TGSI_TEXTURE_CUBE_ARRAY ||
3287 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3288 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3289 }
3290
3291 static bool tgsi_is_array_image(unsigned target)
3292 {
3293 return target == TGSI_TEXTURE_3D ||
3294 target == TGSI_TEXTURE_CUBE ||
3295 target == TGSI_TEXTURE_1D_ARRAY ||
3296 target == TGSI_TEXTURE_2D_ARRAY ||
3297 target == TGSI_TEXTURE_CUBE_ARRAY ||
3298 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3299 }
3300
3301 /**
3302 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3303 *
3304 * At least on Tonga, executing image stores on images with DCC enabled and
3305 * non-trivial can eventually lead to lockups. This can occur when an
3306 * application binds an image as read-only but then uses a shader that writes
3307 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3308 * program termination) in this case, but it doesn't cost much to be a bit
3309 * nicer: disabling DCC in the shader still leads to undefined results but
3310 * avoids the lockup.
3311 */
3312 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3313 LLVMValueRef rsrc)
3314 {
3315 if (ctx->screen->b.chip_class <= CIK) {
3316 return rsrc;
3317 } else {
3318 LLVMBuilderRef builder = ctx->gallivm.builder;
3319 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3320 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3321 LLVMValueRef tmp;
3322
3323 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3324 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3325 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3326 }
3327 }
3328
3329 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3330 {
3331 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3332 CONST_ADDR_SPACE);
3333 }
3334
3335 static LLVMValueRef load_image_desc(struct si_shader_context *ctx,
3336 LLVMValueRef list, LLVMValueRef index,
3337 unsigned target)
3338 {
3339 LLVMBuilderRef builder = ctx->gallivm.builder;
3340
3341 if (target == TGSI_TEXTURE_BUFFER) {
3342 index = LLVMBuildMul(builder, index,
3343 LLVMConstInt(ctx->i32, 2, 0), "");
3344 index = LLVMBuildAdd(builder, index,
3345 ctx->i32_1, "");
3346 list = LLVMBuildPointerCast(builder, list,
3347 const_array(ctx->v4i32, 0), "");
3348 }
3349
3350 return ac_build_indexed_load_const(&ctx->ac, list, index);
3351 }
3352
3353 /**
3354 * Load the resource descriptor for \p image.
3355 */
3356 static void
3357 image_fetch_rsrc(
3358 struct lp_build_tgsi_context *bld_base,
3359 const struct tgsi_full_src_register *image,
3360 bool is_store, unsigned target,
3361 LLVMValueRef *rsrc)
3362 {
3363 struct si_shader_context *ctx = si_shader_context(bld_base);
3364 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3365 SI_PARAM_IMAGES);
3366 LLVMValueRef index;
3367 bool dcc_off = is_store;
3368
3369 assert(image->Register.File == TGSI_FILE_IMAGE);
3370
3371 if (!image->Register.Indirect) {
3372 const struct tgsi_shader_info *info = bld_base->info;
3373 unsigned images_writemask = info->images_store |
3374 info->images_atomic;
3375
3376 index = LLVMConstInt(ctx->i32, image->Register.Index, 0);
3377
3378 if (images_writemask & (1 << image->Register.Index))
3379 dcc_off = true;
3380 } else {
3381 /* From the GL_ARB_shader_image_load_store extension spec:
3382 *
3383 * If a shader performs an image load, store, or atomic
3384 * operation using an image variable declared as an array,
3385 * and if the index used to select an individual element is
3386 * negative or greater than or equal to the size of the
3387 * array, the results of the operation are undefined but may
3388 * not lead to termination.
3389 */
3390 index = get_bounded_indirect_index(ctx, &image->Indirect,
3391 image->Register.Index,
3392 SI_NUM_IMAGES);
3393 }
3394
3395 *rsrc = load_image_desc(ctx, rsrc_ptr, index, target);
3396 if (dcc_off && target != TGSI_TEXTURE_BUFFER)
3397 *rsrc = force_dcc_off(ctx, *rsrc);
3398 }
3399
3400 static LLVMValueRef image_fetch_coords(
3401 struct lp_build_tgsi_context *bld_base,
3402 const struct tgsi_full_instruction *inst,
3403 unsigned src, LLVMValueRef desc)
3404 {
3405 struct si_shader_context *ctx = si_shader_context(bld_base);
3406 struct gallivm_state *gallivm = &ctx->gallivm;
3407 LLVMBuilderRef builder = gallivm->builder;
3408 unsigned target = inst->Memory.Texture;
3409 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3410 LLVMValueRef coords[4];
3411 LLVMValueRef tmp;
3412 int chan;
3413
3414 for (chan = 0; chan < num_coords; ++chan) {
3415 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3416 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
3417 coords[chan] = tmp;
3418 }
3419
3420 if (ctx->screen->b.chip_class >= GFX9) {
3421 /* 1D textures are allocated and used as 2D on GFX9. */
3422 if (target == TGSI_TEXTURE_1D) {
3423 coords[1] = ctx->i32_0;
3424 num_coords++;
3425 } else if (target == TGSI_TEXTURE_1D_ARRAY) {
3426 coords[2] = coords[1];
3427 coords[1] = ctx->i32_0;
3428 num_coords++;
3429 } else if (target == TGSI_TEXTURE_2D) {
3430 /* The hw can't bind a slice of a 3D image as a 2D
3431 * image, because it ignores BASE_ARRAY if the target
3432 * is 3D. The workaround is to read BASE_ARRAY and set
3433 * it as the 3rd address operand for all 2D images.
3434 */
3435 LLVMValueRef first_layer, const5, mask;
3436
3437 const5 = LLVMConstInt(ctx->i32, 5, 0);
3438 mask = LLVMConstInt(ctx->i32, S_008F24_BASE_ARRAY(~0), 0);
3439 first_layer = LLVMBuildExtractElement(builder, desc, const5, "");
3440 first_layer = LLVMBuildAnd(builder, first_layer, mask, "");
3441
3442 coords[2] = first_layer;
3443 num_coords++;
3444 }
3445 }
3446
3447 if (num_coords == 1)
3448 return coords[0];
3449
3450 if (num_coords == 3) {
3451 /* LLVM has difficulties lowering 3-element vectors. */
3452 coords[3] = bld_base->uint_bld.undef;
3453 num_coords = 4;
3454 }
3455
3456 return lp_build_gather_values(gallivm, coords, num_coords);
3457 }
3458
3459 /**
3460 * Append the extra mode bits that are used by image load and store.
3461 */
3462 static void image_append_args(
3463 struct si_shader_context *ctx,
3464 struct lp_build_emit_data * emit_data,
3465 unsigned target,
3466 bool atomic,
3467 bool force_glc)
3468 {
3469 const struct tgsi_full_instruction *inst = emit_data->inst;
3470 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3471 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3472 LLVMValueRef r128 = i1false;
3473 LLVMValueRef da = tgsi_is_array_image(target) ? i1true : i1false;
3474 LLVMValueRef glc =
3475 force_glc ||
3476 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3477 i1true : i1false;
3478 LLVMValueRef slc = i1false;
3479 LLVMValueRef lwe = i1false;
3480
3481 if (atomic || (HAVE_LLVM <= 0x0309)) {
3482 emit_data->args[emit_data->arg_count++] = r128;
3483 emit_data->args[emit_data->arg_count++] = da;
3484 if (!atomic) {
3485 emit_data->args[emit_data->arg_count++] = glc;
3486 }
3487 emit_data->args[emit_data->arg_count++] = slc;
3488 return;
3489 }
3490
3491 /* HAVE_LLVM >= 0x0400 */
3492 emit_data->args[emit_data->arg_count++] = glc;
3493 emit_data->args[emit_data->arg_count++] = slc;
3494 emit_data->args[emit_data->arg_count++] = lwe;
3495 emit_data->args[emit_data->arg_count++] = da;
3496 }
3497
3498 /**
3499 * Append the resource and indexing arguments for buffer intrinsics.
3500 *
3501 * \param rsrc the v4i32 buffer resource
3502 * \param index index into the buffer (stride-based)
3503 * \param offset byte offset into the buffer
3504 */
3505 static void buffer_append_args(
3506 struct si_shader_context *ctx,
3507 struct lp_build_emit_data *emit_data,
3508 LLVMValueRef rsrc,
3509 LLVMValueRef index,
3510 LLVMValueRef offset,
3511 bool atomic,
3512 bool force_glc)
3513 {
3514 const struct tgsi_full_instruction *inst = emit_data->inst;
3515 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3516 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3517
3518 emit_data->args[emit_data->arg_count++] = rsrc;
3519 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3520 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3521 if (!atomic) {
3522 emit_data->args[emit_data->arg_count++] =
3523 force_glc ||
3524 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3525 i1true : i1false; /* glc */
3526 }
3527 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3528 }
3529
3530 static void load_fetch_args(
3531 struct lp_build_tgsi_context * bld_base,
3532 struct lp_build_emit_data * emit_data)
3533 {
3534 struct si_shader_context *ctx = si_shader_context(bld_base);
3535 struct gallivm_state *gallivm = &ctx->gallivm;
3536 const struct tgsi_full_instruction * inst = emit_data->inst;
3537 unsigned target = inst->Memory.Texture;
3538 LLVMValueRef rsrc;
3539
3540 emit_data->dst_type = ctx->v4f32;
3541
3542 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3543 LLVMBuilderRef builder = gallivm->builder;
3544 LLVMValueRef offset;
3545 LLVMValueRef tmp;
3546
3547 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3548
3549 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3550 offset = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
3551
3552 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
3553 offset, false, false);
3554 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3555 LLVMValueRef coords;
3556
3557 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
3558 coords = image_fetch_coords(bld_base, inst, 1, rsrc);
3559
3560 if (target == TGSI_TEXTURE_BUFFER) {
3561 buffer_append_args(ctx, emit_data, rsrc, coords,
3562 ctx->i32_0, false, false);
3563 } else {
3564 emit_data->args[0] = coords;
3565 emit_data->args[1] = rsrc;
3566 emit_data->args[2] = LLVMConstInt(ctx->i32, 15, 0); /* dmask */
3567 emit_data->arg_count = 3;
3568
3569 image_append_args(ctx, emit_data, target, false, false);
3570 }
3571 }
3572 }
3573
3574 static unsigned get_load_intr_attribs(bool readonly_memory)
3575 {
3576 /* READNONE means writes can't affect it, while READONLY means that
3577 * writes can affect it. */
3578 return readonly_memory && HAVE_LLVM >= 0x0400 ?
3579 LP_FUNC_ATTR_READNONE :
3580 LP_FUNC_ATTR_READONLY;
3581 }
3582
3583 static unsigned get_store_intr_attribs(bool writeonly_memory)
3584 {
3585 return writeonly_memory && HAVE_LLVM >= 0x0400 ?
3586 LP_FUNC_ATTR_INACCESSIBLE_MEM_ONLY :
3587 LP_FUNC_ATTR_WRITEONLY;
3588 }
3589
3590 static void load_emit_buffer(struct si_shader_context *ctx,
3591 struct lp_build_emit_data *emit_data,
3592 bool readonly_memory)
3593 {
3594 const struct tgsi_full_instruction *inst = emit_data->inst;
3595 struct gallivm_state *gallivm = &ctx->gallivm;
3596 LLVMBuilderRef builder = gallivm->builder;
3597 uint writemask = inst->Dst[0].Register.WriteMask;
3598 uint count = util_last_bit(writemask);
3599 const char *intrinsic_name;
3600 LLVMTypeRef dst_type;
3601
3602 switch (count) {
3603 case 1:
3604 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3605 dst_type = ctx->f32;
3606 break;
3607 case 2:
3608 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3609 dst_type = LLVMVectorType(ctx->f32, 2);
3610 break;
3611 default: // 3 & 4
3612 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3613 dst_type = ctx->v4f32;
3614 count = 4;
3615 }
3616
3617 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3618 builder, intrinsic_name, dst_type,
3619 emit_data->args, emit_data->arg_count,
3620 get_load_intr_attribs(readonly_memory));
3621 }
3622
3623 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3624 const struct tgsi_full_instruction *inst,
3625 LLVMTypeRef type, int arg)
3626 {
3627 struct gallivm_state *gallivm = &ctx->gallivm;
3628 LLVMBuilderRef builder = gallivm->builder;
3629 LLVMValueRef offset, ptr;
3630 int addr_space;
3631
3632 offset = lp_build_emit_fetch(&ctx->bld_base, inst, arg, 0);
3633 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3634
3635 ptr = ctx->shared_memory;
3636 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3637 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3638 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3639
3640 return ptr;
3641 }
3642
3643 static void load_emit_memory(
3644 struct si_shader_context *ctx,
3645 struct lp_build_emit_data *emit_data)
3646 {
3647 const struct tgsi_full_instruction *inst = emit_data->inst;
3648 struct gallivm_state *gallivm = &ctx->gallivm;
3649 LLVMBuilderRef builder = gallivm->builder;
3650 unsigned writemask = inst->Dst[0].Register.WriteMask;
3651 LLVMValueRef channels[4], ptr, derived_ptr, index;
3652 int chan;
3653
3654 ptr = get_memory_ptr(ctx, inst, ctx->f32, 1);
3655
3656 for (chan = 0; chan < 4; ++chan) {
3657 if (!(writemask & (1 << chan))) {
3658 channels[chan] = LLVMGetUndef(ctx->f32);
3659 continue;
3660 }
3661
3662 index = LLVMConstInt(ctx->i32, chan, 0);
3663 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3664 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3665 }
3666 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3667 }
3668
3669 /**
3670 * Return true if the memory accessed by a LOAD or STORE instruction is
3671 * read-only or write-only, respectively.
3672 *
3673 * \param shader_buffers_reverse_access_mask
3674 * For LOAD, set this to (store | atomic) slot usage in the shader.
3675 * For STORE, set this to (load | atomic) slot usage in the shader.
3676 * \param images_reverse_access_mask Same as above, but for images.
3677 */
3678 static bool is_oneway_access_only(const struct tgsi_full_instruction *inst,
3679 const struct tgsi_shader_info *info,
3680 unsigned shader_buffers_reverse_access_mask,
3681 unsigned images_reverse_access_mask)
3682 {
3683 /* RESTRICT means NOALIAS.
3684 * If there are no writes, we can assume the accessed memory is read-only.
3685 * If there are no reads, we can assume the accessed memory is write-only.
3686 */
3687 if (inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT) {
3688 unsigned reverse_access_mask;
3689
3690 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3691 reverse_access_mask = shader_buffers_reverse_access_mask;
3692 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3693 reverse_access_mask = info->images_buffers &
3694 images_reverse_access_mask;
3695 } else {
3696 reverse_access_mask = ~info->images_buffers &
3697 images_reverse_access_mask;
3698 }
3699
3700 if (inst->Src[0].Register.Indirect) {
3701 if (!reverse_access_mask)
3702 return true;
3703 } else {
3704 if (!(reverse_access_mask &
3705 (1u << inst->Src[0].Register.Index)))
3706 return true;
3707 }
3708 }
3709
3710 /* If there are no buffer writes (for both shader buffers & image
3711 * buffers), it implies that buffer memory is read-only.
3712 * If there are no buffer reads (for both shader buffers & image
3713 * buffers), it implies that buffer memory is write-only.
3714 *
3715 * Same for the case when there are no writes/reads for non-buffer
3716 * images.
3717 */
3718 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
3719 (inst->Src[0].Register.File == TGSI_FILE_IMAGE &&
3720 inst->Memory.Texture == TGSI_TEXTURE_BUFFER)) {
3721 if (!shader_buffers_reverse_access_mask &&
3722 !(info->images_buffers & images_reverse_access_mask))
3723 return true;
3724 } else {
3725 if (!(~info->images_buffers & images_reverse_access_mask))
3726 return true;
3727 }
3728 return false;
3729 }
3730
3731 static void load_emit(
3732 const struct lp_build_tgsi_action *action,
3733 struct lp_build_tgsi_context *bld_base,
3734 struct lp_build_emit_data *emit_data)
3735 {
3736 struct si_shader_context *ctx = si_shader_context(bld_base);
3737 struct gallivm_state *gallivm = &ctx->gallivm;
3738 LLVMBuilderRef builder = gallivm->builder;
3739 const struct tgsi_full_instruction * inst = emit_data->inst;
3740 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
3741 char intrinsic_name[64];
3742 bool readonly_memory = false;
3743
3744 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3745 load_emit_memory(ctx, emit_data);
3746 return;
3747 }
3748
3749 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3750 emit_waitcnt(ctx, VM_CNT);
3751
3752 readonly_memory = !(inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE) &&
3753 is_oneway_access_only(inst, info,
3754 info->shader_buffers_store |
3755 info->shader_buffers_atomic,
3756 info->images_store |
3757 info->images_atomic);
3758
3759 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3760 load_emit_buffer(ctx, emit_data, readonly_memory);
3761 return;
3762 }
3763
3764 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3765 emit_data->output[emit_data->chan] =
3766 lp_build_intrinsic(
3767 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3768 emit_data->args, emit_data->arg_count,
3769 get_load_intr_attribs(readonly_memory));
3770 } else {
3771 ac_get_image_intr_name("llvm.amdgcn.image.load",
3772 emit_data->dst_type, /* vdata */
3773 LLVMTypeOf(emit_data->args[0]), /* coords */
3774 LLVMTypeOf(emit_data->args[1]), /* rsrc */
3775 intrinsic_name, sizeof(intrinsic_name));
3776
3777 emit_data->output[emit_data->chan] =
3778 lp_build_intrinsic(
3779 builder, intrinsic_name, emit_data->dst_type,
3780 emit_data->args, emit_data->arg_count,
3781 get_load_intr_attribs(readonly_memory));
3782 }
3783 }
3784
3785 static void store_fetch_args(
3786 struct lp_build_tgsi_context * bld_base,
3787 struct lp_build_emit_data * emit_data)
3788 {
3789 struct si_shader_context *ctx = si_shader_context(bld_base);
3790 struct gallivm_state *gallivm = &ctx->gallivm;
3791 LLVMBuilderRef builder = gallivm->builder;
3792 const struct tgsi_full_instruction * inst = emit_data->inst;
3793 struct tgsi_full_src_register memory;
3794 LLVMValueRef chans[4];
3795 LLVMValueRef data;
3796 LLVMValueRef rsrc;
3797 unsigned chan;
3798
3799 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3800
3801 for (chan = 0; chan < 4; ++chan) {
3802 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3803 }
3804 data = lp_build_gather_values(gallivm, chans, 4);
3805
3806 emit_data->args[emit_data->arg_count++] = data;
3807
3808 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3809
3810 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3811 LLVMValueRef offset;
3812 LLVMValueRef tmp;
3813
3814 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3815
3816 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3817 offset = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
3818
3819 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
3820 offset, false, false);
3821 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3822 unsigned target = inst->Memory.Texture;
3823 LLVMValueRef coords;
3824
3825 /* 8bit/16bit TC L1 write corruption bug on SI.
3826 * All store opcodes not aligned to a dword are affected.
3827 *
3828 * The only way to get unaligned stores in radeonsi is through
3829 * shader images.
3830 */
3831 bool force_glc = ctx->screen->b.chip_class == SI;
3832
3833 image_fetch_rsrc(bld_base, &memory, true, target, &rsrc);
3834 coords = image_fetch_coords(bld_base, inst, 0, rsrc);
3835
3836 if (target == TGSI_TEXTURE_BUFFER) {
3837 buffer_append_args(ctx, emit_data, rsrc, coords,
3838 ctx->i32_0, false, force_glc);
3839 } else {
3840 emit_data->args[1] = coords;
3841 emit_data->args[2] = rsrc;
3842 emit_data->args[3] = LLVMConstInt(ctx->i32, 15, 0); /* dmask */
3843 emit_data->arg_count = 4;
3844
3845 image_append_args(ctx, emit_data, target, false, force_glc);
3846 }
3847 }
3848 }
3849
3850 static void store_emit_buffer(
3851 struct si_shader_context *ctx,
3852 struct lp_build_emit_data *emit_data,
3853 bool writeonly_memory)
3854 {
3855 const struct tgsi_full_instruction *inst = emit_data->inst;
3856 struct gallivm_state *gallivm = &ctx->gallivm;
3857 LLVMBuilderRef builder = gallivm->builder;
3858 LLVMValueRef base_data = emit_data->args[0];
3859 LLVMValueRef base_offset = emit_data->args[3];
3860 unsigned writemask = inst->Dst[0].Register.WriteMask;
3861
3862 while (writemask) {
3863 int start, count;
3864 const char *intrinsic_name;
3865 LLVMValueRef data;
3866 LLVMValueRef offset;
3867 LLVMValueRef tmp;
3868
3869 u_bit_scan_consecutive_range(&writemask, &start, &count);
3870
3871 /* Due to an LLVM limitation, split 3-element writes
3872 * into a 2-element and a 1-element write. */
3873 if (count == 3) {
3874 writemask |= 1 << (start + 2);
3875 count = 2;
3876 }
3877
3878 if (count == 4) {
3879 data = base_data;
3880 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3881 } else if (count == 2) {
3882 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3883
3884 tmp = LLVMBuildExtractElement(
3885 builder, base_data,
3886 LLVMConstInt(ctx->i32, start, 0), "");
3887 data = LLVMBuildInsertElement(
3888 builder, LLVMGetUndef(v2f32), tmp,
3889 ctx->i32_0, "");
3890
3891 tmp = LLVMBuildExtractElement(
3892 builder, base_data,
3893 LLVMConstInt(ctx->i32, start + 1, 0), "");
3894 data = LLVMBuildInsertElement(
3895 builder, data, tmp, ctx->i32_1, "");
3896
3897 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3898 } else {
3899 assert(count == 1);
3900 data = LLVMBuildExtractElement(
3901 builder, base_data,
3902 LLVMConstInt(ctx->i32, start, 0), "");
3903 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3904 }
3905
3906 offset = base_offset;
3907 if (start != 0) {
3908 offset = LLVMBuildAdd(
3909 builder, offset,
3910 LLVMConstInt(ctx->i32, start * 4, 0), "");
3911 }
3912
3913 emit_data->args[0] = data;
3914 emit_data->args[3] = offset;
3915
3916 lp_build_intrinsic(
3917 builder, intrinsic_name, emit_data->dst_type,
3918 emit_data->args, emit_data->arg_count,
3919 get_store_intr_attribs(writeonly_memory));
3920 }
3921 }
3922
3923 static void store_emit_memory(
3924 struct si_shader_context *ctx,
3925 struct lp_build_emit_data *emit_data)
3926 {
3927 const struct tgsi_full_instruction *inst = emit_data->inst;
3928 struct gallivm_state *gallivm = &ctx->gallivm;
3929 LLVMBuilderRef builder = gallivm->builder;
3930 unsigned writemask = inst->Dst[0].Register.WriteMask;
3931 LLVMValueRef ptr, derived_ptr, data, index;
3932 int chan;
3933
3934 ptr = get_memory_ptr(ctx, inst, ctx->f32, 0);
3935
3936 for (chan = 0; chan < 4; ++chan) {
3937 if (!(writemask & (1 << chan))) {
3938 continue;
3939 }
3940 data = lp_build_emit_fetch(&ctx->bld_base, inst, 1, chan);
3941 index = LLVMConstInt(ctx->i32, chan, 0);
3942 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3943 LLVMBuildStore(builder, data, derived_ptr);
3944 }
3945 }
3946
3947 static void store_emit(
3948 const struct lp_build_tgsi_action *action,
3949 struct lp_build_tgsi_context *bld_base,
3950 struct lp_build_emit_data *emit_data)
3951 {
3952 struct si_shader_context *ctx = si_shader_context(bld_base);
3953 struct gallivm_state *gallivm = &ctx->gallivm;
3954 LLVMBuilderRef builder = gallivm->builder;
3955 const struct tgsi_full_instruction * inst = emit_data->inst;
3956 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
3957 unsigned target = inst->Memory.Texture;
3958 char intrinsic_name[64];
3959 bool writeonly_memory = false;
3960
3961 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3962 store_emit_memory(ctx, emit_data);
3963 return;
3964 }
3965
3966 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3967 emit_waitcnt(ctx, VM_CNT);
3968
3969 writeonly_memory = is_oneway_access_only(inst, info,
3970 info->shader_buffers_load |
3971 info->shader_buffers_atomic,
3972 info->images_load |
3973 info->images_atomic);
3974
3975 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3976 store_emit_buffer(ctx, emit_data, writeonly_memory);
3977 return;
3978 }
3979
3980 if (target == TGSI_TEXTURE_BUFFER) {
3981 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3982 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3983 emit_data->dst_type, emit_data->args,
3984 emit_data->arg_count,
3985 get_store_intr_attribs(writeonly_memory));
3986 } else {
3987 ac_get_image_intr_name("llvm.amdgcn.image.store",
3988 LLVMTypeOf(emit_data->args[0]), /* vdata */
3989 LLVMTypeOf(emit_data->args[1]), /* coords */
3990 LLVMTypeOf(emit_data->args[2]), /* rsrc */
3991 intrinsic_name, sizeof(intrinsic_name));
3992
3993 emit_data->output[emit_data->chan] =
3994 lp_build_intrinsic(
3995 builder, intrinsic_name, emit_data->dst_type,
3996 emit_data->args, emit_data->arg_count,
3997 get_store_intr_attribs(writeonly_memory));
3998 }
3999 }
4000
4001 static void atomic_fetch_args(
4002 struct lp_build_tgsi_context * bld_base,
4003 struct lp_build_emit_data * emit_data)
4004 {
4005 struct si_shader_context *ctx = si_shader_context(bld_base);
4006 struct gallivm_state *gallivm = &ctx->gallivm;
4007 LLVMBuilderRef builder = gallivm->builder;
4008 const struct tgsi_full_instruction * inst = emit_data->inst;
4009 LLVMValueRef data1, data2;
4010 LLVMValueRef rsrc;
4011 LLVMValueRef tmp;
4012
4013 emit_data->dst_type = ctx->f32;
4014
4015 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
4016 data1 = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4017
4018 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4019 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
4020 data2 = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4021 }
4022
4023 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
4024 * of arguments, which is reversed relative to TGSI (and GLSL)
4025 */
4026 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4027 emit_data->args[emit_data->arg_count++] = data2;
4028 emit_data->args[emit_data->arg_count++] = data1;
4029
4030 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4031 LLVMValueRef offset;
4032
4033 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
4034
4035 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
4036 offset = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4037
4038 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
4039 offset, true, false);
4040 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
4041 unsigned target = inst->Memory.Texture;
4042 LLVMValueRef coords;
4043
4044 image_fetch_rsrc(bld_base, &inst->Src[0], true, target, &rsrc);
4045 coords = image_fetch_coords(bld_base, inst, 1, rsrc);
4046
4047 if (target == TGSI_TEXTURE_BUFFER) {
4048 buffer_append_args(ctx, emit_data, rsrc, coords,
4049 ctx->i32_0, true, false);
4050 } else {
4051 emit_data->args[emit_data->arg_count++] = coords;
4052 emit_data->args[emit_data->arg_count++] = rsrc;
4053
4054 image_append_args(ctx, emit_data, target, true, false);
4055 }
4056 }
4057 }
4058
4059 static void atomic_emit_memory(struct si_shader_context *ctx,
4060 struct lp_build_emit_data *emit_data) {
4061 struct gallivm_state *gallivm = &ctx->gallivm;
4062 LLVMBuilderRef builder = gallivm->builder;
4063 const struct tgsi_full_instruction * inst = emit_data->inst;
4064 LLVMValueRef ptr, result, arg;
4065
4066 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
4067
4068 arg = lp_build_emit_fetch(&ctx->bld_base, inst, 2, 0);
4069 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
4070
4071 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4072 LLVMValueRef new_data;
4073 new_data = lp_build_emit_fetch(&ctx->bld_base,
4074 inst, 3, 0);
4075
4076 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
4077
4078 #if HAVE_LLVM >= 0x309
4079 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
4080 LLVMAtomicOrderingSequentiallyConsistent,
4081 LLVMAtomicOrderingSequentiallyConsistent,
4082 false);
4083 #endif
4084
4085 result = LLVMBuildExtractValue(builder, result, 0, "");
4086 } else {
4087 LLVMAtomicRMWBinOp op;
4088
4089 switch(inst->Instruction.Opcode) {
4090 case TGSI_OPCODE_ATOMUADD:
4091 op = LLVMAtomicRMWBinOpAdd;
4092 break;
4093 case TGSI_OPCODE_ATOMXCHG:
4094 op = LLVMAtomicRMWBinOpXchg;
4095 break;
4096 case TGSI_OPCODE_ATOMAND:
4097 op = LLVMAtomicRMWBinOpAnd;
4098 break;
4099 case TGSI_OPCODE_ATOMOR:
4100 op = LLVMAtomicRMWBinOpOr;
4101 break;
4102 case TGSI_OPCODE_ATOMXOR:
4103 op = LLVMAtomicRMWBinOpXor;
4104 break;
4105 case TGSI_OPCODE_ATOMUMIN:
4106 op = LLVMAtomicRMWBinOpUMin;
4107 break;
4108 case TGSI_OPCODE_ATOMUMAX:
4109 op = LLVMAtomicRMWBinOpUMax;
4110 break;
4111 case TGSI_OPCODE_ATOMIMIN:
4112 op = LLVMAtomicRMWBinOpMin;
4113 break;
4114 case TGSI_OPCODE_ATOMIMAX:
4115 op = LLVMAtomicRMWBinOpMax;
4116 break;
4117 default:
4118 unreachable("unknown atomic opcode");
4119 }
4120
4121 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
4122 LLVMAtomicOrderingSequentiallyConsistent,
4123 false);
4124 }
4125 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
4126 }
4127
4128 static void atomic_emit(
4129 const struct lp_build_tgsi_action *action,
4130 struct lp_build_tgsi_context *bld_base,
4131 struct lp_build_emit_data *emit_data)
4132 {
4133 struct si_shader_context *ctx = si_shader_context(bld_base);
4134 struct gallivm_state *gallivm = &ctx->gallivm;
4135 LLVMBuilderRef builder = gallivm->builder;
4136 const struct tgsi_full_instruction * inst = emit_data->inst;
4137 char intrinsic_name[40];
4138 LLVMValueRef tmp;
4139
4140 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
4141 atomic_emit_memory(ctx, emit_data);
4142 return;
4143 }
4144
4145 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
4146 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4147 snprintf(intrinsic_name, sizeof(intrinsic_name),
4148 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
4149 } else {
4150 LLVMValueRef coords;
4151 char coords_type[8];
4152
4153 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4154 coords = emit_data->args[2];
4155 else
4156 coords = emit_data->args[1];
4157
4158 ac_build_type_name_for_intr(LLVMTypeOf(coords), coords_type, sizeof(coords_type));
4159 snprintf(intrinsic_name, sizeof(intrinsic_name),
4160 "llvm.amdgcn.image.atomic.%s.%s",
4161 action->intr_name, coords_type);
4162 }
4163
4164 tmp = lp_build_intrinsic(
4165 builder, intrinsic_name, ctx->i32,
4166 emit_data->args, emit_data->arg_count, 0);
4167 emit_data->output[emit_data->chan] =
4168 LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4169 }
4170
4171 static void set_tex_fetch_args(struct si_shader_context *ctx,
4172 struct lp_build_emit_data *emit_data,
4173 unsigned target,
4174 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4175 LLVMValueRef *param, unsigned count,
4176 unsigned dmask)
4177 {
4178 struct gallivm_state *gallivm = &ctx->gallivm;
4179 struct ac_image_args args = {};
4180
4181 /* Pad to power of two vector */
4182 while (count < util_next_power_of_two(count))
4183 param[count++] = LLVMGetUndef(ctx->i32);
4184
4185 if (count > 1)
4186 args.addr = lp_build_gather_values(gallivm, param, count);
4187 else
4188 args.addr = param[0];
4189
4190 args.resource = res_ptr;
4191 args.sampler = samp_ptr;
4192 args.dmask = dmask;
4193 args.unorm = target == TGSI_TEXTURE_RECT ||
4194 target == TGSI_TEXTURE_SHADOWRECT;
4195 args.da = tgsi_is_array_sampler(target);
4196
4197 /* Ugly, but we seem to have no other choice right now. */
4198 STATIC_ASSERT(sizeof(args) <= sizeof(emit_data->args));
4199 memcpy(emit_data->args, &args, sizeof(args));
4200 }
4201
4202 static LLVMValueRef fix_resinfo(struct si_shader_context *ctx,
4203 unsigned target, LLVMValueRef out)
4204 {
4205 LLVMBuilderRef builder = ctx->gallivm.builder;
4206
4207 /* 1D textures are allocated and used as 2D on GFX9. */
4208 if (ctx->screen->b.chip_class >= GFX9 &&
4209 (target == TGSI_TEXTURE_1D_ARRAY ||
4210 target == TGSI_TEXTURE_SHADOW1D_ARRAY)) {
4211 LLVMValueRef layers =
4212 LLVMBuildExtractElement(builder, out,
4213 LLVMConstInt(ctx->i32, 2, 0), "");
4214 out = LLVMBuildInsertElement(builder, out, layers,
4215 ctx->i32_1, "");
4216 }
4217
4218 /* Divide the number of layers by 6 to get the number of cubes. */
4219 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4220 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4221 LLVMValueRef imm2 = LLVMConstInt(ctx->i32, 2, 0);
4222
4223 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4224 z = LLVMBuildSDiv(builder, z, LLVMConstInt(ctx->i32, 6, 0), "");
4225
4226 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4227 }
4228 return out;
4229 }
4230
4231 static void resq_fetch_args(
4232 struct lp_build_tgsi_context * bld_base,
4233 struct lp_build_emit_data * emit_data)
4234 {
4235 struct si_shader_context *ctx = si_shader_context(bld_base);
4236 const struct tgsi_full_instruction *inst = emit_data->inst;
4237 const struct tgsi_full_src_register *reg = &inst->Src[0];
4238
4239 emit_data->dst_type = ctx->v4i32;
4240
4241 if (reg->Register.File == TGSI_FILE_BUFFER) {
4242 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4243 emit_data->arg_count = 1;
4244 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4245 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4246 &emit_data->args[0]);
4247 emit_data->arg_count = 1;
4248 } else {
4249 LLVMValueRef res_ptr;
4250 unsigned image_target;
4251
4252 if (inst->Memory.Texture == TGSI_TEXTURE_3D)
4253 image_target = TGSI_TEXTURE_2D_ARRAY;
4254 else
4255 image_target = inst->Memory.Texture;
4256
4257 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4258 &res_ptr);
4259 set_tex_fetch_args(ctx, emit_data, image_target,
4260 res_ptr, NULL, &ctx->i32_0, 1,
4261 0xf);
4262 }
4263 }
4264
4265 static void resq_emit(
4266 const struct lp_build_tgsi_action *action,
4267 struct lp_build_tgsi_context *bld_base,
4268 struct lp_build_emit_data *emit_data)
4269 {
4270 struct si_shader_context *ctx = si_shader_context(bld_base);
4271 struct gallivm_state *gallivm = &ctx->gallivm;
4272 LLVMBuilderRef builder = gallivm->builder;
4273 const struct tgsi_full_instruction *inst = emit_data->inst;
4274 LLVMValueRef out;
4275
4276 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4277 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4278 LLVMConstInt(ctx->i32, 2, 0), "");
4279 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4280 out = get_buffer_size(bld_base, emit_data->args[0]);
4281 } else {
4282 struct ac_image_args args;
4283
4284 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
4285 args.opcode = ac_image_get_resinfo;
4286 out = ac_build_image_opcode(&ctx->ac, &args);
4287
4288 out = fix_resinfo(ctx, inst->Memory.Texture, out);
4289 }
4290
4291 emit_data->output[emit_data->chan] = out;
4292 }
4293
4294 static const struct lp_build_tgsi_action tex_action;
4295
4296 enum desc_type {
4297 DESC_IMAGE,
4298 DESC_BUFFER,
4299 DESC_FMASK,
4300 DESC_SAMPLER,
4301 };
4302
4303 /**
4304 * Load an image view, fmask view. or sampler state descriptor.
4305 */
4306 static LLVMValueRef load_sampler_desc(struct si_shader_context *ctx,
4307 LLVMValueRef list, LLVMValueRef index,
4308 enum desc_type type)
4309 {
4310 struct gallivm_state *gallivm = &ctx->gallivm;
4311 LLVMBuilderRef builder = gallivm->builder;
4312
4313 switch (type) {
4314 case DESC_IMAGE:
4315 /* The image is at [0:7]. */
4316 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4317 break;
4318 case DESC_BUFFER:
4319 /* The buffer is in [4:7]. */
4320 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4321 index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
4322 list = LLVMBuildPointerCast(builder, list,
4323 const_array(ctx->v4i32, 0), "");
4324 break;
4325 case DESC_FMASK:
4326 /* The FMASK is at [8:15]. */
4327 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4328 index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
4329 break;
4330 case DESC_SAMPLER:
4331 /* The sampler state is at [12:15]. */
4332 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4333 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4334 list = LLVMBuildPointerCast(builder, list,
4335 const_array(ctx->v4i32, 0), "");
4336 break;
4337 }
4338
4339 return ac_build_indexed_load_const(&ctx->ac, list, index);
4340 }
4341
4342 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4343 *
4344 * SI-CI:
4345 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4346 * filtering manually. The driver sets img7 to a mask clearing
4347 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4348 * s_and_b32 samp0, samp0, img7
4349 *
4350 * VI:
4351 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4352 */
4353 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4354 LLVMValueRef res, LLVMValueRef samp)
4355 {
4356 LLVMBuilderRef builder = ctx->gallivm.builder;
4357 LLVMValueRef img7, samp0;
4358
4359 if (ctx->screen->b.chip_class >= VI)
4360 return samp;
4361
4362 img7 = LLVMBuildExtractElement(builder, res,
4363 LLVMConstInt(ctx->i32, 7, 0), "");
4364 samp0 = LLVMBuildExtractElement(builder, samp,
4365 ctx->i32_0, "");
4366 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4367 return LLVMBuildInsertElement(builder, samp, samp0,
4368 ctx->i32_0, "");
4369 }
4370
4371 static void tex_fetch_ptrs(
4372 struct lp_build_tgsi_context *bld_base,
4373 struct lp_build_emit_data *emit_data,
4374 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4375 {
4376 struct si_shader_context *ctx = si_shader_context(bld_base);
4377 LLVMValueRef list = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLERS);
4378 const struct tgsi_full_instruction *inst = emit_data->inst;
4379 const struct tgsi_full_src_register *reg;
4380 unsigned target = inst->Texture.Texture;
4381 unsigned sampler_src;
4382 LLVMValueRef index;
4383
4384 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4385 reg = &emit_data->inst->Src[sampler_src];
4386
4387 if (reg->Register.Indirect) {
4388 index = get_bounded_indirect_index(ctx,
4389 &reg->Indirect,
4390 reg->Register.Index,
4391 SI_NUM_SAMPLERS);
4392 } else {
4393 index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
4394 }
4395
4396 if (target == TGSI_TEXTURE_BUFFER)
4397 *res_ptr = load_sampler_desc(ctx, list, index, DESC_BUFFER);
4398 else
4399 *res_ptr = load_sampler_desc(ctx, list, index, DESC_IMAGE);
4400
4401 if (samp_ptr)
4402 *samp_ptr = NULL;
4403 if (fmask_ptr)
4404 *fmask_ptr = NULL;
4405
4406 if (target == TGSI_TEXTURE_2D_MSAA ||
4407 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4408 if (fmask_ptr)
4409 *fmask_ptr = load_sampler_desc(ctx, list, index,
4410 DESC_FMASK);
4411 } else if (target != TGSI_TEXTURE_BUFFER) {
4412 if (samp_ptr) {
4413 *samp_ptr = load_sampler_desc(ctx, list, index,
4414 DESC_SAMPLER);
4415 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4416 }
4417 }
4418 }
4419
4420 static void txq_fetch_args(
4421 struct lp_build_tgsi_context *bld_base,
4422 struct lp_build_emit_data *emit_data)
4423 {
4424 struct si_shader_context *ctx = si_shader_context(bld_base);
4425 const struct tgsi_full_instruction *inst = emit_data->inst;
4426 unsigned target = inst->Texture.Texture;
4427 LLVMValueRef res_ptr;
4428 LLVMValueRef address;
4429
4430 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4431
4432 if (target == TGSI_TEXTURE_BUFFER) {
4433 /* Read the size from the buffer descriptor directly. */
4434 emit_data->args[0] = get_buffer_size(bld_base, res_ptr);
4435 return;
4436 }
4437
4438 /* Textures - set the mip level. */
4439 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4440
4441 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
4442 NULL, &address, 1, 0xf);
4443 }
4444
4445 static void txq_emit(const struct lp_build_tgsi_action *action,
4446 struct lp_build_tgsi_context *bld_base,
4447 struct lp_build_emit_data *emit_data)
4448 {
4449 struct si_shader_context *ctx = si_shader_context(bld_base);
4450 struct ac_image_args args;
4451 unsigned target = emit_data->inst->Texture.Texture;
4452
4453 if (target == TGSI_TEXTURE_BUFFER) {
4454 /* Just return the buffer size. */
4455 emit_data->output[emit_data->chan] = emit_data->args[0];
4456 return;
4457 }
4458
4459 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
4460
4461 args.opcode = ac_image_get_resinfo;
4462 LLVMValueRef result = ac_build_image_opcode(&ctx->ac, &args);
4463
4464 emit_data->output[emit_data->chan] = fix_resinfo(ctx, target, result);
4465 }
4466
4467 static void tex_fetch_args(
4468 struct lp_build_tgsi_context *bld_base,
4469 struct lp_build_emit_data *emit_data)
4470 {
4471 struct si_shader_context *ctx = si_shader_context(bld_base);
4472 struct gallivm_state *gallivm = &ctx->gallivm;
4473 const struct tgsi_full_instruction *inst = emit_data->inst;
4474 unsigned opcode = inst->Instruction.Opcode;
4475 unsigned target = inst->Texture.Texture;
4476 LLVMValueRef coords[5], derivs[6];
4477 LLVMValueRef address[16];
4478 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4479 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4480 unsigned count = 0;
4481 unsigned chan;
4482 unsigned num_deriv_channels = 0;
4483 bool has_offset = inst->Texture.NumOffsets > 0;
4484 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4485 unsigned dmask = 0xf;
4486
4487 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4488
4489 if (target == TGSI_TEXTURE_BUFFER) {
4490 emit_data->dst_type = ctx->v4f32;
4491 emit_data->args[0] = LLVMBuildBitCast(gallivm->builder, res_ptr,
4492 ctx->v16i8, "");
4493 emit_data->args[1] = ctx->i32_0;
4494 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4495 emit_data->arg_count = 3;
4496 return;
4497 }
4498
4499 /* Fetch and project texture coordinates */
4500 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4501 for (chan = 0; chan < 3; chan++ ) {
4502 coords[chan] = lp_build_emit_fetch(bld_base,
4503 emit_data->inst, 0,
4504 chan);
4505 if (opcode == TGSI_OPCODE_TXP)
4506 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4507 TGSI_OPCODE_DIV,
4508 coords[chan],
4509 coords[3]);
4510 }
4511
4512 if (opcode == TGSI_OPCODE_TXP)
4513 coords[3] = bld_base->base.one;
4514
4515 /* Pack offsets. */
4516 if (has_offset &&
4517 opcode != TGSI_OPCODE_TXF &&
4518 opcode != TGSI_OPCODE_TXF_LZ) {
4519 /* The offsets are six-bit signed integers packed like this:
4520 * X=[5:0], Y=[13:8], and Z=[21:16].
4521 */
4522 LLVMValueRef offset[3], pack;
4523
4524 assert(inst->Texture.NumOffsets == 1);
4525
4526 for (chan = 0; chan < 3; chan++) {
4527 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4528 emit_data->inst, 0, chan);
4529 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4530 LLVMConstInt(ctx->i32, 0x3f, 0), "");
4531 if (chan)
4532 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4533 LLVMConstInt(ctx->i32, chan*8, 0), "");
4534 }
4535
4536 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4537 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4538 address[count++] = pack;
4539 }
4540
4541 /* Pack LOD bias value */
4542 if (opcode == TGSI_OPCODE_TXB)
4543 address[count++] = coords[3];
4544 if (opcode == TGSI_OPCODE_TXB2)
4545 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4546
4547 /* Pack depth comparison value */
4548 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4549 LLVMValueRef z;
4550
4551 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4552 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4553 } else {
4554 assert(ref_pos >= 0);
4555 z = coords[ref_pos];
4556 }
4557
4558 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4559 * so the depth comparison value isn't clamped for Z16 and
4560 * Z24 anymore. Do it manually here.
4561 *
4562 * It's unnecessary if the original texture format was
4563 * Z32_FLOAT, but we don't know that here.
4564 */
4565 if (ctx->screen->b.chip_class == VI)
4566 z = ac_build_clamp(&ctx->ac, z);
4567
4568 address[count++] = z;
4569 }
4570
4571 /* Pack user derivatives */
4572 if (opcode == TGSI_OPCODE_TXD) {
4573 int param, num_src_deriv_channels, num_dst_deriv_channels;
4574
4575 switch (target) {
4576 case TGSI_TEXTURE_3D:
4577 num_src_deriv_channels = 3;
4578 num_dst_deriv_channels = 3;
4579 num_deriv_channels = 3;
4580 break;
4581 case TGSI_TEXTURE_2D:
4582 case TGSI_TEXTURE_SHADOW2D:
4583 case TGSI_TEXTURE_RECT:
4584 case TGSI_TEXTURE_SHADOWRECT:
4585 case TGSI_TEXTURE_2D_ARRAY:
4586 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4587 num_src_deriv_channels = 2;
4588 num_dst_deriv_channels = 2;
4589 num_deriv_channels = 2;
4590 break;
4591 case TGSI_TEXTURE_CUBE:
4592 case TGSI_TEXTURE_SHADOWCUBE:
4593 case TGSI_TEXTURE_CUBE_ARRAY:
4594 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4595 /* Cube derivatives will be converted to 2D. */
4596 num_src_deriv_channels = 3;
4597 num_dst_deriv_channels = 3;
4598 num_deriv_channels = 2;
4599 break;
4600 case TGSI_TEXTURE_1D:
4601 case TGSI_TEXTURE_SHADOW1D:
4602 case TGSI_TEXTURE_1D_ARRAY:
4603 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4604 num_src_deriv_channels = 1;
4605
4606 /* 1D textures are allocated and used as 2D on GFX9. */
4607 if (ctx->screen->b.chip_class >= GFX9) {
4608 num_dst_deriv_channels = 2;
4609 num_deriv_channels = 2;
4610 } else {
4611 num_dst_deriv_channels = 1;
4612 num_deriv_channels = 1;
4613 }
4614 break;
4615 default:
4616 unreachable("invalid target");
4617 }
4618
4619 for (param = 0; param < 2; param++) {
4620 for (chan = 0; chan < num_src_deriv_channels; chan++)
4621 derivs[param * num_dst_deriv_channels + chan] =
4622 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4623
4624 /* Fill in the rest with zeros. */
4625 for (chan = num_src_deriv_channels;
4626 chan < num_dst_deriv_channels; chan++)
4627 derivs[param * num_dst_deriv_channels + chan] =
4628 bld_base->base.zero;
4629 }
4630 }
4631
4632 if (target == TGSI_TEXTURE_CUBE ||
4633 target == TGSI_TEXTURE_CUBE_ARRAY ||
4634 target == TGSI_TEXTURE_SHADOWCUBE ||
4635 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4636 ac_prepare_cube_coords(&ctx->ac,
4637 opcode == TGSI_OPCODE_TXD,
4638 target == TGSI_TEXTURE_CUBE_ARRAY ||
4639 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
4640 coords, derivs);
4641
4642 if (opcode == TGSI_OPCODE_TXD)
4643 for (int i = 0; i < num_deriv_channels * 2; i++)
4644 address[count++] = derivs[i];
4645
4646 /* Pack texture coordinates */
4647 address[count++] = coords[0];
4648 if (num_coords > 1)
4649 address[count++] = coords[1];
4650 if (num_coords > 2)
4651 address[count++] = coords[2];
4652
4653 /* 1D textures are allocated and used as 2D on GFX9. */
4654 if (ctx->screen->b.chip_class >= GFX9) {
4655 LLVMValueRef filler;
4656
4657 /* Use 0.5, so that we don't sample the border color. */
4658 if (opcode == TGSI_OPCODE_TXF)
4659 filler = ctx->i32_0;
4660 else
4661 filler = LLVMConstReal(ctx->f32, 0.5);
4662
4663 if (target == TGSI_TEXTURE_1D ||
4664 target == TGSI_TEXTURE_SHADOW1D) {
4665 address[count++] = filler;
4666 } else if (target == TGSI_TEXTURE_1D_ARRAY ||
4667 target == TGSI_TEXTURE_SHADOW1D_ARRAY) {
4668 address[count] = address[count - 1];
4669 address[count - 1] = filler;
4670 count++;
4671 }
4672 }
4673
4674 /* Pack LOD or sample index */
4675 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4676 address[count++] = coords[3];
4677 else if (opcode == TGSI_OPCODE_TXL2)
4678 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4679
4680 if (count > 16) {
4681 assert(!"Cannot handle more than 16 texture address parameters");
4682 count = 16;
4683 }
4684
4685 for (chan = 0; chan < count; chan++ ) {
4686 address[chan] = LLVMBuildBitCast(gallivm->builder,
4687 address[chan], ctx->i32, "");
4688 }
4689
4690 /* Adjust the sample index according to FMASK.
4691 *
4692 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4693 * which is the identity mapping. Each nibble says which physical sample
4694 * should be fetched to get that sample.
4695 *
4696 * For example, 0x11111100 means there are only 2 samples stored and
4697 * the second sample covers 3/4 of the pixel. When reading samples 0
4698 * and 1, return physical sample 0 (determined by the first two 0s
4699 * in FMASK), otherwise return physical sample 1.
4700 *
4701 * The sample index should be adjusted as follows:
4702 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4703 */
4704 if (target == TGSI_TEXTURE_2D_MSAA ||
4705 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4706 struct lp_build_emit_data txf_emit_data = *emit_data;
4707 LLVMValueRef txf_address[4];
4708 /* We only need .xy for non-arrays, and .xyz for arrays. */
4709 unsigned txf_count = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4710 struct tgsi_full_instruction inst = {};
4711
4712 memcpy(txf_address, address, sizeof(txf_address));
4713
4714 /* Read FMASK using TXF_LZ. */
4715 inst.Instruction.Opcode = TGSI_OPCODE_TXF_LZ;
4716 inst.Texture.Texture = target;
4717 txf_emit_data.inst = &inst;
4718 txf_emit_data.chan = 0;
4719 set_tex_fetch_args(ctx, &txf_emit_data,
4720 target, fmask_ptr, NULL,
4721 txf_address, txf_count, 0xf);
4722 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4723
4724 /* Initialize some constants. */
4725 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4726 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4727
4728 /* Apply the formula. */
4729 LLVMValueRef fmask =
4730 LLVMBuildExtractElement(gallivm->builder,
4731 txf_emit_data.output[0],
4732 ctx->i32_0, "");
4733
4734 unsigned sample_chan = txf_count; /* the sample index is last */
4735
4736 LLVMValueRef sample_index4 =
4737 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4738
4739 LLVMValueRef shifted_fmask =
4740 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4741
4742 LLVMValueRef final_sample =
4743 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4744
4745 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4746 * resource descriptor is 0 (invalid),
4747 */
4748 LLVMValueRef fmask_desc =
4749 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4750 ctx->v8i32, "");
4751
4752 LLVMValueRef fmask_word1 =
4753 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4754 ctx->i32_1, "");
4755
4756 LLVMValueRef word1_is_nonzero =
4757 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4758 fmask_word1, ctx->i32_0, "");
4759
4760 /* Replace the MSAA sample index. */
4761 address[sample_chan] =
4762 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4763 final_sample, address[sample_chan], "");
4764 }
4765
4766 if (opcode == TGSI_OPCODE_TXF ||
4767 opcode == TGSI_OPCODE_TXF_LZ) {
4768 /* add tex offsets */
4769 if (inst->Texture.NumOffsets) {
4770 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4771 const struct tgsi_texture_offset *off = inst->TexOffsets;
4772
4773 assert(inst->Texture.NumOffsets == 1);
4774
4775 switch (target) {
4776 case TGSI_TEXTURE_3D:
4777 address[2] = lp_build_add(uint_bld, address[2],
4778 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ]);
4779 /* fall through */
4780 case TGSI_TEXTURE_2D:
4781 case TGSI_TEXTURE_SHADOW2D:
4782 case TGSI_TEXTURE_RECT:
4783 case TGSI_TEXTURE_SHADOWRECT:
4784 case TGSI_TEXTURE_2D_ARRAY:
4785 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4786 address[1] =
4787 lp_build_add(uint_bld, address[1],
4788 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY]);
4789 /* fall through */
4790 case TGSI_TEXTURE_1D:
4791 case TGSI_TEXTURE_SHADOW1D:
4792 case TGSI_TEXTURE_1D_ARRAY:
4793 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4794 address[0] =
4795 lp_build_add(uint_bld, address[0],
4796 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX]);
4797 break;
4798 /* texture offsets do not apply to other texture targets */
4799 }
4800 }
4801 }
4802
4803 if (opcode == TGSI_OPCODE_TG4) {
4804 unsigned gather_comp = 0;
4805
4806 /* DMASK was repurposed for GATHER4. 4 components are always
4807 * returned and DMASK works like a swizzle - it selects
4808 * the component to fetch. The only valid DMASK values are
4809 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4810 * (red,red,red,red) etc.) The ISA document doesn't mention
4811 * this.
4812 */
4813
4814 /* Get the component index from src1.x for Gather4. */
4815 if (!tgsi_is_shadow_target(target)) {
4816 LLVMValueRef comp_imm;
4817 struct tgsi_src_register src1 = inst->Src[1].Register;
4818
4819 assert(src1.File == TGSI_FILE_IMMEDIATE);
4820
4821 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX];
4822 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4823 gather_comp = CLAMP(gather_comp, 0, 3);
4824 }
4825
4826 dmask = 1 << gather_comp;
4827 }
4828
4829 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
4830 samp_ptr, address, count, dmask);
4831 }
4832
4833 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
4834 * incorrectly forces nearest filtering if the texture format is integer.
4835 * The only effect it has on Gather4, which always returns 4 texels for
4836 * bilinear filtering, is that the final coordinates are off by 0.5 of
4837 * the texel size.
4838 *
4839 * The workaround is to subtract 0.5 from the unnormalized coordinates,
4840 * or (0.5 / size) from the normalized coordinates.
4841 */
4842 static void si_lower_gather4_integer(struct si_shader_context *ctx,
4843 struct ac_image_args *args,
4844 unsigned target)
4845 {
4846 LLVMBuilderRef builder = ctx->gallivm.builder;
4847 LLVMValueRef coord = args->addr;
4848 LLVMValueRef half_texel[2];
4849 /* Texture coordinates start after:
4850 * {offset, bias, z-compare, derivatives}
4851 * Only the offset and z-compare can occur here.
4852 */
4853 unsigned coord_vgpr_index = (int)args->offset + (int)args->compare;
4854 int c;
4855
4856 if (target == TGSI_TEXTURE_RECT ||
4857 target == TGSI_TEXTURE_SHADOWRECT) {
4858 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
4859 } else {
4860 struct tgsi_full_instruction txq_inst = {};
4861 struct lp_build_emit_data txq_emit_data = {};
4862
4863 /* Query the texture size. */
4864 txq_inst.Texture.Texture = target;
4865 txq_emit_data.inst = &txq_inst;
4866 txq_emit_data.dst_type = ctx->v4i32;
4867 set_tex_fetch_args(ctx, &txq_emit_data, target,
4868 args->resource, NULL, &ctx->i32_0,
4869 1, 0xf);
4870 txq_emit(NULL, &ctx->bld_base, &txq_emit_data);
4871
4872 /* Compute -0.5 / size. */
4873 for (c = 0; c < 2; c++) {
4874 half_texel[c] =
4875 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
4876 LLVMConstInt(ctx->i32, c, 0), "");
4877 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
4878 half_texel[c] =
4879 lp_build_emit_llvm_unary(&ctx->bld_base,
4880 TGSI_OPCODE_RCP, half_texel[c]);
4881 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
4882 LLVMConstReal(ctx->f32, -0.5), "");
4883 }
4884 }
4885
4886 for (c = 0; c < 2; c++) {
4887 LLVMValueRef tmp;
4888 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
4889
4890 tmp = LLVMBuildExtractElement(builder, coord, index, "");
4891 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4892 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
4893 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4894 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
4895 }
4896
4897 args->addr = coord;
4898 }
4899
4900 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4901 struct lp_build_tgsi_context *bld_base,
4902 struct lp_build_emit_data *emit_data)
4903 {
4904 struct si_shader_context *ctx = si_shader_context(bld_base);
4905 const struct tgsi_full_instruction *inst = emit_data->inst;
4906 struct ac_image_args args;
4907 unsigned opcode = inst->Instruction.Opcode;
4908 unsigned target = inst->Texture.Texture;
4909
4910 if (target == TGSI_TEXTURE_BUFFER) {
4911 emit_data->output[emit_data->chan] =
4912 ac_build_buffer_load_format(&ctx->ac,
4913 emit_data->args[0],
4914 emit_data->args[2],
4915 emit_data->args[1],
4916 true);
4917 return;
4918 }
4919
4920 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
4921
4922 args.opcode = ac_image_sample;
4923 args.compare = tgsi_is_shadow_target(target);
4924 args.offset = inst->Texture.NumOffsets > 0;
4925
4926 switch (opcode) {
4927 case TGSI_OPCODE_TXF:
4928 case TGSI_OPCODE_TXF_LZ:
4929 args.opcode = opcode == TGSI_OPCODE_TXF_LZ ||
4930 target == TGSI_TEXTURE_2D_MSAA ||
4931 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4932 ac_image_load : ac_image_load_mip;
4933 args.compare = false;
4934 args.offset = false;
4935 break;
4936 case TGSI_OPCODE_LODQ:
4937 args.opcode = ac_image_get_lod;
4938 args.compare = false;
4939 args.offset = false;
4940 break;
4941 case TGSI_OPCODE_TEX:
4942 case TGSI_OPCODE_TEX2:
4943 case TGSI_OPCODE_TXP:
4944 if (ctx->type != PIPE_SHADER_FRAGMENT)
4945 args.level_zero = true;
4946 break;
4947 case TGSI_OPCODE_TEX_LZ:
4948 args.level_zero = true;
4949 break;
4950 case TGSI_OPCODE_TXB:
4951 case TGSI_OPCODE_TXB2:
4952 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4953 args.bias = true;
4954 break;
4955 case TGSI_OPCODE_TXL:
4956 case TGSI_OPCODE_TXL2:
4957 args.lod = true;
4958 break;
4959 case TGSI_OPCODE_TXD:
4960 args.deriv = true;
4961 break;
4962 case TGSI_OPCODE_TG4:
4963 args.opcode = ac_image_gather4;
4964 args.level_zero = true;
4965 break;
4966 default:
4967 assert(0);
4968 return;
4969 }
4970
4971 /* The hardware needs special lowering for Gather4 with integer formats. */
4972 if (ctx->screen->b.chip_class <= VI &&
4973 opcode == TGSI_OPCODE_TG4) {
4974 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4975 /* This will also work with non-constant indexing because of how
4976 * glsl_to_tgsi works and we intent to preserve that behavior.
4977 */
4978 const unsigned src_idx = 2;
4979 unsigned sampler = inst->Src[src_idx].Register.Index;
4980
4981 assert(inst->Src[src_idx].Register.File == TGSI_FILE_SAMPLER);
4982
4983 if (info->sampler_type[sampler] == TGSI_RETURN_TYPE_SINT ||
4984 info->sampler_type[sampler] == TGSI_RETURN_TYPE_UINT)
4985 si_lower_gather4_integer(ctx, &args, target);
4986 }
4987
4988 emit_data->output[emit_data->chan] =
4989 ac_build_image_opcode(&ctx->ac, &args);
4990 }
4991
4992 static void si_llvm_emit_txqs(
4993 const struct lp_build_tgsi_action *action,
4994 struct lp_build_tgsi_context *bld_base,
4995 struct lp_build_emit_data *emit_data)
4996 {
4997 struct si_shader_context *ctx = si_shader_context(bld_base);
4998 struct gallivm_state *gallivm = &ctx->gallivm;
4999 LLVMBuilderRef builder = gallivm->builder;
5000 LLVMValueRef res, samples;
5001 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
5002
5003 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
5004
5005
5006 /* Read the samples from the descriptor directly. */
5007 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
5008 samples = LLVMBuildExtractElement(
5009 builder, res,
5010 LLVMConstInt(ctx->i32, 3, 0), "");
5011 samples = LLVMBuildLShr(builder, samples,
5012 LLVMConstInt(ctx->i32, 16, 0), "");
5013 samples = LLVMBuildAnd(builder, samples,
5014 LLVMConstInt(ctx->i32, 0xf, 0), "");
5015 samples = LLVMBuildShl(builder, ctx->i32_1,
5016 samples, "");
5017
5018 emit_data->output[emit_data->chan] = samples;
5019 }
5020
5021 static void si_llvm_emit_ddxy(
5022 const struct lp_build_tgsi_action *action,
5023 struct lp_build_tgsi_context *bld_base,
5024 struct lp_build_emit_data *emit_data)
5025 {
5026 struct si_shader_context *ctx = si_shader_context(bld_base);
5027 struct gallivm_state *gallivm = &ctx->gallivm;
5028 unsigned opcode = emit_data->info->opcode;
5029 LLVMValueRef val;
5030 int idx;
5031 unsigned mask;
5032
5033 if (opcode == TGSI_OPCODE_DDX_FINE)
5034 mask = AC_TID_MASK_LEFT;
5035 else if (opcode == TGSI_OPCODE_DDY_FINE)
5036 mask = AC_TID_MASK_TOP;
5037 else
5038 mask = AC_TID_MASK_TOP_LEFT;
5039
5040 /* for DDX we want to next X pixel, DDY next Y pixel. */
5041 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
5042
5043 val = LLVMBuildBitCast(gallivm->builder, emit_data->args[0], ctx->i32, "");
5044 val = ac_build_ddxy(&ctx->ac, ctx->screen->has_ds_bpermute,
5045 mask, idx, ctx->lds, val);
5046 emit_data->output[emit_data->chan] = val;
5047 }
5048
5049 /*
5050 * this takes an I,J coordinate pair,
5051 * and works out the X and Y derivatives.
5052 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
5053 */
5054 static LLVMValueRef si_llvm_emit_ddxy_interp(
5055 struct lp_build_tgsi_context *bld_base,
5056 LLVMValueRef interp_ij)
5057 {
5058 struct si_shader_context *ctx = si_shader_context(bld_base);
5059 struct gallivm_state *gallivm = &ctx->gallivm;
5060 LLVMValueRef result[4], a;
5061 unsigned i;
5062
5063 for (i = 0; i < 2; i++) {
5064 a = LLVMBuildExtractElement(gallivm->builder, interp_ij,
5065 LLVMConstInt(ctx->i32, i, 0), "");
5066 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
5067 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
5068 }
5069
5070 return lp_build_gather_values(gallivm, result, 4);
5071 }
5072
5073 static void interp_fetch_args(
5074 struct lp_build_tgsi_context *bld_base,
5075 struct lp_build_emit_data *emit_data)
5076 {
5077 struct si_shader_context *ctx = si_shader_context(bld_base);
5078 struct gallivm_state *gallivm = &ctx->gallivm;
5079 const struct tgsi_full_instruction *inst = emit_data->inst;
5080
5081 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
5082 /* offset is in second src, first two channels */
5083 emit_data->args[0] = lp_build_emit_fetch(bld_base,
5084 emit_data->inst, 1,
5085 TGSI_CHAN_X);
5086 emit_data->args[1] = lp_build_emit_fetch(bld_base,
5087 emit_data->inst, 1,
5088 TGSI_CHAN_Y);
5089 emit_data->arg_count = 2;
5090 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5091 LLVMValueRef sample_position;
5092 LLVMValueRef sample_id;
5093 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
5094
5095 /* fetch sample ID, then fetch its sample position,
5096 * and place into first two channels.
5097 */
5098 sample_id = lp_build_emit_fetch(bld_base,
5099 emit_data->inst, 1, TGSI_CHAN_X);
5100 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
5101 ctx->i32, "");
5102 sample_position = load_sample_position(ctx, sample_id);
5103
5104 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
5105 sample_position,
5106 ctx->i32_0, "");
5107
5108 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
5109 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
5110 sample_position,
5111 ctx->i32_1, "");
5112 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
5113 emit_data->arg_count = 2;
5114 }
5115 }
5116
5117 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
5118 struct lp_build_tgsi_context *bld_base,
5119 struct lp_build_emit_data *emit_data)
5120 {
5121 struct si_shader_context *ctx = si_shader_context(bld_base);
5122 struct si_shader *shader = ctx->shader;
5123 struct gallivm_state *gallivm = &ctx->gallivm;
5124 LLVMValueRef interp_param;
5125 const struct tgsi_full_instruction *inst = emit_data->inst;
5126 int input_index = inst->Src[0].Register.Index;
5127 int chan;
5128 int i;
5129 LLVMValueRef attr_number;
5130 LLVMValueRef params = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
5131 int interp_param_idx;
5132 unsigned interp = shader->selector->info.input_interpolate[input_index];
5133 unsigned location;
5134
5135 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5136
5137 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5138 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
5139 location = TGSI_INTERPOLATE_LOC_CENTER;
5140 else
5141 location = TGSI_INTERPOLATE_LOC_CENTROID;
5142
5143 interp_param_idx = lookup_interp_param_index(interp, location);
5144 if (interp_param_idx == -1)
5145 return;
5146 else if (interp_param_idx)
5147 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
5148 else
5149 interp_param = NULL;
5150
5151 attr_number = LLVMConstInt(ctx->i32, input_index, 0);
5152
5153 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5154 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5155 LLVMValueRef ij_out[2];
5156 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
5157
5158 /*
5159 * take the I then J parameters, and the DDX/Y for it, and
5160 * calculate the IJ inputs for the interpolator.
5161 * temp1 = ddx * offset/sample.x + I;
5162 * interp_param.I = ddy * offset/sample.y + temp1;
5163 * temp1 = ddx * offset/sample.x + J;
5164 * interp_param.J = ddy * offset/sample.y + temp1;
5165 */
5166 for (i = 0; i < 2; i++) {
5167 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
5168 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
5169 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
5170 ddxy_out, ix_ll, "");
5171 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
5172 ddxy_out, iy_ll, "");
5173 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5174 interp_param, ix_ll, "");
5175 LLVMValueRef temp1, temp2;
5176
5177 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5178 ctx->f32, "");
5179
5180 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5181
5182 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5183
5184 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5185
5186 ij_out[i] = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5187 }
5188 interp_param = lp_build_gather_values(gallivm, ij_out, 2);
5189 }
5190
5191 for (chan = 0; chan < 4; chan++) {
5192 LLVMValueRef llvm_chan;
5193 unsigned schan;
5194
5195 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5196 llvm_chan = LLVMConstInt(ctx->i32, schan, 0);
5197
5198 if (interp_param) {
5199 interp_param = LLVMBuildBitCast(gallivm->builder,
5200 interp_param, LLVMVectorType(ctx->f32, 2), "");
5201 LLVMValueRef i = LLVMBuildExtractElement(
5202 gallivm->builder, interp_param, ctx->i32_0, "");
5203 LLVMValueRef j = LLVMBuildExtractElement(
5204 gallivm->builder, interp_param, ctx->i32_1, "");
5205 emit_data->output[chan] = ac_build_fs_interp(&ctx->ac,
5206 llvm_chan, attr_number, params,
5207 i, j);
5208 } else {
5209 emit_data->output[chan] = ac_build_fs_interp_mov(&ctx->ac,
5210 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
5211 llvm_chan, attr_number, params);
5212 }
5213 }
5214 }
5215
5216 static LLVMValueRef si_emit_ballot(struct si_shader_context *ctx,
5217 LLVMValueRef value)
5218 {
5219 struct gallivm_state *gallivm = &ctx->gallivm;
5220 LLVMValueRef args[3] = {
5221 value,
5222 ctx->i32_0,
5223 LLVMConstInt(ctx->i32, LLVMIntNE, 0)
5224 };
5225
5226 /* We currently have no other way to prevent LLVM from lifting the icmp
5227 * calls to a dominating basic block.
5228 */
5229 emit_optimization_barrier(ctx, &args[0]);
5230
5231 if (LLVMTypeOf(args[0]) != ctx->i32)
5232 args[0] = LLVMBuildBitCast(gallivm->builder, args[0], ctx->i32, "");
5233
5234 return lp_build_intrinsic(gallivm->builder,
5235 "llvm.amdgcn.icmp.i32",
5236 ctx->i64, args, 3,
5237 LP_FUNC_ATTR_NOUNWIND |
5238 LP_FUNC_ATTR_READNONE |
5239 LP_FUNC_ATTR_CONVERGENT);
5240 }
5241
5242 static void vote_all_emit(
5243 const struct lp_build_tgsi_action *action,
5244 struct lp_build_tgsi_context *bld_base,
5245 struct lp_build_emit_data *emit_data)
5246 {
5247 struct si_shader_context *ctx = si_shader_context(bld_base);
5248 struct gallivm_state *gallivm = &ctx->gallivm;
5249 LLVMValueRef active_set, vote_set;
5250 LLVMValueRef tmp;
5251
5252 active_set = si_emit_ballot(ctx, ctx->i32_1);
5253 vote_set = si_emit_ballot(ctx, emit_data->args[0]);
5254
5255 tmp = LLVMBuildICmp(gallivm->builder, LLVMIntEQ, vote_set, active_set, "");
5256 emit_data->output[emit_data->chan] =
5257 LLVMBuildSExt(gallivm->builder, tmp, ctx->i32, "");
5258 }
5259
5260 static void vote_any_emit(
5261 const struct lp_build_tgsi_action *action,
5262 struct lp_build_tgsi_context *bld_base,
5263 struct lp_build_emit_data *emit_data)
5264 {
5265 struct si_shader_context *ctx = si_shader_context(bld_base);
5266 struct gallivm_state *gallivm = &ctx->gallivm;
5267 LLVMValueRef vote_set;
5268 LLVMValueRef tmp;
5269
5270 vote_set = si_emit_ballot(ctx, emit_data->args[0]);
5271
5272 tmp = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
5273 vote_set, LLVMConstInt(ctx->i64, 0, 0), "");
5274 emit_data->output[emit_data->chan] =
5275 LLVMBuildSExt(gallivm->builder, tmp, ctx->i32, "");
5276 }
5277
5278 static void vote_eq_emit(
5279 const struct lp_build_tgsi_action *action,
5280 struct lp_build_tgsi_context *bld_base,
5281 struct lp_build_emit_data *emit_data)
5282 {
5283 struct si_shader_context *ctx = si_shader_context(bld_base);
5284 struct gallivm_state *gallivm = &ctx->gallivm;
5285 LLVMValueRef active_set, vote_set;
5286 LLVMValueRef all, none, tmp;
5287
5288 active_set = si_emit_ballot(ctx, ctx->i32_1);
5289 vote_set = si_emit_ballot(ctx, emit_data->args[0]);
5290
5291 all = LLVMBuildICmp(gallivm->builder, LLVMIntEQ, vote_set, active_set, "");
5292 none = LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
5293 vote_set, LLVMConstInt(ctx->i64, 0, 0), "");
5294 tmp = LLVMBuildOr(gallivm->builder, all, none, "");
5295 emit_data->output[emit_data->chan] =
5296 LLVMBuildSExt(gallivm->builder, tmp, ctx->i32, "");
5297 }
5298
5299 static void ballot_emit(
5300 const struct lp_build_tgsi_action *action,
5301 struct lp_build_tgsi_context *bld_base,
5302 struct lp_build_emit_data *emit_data)
5303 {
5304 struct si_shader_context *ctx = si_shader_context(bld_base);
5305 LLVMBuilderRef builder = ctx->gallivm.builder;
5306 LLVMValueRef tmp;
5307
5308 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
5309 tmp = si_emit_ballot(ctx, tmp);
5310 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
5311
5312 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
5313 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
5314 }
5315
5316 static void read_invoc_fetch_args(
5317 struct lp_build_tgsi_context *bld_base,
5318 struct lp_build_emit_data *emit_data)
5319 {
5320 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
5321 0, emit_data->src_chan);
5322
5323 /* Always read the source invocation (= lane) from the X channel. */
5324 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
5325 1, TGSI_CHAN_X);
5326 emit_data->arg_count = 2;
5327 }
5328
5329 static void read_lane_emit(
5330 const struct lp_build_tgsi_action *action,
5331 struct lp_build_tgsi_context *bld_base,
5332 struct lp_build_emit_data *emit_data)
5333 {
5334 struct si_shader_context *ctx = si_shader_context(bld_base);
5335 LLVMBuilderRef builder = ctx->gallivm.builder;
5336
5337 /* We currently have no other way to prevent LLVM from lifting the icmp
5338 * calls to a dominating basic block.
5339 */
5340 emit_optimization_barrier(ctx, &emit_data->args[0]);
5341
5342 for (unsigned i = 0; i < emit_data->arg_count; ++i) {
5343 emit_data->args[i] = LLVMBuildBitCast(builder, emit_data->args[i],
5344 ctx->i32, "");
5345 }
5346
5347 emit_data->output[emit_data->chan] =
5348 ac_build_intrinsic(&ctx->ac, action->intr_name,
5349 ctx->i32, emit_data->args, emit_data->arg_count,
5350 AC_FUNC_ATTR_READNONE |
5351 AC_FUNC_ATTR_CONVERGENT);
5352 }
5353
5354 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5355 struct lp_build_emit_data *emit_data)
5356 {
5357 struct si_shader_context *ctx = si_shader_context(bld_base);
5358 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5359 LLVMValueRef imm;
5360 unsigned stream;
5361
5362 assert(src0.File == TGSI_FILE_IMMEDIATE);
5363
5364 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
5365 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
5366 return stream;
5367 }
5368
5369 /* Emit one vertex from the geometry shader */
5370 static void si_llvm_emit_vertex(
5371 const struct lp_build_tgsi_action *action,
5372 struct lp_build_tgsi_context *bld_base,
5373 struct lp_build_emit_data *emit_data)
5374 {
5375 struct si_shader_context *ctx = si_shader_context(bld_base);
5376 struct lp_build_context *uint = &bld_base->uint_bld;
5377 struct si_shader *shader = ctx->shader;
5378 struct tgsi_shader_info *info = &shader->selector->info;
5379 struct gallivm_state *gallivm = &ctx->gallivm;
5380 struct lp_build_if_state if_state;
5381 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
5382 SI_PARAM_GS2VS_OFFSET);
5383 LLVMValueRef gs_next_vertex;
5384 LLVMValueRef can_emit, kill;
5385 unsigned chan, offset;
5386 int i;
5387 unsigned stream;
5388
5389 stream = si_llvm_get_stream(bld_base, emit_data);
5390
5391 /* Write vertex attribute values to GSVS ring */
5392 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5393 ctx->gs_next_vertex[stream],
5394 "");
5395
5396 /* If this thread has already emitted the declared maximum number of
5397 * vertices, skip the write: excessive vertex emissions are not
5398 * supposed to have any effect.
5399 *
5400 * If the shader has no writes to memory, kill it instead. This skips
5401 * further memory loads and may allow LLVM to skip to the end
5402 * altogether.
5403 */
5404 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULT, gs_next_vertex,
5405 LLVMConstInt(ctx->i32,
5406 shader->selector->gs_max_out_vertices, 0), "");
5407
5408 bool use_kill = !info->writes_memory;
5409 if (use_kill) {
5410 kill = lp_build_select(&bld_base->base, can_emit,
5411 LLVMConstReal(ctx->f32, 1.0f),
5412 LLVMConstReal(ctx->f32, -1.0f));
5413
5414 ac_build_kill(&ctx->ac, kill);
5415 } else {
5416 lp_build_if(&if_state, gallivm, can_emit);
5417 }
5418
5419 offset = 0;
5420 for (i = 0; i < info->num_outputs; i++) {
5421 LLVMValueRef *out_ptr = ctx->outputs[i];
5422
5423 for (chan = 0; chan < 4; chan++) {
5424 if (!(info->output_usagemask[i] & (1 << chan)) ||
5425 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
5426 continue;
5427
5428 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5429 LLVMValueRef voffset =
5430 LLVMConstInt(ctx->i32, offset *
5431 shader->selector->gs_max_out_vertices, 0);
5432 offset++;
5433
5434 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5435 voffset = lp_build_mul_imm(uint, voffset, 4);
5436
5437 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5438
5439 ac_build_buffer_store_dword(&ctx->ac,
5440 ctx->gsvs_ring[stream],
5441 out_val, 1,
5442 voffset, soffset, 0,
5443 1, 1, true, true);
5444 }
5445 }
5446
5447 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5448 ctx->i32_1);
5449
5450 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5451
5452 /* Signal vertex emission */
5453 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
5454 LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID));
5455 if (!use_kill)
5456 lp_build_endif(&if_state);
5457 }
5458
5459 /* Cut one primitive from the geometry shader */
5460 static void si_llvm_emit_primitive(
5461 const struct lp_build_tgsi_action *action,
5462 struct lp_build_tgsi_context *bld_base,
5463 struct lp_build_emit_data *emit_data)
5464 {
5465 struct si_shader_context *ctx = si_shader_context(bld_base);
5466 unsigned stream;
5467
5468 /* Signal primitive cut */
5469 stream = si_llvm_get_stream(bld_base, emit_data);
5470 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
5471 LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID));
5472 }
5473
5474 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5475 struct lp_build_tgsi_context *bld_base,
5476 struct lp_build_emit_data *emit_data)
5477 {
5478 struct si_shader_context *ctx = si_shader_context(bld_base);
5479 struct gallivm_state *gallivm = &ctx->gallivm;
5480
5481 /* SI only (thanks to a hw bug workaround):
5482 * The real barrier instruction isn’t needed, because an entire patch
5483 * always fits into a single wave.
5484 */
5485 if (HAVE_LLVM >= 0x0309 &&
5486 ctx->screen->b.chip_class == SI &&
5487 ctx->type == PIPE_SHADER_TESS_CTRL) {
5488 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
5489 return;
5490 }
5491
5492 lp_build_intrinsic(gallivm->builder,
5493 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5494 : "llvm.AMDGPU.barrier.local",
5495 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
5496 }
5497
5498 static const struct lp_build_tgsi_action tex_action = {
5499 .fetch_args = tex_fetch_args,
5500 .emit = build_tex_intrinsic,
5501 };
5502
5503 static const struct lp_build_tgsi_action interp_action = {
5504 .fetch_args = interp_fetch_args,
5505 .emit = build_interp_intrinsic,
5506 };
5507
5508 static void si_create_function(struct si_shader_context *ctx,
5509 const char *name,
5510 LLVMTypeRef *returns, unsigned num_returns,
5511 LLVMTypeRef *params, unsigned num_params,
5512 int last_sgpr)
5513 {
5514 int i;
5515
5516 si_llvm_create_func(ctx, name, returns, num_returns,
5517 params, num_params);
5518 si_llvm_shader_type(ctx->main_fn, ctx->type);
5519 ctx->return_value = LLVMGetUndef(ctx->return_type);
5520
5521 for (i = 0; i <= last_sgpr; ++i) {
5522 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
5523
5524 /* The combination of:
5525 * - ByVal
5526 * - dereferenceable
5527 * - invariant.load
5528 * allows the optimization passes to move loads and reduces
5529 * SGPR spilling significantly.
5530 */
5531 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
5532 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
5533 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
5534 ac_add_attr_dereferenceable(P, UINT64_MAX);
5535 } else
5536 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
5537 }
5538
5539 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5540 "no-signed-zeros-fp-math",
5541 "true");
5542
5543 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5544 /* These were copied from some LLVM test. */
5545 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5546 "less-precise-fpmad",
5547 "true");
5548 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5549 "no-infs-fp-math",
5550 "true");
5551 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5552 "no-nans-fp-math",
5553 "true");
5554 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5555 "unsafe-fp-math",
5556 "true");
5557 }
5558 }
5559
5560 static void declare_streamout_params(struct si_shader_context *ctx,
5561 struct pipe_stream_output_info *so,
5562 LLVMTypeRef *params, LLVMTypeRef i32,
5563 unsigned *num_params)
5564 {
5565 int i;
5566
5567 /* Streamout SGPRs. */
5568 if (so->num_outputs) {
5569 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5570 params[ctx->param_streamout_config = (*num_params)++] = i32;
5571 else
5572 ctx->param_streamout_config = *num_params - 1;
5573
5574 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5575 }
5576 /* A streamout buffer offset is loaded if the stride is non-zero. */
5577 for (i = 0; i < 4; i++) {
5578 if (!so->stride[i])
5579 continue;
5580
5581 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5582 }
5583 }
5584
5585 static unsigned llvm_get_type_size(LLVMTypeRef type)
5586 {
5587 LLVMTypeKind kind = LLVMGetTypeKind(type);
5588
5589 switch (kind) {
5590 case LLVMIntegerTypeKind:
5591 return LLVMGetIntTypeWidth(type) / 8;
5592 case LLVMFloatTypeKind:
5593 return 4;
5594 case LLVMPointerTypeKind:
5595 return 8;
5596 case LLVMVectorTypeKind:
5597 return LLVMGetVectorSize(type) *
5598 llvm_get_type_size(LLVMGetElementType(type));
5599 case LLVMArrayTypeKind:
5600 return LLVMGetArrayLength(type) *
5601 llvm_get_type_size(LLVMGetElementType(type));
5602 default:
5603 assert(0);
5604 return 0;
5605 }
5606 }
5607
5608 static void declare_tess_lds(struct si_shader_context *ctx)
5609 {
5610 struct gallivm_state *gallivm = &ctx->gallivm;
5611
5612 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5613 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, ctx->i32_0,
5614 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
5615 "tess_lds");
5616 }
5617
5618 static unsigned si_get_max_workgroup_size(struct si_shader *shader)
5619 {
5620 const unsigned *properties = shader->selector->info.properties;
5621 unsigned max_work_group_size =
5622 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5623 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5624 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5625
5626 if (!max_work_group_size) {
5627 /* This is a variable group size compute shader,
5628 * compile it for the maximum possible group size.
5629 */
5630 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
5631 }
5632 return max_work_group_size;
5633 }
5634
5635 static void create_function(struct si_shader_context *ctx)
5636 {
5637 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5638 struct gallivm_state *gallivm = &ctx->gallivm;
5639 struct si_shader *shader = ctx->shader;
5640 LLVMTypeRef params[SI_NUM_PARAMS + SI_MAX_ATTRIBS], v3i32;
5641 LLVMTypeRef returns[16+32*4];
5642 unsigned i, last_sgpr, num_params, num_return_sgprs;
5643 unsigned num_returns = 0;
5644 unsigned num_prolog_vgprs = 0;
5645
5646 v3i32 = LLVMVectorType(ctx->i32, 3);
5647
5648 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5649 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5650 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5651 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5652 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5653
5654 switch (ctx->type) {
5655 case PIPE_SHADER_VERTEX:
5656 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_MAX_ATTRIBS);
5657 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5658 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5659 params[SI_PARAM_DRAWID] = ctx->i32;
5660 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5661 num_params = SI_PARAM_VS_STATE_BITS+1;
5662
5663 if (shader->key.as_es) {
5664 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5665 } else if (shader->key.as_ls) {
5666 /* no extra parameters */
5667 } else {
5668 if (shader->is_gs_copy_shader) {
5669 num_params = SI_PARAM_RW_BUFFERS+1;
5670 }
5671
5672 /* The locations of the other parameters are assigned dynamically. */
5673 declare_streamout_params(ctx, &shader->selector->so,
5674 params, ctx->i32, &num_params);
5675 }
5676
5677 last_sgpr = num_params-1;
5678
5679 /* VGPRs */
5680 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5681 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5682 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5683 params[ctx->param_instance_id = num_params++] = ctx->i32;
5684
5685 if (!shader->is_gs_copy_shader) {
5686 /* Vertex load indices. */
5687 ctx->param_vertex_index0 = num_params;
5688
5689 for (i = 0; i < shader->selector->info.num_inputs; i++)
5690 params[num_params++] = ctx->i32;
5691
5692 num_prolog_vgprs += shader->selector->info.num_inputs;
5693
5694 /* PrimitiveID output. */
5695 if (!shader->key.as_es && !shader->key.as_ls)
5696 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5697 returns[num_returns++] = ctx->f32;
5698 }
5699 break;
5700
5701 case PIPE_SHADER_TESS_CTRL:
5702 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5703 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5704 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5705 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5706 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5707 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5708 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5709
5710 /* VGPRs */
5711 params[SI_PARAM_PATCH_ID] = ctx->i32;
5712 params[SI_PARAM_REL_IDS] = ctx->i32;
5713 num_params = SI_PARAM_REL_IDS+1;
5714
5715 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5716 * placed after the user SGPRs.
5717 */
5718 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5719 returns[num_returns++] = ctx->i32; /* SGPRs */
5720
5721 for (i = 0; i < 3; i++)
5722 returns[num_returns++] = ctx->f32; /* VGPRs */
5723 break;
5724
5725 case PIPE_SHADER_TESS_EVAL:
5726 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5727 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5728
5729 if (shader->key.as_es) {
5730 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5731 params[num_params++] = ctx->i32;
5732 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5733 } else {
5734 params[num_params++] = ctx->i32;
5735 declare_streamout_params(ctx, &shader->selector->so,
5736 params, ctx->i32, &num_params);
5737 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5738 }
5739 last_sgpr = num_params - 1;
5740
5741 /* VGPRs */
5742 params[ctx->param_tes_u = num_params++] = ctx->f32;
5743 params[ctx->param_tes_v = num_params++] = ctx->f32;
5744 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5745 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5746
5747 /* PrimitiveID output. */
5748 if (!shader->key.as_es)
5749 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5750 returns[num_returns++] = ctx->f32;
5751 break;
5752
5753 case PIPE_SHADER_GEOMETRY:
5754 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5755 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5756 last_sgpr = SI_PARAM_GS_WAVE_ID;
5757
5758 /* VGPRs */
5759 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5760 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5761 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5762 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5763 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5764 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5765 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5766 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5767 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5768 break;
5769
5770 case PIPE_SHADER_FRAGMENT:
5771 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5772 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5773 last_sgpr = SI_PARAM_PRIM_MASK;
5774 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5775 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5776 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5777 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5778 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5779 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5780 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5781 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5782 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5783 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5784 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5785 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5786 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5787 shader->info.face_vgpr_index = 20;
5788 params[SI_PARAM_ANCILLARY] = ctx->i32;
5789 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5790 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5791 num_params = SI_PARAM_POS_FIXED_PT+1;
5792
5793 /* Color inputs from the prolog. */
5794 if (shader->selector->info.colors_read) {
5795 unsigned num_color_elements =
5796 util_bitcount(shader->selector->info.colors_read);
5797
5798 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5799 for (i = 0; i < num_color_elements; i++)
5800 params[num_params++] = ctx->f32;
5801
5802 num_prolog_vgprs += num_color_elements;
5803 }
5804
5805 /* Outputs for the epilog. */
5806 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5807 num_returns =
5808 num_return_sgprs +
5809 util_bitcount(shader->selector->info.colors_written) * 4 +
5810 shader->selector->info.writes_z +
5811 shader->selector->info.writes_stencil +
5812 shader->selector->info.writes_samplemask +
5813 1 /* SampleMaskIn */;
5814
5815 num_returns = MAX2(num_returns,
5816 num_return_sgprs +
5817 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5818
5819 for (i = 0; i < num_return_sgprs; i++)
5820 returns[i] = ctx->i32;
5821 for (; i < num_returns; i++)
5822 returns[i] = ctx->f32;
5823 break;
5824
5825 case PIPE_SHADER_COMPUTE:
5826 params[SI_PARAM_GRID_SIZE] = v3i32;
5827 params[SI_PARAM_BLOCK_SIZE] = v3i32;
5828 params[SI_PARAM_BLOCK_ID] = v3i32;
5829 last_sgpr = SI_PARAM_BLOCK_ID;
5830
5831 params[SI_PARAM_THREAD_ID] = v3i32;
5832 num_params = SI_PARAM_THREAD_ID + 1;
5833 break;
5834 default:
5835 assert(0 && "unimplemented shader");
5836 return;
5837 }
5838
5839 assert(num_params <= ARRAY_SIZE(params));
5840
5841 si_create_function(ctx, "main", returns, num_returns, params,
5842 num_params, last_sgpr);
5843
5844 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5845 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5846 ctx->separate_prolog) {
5847 si_llvm_add_attribute(ctx->main_fn,
5848 "InitialPSInputAddr",
5849 S_0286D0_PERSP_SAMPLE_ENA(1) |
5850 S_0286D0_PERSP_CENTER_ENA(1) |
5851 S_0286D0_PERSP_CENTROID_ENA(1) |
5852 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5853 S_0286D0_LINEAR_CENTER_ENA(1) |
5854 S_0286D0_LINEAR_CENTROID_ENA(1) |
5855 S_0286D0_FRONT_FACE_ENA(1) |
5856 S_0286D0_POS_FIXED_PT_ENA(1));
5857 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5858 si_llvm_add_attribute(ctx->main_fn,
5859 "amdgpu-max-work-group-size",
5860 si_get_max_workgroup_size(shader));
5861 }
5862
5863 shader->info.num_input_sgprs = 0;
5864 shader->info.num_input_vgprs = 0;
5865
5866 for (i = 0; i <= last_sgpr; ++i)
5867 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5868
5869 for (; i < num_params; ++i)
5870 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5871
5872 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5873 shader->info.num_input_vgprs -= num_prolog_vgprs;
5874
5875 if (!ctx->screen->has_ds_bpermute &&
5876 bld_base->info &&
5877 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5878 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5879 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5880 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5881 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5882 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5883 ctx->lds =
5884 LLVMAddGlobalInAddressSpace(gallivm->module,
5885 LLVMArrayType(ctx->i32, 64),
5886 "ddxy_lds",
5887 LOCAL_ADDR_SPACE);
5888
5889 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.as_ls) ||
5890 ctx->type == PIPE_SHADER_TESS_CTRL)
5891 declare_tess_lds(ctx);
5892 }
5893
5894 /**
5895 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5896 * for later use.
5897 */
5898 static void preload_ring_buffers(struct si_shader_context *ctx)
5899 {
5900 struct gallivm_state *gallivm = &ctx->gallivm;
5901 LLVMBuilderRef builder = gallivm->builder;
5902
5903 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5904 SI_PARAM_RW_BUFFERS);
5905
5906 if ((ctx->type == PIPE_SHADER_VERTEX &&
5907 ctx->shader->key.as_es) ||
5908 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5909 ctx->shader->key.as_es) ||
5910 ctx->type == PIPE_SHADER_GEOMETRY) {
5911 unsigned ring =
5912 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5913 : SI_ES_RING_ESGS;
5914 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
5915
5916 ctx->esgs_ring =
5917 ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
5918 }
5919
5920 if (ctx->shader->is_gs_copy_shader) {
5921 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5922
5923 ctx->gsvs_ring[0] =
5924 ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
5925 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5926 const struct si_shader_selector *sel = ctx->shader->selector;
5927 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5928 LLVMValueRef base_ring;
5929
5930 base_ring = ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
5931
5932 /* The conceptual layout of the GSVS ring is
5933 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5934 * but the real memory layout is swizzled across
5935 * threads:
5936 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5937 * t16v0c0 ..
5938 * Override the buffer descriptor accordingly.
5939 */
5940 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5941 uint64_t stream_offset = 0;
5942
5943 for (unsigned stream = 0; stream < 4; ++stream) {
5944 unsigned num_components;
5945 unsigned stride;
5946 unsigned num_records;
5947 LLVMValueRef ring, tmp;
5948
5949 num_components = sel->info.num_stream_output_components[stream];
5950 if (!num_components)
5951 continue;
5952
5953 stride = 4 * num_components * sel->gs_max_out_vertices;
5954
5955 /* Limit on the stride field for <= CIK. */
5956 assert(stride < (1 << 14));
5957
5958 num_records = 64;
5959
5960 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5961 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
5962 tmp = LLVMBuildAdd(builder, tmp,
5963 LLVMConstInt(ctx->i64,
5964 stream_offset, 0), "");
5965 stream_offset += stride * 64;
5966
5967 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5968 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5969 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5970 tmp = LLVMBuildOr(builder, tmp,
5971 LLVMConstInt(ctx->i32,
5972 S_008F04_STRIDE(stride) |
5973 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5974 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5975 ring = LLVMBuildInsertElement(builder, ring,
5976 LLVMConstInt(ctx->i32, num_records, 0),
5977 LLVMConstInt(ctx->i32, 2, 0), "");
5978 ring = LLVMBuildInsertElement(builder, ring,
5979 LLVMConstInt(ctx->i32,
5980 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5981 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5982 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5983 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5984 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5985 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5986 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5987 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5988 S_008F0C_ADD_TID_ENABLE(1),
5989 0),
5990 LLVMConstInt(ctx->i32, 3, 0), "");
5991 ring = LLVMBuildBitCast(builder, ring, ctx->v16i8, "");
5992
5993 ctx->gsvs_ring[stream] = ring;
5994 }
5995 }
5996 }
5997
5998 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5999 LLVMValueRef param_rw_buffers,
6000 unsigned param_pos_fixed_pt)
6001 {
6002 struct gallivm_state *gallivm = &ctx->gallivm;
6003 LLVMBuilderRef builder = gallivm->builder;
6004 LLVMValueRef slot, desc, offset, row, bit, address[2];
6005
6006 /* Use the fixed-point gl_FragCoord input.
6007 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
6008 * per coordinate to get the repeating effect.
6009 */
6010 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
6011 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
6012
6013 /* Load the buffer descriptor. */
6014 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
6015 desc = ac_build_indexed_load_const(&ctx->ac, param_rw_buffers, slot);
6016
6017 /* The stipple pattern is 32x32, each row has 32 bits. */
6018 offset = LLVMBuildMul(builder, address[1],
6019 LLVMConstInt(ctx->i32, 4, 0), "");
6020 row = buffer_load_const(ctx, desc, offset);
6021 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
6022 bit = LLVMBuildLShr(builder, row, address[0], "");
6023 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
6024
6025 /* The intrinsic kills the thread if arg < 0. */
6026 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
6027 LLVMConstReal(ctx->f32, -1), "");
6028 ac_build_kill(&ctx->ac, bit);
6029 }
6030
6031 void si_shader_binary_read_config(struct ac_shader_binary *binary,
6032 struct si_shader_config *conf,
6033 unsigned symbol_offset)
6034 {
6035 unsigned i;
6036 const unsigned char *config =
6037 ac_shader_binary_config_start(binary, symbol_offset);
6038 bool really_needs_scratch = false;
6039
6040 /* LLVM adds SGPR spills to the scratch size.
6041 * Find out if we really need the scratch buffer.
6042 */
6043 for (i = 0; i < binary->reloc_count; i++) {
6044 const struct ac_shader_reloc *reloc = &binary->relocs[i];
6045
6046 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
6047 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
6048 really_needs_scratch = true;
6049 break;
6050 }
6051 }
6052
6053 /* XXX: We may be able to emit some of these values directly rather than
6054 * extracting fields to be emitted later.
6055 */
6056
6057 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
6058 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
6059 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
6060 switch (reg) {
6061 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
6062 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
6063 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
6064 case R_00B848_COMPUTE_PGM_RSRC1:
6065 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
6066 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
6067 conf->float_mode = G_00B028_FLOAT_MODE(value);
6068 conf->rsrc1 = value;
6069 break;
6070 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
6071 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
6072 break;
6073 case R_00B84C_COMPUTE_PGM_RSRC2:
6074 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
6075 conf->rsrc2 = value;
6076 break;
6077 case R_0286CC_SPI_PS_INPUT_ENA:
6078 conf->spi_ps_input_ena = value;
6079 break;
6080 case R_0286D0_SPI_PS_INPUT_ADDR:
6081 conf->spi_ps_input_addr = value;
6082 break;
6083 case R_0286E8_SPI_TMPRING_SIZE:
6084 case R_00B860_COMPUTE_TMPRING_SIZE:
6085 /* WAVESIZE is in units of 256 dwords. */
6086 if (really_needs_scratch)
6087 conf->scratch_bytes_per_wave =
6088 G_00B860_WAVESIZE(value) * 256 * 4;
6089 break;
6090 case 0x4: /* SPILLED_SGPRS */
6091 conf->spilled_sgprs = value;
6092 break;
6093 case 0x8: /* SPILLED_VGPRS */
6094 conf->spilled_vgprs = value;
6095 break;
6096 default:
6097 {
6098 static bool printed;
6099
6100 if (!printed) {
6101 fprintf(stderr, "Warning: LLVM emitted unknown "
6102 "config register: 0x%x\n", reg);
6103 printed = true;
6104 }
6105 }
6106 break;
6107 }
6108 }
6109
6110 if (!conf->spi_ps_input_addr)
6111 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
6112 }
6113
6114 void si_shader_apply_scratch_relocs(struct si_context *sctx,
6115 struct si_shader *shader,
6116 struct si_shader_config *config,
6117 uint64_t scratch_va)
6118 {
6119 unsigned i;
6120 uint32_t scratch_rsrc_dword0 = scratch_va;
6121 uint32_t scratch_rsrc_dword1 =
6122 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
6123
6124 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
6125 * correctly.
6126 */
6127 if (HAVE_LLVM >= 0x0309)
6128 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
6129 else
6130 scratch_rsrc_dword1 |=
6131 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
6132
6133 for (i = 0 ; i < shader->binary.reloc_count; i++) {
6134 const struct ac_shader_reloc *reloc =
6135 &shader->binary.relocs[i];
6136 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
6137 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
6138 &scratch_rsrc_dword0, 4);
6139 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
6140 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
6141 &scratch_rsrc_dword1, 4);
6142 }
6143 }
6144 }
6145
6146 static unsigned si_get_shader_binary_size(struct si_shader *shader)
6147 {
6148 unsigned size = shader->binary.code_size;
6149
6150 if (shader->prolog)
6151 size += shader->prolog->binary.code_size;
6152 if (shader->epilog)
6153 size += shader->epilog->binary.code_size;
6154 return size;
6155 }
6156
6157 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
6158 {
6159 const struct ac_shader_binary *prolog =
6160 shader->prolog ? &shader->prolog->binary : NULL;
6161 const struct ac_shader_binary *epilog =
6162 shader->epilog ? &shader->epilog->binary : NULL;
6163 const struct ac_shader_binary *mainb = &shader->binary;
6164 unsigned bo_size = si_get_shader_binary_size(shader) +
6165 (!epilog ? mainb->rodata_size : 0);
6166 unsigned char *ptr;
6167
6168 assert(!prolog || !prolog->rodata_size);
6169 assert((!prolog && !epilog) || !mainb->rodata_size);
6170 assert(!epilog || !epilog->rodata_size);
6171
6172 /* GFX9 can fetch at most 128 bytes past the end of the shader.
6173 * Prevent VM faults.
6174 */
6175 if (sscreen->b.chip_class >= GFX9)
6176 bo_size += 128;
6177
6178 r600_resource_reference(&shader->bo, NULL);
6179 shader->bo = (struct r600_resource*)
6180 pipe_buffer_create(&sscreen->b.b, 0,
6181 PIPE_USAGE_IMMUTABLE,
6182 align(bo_size, SI_CPDMA_ALIGNMENT));
6183 if (!shader->bo)
6184 return -ENOMEM;
6185
6186 /* Upload. */
6187 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
6188 PIPE_TRANSFER_READ_WRITE);
6189
6190 if (prolog) {
6191 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
6192 ptr += prolog->code_size;
6193 }
6194
6195 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
6196 ptr += mainb->code_size;
6197
6198 if (epilog)
6199 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
6200 else if (mainb->rodata_size > 0)
6201 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
6202
6203 sscreen->b.ws->buffer_unmap(shader->bo->buf);
6204 return 0;
6205 }
6206
6207 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
6208 struct pipe_debug_callback *debug,
6209 const char *name, FILE *file)
6210 {
6211 char *line, *p;
6212 unsigned i, count;
6213
6214 if (binary->disasm_string) {
6215 fprintf(file, "Shader %s disassembly:\n", name);
6216 fprintf(file, "%s", binary->disasm_string);
6217
6218 if (debug && debug->debug_message) {
6219 /* Very long debug messages are cut off, so send the
6220 * disassembly one line at a time. This causes more
6221 * overhead, but on the plus side it simplifies
6222 * parsing of resulting logs.
6223 */
6224 pipe_debug_message(debug, SHADER_INFO,
6225 "Shader Disassembly Begin");
6226
6227 line = binary->disasm_string;
6228 while (*line) {
6229 p = util_strchrnul(line, '\n');
6230 count = p - line;
6231
6232 if (count) {
6233 pipe_debug_message(debug, SHADER_INFO,
6234 "%.*s", count, line);
6235 }
6236
6237 if (!*p)
6238 break;
6239 line = p + 1;
6240 }
6241
6242 pipe_debug_message(debug, SHADER_INFO,
6243 "Shader Disassembly End");
6244 }
6245 } else {
6246 fprintf(file, "Shader %s binary:\n", name);
6247 for (i = 0; i < binary->code_size; i += 4) {
6248 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
6249 binary->code[i + 3], binary->code[i + 2],
6250 binary->code[i + 1], binary->code[i]);
6251 }
6252 }
6253 }
6254
6255 static void si_shader_dump_stats(struct si_screen *sscreen,
6256 struct si_shader *shader,
6257 struct pipe_debug_callback *debug,
6258 unsigned processor,
6259 FILE *file,
6260 bool check_debug_option)
6261 {
6262 struct si_shader_config *conf = &shader->config;
6263 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
6264 unsigned code_size = si_get_shader_binary_size(shader);
6265 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
6266 unsigned lds_per_wave = 0;
6267 unsigned max_simd_waves = 10;
6268
6269 /* Compute LDS usage for PS. */
6270 switch (processor) {
6271 case PIPE_SHADER_FRAGMENT:
6272 /* The minimum usage per wave is (num_inputs * 48). The maximum
6273 * usage is (num_inputs * 48 * 16).
6274 * We can get anything in between and it varies between waves.
6275 *
6276 * The 48 bytes per input for a single primitive is equal to
6277 * 4 bytes/component * 4 components/input * 3 points.
6278 *
6279 * Other stages don't know the size at compile time or don't
6280 * allocate LDS per wave, but instead they do it per thread group.
6281 */
6282 lds_per_wave = conf->lds_size * lds_increment +
6283 align(num_inputs * 48, lds_increment);
6284 break;
6285 case PIPE_SHADER_COMPUTE:
6286 if (shader->selector) {
6287 unsigned max_workgroup_size =
6288 si_get_max_workgroup_size(shader);
6289 lds_per_wave = (conf->lds_size * lds_increment) /
6290 DIV_ROUND_UP(max_workgroup_size, 64);
6291 }
6292 break;
6293 }
6294
6295 /* Compute the per-SIMD wave counts. */
6296 if (conf->num_sgprs) {
6297 if (sscreen->b.chip_class >= VI)
6298 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
6299 else
6300 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
6301 }
6302
6303 if (conf->num_vgprs)
6304 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
6305
6306 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
6307 * 16KB makes some SIMDs unoccupied). */
6308 if (lds_per_wave)
6309 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
6310
6311 if (!check_debug_option ||
6312 r600_can_dump_shader(&sscreen->b, processor)) {
6313 if (processor == PIPE_SHADER_FRAGMENT) {
6314 fprintf(file, "*** SHADER CONFIG ***\n"
6315 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6316 "SPI_PS_INPUT_ENA = 0x%04x\n",
6317 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
6318 }
6319
6320 fprintf(file, "*** SHADER STATS ***\n"
6321 "SGPRS: %d\n"
6322 "VGPRS: %d\n"
6323 "Spilled SGPRs: %d\n"
6324 "Spilled VGPRs: %d\n"
6325 "Private memory VGPRs: %d\n"
6326 "Code Size: %d bytes\n"
6327 "LDS: %d blocks\n"
6328 "Scratch: %d bytes per wave\n"
6329 "Max Waves: %d\n"
6330 "********************\n\n\n",
6331 conf->num_sgprs, conf->num_vgprs,
6332 conf->spilled_sgprs, conf->spilled_vgprs,
6333 conf->private_mem_vgprs, code_size,
6334 conf->lds_size, conf->scratch_bytes_per_wave,
6335 max_simd_waves);
6336 }
6337
6338 pipe_debug_message(debug, SHADER_INFO,
6339 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6340 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
6341 "Spilled VGPRs: %d PrivMem VGPRs: %d",
6342 conf->num_sgprs, conf->num_vgprs, code_size,
6343 conf->lds_size, conf->scratch_bytes_per_wave,
6344 max_simd_waves, conf->spilled_sgprs,
6345 conf->spilled_vgprs, conf->private_mem_vgprs);
6346 }
6347
6348 const char *si_get_shader_name(struct si_shader *shader, unsigned processor)
6349 {
6350 switch (processor) {
6351 case PIPE_SHADER_VERTEX:
6352 if (shader->key.as_es)
6353 return "Vertex Shader as ES";
6354 else if (shader->key.as_ls)
6355 return "Vertex Shader as LS";
6356 else
6357 return "Vertex Shader as VS";
6358 case PIPE_SHADER_TESS_CTRL:
6359 return "Tessellation Control Shader";
6360 case PIPE_SHADER_TESS_EVAL:
6361 if (shader->key.as_es)
6362 return "Tessellation Evaluation Shader as ES";
6363 else
6364 return "Tessellation Evaluation Shader as VS";
6365 case PIPE_SHADER_GEOMETRY:
6366 if (shader->is_gs_copy_shader)
6367 return "GS Copy Shader as VS";
6368 else
6369 return "Geometry Shader";
6370 case PIPE_SHADER_FRAGMENT:
6371 return "Pixel Shader";
6372 case PIPE_SHADER_COMPUTE:
6373 return "Compute Shader";
6374 default:
6375 return "Unknown Shader";
6376 }
6377 }
6378
6379 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6380 struct pipe_debug_callback *debug, unsigned processor,
6381 FILE *file, bool check_debug_option)
6382 {
6383 if (!check_debug_option ||
6384 r600_can_dump_shader(&sscreen->b, processor))
6385 si_dump_shader_key(processor, &shader->key, file);
6386
6387 if (!check_debug_option && shader->binary.llvm_ir_string) {
6388 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
6389 si_get_shader_name(shader, processor));
6390 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
6391 }
6392
6393 if (!check_debug_option ||
6394 (r600_can_dump_shader(&sscreen->b, processor) &&
6395 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6396 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6397
6398 if (shader->prolog)
6399 si_shader_dump_disassembly(&shader->prolog->binary,
6400 debug, "prolog", file);
6401
6402 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6403
6404 if (shader->epilog)
6405 si_shader_dump_disassembly(&shader->epilog->binary,
6406 debug, "epilog", file);
6407 fprintf(file, "\n");
6408 }
6409
6410 si_shader_dump_stats(sscreen, shader, debug, processor, file,
6411 check_debug_option);
6412 }
6413
6414 int si_compile_llvm(struct si_screen *sscreen,
6415 struct ac_shader_binary *binary,
6416 struct si_shader_config *conf,
6417 LLVMTargetMachineRef tm,
6418 LLVMModuleRef mod,
6419 struct pipe_debug_callback *debug,
6420 unsigned processor,
6421 const char *name)
6422 {
6423 int r = 0;
6424 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6425
6426 if (r600_can_dump_shader(&sscreen->b, processor)) {
6427 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6428
6429 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6430 fprintf(stderr, "%s LLVM IR:\n\n", name);
6431 ac_dump_module(mod);
6432 fprintf(stderr, "\n");
6433 }
6434 }
6435
6436 if (sscreen->record_llvm_ir) {
6437 char *ir = LLVMPrintModuleToString(mod);
6438 binary->llvm_ir_string = strdup(ir);
6439 LLVMDisposeMessage(ir);
6440 }
6441
6442 if (!si_replace_shader(count, binary)) {
6443 r = si_llvm_compile(mod, binary, tm, debug);
6444 if (r)
6445 return r;
6446 }
6447
6448 si_shader_binary_read_config(binary, conf, 0);
6449
6450 /* Enable 64-bit and 16-bit denormals, because there is no performance
6451 * cost.
6452 *
6453 * If denormals are enabled, all floating-point output modifiers are
6454 * ignored.
6455 *
6456 * Don't enable denormals for 32-bit floats, because:
6457 * - Floating-point output modifiers would be ignored by the hw.
6458 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6459 * have to stop using those.
6460 * - SI & CI would be very slow.
6461 */
6462 conf->float_mode |= V_00B028_FP_64_DENORMS;
6463
6464 FREE(binary->config);
6465 FREE(binary->global_symbol_offsets);
6466 binary->config = NULL;
6467 binary->global_symbol_offsets = NULL;
6468
6469 /* Some shaders can't have rodata because their binaries can be
6470 * concatenated.
6471 */
6472 if (binary->rodata_size &&
6473 (processor == PIPE_SHADER_VERTEX ||
6474 processor == PIPE_SHADER_TESS_CTRL ||
6475 processor == PIPE_SHADER_TESS_EVAL ||
6476 processor == PIPE_SHADER_FRAGMENT)) {
6477 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6478 return -EINVAL;
6479 }
6480
6481 return r;
6482 }
6483
6484 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6485 {
6486 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6487 LLVMBuildRetVoid(ctx->gallivm.builder);
6488 else
6489 LLVMBuildRet(ctx->gallivm.builder, ret);
6490 }
6491
6492 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6493 struct si_shader *
6494 si_generate_gs_copy_shader(struct si_screen *sscreen,
6495 LLVMTargetMachineRef tm,
6496 struct si_shader_selector *gs_selector,
6497 struct pipe_debug_callback *debug)
6498 {
6499 struct si_shader_context ctx;
6500 struct si_shader *shader;
6501 struct gallivm_state *gallivm = &ctx.gallivm;
6502 LLVMBuilderRef builder;
6503 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
6504 struct lp_build_context *uint = &bld_base->uint_bld;
6505 struct si_shader_output_values *outputs;
6506 struct tgsi_shader_info *gsinfo = &gs_selector->info;
6507 int i, r;
6508
6509 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6510
6511 if (!outputs)
6512 return NULL;
6513
6514 shader = CALLOC_STRUCT(si_shader);
6515 if (!shader) {
6516 FREE(outputs);
6517 return NULL;
6518 }
6519
6520
6521 shader->selector = gs_selector;
6522 shader->is_gs_copy_shader = true;
6523
6524 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6525 ctx.type = PIPE_SHADER_VERTEX;
6526
6527 builder = gallivm->builder;
6528
6529 create_function(&ctx);
6530 preload_ring_buffers(&ctx);
6531
6532 LLVMValueRef voffset =
6533 lp_build_mul_imm(uint, LLVMGetParam(ctx.main_fn,
6534 ctx.param_vertex_id), 4);
6535
6536 /* Fetch the vertex stream ID.*/
6537 LLVMValueRef stream_id;
6538
6539 if (gs_selector->so.num_outputs)
6540 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
6541 else
6542 stream_id = ctx.i32_0;
6543
6544 /* Fill in output information. */
6545 for (i = 0; i < gsinfo->num_outputs; ++i) {
6546 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
6547 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
6548
6549 for (int chan = 0; chan < 4; chan++) {
6550 outputs[i].vertex_stream[chan] =
6551 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
6552 }
6553 }
6554
6555 LLVMBasicBlockRef end_bb;
6556 LLVMValueRef switch_inst;
6557
6558 end_bb = LLVMAppendBasicBlockInContext(gallivm->context, ctx.main_fn, "end");
6559 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
6560
6561 for (int stream = 0; stream < 4; stream++) {
6562 LLVMBasicBlockRef bb;
6563 unsigned offset;
6564
6565 if (!gsinfo->num_stream_output_components[stream])
6566 continue;
6567
6568 if (stream > 0 && !gs_selector->so.num_outputs)
6569 continue;
6570
6571 bb = LLVMInsertBasicBlockInContext(gallivm->context, end_bb, "out");
6572 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
6573 LLVMPositionBuilderAtEnd(builder, bb);
6574
6575 /* Fetch vertex data from GSVS ring */
6576 offset = 0;
6577 for (i = 0; i < gsinfo->num_outputs; ++i) {
6578 for (unsigned chan = 0; chan < 4; chan++) {
6579 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
6580 outputs[i].vertex_stream[chan] != stream) {
6581 outputs[i].values[chan] = ctx.bld_base.base.undef;
6582 continue;
6583 }
6584
6585 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
6586 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
6587 offset++;
6588
6589 outputs[i].values[chan] =
6590 ac_build_buffer_load(&ctx.ac,
6591 ctx.gsvs_ring[0], 1,
6592 ctx.i32_0, voffset,
6593 soffset, 0, 1, 1, true);
6594 }
6595 }
6596
6597 /* Streamout and exports. */
6598 if (gs_selector->so.num_outputs) {
6599 si_llvm_emit_streamout(&ctx, outputs,
6600 gsinfo->num_outputs,
6601 stream);
6602 }
6603
6604 if (stream == 0)
6605 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6606
6607 LLVMBuildBr(builder, end_bb);
6608 }
6609
6610 LLVMPositionBuilderAtEnd(builder, end_bb);
6611
6612 LLVMBuildRetVoid(gallivm->builder);
6613
6614 /* Dump LLVM IR before any optimization passes */
6615 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6616 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6617 ac_dump_module(ctx.gallivm.module);
6618
6619 si_llvm_finalize_module(&ctx,
6620 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_GEOMETRY));
6621
6622 r = si_compile_llvm(sscreen, &ctx.shader->binary,
6623 &ctx.shader->config, ctx.tm,
6624 ctx.gallivm.module,
6625 debug, PIPE_SHADER_GEOMETRY,
6626 "GS Copy Shader");
6627 if (!r) {
6628 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6629 fprintf(stderr, "GS Copy Shader:\n");
6630 si_shader_dump(sscreen, ctx.shader, debug,
6631 PIPE_SHADER_GEOMETRY, stderr, true);
6632 r = si_shader_binary_upload(sscreen, ctx.shader);
6633 }
6634
6635 si_llvm_dispose(&ctx);
6636
6637 FREE(outputs);
6638
6639 if (r != 0) {
6640 FREE(shader);
6641 shader = NULL;
6642 }
6643 return shader;
6644 }
6645
6646 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
6647 FILE *f)
6648 {
6649 int i;
6650
6651 fprintf(f, "SHADER KEY\n");
6652
6653 switch (shader) {
6654 case PIPE_SHADER_VERTEX:
6655 fprintf(f, " part.vs.prolog.instance_divisors = {");
6656 for (i = 0; i < ARRAY_SIZE(key->part.vs.prolog.instance_divisors); i++)
6657 fprintf(f, !i ? "%u" : ", %u",
6658 key->part.vs.prolog.instance_divisors[i]);
6659 fprintf(f, "}\n");
6660 fprintf(f, " part.vs.epilog.export_prim_id = %u\n", key->part.vs.epilog.export_prim_id);
6661 fprintf(f, " as_es = %u\n", key->as_es);
6662 fprintf(f, " as_ls = %u\n", key->as_ls);
6663
6664 fprintf(f, " mono.vs_fix_fetch = {");
6665 for (i = 0; i < SI_MAX_ATTRIBS; i++)
6666 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
6667 fprintf(f, "}\n");
6668 break;
6669
6670 case PIPE_SHADER_TESS_CTRL:
6671 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
6672 fprintf(f, " mono.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.ff_tcs_inputs_to_copy);
6673 break;
6674
6675 case PIPE_SHADER_TESS_EVAL:
6676 fprintf(f, " part.tes.epilog.export_prim_id = %u\n", key->part.tes.epilog.export_prim_id);
6677 fprintf(f, " as_es = %u\n", key->as_es);
6678 break;
6679
6680 case PIPE_SHADER_GEOMETRY:
6681 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
6682 break;
6683
6684 case PIPE_SHADER_COMPUTE:
6685 break;
6686
6687 case PIPE_SHADER_FRAGMENT:
6688 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
6689 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
6690 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
6691 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
6692 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
6693 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
6694 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
6695 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
6696 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
6697 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
6698 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
6699 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
6700 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
6701 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
6702 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
6703 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
6704 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
6705 break;
6706
6707 default:
6708 assert(0);
6709 }
6710
6711 if ((shader == PIPE_SHADER_GEOMETRY ||
6712 shader == PIPE_SHADER_TESS_EVAL ||
6713 shader == PIPE_SHADER_VERTEX) &&
6714 !key->as_es && !key->as_ls) {
6715 fprintf(f, " opt.hw_vs.kill_outputs = 0x%"PRIx64"\n", key->opt.hw_vs.kill_outputs);
6716 fprintf(f, " opt.hw_vs.kill_outputs2 = 0x%x\n", key->opt.hw_vs.kill_outputs2);
6717 fprintf(f, " opt.hw_vs.clip_disable = %u\n", key->opt.hw_vs.clip_disable);
6718 }
6719 }
6720
6721 static void si_init_shader_ctx(struct si_shader_context *ctx,
6722 struct si_screen *sscreen,
6723 struct si_shader *shader,
6724 LLVMTargetMachineRef tm)
6725 {
6726 struct lp_build_tgsi_context *bld_base;
6727 struct lp_build_tgsi_action tmpl = {};
6728
6729 si_llvm_context_init(ctx, sscreen, shader, tm,
6730 (shader && shader->selector) ? &shader->selector->info : NULL,
6731 (shader && shader->selector) ? shader->selector->tokens : NULL);
6732
6733 bld_base = &ctx->bld_base;
6734 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6735
6736 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6737 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6738 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6739
6740 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6741 bld_base->op_actions[TGSI_OPCODE_TEX_LZ] = tex_action;
6742 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6743 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6744 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6745 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6746 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6747 bld_base->op_actions[TGSI_OPCODE_TXF_LZ] = tex_action;
6748 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6749 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6750 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6751 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6752 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6753 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6754 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6755 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6756
6757 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6758 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6759 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6760 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6761 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6762 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6763
6764 tmpl.fetch_args = atomic_fetch_args;
6765 tmpl.emit = atomic_emit;
6766 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6767 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6768 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6769 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6770 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6771 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6772 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6773 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6774 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6775 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6776 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6777 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6778 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6779 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6780 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6781 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6782 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6783 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6784 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6785 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6786
6787 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6788
6789 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
6790
6791 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6792 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6793 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6794 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6795
6796 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
6797 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
6798 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
6799 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
6800 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
6801 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
6802 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
6803 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
6804 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
6805
6806 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6807 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6808 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6809 }
6810
6811 #define EXP_TARGET (HAVE_LLVM >= 0x0500 ? 0 : 3)
6812 #define EXP_OUT0 (HAVE_LLVM >= 0x0500 ? 2 : 5)
6813
6814 /* Return true if the PARAM export has been eliminated. */
6815 static bool si_eliminate_const_output(struct si_shader_context *ctx,
6816 LLVMValueRef inst, unsigned offset)
6817 {
6818 struct si_shader *shader = ctx->shader;
6819 unsigned num_outputs = shader->selector->info.num_outputs;
6820 unsigned i, default_val; /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL */
6821 bool is_zero[4] = {}, is_one[4] = {};
6822
6823 for (i = 0; i < 4; i++) {
6824 LLVMBool loses_info;
6825 LLVMValueRef p = LLVMGetOperand(inst, EXP_OUT0 + i);
6826
6827 /* It's a constant expression. Undef outputs are eliminated too. */
6828 if (LLVMIsUndef(p)) {
6829 is_zero[i] = true;
6830 is_one[i] = true;
6831 } else if (LLVMIsAConstantFP(p)) {
6832 double a = LLVMConstRealGetDouble(p, &loses_info);
6833
6834 if (a == 0)
6835 is_zero[i] = true;
6836 else if (a == 1)
6837 is_one[i] = true;
6838 else
6839 return false; /* other constant */
6840 } else
6841 return false;
6842 }
6843
6844 /* Only certain combinations of 0 and 1 can be eliminated. */
6845 if (is_zero[0] && is_zero[1] && is_zero[2])
6846 default_val = is_zero[3] ? 0 : 1;
6847 else if (is_one[0] && is_one[1] && is_one[2])
6848 default_val = is_zero[3] ? 2 : 3;
6849 else
6850 return false;
6851
6852 /* The PARAM export can be represented as DEFAULT_VAL. Kill it. */
6853 LLVMInstructionEraseFromParent(inst);
6854
6855 /* Change OFFSET to DEFAULT_VAL. */
6856 for (i = 0; i < num_outputs; i++) {
6857 if (shader->info.vs_output_param_offset[i] == offset) {
6858 shader->info.vs_output_param_offset[i] =
6859 EXP_PARAM_DEFAULT_VAL_0000 + default_val;
6860 break;
6861 }
6862 }
6863 return true;
6864 }
6865
6866 struct si_vs_exports {
6867 unsigned num;
6868 unsigned offset[SI_MAX_VS_OUTPUTS];
6869 LLVMValueRef inst[SI_MAX_VS_OUTPUTS];
6870 };
6871
6872 static void si_eliminate_const_vs_outputs(struct si_shader_context *ctx)
6873 {
6874 struct si_shader *shader = ctx->shader;
6875 struct tgsi_shader_info *info = &shader->selector->info;
6876 LLVMBasicBlockRef bb;
6877 struct si_vs_exports exports;
6878 bool removed_any = false;
6879
6880 exports.num = 0;
6881
6882 if (ctx->type == PIPE_SHADER_FRAGMENT ||
6883 ctx->type == PIPE_SHADER_COMPUTE ||
6884 shader->key.as_es ||
6885 shader->key.as_ls)
6886 return;
6887
6888 /* Process all LLVM instructions. */
6889 bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6890 while (bb) {
6891 LLVMValueRef inst = LLVMGetFirstInstruction(bb);
6892
6893 while (inst) {
6894 LLVMValueRef cur = inst;
6895 inst = LLVMGetNextInstruction(inst);
6896
6897 if (LLVMGetInstructionOpcode(cur) != LLVMCall)
6898 continue;
6899
6900 LLVMValueRef callee = lp_get_called_value(cur);
6901
6902 if (!lp_is_function(callee))
6903 continue;
6904
6905 const char *name = LLVMGetValueName(callee);
6906 unsigned num_args = LLVMCountParams(callee);
6907
6908 /* Check if this is an export instruction. */
6909 if ((num_args != 9 && num_args != 8) ||
6910 (strcmp(name, "llvm.SI.export") &&
6911 strcmp(name, "llvm.amdgcn.exp.f32")))
6912 continue;
6913
6914 LLVMValueRef arg = LLVMGetOperand(cur, EXP_TARGET);
6915 unsigned target = LLVMConstIntGetZExtValue(arg);
6916
6917 if (target < V_008DFC_SQ_EXP_PARAM)
6918 continue;
6919
6920 target -= V_008DFC_SQ_EXP_PARAM;
6921
6922 /* Eliminate constant value PARAM exports. */
6923 if (si_eliminate_const_output(ctx, cur, target)) {
6924 removed_any = true;
6925 } else {
6926 exports.offset[exports.num] = target;
6927 exports.inst[exports.num] = cur;
6928 exports.num++;
6929 }
6930 }
6931 bb = LLVMGetNextBasicBlock(bb);
6932 }
6933
6934 /* Remove holes in export memory due to removed PARAM exports.
6935 * This is done by renumbering all PARAM exports.
6936 */
6937 if (removed_any) {
6938 ubyte current_offset[SI_MAX_VS_OUTPUTS];
6939 unsigned new_count = 0;
6940 unsigned out, i;
6941
6942 /* Make a copy of the offsets. We need the old version while
6943 * we are modifying some of them. */
6944 assert(sizeof(current_offset) ==
6945 sizeof(shader->info.vs_output_param_offset));
6946 memcpy(current_offset, shader->info.vs_output_param_offset,
6947 sizeof(current_offset));
6948
6949 for (i = 0; i < exports.num; i++) {
6950 unsigned offset = exports.offset[i];
6951
6952 for (out = 0; out < info->num_outputs; out++) {
6953 if (current_offset[out] != offset)
6954 continue;
6955
6956 LLVMSetOperand(exports.inst[i], EXP_TARGET,
6957 LLVMConstInt(ctx->i32,
6958 V_008DFC_SQ_EXP_PARAM + new_count, 0));
6959 shader->info.vs_output_param_offset[out] = new_count;
6960 new_count++;
6961 break;
6962 }
6963 }
6964 shader->info.nr_param_exports = new_count;
6965 }
6966 }
6967
6968 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
6969 {
6970 ctx->shader->config.private_mem_vgprs = 0;
6971
6972 /* Process all LLVM instructions. */
6973 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6974 while (bb) {
6975 LLVMValueRef next = LLVMGetFirstInstruction(bb);
6976
6977 while (next) {
6978 LLVMValueRef inst = next;
6979 next = LLVMGetNextInstruction(next);
6980
6981 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
6982 continue;
6983
6984 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
6985 /* No idea why LLVM aligns allocas to 4 elements. */
6986 unsigned alignment = LLVMGetAlignment(inst);
6987 unsigned dw_size = align(llvm_get_type_size(type) / 4, alignment);
6988 ctx->shader->config.private_mem_vgprs += dw_size;
6989 }
6990 bb = LLVMGetNextBasicBlock(bb);
6991 }
6992 }
6993
6994 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
6995 struct si_shader *shader)
6996 {
6997 struct si_shader_selector *sel = shader->selector;
6998 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6999
7000 switch (ctx->type) {
7001 case PIPE_SHADER_VERTEX:
7002 ctx->load_input = declare_input_vs;
7003 if (shader->key.as_ls)
7004 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
7005 else if (shader->key.as_es)
7006 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
7007 else
7008 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
7009 break;
7010 case PIPE_SHADER_TESS_CTRL:
7011 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
7012 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
7013 bld_base->emit_store = store_output_tcs;
7014 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
7015 break;
7016 case PIPE_SHADER_TESS_EVAL:
7017 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
7018 if (shader->key.as_es)
7019 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
7020 else
7021 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
7022 break;
7023 case PIPE_SHADER_GEOMETRY:
7024 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
7025 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
7026 break;
7027 case PIPE_SHADER_FRAGMENT:
7028 ctx->load_input = declare_input_fs;
7029 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
7030 break;
7031 case PIPE_SHADER_COMPUTE:
7032 ctx->declare_memory_region = declare_compute_memory;
7033 break;
7034 default:
7035 assert(!"Unsupported shader type");
7036 return false;
7037 }
7038
7039 create_function(ctx);
7040 preload_ring_buffers(ctx);
7041
7042 if (ctx->type == PIPE_SHADER_GEOMETRY) {
7043 int i;
7044 for (i = 0; i < 4; i++) {
7045 ctx->gs_next_vertex[i] =
7046 lp_build_alloca(&ctx->gallivm,
7047 ctx->i32, "");
7048 }
7049 }
7050
7051 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
7052 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
7053 return false;
7054 }
7055
7056 si_llvm_build_ret(ctx, ctx->return_value);
7057 return true;
7058 }
7059
7060 /**
7061 * Compute the VS prolog key, which contains all the information needed to
7062 * build the VS prolog function, and set shader->info bits where needed.
7063 */
7064 static void si_get_vs_prolog_key(struct si_shader *shader,
7065 union si_shader_part_key *key)
7066 {
7067 struct tgsi_shader_info *info = &shader->selector->info;
7068
7069 memset(key, 0, sizeof(*key));
7070 key->vs_prolog.states = shader->key.part.vs.prolog;
7071 key->vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7072 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
7073
7074 /* Set the instanceID flag. */
7075 for (unsigned i = 0; i < info->num_inputs; i++)
7076 if (key->vs_prolog.states.instance_divisors[i])
7077 shader->info.uses_instanceid = true;
7078 }
7079
7080 /**
7081 * Compute the VS epilog key, which contains all the information needed to
7082 * build the VS epilog function, and set the PrimitiveID output offset.
7083 */
7084 static void si_get_vs_epilog_key(struct si_shader *shader,
7085 struct si_vs_epilog_bits *states,
7086 union si_shader_part_key *key)
7087 {
7088 memset(key, 0, sizeof(*key));
7089 key->vs_epilog.states = *states;
7090
7091 /* Set up the PrimitiveID output. */
7092 if (shader->key.part.vs.epilog.export_prim_id) {
7093 unsigned index = shader->selector->info.num_outputs;
7094 unsigned offset = shader->info.nr_param_exports++;
7095
7096 key->vs_epilog.prim_id_param_offset = offset;
7097 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
7098 shader->info.vs_output_param_offset[index] = offset;
7099 }
7100 }
7101
7102 /**
7103 * Compute the PS prolog key, which contains all the information needed to
7104 * build the PS prolog function, and set related bits in shader->config.
7105 */
7106 static void si_get_ps_prolog_key(struct si_shader *shader,
7107 union si_shader_part_key *key,
7108 bool separate_prolog)
7109 {
7110 struct tgsi_shader_info *info = &shader->selector->info;
7111
7112 memset(key, 0, sizeof(*key));
7113 key->ps_prolog.states = shader->key.part.ps.prolog;
7114 key->ps_prolog.colors_read = info->colors_read;
7115 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7116 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
7117 key->ps_prolog.wqm = info->uses_derivatives &&
7118 (key->ps_prolog.colors_read ||
7119 key->ps_prolog.states.force_persp_sample_interp ||
7120 key->ps_prolog.states.force_linear_sample_interp ||
7121 key->ps_prolog.states.force_persp_center_interp ||
7122 key->ps_prolog.states.force_linear_center_interp ||
7123 key->ps_prolog.states.bc_optimize_for_persp ||
7124 key->ps_prolog.states.bc_optimize_for_linear);
7125
7126 if (info->colors_read) {
7127 unsigned *color = shader->selector->color_attr_index;
7128
7129 if (shader->key.part.ps.prolog.color_two_side) {
7130 /* BCOLORs are stored after the last input. */
7131 key->ps_prolog.num_interp_inputs = info->num_inputs;
7132 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
7133 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
7134 }
7135
7136 for (unsigned i = 0; i < 2; i++) {
7137 unsigned interp = info->input_interpolate[color[i]];
7138 unsigned location = info->input_interpolate_loc[color[i]];
7139
7140 if (!(info->colors_read & (0xf << i*4)))
7141 continue;
7142
7143 key->ps_prolog.color_attr_index[i] = color[i];
7144
7145 if (shader->key.part.ps.prolog.flatshade_colors &&
7146 interp == TGSI_INTERPOLATE_COLOR)
7147 interp = TGSI_INTERPOLATE_CONSTANT;
7148
7149 switch (interp) {
7150 case TGSI_INTERPOLATE_CONSTANT:
7151 key->ps_prolog.color_interp_vgpr_index[i] = -1;
7152 break;
7153 case TGSI_INTERPOLATE_PERSPECTIVE:
7154 case TGSI_INTERPOLATE_COLOR:
7155 /* Force the interpolation location for colors here. */
7156 if (shader->key.part.ps.prolog.force_persp_sample_interp)
7157 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7158 if (shader->key.part.ps.prolog.force_persp_center_interp)
7159 location = TGSI_INTERPOLATE_LOC_CENTER;
7160
7161 switch (location) {
7162 case TGSI_INTERPOLATE_LOC_SAMPLE:
7163 key->ps_prolog.color_interp_vgpr_index[i] = 0;
7164 shader->config.spi_ps_input_ena |=
7165 S_0286CC_PERSP_SAMPLE_ENA(1);
7166 break;
7167 case TGSI_INTERPOLATE_LOC_CENTER:
7168 key->ps_prolog.color_interp_vgpr_index[i] = 2;
7169 shader->config.spi_ps_input_ena |=
7170 S_0286CC_PERSP_CENTER_ENA(1);
7171 break;
7172 case TGSI_INTERPOLATE_LOC_CENTROID:
7173 key->ps_prolog.color_interp_vgpr_index[i] = 4;
7174 shader->config.spi_ps_input_ena |=
7175 S_0286CC_PERSP_CENTROID_ENA(1);
7176 break;
7177 default:
7178 assert(0);
7179 }
7180 break;
7181 case TGSI_INTERPOLATE_LINEAR:
7182 /* Force the interpolation location for colors here. */
7183 if (shader->key.part.ps.prolog.force_linear_sample_interp)
7184 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7185 if (shader->key.part.ps.prolog.force_linear_center_interp)
7186 location = TGSI_INTERPOLATE_LOC_CENTER;
7187
7188 /* The VGPR assignment for non-monolithic shaders
7189 * works because InitialPSInputAddr is set on the
7190 * main shader and PERSP_PULL_MODEL is never used.
7191 */
7192 switch (location) {
7193 case TGSI_INTERPOLATE_LOC_SAMPLE:
7194 key->ps_prolog.color_interp_vgpr_index[i] =
7195 separate_prolog ? 6 : 9;
7196 shader->config.spi_ps_input_ena |=
7197 S_0286CC_LINEAR_SAMPLE_ENA(1);
7198 break;
7199 case TGSI_INTERPOLATE_LOC_CENTER:
7200 key->ps_prolog.color_interp_vgpr_index[i] =
7201 separate_prolog ? 8 : 11;
7202 shader->config.spi_ps_input_ena |=
7203 S_0286CC_LINEAR_CENTER_ENA(1);
7204 break;
7205 case TGSI_INTERPOLATE_LOC_CENTROID:
7206 key->ps_prolog.color_interp_vgpr_index[i] =
7207 separate_prolog ? 10 : 13;
7208 shader->config.spi_ps_input_ena |=
7209 S_0286CC_LINEAR_CENTROID_ENA(1);
7210 break;
7211 default:
7212 assert(0);
7213 }
7214 break;
7215 default:
7216 assert(0);
7217 }
7218 }
7219 }
7220 }
7221
7222 /**
7223 * Check whether a PS prolog is required based on the key.
7224 */
7225 static bool si_need_ps_prolog(const union si_shader_part_key *key)
7226 {
7227 return key->ps_prolog.colors_read ||
7228 key->ps_prolog.states.force_persp_sample_interp ||
7229 key->ps_prolog.states.force_linear_sample_interp ||
7230 key->ps_prolog.states.force_persp_center_interp ||
7231 key->ps_prolog.states.force_linear_center_interp ||
7232 key->ps_prolog.states.bc_optimize_for_persp ||
7233 key->ps_prolog.states.bc_optimize_for_linear ||
7234 key->ps_prolog.states.poly_stipple;
7235 }
7236
7237 /**
7238 * Compute the PS epilog key, which contains all the information needed to
7239 * build the PS epilog function.
7240 */
7241 static void si_get_ps_epilog_key(struct si_shader *shader,
7242 union si_shader_part_key *key)
7243 {
7244 struct tgsi_shader_info *info = &shader->selector->info;
7245 memset(key, 0, sizeof(*key));
7246 key->ps_epilog.colors_written = info->colors_written;
7247 key->ps_epilog.writes_z = info->writes_z;
7248 key->ps_epilog.writes_stencil = info->writes_stencil;
7249 key->ps_epilog.writes_samplemask = info->writes_samplemask;
7250 key->ps_epilog.states = shader->key.part.ps.epilog;
7251 }
7252
7253 /**
7254 * Build the GS prolog function. Rotate the input vertices for triangle strips
7255 * with adjacency.
7256 */
7257 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
7258 union si_shader_part_key *key)
7259 {
7260 const unsigned num_sgprs = SI_GS_NUM_USER_SGPR + 2;
7261 const unsigned num_vgprs = 8;
7262 struct gallivm_state *gallivm = &ctx->gallivm;
7263 LLVMBuilderRef builder = gallivm->builder;
7264 LLVMTypeRef params[32];
7265 LLVMTypeRef returns[32];
7266 LLVMValueRef func, ret;
7267
7268 for (unsigned i = 0; i < num_sgprs; ++i) {
7269 params[i] = ctx->i32;
7270 returns[i] = ctx->i32;
7271 }
7272
7273 for (unsigned i = 0; i < num_vgprs; ++i) {
7274 params[num_sgprs + i] = ctx->i32;
7275 returns[num_sgprs + i] = ctx->f32;
7276 }
7277
7278 /* Create the function. */
7279 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
7280 params, num_sgprs + num_vgprs, num_sgprs - 1);
7281 func = ctx->main_fn;
7282
7283 /* Copy inputs to outputs. This should be no-op, as the registers match,
7284 * but it will prevent the compiler from overwriting them unintentionally.
7285 */
7286 ret = ctx->return_value;
7287 for (unsigned i = 0; i < num_sgprs; i++) {
7288 LLVMValueRef p = LLVMGetParam(func, i);
7289 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
7290 }
7291 for (unsigned i = 0; i < num_vgprs; i++) {
7292 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
7293 p = LLVMBuildBitCast(builder, p, ctx->f32, "");
7294 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
7295 }
7296
7297 if (key->gs_prolog.states.tri_strip_adj_fix) {
7298 /* Remap the input vertices for every other primitive. */
7299 const unsigned vtx_params[6] = {
7300 num_sgprs,
7301 num_sgprs + 1,
7302 num_sgprs + 3,
7303 num_sgprs + 4,
7304 num_sgprs + 5,
7305 num_sgprs + 6
7306 };
7307 LLVMValueRef prim_id, rotate;
7308
7309 prim_id = LLVMGetParam(func, num_sgprs + 2);
7310 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
7311
7312 for (unsigned i = 0; i < 6; ++i) {
7313 LLVMValueRef base, rotated, actual;
7314 base = LLVMGetParam(func, vtx_params[i]);
7315 rotated = LLVMGetParam(func, vtx_params[(i + 4) % 6]);
7316 actual = LLVMBuildSelect(builder, rotate, rotated, base, "");
7317 actual = LLVMBuildBitCast(builder, actual, ctx->f32, "");
7318 ret = LLVMBuildInsertValue(builder, ret, actual, vtx_params[i], "");
7319 }
7320 }
7321
7322 LLVMBuildRet(builder, ret);
7323 }
7324
7325 /**
7326 * Given a list of shader part functions, build a wrapper function that
7327 * runs them in sequence to form a monolithic shader.
7328 */
7329 static void si_build_wrapper_function(struct si_shader_context *ctx,
7330 LLVMValueRef *parts,
7331 unsigned num_parts,
7332 unsigned main_part)
7333 {
7334 struct gallivm_state *gallivm = &ctx->gallivm;
7335 LLVMBuilderRef builder = ctx->gallivm.builder;
7336 /* PS epilog has one arg per color component */
7337 LLVMTypeRef param_types[48];
7338 LLVMValueRef out[48];
7339 LLVMTypeRef function_type;
7340 unsigned num_params;
7341 unsigned num_out;
7342 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
7343 unsigned num_sgprs, num_vgprs;
7344 unsigned last_sgpr_param;
7345 unsigned gprs;
7346
7347 for (unsigned i = 0; i < num_parts; ++i) {
7348 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
7349 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
7350 }
7351
7352 /* The parameters of the wrapper function correspond to those of the
7353 * first part in terms of SGPRs and VGPRs, but we use the types of the
7354 * main part to get the right types. This is relevant for the
7355 * dereferenceable attribute on descriptor table pointers.
7356 */
7357 num_sgprs = 0;
7358 num_vgprs = 0;
7359
7360 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
7361 num_params = LLVMCountParamTypes(function_type);
7362
7363 for (unsigned i = 0; i < num_params; ++i) {
7364 LLVMValueRef param = LLVMGetParam(parts[0], i);
7365
7366 if (ac_is_sgpr_param(param)) {
7367 assert(num_vgprs == 0);
7368 num_sgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
7369 } else {
7370 num_vgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
7371 }
7372 }
7373 assert(num_vgprs + num_sgprs <= ARRAY_SIZE(param_types));
7374
7375 num_params = 0;
7376 last_sgpr_param = 0;
7377 gprs = 0;
7378 while (gprs < num_sgprs + num_vgprs) {
7379 LLVMValueRef param = LLVMGetParam(parts[main_part], num_params);
7380 unsigned size;
7381
7382 param_types[num_params] = LLVMTypeOf(param);
7383 if (gprs < num_sgprs)
7384 last_sgpr_param = num_params;
7385 size = llvm_get_type_size(param_types[num_params]) / 4;
7386 num_params++;
7387
7388 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
7389 assert(gprs + size <= num_sgprs + num_vgprs &&
7390 (gprs >= num_sgprs || gprs + size <= num_sgprs));
7391
7392 gprs += size;
7393 }
7394
7395 si_create_function(ctx, "wrapper", NULL, 0, param_types, num_params, last_sgpr_param);
7396
7397 /* Record the arguments of the function as if they were an output of
7398 * a previous part.
7399 */
7400 num_out = 0;
7401 num_out_sgpr = 0;
7402
7403 for (unsigned i = 0; i < num_params; ++i) {
7404 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
7405 LLVMTypeRef param_type = LLVMTypeOf(param);
7406 LLVMTypeRef out_type = i <= last_sgpr_param ? ctx->i32 : ctx->f32;
7407 unsigned size = llvm_get_type_size(param_type) / 4;
7408
7409 if (size == 1) {
7410 if (param_type != out_type)
7411 param = LLVMBuildBitCast(builder, param, out_type, "");
7412 out[num_out++] = param;
7413 } else {
7414 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
7415
7416 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7417 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
7418 param_type = ctx->i64;
7419 }
7420
7421 if (param_type != vector_type)
7422 param = LLVMBuildBitCast(builder, param, vector_type, "");
7423
7424 for (unsigned j = 0; j < size; ++j)
7425 out[num_out++] = LLVMBuildExtractElement(
7426 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
7427 }
7428
7429 if (i <= last_sgpr_param)
7430 num_out_sgpr = num_out;
7431 }
7432
7433 /* Now chain the parts. */
7434 for (unsigned part = 0; part < num_parts; ++part) {
7435 LLVMValueRef in[48];
7436 LLVMValueRef ret;
7437 LLVMTypeRef ret_type;
7438 unsigned out_idx = 0;
7439
7440 num_params = LLVMCountParams(parts[part]);
7441 assert(num_params <= ARRAY_SIZE(param_types));
7442
7443 /* Derive arguments for the next part from outputs of the
7444 * previous one.
7445 */
7446 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
7447 LLVMValueRef param;
7448 LLVMTypeRef param_type;
7449 bool is_sgpr;
7450 unsigned param_size;
7451 LLVMValueRef arg = NULL;
7452
7453 param = LLVMGetParam(parts[part], param_idx);
7454 param_type = LLVMTypeOf(param);
7455 param_size = llvm_get_type_size(param_type) / 4;
7456 is_sgpr = ac_is_sgpr_param(param);
7457
7458 if (is_sgpr) {
7459 #if HAVE_LLVM < 0x0400
7460 LLVMRemoveAttribute(param, LLVMByValAttribute);
7461 #else
7462 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
7463 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
7464 #endif
7465 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
7466 }
7467
7468 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
7469 assert(is_sgpr || out_idx >= num_out_sgpr);
7470
7471 if (param_size == 1)
7472 arg = out[out_idx];
7473 else
7474 arg = lp_build_gather_values(gallivm, &out[out_idx], param_size);
7475
7476 if (LLVMTypeOf(arg) != param_type) {
7477 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7478 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
7479 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
7480 } else {
7481 arg = LLVMBuildBitCast(builder, arg, param_type, "");
7482 }
7483 }
7484
7485 in[param_idx] = arg;
7486 out_idx += param_size;
7487 }
7488
7489 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
7490 ret_type = LLVMTypeOf(ret);
7491
7492 /* Extract the returned GPRs. */
7493 num_out = 0;
7494 num_out_sgpr = 0;
7495
7496 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
7497 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
7498
7499 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
7500
7501 for (unsigned i = 0; i < ret_size; ++i) {
7502 LLVMValueRef val =
7503 LLVMBuildExtractValue(builder, ret, i, "");
7504
7505 out[num_out++] = val;
7506
7507 if (LLVMTypeOf(val) == ctx->i32) {
7508 assert(num_out_sgpr + 1 == num_out);
7509 num_out_sgpr = num_out;
7510 }
7511 }
7512 }
7513 }
7514
7515 LLVMBuildRetVoid(builder);
7516 }
7517
7518 int si_compile_tgsi_shader(struct si_screen *sscreen,
7519 LLVMTargetMachineRef tm,
7520 struct si_shader *shader,
7521 bool is_monolithic,
7522 struct pipe_debug_callback *debug)
7523 {
7524 struct si_shader_selector *sel = shader->selector;
7525 struct si_shader_context ctx;
7526 int r = -1;
7527
7528 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
7529 * conversion fails. */
7530 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
7531 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
7532 tgsi_dump(sel->tokens, 0);
7533 si_dump_streamout(&sel->so);
7534 }
7535
7536 si_init_shader_ctx(&ctx, sscreen, shader, tm);
7537 ctx.separate_prolog = !is_monolithic;
7538
7539 memset(shader->info.vs_output_param_offset, EXP_PARAM_UNDEFINED,
7540 sizeof(shader->info.vs_output_param_offset));
7541
7542 shader->info.uses_instanceid = sel->info.uses_instanceid;
7543
7544 ctx.load_system_value = declare_system_value;
7545
7546 if (!si_compile_tgsi_main(&ctx, shader)) {
7547 si_llvm_dispose(&ctx);
7548 return -1;
7549 }
7550
7551 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
7552 LLVMValueRef parts[3];
7553 bool need_prolog;
7554 bool need_epilog;
7555
7556 need_prolog = sel->vs_needs_prolog;
7557 need_epilog = !shader->key.as_es && !shader->key.as_ls;
7558
7559 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7560
7561 if (need_prolog) {
7562 union si_shader_part_key prolog_key;
7563 si_get_vs_prolog_key(shader, &prolog_key);
7564 si_build_vs_prolog_function(&ctx, &prolog_key);
7565 parts[0] = ctx.main_fn;
7566 }
7567
7568 if (need_epilog) {
7569 union si_shader_part_key epilog_key;
7570 si_get_vs_epilog_key(shader, &shader->key.part.vs.epilog, &epilog_key);
7571 si_build_vs_epilog_function(&ctx, &epilog_key);
7572 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7573 }
7574
7575 si_build_wrapper_function(&ctx, parts, 1 + need_prolog + need_epilog,
7576 need_prolog ? 1 : 0);
7577 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
7578 LLVMValueRef parts[2];
7579 union si_shader_part_key epilog_key;
7580
7581 parts[0] = ctx.main_fn;
7582
7583 memset(&epilog_key, 0, sizeof(epilog_key));
7584 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7585 si_build_tcs_epilog_function(&ctx, &epilog_key);
7586 parts[1] = ctx.main_fn;
7587
7588 si_build_wrapper_function(&ctx, parts, 2, 0);
7589 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_EVAL &&
7590 !shader->key.as_es) {
7591 LLVMValueRef parts[2];
7592 union si_shader_part_key epilog_key;
7593
7594 parts[0] = ctx.main_fn;
7595
7596 si_get_vs_epilog_key(shader, &shader->key.part.tes.epilog, &epilog_key);
7597 si_build_vs_epilog_function(&ctx, &epilog_key);
7598 parts[1] = ctx.main_fn;
7599
7600 si_build_wrapper_function(&ctx, parts, 2, 0);
7601 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
7602 LLVMValueRef parts[2];
7603 union si_shader_part_key prolog_key;
7604
7605 parts[1] = ctx.main_fn;
7606
7607 memset(&prolog_key, 0, sizeof(prolog_key));
7608 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7609 si_build_gs_prolog_function(&ctx, &prolog_key);
7610 parts[0] = ctx.main_fn;
7611
7612 si_build_wrapper_function(&ctx, parts, 2, 1);
7613 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
7614 LLVMValueRef parts[3];
7615 union si_shader_part_key prolog_key;
7616 union si_shader_part_key epilog_key;
7617 bool need_prolog;
7618
7619 si_get_ps_prolog_key(shader, &prolog_key, false);
7620 need_prolog = si_need_ps_prolog(&prolog_key);
7621
7622 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7623
7624 if (need_prolog) {
7625 si_build_ps_prolog_function(&ctx, &prolog_key);
7626 parts[0] = ctx.main_fn;
7627 }
7628
7629 si_get_ps_epilog_key(shader, &epilog_key);
7630 si_build_ps_epilog_function(&ctx, &epilog_key);
7631 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7632
7633 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2, need_prolog ? 1 : 0);
7634 }
7635
7636 /* Dump LLVM IR before any optimization passes */
7637 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
7638 r600_can_dump_shader(&sscreen->b, ctx.type))
7639 LLVMDumpModule(ctx.gallivm.module);
7640
7641 si_llvm_finalize_module(&ctx,
7642 r600_extra_shader_checks(&sscreen->b, ctx.type));
7643
7644 /* Post-optimization transformations and analysis. */
7645 si_eliminate_const_vs_outputs(&ctx);
7646
7647 if ((debug && debug->debug_message) ||
7648 r600_can_dump_shader(&sscreen->b, ctx.type))
7649 si_count_scratch_private_memory(&ctx);
7650
7651 /* Compile to bytecode. */
7652 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
7653 ctx.gallivm.module, debug, ctx.type, "TGSI shader");
7654 si_llvm_dispose(&ctx);
7655 if (r) {
7656 fprintf(stderr, "LLVM failed to compile shader\n");
7657 return r;
7658 }
7659
7660 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
7661 * LLVM 3.9svn has this bug.
7662 */
7663 if (sel->type == PIPE_SHADER_COMPUTE) {
7664 unsigned wave_size = 64;
7665 unsigned max_vgprs = 256;
7666 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
7667 unsigned max_sgprs_per_wave = 128;
7668 unsigned max_block_threads = si_get_max_workgroup_size(shader);
7669 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
7670 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
7671
7672 max_vgprs = max_vgprs / min_waves_per_simd;
7673 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
7674
7675 if (shader->config.num_sgprs > max_sgprs ||
7676 shader->config.num_vgprs > max_vgprs) {
7677 fprintf(stderr, "LLVM failed to compile a shader correctly: "
7678 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7679 shader->config.num_sgprs, shader->config.num_vgprs,
7680 max_sgprs, max_vgprs);
7681
7682 /* Just terminate the process, because dependent
7683 * shaders can hang due to bad input data, but use
7684 * the env var to allow shader-db to work.
7685 */
7686 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7687 abort();
7688 }
7689 }
7690
7691 /* Add the scratch offset to input SGPRs. */
7692 if (shader->config.scratch_bytes_per_wave)
7693 shader->info.num_input_sgprs += 1; /* scratch byte offset */
7694
7695 /* Calculate the number of fragment input VGPRs. */
7696 if (ctx.type == PIPE_SHADER_FRAGMENT) {
7697 shader->info.num_input_vgprs = 0;
7698 shader->info.face_vgpr_index = -1;
7699
7700 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7701 shader->info.num_input_vgprs += 2;
7702 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
7703 shader->info.num_input_vgprs += 2;
7704 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
7705 shader->info.num_input_vgprs += 2;
7706 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
7707 shader->info.num_input_vgprs += 3;
7708 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7709 shader->info.num_input_vgprs += 2;
7710 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7711 shader->info.num_input_vgprs += 2;
7712 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7713 shader->info.num_input_vgprs += 2;
7714 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7715 shader->info.num_input_vgprs += 1;
7716 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7717 shader->info.num_input_vgprs += 1;
7718 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7719 shader->info.num_input_vgprs += 1;
7720 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7721 shader->info.num_input_vgprs += 1;
7722 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7723 shader->info.num_input_vgprs += 1;
7724 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7725 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7726 shader->info.num_input_vgprs += 1;
7727 }
7728 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
7729 shader->info.num_input_vgprs += 1;
7730 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7731 shader->info.num_input_vgprs += 1;
7732 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7733 shader->info.num_input_vgprs += 1;
7734 }
7735
7736 return 0;
7737 }
7738
7739 /**
7740 * Create, compile and return a shader part (prolog or epilog).
7741 *
7742 * \param sscreen screen
7743 * \param list list of shader parts of the same category
7744 * \param type shader type
7745 * \param key shader part key
7746 * \param prolog whether the part being requested is a prolog
7747 * \param tm LLVM target machine
7748 * \param debug debug callback
7749 * \param build the callback responsible for building the main function
7750 * \return non-NULL on success
7751 */
7752 static struct si_shader_part *
7753 si_get_shader_part(struct si_screen *sscreen,
7754 struct si_shader_part **list,
7755 enum pipe_shader_type type,
7756 bool prolog,
7757 union si_shader_part_key *key,
7758 LLVMTargetMachineRef tm,
7759 struct pipe_debug_callback *debug,
7760 void (*build)(struct si_shader_context *,
7761 union si_shader_part_key *),
7762 const char *name)
7763 {
7764 struct si_shader_part *result;
7765
7766 mtx_lock(&sscreen->shader_parts_mutex);
7767
7768 /* Find existing. */
7769 for (result = *list; result; result = result->next) {
7770 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7771 mtx_unlock(&sscreen->shader_parts_mutex);
7772 return result;
7773 }
7774 }
7775
7776 /* Compile a new one. */
7777 result = CALLOC_STRUCT(si_shader_part);
7778 result->key = *key;
7779
7780 struct si_shader shader = {};
7781 struct si_shader_context ctx;
7782 struct gallivm_state *gallivm = &ctx.gallivm;
7783
7784 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7785 ctx.type = type;
7786
7787 switch (type) {
7788 case PIPE_SHADER_VERTEX:
7789 break;
7790 case PIPE_SHADER_TESS_CTRL:
7791 assert(!prolog);
7792 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7793 break;
7794 case PIPE_SHADER_GEOMETRY:
7795 assert(prolog);
7796 break;
7797 case PIPE_SHADER_FRAGMENT:
7798 if (prolog)
7799 shader.key.part.ps.prolog = key->ps_prolog.states;
7800 else
7801 shader.key.part.ps.epilog = key->ps_epilog.states;
7802 break;
7803 default:
7804 unreachable("bad shader part");
7805 }
7806
7807 build(&ctx, key);
7808
7809 /* Compile. */
7810 si_llvm_finalize_module(&ctx,
7811 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT));
7812
7813 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7814 gallivm->module, debug, ctx.type, name)) {
7815 FREE(result);
7816 result = NULL;
7817 goto out;
7818 }
7819
7820 result->next = *list;
7821 *list = result;
7822
7823 out:
7824 si_llvm_dispose(&ctx);
7825 mtx_unlock(&sscreen->shader_parts_mutex);
7826 return result;
7827 }
7828
7829 /**
7830 * Build the vertex shader prolog function.
7831 *
7832 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7833 * All inputs are returned unmodified. The vertex load indices are
7834 * stored after them, which will be used by the API VS for fetching inputs.
7835 *
7836 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7837 * input_v0,
7838 * input_v1,
7839 * input_v2,
7840 * input_v3,
7841 * (VertexID + BaseVertex),
7842 * (InstanceID + StartInstance),
7843 * (InstanceID / 2 + StartInstance)
7844 */
7845 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7846 union si_shader_part_key *key)
7847 {
7848 struct gallivm_state *gallivm = &ctx->gallivm;
7849 LLVMTypeRef *params, *returns;
7850 LLVMValueRef ret, func;
7851 int last_sgpr, num_params, num_returns, i;
7852
7853 ctx->param_vertex_id = key->vs_prolog.num_input_sgprs;
7854 ctx->param_instance_id = key->vs_prolog.num_input_sgprs + 3;
7855
7856 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7857 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
7858 sizeof(LLVMTypeRef));
7859 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
7860 key->vs_prolog.last_input + 1) *
7861 sizeof(LLVMTypeRef));
7862 num_params = 0;
7863 num_returns = 0;
7864
7865 /* Declare input and output SGPRs. */
7866 num_params = 0;
7867 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7868 params[num_params++] = ctx->i32;
7869 returns[num_returns++] = ctx->i32;
7870 }
7871 last_sgpr = num_params - 1;
7872
7873 /* 4 preloaded VGPRs (outputs must be floats) */
7874 for (i = 0; i < 4; i++) {
7875 params[num_params++] = ctx->i32;
7876 returns[num_returns++] = ctx->f32;
7877 }
7878
7879 /* Vertex load indices. */
7880 for (i = 0; i <= key->vs_prolog.last_input; i++)
7881 returns[num_returns++] = ctx->f32;
7882
7883 /* Create the function. */
7884 si_create_function(ctx, "vs_prolog", returns, num_returns, params,
7885 num_params, last_sgpr);
7886 func = ctx->main_fn;
7887
7888 /* Copy inputs to outputs. This should be no-op, as the registers match,
7889 * but it will prevent the compiler from overwriting them unintentionally.
7890 */
7891 ret = ctx->return_value;
7892 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7893 LLVMValueRef p = LLVMGetParam(func, i);
7894 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7895 }
7896 for (i = num_params - 4; i < num_params; i++) {
7897 LLVMValueRef p = LLVMGetParam(func, i);
7898 p = LLVMBuildBitCast(gallivm->builder, p, ctx->f32, "");
7899 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7900 }
7901
7902 /* Compute vertex load indices from instance divisors. */
7903 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7904 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
7905 LLVMValueRef index;
7906
7907 if (divisor) {
7908 /* InstanceID / Divisor + StartInstance */
7909 index = get_instance_index_for_fetch(ctx,
7910 SI_SGPR_START_INSTANCE,
7911 divisor);
7912 } else {
7913 /* VertexID + BaseVertex */
7914 index = LLVMBuildAdd(gallivm->builder,
7915 LLVMGetParam(func, ctx->param_vertex_id),
7916 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
7917 }
7918
7919 index = LLVMBuildBitCast(gallivm->builder, index, ctx->f32, "");
7920 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
7921 num_params++, "");
7922 }
7923
7924 si_llvm_build_ret(ctx, ret);
7925 }
7926
7927 /**
7928 * Build the vertex shader epilog function. This is also used by the tessellation
7929 * evaluation shader compiled as VS.
7930 *
7931 * The input is PrimitiveID.
7932 *
7933 * If PrimitiveID is required by the pixel shader, export it.
7934 * Otherwise, do nothing.
7935 */
7936 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
7937 union si_shader_part_key *key)
7938 {
7939 struct gallivm_state *gallivm = &ctx->gallivm;
7940 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7941 LLVMTypeRef params[5];
7942 int num_params, i;
7943
7944 /* Declare input VGPRs. */
7945 num_params = key->vs_epilog.states.export_prim_id ?
7946 (VS_EPILOG_PRIMID_LOC + 1) : 0;
7947 assert(num_params <= ARRAY_SIZE(params));
7948
7949 for (i = 0; i < num_params; i++)
7950 params[i] = ctx->f32;
7951
7952 /* Create the function. */
7953 si_create_function(ctx, "vs_epilog", NULL, 0, params, num_params, -1);
7954
7955 /* Emit exports. */
7956 if (key->vs_epilog.states.export_prim_id) {
7957 struct lp_build_context *base = &bld_base->base;
7958 struct ac_export_args args;
7959
7960 args.enabled_channels = 0x1; /* enabled channels */
7961 args.valid_mask = 0; /* whether the EXEC mask is valid */
7962 args.done = 0; /* DONE bit */
7963 args.target = V_008DFC_SQ_EXP_PARAM +
7964 key->vs_epilog.prim_id_param_offset;
7965 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
7966 args.out[0] = LLVMGetParam(ctx->main_fn,
7967 VS_EPILOG_PRIMID_LOC); /* X */
7968 args.out[1] = base->undef; /* Y */
7969 args.out[2] = base->undef; /* Z */
7970 args.out[3] = base->undef; /* W */
7971
7972 ac_build_export(&ctx->ac, &args);
7973 }
7974
7975 LLVMBuildRetVoid(gallivm->builder);
7976 }
7977
7978 /**
7979 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7980 */
7981 static bool si_get_vs_epilog(struct si_screen *sscreen,
7982 LLVMTargetMachineRef tm,
7983 struct si_shader *shader,
7984 struct pipe_debug_callback *debug,
7985 struct si_vs_epilog_bits *states)
7986 {
7987 union si_shader_part_key epilog_key;
7988
7989 si_get_vs_epilog_key(shader, states, &epilog_key);
7990
7991 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
7992 PIPE_SHADER_VERTEX, true,
7993 &epilog_key, tm, debug,
7994 si_build_vs_epilog_function,
7995 "Vertex Shader Epilog");
7996 return shader->epilog != NULL;
7997 }
7998
7999 /**
8000 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
8001 */
8002 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
8003 LLVMTargetMachineRef tm,
8004 struct si_shader *shader,
8005 struct pipe_debug_callback *debug)
8006 {
8007 if (shader->selector->vs_needs_prolog) {
8008 union si_shader_part_key prolog_key;
8009
8010 /* Get the prolog. */
8011 si_get_vs_prolog_key(shader, &prolog_key);
8012
8013 shader->prolog =
8014 si_get_shader_part(sscreen, &sscreen->vs_prologs,
8015 PIPE_SHADER_VERTEX, true,
8016 &prolog_key, tm, debug,
8017 si_build_vs_prolog_function,
8018 "Vertex Shader Prolog");
8019 if (!shader->prolog)
8020 return false;
8021 }
8022
8023 /* Get the epilog. */
8024 if (!shader->key.as_es && !shader->key.as_ls &&
8025 !si_get_vs_epilog(sscreen, tm, shader, debug,
8026 &shader->key.part.vs.epilog))
8027 return false;
8028
8029 return true;
8030 }
8031
8032 /**
8033 * Select and compile (or reuse) TES parts (epilog).
8034 */
8035 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
8036 LLVMTargetMachineRef tm,
8037 struct si_shader *shader,
8038 struct pipe_debug_callback *debug)
8039 {
8040 if (shader->key.as_es)
8041 return true;
8042
8043 /* TES compiled as VS. */
8044 return si_get_vs_epilog(sscreen, tm, shader, debug,
8045 &shader->key.part.tes.epilog);
8046 }
8047
8048 /**
8049 * Compile the TCS epilog function. This writes tesselation factors to memory
8050 * based on the output primitive type of the tesselator (determined by TES).
8051 */
8052 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
8053 union si_shader_part_key *key)
8054 {
8055 struct gallivm_state *gallivm = &ctx->gallivm;
8056 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
8057 LLVMTypeRef params[16];
8058 LLVMValueRef func;
8059 int last_sgpr, num_params;
8060
8061 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
8062 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
8063 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
8064 params[SI_PARAM_SAMPLERS] = ctx->i64;
8065 params[SI_PARAM_IMAGES] = ctx->i64;
8066 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
8067 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
8068 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
8069 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
8070 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
8071 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
8072 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
8073 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
8074 num_params = last_sgpr + 1;
8075
8076 params[num_params++] = ctx->i32; /* patch index within the wave (REL_PATCH_ID) */
8077 params[num_params++] = ctx->i32; /* invocation ID within the patch */
8078 params[num_params++] = ctx->i32; /* LDS offset where tess factors should be loaded from */
8079
8080 /* Create the function. */
8081 si_create_function(ctx, "tcs_epilog", NULL, 0, params, num_params, last_sgpr);
8082 declare_tess_lds(ctx);
8083 func = ctx->main_fn;
8084
8085 si_write_tess_factors(bld_base,
8086 LLVMGetParam(func, last_sgpr + 1),
8087 LLVMGetParam(func, last_sgpr + 2),
8088 LLVMGetParam(func, last_sgpr + 3));
8089
8090 LLVMBuildRetVoid(gallivm->builder);
8091 }
8092
8093 /**
8094 * Select and compile (or reuse) TCS parts (epilog).
8095 */
8096 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
8097 LLVMTargetMachineRef tm,
8098 struct si_shader *shader,
8099 struct pipe_debug_callback *debug)
8100 {
8101 union si_shader_part_key epilog_key;
8102
8103 /* Get the epilog. */
8104 memset(&epilog_key, 0, sizeof(epilog_key));
8105 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
8106
8107 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
8108 PIPE_SHADER_TESS_CTRL, false,
8109 &epilog_key, tm, debug,
8110 si_build_tcs_epilog_function,
8111 "Tessellation Control Shader Epilog");
8112 return shader->epilog != NULL;
8113 }
8114
8115 /**
8116 * Select and compile (or reuse) GS parts (prolog).
8117 */
8118 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
8119 LLVMTargetMachineRef tm,
8120 struct si_shader *shader,
8121 struct pipe_debug_callback *debug)
8122 {
8123 union si_shader_part_key prolog_key;
8124
8125 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
8126 return true;
8127
8128 memset(&prolog_key, 0, sizeof(prolog_key));
8129 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
8130
8131 shader->prolog = si_get_shader_part(sscreen, &sscreen->gs_prologs,
8132 PIPE_SHADER_GEOMETRY, true,
8133 &prolog_key, tm, debug,
8134 si_build_gs_prolog_function,
8135 "Geometry Shader Prolog");
8136 return shader->prolog != NULL;
8137 }
8138
8139 /**
8140 * Build the pixel shader prolog function. This handles:
8141 * - two-side color selection and interpolation
8142 * - overriding interpolation parameters for the API PS
8143 * - polygon stippling
8144 *
8145 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
8146 * overriden by other states. (e.g. per-sample interpolation)
8147 * Interpolated colors are stored after the preloaded VGPRs.
8148 */
8149 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
8150 union si_shader_part_key *key)
8151 {
8152 struct gallivm_state *gallivm = &ctx->gallivm;
8153 LLVMTypeRef *params;
8154 LLVMValueRef ret, func;
8155 int last_sgpr, num_params, num_returns, i, num_color_channels;
8156
8157 assert(si_need_ps_prolog(key));
8158
8159 /* Number of inputs + 8 color elements. */
8160 params = alloca((key->ps_prolog.num_input_sgprs +
8161 key->ps_prolog.num_input_vgprs + 8) *
8162 sizeof(LLVMTypeRef));
8163
8164 /* Declare inputs. */
8165 num_params = 0;
8166 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
8167 params[num_params++] = ctx->i32;
8168 last_sgpr = num_params - 1;
8169
8170 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
8171 params[num_params++] = ctx->f32;
8172
8173 /* Declare outputs (same as inputs + add colors if needed) */
8174 num_returns = num_params;
8175 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
8176 for (i = 0; i < num_color_channels; i++)
8177 params[num_returns++] = ctx->f32;
8178
8179 /* Create the function. */
8180 si_create_function(ctx, "ps_prolog", params, num_returns, params,
8181 num_params, last_sgpr);
8182 func = ctx->main_fn;
8183
8184 /* Copy inputs to outputs. This should be no-op, as the registers match,
8185 * but it will prevent the compiler from overwriting them unintentionally.
8186 */
8187 ret = ctx->return_value;
8188 for (i = 0; i < num_params; i++) {
8189 LLVMValueRef p = LLVMGetParam(func, i);
8190 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
8191 }
8192
8193 /* Polygon stippling. */
8194 if (key->ps_prolog.states.poly_stipple) {
8195 /* POS_FIXED_PT is always last. */
8196 unsigned pos = key->ps_prolog.num_input_sgprs +
8197 key->ps_prolog.num_input_vgprs - 1;
8198 LLVMValueRef ptr[2], list;
8199
8200 /* Get the pointer to rw buffers. */
8201 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
8202 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
8203 list = lp_build_gather_values(gallivm, ptr, 2);
8204 list = LLVMBuildBitCast(gallivm->builder, list, ctx->i64, "");
8205 list = LLVMBuildIntToPtr(gallivm->builder, list,
8206 const_array(ctx->v16i8, SI_NUM_RW_BUFFERS), "");
8207
8208 si_llvm_emit_polygon_stipple(ctx, list, pos);
8209 }
8210
8211 if (key->ps_prolog.states.bc_optimize_for_persp ||
8212 key->ps_prolog.states.bc_optimize_for_linear) {
8213 unsigned i, base = key->ps_prolog.num_input_sgprs;
8214 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
8215
8216 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
8217 * The hw doesn't compute CENTROID if the whole wave only
8218 * contains fully-covered quads.
8219 *
8220 * PRIM_MASK is after user SGPRs.
8221 */
8222 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
8223 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
8224 LLVMConstInt(ctx->i32, 31, 0), "");
8225 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
8226 ctx->i1, "");
8227
8228 if (key->ps_prolog.states.bc_optimize_for_persp) {
8229 /* Read PERSP_CENTER. */
8230 for (i = 0; i < 2; i++)
8231 center[i] = LLVMGetParam(func, base + 2 + i);
8232 /* Read PERSP_CENTROID. */
8233 for (i = 0; i < 2; i++)
8234 centroid[i] = LLVMGetParam(func, base + 4 + i);
8235 /* Select PERSP_CENTROID. */
8236 for (i = 0; i < 2; i++) {
8237 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
8238 center[i], centroid[i], "");
8239 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8240 tmp, base + 4 + i, "");
8241 }
8242 }
8243 if (key->ps_prolog.states.bc_optimize_for_linear) {
8244 /* Read LINEAR_CENTER. */
8245 for (i = 0; i < 2; i++)
8246 center[i] = LLVMGetParam(func, base + 8 + i);
8247 /* Read LINEAR_CENTROID. */
8248 for (i = 0; i < 2; i++)
8249 centroid[i] = LLVMGetParam(func, base + 10 + i);
8250 /* Select LINEAR_CENTROID. */
8251 for (i = 0; i < 2; i++) {
8252 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
8253 center[i], centroid[i], "");
8254 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8255 tmp, base + 10 + i, "");
8256 }
8257 }
8258 }
8259
8260 /* Force per-sample interpolation. */
8261 if (key->ps_prolog.states.force_persp_sample_interp) {
8262 unsigned i, base = key->ps_prolog.num_input_sgprs;
8263 LLVMValueRef persp_sample[2];
8264
8265 /* Read PERSP_SAMPLE. */
8266 for (i = 0; i < 2; i++)
8267 persp_sample[i] = LLVMGetParam(func, base + i);
8268 /* Overwrite PERSP_CENTER. */
8269 for (i = 0; i < 2; i++)
8270 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8271 persp_sample[i], base + 2 + i, "");
8272 /* Overwrite PERSP_CENTROID. */
8273 for (i = 0; i < 2; i++)
8274 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8275 persp_sample[i], base + 4 + i, "");
8276 }
8277 if (key->ps_prolog.states.force_linear_sample_interp) {
8278 unsigned i, base = key->ps_prolog.num_input_sgprs;
8279 LLVMValueRef linear_sample[2];
8280
8281 /* Read LINEAR_SAMPLE. */
8282 for (i = 0; i < 2; i++)
8283 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
8284 /* Overwrite LINEAR_CENTER. */
8285 for (i = 0; i < 2; i++)
8286 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8287 linear_sample[i], base + 8 + i, "");
8288 /* Overwrite LINEAR_CENTROID. */
8289 for (i = 0; i < 2; i++)
8290 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8291 linear_sample[i], base + 10 + i, "");
8292 }
8293
8294 /* Force center interpolation. */
8295 if (key->ps_prolog.states.force_persp_center_interp) {
8296 unsigned i, base = key->ps_prolog.num_input_sgprs;
8297 LLVMValueRef persp_center[2];
8298
8299 /* Read PERSP_CENTER. */
8300 for (i = 0; i < 2; i++)
8301 persp_center[i] = LLVMGetParam(func, base + 2 + i);
8302 /* Overwrite PERSP_SAMPLE. */
8303 for (i = 0; i < 2; i++)
8304 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8305 persp_center[i], base + i, "");
8306 /* Overwrite PERSP_CENTROID. */
8307 for (i = 0; i < 2; i++)
8308 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8309 persp_center[i], base + 4 + i, "");
8310 }
8311 if (key->ps_prolog.states.force_linear_center_interp) {
8312 unsigned i, base = key->ps_prolog.num_input_sgprs;
8313 LLVMValueRef linear_center[2];
8314
8315 /* Read LINEAR_CENTER. */
8316 for (i = 0; i < 2; i++)
8317 linear_center[i] = LLVMGetParam(func, base + 8 + i);
8318 /* Overwrite LINEAR_SAMPLE. */
8319 for (i = 0; i < 2; i++)
8320 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8321 linear_center[i], base + 6 + i, "");
8322 /* Overwrite LINEAR_CENTROID. */
8323 for (i = 0; i < 2; i++)
8324 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8325 linear_center[i], base + 10 + i, "");
8326 }
8327
8328 /* Interpolate colors. */
8329 for (i = 0; i < 2; i++) {
8330 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
8331 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
8332 key->ps_prolog.face_vgpr_index;
8333 LLVMValueRef interp[2], color[4];
8334 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
8335
8336 if (!writemask)
8337 continue;
8338
8339 /* If the interpolation qualifier is not CONSTANT (-1). */
8340 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
8341 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
8342 key->ps_prolog.color_interp_vgpr_index[i];
8343
8344 /* Get the (i,j) updated by bc_optimize handling. */
8345 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
8346 interp_vgpr, "");
8347 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
8348 interp_vgpr + 1, "");
8349 interp_ij = lp_build_gather_values(gallivm, interp, 2);
8350 }
8351
8352 /* Use the absolute location of the input. */
8353 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
8354
8355 if (key->ps_prolog.states.color_two_side) {
8356 face = LLVMGetParam(func, face_vgpr);
8357 face = LLVMBuildBitCast(gallivm->builder, face, ctx->i32, "");
8358 }
8359
8360 interp_fs_input(ctx,
8361 key->ps_prolog.color_attr_index[i],
8362 TGSI_SEMANTIC_COLOR, i,
8363 key->ps_prolog.num_interp_inputs,
8364 key->ps_prolog.colors_read, interp_ij,
8365 prim_mask, face, color);
8366
8367 while (writemask) {
8368 unsigned chan = u_bit_scan(&writemask);
8369 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
8370 num_params++, "");
8371 }
8372 }
8373
8374 /* Tell LLVM to insert WQM instruction sequence when needed. */
8375 if (key->ps_prolog.wqm) {
8376 LLVMAddTargetDependentFunctionAttr(func,
8377 "amdgpu-ps-wqm-outputs", "");
8378 }
8379
8380 si_llvm_build_ret(ctx, ret);
8381 }
8382
8383 /**
8384 * Build the pixel shader epilog function. This handles everything that must be
8385 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
8386 */
8387 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
8388 union si_shader_part_key *key)
8389 {
8390 struct gallivm_state *gallivm = &ctx->gallivm;
8391 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
8392 LLVMTypeRef params[16+8*4+3];
8393 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
8394 int last_sgpr, num_params, i;
8395 struct si_ps_exports exp = {};
8396
8397 /* Declare input SGPRs. */
8398 params[SI_PARAM_RW_BUFFERS] = ctx->i64;
8399 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
8400 params[SI_PARAM_SAMPLERS] = ctx->i64;
8401 params[SI_PARAM_IMAGES] = ctx->i64;
8402 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
8403 params[SI_PARAM_ALPHA_REF] = ctx->f32;
8404 last_sgpr = SI_PARAM_ALPHA_REF;
8405
8406 /* Declare input VGPRs. */
8407 num_params = (last_sgpr + 1) +
8408 util_bitcount(key->ps_epilog.colors_written) * 4 +
8409 key->ps_epilog.writes_z +
8410 key->ps_epilog.writes_stencil +
8411 key->ps_epilog.writes_samplemask;
8412
8413 num_params = MAX2(num_params,
8414 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
8415
8416 assert(num_params <= ARRAY_SIZE(params));
8417
8418 for (i = last_sgpr + 1; i < num_params; i++)
8419 params[i] = ctx->f32;
8420
8421 /* Create the function. */
8422 si_create_function(ctx, "ps_epilog", NULL, 0, params, num_params, last_sgpr);
8423 /* Disable elimination of unused inputs. */
8424 si_llvm_add_attribute(ctx->main_fn,
8425 "InitialPSInputAddr", 0xffffff);
8426
8427 /* Process colors. */
8428 unsigned vgpr = last_sgpr + 1;
8429 unsigned colors_written = key->ps_epilog.colors_written;
8430 int last_color_export = -1;
8431
8432 /* Find the last color export. */
8433 if (!key->ps_epilog.writes_z &&
8434 !key->ps_epilog.writes_stencil &&
8435 !key->ps_epilog.writes_samplemask) {
8436 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
8437
8438 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
8439 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
8440 /* Just set this if any of the colorbuffers are enabled. */
8441 if (spi_format &
8442 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
8443 last_color_export = 0;
8444 } else {
8445 for (i = 0; i < 8; i++)
8446 if (colors_written & (1 << i) &&
8447 (spi_format >> (i * 4)) & 0xf)
8448 last_color_export = i;
8449 }
8450 }
8451
8452 while (colors_written) {
8453 LLVMValueRef color[4];
8454 int mrt = u_bit_scan(&colors_written);
8455
8456 for (i = 0; i < 4; i++)
8457 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
8458
8459 si_export_mrt_color(bld_base, color, mrt,
8460 num_params - 1,
8461 mrt == last_color_export, &exp);
8462 }
8463
8464 /* Process depth, stencil, samplemask. */
8465 if (key->ps_epilog.writes_z)
8466 depth = LLVMGetParam(ctx->main_fn, vgpr++);
8467 if (key->ps_epilog.writes_stencil)
8468 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
8469 if (key->ps_epilog.writes_samplemask)
8470 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
8471
8472 if (depth || stencil || samplemask)
8473 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
8474 else if (last_color_export == -1)
8475 si_export_null(bld_base);
8476
8477 if (exp.num)
8478 si_emit_ps_exports(ctx, &exp);
8479
8480 /* Compile. */
8481 LLVMBuildRetVoid(gallivm->builder);
8482 }
8483
8484 /**
8485 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
8486 */
8487 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
8488 LLVMTargetMachineRef tm,
8489 struct si_shader *shader,
8490 struct pipe_debug_callback *debug)
8491 {
8492 union si_shader_part_key prolog_key;
8493 union si_shader_part_key epilog_key;
8494
8495 /* Get the prolog. */
8496 si_get_ps_prolog_key(shader, &prolog_key, true);
8497
8498 /* The prolog is a no-op if these aren't set. */
8499 if (si_need_ps_prolog(&prolog_key)) {
8500 shader->prolog =
8501 si_get_shader_part(sscreen, &sscreen->ps_prologs,
8502 PIPE_SHADER_FRAGMENT, true,
8503 &prolog_key, tm, debug,
8504 si_build_ps_prolog_function,
8505 "Fragment Shader Prolog");
8506 if (!shader->prolog)
8507 return false;
8508 }
8509
8510 /* Get the epilog. */
8511 si_get_ps_epilog_key(shader, &epilog_key);
8512
8513 shader->epilog =
8514 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
8515 PIPE_SHADER_FRAGMENT, false,
8516 &epilog_key, tm, debug,
8517 si_build_ps_epilog_function,
8518 "Fragment Shader Epilog");
8519 if (!shader->epilog)
8520 return false;
8521
8522 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
8523 if (shader->key.part.ps.prolog.poly_stipple) {
8524 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
8525 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
8526 }
8527
8528 /* Set up the enable bits for per-sample shading if needed. */
8529 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
8530 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8531 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8532 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
8533 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8534 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
8535 }
8536 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
8537 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8538 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8539 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
8540 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8541 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
8542 }
8543 if (shader->key.part.ps.prolog.force_persp_center_interp &&
8544 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8545 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8546 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
8547 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8548 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8549 }
8550 if (shader->key.part.ps.prolog.force_linear_center_interp &&
8551 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8552 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8553 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
8554 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8555 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8556 }
8557
8558 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
8559 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
8560 !(shader->config.spi_ps_input_ena & 0xf)) {
8561 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8562 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
8563 }
8564
8565 /* At least one pair of interpolation weights must be enabled. */
8566 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
8567 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8568 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
8569 }
8570
8571 /* The sample mask input is always enabled, because the API shader always
8572 * passes it through to the epilog. Disable it here if it's unused.
8573 */
8574 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
8575 !shader->selector->info.reads_samplemask)
8576 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
8577
8578 return true;
8579 }
8580
8581 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
8582 unsigned *lds_size)
8583 {
8584 /* SPI barrier management bug:
8585 * Make sure we have at least 4k of LDS in use to avoid the bug.
8586 * It applies to workgroup sizes of more than one wavefront.
8587 */
8588 if (sscreen->b.family == CHIP_BONAIRE ||
8589 sscreen->b.family == CHIP_KABINI ||
8590 sscreen->b.family == CHIP_MULLINS)
8591 *lds_size = MAX2(*lds_size, 8);
8592 }
8593
8594 static void si_fix_resource_usage(struct si_screen *sscreen,
8595 struct si_shader *shader)
8596 {
8597 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
8598
8599 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
8600
8601 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
8602 si_get_max_workgroup_size(shader) > 64) {
8603 si_multiwave_lds_size_workaround(sscreen,
8604 &shader->config.lds_size);
8605 }
8606 }
8607
8608 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
8609 struct si_shader *shader,
8610 struct pipe_debug_callback *debug)
8611 {
8612 struct si_shader_selector *sel = shader->selector;
8613 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
8614 int r;
8615
8616 /* LS, ES, VS are compiled on demand if the main part hasn't been
8617 * compiled for that stage.
8618 *
8619 * Vertex shaders are compiled on demand when a vertex fetch
8620 * workaround must be applied.
8621 */
8622 if (shader->is_monolithic) {
8623 /* Monolithic shader (compiled as a whole, has many variants,
8624 * may take a long time to compile).
8625 */
8626 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
8627 if (r)
8628 return r;
8629 } else {
8630 /* The shader consists of 2-3 parts:
8631 *
8632 * - the middle part is the user shader, it has 1 variant only
8633 * and it was compiled during the creation of the shader
8634 * selector
8635 * - the prolog part is inserted at the beginning
8636 * - the epilog part is inserted at the end
8637 *
8638 * The prolog and epilog have many (but simple) variants.
8639 */
8640
8641 /* Copy the compiled TGSI shader data over. */
8642 shader->is_binary_shared = true;
8643 shader->binary = mainp->binary;
8644 shader->config = mainp->config;
8645 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8646 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8647 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8648 memcpy(shader->info.vs_output_param_offset,
8649 mainp->info.vs_output_param_offset,
8650 sizeof(mainp->info.vs_output_param_offset));
8651 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8652 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8653 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8654
8655 /* Select prologs and/or epilogs. */
8656 switch (sel->type) {
8657 case PIPE_SHADER_VERTEX:
8658 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
8659 return -1;
8660 break;
8661 case PIPE_SHADER_TESS_CTRL:
8662 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
8663 return -1;
8664 break;
8665 case PIPE_SHADER_TESS_EVAL:
8666 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
8667 return -1;
8668 break;
8669 case PIPE_SHADER_GEOMETRY:
8670 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
8671 return -1;
8672 break;
8673 case PIPE_SHADER_FRAGMENT:
8674 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8675 return -1;
8676
8677 /* Make sure we have at least as many VGPRs as there
8678 * are allocated inputs.
8679 */
8680 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8681 shader->info.num_input_vgprs);
8682 break;
8683 }
8684
8685 /* Update SGPR and VGPR counts. */
8686 if (shader->prolog) {
8687 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8688 shader->prolog->config.num_sgprs);
8689 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8690 shader->prolog->config.num_vgprs);
8691 }
8692 if (shader->epilog) {
8693 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8694 shader->epilog->config.num_sgprs);
8695 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8696 shader->epilog->config.num_vgprs);
8697 }
8698 }
8699
8700 si_fix_resource_usage(sscreen, shader);
8701 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8702 stderr, true);
8703
8704 /* Upload. */
8705 r = si_shader_binary_upload(sscreen, shader);
8706 if (r) {
8707 fprintf(stderr, "LLVM failed to upload shader\n");
8708 return r;
8709 }
8710
8711 return 0;
8712 }
8713
8714 void si_shader_destroy(struct si_shader *shader)
8715 {
8716 if (shader->scratch_bo)
8717 r600_resource_reference(&shader->scratch_bo, NULL);
8718
8719 r600_resource_reference(&shader->bo, NULL);
8720
8721 if (!shader->is_binary_shared)
8722 radeon_shader_binary_clean(&shader->binary);
8723
8724 free(shader->shader_log);
8725 }