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radeon/vce: disable VCE dual instance for harvest part
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_dump.h"
45
46 #include "si_pipe.h"
47 #include "si_shader.h"
48 #include "sid.h"
49
50 #include <errno.h>
51
52 static const char *scratch_rsrc_dword0_symbol =
53 "SCRATCH_RSRC_DWORD0";
54
55 static const char *scratch_rsrc_dword1_symbol =
56 "SCRATCH_RSRC_DWORD1";
57
58 struct si_shader_output_values
59 {
60 LLVMValueRef values[4];
61 unsigned name;
62 unsigned sid;
63 };
64
65 struct si_shader_context
66 {
67 struct radeon_llvm_context radeon_bld;
68 struct si_shader *shader;
69 struct si_screen *screen;
70 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
71 int param_streamout_config;
72 int param_streamout_write_index;
73 int param_streamout_offset[4];
74 int param_vertex_id;
75 int param_rel_auto_id;
76 int param_vs_prim_id;
77 int param_instance_id;
78 int param_tes_u;
79 int param_tes_v;
80 int param_tes_rel_patch_id;
81 int param_tes_patch_id;
82 int param_es2gs_offset;
83 LLVMTargetMachineRef tm;
84 LLVMValueRef const_md;
85 LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
86 LLVMValueRef lds;
87 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
88 LLVMValueRef resources[SI_NUM_SAMPLER_VIEWS];
89 LLVMValueRef samplers[SI_NUM_SAMPLER_STATES];
90 LLVMValueRef so_buffers[4];
91 LLVMValueRef esgs_ring;
92 LLVMValueRef gsvs_ring[4];
93 LLVMValueRef gs_next_vertex[4];
94 };
95
96 static struct si_shader_context * si_shader_context(
97 struct lp_build_tgsi_context * bld_base)
98 {
99 return (struct si_shader_context *)bld_base;
100 }
101
102
103 #define PERSPECTIVE_BASE 0
104 #define LINEAR_BASE 9
105
106 #define SAMPLE_OFFSET 0
107 #define CENTER_OFFSET 2
108 #define CENTROID_OFSET 4
109
110 #define USE_SGPR_MAX_SUFFIX_LEN 5
111 #define CONST_ADDR_SPACE 2
112 #define LOCAL_ADDR_SPACE 3
113 #define USER_SGPR_ADDR_SPACE 8
114
115
116 #define SENDMSG_GS 2
117 #define SENDMSG_GS_DONE 3
118
119 #define SENDMSG_GS_OP_NOP (0 << 4)
120 #define SENDMSG_GS_OP_CUT (1 << 4)
121 #define SENDMSG_GS_OP_EMIT (2 << 4)
122 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
123
124 /**
125 * Returns a unique index for a semantic name and index. The index must be
126 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
127 * calculated.
128 */
129 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
130 {
131 switch (semantic_name) {
132 case TGSI_SEMANTIC_POSITION:
133 return 0;
134 case TGSI_SEMANTIC_PSIZE:
135 return 1;
136 case TGSI_SEMANTIC_CLIPDIST:
137 assert(index <= 1);
138 return 2 + index;
139 case TGSI_SEMANTIC_GENERIC:
140 if (index <= 63-4)
141 return 4 + index;
142 else
143 /* same explanation as in the default statement,
144 * the only user hitting this is st/nine.
145 */
146 return 0;
147
148 /* patch indices are completely separate and thus start from 0 */
149 case TGSI_SEMANTIC_TESSOUTER:
150 return 0;
151 case TGSI_SEMANTIC_TESSINNER:
152 return 1;
153 case TGSI_SEMANTIC_PATCH:
154 return 2 + index;
155
156 default:
157 /* Don't fail here. The result of this function is only used
158 * for LS, TCS, TES, and GS, where legacy GL semantics can't
159 * occur, but this function is called for all vertex shaders
160 * before it's known whether LS will be compiled or not.
161 */
162 return 0;
163 }
164 }
165
166 /**
167 * Given a semantic name and index of a parameter and a mask of used parameters
168 * (inputs or outputs), return the index of the parameter in the list of all
169 * used parameters.
170 *
171 * For example, assume this list of parameters:
172 * POSITION, PSIZE, GENERIC0, GENERIC2
173 * which has the mask:
174 * 11000000000101
175 * Then:
176 * querying POSITION returns 0,
177 * querying PSIZE returns 1,
178 * querying GENERIC0 returns 2,
179 * querying GENERIC2 returns 3.
180 *
181 * Which can be used as an offset to a parameter buffer in units of vec4s.
182 */
183 static int get_param_index(unsigned semantic_name, unsigned index,
184 uint64_t mask)
185 {
186 unsigned unique_index = si_shader_io_get_unique_index(semantic_name, index);
187 int i, param_index = 0;
188
189 /* If not present... */
190 if (!((1llu << unique_index) & mask))
191 return -1;
192
193 for (i = 0; mask; i++) {
194 uint64_t bit = 1llu << i;
195
196 if (bit & mask) {
197 if (i == unique_index)
198 return param_index;
199
200 mask &= ~bit;
201 param_index++;
202 }
203 }
204
205 assert(!"unreachable");
206 return -1;
207 }
208
209 /**
210 * Get the value of a shader input parameter and extract a bitfield.
211 */
212 static LLVMValueRef unpack_param(struct si_shader_context *si_shader_ctx,
213 unsigned param, unsigned rshift,
214 unsigned bitwidth)
215 {
216 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
217 LLVMValueRef value = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
218 param);
219
220 if (rshift)
221 value = LLVMBuildLShr(gallivm->builder, value,
222 lp_build_const_int32(gallivm, rshift), "");
223
224 if (rshift + bitwidth < 32) {
225 unsigned mask = (1 << bitwidth) - 1;
226 value = LLVMBuildAnd(gallivm->builder, value,
227 lp_build_const_int32(gallivm, mask), "");
228 }
229
230 return value;
231 }
232
233 static LLVMValueRef get_rel_patch_id(struct si_shader_context *si_shader_ctx)
234 {
235 switch (si_shader_ctx->type) {
236 case TGSI_PROCESSOR_TESS_CTRL:
237 return unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 0, 8);
238
239 case TGSI_PROCESSOR_TESS_EVAL:
240 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
241 si_shader_ctx->param_tes_rel_patch_id);
242
243 default:
244 assert(0);
245 return NULL;
246 }
247 }
248
249 /* Tessellation shaders pass outputs to the next shader using LDS.
250 *
251 * LS outputs = TCS inputs
252 * TCS outputs = TES inputs
253 *
254 * The LDS layout is:
255 * - TCS inputs for patch 0
256 * - TCS inputs for patch 1
257 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
258 * - ...
259 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
260 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
261 * - TCS outputs for patch 1
262 * - Per-patch TCS outputs for patch 1
263 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
264 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
265 * - ...
266 *
267 * All three shaders VS(LS), TCS, TES share the same LDS space.
268 */
269
270 static LLVMValueRef
271 get_tcs_in_patch_stride(struct si_shader_context *si_shader_ctx)
272 {
273 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX)
274 return unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
275 else if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
276 return unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
277 else {
278 assert(0);
279 return NULL;
280 }
281 }
282
283 static LLVMValueRef
284 get_tcs_out_patch_stride(struct si_shader_context *si_shader_ctx)
285 {
286 return unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
287 }
288
289 static LLVMValueRef
290 get_tcs_out_patch0_offset(struct si_shader_context *si_shader_ctx)
291 {
292 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
293 unpack_param(si_shader_ctx,
294 SI_PARAM_TCS_OUT_OFFSETS,
295 0, 16),
296 4);
297 }
298
299 static LLVMValueRef
300 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *si_shader_ctx)
301 {
302 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
303 unpack_param(si_shader_ctx,
304 SI_PARAM_TCS_OUT_OFFSETS,
305 16, 16),
306 4);
307 }
308
309 static LLVMValueRef
310 get_tcs_in_current_patch_offset(struct si_shader_context *si_shader_ctx)
311 {
312 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
313 LLVMValueRef patch_stride = get_tcs_in_patch_stride(si_shader_ctx);
314 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
315
316 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
317 }
318
319 static LLVMValueRef
320 get_tcs_out_current_patch_offset(struct si_shader_context *si_shader_ctx)
321 {
322 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
323 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(si_shader_ctx);
324 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
325 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
326
327 return LLVMBuildAdd(gallivm->builder, patch0_offset,
328 LLVMBuildMul(gallivm->builder, patch_stride,
329 rel_patch_id, ""),
330 "");
331 }
332
333 static LLVMValueRef
334 get_tcs_out_current_patch_data_offset(struct si_shader_context *si_shader_ctx)
335 {
336 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
337 LLVMValueRef patch0_patch_data_offset =
338 get_tcs_out_patch0_patch_data_offset(si_shader_ctx);
339 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
340 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
341
342 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
343 LLVMBuildMul(gallivm->builder, patch_stride,
344 rel_patch_id, ""),
345 "");
346 }
347
348 static void build_indexed_store(struct si_shader_context *si_shader_ctx,
349 LLVMValueRef base_ptr, LLVMValueRef index,
350 LLVMValueRef value)
351 {
352 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
353 struct gallivm_state *gallivm = bld_base->base.gallivm;
354 LLVMValueRef indices[2], pointer;
355
356 indices[0] = bld_base->uint_bld.zero;
357 indices[1] = index;
358
359 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
360 LLVMBuildStore(gallivm->builder, value, pointer);
361 }
362
363 /**
364 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
365 * It's equivalent to doing a load from &base_ptr[index].
366 *
367 * \param base_ptr Where the array starts.
368 * \param index The element index into the array.
369 */
370 static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
371 LLVMValueRef base_ptr, LLVMValueRef index)
372 {
373 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
374 struct gallivm_state *gallivm = bld_base->base.gallivm;
375 LLVMValueRef indices[2], pointer;
376
377 indices[0] = bld_base->uint_bld.zero;
378 indices[1] = index;
379
380 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
381 return LLVMBuildLoad(gallivm->builder, pointer, "");
382 }
383
384 /**
385 * Do a load from &base_ptr[index], but also add a flag that it's loading
386 * a constant.
387 */
388 static LLVMValueRef build_indexed_load_const(
389 struct si_shader_context * si_shader_ctx,
390 LLVMValueRef base_ptr, LLVMValueRef index)
391 {
392 LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
393 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
394 return result;
395 }
396
397 static LLVMValueRef get_instance_index_for_fetch(
398 struct radeon_llvm_context * radeon_bld,
399 unsigned divisor)
400 {
401 struct si_shader_context *si_shader_ctx =
402 si_shader_context(&radeon_bld->soa.bld_base);
403 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
404
405 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
406 si_shader_ctx->param_instance_id);
407
408 /* The division must be done before START_INSTANCE is added. */
409 if (divisor > 1)
410 result = LLVMBuildUDiv(gallivm->builder, result,
411 lp_build_const_int32(gallivm, divisor), "");
412
413 return LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
414 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
415 }
416
417 static void declare_input_vs(
418 struct radeon_llvm_context *radeon_bld,
419 unsigned input_index,
420 const struct tgsi_full_declaration *decl)
421 {
422 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
423 struct gallivm_state *gallivm = base->gallivm;
424 struct si_shader_context *si_shader_ctx =
425 si_shader_context(&radeon_bld->soa.bld_base);
426 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
427
428 unsigned chan;
429
430 LLVMValueRef t_list_ptr;
431 LLVMValueRef t_offset;
432 LLVMValueRef t_list;
433 LLVMValueRef attribute_offset;
434 LLVMValueRef buffer_index;
435 LLVMValueRef args[3];
436 LLVMTypeRef vec4_type;
437 LLVMValueRef input;
438
439 /* Load the T list */
440 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
441
442 t_offset = lp_build_const_int32(gallivm, input_index);
443
444 t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
445
446 /* Build the attribute offset */
447 attribute_offset = lp_build_const_int32(gallivm, 0);
448
449 if (divisor) {
450 /* Build index from instance ID, start instance and divisor */
451 si_shader_ctx->shader->uses_instanceid = true;
452 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
453 } else {
454 /* Load the buffer index for vertices. */
455 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
456 si_shader_ctx->param_vertex_id);
457 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
458 SI_PARAM_BASE_VERTEX);
459 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
460 }
461
462 vec4_type = LLVMVectorType(base->elem_type, 4);
463 args[0] = t_list;
464 args[1] = attribute_offset;
465 args[2] = buffer_index;
466 input = lp_build_intrinsic(gallivm->builder,
467 "llvm.SI.vs.load.input", vec4_type, args, 3,
468 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
469
470 /* Break up the vec4 into individual components */
471 for (chan = 0; chan < 4; chan++) {
472 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
473 /* XXX: Use a helper function for this. There is one in
474 * tgsi_llvm.c. */
475 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
476 LLVMBuildExtractElement(gallivm->builder,
477 input, llvm_chan, "");
478 }
479 }
480
481 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
482 unsigned swizzle)
483 {
484 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
485
486 if (swizzle > 0)
487 return bld_base->uint_bld.zero;
488
489 switch (si_shader_ctx->type) {
490 case TGSI_PROCESSOR_VERTEX:
491 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
492 si_shader_ctx->param_vs_prim_id);
493 case TGSI_PROCESSOR_TESS_CTRL:
494 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
495 SI_PARAM_PATCH_ID);
496 case TGSI_PROCESSOR_TESS_EVAL:
497 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
498 si_shader_ctx->param_tes_patch_id);
499 case TGSI_PROCESSOR_GEOMETRY:
500 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
501 SI_PARAM_PRIMITIVE_ID);
502 default:
503 assert(0);
504 return bld_base->uint_bld.zero;
505 }
506 }
507
508 /**
509 * Return the value of tgsi_ind_register for indexing.
510 * This is the indirect index with the constant offset added to it.
511 */
512 static LLVMValueRef get_indirect_index(struct si_shader_context *si_shader_ctx,
513 const struct tgsi_ind_register *ind,
514 int rel_index)
515 {
516 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
517 LLVMValueRef result;
518
519 result = si_shader_ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
520 result = LLVMBuildLoad(gallivm->builder, result, "");
521 result = LLVMBuildAdd(gallivm->builder, result,
522 lp_build_const_int32(gallivm, rel_index), "");
523 return result;
524 }
525
526 /**
527 * Calculate a dword address given an input or output register and a stride.
528 */
529 static LLVMValueRef get_dw_address(struct si_shader_context *si_shader_ctx,
530 const struct tgsi_full_dst_register *dst,
531 const struct tgsi_full_src_register *src,
532 LLVMValueRef vertex_dw_stride,
533 LLVMValueRef base_addr)
534 {
535 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
536 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
537 ubyte *name, *index, *array_first;
538 int first, param;
539 struct tgsi_full_dst_register reg;
540
541 /* Set the register description. The address computation is the same
542 * for sources and destinations. */
543 if (src) {
544 reg.Register.File = src->Register.File;
545 reg.Register.Index = src->Register.Index;
546 reg.Register.Indirect = src->Register.Indirect;
547 reg.Register.Dimension = src->Register.Dimension;
548 reg.Indirect = src->Indirect;
549 reg.Dimension = src->Dimension;
550 reg.DimIndirect = src->DimIndirect;
551 } else
552 reg = *dst;
553
554 /* If the register is 2-dimensional (e.g. an array of vertices
555 * in a primitive), calculate the base address of the vertex. */
556 if (reg.Register.Dimension) {
557 LLVMValueRef index;
558
559 if (reg.Dimension.Indirect)
560 index = get_indirect_index(si_shader_ctx, &reg.DimIndirect,
561 reg.Dimension.Index);
562 else
563 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
564
565 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
566 LLVMBuildMul(gallivm->builder, index,
567 vertex_dw_stride, ""), "");
568 }
569
570 /* Get information about the register. */
571 if (reg.Register.File == TGSI_FILE_INPUT) {
572 name = info->input_semantic_name;
573 index = info->input_semantic_index;
574 array_first = info->input_array_first;
575 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
576 name = info->output_semantic_name;
577 index = info->output_semantic_index;
578 array_first = info->output_array_first;
579 } else {
580 assert(0);
581 return NULL;
582 }
583
584 if (reg.Register.Indirect) {
585 /* Add the relative address of the element. */
586 LLVMValueRef ind_index;
587
588 if (reg.Indirect.ArrayID)
589 first = array_first[reg.Indirect.ArrayID];
590 else
591 first = reg.Register.Index;
592
593 ind_index = get_indirect_index(si_shader_ctx, &reg.Indirect,
594 reg.Register.Index - first);
595
596 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
597 LLVMBuildMul(gallivm->builder, ind_index,
598 lp_build_const_int32(gallivm, 4), ""), "");
599
600 param = si_shader_io_get_unique_index(name[first], index[first]);
601 } else {
602 param = si_shader_io_get_unique_index(name[reg.Register.Index],
603 index[reg.Register.Index]);
604 }
605
606 /* Add the base address of the element. */
607 return LLVMBuildAdd(gallivm->builder, base_addr,
608 lp_build_const_int32(gallivm, param * 4), "");
609 }
610
611 /**
612 * Load from LDS.
613 *
614 * \param type output value type
615 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
616 * \param dw_addr address in dwords
617 */
618 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
619 enum tgsi_opcode_type type, unsigned swizzle,
620 LLVMValueRef dw_addr)
621 {
622 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
623 struct gallivm_state *gallivm = bld_base->base.gallivm;
624 LLVMValueRef value;
625
626 if (swizzle == ~0) {
627 LLVMValueRef values[TGSI_NUM_CHANNELS];
628
629 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
630 values[chan] = lds_load(bld_base, type, chan, dw_addr);
631
632 return lp_build_gather_values(bld_base->base.gallivm, values,
633 TGSI_NUM_CHANNELS);
634 }
635
636 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
637 lp_build_const_int32(gallivm, swizzle));
638
639 value = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
640 return LLVMBuildBitCast(gallivm->builder, value,
641 tgsi2llvmtype(bld_base, type), "");
642 }
643
644 /**
645 * Store to LDS.
646 *
647 * \param swizzle offset (typically 0..3)
648 * \param dw_addr address in dwords
649 * \param value value to store
650 */
651 static void lds_store(struct lp_build_tgsi_context * bld_base,
652 unsigned swizzle, LLVMValueRef dw_addr,
653 LLVMValueRef value)
654 {
655 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
656 struct gallivm_state *gallivm = bld_base->base.gallivm;
657
658 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
659 lp_build_const_int32(gallivm, swizzle));
660
661 value = LLVMBuildBitCast(gallivm->builder, value,
662 LLVMInt32TypeInContext(gallivm->context), "");
663 build_indexed_store(si_shader_ctx, si_shader_ctx->lds,
664 dw_addr, value);
665 }
666
667 static LLVMValueRef fetch_input_tcs(
668 struct lp_build_tgsi_context *bld_base,
669 const struct tgsi_full_src_register *reg,
670 enum tgsi_opcode_type type, unsigned swizzle)
671 {
672 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
673 LLVMValueRef dw_addr, stride;
674
675 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
676 dw_addr = get_tcs_in_current_patch_offset(si_shader_ctx);
677 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
678
679 return lds_load(bld_base, type, swizzle, dw_addr);
680 }
681
682 static LLVMValueRef fetch_output_tcs(
683 struct lp_build_tgsi_context *bld_base,
684 const struct tgsi_full_src_register *reg,
685 enum tgsi_opcode_type type, unsigned swizzle)
686 {
687 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
688 LLVMValueRef dw_addr, stride;
689
690 if (reg->Register.Dimension) {
691 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
692 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
693 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
694 } else {
695 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
696 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
697 }
698
699 return lds_load(bld_base, type, swizzle, dw_addr);
700 }
701
702 static LLVMValueRef fetch_input_tes(
703 struct lp_build_tgsi_context *bld_base,
704 const struct tgsi_full_src_register *reg,
705 enum tgsi_opcode_type type, unsigned swizzle)
706 {
707 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
708 LLVMValueRef dw_addr, stride;
709
710 if (reg->Register.Dimension) {
711 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
712 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
713 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
714 } else {
715 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
716 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
717 }
718
719 return lds_load(bld_base, type, swizzle, dw_addr);
720 }
721
722 static void store_output_tcs(struct lp_build_tgsi_context * bld_base,
723 const struct tgsi_full_instruction * inst,
724 const struct tgsi_opcode_info * info,
725 LLVMValueRef dst[4])
726 {
727 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
728 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
729 unsigned chan_index;
730 LLVMValueRef dw_addr, stride;
731
732 /* Only handle per-patch and per-vertex outputs here.
733 * Vectors will be lowered to scalars and this function will be called again.
734 */
735 if (reg->Register.File != TGSI_FILE_OUTPUT ||
736 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
737 radeon_llvm_emit_store(bld_base, inst, info, dst);
738 return;
739 }
740
741 if (reg->Register.Dimension) {
742 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
743 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
744 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, stride, dw_addr);
745 } else {
746 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
747 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, NULL, dw_addr);
748 }
749
750 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
751 LLVMValueRef value = dst[chan_index];
752
753 if (inst->Instruction.Saturate)
754 value = radeon_llvm_saturate(bld_base, value);
755
756 lds_store(bld_base, chan_index, dw_addr, value);
757 }
758 }
759
760 static LLVMValueRef fetch_input_gs(
761 struct lp_build_tgsi_context *bld_base,
762 const struct tgsi_full_src_register *reg,
763 enum tgsi_opcode_type type,
764 unsigned swizzle)
765 {
766 struct lp_build_context *base = &bld_base->base;
767 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
768 struct si_shader *shader = si_shader_ctx->shader;
769 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
770 struct gallivm_state *gallivm = base->gallivm;
771 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
772 LLVMValueRef vtx_offset;
773 LLVMValueRef args[9];
774 unsigned vtx_offset_param;
775 struct tgsi_shader_info *info = &shader->selector->info;
776 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
777 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
778
779 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
780 return get_primitive_id(bld_base, swizzle);
781
782 if (!reg->Register.Dimension)
783 return NULL;
784
785 if (swizzle == ~0) {
786 LLVMValueRef values[TGSI_NUM_CHANNELS];
787 unsigned chan;
788 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
789 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
790 }
791 return lp_build_gather_values(bld_base->base.gallivm, values,
792 TGSI_NUM_CHANNELS);
793 }
794
795 /* Get the vertex offset parameter */
796 vtx_offset_param = reg->Dimension.Index;
797 if (vtx_offset_param < 2) {
798 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
799 } else {
800 assert(vtx_offset_param < 6);
801 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
802 }
803 vtx_offset = lp_build_mul_imm(uint,
804 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
805 vtx_offset_param),
806 4);
807
808 args[0] = si_shader_ctx->esgs_ring;
809 args[1] = vtx_offset;
810 args[2] = lp_build_const_int32(gallivm,
811 (get_param_index(semantic_name, semantic_index,
812 shader->selector->inputs_read) * 4 +
813 swizzle) * 256);
814 args[3] = uint->zero;
815 args[4] = uint->one; /* OFFEN */
816 args[5] = uint->zero; /* IDXEN */
817 args[6] = uint->one; /* GLC */
818 args[7] = uint->zero; /* SLC */
819 args[8] = uint->zero; /* TFE */
820
821 return LLVMBuildBitCast(gallivm->builder,
822 lp_build_intrinsic(gallivm->builder,
823 "llvm.SI.buffer.load.dword.i32.i32",
824 i32, args, 9,
825 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
826 tgsi2llvmtype(bld_base, type), "");
827 }
828
829 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
830 {
831 switch (interpolate) {
832 case TGSI_INTERPOLATE_CONSTANT:
833 return 0;
834
835 case TGSI_INTERPOLATE_LINEAR:
836 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
837 return SI_PARAM_LINEAR_SAMPLE;
838 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
839 return SI_PARAM_LINEAR_CENTROID;
840 else
841 return SI_PARAM_LINEAR_CENTER;
842 break;
843 case TGSI_INTERPOLATE_COLOR:
844 case TGSI_INTERPOLATE_PERSPECTIVE:
845 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
846 return SI_PARAM_PERSP_SAMPLE;
847 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
848 return SI_PARAM_PERSP_CENTROID;
849 else
850 return SI_PARAM_PERSP_CENTER;
851 break;
852 default:
853 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
854 return -1;
855 }
856 }
857
858 static void declare_input_fs(
859 struct radeon_llvm_context *radeon_bld,
860 unsigned input_index,
861 const struct tgsi_full_declaration *decl)
862 {
863 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
864 struct si_shader_context *si_shader_ctx =
865 si_shader_context(&radeon_bld->soa.bld_base);
866 struct si_shader *shader = si_shader_ctx->shader;
867 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
868 struct gallivm_state *gallivm = base->gallivm;
869 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
870 LLVMValueRef main_fn = radeon_bld->main_fn;
871
872 LLVMValueRef interp_param = NULL;
873 int interp_param_idx;
874 const char * intr_name;
875
876 /* This value is:
877 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
878 * quad begins a new primitive. Bit 0 always needs
879 * to be unset)
880 * [32:16] ParamOffset
881 *
882 */
883 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
884 LLVMValueRef attr_number;
885
886 unsigned chan;
887
888 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
889 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
890 unsigned soa_index =
891 radeon_llvm_reg_index_soa(input_index, chan);
892 radeon_bld->inputs[soa_index] =
893 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
894
895 if (chan == 3)
896 /* RCP for fragcoord.w */
897 radeon_bld->inputs[soa_index] =
898 LLVMBuildFDiv(gallivm->builder,
899 lp_build_const_float(gallivm, 1.0f),
900 radeon_bld->inputs[soa_index],
901 "");
902 }
903 return;
904 }
905
906 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
907 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
908 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
909 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
910 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
911 lp_build_const_float(gallivm, 0.0f);
912 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
913 lp_build_const_float(gallivm, 1.0f);
914
915 return;
916 }
917
918 shader->ps_input_param_offset[input_index] = shader->nparam++;
919 attr_number = lp_build_const_int32(gallivm,
920 shader->ps_input_param_offset[input_index]);
921
922 shader->ps_input_interpolate[input_index] = decl->Interp.Interpolate;
923 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
924 decl->Interp.Location);
925 if (interp_param_idx == -1)
926 return;
927 else if (interp_param_idx)
928 interp_param = LLVMGetParam(main_fn, interp_param_idx);
929
930 /* fs.constant returns the param from the middle vertex, so it's not
931 * really useful for flat shading. It's meant to be used for custom
932 * interpolation (but the intrinsic can't fetch from the other two
933 * vertices).
934 *
935 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
936 * to do the right thing. The only reason we use fs.constant is that
937 * fs.interp cannot be used on integers, because they can be equal
938 * to NaN.
939 */
940 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
941
942 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
943 si_shader_ctx->shader->key.ps.color_two_side) {
944 LLVMValueRef args[4];
945 LLVMValueRef face, is_face_positive;
946 LLVMValueRef back_attr_number =
947 lp_build_const_int32(gallivm,
948 shader->ps_input_param_offset[input_index] + 1);
949
950 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
951
952 is_face_positive = LLVMBuildFCmp(gallivm->builder,
953 LLVMRealOGT, face,
954 lp_build_const_float(gallivm, 0.0f),
955 "");
956
957 args[2] = params;
958 args[3] = interp_param;
959 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
960 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
961 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
962 LLVMValueRef front, back;
963
964 args[0] = llvm_chan;
965 args[1] = attr_number;
966 front = lp_build_intrinsic(gallivm->builder, intr_name,
967 input_type, args, args[3] ? 4 : 3,
968 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
969
970 args[1] = back_attr_number;
971 back = lp_build_intrinsic(gallivm->builder, intr_name,
972 input_type, args, args[3] ? 4 : 3,
973 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
974
975 radeon_bld->inputs[soa_index] =
976 LLVMBuildSelect(gallivm->builder,
977 is_face_positive,
978 front,
979 back,
980 "");
981 }
982
983 shader->nparam++;
984 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
985 LLVMValueRef args[4];
986
987 args[0] = uint->zero;
988 args[1] = attr_number;
989 args[2] = params;
990 args[3] = interp_param;
991 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
992 lp_build_intrinsic(gallivm->builder, intr_name,
993 input_type, args, args[3] ? 4 : 3,
994 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
995 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
996 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
997 lp_build_const_float(gallivm, 0.0f);
998 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
999 lp_build_const_float(gallivm, 1.0f);
1000 } else {
1001 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1002 LLVMValueRef args[4];
1003 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1004 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
1005 args[0] = llvm_chan;
1006 args[1] = attr_number;
1007 args[2] = params;
1008 args[3] = interp_param;
1009 radeon_bld->inputs[soa_index] =
1010 lp_build_intrinsic(gallivm->builder, intr_name,
1011 input_type, args, args[3] ? 4 : 3,
1012 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1013 }
1014 }
1015 }
1016
1017 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1018 {
1019 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1020 SI_PARAM_ANCILLARY, 8, 4);
1021 }
1022
1023 /**
1024 * Load a dword from a constant buffer.
1025 */
1026 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1027 LLVMValueRef offset, LLVMTypeRef return_type)
1028 {
1029 LLVMValueRef args[2] = {resource, offset};
1030
1031 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1032 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1033 }
1034
1035 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1036 {
1037 struct si_shader_context *si_shader_ctx =
1038 si_shader_context(&radeon_bld->soa.bld_base);
1039 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1040 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1041 LLVMBuilderRef builder = gallivm->builder;
1042 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1043 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
1044 LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
1045
1046 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1047 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1048 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1049
1050 LLVMValueRef pos[4] = {
1051 buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
1052 buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
1053 lp_build_const_float(gallivm, 0),
1054 lp_build_const_float(gallivm, 0)
1055 };
1056
1057 return lp_build_gather_values(gallivm, pos, 4);
1058 }
1059
1060 static void declare_system_value(
1061 struct radeon_llvm_context * radeon_bld,
1062 unsigned index,
1063 const struct tgsi_full_declaration *decl)
1064 {
1065 struct si_shader_context *si_shader_ctx =
1066 si_shader_context(&radeon_bld->soa.bld_base);
1067 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1068 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1069 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1070 LLVMValueRef value = 0;
1071
1072 switch (decl->Semantic.Name) {
1073 case TGSI_SEMANTIC_INSTANCEID:
1074 value = LLVMGetParam(radeon_bld->main_fn,
1075 si_shader_ctx->param_instance_id);
1076 break;
1077
1078 case TGSI_SEMANTIC_VERTEXID:
1079 value = LLVMBuildAdd(gallivm->builder,
1080 LLVMGetParam(radeon_bld->main_fn,
1081 si_shader_ctx->param_vertex_id),
1082 LLVMGetParam(radeon_bld->main_fn,
1083 SI_PARAM_BASE_VERTEX), "");
1084 break;
1085
1086 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1087 value = LLVMGetParam(radeon_bld->main_fn,
1088 si_shader_ctx->param_vertex_id);
1089 break;
1090
1091 case TGSI_SEMANTIC_BASEVERTEX:
1092 value = LLVMGetParam(radeon_bld->main_fn,
1093 SI_PARAM_BASE_VERTEX);
1094 break;
1095
1096 case TGSI_SEMANTIC_INVOCATIONID:
1097 if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
1098 value = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1099 else if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY)
1100 value = LLVMGetParam(radeon_bld->main_fn,
1101 SI_PARAM_GS_INSTANCE_ID);
1102 else
1103 assert(!"INVOCATIONID not implemented");
1104 break;
1105
1106 case TGSI_SEMANTIC_SAMPLEID:
1107 value = get_sample_id(radeon_bld);
1108 break;
1109
1110 case TGSI_SEMANTIC_SAMPLEPOS:
1111 value = load_sample_position(radeon_bld, get_sample_id(radeon_bld));
1112 break;
1113
1114 case TGSI_SEMANTIC_SAMPLEMASK:
1115 /* Smoothing isn't MSAA in GL, but it's MSAA in hardware.
1116 * Therefore, force gl_SampleMaskIn to 1 for GL. */
1117 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
1118 value = uint_bld->one;
1119 else
1120 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1121 break;
1122
1123 case TGSI_SEMANTIC_TESSCOORD:
1124 {
1125 LLVMValueRef coord[4] = {
1126 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_u),
1127 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_v),
1128 bld->zero,
1129 bld->zero
1130 };
1131
1132 /* For triangles, the vector should be (u, v, 1-u-v). */
1133 if (si_shader_ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1134 PIPE_PRIM_TRIANGLES)
1135 coord[2] = lp_build_sub(bld, bld->one,
1136 lp_build_add(bld, coord[0], coord[1]));
1137
1138 value = lp_build_gather_values(gallivm, coord, 4);
1139 break;
1140 }
1141
1142 case TGSI_SEMANTIC_VERTICESIN:
1143 value = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1144 break;
1145
1146 case TGSI_SEMANTIC_TESSINNER:
1147 case TGSI_SEMANTIC_TESSOUTER:
1148 {
1149 LLVMValueRef dw_addr;
1150 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1151
1152 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1153 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1154 lp_build_const_int32(gallivm, param * 4), "");
1155
1156 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1157 ~0, dw_addr);
1158 break;
1159 }
1160
1161 case TGSI_SEMANTIC_PRIMID:
1162 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1163 break;
1164
1165 default:
1166 assert(!"unknown system value");
1167 return;
1168 }
1169
1170 radeon_bld->system_values[index] = value;
1171 }
1172
1173 static LLVMValueRef fetch_constant(
1174 struct lp_build_tgsi_context * bld_base,
1175 const struct tgsi_full_src_register *reg,
1176 enum tgsi_opcode_type type,
1177 unsigned swizzle)
1178 {
1179 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1180 struct lp_build_context * base = &bld_base->base;
1181 const struct tgsi_ind_register *ireg = &reg->Indirect;
1182 unsigned buf, idx;
1183
1184 LLVMValueRef addr, bufp;
1185 LLVMValueRef result;
1186
1187 if (swizzle == LP_CHAN_ALL) {
1188 unsigned chan;
1189 LLVMValueRef values[4];
1190 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1191 values[chan] = fetch_constant(bld_base, reg, type, chan);
1192
1193 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1194 }
1195
1196 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1197 idx = reg->Register.Index * 4 + swizzle;
1198
1199 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1200 if (type != TGSI_TYPE_DOUBLE)
1201 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
1202 else {
1203 return radeon_llvm_emit_fetch_double(bld_base,
1204 si_shader_ctx->constants[buf][idx],
1205 si_shader_ctx->constants[buf][idx + 1]);
1206 }
1207 }
1208
1209 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1210 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1211 LLVMValueRef index;
1212 index = get_indirect_index(si_shader_ctx, &reg->DimIndirect,
1213 reg->Dimension.Index);
1214 bufp = build_indexed_load_const(si_shader_ctx, ptr, index);
1215 } else
1216 bufp = si_shader_ctx->const_resource[buf];
1217
1218 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1219 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1220 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1221 addr = lp_build_add(&bld_base->uint_bld, addr,
1222 lp_build_const_int32(base->gallivm, idx * 4));
1223
1224 result = buffer_load_const(base->gallivm->builder, bufp,
1225 addr, bld_base->base.elem_type);
1226
1227 if (type != TGSI_TYPE_DOUBLE)
1228 result = bitcast(bld_base, type, result);
1229 else {
1230 LLVMValueRef addr2, result2;
1231 addr2 = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1232 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1233 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1234 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1235 lp_build_const_int32(base->gallivm, idx * 4));
1236
1237 result2 = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
1238 addr2, bld_base->base.elem_type);
1239
1240 result = radeon_llvm_emit_fetch_double(bld_base,
1241 result, result2);
1242 }
1243 return result;
1244 }
1245
1246 /* Initialize arguments for the shader export intrinsic */
1247 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1248 LLVMValueRef *values,
1249 unsigned target,
1250 LLVMValueRef *args)
1251 {
1252 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1253 struct lp_build_context *uint =
1254 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1255 struct lp_build_context *base = &bld_base->base;
1256 unsigned compressed = 0;
1257 unsigned chan;
1258
1259 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
1260 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1261
1262 if (cbuf >= 0 && cbuf < 8) {
1263 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
1264
1265 if (compressed)
1266 si_shader_ctx->shader->spi_shader_col_format |=
1267 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
1268 else
1269 si_shader_ctx->shader->spi_shader_col_format |=
1270 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
1271
1272 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
1273 }
1274 }
1275
1276 if (compressed) {
1277 /* Pixel shader needs to pack output values before export */
1278 for (chan = 0; chan < 2; chan++ ) {
1279 args[0] = values[2 * chan];
1280 args[1] = values[2 * chan + 1];
1281 args[chan + 5] =
1282 lp_build_intrinsic(base->gallivm->builder,
1283 "llvm.SI.packf16",
1284 LLVMInt32TypeInContext(base->gallivm->context),
1285 args, 2,
1286 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1287 args[chan + 7] = args[chan + 5] =
1288 LLVMBuildBitCast(base->gallivm->builder,
1289 args[chan + 5],
1290 LLVMFloatTypeInContext(base->gallivm->context),
1291 "");
1292 }
1293
1294 /* Set COMPR flag */
1295 args[4] = uint->one;
1296 } else {
1297 for (chan = 0; chan < 4; chan++ )
1298 /* +5 because the first output value will be
1299 * the 6th argument to the intrinsic. */
1300 args[chan + 5] = values[chan];
1301
1302 /* Clear COMPR flag */
1303 args[4] = uint->zero;
1304 }
1305
1306 /* XXX: This controls which components of the output
1307 * registers actually get exported. (e.g bit 0 means export
1308 * X component, bit 1 means export Y component, etc.) I'm
1309 * hard coding this to 0xf for now. In the future, we might
1310 * want to do something else. */
1311 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1312
1313 /* Specify whether the EXEC mask represents the valid mask */
1314 args[1] = uint->zero;
1315
1316 /* Specify whether this is the last export */
1317 args[2] = uint->zero;
1318
1319 /* Specify the target we are exporting */
1320 args[3] = lp_build_const_int32(base->gallivm, target);
1321
1322 /* XXX: We probably need to keep track of the output
1323 * values, so we know what we are passing to the next
1324 * stage. */
1325 }
1326
1327 /* Load from output pointers and initialize arguments for the shader export intrinsic */
1328 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
1329 LLVMValueRef *out_ptr,
1330 unsigned target,
1331 LLVMValueRef *args)
1332 {
1333 struct gallivm_state *gallivm = bld_base->base.gallivm;
1334 LLVMValueRef values[4];
1335 int i;
1336
1337 for (i = 0; i < 4; i++)
1338 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
1339
1340 si_llvm_init_export_args(bld_base, values, target, args);
1341 }
1342
1343 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1344 LLVMValueRef alpha_ptr)
1345 {
1346 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1347 struct gallivm_state *gallivm = bld_base->base.gallivm;
1348
1349 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
1350 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1351 SI_PARAM_ALPHA_REF);
1352
1353 LLVMValueRef alpha_pass =
1354 lp_build_cmp(&bld_base->base,
1355 si_shader_ctx->shader->key.ps.alpha_func,
1356 LLVMBuildLoad(gallivm->builder, alpha_ptr, ""),
1357 alpha_ref);
1358 LLVMValueRef arg =
1359 lp_build_select(&bld_base->base,
1360 alpha_pass,
1361 lp_build_const_float(gallivm, 1.0f),
1362 lp_build_const_float(gallivm, -1.0f));
1363
1364 lp_build_intrinsic(gallivm->builder,
1365 "llvm.AMDGPU.kill",
1366 LLVMVoidTypeInContext(gallivm->context),
1367 &arg, 1, 0);
1368 } else {
1369 lp_build_intrinsic(gallivm->builder,
1370 "llvm.AMDGPU.kilp",
1371 LLVMVoidTypeInContext(gallivm->context),
1372 NULL, 0, 0);
1373 }
1374
1375 si_shader_ctx->shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
1376 }
1377
1378 static void si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1379 LLVMValueRef alpha_ptr)
1380 {
1381 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1382 struct gallivm_state *gallivm = bld_base->base.gallivm;
1383 LLVMValueRef coverage, alpha;
1384
1385 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1386 coverage = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1387 SI_PARAM_SAMPLE_COVERAGE);
1388 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1389
1390 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1391 bld_base->int_bld.elem_type,
1392 &coverage, 1, LLVMReadNoneAttribute);
1393
1394 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1395 bld_base->base.elem_type, "");
1396
1397 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1398 lp_build_const_float(gallivm,
1399 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1400
1401 alpha = LLVMBuildLoad(gallivm->builder, alpha_ptr, "");
1402 alpha = LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1403 LLVMBuildStore(gallivm->builder, alpha, alpha_ptr);
1404 }
1405
1406 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
1407 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1408 {
1409 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1410 struct lp_build_context *base = &bld_base->base;
1411 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1412 unsigned reg_index;
1413 unsigned chan;
1414 unsigned const_chan;
1415 LLVMValueRef base_elt;
1416 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1417 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
1418 LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
1419
1420 for (reg_index = 0; reg_index < 2; reg_index ++) {
1421 LLVMValueRef *args = pos[2 + reg_index];
1422
1423 args[5] =
1424 args[6] =
1425 args[7] =
1426 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1427
1428 /* Compute dot products of position and user clip plane vectors */
1429 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1430 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1431 args[1] = lp_build_const_int32(base->gallivm,
1432 ((reg_index * 4 + chan) * 4 +
1433 const_chan) * 4);
1434 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1435 args[1], base->elem_type);
1436 args[5 + chan] =
1437 lp_build_add(base, args[5 + chan],
1438 lp_build_mul(base, base_elt,
1439 out_elts[const_chan]));
1440 }
1441 }
1442
1443 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1444 args[1] = uint->zero;
1445 args[2] = uint->zero;
1446 args[3] = lp_build_const_int32(base->gallivm,
1447 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1448 args[4] = uint->zero;
1449 }
1450 }
1451
1452 static void si_dump_streamout(struct pipe_stream_output_info *so)
1453 {
1454 unsigned i;
1455
1456 if (so->num_outputs)
1457 fprintf(stderr, "STREAMOUT\n");
1458
1459 for (i = 0; i < so->num_outputs; i++) {
1460 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1461 so->output[i].start_component;
1462 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1463 i, so->output[i].output_buffer,
1464 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1465 so->output[i].register_index,
1466 mask & 1 ? "x" : "",
1467 mask & 2 ? "y" : "",
1468 mask & 4 ? "z" : "",
1469 mask & 8 ? "w" : "");
1470 }
1471 }
1472
1473 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1474 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1475 * or v4i32 (num_channels=3,4). */
1476 static void build_tbuffer_store(struct si_shader_context *shader,
1477 LLVMValueRef rsrc,
1478 LLVMValueRef vdata,
1479 unsigned num_channels,
1480 LLVMValueRef vaddr,
1481 LLVMValueRef soffset,
1482 unsigned inst_offset,
1483 unsigned dfmt,
1484 unsigned nfmt,
1485 unsigned offen,
1486 unsigned idxen,
1487 unsigned glc,
1488 unsigned slc,
1489 unsigned tfe)
1490 {
1491 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1492 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1493 LLVMValueRef args[] = {
1494 rsrc,
1495 vdata,
1496 LLVMConstInt(i32, num_channels, 0),
1497 vaddr,
1498 soffset,
1499 LLVMConstInt(i32, inst_offset, 0),
1500 LLVMConstInt(i32, dfmt, 0),
1501 LLVMConstInt(i32, nfmt, 0),
1502 LLVMConstInt(i32, offen, 0),
1503 LLVMConstInt(i32, idxen, 0),
1504 LLVMConstInt(i32, glc, 0),
1505 LLVMConstInt(i32, slc, 0),
1506 LLVMConstInt(i32, tfe, 0)
1507 };
1508
1509 /* The instruction offset field has 12 bits */
1510 assert(offen || inst_offset < (1 << 12));
1511
1512 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1513 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1514 const char *types[] = {"i32", "v2i32", "v4i32"};
1515 char name[256];
1516 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1517
1518 lp_build_intrinsic(gallivm->builder, name,
1519 LLVMVoidTypeInContext(gallivm->context),
1520 args, Elements(args), 0);
1521 }
1522
1523 static void build_tbuffer_store_dwords(struct si_shader_context *shader,
1524 LLVMValueRef rsrc,
1525 LLVMValueRef vdata,
1526 unsigned num_channels,
1527 LLVMValueRef vaddr,
1528 LLVMValueRef soffset,
1529 unsigned inst_offset)
1530 {
1531 static unsigned dfmt[] = {
1532 V_008F0C_BUF_DATA_FORMAT_32,
1533 V_008F0C_BUF_DATA_FORMAT_32_32,
1534 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1535 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1536 };
1537 assert(num_channels >= 1 && num_channels <= 4);
1538
1539 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
1540 inst_offset, dfmt[num_channels-1],
1541 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1542 }
1543
1544 /* On SI, the vertex shader is responsible for writing streamout data
1545 * to buffers. */
1546 static void si_llvm_emit_streamout(struct si_shader_context *shader,
1547 struct si_shader_output_values *outputs,
1548 unsigned noutput)
1549 {
1550 struct pipe_stream_output_info *so = &shader->shader->selector->so;
1551 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1552 LLVMBuilderRef builder = gallivm->builder;
1553 int i, j;
1554 struct lp_build_if_state if_ctx;
1555
1556 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1557
1558 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1559 LLVMValueRef so_vtx_count =
1560 unpack_param(shader, shader->param_streamout_config, 16, 7);
1561
1562 LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", i32,
1563 NULL, 0, LLVMReadNoneAttribute);
1564
1565 /* can_emit = tid < so_vtx_count; */
1566 LLVMValueRef can_emit =
1567 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1568
1569 LLVMValueRef stream_id =
1570 unpack_param(shader, shader->param_streamout_config, 24, 2);
1571
1572 /* Emit the streamout code conditionally. This actually avoids
1573 * out-of-bounds buffer access. The hw tells us via the SGPR
1574 * (so_vtx_count) which threads are allowed to emit streamout data. */
1575 lp_build_if(&if_ctx, gallivm, can_emit);
1576 {
1577 /* The buffer offset is computed as follows:
1578 * ByteOffset = streamout_offset[buffer_id]*4 +
1579 * (streamout_write_index + thread_id)*stride[buffer_id] +
1580 * attrib_offset
1581 */
1582
1583 LLVMValueRef so_write_index =
1584 LLVMGetParam(shader->radeon_bld.main_fn,
1585 shader->param_streamout_write_index);
1586
1587 /* Compute (streamout_write_index + thread_id). */
1588 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1589
1590 /* Compute the write offset for each enabled buffer. */
1591 LLVMValueRef so_write_offset[4] = {};
1592 for (i = 0; i < 4; i++) {
1593 if (!so->stride[i])
1594 continue;
1595
1596 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1597 shader->param_streamout_offset[i]);
1598 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1599
1600 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1601 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1602 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1603 }
1604
1605 /* Write streamout data. */
1606 for (i = 0; i < so->num_outputs; i++) {
1607 unsigned buf_idx = so->output[i].output_buffer;
1608 unsigned reg = so->output[i].register_index;
1609 unsigned start = so->output[i].start_component;
1610 unsigned num_comps = so->output[i].num_components;
1611 unsigned stream = so->output[i].stream;
1612 LLVMValueRef out[4];
1613 struct lp_build_if_state if_ctx_stream;
1614
1615 assert(num_comps && num_comps <= 4);
1616 if (!num_comps || num_comps > 4)
1617 continue;
1618
1619 if (reg >= noutput)
1620 continue;
1621
1622 /* Load the output as int. */
1623 for (j = 0; j < num_comps; j++) {
1624 out[j] = LLVMBuildBitCast(builder,
1625 outputs[reg].values[start+j],
1626 i32, "");
1627 }
1628
1629 /* Pack the output. */
1630 LLVMValueRef vdata = NULL;
1631
1632 switch (num_comps) {
1633 case 1: /* as i32 */
1634 vdata = out[0];
1635 break;
1636 case 2: /* as v2i32 */
1637 case 3: /* as v4i32 (aligned to 4) */
1638 case 4: /* as v4i32 */
1639 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1640 for (j = 0; j < num_comps; j++) {
1641 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1642 LLVMConstInt(i32, j, 0), "");
1643 }
1644 break;
1645 }
1646
1647 LLVMValueRef can_emit_stream =
1648 LLVMBuildICmp(builder, LLVMIntEQ,
1649 stream_id,
1650 lp_build_const_int32(gallivm, stream), "");
1651
1652 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1653 build_tbuffer_store_dwords(shader, shader->so_buffers[buf_idx],
1654 vdata, num_comps,
1655 so_write_offset[buf_idx],
1656 LLVMConstInt(i32, 0, 0),
1657 so->output[i].dst_offset*4);
1658 lp_build_endif(&if_ctx_stream);
1659 }
1660 }
1661 lp_build_endif(&if_ctx);
1662 }
1663
1664
1665 /* Generate export instructions for hardware VS shader stage */
1666 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1667 struct si_shader_output_values *outputs,
1668 unsigned noutput)
1669 {
1670 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1671 struct si_shader * shader = si_shader_ctx->shader;
1672 struct lp_build_context * base = &bld_base->base;
1673 struct lp_build_context * uint =
1674 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1675 LLVMValueRef args[9];
1676 LLVMValueRef pos_args[4][9] = { { 0 } };
1677 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1678 unsigned semantic_name, semantic_index;
1679 unsigned target;
1680 unsigned param_count = 0;
1681 unsigned pos_idx;
1682 int i;
1683
1684 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1685 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1686 }
1687
1688 for (i = 0; i < noutput; i++) {
1689 semantic_name = outputs[i].name;
1690 semantic_index = outputs[i].sid;
1691
1692 handle_semantic:
1693 /* Select the correct target */
1694 switch(semantic_name) {
1695 case TGSI_SEMANTIC_PSIZE:
1696 psize_value = outputs[i].values[0];
1697 continue;
1698 case TGSI_SEMANTIC_EDGEFLAG:
1699 edgeflag_value = outputs[i].values[0];
1700 continue;
1701 case TGSI_SEMANTIC_LAYER:
1702 layer_value = outputs[i].values[0];
1703 semantic_name = TGSI_SEMANTIC_GENERIC;
1704 goto handle_semantic;
1705 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1706 viewport_index_value = outputs[i].values[0];
1707 semantic_name = TGSI_SEMANTIC_GENERIC;
1708 goto handle_semantic;
1709 case TGSI_SEMANTIC_POSITION:
1710 target = V_008DFC_SQ_EXP_POS;
1711 break;
1712 case TGSI_SEMANTIC_COLOR:
1713 case TGSI_SEMANTIC_BCOLOR:
1714 target = V_008DFC_SQ_EXP_PARAM + param_count;
1715 shader->vs_output_param_offset[i] = param_count;
1716 param_count++;
1717 break;
1718 case TGSI_SEMANTIC_CLIPDIST:
1719 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1720 break;
1721 case TGSI_SEMANTIC_CLIPVERTEX:
1722 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1723 continue;
1724 case TGSI_SEMANTIC_PRIMID:
1725 case TGSI_SEMANTIC_FOG:
1726 case TGSI_SEMANTIC_TEXCOORD:
1727 case TGSI_SEMANTIC_GENERIC:
1728 target = V_008DFC_SQ_EXP_PARAM + param_count;
1729 shader->vs_output_param_offset[i] = param_count;
1730 param_count++;
1731 break;
1732 default:
1733 target = 0;
1734 fprintf(stderr,
1735 "Warning: SI unhandled vs output type:%d\n",
1736 semantic_name);
1737 }
1738
1739 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1740
1741 if (target >= V_008DFC_SQ_EXP_POS &&
1742 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1743 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1744 args, sizeof(args));
1745 } else {
1746 lp_build_intrinsic(base->gallivm->builder,
1747 "llvm.SI.export",
1748 LLVMVoidTypeInContext(base->gallivm->context),
1749 args, 9, 0);
1750 }
1751
1752 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1753 semantic_name = TGSI_SEMANTIC_GENERIC;
1754 goto handle_semantic;
1755 }
1756 }
1757
1758 shader->nr_param_exports = param_count;
1759
1760 /* We need to add the position output manually if it's missing. */
1761 if (!pos_args[0][0]) {
1762 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1763 pos_args[0][1] = uint->zero; /* EXEC mask */
1764 pos_args[0][2] = uint->zero; /* last export? */
1765 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1766 pos_args[0][4] = uint->zero; /* COMPR flag */
1767 pos_args[0][5] = base->zero; /* X */
1768 pos_args[0][6] = base->zero; /* Y */
1769 pos_args[0][7] = base->zero; /* Z */
1770 pos_args[0][8] = base->one; /* W */
1771 }
1772
1773 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1774 if (shader->selector->info.writes_psize ||
1775 shader->selector->info.writes_edgeflag ||
1776 shader->selector->info.writes_viewport_index ||
1777 shader->selector->info.writes_layer) {
1778 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1779 shader->selector->info.writes_psize |
1780 (shader->selector->info.writes_edgeflag << 1) |
1781 (shader->selector->info.writes_layer << 2) |
1782 (shader->selector->info.writes_viewport_index << 3));
1783 pos_args[1][1] = uint->zero; /* EXEC mask */
1784 pos_args[1][2] = uint->zero; /* last export? */
1785 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1786 pos_args[1][4] = uint->zero; /* COMPR flag */
1787 pos_args[1][5] = base->zero; /* X */
1788 pos_args[1][6] = base->zero; /* Y */
1789 pos_args[1][7] = base->zero; /* Z */
1790 pos_args[1][8] = base->zero; /* W */
1791
1792 if (shader->selector->info.writes_psize)
1793 pos_args[1][5] = psize_value;
1794
1795 if (shader->selector->info.writes_edgeflag) {
1796 /* The output is a float, but the hw expects an integer
1797 * with the first bit containing the edge flag. */
1798 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1799 edgeflag_value,
1800 bld_base->uint_bld.elem_type, "");
1801 edgeflag_value = lp_build_min(&bld_base->int_bld,
1802 edgeflag_value,
1803 bld_base->int_bld.one);
1804
1805 /* The LLVM intrinsic expects a float. */
1806 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1807 edgeflag_value,
1808 base->elem_type, "");
1809 }
1810
1811 if (shader->selector->info.writes_layer)
1812 pos_args[1][7] = layer_value;
1813
1814 if (shader->selector->info.writes_viewport_index)
1815 pos_args[1][8] = viewport_index_value;
1816 }
1817
1818 for (i = 0; i < 4; i++)
1819 if (pos_args[i][0])
1820 shader->nr_pos_exports++;
1821
1822 pos_idx = 0;
1823 for (i = 0; i < 4; i++) {
1824 if (!pos_args[i][0])
1825 continue;
1826
1827 /* Specify the target we are exporting */
1828 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1829
1830 if (pos_idx == shader->nr_pos_exports)
1831 /* Specify that this is the last export */
1832 pos_args[i][2] = uint->one;
1833
1834 lp_build_intrinsic(base->gallivm->builder,
1835 "llvm.SI.export",
1836 LLVMVoidTypeInContext(base->gallivm->context),
1837 pos_args[i], 9, 0);
1838 }
1839 }
1840
1841 /* This only writes the tessellation factor levels. */
1842 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
1843 {
1844 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1845 struct gallivm_state *gallivm = bld_base->base.gallivm;
1846 struct si_shader *shader = si_shader_ctx->shader;
1847 unsigned tess_inner_index, tess_outer_index;
1848 LLVMValueRef lds_base, lds_inner, lds_outer;
1849 LLVMValueRef tf_base, rel_patch_id, byteoffset, buffer, rw_buffers;
1850 LLVMValueRef out[6], vec0, vec1, invocation_id;
1851 unsigned stride, outer_comps, inner_comps, i;
1852 struct lp_build_if_state if_ctx;
1853
1854 invocation_id = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1855
1856 /* Do this only for invocation 0, because the tess levels are per-patch,
1857 * not per-vertex.
1858 *
1859 * This can't jump, because invocation 0 executes this. It should
1860 * at least mask out the loads and stores for other invocations.
1861 */
1862 lp_build_if(&if_ctx, gallivm,
1863 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
1864 invocation_id, bld_base->uint_bld.zero, ""));
1865
1866 /* Determine the layout of one tess factor element in the buffer. */
1867 switch (shader->key.tcs.prim_mode) {
1868 case PIPE_PRIM_LINES:
1869 stride = 2; /* 2 dwords, 1 vec2 store */
1870 outer_comps = 2;
1871 inner_comps = 0;
1872 break;
1873 case PIPE_PRIM_TRIANGLES:
1874 stride = 4; /* 4 dwords, 1 vec4 store */
1875 outer_comps = 3;
1876 inner_comps = 1;
1877 break;
1878 case PIPE_PRIM_QUADS:
1879 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
1880 outer_comps = 4;
1881 inner_comps = 2;
1882 break;
1883 default:
1884 assert(0);
1885 return;
1886 }
1887
1888 /* Load tess_inner and tess_outer from LDS.
1889 * Any invocation can write them, so we can't get them from a temporary.
1890 */
1891 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
1892 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
1893
1894 lds_base = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1895 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
1896 lp_build_const_int32(gallivm,
1897 tess_inner_index * 4), "");
1898 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
1899 lp_build_const_int32(gallivm,
1900 tess_outer_index * 4), "");
1901
1902 for (i = 0; i < outer_comps; i++)
1903 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
1904 for (i = 0; i < inner_comps; i++)
1905 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
1906
1907 /* Convert the outputs to vectors for stores. */
1908 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
1909 vec1 = NULL;
1910
1911 if (stride > 4)
1912 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
1913
1914 /* Get the buffer. */
1915 rw_buffers = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1916 SI_PARAM_RW_BUFFERS);
1917 buffer = build_indexed_load_const(si_shader_ctx, rw_buffers,
1918 lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR));
1919
1920 /* Get the offset. */
1921 tf_base = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1922 SI_PARAM_TESS_FACTOR_OFFSET);
1923 rel_patch_id = get_rel_patch_id(si_shader_ctx);
1924 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
1925 lp_build_const_int32(gallivm, 4 * stride), "");
1926
1927 /* Store the outputs. */
1928 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec0,
1929 MIN2(stride, 4), byteoffset, tf_base, 0);
1930 if (vec1)
1931 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec1,
1932 stride - 4, byteoffset, tf_base, 16);
1933 lp_build_endif(&if_ctx);
1934 }
1935
1936 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context * bld_base)
1937 {
1938 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1939 struct si_shader *shader = si_shader_ctx->shader;
1940 struct tgsi_shader_info *info = &shader->selector->info;
1941 struct gallivm_state *gallivm = bld_base->base.gallivm;
1942 unsigned i, chan;
1943 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1944 si_shader_ctx->param_rel_auto_id);
1945 LLVMValueRef vertex_dw_stride =
1946 unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
1947 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
1948 vertex_dw_stride, "");
1949
1950 /* Write outputs to LDS. The next shader (TCS aka HS) will read
1951 * its inputs from it. */
1952 for (i = 0; i < info->num_outputs; i++) {
1953 LLVMValueRef *out_ptr = si_shader_ctx->radeon_bld.soa.outputs[i];
1954 unsigned name = info->output_semantic_name[i];
1955 unsigned index = info->output_semantic_index[i];
1956 int param = si_shader_io_get_unique_index(name, index);
1957 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
1958 lp_build_const_int32(gallivm, param * 4), "");
1959
1960 for (chan = 0; chan < 4; chan++) {
1961 lds_store(bld_base, chan, dw_addr,
1962 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
1963 }
1964 }
1965 }
1966
1967 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1968 {
1969 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1970 struct gallivm_state *gallivm = bld_base->base.gallivm;
1971 struct si_shader *es = si_shader_ctx->shader;
1972 struct tgsi_shader_info *info = &es->selector->info;
1973 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1974 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1975 si_shader_ctx->param_es2gs_offset);
1976 uint64_t enabled_outputs = si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL ?
1977 es->key.tes.es_enabled_outputs :
1978 es->key.vs.es_enabled_outputs;
1979 unsigned chan;
1980 int i;
1981
1982 for (i = 0; i < info->num_outputs; i++) {
1983 LLVMValueRef *out_ptr =
1984 si_shader_ctx->radeon_bld.soa.outputs[i];
1985 int param_index;
1986
1987 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
1988 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
1989 continue;
1990
1991 param_index = get_param_index(info->output_semantic_name[i],
1992 info->output_semantic_index[i],
1993 enabled_outputs);
1994 if (param_index < 0)
1995 continue;
1996
1997 for (chan = 0; chan < 4; chan++) {
1998 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1999 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2000
2001 build_tbuffer_store(si_shader_ctx,
2002 si_shader_ctx->esgs_ring,
2003 out_val, 1,
2004 LLVMGetUndef(i32), soffset,
2005 (4 * param_index + chan) * 4,
2006 V_008F0C_BUF_DATA_FORMAT_32,
2007 V_008F0C_BUF_NUM_FORMAT_UINT,
2008 0, 0, 1, 1, 0);
2009 }
2010 }
2011 }
2012
2013 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2014 {
2015 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2016 struct gallivm_state *gallivm = bld_base->base.gallivm;
2017 LLVMValueRef args[2];
2018
2019 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2020 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2021 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2022 LLVMVoidTypeInContext(gallivm->context), args, 2,
2023 LLVMNoUnwindAttribute);
2024 }
2025
2026 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
2027 {
2028 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2029 struct gallivm_state *gallivm = bld_base->base.gallivm;
2030 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
2031 struct si_shader_output_values *outputs = NULL;
2032 int i,j;
2033
2034 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2035
2036 for (i = 0; i < info->num_outputs; i++) {
2037 outputs[i].name = info->output_semantic_name[i];
2038 outputs[i].sid = info->output_semantic_index[i];
2039
2040 for (j = 0; j < 4; j++)
2041 outputs[i].values[j] =
2042 LLVMBuildLoad(gallivm->builder,
2043 si_shader_ctx->radeon_bld.soa.outputs[i][j],
2044 "");
2045 }
2046
2047 /* Export PrimitiveID when PS needs it. */
2048 if (si_vs_exports_prim_id(si_shader_ctx->shader)) {
2049 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2050 outputs[i].sid = 0;
2051 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2052 get_primitive_id(bld_base, 0));
2053 outputs[i].values[1] = bld_base->base.undef;
2054 outputs[i].values[2] = bld_base->base.undef;
2055 outputs[i].values[3] = bld_base->base.undef;
2056 i++;
2057 }
2058
2059 si_llvm_export_vs(bld_base, outputs, i);
2060 FREE(outputs);
2061 }
2062
2063 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
2064 {
2065 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
2066 struct si_shader * shader = si_shader_ctx->shader;
2067 struct lp_build_context * base = &bld_base->base;
2068 struct lp_build_context * uint = &bld_base->uint_bld;
2069 struct tgsi_shader_info *info = &shader->selector->info;
2070 LLVMValueRef args[9];
2071 LLVMValueRef last_args[9] = { 0 };
2072 int depth_index = -1, stencil_index = -1, samplemask_index = -1;
2073 int i;
2074
2075 for (i = 0; i < info->num_outputs; i++) {
2076 unsigned semantic_name = info->output_semantic_name[i];
2077 unsigned semantic_index = info->output_semantic_index[i];
2078 unsigned target;
2079 LLVMValueRef alpha_ptr;
2080
2081 /* Select the correct target */
2082 switch (semantic_name) {
2083 case TGSI_SEMANTIC_POSITION:
2084 depth_index = i;
2085 continue;
2086 case TGSI_SEMANTIC_STENCIL:
2087 stencil_index = i;
2088 continue;
2089 case TGSI_SEMANTIC_SAMPLEMASK:
2090 samplemask_index = i;
2091 continue;
2092 case TGSI_SEMANTIC_COLOR:
2093 target = V_008DFC_SQ_EXP_MRT + semantic_index;
2094 alpha_ptr = si_shader_ctx->radeon_bld.soa.outputs[i][3];
2095
2096 if (si_shader_ctx->shader->key.ps.alpha_to_one)
2097 LLVMBuildStore(base->gallivm->builder,
2098 base->one, alpha_ptr);
2099
2100 if (semantic_index == 0 &&
2101 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
2102 si_alpha_test(bld_base, alpha_ptr);
2103
2104 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
2105 si_scale_alpha_by_sample_mask(bld_base, alpha_ptr);
2106 break;
2107 default:
2108 target = 0;
2109 fprintf(stderr,
2110 "Warning: SI unhandled fs output type:%d\n",
2111 semantic_name);
2112 }
2113
2114 si_llvm_init_export_args_load(bld_base,
2115 si_shader_ctx->radeon_bld.soa.outputs[i],
2116 target, args);
2117
2118 if (semantic_name == TGSI_SEMANTIC_COLOR) {
2119 /* If there is an export instruction waiting to be emitted, do so now. */
2120 if (last_args[0]) {
2121 lp_build_intrinsic(base->gallivm->builder,
2122 "llvm.SI.export",
2123 LLVMVoidTypeInContext(base->gallivm->context),
2124 last_args, 9, 0);
2125 }
2126
2127 /* This instruction will be emitted at the end of the shader. */
2128 memcpy(last_args, args, sizeof(args));
2129
2130 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
2131 if (shader->selector->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
2132 semantic_index == 0 &&
2133 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
2134 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
2135 si_llvm_init_export_args_load(bld_base,
2136 si_shader_ctx->radeon_bld.soa.outputs[i],
2137 V_008DFC_SQ_EXP_MRT + c, args);
2138 lp_build_intrinsic(base->gallivm->builder,
2139 "llvm.SI.export",
2140 LLVMVoidTypeInContext(base->gallivm->context),
2141 args, 9, 0);
2142 }
2143 }
2144 } else {
2145 lp_build_intrinsic(base->gallivm->builder,
2146 "llvm.SI.export",
2147 LLVMVoidTypeInContext(base->gallivm->context),
2148 args, 9, 0);
2149 }
2150 }
2151
2152 if (depth_index >= 0 || stencil_index >= 0 || samplemask_index >= 0) {
2153 LLVMValueRef out_ptr;
2154 unsigned mask = 0;
2155
2156 /* Specify the target we are exporting */
2157 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2158
2159 args[5] = base->zero; /* R, depth */
2160 args[6] = base->zero; /* G, stencil test value[0:7], stencil op value[8:15] */
2161 args[7] = base->zero; /* B, sample mask */
2162 args[8] = base->zero; /* A, alpha to mask */
2163
2164 if (depth_index >= 0) {
2165 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
2166 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2167 mask |= 0x1;
2168 si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2169 }
2170
2171 if (stencil_index >= 0) {
2172 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
2173 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2174 mask |= 0x2;
2175 si_shader_ctx->shader->db_shader_control |=
2176 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
2177 }
2178
2179 if (samplemask_index >= 0) {
2180 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[samplemask_index][0];
2181 args[7] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2182 mask |= 0x4;
2183 si_shader_ctx->shader->db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(1);
2184 }
2185
2186 /* SI (except OLAND) has a bug that it only looks
2187 * at the X writemask component. */
2188 if (si_shader_ctx->screen->b.chip_class == SI &&
2189 si_shader_ctx->screen->b.family != CHIP_OLAND)
2190 mask |= 0x1;
2191
2192 if (samplemask_index >= 0)
2193 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
2194 else if (stencil_index >= 0)
2195 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
2196 else
2197 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
2198
2199 /* Specify which components to enable */
2200 args[0] = lp_build_const_int32(base->gallivm, mask);
2201
2202 args[1] =
2203 args[2] =
2204 args[4] = uint->zero;
2205
2206 if (last_args[0])
2207 lp_build_intrinsic(base->gallivm->builder,
2208 "llvm.SI.export",
2209 LLVMVoidTypeInContext(base->gallivm->context),
2210 args, 9, 0);
2211 else
2212 memcpy(last_args, args, sizeof(args));
2213 }
2214
2215 if (!last_args[0]) {
2216 /* Specify which components to enable */
2217 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
2218
2219 /* Specify the target we are exporting */
2220 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
2221
2222 /* Set COMPR flag to zero to export data as 32-bit */
2223 last_args[4] = uint->zero;
2224
2225 /* dummy bits */
2226 last_args[5]= uint->zero;
2227 last_args[6]= uint->zero;
2228 last_args[7]= uint->zero;
2229 last_args[8]= uint->zero;
2230 }
2231
2232 /* Specify whether the EXEC mask represents the valid mask */
2233 last_args[1] = uint->one;
2234
2235 /* Specify that this is the last export */
2236 last_args[2] = lp_build_const_int32(base->gallivm, 1);
2237
2238 lp_build_intrinsic(base->gallivm->builder,
2239 "llvm.SI.export",
2240 LLVMVoidTypeInContext(base->gallivm->context),
2241 last_args, 9, 0);
2242 }
2243
2244 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2245 struct lp_build_tgsi_context * bld_base,
2246 struct lp_build_emit_data * emit_data);
2247
2248 static bool tgsi_is_shadow_sampler(unsigned target)
2249 {
2250 return target == TGSI_TEXTURE_SHADOW1D ||
2251 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2252 target == TGSI_TEXTURE_SHADOW2D ||
2253 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2254 target == TGSI_TEXTURE_SHADOWCUBE ||
2255 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2256 target == TGSI_TEXTURE_SHADOWRECT;
2257 }
2258
2259 static const struct lp_build_tgsi_action tex_action;
2260
2261 static void tex_fetch_args(
2262 struct lp_build_tgsi_context * bld_base,
2263 struct lp_build_emit_data * emit_data)
2264 {
2265 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2266 struct gallivm_state *gallivm = bld_base->base.gallivm;
2267 const struct tgsi_full_instruction * inst = emit_data->inst;
2268 unsigned opcode = inst->Instruction.Opcode;
2269 unsigned target = inst->Texture.Texture;
2270 LLVMValueRef coords[5], derivs[6];
2271 LLVMValueRef address[16];
2272 int ref_pos;
2273 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
2274 unsigned count = 0;
2275 unsigned chan;
2276 unsigned sampler_src;
2277 unsigned sampler_index;
2278 unsigned num_deriv_channels = 0;
2279 bool has_offset = HAVE_LLVM >= 0x0305 ? inst->Texture.NumOffsets > 0 : false;
2280 LLVMValueRef res_ptr, samp_ptr;
2281
2282 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
2283 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
2284
2285 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
2286 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
2287 LLVMValueRef ind_index;
2288
2289 ind_index = get_indirect_index(si_shader_ctx, &reg->Indirect, reg->Register.Index);
2290
2291 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2292 res_ptr = build_indexed_load_const(si_shader_ctx, res_ptr, ind_index);
2293
2294 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2295 samp_ptr = build_indexed_load_const(si_shader_ctx, samp_ptr, ind_index);
2296 } else {
2297 res_ptr = si_shader_ctx->resources[sampler_index];
2298 samp_ptr = si_shader_ctx->samplers[sampler_index];
2299 }
2300
2301 if (target == TGSI_TEXTURE_BUFFER) {
2302 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
2303 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
2304 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
2305 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
2306
2307 /* Bitcast and truncate v8i32 to v16i8. */
2308 LLVMValueRef res = res_ptr;
2309 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
2310 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
2311 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
2312
2313 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
2314 emit_data->args[0] = res;
2315 emit_data->args[1] = bld_base->uint_bld.zero;
2316 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
2317 emit_data->arg_count = 3;
2318 return;
2319 }
2320
2321 /* Fetch and project texture coordinates */
2322 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
2323 for (chan = 0; chan < 3; chan++ ) {
2324 coords[chan] = lp_build_emit_fetch(bld_base,
2325 emit_data->inst, 0,
2326 chan);
2327 if (opcode == TGSI_OPCODE_TXP)
2328 coords[chan] = lp_build_emit_llvm_binary(bld_base,
2329 TGSI_OPCODE_DIV,
2330 coords[chan],
2331 coords[3]);
2332 }
2333
2334 if (opcode == TGSI_OPCODE_TXP)
2335 coords[3] = bld_base->base.one;
2336
2337 /* Pack offsets. */
2338 if (has_offset && opcode != TGSI_OPCODE_TXF) {
2339 /* The offsets are six-bit signed integers packed like this:
2340 * X=[5:0], Y=[13:8], and Z=[21:16].
2341 */
2342 LLVMValueRef offset[3], pack;
2343
2344 assert(inst->Texture.NumOffsets == 1);
2345
2346 for (chan = 0; chan < 3; chan++) {
2347 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
2348 emit_data->inst, 0, chan);
2349 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
2350 lp_build_const_int32(gallivm, 0x3f), "");
2351 if (chan)
2352 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
2353 lp_build_const_int32(gallivm, chan*8), "");
2354 }
2355
2356 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
2357 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
2358 address[count++] = pack;
2359 }
2360
2361 /* Pack LOD bias value */
2362 if (opcode == TGSI_OPCODE_TXB)
2363 address[count++] = coords[3];
2364 if (opcode == TGSI_OPCODE_TXB2)
2365 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2366
2367 /* Pack depth comparison value */
2368 if (tgsi_is_shadow_sampler(target) && opcode != TGSI_OPCODE_LODQ) {
2369 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2370 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2371 } else {
2372 assert(ref_pos >= 0);
2373 address[count++] = coords[ref_pos];
2374 }
2375 }
2376
2377 /* Pack user derivatives */
2378 if (opcode == TGSI_OPCODE_TXD) {
2379 int param, num_src_deriv_channels;
2380
2381 switch (target) {
2382 case TGSI_TEXTURE_3D:
2383 num_src_deriv_channels = 3;
2384 num_deriv_channels = 3;
2385 break;
2386 case TGSI_TEXTURE_2D:
2387 case TGSI_TEXTURE_SHADOW2D:
2388 case TGSI_TEXTURE_RECT:
2389 case TGSI_TEXTURE_SHADOWRECT:
2390 case TGSI_TEXTURE_2D_ARRAY:
2391 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2392 num_src_deriv_channels = 2;
2393 num_deriv_channels = 2;
2394 break;
2395 case TGSI_TEXTURE_CUBE:
2396 case TGSI_TEXTURE_SHADOWCUBE:
2397 case TGSI_TEXTURE_CUBE_ARRAY:
2398 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
2399 /* Cube derivatives will be converted to 2D. */
2400 num_src_deriv_channels = 3;
2401 num_deriv_channels = 2;
2402 break;
2403 case TGSI_TEXTURE_1D:
2404 case TGSI_TEXTURE_SHADOW1D:
2405 case TGSI_TEXTURE_1D_ARRAY:
2406 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2407 num_src_deriv_channels = 1;
2408 num_deriv_channels = 1;
2409 break;
2410 default:
2411 assert(0); /* no other targets are valid here */
2412 }
2413
2414 for (param = 0; param < 2; param++)
2415 for (chan = 0; chan < num_src_deriv_channels; chan++)
2416 derivs[param * num_src_deriv_channels + chan] =
2417 lp_build_emit_fetch(bld_base, inst, param+1, chan);
2418 }
2419
2420 if (target == TGSI_TEXTURE_CUBE ||
2421 target == TGSI_TEXTURE_CUBE_ARRAY ||
2422 target == TGSI_TEXTURE_SHADOWCUBE ||
2423 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2424 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
2425
2426 if (opcode == TGSI_OPCODE_TXD)
2427 for (int i = 0; i < num_deriv_channels * 2; i++)
2428 address[count++] = derivs[i];
2429
2430 /* Pack texture coordinates */
2431 address[count++] = coords[0];
2432 if (num_coords > 1)
2433 address[count++] = coords[1];
2434 if (num_coords > 2)
2435 address[count++] = coords[2];
2436
2437 /* Pack LOD or sample index */
2438 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
2439 address[count++] = coords[3];
2440 else if (opcode == TGSI_OPCODE_TXL2)
2441 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2442
2443 if (count > 16) {
2444 assert(!"Cannot handle more than 16 texture address parameters");
2445 count = 16;
2446 }
2447
2448 for (chan = 0; chan < count; chan++ ) {
2449 address[chan] = LLVMBuildBitCast(gallivm->builder,
2450 address[chan],
2451 LLVMInt32TypeInContext(gallivm->context),
2452 "");
2453 }
2454
2455 /* Adjust the sample index according to FMASK.
2456 *
2457 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2458 * which is the identity mapping. Each nibble says which physical sample
2459 * should be fetched to get that sample.
2460 *
2461 * For example, 0x11111100 means there are only 2 samples stored and
2462 * the second sample covers 3/4 of the pixel. When reading samples 0
2463 * and 1, return physical sample 0 (determined by the first two 0s
2464 * in FMASK), otherwise return physical sample 1.
2465 *
2466 * The sample index should be adjusted as follows:
2467 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2468 */
2469 if (target == TGSI_TEXTURE_2D_MSAA ||
2470 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2471 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2472 struct lp_build_emit_data txf_emit_data = *emit_data;
2473 LLVMValueRef txf_address[4];
2474 unsigned txf_count = count;
2475 struct tgsi_full_instruction inst = {};
2476
2477 memcpy(txf_address, address, sizeof(txf_address));
2478
2479 if (target == TGSI_TEXTURE_2D_MSAA) {
2480 txf_address[2] = bld_base->uint_bld.zero;
2481 }
2482 txf_address[3] = bld_base->uint_bld.zero;
2483
2484 /* Pad to a power-of-two size. */
2485 while (txf_count < util_next_power_of_two(txf_count))
2486 txf_address[txf_count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
2487
2488 /* Read FMASK using TXF. */
2489 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
2490 inst.Texture.Texture = target == TGSI_TEXTURE_2D_MSAA ? TGSI_TEXTURE_2D : TGSI_TEXTURE_2D_ARRAY;
2491 txf_emit_data.inst = &inst;
2492 txf_emit_data.chan = 0;
2493 txf_emit_data.dst_type = LLVMVectorType(
2494 LLVMInt32TypeInContext(gallivm->context), 4);
2495 txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
2496 txf_emit_data.args[1] = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
2497 txf_emit_data.args[2] = lp_build_const_int32(gallivm, inst.Texture.Texture);
2498 txf_emit_data.arg_count = 3;
2499
2500 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
2501
2502 /* Initialize some constants. */
2503 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
2504 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
2505
2506 /* Apply the formula. */
2507 LLVMValueRef fmask =
2508 LLVMBuildExtractElement(gallivm->builder,
2509 txf_emit_data.output[0],
2510 uint_bld->zero, "");
2511
2512 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
2513
2514 LLVMValueRef sample_index4 =
2515 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
2516
2517 LLVMValueRef shifted_fmask =
2518 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
2519
2520 LLVMValueRef final_sample =
2521 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
2522
2523 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2524 * resource descriptor is 0 (invalid),
2525 */
2526 LLVMValueRef fmask_desc =
2527 LLVMBuildBitCast(gallivm->builder,
2528 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index],
2529 LLVMVectorType(uint_bld->elem_type, 8), "");
2530
2531 LLVMValueRef fmask_word1 =
2532 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
2533 uint_bld->one, "");
2534
2535 LLVMValueRef word1_is_nonzero =
2536 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
2537 fmask_word1, uint_bld->zero, "");
2538
2539 /* Replace the MSAA sample index. */
2540 address[sample_chan] =
2541 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
2542 final_sample, address[sample_chan], "");
2543 }
2544
2545 /* Resource */
2546 emit_data->args[1] = res_ptr;
2547
2548 if (opcode == TGSI_OPCODE_TXF) {
2549 /* add tex offsets */
2550 if (inst->Texture.NumOffsets) {
2551 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2552 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
2553 const struct tgsi_texture_offset * off = inst->TexOffsets;
2554
2555 assert(inst->Texture.NumOffsets == 1);
2556
2557 switch (target) {
2558 case TGSI_TEXTURE_3D:
2559 address[2] = lp_build_add(uint_bld, address[2],
2560 bld->immediates[off->Index][off->SwizzleZ]);
2561 /* fall through */
2562 case TGSI_TEXTURE_2D:
2563 case TGSI_TEXTURE_SHADOW2D:
2564 case TGSI_TEXTURE_RECT:
2565 case TGSI_TEXTURE_SHADOWRECT:
2566 case TGSI_TEXTURE_2D_ARRAY:
2567 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2568 address[1] =
2569 lp_build_add(uint_bld, address[1],
2570 bld->immediates[off->Index][off->SwizzleY]);
2571 /* fall through */
2572 case TGSI_TEXTURE_1D:
2573 case TGSI_TEXTURE_SHADOW1D:
2574 case TGSI_TEXTURE_1D_ARRAY:
2575 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2576 address[0] =
2577 lp_build_add(uint_bld, address[0],
2578 bld->immediates[off->Index][off->SwizzleX]);
2579 break;
2580 /* texture offsets do not apply to other texture targets */
2581 }
2582 }
2583
2584 emit_data->args[2] = lp_build_const_int32(gallivm, target);
2585 emit_data->arg_count = 3;
2586
2587 emit_data->dst_type = LLVMVectorType(
2588 LLVMInt32TypeInContext(gallivm->context),
2589 4);
2590 } else if (opcode == TGSI_OPCODE_TG4 ||
2591 opcode == TGSI_OPCODE_LODQ ||
2592 has_offset) {
2593 unsigned is_array = target == TGSI_TEXTURE_1D_ARRAY ||
2594 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2595 target == TGSI_TEXTURE_2D_ARRAY ||
2596 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2597 target == TGSI_TEXTURE_CUBE_ARRAY ||
2598 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY;
2599 unsigned is_rect = target == TGSI_TEXTURE_RECT;
2600 unsigned dmask = 0xf;
2601
2602 if (opcode == TGSI_OPCODE_TG4) {
2603 unsigned gather_comp = 0;
2604
2605 /* DMASK was repurposed for GATHER4. 4 components are always
2606 * returned and DMASK works like a swizzle - it selects
2607 * the component to fetch. The only valid DMASK values are
2608 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2609 * (red,red,red,red) etc.) The ISA document doesn't mention
2610 * this.
2611 */
2612
2613 /* Get the component index from src1.x for Gather4. */
2614 if (!tgsi_is_shadow_sampler(target)) {
2615 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
2616 LLVMValueRef comp_imm;
2617 struct tgsi_src_register src1 = inst->Src[1].Register;
2618
2619 assert(src1.File == TGSI_FILE_IMMEDIATE);
2620
2621 comp_imm = imms[src1.Index][src1.SwizzleX];
2622 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
2623 gather_comp = CLAMP(gather_comp, 0, 3);
2624 }
2625
2626 dmask = 1 << gather_comp;
2627 }
2628
2629 emit_data->args[2] = samp_ptr;
2630 emit_data->args[3] = lp_build_const_int32(gallivm, dmask);
2631 emit_data->args[4] = lp_build_const_int32(gallivm, is_rect); /* unorm */
2632 emit_data->args[5] = lp_build_const_int32(gallivm, 0); /* r128 */
2633 emit_data->args[6] = lp_build_const_int32(gallivm, is_array); /* da */
2634 emit_data->args[7] = lp_build_const_int32(gallivm, 0); /* glc */
2635 emit_data->args[8] = lp_build_const_int32(gallivm, 0); /* slc */
2636 emit_data->args[9] = lp_build_const_int32(gallivm, 0); /* tfe */
2637 emit_data->args[10] = lp_build_const_int32(gallivm, 0); /* lwe */
2638
2639 emit_data->arg_count = 11;
2640
2641 emit_data->dst_type = LLVMVectorType(
2642 LLVMFloatTypeInContext(gallivm->context),
2643 4);
2644 } else {
2645 emit_data->args[2] = samp_ptr;
2646 emit_data->args[3] = lp_build_const_int32(gallivm, target);
2647 emit_data->arg_count = 4;
2648
2649 emit_data->dst_type = LLVMVectorType(
2650 LLVMFloatTypeInContext(gallivm->context),
2651 4);
2652 }
2653
2654 /* The fetch opcode has been converted to a 2D array fetch.
2655 * This simplifies the LLVM backend. */
2656 if (target == TGSI_TEXTURE_CUBE_ARRAY)
2657 target = TGSI_TEXTURE_2D_ARRAY;
2658 else if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2659 target = TGSI_TEXTURE_SHADOW2D_ARRAY;
2660
2661 /* Pad to power of two vector */
2662 while (count < util_next_power_of_two(count))
2663 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
2664
2665 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
2666 }
2667
2668 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2669 struct lp_build_tgsi_context * bld_base,
2670 struct lp_build_emit_data * emit_data)
2671 {
2672 struct lp_build_context * base = &bld_base->base;
2673 unsigned opcode = emit_data->inst->Instruction.Opcode;
2674 unsigned target = emit_data->inst->Texture.Texture;
2675 char intr_name[127];
2676 bool has_offset = HAVE_LLVM >= 0x0305 ?
2677 emit_data->inst->Texture.NumOffsets > 0 : false;
2678
2679 if (target == TGSI_TEXTURE_BUFFER) {
2680 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2681 base->gallivm->builder,
2682 "llvm.SI.vs.load.input", emit_data->dst_type,
2683 emit_data->args, emit_data->arg_count,
2684 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2685 return;
2686 }
2687
2688 if (opcode == TGSI_OPCODE_TG4 ||
2689 opcode == TGSI_OPCODE_LODQ ||
2690 (opcode != TGSI_OPCODE_TXF && has_offset)) {
2691 bool is_shadow = tgsi_is_shadow_sampler(target);
2692 const char *name = "llvm.SI.image.sample";
2693 const char *infix = "";
2694
2695 switch (opcode) {
2696 case TGSI_OPCODE_TEX:
2697 case TGSI_OPCODE_TEX2:
2698 case TGSI_OPCODE_TXP:
2699 break;
2700 case TGSI_OPCODE_TXB:
2701 case TGSI_OPCODE_TXB2:
2702 infix = ".b";
2703 break;
2704 case TGSI_OPCODE_TXL:
2705 case TGSI_OPCODE_TXL2:
2706 infix = ".l";
2707 break;
2708 case TGSI_OPCODE_TXD:
2709 infix = ".d";
2710 break;
2711 case TGSI_OPCODE_TG4:
2712 name = "llvm.SI.gather4";
2713 break;
2714 case TGSI_OPCODE_LODQ:
2715 name = "llvm.SI.getlod";
2716 is_shadow = false;
2717 has_offset = false;
2718 break;
2719 default:
2720 assert(0);
2721 return;
2722 }
2723
2724 /* Add the type and suffixes .c, .o if needed. */
2725 sprintf(intr_name, "%s%s%s%s.v%ui32", name,
2726 is_shadow ? ".c" : "", infix, has_offset ? ".o" : "",
2727 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2728
2729 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2730 base->gallivm->builder, intr_name, emit_data->dst_type,
2731 emit_data->args, emit_data->arg_count,
2732 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2733 } else {
2734 LLVMTypeRef i8, v16i8, v32i8;
2735 const char *name;
2736
2737 switch (opcode) {
2738 case TGSI_OPCODE_TEX:
2739 case TGSI_OPCODE_TEX2:
2740 case TGSI_OPCODE_TXP:
2741 name = "llvm.SI.sample";
2742 break;
2743 case TGSI_OPCODE_TXB:
2744 case TGSI_OPCODE_TXB2:
2745 name = "llvm.SI.sampleb";
2746 break;
2747 case TGSI_OPCODE_TXD:
2748 name = "llvm.SI.sampled";
2749 break;
2750 case TGSI_OPCODE_TXF:
2751 name = "llvm.SI.imageload";
2752 break;
2753 case TGSI_OPCODE_TXL:
2754 case TGSI_OPCODE_TXL2:
2755 name = "llvm.SI.samplel";
2756 break;
2757 default:
2758 assert(0);
2759 return;
2760 }
2761
2762 i8 = LLVMInt8TypeInContext(base->gallivm->context);
2763 v16i8 = LLVMVectorType(i8, 16);
2764 v32i8 = LLVMVectorType(i8, 32);
2765
2766 emit_data->args[1] = LLVMBuildBitCast(base->gallivm->builder,
2767 emit_data->args[1], v32i8, "");
2768 if (opcode != TGSI_OPCODE_TXF) {
2769 emit_data->args[2] = LLVMBuildBitCast(base->gallivm->builder,
2770 emit_data->args[2], v16i8, "");
2771 }
2772
2773 sprintf(intr_name, "%s.v%ui32", name,
2774 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2775
2776 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2777 base->gallivm->builder, intr_name, emit_data->dst_type,
2778 emit_data->args, emit_data->arg_count,
2779 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2780 }
2781 }
2782
2783 static void txq_fetch_args(
2784 struct lp_build_tgsi_context * bld_base,
2785 struct lp_build_emit_data * emit_data)
2786 {
2787 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2788 const struct tgsi_full_instruction *inst = emit_data->inst;
2789 struct gallivm_state *gallivm = bld_base->base.gallivm;
2790 LLVMBuilderRef builder = gallivm->builder;
2791 unsigned target = inst->Texture.Texture;
2792 LLVMValueRef res_ptr;
2793
2794 if (inst->Src[1].Register.Indirect) {
2795 const struct tgsi_full_src_register *reg = &inst->Src[1];
2796 LLVMValueRef ind_index;
2797
2798 ind_index = get_indirect_index(si_shader_ctx, &reg->Indirect, reg->Register.Index);
2799
2800 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2801 res_ptr = build_indexed_load_const(si_shader_ctx, res_ptr,
2802 ind_index);
2803 } else
2804 res_ptr = si_shader_ctx->resources[inst->Src[1].Register.Index];
2805
2806 if (target == TGSI_TEXTURE_BUFFER) {
2807 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2808 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2809
2810 /* Read the size from the buffer descriptor directly. */
2811 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2812 LLVMValueRef size = LLVMBuildExtractElement(builder, res,
2813 lp_build_const_int32(gallivm, 6), "");
2814
2815 if (si_shader_ctx->screen->b.chip_class >= VI) {
2816 /* On VI, the descriptor contains the size in bytes,
2817 * but TXQ must return the size in elements.
2818 * The stride is always non-zero for resources using TXQ.
2819 */
2820 LLVMValueRef stride =
2821 LLVMBuildExtractElement(builder, res,
2822 lp_build_const_int32(gallivm, 5), "");
2823 stride = LLVMBuildLShr(builder, stride,
2824 lp_build_const_int32(gallivm, 16), "");
2825 stride = LLVMBuildAnd(builder, stride,
2826 lp_build_const_int32(gallivm, 0x3FFF), "");
2827
2828 size = LLVMBuildUDiv(builder, size, stride, "");
2829 }
2830
2831 emit_data->args[0] = size;
2832 return;
2833 }
2834
2835 /* Mip level */
2836 emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2837
2838 /* Resource */
2839 emit_data->args[1] = res_ptr;
2840
2841 /* Texture target */
2842 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2843 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2844 target = TGSI_TEXTURE_2D_ARRAY;
2845
2846 emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
2847 target);
2848
2849 emit_data->arg_count = 3;
2850
2851 emit_data->dst_type = LLVMVectorType(
2852 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
2853 4);
2854 }
2855
2856 static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
2857 struct lp_build_tgsi_context * bld_base,
2858 struct lp_build_emit_data * emit_data)
2859 {
2860 unsigned target = emit_data->inst->Texture.Texture;
2861
2862 if (target == TGSI_TEXTURE_BUFFER) {
2863 /* Just return the buffer size. */
2864 emit_data->output[emit_data->chan] = emit_data->args[0];
2865 return;
2866 }
2867
2868 build_tgsi_intrinsic_nomem(action, bld_base, emit_data);
2869
2870 /* Divide the number of layers by 6 to get the number of cubes. */
2871 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2872 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2873 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2874 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2875 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2876
2877 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2878 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2879 z = LLVMBuildSDiv(builder, z, six, "");
2880
2881 emit_data->output[emit_data->chan] =
2882 LLVMBuildInsertElement(builder, v4, z, two, "");
2883 }
2884 }
2885
2886 /*
2887 * SI implements derivatives using the local data store (LDS)
2888 * All writes to the LDS happen in all executing threads at
2889 * the same time. TID is the Thread ID for the current
2890 * thread and is a value between 0 and 63, representing
2891 * the thread's position in the wavefront.
2892 *
2893 * For the pixel shader threads are grouped into quads of four pixels.
2894 * The TIDs of the pixels of a quad are:
2895 *
2896 * +------+------+
2897 * |4n + 0|4n + 1|
2898 * +------+------+
2899 * |4n + 2|4n + 3|
2900 * +------+------+
2901 *
2902 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
2903 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
2904 * the current pixel's column, and masking with 0xfffffffe yields the TID
2905 * of the left pixel of the current pixel's row.
2906 *
2907 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
2908 * adding 2 yields the TID of the pixel below the top pixel.
2909 */
2910 /* masks for thread ID. */
2911 #define TID_MASK_TOP_LEFT 0xfffffffc
2912 #define TID_MASK_TOP 0xfffffffd
2913 #define TID_MASK_LEFT 0xfffffffe
2914
2915 static void si_llvm_emit_ddxy(
2916 const struct lp_build_tgsi_action * action,
2917 struct lp_build_tgsi_context * bld_base,
2918 struct lp_build_emit_data * emit_data)
2919 {
2920 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2921 struct gallivm_state *gallivm = bld_base->base.gallivm;
2922 struct lp_build_context * base = &bld_base->base;
2923 const struct tgsi_full_instruction *inst = emit_data->inst;
2924 unsigned opcode = inst->Instruction.Opcode;
2925 LLVMValueRef indices[2];
2926 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2927 LLVMValueRef tl, trbl, result[4];
2928 LLVMTypeRef i32;
2929 unsigned swizzle[4];
2930 unsigned c;
2931 int idx;
2932 unsigned mask;
2933
2934 i32 = LLVMInt32TypeInContext(gallivm->context);
2935
2936 indices[0] = bld_base->uint_bld.zero;
2937 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2938 NULL, 0, LLVMReadNoneAttribute);
2939 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2940 indices, 2, "");
2941
2942 if (opcode == TGSI_OPCODE_DDX_FINE)
2943 mask = TID_MASK_LEFT;
2944 else if (opcode == TGSI_OPCODE_DDY_FINE)
2945 mask = TID_MASK_TOP;
2946 else
2947 mask = TID_MASK_TOP_LEFT;
2948
2949 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2950 lp_build_const_int32(gallivm, mask), "");
2951 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2952 indices, 2, "");
2953
2954 /* for DDX we want to next X pixel, DDY next Y pixel. */
2955 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
2956 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
2957 lp_build_const_int32(gallivm, idx), "");
2958 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2959 indices, 2, "");
2960
2961 for (c = 0; c < 4; ++c) {
2962 unsigned i;
2963
2964 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
2965 for (i = 0; i < c; ++i) {
2966 if (swizzle[i] == swizzle[c]) {
2967 result[c] = result[i];
2968 break;
2969 }
2970 }
2971 if (i != c)
2972 continue;
2973
2974 LLVMBuildStore(gallivm->builder,
2975 LLVMBuildBitCast(gallivm->builder,
2976 lp_build_emit_fetch(bld_base, inst, 0, c),
2977 i32, ""),
2978 store_ptr);
2979
2980 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
2981 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
2982
2983 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
2984 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
2985
2986 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
2987 }
2988
2989 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
2990 }
2991
2992 /*
2993 * this takes an I,J coordinate pair,
2994 * and works out the X and Y derivatives.
2995 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
2996 */
2997 static LLVMValueRef si_llvm_emit_ddxy_interp(
2998 struct lp_build_tgsi_context *bld_base,
2999 LLVMValueRef interp_ij)
3000 {
3001 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3002 struct gallivm_state *gallivm = bld_base->base.gallivm;
3003 struct lp_build_context *base = &bld_base->base;
3004 LLVMValueRef indices[2];
3005 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
3006 LLVMValueRef tl, tr, bl, result[4];
3007 LLVMTypeRef i32;
3008 unsigned c;
3009
3010 i32 = LLVMInt32TypeInContext(gallivm->context);
3011
3012 indices[0] = bld_base->uint_bld.zero;
3013 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
3014 NULL, 0, LLVMReadNoneAttribute);
3015 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3016 indices, 2, "");
3017
3018 temp = LLVMBuildAnd(gallivm->builder, indices[1],
3019 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
3020
3021 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
3022 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
3023
3024 indices[1] = temp;
3025 load_ptr_x = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3026 indices, 2, "");
3027
3028 indices[1] = temp2;
3029 load_ptr_y = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3030 indices, 2, "");
3031
3032 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
3033 lp_build_const_int32(gallivm, 1), "");
3034 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3035 indices, 2, "");
3036
3037 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
3038 lp_build_const_int32(gallivm, 2), "");
3039 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3040 indices, 2, "");
3041
3042 for (c = 0; c < 2; ++c) {
3043 LLVMValueRef store_val;
3044 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
3045
3046 store_val = LLVMBuildExtractElement(gallivm->builder,
3047 interp_ij, c_ll, "");
3048 LLVMBuildStore(gallivm->builder,
3049 store_val,
3050 store_ptr);
3051
3052 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
3053 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3054
3055 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
3056 tr = LLVMBuildBitCast(gallivm->builder, tr, base->elem_type, "");
3057
3058 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
3059
3060 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
3061 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3062
3063 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
3064 bl = LLVMBuildBitCast(gallivm->builder, bl, base->elem_type, "");
3065
3066 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
3067 }
3068
3069 return lp_build_gather_values(gallivm, result, 4);
3070 }
3071
3072 static void interp_fetch_args(
3073 struct lp_build_tgsi_context *bld_base,
3074 struct lp_build_emit_data *emit_data)
3075 {
3076 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3077 struct gallivm_state *gallivm = bld_base->base.gallivm;
3078 const struct tgsi_full_instruction *inst = emit_data->inst;
3079
3080 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3081 /* offset is in second src, first two channels */
3082 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3083 emit_data->inst, 1,
3084 0);
3085 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3086 emit_data->inst, 1,
3087 1);
3088 emit_data->arg_count = 2;
3089 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3090 LLVMValueRef sample_position;
3091 LLVMValueRef sample_id;
3092 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
3093
3094 /* fetch sample ID, then fetch its sample position,
3095 * and place into first two channels.
3096 */
3097 sample_id = lp_build_emit_fetch(bld_base,
3098 emit_data->inst, 1, 0);
3099 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
3100 LLVMInt32TypeInContext(gallivm->context),
3101 "");
3102 sample_position = load_sample_position(&si_shader_ctx->radeon_bld, sample_id);
3103
3104 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
3105 sample_position,
3106 lp_build_const_int32(gallivm, 0), "");
3107
3108 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
3109 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
3110 sample_position,
3111 lp_build_const_int32(gallivm, 1), "");
3112 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
3113 emit_data->arg_count = 2;
3114 }
3115 }
3116
3117 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3118 struct lp_build_tgsi_context *bld_base,
3119 struct lp_build_emit_data *emit_data)
3120 {
3121 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3122 struct si_shader *shader = si_shader_ctx->shader;
3123 struct gallivm_state *gallivm = bld_base->base.gallivm;
3124 LLVMValueRef interp_param;
3125 const struct tgsi_full_instruction *inst = emit_data->inst;
3126 const char *intr_name;
3127 int input_index;
3128 int chan;
3129 int i;
3130 LLVMValueRef attr_number;
3131 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
3132 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
3133 int interp_param_idx;
3134 unsigned location;
3135
3136 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
3137 input_index = inst->Src[0].Register.Index;
3138
3139 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3140 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3141 location = TGSI_INTERPOLATE_LOC_CENTER;
3142 else
3143 location = TGSI_INTERPOLATE_LOC_CENTROID;
3144
3145 interp_param_idx = lookup_interp_param_index(shader->ps_input_interpolate[input_index],
3146 location);
3147 if (interp_param_idx == -1)
3148 return;
3149 else if (interp_param_idx)
3150 interp_param = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, interp_param_idx);
3151 else
3152 interp_param = NULL;
3153
3154 attr_number = lp_build_const_int32(gallivm,
3155 shader->ps_input_param_offset[input_index]);
3156
3157 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3158 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3159 LLVMValueRef ij_out[2];
3160 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3161
3162 /*
3163 * take the I then J parameters, and the DDX/Y for it, and
3164 * calculate the IJ inputs for the interpolator.
3165 * temp1 = ddx * offset/sample.x + I;
3166 * interp_param.I = ddy * offset/sample.y + temp1;
3167 * temp1 = ddx * offset/sample.x + J;
3168 * interp_param.J = ddy * offset/sample.y + temp1;
3169 */
3170 for (i = 0; i < 2; i++) {
3171 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
3172 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
3173 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
3174 ddxy_out, ix_ll, "");
3175 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
3176 ddxy_out, iy_ll, "");
3177 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
3178 interp_param, ix_ll, "");
3179 LLVMValueRef temp1, temp2;
3180
3181 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
3182 LLVMFloatTypeInContext(gallivm->context), "");
3183
3184 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
3185
3186 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
3187
3188 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
3189
3190 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
3191
3192 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
3193 temp2,
3194 LLVMIntTypeInContext(gallivm->context, 32), "");
3195 }
3196 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
3197 }
3198
3199 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3200 for (chan = 0; chan < 2; chan++) {
3201 LLVMValueRef args[4];
3202 LLVMValueRef llvm_chan;
3203 unsigned schan;
3204
3205 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3206 llvm_chan = lp_build_const_int32(gallivm, schan);
3207
3208 args[0] = llvm_chan;
3209 args[1] = attr_number;
3210 args[2] = params;
3211 args[3] = interp_param;
3212
3213 emit_data->output[chan] =
3214 lp_build_intrinsic(gallivm->builder, intr_name,
3215 input_type, args, args[3] ? 4 : 3,
3216 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3217 }
3218 }
3219
3220 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
3221 struct lp_build_emit_data *emit_data)
3222 {
3223 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3224 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
3225 unsigned stream;
3226
3227 assert(src0.File == TGSI_FILE_IMMEDIATE);
3228
3229 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
3230 return stream;
3231 }
3232
3233 /* Emit one vertex from the geometry shader */
3234 static void si_llvm_emit_vertex(
3235 const struct lp_build_tgsi_action *action,
3236 struct lp_build_tgsi_context *bld_base,
3237 struct lp_build_emit_data *emit_data)
3238 {
3239 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3240 struct lp_build_context *uint = &bld_base->uint_bld;
3241 struct si_shader *shader = si_shader_ctx->shader;
3242 struct tgsi_shader_info *info = &shader->selector->info;
3243 struct gallivm_state *gallivm = bld_base->base.gallivm;
3244 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
3245 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3246 SI_PARAM_GS2VS_OFFSET);
3247 LLVMValueRef gs_next_vertex;
3248 LLVMValueRef can_emit, kill;
3249 LLVMValueRef args[2];
3250 unsigned chan;
3251 int i;
3252 unsigned stream;
3253
3254 stream = si_llvm_get_stream(bld_base, emit_data);
3255
3256 /* Write vertex attribute values to GSVS ring */
3257 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
3258 si_shader_ctx->gs_next_vertex[stream],
3259 "");
3260
3261 /* If this thread has already emitted the declared maximum number of
3262 * vertices, kill it: excessive vertex emissions are not supposed to
3263 * have any effect, and GS threads have no externally observable
3264 * effects other than emitting vertices.
3265 */
3266 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
3267 lp_build_const_int32(gallivm,
3268 shader->selector->gs_max_out_vertices), "");
3269 kill = lp_build_select(&bld_base->base, can_emit,
3270 lp_build_const_float(gallivm, 1.0f),
3271 lp_build_const_float(gallivm, -1.0f));
3272
3273 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
3274 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
3275
3276 for (i = 0; i < info->num_outputs; i++) {
3277 LLVMValueRef *out_ptr =
3278 si_shader_ctx->radeon_bld.soa.outputs[i];
3279
3280 for (chan = 0; chan < 4; chan++) {
3281 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3282 LLVMValueRef voffset =
3283 lp_build_const_int32(gallivm, (i * 4 + chan) *
3284 shader->selector->gs_max_out_vertices);
3285
3286 voffset = lp_build_add(uint, voffset, gs_next_vertex);
3287 voffset = lp_build_mul_imm(uint, voffset, 4);
3288
3289 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
3290
3291 build_tbuffer_store(si_shader_ctx,
3292 si_shader_ctx->gsvs_ring[stream],
3293 out_val, 1,
3294 voffset, soffset, 0,
3295 V_008F0C_BUF_DATA_FORMAT_32,
3296 V_008F0C_BUF_NUM_FORMAT_UINT,
3297 1, 0, 1, 1, 0);
3298 }
3299 }
3300 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
3301 lp_build_const_int32(gallivm, 1));
3302
3303 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex[stream]);
3304
3305 /* Signal vertex emission */
3306 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
3307 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3308 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3309 LLVMVoidTypeInContext(gallivm->context), args, 2,
3310 LLVMNoUnwindAttribute);
3311 }
3312
3313 /* Cut one primitive from the geometry shader */
3314 static void si_llvm_emit_primitive(
3315 const struct lp_build_tgsi_action *action,
3316 struct lp_build_tgsi_context *bld_base,
3317 struct lp_build_emit_data *emit_data)
3318 {
3319 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3320 struct gallivm_state *gallivm = bld_base->base.gallivm;
3321 LLVMValueRef args[2];
3322 unsigned stream;
3323
3324 /* Signal primitive cut */
3325 stream = si_llvm_get_stream(bld_base, emit_data);
3326 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
3327 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3328 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3329 LLVMVoidTypeInContext(gallivm->context), args, 2,
3330 LLVMNoUnwindAttribute);
3331 }
3332
3333 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
3334 struct lp_build_tgsi_context *bld_base,
3335 struct lp_build_emit_data *emit_data)
3336 {
3337 struct gallivm_state *gallivm = bld_base->base.gallivm;
3338
3339 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.barrier.local",
3340 LLVMVoidTypeInContext(gallivm->context), NULL, 0,
3341 LLVMNoUnwindAttribute);
3342 }
3343
3344 static const struct lp_build_tgsi_action tex_action = {
3345 .fetch_args = tex_fetch_args,
3346 .emit = build_tex_intrinsic,
3347 };
3348
3349 static const struct lp_build_tgsi_action txq_action = {
3350 .fetch_args = txq_fetch_args,
3351 .emit = build_txq_intrinsic,
3352 .intr_name = "llvm.SI.resinfo"
3353 };
3354
3355 static const struct lp_build_tgsi_action interp_action = {
3356 .fetch_args = interp_fetch_args,
3357 .emit = build_interp_intrinsic,
3358 };
3359
3360 static void create_meta_data(struct si_shader_context *si_shader_ctx)
3361 {
3362 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3363 LLVMValueRef args[3];
3364
3365 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
3366 args[1] = 0;
3367 args[2] = lp_build_const_int32(gallivm, 1);
3368
3369 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
3370 }
3371
3372 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3373 {
3374 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3375 CONST_ADDR_SPACE);
3376 }
3377
3378 static void declare_streamout_params(struct si_shader_context *si_shader_ctx,
3379 struct pipe_stream_output_info *so,
3380 LLVMTypeRef *params, LLVMTypeRef i32,
3381 unsigned *num_params)
3382 {
3383 int i;
3384
3385 /* Streamout SGPRs. */
3386 if (so->num_outputs) {
3387 params[si_shader_ctx->param_streamout_config = (*num_params)++] = i32;
3388 params[si_shader_ctx->param_streamout_write_index = (*num_params)++] = i32;
3389 }
3390 /* A streamout buffer offset is loaded if the stride is non-zero. */
3391 for (i = 0; i < 4; i++) {
3392 if (!so->stride[i])
3393 continue;
3394
3395 params[si_shader_ctx->param_streamout_offset[i] = (*num_params)++] = i32;
3396 }
3397 }
3398
3399 static void create_function(struct si_shader_context *si_shader_ctx)
3400 {
3401 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3402 struct gallivm_state *gallivm = bld_base->base.gallivm;
3403 struct si_shader *shader = si_shader_ctx->shader;
3404 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
3405 unsigned i, last_array_pointer, last_sgpr, num_params;
3406
3407 i8 = LLVMInt8TypeInContext(gallivm->context);
3408 i32 = LLVMInt32TypeInContext(gallivm->context);
3409 f32 = LLVMFloatTypeInContext(gallivm->context);
3410 v2i32 = LLVMVectorType(i32, 2);
3411 v3i32 = LLVMVectorType(i32, 3);
3412 v4i32 = LLVMVectorType(i32, 4);
3413 v8i32 = LLVMVectorType(i32, 8);
3414 v16i8 = LLVMVectorType(i8, 16);
3415
3416 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
3417 params[SI_PARAM_CONST] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
3418 params[SI_PARAM_SAMPLER] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
3419 params[SI_PARAM_RESOURCE] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
3420 last_array_pointer = SI_PARAM_RESOURCE;
3421
3422 switch (si_shader_ctx->type) {
3423 case TGSI_PROCESSOR_VERTEX:
3424 params[SI_PARAM_VERTEX_BUFFER] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
3425 last_array_pointer = SI_PARAM_VERTEX_BUFFER;
3426 params[SI_PARAM_BASE_VERTEX] = i32;
3427 params[SI_PARAM_START_INSTANCE] = i32;
3428 num_params = SI_PARAM_START_INSTANCE+1;
3429
3430 if (shader->key.vs.as_es) {
3431 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3432 } else if (shader->key.vs.as_ls) {
3433 params[SI_PARAM_LS_OUT_LAYOUT] = i32;
3434 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
3435 } else {
3436 if (shader->is_gs_copy_shader) {
3437 last_array_pointer = SI_PARAM_CONST;
3438 num_params = SI_PARAM_CONST+1;
3439 }
3440
3441 /* The locations of the other parameters are assigned dynamically. */
3442 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3443 params, i32, &num_params);
3444 }
3445
3446 last_sgpr = num_params-1;
3447
3448 /* VGPRs */
3449 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
3450 params[si_shader_ctx->param_rel_auto_id = num_params++] = i32;
3451 params[si_shader_ctx->param_vs_prim_id = num_params++] = i32;
3452 params[si_shader_ctx->param_instance_id = num_params++] = i32;
3453 break;
3454
3455 case TGSI_PROCESSOR_TESS_CTRL:
3456 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3457 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3458 params[SI_PARAM_TCS_IN_LAYOUT] = i32;
3459 params[SI_PARAM_TESS_FACTOR_OFFSET] = i32;
3460 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
3461
3462 /* VGPRs */
3463 params[SI_PARAM_PATCH_ID] = i32;
3464 params[SI_PARAM_REL_IDS] = i32;
3465 num_params = SI_PARAM_REL_IDS+1;
3466 break;
3467
3468 case TGSI_PROCESSOR_TESS_EVAL:
3469 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3470 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3471 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
3472
3473 if (shader->key.tes.as_es) {
3474 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3475 } else {
3476 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3477 params, i32, &num_params);
3478 }
3479 last_sgpr = num_params - 1;
3480
3481 /* VGPRs */
3482 params[si_shader_ctx->param_tes_u = num_params++] = f32;
3483 params[si_shader_ctx->param_tes_v = num_params++] = f32;
3484 params[si_shader_ctx->param_tes_rel_patch_id = num_params++] = i32;
3485 params[si_shader_ctx->param_tes_patch_id = num_params++] = i32;
3486 break;
3487
3488 case TGSI_PROCESSOR_GEOMETRY:
3489 params[SI_PARAM_GS2VS_OFFSET] = i32;
3490 params[SI_PARAM_GS_WAVE_ID] = i32;
3491 last_sgpr = SI_PARAM_GS_WAVE_ID;
3492
3493 /* VGPRs */
3494 params[SI_PARAM_VTX0_OFFSET] = i32;
3495 params[SI_PARAM_VTX1_OFFSET] = i32;
3496 params[SI_PARAM_PRIMITIVE_ID] = i32;
3497 params[SI_PARAM_VTX2_OFFSET] = i32;
3498 params[SI_PARAM_VTX3_OFFSET] = i32;
3499 params[SI_PARAM_VTX4_OFFSET] = i32;
3500 params[SI_PARAM_VTX5_OFFSET] = i32;
3501 params[SI_PARAM_GS_INSTANCE_ID] = i32;
3502 num_params = SI_PARAM_GS_INSTANCE_ID+1;
3503 break;
3504
3505 case TGSI_PROCESSOR_FRAGMENT:
3506 params[SI_PARAM_ALPHA_REF] = f32;
3507 params[SI_PARAM_PRIM_MASK] = i32;
3508 last_sgpr = SI_PARAM_PRIM_MASK;
3509 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
3510 params[SI_PARAM_PERSP_CENTER] = v2i32;
3511 params[SI_PARAM_PERSP_CENTROID] = v2i32;
3512 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
3513 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
3514 params[SI_PARAM_LINEAR_CENTER] = v2i32;
3515 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
3516 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
3517 params[SI_PARAM_POS_X_FLOAT] = f32;
3518 params[SI_PARAM_POS_Y_FLOAT] = f32;
3519 params[SI_PARAM_POS_Z_FLOAT] = f32;
3520 params[SI_PARAM_POS_W_FLOAT] = f32;
3521 params[SI_PARAM_FRONT_FACE] = f32;
3522 params[SI_PARAM_ANCILLARY] = i32;
3523 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
3524 params[SI_PARAM_POS_FIXED_PT] = f32;
3525 num_params = SI_PARAM_POS_FIXED_PT+1;
3526 break;
3527
3528 default:
3529 assert(0 && "unimplemented shader");
3530 return;
3531 }
3532
3533 assert(num_params <= Elements(params));
3534 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
3535 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
3536
3537 if (shader->dx10_clamp_mode)
3538 LLVMAddTargetDependentFunctionAttr(si_shader_ctx->radeon_bld.main_fn,
3539 "enable-no-nans-fp-math", "true");
3540
3541 for (i = 0; i <= last_sgpr; ++i) {
3542 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
3543
3544 /* We tell llvm that array inputs are passed by value to allow Sinking pass
3545 * to move load. Inputs are constant so this is fine. */
3546 if (i <= last_array_pointer)
3547 LLVMAddAttribute(P, LLVMByValAttribute);
3548 else
3549 LLVMAddAttribute(P, LLVMInRegAttribute);
3550 }
3551
3552 if (bld_base->info &&
3553 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
3554 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
3555 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
3556 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
3557 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
3558 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
3559 si_shader_ctx->lds =
3560 LLVMAddGlobalInAddressSpace(gallivm->module,
3561 LLVMArrayType(i32, 64),
3562 "ddxy_lds",
3563 LOCAL_ADDR_SPACE);
3564
3565 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
3566 si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
3567 si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL) {
3568 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
3569 unsigned vertex_data_dw_size = 32*32*4;
3570 unsigned patch_data_dw_size = 32*4;
3571 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
3572 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
3573 unsigned lds_dwords = patch_dw_size;
3574
3575 /* The actual size is computed outside of the shader to reduce
3576 * the number of shader variants. */
3577 si_shader_ctx->lds =
3578 LLVMAddGlobalInAddressSpace(gallivm->module,
3579 LLVMArrayType(i32, lds_dwords),
3580 "tess_lds",
3581 LOCAL_ADDR_SPACE);
3582 }
3583 }
3584
3585 static void preload_constants(struct si_shader_context *si_shader_ctx)
3586 {
3587 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3588 struct gallivm_state * gallivm = bld_base->base.gallivm;
3589 const struct tgsi_shader_info * info = bld_base->info;
3590 unsigned buf;
3591 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
3592
3593 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
3594 unsigned i, num_const = info->const_file_max[buf] + 1;
3595
3596 if (num_const == 0)
3597 continue;
3598
3599 /* Allocate space for the constant values */
3600 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
3601
3602 /* Load the resource descriptor */
3603 si_shader_ctx->const_resource[buf] =
3604 build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
3605
3606 /* Load the constants, we rely on the code sinking to do the rest */
3607 for (i = 0; i < num_const * 4; ++i) {
3608 si_shader_ctx->constants[buf][i] =
3609 buffer_load_const(gallivm->builder,
3610 si_shader_ctx->const_resource[buf],
3611 lp_build_const_int32(gallivm, i * 4),
3612 bld_base->base.elem_type);
3613 }
3614 }
3615 }
3616
3617 static void preload_samplers(struct si_shader_context *si_shader_ctx)
3618 {
3619 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3620 struct gallivm_state * gallivm = bld_base->base.gallivm;
3621 const struct tgsi_shader_info * info = bld_base->info;
3622
3623 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
3624
3625 LLVMValueRef res_ptr, samp_ptr;
3626 LLVMValueRef offset;
3627
3628 if (num_samplers == 0)
3629 return;
3630
3631 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
3632 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
3633
3634 /* Load the resources and samplers, we rely on the code sinking to do the rest */
3635 for (i = 0; i < num_samplers; ++i) {
3636 /* Resource */
3637 offset = lp_build_const_int32(gallivm, i);
3638 si_shader_ctx->resources[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3639
3640 /* Sampler */
3641 offset = lp_build_const_int32(gallivm, i);
3642 si_shader_ctx->samplers[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
3643
3644 /* FMASK resource */
3645 if (info->is_msaa_sampler[i]) {
3646 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
3647 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + i] =
3648 build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3649 }
3650 }
3651 }
3652
3653 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
3654 {
3655 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3656 struct gallivm_state * gallivm = bld_base->base.gallivm;
3657 unsigned i;
3658
3659 /* Streamout can only be used if the shader is compiled as VS. */
3660 if (!si_shader_ctx->shader->selector->so.num_outputs ||
3661 (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3662 (si_shader_ctx->shader->key.vs.as_es ||
3663 si_shader_ctx->shader->key.vs.as_ls)) ||
3664 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3665 si_shader_ctx->shader->key.tes.as_es))
3666 return;
3667
3668 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3669 SI_PARAM_RW_BUFFERS);
3670
3671 /* Load the resources, we rely on the code sinking to do the rest */
3672 for (i = 0; i < 4; ++i) {
3673 if (si_shader_ctx->shader->selector->so.stride[i]) {
3674 LLVMValueRef offset = lp_build_const_int32(gallivm,
3675 SI_SO_BUF_OFFSET + i);
3676
3677 si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3678 }
3679 }
3680 }
3681
3682 /**
3683 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
3684 * for later use.
3685 */
3686 static void preload_ring_buffers(struct si_shader_context *si_shader_ctx)
3687 {
3688 struct gallivm_state *gallivm =
3689 si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3690
3691 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3692 SI_PARAM_RW_BUFFERS);
3693
3694 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3695 si_shader_ctx->shader->key.vs.as_es) ||
3696 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3697 si_shader_ctx->shader->key.tes.as_es) ||
3698 si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3699 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
3700
3701 si_shader_ctx->esgs_ring =
3702 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3703 }
3704
3705 if (si_shader_ctx->shader->is_gs_copy_shader) {
3706 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
3707
3708 si_shader_ctx->gsvs_ring[0] =
3709 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3710 }
3711 if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3712 int i;
3713 for (i = 0; i < 4; i++) {
3714 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i);
3715
3716 si_shader_ctx->gsvs_ring[i] =
3717 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3718 }
3719 }
3720 }
3721
3722 void si_shader_binary_read_config(const struct si_screen *sscreen,
3723 struct si_shader *shader,
3724 unsigned symbol_offset)
3725 {
3726 unsigned i;
3727 const unsigned char *config =
3728 radeon_shader_binary_config_start(&shader->binary,
3729 symbol_offset);
3730
3731 /* XXX: We may be able to emit some of these values directly rather than
3732 * extracting fields to be emitted later.
3733 */
3734
3735 for (i = 0; i < shader->binary.config_size_per_symbol; i+= 8) {
3736 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
3737 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
3738 switch (reg) {
3739 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
3740 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
3741 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
3742 case R_00B848_COMPUTE_PGM_RSRC1:
3743 shader->num_sgprs = MAX2(shader->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
3744 shader->num_vgprs = MAX2(shader->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
3745 shader->float_mode = G_00B028_FLOAT_MODE(value);
3746 break;
3747 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
3748 shader->lds_size = MAX2(shader->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
3749 break;
3750 case R_00B84C_COMPUTE_PGM_RSRC2:
3751 shader->lds_size = MAX2(shader->lds_size, G_00B84C_LDS_SIZE(value));
3752 break;
3753 case R_0286CC_SPI_PS_INPUT_ENA:
3754 shader->spi_ps_input_ena = value;
3755 break;
3756 case R_0286E8_SPI_TMPRING_SIZE:
3757 case R_00B860_COMPUTE_TMPRING_SIZE:
3758 /* WAVESIZE is in units of 256 dwords. */
3759 shader->scratch_bytes_per_wave =
3760 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
3761 break;
3762 default:
3763 fprintf(stderr, "Warning: Compiler emitted unknown "
3764 "config register: 0x%x\n", reg);
3765 break;
3766 }
3767 }
3768 }
3769
3770 void si_shader_apply_scratch_relocs(struct si_context *sctx,
3771 struct si_shader *shader,
3772 uint64_t scratch_va)
3773 {
3774 unsigned i;
3775 uint32_t scratch_rsrc_dword0 = scratch_va & 0xffffffff;
3776 uint32_t scratch_rsrc_dword1 =
3777 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
3778 | S_008F04_STRIDE(shader->scratch_bytes_per_wave / 64);
3779
3780 for (i = 0 ; i < shader->binary.reloc_count; i++) {
3781 const struct radeon_shader_reloc *reloc =
3782 &shader->binary.relocs[i];
3783 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
3784 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3785 &scratch_rsrc_dword0, 4);
3786 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
3787 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3788 &scratch_rsrc_dword1, 4);
3789 }
3790 }
3791 }
3792
3793 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
3794 {
3795 const struct radeon_shader_binary *binary = &shader->binary;
3796 unsigned code_size = binary->code_size + binary->rodata_size;
3797 unsigned char *ptr;
3798
3799 r600_resource_reference(&shader->bo, NULL);
3800 shader->bo = si_resource_create_custom(&sscreen->b.b,
3801 PIPE_USAGE_IMMUTABLE,
3802 code_size);
3803 if (!shader->bo)
3804 return -ENOMEM;
3805
3806 ptr = sscreen->b.ws->buffer_map(shader->bo->cs_buf, NULL,
3807 PIPE_TRANSFER_READ_WRITE);
3808 util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
3809 if (binary->rodata_size > 0) {
3810 ptr += binary->code_size;
3811 util_memcpy_cpu_to_le32(ptr, binary->rodata,
3812 binary->rodata_size);
3813 }
3814
3815 sscreen->b.ws->buffer_unmap(shader->bo->cs_buf);
3816 return 0;
3817 }
3818
3819 int si_shader_binary_read(struct si_screen *sscreen, struct si_shader *shader)
3820 {
3821 const struct radeon_shader_binary *binary = &shader->binary;
3822 unsigned i;
3823 bool dump = r600_can_dump_shader(&sscreen->b,
3824 shader->selector ? shader->selector->tokens : NULL);
3825
3826 si_shader_binary_read_config(sscreen, shader, 0);
3827 si_shader_binary_upload(sscreen, shader);
3828
3829 if (dump) {
3830 if (!(sscreen->b.debug_flags & DBG_NO_ASM)) {
3831 if (binary->disasm_string) {
3832 fprintf(stderr, "\nShader Disassembly:\n\n");
3833 fprintf(stderr, "%s\n", binary->disasm_string);
3834 } else {
3835 fprintf(stderr, "SI CODE:\n");
3836 for (i = 0; i < binary->code_size; i+=4 ) {
3837 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i, binary->code[i + 3],
3838 binary->code[i + 2], binary->code[i + 1],
3839 binary->code[i]);
3840 }
3841 }
3842 }
3843
3844 fprintf(stderr, "*** SHADER STATS ***\n"
3845 "SGPRS: %d\nVGPRS: %d\nCode Size: %d bytes\nLDS: %d blocks\n"
3846 "Scratch: %d bytes per wave\n********************\n",
3847 shader->num_sgprs, shader->num_vgprs, binary->code_size,
3848 shader->lds_size, shader->scratch_bytes_per_wave);
3849 }
3850 return 0;
3851 }
3852
3853 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
3854 LLVMTargetMachineRef tm, LLVMModuleRef mod)
3855 {
3856 int r = 0;
3857 bool dump_asm = r600_can_dump_shader(&sscreen->b,
3858 shader->selector ? shader->selector->tokens : NULL);
3859 bool dump_ir = dump_asm && !(sscreen->b.debug_flags & DBG_NO_IR);
3860
3861 r = radeon_llvm_compile(mod, &shader->binary,
3862 r600_get_llvm_processor_name(sscreen->b.family), dump_ir, dump_asm, tm);
3863 if (r)
3864 return r;
3865
3866 r = si_shader_binary_read(sscreen, shader);
3867
3868 FREE(shader->binary.config);
3869 FREE(shader->binary.rodata);
3870 FREE(shader->binary.global_symbol_offsets);
3871 if (shader->scratch_bytes_per_wave == 0) {
3872 FREE(shader->binary.code);
3873 FREE(shader->binary.relocs);
3874 memset(&shader->binary, 0,
3875 offsetof(struct radeon_shader_binary, disasm_string));
3876 }
3877 return r;
3878 }
3879
3880 /* Generate code for the hardware VS shader stage to go with a geometry shader */
3881 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
3882 struct si_shader_context *si_shader_ctx,
3883 struct si_shader *gs, bool dump)
3884 {
3885 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
3886 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3887 struct lp_build_context *base = &bld_base->base;
3888 struct lp_build_context *uint = &bld_base->uint_bld;
3889 struct si_shader *shader = si_shader_ctx->shader;
3890 struct si_shader_output_values *outputs;
3891 struct tgsi_shader_info *gsinfo = &gs->selector->info;
3892 LLVMValueRef args[9];
3893 int i, r;
3894
3895 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
3896
3897 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
3898 shader->is_gs_copy_shader = true;
3899
3900 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
3901
3902 create_meta_data(si_shader_ctx);
3903 create_function(si_shader_ctx);
3904 preload_streamout_buffers(si_shader_ctx);
3905 preload_ring_buffers(si_shader_ctx);
3906
3907 args[0] = si_shader_ctx->gsvs_ring[0];
3908 args[1] = lp_build_mul_imm(uint,
3909 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3910 si_shader_ctx->param_vertex_id),
3911 4);
3912 args[3] = uint->zero;
3913 args[4] = uint->one; /* OFFEN */
3914 args[5] = uint->zero; /* IDXEN */
3915 args[6] = uint->one; /* GLC */
3916 args[7] = uint->one; /* SLC */
3917 args[8] = uint->zero; /* TFE */
3918
3919 /* Fetch vertex data from GSVS ring */
3920 for (i = 0; i < gsinfo->num_outputs; ++i) {
3921 unsigned chan;
3922
3923 outputs[i].name = gsinfo->output_semantic_name[i];
3924 outputs[i].sid = gsinfo->output_semantic_index[i];
3925
3926 for (chan = 0; chan < 4; chan++) {
3927 args[2] = lp_build_const_int32(gallivm,
3928 (i * 4 + chan) *
3929 gs->selector->gs_max_out_vertices * 16 * 4);
3930
3931 outputs[i].values[chan] =
3932 LLVMBuildBitCast(gallivm->builder,
3933 lp_build_intrinsic(gallivm->builder,
3934 "llvm.SI.buffer.load.dword.i32.i32",
3935 LLVMInt32TypeInContext(gallivm->context),
3936 args, 9,
3937 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
3938 base->elem_type, "");
3939 }
3940 }
3941
3942 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
3943
3944 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
3945
3946 if (dump)
3947 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
3948
3949 r = si_compile_llvm(sscreen, si_shader_ctx->shader,
3950 si_shader_ctx->tm, bld_base->base.gallivm->module);
3951
3952 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
3953
3954 FREE(outputs);
3955 return r;
3956 }
3957
3958 static void si_dump_key(unsigned shader, union si_shader_key *key)
3959 {
3960 int i;
3961
3962 fprintf(stderr, "SHADER KEY\n");
3963
3964 switch (shader) {
3965 case PIPE_SHADER_VERTEX:
3966 fprintf(stderr, " instance_divisors = {");
3967 for (i = 0; i < Elements(key->vs.instance_divisors); i++)
3968 fprintf(stderr, !i ? "%u" : ", %u",
3969 key->vs.instance_divisors[i]);
3970 fprintf(stderr, "}\n");
3971
3972 if (key->vs.as_es)
3973 fprintf(stderr, " es_enabled_outputs = 0x%"PRIx64"\n",
3974 key->vs.es_enabled_outputs);
3975 fprintf(stderr, " as_es = %u\n", key->vs.as_es);
3976 fprintf(stderr, " as_es = %u\n", key->vs.as_ls);
3977 break;
3978
3979 case PIPE_SHADER_TESS_CTRL:
3980 fprintf(stderr, " prim_mode = %u\n", key->tcs.prim_mode);
3981 break;
3982
3983 case PIPE_SHADER_TESS_EVAL:
3984 if (key->tes.as_es)
3985 fprintf(stderr, " es_enabled_outputs = 0x%"PRIx64"\n",
3986 key->tes.es_enabled_outputs);
3987 fprintf(stderr, " as_es = %u\n", key->tes.as_es);
3988 break;
3989
3990 case PIPE_SHADER_GEOMETRY:
3991 break;
3992
3993 case PIPE_SHADER_FRAGMENT:
3994 fprintf(stderr, " export_16bpc = 0x%X\n", key->ps.export_16bpc);
3995 fprintf(stderr, " last_cbuf = %u\n", key->ps.last_cbuf);
3996 fprintf(stderr, " color_two_side = %u\n", key->ps.color_two_side);
3997 fprintf(stderr, " alpha_func = %u\n", key->ps.alpha_func);
3998 fprintf(stderr, " alpha_to_one = %u\n", key->ps.alpha_to_one);
3999 fprintf(stderr, " poly_stipple = %u\n", key->ps.poly_stipple);
4000 break;
4001
4002 default:
4003 assert(0);
4004 }
4005 }
4006
4007 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
4008 struct si_shader *shader)
4009 {
4010 struct si_shader_selector *sel = shader->selector;
4011 struct tgsi_token *tokens = sel->tokens;
4012 struct si_shader_context si_shader_ctx;
4013 struct lp_build_tgsi_context * bld_base;
4014 struct tgsi_shader_info stipple_shader_info;
4015 LLVMModuleRef mod;
4016 int r = 0;
4017 bool poly_stipple = sel->type == PIPE_SHADER_FRAGMENT &&
4018 shader->key.ps.poly_stipple;
4019 bool dump = r600_can_dump_shader(&sscreen->b, sel->tokens);
4020
4021 if (poly_stipple) {
4022 tokens = util_pstipple_create_fragment_shader(tokens, NULL,
4023 SI_POLY_STIPPLE_SAMPLER);
4024 tgsi_scan_shader(tokens, &stipple_shader_info);
4025 }
4026
4027 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
4028 * conversion fails. */
4029 if (dump && !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
4030 si_dump_key(sel->type, &shader->key);
4031 tgsi_dump(tokens, 0);
4032 si_dump_streamout(&sel->so);
4033 }
4034
4035 assert(shader->nparam == 0);
4036
4037 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
4038 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
4039 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
4040
4041 if (sel->type != PIPE_SHADER_COMPUTE)
4042 shader->dx10_clamp_mode = true;
4043
4044 if (sel->info.uses_kill)
4045 shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
4046
4047 shader->uses_instanceid = sel->info.uses_instanceid;
4048 bld_base->info = poly_stipple ? &stipple_shader_info : &sel->info;
4049 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
4050
4051 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
4052 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
4053 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
4054
4055 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
4056 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
4057 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
4058 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
4059 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
4060 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
4061 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
4062 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
4063 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
4064 bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
4065 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
4066 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
4067
4068 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
4069 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
4070 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
4071 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
4072
4073 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
4074 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
4075 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
4076
4077 if (HAVE_LLVM >= 0x0306) {
4078 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
4079 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
4080 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
4081 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
4082 }
4083
4084 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
4085 si_shader_ctx.shader = shader;
4086 si_shader_ctx.type = tgsi_get_processor_type(tokens);
4087 si_shader_ctx.screen = sscreen;
4088 si_shader_ctx.tm = tm;
4089
4090 switch (si_shader_ctx.type) {
4091 case TGSI_PROCESSOR_VERTEX:
4092 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
4093 if (shader->key.vs.as_ls)
4094 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
4095 else if (shader->key.vs.as_es)
4096 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4097 else
4098 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4099 break;
4100 case TGSI_PROCESSOR_TESS_CTRL:
4101 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
4102 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
4103 bld_base->emit_store = store_output_tcs;
4104 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
4105 break;
4106 case TGSI_PROCESSOR_TESS_EVAL:
4107 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
4108 if (shader->key.tes.as_es)
4109 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4110 else
4111 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4112 break;
4113 case TGSI_PROCESSOR_GEOMETRY:
4114 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
4115 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
4116 break;
4117 case TGSI_PROCESSOR_FRAGMENT:
4118 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
4119 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
4120
4121 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
4122 case TGSI_FS_DEPTH_LAYOUT_GREATER:
4123 shader->db_shader_control |=
4124 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
4125 break;
4126 case TGSI_FS_DEPTH_LAYOUT_LESS:
4127 shader->db_shader_control |=
4128 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
4129 break;
4130 }
4131 break;
4132 default:
4133 assert(!"Unsupported shader type");
4134 return -1;
4135 }
4136
4137 create_meta_data(&si_shader_ctx);
4138 create_function(&si_shader_ctx);
4139 preload_constants(&si_shader_ctx);
4140 preload_samplers(&si_shader_ctx);
4141 preload_streamout_buffers(&si_shader_ctx);
4142 preload_ring_buffers(&si_shader_ctx);
4143
4144 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4145 int i;
4146 for (i = 0; i < 4; i++) {
4147 si_shader_ctx.gs_next_vertex[i] =
4148 lp_build_alloca(bld_base->base.gallivm,
4149 bld_base->uint_bld.elem_type, "");
4150 }
4151 }
4152
4153 if (!lp_build_tgsi_llvm(bld_base, tokens)) {
4154 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
4155 goto out;
4156 }
4157
4158 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
4159
4160 mod = bld_base->base.gallivm->module;
4161 r = si_compile_llvm(sscreen, shader, tm, mod);
4162 if (r) {
4163 fprintf(stderr, "LLVM failed to compile shader\n");
4164 goto out;
4165 }
4166
4167 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
4168
4169 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4170 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
4171 shader->gs_copy_shader->selector = shader->selector;
4172 shader->gs_copy_shader->key = shader->key;
4173 si_shader_ctx.shader = shader->gs_copy_shader;
4174 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
4175 shader, dump))) {
4176 free(shader->gs_copy_shader);
4177 shader->gs_copy_shader = NULL;
4178 goto out;
4179 }
4180 }
4181
4182 out:
4183 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
4184 FREE(si_shader_ctx.constants[i]);
4185 if (poly_stipple)
4186 tgsi_free_tokens(tokens);
4187 return r;
4188 }
4189
4190 void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader)
4191 {
4192 if (shader->gs_copy_shader)
4193 si_shader_destroy(ctx, shader->gs_copy_shader);
4194
4195 if (shader->scratch_bo)
4196 r600_resource_reference(&shader->scratch_bo, NULL);
4197
4198 r600_resource_reference(&shader->bo, NULL);
4199
4200 FREE(shader->binary.code);
4201 FREE(shader->binary.relocs);
4202 FREE(shader->binary.disasm_string);
4203 }