2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "gallivm/lp_bld_misc.h"
37 #include "radeon/r600_cs.h"
38 #include "radeon/radeon_llvm.h"
39 #include "radeon/radeon_elf_util.h"
40 #include "radeon/radeon_llvm_emit.h"
41 #include "util/u_memory.h"
42 #include "util/u_string.h"
43 #include "tgsi/tgsi_parse.h"
44 #include "tgsi/tgsi_build.h"
45 #include "tgsi/tgsi_util.h"
46 #include "tgsi/tgsi_dump.h"
49 #include "si_shader.h"
54 static const char *scratch_rsrc_dword0_symbol
=
55 "SCRATCH_RSRC_DWORD0";
57 static const char *scratch_rsrc_dword1_symbol
=
58 "SCRATCH_RSRC_DWORD1";
60 struct si_shader_output_values
62 LLVMValueRef values
[4];
67 struct si_shader_context
69 struct radeon_llvm_context radeon_bld
;
70 struct si_shader
*shader
;
71 struct si_screen
*screen
;
73 unsigned type
; /* PIPE_SHADER_* specifies the type of shader. */
74 bool is_gs_copy_shader
;
76 /* Whether to generate the optimized shader variant compiled as a whole
77 * (without a prolog and epilog)
81 int param_streamout_config
;
82 int param_streamout_write_index
;
83 int param_streamout_offset
[4];
85 int param_rel_auto_id
;
87 int param_instance_id
;
88 int param_vertex_index0
;
91 int param_tes_rel_patch_id
;
92 int param_tes_patch_id
;
93 int param_es2gs_offset
;
96 /* Sets a bit if the dynamic HS control word was 0x80000000. The bit is
97 * 0x800000 for VS, 0x1 for ES.
99 int param_tess_offchip
;
101 LLVMTargetMachineRef tm
;
103 unsigned invariant_load_md_kind
;
104 unsigned range_md_kind
;
105 unsigned uniform_md_kind
;
106 LLVMValueRef empty_md
;
108 LLVMValueRef const_buffers
[SI_NUM_CONST_BUFFERS
];
110 LLVMValueRef
*constants
[SI_NUM_CONST_BUFFERS
];
111 LLVMValueRef shader_buffers
[SI_NUM_SHADER_BUFFERS
];
112 LLVMValueRef sampler_views
[SI_NUM_SAMPLERS
];
113 LLVMValueRef sampler_states
[SI_NUM_SAMPLERS
];
114 LLVMValueRef fmasks
[SI_NUM_SAMPLERS
];
115 LLVMValueRef images
[SI_NUM_IMAGES
];
116 LLVMValueRef so_buffers
[4];
117 LLVMValueRef esgs_ring
;
118 LLVMValueRef gsvs_ring
[4];
119 LLVMValueRef gs_next_vertex
[4];
120 LLVMValueRef return_value
;
135 LLVMValueRef shared_memory
;
138 static struct si_shader_context
*si_shader_context(
139 struct lp_build_tgsi_context
*bld_base
)
141 return (struct si_shader_context
*)bld_base
;
144 static void si_init_shader_ctx(struct si_shader_context
*ctx
,
145 struct si_screen
*sscreen
,
146 struct si_shader
*shader
,
147 LLVMTargetMachineRef tm
);
149 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action
*action
,
150 struct lp_build_tgsi_context
*bld_base
,
151 struct lp_build_emit_data
*emit_data
);
153 static void si_dump_shader_key(unsigned shader
, union si_shader_key
*key
,
156 /* Ideally pass the sample mask input to the PS epilog as v13, which
157 * is its usual location, so that the shader doesn't have to add v_mov.
159 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
161 /* The VS location of the PrimitiveID input is the same in the epilog,
162 * so that the main shader part doesn't have to move it.
164 #define VS_EPILOG_PRIMID_LOC 2
166 #define PERSPECTIVE_BASE 0
167 #define LINEAR_BASE 9
169 #define SAMPLE_OFFSET 0
170 #define CENTER_OFFSET 2
171 #define CENTROID_OFSET 4
173 #define USE_SGPR_MAX_SUFFIX_LEN 5
174 #define CONST_ADDR_SPACE 2
175 #define LOCAL_ADDR_SPACE 3
176 #define USER_SGPR_ADDR_SPACE 8
180 #define SENDMSG_GS_DONE 3
182 #define SENDMSG_GS_OP_NOP (0 << 4)
183 #define SENDMSG_GS_OP_CUT (1 << 4)
184 #define SENDMSG_GS_OP_EMIT (2 << 4)
185 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
188 * Returns a unique index for a semantic name and index. The index must be
189 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
192 unsigned si_shader_io_get_unique_index(unsigned semantic_name
, unsigned index
)
194 switch (semantic_name
) {
195 case TGSI_SEMANTIC_POSITION
:
197 case TGSI_SEMANTIC_PSIZE
:
199 case TGSI_SEMANTIC_CLIPDIST
:
202 case TGSI_SEMANTIC_GENERIC
:
206 /* same explanation as in the default statement,
207 * the only user hitting this is st/nine.
211 /* patch indices are completely separate and thus start from 0 */
212 case TGSI_SEMANTIC_TESSOUTER
:
214 case TGSI_SEMANTIC_TESSINNER
:
216 case TGSI_SEMANTIC_PATCH
:
220 /* Don't fail here. The result of this function is only used
221 * for LS, TCS, TES, and GS, where legacy GL semantics can't
222 * occur, but this function is called for all vertex shaders
223 * before it's known whether LS will be compiled or not.
230 * Get the value of a shader input parameter and extract a bitfield.
232 static LLVMValueRef
unpack_param(struct si_shader_context
*ctx
,
233 unsigned param
, unsigned rshift
,
236 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
237 LLVMValueRef value
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
240 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMFloatTypeKind
)
241 value
= bitcast(&ctx
->radeon_bld
.soa
.bld_base
,
242 TGSI_TYPE_UNSIGNED
, value
);
245 value
= LLVMBuildLShr(gallivm
->builder
, value
,
246 lp_build_const_int32(gallivm
, rshift
), "");
248 if (rshift
+ bitwidth
< 32) {
249 unsigned mask
= (1 << bitwidth
) - 1;
250 value
= LLVMBuildAnd(gallivm
->builder
, value
,
251 lp_build_const_int32(gallivm
, mask
), "");
257 static LLVMValueRef
get_rel_patch_id(struct si_shader_context
*ctx
)
260 case PIPE_SHADER_TESS_CTRL
:
261 return unpack_param(ctx
, SI_PARAM_REL_IDS
, 0, 8);
263 case PIPE_SHADER_TESS_EVAL
:
264 return LLVMGetParam(ctx
->radeon_bld
.main_fn
,
265 ctx
->param_tes_rel_patch_id
);
273 /* Tessellation shaders pass outputs to the next shader using LDS.
275 * LS outputs = TCS inputs
276 * TCS outputs = TES inputs
279 * - TCS inputs for patch 0
280 * - TCS inputs for patch 1
281 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
283 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
284 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
285 * - TCS outputs for patch 1
286 * - Per-patch TCS outputs for patch 1
287 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
288 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
291 * All three shaders VS(LS), TCS, TES share the same LDS space.
295 get_tcs_in_patch_stride(struct si_shader_context
*ctx
)
297 if (ctx
->type
== PIPE_SHADER_VERTEX
)
298 return unpack_param(ctx
, SI_PARAM_LS_OUT_LAYOUT
, 0, 13);
299 else if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
300 return unpack_param(ctx
, SI_PARAM_TCS_IN_LAYOUT
, 0, 13);
308 get_tcs_out_patch_stride(struct si_shader_context
*ctx
)
310 return unpack_param(ctx
, SI_PARAM_TCS_OUT_LAYOUT
, 0, 13);
314 get_tcs_out_patch0_offset(struct si_shader_context
*ctx
)
316 return lp_build_mul_imm(&ctx
->radeon_bld
.soa
.bld_base
.uint_bld
,
318 SI_PARAM_TCS_OUT_OFFSETS
,
324 get_tcs_out_patch0_patch_data_offset(struct si_shader_context
*ctx
)
326 return lp_build_mul_imm(&ctx
->radeon_bld
.soa
.bld_base
.uint_bld
,
328 SI_PARAM_TCS_OUT_OFFSETS
,
334 get_tcs_in_current_patch_offset(struct si_shader_context
*ctx
)
336 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
337 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
338 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
340 return LLVMBuildMul(gallivm
->builder
, patch_stride
, rel_patch_id
, "");
344 get_tcs_out_current_patch_offset(struct si_shader_context
*ctx
)
346 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
347 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
348 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
349 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
351 return LLVMBuildAdd(gallivm
->builder
, patch0_offset
,
352 LLVMBuildMul(gallivm
->builder
, patch_stride
,
358 get_tcs_out_current_patch_data_offset(struct si_shader_context
*ctx
)
360 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
361 LLVMValueRef patch0_patch_data_offset
=
362 get_tcs_out_patch0_patch_data_offset(ctx
);
363 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
364 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
366 return LLVMBuildAdd(gallivm
->builder
, patch0_patch_data_offset
,
367 LLVMBuildMul(gallivm
->builder
, patch_stride
,
372 static void build_indexed_store(struct si_shader_context
*ctx
,
373 LLVMValueRef base_ptr
, LLVMValueRef index
,
376 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
377 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
378 LLVMValueRef indices
[2], pointer
;
380 indices
[0] = bld_base
->uint_bld
.zero
;
383 pointer
= LLVMBuildGEP(gallivm
->builder
, base_ptr
, indices
, 2, "");
384 LLVMBuildStore(gallivm
->builder
, value
, pointer
);
388 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
389 * It's equivalent to doing a load from &base_ptr[index].
391 * \param base_ptr Where the array starts.
392 * \param index The element index into the array.
393 * \param uniform Whether the base_ptr and index can be assumed to be
394 * dynamically uniform
396 static LLVMValueRef
build_indexed_load(struct si_shader_context
*ctx
,
397 LLVMValueRef base_ptr
, LLVMValueRef index
,
400 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
401 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
402 LLVMValueRef indices
[2], pointer
;
404 indices
[0] = bld_base
->uint_bld
.zero
;
407 pointer
= LLVMBuildGEP(gallivm
->builder
, base_ptr
, indices
, 2, "");
409 LLVMSetMetadata(pointer
, ctx
->uniform_md_kind
, ctx
->empty_md
);
410 return LLVMBuildLoad(gallivm
->builder
, pointer
, "");
414 * Do a load from &base_ptr[index], but also add a flag that it's loading
415 * a constant from a dynamically uniform index.
417 static LLVMValueRef
build_indexed_load_const(
418 struct si_shader_context
*ctx
,
419 LLVMValueRef base_ptr
, LLVMValueRef index
)
421 LLVMValueRef result
= build_indexed_load(ctx
, base_ptr
, index
, true);
422 LLVMSetMetadata(result
, ctx
->invariant_load_md_kind
, ctx
->empty_md
);
426 static LLVMValueRef
get_instance_index_for_fetch(
427 struct radeon_llvm_context
*radeon_bld
,
428 unsigned param_start_instance
, unsigned divisor
)
430 struct si_shader_context
*ctx
=
431 si_shader_context(&radeon_bld
->soa
.bld_base
);
432 struct gallivm_state
*gallivm
= radeon_bld
->soa
.bld_base
.base
.gallivm
;
434 LLVMValueRef result
= LLVMGetParam(radeon_bld
->main_fn
,
435 ctx
->param_instance_id
);
437 /* The division must be done before START_INSTANCE is added. */
439 result
= LLVMBuildUDiv(gallivm
->builder
, result
,
440 lp_build_const_int32(gallivm
, divisor
), "");
442 return LLVMBuildAdd(gallivm
->builder
, result
,
443 LLVMGetParam(radeon_bld
->main_fn
, param_start_instance
), "");
446 static void declare_input_vs(
447 struct radeon_llvm_context
*radeon_bld
,
448 unsigned input_index
,
449 const struct tgsi_full_declaration
*decl
)
451 struct lp_build_context
*base
= &radeon_bld
->soa
.bld_base
.base
;
452 struct gallivm_state
*gallivm
= base
->gallivm
;
453 struct si_shader_context
*ctx
=
454 si_shader_context(&radeon_bld
->soa
.bld_base
);
456 ctx
->shader
->key
.vs
.prolog
.instance_divisors
[input_index
];
460 LLVMValueRef t_list_ptr
;
461 LLVMValueRef t_offset
;
463 LLVMValueRef attribute_offset
;
464 LLVMValueRef buffer_index
;
465 LLVMValueRef args
[3];
468 /* Load the T list */
469 t_list_ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_VERTEX_BUFFERS
);
471 t_offset
= lp_build_const_int32(gallivm
, input_index
);
473 t_list
= build_indexed_load_const(ctx
, t_list_ptr
, t_offset
);
475 /* Build the attribute offset */
476 attribute_offset
= lp_build_const_int32(gallivm
, 0);
478 if (!ctx
->is_monolithic
) {
479 buffer_index
= LLVMGetParam(radeon_bld
->main_fn
,
480 ctx
->param_vertex_index0
+
482 } else if (divisor
) {
483 /* Build index from instance ID, start instance and divisor */
484 ctx
->shader
->info
.uses_instanceid
= true;
485 buffer_index
= get_instance_index_for_fetch(&ctx
->radeon_bld
,
486 SI_PARAM_START_INSTANCE
,
489 /* Load the buffer index for vertices. */
490 LLVMValueRef vertex_id
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
491 ctx
->param_vertex_id
);
492 LLVMValueRef base_vertex
= LLVMGetParam(radeon_bld
->main_fn
,
493 SI_PARAM_BASE_VERTEX
);
494 buffer_index
= LLVMBuildAdd(gallivm
->builder
, base_vertex
, vertex_id
, "");
498 args
[1] = attribute_offset
;
499 args
[2] = buffer_index
;
500 input
= lp_build_intrinsic(gallivm
->builder
,
501 "llvm.SI.vs.load.input", ctx
->v4f32
, args
, 3,
502 LLVMReadNoneAttribute
);
504 /* Break up the vec4 into individual components */
505 for (chan
= 0; chan
< 4; chan
++) {
506 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
507 /* XXX: Use a helper function for this. There is one in
509 ctx
->radeon_bld
.inputs
[radeon_llvm_reg_index_soa(input_index
, chan
)] =
510 LLVMBuildExtractElement(gallivm
->builder
,
511 input
, llvm_chan
, "");
515 static LLVMValueRef
get_primitive_id(struct lp_build_tgsi_context
*bld_base
,
518 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
521 return bld_base
->uint_bld
.zero
;
524 case PIPE_SHADER_VERTEX
:
525 return LLVMGetParam(ctx
->radeon_bld
.main_fn
,
526 ctx
->param_vs_prim_id
);
527 case PIPE_SHADER_TESS_CTRL
:
528 return LLVMGetParam(ctx
->radeon_bld
.main_fn
,
530 case PIPE_SHADER_TESS_EVAL
:
531 return LLVMGetParam(ctx
->radeon_bld
.main_fn
,
532 ctx
->param_tes_patch_id
);
533 case PIPE_SHADER_GEOMETRY
:
534 return LLVMGetParam(ctx
->radeon_bld
.main_fn
,
535 SI_PARAM_PRIMITIVE_ID
);
538 return bld_base
->uint_bld
.zero
;
543 * Return the value of tgsi_ind_register for indexing.
544 * This is the indirect index with the constant offset added to it.
546 static LLVMValueRef
get_indirect_index(struct si_shader_context
*ctx
,
547 const struct tgsi_ind_register
*ind
,
550 struct gallivm_state
*gallivm
= ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
553 result
= ctx
->radeon_bld
.soa
.addr
[ind
->Index
][ind
->Swizzle
];
554 result
= LLVMBuildLoad(gallivm
->builder
, result
, "");
555 result
= LLVMBuildAdd(gallivm
->builder
, result
,
556 lp_build_const_int32(gallivm
, rel_index
), "");
561 * Like get_indirect_index, but restricts the return value to a (possibly
562 * undefined) value inside [0..num).
564 static LLVMValueRef
get_bounded_indirect_index(struct si_shader_context
*ctx
,
565 const struct tgsi_ind_register
*ind
,
566 int rel_index
, unsigned num
)
568 LLVMValueRef result
= get_indirect_index(ctx
, ind
, rel_index
);
570 /* LLVM 3.8: If indirect resource indexing is used:
574 if (HAVE_LLVM
<= 0x0308)
575 return LLVMGetUndef(ctx
->i32
);
577 return radeon_llvm_bound_index(&ctx
->radeon_bld
, result
, num
);
582 * Calculate a dword address given an input or output register and a stride.
584 static LLVMValueRef
get_dw_address(struct si_shader_context
*ctx
,
585 const struct tgsi_full_dst_register
*dst
,
586 const struct tgsi_full_src_register
*src
,
587 LLVMValueRef vertex_dw_stride
,
588 LLVMValueRef base_addr
)
590 struct gallivm_state
*gallivm
= ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
591 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
592 ubyte
*name
, *index
, *array_first
;
594 struct tgsi_full_dst_register reg
;
596 /* Set the register description. The address computation is the same
597 * for sources and destinations. */
599 reg
.Register
.File
= src
->Register
.File
;
600 reg
.Register
.Index
= src
->Register
.Index
;
601 reg
.Register
.Indirect
= src
->Register
.Indirect
;
602 reg
.Register
.Dimension
= src
->Register
.Dimension
;
603 reg
.Indirect
= src
->Indirect
;
604 reg
.Dimension
= src
->Dimension
;
605 reg
.DimIndirect
= src
->DimIndirect
;
609 /* If the register is 2-dimensional (e.g. an array of vertices
610 * in a primitive), calculate the base address of the vertex. */
611 if (reg
.Register
.Dimension
) {
614 if (reg
.Dimension
.Indirect
)
615 index
= get_indirect_index(ctx
, ®
.DimIndirect
,
616 reg
.Dimension
.Index
);
618 index
= lp_build_const_int32(gallivm
, reg
.Dimension
.Index
);
620 base_addr
= LLVMBuildAdd(gallivm
->builder
, base_addr
,
621 LLVMBuildMul(gallivm
->builder
, index
,
622 vertex_dw_stride
, ""), "");
625 /* Get information about the register. */
626 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
627 name
= info
->input_semantic_name
;
628 index
= info
->input_semantic_index
;
629 array_first
= info
->input_array_first
;
630 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
631 name
= info
->output_semantic_name
;
632 index
= info
->output_semantic_index
;
633 array_first
= info
->output_array_first
;
639 if (reg
.Register
.Indirect
) {
640 /* Add the relative address of the element. */
641 LLVMValueRef ind_index
;
643 if (reg
.Indirect
.ArrayID
)
644 first
= array_first
[reg
.Indirect
.ArrayID
];
646 first
= reg
.Register
.Index
;
648 ind_index
= get_indirect_index(ctx
, ®
.Indirect
,
649 reg
.Register
.Index
- first
);
651 base_addr
= LLVMBuildAdd(gallivm
->builder
, base_addr
,
652 LLVMBuildMul(gallivm
->builder
, ind_index
,
653 lp_build_const_int32(gallivm
, 4), ""), "");
655 param
= si_shader_io_get_unique_index(name
[first
], index
[first
]);
657 param
= si_shader_io_get_unique_index(name
[reg
.Register
.Index
],
658 index
[reg
.Register
.Index
]);
661 /* Add the base address of the element. */
662 return LLVMBuildAdd(gallivm
->builder
, base_addr
,
663 lp_build_const_int32(gallivm
, param
* 4), "");
666 /* The offchip buffer layout for TCS->TES is
668 * - attribute 0 of patch 0 vertex 0
669 * - attribute 0 of patch 0 vertex 1
670 * - attribute 0 of patch 0 vertex 2
672 * - attribute 0 of patch 1 vertex 0
673 * - attribute 0 of patch 1 vertex 1
675 * - attribute 1 of patch 0 vertex 0
676 * - attribute 1 of patch 0 vertex 1
678 * - per patch attribute 0 of patch 0
679 * - per patch attribute 0 of patch 1
682 * Note that every attribute has 4 components.
684 static LLVMValueRef
get_tcs_tes_buffer_address(struct si_shader_context
*ctx
,
685 LLVMValueRef vertex_index
,
686 LLVMValueRef param_index
)
688 struct gallivm_state
*gallivm
= ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
689 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
, total_vertices
;
690 LLVMValueRef param_stride
, constant16
;
692 vertices_per_patch
= unpack_param(ctx
, SI_PARAM_TCS_OFFCHIP_LAYOUT
, 9, 6);
693 num_patches
= unpack_param(ctx
, SI_PARAM_TCS_OFFCHIP_LAYOUT
, 0, 9);
694 total_vertices
= LLVMBuildMul(gallivm
->builder
, vertices_per_patch
,
697 constant16
= lp_build_const_int32(gallivm
, 16);
699 base_addr
= LLVMBuildMul(gallivm
->builder
, get_rel_patch_id(ctx
),
700 vertices_per_patch
, "");
702 base_addr
= LLVMBuildAdd(gallivm
->builder
, base_addr
,
705 param_stride
= total_vertices
;
707 base_addr
= get_rel_patch_id(ctx
);
708 param_stride
= num_patches
;
711 base_addr
= LLVMBuildAdd(gallivm
->builder
, base_addr
,
712 LLVMBuildMul(gallivm
->builder
, param_index
,
713 param_stride
, ""), "");
715 base_addr
= LLVMBuildMul(gallivm
->builder
, base_addr
, constant16
, "");
718 LLVMValueRef patch_data_offset
=
719 unpack_param(ctx
, SI_PARAM_TCS_OFFCHIP_LAYOUT
, 16, 16);
721 base_addr
= LLVMBuildAdd(gallivm
->builder
, base_addr
,
722 patch_data_offset
, "");
727 static LLVMValueRef
get_tcs_tes_buffer_address_from_reg(
728 struct si_shader_context
*ctx
,
729 const struct tgsi_full_dst_register
*dst
,
730 const struct tgsi_full_src_register
*src
)
732 struct gallivm_state
*gallivm
= ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
733 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
734 ubyte
*name
, *index
, *array_first
;
735 struct tgsi_full_src_register reg
;
736 LLVMValueRef vertex_index
= NULL
;
737 LLVMValueRef param_index
= NULL
;
738 unsigned param_index_base
, param_base
;
740 reg
= src
? *src
: tgsi_full_src_register_from_dst(dst
);
742 if (reg
.Register
.Dimension
) {
744 if (reg
.Dimension
.Indirect
)
745 vertex_index
= get_indirect_index(ctx
, ®
.DimIndirect
,
746 reg
.Dimension
.Index
);
748 vertex_index
= lp_build_const_int32(gallivm
,
749 reg
.Dimension
.Index
);
752 /* Get information about the register. */
753 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
754 name
= info
->input_semantic_name
;
755 index
= info
->input_semantic_index
;
756 array_first
= info
->input_array_first
;
757 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
758 name
= info
->output_semantic_name
;
759 index
= info
->output_semantic_index
;
760 array_first
= info
->output_array_first
;
766 if (reg
.Register
.Indirect
) {
767 if (reg
.Indirect
.ArrayID
)
768 param_base
= array_first
[reg
.Indirect
.ArrayID
];
770 param_base
= reg
.Register
.Index
;
772 param_index
= get_indirect_index(ctx
, ®
.Indirect
,
773 reg
.Register
.Index
- param_base
);
776 param_base
= reg
.Register
.Index
;
777 param_index
= lp_build_const_int32(gallivm
, 0);
780 param_index_base
= si_shader_io_get_unique_index(name
[param_base
],
783 param_index
= LLVMBuildAdd(gallivm
->builder
, param_index
,
784 lp_build_const_int32(gallivm
, param_index_base
),
787 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
790 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
791 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
792 * or v4i32 (num_channels=3,4). */
793 static void build_tbuffer_store(struct si_shader_context
*ctx
,
796 unsigned num_channels
,
798 LLVMValueRef soffset
,
799 unsigned inst_offset
,
808 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
809 LLVMValueRef args
[] = {
812 LLVMConstInt(ctx
->i32
, num_channels
, 0),
815 LLVMConstInt(ctx
->i32
, inst_offset
, 0),
816 LLVMConstInt(ctx
->i32
, dfmt
, 0),
817 LLVMConstInt(ctx
->i32
, nfmt
, 0),
818 LLVMConstInt(ctx
->i32
, offen
, 0),
819 LLVMConstInt(ctx
->i32
, idxen
, 0),
820 LLVMConstInt(ctx
->i32
, glc
, 0),
821 LLVMConstInt(ctx
->i32
, slc
, 0),
822 LLVMConstInt(ctx
->i32
, tfe
, 0)
825 /* The instruction offset field has 12 bits */
826 assert(offen
|| inst_offset
< (1 << 12));
828 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
829 unsigned func
= CLAMP(num_channels
, 1, 3) - 1;
830 const char *types
[] = {"i32", "v2i32", "v4i32"};
832 snprintf(name
, sizeof(name
), "llvm.SI.tbuffer.store.%s", types
[func
]);
834 lp_build_intrinsic(gallivm
->builder
, name
, ctx
->voidt
,
835 args
, ARRAY_SIZE(args
), 0);
838 static void build_tbuffer_store_dwords(struct si_shader_context
*ctx
,
841 unsigned num_channels
,
843 LLVMValueRef soffset
,
844 unsigned inst_offset
)
846 static unsigned dfmt
[] = {
847 V_008F0C_BUF_DATA_FORMAT_32
,
848 V_008F0C_BUF_DATA_FORMAT_32_32
,
849 V_008F0C_BUF_DATA_FORMAT_32_32_32
,
850 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
852 assert(num_channels
>= 1 && num_channels
<= 4);
854 build_tbuffer_store(ctx
, rsrc
, vdata
, num_channels
, vaddr
, soffset
,
855 inst_offset
, dfmt
[num_channels
-1],
856 V_008F0C_BUF_NUM_FORMAT_UINT
, 1, 0, 1, 1, 0);
859 static LLVMValueRef
build_buffer_load(struct si_shader_context
*ctx
,
863 LLVMValueRef voffset
,
864 LLVMValueRef soffset
,
865 unsigned inst_offset
,
869 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
870 unsigned func
= CLAMP(num_channels
, 1, 3) - 1;
872 if (HAVE_LLVM
>= 0x309) {
873 LLVMValueRef args
[] = {
874 LLVMBuildBitCast(gallivm
->builder
, rsrc
, ctx
->v4i32
, ""),
875 vindex
? vindex
: LLVMConstInt(ctx
->i32
, 0, 0),
876 LLVMConstInt(ctx
->i32
, inst_offset
, 0),
877 LLVMConstInt(ctx
->i1
, glc
, 0),
878 LLVMConstInt(ctx
->i1
, slc
, 0)
881 LLVMTypeRef types
[] = {ctx
->f32
, LLVMVectorType(ctx
->f32
, 2),
883 const char *type_names
[] = {"f32", "v2f32", "v4f32"};
887 args
[2] = LLVMBuildAdd(gallivm
->builder
, args
[2], voffset
,
892 args
[2] = LLVMBuildAdd(gallivm
->builder
, args
[2], soffset
,
896 snprintf(name
, sizeof(name
), "llvm.amdgcn.buffer.load.%s",
899 return lp_build_intrinsic(gallivm
->builder
, name
, types
[func
], args
,
900 ARRAY_SIZE(args
), LLVMReadOnlyAttribute
);
902 LLVMValueRef args
[] = {
903 LLVMBuildBitCast(gallivm
->builder
, rsrc
, ctx
->v16i8
, ""),
904 voffset
? voffset
: vindex
,
906 LLVMConstInt(ctx
->i32
, inst_offset
, 0),
907 LLVMConstInt(ctx
->i32
, voffset
? 1 : 0, 0), // offen
908 LLVMConstInt(ctx
->i32
, vindex
? 1 : 0, 0), //idxen
909 LLVMConstInt(ctx
->i32
, glc
, 0),
910 LLVMConstInt(ctx
->i32
, slc
, 0),
911 LLVMConstInt(ctx
->i32
, 0, 0), // TFE
914 LLVMTypeRef types
[] = {ctx
->i32
, LLVMVectorType(ctx
->i32
, 2),
916 const char *type_names
[] = {"i32", "v2i32", "v4i32"};
917 const char *arg_type
= "i32";
920 if (voffset
&& vindex
) {
921 LLVMValueRef vaddr
[] = {vindex
, voffset
};
924 args
[1] = lp_build_gather_values(gallivm
, vaddr
, 2);
927 snprintf(name
, sizeof(name
), "llvm.SI.buffer.load.dword.%s.%s",
928 type_names
[func
], arg_type
);
930 return lp_build_intrinsic(gallivm
->builder
, name
, types
[func
], args
,
931 ARRAY_SIZE(args
), LLVMReadOnlyAttribute
);
935 static LLVMValueRef
buffer_load(struct lp_build_tgsi_context
*bld_base
,
936 enum tgsi_opcode_type type
, unsigned swizzle
,
937 LLVMValueRef buffer
, LLVMValueRef offset
,
940 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
941 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
942 LLVMValueRef value
, value2
;
943 LLVMTypeRef llvm_type
= tgsi2llvmtype(bld_base
, type
);
944 LLVMTypeRef vec_type
= LLVMVectorType(llvm_type
, 4);
947 value
= build_buffer_load(ctx
, buffer
, 4, NULL
, base
, offset
,
950 return LLVMBuildBitCast(gallivm
->builder
, value
, vec_type
, "");
953 if (!tgsi_type_is_64bit(type
)) {
954 value
= build_buffer_load(ctx
, buffer
, 4, NULL
, base
, offset
,
957 value
= LLVMBuildBitCast(gallivm
->builder
, value
, vec_type
, "");
958 return LLVMBuildExtractElement(gallivm
->builder
, value
,
959 lp_build_const_int32(gallivm
, swizzle
), "");
962 value
= build_buffer_load(ctx
, buffer
, 1, NULL
, base
, offset
,
965 value2
= build_buffer_load(ctx
, buffer
, 1, NULL
, base
, offset
,
966 swizzle
* 4 + 4, 1, 0);
968 return radeon_llvm_emit_fetch_64bit(bld_base
, type
, value
, value2
);
974 * \param type output value type
975 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
976 * \param dw_addr address in dwords
978 static LLVMValueRef
lds_load(struct lp_build_tgsi_context
*bld_base
,
979 enum tgsi_opcode_type type
, unsigned swizzle
,
980 LLVMValueRef dw_addr
)
982 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
983 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
987 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
989 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++)
990 values
[chan
] = lds_load(bld_base
, type
, chan
, dw_addr
);
992 return lp_build_gather_values(bld_base
->base
.gallivm
, values
,
996 dw_addr
= lp_build_add(&bld_base
->uint_bld
, dw_addr
,
997 lp_build_const_int32(gallivm
, swizzle
));
999 value
= build_indexed_load(ctx
, ctx
->lds
, dw_addr
, false);
1000 if (tgsi_type_is_64bit(type
)) {
1001 LLVMValueRef value2
;
1002 dw_addr
= lp_build_add(&bld_base
->uint_bld
, dw_addr
,
1003 lp_build_const_int32(gallivm
, swizzle
+ 1));
1004 value2
= build_indexed_load(ctx
, ctx
->lds
, dw_addr
, false);
1005 return radeon_llvm_emit_fetch_64bit(bld_base
, type
, value
, value2
);
1008 return LLVMBuildBitCast(gallivm
->builder
, value
,
1009 tgsi2llvmtype(bld_base
, type
), "");
1015 * \param swizzle offset (typically 0..3)
1016 * \param dw_addr address in dwords
1017 * \param value value to store
1019 static void lds_store(struct lp_build_tgsi_context
*bld_base
,
1020 unsigned swizzle
, LLVMValueRef dw_addr
,
1023 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1024 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1026 dw_addr
= lp_build_add(&bld_base
->uint_bld
, dw_addr
,
1027 lp_build_const_int32(gallivm
, swizzle
));
1029 value
= LLVMBuildBitCast(gallivm
->builder
, value
, ctx
->i32
, "");
1030 build_indexed_store(ctx
, ctx
->lds
,
1034 static LLVMValueRef
fetch_input_tcs(
1035 struct lp_build_tgsi_context
*bld_base
,
1036 const struct tgsi_full_src_register
*reg
,
1037 enum tgsi_opcode_type type
, unsigned swizzle
)
1039 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1040 LLVMValueRef dw_addr
, stride
;
1042 stride
= unpack_param(ctx
, SI_PARAM_TCS_IN_LAYOUT
, 13, 8);
1043 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1044 dw_addr
= get_dw_address(ctx
, NULL
, reg
, stride
, dw_addr
);
1046 return lds_load(bld_base
, type
, swizzle
, dw_addr
);
1049 static LLVMValueRef
fetch_output_tcs(
1050 struct lp_build_tgsi_context
*bld_base
,
1051 const struct tgsi_full_src_register
*reg
,
1052 enum tgsi_opcode_type type
, unsigned swizzle
)
1054 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1055 LLVMValueRef dw_addr
, stride
;
1057 if (reg
->Register
.Dimension
) {
1058 stride
= unpack_param(ctx
, SI_PARAM_TCS_OUT_LAYOUT
, 13, 8);
1059 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1060 dw_addr
= get_dw_address(ctx
, NULL
, reg
, stride
, dw_addr
);
1062 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1063 dw_addr
= get_dw_address(ctx
, NULL
, reg
, NULL
, dw_addr
);
1066 return lds_load(bld_base
, type
, swizzle
, dw_addr
);
1069 static LLVMValueRef
fetch_input_tes(
1070 struct lp_build_tgsi_context
*bld_base
,
1071 const struct tgsi_full_src_register
*reg
,
1072 enum tgsi_opcode_type type
, unsigned swizzle
)
1074 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1075 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1076 LLVMValueRef rw_buffers
, buffer
, base
, addr
;
1078 rw_buffers
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
1079 SI_PARAM_RW_BUFFERS
);
1080 buffer
= build_indexed_load_const(ctx
, rw_buffers
,
1081 lp_build_const_int32(gallivm
, SI_HS_RING_TESS_OFFCHIP
));
1083 base
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, ctx
->param_oc_lds
);
1084 addr
= get_tcs_tes_buffer_address_from_reg(ctx
, NULL
, reg
);
1086 return buffer_load(bld_base
, type
, swizzle
, buffer
, base
, addr
);
1089 static void store_output_tcs(struct lp_build_tgsi_context
*bld_base
,
1090 const struct tgsi_full_instruction
*inst
,
1091 const struct tgsi_opcode_info
*info
,
1092 LLVMValueRef dst
[4])
1094 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1095 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1096 const struct tgsi_full_dst_register
*reg
= &inst
->Dst
[0];
1097 unsigned chan_index
;
1098 LLVMValueRef dw_addr
, stride
;
1099 LLVMValueRef rw_buffers
, buffer
, base
, buf_addr
;
1100 LLVMValueRef values
[4];
1102 /* Only handle per-patch and per-vertex outputs here.
1103 * Vectors will be lowered to scalars and this function will be called again.
1105 if (reg
->Register
.File
!= TGSI_FILE_OUTPUT
||
1106 (dst
[0] && LLVMGetTypeKind(LLVMTypeOf(dst
[0])) == LLVMVectorTypeKind
)) {
1107 radeon_llvm_emit_store(bld_base
, inst
, info
, dst
);
1111 if (reg
->Register
.Dimension
) {
1112 stride
= unpack_param(ctx
, SI_PARAM_TCS_OUT_LAYOUT
, 13, 8);
1113 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1114 dw_addr
= get_dw_address(ctx
, reg
, NULL
, stride
, dw_addr
);
1116 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1117 dw_addr
= get_dw_address(ctx
, reg
, NULL
, NULL
, dw_addr
);
1120 rw_buffers
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
1121 SI_PARAM_RW_BUFFERS
);
1122 buffer
= build_indexed_load_const(ctx
, rw_buffers
,
1123 lp_build_const_int32(gallivm
, SI_HS_RING_TESS_OFFCHIP
));
1125 base
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, ctx
->param_oc_lds
);
1126 buf_addr
= get_tcs_tes_buffer_address_from_reg(ctx
, reg
, NULL
);
1129 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst
, chan_index
) {
1130 LLVMValueRef value
= dst
[chan_index
];
1132 if (inst
->Instruction
.Saturate
)
1133 value
= radeon_llvm_saturate(bld_base
, value
);
1135 lds_store(bld_base
, chan_index
, dw_addr
, value
);
1137 value
= LLVMBuildBitCast(gallivm
->builder
, value
, ctx
->i32
, "");
1138 values
[chan_index
] = value
;
1140 if (inst
->Dst
[0].Register
.WriteMask
!= 0xF) {
1141 build_tbuffer_store_dwords(ctx
, buffer
, value
, 1,
1147 if (inst
->Dst
[0].Register
.WriteMask
== 0xF) {
1148 LLVMValueRef value
= lp_build_gather_values(bld_base
->base
.gallivm
,
1150 build_tbuffer_store_dwords(ctx
, buffer
, value
, 4, buf_addr
,
1155 static LLVMValueRef
fetch_input_gs(
1156 struct lp_build_tgsi_context
*bld_base
,
1157 const struct tgsi_full_src_register
*reg
,
1158 enum tgsi_opcode_type type
,
1161 struct lp_build_context
*base
= &bld_base
->base
;
1162 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1163 struct si_shader
*shader
= ctx
->shader
;
1164 struct lp_build_context
*uint
= &ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
1165 struct gallivm_state
*gallivm
= base
->gallivm
;
1166 LLVMValueRef vtx_offset
;
1167 LLVMValueRef args
[9];
1168 unsigned vtx_offset_param
;
1169 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1170 unsigned semantic_name
= info
->input_semantic_name
[reg
->Register
.Index
];
1171 unsigned semantic_index
= info
->input_semantic_index
[reg
->Register
.Index
];
1175 if (swizzle
!= ~0 && semantic_name
== TGSI_SEMANTIC_PRIMID
)
1176 return get_primitive_id(bld_base
, swizzle
);
1178 if (!reg
->Register
.Dimension
)
1181 if (swizzle
== ~0) {
1182 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
1184 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1185 values
[chan
] = fetch_input_gs(bld_base
, reg
, type
, chan
);
1187 return lp_build_gather_values(bld_base
->base
.gallivm
, values
,
1191 /* Get the vertex offset parameter */
1192 vtx_offset_param
= reg
->Dimension
.Index
;
1193 if (vtx_offset_param
< 2) {
1194 vtx_offset_param
+= SI_PARAM_VTX0_OFFSET
;
1196 assert(vtx_offset_param
< 6);
1197 vtx_offset_param
+= SI_PARAM_VTX2_OFFSET
- 2;
1199 vtx_offset
= lp_build_mul_imm(uint
,
1200 LLVMGetParam(ctx
->radeon_bld
.main_fn
,
1204 param
= si_shader_io_get_unique_index(semantic_name
, semantic_index
);
1205 args
[0] = ctx
->esgs_ring
;
1206 args
[1] = vtx_offset
;
1207 args
[2] = lp_build_const_int32(gallivm
, (param
* 4 + swizzle
) * 256);
1208 args
[3] = uint
->zero
;
1209 args
[4] = uint
->one
; /* OFFEN */
1210 args
[5] = uint
->zero
; /* IDXEN */
1211 args
[6] = uint
->one
; /* GLC */
1212 args
[7] = uint
->zero
; /* SLC */
1213 args
[8] = uint
->zero
; /* TFE */
1215 value
= lp_build_intrinsic(gallivm
->builder
,
1216 "llvm.SI.buffer.load.dword.i32.i32",
1218 LLVMReadOnlyAttribute
);
1219 if (tgsi_type_is_64bit(type
)) {
1220 LLVMValueRef value2
;
1221 args
[2] = lp_build_const_int32(gallivm
, (param
* 4 + swizzle
+ 1) * 256);
1222 value2
= lp_build_intrinsic(gallivm
->builder
,
1223 "llvm.SI.buffer.load.dword.i32.i32",
1225 LLVMReadOnlyAttribute
);
1226 return radeon_llvm_emit_fetch_64bit(bld_base
, type
,
1229 return LLVMBuildBitCast(gallivm
->builder
,
1231 tgsi2llvmtype(bld_base
, type
), "");
1234 static int lookup_interp_param_index(unsigned interpolate
, unsigned location
)
1236 switch (interpolate
) {
1237 case TGSI_INTERPOLATE_CONSTANT
:
1240 case TGSI_INTERPOLATE_LINEAR
:
1241 if (location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
1242 return SI_PARAM_LINEAR_SAMPLE
;
1243 else if (location
== TGSI_INTERPOLATE_LOC_CENTROID
)
1244 return SI_PARAM_LINEAR_CENTROID
;
1246 return SI_PARAM_LINEAR_CENTER
;
1248 case TGSI_INTERPOLATE_COLOR
:
1249 case TGSI_INTERPOLATE_PERSPECTIVE
:
1250 if (location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
1251 return SI_PARAM_PERSP_SAMPLE
;
1252 else if (location
== TGSI_INTERPOLATE_LOC_CENTROID
)
1253 return SI_PARAM_PERSP_CENTROID
;
1255 return SI_PARAM_PERSP_CENTER
;
1258 fprintf(stderr
, "Warning: Unhandled interpolation mode.\n");
1263 /* This shouldn't be used by explicit INTERP opcodes. */
1264 static unsigned select_interp_param(struct si_shader_context
*ctx
,
1267 if (!ctx
->is_monolithic
)
1270 if (ctx
->shader
->key
.ps
.prolog
.force_persp_sample_interp
) {
1272 case SI_PARAM_PERSP_CENTROID
:
1273 case SI_PARAM_PERSP_CENTER
:
1274 return SI_PARAM_PERSP_SAMPLE
;
1277 if (ctx
->shader
->key
.ps
.prolog
.force_linear_sample_interp
) {
1279 case SI_PARAM_LINEAR_CENTROID
:
1280 case SI_PARAM_LINEAR_CENTER
:
1281 return SI_PARAM_LINEAR_SAMPLE
;
1284 if (ctx
->shader
->key
.ps
.prolog
.force_persp_center_interp
) {
1286 case SI_PARAM_PERSP_CENTROID
:
1287 case SI_PARAM_PERSP_SAMPLE
:
1288 return SI_PARAM_PERSP_CENTER
;
1291 if (ctx
->shader
->key
.ps
.prolog
.force_linear_center_interp
) {
1293 case SI_PARAM_LINEAR_CENTROID
:
1294 case SI_PARAM_LINEAR_SAMPLE
:
1295 return SI_PARAM_LINEAR_CENTER
;
1303 * Interpolate a fragment shader input.
1305 * @param ctx context
1306 * @param input_index index of the input in hardware
1307 * @param semantic_name TGSI_SEMANTIC_*
1308 * @param semantic_index semantic index
1309 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1310 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1311 * @param interp_param interpolation weights (i,j)
1312 * @param prim_mask SI_PARAM_PRIM_MASK
1313 * @param face SI_PARAM_FRONT_FACE
1314 * @param result the return value (4 components)
1316 static void interp_fs_input(struct si_shader_context
*ctx
,
1317 unsigned input_index
,
1318 unsigned semantic_name
,
1319 unsigned semantic_index
,
1320 unsigned num_interp_inputs
,
1321 unsigned colors_read_mask
,
1322 LLVMValueRef interp_param
,
1323 LLVMValueRef prim_mask
,
1325 LLVMValueRef result
[4])
1327 struct lp_build_context
*base
= &ctx
->radeon_bld
.soa
.bld_base
.base
;
1328 struct lp_build_context
*uint
= &ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
1329 struct gallivm_state
*gallivm
= base
->gallivm
;
1330 const char *intr_name
;
1331 LLVMValueRef attr_number
;
1335 attr_number
= lp_build_const_int32(gallivm
, input_index
);
1337 /* fs.constant returns the param from the middle vertex, so it's not
1338 * really useful for flat shading. It's meant to be used for custom
1339 * interpolation (but the intrinsic can't fetch from the other two
1342 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1343 * to do the right thing. The only reason we use fs.constant is that
1344 * fs.interp cannot be used on integers, because they can be equal
1347 intr_name
= interp_param
? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
1349 if (semantic_name
== TGSI_SEMANTIC_COLOR
&&
1350 ctx
->shader
->key
.ps
.prolog
.color_two_side
) {
1351 LLVMValueRef args
[4];
1352 LLVMValueRef is_face_positive
;
1353 LLVMValueRef back_attr_number
;
1355 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1356 * otherwise it's at offset "num_inputs".
1358 unsigned back_attr_offset
= num_interp_inputs
;
1359 if (semantic_index
== 1 && colors_read_mask
& 0xf)
1360 back_attr_offset
+= 1;
1362 back_attr_number
= lp_build_const_int32(gallivm
, back_attr_offset
);
1364 is_face_positive
= LLVMBuildICmp(gallivm
->builder
, LLVMIntNE
,
1365 face
, uint
->zero
, "");
1367 args
[2] = prim_mask
;
1368 args
[3] = interp_param
;
1369 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1370 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
1371 LLVMValueRef front
, back
;
1373 args
[0] = llvm_chan
;
1374 args
[1] = attr_number
;
1375 front
= lp_build_intrinsic(gallivm
->builder
, intr_name
,
1376 ctx
->f32
, args
, args
[3] ? 4 : 3,
1377 LLVMReadNoneAttribute
);
1379 args
[1] = back_attr_number
;
1380 back
= lp_build_intrinsic(gallivm
->builder
, intr_name
,
1381 ctx
->f32
, args
, args
[3] ? 4 : 3,
1382 LLVMReadNoneAttribute
);
1384 result
[chan
] = LLVMBuildSelect(gallivm
->builder
,
1390 } else if (semantic_name
== TGSI_SEMANTIC_FOG
) {
1391 LLVMValueRef args
[4];
1393 args
[0] = uint
->zero
;
1394 args
[1] = attr_number
;
1395 args
[2] = prim_mask
;
1396 args
[3] = interp_param
;
1397 result
[0] = lp_build_intrinsic(gallivm
->builder
, intr_name
,
1398 ctx
->f32
, args
, args
[3] ? 4 : 3,
1399 LLVMReadNoneAttribute
);
1401 result
[2] = lp_build_const_float(gallivm
, 0.0f
);
1402 result
[3] = lp_build_const_float(gallivm
, 1.0f
);
1404 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1405 LLVMValueRef args
[4];
1406 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
1408 args
[0] = llvm_chan
;
1409 args
[1] = attr_number
;
1410 args
[2] = prim_mask
;
1411 args
[3] = interp_param
;
1412 result
[chan
] = lp_build_intrinsic(gallivm
->builder
, intr_name
,
1413 ctx
->f32
, args
, args
[3] ? 4 : 3,
1414 LLVMReadNoneAttribute
);
1419 /* LLVMGetParam with bc_optimize resolved. */
1420 static LLVMValueRef
get_interp_param(struct si_shader_context
*ctx
,
1421 int interp_param_idx
)
1423 LLVMBuilderRef builder
= ctx
->radeon_bld
.gallivm
.builder
;
1424 LLVMValueRef main_fn
= ctx
->radeon_bld
.main_fn
;
1425 LLVMValueRef param
= NULL
;
1427 /* Handle PRIM_MASK[31] (bc_optimize). */
1428 if (ctx
->is_monolithic
&&
1429 ((ctx
->shader
->key
.ps
.prolog
.bc_optimize_for_persp
&&
1430 interp_param_idx
== SI_PARAM_PERSP_CENTROID
) ||
1431 (ctx
->shader
->key
.ps
.prolog
.bc_optimize_for_linear
&&
1432 interp_param_idx
== SI_PARAM_LINEAR_CENTROID
))) {
1433 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
1434 * The hw doesn't compute CENTROID if the whole wave only
1435 * contains fully-covered quads.
1437 LLVMValueRef bc_optimize
=
1438 LLVMGetParam(main_fn
, SI_PARAM_PRIM_MASK
);
1439 bc_optimize
= LLVMBuildLShr(builder
,
1441 LLVMConstInt(ctx
->i32
, 31, 0), "");
1442 bc_optimize
= LLVMBuildTrunc(builder
, bc_optimize
, ctx
->i1
, "");
1444 if (ctx
->shader
->key
.ps
.prolog
.bc_optimize_for_persp
&&
1445 interp_param_idx
== SI_PARAM_PERSP_CENTROID
) {
1446 param
= LLVMBuildSelect(builder
, bc_optimize
,
1447 LLVMGetParam(main_fn
,
1448 SI_PARAM_PERSP_CENTER
),
1449 LLVMGetParam(main_fn
,
1450 SI_PARAM_PERSP_CENTROID
),
1453 if (ctx
->shader
->key
.ps
.prolog
.bc_optimize_for_linear
&&
1454 interp_param_idx
== SI_PARAM_LINEAR_CENTROID
) {
1455 param
= LLVMBuildSelect(builder
, bc_optimize
,
1456 LLVMGetParam(main_fn
,
1457 SI_PARAM_LINEAR_CENTER
),
1458 LLVMGetParam(main_fn
,
1459 SI_PARAM_LINEAR_CENTROID
),
1465 param
= LLVMGetParam(main_fn
, interp_param_idx
);
1469 static void declare_input_fs(
1470 struct radeon_llvm_context
*radeon_bld
,
1471 unsigned input_index
,
1472 const struct tgsi_full_declaration
*decl
)
1474 struct lp_build_context
*base
= &radeon_bld
->soa
.bld_base
.base
;
1475 struct si_shader_context
*ctx
=
1476 si_shader_context(&radeon_bld
->soa
.bld_base
);
1477 struct si_shader
*shader
= ctx
->shader
;
1478 LLVMValueRef main_fn
= radeon_bld
->main_fn
;
1479 LLVMValueRef interp_param
= NULL
;
1480 int interp_param_idx
;
1482 /* Get colors from input VGPRs (set by the prolog). */
1483 if (!ctx
->is_monolithic
&&
1484 decl
->Semantic
.Name
== TGSI_SEMANTIC_COLOR
) {
1485 unsigned i
= decl
->Semantic
.Index
;
1486 unsigned colors_read
= shader
->selector
->info
.colors_read
;
1487 unsigned mask
= colors_read
>> (i
* 4);
1488 unsigned offset
= SI_PARAM_POS_FIXED_PT
+ 1 +
1489 (i
? util_bitcount(colors_read
& 0xf) : 0);
1491 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 0)] =
1492 mask
& 0x1 ? LLVMGetParam(main_fn
, offset
++) : base
->undef
;
1493 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 1)] =
1494 mask
& 0x2 ? LLVMGetParam(main_fn
, offset
++) : base
->undef
;
1495 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 2)] =
1496 mask
& 0x4 ? LLVMGetParam(main_fn
, offset
++) : base
->undef
;
1497 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 3)] =
1498 mask
& 0x8 ? LLVMGetParam(main_fn
, offset
++) : base
->undef
;
1502 interp_param_idx
= lookup_interp_param_index(decl
->Interp
.Interpolate
,
1503 decl
->Interp
.Location
);
1504 if (interp_param_idx
== -1)
1506 else if (interp_param_idx
) {
1507 interp_param_idx
= select_interp_param(ctx
,
1509 interp_param
= get_interp_param(ctx
, interp_param_idx
);
1512 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_COLOR
&&
1513 decl
->Interp
.Interpolate
== TGSI_INTERPOLATE_COLOR
&&
1514 ctx
->shader
->key
.ps
.prolog
.flatshade_colors
)
1515 interp_param
= NULL
; /* load the constant color */
1517 interp_fs_input(ctx
, input_index
, decl
->Semantic
.Name
,
1518 decl
->Semantic
.Index
, shader
->selector
->info
.num_inputs
,
1519 shader
->selector
->info
.colors_read
, interp_param
,
1520 LLVMGetParam(main_fn
, SI_PARAM_PRIM_MASK
),
1521 LLVMGetParam(main_fn
, SI_PARAM_FRONT_FACE
),
1522 &radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 0)]);
1525 static LLVMValueRef
get_sample_id(struct radeon_llvm_context
*radeon_bld
)
1527 return unpack_param(si_shader_context(&radeon_bld
->soa
.bld_base
),
1528 SI_PARAM_ANCILLARY
, 8, 4);
1532 * Set range metadata on an instruction. This can only be used on load and
1533 * call instructions. If you know an instruction can only produce the values
1534 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1535 * \p lo is the minimum value inclusive.
1536 * \p hi is the maximum value exclusive.
1538 static void set_range_metadata(struct si_shader_context
*ctx
,
1539 LLVMValueRef value
, unsigned lo
, unsigned hi
)
1541 LLVMValueRef range_md
, md_args
[2];
1542 LLVMTypeRef type
= LLVMTypeOf(value
);
1543 LLVMContextRef context
= LLVMGetTypeContext(type
);
1545 md_args
[0] = LLVMConstInt(type
, lo
, false);
1546 md_args
[1] = LLVMConstInt(type
, hi
, false);
1547 range_md
= LLVMMDNodeInContext(context
, md_args
, 2);
1548 LLVMSetMetadata(value
, ctx
->range_md_kind
, range_md
);
1551 static LLVMValueRef
get_thread_id(struct si_shader_context
*ctx
)
1553 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
1556 if (HAVE_LLVM
< 0x0308) {
1557 tid
= lp_build_intrinsic(gallivm
->builder
, "llvm.SI.tid",
1558 ctx
->i32
, NULL
, 0, LLVMReadNoneAttribute
);
1560 LLVMValueRef tid_args
[2];
1561 tid_args
[0] = lp_build_const_int32(gallivm
, 0xffffffff);
1562 tid_args
[1] = lp_build_const_int32(gallivm
, 0);
1563 tid_args
[1] = lp_build_intrinsic(gallivm
->builder
,
1564 "llvm.amdgcn.mbcnt.lo", ctx
->i32
,
1565 tid_args
, 2, LLVMReadNoneAttribute
);
1567 tid
= lp_build_intrinsic(gallivm
->builder
,
1568 "llvm.amdgcn.mbcnt.hi", ctx
->i32
,
1569 tid_args
, 2, LLVMReadNoneAttribute
);
1571 set_range_metadata(ctx
, tid
, 0, 64);
1576 * Load a dword from a constant buffer.
1578 static LLVMValueRef
buffer_load_const(struct si_shader_context
*ctx
,
1579 LLVMValueRef resource
,
1580 LLVMValueRef offset
)
1582 LLVMBuilderRef builder
= ctx
->radeon_bld
.gallivm
.builder
;
1583 LLVMValueRef args
[2] = {resource
, offset
};
1585 return lp_build_intrinsic(builder
, "llvm.SI.load.const", ctx
->f32
, args
, 2,
1586 LLVMReadNoneAttribute
);
1589 static LLVMValueRef
load_sample_position(struct radeon_llvm_context
*radeon_bld
, LLVMValueRef sample_id
)
1591 struct si_shader_context
*ctx
=
1592 si_shader_context(&radeon_bld
->soa
.bld_base
);
1593 struct lp_build_context
*uint_bld
= &radeon_bld
->soa
.bld_base
.uint_bld
;
1594 struct gallivm_state
*gallivm
= &radeon_bld
->gallivm
;
1595 LLVMBuilderRef builder
= gallivm
->builder
;
1596 LLVMValueRef desc
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_RW_BUFFERS
);
1597 LLVMValueRef buf_index
= lp_build_const_int32(gallivm
, SI_PS_CONST_SAMPLE_POSITIONS
);
1598 LLVMValueRef resource
= build_indexed_load_const(ctx
, desc
, buf_index
);
1600 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1601 LLVMValueRef offset0
= lp_build_mul_imm(uint_bld
, sample_id
, 8);
1602 LLVMValueRef offset1
= LLVMBuildAdd(builder
, offset0
, lp_build_const_int32(gallivm
, 4), "");
1604 LLVMValueRef pos
[4] = {
1605 buffer_load_const(ctx
, resource
, offset0
),
1606 buffer_load_const(ctx
, resource
, offset1
),
1607 lp_build_const_float(gallivm
, 0),
1608 lp_build_const_float(gallivm
, 0)
1611 return lp_build_gather_values(gallivm
, pos
, 4);
1614 static void declare_system_value(
1615 struct radeon_llvm_context
*radeon_bld
,
1617 const struct tgsi_full_declaration
*decl
)
1619 struct si_shader_context
*ctx
=
1620 si_shader_context(&radeon_bld
->soa
.bld_base
);
1621 struct lp_build_context
*bld
= &radeon_bld
->soa
.bld_base
.base
;
1622 struct gallivm_state
*gallivm
= &radeon_bld
->gallivm
;
1623 LLVMValueRef value
= 0;
1625 switch (decl
->Semantic
.Name
) {
1626 case TGSI_SEMANTIC_INSTANCEID
:
1627 value
= LLVMGetParam(radeon_bld
->main_fn
,
1628 ctx
->param_instance_id
);
1631 case TGSI_SEMANTIC_VERTEXID
:
1632 value
= LLVMBuildAdd(gallivm
->builder
,
1633 LLVMGetParam(radeon_bld
->main_fn
,
1634 ctx
->param_vertex_id
),
1635 LLVMGetParam(radeon_bld
->main_fn
,
1636 SI_PARAM_BASE_VERTEX
), "");
1639 case TGSI_SEMANTIC_VERTEXID_NOBASE
:
1640 value
= LLVMGetParam(radeon_bld
->main_fn
,
1641 ctx
->param_vertex_id
);
1644 case TGSI_SEMANTIC_BASEVERTEX
:
1645 value
= LLVMGetParam(radeon_bld
->main_fn
,
1646 SI_PARAM_BASE_VERTEX
);
1649 case TGSI_SEMANTIC_BASEINSTANCE
:
1650 value
= LLVMGetParam(radeon_bld
->main_fn
,
1651 SI_PARAM_START_INSTANCE
);
1654 case TGSI_SEMANTIC_DRAWID
:
1655 value
= LLVMGetParam(radeon_bld
->main_fn
,
1659 case TGSI_SEMANTIC_INVOCATIONID
:
1660 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
1661 value
= unpack_param(ctx
, SI_PARAM_REL_IDS
, 8, 5);
1662 else if (ctx
->type
== PIPE_SHADER_GEOMETRY
)
1663 value
= LLVMGetParam(radeon_bld
->main_fn
,
1664 SI_PARAM_GS_INSTANCE_ID
);
1666 assert(!"INVOCATIONID not implemented");
1669 case TGSI_SEMANTIC_POSITION
:
1671 LLVMValueRef pos
[4] = {
1672 LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_POS_X_FLOAT
),
1673 LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_POS_Y_FLOAT
),
1674 LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_POS_Z_FLOAT
),
1675 lp_build_emit_llvm_unary(&radeon_bld
->soa
.bld_base
, TGSI_OPCODE_RCP
,
1676 LLVMGetParam(radeon_bld
->main_fn
,
1677 SI_PARAM_POS_W_FLOAT
)),
1679 value
= lp_build_gather_values(gallivm
, pos
, 4);
1683 case TGSI_SEMANTIC_FACE
:
1684 value
= LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_FRONT_FACE
);
1687 case TGSI_SEMANTIC_SAMPLEID
:
1688 value
= get_sample_id(radeon_bld
);
1691 case TGSI_SEMANTIC_SAMPLEPOS
: {
1692 LLVMValueRef pos
[4] = {
1693 LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_POS_X_FLOAT
),
1694 LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_POS_Y_FLOAT
),
1695 lp_build_const_float(gallivm
, 0),
1696 lp_build_const_float(gallivm
, 0)
1698 pos
[0] = lp_build_emit_llvm_unary(&radeon_bld
->soa
.bld_base
,
1699 TGSI_OPCODE_FRC
, pos
[0]);
1700 pos
[1] = lp_build_emit_llvm_unary(&radeon_bld
->soa
.bld_base
,
1701 TGSI_OPCODE_FRC
, pos
[1]);
1702 value
= lp_build_gather_values(gallivm
, pos
, 4);
1706 case TGSI_SEMANTIC_SAMPLEMASK
:
1707 /* This can only occur with the OpenGL Core profile, which
1708 * doesn't support smoothing.
1710 value
= LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_SAMPLE_COVERAGE
);
1713 case TGSI_SEMANTIC_TESSCOORD
:
1715 LLVMValueRef coord
[4] = {
1716 LLVMGetParam(radeon_bld
->main_fn
, ctx
->param_tes_u
),
1717 LLVMGetParam(radeon_bld
->main_fn
, ctx
->param_tes_v
),
1722 /* For triangles, the vector should be (u, v, 1-u-v). */
1723 if (ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] ==
1724 PIPE_PRIM_TRIANGLES
)
1725 coord
[2] = lp_build_sub(bld
, bld
->one
,
1726 lp_build_add(bld
, coord
[0], coord
[1]));
1728 value
= lp_build_gather_values(gallivm
, coord
, 4);
1732 case TGSI_SEMANTIC_VERTICESIN
:
1733 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
1734 value
= unpack_param(ctx
, SI_PARAM_TCS_OUT_LAYOUT
, 26, 6);
1735 else if (ctx
->type
== PIPE_SHADER_TESS_EVAL
)
1736 value
= unpack_param(ctx
, SI_PARAM_TCS_OFFCHIP_LAYOUT
, 9, 7);
1738 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1741 case TGSI_SEMANTIC_TESSINNER
:
1742 case TGSI_SEMANTIC_TESSOUTER
:
1744 LLVMValueRef rw_buffers
, buffer
, base
, addr
;
1745 int param
= si_shader_io_get_unique_index(decl
->Semantic
.Name
, 0);
1747 rw_buffers
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
1748 SI_PARAM_RW_BUFFERS
);
1749 buffer
= build_indexed_load_const(ctx
, rw_buffers
,
1750 lp_build_const_int32(gallivm
, SI_HS_RING_TESS_OFFCHIP
));
1752 base
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, ctx
->param_oc_lds
);
1753 addr
= get_tcs_tes_buffer_address(ctx
, NULL
,
1754 lp_build_const_int32(gallivm
, param
));
1756 value
= buffer_load(&radeon_bld
->soa
.bld_base
, TGSI_TYPE_FLOAT
,
1757 ~0, buffer
, base
, addr
);
1762 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
:
1763 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
:
1765 LLVMValueRef buf
, slot
, val
[4];
1768 slot
= lp_build_const_int32(gallivm
, SI_HS_CONST_DEFAULT_TESS_LEVELS
);
1769 buf
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_RW_BUFFERS
);
1770 buf
= build_indexed_load_const(ctx
, buf
, slot
);
1771 offset
= decl
->Semantic
.Name
== TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
? 4 : 0;
1773 for (i
= 0; i
< 4; i
++)
1774 val
[i
] = buffer_load_const(ctx
, buf
,
1775 lp_build_const_int32(gallivm
, (offset
+ i
) * 4));
1776 value
= lp_build_gather_values(gallivm
, val
, 4);
1780 case TGSI_SEMANTIC_PRIMID
:
1781 value
= get_primitive_id(&radeon_bld
->soa
.bld_base
, 0);
1784 case TGSI_SEMANTIC_GRID_SIZE
:
1785 value
= LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_GRID_SIZE
);
1788 case TGSI_SEMANTIC_BLOCK_SIZE
:
1790 LLVMValueRef values
[3];
1792 unsigned *properties
= ctx
->shader
->selector
->info
.properties
;
1793 unsigned sizes
[3] = {
1794 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
],
1795 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
],
1796 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
]
1799 for (i
= 0; i
< 3; ++i
)
1800 values
[i
] = lp_build_const_int32(gallivm
, sizes
[i
]);
1802 value
= lp_build_gather_values(gallivm
, values
, 3);
1806 case TGSI_SEMANTIC_BLOCK_ID
:
1807 value
= LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_BLOCK_ID
);
1810 case TGSI_SEMANTIC_THREAD_ID
:
1811 value
= LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_THREAD_ID
);
1814 #if HAVE_LLVM >= 0x0309
1815 case TGSI_SEMANTIC_HELPER_INVOCATION
:
1816 value
= lp_build_intrinsic(gallivm
->builder
,
1817 "llvm.amdgcn.ps.live",
1819 LLVMReadNoneAttribute
);
1820 value
= LLVMBuildNot(gallivm
->builder
, value
, "");
1821 value
= LLVMBuildSExt(gallivm
->builder
, value
, ctx
->i32
, "");
1826 assert(!"unknown system value");
1830 radeon_bld
->system_values
[index
] = value
;
1833 static void declare_compute_memory(struct radeon_llvm_context
*radeon_bld
,
1834 const struct tgsi_full_declaration
*decl
)
1836 struct si_shader_context
*ctx
=
1837 si_shader_context(&radeon_bld
->soa
.bld_base
);
1838 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
1839 struct gallivm_state
*gallivm
= &radeon_bld
->gallivm
;
1841 LLVMTypeRef i8p
= LLVMPointerType(ctx
->i8
, LOCAL_ADDR_SPACE
);
1844 assert(decl
->Declaration
.MemType
== TGSI_MEMORY_TYPE_SHARED
);
1845 assert(decl
->Range
.First
== decl
->Range
.Last
);
1846 assert(!ctx
->shared_memory
);
1848 var
= LLVMAddGlobalInAddressSpace(gallivm
->module
,
1849 LLVMArrayType(ctx
->i8
, sel
->local_size
),
1852 LLVMSetAlignment(var
, 4);
1854 ctx
->shared_memory
= LLVMBuildBitCast(gallivm
->builder
, var
, i8p
, "");
1857 static LLVMValueRef
fetch_constant(
1858 struct lp_build_tgsi_context
*bld_base
,
1859 const struct tgsi_full_src_register
*reg
,
1860 enum tgsi_opcode_type type
,
1863 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1864 struct lp_build_context
*base
= &bld_base
->base
;
1865 const struct tgsi_ind_register
*ireg
= ®
->Indirect
;
1868 LLVMValueRef addr
, bufp
;
1869 LLVMValueRef result
;
1871 if (swizzle
== LP_CHAN_ALL
) {
1873 LLVMValueRef values
[4];
1874 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; ++chan
)
1875 values
[chan
] = fetch_constant(bld_base
, reg
, type
, chan
);
1877 return lp_build_gather_values(bld_base
->base
.gallivm
, values
, 4);
1880 buf
= reg
->Register
.Dimension
? reg
->Dimension
.Index
: 0;
1881 idx
= reg
->Register
.Index
* 4 + swizzle
;
1883 if (!reg
->Register
.Indirect
&& !reg
->Dimension
.Indirect
) {
1884 if (!tgsi_type_is_64bit(type
))
1885 return bitcast(bld_base
, type
, ctx
->constants
[buf
][idx
]);
1887 return radeon_llvm_emit_fetch_64bit(bld_base
, type
,
1888 ctx
->constants
[buf
][idx
],
1889 ctx
->constants
[buf
][idx
+ 1]);
1893 if (reg
->Register
.Dimension
&& reg
->Dimension
.Indirect
) {
1894 LLVMValueRef ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_CONST_BUFFERS
);
1896 index
= get_bounded_indirect_index(ctx
, ®
->DimIndirect
,
1897 reg
->Dimension
.Index
,
1898 SI_NUM_CONST_BUFFERS
);
1899 bufp
= build_indexed_load_const(ctx
, ptr
, index
);
1901 bufp
= ctx
->const_buffers
[buf
];
1903 addr
= ctx
->radeon_bld
.soa
.addr
[ireg
->Index
][ireg
->Swizzle
];
1904 addr
= LLVMBuildLoad(base
->gallivm
->builder
, addr
, "load addr reg");
1905 addr
= lp_build_mul_imm(&bld_base
->uint_bld
, addr
, 16);
1906 addr
= lp_build_add(&bld_base
->uint_bld
, addr
,
1907 lp_build_const_int32(base
->gallivm
, idx
* 4));
1909 result
= buffer_load_const(ctx
, bufp
, addr
);
1911 if (!tgsi_type_is_64bit(type
))
1912 result
= bitcast(bld_base
, type
, result
);
1914 LLVMValueRef addr2
, result2
;
1915 addr2
= ctx
->radeon_bld
.soa
.addr
[ireg
->Index
][ireg
->Swizzle
+ 1];
1916 addr2
= LLVMBuildLoad(base
->gallivm
->builder
, addr2
, "load addr reg2");
1917 addr2
= lp_build_mul_imm(&bld_base
->uint_bld
, addr2
, 16);
1918 addr2
= lp_build_add(&bld_base
->uint_bld
, addr2
,
1919 lp_build_const_int32(base
->gallivm
, idx
* 4));
1921 result2
= buffer_load_const(ctx
, ctx
->const_buffers
[buf
],
1924 result
= radeon_llvm_emit_fetch_64bit(bld_base
, type
,
1930 /* Upper 16 bits must be zero. */
1931 static LLVMValueRef
si_llvm_pack_two_int16(struct gallivm_state
*gallivm
,
1932 LLVMValueRef val
[2])
1934 return LLVMBuildOr(gallivm
->builder
, val
[0],
1935 LLVMBuildShl(gallivm
->builder
, val
[1],
1936 lp_build_const_int32(gallivm
, 16),
1940 /* Upper 16 bits are ignored and will be dropped. */
1941 static LLVMValueRef
si_llvm_pack_two_int32_as_int16(struct gallivm_state
*gallivm
,
1942 LLVMValueRef val
[2])
1944 LLVMValueRef v
[2] = {
1945 LLVMBuildAnd(gallivm
->builder
, val
[0],
1946 lp_build_const_int32(gallivm
, 0xffff), ""),
1949 return si_llvm_pack_two_int16(gallivm
, v
);
1952 /* Initialize arguments for the shader export intrinsic */
1953 static void si_llvm_init_export_args(struct lp_build_tgsi_context
*bld_base
,
1954 LLVMValueRef
*values
,
1958 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1959 struct lp_build_context
*uint
=
1960 &ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
1961 struct lp_build_context
*base
= &bld_base
->base
;
1962 struct gallivm_state
*gallivm
= base
->gallivm
;
1963 LLVMBuilderRef builder
= base
->gallivm
->builder
;
1964 LLVMValueRef val
[4];
1965 unsigned spi_shader_col_format
= V_028714_SPI_SHADER_32_ABGR
;
1969 /* Default is 0xf. Adjusted below depending on the format. */
1970 args
[0] = lp_build_const_int32(base
->gallivm
, 0xf); /* writemask */
1972 /* Specify whether the EXEC mask represents the valid mask */
1973 args
[1] = uint
->zero
;
1975 /* Specify whether this is the last export */
1976 args
[2] = uint
->zero
;
1978 /* Specify the target we are exporting */
1979 args
[3] = lp_build_const_int32(base
->gallivm
, target
);
1981 if (ctx
->type
== PIPE_SHADER_FRAGMENT
) {
1982 const union si_shader_key
*key
= &ctx
->shader
->key
;
1983 unsigned col_formats
= key
->ps
.epilog
.spi_shader_col_format
;
1984 int cbuf
= target
- V_008DFC_SQ_EXP_MRT
;
1986 assert(cbuf
>= 0 && cbuf
< 8);
1987 spi_shader_col_format
= (col_formats
>> (cbuf
* 4)) & 0xf;
1988 is_int8
= (key
->ps
.epilog
.color_is_int8
>> cbuf
) & 0x1;
1991 args
[4] = uint
->zero
; /* COMPR flag */
1992 args
[5] = base
->undef
;
1993 args
[6] = base
->undef
;
1994 args
[7] = base
->undef
;
1995 args
[8] = base
->undef
;
1997 switch (spi_shader_col_format
) {
1998 case V_028714_SPI_SHADER_ZERO
:
1999 args
[0] = uint
->zero
; /* writemask */
2000 args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_NULL
);
2003 case V_028714_SPI_SHADER_32_R
:
2004 args
[0] = uint
->one
; /* writemask */
2005 args
[5] = values
[0];
2008 case V_028714_SPI_SHADER_32_GR
:
2009 args
[0] = lp_build_const_int32(base
->gallivm
, 0x3); /* writemask */
2010 args
[5] = values
[0];
2011 args
[6] = values
[1];
2014 case V_028714_SPI_SHADER_32_AR
:
2015 args
[0] = lp_build_const_int32(base
->gallivm
, 0x9); /* writemask */
2016 args
[5] = values
[0];
2017 args
[8] = values
[3];
2020 case V_028714_SPI_SHADER_FP16_ABGR
:
2021 args
[4] = uint
->one
; /* COMPR flag */
2023 for (chan
= 0; chan
< 2; chan
++) {
2024 LLVMValueRef pack_args
[2] = {
2026 values
[2 * chan
+ 1]
2028 LLVMValueRef packed
;
2030 packed
= lp_build_intrinsic(base
->gallivm
->builder
,
2032 ctx
->i32
, pack_args
, 2,
2033 LLVMReadNoneAttribute
);
2035 LLVMBuildBitCast(base
->gallivm
->builder
,
2036 packed
, ctx
->f32
, "");
2040 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2041 for (chan
= 0; chan
< 4; chan
++) {
2042 val
[chan
] = radeon_llvm_saturate(bld_base
, values
[chan
]);
2043 val
[chan
] = LLVMBuildFMul(builder
, val
[chan
],
2044 lp_build_const_float(gallivm
, 65535), "");
2045 val
[chan
] = LLVMBuildFAdd(builder
, val
[chan
],
2046 lp_build_const_float(gallivm
, 0.5), "");
2047 val
[chan
] = LLVMBuildFPToUI(builder
, val
[chan
],
2051 args
[4] = uint
->one
; /* COMPR flag */
2052 args
[5] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2053 si_llvm_pack_two_int16(gallivm
, val
));
2054 args
[6] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2055 si_llvm_pack_two_int16(gallivm
, val
+2));
2058 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2059 for (chan
= 0; chan
< 4; chan
++) {
2060 /* Clamp between [-1, 1]. */
2061 val
[chan
] = lp_build_emit_llvm_binary(bld_base
, TGSI_OPCODE_MIN
,
2063 lp_build_const_float(gallivm
, 1));
2064 val
[chan
] = lp_build_emit_llvm_binary(bld_base
, TGSI_OPCODE_MAX
,
2066 lp_build_const_float(gallivm
, -1));
2067 /* Convert to a signed integer in [-32767, 32767]. */
2068 val
[chan
] = LLVMBuildFMul(builder
, val
[chan
],
2069 lp_build_const_float(gallivm
, 32767), "");
2070 /* If positive, add 0.5, else add -0.5. */
2071 val
[chan
] = LLVMBuildFAdd(builder
, val
[chan
],
2072 LLVMBuildSelect(builder
,
2073 LLVMBuildFCmp(builder
, LLVMRealOGE
,
2074 val
[chan
], base
->zero
, ""),
2075 lp_build_const_float(gallivm
, 0.5),
2076 lp_build_const_float(gallivm
, -0.5), ""), "");
2077 val
[chan
] = LLVMBuildFPToSI(builder
, val
[chan
], ctx
->i32
, "");
2080 args
[4] = uint
->one
; /* COMPR flag */
2081 args
[5] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2082 si_llvm_pack_two_int32_as_int16(gallivm
, val
));
2083 args
[6] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2084 si_llvm_pack_two_int32_as_int16(gallivm
, val
+2));
2087 case V_028714_SPI_SHADER_UINT16_ABGR
: {
2088 LLVMValueRef max
= lp_build_const_int32(gallivm
, is_int8
?
2091 for (chan
= 0; chan
< 4; chan
++) {
2092 val
[chan
] = bitcast(bld_base
, TGSI_TYPE_UNSIGNED
, values
[chan
]);
2093 val
[chan
] = lp_build_emit_llvm_binary(bld_base
, TGSI_OPCODE_UMIN
,
2097 args
[4] = uint
->one
; /* COMPR flag */
2098 args
[5] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2099 si_llvm_pack_two_int16(gallivm
, val
));
2100 args
[6] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2101 si_llvm_pack_two_int16(gallivm
, val
+2));
2105 case V_028714_SPI_SHADER_SINT16_ABGR
: {
2106 LLVMValueRef max
= lp_build_const_int32(gallivm
, is_int8
?
2108 LLVMValueRef min
= lp_build_const_int32(gallivm
, is_int8
?
2111 for (chan
= 0; chan
< 4; chan
++) {
2112 val
[chan
] = bitcast(bld_base
, TGSI_TYPE_UNSIGNED
, values
[chan
]);
2113 val
[chan
] = lp_build_emit_llvm_binary(bld_base
,
2116 val
[chan
] = lp_build_emit_llvm_binary(bld_base
,
2121 args
[4] = uint
->one
; /* COMPR flag */
2122 args
[5] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2123 si_llvm_pack_two_int32_as_int16(gallivm
, val
));
2124 args
[6] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2125 si_llvm_pack_two_int32_as_int16(gallivm
, val
+2));
2129 case V_028714_SPI_SHADER_32_ABGR
:
2130 memcpy(&args
[5], values
, sizeof(values
[0]) * 4);
2135 static void si_alpha_test(struct lp_build_tgsi_context
*bld_base
,
2138 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2139 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2141 if (ctx
->shader
->key
.ps
.epilog
.alpha_func
!= PIPE_FUNC_NEVER
) {
2142 LLVMValueRef alpha_ref
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2143 SI_PARAM_ALPHA_REF
);
2145 LLVMValueRef alpha_pass
=
2146 lp_build_cmp(&bld_base
->base
,
2147 ctx
->shader
->key
.ps
.epilog
.alpha_func
,
2150 lp_build_select(&bld_base
->base
,
2152 lp_build_const_float(gallivm
, 1.0f
),
2153 lp_build_const_float(gallivm
, -1.0f
));
2155 lp_build_intrinsic(gallivm
->builder
, "llvm.AMDGPU.kill",
2156 ctx
->voidt
, &arg
, 1, 0);
2158 lp_build_intrinsic(gallivm
->builder
, "llvm.AMDGPU.kilp",
2159 ctx
->voidt
, NULL
, 0, 0);
2163 static LLVMValueRef
si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context
*bld_base
,
2165 unsigned samplemask_param
)
2167 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2168 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2169 LLVMValueRef coverage
;
2171 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2172 coverage
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2174 coverage
= bitcast(bld_base
, TGSI_TYPE_SIGNED
, coverage
);
2176 coverage
= lp_build_intrinsic(gallivm
->builder
, "llvm.ctpop.i32",
2178 &coverage
, 1, LLVMReadNoneAttribute
);
2180 coverage
= LLVMBuildUIToFP(gallivm
->builder
, coverage
,
2183 coverage
= LLVMBuildFMul(gallivm
->builder
, coverage
,
2184 lp_build_const_float(gallivm
,
2185 1.0 / SI_NUM_SMOOTH_AA_SAMPLES
), "");
2187 return LLVMBuildFMul(gallivm
->builder
, alpha
, coverage
, "");
2190 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context
*bld_base
,
2191 LLVMValueRef (*pos
)[9], LLVMValueRef
*out_elts
)
2193 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2194 struct lp_build_context
*base
= &bld_base
->base
;
2195 struct lp_build_context
*uint
= &ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
2198 unsigned const_chan
;
2199 LLVMValueRef base_elt
;
2200 LLVMValueRef ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_RW_BUFFERS
);
2201 LLVMValueRef constbuf_index
= lp_build_const_int32(base
->gallivm
,
2202 SI_VS_CONST_CLIP_PLANES
);
2203 LLVMValueRef const_resource
= build_indexed_load_const(ctx
, ptr
, constbuf_index
);
2205 for (reg_index
= 0; reg_index
< 2; reg_index
++) {
2206 LLVMValueRef
*args
= pos
[2 + reg_index
];
2211 args
[8] = lp_build_const_float(base
->gallivm
, 0.0f
);
2213 /* Compute dot products of position and user clip plane vectors */
2214 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2215 for (const_chan
= 0; const_chan
< TGSI_NUM_CHANNELS
; const_chan
++) {
2216 args
[1] = lp_build_const_int32(base
->gallivm
,
2217 ((reg_index
* 4 + chan
) * 4 +
2219 base_elt
= buffer_load_const(ctx
, const_resource
,
2222 lp_build_add(base
, args
[5 + chan
],
2223 lp_build_mul(base
, base_elt
,
2224 out_elts
[const_chan
]));
2228 args
[0] = lp_build_const_int32(base
->gallivm
, 0xf);
2229 args
[1] = uint
->zero
;
2230 args
[2] = uint
->zero
;
2231 args
[3] = lp_build_const_int32(base
->gallivm
,
2232 V_008DFC_SQ_EXP_POS
+ 2 + reg_index
);
2233 args
[4] = uint
->zero
;
2237 static void si_dump_streamout(struct pipe_stream_output_info
*so
)
2241 if (so
->num_outputs
)
2242 fprintf(stderr
, "STREAMOUT\n");
2244 for (i
= 0; i
< so
->num_outputs
; i
++) {
2245 unsigned mask
= ((1 << so
->output
[i
].num_components
) - 1) <<
2246 so
->output
[i
].start_component
;
2247 fprintf(stderr
, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2248 i
, so
->output
[i
].output_buffer
,
2249 so
->output
[i
].dst_offset
, so
->output
[i
].dst_offset
+ so
->output
[i
].num_components
- 1,
2250 so
->output
[i
].register_index
,
2251 mask
& 1 ? "x" : "",
2252 mask
& 2 ? "y" : "",
2253 mask
& 4 ? "z" : "",
2254 mask
& 8 ? "w" : "");
2258 /* On SI, the vertex shader is responsible for writing streamout data
2260 static void si_llvm_emit_streamout(struct si_shader_context
*ctx
,
2261 struct si_shader_output_values
*outputs
,
2264 struct pipe_stream_output_info
*so
= &ctx
->shader
->selector
->so
;
2265 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
2266 LLVMBuilderRef builder
= gallivm
->builder
;
2268 struct lp_build_if_state if_ctx
;
2270 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2271 LLVMValueRef so_vtx_count
=
2272 unpack_param(ctx
, ctx
->param_streamout_config
, 16, 7);
2274 LLVMValueRef tid
= get_thread_id(ctx
);
2276 /* can_emit = tid < so_vtx_count; */
2277 LLVMValueRef can_emit
=
2278 LLVMBuildICmp(builder
, LLVMIntULT
, tid
, so_vtx_count
, "");
2280 LLVMValueRef stream_id
=
2281 unpack_param(ctx
, ctx
->param_streamout_config
, 24, 2);
2283 /* Emit the streamout code conditionally. This actually avoids
2284 * out-of-bounds buffer access. The hw tells us via the SGPR
2285 * (so_vtx_count) which threads are allowed to emit streamout data. */
2286 lp_build_if(&if_ctx
, gallivm
, can_emit
);
2288 /* The buffer offset is computed as follows:
2289 * ByteOffset = streamout_offset[buffer_id]*4 +
2290 * (streamout_write_index + thread_id)*stride[buffer_id] +
2294 LLVMValueRef so_write_index
=
2295 LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2296 ctx
->param_streamout_write_index
);
2298 /* Compute (streamout_write_index + thread_id). */
2299 so_write_index
= LLVMBuildAdd(builder
, so_write_index
, tid
, "");
2301 /* Compute the write offset for each enabled buffer. */
2302 LLVMValueRef so_write_offset
[4] = {};
2303 for (i
= 0; i
< 4; i
++) {
2307 LLVMValueRef so_offset
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2308 ctx
->param_streamout_offset
[i
]);
2309 so_offset
= LLVMBuildMul(builder
, so_offset
, LLVMConstInt(ctx
->i32
, 4, 0), "");
2311 so_write_offset
[i
] = LLVMBuildMul(builder
, so_write_index
,
2312 LLVMConstInt(ctx
->i32
, so
->stride
[i
]*4, 0), "");
2313 so_write_offset
[i
] = LLVMBuildAdd(builder
, so_write_offset
[i
], so_offset
, "");
2316 /* Write streamout data. */
2317 for (i
= 0; i
< so
->num_outputs
; i
++) {
2318 unsigned buf_idx
= so
->output
[i
].output_buffer
;
2319 unsigned reg
= so
->output
[i
].register_index
;
2320 unsigned start
= so
->output
[i
].start_component
;
2321 unsigned num_comps
= so
->output
[i
].num_components
;
2322 unsigned stream
= so
->output
[i
].stream
;
2323 LLVMValueRef out
[4];
2324 struct lp_build_if_state if_ctx_stream
;
2326 assert(num_comps
&& num_comps
<= 4);
2327 if (!num_comps
|| num_comps
> 4)
2333 /* Load the output as int. */
2334 for (j
= 0; j
< num_comps
; j
++) {
2335 out
[j
] = LLVMBuildBitCast(builder
,
2336 outputs
[reg
].values
[start
+j
],
2340 /* Pack the output. */
2341 LLVMValueRef vdata
= NULL
;
2343 switch (num_comps
) {
2344 case 1: /* as i32 */
2347 case 2: /* as v2i32 */
2348 case 3: /* as v4i32 (aligned to 4) */
2349 case 4: /* as v4i32 */
2350 vdata
= LLVMGetUndef(LLVMVectorType(ctx
->i32
, util_next_power_of_two(num_comps
)));
2351 for (j
= 0; j
< num_comps
; j
++) {
2352 vdata
= LLVMBuildInsertElement(builder
, vdata
, out
[j
],
2353 LLVMConstInt(ctx
->i32
, j
, 0), "");
2358 LLVMValueRef can_emit_stream
=
2359 LLVMBuildICmp(builder
, LLVMIntEQ
,
2361 lp_build_const_int32(gallivm
, stream
), "");
2363 lp_build_if(&if_ctx_stream
, gallivm
, can_emit_stream
);
2364 build_tbuffer_store_dwords(ctx
, ctx
->so_buffers
[buf_idx
],
2366 so_write_offset
[buf_idx
],
2367 LLVMConstInt(ctx
->i32
, 0, 0),
2368 so
->output
[i
].dst_offset
*4);
2369 lp_build_endif(&if_ctx_stream
);
2372 lp_build_endif(&if_ctx
);
2376 /* Generate export instructions for hardware VS shader stage */
2377 static void si_llvm_export_vs(struct lp_build_tgsi_context
*bld_base
,
2378 struct si_shader_output_values
*outputs
,
2381 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2382 struct si_shader
*shader
= ctx
->shader
;
2383 struct lp_build_context
*base
= &bld_base
->base
;
2384 struct lp_build_context
*uint
=
2385 &ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
2386 LLVMValueRef args
[9];
2387 LLVMValueRef pos_args
[4][9] = { { 0 } };
2388 LLVMValueRef psize_value
= NULL
, edgeflag_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
2389 unsigned semantic_name
, semantic_index
;
2391 unsigned param_count
= 0;
2395 if (outputs
&& ctx
->shader
->selector
->so
.num_outputs
) {
2396 si_llvm_emit_streamout(ctx
, outputs
, noutput
);
2399 for (i
= 0; i
< noutput
; i
++) {
2400 semantic_name
= outputs
[i
].name
;
2401 semantic_index
= outputs
[i
].sid
;
2404 /* Select the correct target */
2405 switch(semantic_name
) {
2406 case TGSI_SEMANTIC_PSIZE
:
2407 psize_value
= outputs
[i
].values
[0];
2409 case TGSI_SEMANTIC_EDGEFLAG
:
2410 edgeflag_value
= outputs
[i
].values
[0];
2412 case TGSI_SEMANTIC_LAYER
:
2413 layer_value
= outputs
[i
].values
[0];
2414 semantic_name
= TGSI_SEMANTIC_GENERIC
;
2415 goto handle_semantic
;
2416 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
2417 viewport_index_value
= outputs
[i
].values
[0];
2418 semantic_name
= TGSI_SEMANTIC_GENERIC
;
2419 goto handle_semantic
;
2420 case TGSI_SEMANTIC_POSITION
:
2421 target
= V_008DFC_SQ_EXP_POS
;
2423 case TGSI_SEMANTIC_COLOR
:
2424 case TGSI_SEMANTIC_BCOLOR
:
2425 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
2426 assert(i
< ARRAY_SIZE(shader
->info
.vs_output_param_offset
));
2427 shader
->info
.vs_output_param_offset
[i
] = param_count
;
2430 case TGSI_SEMANTIC_CLIPDIST
:
2431 target
= V_008DFC_SQ_EXP_POS
+ 2 + semantic_index
;
2433 case TGSI_SEMANTIC_CLIPVERTEX
:
2434 si_llvm_emit_clipvertex(bld_base
, pos_args
, outputs
[i
].values
);
2436 case TGSI_SEMANTIC_PRIMID
:
2437 case TGSI_SEMANTIC_FOG
:
2438 case TGSI_SEMANTIC_TEXCOORD
:
2439 case TGSI_SEMANTIC_GENERIC
:
2440 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
2441 assert(i
< ARRAY_SIZE(shader
->info
.vs_output_param_offset
));
2442 shader
->info
.vs_output_param_offset
[i
] = param_count
;
2448 "Warning: SI unhandled vs output type:%d\n",
2452 si_llvm_init_export_args(bld_base
, outputs
[i
].values
, target
, args
);
2454 if (target
>= V_008DFC_SQ_EXP_POS
&&
2455 target
<= (V_008DFC_SQ_EXP_POS
+ 3)) {
2456 memcpy(pos_args
[target
- V_008DFC_SQ_EXP_POS
],
2457 args
, sizeof(args
));
2459 lp_build_intrinsic(base
->gallivm
->builder
,
2460 "llvm.SI.export", ctx
->voidt
,
2464 if (semantic_name
== TGSI_SEMANTIC_CLIPDIST
) {
2465 semantic_name
= TGSI_SEMANTIC_GENERIC
;
2466 goto handle_semantic
;
2470 shader
->info
.nr_param_exports
= param_count
;
2472 /* We need to add the position output manually if it's missing. */
2473 if (!pos_args
[0][0]) {
2474 pos_args
[0][0] = lp_build_const_int32(base
->gallivm
, 0xf); /* writemask */
2475 pos_args
[0][1] = uint
->zero
; /* EXEC mask */
2476 pos_args
[0][2] = uint
->zero
; /* last export? */
2477 pos_args
[0][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
);
2478 pos_args
[0][4] = uint
->zero
; /* COMPR flag */
2479 pos_args
[0][5] = base
->zero
; /* X */
2480 pos_args
[0][6] = base
->zero
; /* Y */
2481 pos_args
[0][7] = base
->zero
; /* Z */
2482 pos_args
[0][8] = base
->one
; /* W */
2485 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2486 if (shader
->selector
->info
.writes_psize
||
2487 shader
->selector
->info
.writes_edgeflag
||
2488 shader
->selector
->info
.writes_viewport_index
||
2489 shader
->selector
->info
.writes_layer
) {
2490 pos_args
[1][0] = lp_build_const_int32(base
->gallivm
, /* writemask */
2491 shader
->selector
->info
.writes_psize
|
2492 (shader
->selector
->info
.writes_edgeflag
<< 1) |
2493 (shader
->selector
->info
.writes_layer
<< 2) |
2494 (shader
->selector
->info
.writes_viewport_index
<< 3));
2495 pos_args
[1][1] = uint
->zero
; /* EXEC mask */
2496 pos_args
[1][2] = uint
->zero
; /* last export? */
2497 pos_args
[1][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
+ 1);
2498 pos_args
[1][4] = uint
->zero
; /* COMPR flag */
2499 pos_args
[1][5] = base
->zero
; /* X */
2500 pos_args
[1][6] = base
->zero
; /* Y */
2501 pos_args
[1][7] = base
->zero
; /* Z */
2502 pos_args
[1][8] = base
->zero
; /* W */
2504 if (shader
->selector
->info
.writes_psize
)
2505 pos_args
[1][5] = psize_value
;
2507 if (shader
->selector
->info
.writes_edgeflag
) {
2508 /* The output is a float, but the hw expects an integer
2509 * with the first bit containing the edge flag. */
2510 edgeflag_value
= LLVMBuildFPToUI(base
->gallivm
->builder
,
2513 edgeflag_value
= lp_build_min(&bld_base
->int_bld
,
2515 bld_base
->int_bld
.one
);
2517 /* The LLVM intrinsic expects a float. */
2518 pos_args
[1][6] = LLVMBuildBitCast(base
->gallivm
->builder
,
2523 if (shader
->selector
->info
.writes_layer
)
2524 pos_args
[1][7] = layer_value
;
2526 if (shader
->selector
->info
.writes_viewport_index
)
2527 pos_args
[1][8] = viewport_index_value
;
2530 for (i
= 0; i
< 4; i
++)
2532 shader
->info
.nr_pos_exports
++;
2535 for (i
= 0; i
< 4; i
++) {
2536 if (!pos_args
[i
][0])
2539 /* Specify the target we are exporting */
2540 pos_args
[i
][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
+ pos_idx
++);
2542 if (pos_idx
== shader
->info
.nr_pos_exports
)
2543 /* Specify that this is the last export */
2544 pos_args
[i
][2] = uint
->one
;
2546 lp_build_intrinsic(base
->gallivm
->builder
, "llvm.SI.export",
2547 ctx
->voidt
, pos_args
[i
], 9, 0);
2551 static void si_copy_tcs_inputs(struct lp_build_tgsi_context
*bld_base
)
2553 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2554 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2555 LLVMValueRef invocation_id
, rw_buffers
, buffer
, buffer_offset
;
2556 LLVMValueRef lds_vertex_stride
, lds_vertex_offset
, lds_base
;
2559 invocation_id
= unpack_param(ctx
, SI_PARAM_REL_IDS
, 8, 5);
2561 rw_buffers
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_RW_BUFFERS
);
2562 buffer
= build_indexed_load_const(ctx
, rw_buffers
,
2563 lp_build_const_int32(gallivm
, SI_HS_RING_TESS_OFFCHIP
));
2565 buffer_offset
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, ctx
->param_oc_lds
);
2567 lds_vertex_stride
= unpack_param(ctx
, SI_PARAM_TCS_IN_LAYOUT
, 13, 8);
2568 lds_vertex_offset
= LLVMBuildMul(gallivm
->builder
, invocation_id
,
2569 lds_vertex_stride
, "");
2570 lds_base
= get_tcs_in_current_patch_offset(ctx
);
2571 lds_base
= LLVMBuildAdd(gallivm
->builder
, lds_base
, lds_vertex_offset
, "");
2573 inputs
= ctx
->shader
->key
.tcs
.epilog
.inputs_to_copy
;
2575 unsigned i
= u_bit_scan64(&inputs
);
2577 LLVMValueRef lds_ptr
= LLVMBuildAdd(gallivm
->builder
, lds_base
,
2578 lp_build_const_int32(gallivm
, 4 * i
),
2581 LLVMValueRef buffer_addr
= get_tcs_tes_buffer_address(ctx
,
2583 lp_build_const_int32(gallivm
, i
));
2585 LLVMValueRef value
= lds_load(bld_base
, TGSI_TYPE_SIGNED
, ~0,
2588 build_tbuffer_store_dwords(ctx
, buffer
, value
, 4, buffer_addr
,
2593 static void si_write_tess_factors(struct lp_build_tgsi_context
*bld_base
,
2594 LLVMValueRef rel_patch_id
,
2595 LLVMValueRef invocation_id
,
2596 LLVMValueRef tcs_out_current_patch_data_offset
)
2598 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2599 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2600 struct si_shader
*shader
= ctx
->shader
;
2601 unsigned tess_inner_index
, tess_outer_index
;
2602 LLVMValueRef lds_base
, lds_inner
, lds_outer
, byteoffset
, buffer
;
2603 LLVMValueRef out
[6], vec0
, vec1
, rw_buffers
, tf_base
;
2604 unsigned stride
, outer_comps
, inner_comps
, i
;
2605 struct lp_build_if_state if_ctx
, inner_if_ctx
;
2607 si_llvm_emit_barrier(NULL
, bld_base
, NULL
);
2609 /* Do this only for invocation 0, because the tess levels are per-patch,
2612 * This can't jump, because invocation 0 executes this. It should
2613 * at least mask out the loads and stores for other invocations.
2615 lp_build_if(&if_ctx
, gallivm
,
2616 LLVMBuildICmp(gallivm
->builder
, LLVMIntEQ
,
2617 invocation_id
, bld_base
->uint_bld
.zero
, ""));
2619 /* Determine the layout of one tess factor element in the buffer. */
2620 switch (shader
->key
.tcs
.epilog
.prim_mode
) {
2621 case PIPE_PRIM_LINES
:
2622 stride
= 2; /* 2 dwords, 1 vec2 store */
2626 case PIPE_PRIM_TRIANGLES
:
2627 stride
= 4; /* 4 dwords, 1 vec4 store */
2631 case PIPE_PRIM_QUADS
:
2632 stride
= 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2641 /* Load tess_inner and tess_outer from LDS.
2642 * Any invocation can write them, so we can't get them from a temporary.
2644 tess_inner_index
= si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER
, 0);
2645 tess_outer_index
= si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER
, 0);
2647 lds_base
= tcs_out_current_patch_data_offset
;
2648 lds_inner
= LLVMBuildAdd(gallivm
->builder
, lds_base
,
2649 lp_build_const_int32(gallivm
,
2650 tess_inner_index
* 4), "");
2651 lds_outer
= LLVMBuildAdd(gallivm
->builder
, lds_base
,
2652 lp_build_const_int32(gallivm
,
2653 tess_outer_index
* 4), "");
2655 for (i
= 0; i
< outer_comps
; i
++)
2656 out
[i
] = lds_load(bld_base
, TGSI_TYPE_SIGNED
, i
, lds_outer
);
2657 for (i
= 0; i
< inner_comps
; i
++)
2658 out
[outer_comps
+i
] = lds_load(bld_base
, TGSI_TYPE_SIGNED
, i
, lds_inner
);
2660 /* Convert the outputs to vectors for stores. */
2661 vec0
= lp_build_gather_values(gallivm
, out
, MIN2(stride
, 4));
2665 vec1
= lp_build_gather_values(gallivm
, out
+4, stride
- 4);
2667 /* Get the buffer. */
2668 rw_buffers
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2669 SI_PARAM_RW_BUFFERS
);
2670 buffer
= build_indexed_load_const(ctx
, rw_buffers
,
2671 lp_build_const_int32(gallivm
, SI_HS_RING_TESS_FACTOR
));
2673 /* Get the offset. */
2674 tf_base
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2675 SI_PARAM_TESS_FACTOR_OFFSET
);
2676 byteoffset
= LLVMBuildMul(gallivm
->builder
, rel_patch_id
,
2677 lp_build_const_int32(gallivm
, 4 * stride
), "");
2679 lp_build_if(&inner_if_ctx
, gallivm
,
2680 LLVMBuildICmp(gallivm
->builder
, LLVMIntEQ
,
2681 rel_patch_id
, bld_base
->uint_bld
.zero
, ""));
2683 /* Store the dynamic HS control word. */
2684 build_tbuffer_store_dwords(ctx
, buffer
,
2685 lp_build_const_int32(gallivm
, 0x80000000),
2686 1, lp_build_const_int32(gallivm
, 0), tf_base
, 0);
2688 lp_build_endif(&inner_if_ctx
);
2690 /* Store the tessellation factors. */
2691 build_tbuffer_store_dwords(ctx
, buffer
, vec0
,
2692 MIN2(stride
, 4), byteoffset
, tf_base
, 4);
2694 build_tbuffer_store_dwords(ctx
, buffer
, vec1
,
2695 stride
- 4, byteoffset
, tf_base
, 20);
2696 lp_build_endif(&if_ctx
);
2699 /* This only writes the tessellation factor levels. */
2700 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context
*bld_base
)
2702 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2703 LLVMValueRef rel_patch_id
, invocation_id
, tf_lds_offset
;
2705 rel_patch_id
= get_rel_patch_id(ctx
);
2706 invocation_id
= unpack_param(ctx
, SI_PARAM_REL_IDS
, 8, 5);
2707 tf_lds_offset
= get_tcs_out_current_patch_data_offset(ctx
);
2709 if (!ctx
->is_monolithic
) {
2710 /* Return epilog parameters from this function. */
2711 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
2712 LLVMValueRef ret
= ctx
->return_value
;
2713 LLVMValueRef rw_buffers
, rw0
, rw1
, tf_soffset
;
2716 /* RW_BUFFERS pointer */
2717 rw_buffers
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2718 SI_PARAM_RW_BUFFERS
);
2719 rw_buffers
= LLVMBuildPtrToInt(builder
, rw_buffers
, ctx
->i64
, "");
2720 rw_buffers
= LLVMBuildBitCast(builder
, rw_buffers
, ctx
->v2i32
, "");
2721 rw0
= LLVMBuildExtractElement(builder
, rw_buffers
,
2722 bld_base
->uint_bld
.zero
, "");
2723 rw1
= LLVMBuildExtractElement(builder
, rw_buffers
,
2724 bld_base
->uint_bld
.one
, "");
2725 ret
= LLVMBuildInsertValue(builder
, ret
, rw0
, 0, "");
2726 ret
= LLVMBuildInsertValue(builder
, ret
, rw1
, 1, "");
2728 /* Tess factor buffer soffset is after user SGPRs. */
2729 tf_soffset
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2730 SI_PARAM_TESS_FACTOR_OFFSET
);
2731 ret
= LLVMBuildInsertValue(builder
, ret
, tf_soffset
,
2732 SI_TCS_NUM_USER_SGPR
+ 1, "");
2735 rel_patch_id
= bitcast(bld_base
, TGSI_TYPE_FLOAT
, rel_patch_id
);
2736 invocation_id
= bitcast(bld_base
, TGSI_TYPE_FLOAT
, invocation_id
);
2737 tf_lds_offset
= bitcast(bld_base
, TGSI_TYPE_FLOAT
, tf_lds_offset
);
2739 vgpr
= SI_TCS_NUM_USER_SGPR
+ 2;
2740 ret
= LLVMBuildInsertValue(builder
, ret
, rel_patch_id
, vgpr
++, "");
2741 ret
= LLVMBuildInsertValue(builder
, ret
, invocation_id
, vgpr
++, "");
2742 ret
= LLVMBuildInsertValue(builder
, ret
, tf_lds_offset
, vgpr
++, "");
2743 ctx
->return_value
= ret
;
2747 si_copy_tcs_inputs(bld_base
);
2748 si_write_tess_factors(bld_base
, rel_patch_id
, invocation_id
, tf_lds_offset
);
2751 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context
*bld_base
)
2753 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2754 struct si_shader
*shader
= ctx
->shader
;
2755 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
2756 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2758 LLVMValueRef vertex_id
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2759 ctx
->param_rel_auto_id
);
2760 LLVMValueRef vertex_dw_stride
=
2761 unpack_param(ctx
, SI_PARAM_LS_OUT_LAYOUT
, 13, 8);
2762 LLVMValueRef base_dw_addr
= LLVMBuildMul(gallivm
->builder
, vertex_id
,
2763 vertex_dw_stride
, "");
2765 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2766 * its inputs from it. */
2767 for (i
= 0; i
< info
->num_outputs
; i
++) {
2768 LLVMValueRef
*out_ptr
= ctx
->radeon_bld
.soa
.outputs
[i
];
2769 unsigned name
= info
->output_semantic_name
[i
];
2770 unsigned index
= info
->output_semantic_index
[i
];
2771 int param
= si_shader_io_get_unique_index(name
, index
);
2772 LLVMValueRef dw_addr
= LLVMBuildAdd(gallivm
->builder
, base_dw_addr
,
2773 lp_build_const_int32(gallivm
, param
* 4), "");
2775 for (chan
= 0; chan
< 4; chan
++) {
2776 lds_store(bld_base
, chan
, dw_addr
,
2777 LLVMBuildLoad(gallivm
->builder
, out_ptr
[chan
], ""));
2782 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context
*bld_base
)
2784 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2785 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2786 struct si_shader
*es
= ctx
->shader
;
2787 struct tgsi_shader_info
*info
= &es
->selector
->info
;
2788 LLVMValueRef soffset
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2789 ctx
->param_es2gs_offset
);
2793 for (i
= 0; i
< info
->num_outputs
; i
++) {
2794 LLVMValueRef
*out_ptr
=
2795 ctx
->radeon_bld
.soa
.outputs
[i
];
2798 if (info
->output_semantic_name
[i
] == TGSI_SEMANTIC_VIEWPORT_INDEX
||
2799 info
->output_semantic_name
[i
] == TGSI_SEMANTIC_LAYER
)
2802 param_index
= si_shader_io_get_unique_index(info
->output_semantic_name
[i
],
2803 info
->output_semantic_index
[i
]);
2805 for (chan
= 0; chan
< 4; chan
++) {
2806 LLVMValueRef out_val
= LLVMBuildLoad(gallivm
->builder
, out_ptr
[chan
], "");
2807 out_val
= LLVMBuildBitCast(gallivm
->builder
, out_val
, ctx
->i32
, "");
2809 build_tbuffer_store(ctx
,
2812 LLVMGetUndef(ctx
->i32
), soffset
,
2813 (4 * param_index
+ chan
) * 4,
2814 V_008F0C_BUF_DATA_FORMAT_32
,
2815 V_008F0C_BUF_NUM_FORMAT_UINT
,
2821 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context
*bld_base
)
2823 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2824 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2825 LLVMValueRef args
[2];
2827 args
[0] = lp_build_const_int32(gallivm
, SENDMSG_GS_OP_NOP
| SENDMSG_GS_DONE
);
2828 args
[1] = LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_GS_WAVE_ID
);
2829 lp_build_intrinsic(gallivm
->builder
, "llvm.SI.sendmsg",
2830 ctx
->voidt
, args
, 2, 0);
2833 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context
*bld_base
)
2835 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2836 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2837 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
2838 struct si_shader_output_values
*outputs
= NULL
;
2841 assert(!ctx
->is_gs_copy_shader
);
2843 outputs
= MALLOC((info
->num_outputs
+ 1) * sizeof(outputs
[0]));
2845 /* Vertex color clamping.
2847 * This uses a state constant loaded in a user data SGPR and
2848 * an IF statement is added that clamps all colors if the constant
2851 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
2852 struct lp_build_if_state if_ctx
;
2853 LLVMValueRef cond
= NULL
;
2854 LLVMValueRef addr
, val
;
2856 for (i
= 0; i
< info
->num_outputs
; i
++) {
2857 if (info
->output_semantic_name
[i
] != TGSI_SEMANTIC_COLOR
&&
2858 info
->output_semantic_name
[i
] != TGSI_SEMANTIC_BCOLOR
)
2861 /* We've found a color. */
2863 /* The state is in the first bit of the user SGPR. */
2864 cond
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2865 SI_PARAM_VS_STATE_BITS
);
2866 cond
= LLVMBuildTrunc(gallivm
->builder
, cond
,
2868 lp_build_if(&if_ctx
, gallivm
, cond
);
2871 for (j
= 0; j
< 4; j
++) {
2872 addr
= ctx
->radeon_bld
.soa
.outputs
[i
][j
];
2873 val
= LLVMBuildLoad(gallivm
->builder
, addr
, "");
2874 val
= radeon_llvm_saturate(bld_base
, val
);
2875 LLVMBuildStore(gallivm
->builder
, val
, addr
);
2880 lp_build_endif(&if_ctx
);
2883 for (i
= 0; i
< info
->num_outputs
; i
++) {
2884 outputs
[i
].name
= info
->output_semantic_name
[i
];
2885 outputs
[i
].sid
= info
->output_semantic_index
[i
];
2887 for (j
= 0; j
< 4; j
++)
2888 outputs
[i
].values
[j
] =
2889 LLVMBuildLoad(gallivm
->builder
,
2890 ctx
->radeon_bld
.soa
.outputs
[i
][j
],
2894 if (ctx
->is_monolithic
) {
2895 /* Export PrimitiveID when PS needs it. */
2896 if (si_vs_exports_prim_id(ctx
->shader
)) {
2897 outputs
[i
].name
= TGSI_SEMANTIC_PRIMID
;
2899 outputs
[i
].values
[0] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2900 get_primitive_id(bld_base
, 0));
2901 outputs
[i
].values
[1] = bld_base
->base
.undef
;
2902 outputs
[i
].values
[2] = bld_base
->base
.undef
;
2903 outputs
[i
].values
[3] = bld_base
->base
.undef
;
2907 /* Return the primitive ID from the LLVM function. */
2909 LLVMBuildInsertValue(gallivm
->builder
,
2911 bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2912 get_primitive_id(bld_base
, 0)),
2913 VS_EPILOG_PRIMID_LOC
, "");
2916 si_llvm_export_vs(bld_base
, outputs
, i
);
2920 struct si_ps_exports
{
2922 LLVMValueRef args
[10][9];
2925 static void si_export_mrt_z(struct lp_build_tgsi_context
*bld_base
,
2926 LLVMValueRef depth
, LLVMValueRef stencil
,
2927 LLVMValueRef samplemask
, struct si_ps_exports
*exp
)
2929 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2930 struct lp_build_context
*base
= &bld_base
->base
;
2931 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
2932 LLVMValueRef args
[9];
2935 assert(depth
|| stencil
|| samplemask
);
2937 args
[1] = uint
->one
; /* whether the EXEC mask is valid */
2938 args
[2] = uint
->one
; /* DONE bit */
2940 /* Specify the target we are exporting */
2941 args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_MRTZ
);
2943 args
[4] = uint
->zero
; /* COMP flag */
2944 args
[5] = base
->undef
; /* R, depth */
2945 args
[6] = base
->undef
; /* G, stencil test value[0:7], stencil op value[8:15] */
2946 args
[7] = base
->undef
; /* B, sample mask */
2947 args
[8] = base
->undef
; /* A, alpha to mask */
2960 args
[7] = samplemask
;
2964 /* SI (except OLAND) has a bug that it only looks
2965 * at the X writemask component. */
2966 if (ctx
->screen
->b
.chip_class
== SI
&&
2967 ctx
->screen
->b
.family
!= CHIP_OLAND
)
2970 /* Specify which components to enable */
2971 args
[0] = lp_build_const_int32(base
->gallivm
, mask
);
2973 memcpy(exp
->args
[exp
->num
++], args
, sizeof(args
));
2976 static void si_export_mrt_color(struct lp_build_tgsi_context
*bld_base
,
2977 LLVMValueRef
*color
, unsigned index
,
2978 unsigned samplemask_param
,
2979 bool is_last
, struct si_ps_exports
*exp
)
2981 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2982 struct lp_build_context
*base
= &bld_base
->base
;
2986 if (ctx
->shader
->key
.ps
.epilog
.clamp_color
)
2987 for (i
= 0; i
< 4; i
++)
2988 color
[i
] = radeon_llvm_saturate(bld_base
, color
[i
]);
2991 if (ctx
->shader
->key
.ps
.epilog
.alpha_to_one
)
2992 color
[3] = base
->one
;
2996 ctx
->shader
->key
.ps
.epilog
.alpha_func
!= PIPE_FUNC_ALWAYS
)
2997 si_alpha_test(bld_base
, color
[3]);
2999 /* Line & polygon smoothing */
3000 if (ctx
->shader
->key
.ps
.epilog
.poly_line_smoothing
)
3001 color
[3] = si_scale_alpha_by_sample_mask(bld_base
, color
[3],
3004 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3005 if (ctx
->shader
->key
.ps
.epilog
.last_cbuf
> 0) {
3006 LLVMValueRef args
[8][9];
3009 /* Get the export arguments, also find out what the last one is. */
3010 for (c
= 0; c
<= ctx
->shader
->key
.ps
.epilog
.last_cbuf
; c
++) {
3011 si_llvm_init_export_args(bld_base
, color
,
3012 V_008DFC_SQ_EXP_MRT
+ c
, args
[c
]);
3013 if (args
[c
][0] != bld_base
->uint_bld
.zero
)
3017 /* Emit all exports. */
3018 for (c
= 0; c
<= ctx
->shader
->key
.ps
.epilog
.last_cbuf
; c
++) {
3019 if (is_last
&& last
== c
) {
3020 args
[c
][1] = bld_base
->uint_bld
.one
; /* whether the EXEC mask is valid */
3021 args
[c
][2] = bld_base
->uint_bld
.one
; /* DONE bit */
3022 } else if (args
[c
][0] == bld_base
->uint_bld
.zero
)
3023 continue; /* unnecessary NULL export */
3025 memcpy(exp
->args
[exp
->num
++], args
[c
], sizeof(args
[c
]));
3028 LLVMValueRef args
[9];
3031 si_llvm_init_export_args(bld_base
, color
, V_008DFC_SQ_EXP_MRT
+ index
,
3034 args
[1] = bld_base
->uint_bld
.one
; /* whether the EXEC mask is valid */
3035 args
[2] = bld_base
->uint_bld
.one
; /* DONE bit */
3036 } else if (args
[0] == bld_base
->uint_bld
.zero
)
3037 return; /* unnecessary NULL export */
3039 memcpy(exp
->args
[exp
->num
++], args
, sizeof(args
));
3043 static void si_emit_ps_exports(struct si_shader_context
*ctx
,
3044 struct si_ps_exports
*exp
)
3046 for (unsigned i
= 0; i
< exp
->num
; i
++)
3047 lp_build_intrinsic(ctx
->radeon_bld
.gallivm
.builder
,
3048 "llvm.SI.export", ctx
->voidt
,
3049 exp
->args
[i
], 9, 0);
3052 static void si_export_null(struct lp_build_tgsi_context
*bld_base
)
3054 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3055 struct lp_build_context
*base
= &bld_base
->base
;
3056 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
3057 LLVMValueRef args
[9];
3059 args
[0] = lp_build_const_int32(base
->gallivm
, 0x0); /* enabled channels */
3060 args
[1] = uint
->one
; /* whether the EXEC mask is valid */
3061 args
[2] = uint
->one
; /* DONE bit */
3062 args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_NULL
);
3063 args
[4] = uint
->zero
; /* COMPR flag (0 = 32-bit export) */
3064 args
[5] = base
->undef
; /* R */
3065 args
[6] = base
->undef
; /* G */
3066 args
[7] = base
->undef
; /* B */
3067 args
[8] = base
->undef
; /* A */
3069 lp_build_intrinsic(base
->gallivm
->builder
, "llvm.SI.export",
3070 ctx
->voidt
, args
, 9, 0);
3073 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context
*bld_base
)
3075 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3076 struct si_shader
*shader
= ctx
->shader
;
3077 struct lp_build_context
*base
= &bld_base
->base
;
3078 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
3079 LLVMBuilderRef builder
= base
->gallivm
->builder
;
3080 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3081 int last_color_export
= -1;
3083 struct si_ps_exports exp
= {};
3085 /* Determine the last export. If MRTZ is present, it's always last.
3086 * Otherwise, find the last color export.
3088 if (!info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
) {
3089 unsigned spi_format
= shader
->key
.ps
.epilog
.spi_shader_col_format
;
3091 /* Don't export NULL and return if alpha-test is enabled. */
3092 if (shader
->key
.ps
.epilog
.alpha_func
!= PIPE_FUNC_ALWAYS
&&
3093 shader
->key
.ps
.epilog
.alpha_func
!= PIPE_FUNC_NEVER
&&
3094 (spi_format
& 0xf) == 0)
3095 spi_format
|= V_028714_SPI_SHADER_32_AR
;
3097 for (i
= 0; i
< info
->num_outputs
; i
++) {
3098 unsigned index
= info
->output_semantic_index
[i
];
3100 if (info
->output_semantic_name
[i
] != TGSI_SEMANTIC_COLOR
)
3103 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3104 if (shader
->key
.ps
.epilog
.last_cbuf
> 0) {
3105 /* Just set this if any of the colorbuffers are enabled. */
3107 ((1llu << (4 * (shader
->key
.ps
.epilog
.last_cbuf
+ 1))) - 1))
3108 last_color_export
= i
;
3112 if ((spi_format
>> (index
* 4)) & 0xf)
3113 last_color_export
= i
;
3116 /* If there are no outputs, export NULL. */
3117 if (last_color_export
== -1) {
3118 si_export_null(bld_base
);
3123 for (i
= 0; i
< info
->num_outputs
; i
++) {
3124 unsigned semantic_name
= info
->output_semantic_name
[i
];
3125 unsigned semantic_index
= info
->output_semantic_index
[i
];
3127 LLVMValueRef color
[4] = {};
3129 /* Select the correct target */
3130 switch (semantic_name
) {
3131 case TGSI_SEMANTIC_POSITION
:
3132 depth
= LLVMBuildLoad(builder
,
3133 ctx
->radeon_bld
.soa
.outputs
[i
][2], "");
3135 case TGSI_SEMANTIC_STENCIL
:
3136 stencil
= LLVMBuildLoad(builder
,
3137 ctx
->radeon_bld
.soa
.outputs
[i
][1], "");
3139 case TGSI_SEMANTIC_SAMPLEMASK
:
3140 samplemask
= LLVMBuildLoad(builder
,
3141 ctx
->radeon_bld
.soa
.outputs
[i
][0], "");
3143 case TGSI_SEMANTIC_COLOR
:
3144 for (j
= 0; j
< 4; j
++)
3145 color
[j
] = LLVMBuildLoad(builder
,
3146 ctx
->radeon_bld
.soa
.outputs
[i
][j
], "");
3148 si_export_mrt_color(bld_base
, color
, semantic_index
,
3149 SI_PARAM_SAMPLE_COVERAGE
,
3150 last_color_export
== i
, &exp
);
3154 "Warning: SI unhandled fs output type:%d\n",
3159 if (depth
|| stencil
|| samplemask
)
3160 si_export_mrt_z(bld_base
, depth
, stencil
, samplemask
, &exp
);
3162 si_emit_ps_exports(ctx
, &exp
);
3166 * Return PS outputs in this order:
3168 * v[0:3] = color0.xyzw
3169 * v[4:7] = color1.xyzw
3174 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3176 * The alpha-ref SGPR is returned via its original location.
3178 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context
*bld_base
)
3180 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3181 struct si_shader
*shader
= ctx
->shader
;
3182 struct lp_build_context
*base
= &bld_base
->base
;
3183 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
3184 LLVMBuilderRef builder
= base
->gallivm
->builder
;
3185 unsigned i
, j
, first_vgpr
, vgpr
;
3187 LLVMValueRef color
[8][4] = {};
3188 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3191 /* Read the output values. */
3192 for (i
= 0; i
< info
->num_outputs
; i
++) {
3193 unsigned semantic_name
= info
->output_semantic_name
[i
];
3194 unsigned semantic_index
= info
->output_semantic_index
[i
];
3196 switch (semantic_name
) {
3197 case TGSI_SEMANTIC_COLOR
:
3198 assert(semantic_index
< 8);
3199 for (j
= 0; j
< 4; j
++) {
3200 LLVMValueRef ptr
= ctx
->radeon_bld
.soa
.outputs
[i
][j
];
3201 LLVMValueRef result
= LLVMBuildLoad(builder
, ptr
, "");
3202 color
[semantic_index
][j
] = result
;
3205 case TGSI_SEMANTIC_POSITION
:
3206 depth
= LLVMBuildLoad(builder
,
3207 ctx
->radeon_bld
.soa
.outputs
[i
][2], "");
3209 case TGSI_SEMANTIC_STENCIL
:
3210 stencil
= LLVMBuildLoad(builder
,
3211 ctx
->radeon_bld
.soa
.outputs
[i
][1], "");
3213 case TGSI_SEMANTIC_SAMPLEMASK
:
3214 samplemask
= LLVMBuildLoad(builder
,
3215 ctx
->radeon_bld
.soa
.outputs
[i
][0], "");
3218 fprintf(stderr
, "Warning: SI unhandled fs output type:%d\n",
3223 /* Fill the return structure. */
3224 ret
= ctx
->return_value
;
3227 ret
= LLVMBuildInsertValue(builder
, ret
,
3228 bitcast(bld_base
, TGSI_TYPE_SIGNED
,
3229 LLVMGetParam(ctx
->radeon_bld
.main_fn
,
3230 SI_PARAM_ALPHA_REF
)),
3231 SI_SGPR_ALPHA_REF
, "");
3234 first_vgpr
= vgpr
= SI_SGPR_ALPHA_REF
+ 1;
3235 for (i
= 0; i
< ARRAY_SIZE(color
); i
++) {
3239 for (j
= 0; j
< 4; j
++)
3240 ret
= LLVMBuildInsertValue(builder
, ret
, color
[i
][j
], vgpr
++, "");
3243 ret
= LLVMBuildInsertValue(builder
, ret
, depth
, vgpr
++, "");
3245 ret
= LLVMBuildInsertValue(builder
, ret
, stencil
, vgpr
++, "");
3247 ret
= LLVMBuildInsertValue(builder
, ret
, samplemask
, vgpr
++, "");
3249 /* Add the input sample mask for smoothing at the end. */
3250 if (vgpr
< first_vgpr
+ PS_EPILOG_SAMPLEMASK_MIN_LOC
)
3251 vgpr
= first_vgpr
+ PS_EPILOG_SAMPLEMASK_MIN_LOC
;
3252 ret
= LLVMBuildInsertValue(builder
, ret
,
3253 LLVMGetParam(ctx
->radeon_bld
.main_fn
,
3254 SI_PARAM_SAMPLE_COVERAGE
), vgpr
++, "");
3256 ctx
->return_value
= ret
;
3260 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3261 * buffer in number of elements and return it as an i32.
3263 static LLVMValueRef
get_buffer_size(
3264 struct lp_build_tgsi_context
*bld_base
,
3265 LLVMValueRef descriptor
)
3267 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3268 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3269 LLVMBuilderRef builder
= gallivm
->builder
;
3271 LLVMBuildExtractElement(builder
, descriptor
,
3272 lp_build_const_int32(gallivm
, 6), "");
3274 if (ctx
->screen
->b
.chip_class
>= VI
) {
3275 /* On VI, the descriptor contains the size in bytes,
3276 * but TXQ must return the size in elements.
3277 * The stride is always non-zero for resources using TXQ.
3279 LLVMValueRef stride
=
3280 LLVMBuildExtractElement(builder
, descriptor
,
3281 lp_build_const_int32(gallivm
, 5), "");
3282 stride
= LLVMBuildLShr(builder
, stride
,
3283 lp_build_const_int32(gallivm
, 16), "");
3284 stride
= LLVMBuildAnd(builder
, stride
,
3285 lp_build_const_int32(gallivm
, 0x3FFF), "");
3287 size
= LLVMBuildUDiv(builder
, size
, stride
, "");
3294 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
3297 static void build_int_type_name(
3299 char *buf
, unsigned bufsize
)
3301 assert(bufsize
>= 6);
3303 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
3304 snprintf(buf
, bufsize
, "v%ui32",
3305 LLVMGetVectorSize(type
));
3310 static void build_tex_intrinsic(const struct lp_build_tgsi_action
*action
,
3311 struct lp_build_tgsi_context
*bld_base
,
3312 struct lp_build_emit_data
*emit_data
);
3314 /* Prevent optimizations (at least of memory accesses) across the current
3315 * point in the program by emitting empty inline assembly that is marked as
3316 * having side effects.
3318 static void emit_optimization_barrier(struct si_shader_context
*ctx
)
3320 LLVMBuilderRef builder
= ctx
->radeon_bld
.gallivm
.builder
;
3321 LLVMTypeRef ftype
= LLVMFunctionType(ctx
->voidt
, NULL
, 0, false);
3322 LLVMValueRef inlineasm
= LLVMConstInlineAsm(ftype
, "", "", true, false);
3323 LLVMBuildCall(builder
, inlineasm
, NULL
, 0, "");
3326 static void emit_waitcnt(struct si_shader_context
*ctx
)
3328 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3329 LLVMBuilderRef builder
= gallivm
->builder
;
3330 LLVMValueRef args
[1] = {
3331 lp_build_const_int32(gallivm
, 0xf70)
3333 lp_build_intrinsic(builder
, "llvm.amdgcn.s.waitcnt",
3334 ctx
->voidt
, args
, 1, 0);
3337 static void membar_emit(
3338 const struct lp_build_tgsi_action
*action
,
3339 struct lp_build_tgsi_context
*bld_base
,
3340 struct lp_build_emit_data
*emit_data
)
3342 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3348 shader_buffer_fetch_rsrc(struct si_shader_context
*ctx
,
3349 const struct tgsi_full_src_register
*reg
)
3351 LLVMValueRef ind_index
;
3352 LLVMValueRef rsrc_ptr
;
3354 if (!reg
->Register
.Indirect
)
3355 return ctx
->shader_buffers
[reg
->Register
.Index
];
3357 ind_index
= get_bounded_indirect_index(ctx
, ®
->Indirect
,
3358 reg
->Register
.Index
,
3359 SI_NUM_SHADER_BUFFERS
);
3361 rsrc_ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_SHADER_BUFFERS
);
3362 return build_indexed_load_const(ctx
, rsrc_ptr
, ind_index
);
3365 static bool tgsi_is_array_sampler(unsigned target
)
3367 return target
== TGSI_TEXTURE_1D_ARRAY
||
3368 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
3369 target
== TGSI_TEXTURE_2D_ARRAY
||
3370 target
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
3371 target
== TGSI_TEXTURE_CUBE_ARRAY
||
3372 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
||
3373 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
;
3376 static bool tgsi_is_array_image(unsigned target
)
3378 return target
== TGSI_TEXTURE_3D
||
3379 target
== TGSI_TEXTURE_CUBE
||
3380 target
== TGSI_TEXTURE_1D_ARRAY
||
3381 target
== TGSI_TEXTURE_2D_ARRAY
||
3382 target
== TGSI_TEXTURE_CUBE_ARRAY
||
3383 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
;
3387 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3389 * At least on Tonga, executing image stores on images with DCC enabled and
3390 * non-trivial can eventually lead to lockups. This can occur when an
3391 * application binds an image as read-only but then uses a shader that writes
3392 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3393 * program termination) in this case, but it doesn't cost much to be a bit
3394 * nicer: disabling DCC in the shader still leads to undefined results but
3395 * avoids the lockup.
3397 static LLVMValueRef
force_dcc_off(struct si_shader_context
*ctx
,
3400 if (ctx
->screen
->b
.chip_class
<= CIK
) {
3403 LLVMBuilderRef builder
= ctx
->radeon_bld
.gallivm
.builder
;
3404 LLVMValueRef i32_6
= LLVMConstInt(ctx
->i32
, 6, 0);
3405 LLVMValueRef i32_C
= LLVMConstInt(ctx
->i32
, C_008F28_COMPRESSION_EN
, 0);
3408 tmp
= LLVMBuildExtractElement(builder
, rsrc
, i32_6
, "");
3409 tmp
= LLVMBuildAnd(builder
, tmp
, i32_C
, "");
3410 return LLVMBuildInsertElement(builder
, rsrc
, tmp
, i32_6
, "");
3415 * Load the resource descriptor for \p image.
3419 struct lp_build_tgsi_context
*bld_base
,
3420 const struct tgsi_full_src_register
*image
,
3424 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3426 assert(image
->Register
.File
== TGSI_FILE_IMAGE
);
3428 if (!image
->Register
.Indirect
) {
3429 /* Fast path: use preloaded resources */
3430 *rsrc
= ctx
->images
[image
->Register
.Index
];
3432 /* Indexing and manual load */
3433 LLVMValueRef ind_index
;
3434 LLVMValueRef rsrc_ptr
;
3437 /* From the GL_ARB_shader_image_load_store extension spec:
3439 * If a shader performs an image load, store, or atomic
3440 * operation using an image variable declared as an array,
3441 * and if the index used to select an individual element is
3442 * negative or greater than or equal to the size of the
3443 * array, the results of the operation are undefined but may
3444 * not lead to termination.
3446 ind_index
= get_bounded_indirect_index(ctx
, &image
->Indirect
,
3447 image
->Register
.Index
,
3450 rsrc_ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_IMAGES
);
3451 tmp
= build_indexed_load_const(ctx
, rsrc_ptr
, ind_index
);
3453 tmp
= force_dcc_off(ctx
, tmp
);
3458 static LLVMValueRef
image_fetch_coords(
3459 struct lp_build_tgsi_context
*bld_base
,
3460 const struct tgsi_full_instruction
*inst
,
3463 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3464 LLVMBuilderRef builder
= gallivm
->builder
;
3465 unsigned target
= inst
->Memory
.Texture
;
3466 unsigned num_coords
= tgsi_util_get_texture_coord_dim(target
);
3467 LLVMValueRef coords
[4];
3471 for (chan
= 0; chan
< num_coords
; ++chan
) {
3472 tmp
= lp_build_emit_fetch(bld_base
, inst
, src
, chan
);
3473 tmp
= LLVMBuildBitCast(builder
, tmp
, bld_base
->uint_bld
.elem_type
, "");
3477 if (num_coords
== 1)
3480 if (num_coords
== 3) {
3481 /* LLVM has difficulties lowering 3-element vectors. */
3482 coords
[3] = bld_base
->uint_bld
.undef
;
3486 return lp_build_gather_values(gallivm
, coords
, num_coords
);
3490 * Append the extra mode bits that are used by image load and store.
3492 static void image_append_args(
3493 struct si_shader_context
*ctx
,
3494 struct lp_build_emit_data
* emit_data
,
3498 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3499 LLVMValueRef i1false
= LLVMConstInt(ctx
->i1
, 0, 0);
3500 LLVMValueRef i1true
= LLVMConstInt(ctx
->i1
, 1, 0);
3502 emit_data
->args
[emit_data
->arg_count
++] = i1false
; /* r128 */
3503 emit_data
->args
[emit_data
->arg_count
++] =
3504 tgsi_is_array_image(target
) ? i1true
: i1false
; /* da */
3506 emit_data
->args
[emit_data
->arg_count
++] =
3507 inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
) ?
3508 i1true
: i1false
; /* glc */
3510 emit_data
->args
[emit_data
->arg_count
++] = i1false
; /* slc */
3514 * Given a 256 bit resource, extract the top half (which stores the buffer
3515 * resource in the case of textures and images).
3517 static LLVMValueRef
extract_rsrc_top_half(
3518 struct si_shader_context
*ctx
,
3521 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3522 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
3523 LLVMTypeRef v2i128
= LLVMVectorType(ctx
->i128
, 2);
3525 rsrc
= LLVMBuildBitCast(gallivm
->builder
, rsrc
, v2i128
, "");
3526 rsrc
= LLVMBuildExtractElement(gallivm
->builder
, rsrc
, bld_base
->uint_bld
.one
, "");
3527 rsrc
= LLVMBuildBitCast(gallivm
->builder
, rsrc
, ctx
->v4i32
, "");
3533 * Append the resource and indexing arguments for buffer intrinsics.
3535 * \param rsrc the v4i32 buffer resource
3536 * \param index index into the buffer (stride-based)
3537 * \param offset byte offset into the buffer
3539 static void buffer_append_args(
3540 struct si_shader_context
*ctx
,
3541 struct lp_build_emit_data
*emit_data
,
3544 LLVMValueRef offset
,
3547 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3548 LLVMValueRef i1false
= LLVMConstInt(ctx
->i1
, 0, 0);
3549 LLVMValueRef i1true
= LLVMConstInt(ctx
->i1
, 1, 0);
3551 emit_data
->args
[emit_data
->arg_count
++] = rsrc
;
3552 emit_data
->args
[emit_data
->arg_count
++] = index
; /* vindex */
3553 emit_data
->args
[emit_data
->arg_count
++] = offset
; /* voffset */
3555 emit_data
->args
[emit_data
->arg_count
++] =
3556 inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
) ?
3557 i1true
: i1false
; /* glc */
3559 emit_data
->args
[emit_data
->arg_count
++] = i1false
; /* slc */
3562 static void load_fetch_args(
3563 struct lp_build_tgsi_context
* bld_base
,
3564 struct lp_build_emit_data
* emit_data
)
3566 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3567 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3568 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
3569 unsigned target
= inst
->Memory
.Texture
;
3572 emit_data
->dst_type
= LLVMVectorType(bld_base
->base
.elem_type
, 4);
3574 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
3575 LLVMBuilderRef builder
= gallivm
->builder
;
3576 LLVMValueRef offset
;
3579 rsrc
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0]);
3581 tmp
= lp_build_emit_fetch(bld_base
, inst
, 1, 0);
3582 offset
= LLVMBuildBitCast(builder
, tmp
, bld_base
->uint_bld
.elem_type
, "");
3584 buffer_append_args(ctx
, emit_data
, rsrc
, bld_base
->uint_bld
.zero
,
3586 } else if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
) {
3587 LLVMValueRef coords
;
3589 image_fetch_rsrc(bld_base
, &inst
->Src
[0], false, &rsrc
);
3590 coords
= image_fetch_coords(bld_base
, inst
, 1);
3592 if (target
== TGSI_TEXTURE_BUFFER
) {
3593 rsrc
= extract_rsrc_top_half(ctx
, rsrc
);
3594 buffer_append_args(ctx
, emit_data
, rsrc
, coords
,
3595 bld_base
->uint_bld
.zero
, false);
3597 emit_data
->args
[0] = coords
;
3598 emit_data
->args
[1] = rsrc
;
3599 emit_data
->args
[2] = lp_build_const_int32(gallivm
, 15); /* dmask */
3600 emit_data
->arg_count
= 3;
3602 image_append_args(ctx
, emit_data
, target
, false);
3607 static void load_emit_buffer(struct si_shader_context
*ctx
,
3608 struct lp_build_emit_data
*emit_data
)
3610 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3611 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3612 LLVMBuilderRef builder
= gallivm
->builder
;
3613 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
3614 uint count
= util_last_bit(writemask
);
3615 const char *intrinsic_name
;
3616 LLVMTypeRef dst_type
;
3620 intrinsic_name
= "llvm.amdgcn.buffer.load.f32";
3621 dst_type
= ctx
->f32
;
3624 intrinsic_name
= "llvm.amdgcn.buffer.load.v2f32";
3625 dst_type
= LLVMVectorType(ctx
->f32
, 2);
3628 intrinsic_name
= "llvm.amdgcn.buffer.load.v4f32";
3629 dst_type
= ctx
->v4f32
;
3633 emit_data
->output
[emit_data
->chan
] = lp_build_intrinsic(
3634 builder
, intrinsic_name
, dst_type
,
3635 emit_data
->args
, emit_data
->arg_count
,
3636 LLVMReadOnlyAttribute
);
3639 static LLVMValueRef
get_memory_ptr(struct si_shader_context
*ctx
,
3640 const struct tgsi_full_instruction
*inst
,
3641 LLVMTypeRef type
, int arg
)
3643 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3644 LLVMBuilderRef builder
= gallivm
->builder
;
3645 LLVMValueRef offset
, ptr
;
3648 offset
= lp_build_emit_fetch(&ctx
->radeon_bld
.soa
.bld_base
, inst
, arg
, 0);
3649 offset
= LLVMBuildBitCast(builder
, offset
, ctx
->i32
, "");
3651 ptr
= ctx
->shared_memory
;
3652 ptr
= LLVMBuildGEP(builder
, ptr
, &offset
, 1, "");
3653 addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
3654 ptr
= LLVMBuildBitCast(builder
, ptr
, LLVMPointerType(type
, addr_space
), "");
3659 static void load_emit_memory(
3660 struct si_shader_context
*ctx
,
3661 struct lp_build_emit_data
*emit_data
)
3663 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3664 struct lp_build_context
*base
= &ctx
->radeon_bld
.soa
.bld_base
.base
;
3665 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3666 LLVMBuilderRef builder
= gallivm
->builder
;
3667 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
3668 LLVMValueRef channels
[4], ptr
, derived_ptr
, index
;
3671 ptr
= get_memory_ptr(ctx
, inst
, base
->elem_type
, 1);
3673 for (chan
= 0; chan
< 4; ++chan
) {
3674 if (!(writemask
& (1 << chan
))) {
3675 channels
[chan
] = LLVMGetUndef(base
->elem_type
);
3679 index
= lp_build_const_int32(gallivm
, chan
);
3680 derived_ptr
= LLVMBuildGEP(builder
, ptr
, &index
, 1, "");
3681 channels
[chan
] = LLVMBuildLoad(builder
, derived_ptr
, "");
3683 emit_data
->output
[emit_data
->chan
] = lp_build_gather_values(gallivm
, channels
, 4);
3686 static void load_emit(
3687 const struct lp_build_tgsi_action
*action
,
3688 struct lp_build_tgsi_context
*bld_base
,
3689 struct lp_build_emit_data
*emit_data
)
3691 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3692 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3693 LLVMBuilderRef builder
= gallivm
->builder
;
3694 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
3695 char intrinsic_name
[32];
3696 char coords_type
[8];
3698 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
3699 load_emit_memory(ctx
, emit_data
);
3703 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
3706 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
3707 load_emit_buffer(ctx
, emit_data
);
3711 if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
3712 emit_data
->output
[emit_data
->chan
] =
3714 builder
, "llvm.amdgcn.buffer.load.format.v4f32", emit_data
->dst_type
,
3715 emit_data
->args
, emit_data
->arg_count
,
3716 LLVMReadOnlyAttribute
);
3718 build_int_type_name(LLVMTypeOf(emit_data
->args
[0]),
3719 coords_type
, sizeof(coords_type
));
3721 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3722 "llvm.amdgcn.image.load.%s", coords_type
);
3724 emit_data
->output
[emit_data
->chan
] =
3726 builder
, intrinsic_name
, emit_data
->dst_type
,
3727 emit_data
->args
, emit_data
->arg_count
,
3728 LLVMReadOnlyAttribute
);
3732 static void store_fetch_args(
3733 struct lp_build_tgsi_context
* bld_base
,
3734 struct lp_build_emit_data
* emit_data
)
3736 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3737 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3738 LLVMBuilderRef builder
= gallivm
->builder
;
3739 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
3740 struct tgsi_full_src_register memory
;
3741 LLVMValueRef chans
[4];
3746 emit_data
->dst_type
= LLVMVoidTypeInContext(gallivm
->context
);
3748 for (chan
= 0; chan
< 4; ++chan
) {
3749 chans
[chan
] = lp_build_emit_fetch(bld_base
, inst
, 1, chan
);
3751 data
= lp_build_gather_values(gallivm
, chans
, 4);
3753 emit_data
->args
[emit_data
->arg_count
++] = data
;
3755 memory
= tgsi_full_src_register_from_dst(&inst
->Dst
[0]);
3757 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
3758 LLVMValueRef offset
;
3761 rsrc
= shader_buffer_fetch_rsrc(ctx
, &memory
);
3763 tmp
= lp_build_emit_fetch(bld_base
, inst
, 0, 0);
3764 offset
= LLVMBuildBitCast(builder
, tmp
, bld_base
->uint_bld
.elem_type
, "");
3766 buffer_append_args(ctx
, emit_data
, rsrc
, bld_base
->uint_bld
.zero
,
3768 } else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_IMAGE
) {
3769 unsigned target
= inst
->Memory
.Texture
;
3770 LLVMValueRef coords
;
3772 coords
= image_fetch_coords(bld_base
, inst
, 0);
3774 if (target
== TGSI_TEXTURE_BUFFER
) {
3775 image_fetch_rsrc(bld_base
, &memory
, false, &rsrc
);
3777 rsrc
= extract_rsrc_top_half(ctx
, rsrc
);
3778 buffer_append_args(ctx
, emit_data
, rsrc
, coords
,
3779 bld_base
->uint_bld
.zero
, false);
3781 emit_data
->args
[1] = coords
;
3782 image_fetch_rsrc(bld_base
, &memory
, true, &emit_data
->args
[2]);
3783 emit_data
->args
[3] = lp_build_const_int32(gallivm
, 15); /* dmask */
3784 emit_data
->arg_count
= 4;
3786 image_append_args(ctx
, emit_data
, target
, false);
3791 static void store_emit_buffer(
3792 struct si_shader_context
*ctx
,
3793 struct lp_build_emit_data
*emit_data
)
3795 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3796 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3797 LLVMBuilderRef builder
= gallivm
->builder
;
3798 struct lp_build_context
*uint_bld
= &ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
3799 LLVMValueRef base_data
= emit_data
->args
[0];
3800 LLVMValueRef base_offset
= emit_data
->args
[3];
3801 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
3805 const char *intrinsic_name
;
3807 LLVMValueRef offset
;
3810 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
3812 /* Due to an LLVM limitation, split 3-element writes
3813 * into a 2-element and a 1-element write. */
3815 writemask
|= 1 << (start
+ 2);
3821 intrinsic_name
= "llvm.amdgcn.buffer.store.v4f32";
3822 } else if (count
== 2) {
3823 LLVMTypeRef v2f32
= LLVMVectorType(ctx
->f32
, 2);
3825 tmp
= LLVMBuildExtractElement(
3827 lp_build_const_int32(gallivm
, start
), "");
3828 data
= LLVMBuildInsertElement(
3829 builder
, LLVMGetUndef(v2f32
), tmp
,
3830 uint_bld
->zero
, "");
3832 tmp
= LLVMBuildExtractElement(
3834 lp_build_const_int32(gallivm
, start
+ 1), "");
3835 data
= LLVMBuildInsertElement(
3836 builder
, data
, tmp
, uint_bld
->one
, "");
3838 intrinsic_name
= "llvm.amdgcn.buffer.store.v2f32";
3841 data
= LLVMBuildExtractElement(
3843 lp_build_const_int32(gallivm
, start
), "");
3844 intrinsic_name
= "llvm.amdgcn.buffer.store.f32";
3847 offset
= base_offset
;
3849 offset
= LLVMBuildAdd(
3851 lp_build_const_int32(gallivm
, start
* 4), "");
3854 emit_data
->args
[0] = data
;
3855 emit_data
->args
[3] = offset
;
3858 builder
, intrinsic_name
, emit_data
->dst_type
,
3859 emit_data
->args
, emit_data
->arg_count
, 0);
3863 static void store_emit_memory(
3864 struct si_shader_context
*ctx
,
3865 struct lp_build_emit_data
*emit_data
)
3867 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3868 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3869 struct lp_build_context
*base
= &ctx
->radeon_bld
.soa
.bld_base
.base
;
3870 LLVMBuilderRef builder
= gallivm
->builder
;
3871 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
3872 LLVMValueRef ptr
, derived_ptr
, data
, index
;
3875 ptr
= get_memory_ptr(ctx
, inst
, base
->elem_type
, 0);
3877 for (chan
= 0; chan
< 4; ++chan
) {
3878 if (!(writemask
& (1 << chan
))) {
3881 data
= lp_build_emit_fetch(&ctx
->radeon_bld
.soa
.bld_base
, inst
, 1, chan
);
3882 index
= lp_build_const_int32(gallivm
, chan
);
3883 derived_ptr
= LLVMBuildGEP(builder
, ptr
, &index
, 1, "");
3884 LLVMBuildStore(builder
, data
, derived_ptr
);
3888 static void store_emit(
3889 const struct lp_build_tgsi_action
*action
,
3890 struct lp_build_tgsi_context
*bld_base
,
3891 struct lp_build_emit_data
*emit_data
)
3893 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3894 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3895 LLVMBuilderRef builder
= gallivm
->builder
;
3896 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
3897 unsigned target
= inst
->Memory
.Texture
;
3898 char intrinsic_name
[32];
3899 char coords_type
[8];
3901 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
) {
3902 store_emit_memory(ctx
, emit_data
);
3906 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
3909 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
3910 store_emit_buffer(ctx
, emit_data
);
3914 if (target
== TGSI_TEXTURE_BUFFER
) {
3915 emit_data
->output
[emit_data
->chan
] = lp_build_intrinsic(
3916 builder
, "llvm.amdgcn.buffer.store.format.v4f32",
3917 emit_data
->dst_type
, emit_data
->args
,
3918 emit_data
->arg_count
, 0);
3920 build_int_type_name(LLVMTypeOf(emit_data
->args
[1]),
3921 coords_type
, sizeof(coords_type
));
3922 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3923 "llvm.amdgcn.image.store.%s", coords_type
);
3925 emit_data
->output
[emit_data
->chan
] =
3927 builder
, intrinsic_name
, emit_data
->dst_type
,
3928 emit_data
->args
, emit_data
->arg_count
, 0);
3932 static void atomic_fetch_args(
3933 struct lp_build_tgsi_context
* bld_base
,
3934 struct lp_build_emit_data
* emit_data
)
3936 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3937 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3938 LLVMBuilderRef builder
= gallivm
->builder
;
3939 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
3940 LLVMValueRef data1
, data2
;
3944 emit_data
->dst_type
= bld_base
->base
.elem_type
;
3946 tmp
= lp_build_emit_fetch(bld_base
, inst
, 2, 0);
3947 data1
= LLVMBuildBitCast(builder
, tmp
, bld_base
->uint_bld
.elem_type
, "");
3949 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
3950 tmp
= lp_build_emit_fetch(bld_base
, inst
, 3, 0);
3951 data2
= LLVMBuildBitCast(builder
, tmp
, bld_base
->uint_bld
.elem_type
, "");
3954 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3955 * of arguments, which is reversed relative to TGSI (and GLSL)
3957 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
3958 emit_data
->args
[emit_data
->arg_count
++] = data2
;
3959 emit_data
->args
[emit_data
->arg_count
++] = data1
;
3961 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
3962 LLVMValueRef offset
;
3964 rsrc
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0]);
3966 tmp
= lp_build_emit_fetch(bld_base
, inst
, 1, 0);
3967 offset
= LLVMBuildBitCast(builder
, tmp
, bld_base
->uint_bld
.elem_type
, "");
3969 buffer_append_args(ctx
, emit_data
, rsrc
, bld_base
->uint_bld
.zero
,
3971 } else if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
) {
3972 unsigned target
= inst
->Memory
.Texture
;
3973 LLVMValueRef coords
;
3975 image_fetch_rsrc(bld_base
, &inst
->Src
[0],
3976 target
!= TGSI_TEXTURE_BUFFER
, &rsrc
);
3977 coords
= image_fetch_coords(bld_base
, inst
, 1);
3979 if (target
== TGSI_TEXTURE_BUFFER
) {
3980 rsrc
= extract_rsrc_top_half(ctx
, rsrc
);
3981 buffer_append_args(ctx
, emit_data
, rsrc
, coords
,
3982 bld_base
->uint_bld
.zero
, true);
3984 emit_data
->args
[emit_data
->arg_count
++] = coords
;
3985 emit_data
->args
[emit_data
->arg_count
++] = rsrc
;
3987 image_append_args(ctx
, emit_data
, target
, true);
3992 static void atomic_emit_memory(struct si_shader_context
*ctx
,
3993 struct lp_build_emit_data
*emit_data
) {
3994 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3995 LLVMBuilderRef builder
= gallivm
->builder
;
3996 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
3997 LLVMValueRef ptr
, result
, arg
;
3999 ptr
= get_memory_ptr(ctx
, inst
, ctx
->i32
, 1);
4001 arg
= lp_build_emit_fetch(&ctx
->radeon_bld
.soa
.bld_base
, inst
, 2, 0);
4002 arg
= LLVMBuildBitCast(builder
, arg
, ctx
->i32
, "");
4004 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4005 LLVMValueRef new_data
;
4006 new_data
= lp_build_emit_fetch(&ctx
->radeon_bld
.soa
.bld_base
,
4009 new_data
= LLVMBuildBitCast(builder
, new_data
, ctx
->i32
, "");
4011 #if HAVE_LLVM >= 0x309
4012 result
= LLVMBuildAtomicCmpXchg(builder
, ptr
, arg
, new_data
,
4013 LLVMAtomicOrderingSequentiallyConsistent
,
4014 LLVMAtomicOrderingSequentiallyConsistent
,
4018 result
= LLVMBuildExtractValue(builder
, result
, 0, "");
4020 LLVMAtomicRMWBinOp op
;
4022 switch(inst
->Instruction
.Opcode
) {
4023 case TGSI_OPCODE_ATOMUADD
:
4024 op
= LLVMAtomicRMWBinOpAdd
;
4026 case TGSI_OPCODE_ATOMXCHG
:
4027 op
= LLVMAtomicRMWBinOpXchg
;
4029 case TGSI_OPCODE_ATOMAND
:
4030 op
= LLVMAtomicRMWBinOpAnd
;
4032 case TGSI_OPCODE_ATOMOR
:
4033 op
= LLVMAtomicRMWBinOpOr
;
4035 case TGSI_OPCODE_ATOMXOR
:
4036 op
= LLVMAtomicRMWBinOpXor
;
4038 case TGSI_OPCODE_ATOMUMIN
:
4039 op
= LLVMAtomicRMWBinOpUMin
;
4041 case TGSI_OPCODE_ATOMUMAX
:
4042 op
= LLVMAtomicRMWBinOpUMax
;
4044 case TGSI_OPCODE_ATOMIMIN
:
4045 op
= LLVMAtomicRMWBinOpMin
;
4047 case TGSI_OPCODE_ATOMIMAX
:
4048 op
= LLVMAtomicRMWBinOpMax
;
4051 unreachable("unknown atomic opcode");
4054 result
= LLVMBuildAtomicRMW(builder
, op
, ptr
, arg
,
4055 LLVMAtomicOrderingSequentiallyConsistent
,
4058 emit_data
->output
[emit_data
->chan
] = LLVMBuildBitCast(builder
, result
, emit_data
->dst_type
, "");
4061 static void atomic_emit(
4062 const struct lp_build_tgsi_action
*action
,
4063 struct lp_build_tgsi_context
*bld_base
,
4064 struct lp_build_emit_data
*emit_data
)
4066 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4067 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4068 LLVMBuilderRef builder
= gallivm
->builder
;
4069 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
4070 char intrinsic_name
[40];
4073 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
4074 atomic_emit_memory(ctx
, emit_data
);
4078 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
4079 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
4080 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
4081 "llvm.amdgcn.buffer.atomic.%s", action
->intr_name
);
4083 char coords_type
[8];
4085 build_int_type_name(LLVMTypeOf(emit_data
->args
[1]),
4086 coords_type
, sizeof(coords_type
));
4087 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
4088 "llvm.amdgcn.image.atomic.%s.%s",
4089 action
->intr_name
, coords_type
);
4092 tmp
= lp_build_intrinsic(
4093 builder
, intrinsic_name
, bld_base
->uint_bld
.elem_type
,
4094 emit_data
->args
, emit_data
->arg_count
, 0);
4095 emit_data
->output
[emit_data
->chan
] =
4096 LLVMBuildBitCast(builder
, tmp
, bld_base
->base
.elem_type
, "");
4099 static void resq_fetch_args(
4100 struct lp_build_tgsi_context
* bld_base
,
4101 struct lp_build_emit_data
* emit_data
)
4103 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4104 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4105 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4106 const struct tgsi_full_src_register
*reg
= &inst
->Src
[0];
4108 emit_data
->dst_type
= LLVMVectorType(bld_base
->base
.elem_type
, 4);
4110 if (reg
->Register
.File
== TGSI_FILE_BUFFER
) {
4111 emit_data
->args
[0] = shader_buffer_fetch_rsrc(ctx
, reg
);
4112 emit_data
->arg_count
= 1;
4113 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
4114 image_fetch_rsrc(bld_base
, reg
, false, &emit_data
->args
[0]);
4115 emit_data
->arg_count
= 1;
4117 emit_data
->args
[0] = bld_base
->uint_bld
.zero
; /* mip level */
4118 image_fetch_rsrc(bld_base
, reg
, false, &emit_data
->args
[1]);
4119 emit_data
->args
[2] = lp_build_const_int32(gallivm
, 15); /* dmask */
4120 emit_data
->args
[3] = bld_base
->uint_bld
.zero
; /* unorm */
4121 emit_data
->args
[4] = bld_base
->uint_bld
.zero
; /* r128 */
4122 emit_data
->args
[5] = tgsi_is_array_image(inst
->Memory
.Texture
) ?
4123 bld_base
->uint_bld
.one
: bld_base
->uint_bld
.zero
; /* da */
4124 emit_data
->args
[6] = bld_base
->uint_bld
.zero
; /* glc */
4125 emit_data
->args
[7] = bld_base
->uint_bld
.zero
; /* slc */
4126 emit_data
->args
[8] = bld_base
->uint_bld
.zero
; /* tfe */
4127 emit_data
->args
[9] = bld_base
->uint_bld
.zero
; /* lwe */
4128 emit_data
->arg_count
= 10;
4132 static void resq_emit(
4133 const struct lp_build_tgsi_action
*action
,
4134 struct lp_build_tgsi_context
*bld_base
,
4135 struct lp_build_emit_data
*emit_data
)
4137 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4138 LLVMBuilderRef builder
= gallivm
->builder
;
4139 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4142 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
4143 out
= LLVMBuildExtractElement(builder
, emit_data
->args
[0],
4144 lp_build_const_int32(gallivm
, 2), "");
4145 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
4146 out
= get_buffer_size(bld_base
, emit_data
->args
[0]);
4148 out
= lp_build_intrinsic(
4149 builder
, "llvm.SI.getresinfo.i32", emit_data
->dst_type
,
4150 emit_data
->args
, emit_data
->arg_count
,
4151 LLVMReadNoneAttribute
);
4153 /* Divide the number of layers by 6 to get the number of cubes. */
4154 if (inst
->Memory
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
) {
4155 LLVMValueRef imm2
= lp_build_const_int32(gallivm
, 2);
4156 LLVMValueRef imm6
= lp_build_const_int32(gallivm
, 6);
4158 LLVMValueRef z
= LLVMBuildExtractElement(builder
, out
, imm2
, "");
4159 z
= LLVMBuildBitCast(builder
, z
, bld_base
->uint_bld
.elem_type
, "");
4160 z
= LLVMBuildSDiv(builder
, z
, imm6
, "");
4161 z
= LLVMBuildBitCast(builder
, z
, bld_base
->base
.elem_type
, "");
4162 out
= LLVMBuildInsertElement(builder
, out
, z
, imm2
, "");
4166 emit_data
->output
[emit_data
->chan
] = out
;
4169 static void set_tex_fetch_args(struct si_shader_context
*ctx
,
4170 struct lp_build_emit_data
*emit_data
,
4171 unsigned opcode
, unsigned target
,
4172 LLVMValueRef res_ptr
, LLVMValueRef samp_ptr
,
4173 LLVMValueRef
*param
, unsigned count
,
4176 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
4178 unsigned is_rect
= target
== TGSI_TEXTURE_RECT
;
4180 /* Pad to power of two vector */
4181 while (count
< util_next_power_of_two(count
))
4182 param
[count
++] = LLVMGetUndef(ctx
->i32
);
4184 /* Texture coordinates. */
4186 emit_data
->args
[0] = lp_build_gather_values(gallivm
, param
, count
);
4188 emit_data
->args
[0] = param
[0];
4191 emit_data
->args
[1] = res_ptr
;
4194 if (opcode
== TGSI_OPCODE_TXF
|| opcode
== TGSI_OPCODE_TXQ
)
4195 emit_data
->dst_type
= ctx
->v4i32
;
4197 emit_data
->dst_type
= ctx
->v4f32
;
4199 emit_data
->args
[num_args
++] = samp_ptr
;
4202 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, dmask
);
4203 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, is_rect
); /* unorm */
4204 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, 0); /* r128 */
4205 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
,
4206 tgsi_is_array_sampler(target
)); /* da */
4207 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, 0); /* glc */
4208 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, 0); /* slc */
4209 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, 0); /* tfe */
4210 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, 0); /* lwe */
4212 emit_data
->arg_count
= num_args
;
4215 static const struct lp_build_tgsi_action tex_action
;
4223 static LLVMTypeRef
const_array(LLVMTypeRef elem_type
, int num_elements
)
4225 return LLVMPointerType(LLVMArrayType(elem_type
, num_elements
),
4230 * Load an image view, fmask view. or sampler state descriptor.
4232 static LLVMValueRef
get_sampler_desc_custom(struct si_shader_context
*ctx
,
4233 LLVMValueRef list
, LLVMValueRef index
,
4234 enum desc_type type
)
4236 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
4237 LLVMBuilderRef builder
= gallivm
->builder
;
4241 /* The image is at [0:7]. */
4242 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
4245 /* The FMASK is at [8:15]. */
4246 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
4247 index
= LLVMBuildAdd(builder
, index
, LLVMConstInt(ctx
->i32
, 1, 0), "");
4250 /* The sampler state is at [12:15]. */
4251 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 4, 0), "");
4252 index
= LLVMBuildAdd(builder
, index
, LLVMConstInt(ctx
->i32
, 3, 0), "");
4253 list
= LLVMBuildPointerCast(builder
, list
,
4254 const_array(ctx
->v4i32
, 0), "");
4258 return build_indexed_load_const(ctx
, list
, index
);
4261 static LLVMValueRef
get_sampler_desc(struct si_shader_context
*ctx
,
4262 LLVMValueRef index
, enum desc_type type
)
4264 LLVMValueRef list
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
4267 return get_sampler_desc_custom(ctx
, list
, index
, type
);
4270 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4273 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4274 * filtering manually. The driver sets img7 to a mask clearing
4275 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4276 * s_and_b32 samp0, samp0, img7
4279 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4281 static LLVMValueRef
sici_fix_sampler_aniso(struct si_shader_context
*ctx
,
4282 LLVMValueRef res
, LLVMValueRef samp
)
4284 LLVMBuilderRef builder
= ctx
->radeon_bld
.gallivm
.builder
;
4285 LLVMValueRef img7
, samp0
;
4287 if (ctx
->screen
->b
.chip_class
>= VI
)
4290 img7
= LLVMBuildExtractElement(builder
, res
,
4291 LLVMConstInt(ctx
->i32
, 7, 0), "");
4292 samp0
= LLVMBuildExtractElement(builder
, samp
,
4293 LLVMConstInt(ctx
->i32
, 0, 0), "");
4294 samp0
= LLVMBuildAnd(builder
, samp0
, img7
, "");
4295 return LLVMBuildInsertElement(builder
, samp
, samp0
,
4296 LLVMConstInt(ctx
->i32
, 0, 0), "");
4299 static void tex_fetch_ptrs(
4300 struct lp_build_tgsi_context
*bld_base
,
4301 struct lp_build_emit_data
*emit_data
,
4302 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
, LLVMValueRef
*fmask_ptr
)
4304 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4305 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4306 unsigned target
= inst
->Texture
.Texture
;
4307 unsigned sampler_src
;
4308 unsigned sampler_index
;
4310 sampler_src
= emit_data
->inst
->Instruction
.NumSrcRegs
- 1;
4311 sampler_index
= emit_data
->inst
->Src
[sampler_src
].Register
.Index
;
4313 if (emit_data
->inst
->Src
[sampler_src
].Register
.Indirect
) {
4314 const struct tgsi_full_src_register
*reg
= &emit_data
->inst
->Src
[sampler_src
];
4315 LLVMValueRef ind_index
;
4317 ind_index
= get_bounded_indirect_index(ctx
,
4319 reg
->Register
.Index
,
4322 *res_ptr
= get_sampler_desc(ctx
, ind_index
, DESC_IMAGE
);
4324 if (target
== TGSI_TEXTURE_2D_MSAA
||
4325 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
4329 *fmask_ptr
= get_sampler_desc(ctx
, ind_index
, DESC_FMASK
);
4332 *samp_ptr
= get_sampler_desc(ctx
, ind_index
, DESC_SAMPLER
);
4333 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
4339 *res_ptr
= ctx
->sampler_views
[sampler_index
];
4341 *samp_ptr
= ctx
->sampler_states
[sampler_index
];
4343 *fmask_ptr
= ctx
->fmasks
[sampler_index
];
4347 static void txq_fetch_args(
4348 struct lp_build_tgsi_context
*bld_base
,
4349 struct lp_build_emit_data
*emit_data
)
4351 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4352 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4353 LLVMBuilderRef builder
= gallivm
->builder
;
4354 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4355 unsigned target
= inst
->Texture
.Texture
;
4356 LLVMValueRef res_ptr
;
4357 LLVMValueRef address
;
4359 tex_fetch_ptrs(bld_base
, emit_data
, &res_ptr
, NULL
, NULL
);
4361 if (target
== TGSI_TEXTURE_BUFFER
) {
4362 /* Read the size from the buffer descriptor directly. */
4363 LLVMValueRef res
= LLVMBuildBitCast(builder
, res_ptr
, ctx
->v8i32
, "");
4364 emit_data
->args
[0] = get_buffer_size(bld_base
, res
);
4368 /* Textures - set the mip level. */
4369 address
= lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_X
);
4371 set_tex_fetch_args(ctx
, emit_data
, TGSI_OPCODE_TXQ
, target
, res_ptr
,
4372 NULL
, &address
, 1, 0xf);
4375 static void txq_emit(const struct lp_build_tgsi_action
*action
,
4376 struct lp_build_tgsi_context
*bld_base
,
4377 struct lp_build_emit_data
*emit_data
)
4379 struct lp_build_context
*base
= &bld_base
->base
;
4380 unsigned target
= emit_data
->inst
->Texture
.Texture
;
4382 if (target
== TGSI_TEXTURE_BUFFER
) {
4383 /* Just return the buffer size. */
4384 emit_data
->output
[emit_data
->chan
] = emit_data
->args
[0];
4388 emit_data
->output
[emit_data
->chan
] = lp_build_intrinsic(
4389 base
->gallivm
->builder
, "llvm.SI.getresinfo.i32",
4390 emit_data
->dst_type
, emit_data
->args
, emit_data
->arg_count
,
4391 LLVMReadNoneAttribute
);
4393 /* Divide the number of layers by 6 to get the number of cubes. */
4394 if (target
== TGSI_TEXTURE_CUBE_ARRAY
||
4395 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
4396 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
4397 LLVMValueRef two
= lp_build_const_int32(bld_base
->base
.gallivm
, 2);
4398 LLVMValueRef six
= lp_build_const_int32(bld_base
->base
.gallivm
, 6);
4400 LLVMValueRef v4
= emit_data
->output
[emit_data
->chan
];
4401 LLVMValueRef z
= LLVMBuildExtractElement(builder
, v4
, two
, "");
4402 z
= LLVMBuildSDiv(builder
, z
, six
, "");
4404 emit_data
->output
[emit_data
->chan
] =
4405 LLVMBuildInsertElement(builder
, v4
, z
, two
, "");
4409 static void tex_fetch_args(
4410 struct lp_build_tgsi_context
*bld_base
,
4411 struct lp_build_emit_data
*emit_data
)
4413 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4414 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4415 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4416 unsigned opcode
= inst
->Instruction
.Opcode
;
4417 unsigned target
= inst
->Texture
.Texture
;
4418 LLVMValueRef coords
[5], derivs
[6];
4419 LLVMValueRef address
[16];
4420 unsigned num_coords
= tgsi_util_get_texture_coord_dim(target
);
4421 int ref_pos
= tgsi_util_get_shadow_ref_src_index(target
);
4424 unsigned num_deriv_channels
= 0;
4425 bool has_offset
= inst
->Texture
.NumOffsets
> 0;
4426 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
;
4427 unsigned dmask
= 0xf;
4429 tex_fetch_ptrs(bld_base
, emit_data
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
4431 if (target
== TGSI_TEXTURE_BUFFER
) {
4432 LLVMTypeRef v2i128
= LLVMVectorType(ctx
->i128
, 2);
4434 /* Bitcast and truncate v8i32 to v16i8. */
4435 LLVMValueRef res
= res_ptr
;
4436 res
= LLVMBuildBitCast(gallivm
->builder
, res
, v2i128
, "");
4437 res
= LLVMBuildExtractElement(gallivm
->builder
, res
, bld_base
->uint_bld
.one
, "");
4438 res
= LLVMBuildBitCast(gallivm
->builder
, res
, ctx
->v16i8
, "");
4440 emit_data
->dst_type
= ctx
->v4f32
;
4441 emit_data
->args
[0] = res
;
4442 emit_data
->args
[1] = bld_base
->uint_bld
.zero
;
4443 emit_data
->args
[2] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_X
);
4444 emit_data
->arg_count
= 3;
4448 /* Fetch and project texture coordinates */
4449 coords
[3] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_W
);
4450 for (chan
= 0; chan
< 3; chan
++ ) {
4451 coords
[chan
] = lp_build_emit_fetch(bld_base
,
4454 if (opcode
== TGSI_OPCODE_TXP
)
4455 coords
[chan
] = lp_build_emit_llvm_binary(bld_base
,
4461 if (opcode
== TGSI_OPCODE_TXP
)
4462 coords
[3] = bld_base
->base
.one
;
4465 if (has_offset
&& opcode
!= TGSI_OPCODE_TXF
) {
4466 /* The offsets are six-bit signed integers packed like this:
4467 * X=[5:0], Y=[13:8], and Z=[21:16].
4469 LLVMValueRef offset
[3], pack
;
4471 assert(inst
->Texture
.NumOffsets
== 1);
4473 for (chan
= 0; chan
< 3; chan
++) {
4474 offset
[chan
] = lp_build_emit_fetch_texoffset(bld_base
,
4475 emit_data
->inst
, 0, chan
);
4476 offset
[chan
] = LLVMBuildAnd(gallivm
->builder
, offset
[chan
],
4477 lp_build_const_int32(gallivm
, 0x3f), "");
4479 offset
[chan
] = LLVMBuildShl(gallivm
->builder
, offset
[chan
],
4480 lp_build_const_int32(gallivm
, chan
*8), "");
4483 pack
= LLVMBuildOr(gallivm
->builder
, offset
[0], offset
[1], "");
4484 pack
= LLVMBuildOr(gallivm
->builder
, pack
, offset
[2], "");
4485 address
[count
++] = pack
;
4488 /* Pack LOD bias value */
4489 if (opcode
== TGSI_OPCODE_TXB
)
4490 address
[count
++] = coords
[3];
4491 if (opcode
== TGSI_OPCODE_TXB2
)
4492 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
4494 /* Pack depth comparison value */
4495 if (tgsi_is_shadow_target(target
) && opcode
!= TGSI_OPCODE_LODQ
) {
4496 if (target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
4497 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
4499 assert(ref_pos
>= 0);
4500 address
[count
++] = coords
[ref_pos
];
4504 /* Pack user derivatives */
4505 if (opcode
== TGSI_OPCODE_TXD
) {
4506 int param
, num_src_deriv_channels
;
4509 case TGSI_TEXTURE_3D
:
4510 num_src_deriv_channels
= 3;
4511 num_deriv_channels
= 3;
4513 case TGSI_TEXTURE_2D
:
4514 case TGSI_TEXTURE_SHADOW2D
:
4515 case TGSI_TEXTURE_RECT
:
4516 case TGSI_TEXTURE_SHADOWRECT
:
4517 case TGSI_TEXTURE_2D_ARRAY
:
4518 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
4519 num_src_deriv_channels
= 2;
4520 num_deriv_channels
= 2;
4522 case TGSI_TEXTURE_CUBE
:
4523 case TGSI_TEXTURE_SHADOWCUBE
:
4524 case TGSI_TEXTURE_CUBE_ARRAY
:
4525 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
4526 /* Cube derivatives will be converted to 2D. */
4527 num_src_deriv_channels
= 3;
4528 num_deriv_channels
= 2;
4530 case TGSI_TEXTURE_1D
:
4531 case TGSI_TEXTURE_SHADOW1D
:
4532 case TGSI_TEXTURE_1D_ARRAY
:
4533 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
4534 num_src_deriv_channels
= 1;
4535 num_deriv_channels
= 1;
4538 unreachable("invalid target");
4541 for (param
= 0; param
< 2; param
++)
4542 for (chan
= 0; chan
< num_src_deriv_channels
; chan
++)
4543 derivs
[param
* num_src_deriv_channels
+ chan
] =
4544 lp_build_emit_fetch(bld_base
, inst
, param
+1, chan
);
4547 if (target
== TGSI_TEXTURE_CUBE
||
4548 target
== TGSI_TEXTURE_CUBE_ARRAY
||
4549 target
== TGSI_TEXTURE_SHADOWCUBE
||
4550 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)
4551 radeon_llvm_emit_prepare_cube_coords(bld_base
, emit_data
, coords
, derivs
);
4553 if (opcode
== TGSI_OPCODE_TXD
)
4554 for (int i
= 0; i
< num_deriv_channels
* 2; i
++)
4555 address
[count
++] = derivs
[i
];
4557 /* Pack texture coordinates */
4558 address
[count
++] = coords
[0];
4560 address
[count
++] = coords
[1];
4562 address
[count
++] = coords
[2];
4564 /* Pack LOD or sample index */
4565 if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXF
)
4566 address
[count
++] = coords
[3];
4567 else if (opcode
== TGSI_OPCODE_TXL2
)
4568 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
4571 assert(!"Cannot handle more than 16 texture address parameters");
4575 for (chan
= 0; chan
< count
; chan
++ ) {
4576 address
[chan
] = LLVMBuildBitCast(gallivm
->builder
,
4577 address
[chan
], ctx
->i32
, "");
4580 /* Adjust the sample index according to FMASK.
4582 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4583 * which is the identity mapping. Each nibble says which physical sample
4584 * should be fetched to get that sample.
4586 * For example, 0x11111100 means there are only 2 samples stored and
4587 * the second sample covers 3/4 of the pixel. When reading samples 0
4588 * and 1, return physical sample 0 (determined by the first two 0s
4589 * in FMASK), otherwise return physical sample 1.
4591 * The sample index should be adjusted as follows:
4592 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4594 if (target
== TGSI_TEXTURE_2D_MSAA
||
4595 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
4596 struct lp_build_context
*uint_bld
= &bld_base
->uint_bld
;
4597 struct lp_build_emit_data txf_emit_data
= *emit_data
;
4598 LLVMValueRef txf_address
[4];
4599 unsigned txf_count
= count
;
4600 struct tgsi_full_instruction inst
= {};
4602 memcpy(txf_address
, address
, sizeof(txf_address
));
4604 if (target
== TGSI_TEXTURE_2D_MSAA
) {
4605 txf_address
[2] = bld_base
->uint_bld
.zero
;
4607 txf_address
[3] = bld_base
->uint_bld
.zero
;
4609 /* Read FMASK using TXF. */
4610 inst
.Instruction
.Opcode
= TGSI_OPCODE_TXF
;
4611 inst
.Texture
.Texture
= target
;
4612 txf_emit_data
.inst
= &inst
;
4613 txf_emit_data
.chan
= 0;
4614 set_tex_fetch_args(ctx
, &txf_emit_data
, TGSI_OPCODE_TXF
,
4615 target
, fmask_ptr
, NULL
,
4616 txf_address
, txf_count
, 0xf);
4617 build_tex_intrinsic(&tex_action
, bld_base
, &txf_emit_data
);
4619 /* Initialize some constants. */
4620 LLVMValueRef four
= LLVMConstInt(ctx
->i32
, 4, 0);
4621 LLVMValueRef F
= LLVMConstInt(ctx
->i32
, 0xF, 0);
4623 /* Apply the formula. */
4624 LLVMValueRef fmask
=
4625 LLVMBuildExtractElement(gallivm
->builder
,
4626 txf_emit_data
.output
[0],
4627 uint_bld
->zero
, "");
4629 unsigned sample_chan
= target
== TGSI_TEXTURE_2D_MSAA
? 2 : 3;
4631 LLVMValueRef sample_index4
=
4632 LLVMBuildMul(gallivm
->builder
, address
[sample_chan
], four
, "");
4634 LLVMValueRef shifted_fmask
=
4635 LLVMBuildLShr(gallivm
->builder
, fmask
, sample_index4
, "");
4637 LLVMValueRef final_sample
=
4638 LLVMBuildAnd(gallivm
->builder
, shifted_fmask
, F
, "");
4640 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4641 * resource descriptor is 0 (invalid),
4643 LLVMValueRef fmask_desc
=
4644 LLVMBuildBitCast(gallivm
->builder
, fmask_ptr
,
4647 LLVMValueRef fmask_word1
=
4648 LLVMBuildExtractElement(gallivm
->builder
, fmask_desc
,
4651 LLVMValueRef word1_is_nonzero
=
4652 LLVMBuildICmp(gallivm
->builder
, LLVMIntNE
,
4653 fmask_word1
, uint_bld
->zero
, "");
4655 /* Replace the MSAA sample index. */
4656 address
[sample_chan
] =
4657 LLVMBuildSelect(gallivm
->builder
, word1_is_nonzero
,
4658 final_sample
, address
[sample_chan
], "");
4661 if (opcode
== TGSI_OPCODE_TXF
) {
4662 /* add tex offsets */
4663 if (inst
->Texture
.NumOffsets
) {
4664 struct lp_build_context
*uint_bld
= &bld_base
->uint_bld
;
4665 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
4666 const struct tgsi_texture_offset
*off
= inst
->TexOffsets
;
4668 assert(inst
->Texture
.NumOffsets
== 1);
4671 case TGSI_TEXTURE_3D
:
4672 address
[2] = lp_build_add(uint_bld
, address
[2],
4673 bld
->immediates
[off
->Index
][off
->SwizzleZ
]);
4675 case TGSI_TEXTURE_2D
:
4676 case TGSI_TEXTURE_SHADOW2D
:
4677 case TGSI_TEXTURE_RECT
:
4678 case TGSI_TEXTURE_SHADOWRECT
:
4679 case TGSI_TEXTURE_2D_ARRAY
:
4680 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
4682 lp_build_add(uint_bld
, address
[1],
4683 bld
->immediates
[off
->Index
][off
->SwizzleY
]);
4685 case TGSI_TEXTURE_1D
:
4686 case TGSI_TEXTURE_SHADOW1D
:
4687 case TGSI_TEXTURE_1D_ARRAY
:
4688 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
4690 lp_build_add(uint_bld
, address
[0],
4691 bld
->immediates
[off
->Index
][off
->SwizzleX
]);
4693 /* texture offsets do not apply to other texture targets */
4698 if (opcode
== TGSI_OPCODE_TG4
) {
4699 unsigned gather_comp
= 0;
4701 /* DMASK was repurposed for GATHER4. 4 components are always
4702 * returned and DMASK works like a swizzle - it selects
4703 * the component to fetch. The only valid DMASK values are
4704 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4705 * (red,red,red,red) etc.) The ISA document doesn't mention
4709 /* Get the component index from src1.x for Gather4. */
4710 if (!tgsi_is_shadow_target(target
)) {
4711 LLVMValueRef (*imms
)[4] = lp_soa_context(bld_base
)->immediates
;
4712 LLVMValueRef comp_imm
;
4713 struct tgsi_src_register src1
= inst
->Src
[1].Register
;
4715 assert(src1
.File
== TGSI_FILE_IMMEDIATE
);
4717 comp_imm
= imms
[src1
.Index
][src1
.SwizzleX
];
4718 gather_comp
= LLVMConstIntGetZExtValue(comp_imm
);
4719 gather_comp
= CLAMP(gather_comp
, 0, 3);
4722 dmask
= 1 << gather_comp
;
4725 set_tex_fetch_args(ctx
, emit_data
, opcode
, target
, res_ptr
,
4726 samp_ptr
, address
, count
, dmask
);
4729 static void build_tex_intrinsic(const struct lp_build_tgsi_action
*action
,
4730 struct lp_build_tgsi_context
*bld_base
,
4731 struct lp_build_emit_data
*emit_data
)
4733 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4734 struct lp_build_context
*base
= &bld_base
->base
;
4735 unsigned opcode
= emit_data
->inst
->Instruction
.Opcode
;
4736 unsigned target
= emit_data
->inst
->Texture
.Texture
;
4737 char intr_name
[127];
4738 bool has_offset
= emit_data
->inst
->Texture
.NumOffsets
> 0;
4739 bool is_shadow
= tgsi_is_shadow_target(target
);
4741 const char *name
= "llvm.SI.image.sample";
4742 const char *infix
= "";
4744 if (target
== TGSI_TEXTURE_BUFFER
) {
4745 emit_data
->output
[emit_data
->chan
] = lp_build_intrinsic(
4746 base
->gallivm
->builder
,
4747 "llvm.SI.vs.load.input", emit_data
->dst_type
,
4748 emit_data
->args
, emit_data
->arg_count
,
4749 LLVMReadNoneAttribute
);
4754 case TGSI_OPCODE_TXF
:
4755 name
= target
== TGSI_TEXTURE_2D_MSAA
||
4756 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
?
4757 "llvm.SI.image.load" :
4758 "llvm.SI.image.load.mip";
4762 case TGSI_OPCODE_LODQ
:
4763 name
= "llvm.SI.getlod";
4767 case TGSI_OPCODE_TEX
:
4768 case TGSI_OPCODE_TEX2
:
4769 case TGSI_OPCODE_TXP
:
4770 if (ctx
->type
!= PIPE_SHADER_FRAGMENT
)
4773 case TGSI_OPCODE_TXB
:
4774 case TGSI_OPCODE_TXB2
:
4775 assert(ctx
->type
== PIPE_SHADER_FRAGMENT
);
4778 case TGSI_OPCODE_TXL
:
4779 case TGSI_OPCODE_TXL2
:
4782 case TGSI_OPCODE_TXD
:
4785 case TGSI_OPCODE_TG4
:
4786 name
= "llvm.SI.gather4";
4794 /* Add the type and suffixes .c, .o if needed. */
4795 build_int_type_name(LLVMTypeOf(emit_data
->args
[0]), type
, sizeof(type
));
4796 sprintf(intr_name
, "%s%s%s%s.%s",
4797 name
, is_shadow
? ".c" : "", infix
,
4798 has_offset
? ".o" : "", type
);
4800 emit_data
->output
[emit_data
->chan
] = lp_build_intrinsic(
4801 base
->gallivm
->builder
, intr_name
, emit_data
->dst_type
,
4802 emit_data
->args
, emit_data
->arg_count
,
4803 LLVMReadNoneAttribute
);
4806 static void si_llvm_emit_txqs(
4807 const struct lp_build_tgsi_action
*action
,
4808 struct lp_build_tgsi_context
*bld_base
,
4809 struct lp_build_emit_data
*emit_data
)
4811 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4812 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4813 LLVMBuilderRef builder
= gallivm
->builder
;
4814 LLVMValueRef res
, samples
;
4815 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
;
4817 tex_fetch_ptrs(bld_base
, emit_data
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
4820 /* Read the samples from the descriptor directly. */
4821 res
= LLVMBuildBitCast(builder
, res_ptr
, ctx
->v8i32
, "");
4822 samples
= LLVMBuildExtractElement(
4824 lp_build_const_int32(gallivm
, 3), "");
4825 samples
= LLVMBuildLShr(builder
, samples
,
4826 lp_build_const_int32(gallivm
, 16), "");
4827 samples
= LLVMBuildAnd(builder
, samples
,
4828 lp_build_const_int32(gallivm
, 0xf), "");
4829 samples
= LLVMBuildShl(builder
, lp_build_const_int32(gallivm
, 1),
4832 emit_data
->output
[emit_data
->chan
] = samples
;
4836 * SI implements derivatives using the local data store (LDS)
4837 * All writes to the LDS happen in all executing threads at
4838 * the same time. TID is the Thread ID for the current
4839 * thread and is a value between 0 and 63, representing
4840 * the thread's position in the wavefront.
4842 * For the pixel shader threads are grouped into quads of four pixels.
4843 * The TIDs of the pixels of a quad are:
4851 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
4852 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
4853 * the current pixel's column, and masking with 0xfffffffe yields the TID
4854 * of the left pixel of the current pixel's row.
4856 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
4857 * adding 2 yields the TID of the pixel below the top pixel.
4859 /* masks for thread ID. */
4860 #define TID_MASK_TOP_LEFT 0xfffffffc
4861 #define TID_MASK_TOP 0xfffffffd
4862 #define TID_MASK_LEFT 0xfffffffe
4864 static void si_llvm_emit_ddxy(
4865 const struct lp_build_tgsi_action
*action
,
4866 struct lp_build_tgsi_context
*bld_base
,
4867 struct lp_build_emit_data
*emit_data
)
4869 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4870 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4871 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4872 unsigned opcode
= inst
->Instruction
.Opcode
;
4873 LLVMValueRef indices
[2];
4874 LLVMValueRef store_ptr
, load_ptr0
, load_ptr1
;
4875 LLVMValueRef tl
, trbl
, result
[4];
4876 LLVMValueRef tl_tid
, trbl_tid
;
4877 unsigned swizzle
[4];
4882 indices
[0] = bld_base
->uint_bld
.zero
;
4883 indices
[1] = get_thread_id(ctx
);
4884 store_ptr
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4887 if (opcode
== TGSI_OPCODE_DDX_FINE
)
4888 mask
= TID_MASK_LEFT
;
4889 else if (opcode
== TGSI_OPCODE_DDY_FINE
)
4890 mask
= TID_MASK_TOP
;
4892 mask
= TID_MASK_TOP_LEFT
;
4894 tl_tid
= LLVMBuildAnd(gallivm
->builder
, indices
[1],
4895 lp_build_const_int32(gallivm
, mask
), "");
4896 indices
[1] = tl_tid
;
4897 load_ptr0
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4900 /* for DDX we want to next X pixel, DDY next Y pixel. */
4901 idx
= (opcode
== TGSI_OPCODE_DDX
|| opcode
== TGSI_OPCODE_DDX_FINE
) ? 1 : 2;
4902 trbl_tid
= LLVMBuildAdd(gallivm
->builder
, indices
[1],
4903 lp_build_const_int32(gallivm
, idx
), "");
4904 indices
[1] = trbl_tid
;
4905 load_ptr1
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4908 for (c
= 0; c
< 4; ++c
) {
4911 LLVMValueRef args
[2];
4913 swizzle
[c
] = tgsi_util_get_full_src_register_swizzle(&inst
->Src
[0], c
);
4914 for (i
= 0; i
< c
; ++i
) {
4915 if (swizzle
[i
] == swizzle
[c
]) {
4916 result
[c
] = result
[i
];
4923 val
= LLVMBuildBitCast(gallivm
->builder
,
4924 lp_build_emit_fetch(bld_base
, inst
, 0, c
),
4927 if ((HAVE_LLVM
>= 0x0309) && ctx
->screen
->b
.family
>= CHIP_TONGA
) {
4929 args
[0] = LLVMBuildMul(gallivm
->builder
, tl_tid
,
4930 lp_build_const_int32(gallivm
, 4), "");
4932 tl
= lp_build_intrinsic(gallivm
->builder
,
4933 "llvm.amdgcn.ds.bpermute", ctx
->i32
,
4934 args
, 2, LLVMReadNoneAttribute
);
4936 args
[0] = LLVMBuildMul(gallivm
->builder
, trbl_tid
,
4937 lp_build_const_int32(gallivm
, 4), "");
4938 trbl
= lp_build_intrinsic(gallivm
->builder
,
4939 "llvm.amdgcn.ds.bpermute", ctx
->i32
,
4940 args
, 2, LLVMReadNoneAttribute
);
4942 LLVMBuildStore(gallivm
->builder
, val
, store_ptr
);
4943 tl
= LLVMBuildLoad(gallivm
->builder
, load_ptr0
, "");
4944 trbl
= LLVMBuildLoad(gallivm
->builder
, load_ptr1
, "");
4946 tl
= LLVMBuildBitCast(gallivm
->builder
, tl
, ctx
->f32
, "");
4947 trbl
= LLVMBuildBitCast(gallivm
->builder
, trbl
, ctx
->f32
, "");
4948 result
[c
] = LLVMBuildFSub(gallivm
->builder
, trbl
, tl
, "");
4951 emit_data
->output
[0] = lp_build_gather_values(gallivm
, result
, 4);
4955 * this takes an I,J coordinate pair,
4956 * and works out the X and Y derivatives.
4957 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
4959 static LLVMValueRef
si_llvm_emit_ddxy_interp(
4960 struct lp_build_tgsi_context
*bld_base
,
4961 LLVMValueRef interp_ij
)
4963 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4964 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4965 LLVMValueRef indices
[2];
4966 LLVMValueRef store_ptr
, load_ptr_x
, load_ptr_y
, load_ptr_ddx
, load_ptr_ddy
, temp
, temp2
;
4967 LLVMValueRef tl
, tr
, bl
, result
[4];
4970 indices
[0] = bld_base
->uint_bld
.zero
;
4971 indices
[1] = get_thread_id(ctx
);
4972 store_ptr
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4975 temp
= LLVMBuildAnd(gallivm
->builder
, indices
[1],
4976 lp_build_const_int32(gallivm
, TID_MASK_LEFT
), "");
4978 temp2
= LLVMBuildAnd(gallivm
->builder
, indices
[1],
4979 lp_build_const_int32(gallivm
, TID_MASK_TOP
), "");
4982 load_ptr_x
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4986 load_ptr_y
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4989 indices
[1] = LLVMBuildAdd(gallivm
->builder
, temp
,
4990 lp_build_const_int32(gallivm
, 1), "");
4991 load_ptr_ddx
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4994 indices
[1] = LLVMBuildAdd(gallivm
->builder
, temp2
,
4995 lp_build_const_int32(gallivm
, 2), "");
4996 load_ptr_ddy
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4999 for (c
= 0; c
< 2; ++c
) {
5000 LLVMValueRef store_val
;
5001 LLVMValueRef c_ll
= lp_build_const_int32(gallivm
, c
);
5003 store_val
= LLVMBuildExtractElement(gallivm
->builder
,
5004 interp_ij
, c_ll
, "");
5005 LLVMBuildStore(gallivm
->builder
,
5009 tl
= LLVMBuildLoad(gallivm
->builder
, load_ptr_x
, "");
5010 tl
= LLVMBuildBitCast(gallivm
->builder
, tl
, ctx
->f32
, "");
5012 tr
= LLVMBuildLoad(gallivm
->builder
, load_ptr_ddx
, "");
5013 tr
= LLVMBuildBitCast(gallivm
->builder
, tr
, ctx
->f32
, "");
5015 result
[c
] = LLVMBuildFSub(gallivm
->builder
, tr
, tl
, "");
5017 tl
= LLVMBuildLoad(gallivm
->builder
, load_ptr_y
, "");
5018 tl
= LLVMBuildBitCast(gallivm
->builder
, tl
, ctx
->f32
, "");
5020 bl
= LLVMBuildLoad(gallivm
->builder
, load_ptr_ddy
, "");
5021 bl
= LLVMBuildBitCast(gallivm
->builder
, bl
, ctx
->f32
, "");
5023 result
[c
+ 2] = LLVMBuildFSub(gallivm
->builder
, bl
, tl
, "");
5026 return lp_build_gather_values(gallivm
, result
, 4);
5029 static void interp_fetch_args(
5030 struct lp_build_tgsi_context
*bld_base
,
5031 struct lp_build_emit_data
*emit_data
)
5033 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
5034 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5035 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
5037 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
5038 /* offset is in second src, first two channels */
5039 emit_data
->args
[0] = lp_build_emit_fetch(bld_base
,
5042 emit_data
->args
[1] = lp_build_emit_fetch(bld_base
,
5045 emit_data
->arg_count
= 2;
5046 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
5047 LLVMValueRef sample_position
;
5048 LLVMValueRef sample_id
;
5049 LLVMValueRef halfval
= lp_build_const_float(gallivm
, 0.5f
);
5051 /* fetch sample ID, then fetch its sample position,
5052 * and place into first two channels.
5054 sample_id
= lp_build_emit_fetch(bld_base
,
5055 emit_data
->inst
, 1, TGSI_CHAN_X
);
5056 sample_id
= LLVMBuildBitCast(gallivm
->builder
, sample_id
,
5058 sample_position
= load_sample_position(&ctx
->radeon_bld
, sample_id
);
5060 emit_data
->args
[0] = LLVMBuildExtractElement(gallivm
->builder
,
5062 lp_build_const_int32(gallivm
, 0), "");
5064 emit_data
->args
[0] = LLVMBuildFSub(gallivm
->builder
, emit_data
->args
[0], halfval
, "");
5065 emit_data
->args
[1] = LLVMBuildExtractElement(gallivm
->builder
,
5067 lp_build_const_int32(gallivm
, 1), "");
5068 emit_data
->args
[1] = LLVMBuildFSub(gallivm
->builder
, emit_data
->args
[1], halfval
, "");
5069 emit_data
->arg_count
= 2;
5073 static void build_interp_intrinsic(const struct lp_build_tgsi_action
*action
,
5074 struct lp_build_tgsi_context
*bld_base
,
5075 struct lp_build_emit_data
*emit_data
)
5077 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
5078 struct si_shader
*shader
= ctx
->shader
;
5079 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5080 LLVMValueRef interp_param
;
5081 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
5082 const char *intr_name
;
5083 int input_index
= inst
->Src
[0].Register
.Index
;
5086 LLVMValueRef attr_number
;
5087 LLVMValueRef params
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_PRIM_MASK
);
5088 int interp_param_idx
;
5089 unsigned interp
= shader
->selector
->info
.input_interpolate
[input_index
];
5092 assert(inst
->Src
[0].Register
.File
== TGSI_FILE_INPUT
);
5094 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
5095 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
)
5096 location
= TGSI_INTERPOLATE_LOC_CENTER
;
5098 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
5100 interp_param_idx
= lookup_interp_param_index(interp
, location
);
5101 if (interp_param_idx
== -1)
5103 else if (interp_param_idx
)
5104 interp_param
= get_interp_param(ctx
, interp_param_idx
);
5106 interp_param
= NULL
;
5108 attr_number
= lp_build_const_int32(gallivm
, input_index
);
5110 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
5111 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
5112 LLVMValueRef ij_out
[2];
5113 LLVMValueRef ddxy_out
= si_llvm_emit_ddxy_interp(bld_base
, interp_param
);
5116 * take the I then J parameters, and the DDX/Y for it, and
5117 * calculate the IJ inputs for the interpolator.
5118 * temp1 = ddx * offset/sample.x + I;
5119 * interp_param.I = ddy * offset/sample.y + temp1;
5120 * temp1 = ddx * offset/sample.x + J;
5121 * interp_param.J = ddy * offset/sample.y + temp1;
5123 for (i
= 0; i
< 2; i
++) {
5124 LLVMValueRef ix_ll
= lp_build_const_int32(gallivm
, i
);
5125 LLVMValueRef iy_ll
= lp_build_const_int32(gallivm
, i
+ 2);
5126 LLVMValueRef ddx_el
= LLVMBuildExtractElement(gallivm
->builder
,
5127 ddxy_out
, ix_ll
, "");
5128 LLVMValueRef ddy_el
= LLVMBuildExtractElement(gallivm
->builder
,
5129 ddxy_out
, iy_ll
, "");
5130 LLVMValueRef interp_el
= LLVMBuildExtractElement(gallivm
->builder
,
5131 interp_param
, ix_ll
, "");
5132 LLVMValueRef temp1
, temp2
;
5134 interp_el
= LLVMBuildBitCast(gallivm
->builder
, interp_el
,
5137 temp1
= LLVMBuildFMul(gallivm
->builder
, ddx_el
, emit_data
->args
[0], "");
5139 temp1
= LLVMBuildFAdd(gallivm
->builder
, temp1
, interp_el
, "");
5141 temp2
= LLVMBuildFMul(gallivm
->builder
, ddy_el
, emit_data
->args
[1], "");
5143 temp2
= LLVMBuildFAdd(gallivm
->builder
, temp2
, temp1
, "");
5145 ij_out
[i
] = LLVMBuildBitCast(gallivm
->builder
,
5146 temp2
, ctx
->i32
, "");
5148 interp_param
= lp_build_gather_values(bld_base
->base
.gallivm
, ij_out
, 2);
5151 intr_name
= interp_param
? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
5152 for (chan
= 0; chan
< 2; chan
++) {
5153 LLVMValueRef args
[4];
5154 LLVMValueRef llvm_chan
;
5157 schan
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[0], chan
);
5158 llvm_chan
= lp_build_const_int32(gallivm
, schan
);
5160 args
[0] = llvm_chan
;
5161 args
[1] = attr_number
;
5163 args
[3] = interp_param
;
5165 emit_data
->output
[chan
] =
5166 lp_build_intrinsic(gallivm
->builder
, intr_name
,
5167 ctx
->f32
, args
, args
[3] ? 4 : 3,
5168 LLVMReadNoneAttribute
);
5172 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context
*bld_base
,
5173 struct lp_build_emit_data
*emit_data
)
5175 LLVMValueRef (*imms
)[4] = lp_soa_context(bld_base
)->immediates
;
5176 struct tgsi_src_register src0
= emit_data
->inst
->Src
[0].Register
;
5179 assert(src0
.File
== TGSI_FILE_IMMEDIATE
);
5181 stream
= LLVMConstIntGetZExtValue(imms
[src0
.Index
][src0
.SwizzleX
]) & 0x3;
5185 /* Emit one vertex from the geometry shader */
5186 static void si_llvm_emit_vertex(
5187 const struct lp_build_tgsi_action
*action
,
5188 struct lp_build_tgsi_context
*bld_base
,
5189 struct lp_build_emit_data
*emit_data
)
5191 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
5192 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
5193 struct si_shader
*shader
= ctx
->shader
;
5194 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
5195 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5196 LLVMValueRef soffset
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
5197 SI_PARAM_GS2VS_OFFSET
);
5198 LLVMValueRef gs_next_vertex
;
5199 LLVMValueRef can_emit
, kill
;
5200 LLVMValueRef args
[2];
5205 stream
= si_llvm_get_stream(bld_base
, emit_data
);
5207 /* Write vertex attribute values to GSVS ring */
5208 gs_next_vertex
= LLVMBuildLoad(gallivm
->builder
,
5209 ctx
->gs_next_vertex
[stream
],
5212 /* If this thread has already emitted the declared maximum number of
5213 * vertices, kill it: excessive vertex emissions are not supposed to
5214 * have any effect, and GS threads have no externally observable
5215 * effects other than emitting vertices.
5217 can_emit
= LLVMBuildICmp(gallivm
->builder
, LLVMIntULE
, gs_next_vertex
,
5218 lp_build_const_int32(gallivm
,
5219 shader
->selector
->gs_max_out_vertices
), "");
5220 kill
= lp_build_select(&bld_base
->base
, can_emit
,
5221 lp_build_const_float(gallivm
, 1.0f
),
5222 lp_build_const_float(gallivm
, -1.0f
));
5224 lp_build_intrinsic(gallivm
->builder
, "llvm.AMDGPU.kill",
5225 ctx
->voidt
, &kill
, 1, 0);
5227 for (i
= 0; i
< info
->num_outputs
; i
++) {
5228 LLVMValueRef
*out_ptr
=
5229 ctx
->radeon_bld
.soa
.outputs
[i
];
5231 for (chan
= 0; chan
< 4; chan
++) {
5232 LLVMValueRef out_val
= LLVMBuildLoad(gallivm
->builder
, out_ptr
[chan
], "");
5233 LLVMValueRef voffset
=
5234 lp_build_const_int32(gallivm
, (i
* 4 + chan
) *
5235 shader
->selector
->gs_max_out_vertices
);
5237 voffset
= lp_build_add(uint
, voffset
, gs_next_vertex
);
5238 voffset
= lp_build_mul_imm(uint
, voffset
, 4);
5240 out_val
= LLVMBuildBitCast(gallivm
->builder
, out_val
, ctx
->i32
, "");
5242 build_tbuffer_store(ctx
,
5243 ctx
->gsvs_ring
[stream
],
5245 voffset
, soffset
, 0,
5246 V_008F0C_BUF_DATA_FORMAT_32
,
5247 V_008F0C_BUF_NUM_FORMAT_UINT
,
5251 gs_next_vertex
= lp_build_add(uint
, gs_next_vertex
,
5252 lp_build_const_int32(gallivm
, 1));
5254 LLVMBuildStore(gallivm
->builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
5256 /* Signal vertex emission */
5257 args
[0] = lp_build_const_int32(gallivm
, SENDMSG_GS_OP_EMIT
| SENDMSG_GS
| (stream
<< 8));
5258 args
[1] = LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_GS_WAVE_ID
);
5259 lp_build_intrinsic(gallivm
->builder
, "llvm.SI.sendmsg",
5260 ctx
->voidt
, args
, 2, 0);
5263 /* Cut one primitive from the geometry shader */
5264 static void si_llvm_emit_primitive(
5265 const struct lp_build_tgsi_action
*action
,
5266 struct lp_build_tgsi_context
*bld_base
,
5267 struct lp_build_emit_data
*emit_data
)
5269 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
5270 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5271 LLVMValueRef args
[2];
5274 /* Signal primitive cut */
5275 stream
= si_llvm_get_stream(bld_base
, emit_data
);
5276 args
[0] = lp_build_const_int32(gallivm
, SENDMSG_GS_OP_CUT
| SENDMSG_GS
| (stream
<< 8));
5277 args
[1] = LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_GS_WAVE_ID
);
5278 lp_build_intrinsic(gallivm
->builder
, "llvm.SI.sendmsg",
5279 ctx
->voidt
, args
, 2, 0);
5282 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action
*action
,
5283 struct lp_build_tgsi_context
*bld_base
,
5284 struct lp_build_emit_data
*emit_data
)
5286 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
5287 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5289 /* The real barrier instruction isn’t needed, because an entire patch
5290 * always fits into a single wave.
5292 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
) {
5293 emit_optimization_barrier(ctx
);
5297 lp_build_intrinsic(gallivm
->builder
,
5298 HAVE_LLVM
>= 0x0309 ? "llvm.amdgcn.s.barrier"
5299 : "llvm.AMDGPU.barrier.local",
5300 ctx
->voidt
, NULL
, 0, 0);
5303 static const struct lp_build_tgsi_action tex_action
= {
5304 .fetch_args
= tex_fetch_args
,
5305 .emit
= build_tex_intrinsic
,
5308 static const struct lp_build_tgsi_action interp_action
= {
5309 .fetch_args
= interp_fetch_args
,
5310 .emit
= build_interp_intrinsic
,
5313 static void si_create_function(struct si_shader_context
*ctx
,
5314 LLVMTypeRef
*returns
, unsigned num_returns
,
5315 LLVMTypeRef
*params
, unsigned num_params
,
5320 radeon_llvm_create_func(&ctx
->radeon_bld
, returns
, num_returns
,
5321 params
, num_params
);
5322 radeon_llvm_shader_type(ctx
->radeon_bld
.main_fn
, ctx
->type
);
5323 ctx
->return_value
= LLVMGetUndef(ctx
->radeon_bld
.return_type
);
5325 for (i
= 0; i
<= last_sgpr
; ++i
) {
5326 LLVMValueRef P
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, i
);
5328 /* The combination of:
5332 * allows the optimization passes to move loads and reduces
5333 * SGPR spilling significantly.
5335 if (LLVMGetTypeKind(LLVMTypeOf(P
)) == LLVMPointerTypeKind
) {
5336 LLVMAddAttribute(P
, LLVMByValAttribute
);
5337 lp_add_attr_dereferenceable(P
, UINT64_MAX
);
5339 LLVMAddAttribute(P
, LLVMInRegAttribute
);
5342 if (ctx
->screen
->b
.debug_flags
& DBG_UNSAFE_MATH
) {
5343 /* These were copied from some LLVM test. */
5344 LLVMAddTargetDependentFunctionAttr(ctx
->radeon_bld
.main_fn
,
5345 "less-precise-fpmad",
5347 LLVMAddTargetDependentFunctionAttr(ctx
->radeon_bld
.main_fn
,
5350 LLVMAddTargetDependentFunctionAttr(ctx
->radeon_bld
.main_fn
,
5353 LLVMAddTargetDependentFunctionAttr(ctx
->radeon_bld
.main_fn
,
5359 static void create_meta_data(struct si_shader_context
*ctx
)
5361 struct gallivm_state
*gallivm
= ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
5363 ctx
->invariant_load_md_kind
= LLVMGetMDKindIDInContext(gallivm
->context
,
5364 "invariant.load", 14);
5365 ctx
->range_md_kind
= LLVMGetMDKindIDInContext(gallivm
->context
,
5367 ctx
->uniform_md_kind
= LLVMGetMDKindIDInContext(gallivm
->context
,
5368 "amdgpu.uniform", 14);
5370 ctx
->empty_md
= LLVMMDNodeInContext(gallivm
->context
, NULL
, 0);
5373 static void declare_streamout_params(struct si_shader_context
*ctx
,
5374 struct pipe_stream_output_info
*so
,
5375 LLVMTypeRef
*params
, LLVMTypeRef i32
,
5376 unsigned *num_params
)
5380 /* Streamout SGPRs. */
5381 if (so
->num_outputs
) {
5382 if (ctx
->type
!= PIPE_SHADER_TESS_EVAL
)
5383 params
[ctx
->param_streamout_config
= (*num_params
)++] = i32
;
5385 ctx
->param_streamout_config
= ctx
->param_tess_offchip
;
5387 params
[ctx
->param_streamout_write_index
= (*num_params
)++] = i32
;
5389 /* A streamout buffer offset is loaded if the stride is non-zero. */
5390 for (i
= 0; i
< 4; i
++) {
5394 params
[ctx
->param_streamout_offset
[i
] = (*num_params
)++] = i32
;
5398 static unsigned llvm_get_type_size(LLVMTypeRef type
)
5400 LLVMTypeKind kind
= LLVMGetTypeKind(type
);
5403 case LLVMIntegerTypeKind
:
5404 return LLVMGetIntTypeWidth(type
) / 8;
5405 case LLVMFloatTypeKind
:
5407 case LLVMPointerTypeKind
:
5409 case LLVMVectorTypeKind
:
5410 return LLVMGetVectorSize(type
) *
5411 llvm_get_type_size(LLVMGetElementType(type
));
5418 static void declare_tess_lds(struct si_shader_context
*ctx
)
5420 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
5421 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
5422 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
5424 unsigned lds_size
= ctx
->screen
->b
.chip_class
>= CIK
? 65536 : 32768;
5425 ctx
->lds
= LLVMBuildIntToPtr(gallivm
->builder
, uint
->zero
,
5426 LLVMPointerType(LLVMArrayType(ctx
->i32
, lds_size
/ 4), LOCAL_ADDR_SPACE
),
5430 static void create_function(struct si_shader_context
*ctx
)
5432 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
5433 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5434 struct si_shader
*shader
= ctx
->shader
;
5435 LLVMTypeRef params
[SI_NUM_PARAMS
+ SI_NUM_VERTEX_BUFFERS
], v3i32
;
5436 LLVMTypeRef returns
[16+32*4];
5437 unsigned i
, last_sgpr
, num_params
, num_return_sgprs
;
5438 unsigned num_returns
= 0;
5440 v3i32
= LLVMVectorType(ctx
->i32
, 3);
5442 params
[SI_PARAM_RW_BUFFERS
] = const_array(ctx
->v16i8
, SI_NUM_RW_BUFFERS
);
5443 params
[SI_PARAM_CONST_BUFFERS
] = const_array(ctx
->v16i8
, SI_NUM_CONST_BUFFERS
);
5444 params
[SI_PARAM_SAMPLERS
] = const_array(ctx
->v8i32
, SI_NUM_SAMPLERS
);
5445 params
[SI_PARAM_IMAGES
] = const_array(ctx
->v8i32
, SI_NUM_IMAGES
);
5446 params
[SI_PARAM_SHADER_BUFFERS
] = const_array(ctx
->v4i32
, SI_NUM_SHADER_BUFFERS
);
5448 switch (ctx
->type
) {
5449 case PIPE_SHADER_VERTEX
:
5450 params
[SI_PARAM_VERTEX_BUFFERS
] = const_array(ctx
->v16i8
, SI_NUM_VERTEX_BUFFERS
);
5451 params
[SI_PARAM_BASE_VERTEX
] = ctx
->i32
;
5452 params
[SI_PARAM_START_INSTANCE
] = ctx
->i32
;
5453 params
[SI_PARAM_DRAWID
] = ctx
->i32
;
5454 num_params
= SI_PARAM_DRAWID
+1;
5456 if (shader
->key
.vs
.as_es
) {
5457 params
[ctx
->param_es2gs_offset
= num_params
++] = ctx
->i32
;
5458 } else if (shader
->key
.vs
.as_ls
) {
5459 params
[SI_PARAM_LS_OUT_LAYOUT
] = ctx
->i32
;
5460 num_params
= SI_PARAM_LS_OUT_LAYOUT
+1;
5462 if (ctx
->is_gs_copy_shader
) {
5463 num_params
= SI_PARAM_RW_BUFFERS
+1;
5465 params
[SI_PARAM_VS_STATE_BITS
] = ctx
->i32
;
5466 num_params
= SI_PARAM_VS_STATE_BITS
+1;
5469 /* The locations of the other parameters are assigned dynamically. */
5470 declare_streamout_params(ctx
, &shader
->selector
->so
,
5471 params
, ctx
->i32
, &num_params
);
5474 last_sgpr
= num_params
-1;
5477 params
[ctx
->param_vertex_id
= num_params
++] = ctx
->i32
;
5478 params
[ctx
->param_rel_auto_id
= num_params
++] = ctx
->i32
;
5479 params
[ctx
->param_vs_prim_id
= num_params
++] = ctx
->i32
;
5480 params
[ctx
->param_instance_id
= num_params
++] = ctx
->i32
;
5482 if (!ctx
->is_monolithic
&&
5483 !ctx
->is_gs_copy_shader
) {
5484 /* Vertex load indices. */
5485 ctx
->param_vertex_index0
= num_params
;
5487 for (i
= 0; i
< shader
->selector
->info
.num_inputs
; i
++)
5488 params
[num_params
++] = ctx
->i32
;
5490 /* PrimitiveID output. */
5491 if (!shader
->key
.vs
.as_es
&& !shader
->key
.vs
.as_ls
)
5492 for (i
= 0; i
<= VS_EPILOG_PRIMID_LOC
; i
++)
5493 returns
[num_returns
++] = ctx
->f32
;
5497 case PIPE_SHADER_TESS_CTRL
:
5498 params
[SI_PARAM_TCS_OFFCHIP_LAYOUT
] = ctx
->i32
;
5499 params
[SI_PARAM_TCS_OUT_OFFSETS
] = ctx
->i32
;
5500 params
[SI_PARAM_TCS_OUT_LAYOUT
] = ctx
->i32
;
5501 params
[SI_PARAM_TCS_IN_LAYOUT
] = ctx
->i32
;
5502 params
[ctx
->param_oc_lds
= SI_PARAM_TCS_OC_LDS
] = ctx
->i32
;
5503 params
[SI_PARAM_TESS_FACTOR_OFFSET
] = ctx
->i32
;
5504 last_sgpr
= SI_PARAM_TESS_FACTOR_OFFSET
;
5507 params
[SI_PARAM_PATCH_ID
] = ctx
->i32
;
5508 params
[SI_PARAM_REL_IDS
] = ctx
->i32
;
5509 num_params
= SI_PARAM_REL_IDS
+1;
5511 if (!ctx
->is_monolithic
) {
5512 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5513 * placed after the user SGPRs.
5515 for (i
= 0; i
< SI_TCS_NUM_USER_SGPR
+ 2; i
++)
5516 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
5518 for (i
= 0; i
< 3; i
++)
5519 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
5523 case PIPE_SHADER_TESS_EVAL
:
5524 params
[SI_PARAM_TCS_OFFCHIP_LAYOUT
] = ctx
->i32
;
5525 num_params
= SI_PARAM_TCS_OFFCHIP_LAYOUT
+1;
5527 if (shader
->key
.tes
.as_es
) {
5528 params
[ctx
->param_oc_lds
= num_params
++] = ctx
->i32
;
5529 params
[ctx
->param_tess_offchip
= num_params
++] = ctx
->i32
;
5530 params
[ctx
->param_es2gs_offset
= num_params
++] = ctx
->i32
;
5532 params
[ctx
->param_tess_offchip
= num_params
++] = ctx
->i32
;
5533 declare_streamout_params(ctx
, &shader
->selector
->so
,
5534 params
, ctx
->i32
, &num_params
);
5535 params
[ctx
->param_oc_lds
= num_params
++] = ctx
->i32
;
5537 last_sgpr
= num_params
- 1;
5540 params
[ctx
->param_tes_u
= num_params
++] = ctx
->f32
;
5541 params
[ctx
->param_tes_v
= num_params
++] = ctx
->f32
;
5542 params
[ctx
->param_tes_rel_patch_id
= num_params
++] = ctx
->i32
;
5543 params
[ctx
->param_tes_patch_id
= num_params
++] = ctx
->i32
;
5545 /* PrimitiveID output. */
5546 if (!ctx
->is_monolithic
&& !shader
->key
.tes
.as_es
)
5547 for (i
= 0; i
<= VS_EPILOG_PRIMID_LOC
; i
++)
5548 returns
[num_returns
++] = ctx
->f32
;
5551 case PIPE_SHADER_GEOMETRY
:
5552 params
[SI_PARAM_GS2VS_OFFSET
] = ctx
->i32
;
5553 params
[SI_PARAM_GS_WAVE_ID
] = ctx
->i32
;
5554 last_sgpr
= SI_PARAM_GS_WAVE_ID
;
5557 params
[SI_PARAM_VTX0_OFFSET
] = ctx
->i32
;
5558 params
[SI_PARAM_VTX1_OFFSET
] = ctx
->i32
;
5559 params
[SI_PARAM_PRIMITIVE_ID
] = ctx
->i32
;
5560 params
[SI_PARAM_VTX2_OFFSET
] = ctx
->i32
;
5561 params
[SI_PARAM_VTX3_OFFSET
] = ctx
->i32
;
5562 params
[SI_PARAM_VTX4_OFFSET
] = ctx
->i32
;
5563 params
[SI_PARAM_VTX5_OFFSET
] = ctx
->i32
;
5564 params
[SI_PARAM_GS_INSTANCE_ID
] = ctx
->i32
;
5565 num_params
= SI_PARAM_GS_INSTANCE_ID
+1;
5568 case PIPE_SHADER_FRAGMENT
:
5569 params
[SI_PARAM_ALPHA_REF
] = ctx
->f32
;
5570 params
[SI_PARAM_PRIM_MASK
] = ctx
->i32
;
5571 last_sgpr
= SI_PARAM_PRIM_MASK
;
5572 params
[SI_PARAM_PERSP_SAMPLE
] = ctx
->v2i32
;
5573 params
[SI_PARAM_PERSP_CENTER
] = ctx
->v2i32
;
5574 params
[SI_PARAM_PERSP_CENTROID
] = ctx
->v2i32
;
5575 params
[SI_PARAM_PERSP_PULL_MODEL
] = v3i32
;
5576 params
[SI_PARAM_LINEAR_SAMPLE
] = ctx
->v2i32
;
5577 params
[SI_PARAM_LINEAR_CENTER
] = ctx
->v2i32
;
5578 params
[SI_PARAM_LINEAR_CENTROID
] = ctx
->v2i32
;
5579 params
[SI_PARAM_LINE_STIPPLE_TEX
] = ctx
->f32
;
5580 params
[SI_PARAM_POS_X_FLOAT
] = ctx
->f32
;
5581 params
[SI_PARAM_POS_Y_FLOAT
] = ctx
->f32
;
5582 params
[SI_PARAM_POS_Z_FLOAT
] = ctx
->f32
;
5583 params
[SI_PARAM_POS_W_FLOAT
] = ctx
->f32
;
5584 params
[SI_PARAM_FRONT_FACE
] = ctx
->i32
;
5585 params
[SI_PARAM_ANCILLARY
] = ctx
->i32
;
5586 params
[SI_PARAM_SAMPLE_COVERAGE
] = ctx
->f32
;
5587 params
[SI_PARAM_POS_FIXED_PT
] = ctx
->i32
;
5588 num_params
= SI_PARAM_POS_FIXED_PT
+1;
5590 if (!ctx
->is_monolithic
) {
5591 /* Color inputs from the prolog. */
5592 if (shader
->selector
->info
.colors_read
) {
5593 unsigned num_color_elements
=
5594 util_bitcount(shader
->selector
->info
.colors_read
);
5596 assert(num_params
+ num_color_elements
<= ARRAY_SIZE(params
));
5597 for (i
= 0; i
< num_color_elements
; i
++)
5598 params
[num_params
++] = ctx
->f32
;
5601 /* Outputs for the epilog. */
5602 num_return_sgprs
= SI_SGPR_ALPHA_REF
+ 1;
5605 util_bitcount(shader
->selector
->info
.colors_written
) * 4 +
5606 shader
->selector
->info
.writes_z
+
5607 shader
->selector
->info
.writes_stencil
+
5608 shader
->selector
->info
.writes_samplemask
+
5609 1 /* SampleMaskIn */;
5611 num_returns
= MAX2(num_returns
,
5613 PS_EPILOG_SAMPLEMASK_MIN_LOC
+ 1);
5615 for (i
= 0; i
< num_return_sgprs
; i
++)
5616 returns
[i
] = ctx
->i32
;
5617 for (; i
< num_returns
; i
++)
5618 returns
[i
] = ctx
->f32
;
5622 case PIPE_SHADER_COMPUTE
:
5623 params
[SI_PARAM_GRID_SIZE
] = v3i32
;
5624 params
[SI_PARAM_BLOCK_ID
] = v3i32
;
5625 last_sgpr
= SI_PARAM_BLOCK_ID
;
5627 params
[SI_PARAM_THREAD_ID
] = v3i32
;
5628 num_params
= SI_PARAM_THREAD_ID
+ 1;
5631 assert(0 && "unimplemented shader");
5635 assert(num_params
<= ARRAY_SIZE(params
));
5637 si_create_function(ctx
, returns
, num_returns
, params
,
5638 num_params
, last_sgpr
);
5640 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5641 if (ctx
->type
== PIPE_SHADER_FRAGMENT
&&
5642 !ctx
->is_monolithic
) {
5643 radeon_llvm_add_attribute(ctx
->radeon_bld
.main_fn
,
5644 "InitialPSInputAddr",
5645 S_0286D0_PERSP_SAMPLE_ENA(1) |
5646 S_0286D0_PERSP_CENTER_ENA(1) |
5647 S_0286D0_PERSP_CENTROID_ENA(1) |
5648 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5649 S_0286D0_LINEAR_CENTER_ENA(1) |
5650 S_0286D0_LINEAR_CENTROID_ENA(1) |
5651 S_0286D0_FRONT_FACE_ENA(1) |
5652 S_0286D0_POS_FIXED_PT_ENA(1));
5653 } else if (ctx
->type
== PIPE_SHADER_COMPUTE
) {
5654 const unsigned *properties
= shader
->selector
->info
.properties
;
5655 unsigned max_work_group_size
=
5656 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] *
5657 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
] *
5658 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
];
5660 assert(max_work_group_size
);
5662 radeon_llvm_add_attribute(ctx
->radeon_bld
.main_fn
,
5663 "amdgpu-max-work-group-size",
5664 max_work_group_size
);
5667 shader
->info
.num_input_sgprs
= 0;
5668 shader
->info
.num_input_vgprs
= 0;
5670 for (i
= 0; i
<= last_sgpr
; ++i
)
5671 shader
->info
.num_input_sgprs
+= llvm_get_type_size(params
[i
]) / 4;
5673 /* Unused fragment shader inputs are eliminated by the compiler,
5674 * so we don't know yet how many there will be.
5676 if (ctx
->type
!= PIPE_SHADER_FRAGMENT
)
5677 for (; i
< num_params
; ++i
)
5678 shader
->info
.num_input_vgprs
+= llvm_get_type_size(params
[i
]) / 4;
5680 if (bld_base
->info
&&
5681 (bld_base
->info
->opcode_count
[TGSI_OPCODE_DDX
] > 0 ||
5682 bld_base
->info
->opcode_count
[TGSI_OPCODE_DDY
] > 0 ||
5683 bld_base
->info
->opcode_count
[TGSI_OPCODE_DDX_FINE
] > 0 ||
5684 bld_base
->info
->opcode_count
[TGSI_OPCODE_DDY_FINE
] > 0 ||
5685 bld_base
->info
->opcode_count
[TGSI_OPCODE_INTERP_OFFSET
] > 0 ||
5686 bld_base
->info
->opcode_count
[TGSI_OPCODE_INTERP_SAMPLE
] > 0))
5688 LLVMAddGlobalInAddressSpace(gallivm
->module
,
5689 LLVMArrayType(ctx
->i32
, 64),
5693 if ((ctx
->type
== PIPE_SHADER_VERTEX
&& shader
->key
.vs
.as_ls
) ||
5694 ctx
->type
== PIPE_SHADER_TESS_CTRL
||
5695 ctx
->type
== PIPE_SHADER_TESS_EVAL
)
5696 declare_tess_lds(ctx
);
5699 static void preload_constants(struct si_shader_context
*ctx
)
5701 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
5702 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5703 const struct tgsi_shader_info
*info
= bld_base
->info
;
5705 LLVMValueRef ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_CONST_BUFFERS
);
5707 for (buf
= 0; buf
< SI_NUM_CONST_BUFFERS
; buf
++) {
5708 unsigned i
, num_const
= info
->const_file_max
[buf
] + 1;
5713 /* Allocate space for the constant values */
5714 ctx
->constants
[buf
] = CALLOC(num_const
* 4, sizeof(LLVMValueRef
));
5716 /* Load the resource descriptor */
5717 ctx
->const_buffers
[buf
] =
5718 build_indexed_load_const(ctx
, ptr
, lp_build_const_int32(gallivm
, buf
));
5720 /* Load the constants, we rely on the code sinking to do the rest */
5721 for (i
= 0; i
< num_const
* 4; ++i
) {
5722 ctx
->constants
[buf
][i
] =
5723 buffer_load_const(ctx
,
5724 ctx
->const_buffers
[buf
],
5725 lp_build_const_int32(gallivm
, i
* 4));
5730 static void preload_shader_buffers(struct si_shader_context
*ctx
)
5732 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
5733 LLVMValueRef ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_SHADER_BUFFERS
);
5736 maxbuf
= MIN2(ctx
->shader
->selector
->info
.file_max
[TGSI_FILE_BUFFER
],
5737 SI_NUM_SHADER_BUFFERS
- 1);
5738 for (buf
= 0; buf
<= maxbuf
; ++buf
) {
5739 ctx
->shader_buffers
[buf
] =
5740 build_indexed_load_const(
5741 ctx
, ptr
, lp_build_const_int32(gallivm
, buf
));
5745 static void preload_samplers(struct si_shader_context
*ctx
)
5747 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
5748 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5749 const struct tgsi_shader_info
*info
= bld_base
->info
;
5750 unsigned i
, num_samplers
= info
->file_max
[TGSI_FILE_SAMPLER
] + 1;
5751 LLVMValueRef offset
;
5753 if (num_samplers
== 0)
5756 /* Load the resources and samplers, we rely on the code sinking to do the rest */
5757 for (i
= 0; i
< num_samplers
; ++i
) {
5759 offset
= lp_build_const_int32(gallivm
, i
);
5760 ctx
->sampler_views
[i
] =
5761 get_sampler_desc(ctx
, offset
, DESC_IMAGE
);
5763 /* FMASK resource */
5764 if (info
->is_msaa_sampler
[i
])
5766 get_sampler_desc(ctx
, offset
, DESC_FMASK
);
5768 ctx
->sampler_states
[i
] =
5769 get_sampler_desc(ctx
, offset
, DESC_SAMPLER
);
5770 ctx
->sampler_states
[i
] =
5771 sici_fix_sampler_aniso(ctx
, ctx
->sampler_views
[i
],
5772 ctx
->sampler_states
[i
]);
5777 static void preload_images(struct si_shader_context
*ctx
)
5779 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
5780 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
5781 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5782 unsigned num_images
= bld_base
->info
->file_max
[TGSI_FILE_IMAGE
] + 1;
5783 LLVMValueRef res_ptr
;
5786 if (num_images
== 0)
5789 res_ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_IMAGES
);
5791 for (i
= 0; i
< num_images
; ++i
) {
5792 /* Rely on LLVM to shrink the load for buffer resources. */
5794 build_indexed_load_const(ctx
, res_ptr
,
5795 lp_build_const_int32(gallivm
, i
));
5797 if (info
->images_writemask
& (1 << i
) &&
5798 !(info
->images_buffers
& (1 << i
)))
5799 rsrc
= force_dcc_off(ctx
, rsrc
);
5801 ctx
->images
[i
] = rsrc
;
5805 static void preload_streamout_buffers(struct si_shader_context
*ctx
)
5807 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
5808 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5811 /* Streamout can only be used if the shader is compiled as VS. */
5812 if (!ctx
->shader
->selector
->so
.num_outputs
||
5813 (ctx
->type
== PIPE_SHADER_VERTEX
&&
5814 (ctx
->shader
->key
.vs
.as_es
||
5815 ctx
->shader
->key
.vs
.as_ls
)) ||
5816 (ctx
->type
== PIPE_SHADER_TESS_EVAL
&&
5817 ctx
->shader
->key
.tes
.as_es
))
5820 LLVMValueRef buf_ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
5821 SI_PARAM_RW_BUFFERS
);
5823 /* Load the resources, we rely on the code sinking to do the rest */
5824 for (i
= 0; i
< 4; ++i
) {
5825 if (ctx
->shader
->selector
->so
.stride
[i
]) {
5826 LLVMValueRef offset
= lp_build_const_int32(gallivm
,
5827 SI_VS_STREAMOUT_BUF0
+ i
);
5829 ctx
->so_buffers
[i
] = build_indexed_load_const(ctx
, buf_ptr
, offset
);
5835 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5838 static void preload_ring_buffers(struct si_shader_context
*ctx
)
5840 struct gallivm_state
*gallivm
=
5841 ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
5843 LLVMValueRef buf_ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
5844 SI_PARAM_RW_BUFFERS
);
5846 if ((ctx
->type
== PIPE_SHADER_VERTEX
&&
5847 ctx
->shader
->key
.vs
.as_es
) ||
5848 (ctx
->type
== PIPE_SHADER_TESS_EVAL
&&
5849 ctx
->shader
->key
.tes
.as_es
) ||
5850 ctx
->type
== PIPE_SHADER_GEOMETRY
) {
5852 ctx
->type
== PIPE_SHADER_GEOMETRY
? SI_GS_RING_ESGS
5854 LLVMValueRef offset
= lp_build_const_int32(gallivm
, ring
);
5857 build_indexed_load_const(ctx
, buf_ptr
, offset
);
5860 if (ctx
->is_gs_copy_shader
) {
5861 LLVMValueRef offset
= lp_build_const_int32(gallivm
, SI_VS_RING_GSVS
);
5864 build_indexed_load_const(ctx
, buf_ptr
, offset
);
5866 if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
5868 for (i
= 0; i
< 4; i
++) {
5869 LLVMValueRef offset
= lp_build_const_int32(gallivm
, SI_GS_RING_GSVS0
+ i
);
5872 build_indexed_load_const(ctx
, buf_ptr
, offset
);
5877 static void si_llvm_emit_polygon_stipple(struct si_shader_context
*ctx
,
5878 LLVMValueRef param_rw_buffers
,
5879 unsigned param_pos_fixed_pt
)
5881 struct lp_build_tgsi_context
*bld_base
=
5882 &ctx
->radeon_bld
.soa
.bld_base
;
5883 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5884 LLVMBuilderRef builder
= gallivm
->builder
;
5885 LLVMValueRef slot
, desc
, offset
, row
, bit
, address
[2];
5887 /* Use the fixed-point gl_FragCoord input.
5888 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5889 * per coordinate to get the repeating effect.
5891 address
[0] = unpack_param(ctx
, param_pos_fixed_pt
, 0, 5);
5892 address
[1] = unpack_param(ctx
, param_pos_fixed_pt
, 16, 5);
5894 /* Load the buffer descriptor. */
5895 slot
= lp_build_const_int32(gallivm
, SI_PS_CONST_POLY_STIPPLE
);
5896 desc
= build_indexed_load_const(ctx
, param_rw_buffers
, slot
);
5898 /* The stipple pattern is 32x32, each row has 32 bits. */
5899 offset
= LLVMBuildMul(builder
, address
[1],
5900 LLVMConstInt(ctx
->i32
, 4, 0), "");
5901 row
= buffer_load_const(ctx
, desc
, offset
);
5902 row
= LLVMBuildBitCast(builder
, row
, ctx
->i32
, "");
5903 bit
= LLVMBuildLShr(builder
, row
, address
[0], "");
5904 bit
= LLVMBuildTrunc(builder
, bit
, ctx
->i1
, "");
5906 /* The intrinsic kills the thread if arg < 0. */
5907 bit
= LLVMBuildSelect(builder
, bit
, LLVMConstReal(ctx
->f32
, 0),
5908 LLVMConstReal(ctx
->f32
, -1), "");
5909 lp_build_intrinsic(builder
, "llvm.AMDGPU.kill", ctx
->voidt
, &bit
, 1, 0);
5912 void si_shader_binary_read_config(struct radeon_shader_binary
*binary
,
5913 struct si_shader_config
*conf
,
5914 unsigned symbol_offset
)
5917 const unsigned char *config
=
5918 radeon_shader_binary_config_start(binary
, symbol_offset
);
5919 bool really_needs_scratch
= false;
5921 /* LLVM adds SGPR spills to the scratch size.
5922 * Find out if we really need the scratch buffer.
5924 for (i
= 0; i
< binary
->reloc_count
; i
++) {
5925 const struct radeon_shader_reloc
*reloc
= &binary
->relocs
[i
];
5927 if (!strcmp(scratch_rsrc_dword0_symbol
, reloc
->name
) ||
5928 !strcmp(scratch_rsrc_dword1_symbol
, reloc
->name
)) {
5929 really_needs_scratch
= true;
5934 /* XXX: We may be able to emit some of these values directly rather than
5935 * extracting fields to be emitted later.
5938 for (i
= 0; i
< binary
->config_size_per_symbol
; i
+= 8) {
5939 unsigned reg
= util_le32_to_cpu(*(uint32_t*)(config
+ i
));
5940 unsigned value
= util_le32_to_cpu(*(uint32_t*)(config
+ i
+ 4));
5942 case R_00B028_SPI_SHADER_PGM_RSRC1_PS
:
5943 case R_00B128_SPI_SHADER_PGM_RSRC1_VS
:
5944 case R_00B228_SPI_SHADER_PGM_RSRC1_GS
:
5945 case R_00B848_COMPUTE_PGM_RSRC1
:
5946 conf
->num_sgprs
= MAX2(conf
->num_sgprs
, (G_00B028_SGPRS(value
) + 1) * 8);
5947 conf
->num_vgprs
= MAX2(conf
->num_vgprs
, (G_00B028_VGPRS(value
) + 1) * 4);
5948 conf
->float_mode
= G_00B028_FLOAT_MODE(value
);
5949 conf
->rsrc1
= value
;
5951 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS
:
5952 conf
->lds_size
= MAX2(conf
->lds_size
, G_00B02C_EXTRA_LDS_SIZE(value
));
5954 case R_00B84C_COMPUTE_PGM_RSRC2
:
5955 conf
->lds_size
= MAX2(conf
->lds_size
, G_00B84C_LDS_SIZE(value
));
5956 conf
->rsrc2
= value
;
5958 case R_0286CC_SPI_PS_INPUT_ENA
:
5959 conf
->spi_ps_input_ena
= value
;
5961 case R_0286D0_SPI_PS_INPUT_ADDR
:
5962 conf
->spi_ps_input_addr
= value
;
5964 case R_0286E8_SPI_TMPRING_SIZE
:
5965 case R_00B860_COMPUTE_TMPRING_SIZE
:
5966 /* WAVESIZE is in units of 256 dwords. */
5967 if (really_needs_scratch
)
5968 conf
->scratch_bytes_per_wave
=
5969 G_00B860_WAVESIZE(value
) * 256 * 4;
5971 case 0x4: /* SPILLED_SGPRS */
5972 conf
->spilled_sgprs
= value
;
5974 case 0x8: /* SPILLED_VGPRS */
5975 conf
->spilled_vgprs
= value
;
5979 static bool printed
;
5982 fprintf(stderr
, "Warning: LLVM emitted unknown "
5983 "config register: 0x%x\n", reg
);
5991 if (!conf
->spi_ps_input_addr
)
5992 conf
->spi_ps_input_addr
= conf
->spi_ps_input_ena
;
5995 void si_shader_apply_scratch_relocs(struct si_context
*sctx
,
5996 struct si_shader
*shader
,
5997 struct si_shader_config
*config
,
5998 uint64_t scratch_va
)
6001 uint32_t scratch_rsrc_dword0
= scratch_va
;
6002 uint32_t scratch_rsrc_dword1
=
6003 S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32);
6005 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
6008 if (HAVE_LLVM
>= 0x0309)
6009 scratch_rsrc_dword1
|= S_008F04_SWIZZLE_ENABLE(1);
6011 scratch_rsrc_dword1
|=
6012 S_008F04_STRIDE(config
->scratch_bytes_per_wave
/ 64);
6014 for (i
= 0 ; i
< shader
->binary
.reloc_count
; i
++) {
6015 const struct radeon_shader_reloc
*reloc
=
6016 &shader
->binary
.relocs
[i
];
6017 if (!strcmp(scratch_rsrc_dword0_symbol
, reloc
->name
)) {
6018 util_memcpy_cpu_to_le32(shader
->binary
.code
+ reloc
->offset
,
6019 &scratch_rsrc_dword0
, 4);
6020 } else if (!strcmp(scratch_rsrc_dword1_symbol
, reloc
->name
)) {
6021 util_memcpy_cpu_to_le32(shader
->binary
.code
+ reloc
->offset
,
6022 &scratch_rsrc_dword1
, 4);
6027 static unsigned si_get_shader_binary_size(struct si_shader
*shader
)
6029 unsigned size
= shader
->binary
.code_size
;
6032 size
+= shader
->prolog
->binary
.code_size
;
6034 size
+= shader
->epilog
->binary
.code_size
;
6038 int si_shader_binary_upload(struct si_screen
*sscreen
, struct si_shader
*shader
)
6040 const struct radeon_shader_binary
*prolog
=
6041 shader
->prolog
? &shader
->prolog
->binary
: NULL
;
6042 const struct radeon_shader_binary
*epilog
=
6043 shader
->epilog
? &shader
->epilog
->binary
: NULL
;
6044 const struct radeon_shader_binary
*mainb
= &shader
->binary
;
6045 unsigned bo_size
= si_get_shader_binary_size(shader
) +
6046 (!epilog
? mainb
->rodata_size
: 0);
6049 assert(!prolog
|| !prolog
->rodata_size
);
6050 assert((!prolog
&& !epilog
) || !mainb
->rodata_size
);
6051 assert(!epilog
|| !epilog
->rodata_size
);
6053 r600_resource_reference(&shader
->bo
, NULL
);
6054 shader
->bo
= si_resource_create_custom(&sscreen
->b
.b
,
6055 PIPE_USAGE_IMMUTABLE
,
6061 ptr
= sscreen
->b
.ws
->buffer_map(shader
->bo
->buf
, NULL
,
6062 PIPE_TRANSFER_READ_WRITE
);
6065 util_memcpy_cpu_to_le32(ptr
, prolog
->code
, prolog
->code_size
);
6066 ptr
+= prolog
->code_size
;
6069 util_memcpy_cpu_to_le32(ptr
, mainb
->code
, mainb
->code_size
);
6070 ptr
+= mainb
->code_size
;
6073 util_memcpy_cpu_to_le32(ptr
, epilog
->code
, epilog
->code_size
);
6074 else if (mainb
->rodata_size
> 0)
6075 util_memcpy_cpu_to_le32(ptr
, mainb
->rodata
, mainb
->rodata_size
);
6077 sscreen
->b
.ws
->buffer_unmap(shader
->bo
->buf
);
6081 static void si_shader_dump_disassembly(const struct radeon_shader_binary
*binary
,
6082 struct pipe_debug_callback
*debug
,
6083 const char *name
, FILE *file
)
6088 if (binary
->disasm_string
) {
6089 fprintf(file
, "Shader %s disassembly:\n", name
);
6090 fprintf(file
, "%s", binary
->disasm_string
);
6092 if (debug
&& debug
->debug_message
) {
6093 /* Very long debug messages are cut off, so send the
6094 * disassembly one line at a time. This causes more
6095 * overhead, but on the plus side it simplifies
6096 * parsing of resulting logs.
6098 pipe_debug_message(debug
, SHADER_INFO
,
6099 "Shader Disassembly Begin");
6101 line
= binary
->disasm_string
;
6103 p
= util_strchrnul(line
, '\n');
6107 pipe_debug_message(debug
, SHADER_INFO
,
6108 "%.*s", count
, line
);
6116 pipe_debug_message(debug
, SHADER_INFO
,
6117 "Shader Disassembly End");
6120 fprintf(file
, "Shader %s binary:\n", name
);
6121 for (i
= 0; i
< binary
->code_size
; i
+= 4) {
6122 fprintf(file
, "@0x%x: %02x%02x%02x%02x\n", i
,
6123 binary
->code
[i
+ 3], binary
->code
[i
+ 2],
6124 binary
->code
[i
+ 1], binary
->code
[i
]);
6129 static void si_shader_dump_stats(struct si_screen
*sscreen
,
6130 struct si_shader_config
*conf
,
6131 unsigned num_inputs
,
6133 struct pipe_debug_callback
*debug
,
6137 unsigned lds_increment
= sscreen
->b
.chip_class
>= CIK
? 512 : 256;
6138 unsigned lds_per_wave
= 0;
6139 unsigned max_simd_waves
= 10;
6141 /* Compute LDS usage for PS. */
6142 if (processor
== PIPE_SHADER_FRAGMENT
) {
6143 /* The minimum usage per wave is (num_inputs * 48). The maximum
6144 * usage is (num_inputs * 48 * 16).
6145 * We can get anything in between and it varies between waves.
6147 * The 48 bytes per input for a single primitive is equal to
6148 * 4 bytes/component * 4 components/input * 3 points.
6150 * Other stages don't know the size at compile time or don't
6151 * allocate LDS per wave, but instead they do it per thread group.
6153 lds_per_wave
= conf
->lds_size
* lds_increment
+
6154 align(num_inputs
* 48, lds_increment
);
6157 /* Compute the per-SIMD wave counts. */
6158 if (conf
->num_sgprs
) {
6159 if (sscreen
->b
.chip_class
>= VI
)
6160 max_simd_waves
= MIN2(max_simd_waves
, 800 / conf
->num_sgprs
);
6162 max_simd_waves
= MIN2(max_simd_waves
, 512 / conf
->num_sgprs
);
6165 if (conf
->num_vgprs
)
6166 max_simd_waves
= MIN2(max_simd_waves
, 256 / conf
->num_vgprs
);
6168 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
6172 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
6174 if (file
!= stderr
||
6175 r600_can_dump_shader(&sscreen
->b
, processor
)) {
6176 if (processor
== PIPE_SHADER_FRAGMENT
) {
6177 fprintf(file
, "*** SHADER CONFIG ***\n"
6178 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6179 "SPI_PS_INPUT_ENA = 0x%04x\n",
6180 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
6183 fprintf(file
, "*** SHADER STATS ***\n"
6186 "Spilled SGPRs: %d\n"
6187 "Spilled VGPRs: %d\n"
6188 "Code Size: %d bytes\n"
6190 "Scratch: %d bytes per wave\n"
6192 "********************\n\n\n",
6193 conf
->num_sgprs
, conf
->num_vgprs
,
6194 conf
->spilled_sgprs
, conf
->spilled_vgprs
, code_size
,
6195 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
6199 pipe_debug_message(debug
, SHADER_INFO
,
6200 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6201 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
6202 "Spilled VGPRs: %d",
6203 conf
->num_sgprs
, conf
->num_vgprs
, code_size
,
6204 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
6205 max_simd_waves
, conf
->spilled_sgprs
,
6206 conf
->spilled_vgprs
);
6209 static const char *si_get_shader_name(struct si_shader
*shader
,
6212 switch (processor
) {
6213 case PIPE_SHADER_VERTEX
:
6214 if (shader
->key
.vs
.as_es
)
6215 return "Vertex Shader as ES";
6216 else if (shader
->key
.vs
.as_ls
)
6217 return "Vertex Shader as LS";
6219 return "Vertex Shader as VS";
6220 case PIPE_SHADER_TESS_CTRL
:
6221 return "Tessellation Control Shader";
6222 case PIPE_SHADER_TESS_EVAL
:
6223 if (shader
->key
.tes
.as_es
)
6224 return "Tessellation Evaluation Shader as ES";
6226 return "Tessellation Evaluation Shader as VS";
6227 case PIPE_SHADER_GEOMETRY
:
6228 if (shader
->gs_copy_shader
== NULL
)
6229 return "GS Copy Shader as VS";
6231 return "Geometry Shader";
6232 case PIPE_SHADER_FRAGMENT
:
6233 return "Pixel Shader";
6234 case PIPE_SHADER_COMPUTE
:
6235 return "Compute Shader";
6237 return "Unknown Shader";
6241 void si_shader_dump(struct si_screen
*sscreen
, struct si_shader
*shader
,
6242 struct pipe_debug_callback
*debug
, unsigned processor
,
6245 if (file
!= stderr
||
6246 r600_can_dump_shader(&sscreen
->b
, processor
))
6247 si_dump_shader_key(processor
, &shader
->key
, file
);
6249 if (file
!= stderr
&& shader
->binary
.llvm_ir_string
) {
6250 fprintf(file
, "\n%s - main shader part - LLVM IR:\n\n",
6251 si_get_shader_name(shader
, processor
));
6252 fprintf(file
, "%s\n", shader
->binary
.llvm_ir_string
);
6255 if (file
!= stderr
||
6256 (r600_can_dump_shader(&sscreen
->b
, processor
) &&
6257 !(sscreen
->b
.debug_flags
& DBG_NO_ASM
))) {
6258 fprintf(file
, "\n%s:\n", si_get_shader_name(shader
, processor
));
6261 si_shader_dump_disassembly(&shader
->prolog
->binary
,
6262 debug
, "prolog", file
);
6264 si_shader_dump_disassembly(&shader
->binary
, debug
, "main", file
);
6267 si_shader_dump_disassembly(&shader
->epilog
->binary
,
6268 debug
, "epilog", file
);
6269 fprintf(file
, "\n");
6272 si_shader_dump_stats(sscreen
, &shader
->config
,
6273 shader
->selector
? shader
->selector
->info
.num_inputs
: 0,
6274 si_get_shader_binary_size(shader
), debug
, processor
,
6278 int si_compile_llvm(struct si_screen
*sscreen
,
6279 struct radeon_shader_binary
*binary
,
6280 struct si_shader_config
*conf
,
6281 LLVMTargetMachineRef tm
,
6283 struct pipe_debug_callback
*debug
,
6288 unsigned count
= p_atomic_inc_return(&sscreen
->b
.num_compilations
);
6290 if (r600_can_dump_shader(&sscreen
->b
, processor
)) {
6291 fprintf(stderr
, "radeonsi: Compiling shader %d\n", count
);
6293 if (!(sscreen
->b
.debug_flags
& (DBG_NO_IR
| DBG_PREOPT_IR
))) {
6294 fprintf(stderr
, "%s LLVM IR:\n\n", name
);
6295 LLVMDumpModule(mod
);
6296 fprintf(stderr
, "\n");
6300 if (sscreen
->record_llvm_ir
) {
6301 char *ir
= LLVMPrintModuleToString(mod
);
6302 binary
->llvm_ir_string
= strdup(ir
);
6303 LLVMDisposeMessage(ir
);
6306 if (!si_replace_shader(count
, binary
)) {
6307 r
= radeon_llvm_compile(mod
, binary
, tm
, debug
);
6312 si_shader_binary_read_config(binary
, conf
, 0);
6314 /* Enable 64-bit and 16-bit denormals, because there is no performance
6317 * If denormals are enabled, all floating-point output modifiers are
6320 * Don't enable denormals for 32-bit floats, because:
6321 * - Floating-point output modifiers would be ignored by the hw.
6322 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6323 * have to stop using those.
6324 * - SI & CI would be very slow.
6326 conf
->float_mode
|= V_00B028_FP_64_DENORMS
;
6328 FREE(binary
->config
);
6329 FREE(binary
->global_symbol_offsets
);
6330 binary
->config
= NULL
;
6331 binary
->global_symbol_offsets
= NULL
;
6333 /* Some shaders can't have rodata because their binaries can be
6336 if (binary
->rodata_size
&&
6337 (processor
== PIPE_SHADER_VERTEX
||
6338 processor
== PIPE_SHADER_TESS_CTRL
||
6339 processor
== PIPE_SHADER_TESS_EVAL
||
6340 processor
== PIPE_SHADER_FRAGMENT
)) {
6341 fprintf(stderr
, "radeonsi: The shader can't have rodata.");
6348 static void si_llvm_build_ret(struct si_shader_context
*ctx
, LLVMValueRef ret
)
6350 if (LLVMGetTypeKind(LLVMTypeOf(ret
)) == LLVMVoidTypeKind
)
6351 LLVMBuildRetVoid(ctx
->radeon_bld
.gallivm
.builder
);
6353 LLVMBuildRet(ctx
->radeon_bld
.gallivm
.builder
, ret
);
6356 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6357 static int si_generate_gs_copy_shader(struct si_screen
*sscreen
,
6358 struct si_shader_context
*ctx
,
6359 struct si_shader
*gs
,
6360 struct pipe_debug_callback
*debug
)
6362 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
6363 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
6364 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
6365 struct si_shader_output_values
*outputs
;
6366 struct tgsi_shader_info
*gsinfo
= &gs
->selector
->info
;
6367 LLVMValueRef args
[9];
6370 outputs
= MALLOC(gsinfo
->num_outputs
* sizeof(outputs
[0]));
6372 si_init_shader_ctx(ctx
, sscreen
, ctx
->shader
, ctx
->tm
);
6373 ctx
->type
= PIPE_SHADER_VERTEX
;
6374 ctx
->is_gs_copy_shader
= true;
6376 create_meta_data(ctx
);
6377 create_function(ctx
);
6378 preload_streamout_buffers(ctx
);
6379 preload_ring_buffers(ctx
);
6381 args
[0] = ctx
->gsvs_ring
[0];
6382 args
[1] = lp_build_mul_imm(uint
,
6383 LLVMGetParam(ctx
->radeon_bld
.main_fn
,
6384 ctx
->param_vertex_id
),
6386 args
[3] = uint
->zero
;
6387 args
[4] = uint
->one
; /* OFFEN */
6388 args
[5] = uint
->zero
; /* IDXEN */
6389 args
[6] = uint
->one
; /* GLC */
6390 args
[7] = uint
->one
; /* SLC */
6391 args
[8] = uint
->zero
; /* TFE */
6393 /* Fetch vertex data from GSVS ring */
6394 for (i
= 0; i
< gsinfo
->num_outputs
; ++i
) {
6397 outputs
[i
].name
= gsinfo
->output_semantic_name
[i
];
6398 outputs
[i
].sid
= gsinfo
->output_semantic_index
[i
];
6400 for (chan
= 0; chan
< 4; chan
++) {
6401 args
[2] = lp_build_const_int32(gallivm
,
6403 gs
->selector
->gs_max_out_vertices
* 16 * 4);
6405 outputs
[i
].values
[chan
] =
6406 LLVMBuildBitCast(gallivm
->builder
,
6407 lp_build_intrinsic(gallivm
->builder
,
6408 "llvm.SI.buffer.load.dword.i32.i32",
6410 LLVMReadOnlyAttribute
),
6415 si_llvm_export_vs(bld_base
, outputs
, gsinfo
->num_outputs
);
6417 LLVMBuildRetVoid(gallivm
->builder
);
6419 /* Dump LLVM IR before any optimization passes */
6420 if (sscreen
->b
.debug_flags
& DBG_PREOPT_IR
&&
6421 r600_can_dump_shader(&sscreen
->b
, PIPE_SHADER_GEOMETRY
))
6422 LLVMDumpModule(bld_base
->base
.gallivm
->module
);
6424 radeon_llvm_finalize_module(&ctx
->radeon_bld
);
6426 r
= si_compile_llvm(sscreen
, &ctx
->shader
->binary
,
6427 &ctx
->shader
->config
, ctx
->tm
,
6428 bld_base
->base
.gallivm
->module
,
6429 debug
, PIPE_SHADER_GEOMETRY
,
6432 if (r600_can_dump_shader(&sscreen
->b
, PIPE_SHADER_GEOMETRY
))
6433 fprintf(stderr
, "GS Copy Shader:\n");
6434 si_shader_dump(sscreen
, ctx
->shader
, debug
,
6435 PIPE_SHADER_GEOMETRY
, stderr
);
6436 r
= si_shader_binary_upload(sscreen
, ctx
->shader
);
6439 radeon_llvm_dispose(&ctx
->radeon_bld
);
6445 static void si_dump_shader_key(unsigned shader
, union si_shader_key
*key
,
6450 fprintf(f
, "SHADER KEY\n");
6453 case PIPE_SHADER_VERTEX
:
6454 fprintf(f
, " instance_divisors = {");
6455 for (i
= 0; i
< ARRAY_SIZE(key
->vs
.prolog
.instance_divisors
); i
++)
6456 fprintf(f
, !i
? "%u" : ", %u",
6457 key
->vs
.prolog
.instance_divisors
[i
]);
6459 fprintf(f
, " as_es = %u\n", key
->vs
.as_es
);
6460 fprintf(f
, " as_ls = %u\n", key
->vs
.as_ls
);
6461 fprintf(f
, " export_prim_id = %u\n", key
->vs
.epilog
.export_prim_id
);
6464 case PIPE_SHADER_TESS_CTRL
:
6465 fprintf(f
, " prim_mode = %u\n", key
->tcs
.epilog
.prim_mode
);
6468 case PIPE_SHADER_TESS_EVAL
:
6469 fprintf(f
, " as_es = %u\n", key
->tes
.as_es
);
6470 fprintf(f
, " export_prim_id = %u\n", key
->tes
.epilog
.export_prim_id
);
6473 case PIPE_SHADER_GEOMETRY
:
6474 case PIPE_SHADER_COMPUTE
:
6477 case PIPE_SHADER_FRAGMENT
:
6478 fprintf(f
, " prolog.color_two_side = %u\n", key
->ps
.prolog
.color_two_side
);
6479 fprintf(f
, " prolog.flatshade_colors = %u\n", key
->ps
.prolog
.flatshade_colors
);
6480 fprintf(f
, " prolog.poly_stipple = %u\n", key
->ps
.prolog
.poly_stipple
);
6481 fprintf(f
, " prolog.force_persp_sample_interp = %u\n", key
->ps
.prolog
.force_persp_sample_interp
);
6482 fprintf(f
, " prolog.force_linear_sample_interp = %u\n", key
->ps
.prolog
.force_linear_sample_interp
);
6483 fprintf(f
, " prolog.force_persp_center_interp = %u\n", key
->ps
.prolog
.force_persp_center_interp
);
6484 fprintf(f
, " prolog.force_linear_center_interp = %u\n", key
->ps
.prolog
.force_linear_center_interp
);
6485 fprintf(f
, " prolog.bc_optimize_for_persp = %u\n", key
->ps
.prolog
.bc_optimize_for_persp
);
6486 fprintf(f
, " prolog.bc_optimize_for_linear = %u\n", key
->ps
.prolog
.bc_optimize_for_linear
);
6487 fprintf(f
, " epilog.spi_shader_col_format = 0x%x\n", key
->ps
.epilog
.spi_shader_col_format
);
6488 fprintf(f
, " epilog.color_is_int8 = 0x%X\n", key
->ps
.epilog
.color_is_int8
);
6489 fprintf(f
, " epilog.last_cbuf = %u\n", key
->ps
.epilog
.last_cbuf
);
6490 fprintf(f
, " epilog.alpha_func = %u\n", key
->ps
.epilog
.alpha_func
);
6491 fprintf(f
, " epilog.alpha_to_one = %u\n", key
->ps
.epilog
.alpha_to_one
);
6492 fprintf(f
, " epilog.poly_line_smoothing = %u\n", key
->ps
.epilog
.poly_line_smoothing
);
6493 fprintf(f
, " epilog.clamp_color = %u\n", key
->ps
.epilog
.clamp_color
);
6501 static void si_init_shader_ctx(struct si_shader_context
*ctx
,
6502 struct si_screen
*sscreen
,
6503 struct si_shader
*shader
,
6504 LLVMTargetMachineRef tm
)
6506 struct lp_build_tgsi_context
*bld_base
;
6507 struct lp_build_tgsi_action tmpl
= {};
6509 memset(ctx
, 0, sizeof(*ctx
));
6510 radeon_llvm_context_init(
6511 &ctx
->radeon_bld
, "amdgcn--",
6512 (shader
&& shader
->selector
) ? &shader
->selector
->info
: NULL
,
6513 (shader
&& shader
->selector
) ? shader
->selector
->tokens
: NULL
);
6515 ctx
->screen
= sscreen
;
6516 if (shader
&& shader
->selector
)
6517 ctx
->type
= shader
->selector
->info
.processor
;
6520 ctx
->shader
= shader
;
6522 ctx
->voidt
= LLVMVoidTypeInContext(ctx
->radeon_bld
.gallivm
.context
);
6523 ctx
->i1
= LLVMInt1TypeInContext(ctx
->radeon_bld
.gallivm
.context
);
6524 ctx
->i8
= LLVMInt8TypeInContext(ctx
->radeon_bld
.gallivm
.context
);
6525 ctx
->i32
= LLVMInt32TypeInContext(ctx
->radeon_bld
.gallivm
.context
);
6526 ctx
->i64
= LLVMInt64TypeInContext(ctx
->radeon_bld
.gallivm
.context
);
6527 ctx
->i128
= LLVMIntTypeInContext(ctx
->radeon_bld
.gallivm
.context
, 128);
6528 ctx
->f32
= LLVMFloatTypeInContext(ctx
->radeon_bld
.gallivm
.context
);
6529 ctx
->v16i8
= LLVMVectorType(ctx
->i8
, 16);
6530 ctx
->v2i32
= LLVMVectorType(ctx
->i32
, 2);
6531 ctx
->v4i32
= LLVMVectorType(ctx
->i32
, 4);
6532 ctx
->v4f32
= LLVMVectorType(ctx
->f32
, 4);
6533 ctx
->v8i32
= LLVMVectorType(ctx
->i32
, 8);
6535 bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
6536 bld_base
->emit_fetch_funcs
[TGSI_FILE_CONSTANT
] = fetch_constant
;
6538 bld_base
->op_actions
[TGSI_OPCODE_INTERP_CENTROID
] = interp_action
;
6539 bld_base
->op_actions
[TGSI_OPCODE_INTERP_SAMPLE
] = interp_action
;
6540 bld_base
->op_actions
[TGSI_OPCODE_INTERP_OFFSET
] = interp_action
;
6542 bld_base
->op_actions
[TGSI_OPCODE_TEX
] = tex_action
;
6543 bld_base
->op_actions
[TGSI_OPCODE_TEX2
] = tex_action
;
6544 bld_base
->op_actions
[TGSI_OPCODE_TXB
] = tex_action
;
6545 bld_base
->op_actions
[TGSI_OPCODE_TXB2
] = tex_action
;
6546 bld_base
->op_actions
[TGSI_OPCODE_TXD
] = tex_action
;
6547 bld_base
->op_actions
[TGSI_OPCODE_TXF
] = tex_action
;
6548 bld_base
->op_actions
[TGSI_OPCODE_TXL
] = tex_action
;
6549 bld_base
->op_actions
[TGSI_OPCODE_TXL2
] = tex_action
;
6550 bld_base
->op_actions
[TGSI_OPCODE_TXP
] = tex_action
;
6551 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].fetch_args
= txq_fetch_args
;
6552 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].emit
= txq_emit
;
6553 bld_base
->op_actions
[TGSI_OPCODE_TG4
] = tex_action
;
6554 bld_base
->op_actions
[TGSI_OPCODE_LODQ
] = tex_action
;
6555 bld_base
->op_actions
[TGSI_OPCODE_TXQS
].emit
= si_llvm_emit_txqs
;
6557 bld_base
->op_actions
[TGSI_OPCODE_LOAD
].fetch_args
= load_fetch_args
;
6558 bld_base
->op_actions
[TGSI_OPCODE_LOAD
].emit
= load_emit
;
6559 bld_base
->op_actions
[TGSI_OPCODE_STORE
].fetch_args
= store_fetch_args
;
6560 bld_base
->op_actions
[TGSI_OPCODE_STORE
].emit
= store_emit
;
6561 bld_base
->op_actions
[TGSI_OPCODE_RESQ
].fetch_args
= resq_fetch_args
;
6562 bld_base
->op_actions
[TGSI_OPCODE_RESQ
].emit
= resq_emit
;
6564 tmpl
.fetch_args
= atomic_fetch_args
;
6565 tmpl
.emit
= atomic_emit
;
6566 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
] = tmpl
;
6567 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
].intr_name
= "add";
6568 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
] = tmpl
;
6569 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
].intr_name
= "swap";
6570 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
] = tmpl
;
6571 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
].intr_name
= "cmpswap";
6572 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
] = tmpl
;
6573 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
].intr_name
= "and";
6574 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
] = tmpl
;
6575 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
].intr_name
= "or";
6576 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
] = tmpl
;
6577 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
].intr_name
= "xor";
6578 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
] = tmpl
;
6579 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
].intr_name
= "umin";
6580 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
] = tmpl
;
6581 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
].intr_name
= "umax";
6582 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
] = tmpl
;
6583 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
].intr_name
= "smin";
6584 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
] = tmpl
;
6585 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
].intr_name
= "smax";
6587 bld_base
->op_actions
[TGSI_OPCODE_MEMBAR
].emit
= membar_emit
;
6589 bld_base
->op_actions
[TGSI_OPCODE_DDX
].emit
= si_llvm_emit_ddxy
;
6590 bld_base
->op_actions
[TGSI_OPCODE_DDY
].emit
= si_llvm_emit_ddxy
;
6591 bld_base
->op_actions
[TGSI_OPCODE_DDX_FINE
].emit
= si_llvm_emit_ddxy
;
6592 bld_base
->op_actions
[TGSI_OPCODE_DDY_FINE
].emit
= si_llvm_emit_ddxy
;
6594 bld_base
->op_actions
[TGSI_OPCODE_EMIT
].emit
= si_llvm_emit_vertex
;
6595 bld_base
->op_actions
[TGSI_OPCODE_ENDPRIM
].emit
= si_llvm_emit_primitive
;
6596 bld_base
->op_actions
[TGSI_OPCODE_BARRIER
].emit
= si_llvm_emit_barrier
;
6598 bld_base
->op_actions
[TGSI_OPCODE_MAX
].emit
= build_tgsi_intrinsic_nomem
;
6599 bld_base
->op_actions
[TGSI_OPCODE_MAX
].intr_name
= "llvm.maxnum.f32";
6600 bld_base
->op_actions
[TGSI_OPCODE_MIN
].emit
= build_tgsi_intrinsic_nomem
;
6601 bld_base
->op_actions
[TGSI_OPCODE_MIN
].intr_name
= "llvm.minnum.f32";
6604 int si_compile_tgsi_shader(struct si_screen
*sscreen
,
6605 LLVMTargetMachineRef tm
,
6606 struct si_shader
*shader
,
6608 struct pipe_debug_callback
*debug
)
6610 struct si_shader_selector
*sel
= shader
->selector
;
6611 struct si_shader_context ctx
;
6612 struct lp_build_tgsi_context
*bld_base
;
6616 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6617 * conversion fails. */
6618 if (r600_can_dump_shader(&sscreen
->b
, sel
->info
.processor
) &&
6619 !(sscreen
->b
.debug_flags
& DBG_NO_TGSI
)) {
6620 tgsi_dump(sel
->tokens
, 0);
6621 si_dump_streamout(&sel
->so
);
6624 si_init_shader_ctx(&ctx
, sscreen
, shader
, tm
);
6625 ctx
.is_monolithic
= is_monolithic
;
6627 shader
->info
.uses_instanceid
= sel
->info
.uses_instanceid
;
6629 bld_base
= &ctx
.radeon_bld
.soa
.bld_base
;
6630 ctx
.radeon_bld
.load_system_value
= declare_system_value
;
6633 case PIPE_SHADER_VERTEX
:
6634 ctx
.radeon_bld
.load_input
= declare_input_vs
;
6635 if (shader
->key
.vs
.as_ls
)
6636 bld_base
->emit_epilogue
= si_llvm_emit_ls_epilogue
;
6637 else if (shader
->key
.vs
.as_es
)
6638 bld_base
->emit_epilogue
= si_llvm_emit_es_epilogue
;
6640 bld_base
->emit_epilogue
= si_llvm_emit_vs_epilogue
;
6642 case PIPE_SHADER_TESS_CTRL
:
6643 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_tcs
;
6644 bld_base
->emit_fetch_funcs
[TGSI_FILE_OUTPUT
] = fetch_output_tcs
;
6645 bld_base
->emit_store
= store_output_tcs
;
6646 bld_base
->emit_epilogue
= si_llvm_emit_tcs_epilogue
;
6648 case PIPE_SHADER_TESS_EVAL
:
6649 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_tes
;
6650 if (shader
->key
.tes
.as_es
)
6651 bld_base
->emit_epilogue
= si_llvm_emit_es_epilogue
;
6653 bld_base
->emit_epilogue
= si_llvm_emit_vs_epilogue
;
6655 case PIPE_SHADER_GEOMETRY
:
6656 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_gs
;
6657 bld_base
->emit_epilogue
= si_llvm_emit_gs_epilogue
;
6659 case PIPE_SHADER_FRAGMENT
:
6660 ctx
.radeon_bld
.load_input
= declare_input_fs
;
6662 bld_base
->emit_epilogue
= si_llvm_emit_fs_epilogue
;
6664 bld_base
->emit_epilogue
= si_llvm_return_fs_outputs
;
6666 case PIPE_SHADER_COMPUTE
:
6667 ctx
.radeon_bld
.declare_memory_region
= declare_compute_memory
;
6670 assert(!"Unsupported shader type");
6674 create_meta_data(&ctx
);
6675 create_function(&ctx
);
6676 preload_constants(&ctx
);
6677 preload_shader_buffers(&ctx
);
6678 preload_samplers(&ctx
);
6679 preload_images(&ctx
);
6680 preload_streamout_buffers(&ctx
);
6681 preload_ring_buffers(&ctx
);
6683 if (ctx
.is_monolithic
&& sel
->type
== PIPE_SHADER_FRAGMENT
&&
6684 shader
->key
.ps
.prolog
.poly_stipple
) {
6685 LLVMValueRef list
= LLVMGetParam(ctx
.radeon_bld
.main_fn
,
6686 SI_PARAM_RW_BUFFERS
);
6687 si_llvm_emit_polygon_stipple(&ctx
, list
,
6688 SI_PARAM_POS_FIXED_PT
);
6691 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
6693 for (i
= 0; i
< 4; i
++) {
6694 ctx
.gs_next_vertex
[i
] =
6695 lp_build_alloca(bld_base
->base
.gallivm
,
6700 if (!lp_build_tgsi_llvm(bld_base
, sel
->tokens
)) {
6701 fprintf(stderr
, "Failed to translate shader from TGSI to LLVM\n");
6705 si_llvm_build_ret(&ctx
, ctx
.return_value
);
6706 mod
= bld_base
->base
.gallivm
->module
;
6708 /* Dump LLVM IR before any optimization passes */
6709 if (sscreen
->b
.debug_flags
& DBG_PREOPT_IR
&&
6710 r600_can_dump_shader(&sscreen
->b
, ctx
.type
))
6711 LLVMDumpModule(mod
);
6713 radeon_llvm_finalize_module(&ctx
.radeon_bld
);
6715 r
= si_compile_llvm(sscreen
, &shader
->binary
, &shader
->config
, tm
,
6716 mod
, debug
, ctx
.type
, "TGSI shader");
6718 fprintf(stderr
, "LLVM failed to compile shader\n");
6722 radeon_llvm_dispose(&ctx
.radeon_bld
);
6724 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6725 * LLVM 3.9svn has this bug.
6727 if (sel
->type
== PIPE_SHADER_COMPUTE
) {
6728 unsigned *props
= sel
->info
.properties
;
6729 unsigned wave_size
= 64;
6730 unsigned max_vgprs
= 256;
6731 unsigned max_sgprs
= sscreen
->b
.chip_class
>= VI
? 800 : 512;
6732 unsigned max_sgprs_per_wave
= 128;
6733 unsigned min_waves_per_cu
=
6734 DIV_ROUND_UP(props
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] *
6735 props
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
] *
6736 props
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
],
6738 unsigned min_waves_per_simd
= DIV_ROUND_UP(min_waves_per_cu
, 4);
6740 max_vgprs
= max_vgprs
/ min_waves_per_simd
;
6741 max_sgprs
= MIN2(max_sgprs
/ min_waves_per_simd
, max_sgprs_per_wave
);
6743 if (shader
->config
.num_sgprs
> max_sgprs
||
6744 shader
->config
.num_vgprs
> max_vgprs
) {
6745 fprintf(stderr
, "LLVM failed to compile a shader correctly: "
6746 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6747 shader
->config
.num_sgprs
, shader
->config
.num_vgprs
,
6748 max_sgprs
, max_vgprs
);
6750 /* Just terminate the process, because dependent
6751 * shaders can hang due to bad input data, but use
6752 * the env var to allow shader-db to work.
6754 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6759 /* Add the scratch offset to input SGPRs. */
6760 if (shader
->config
.scratch_bytes_per_wave
)
6761 shader
->info
.num_input_sgprs
+= 1; /* scratch byte offset */
6763 /* Calculate the number of fragment input VGPRs. */
6764 if (ctx
.type
== PIPE_SHADER_FRAGMENT
) {
6765 shader
->info
.num_input_vgprs
= 0;
6766 shader
->info
.face_vgpr_index
= -1;
6768 if (G_0286CC_PERSP_SAMPLE_ENA(shader
->config
.spi_ps_input_addr
))
6769 shader
->info
.num_input_vgprs
+= 2;
6770 if (G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_addr
))
6771 shader
->info
.num_input_vgprs
+= 2;
6772 if (G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_addr
))
6773 shader
->info
.num_input_vgprs
+= 2;
6774 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader
->config
.spi_ps_input_addr
))
6775 shader
->info
.num_input_vgprs
+= 3;
6776 if (G_0286CC_LINEAR_SAMPLE_ENA(shader
->config
.spi_ps_input_addr
))
6777 shader
->info
.num_input_vgprs
+= 2;
6778 if (G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_addr
))
6779 shader
->info
.num_input_vgprs
+= 2;
6780 if (G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_addr
))
6781 shader
->info
.num_input_vgprs
+= 2;
6782 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader
->config
.spi_ps_input_addr
))
6783 shader
->info
.num_input_vgprs
+= 1;
6784 if (G_0286CC_POS_X_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
6785 shader
->info
.num_input_vgprs
+= 1;
6786 if (G_0286CC_POS_Y_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
6787 shader
->info
.num_input_vgprs
+= 1;
6788 if (G_0286CC_POS_Z_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
6789 shader
->info
.num_input_vgprs
+= 1;
6790 if (G_0286CC_POS_W_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
6791 shader
->info
.num_input_vgprs
+= 1;
6792 if (G_0286CC_FRONT_FACE_ENA(shader
->config
.spi_ps_input_addr
)) {
6793 shader
->info
.face_vgpr_index
= shader
->info
.num_input_vgprs
;
6794 shader
->info
.num_input_vgprs
+= 1;
6796 if (G_0286CC_ANCILLARY_ENA(shader
->config
.spi_ps_input_addr
))
6797 shader
->info
.num_input_vgprs
+= 1;
6798 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader
->config
.spi_ps_input_addr
))
6799 shader
->info
.num_input_vgprs
+= 1;
6800 if (G_0286CC_POS_FIXED_PT_ENA(shader
->config
.spi_ps_input_addr
))
6801 shader
->info
.num_input_vgprs
+= 1;
6804 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
6805 shader
->gs_copy_shader
= CALLOC_STRUCT(si_shader
);
6806 shader
->gs_copy_shader
->selector
= shader
->selector
;
6807 ctx
.shader
= shader
->gs_copy_shader
;
6808 if ((r
= si_generate_gs_copy_shader(sscreen
, &ctx
,
6810 free(shader
->gs_copy_shader
);
6811 shader
->gs_copy_shader
= NULL
;
6817 for (int i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++)
6818 FREE(ctx
.constants
[i
]);
6823 * Create, compile and return a shader part (prolog or epilog).
6825 * \param sscreen screen
6826 * \param list list of shader parts of the same category
6827 * \param key shader part key
6828 * \param tm LLVM target machine
6829 * \param debug debug callback
6830 * \param compile the callback responsible for compilation
6831 * \return non-NULL on success
6833 static struct si_shader_part
*
6834 si_get_shader_part(struct si_screen
*sscreen
,
6835 struct si_shader_part
**list
,
6836 union si_shader_part_key
*key
,
6837 LLVMTargetMachineRef tm
,
6838 struct pipe_debug_callback
*debug
,
6839 bool (*compile
)(struct si_screen
*,
6840 LLVMTargetMachineRef
,
6841 struct pipe_debug_callback
*,
6842 struct si_shader_part
*))
6844 struct si_shader_part
*result
;
6846 pipe_mutex_lock(sscreen
->shader_parts_mutex
);
6848 /* Find existing. */
6849 for (result
= *list
; result
; result
= result
->next
) {
6850 if (memcmp(&result
->key
, key
, sizeof(*key
)) == 0) {
6851 pipe_mutex_unlock(sscreen
->shader_parts_mutex
);
6856 /* Compile a new one. */
6857 result
= CALLOC_STRUCT(si_shader_part
);
6859 if (!compile(sscreen
, tm
, debug
, result
)) {
6861 pipe_mutex_unlock(sscreen
->shader_parts_mutex
);
6865 result
->next
= *list
;
6867 pipe_mutex_unlock(sscreen
->shader_parts_mutex
);
6872 * Create a vertex shader prolog.
6874 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6875 * All inputs are returned unmodified. The vertex load indices are
6876 * stored after them, which will used by the API VS for fetching inputs.
6878 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6883 * (VertexID + BaseVertex),
6884 * (InstanceID + StartInstance),
6885 * (InstanceID / 2 + StartInstance)
6887 static bool si_compile_vs_prolog(struct si_screen
*sscreen
,
6888 LLVMTargetMachineRef tm
,
6889 struct pipe_debug_callback
*debug
,
6890 struct si_shader_part
*out
)
6892 union si_shader_part_key
*key
= &out
->key
;
6893 struct si_shader shader
= {};
6894 struct si_shader_context ctx
;
6895 struct gallivm_state
*gallivm
= &ctx
.radeon_bld
.gallivm
;
6896 LLVMTypeRef
*params
, *returns
;
6897 LLVMValueRef ret
, func
;
6898 int last_sgpr
, num_params
, num_returns
, i
;
6901 si_init_shader_ctx(&ctx
, sscreen
, &shader
, tm
);
6902 ctx
.type
= PIPE_SHADER_VERTEX
;
6903 ctx
.param_vertex_id
= key
->vs_prolog
.num_input_sgprs
;
6904 ctx
.param_instance_id
= key
->vs_prolog
.num_input_sgprs
+ 3;
6906 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6907 params
= alloca((key
->vs_prolog
.num_input_sgprs
+ 4) *
6908 sizeof(LLVMTypeRef
));
6909 returns
= alloca((key
->vs_prolog
.num_input_sgprs
+ 4 +
6910 key
->vs_prolog
.last_input
+ 1) *
6911 sizeof(LLVMTypeRef
));
6915 /* Declare input and output SGPRs. */
6917 for (i
= 0; i
< key
->vs_prolog
.num_input_sgprs
; i
++) {
6918 params
[num_params
++] = ctx
.i32
;
6919 returns
[num_returns
++] = ctx
.i32
;
6921 last_sgpr
= num_params
- 1;
6923 /* 4 preloaded VGPRs (outputs must be floats) */
6924 for (i
= 0; i
< 4; i
++) {
6925 params
[num_params
++] = ctx
.i32
;
6926 returns
[num_returns
++] = ctx
.f32
;
6929 /* Vertex load indices. */
6930 for (i
= 0; i
<= key
->vs_prolog
.last_input
; i
++)
6931 returns
[num_returns
++] = ctx
.f32
;
6933 /* Create the function. */
6934 si_create_function(&ctx
, returns
, num_returns
, params
,
6935 num_params
, last_sgpr
);
6936 func
= ctx
.radeon_bld
.main_fn
;
6938 /* Copy inputs to outputs. This should be no-op, as the registers match,
6939 * but it will prevent the compiler from overwriting them unintentionally.
6941 ret
= ctx
.return_value
;
6942 for (i
= 0; i
< key
->vs_prolog
.num_input_sgprs
; i
++) {
6943 LLVMValueRef p
= LLVMGetParam(func
, i
);
6944 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
, p
, i
, "");
6946 for (i
= num_params
- 4; i
< num_params
; i
++) {
6947 LLVMValueRef p
= LLVMGetParam(func
, i
);
6948 p
= LLVMBuildBitCast(gallivm
->builder
, p
, ctx
.f32
, "");
6949 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
, p
, i
, "");
6952 /* Compute vertex load indices from instance divisors. */
6953 for (i
= 0; i
<= key
->vs_prolog
.last_input
; i
++) {
6954 unsigned divisor
= key
->vs_prolog
.states
.instance_divisors
[i
];
6958 /* InstanceID / Divisor + StartInstance */
6959 index
= get_instance_index_for_fetch(&ctx
.radeon_bld
,
6960 SI_SGPR_START_INSTANCE
,
6963 /* VertexID + BaseVertex */
6964 index
= LLVMBuildAdd(gallivm
->builder
,
6965 LLVMGetParam(func
, ctx
.param_vertex_id
),
6966 LLVMGetParam(func
, SI_SGPR_BASE_VERTEX
), "");
6969 index
= LLVMBuildBitCast(gallivm
->builder
, index
, ctx
.f32
, "");
6970 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
, index
,
6975 si_llvm_build_ret(&ctx
, ret
);
6976 radeon_llvm_finalize_module(&ctx
.radeon_bld
);
6978 if (si_compile_llvm(sscreen
, &out
->binary
, &out
->config
, tm
,
6979 gallivm
->module
, debug
, ctx
.type
,
6980 "Vertex Shader Prolog"))
6983 radeon_llvm_dispose(&ctx
.radeon_bld
);
6988 * Compile the vertex shader epilog. This is also used by the tessellation
6989 * evaluation shader compiled as VS.
6991 * The input is PrimitiveID.
6993 * If PrimitiveID is required by the pixel shader, export it.
6994 * Otherwise, do nothing.
6996 static bool si_compile_vs_epilog(struct si_screen
*sscreen
,
6997 LLVMTargetMachineRef tm
,
6998 struct pipe_debug_callback
*debug
,
6999 struct si_shader_part
*out
)
7001 union si_shader_part_key
*key
= &out
->key
;
7002 struct si_shader_context ctx
;
7003 struct gallivm_state
*gallivm
= &ctx
.radeon_bld
.gallivm
;
7004 struct lp_build_tgsi_context
*bld_base
= &ctx
.radeon_bld
.soa
.bld_base
;
7005 LLVMTypeRef params
[5];
7009 si_init_shader_ctx(&ctx
, sscreen
, NULL
, tm
);
7010 ctx
.type
= PIPE_SHADER_VERTEX
;
7012 /* Declare input VGPRs. */
7013 num_params
= key
->vs_epilog
.states
.export_prim_id
?
7014 (VS_EPILOG_PRIMID_LOC
+ 1) : 0;
7015 assert(num_params
<= ARRAY_SIZE(params
));
7017 for (i
= 0; i
< num_params
; i
++)
7018 params
[i
] = ctx
.f32
;
7020 /* Create the function. */
7021 si_create_function(&ctx
, NULL
, 0, params
, num_params
, -1);
7024 if (key
->vs_epilog
.states
.export_prim_id
) {
7025 struct lp_build_context
*base
= &bld_base
->base
;
7026 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
7027 LLVMValueRef args
[9];
7029 args
[0] = lp_build_const_int32(base
->gallivm
, 0x0); /* enabled channels */
7030 args
[1] = uint
->zero
; /* whether the EXEC mask is valid */
7031 args
[2] = uint
->zero
; /* DONE bit */
7032 args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_PARAM
+
7033 key
->vs_epilog
.prim_id_param_offset
);
7034 args
[4] = uint
->zero
; /* COMPR flag (0 = 32-bit export) */
7035 args
[5] = LLVMGetParam(ctx
.radeon_bld
.main_fn
,
7036 VS_EPILOG_PRIMID_LOC
); /* X */
7037 args
[6] = uint
->undef
; /* Y */
7038 args
[7] = uint
->undef
; /* Z */
7039 args
[8] = uint
->undef
; /* W */
7041 lp_build_intrinsic(base
->gallivm
->builder
, "llvm.SI.export",
7042 LLVMVoidTypeInContext(base
->gallivm
->context
),
7047 LLVMBuildRetVoid(gallivm
->builder
);
7048 radeon_llvm_finalize_module(&ctx
.radeon_bld
);
7050 if (si_compile_llvm(sscreen
, &out
->binary
, &out
->config
, tm
,
7051 gallivm
->module
, debug
, ctx
.type
,
7052 "Vertex Shader Epilog"))
7055 radeon_llvm_dispose(&ctx
.radeon_bld
);
7060 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7062 static bool si_get_vs_epilog(struct si_screen
*sscreen
,
7063 LLVMTargetMachineRef tm
,
7064 struct si_shader
*shader
,
7065 struct pipe_debug_callback
*debug
,
7066 struct si_vs_epilog_bits
*states
)
7068 union si_shader_part_key epilog_key
;
7070 memset(&epilog_key
, 0, sizeof(epilog_key
));
7071 epilog_key
.vs_epilog
.states
= *states
;
7073 /* Set up the PrimitiveID output. */
7074 if (shader
->key
.vs
.epilog
.export_prim_id
) {
7075 unsigned index
= shader
->selector
->info
.num_outputs
;
7076 unsigned offset
= shader
->info
.nr_param_exports
++;
7078 epilog_key
.vs_epilog
.prim_id_param_offset
= offset
;
7079 assert(index
< ARRAY_SIZE(shader
->info
.vs_output_param_offset
));
7080 shader
->info
.vs_output_param_offset
[index
] = offset
;
7083 shader
->epilog
= si_get_shader_part(sscreen
, &sscreen
->vs_epilogs
,
7084 &epilog_key
, tm
, debug
,
7085 si_compile_vs_epilog
);
7086 return shader
->epilog
!= NULL
;
7090 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7092 static bool si_shader_select_vs_parts(struct si_screen
*sscreen
,
7093 LLVMTargetMachineRef tm
,
7094 struct si_shader
*shader
,
7095 struct pipe_debug_callback
*debug
)
7097 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
7098 union si_shader_part_key prolog_key
;
7101 /* Get the prolog. */
7102 memset(&prolog_key
, 0, sizeof(prolog_key
));
7103 prolog_key
.vs_prolog
.states
= shader
->key
.vs
.prolog
;
7104 prolog_key
.vs_prolog
.num_input_sgprs
= shader
->info
.num_input_sgprs
;
7105 prolog_key
.vs_prolog
.last_input
= MAX2(1, info
->num_inputs
) - 1;
7107 /* The prolog is a no-op if there are no inputs. */
7108 if (info
->num_inputs
) {
7110 si_get_shader_part(sscreen
, &sscreen
->vs_prologs
,
7111 &prolog_key
, tm
, debug
,
7112 si_compile_vs_prolog
);
7113 if (!shader
->prolog
)
7117 /* Get the epilog. */
7118 if (!shader
->key
.vs
.as_es
&& !shader
->key
.vs
.as_ls
&&
7119 !si_get_vs_epilog(sscreen
, tm
, shader
, debug
,
7120 &shader
->key
.vs
.epilog
))
7123 /* Set the instanceID flag. */
7124 for (i
= 0; i
< info
->num_inputs
; i
++)
7125 if (prolog_key
.vs_prolog
.states
.instance_divisors
[i
])
7126 shader
->info
.uses_instanceid
= true;
7132 * Select and compile (or reuse) TES parts (epilog).
7134 static bool si_shader_select_tes_parts(struct si_screen
*sscreen
,
7135 LLVMTargetMachineRef tm
,
7136 struct si_shader
*shader
,
7137 struct pipe_debug_callback
*debug
)
7139 if (shader
->key
.tes
.as_es
)
7142 /* TES compiled as VS. */
7143 return si_get_vs_epilog(sscreen
, tm
, shader
, debug
,
7144 &shader
->key
.tes
.epilog
);
7148 * Compile the TCS epilog. This writes tesselation factors to memory based on
7149 * the output primitive type of the tesselator (determined by TES).
7151 static bool si_compile_tcs_epilog(struct si_screen
*sscreen
,
7152 LLVMTargetMachineRef tm
,
7153 struct pipe_debug_callback
*debug
,
7154 struct si_shader_part
*out
)
7156 union si_shader_part_key
*key
= &out
->key
;
7157 struct si_shader shader
= {};
7158 struct si_shader_context ctx
;
7159 struct gallivm_state
*gallivm
= &ctx
.radeon_bld
.gallivm
;
7160 struct lp_build_tgsi_context
*bld_base
= &ctx
.radeon_bld
.soa
.bld_base
;
7161 LLVMTypeRef params
[16];
7163 int last_sgpr
, num_params
;
7166 si_init_shader_ctx(&ctx
, sscreen
, &shader
, tm
);
7167 ctx
.type
= PIPE_SHADER_TESS_CTRL
;
7168 shader
.key
.tcs
.epilog
= key
->tcs_epilog
.states
;
7170 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
7171 params
[SI_PARAM_RW_BUFFERS
] = const_array(ctx
.v16i8
, SI_NUM_RW_BUFFERS
);
7172 params
[SI_PARAM_CONST_BUFFERS
] = ctx
.i64
;
7173 params
[SI_PARAM_SAMPLERS
] = ctx
.i64
;
7174 params
[SI_PARAM_IMAGES
] = ctx
.i64
;
7175 params
[SI_PARAM_SHADER_BUFFERS
] = ctx
.i64
;
7176 params
[SI_PARAM_TCS_OFFCHIP_LAYOUT
] = ctx
.i32
;
7177 params
[SI_PARAM_TCS_OUT_OFFSETS
] = ctx
.i32
;
7178 params
[SI_PARAM_TCS_OUT_LAYOUT
] = ctx
.i32
;
7179 params
[SI_PARAM_TCS_IN_LAYOUT
] = ctx
.i32
;
7180 params
[ctx
.param_oc_lds
= SI_PARAM_TCS_OC_LDS
] = ctx
.i32
;
7181 params
[SI_PARAM_TESS_FACTOR_OFFSET
] = ctx
.i32
;
7182 last_sgpr
= SI_PARAM_TESS_FACTOR_OFFSET
;
7183 num_params
= last_sgpr
+ 1;
7185 params
[num_params
++] = ctx
.i32
; /* patch index within the wave (REL_PATCH_ID) */
7186 params
[num_params
++] = ctx
.i32
; /* invocation ID within the patch */
7187 params
[num_params
++] = ctx
.i32
; /* LDS offset where tess factors should be loaded from */
7189 /* Create the function. */
7190 si_create_function(&ctx
, NULL
, 0, params
, num_params
, last_sgpr
);
7191 declare_tess_lds(&ctx
);
7192 func
= ctx
.radeon_bld
.main_fn
;
7194 si_write_tess_factors(bld_base
,
7195 LLVMGetParam(func
, last_sgpr
+ 1),
7196 LLVMGetParam(func
, last_sgpr
+ 2),
7197 LLVMGetParam(func
, last_sgpr
+ 3));
7200 LLVMBuildRetVoid(gallivm
->builder
);
7201 radeon_llvm_finalize_module(&ctx
.radeon_bld
);
7203 if (si_compile_llvm(sscreen
, &out
->binary
, &out
->config
, tm
,
7204 gallivm
->module
, debug
, ctx
.type
,
7205 "Tessellation Control Shader Epilog"))
7208 radeon_llvm_dispose(&ctx
.radeon_bld
);
7213 * Select and compile (or reuse) TCS parts (epilog).
7215 static bool si_shader_select_tcs_parts(struct si_screen
*sscreen
,
7216 LLVMTargetMachineRef tm
,
7217 struct si_shader
*shader
,
7218 struct pipe_debug_callback
*debug
)
7220 union si_shader_part_key epilog_key
;
7222 /* Get the epilog. */
7223 memset(&epilog_key
, 0, sizeof(epilog_key
));
7224 epilog_key
.tcs_epilog
.states
= shader
->key
.tcs
.epilog
;
7226 shader
->epilog
= si_get_shader_part(sscreen
, &sscreen
->tcs_epilogs
,
7227 &epilog_key
, tm
, debug
,
7228 si_compile_tcs_epilog
);
7229 return shader
->epilog
!= NULL
;
7233 * Compile the pixel shader prolog. This handles:
7234 * - two-side color selection and interpolation
7235 * - overriding interpolation parameters for the API PS
7236 * - polygon stippling
7238 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7239 * overriden by other states. (e.g. per-sample interpolation)
7240 * Interpolated colors are stored after the preloaded VGPRs.
7242 static bool si_compile_ps_prolog(struct si_screen
*sscreen
,
7243 LLVMTargetMachineRef tm
,
7244 struct pipe_debug_callback
*debug
,
7245 struct si_shader_part
*out
)
7247 union si_shader_part_key
*key
= &out
->key
;
7248 struct si_shader shader
= {};
7249 struct si_shader_context ctx
;
7250 struct gallivm_state
*gallivm
= &ctx
.radeon_bld
.gallivm
;
7251 LLVMTypeRef
*params
;
7252 LLVMValueRef ret
, func
;
7253 int last_sgpr
, num_params
, num_returns
, i
, num_color_channels
;
7256 si_init_shader_ctx(&ctx
, sscreen
, &shader
, tm
);
7257 ctx
.type
= PIPE_SHADER_FRAGMENT
;
7258 shader
.key
.ps
.prolog
= key
->ps_prolog
.states
;
7260 /* Number of inputs + 8 color elements. */
7261 params
= alloca((key
->ps_prolog
.num_input_sgprs
+
7262 key
->ps_prolog
.num_input_vgprs
+ 8) *
7263 sizeof(LLVMTypeRef
));
7265 /* Declare inputs. */
7267 for (i
= 0; i
< key
->ps_prolog
.num_input_sgprs
; i
++)
7268 params
[num_params
++] = ctx
.i32
;
7269 last_sgpr
= num_params
- 1;
7271 for (i
= 0; i
< key
->ps_prolog
.num_input_vgprs
; i
++)
7272 params
[num_params
++] = ctx
.f32
;
7274 /* Declare outputs (same as inputs + add colors if needed) */
7275 num_returns
= num_params
;
7276 num_color_channels
= util_bitcount(key
->ps_prolog
.colors_read
);
7277 for (i
= 0; i
< num_color_channels
; i
++)
7278 params
[num_returns
++] = ctx
.f32
;
7280 /* Create the function. */
7281 si_create_function(&ctx
, params
, num_returns
, params
,
7282 num_params
, last_sgpr
);
7283 func
= ctx
.radeon_bld
.main_fn
;
7285 /* Copy inputs to outputs. This should be no-op, as the registers match,
7286 * but it will prevent the compiler from overwriting them unintentionally.
7288 ret
= ctx
.return_value
;
7289 for (i
= 0; i
< num_params
; i
++) {
7290 LLVMValueRef p
= LLVMGetParam(func
, i
);
7291 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
, p
, i
, "");
7294 /* Polygon stippling. */
7295 if (key
->ps_prolog
.states
.poly_stipple
) {
7296 /* POS_FIXED_PT is always last. */
7297 unsigned pos
= key
->ps_prolog
.num_input_sgprs
+
7298 key
->ps_prolog
.num_input_vgprs
- 1;
7299 LLVMValueRef ptr
[2], list
;
7301 /* Get the pointer to rw buffers. */
7302 ptr
[0] = LLVMGetParam(func
, SI_SGPR_RW_BUFFERS
);
7303 ptr
[1] = LLVMGetParam(func
, SI_SGPR_RW_BUFFERS_HI
);
7304 list
= lp_build_gather_values(gallivm
, ptr
, 2);
7305 list
= LLVMBuildBitCast(gallivm
->builder
, list
, ctx
.i64
, "");
7306 list
= LLVMBuildIntToPtr(gallivm
->builder
, list
,
7307 const_array(ctx
.v16i8
, SI_NUM_RW_BUFFERS
), "");
7309 si_llvm_emit_polygon_stipple(&ctx
, list
, pos
);
7312 if (key
->ps_prolog
.states
.bc_optimize_for_persp
||
7313 key
->ps_prolog
.states
.bc_optimize_for_linear
) {
7314 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7315 LLVMValueRef center
[2], centroid
[2], tmp
, bc_optimize
;
7317 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7318 * The hw doesn't compute CENTROID if the whole wave only
7319 * contains fully-covered quads.
7321 * PRIM_MASK is after user SGPRs.
7323 bc_optimize
= LLVMGetParam(func
, SI_PS_NUM_USER_SGPR
);
7324 bc_optimize
= LLVMBuildLShr(gallivm
->builder
, bc_optimize
,
7325 LLVMConstInt(ctx
.i32
, 31, 0), "");
7326 bc_optimize
= LLVMBuildTrunc(gallivm
->builder
, bc_optimize
,
7329 if (key
->ps_prolog
.states
.bc_optimize_for_persp
) {
7330 /* Read PERSP_CENTER. */
7331 for (i
= 0; i
< 2; i
++)
7332 center
[i
] = LLVMGetParam(func
, base
+ 2 + i
);
7333 /* Read PERSP_CENTROID. */
7334 for (i
= 0; i
< 2; i
++)
7335 centroid
[i
] = LLVMGetParam(func
, base
+ 4 + i
);
7336 /* Select PERSP_CENTROID. */
7337 for (i
= 0; i
< 2; i
++) {
7338 tmp
= LLVMBuildSelect(gallivm
->builder
, bc_optimize
,
7339 center
[i
], centroid
[i
], "");
7340 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7341 tmp
, base
+ 4 + i
, "");
7344 if (key
->ps_prolog
.states
.bc_optimize_for_linear
) {
7345 /* Read LINEAR_CENTER. */
7346 for (i
= 0; i
< 2; i
++)
7347 center
[i
] = LLVMGetParam(func
, base
+ 8 + i
);
7348 /* Read LINEAR_CENTROID. */
7349 for (i
= 0; i
< 2; i
++)
7350 centroid
[i
] = LLVMGetParam(func
, base
+ 10 + i
);
7351 /* Select LINEAR_CENTROID. */
7352 for (i
= 0; i
< 2; i
++) {
7353 tmp
= LLVMBuildSelect(gallivm
->builder
, bc_optimize
,
7354 center
[i
], centroid
[i
], "");
7355 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7356 tmp
, base
+ 10 + i
, "");
7361 /* Interpolate colors. */
7362 for (i
= 0; i
< 2; i
++) {
7363 unsigned writemask
= (key
->ps_prolog
.colors_read
>> (i
* 4)) & 0xf;
7364 unsigned face_vgpr
= key
->ps_prolog
.num_input_sgprs
+
7365 key
->ps_prolog
.face_vgpr_index
;
7366 LLVMValueRef interp
[2], color
[4];
7367 LLVMValueRef interp_ij
= NULL
, prim_mask
= NULL
, face
= NULL
;
7372 /* If the interpolation qualifier is not CONSTANT (-1). */
7373 if (key
->ps_prolog
.color_interp_vgpr_index
[i
] != -1) {
7374 unsigned interp_vgpr
= key
->ps_prolog
.num_input_sgprs
+
7375 key
->ps_prolog
.color_interp_vgpr_index
[i
];
7377 /* Get the (i,j) updated by bc_optimize handling. */
7378 interp
[0] = LLVMBuildExtractValue(gallivm
->builder
, ret
,
7380 interp
[1] = LLVMBuildExtractValue(gallivm
->builder
, ret
,
7381 interp_vgpr
+ 1, "");
7382 interp_ij
= lp_build_gather_values(gallivm
, interp
, 2);
7383 interp_ij
= LLVMBuildBitCast(gallivm
->builder
, interp_ij
,
7387 /* Use the absolute location of the input. */
7388 prim_mask
= LLVMGetParam(func
, SI_PS_NUM_USER_SGPR
);
7390 if (key
->ps_prolog
.states
.color_two_side
) {
7391 face
= LLVMGetParam(func
, face_vgpr
);
7392 face
= LLVMBuildBitCast(gallivm
->builder
, face
, ctx
.i32
, "");
7395 interp_fs_input(&ctx
,
7396 key
->ps_prolog
.color_attr_index
[i
],
7397 TGSI_SEMANTIC_COLOR
, i
,
7398 key
->ps_prolog
.num_interp_inputs
,
7399 key
->ps_prolog
.colors_read
, interp_ij
,
7400 prim_mask
, face
, color
);
7403 unsigned chan
= u_bit_scan(&writemask
);
7404 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
, color
[chan
],
7409 /* Force per-sample interpolation. */
7410 if (key
->ps_prolog
.states
.force_persp_sample_interp
) {
7411 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7412 LLVMValueRef persp_sample
[2];
7414 /* Read PERSP_SAMPLE. */
7415 for (i
= 0; i
< 2; i
++)
7416 persp_sample
[i
] = LLVMGetParam(func
, base
+ i
);
7417 /* Overwrite PERSP_CENTER. */
7418 for (i
= 0; i
< 2; i
++)
7419 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7420 persp_sample
[i
], base
+ 2 + i
, "");
7421 /* Overwrite PERSP_CENTROID. */
7422 for (i
= 0; i
< 2; i
++)
7423 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7424 persp_sample
[i
], base
+ 4 + i
, "");
7426 if (key
->ps_prolog
.states
.force_linear_sample_interp
) {
7427 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7428 LLVMValueRef linear_sample
[2];
7430 /* Read LINEAR_SAMPLE. */
7431 for (i
= 0; i
< 2; i
++)
7432 linear_sample
[i
] = LLVMGetParam(func
, base
+ 6 + i
);
7433 /* Overwrite LINEAR_CENTER. */
7434 for (i
= 0; i
< 2; i
++)
7435 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7436 linear_sample
[i
], base
+ 8 + i
, "");
7437 /* Overwrite LINEAR_CENTROID. */
7438 for (i
= 0; i
< 2; i
++)
7439 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7440 linear_sample
[i
], base
+ 10 + i
, "");
7443 /* Force center interpolation. */
7444 if (key
->ps_prolog
.states
.force_persp_center_interp
) {
7445 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7446 LLVMValueRef persp_center
[2];
7448 /* Read PERSP_CENTER. */
7449 for (i
= 0; i
< 2; i
++)
7450 persp_center
[i
] = LLVMGetParam(func
, base
+ 2 + i
);
7451 /* Overwrite PERSP_SAMPLE. */
7452 for (i
= 0; i
< 2; i
++)
7453 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7454 persp_center
[i
], base
+ i
, "");
7455 /* Overwrite PERSP_CENTROID. */
7456 for (i
= 0; i
< 2; i
++)
7457 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7458 persp_center
[i
], base
+ 4 + i
, "");
7460 if (key
->ps_prolog
.states
.force_linear_center_interp
) {
7461 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7462 LLVMValueRef linear_center
[2];
7464 /* Read LINEAR_CENTER. */
7465 for (i
= 0; i
< 2; i
++)
7466 linear_center
[i
] = LLVMGetParam(func
, base
+ 8 + i
);
7467 /* Overwrite LINEAR_SAMPLE. */
7468 for (i
= 0; i
< 2; i
++)
7469 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7470 linear_center
[i
], base
+ 6 + i
, "");
7471 /* Overwrite LINEAR_CENTROID. */
7472 for (i
= 0; i
< 2; i
++)
7473 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7474 linear_center
[i
], base
+ 10 + i
, "");
7477 /* Tell LLVM to insert WQM instruction sequence when needed. */
7478 if (key
->ps_prolog
.wqm
) {
7479 LLVMAddTargetDependentFunctionAttr(func
,
7480 "amdgpu-ps-wqm-outputs", "");
7484 si_llvm_build_ret(&ctx
, ret
);
7485 radeon_llvm_finalize_module(&ctx
.radeon_bld
);
7487 if (si_compile_llvm(sscreen
, &out
->binary
, &out
->config
, tm
,
7488 gallivm
->module
, debug
, ctx
.type
,
7489 "Fragment Shader Prolog"))
7492 radeon_llvm_dispose(&ctx
.radeon_bld
);
7497 * Compile the pixel shader epilog. This handles everything that must be
7498 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7500 static bool si_compile_ps_epilog(struct si_screen
*sscreen
,
7501 LLVMTargetMachineRef tm
,
7502 struct pipe_debug_callback
*debug
,
7503 struct si_shader_part
*out
)
7505 union si_shader_part_key
*key
= &out
->key
;
7506 struct si_shader shader
= {};
7507 struct si_shader_context ctx
;
7508 struct gallivm_state
*gallivm
= &ctx
.radeon_bld
.gallivm
;
7509 struct lp_build_tgsi_context
*bld_base
= &ctx
.radeon_bld
.soa
.bld_base
;
7510 LLVMTypeRef params
[16+8*4+3];
7511 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
7512 int last_sgpr
, num_params
, i
;
7514 struct si_ps_exports exp
= {};
7516 si_init_shader_ctx(&ctx
, sscreen
, &shader
, tm
);
7517 ctx
.type
= PIPE_SHADER_FRAGMENT
;
7518 shader
.key
.ps
.epilog
= key
->ps_epilog
.states
;
7520 /* Declare input SGPRs. */
7521 params
[SI_PARAM_RW_BUFFERS
] = ctx
.i64
;
7522 params
[SI_PARAM_CONST_BUFFERS
] = ctx
.i64
;
7523 params
[SI_PARAM_SAMPLERS
] = ctx
.i64
;
7524 params
[SI_PARAM_IMAGES
] = ctx
.i64
;
7525 params
[SI_PARAM_SHADER_BUFFERS
] = ctx
.i64
;
7526 params
[SI_PARAM_ALPHA_REF
] = ctx
.f32
;
7527 last_sgpr
= SI_PARAM_ALPHA_REF
;
7529 /* Declare input VGPRs. */
7530 num_params
= (last_sgpr
+ 1) +
7531 util_bitcount(key
->ps_epilog
.colors_written
) * 4 +
7532 key
->ps_epilog
.writes_z
+
7533 key
->ps_epilog
.writes_stencil
+
7534 key
->ps_epilog
.writes_samplemask
;
7536 num_params
= MAX2(num_params
,
7537 last_sgpr
+ 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC
+ 1);
7539 assert(num_params
<= ARRAY_SIZE(params
));
7541 for (i
= last_sgpr
+ 1; i
< num_params
; i
++)
7542 params
[i
] = ctx
.f32
;
7544 /* Create the function. */
7545 si_create_function(&ctx
, NULL
, 0, params
, num_params
, last_sgpr
);
7546 /* Disable elimination of unused inputs. */
7547 radeon_llvm_add_attribute(ctx
.radeon_bld
.main_fn
,
7548 "InitialPSInputAddr", 0xffffff);
7550 /* Process colors. */
7551 unsigned vgpr
= last_sgpr
+ 1;
7552 unsigned colors_written
= key
->ps_epilog
.colors_written
;
7553 int last_color_export
= -1;
7555 /* Find the last color export. */
7556 if (!key
->ps_epilog
.writes_z
&&
7557 !key
->ps_epilog
.writes_stencil
&&
7558 !key
->ps_epilog
.writes_samplemask
) {
7559 unsigned spi_format
= key
->ps_epilog
.states
.spi_shader_col_format
;
7561 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7562 if (colors_written
== 0x1 && key
->ps_epilog
.states
.last_cbuf
> 0) {
7563 /* Just set this if any of the colorbuffers are enabled. */
7565 ((1llu << (4 * (key
->ps_epilog
.states
.last_cbuf
+ 1))) - 1))
7566 last_color_export
= 0;
7568 for (i
= 0; i
< 8; i
++)
7569 if (colors_written
& (1 << i
) &&
7570 (spi_format
>> (i
* 4)) & 0xf)
7571 last_color_export
= i
;
7575 while (colors_written
) {
7576 LLVMValueRef color
[4];
7577 int mrt
= u_bit_scan(&colors_written
);
7579 for (i
= 0; i
< 4; i
++)
7580 color
[i
] = LLVMGetParam(ctx
.radeon_bld
.main_fn
, vgpr
++);
7582 si_export_mrt_color(bld_base
, color
, mrt
,
7584 mrt
== last_color_export
, &exp
);
7587 /* Process depth, stencil, samplemask. */
7588 if (key
->ps_epilog
.writes_z
)
7589 depth
= LLVMGetParam(ctx
.radeon_bld
.main_fn
, vgpr
++);
7590 if (key
->ps_epilog
.writes_stencil
)
7591 stencil
= LLVMGetParam(ctx
.radeon_bld
.main_fn
, vgpr
++);
7592 if (key
->ps_epilog
.writes_samplemask
)
7593 samplemask
= LLVMGetParam(ctx
.radeon_bld
.main_fn
, vgpr
++);
7595 if (depth
|| stencil
|| samplemask
)
7596 si_export_mrt_z(bld_base
, depth
, stencil
, samplemask
, &exp
);
7597 else if (last_color_export
== -1)
7598 si_export_null(bld_base
);
7601 si_emit_ps_exports(&ctx
, &exp
);
7604 LLVMBuildRetVoid(gallivm
->builder
);
7605 radeon_llvm_finalize_module(&ctx
.radeon_bld
);
7607 if (si_compile_llvm(sscreen
, &out
->binary
, &out
->config
, tm
,
7608 gallivm
->module
, debug
, ctx
.type
,
7609 "Fragment Shader Epilog"))
7612 radeon_llvm_dispose(&ctx
.radeon_bld
);
7617 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7619 static bool si_shader_select_ps_parts(struct si_screen
*sscreen
,
7620 LLVMTargetMachineRef tm
,
7621 struct si_shader
*shader
,
7622 struct pipe_debug_callback
*debug
)
7624 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
7625 union si_shader_part_key prolog_key
;
7626 union si_shader_part_key epilog_key
;
7629 /* Get the prolog. */
7630 memset(&prolog_key
, 0, sizeof(prolog_key
));
7631 prolog_key
.ps_prolog
.states
= shader
->key
.ps
.prolog
;
7632 prolog_key
.ps_prolog
.colors_read
= info
->colors_read
;
7633 prolog_key
.ps_prolog
.num_input_sgprs
= shader
->info
.num_input_sgprs
;
7634 prolog_key
.ps_prolog
.num_input_vgprs
= shader
->info
.num_input_vgprs
;
7635 prolog_key
.ps_prolog
.wqm
= info
->uses_derivatives
&&
7636 (prolog_key
.ps_prolog
.colors_read
||
7637 prolog_key
.ps_prolog
.states
.force_persp_sample_interp
||
7638 prolog_key
.ps_prolog
.states
.force_linear_sample_interp
||
7639 prolog_key
.ps_prolog
.states
.force_persp_center_interp
||
7640 prolog_key
.ps_prolog
.states
.force_linear_center_interp
||
7641 prolog_key
.ps_prolog
.states
.bc_optimize_for_persp
||
7642 prolog_key
.ps_prolog
.states
.bc_optimize_for_linear
);
7644 if (info
->colors_read
) {
7645 unsigned *color
= shader
->selector
->color_attr_index
;
7647 if (shader
->key
.ps
.prolog
.color_two_side
) {
7648 /* BCOLORs are stored after the last input. */
7649 prolog_key
.ps_prolog
.num_interp_inputs
= info
->num_inputs
;
7650 prolog_key
.ps_prolog
.face_vgpr_index
= shader
->info
.face_vgpr_index
;
7651 shader
->config
.spi_ps_input_ena
|= S_0286CC_FRONT_FACE_ENA(1);
7654 for (i
= 0; i
< 2; i
++) {
7655 unsigned interp
= info
->input_interpolate
[color
[i
]];
7656 unsigned location
= info
->input_interpolate_loc
[color
[i
]];
7658 if (!(info
->colors_read
& (0xf << i
*4)))
7661 prolog_key
.ps_prolog
.color_attr_index
[i
] = color
[i
];
7663 if (shader
->key
.ps
.prolog
.flatshade_colors
&&
7664 interp
== TGSI_INTERPOLATE_COLOR
)
7665 interp
= TGSI_INTERPOLATE_CONSTANT
;
7668 case TGSI_INTERPOLATE_CONSTANT
:
7669 prolog_key
.ps_prolog
.color_interp_vgpr_index
[i
] = -1;
7671 case TGSI_INTERPOLATE_PERSPECTIVE
:
7672 case TGSI_INTERPOLATE_COLOR
:
7673 /* Force the interpolation location for colors here. */
7674 if (shader
->key
.ps
.prolog
.force_persp_sample_interp
)
7675 location
= TGSI_INTERPOLATE_LOC_SAMPLE
;
7676 if (shader
->key
.ps
.prolog
.force_persp_center_interp
)
7677 location
= TGSI_INTERPOLATE_LOC_CENTER
;
7680 case TGSI_INTERPOLATE_LOC_SAMPLE
:
7681 prolog_key
.ps_prolog
.color_interp_vgpr_index
[i
] = 0;
7682 shader
->config
.spi_ps_input_ena
|=
7683 S_0286CC_PERSP_SAMPLE_ENA(1);
7685 case TGSI_INTERPOLATE_LOC_CENTER
:
7686 prolog_key
.ps_prolog
.color_interp_vgpr_index
[i
] = 2;
7687 shader
->config
.spi_ps_input_ena
|=
7688 S_0286CC_PERSP_CENTER_ENA(1);
7690 case TGSI_INTERPOLATE_LOC_CENTROID
:
7691 prolog_key
.ps_prolog
.color_interp_vgpr_index
[i
] = 4;
7692 shader
->config
.spi_ps_input_ena
|=
7693 S_0286CC_PERSP_CENTROID_ENA(1);
7699 case TGSI_INTERPOLATE_LINEAR
:
7700 /* Force the interpolation location for colors here. */
7701 if (shader
->key
.ps
.prolog
.force_linear_sample_interp
)
7702 location
= TGSI_INTERPOLATE_LOC_SAMPLE
;
7703 if (shader
->key
.ps
.prolog
.force_linear_center_interp
)
7704 location
= TGSI_INTERPOLATE_LOC_CENTER
;
7707 case TGSI_INTERPOLATE_LOC_SAMPLE
:
7708 prolog_key
.ps_prolog
.color_interp_vgpr_index
[i
] = 6;
7709 shader
->config
.spi_ps_input_ena
|=
7710 S_0286CC_LINEAR_SAMPLE_ENA(1);
7712 case TGSI_INTERPOLATE_LOC_CENTER
:
7713 prolog_key
.ps_prolog
.color_interp_vgpr_index
[i
] = 8;
7714 shader
->config
.spi_ps_input_ena
|=
7715 S_0286CC_LINEAR_CENTER_ENA(1);
7717 case TGSI_INTERPOLATE_LOC_CENTROID
:
7718 prolog_key
.ps_prolog
.color_interp_vgpr_index
[i
] = 10;
7719 shader
->config
.spi_ps_input_ena
|=
7720 S_0286CC_LINEAR_CENTROID_ENA(1);
7732 /* The prolog is a no-op if these aren't set. */
7733 if (prolog_key
.ps_prolog
.colors_read
||
7734 prolog_key
.ps_prolog
.states
.force_persp_sample_interp
||
7735 prolog_key
.ps_prolog
.states
.force_linear_sample_interp
||
7736 prolog_key
.ps_prolog
.states
.force_persp_center_interp
||
7737 prolog_key
.ps_prolog
.states
.force_linear_center_interp
||
7738 prolog_key
.ps_prolog
.states
.bc_optimize_for_persp
||
7739 prolog_key
.ps_prolog
.states
.bc_optimize_for_linear
||
7740 prolog_key
.ps_prolog
.states
.poly_stipple
) {
7742 si_get_shader_part(sscreen
, &sscreen
->ps_prologs
,
7743 &prolog_key
, tm
, debug
,
7744 si_compile_ps_prolog
);
7745 if (!shader
->prolog
)
7749 /* Get the epilog. */
7750 memset(&epilog_key
, 0, sizeof(epilog_key
));
7751 epilog_key
.ps_epilog
.colors_written
= info
->colors_written
;
7752 epilog_key
.ps_epilog
.writes_z
= info
->writes_z
;
7753 epilog_key
.ps_epilog
.writes_stencil
= info
->writes_stencil
;
7754 epilog_key
.ps_epilog
.writes_samplemask
= info
->writes_samplemask
;
7755 epilog_key
.ps_epilog
.states
= shader
->key
.ps
.epilog
;
7758 si_get_shader_part(sscreen
, &sscreen
->ps_epilogs
,
7759 &epilog_key
, tm
, debug
,
7760 si_compile_ps_epilog
);
7761 if (!shader
->epilog
)
7764 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7765 if (shader
->key
.ps
.prolog
.poly_stipple
) {
7766 shader
->config
.spi_ps_input_ena
|= S_0286CC_POS_FIXED_PT_ENA(1);
7767 assert(G_0286CC_POS_FIXED_PT_ENA(shader
->config
.spi_ps_input_addr
));
7770 /* Set up the enable bits for per-sample shading if needed. */
7771 if (shader
->key
.ps
.prolog
.force_persp_sample_interp
&&
7772 (G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_ena
) ||
7773 G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7774 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTER_ENA
;
7775 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTROID_ENA
;
7776 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_SAMPLE_ENA(1);
7778 if (shader
->key
.ps
.prolog
.force_linear_sample_interp
&&
7779 (G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_ena
) ||
7780 G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7781 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTER_ENA
;
7782 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTROID_ENA
;
7783 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_SAMPLE_ENA(1);
7785 if (shader
->key
.ps
.prolog
.force_persp_center_interp
&&
7786 (G_0286CC_PERSP_SAMPLE_ENA(shader
->config
.spi_ps_input_ena
) ||
7787 G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7788 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_SAMPLE_ENA
;
7789 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTROID_ENA
;
7790 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_CENTER_ENA(1);
7792 if (shader
->key
.ps
.prolog
.force_linear_center_interp
&&
7793 (G_0286CC_LINEAR_SAMPLE_ENA(shader
->config
.spi_ps_input_ena
) ||
7794 G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7795 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_SAMPLE_ENA
;
7796 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTROID_ENA
;
7797 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_CENTER_ENA(1);
7800 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7801 if (G_0286CC_POS_W_FLOAT_ENA(shader
->config
.spi_ps_input_ena
) &&
7802 !(shader
->config
.spi_ps_input_ena
& 0xf)) {
7803 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_CENTER_ENA(1);
7804 assert(G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_addr
));
7807 /* At least one pair of interpolation weights must be enabled. */
7808 if (!(shader
->config
.spi_ps_input_ena
& 0x7f)) {
7809 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_CENTER_ENA(1);
7810 assert(G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_addr
));
7813 /* The sample mask input is always enabled, because the API shader always
7814 * passes it through to the epilog. Disable it here if it's unused.
7816 if (!shader
->key
.ps
.epilog
.poly_line_smoothing
&&
7817 !shader
->selector
->info
.reads_samplemask
)
7818 shader
->config
.spi_ps_input_ena
&= C_0286CC_SAMPLE_COVERAGE_ENA
;
7823 static void si_fix_num_sgprs(struct si_shader
*shader
)
7825 unsigned min_sgprs
= shader
->info
.num_input_sgprs
+ 2; /* VCC */
7827 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
, min_sgprs
);
7830 int si_shader_create(struct si_screen
*sscreen
, LLVMTargetMachineRef tm
,
7831 struct si_shader
*shader
,
7832 struct pipe_debug_callback
*debug
)
7834 struct si_shader
*mainp
= shader
->selector
->main_shader_part
;
7837 /* LS, ES, VS are compiled on demand if the main part hasn't been
7838 * compiled for that stage.
7841 (shader
->selector
->type
== PIPE_SHADER_VERTEX
&&
7842 (shader
->key
.vs
.as_es
!= mainp
->key
.vs
.as_es
||
7843 shader
->key
.vs
.as_ls
!= mainp
->key
.vs
.as_ls
)) ||
7844 (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
&&
7845 shader
->key
.tes
.as_es
!= mainp
->key
.tes
.as_es
) ||
7846 (shader
->selector
->type
== PIPE_SHADER_TESS_CTRL
&&
7847 shader
->key
.tcs
.epilog
.inputs_to_copy
) ||
7848 shader
->selector
->type
== PIPE_SHADER_COMPUTE
) {
7849 /* Monolithic shader (compiled as a whole, has many variants,
7850 * may take a long time to compile).
7852 r
= si_compile_tgsi_shader(sscreen
, tm
, shader
, true, debug
);
7856 /* The shader consists of 2-3 parts:
7858 * - the middle part is the user shader, it has 1 variant only
7859 * and it was compiled during the creation of the shader
7861 * - the prolog part is inserted at the beginning
7862 * - the epilog part is inserted at the end
7864 * The prolog and epilog have many (but simple) variants.
7867 /* Copy the compiled TGSI shader data over. */
7868 shader
->is_binary_shared
= true;
7869 shader
->binary
= mainp
->binary
;
7870 shader
->config
= mainp
->config
;
7871 shader
->info
.num_input_sgprs
= mainp
->info
.num_input_sgprs
;
7872 shader
->info
.num_input_vgprs
= mainp
->info
.num_input_vgprs
;
7873 shader
->info
.face_vgpr_index
= mainp
->info
.face_vgpr_index
;
7874 memcpy(shader
->info
.vs_output_param_offset
,
7875 mainp
->info
.vs_output_param_offset
,
7876 sizeof(mainp
->info
.vs_output_param_offset
));
7877 shader
->info
.uses_instanceid
= mainp
->info
.uses_instanceid
;
7878 shader
->info
.nr_pos_exports
= mainp
->info
.nr_pos_exports
;
7879 shader
->info
.nr_param_exports
= mainp
->info
.nr_param_exports
;
7881 /* Select prologs and/or epilogs. */
7882 switch (shader
->selector
->type
) {
7883 case PIPE_SHADER_VERTEX
:
7884 if (!si_shader_select_vs_parts(sscreen
, tm
, shader
, debug
))
7887 case PIPE_SHADER_TESS_CTRL
:
7888 if (!si_shader_select_tcs_parts(sscreen
, tm
, shader
, debug
))
7891 case PIPE_SHADER_TESS_EVAL
:
7892 if (!si_shader_select_tes_parts(sscreen
, tm
, shader
, debug
))
7895 case PIPE_SHADER_FRAGMENT
:
7896 if (!si_shader_select_ps_parts(sscreen
, tm
, shader
, debug
))
7899 /* Make sure we have at least as many VGPRs as there
7900 * are allocated inputs.
7902 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
7903 shader
->info
.num_input_vgprs
);
7907 /* Update SGPR and VGPR counts. */
7908 if (shader
->prolog
) {
7909 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
7910 shader
->prolog
->config
.num_sgprs
);
7911 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
7912 shader
->prolog
->config
.num_vgprs
);
7914 if (shader
->epilog
) {
7915 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
7916 shader
->epilog
->config
.num_sgprs
);
7917 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
7918 shader
->epilog
->config
.num_vgprs
);
7922 si_fix_num_sgprs(shader
);
7923 si_shader_dump(sscreen
, shader
, debug
, shader
->selector
->info
.processor
,
7927 r
= si_shader_binary_upload(sscreen
, shader
);
7929 fprintf(stderr
, "LLVM failed to upload shader\n");
7936 void si_shader_destroy(struct si_shader
*shader
)
7938 if (shader
->gs_copy_shader
) {
7939 si_shader_destroy(shader
->gs_copy_shader
);
7940 FREE(shader
->gs_copy_shader
);
7943 if (shader
->scratch_bo
)
7944 r600_resource_reference(&shader
->scratch_bo
, NULL
);
7946 r600_resource_reference(&shader
->bo
, NULL
);
7948 if (!shader
->is_binary_shared
)
7949 radeon_shader_binary_clean(&shader
->binary
);
7951 free(shader
->shader_log
);