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[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "radeon/radeon_elf_util.h"
37 #include "util/u_memory.h"
38 #include "util/u_string.h"
39 #include "tgsi/tgsi_build.h"
40 #include "tgsi/tgsi_util.h"
41 #include "tgsi/tgsi_dump.h"
42
43 #include "ac_llvm_util.h"
44 #include "si_shader_internal.h"
45 #include "si_pipe.h"
46 #include "sid.h"
47
48
49 static const char *scratch_rsrc_dword0_symbol =
50 "SCRATCH_RSRC_DWORD0";
51
52 static const char *scratch_rsrc_dword1_symbol =
53 "SCRATCH_RSRC_DWORD1";
54
55 struct si_shader_output_values
56 {
57 LLVMValueRef values[4];
58 unsigned name;
59 unsigned sid;
60 };
61
62 static void si_init_shader_ctx(struct si_shader_context *ctx,
63 struct si_screen *sscreen,
64 struct si_shader *shader,
65 LLVMTargetMachineRef tm);
66
67 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
68 struct lp_build_tgsi_context *bld_base,
69 struct lp_build_emit_data *emit_data);
70
71 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
72 FILE *f);
73
74 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
75 union si_shader_part_key *key);
76 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
77 union si_shader_part_key *key);
78 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
79 union si_shader_part_key *key);
80 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
81 union si_shader_part_key *key);
82 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
83 union si_shader_part_key *key);
84
85 /* Ideally pass the sample mask input to the PS epilog as v13, which
86 * is its usual location, so that the shader doesn't have to add v_mov.
87 */
88 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
89
90 /* The VS location of the PrimitiveID input is the same in the epilog,
91 * so that the main shader part doesn't have to move it.
92 */
93 #define VS_EPILOG_PRIMID_LOC 2
94
95 enum {
96 CONST_ADDR_SPACE = 2,
97 LOCAL_ADDR_SPACE = 3,
98 };
99
100 #define SENDMSG_GS 2
101 #define SENDMSG_GS_DONE 3
102
103 #define SENDMSG_GS_OP_NOP (0 << 4)
104 #define SENDMSG_GS_OP_CUT (1 << 4)
105 #define SENDMSG_GS_OP_EMIT (2 << 4)
106 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
107
108 /**
109 * Returns a unique index for a semantic name and index. The index must be
110 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
111 * calculated.
112 */
113 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
114 {
115 switch (semantic_name) {
116 case TGSI_SEMANTIC_POSITION:
117 return 0;
118 case TGSI_SEMANTIC_PSIZE:
119 return 1;
120 case TGSI_SEMANTIC_CLIPDIST:
121 assert(index <= 1);
122 return 2 + index;
123 case TGSI_SEMANTIC_GENERIC:
124 if (index <= 63-4)
125 return 4 + index;
126
127 assert(!"invalid generic index");
128 return 0;
129
130 /* patch indices are completely separate and thus start from 0 */
131 case TGSI_SEMANTIC_TESSOUTER:
132 return 0;
133 case TGSI_SEMANTIC_TESSINNER:
134 return 1;
135 case TGSI_SEMANTIC_PATCH:
136 return 2 + index;
137
138 default:
139 assert(!"invalid semantic name");
140 return 0;
141 }
142 }
143
144 unsigned si_shader_io_get_unique_index2(unsigned name, unsigned index)
145 {
146 switch (name) {
147 case TGSI_SEMANTIC_FOG:
148 return 0;
149 case TGSI_SEMANTIC_LAYER:
150 return 1;
151 case TGSI_SEMANTIC_VIEWPORT_INDEX:
152 return 2;
153 case TGSI_SEMANTIC_PRIMID:
154 return 3;
155 case TGSI_SEMANTIC_COLOR: /* these alias */
156 case TGSI_SEMANTIC_BCOLOR:
157 return 4 + index;
158 case TGSI_SEMANTIC_TEXCOORD:
159 return 6 + index;
160 default:
161 assert(!"invalid semantic name");
162 return 0;
163 }
164 }
165
166 /**
167 * Get the value of a shader input parameter and extract a bitfield.
168 */
169 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
170 unsigned param, unsigned rshift,
171 unsigned bitwidth)
172 {
173 struct gallivm_state *gallivm = &ctx->gallivm;
174 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
175 param);
176
177 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
178 value = bitcast(&ctx->soa.bld_base,
179 TGSI_TYPE_UNSIGNED, value);
180
181 if (rshift)
182 value = LLVMBuildLShr(gallivm->builder, value,
183 lp_build_const_int32(gallivm, rshift), "");
184
185 if (rshift + bitwidth < 32) {
186 unsigned mask = (1 << bitwidth) - 1;
187 value = LLVMBuildAnd(gallivm->builder, value,
188 lp_build_const_int32(gallivm, mask), "");
189 }
190
191 return value;
192 }
193
194 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
195 {
196 switch (ctx->type) {
197 case PIPE_SHADER_TESS_CTRL:
198 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
199
200 case PIPE_SHADER_TESS_EVAL:
201 return LLVMGetParam(ctx->main_fn,
202 ctx->param_tes_rel_patch_id);
203
204 default:
205 assert(0);
206 return NULL;
207 }
208 }
209
210 /* Tessellation shaders pass outputs to the next shader using LDS.
211 *
212 * LS outputs = TCS inputs
213 * TCS outputs = TES inputs
214 *
215 * The LDS layout is:
216 * - TCS inputs for patch 0
217 * - TCS inputs for patch 1
218 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
219 * - ...
220 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
221 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
222 * - TCS outputs for patch 1
223 * - Per-patch TCS outputs for patch 1
224 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
225 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
226 * - ...
227 *
228 * All three shaders VS(LS), TCS, TES share the same LDS space.
229 */
230
231 static LLVMValueRef
232 get_tcs_in_patch_stride(struct si_shader_context *ctx)
233 {
234 if (ctx->type == PIPE_SHADER_VERTEX)
235 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
236 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
237 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
238 else {
239 assert(0);
240 return NULL;
241 }
242 }
243
244 static LLVMValueRef
245 get_tcs_out_patch_stride(struct si_shader_context *ctx)
246 {
247 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
248 }
249
250 static LLVMValueRef
251 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
252 {
253 return lp_build_mul_imm(&ctx->soa.bld_base.uint_bld,
254 unpack_param(ctx,
255 SI_PARAM_TCS_OUT_OFFSETS,
256 0, 16),
257 4);
258 }
259
260 static LLVMValueRef
261 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
262 {
263 return lp_build_mul_imm(&ctx->soa.bld_base.uint_bld,
264 unpack_param(ctx,
265 SI_PARAM_TCS_OUT_OFFSETS,
266 16, 16),
267 4);
268 }
269
270 static LLVMValueRef
271 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
272 {
273 struct gallivm_state *gallivm = &ctx->gallivm;
274 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
275 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
276
277 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
278 }
279
280 static LLVMValueRef
281 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
282 {
283 struct gallivm_state *gallivm = &ctx->gallivm;
284 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
285 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
286 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
287
288 return LLVMBuildAdd(gallivm->builder, patch0_offset,
289 LLVMBuildMul(gallivm->builder, patch_stride,
290 rel_patch_id, ""),
291 "");
292 }
293
294 static LLVMValueRef
295 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
296 {
297 struct gallivm_state *gallivm = &ctx->gallivm;
298 LLVMValueRef patch0_patch_data_offset =
299 get_tcs_out_patch0_patch_data_offset(ctx);
300 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
301 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
302
303 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
304 LLVMBuildMul(gallivm->builder, patch_stride,
305 rel_patch_id, ""),
306 "");
307 }
308
309 static LLVMValueRef build_gep0(struct si_shader_context *ctx,
310 LLVMValueRef base_ptr, LLVMValueRef index)
311 {
312 LLVMValueRef indices[2] = {
313 LLVMConstInt(ctx->i32, 0, 0),
314 index,
315 };
316 return LLVMBuildGEP(ctx->gallivm.builder, base_ptr,
317 indices, 2, "");
318 }
319
320 static void build_indexed_store(struct si_shader_context *ctx,
321 LLVMValueRef base_ptr, LLVMValueRef index,
322 LLVMValueRef value)
323 {
324 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
325 struct gallivm_state *gallivm = bld_base->base.gallivm;
326
327 LLVMBuildStore(gallivm->builder, value,
328 build_gep0(ctx, base_ptr, index));
329 }
330
331 /**
332 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
333 * It's equivalent to doing a load from &base_ptr[index].
334 *
335 * \param base_ptr Where the array starts.
336 * \param index The element index into the array.
337 * \param uniform Whether the base_ptr and index can be assumed to be
338 * dynamically uniform
339 */
340 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
341 LLVMValueRef base_ptr, LLVMValueRef index,
342 bool uniform)
343 {
344 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
345 struct gallivm_state *gallivm = bld_base->base.gallivm;
346 LLVMValueRef pointer;
347
348 pointer = build_gep0(ctx, base_ptr, index);
349 if (uniform)
350 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
351 return LLVMBuildLoad(gallivm->builder, pointer, "");
352 }
353
354 /**
355 * Do a load from &base_ptr[index], but also add a flag that it's loading
356 * a constant from a dynamically uniform index.
357 */
358 static LLVMValueRef build_indexed_load_const(
359 struct si_shader_context *ctx,
360 LLVMValueRef base_ptr, LLVMValueRef index)
361 {
362 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
363 LLVMSetMetadata(result, ctx->invariant_load_md_kind, ctx->empty_md);
364 return result;
365 }
366
367 static LLVMValueRef get_instance_index_for_fetch(
368 struct si_shader_context *radeon_bld,
369 unsigned param_start_instance, unsigned divisor)
370 {
371 struct si_shader_context *ctx =
372 si_shader_context(&radeon_bld->soa.bld_base);
373 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
374
375 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
376 ctx->param_instance_id);
377
378 /* The division must be done before START_INSTANCE is added. */
379 if (divisor > 1)
380 result = LLVMBuildUDiv(gallivm->builder, result,
381 lp_build_const_int32(gallivm, divisor), "");
382
383 return LLVMBuildAdd(gallivm->builder, result,
384 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
385 }
386
387 static void declare_input_vs(
388 struct si_shader_context *ctx,
389 unsigned input_index,
390 const struct tgsi_full_declaration *decl,
391 LLVMValueRef out[4])
392 {
393 struct lp_build_context *base = &ctx->soa.bld_base.base;
394 struct gallivm_state *gallivm = base->gallivm;
395
396 unsigned chan;
397 unsigned fix_fetch;
398
399 LLVMValueRef t_list_ptr;
400 LLVMValueRef t_offset;
401 LLVMValueRef t_list;
402 LLVMValueRef attribute_offset;
403 LLVMValueRef buffer_index;
404 LLVMValueRef args[3];
405 LLVMValueRef input;
406
407 /* Load the T list */
408 t_list_ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_VERTEX_BUFFERS);
409
410 t_offset = lp_build_const_int32(gallivm, input_index);
411
412 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
413
414 /* Build the attribute offset */
415 attribute_offset = lp_build_const_int32(gallivm, 0);
416
417 buffer_index = LLVMGetParam(ctx->main_fn,
418 ctx->param_vertex_index0 +
419 input_index);
420
421 args[0] = t_list;
422 args[1] = attribute_offset;
423 args[2] = buffer_index;
424 input = lp_build_intrinsic(gallivm->builder,
425 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
426 LP_FUNC_ATTR_READNONE);
427
428 /* Break up the vec4 into individual components */
429 for (chan = 0; chan < 4; chan++) {
430 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
431 out[chan] = LLVMBuildExtractElement(gallivm->builder,
432 input, llvm_chan, "");
433 }
434
435 fix_fetch = (ctx->shader->key.mono.vs.fix_fetch >> (2 * input_index)) & 3;
436 if (fix_fetch) {
437 /* The hardware returns an unsigned value; convert it to a
438 * signed one.
439 */
440 LLVMValueRef tmp = out[3];
441 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
442
443 /* First, recover the sign-extended signed integer value. */
444 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
445 tmp = LLVMBuildFPToUI(gallivm->builder, tmp, ctx->i32, "");
446 else
447 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->i32, "");
448
449 /* For the integer-like cases, do a natural sign extension.
450 *
451 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
452 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
453 * exponent.
454 */
455 tmp = LLVMBuildShl(gallivm->builder, tmp,
456 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
457 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
458 tmp = LLVMBuildAShr(gallivm->builder, tmp, c30, "");
459
460 /* Convert back to the right type. */
461 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
462 LLVMValueRef clamp;
463 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
464 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
465 clamp = LLVMBuildFCmp(gallivm->builder, LLVMRealULT, tmp, neg_one, "");
466 tmp = LLVMBuildSelect(gallivm->builder, clamp, neg_one, tmp, "");
467 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
468 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
469 }
470
471 out[3] = tmp;
472 }
473 }
474
475 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
476 unsigned swizzle)
477 {
478 struct si_shader_context *ctx = si_shader_context(bld_base);
479
480 if (swizzle > 0)
481 return bld_base->uint_bld.zero;
482
483 switch (ctx->type) {
484 case PIPE_SHADER_VERTEX:
485 return LLVMGetParam(ctx->main_fn,
486 ctx->param_vs_prim_id);
487 case PIPE_SHADER_TESS_CTRL:
488 return LLVMGetParam(ctx->main_fn,
489 SI_PARAM_PATCH_ID);
490 case PIPE_SHADER_TESS_EVAL:
491 return LLVMGetParam(ctx->main_fn,
492 ctx->param_tes_patch_id);
493 case PIPE_SHADER_GEOMETRY:
494 return LLVMGetParam(ctx->main_fn,
495 SI_PARAM_PRIMITIVE_ID);
496 default:
497 assert(0);
498 return bld_base->uint_bld.zero;
499 }
500 }
501
502 /**
503 * Return the value of tgsi_ind_register for indexing.
504 * This is the indirect index with the constant offset added to it.
505 */
506 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
507 const struct tgsi_ind_register *ind,
508 int rel_index)
509 {
510 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
511 LLVMValueRef result;
512
513 result = ctx->soa.addr[ind->Index][ind->Swizzle];
514 result = LLVMBuildLoad(gallivm->builder, result, "");
515 result = LLVMBuildAdd(gallivm->builder, result,
516 lp_build_const_int32(gallivm, rel_index), "");
517 return result;
518 }
519
520 /**
521 * Like get_indirect_index, but restricts the return value to a (possibly
522 * undefined) value inside [0..num).
523 */
524 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
525 const struct tgsi_ind_register *ind,
526 int rel_index, unsigned num)
527 {
528 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
529
530 /* LLVM 3.8: If indirect resource indexing is used:
531 * - SI & CIK hang
532 * - VI crashes
533 */
534 if (HAVE_LLVM <= 0x0308)
535 return LLVMGetUndef(ctx->i32);
536
537 return si_llvm_bound_index(ctx, result, num);
538 }
539
540
541 /**
542 * Calculate a dword address given an input or output register and a stride.
543 */
544 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
545 const struct tgsi_full_dst_register *dst,
546 const struct tgsi_full_src_register *src,
547 LLVMValueRef vertex_dw_stride,
548 LLVMValueRef base_addr)
549 {
550 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
551 struct tgsi_shader_info *info = &ctx->shader->selector->info;
552 ubyte *name, *index, *array_first;
553 int first, param;
554 struct tgsi_full_dst_register reg;
555
556 /* Set the register description. The address computation is the same
557 * for sources and destinations. */
558 if (src) {
559 reg.Register.File = src->Register.File;
560 reg.Register.Index = src->Register.Index;
561 reg.Register.Indirect = src->Register.Indirect;
562 reg.Register.Dimension = src->Register.Dimension;
563 reg.Indirect = src->Indirect;
564 reg.Dimension = src->Dimension;
565 reg.DimIndirect = src->DimIndirect;
566 } else
567 reg = *dst;
568
569 /* If the register is 2-dimensional (e.g. an array of vertices
570 * in a primitive), calculate the base address of the vertex. */
571 if (reg.Register.Dimension) {
572 LLVMValueRef index;
573
574 if (reg.Dimension.Indirect)
575 index = get_indirect_index(ctx, &reg.DimIndirect,
576 reg.Dimension.Index);
577 else
578 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
579
580 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
581 LLVMBuildMul(gallivm->builder, index,
582 vertex_dw_stride, ""), "");
583 }
584
585 /* Get information about the register. */
586 if (reg.Register.File == TGSI_FILE_INPUT) {
587 name = info->input_semantic_name;
588 index = info->input_semantic_index;
589 array_first = info->input_array_first;
590 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
591 name = info->output_semantic_name;
592 index = info->output_semantic_index;
593 array_first = info->output_array_first;
594 } else {
595 assert(0);
596 return NULL;
597 }
598
599 if (reg.Register.Indirect) {
600 /* Add the relative address of the element. */
601 LLVMValueRef ind_index;
602
603 if (reg.Indirect.ArrayID)
604 first = array_first[reg.Indirect.ArrayID];
605 else
606 first = reg.Register.Index;
607
608 ind_index = get_indirect_index(ctx, &reg.Indirect,
609 reg.Register.Index - first);
610
611 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
612 LLVMBuildMul(gallivm->builder, ind_index,
613 lp_build_const_int32(gallivm, 4), ""), "");
614
615 param = si_shader_io_get_unique_index(name[first], index[first]);
616 } else {
617 param = si_shader_io_get_unique_index(name[reg.Register.Index],
618 index[reg.Register.Index]);
619 }
620
621 /* Add the base address of the element. */
622 return LLVMBuildAdd(gallivm->builder, base_addr,
623 lp_build_const_int32(gallivm, param * 4), "");
624 }
625
626 /* The offchip buffer layout for TCS->TES is
627 *
628 * - attribute 0 of patch 0 vertex 0
629 * - attribute 0 of patch 0 vertex 1
630 * - attribute 0 of patch 0 vertex 2
631 * ...
632 * - attribute 0 of patch 1 vertex 0
633 * - attribute 0 of patch 1 vertex 1
634 * ...
635 * - attribute 1 of patch 0 vertex 0
636 * - attribute 1 of patch 0 vertex 1
637 * ...
638 * - per patch attribute 0 of patch 0
639 * - per patch attribute 0 of patch 1
640 * ...
641 *
642 * Note that every attribute has 4 components.
643 */
644 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
645 LLVMValueRef vertex_index,
646 LLVMValueRef param_index)
647 {
648 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
649 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
650 LLVMValueRef param_stride, constant16;
651
652 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
653 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
654 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
655 num_patches, "");
656
657 constant16 = lp_build_const_int32(gallivm, 16);
658 if (vertex_index) {
659 base_addr = LLVMBuildMul(gallivm->builder, get_rel_patch_id(ctx),
660 vertices_per_patch, "");
661
662 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
663 vertex_index, "");
664
665 param_stride = total_vertices;
666 } else {
667 base_addr = get_rel_patch_id(ctx);
668 param_stride = num_patches;
669 }
670
671 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
672 LLVMBuildMul(gallivm->builder, param_index,
673 param_stride, ""), "");
674
675 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
676
677 if (!vertex_index) {
678 LLVMValueRef patch_data_offset =
679 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
680
681 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
682 patch_data_offset, "");
683 }
684 return base_addr;
685 }
686
687 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
688 struct si_shader_context *ctx,
689 const struct tgsi_full_dst_register *dst,
690 const struct tgsi_full_src_register *src)
691 {
692 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
693 struct tgsi_shader_info *info = &ctx->shader->selector->info;
694 ubyte *name, *index, *array_first;
695 struct tgsi_full_src_register reg;
696 LLVMValueRef vertex_index = NULL;
697 LLVMValueRef param_index = NULL;
698 unsigned param_index_base, param_base;
699
700 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
701
702 if (reg.Register.Dimension) {
703
704 if (reg.Dimension.Indirect)
705 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
706 reg.Dimension.Index);
707 else
708 vertex_index = lp_build_const_int32(gallivm,
709 reg.Dimension.Index);
710 }
711
712 /* Get information about the register. */
713 if (reg.Register.File == TGSI_FILE_INPUT) {
714 name = info->input_semantic_name;
715 index = info->input_semantic_index;
716 array_first = info->input_array_first;
717 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
718 name = info->output_semantic_name;
719 index = info->output_semantic_index;
720 array_first = info->output_array_first;
721 } else {
722 assert(0);
723 return NULL;
724 }
725
726 if (reg.Register.Indirect) {
727 if (reg.Indirect.ArrayID)
728 param_base = array_first[reg.Indirect.ArrayID];
729 else
730 param_base = reg.Register.Index;
731
732 param_index = get_indirect_index(ctx, &reg.Indirect,
733 reg.Register.Index - param_base);
734
735 } else {
736 param_base = reg.Register.Index;
737 param_index = lp_build_const_int32(gallivm, 0);
738 }
739
740 param_index_base = si_shader_io_get_unique_index(name[param_base],
741 index[param_base]);
742
743 param_index = LLVMBuildAdd(gallivm->builder, param_index,
744 lp_build_const_int32(gallivm, param_index_base),
745 "");
746
747 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
748 }
749
750 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
751 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
752 * or v4i32 (num_channels=3,4). */
753 static void build_tbuffer_store(struct si_shader_context *ctx,
754 LLVMValueRef rsrc,
755 LLVMValueRef vdata,
756 unsigned num_channels,
757 LLVMValueRef vaddr,
758 LLVMValueRef soffset,
759 unsigned inst_offset,
760 unsigned dfmt,
761 unsigned nfmt,
762 unsigned offen,
763 unsigned idxen,
764 unsigned glc,
765 unsigned slc,
766 unsigned tfe)
767 {
768 struct gallivm_state *gallivm = &ctx->gallivm;
769 LLVMValueRef args[] = {
770 rsrc,
771 vdata,
772 LLVMConstInt(ctx->i32, num_channels, 0),
773 vaddr,
774 soffset,
775 LLVMConstInt(ctx->i32, inst_offset, 0),
776 LLVMConstInt(ctx->i32, dfmt, 0),
777 LLVMConstInt(ctx->i32, nfmt, 0),
778 LLVMConstInt(ctx->i32, offen, 0),
779 LLVMConstInt(ctx->i32, idxen, 0),
780 LLVMConstInt(ctx->i32, glc, 0),
781 LLVMConstInt(ctx->i32, slc, 0),
782 LLVMConstInt(ctx->i32, tfe, 0)
783 };
784
785 /* The instruction offset field has 12 bits */
786 assert(offen || inst_offset < (1 << 12));
787
788 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
789 unsigned func = CLAMP(num_channels, 1, 3) - 1;
790 const char *types[] = {"i32", "v2i32", "v4i32"};
791 char name[256];
792 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
793
794 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
795 args, ARRAY_SIZE(args), 0);
796 }
797
798 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
799 LLVMValueRef rsrc,
800 LLVMValueRef vdata,
801 unsigned num_channels,
802 LLVMValueRef vaddr,
803 LLVMValueRef soffset,
804 unsigned inst_offset)
805 {
806 static unsigned dfmt[] = {
807 V_008F0C_BUF_DATA_FORMAT_32,
808 V_008F0C_BUF_DATA_FORMAT_32_32,
809 V_008F0C_BUF_DATA_FORMAT_32_32_32,
810 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
811 };
812 assert(num_channels >= 1 && num_channels <= 4);
813
814 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
815 inst_offset, dfmt[num_channels-1],
816 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
817 }
818
819 static LLVMValueRef build_buffer_load(struct si_shader_context *ctx,
820 LLVMValueRef rsrc,
821 int num_channels,
822 LLVMValueRef vindex,
823 LLVMValueRef voffset,
824 LLVMValueRef soffset,
825 unsigned inst_offset,
826 unsigned glc,
827 unsigned slc)
828 {
829 struct gallivm_state *gallivm = &ctx->gallivm;
830 unsigned func = CLAMP(num_channels, 1, 3) - 1;
831
832 if (HAVE_LLVM >= 0x309) {
833 LLVMValueRef args[] = {
834 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, ""),
835 vindex ? vindex : LLVMConstInt(ctx->i32, 0, 0),
836 LLVMConstInt(ctx->i32, inst_offset, 0),
837 LLVMConstInt(ctx->i1, glc, 0),
838 LLVMConstInt(ctx->i1, slc, 0)
839 };
840
841 LLVMTypeRef types[] = {ctx->f32, LLVMVectorType(ctx->f32, 2),
842 ctx->v4f32};
843 const char *type_names[] = {"f32", "v2f32", "v4f32"};
844 char name[256];
845
846 if (voffset) {
847 args[2] = LLVMBuildAdd(gallivm->builder, args[2], voffset,
848 "");
849 }
850
851 if (soffset) {
852 args[2] = LLVMBuildAdd(gallivm->builder, args[2], soffset,
853 "");
854 }
855
856 snprintf(name, sizeof(name), "llvm.amdgcn.buffer.load.%s",
857 type_names[func]);
858
859 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
860 ARRAY_SIZE(args), LP_FUNC_ATTR_READONLY);
861 } else {
862 LLVMValueRef args[] = {
863 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v16i8, ""),
864 voffset ? voffset : vindex,
865 soffset,
866 LLVMConstInt(ctx->i32, inst_offset, 0),
867 LLVMConstInt(ctx->i32, voffset ? 1 : 0, 0), // offen
868 LLVMConstInt(ctx->i32, vindex ? 1 : 0, 0), //idxen
869 LLVMConstInt(ctx->i32, glc, 0),
870 LLVMConstInt(ctx->i32, slc, 0),
871 LLVMConstInt(ctx->i32, 0, 0), // TFE
872 };
873
874 LLVMTypeRef types[] = {ctx->i32, LLVMVectorType(ctx->i32, 2),
875 ctx->v4i32};
876 const char *type_names[] = {"i32", "v2i32", "v4i32"};
877 const char *arg_type = "i32";
878 char name[256];
879
880 if (voffset && vindex) {
881 LLVMValueRef vaddr[] = {vindex, voffset};
882
883 arg_type = "v2i32";
884 args[1] = lp_build_gather_values(gallivm, vaddr, 2);
885 }
886
887 snprintf(name, sizeof(name), "llvm.SI.buffer.load.dword.%s.%s",
888 type_names[func], arg_type);
889
890 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
891 ARRAY_SIZE(args), LP_FUNC_ATTR_READONLY);
892 }
893 }
894
895 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
896 enum tgsi_opcode_type type, unsigned swizzle,
897 LLVMValueRef buffer, LLVMValueRef offset,
898 LLVMValueRef base)
899 {
900 struct si_shader_context *ctx = si_shader_context(bld_base);
901 struct gallivm_state *gallivm = bld_base->base.gallivm;
902 LLVMValueRef value, value2;
903 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
904 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
905
906 if (swizzle == ~0) {
907 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
908 0, 1, 0);
909
910 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
911 }
912
913 if (!tgsi_type_is_64bit(type)) {
914 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
915 0, 1, 0);
916
917 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
918 return LLVMBuildExtractElement(gallivm->builder, value,
919 lp_build_const_int32(gallivm, swizzle), "");
920 }
921
922 value = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
923 swizzle * 4, 1, 0);
924
925 value2 = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
926 swizzle * 4 + 4, 1, 0);
927
928 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
929 }
930
931 /**
932 * Load from LDS.
933 *
934 * \param type output value type
935 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
936 * \param dw_addr address in dwords
937 */
938 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
939 enum tgsi_opcode_type type, unsigned swizzle,
940 LLVMValueRef dw_addr)
941 {
942 struct si_shader_context *ctx = si_shader_context(bld_base);
943 struct gallivm_state *gallivm = bld_base->base.gallivm;
944 LLVMValueRef value;
945
946 if (swizzle == ~0) {
947 LLVMValueRef values[TGSI_NUM_CHANNELS];
948
949 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
950 values[chan] = lds_load(bld_base, type, chan, dw_addr);
951
952 return lp_build_gather_values(bld_base->base.gallivm, values,
953 TGSI_NUM_CHANNELS);
954 }
955
956 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
957 lp_build_const_int32(gallivm, swizzle));
958
959 value = build_indexed_load(ctx, ctx->lds, dw_addr, false);
960 if (tgsi_type_is_64bit(type)) {
961 LLVMValueRef value2;
962 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
963 lp_build_const_int32(gallivm, 1));
964 value2 = build_indexed_load(ctx, ctx->lds, dw_addr, false);
965 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
966 }
967
968 return LLVMBuildBitCast(gallivm->builder, value,
969 tgsi2llvmtype(bld_base, type), "");
970 }
971
972 /**
973 * Store to LDS.
974 *
975 * \param swizzle offset (typically 0..3)
976 * \param dw_addr address in dwords
977 * \param value value to store
978 */
979 static void lds_store(struct lp_build_tgsi_context *bld_base,
980 unsigned swizzle, LLVMValueRef dw_addr,
981 LLVMValueRef value)
982 {
983 struct si_shader_context *ctx = si_shader_context(bld_base);
984 struct gallivm_state *gallivm = bld_base->base.gallivm;
985
986 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
987 lp_build_const_int32(gallivm, swizzle));
988
989 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
990 build_indexed_store(ctx, ctx->lds,
991 dw_addr, value);
992 }
993
994 static LLVMValueRef fetch_input_tcs(
995 struct lp_build_tgsi_context *bld_base,
996 const struct tgsi_full_src_register *reg,
997 enum tgsi_opcode_type type, unsigned swizzle)
998 {
999 struct si_shader_context *ctx = si_shader_context(bld_base);
1000 LLVMValueRef dw_addr, stride;
1001
1002 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
1003 dw_addr = get_tcs_in_current_patch_offset(ctx);
1004 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1005
1006 return lds_load(bld_base, type, swizzle, dw_addr);
1007 }
1008
1009 static LLVMValueRef fetch_output_tcs(
1010 struct lp_build_tgsi_context *bld_base,
1011 const struct tgsi_full_src_register *reg,
1012 enum tgsi_opcode_type type, unsigned swizzle)
1013 {
1014 struct si_shader_context *ctx = si_shader_context(bld_base);
1015 LLVMValueRef dw_addr, stride;
1016
1017 if (reg->Register.Dimension) {
1018 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1019 dw_addr = get_tcs_out_current_patch_offset(ctx);
1020 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1021 } else {
1022 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1023 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1024 }
1025
1026 return lds_load(bld_base, type, swizzle, dw_addr);
1027 }
1028
1029 static LLVMValueRef fetch_input_tes(
1030 struct lp_build_tgsi_context *bld_base,
1031 const struct tgsi_full_src_register *reg,
1032 enum tgsi_opcode_type type, unsigned swizzle)
1033 {
1034 struct si_shader_context *ctx = si_shader_context(bld_base);
1035 struct gallivm_state *gallivm = bld_base->base.gallivm;
1036 LLVMValueRef rw_buffers, buffer, base, addr;
1037
1038 rw_buffers = LLVMGetParam(ctx->main_fn,
1039 SI_PARAM_RW_BUFFERS);
1040 buffer = build_indexed_load_const(ctx, rw_buffers,
1041 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1042
1043 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1044 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1045
1046 return buffer_load(bld_base, type, swizzle, buffer, base, addr);
1047 }
1048
1049 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1050 const struct tgsi_full_instruction *inst,
1051 const struct tgsi_opcode_info *info,
1052 LLVMValueRef dst[4])
1053 {
1054 struct si_shader_context *ctx = si_shader_context(bld_base);
1055 struct gallivm_state *gallivm = bld_base->base.gallivm;
1056 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
1057 unsigned chan_index;
1058 LLVMValueRef dw_addr, stride;
1059 LLVMValueRef rw_buffers, buffer, base, buf_addr;
1060 LLVMValueRef values[4];
1061
1062 /* Only handle per-patch and per-vertex outputs here.
1063 * Vectors will be lowered to scalars and this function will be called again.
1064 */
1065 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1066 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1067 si_llvm_emit_store(bld_base, inst, info, dst);
1068 return;
1069 }
1070
1071 if (reg->Register.Dimension) {
1072 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1073 dw_addr = get_tcs_out_current_patch_offset(ctx);
1074 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1075 } else {
1076 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1077 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1078 }
1079
1080 rw_buffers = LLVMGetParam(ctx->main_fn,
1081 SI_PARAM_RW_BUFFERS);
1082 buffer = build_indexed_load_const(ctx, rw_buffers,
1083 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1084
1085 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1086 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1087
1088
1089 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1090 LLVMValueRef value = dst[chan_index];
1091
1092 if (inst->Instruction.Saturate)
1093 value = si_llvm_saturate(bld_base, value);
1094
1095 lds_store(bld_base, chan_index, dw_addr, value);
1096
1097 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1098 values[chan_index] = value;
1099
1100 if (inst->Dst[0].Register.WriteMask != 0xF) {
1101 build_tbuffer_store_dwords(ctx, buffer, value, 1,
1102 buf_addr, base,
1103 4 * chan_index);
1104 }
1105 }
1106
1107 if (inst->Dst[0].Register.WriteMask == 0xF) {
1108 LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
1109 values, 4);
1110 build_tbuffer_store_dwords(ctx, buffer, value, 4, buf_addr,
1111 base, 0);
1112 }
1113 }
1114
1115 static LLVMValueRef fetch_input_gs(
1116 struct lp_build_tgsi_context *bld_base,
1117 const struct tgsi_full_src_register *reg,
1118 enum tgsi_opcode_type type,
1119 unsigned swizzle)
1120 {
1121 struct lp_build_context *base = &bld_base->base;
1122 struct si_shader_context *ctx = si_shader_context(bld_base);
1123 struct si_shader *shader = ctx->shader;
1124 struct lp_build_context *uint = &ctx->soa.bld_base.uint_bld;
1125 struct gallivm_state *gallivm = base->gallivm;
1126 LLVMValueRef vtx_offset;
1127 LLVMValueRef args[9];
1128 unsigned vtx_offset_param;
1129 struct tgsi_shader_info *info = &shader->selector->info;
1130 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1131 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1132 unsigned param;
1133 LLVMValueRef value;
1134
1135 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1136 return get_primitive_id(bld_base, swizzle);
1137
1138 if (!reg->Register.Dimension)
1139 return NULL;
1140
1141 if (swizzle == ~0) {
1142 LLVMValueRef values[TGSI_NUM_CHANNELS];
1143 unsigned chan;
1144 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1145 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1146 }
1147 return lp_build_gather_values(bld_base->base.gallivm, values,
1148 TGSI_NUM_CHANNELS);
1149 }
1150
1151 /* Get the vertex offset parameter */
1152 vtx_offset_param = reg->Dimension.Index;
1153 if (vtx_offset_param < 2) {
1154 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1155 } else {
1156 assert(vtx_offset_param < 6);
1157 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1158 }
1159 vtx_offset = lp_build_mul_imm(uint,
1160 LLVMGetParam(ctx->main_fn,
1161 vtx_offset_param),
1162 4);
1163
1164 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1165 args[0] = ctx->esgs_ring;
1166 args[1] = vtx_offset;
1167 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
1168 args[3] = uint->zero;
1169 args[4] = uint->one; /* OFFEN */
1170 args[5] = uint->zero; /* IDXEN */
1171 args[6] = uint->one; /* GLC */
1172 args[7] = uint->zero; /* SLC */
1173 args[8] = uint->zero; /* TFE */
1174
1175 value = lp_build_intrinsic(gallivm->builder,
1176 "llvm.SI.buffer.load.dword.i32.i32",
1177 ctx->i32, args, 9,
1178 LP_FUNC_ATTR_READONLY);
1179 if (tgsi_type_is_64bit(type)) {
1180 LLVMValueRef value2;
1181 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
1182 value2 = lp_build_intrinsic(gallivm->builder,
1183 "llvm.SI.buffer.load.dword.i32.i32",
1184 ctx->i32, args, 9,
1185 LP_FUNC_ATTR_READONLY);
1186 return si_llvm_emit_fetch_64bit(bld_base, type,
1187 value, value2);
1188 }
1189 return LLVMBuildBitCast(gallivm->builder,
1190 value,
1191 tgsi2llvmtype(bld_base, type), "");
1192 }
1193
1194 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1195 {
1196 switch (interpolate) {
1197 case TGSI_INTERPOLATE_CONSTANT:
1198 return 0;
1199
1200 case TGSI_INTERPOLATE_LINEAR:
1201 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1202 return SI_PARAM_LINEAR_SAMPLE;
1203 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1204 return SI_PARAM_LINEAR_CENTROID;
1205 else
1206 return SI_PARAM_LINEAR_CENTER;
1207 break;
1208 case TGSI_INTERPOLATE_COLOR:
1209 case TGSI_INTERPOLATE_PERSPECTIVE:
1210 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1211 return SI_PARAM_PERSP_SAMPLE;
1212 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1213 return SI_PARAM_PERSP_CENTROID;
1214 else
1215 return SI_PARAM_PERSP_CENTER;
1216 break;
1217 default:
1218 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1219 return -1;
1220 }
1221 }
1222
1223 /**
1224 * Interpolate a fragment shader input.
1225 *
1226 * @param ctx context
1227 * @param input_index index of the input in hardware
1228 * @param semantic_name TGSI_SEMANTIC_*
1229 * @param semantic_index semantic index
1230 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1231 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1232 * @param interp_param interpolation weights (i,j)
1233 * @param prim_mask SI_PARAM_PRIM_MASK
1234 * @param face SI_PARAM_FRONT_FACE
1235 * @param result the return value (4 components)
1236 */
1237 static void interp_fs_input(struct si_shader_context *ctx,
1238 unsigned input_index,
1239 unsigned semantic_name,
1240 unsigned semantic_index,
1241 unsigned num_interp_inputs,
1242 unsigned colors_read_mask,
1243 LLVMValueRef interp_param,
1244 LLVMValueRef prim_mask,
1245 LLVMValueRef face,
1246 LLVMValueRef result[4])
1247 {
1248 struct lp_build_context *base = &ctx->soa.bld_base.base;
1249 struct lp_build_context *uint = &ctx->soa.bld_base.uint_bld;
1250 struct gallivm_state *gallivm = base->gallivm;
1251 const char *intr_name;
1252 LLVMValueRef attr_number;
1253
1254 unsigned chan;
1255
1256 attr_number = lp_build_const_int32(gallivm, input_index);
1257
1258 /* fs.constant returns the param from the middle vertex, so it's not
1259 * really useful for flat shading. It's meant to be used for custom
1260 * interpolation (but the intrinsic can't fetch from the other two
1261 * vertices).
1262 *
1263 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1264 * to do the right thing. The only reason we use fs.constant is that
1265 * fs.interp cannot be used on integers, because they can be equal
1266 * to NaN.
1267 */
1268 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
1269
1270 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1271 ctx->shader->key.part.ps.prolog.color_two_side) {
1272 LLVMValueRef args[4];
1273 LLVMValueRef is_face_positive;
1274 LLVMValueRef back_attr_number;
1275
1276 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1277 * otherwise it's at offset "num_inputs".
1278 */
1279 unsigned back_attr_offset = num_interp_inputs;
1280 if (semantic_index == 1 && colors_read_mask & 0xf)
1281 back_attr_offset += 1;
1282
1283 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1284
1285 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1286 face, uint->zero, "");
1287
1288 args[2] = prim_mask;
1289 args[3] = interp_param;
1290 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1291 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1292 LLVMValueRef front, back;
1293
1294 args[0] = llvm_chan;
1295 args[1] = attr_number;
1296 front = lp_build_intrinsic(gallivm->builder, intr_name,
1297 ctx->f32, args, args[3] ? 4 : 3,
1298 LP_FUNC_ATTR_READNONE);
1299
1300 args[1] = back_attr_number;
1301 back = lp_build_intrinsic(gallivm->builder, intr_name,
1302 ctx->f32, args, args[3] ? 4 : 3,
1303 LP_FUNC_ATTR_READNONE);
1304
1305 result[chan] = LLVMBuildSelect(gallivm->builder,
1306 is_face_positive,
1307 front,
1308 back,
1309 "");
1310 }
1311 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1312 LLVMValueRef args[4];
1313
1314 args[0] = uint->zero;
1315 args[1] = attr_number;
1316 args[2] = prim_mask;
1317 args[3] = interp_param;
1318 result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
1319 ctx->f32, args, args[3] ? 4 : 3,
1320 LP_FUNC_ATTR_READNONE);
1321 result[1] =
1322 result[2] = lp_build_const_float(gallivm, 0.0f);
1323 result[3] = lp_build_const_float(gallivm, 1.0f);
1324 } else {
1325 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1326 LLVMValueRef args[4];
1327 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1328
1329 args[0] = llvm_chan;
1330 args[1] = attr_number;
1331 args[2] = prim_mask;
1332 args[3] = interp_param;
1333 result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
1334 ctx->f32, args, args[3] ? 4 : 3,
1335 LP_FUNC_ATTR_READNONE);
1336 }
1337 }
1338 }
1339
1340 static void declare_input_fs(
1341 struct si_shader_context *radeon_bld,
1342 unsigned input_index,
1343 const struct tgsi_full_declaration *decl,
1344 LLVMValueRef out[4])
1345 {
1346 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
1347 struct si_shader_context *ctx =
1348 si_shader_context(&radeon_bld->soa.bld_base);
1349 struct si_shader *shader = ctx->shader;
1350 LLVMValueRef main_fn = radeon_bld->main_fn;
1351 LLVMValueRef interp_param = NULL;
1352 int interp_param_idx;
1353
1354 /* Get colors from input VGPRs (set by the prolog). */
1355 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1356 unsigned i = decl->Semantic.Index;
1357 unsigned colors_read = shader->selector->info.colors_read;
1358 unsigned mask = colors_read >> (i * 4);
1359 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1360 (i ? util_bitcount(colors_read & 0xf) : 0);
1361
1362 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1363 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1364 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1365 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1366 return;
1367 }
1368
1369 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1370 decl->Interp.Location);
1371 if (interp_param_idx == -1)
1372 return;
1373 else if (interp_param_idx) {
1374 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1375 }
1376
1377 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
1378 decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR &&
1379 ctx->shader->key.part.ps.prolog.flatshade_colors)
1380 interp_param = NULL; /* load the constant color */
1381
1382 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1383 decl->Semantic.Index, shader->selector->info.num_inputs,
1384 shader->selector->info.colors_read, interp_param,
1385 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1386 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1387 &out[0]);
1388 }
1389
1390 static LLVMValueRef get_sample_id(struct si_shader_context *radeon_bld)
1391 {
1392 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1393 SI_PARAM_ANCILLARY, 8, 4);
1394 }
1395
1396 /**
1397 * Set range metadata on an instruction. This can only be used on load and
1398 * call instructions. If you know an instruction can only produce the values
1399 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1400 * \p lo is the minimum value inclusive.
1401 * \p hi is the maximum value exclusive.
1402 */
1403 static void set_range_metadata(struct si_shader_context *ctx,
1404 LLVMValueRef value, unsigned lo, unsigned hi)
1405 {
1406 LLVMValueRef range_md, md_args[2];
1407 LLVMTypeRef type = LLVMTypeOf(value);
1408 LLVMContextRef context = LLVMGetTypeContext(type);
1409
1410 md_args[0] = LLVMConstInt(type, lo, false);
1411 md_args[1] = LLVMConstInt(type, hi, false);
1412 range_md = LLVMMDNodeInContext(context, md_args, 2);
1413 LLVMSetMetadata(value, ctx->range_md_kind, range_md);
1414 }
1415
1416 static LLVMValueRef get_thread_id(struct si_shader_context *ctx)
1417 {
1418 struct gallivm_state *gallivm = &ctx->gallivm;
1419 LLVMValueRef tid;
1420
1421 if (HAVE_LLVM < 0x0308) {
1422 tid = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid",
1423 ctx->i32, NULL, 0, LP_FUNC_ATTR_READNONE);
1424 } else {
1425 LLVMValueRef tid_args[2];
1426 tid_args[0] = lp_build_const_int32(gallivm, 0xffffffff);
1427 tid_args[1] = lp_build_const_int32(gallivm, 0);
1428 tid_args[1] = lp_build_intrinsic(gallivm->builder,
1429 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1430 tid_args, 2, LP_FUNC_ATTR_READNONE);
1431
1432 tid = lp_build_intrinsic(gallivm->builder,
1433 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1434 tid_args, 2, LP_FUNC_ATTR_READNONE);
1435 }
1436 set_range_metadata(ctx, tid, 0, 64);
1437 return tid;
1438 }
1439
1440 /**
1441 * Load a dword from a constant buffer.
1442 */
1443 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1444 LLVMValueRef resource,
1445 LLVMValueRef offset)
1446 {
1447 LLVMBuilderRef builder = ctx->gallivm.builder;
1448 LLVMValueRef args[2] = {resource, offset};
1449
1450 return lp_build_intrinsic(builder, "llvm.SI.load.const", ctx->f32, args, 2,
1451 LP_FUNC_ATTR_READNONE);
1452 }
1453
1454 static LLVMValueRef load_sample_position(struct si_shader_context *radeon_bld, LLVMValueRef sample_id)
1455 {
1456 struct si_shader_context *ctx =
1457 si_shader_context(&radeon_bld->soa.bld_base);
1458 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1459 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1460 LLVMBuilderRef builder = gallivm->builder;
1461 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1462 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1463 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1464
1465 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1466 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1467 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1468
1469 LLVMValueRef pos[4] = {
1470 buffer_load_const(ctx, resource, offset0),
1471 buffer_load_const(ctx, resource, offset1),
1472 lp_build_const_float(gallivm, 0),
1473 lp_build_const_float(gallivm, 0)
1474 };
1475
1476 return lp_build_gather_values(gallivm, pos, 4);
1477 }
1478
1479 static void declare_system_value(
1480 struct si_shader_context *radeon_bld,
1481 unsigned index,
1482 const struct tgsi_full_declaration *decl)
1483 {
1484 struct si_shader_context *ctx =
1485 si_shader_context(&radeon_bld->soa.bld_base);
1486 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1487 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1488 LLVMValueRef value = 0;
1489
1490 switch (decl->Semantic.Name) {
1491 case TGSI_SEMANTIC_INSTANCEID:
1492 value = LLVMGetParam(radeon_bld->main_fn,
1493 ctx->param_instance_id);
1494 break;
1495
1496 case TGSI_SEMANTIC_VERTEXID:
1497 value = LLVMBuildAdd(gallivm->builder,
1498 LLVMGetParam(radeon_bld->main_fn,
1499 ctx->param_vertex_id),
1500 LLVMGetParam(radeon_bld->main_fn,
1501 SI_PARAM_BASE_VERTEX), "");
1502 break;
1503
1504 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1505 value = LLVMGetParam(radeon_bld->main_fn,
1506 ctx->param_vertex_id);
1507 break;
1508
1509 case TGSI_SEMANTIC_BASEVERTEX:
1510 value = LLVMGetParam(radeon_bld->main_fn,
1511 SI_PARAM_BASE_VERTEX);
1512 break;
1513
1514 case TGSI_SEMANTIC_BASEINSTANCE:
1515 value = LLVMGetParam(radeon_bld->main_fn,
1516 SI_PARAM_START_INSTANCE);
1517 break;
1518
1519 case TGSI_SEMANTIC_DRAWID:
1520 value = LLVMGetParam(radeon_bld->main_fn,
1521 SI_PARAM_DRAWID);
1522 break;
1523
1524 case TGSI_SEMANTIC_INVOCATIONID:
1525 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1526 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1527 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1528 value = LLVMGetParam(radeon_bld->main_fn,
1529 SI_PARAM_GS_INSTANCE_ID);
1530 else
1531 assert(!"INVOCATIONID not implemented");
1532 break;
1533
1534 case TGSI_SEMANTIC_POSITION:
1535 {
1536 LLVMValueRef pos[4] = {
1537 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1538 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1539 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1540 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1541 LLVMGetParam(radeon_bld->main_fn,
1542 SI_PARAM_POS_W_FLOAT)),
1543 };
1544 value = lp_build_gather_values(gallivm, pos, 4);
1545 break;
1546 }
1547
1548 case TGSI_SEMANTIC_FACE:
1549 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1550 break;
1551
1552 case TGSI_SEMANTIC_SAMPLEID:
1553 value = get_sample_id(radeon_bld);
1554 break;
1555
1556 case TGSI_SEMANTIC_SAMPLEPOS: {
1557 LLVMValueRef pos[4] = {
1558 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1559 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1560 lp_build_const_float(gallivm, 0),
1561 lp_build_const_float(gallivm, 0)
1562 };
1563 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1564 TGSI_OPCODE_FRC, pos[0]);
1565 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1566 TGSI_OPCODE_FRC, pos[1]);
1567 value = lp_build_gather_values(gallivm, pos, 4);
1568 break;
1569 }
1570
1571 case TGSI_SEMANTIC_SAMPLEMASK:
1572 /* This can only occur with the OpenGL Core profile, which
1573 * doesn't support smoothing.
1574 */
1575 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1576 break;
1577
1578 case TGSI_SEMANTIC_TESSCOORD:
1579 {
1580 LLVMValueRef coord[4] = {
1581 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1582 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1583 bld->zero,
1584 bld->zero
1585 };
1586
1587 /* For triangles, the vector should be (u, v, 1-u-v). */
1588 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1589 PIPE_PRIM_TRIANGLES)
1590 coord[2] = lp_build_sub(bld, bld->one,
1591 lp_build_add(bld, coord[0], coord[1]));
1592
1593 value = lp_build_gather_values(gallivm, coord, 4);
1594 break;
1595 }
1596
1597 case TGSI_SEMANTIC_VERTICESIN:
1598 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1599 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1600 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1601 value = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 7);
1602 else
1603 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1604 break;
1605
1606 case TGSI_SEMANTIC_TESSINNER:
1607 case TGSI_SEMANTIC_TESSOUTER:
1608 {
1609 LLVMValueRef rw_buffers, buffer, base, addr;
1610 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1611
1612 rw_buffers = LLVMGetParam(ctx->main_fn,
1613 SI_PARAM_RW_BUFFERS);
1614 buffer = build_indexed_load_const(ctx, rw_buffers,
1615 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1616
1617 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1618 addr = get_tcs_tes_buffer_address(ctx, NULL,
1619 lp_build_const_int32(gallivm, param));
1620
1621 value = buffer_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1622 ~0, buffer, base, addr);
1623
1624 break;
1625 }
1626
1627 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1628 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1629 {
1630 LLVMValueRef buf, slot, val[4];
1631 int i, offset;
1632
1633 slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
1634 buf = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1635 buf = build_indexed_load_const(ctx, buf, slot);
1636 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1637
1638 for (i = 0; i < 4; i++)
1639 val[i] = buffer_load_const(ctx, buf,
1640 lp_build_const_int32(gallivm, (offset + i) * 4));
1641 value = lp_build_gather_values(gallivm, val, 4);
1642 break;
1643 }
1644
1645 case TGSI_SEMANTIC_PRIMID:
1646 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1647 break;
1648
1649 case TGSI_SEMANTIC_GRID_SIZE:
1650 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1651 break;
1652
1653 case TGSI_SEMANTIC_BLOCK_SIZE:
1654 {
1655 LLVMValueRef values[3];
1656 unsigned i;
1657 unsigned *properties = ctx->shader->selector->info.properties;
1658
1659 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1660 unsigned sizes[3] = {
1661 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1662 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1663 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1664 };
1665
1666 for (i = 0; i < 3; ++i)
1667 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1668
1669 value = lp_build_gather_values(gallivm, values, 3);
1670 } else {
1671 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_SIZE);
1672 }
1673 break;
1674 }
1675
1676 case TGSI_SEMANTIC_BLOCK_ID:
1677 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1678 break;
1679
1680 case TGSI_SEMANTIC_THREAD_ID:
1681 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1682 break;
1683
1684 #if HAVE_LLVM >= 0x0309
1685 case TGSI_SEMANTIC_HELPER_INVOCATION:
1686 value = lp_build_intrinsic(gallivm->builder,
1687 "llvm.amdgcn.ps.live",
1688 ctx->i1, NULL, 0,
1689 LP_FUNC_ATTR_READNONE);
1690 value = LLVMBuildNot(gallivm->builder, value, "");
1691 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1692 break;
1693 #endif
1694
1695 default:
1696 assert(!"unknown system value");
1697 return;
1698 }
1699
1700 radeon_bld->system_values[index] = value;
1701 }
1702
1703 static void declare_compute_memory(struct si_shader_context *radeon_bld,
1704 const struct tgsi_full_declaration *decl)
1705 {
1706 struct si_shader_context *ctx =
1707 si_shader_context(&radeon_bld->soa.bld_base);
1708 struct si_shader_selector *sel = ctx->shader->selector;
1709 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1710
1711 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1712 LLVMValueRef var;
1713
1714 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1715 assert(decl->Range.First == decl->Range.Last);
1716 assert(!ctx->shared_memory);
1717
1718 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1719 LLVMArrayType(ctx->i8, sel->local_size),
1720 "compute_lds",
1721 LOCAL_ADDR_SPACE);
1722 LLVMSetAlignment(var, 4);
1723
1724 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1725 }
1726
1727 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1728 {
1729 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1730 SI_PARAM_CONST_BUFFERS);
1731
1732 return build_indexed_load_const(ctx, list_ptr,
1733 LLVMConstInt(ctx->i32, i, 0));
1734 }
1735
1736 static LLVMValueRef fetch_constant(
1737 struct lp_build_tgsi_context *bld_base,
1738 const struct tgsi_full_src_register *reg,
1739 enum tgsi_opcode_type type,
1740 unsigned swizzle)
1741 {
1742 struct si_shader_context *ctx = si_shader_context(bld_base);
1743 struct lp_build_context *base = &bld_base->base;
1744 const struct tgsi_ind_register *ireg = &reg->Indirect;
1745 unsigned buf, idx;
1746
1747 LLVMValueRef addr, bufp;
1748 LLVMValueRef result;
1749
1750 if (swizzle == LP_CHAN_ALL) {
1751 unsigned chan;
1752 LLVMValueRef values[4];
1753 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1754 values[chan] = fetch_constant(bld_base, reg, type, chan);
1755
1756 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1757 }
1758
1759 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1760 idx = reg->Register.Index * 4 + swizzle;
1761
1762 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1763 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_CONST_BUFFERS);
1764 LLVMValueRef index;
1765 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1766 reg->Dimension.Index,
1767 SI_NUM_CONST_BUFFERS);
1768 bufp = build_indexed_load_const(ctx, ptr, index);
1769 } else
1770 bufp = load_const_buffer_desc(ctx, buf);
1771
1772 if (reg->Register.Indirect) {
1773 addr = ctx->soa.addr[ireg->Index][ireg->Swizzle];
1774 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1775 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1776 addr = lp_build_add(&bld_base->uint_bld, addr,
1777 lp_build_const_int32(base->gallivm, idx * 4));
1778 } else {
1779 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
1780 }
1781
1782 result = buffer_load_const(ctx, bufp, addr);
1783
1784 if (!tgsi_type_is_64bit(type))
1785 result = bitcast(bld_base, type, result);
1786 else {
1787 LLVMValueRef addr2, result2;
1788
1789 addr2 = lp_build_add(&bld_base->uint_bld, addr,
1790 LLVMConstInt(ctx->i32, 4, 0));
1791 result2 = buffer_load_const(ctx, bufp, addr2);
1792
1793 result = si_llvm_emit_fetch_64bit(bld_base, type,
1794 result, result2);
1795 }
1796 return result;
1797 }
1798
1799 /* Upper 16 bits must be zero. */
1800 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1801 LLVMValueRef val[2])
1802 {
1803 return LLVMBuildOr(gallivm->builder, val[0],
1804 LLVMBuildShl(gallivm->builder, val[1],
1805 lp_build_const_int32(gallivm, 16),
1806 ""), "");
1807 }
1808
1809 /* Upper 16 bits are ignored and will be dropped. */
1810 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1811 LLVMValueRef val[2])
1812 {
1813 LLVMValueRef v[2] = {
1814 LLVMBuildAnd(gallivm->builder, val[0],
1815 lp_build_const_int32(gallivm, 0xffff), ""),
1816 val[1],
1817 };
1818 return si_llvm_pack_two_int16(gallivm, v);
1819 }
1820
1821 /* Initialize arguments for the shader export intrinsic */
1822 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1823 LLVMValueRef *values,
1824 unsigned target,
1825 LLVMValueRef *args)
1826 {
1827 struct si_shader_context *ctx = si_shader_context(bld_base);
1828 struct lp_build_context *uint =
1829 &ctx->soa.bld_base.uint_bld;
1830 struct lp_build_context *base = &bld_base->base;
1831 struct gallivm_state *gallivm = base->gallivm;
1832 LLVMBuilderRef builder = base->gallivm->builder;
1833 LLVMValueRef val[4];
1834 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1835 unsigned chan;
1836 bool is_int8;
1837
1838 /* Default is 0xf. Adjusted below depending on the format. */
1839 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1840
1841 /* Specify whether the EXEC mask represents the valid mask */
1842 args[1] = uint->zero;
1843
1844 /* Specify whether this is the last export */
1845 args[2] = uint->zero;
1846
1847 /* Specify the target we are exporting */
1848 args[3] = lp_build_const_int32(base->gallivm, target);
1849
1850 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1851 const struct si_shader_key *key = &ctx->shader->key;
1852 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
1853 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1854
1855 assert(cbuf >= 0 && cbuf < 8);
1856 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1857 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
1858 }
1859
1860 args[4] = uint->zero; /* COMPR flag */
1861 args[5] = base->undef;
1862 args[6] = base->undef;
1863 args[7] = base->undef;
1864 args[8] = base->undef;
1865
1866 switch (spi_shader_col_format) {
1867 case V_028714_SPI_SHADER_ZERO:
1868 args[0] = uint->zero; /* writemask */
1869 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
1870 break;
1871
1872 case V_028714_SPI_SHADER_32_R:
1873 args[0] = uint->one; /* writemask */
1874 args[5] = values[0];
1875 break;
1876
1877 case V_028714_SPI_SHADER_32_GR:
1878 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
1879 args[5] = values[0];
1880 args[6] = values[1];
1881 break;
1882
1883 case V_028714_SPI_SHADER_32_AR:
1884 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
1885 args[5] = values[0];
1886 args[8] = values[3];
1887 break;
1888
1889 case V_028714_SPI_SHADER_FP16_ABGR:
1890 args[4] = uint->one; /* COMPR flag */
1891
1892 for (chan = 0; chan < 2; chan++) {
1893 LLVMValueRef pack_args[2] = {
1894 values[2 * chan],
1895 values[2 * chan + 1]
1896 };
1897 LLVMValueRef packed;
1898
1899 packed = lp_build_intrinsic(base->gallivm->builder,
1900 "llvm.SI.packf16",
1901 ctx->i32, pack_args, 2,
1902 LP_FUNC_ATTR_READNONE);
1903 args[chan + 5] =
1904 LLVMBuildBitCast(base->gallivm->builder,
1905 packed, ctx->f32, "");
1906 }
1907 break;
1908
1909 case V_028714_SPI_SHADER_UNORM16_ABGR:
1910 for (chan = 0; chan < 4; chan++) {
1911 val[chan] = si_llvm_saturate(bld_base, values[chan]);
1912 val[chan] = LLVMBuildFMul(builder, val[chan],
1913 lp_build_const_float(gallivm, 65535), "");
1914 val[chan] = LLVMBuildFAdd(builder, val[chan],
1915 lp_build_const_float(gallivm, 0.5), "");
1916 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1917 ctx->i32, "");
1918 }
1919
1920 args[4] = uint->one; /* COMPR flag */
1921 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1922 si_llvm_pack_two_int16(gallivm, val));
1923 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1924 si_llvm_pack_two_int16(gallivm, val+2));
1925 break;
1926
1927 case V_028714_SPI_SHADER_SNORM16_ABGR:
1928 for (chan = 0; chan < 4; chan++) {
1929 /* Clamp between [-1, 1]. */
1930 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1931 values[chan],
1932 lp_build_const_float(gallivm, 1));
1933 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1934 val[chan],
1935 lp_build_const_float(gallivm, -1));
1936 /* Convert to a signed integer in [-32767, 32767]. */
1937 val[chan] = LLVMBuildFMul(builder, val[chan],
1938 lp_build_const_float(gallivm, 32767), "");
1939 /* If positive, add 0.5, else add -0.5. */
1940 val[chan] = LLVMBuildFAdd(builder, val[chan],
1941 LLVMBuildSelect(builder,
1942 LLVMBuildFCmp(builder, LLVMRealOGE,
1943 val[chan], base->zero, ""),
1944 lp_build_const_float(gallivm, 0.5),
1945 lp_build_const_float(gallivm, -0.5), ""), "");
1946 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
1947 }
1948
1949 args[4] = uint->one; /* COMPR flag */
1950 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1951 si_llvm_pack_two_int32_as_int16(gallivm, val));
1952 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1953 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1954 break;
1955
1956 case V_028714_SPI_SHADER_UINT16_ABGR: {
1957 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1958 255 : 65535);
1959 /* Clamp. */
1960 for (chan = 0; chan < 4; chan++) {
1961 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1962 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1963 val[chan], max);
1964 }
1965
1966 args[4] = uint->one; /* COMPR flag */
1967 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1968 si_llvm_pack_two_int16(gallivm, val));
1969 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1970 si_llvm_pack_two_int16(gallivm, val+2));
1971 break;
1972 }
1973
1974 case V_028714_SPI_SHADER_SINT16_ABGR: {
1975 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1976 127 : 32767);
1977 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
1978 -128 : -32768);
1979 /* Clamp. */
1980 for (chan = 0; chan < 4; chan++) {
1981 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1982 val[chan] = lp_build_emit_llvm_binary(bld_base,
1983 TGSI_OPCODE_IMIN,
1984 val[chan], max);
1985 val[chan] = lp_build_emit_llvm_binary(bld_base,
1986 TGSI_OPCODE_IMAX,
1987 val[chan], min);
1988 }
1989
1990 args[4] = uint->one; /* COMPR flag */
1991 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1992 si_llvm_pack_two_int32_as_int16(gallivm, val));
1993 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1994 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1995 break;
1996 }
1997
1998 case V_028714_SPI_SHADER_32_ABGR:
1999 memcpy(&args[5], values, sizeof(values[0]) * 4);
2000 break;
2001 }
2002 }
2003
2004 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2005 LLVMValueRef alpha)
2006 {
2007 struct si_shader_context *ctx = si_shader_context(bld_base);
2008 struct gallivm_state *gallivm = bld_base->base.gallivm;
2009
2010 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2011 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2012 SI_PARAM_ALPHA_REF);
2013
2014 LLVMValueRef alpha_pass =
2015 lp_build_cmp(&bld_base->base,
2016 ctx->shader->key.part.ps.epilog.alpha_func,
2017 alpha, alpha_ref);
2018 LLVMValueRef arg =
2019 lp_build_select(&bld_base->base,
2020 alpha_pass,
2021 lp_build_const_float(gallivm, 1.0f),
2022 lp_build_const_float(gallivm, -1.0f));
2023
2024 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2025 ctx->voidt, &arg, 1, 0);
2026 } else {
2027 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
2028 ctx->voidt, NULL, 0, 0);
2029 }
2030 }
2031
2032 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2033 LLVMValueRef alpha,
2034 unsigned samplemask_param)
2035 {
2036 struct si_shader_context *ctx = si_shader_context(bld_base);
2037 struct gallivm_state *gallivm = bld_base->base.gallivm;
2038 LLVMValueRef coverage;
2039
2040 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2041 coverage = LLVMGetParam(ctx->main_fn,
2042 samplemask_param);
2043 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
2044
2045 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
2046 ctx->i32,
2047 &coverage, 1, LP_FUNC_ATTR_READNONE);
2048
2049 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
2050 ctx->f32, "");
2051
2052 coverage = LLVMBuildFMul(gallivm->builder, coverage,
2053 lp_build_const_float(gallivm,
2054 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2055
2056 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
2057 }
2058
2059 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2060 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
2061 {
2062 struct si_shader_context *ctx = si_shader_context(bld_base);
2063 struct lp_build_context *base = &bld_base->base;
2064 struct lp_build_context *uint = &ctx->soa.bld_base.uint_bld;
2065 unsigned reg_index;
2066 unsigned chan;
2067 unsigned const_chan;
2068 LLVMValueRef base_elt;
2069 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2070 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
2071 SI_VS_CONST_CLIP_PLANES);
2072 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
2073
2074 for (reg_index = 0; reg_index < 2; reg_index ++) {
2075 LLVMValueRef *args = pos[2 + reg_index];
2076
2077 args[5] =
2078 args[6] =
2079 args[7] =
2080 args[8] = lp_build_const_float(base->gallivm, 0.0f);
2081
2082 /* Compute dot products of position and user clip plane vectors */
2083 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2084 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2085 args[1] = lp_build_const_int32(base->gallivm,
2086 ((reg_index * 4 + chan) * 4 +
2087 const_chan) * 4);
2088 base_elt = buffer_load_const(ctx, const_resource,
2089 args[1]);
2090 args[5 + chan] =
2091 lp_build_add(base, args[5 + chan],
2092 lp_build_mul(base, base_elt,
2093 out_elts[const_chan]));
2094 }
2095 }
2096
2097 args[0] = lp_build_const_int32(base->gallivm, 0xf);
2098 args[1] = uint->zero;
2099 args[2] = uint->zero;
2100 args[3] = lp_build_const_int32(base->gallivm,
2101 V_008DFC_SQ_EXP_POS + 2 + reg_index);
2102 args[4] = uint->zero;
2103 }
2104 }
2105
2106 static void si_dump_streamout(struct pipe_stream_output_info *so)
2107 {
2108 unsigned i;
2109
2110 if (so->num_outputs)
2111 fprintf(stderr, "STREAMOUT\n");
2112
2113 for (i = 0; i < so->num_outputs; i++) {
2114 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2115 so->output[i].start_component;
2116 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2117 i, so->output[i].output_buffer,
2118 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2119 so->output[i].register_index,
2120 mask & 1 ? "x" : "",
2121 mask & 2 ? "y" : "",
2122 mask & 4 ? "z" : "",
2123 mask & 8 ? "w" : "");
2124 }
2125 }
2126
2127 /* On SI, the vertex shader is responsible for writing streamout data
2128 * to buffers. */
2129 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2130 struct si_shader_output_values *outputs,
2131 unsigned noutput)
2132 {
2133 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
2134 struct gallivm_state *gallivm = &ctx->gallivm;
2135 LLVMBuilderRef builder = gallivm->builder;
2136 int i, j;
2137 struct lp_build_if_state if_ctx;
2138 LLVMValueRef so_buffers[4];
2139 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2140 SI_PARAM_RW_BUFFERS);
2141
2142 /* Load the descriptors. */
2143 for (i = 0; i < 4; ++i) {
2144 if (ctx->shader->selector->so.stride[i]) {
2145 LLVMValueRef offset = lp_build_const_int32(gallivm,
2146 SI_VS_STREAMOUT_BUF0 + i);
2147
2148 so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
2149 }
2150 }
2151
2152 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2153 LLVMValueRef so_vtx_count =
2154 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2155
2156 LLVMValueRef tid = get_thread_id(ctx);
2157
2158 /* can_emit = tid < so_vtx_count; */
2159 LLVMValueRef can_emit =
2160 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2161
2162 LLVMValueRef stream_id =
2163 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
2164
2165 /* Emit the streamout code conditionally. This actually avoids
2166 * out-of-bounds buffer access. The hw tells us via the SGPR
2167 * (so_vtx_count) which threads are allowed to emit streamout data. */
2168 lp_build_if(&if_ctx, gallivm, can_emit);
2169 {
2170 /* The buffer offset is computed as follows:
2171 * ByteOffset = streamout_offset[buffer_id]*4 +
2172 * (streamout_write_index + thread_id)*stride[buffer_id] +
2173 * attrib_offset
2174 */
2175
2176 LLVMValueRef so_write_index =
2177 LLVMGetParam(ctx->main_fn,
2178 ctx->param_streamout_write_index);
2179
2180 /* Compute (streamout_write_index + thread_id). */
2181 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2182
2183 /* Compute the write offset for each enabled buffer. */
2184 LLVMValueRef so_write_offset[4] = {};
2185 for (i = 0; i < 4; i++) {
2186 if (!so->stride[i])
2187 continue;
2188
2189 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2190 ctx->param_streamout_offset[i]);
2191 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2192
2193 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2194 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2195 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2196 }
2197
2198 /* Write streamout data. */
2199 for (i = 0; i < so->num_outputs; i++) {
2200 unsigned buf_idx = so->output[i].output_buffer;
2201 unsigned reg = so->output[i].register_index;
2202 unsigned start = so->output[i].start_component;
2203 unsigned num_comps = so->output[i].num_components;
2204 unsigned stream = so->output[i].stream;
2205 LLVMValueRef out[4];
2206 struct lp_build_if_state if_ctx_stream;
2207
2208 assert(num_comps && num_comps <= 4);
2209 if (!num_comps || num_comps > 4)
2210 continue;
2211
2212 if (reg >= noutput)
2213 continue;
2214
2215 /* Load the output as int. */
2216 for (j = 0; j < num_comps; j++) {
2217 out[j] = LLVMBuildBitCast(builder,
2218 outputs[reg].values[start+j],
2219 ctx->i32, "");
2220 }
2221
2222 /* Pack the output. */
2223 LLVMValueRef vdata = NULL;
2224
2225 switch (num_comps) {
2226 case 1: /* as i32 */
2227 vdata = out[0];
2228 break;
2229 case 2: /* as v2i32 */
2230 case 3: /* as v4i32 (aligned to 4) */
2231 case 4: /* as v4i32 */
2232 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2233 for (j = 0; j < num_comps; j++) {
2234 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2235 LLVMConstInt(ctx->i32, j, 0), "");
2236 }
2237 break;
2238 }
2239
2240 LLVMValueRef can_emit_stream =
2241 LLVMBuildICmp(builder, LLVMIntEQ,
2242 stream_id,
2243 lp_build_const_int32(gallivm, stream), "");
2244
2245 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
2246 build_tbuffer_store_dwords(ctx, so_buffers[buf_idx],
2247 vdata, num_comps,
2248 so_write_offset[buf_idx],
2249 LLVMConstInt(ctx->i32, 0, 0),
2250 so->output[i].dst_offset*4);
2251 lp_build_endif(&if_ctx_stream);
2252 }
2253 }
2254 lp_build_endif(&if_ctx);
2255 }
2256
2257
2258 /* Generate export instructions for hardware VS shader stage */
2259 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2260 struct si_shader_output_values *outputs,
2261 unsigned noutput)
2262 {
2263 struct si_shader_context *ctx = si_shader_context(bld_base);
2264 struct si_shader *shader = ctx->shader;
2265 struct lp_build_context *base = &bld_base->base;
2266 struct lp_build_context *uint =
2267 &ctx->soa.bld_base.uint_bld;
2268 LLVMValueRef args[9];
2269 LLVMValueRef pos_args[4][9] = { { 0 } };
2270 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2271 unsigned semantic_name, semantic_index;
2272 unsigned target;
2273 unsigned param_count = 0;
2274 unsigned pos_idx;
2275 int i;
2276
2277 if (outputs && ctx->shader->selector->so.num_outputs) {
2278 si_llvm_emit_streamout(ctx, outputs, noutput);
2279 }
2280
2281 for (i = 0; i < noutput; i++) {
2282 semantic_name = outputs[i].name;
2283 semantic_index = outputs[i].sid;
2284 bool export_param = true;
2285
2286 switch (semantic_name) {
2287 case TGSI_SEMANTIC_POSITION: /* ignore these */
2288 case TGSI_SEMANTIC_PSIZE:
2289 case TGSI_SEMANTIC_CLIPVERTEX:
2290 case TGSI_SEMANTIC_EDGEFLAG:
2291 break;
2292 case TGSI_SEMANTIC_GENERIC:
2293 case TGSI_SEMANTIC_CLIPDIST:
2294 if (shader->key.opt.hw_vs.kill_outputs &
2295 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2296 export_param = false;
2297 break;
2298 default:
2299 if (shader->key.opt.hw_vs.kill_outputs2 &
2300 (1u << si_shader_io_get_unique_index2(semantic_name, semantic_index)))
2301 export_param = false;
2302 break;
2303 }
2304
2305 handle_semantic:
2306 /* Select the correct target */
2307 switch(semantic_name) {
2308 case TGSI_SEMANTIC_PSIZE:
2309 psize_value = outputs[i].values[0];
2310 continue;
2311 case TGSI_SEMANTIC_EDGEFLAG:
2312 edgeflag_value = outputs[i].values[0];
2313 continue;
2314 case TGSI_SEMANTIC_LAYER:
2315 layer_value = outputs[i].values[0];
2316 semantic_name = TGSI_SEMANTIC_GENERIC;
2317 goto handle_semantic;
2318 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2319 viewport_index_value = outputs[i].values[0];
2320 semantic_name = TGSI_SEMANTIC_GENERIC;
2321 goto handle_semantic;
2322 case TGSI_SEMANTIC_POSITION:
2323 target = V_008DFC_SQ_EXP_POS;
2324 break;
2325 case TGSI_SEMANTIC_COLOR:
2326 case TGSI_SEMANTIC_BCOLOR:
2327 if (!export_param)
2328 continue;
2329 target = V_008DFC_SQ_EXP_PARAM + param_count;
2330 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2331 shader->info.vs_output_param_offset[i] = param_count;
2332 param_count++;
2333 break;
2334 case TGSI_SEMANTIC_CLIPDIST:
2335 if (shader->key.opt.hw_vs.clip_disable) {
2336 semantic_name = TGSI_SEMANTIC_GENERIC;
2337 goto handle_semantic;
2338 }
2339 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2340 break;
2341 case TGSI_SEMANTIC_CLIPVERTEX:
2342 if (shader->key.opt.hw_vs.clip_disable)
2343 continue;
2344 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2345 continue;
2346 case TGSI_SEMANTIC_PRIMID:
2347 case TGSI_SEMANTIC_FOG:
2348 case TGSI_SEMANTIC_TEXCOORD:
2349 case TGSI_SEMANTIC_GENERIC:
2350 if (!export_param)
2351 continue;
2352 target = V_008DFC_SQ_EXP_PARAM + param_count;
2353 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2354 shader->info.vs_output_param_offset[i] = param_count;
2355 param_count++;
2356 break;
2357 default:
2358 target = 0;
2359 fprintf(stderr,
2360 "Warning: SI unhandled vs output type:%d\n",
2361 semantic_name);
2362 }
2363
2364 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
2365
2366 if (target >= V_008DFC_SQ_EXP_POS &&
2367 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2368 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
2369 args, sizeof(args));
2370 } else {
2371 lp_build_intrinsic(base->gallivm->builder,
2372 "llvm.SI.export", ctx->voidt,
2373 args, 9, 0);
2374 }
2375
2376 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2377 semantic_name = TGSI_SEMANTIC_GENERIC;
2378 goto handle_semantic;
2379 }
2380 }
2381
2382 shader->info.nr_param_exports = param_count;
2383
2384 /* We need to add the position output manually if it's missing. */
2385 if (!pos_args[0][0]) {
2386 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
2387 pos_args[0][1] = uint->zero; /* EXEC mask */
2388 pos_args[0][2] = uint->zero; /* last export? */
2389 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
2390 pos_args[0][4] = uint->zero; /* COMPR flag */
2391 pos_args[0][5] = base->zero; /* X */
2392 pos_args[0][6] = base->zero; /* Y */
2393 pos_args[0][7] = base->zero; /* Z */
2394 pos_args[0][8] = base->one; /* W */
2395 }
2396
2397 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2398 if (shader->selector->info.writes_psize ||
2399 shader->selector->info.writes_edgeflag ||
2400 shader->selector->info.writes_viewport_index ||
2401 shader->selector->info.writes_layer) {
2402 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
2403 shader->selector->info.writes_psize |
2404 (shader->selector->info.writes_edgeflag << 1) |
2405 (shader->selector->info.writes_layer << 2) |
2406 (shader->selector->info.writes_viewport_index << 3));
2407 pos_args[1][1] = uint->zero; /* EXEC mask */
2408 pos_args[1][2] = uint->zero; /* last export? */
2409 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
2410 pos_args[1][4] = uint->zero; /* COMPR flag */
2411 pos_args[1][5] = base->zero; /* X */
2412 pos_args[1][6] = base->zero; /* Y */
2413 pos_args[1][7] = base->zero; /* Z */
2414 pos_args[1][8] = base->zero; /* W */
2415
2416 if (shader->selector->info.writes_psize)
2417 pos_args[1][5] = psize_value;
2418
2419 if (shader->selector->info.writes_edgeflag) {
2420 /* The output is a float, but the hw expects an integer
2421 * with the first bit containing the edge flag. */
2422 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2423 edgeflag_value,
2424 ctx->i32, "");
2425 edgeflag_value = lp_build_min(&bld_base->int_bld,
2426 edgeflag_value,
2427 bld_base->int_bld.one);
2428
2429 /* The LLVM intrinsic expects a float. */
2430 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
2431 edgeflag_value,
2432 ctx->f32, "");
2433 }
2434
2435 if (shader->selector->info.writes_layer)
2436 pos_args[1][7] = layer_value;
2437
2438 if (shader->selector->info.writes_viewport_index)
2439 pos_args[1][8] = viewport_index_value;
2440 }
2441
2442 for (i = 0; i < 4; i++)
2443 if (pos_args[i][0])
2444 shader->info.nr_pos_exports++;
2445
2446 pos_idx = 0;
2447 for (i = 0; i < 4; i++) {
2448 if (!pos_args[i][0])
2449 continue;
2450
2451 /* Specify the target we are exporting */
2452 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2453
2454 if (pos_idx == shader->info.nr_pos_exports)
2455 /* Specify that this is the last export */
2456 pos_args[i][2] = uint->one;
2457
2458 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2459 ctx->voidt, pos_args[i], 9, 0);
2460 }
2461 }
2462
2463 /**
2464 * Forward all outputs from the vertex shader to the TES. This is only used
2465 * for the fixed function TCS.
2466 */
2467 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2468 {
2469 struct si_shader_context *ctx = si_shader_context(bld_base);
2470 struct gallivm_state *gallivm = bld_base->base.gallivm;
2471 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2472 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2473 uint64_t inputs;
2474
2475 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2476
2477 rw_buffers = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2478 buffer = build_indexed_load_const(ctx, rw_buffers,
2479 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
2480
2481 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2482
2483 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
2484 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2485 lds_vertex_stride, "");
2486 lds_base = get_tcs_in_current_patch_offset(ctx);
2487 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2488
2489 inputs = ctx->shader->key.mono.tcs.inputs_to_copy;
2490 while (inputs) {
2491 unsigned i = u_bit_scan64(&inputs);
2492
2493 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2494 lp_build_const_int32(gallivm, 4 * i),
2495 "");
2496
2497 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2498 invocation_id,
2499 lp_build_const_int32(gallivm, i));
2500
2501 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2502 lds_ptr);
2503
2504 build_tbuffer_store_dwords(ctx, buffer, value, 4, buffer_addr,
2505 buffer_offset, 0);
2506 }
2507 }
2508
2509 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2510 LLVMValueRef rel_patch_id,
2511 LLVMValueRef invocation_id,
2512 LLVMValueRef tcs_out_current_patch_data_offset)
2513 {
2514 struct si_shader_context *ctx = si_shader_context(bld_base);
2515 struct gallivm_state *gallivm = bld_base->base.gallivm;
2516 struct si_shader *shader = ctx->shader;
2517 unsigned tess_inner_index, tess_outer_index;
2518 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2519 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2520 unsigned stride, outer_comps, inner_comps, i;
2521 struct lp_build_if_state if_ctx, inner_if_ctx;
2522
2523 si_llvm_emit_barrier(NULL, bld_base, NULL);
2524
2525 /* Do this only for invocation 0, because the tess levels are per-patch,
2526 * not per-vertex.
2527 *
2528 * This can't jump, because invocation 0 executes this. It should
2529 * at least mask out the loads and stores for other invocations.
2530 */
2531 lp_build_if(&if_ctx, gallivm,
2532 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2533 invocation_id, bld_base->uint_bld.zero, ""));
2534
2535 /* Determine the layout of one tess factor element in the buffer. */
2536 switch (shader->key.part.tcs.epilog.prim_mode) {
2537 case PIPE_PRIM_LINES:
2538 stride = 2; /* 2 dwords, 1 vec2 store */
2539 outer_comps = 2;
2540 inner_comps = 0;
2541 break;
2542 case PIPE_PRIM_TRIANGLES:
2543 stride = 4; /* 4 dwords, 1 vec4 store */
2544 outer_comps = 3;
2545 inner_comps = 1;
2546 break;
2547 case PIPE_PRIM_QUADS:
2548 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2549 outer_comps = 4;
2550 inner_comps = 2;
2551 break;
2552 default:
2553 assert(0);
2554 return;
2555 }
2556
2557 /* Load tess_inner and tess_outer from LDS.
2558 * Any invocation can write them, so we can't get them from a temporary.
2559 */
2560 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2561 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2562
2563 lds_base = tcs_out_current_patch_data_offset;
2564 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2565 lp_build_const_int32(gallivm,
2566 tess_inner_index * 4), "");
2567 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2568 lp_build_const_int32(gallivm,
2569 tess_outer_index * 4), "");
2570
2571 for (i = 0; i < outer_comps; i++)
2572 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2573 for (i = 0; i < inner_comps; i++)
2574 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2575
2576 /* Convert the outputs to vectors for stores. */
2577 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2578 vec1 = NULL;
2579
2580 if (stride > 4)
2581 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2582
2583 /* Get the buffer. */
2584 rw_buffers = LLVMGetParam(ctx->main_fn,
2585 SI_PARAM_RW_BUFFERS);
2586 buffer = build_indexed_load_const(ctx, rw_buffers,
2587 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2588
2589 /* Get the offset. */
2590 tf_base = LLVMGetParam(ctx->main_fn,
2591 SI_PARAM_TESS_FACTOR_OFFSET);
2592 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2593 lp_build_const_int32(gallivm, 4 * stride), "");
2594
2595 lp_build_if(&inner_if_ctx, gallivm,
2596 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2597 rel_patch_id, bld_base->uint_bld.zero, ""));
2598
2599 /* Store the dynamic HS control word. */
2600 build_tbuffer_store_dwords(ctx, buffer,
2601 lp_build_const_int32(gallivm, 0x80000000),
2602 1, lp_build_const_int32(gallivm, 0), tf_base, 0);
2603
2604 lp_build_endif(&inner_if_ctx);
2605
2606 /* Store the tessellation factors. */
2607 build_tbuffer_store_dwords(ctx, buffer, vec0,
2608 MIN2(stride, 4), byteoffset, tf_base, 4);
2609 if (vec1)
2610 build_tbuffer_store_dwords(ctx, buffer, vec1,
2611 stride - 4, byteoffset, tf_base, 20);
2612 lp_build_endif(&if_ctx);
2613 }
2614
2615 /* This only writes the tessellation factor levels. */
2616 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2617 {
2618 struct si_shader_context *ctx = si_shader_context(bld_base);
2619 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2620
2621 si_copy_tcs_inputs(bld_base);
2622
2623 rel_patch_id = get_rel_patch_id(ctx);
2624 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2625 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2626
2627 /* Return epilog parameters from this function. */
2628 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2629 LLVMValueRef ret = ctx->return_value;
2630 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2631 unsigned vgpr;
2632
2633 /* RW_BUFFERS pointer */
2634 rw_buffers = LLVMGetParam(ctx->main_fn,
2635 SI_PARAM_RW_BUFFERS);
2636 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2637 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2638 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2639 bld_base->uint_bld.zero, "");
2640 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2641 bld_base->uint_bld.one, "");
2642 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2643 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2644
2645 /* Tess factor buffer soffset is after user SGPRs. */
2646 tf_soffset = LLVMGetParam(ctx->main_fn,
2647 SI_PARAM_TESS_FACTOR_OFFSET);
2648 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2649 SI_TCS_NUM_USER_SGPR + 1, "");
2650
2651 /* VGPRs */
2652 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2653 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2654 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2655
2656 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2657 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2658 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2659 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2660 ctx->return_value = ret;
2661 }
2662
2663 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2664 {
2665 struct si_shader_context *ctx = si_shader_context(bld_base);
2666 struct si_shader *shader = ctx->shader;
2667 struct tgsi_shader_info *info = &shader->selector->info;
2668 struct gallivm_state *gallivm = bld_base->base.gallivm;
2669 unsigned i, chan;
2670 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
2671 ctx->param_rel_auto_id);
2672 LLVMValueRef vertex_dw_stride =
2673 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2674 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2675 vertex_dw_stride, "");
2676
2677 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2678 * its inputs from it. */
2679 for (i = 0; i < info->num_outputs; i++) {
2680 LLVMValueRef *out_ptr = ctx->soa.outputs[i];
2681 unsigned name = info->output_semantic_name[i];
2682 unsigned index = info->output_semantic_index[i];
2683 int param = si_shader_io_get_unique_index(name, index);
2684 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2685 lp_build_const_int32(gallivm, param * 4), "");
2686
2687 for (chan = 0; chan < 4; chan++) {
2688 lds_store(bld_base, chan, dw_addr,
2689 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2690 }
2691 }
2692 }
2693
2694 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2695 {
2696 struct si_shader_context *ctx = si_shader_context(bld_base);
2697 struct gallivm_state *gallivm = bld_base->base.gallivm;
2698 struct si_shader *es = ctx->shader;
2699 struct tgsi_shader_info *info = &es->selector->info;
2700 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
2701 ctx->param_es2gs_offset);
2702 unsigned chan;
2703 int i;
2704
2705 for (i = 0; i < info->num_outputs; i++) {
2706 LLVMValueRef *out_ptr =
2707 ctx->soa.outputs[i];
2708 int param_index;
2709
2710 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2711 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2712 continue;
2713
2714 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2715 info->output_semantic_index[i]);
2716
2717 for (chan = 0; chan < 4; chan++) {
2718 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2719 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2720
2721 build_tbuffer_store(ctx,
2722 ctx->esgs_ring,
2723 out_val, 1,
2724 LLVMGetUndef(ctx->i32), soffset,
2725 (4 * param_index + chan) * 4,
2726 V_008F0C_BUF_DATA_FORMAT_32,
2727 V_008F0C_BUF_NUM_FORMAT_UINT,
2728 0, 0, 1, 1, 0);
2729 }
2730 }
2731 }
2732
2733 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2734 {
2735 struct si_shader_context *ctx = si_shader_context(bld_base);
2736 struct gallivm_state *gallivm = bld_base->base.gallivm;
2737 LLVMValueRef args[2];
2738
2739 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2740 args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID);
2741 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2742 ctx->voidt, args, 2, 0);
2743 }
2744
2745 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2746 {
2747 struct si_shader_context *ctx = si_shader_context(bld_base);
2748 struct gallivm_state *gallivm = bld_base->base.gallivm;
2749 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2750 struct si_shader_output_values *outputs = NULL;
2751 int i,j;
2752
2753 assert(!ctx->shader->is_gs_copy_shader);
2754
2755 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2756
2757 /* Vertex color clamping.
2758 *
2759 * This uses a state constant loaded in a user data SGPR and
2760 * an IF statement is added that clamps all colors if the constant
2761 * is true.
2762 */
2763 if (ctx->type == PIPE_SHADER_VERTEX) {
2764 struct lp_build_if_state if_ctx;
2765 LLVMValueRef cond = NULL;
2766 LLVMValueRef addr, val;
2767
2768 for (i = 0; i < info->num_outputs; i++) {
2769 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2770 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2771 continue;
2772
2773 /* We've found a color. */
2774 if (!cond) {
2775 /* The state is in the first bit of the user SGPR. */
2776 cond = LLVMGetParam(ctx->main_fn,
2777 SI_PARAM_VS_STATE_BITS);
2778 cond = LLVMBuildTrunc(gallivm->builder, cond,
2779 ctx->i1, "");
2780 lp_build_if(&if_ctx, gallivm, cond);
2781 }
2782
2783 for (j = 0; j < 4; j++) {
2784 addr = ctx->soa.outputs[i][j];
2785 val = LLVMBuildLoad(gallivm->builder, addr, "");
2786 val = si_llvm_saturate(bld_base, val);
2787 LLVMBuildStore(gallivm->builder, val, addr);
2788 }
2789 }
2790
2791 if (cond)
2792 lp_build_endif(&if_ctx);
2793 }
2794
2795 for (i = 0; i < info->num_outputs; i++) {
2796 outputs[i].name = info->output_semantic_name[i];
2797 outputs[i].sid = info->output_semantic_index[i];
2798
2799 for (j = 0; j < 4; j++)
2800 outputs[i].values[j] =
2801 LLVMBuildLoad(gallivm->builder,
2802 ctx->soa.outputs[i][j],
2803 "");
2804 }
2805
2806 /* Return the primitive ID from the LLVM function. */
2807 ctx->return_value =
2808 LLVMBuildInsertValue(gallivm->builder,
2809 ctx->return_value,
2810 bitcast(bld_base, TGSI_TYPE_FLOAT,
2811 get_primitive_id(bld_base, 0)),
2812 VS_EPILOG_PRIMID_LOC, "");
2813
2814 si_llvm_export_vs(bld_base, outputs, i);
2815 FREE(outputs);
2816 }
2817
2818 struct si_ps_exports {
2819 unsigned num;
2820 LLVMValueRef args[10][9];
2821 };
2822
2823 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
2824 bool writes_samplemask)
2825 {
2826 if (writes_z) {
2827 /* Z needs 32 bits. */
2828 if (writes_samplemask)
2829 return V_028710_SPI_SHADER_32_ABGR;
2830 else if (writes_stencil)
2831 return V_028710_SPI_SHADER_32_GR;
2832 else
2833 return V_028710_SPI_SHADER_32_R;
2834 } else if (writes_stencil || writes_samplemask) {
2835 /* Both stencil and sample mask need only 16 bits. */
2836 return V_028710_SPI_SHADER_UINT16_ABGR;
2837 } else {
2838 return V_028710_SPI_SHADER_ZERO;
2839 }
2840 }
2841
2842 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2843 LLVMValueRef depth, LLVMValueRef stencil,
2844 LLVMValueRef samplemask, struct si_ps_exports *exp)
2845 {
2846 struct si_shader_context *ctx = si_shader_context(bld_base);
2847 struct lp_build_context *base = &bld_base->base;
2848 struct lp_build_context *uint = &bld_base->uint_bld;
2849 LLVMValueRef args[9];
2850 unsigned mask = 0;
2851 unsigned format = si_get_spi_shader_z_format(depth != NULL,
2852 stencil != NULL,
2853 samplemask != NULL);
2854
2855 assert(depth || stencil || samplemask);
2856
2857 args[1] = uint->one; /* whether the EXEC mask is valid */
2858 args[2] = uint->one; /* DONE bit */
2859
2860 /* Specify the target we are exporting */
2861 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2862
2863 args[4] = uint->zero; /* COMP flag */
2864 args[5] = base->undef; /* R, depth */
2865 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2866 args[7] = base->undef; /* B, sample mask */
2867 args[8] = base->undef; /* A, alpha to mask */
2868
2869 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
2870 assert(!depth);
2871 args[4] = uint->one; /* COMPR flag */
2872
2873 if (stencil) {
2874 /* Stencil should be in X[23:16]. */
2875 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
2876 stencil = LLVMBuildShl(base->gallivm->builder, stencil,
2877 LLVMConstInt(ctx->i32, 16, 0), "");
2878 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
2879 mask |= 0x3;
2880 }
2881 if (samplemask) {
2882 /* SampleMask should be in Y[15:0]. */
2883 args[6] = samplemask;
2884 mask |= 0xc;
2885 }
2886 } else {
2887 if (depth) {
2888 args[5] = depth;
2889 mask |= 0x1;
2890 }
2891 if (stencil) {
2892 args[6] = stencil;
2893 mask |= 0x2;
2894 }
2895 if (samplemask) {
2896 args[7] = samplemask;
2897 mask |= 0x4;
2898 }
2899 }
2900
2901 /* SI (except OLAND and HAINAN) has a bug that it only looks
2902 * at the X writemask component. */
2903 if (ctx->screen->b.chip_class == SI &&
2904 ctx->screen->b.family != CHIP_OLAND &&
2905 ctx->screen->b.family != CHIP_HAINAN)
2906 mask |= 0x1;
2907
2908 /* Specify which components to enable */
2909 args[0] = lp_build_const_int32(base->gallivm, mask);
2910
2911 memcpy(exp->args[exp->num++], args, sizeof(args));
2912 }
2913
2914 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2915 LLVMValueRef *color, unsigned index,
2916 unsigned samplemask_param,
2917 bool is_last, struct si_ps_exports *exp)
2918 {
2919 struct si_shader_context *ctx = si_shader_context(bld_base);
2920 struct lp_build_context *base = &bld_base->base;
2921 int i;
2922
2923 /* Clamp color */
2924 if (ctx->shader->key.part.ps.epilog.clamp_color)
2925 for (i = 0; i < 4; i++)
2926 color[i] = si_llvm_saturate(bld_base, color[i]);
2927
2928 /* Alpha to one */
2929 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
2930 color[3] = base->one;
2931
2932 /* Alpha test */
2933 if (index == 0 &&
2934 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2935 si_alpha_test(bld_base, color[3]);
2936
2937 /* Line & polygon smoothing */
2938 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
2939 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
2940 samplemask_param);
2941
2942 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2943 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
2944 LLVMValueRef args[8][9];
2945 int c, last = -1;
2946
2947 /* Get the export arguments, also find out what the last one is. */
2948 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2949 si_llvm_init_export_args(bld_base, color,
2950 V_008DFC_SQ_EXP_MRT + c, args[c]);
2951 if (args[c][0] != bld_base->uint_bld.zero)
2952 last = c;
2953 }
2954
2955 /* Emit all exports. */
2956 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2957 if (is_last && last == c) {
2958 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2959 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
2960 } else if (args[c][0] == bld_base->uint_bld.zero)
2961 continue; /* unnecessary NULL export */
2962
2963 memcpy(exp->args[exp->num++], args[c], sizeof(args[c]));
2964 }
2965 } else {
2966 LLVMValueRef args[9];
2967
2968 /* Export */
2969 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2970 args);
2971 if (is_last) {
2972 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2973 args[2] = bld_base->uint_bld.one; /* DONE bit */
2974 } else if (args[0] == bld_base->uint_bld.zero)
2975 return; /* unnecessary NULL export */
2976
2977 memcpy(exp->args[exp->num++], args, sizeof(args));
2978 }
2979 }
2980
2981 static void si_emit_ps_exports(struct si_shader_context *ctx,
2982 struct si_ps_exports *exp)
2983 {
2984 for (unsigned i = 0; i < exp->num; i++)
2985 lp_build_intrinsic(ctx->gallivm.builder,
2986 "llvm.SI.export", ctx->voidt,
2987 exp->args[i], 9, 0);
2988 }
2989
2990 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2991 {
2992 struct si_shader_context *ctx = si_shader_context(bld_base);
2993 struct lp_build_context *base = &bld_base->base;
2994 struct lp_build_context *uint = &bld_base->uint_bld;
2995 LLVMValueRef args[9];
2996
2997 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
2998 args[1] = uint->one; /* whether the EXEC mask is valid */
2999 args[2] = uint->one; /* DONE bit */
3000 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
3001 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
3002 args[5] = base->undef; /* R */
3003 args[6] = base->undef; /* G */
3004 args[7] = base->undef; /* B */
3005 args[8] = base->undef; /* A */
3006
3007 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
3008 ctx->voidt, args, 9, 0);
3009 }
3010
3011 /**
3012 * Return PS outputs in this order:
3013 *
3014 * v[0:3] = color0.xyzw
3015 * v[4:7] = color1.xyzw
3016 * ...
3017 * vN+0 = Depth
3018 * vN+1 = Stencil
3019 * vN+2 = SampleMask
3020 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3021 *
3022 * The alpha-ref SGPR is returned via its original location.
3023 */
3024 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
3025 {
3026 struct si_shader_context *ctx = si_shader_context(bld_base);
3027 struct si_shader *shader = ctx->shader;
3028 struct lp_build_context *base = &bld_base->base;
3029 struct tgsi_shader_info *info = &shader->selector->info;
3030 LLVMBuilderRef builder = base->gallivm->builder;
3031 unsigned i, j, first_vgpr, vgpr;
3032
3033 LLVMValueRef color[8][4] = {};
3034 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3035 LLVMValueRef ret;
3036
3037 /* Read the output values. */
3038 for (i = 0; i < info->num_outputs; i++) {
3039 unsigned semantic_name = info->output_semantic_name[i];
3040 unsigned semantic_index = info->output_semantic_index[i];
3041
3042 switch (semantic_name) {
3043 case TGSI_SEMANTIC_COLOR:
3044 assert(semantic_index < 8);
3045 for (j = 0; j < 4; j++) {
3046 LLVMValueRef ptr = ctx->soa.outputs[i][j];
3047 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3048 color[semantic_index][j] = result;
3049 }
3050 break;
3051 case TGSI_SEMANTIC_POSITION:
3052 depth = LLVMBuildLoad(builder,
3053 ctx->soa.outputs[i][2], "");
3054 break;
3055 case TGSI_SEMANTIC_STENCIL:
3056 stencil = LLVMBuildLoad(builder,
3057 ctx->soa.outputs[i][1], "");
3058 break;
3059 case TGSI_SEMANTIC_SAMPLEMASK:
3060 samplemask = LLVMBuildLoad(builder,
3061 ctx->soa.outputs[i][0], "");
3062 break;
3063 default:
3064 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3065 semantic_name);
3066 }
3067 }
3068
3069 /* Fill the return structure. */
3070 ret = ctx->return_value;
3071
3072 /* Set SGPRs. */
3073 ret = LLVMBuildInsertValue(builder, ret,
3074 bitcast(bld_base, TGSI_TYPE_SIGNED,
3075 LLVMGetParam(ctx->main_fn,
3076 SI_PARAM_ALPHA_REF)),
3077 SI_SGPR_ALPHA_REF, "");
3078
3079 /* Set VGPRs */
3080 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3081 for (i = 0; i < ARRAY_SIZE(color); i++) {
3082 if (!color[i][0])
3083 continue;
3084
3085 for (j = 0; j < 4; j++)
3086 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3087 }
3088 if (depth)
3089 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3090 if (stencil)
3091 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3092 if (samplemask)
3093 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3094
3095 /* Add the input sample mask for smoothing at the end. */
3096 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3097 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3098 ret = LLVMBuildInsertValue(builder, ret,
3099 LLVMGetParam(ctx->main_fn,
3100 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3101
3102 ctx->return_value = ret;
3103 }
3104
3105 /**
3106 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3107 * buffer in number of elements and return it as an i32.
3108 */
3109 static LLVMValueRef get_buffer_size(
3110 struct lp_build_tgsi_context *bld_base,
3111 LLVMValueRef descriptor)
3112 {
3113 struct si_shader_context *ctx = si_shader_context(bld_base);
3114 struct gallivm_state *gallivm = bld_base->base.gallivm;
3115 LLVMBuilderRef builder = gallivm->builder;
3116 LLVMValueRef size =
3117 LLVMBuildExtractElement(builder, descriptor,
3118 lp_build_const_int32(gallivm, 2), "");
3119
3120 if (ctx->screen->b.chip_class >= VI) {
3121 /* On VI, the descriptor contains the size in bytes,
3122 * but TXQ must return the size in elements.
3123 * The stride is always non-zero for resources using TXQ.
3124 */
3125 LLVMValueRef stride =
3126 LLVMBuildExtractElement(builder, descriptor,
3127 lp_build_const_int32(gallivm, 1), "");
3128 stride = LLVMBuildLShr(builder, stride,
3129 lp_build_const_int32(gallivm, 16), "");
3130 stride = LLVMBuildAnd(builder, stride,
3131 lp_build_const_int32(gallivm, 0x3FFF), "");
3132
3133 size = LLVMBuildUDiv(builder, size, stride, "");
3134 }
3135
3136 return size;
3137 }
3138
3139 /**
3140 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
3141 * intrinsic names).
3142 */
3143 static void build_type_name_for_intr(
3144 LLVMTypeRef type,
3145 char *buf, unsigned bufsize)
3146 {
3147 LLVMTypeRef elem_type = type;
3148
3149 assert(bufsize >= 8);
3150
3151 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
3152 int ret = snprintf(buf, bufsize, "v%u",
3153 LLVMGetVectorSize(type));
3154 if (ret < 0) {
3155 char *type_name = LLVMPrintTypeToString(type);
3156 fprintf(stderr, "Error building type name for: %s\n",
3157 type_name);
3158 return;
3159 }
3160 elem_type = LLVMGetElementType(type);
3161 buf += ret;
3162 bufsize -= ret;
3163 }
3164 switch (LLVMGetTypeKind(elem_type)) {
3165 default: break;
3166 case LLVMIntegerTypeKind:
3167 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
3168 break;
3169 case LLVMFloatTypeKind:
3170 snprintf(buf, bufsize, "f32");
3171 break;
3172 case LLVMDoubleTypeKind:
3173 snprintf(buf, bufsize, "f64");
3174 break;
3175 }
3176 }
3177
3178 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3179 struct lp_build_tgsi_context *bld_base,
3180 struct lp_build_emit_data *emit_data);
3181
3182 /* Prevent optimizations (at least of memory accesses) across the current
3183 * point in the program by emitting empty inline assembly that is marked as
3184 * having side effects.
3185 */
3186 static void emit_optimization_barrier(struct si_shader_context *ctx)
3187 {
3188 LLVMBuilderRef builder = ctx->gallivm.builder;
3189 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3190 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
3191 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3192 }
3193
3194 static void emit_waitcnt(struct si_shader_context *ctx)
3195 {
3196 struct gallivm_state *gallivm = &ctx->gallivm;
3197 LLVMBuilderRef builder = gallivm->builder;
3198 LLVMValueRef args[1] = {
3199 lp_build_const_int32(gallivm, 0xf70)
3200 };
3201 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3202 ctx->voidt, args, 1, 0);
3203 }
3204
3205 static void membar_emit(
3206 const struct lp_build_tgsi_action *action,
3207 struct lp_build_tgsi_context *bld_base,
3208 struct lp_build_emit_data *emit_data)
3209 {
3210 struct si_shader_context *ctx = si_shader_context(bld_base);
3211
3212 emit_waitcnt(ctx);
3213 }
3214
3215 static LLVMValueRef
3216 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3217 const struct tgsi_full_src_register *reg)
3218 {
3219 LLVMValueRef index;
3220 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3221 SI_PARAM_SHADER_BUFFERS);
3222
3223 if (!reg->Register.Indirect)
3224 index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
3225 else
3226 index = get_bounded_indirect_index(ctx, &reg->Indirect,
3227 reg->Register.Index,
3228 SI_NUM_SHADER_BUFFERS);
3229
3230 return build_indexed_load_const(ctx, rsrc_ptr, index);
3231 }
3232
3233 static bool tgsi_is_array_sampler(unsigned target)
3234 {
3235 return target == TGSI_TEXTURE_1D_ARRAY ||
3236 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3237 target == TGSI_TEXTURE_2D_ARRAY ||
3238 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3239 target == TGSI_TEXTURE_CUBE_ARRAY ||
3240 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3241 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3242 }
3243
3244 static bool tgsi_is_array_image(unsigned target)
3245 {
3246 return target == TGSI_TEXTURE_3D ||
3247 target == TGSI_TEXTURE_CUBE ||
3248 target == TGSI_TEXTURE_1D_ARRAY ||
3249 target == TGSI_TEXTURE_2D_ARRAY ||
3250 target == TGSI_TEXTURE_CUBE_ARRAY ||
3251 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3252 }
3253
3254 /**
3255 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3256 *
3257 * At least on Tonga, executing image stores on images with DCC enabled and
3258 * non-trivial can eventually lead to lockups. This can occur when an
3259 * application binds an image as read-only but then uses a shader that writes
3260 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3261 * program termination) in this case, but it doesn't cost much to be a bit
3262 * nicer: disabling DCC in the shader still leads to undefined results but
3263 * avoids the lockup.
3264 */
3265 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3266 LLVMValueRef rsrc)
3267 {
3268 if (ctx->screen->b.chip_class <= CIK) {
3269 return rsrc;
3270 } else {
3271 LLVMBuilderRef builder = ctx->gallivm.builder;
3272 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3273 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3274 LLVMValueRef tmp;
3275
3276 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3277 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3278 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3279 }
3280 }
3281
3282 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3283 {
3284 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3285 CONST_ADDR_SPACE);
3286 }
3287
3288 /**
3289 * Load the resource descriptor for \p image.
3290 */
3291 static void
3292 image_fetch_rsrc(
3293 struct lp_build_tgsi_context *bld_base,
3294 const struct tgsi_full_src_register *image,
3295 bool is_store, unsigned target,
3296 LLVMValueRef *rsrc)
3297 {
3298 struct si_shader_context *ctx = si_shader_context(bld_base);
3299 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3300 SI_PARAM_IMAGES);
3301 LLVMValueRef index, tmp;
3302 bool dcc_off = target != TGSI_TEXTURE_BUFFER && is_store;
3303
3304 assert(image->Register.File == TGSI_FILE_IMAGE);
3305
3306 if (!image->Register.Indirect) {
3307 const struct tgsi_shader_info *info = bld_base->info;
3308
3309 index = LLVMConstInt(ctx->i32, image->Register.Index, 0);
3310
3311 if (info->images_writemask & (1 << image->Register.Index) &&
3312 target != TGSI_TEXTURE_BUFFER)
3313 dcc_off = true;
3314 } else {
3315 /* From the GL_ARB_shader_image_load_store extension spec:
3316 *
3317 * If a shader performs an image load, store, or atomic
3318 * operation using an image variable declared as an array,
3319 * and if the index used to select an individual element is
3320 * negative or greater than or equal to the size of the
3321 * array, the results of the operation are undefined but may
3322 * not lead to termination.
3323 */
3324 index = get_bounded_indirect_index(ctx, &image->Indirect,
3325 image->Register.Index,
3326 SI_NUM_IMAGES);
3327 }
3328
3329 if (target == TGSI_TEXTURE_BUFFER) {
3330 LLVMBuilderRef builder = ctx->gallivm.builder;
3331
3332 rsrc_ptr = LLVMBuildPointerCast(builder, rsrc_ptr,
3333 const_array(ctx->v4i32, 0), "");
3334 index = LLVMBuildMul(builder, index,
3335 LLVMConstInt(ctx->i32, 2, 0), "");
3336 index = LLVMBuildAdd(builder, index,
3337 LLVMConstInt(ctx->i32, 1, 0), "");
3338 *rsrc = build_indexed_load_const(ctx, rsrc_ptr, index);
3339 return;
3340 }
3341
3342 tmp = build_indexed_load_const(ctx, rsrc_ptr, index);
3343 if (dcc_off)
3344 tmp = force_dcc_off(ctx, tmp);
3345 *rsrc = tmp;
3346 }
3347
3348 static LLVMValueRef image_fetch_coords(
3349 struct lp_build_tgsi_context *bld_base,
3350 const struct tgsi_full_instruction *inst,
3351 unsigned src)
3352 {
3353 struct gallivm_state *gallivm = bld_base->base.gallivm;
3354 LLVMBuilderRef builder = gallivm->builder;
3355 unsigned target = inst->Memory.Texture;
3356 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3357 LLVMValueRef coords[4];
3358 LLVMValueRef tmp;
3359 int chan;
3360
3361 for (chan = 0; chan < num_coords; ++chan) {
3362 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3363 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3364 coords[chan] = tmp;
3365 }
3366
3367 if (num_coords == 1)
3368 return coords[0];
3369
3370 if (num_coords == 3) {
3371 /* LLVM has difficulties lowering 3-element vectors. */
3372 coords[3] = bld_base->uint_bld.undef;
3373 num_coords = 4;
3374 }
3375
3376 return lp_build_gather_values(gallivm, coords, num_coords);
3377 }
3378
3379 /**
3380 * Append the extra mode bits that are used by image load and store.
3381 */
3382 static void image_append_args(
3383 struct si_shader_context *ctx,
3384 struct lp_build_emit_data * emit_data,
3385 unsigned target,
3386 bool atomic,
3387 bool force_glc)
3388 {
3389 const struct tgsi_full_instruction *inst = emit_data->inst;
3390 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3391 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3392 LLVMValueRef r128 = i1false;
3393 LLVMValueRef da = tgsi_is_array_image(target) ? i1true : i1false;
3394 LLVMValueRef glc =
3395 force_glc ||
3396 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3397 i1true : i1false;
3398 LLVMValueRef slc = i1false;
3399 LLVMValueRef lwe = i1false;
3400
3401 if (atomic || (HAVE_LLVM <= 0x0309)) {
3402 emit_data->args[emit_data->arg_count++] = r128;
3403 emit_data->args[emit_data->arg_count++] = da;
3404 if (!atomic) {
3405 emit_data->args[emit_data->arg_count++] = glc;
3406 }
3407 emit_data->args[emit_data->arg_count++] = slc;
3408 return;
3409 }
3410
3411 /* HAVE_LLVM >= 0x0400 */
3412 emit_data->args[emit_data->arg_count++] = glc;
3413 emit_data->args[emit_data->arg_count++] = slc;
3414 emit_data->args[emit_data->arg_count++] = lwe;
3415 emit_data->args[emit_data->arg_count++] = da;
3416 }
3417
3418 /**
3419 * Append the resource and indexing arguments for buffer intrinsics.
3420 *
3421 * \param rsrc the v4i32 buffer resource
3422 * \param index index into the buffer (stride-based)
3423 * \param offset byte offset into the buffer
3424 */
3425 static void buffer_append_args(
3426 struct si_shader_context *ctx,
3427 struct lp_build_emit_data *emit_data,
3428 LLVMValueRef rsrc,
3429 LLVMValueRef index,
3430 LLVMValueRef offset,
3431 bool atomic,
3432 bool force_glc)
3433 {
3434 const struct tgsi_full_instruction *inst = emit_data->inst;
3435 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3436 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3437
3438 emit_data->args[emit_data->arg_count++] = rsrc;
3439 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3440 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3441 if (!atomic) {
3442 emit_data->args[emit_data->arg_count++] =
3443 force_glc ||
3444 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3445 i1true : i1false; /* glc */
3446 }
3447 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3448 }
3449
3450 static void load_fetch_args(
3451 struct lp_build_tgsi_context * bld_base,
3452 struct lp_build_emit_data * emit_data)
3453 {
3454 struct si_shader_context *ctx = si_shader_context(bld_base);
3455 struct gallivm_state *gallivm = bld_base->base.gallivm;
3456 const struct tgsi_full_instruction * inst = emit_data->inst;
3457 unsigned target = inst->Memory.Texture;
3458 LLVMValueRef rsrc;
3459
3460 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3461
3462 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3463 LLVMBuilderRef builder = gallivm->builder;
3464 LLVMValueRef offset;
3465 LLVMValueRef tmp;
3466
3467 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3468
3469 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3470 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3471
3472 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3473 offset, false, false);
3474 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3475 LLVMValueRef coords;
3476
3477 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
3478 coords = image_fetch_coords(bld_base, inst, 1);
3479
3480 if (target == TGSI_TEXTURE_BUFFER) {
3481 buffer_append_args(ctx, emit_data, rsrc, coords,
3482 bld_base->uint_bld.zero, false, false);
3483 } else {
3484 emit_data->args[0] = coords;
3485 emit_data->args[1] = rsrc;
3486 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3487 emit_data->arg_count = 3;
3488
3489 image_append_args(ctx, emit_data, target, false, false);
3490 }
3491 }
3492 }
3493
3494 static void load_emit_buffer(struct si_shader_context *ctx,
3495 struct lp_build_emit_data *emit_data)
3496 {
3497 const struct tgsi_full_instruction *inst = emit_data->inst;
3498 struct gallivm_state *gallivm = &ctx->gallivm;
3499 LLVMBuilderRef builder = gallivm->builder;
3500 uint writemask = inst->Dst[0].Register.WriteMask;
3501 uint count = util_last_bit(writemask);
3502 const char *intrinsic_name;
3503 LLVMTypeRef dst_type;
3504
3505 switch (count) {
3506 case 1:
3507 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3508 dst_type = ctx->f32;
3509 break;
3510 case 2:
3511 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3512 dst_type = LLVMVectorType(ctx->f32, 2);
3513 break;
3514 default: // 3 & 4
3515 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3516 dst_type = ctx->v4f32;
3517 count = 4;
3518 }
3519
3520 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3521 builder, intrinsic_name, dst_type,
3522 emit_data->args, emit_data->arg_count,
3523 LP_FUNC_ATTR_READONLY);
3524 }
3525
3526 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3527 const struct tgsi_full_instruction *inst,
3528 LLVMTypeRef type, int arg)
3529 {
3530 struct gallivm_state *gallivm = &ctx->gallivm;
3531 LLVMBuilderRef builder = gallivm->builder;
3532 LLVMValueRef offset, ptr;
3533 int addr_space;
3534
3535 offset = lp_build_emit_fetch(&ctx->soa.bld_base, inst, arg, 0);
3536 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3537
3538 ptr = ctx->shared_memory;
3539 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3540 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3541 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3542
3543 return ptr;
3544 }
3545
3546 static void load_emit_memory(
3547 struct si_shader_context *ctx,
3548 struct lp_build_emit_data *emit_data)
3549 {
3550 const struct tgsi_full_instruction *inst = emit_data->inst;
3551 struct lp_build_context *base = &ctx->soa.bld_base.base;
3552 struct gallivm_state *gallivm = &ctx->gallivm;
3553 LLVMBuilderRef builder = gallivm->builder;
3554 unsigned writemask = inst->Dst[0].Register.WriteMask;
3555 LLVMValueRef channels[4], ptr, derived_ptr, index;
3556 int chan;
3557
3558 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3559
3560 for (chan = 0; chan < 4; ++chan) {
3561 if (!(writemask & (1 << chan))) {
3562 channels[chan] = LLVMGetUndef(base->elem_type);
3563 continue;
3564 }
3565
3566 index = lp_build_const_int32(gallivm, chan);
3567 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3568 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3569 }
3570 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3571 }
3572
3573 static void get_image_intr_name(const char *base_name,
3574 LLVMTypeRef data_type,
3575 LLVMTypeRef coords_type,
3576 LLVMTypeRef rsrc_type,
3577 char *out_name, unsigned out_len)
3578 {
3579 char coords_type_name[8];
3580
3581 build_type_name_for_intr(coords_type, coords_type_name,
3582 sizeof(coords_type_name));
3583
3584 if (HAVE_LLVM <= 0x0309) {
3585 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
3586 } else {
3587 char data_type_name[8];
3588 char rsrc_type_name[8];
3589
3590 build_type_name_for_intr(data_type, data_type_name,
3591 sizeof(data_type_name));
3592 build_type_name_for_intr(rsrc_type, rsrc_type_name,
3593 sizeof(rsrc_type_name));
3594 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
3595 data_type_name, coords_type_name, rsrc_type_name);
3596 }
3597 }
3598
3599 static void load_emit(
3600 const struct lp_build_tgsi_action *action,
3601 struct lp_build_tgsi_context *bld_base,
3602 struct lp_build_emit_data *emit_data)
3603 {
3604 struct si_shader_context *ctx = si_shader_context(bld_base);
3605 struct gallivm_state *gallivm = bld_base->base.gallivm;
3606 LLVMBuilderRef builder = gallivm->builder;
3607 const struct tgsi_full_instruction * inst = emit_data->inst;
3608 char intrinsic_name[64];
3609
3610 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3611 load_emit_memory(ctx, emit_data);
3612 return;
3613 }
3614
3615 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3616 emit_waitcnt(ctx);
3617
3618 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3619 load_emit_buffer(ctx, emit_data);
3620 return;
3621 }
3622
3623 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3624 emit_data->output[emit_data->chan] =
3625 lp_build_intrinsic(
3626 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3627 emit_data->args, emit_data->arg_count,
3628 LP_FUNC_ATTR_READONLY);
3629 } else {
3630 get_image_intr_name("llvm.amdgcn.image.load",
3631 emit_data->dst_type, /* vdata */
3632 LLVMTypeOf(emit_data->args[0]), /* coords */
3633 LLVMTypeOf(emit_data->args[1]), /* rsrc */
3634 intrinsic_name, sizeof(intrinsic_name));
3635
3636 emit_data->output[emit_data->chan] =
3637 lp_build_intrinsic(
3638 builder, intrinsic_name, emit_data->dst_type,
3639 emit_data->args, emit_data->arg_count,
3640 LP_FUNC_ATTR_READONLY);
3641 }
3642 }
3643
3644 static void store_fetch_args(
3645 struct lp_build_tgsi_context * bld_base,
3646 struct lp_build_emit_data * emit_data)
3647 {
3648 struct si_shader_context *ctx = si_shader_context(bld_base);
3649 struct gallivm_state *gallivm = bld_base->base.gallivm;
3650 LLVMBuilderRef builder = gallivm->builder;
3651 const struct tgsi_full_instruction * inst = emit_data->inst;
3652 struct tgsi_full_src_register memory;
3653 LLVMValueRef chans[4];
3654 LLVMValueRef data;
3655 LLVMValueRef rsrc;
3656 unsigned chan;
3657
3658 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3659
3660 for (chan = 0; chan < 4; ++chan) {
3661 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3662 }
3663 data = lp_build_gather_values(gallivm, chans, 4);
3664
3665 emit_data->args[emit_data->arg_count++] = data;
3666
3667 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3668
3669 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3670 LLVMValueRef offset;
3671 LLVMValueRef tmp;
3672
3673 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3674
3675 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3676 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3677
3678 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3679 offset, false, false);
3680 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3681 unsigned target = inst->Memory.Texture;
3682 LLVMValueRef coords;
3683
3684 /* 8bit/16bit TC L1 write corruption bug on SI.
3685 * All store opcodes not aligned to a dword are affected.
3686 *
3687 * The only way to get unaligned stores in radeonsi is through
3688 * shader images.
3689 */
3690 bool force_glc = ctx->screen->b.chip_class == SI;
3691
3692 coords = image_fetch_coords(bld_base, inst, 0);
3693
3694 if (target == TGSI_TEXTURE_BUFFER) {
3695 image_fetch_rsrc(bld_base, &memory, true, target, &rsrc);
3696 buffer_append_args(ctx, emit_data, rsrc, coords,
3697 bld_base->uint_bld.zero, false, force_glc);
3698 } else {
3699 emit_data->args[1] = coords;
3700 image_fetch_rsrc(bld_base, &memory, true, target,
3701 &emit_data->args[2]);
3702 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3703 emit_data->arg_count = 4;
3704
3705 image_append_args(ctx, emit_data, target, false, force_glc);
3706 }
3707 }
3708 }
3709
3710 static void store_emit_buffer(
3711 struct si_shader_context *ctx,
3712 struct lp_build_emit_data *emit_data)
3713 {
3714 const struct tgsi_full_instruction *inst = emit_data->inst;
3715 struct gallivm_state *gallivm = &ctx->gallivm;
3716 LLVMBuilderRef builder = gallivm->builder;
3717 struct lp_build_context *uint_bld = &ctx->soa.bld_base.uint_bld;
3718 LLVMValueRef base_data = emit_data->args[0];
3719 LLVMValueRef base_offset = emit_data->args[3];
3720 unsigned writemask = inst->Dst[0].Register.WriteMask;
3721
3722 while (writemask) {
3723 int start, count;
3724 const char *intrinsic_name;
3725 LLVMValueRef data;
3726 LLVMValueRef offset;
3727 LLVMValueRef tmp;
3728
3729 u_bit_scan_consecutive_range(&writemask, &start, &count);
3730
3731 /* Due to an LLVM limitation, split 3-element writes
3732 * into a 2-element and a 1-element write. */
3733 if (count == 3) {
3734 writemask |= 1 << (start + 2);
3735 count = 2;
3736 }
3737
3738 if (count == 4) {
3739 data = base_data;
3740 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3741 } else if (count == 2) {
3742 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3743
3744 tmp = LLVMBuildExtractElement(
3745 builder, base_data,
3746 lp_build_const_int32(gallivm, start), "");
3747 data = LLVMBuildInsertElement(
3748 builder, LLVMGetUndef(v2f32), tmp,
3749 uint_bld->zero, "");
3750
3751 tmp = LLVMBuildExtractElement(
3752 builder, base_data,
3753 lp_build_const_int32(gallivm, start + 1), "");
3754 data = LLVMBuildInsertElement(
3755 builder, data, tmp, uint_bld->one, "");
3756
3757 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3758 } else {
3759 assert(count == 1);
3760 data = LLVMBuildExtractElement(
3761 builder, base_data,
3762 lp_build_const_int32(gallivm, start), "");
3763 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3764 }
3765
3766 offset = base_offset;
3767 if (start != 0) {
3768 offset = LLVMBuildAdd(
3769 builder, offset,
3770 lp_build_const_int32(gallivm, start * 4), "");
3771 }
3772
3773 emit_data->args[0] = data;
3774 emit_data->args[3] = offset;
3775
3776 lp_build_intrinsic(
3777 builder, intrinsic_name, emit_data->dst_type,
3778 emit_data->args, emit_data->arg_count, 0);
3779 }
3780 }
3781
3782 static void store_emit_memory(
3783 struct si_shader_context *ctx,
3784 struct lp_build_emit_data *emit_data)
3785 {
3786 const struct tgsi_full_instruction *inst = emit_data->inst;
3787 struct gallivm_state *gallivm = &ctx->gallivm;
3788 struct lp_build_context *base = &ctx->soa.bld_base.base;
3789 LLVMBuilderRef builder = gallivm->builder;
3790 unsigned writemask = inst->Dst[0].Register.WriteMask;
3791 LLVMValueRef ptr, derived_ptr, data, index;
3792 int chan;
3793
3794 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3795
3796 for (chan = 0; chan < 4; ++chan) {
3797 if (!(writemask & (1 << chan))) {
3798 continue;
3799 }
3800 data = lp_build_emit_fetch(&ctx->soa.bld_base, inst, 1, chan);
3801 index = lp_build_const_int32(gallivm, chan);
3802 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3803 LLVMBuildStore(builder, data, derived_ptr);
3804 }
3805 }
3806
3807 static void store_emit(
3808 const struct lp_build_tgsi_action *action,
3809 struct lp_build_tgsi_context *bld_base,
3810 struct lp_build_emit_data *emit_data)
3811 {
3812 struct si_shader_context *ctx = si_shader_context(bld_base);
3813 struct gallivm_state *gallivm = bld_base->base.gallivm;
3814 LLVMBuilderRef builder = gallivm->builder;
3815 const struct tgsi_full_instruction * inst = emit_data->inst;
3816 unsigned target = inst->Memory.Texture;
3817 char intrinsic_name[64];
3818
3819 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3820 store_emit_memory(ctx, emit_data);
3821 return;
3822 }
3823
3824 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3825 emit_waitcnt(ctx);
3826
3827 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3828 store_emit_buffer(ctx, emit_data);
3829 return;
3830 }
3831
3832 if (target == TGSI_TEXTURE_BUFFER) {
3833 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3834 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3835 emit_data->dst_type, emit_data->args,
3836 emit_data->arg_count, 0);
3837 } else {
3838 get_image_intr_name("llvm.amdgcn.image.store",
3839 LLVMTypeOf(emit_data->args[0]), /* vdata */
3840 LLVMTypeOf(emit_data->args[1]), /* coords */
3841 LLVMTypeOf(emit_data->args[2]), /* rsrc */
3842 intrinsic_name, sizeof(intrinsic_name));
3843
3844 emit_data->output[emit_data->chan] =
3845 lp_build_intrinsic(
3846 builder, intrinsic_name, emit_data->dst_type,
3847 emit_data->args, emit_data->arg_count, 0);
3848 }
3849 }
3850
3851 static void atomic_fetch_args(
3852 struct lp_build_tgsi_context * bld_base,
3853 struct lp_build_emit_data * emit_data)
3854 {
3855 struct si_shader_context *ctx = si_shader_context(bld_base);
3856 struct gallivm_state *gallivm = bld_base->base.gallivm;
3857 LLVMBuilderRef builder = gallivm->builder;
3858 const struct tgsi_full_instruction * inst = emit_data->inst;
3859 LLVMValueRef data1, data2;
3860 LLVMValueRef rsrc;
3861 LLVMValueRef tmp;
3862
3863 emit_data->dst_type = bld_base->base.elem_type;
3864
3865 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
3866 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3867
3868 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3869 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
3870 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3871 }
3872
3873 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3874 * of arguments, which is reversed relative to TGSI (and GLSL)
3875 */
3876 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3877 emit_data->args[emit_data->arg_count++] = data2;
3878 emit_data->args[emit_data->arg_count++] = data1;
3879
3880 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3881 LLVMValueRef offset;
3882
3883 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3884
3885 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3886 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3887
3888 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3889 offset, true, false);
3890 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3891 unsigned target = inst->Memory.Texture;
3892 LLVMValueRef coords;
3893
3894 image_fetch_rsrc(bld_base, &inst->Src[0], true, target, &rsrc);
3895 coords = image_fetch_coords(bld_base, inst, 1);
3896
3897 if (target == TGSI_TEXTURE_BUFFER) {
3898 buffer_append_args(ctx, emit_data, rsrc, coords,
3899 bld_base->uint_bld.zero, true, false);
3900 } else {
3901 emit_data->args[emit_data->arg_count++] = coords;
3902 emit_data->args[emit_data->arg_count++] = rsrc;
3903
3904 image_append_args(ctx, emit_data, target, true, false);
3905 }
3906 }
3907 }
3908
3909 static void atomic_emit_memory(struct si_shader_context *ctx,
3910 struct lp_build_emit_data *emit_data) {
3911 struct gallivm_state *gallivm = &ctx->gallivm;
3912 LLVMBuilderRef builder = gallivm->builder;
3913 const struct tgsi_full_instruction * inst = emit_data->inst;
3914 LLVMValueRef ptr, result, arg;
3915
3916 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
3917
3918 arg = lp_build_emit_fetch(&ctx->soa.bld_base, inst, 2, 0);
3919 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
3920
3921 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3922 LLVMValueRef new_data;
3923 new_data = lp_build_emit_fetch(&ctx->soa.bld_base,
3924 inst, 3, 0);
3925
3926 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
3927
3928 #if HAVE_LLVM >= 0x309
3929 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
3930 LLVMAtomicOrderingSequentiallyConsistent,
3931 LLVMAtomicOrderingSequentiallyConsistent,
3932 false);
3933 #endif
3934
3935 result = LLVMBuildExtractValue(builder, result, 0, "");
3936 } else {
3937 LLVMAtomicRMWBinOp op;
3938
3939 switch(inst->Instruction.Opcode) {
3940 case TGSI_OPCODE_ATOMUADD:
3941 op = LLVMAtomicRMWBinOpAdd;
3942 break;
3943 case TGSI_OPCODE_ATOMXCHG:
3944 op = LLVMAtomicRMWBinOpXchg;
3945 break;
3946 case TGSI_OPCODE_ATOMAND:
3947 op = LLVMAtomicRMWBinOpAnd;
3948 break;
3949 case TGSI_OPCODE_ATOMOR:
3950 op = LLVMAtomicRMWBinOpOr;
3951 break;
3952 case TGSI_OPCODE_ATOMXOR:
3953 op = LLVMAtomicRMWBinOpXor;
3954 break;
3955 case TGSI_OPCODE_ATOMUMIN:
3956 op = LLVMAtomicRMWBinOpUMin;
3957 break;
3958 case TGSI_OPCODE_ATOMUMAX:
3959 op = LLVMAtomicRMWBinOpUMax;
3960 break;
3961 case TGSI_OPCODE_ATOMIMIN:
3962 op = LLVMAtomicRMWBinOpMin;
3963 break;
3964 case TGSI_OPCODE_ATOMIMAX:
3965 op = LLVMAtomicRMWBinOpMax;
3966 break;
3967 default:
3968 unreachable("unknown atomic opcode");
3969 }
3970
3971 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
3972 LLVMAtomicOrderingSequentiallyConsistent,
3973 false);
3974 }
3975 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
3976 }
3977
3978 static void atomic_emit(
3979 const struct lp_build_tgsi_action *action,
3980 struct lp_build_tgsi_context *bld_base,
3981 struct lp_build_emit_data *emit_data)
3982 {
3983 struct si_shader_context *ctx = si_shader_context(bld_base);
3984 struct gallivm_state *gallivm = bld_base->base.gallivm;
3985 LLVMBuilderRef builder = gallivm->builder;
3986 const struct tgsi_full_instruction * inst = emit_data->inst;
3987 char intrinsic_name[40];
3988 LLVMValueRef tmp;
3989
3990 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3991 atomic_emit_memory(ctx, emit_data);
3992 return;
3993 }
3994
3995 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
3996 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3997 snprintf(intrinsic_name, sizeof(intrinsic_name),
3998 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
3999 } else {
4000 LLVMValueRef coords;
4001 char coords_type[8];
4002
4003 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4004 coords = emit_data->args[2];
4005 else
4006 coords = emit_data->args[1];
4007
4008 build_type_name_for_intr(LLVMTypeOf(coords), coords_type, sizeof(coords_type));
4009 snprintf(intrinsic_name, sizeof(intrinsic_name),
4010 "llvm.amdgcn.image.atomic.%s.%s",
4011 action->intr_name, coords_type);
4012 }
4013
4014 tmp = lp_build_intrinsic(
4015 builder, intrinsic_name, bld_base->uint_bld.elem_type,
4016 emit_data->args, emit_data->arg_count, 0);
4017 emit_data->output[emit_data->chan] =
4018 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
4019 }
4020
4021 static void resq_fetch_args(
4022 struct lp_build_tgsi_context * bld_base,
4023 struct lp_build_emit_data * emit_data)
4024 {
4025 struct si_shader_context *ctx = si_shader_context(bld_base);
4026 struct gallivm_state *gallivm = bld_base->base.gallivm;
4027 const struct tgsi_full_instruction *inst = emit_data->inst;
4028 const struct tgsi_full_src_register *reg = &inst->Src[0];
4029
4030 emit_data->dst_type = ctx->v4i32;
4031
4032 if (reg->Register.File == TGSI_FILE_BUFFER) {
4033 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4034 emit_data->arg_count = 1;
4035 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4036 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4037 &emit_data->args[0]);
4038 emit_data->arg_count = 1;
4039 } else {
4040 emit_data->args[0] = bld_base->uint_bld.zero; /* mip level */
4041 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4042 &emit_data->args[1]);
4043 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
4044 emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
4045 emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
4046 emit_data->args[5] = tgsi_is_array_image(inst->Memory.Texture) ?
4047 bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da */
4048 emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
4049 emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
4050 emit_data->args[8] = bld_base->uint_bld.zero; /* tfe */
4051 emit_data->args[9] = bld_base->uint_bld.zero; /* lwe */
4052 emit_data->arg_count = 10;
4053 }
4054 }
4055
4056 static void resq_emit(
4057 const struct lp_build_tgsi_action *action,
4058 struct lp_build_tgsi_context *bld_base,
4059 struct lp_build_emit_data *emit_data)
4060 {
4061 struct gallivm_state *gallivm = bld_base->base.gallivm;
4062 LLVMBuilderRef builder = gallivm->builder;
4063 const struct tgsi_full_instruction *inst = emit_data->inst;
4064 LLVMValueRef out;
4065
4066 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4067 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4068 lp_build_const_int32(gallivm, 2), "");
4069 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4070 out = get_buffer_size(bld_base, emit_data->args[0]);
4071 } else {
4072 out = lp_build_intrinsic(
4073 builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
4074 emit_data->args, emit_data->arg_count,
4075 LP_FUNC_ATTR_READNONE);
4076
4077 /* Divide the number of layers by 6 to get the number of cubes. */
4078 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
4079 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
4080 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
4081
4082 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4083 z = LLVMBuildSDiv(builder, z, imm6, "");
4084 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4085 }
4086 }
4087
4088 emit_data->output[emit_data->chan] = out;
4089 }
4090
4091 static void set_tex_fetch_args(struct si_shader_context *ctx,
4092 struct lp_build_emit_data *emit_data,
4093 unsigned opcode, unsigned target,
4094 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4095 LLVMValueRef *param, unsigned count,
4096 unsigned dmask)
4097 {
4098 struct gallivm_state *gallivm = &ctx->gallivm;
4099 unsigned num_args;
4100 unsigned is_rect = target == TGSI_TEXTURE_RECT;
4101
4102 /* Pad to power of two vector */
4103 while (count < util_next_power_of_two(count))
4104 param[count++] = LLVMGetUndef(ctx->i32);
4105
4106 /* Texture coordinates. */
4107 if (count > 1)
4108 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
4109 else
4110 emit_data->args[0] = param[0];
4111
4112 /* Resource. */
4113 emit_data->args[1] = res_ptr;
4114 num_args = 2;
4115
4116 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
4117 emit_data->dst_type = ctx->v4i32;
4118 else {
4119 emit_data->dst_type = ctx->v4f32;
4120
4121 emit_data->args[num_args++] = samp_ptr;
4122 }
4123
4124 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
4125 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
4126 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
4127 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
4128 tgsi_is_array_sampler(target)); /* da */
4129 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
4130 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
4131 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
4132 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
4133
4134 emit_data->arg_count = num_args;
4135 }
4136
4137 static const struct lp_build_tgsi_action tex_action;
4138
4139 enum desc_type {
4140 DESC_IMAGE,
4141 DESC_BUFFER,
4142 DESC_FMASK,
4143 DESC_SAMPLER,
4144 };
4145
4146 /**
4147 * Load an image view, fmask view. or sampler state descriptor.
4148 */
4149 static LLVMValueRef load_sampler_desc_custom(struct si_shader_context *ctx,
4150 LLVMValueRef list, LLVMValueRef index,
4151 enum desc_type type)
4152 {
4153 struct gallivm_state *gallivm = &ctx->gallivm;
4154 LLVMBuilderRef builder = gallivm->builder;
4155
4156 switch (type) {
4157 case DESC_IMAGE:
4158 /* The image is at [0:7]. */
4159 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4160 break;
4161 case DESC_BUFFER:
4162 /* The buffer is in [4:7]. */
4163 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4164 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4165 list = LLVMBuildPointerCast(builder, list,
4166 const_array(ctx->v4i32, 0), "");
4167 break;
4168 case DESC_FMASK:
4169 /* The FMASK is at [8:15]. */
4170 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4171 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4172 break;
4173 case DESC_SAMPLER:
4174 /* The sampler state is at [12:15]. */
4175 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4176 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4177 list = LLVMBuildPointerCast(builder, list,
4178 const_array(ctx->v4i32, 0), "");
4179 break;
4180 }
4181
4182 return build_indexed_load_const(ctx, list, index);
4183 }
4184
4185 static LLVMValueRef load_sampler_desc(struct si_shader_context *ctx,
4186 LLVMValueRef index, enum desc_type type)
4187 {
4188 LLVMValueRef list = LLVMGetParam(ctx->main_fn,
4189 SI_PARAM_SAMPLERS);
4190
4191 return load_sampler_desc_custom(ctx, list, index, type);
4192 }
4193
4194 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4195 *
4196 * SI-CI:
4197 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4198 * filtering manually. The driver sets img7 to a mask clearing
4199 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4200 * s_and_b32 samp0, samp0, img7
4201 *
4202 * VI:
4203 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4204 */
4205 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4206 LLVMValueRef res, LLVMValueRef samp)
4207 {
4208 LLVMBuilderRef builder = ctx->gallivm.builder;
4209 LLVMValueRef img7, samp0;
4210
4211 if (ctx->screen->b.chip_class >= VI)
4212 return samp;
4213
4214 img7 = LLVMBuildExtractElement(builder, res,
4215 LLVMConstInt(ctx->i32, 7, 0), "");
4216 samp0 = LLVMBuildExtractElement(builder, samp,
4217 LLVMConstInt(ctx->i32, 0, 0), "");
4218 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4219 return LLVMBuildInsertElement(builder, samp, samp0,
4220 LLVMConstInt(ctx->i32, 0, 0), "");
4221 }
4222
4223 static void tex_fetch_ptrs(
4224 struct lp_build_tgsi_context *bld_base,
4225 struct lp_build_emit_data *emit_data,
4226 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4227 {
4228 struct si_shader_context *ctx = si_shader_context(bld_base);
4229 const struct tgsi_full_instruction *inst = emit_data->inst;
4230 unsigned target = inst->Texture.Texture;
4231 unsigned sampler_src;
4232 unsigned sampler_index;
4233 LLVMValueRef index;
4234
4235 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4236 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
4237
4238 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
4239 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
4240
4241 index = get_bounded_indirect_index(ctx,
4242 &reg->Indirect,
4243 reg->Register.Index,
4244 SI_NUM_SAMPLERS);
4245 } else {
4246 index = LLVMConstInt(ctx->i32, sampler_index, 0);
4247 }
4248
4249 if (target == TGSI_TEXTURE_BUFFER)
4250 *res_ptr = load_sampler_desc(ctx, index, DESC_BUFFER);
4251 else
4252 *res_ptr = load_sampler_desc(ctx, index, DESC_IMAGE);
4253
4254 if (samp_ptr)
4255 *samp_ptr = NULL;
4256 if (fmask_ptr)
4257 *fmask_ptr = NULL;
4258
4259 if (target == TGSI_TEXTURE_2D_MSAA ||
4260 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4261 if (fmask_ptr)
4262 *fmask_ptr = load_sampler_desc(ctx, index, DESC_FMASK);
4263 } else if (target != TGSI_TEXTURE_BUFFER) {
4264 if (samp_ptr) {
4265 *samp_ptr = load_sampler_desc(ctx, index, DESC_SAMPLER);
4266 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4267 }
4268 }
4269 }
4270
4271 static void txq_fetch_args(
4272 struct lp_build_tgsi_context *bld_base,
4273 struct lp_build_emit_data *emit_data)
4274 {
4275 struct si_shader_context *ctx = si_shader_context(bld_base);
4276 const struct tgsi_full_instruction *inst = emit_data->inst;
4277 unsigned target = inst->Texture.Texture;
4278 LLVMValueRef res_ptr;
4279 LLVMValueRef address;
4280
4281 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4282
4283 if (target == TGSI_TEXTURE_BUFFER) {
4284 /* Read the size from the buffer descriptor directly. */
4285 emit_data->args[0] = get_buffer_size(bld_base, res_ptr);
4286 return;
4287 }
4288
4289 /* Textures - set the mip level. */
4290 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4291
4292 set_tex_fetch_args(ctx, emit_data, TGSI_OPCODE_TXQ, target, res_ptr,
4293 NULL, &address, 1, 0xf);
4294 }
4295
4296 static void txq_emit(const struct lp_build_tgsi_action *action,
4297 struct lp_build_tgsi_context *bld_base,
4298 struct lp_build_emit_data *emit_data)
4299 {
4300 struct lp_build_context *base = &bld_base->base;
4301 unsigned target = emit_data->inst->Texture.Texture;
4302
4303 if (target == TGSI_TEXTURE_BUFFER) {
4304 /* Just return the buffer size. */
4305 emit_data->output[emit_data->chan] = emit_data->args[0];
4306 return;
4307 }
4308
4309 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4310 base->gallivm->builder, "llvm.SI.getresinfo.i32",
4311 emit_data->dst_type, emit_data->args, emit_data->arg_count,
4312 LP_FUNC_ATTR_READNONE);
4313
4314 /* Divide the number of layers by 6 to get the number of cubes. */
4315 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4316 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4317 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4318 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4319 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4320
4321 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4322 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4323 z = LLVMBuildSDiv(builder, z, six, "");
4324
4325 emit_data->output[emit_data->chan] =
4326 LLVMBuildInsertElement(builder, v4, z, two, "");
4327 }
4328 }
4329
4330 static void tex_fetch_args(
4331 struct lp_build_tgsi_context *bld_base,
4332 struct lp_build_emit_data *emit_data)
4333 {
4334 struct si_shader_context *ctx = si_shader_context(bld_base);
4335 struct gallivm_state *gallivm = bld_base->base.gallivm;
4336 const struct tgsi_full_instruction *inst = emit_data->inst;
4337 unsigned opcode = inst->Instruction.Opcode;
4338 unsigned target = inst->Texture.Texture;
4339 LLVMValueRef coords[5], derivs[6];
4340 LLVMValueRef address[16];
4341 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4342 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4343 unsigned count = 0;
4344 unsigned chan;
4345 unsigned num_deriv_channels = 0;
4346 bool has_offset = inst->Texture.NumOffsets > 0;
4347 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4348 unsigned dmask = 0xf;
4349
4350 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4351
4352 if (target == TGSI_TEXTURE_BUFFER) {
4353 emit_data->dst_type = ctx->v4f32;
4354 emit_data->args[0] = LLVMBuildBitCast(gallivm->builder, res_ptr,
4355 ctx->v16i8, "");
4356 emit_data->args[1] = bld_base->uint_bld.zero;
4357 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4358 emit_data->arg_count = 3;
4359 return;
4360 }
4361
4362 /* Fetch and project texture coordinates */
4363 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4364 for (chan = 0; chan < 3; chan++ ) {
4365 coords[chan] = lp_build_emit_fetch(bld_base,
4366 emit_data->inst, 0,
4367 chan);
4368 if (opcode == TGSI_OPCODE_TXP)
4369 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4370 TGSI_OPCODE_DIV,
4371 coords[chan],
4372 coords[3]);
4373 }
4374
4375 if (opcode == TGSI_OPCODE_TXP)
4376 coords[3] = bld_base->base.one;
4377
4378 /* Pack offsets. */
4379 if (has_offset && opcode != TGSI_OPCODE_TXF) {
4380 /* The offsets are six-bit signed integers packed like this:
4381 * X=[5:0], Y=[13:8], and Z=[21:16].
4382 */
4383 LLVMValueRef offset[3], pack;
4384
4385 assert(inst->Texture.NumOffsets == 1);
4386
4387 for (chan = 0; chan < 3; chan++) {
4388 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4389 emit_data->inst, 0, chan);
4390 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4391 lp_build_const_int32(gallivm, 0x3f), "");
4392 if (chan)
4393 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4394 lp_build_const_int32(gallivm, chan*8), "");
4395 }
4396
4397 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4398 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4399 address[count++] = pack;
4400 }
4401
4402 /* Pack LOD bias value */
4403 if (opcode == TGSI_OPCODE_TXB)
4404 address[count++] = coords[3];
4405 if (opcode == TGSI_OPCODE_TXB2)
4406 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4407
4408 /* Pack depth comparison value */
4409 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4410 LLVMValueRef z;
4411
4412 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4413 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4414 } else {
4415 assert(ref_pos >= 0);
4416 z = coords[ref_pos];
4417 }
4418
4419 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4420 * so the depth comparison value isn't clamped for Z16 and
4421 * Z24 anymore. Do it manually here.
4422 *
4423 * It's unnecessary if the original texture format was
4424 * Z32_FLOAT, but we don't know that here.
4425 */
4426 if (ctx->screen->b.chip_class == VI)
4427 z = si_llvm_saturate(bld_base, z);
4428
4429 address[count++] = z;
4430 }
4431
4432 /* Pack user derivatives */
4433 if (opcode == TGSI_OPCODE_TXD) {
4434 int param, num_src_deriv_channels;
4435
4436 switch (target) {
4437 case TGSI_TEXTURE_3D:
4438 num_src_deriv_channels = 3;
4439 num_deriv_channels = 3;
4440 break;
4441 case TGSI_TEXTURE_2D:
4442 case TGSI_TEXTURE_SHADOW2D:
4443 case TGSI_TEXTURE_RECT:
4444 case TGSI_TEXTURE_SHADOWRECT:
4445 case TGSI_TEXTURE_2D_ARRAY:
4446 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4447 num_src_deriv_channels = 2;
4448 num_deriv_channels = 2;
4449 break;
4450 case TGSI_TEXTURE_CUBE:
4451 case TGSI_TEXTURE_SHADOWCUBE:
4452 case TGSI_TEXTURE_CUBE_ARRAY:
4453 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4454 /* Cube derivatives will be converted to 2D. */
4455 num_src_deriv_channels = 3;
4456 num_deriv_channels = 2;
4457 break;
4458 case TGSI_TEXTURE_1D:
4459 case TGSI_TEXTURE_SHADOW1D:
4460 case TGSI_TEXTURE_1D_ARRAY:
4461 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4462 num_src_deriv_channels = 1;
4463 num_deriv_channels = 1;
4464 break;
4465 default:
4466 unreachable("invalid target");
4467 }
4468
4469 for (param = 0; param < 2; param++)
4470 for (chan = 0; chan < num_src_deriv_channels; chan++)
4471 derivs[param * num_src_deriv_channels + chan] =
4472 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4473 }
4474
4475 if (target == TGSI_TEXTURE_CUBE ||
4476 target == TGSI_TEXTURE_CUBE_ARRAY ||
4477 target == TGSI_TEXTURE_SHADOWCUBE ||
4478 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4479 si_prepare_cube_coords(bld_base, emit_data, coords, derivs);
4480
4481 if (opcode == TGSI_OPCODE_TXD)
4482 for (int i = 0; i < num_deriv_channels * 2; i++)
4483 address[count++] = derivs[i];
4484
4485 /* Pack texture coordinates */
4486 address[count++] = coords[0];
4487 if (num_coords > 1)
4488 address[count++] = coords[1];
4489 if (num_coords > 2)
4490 address[count++] = coords[2];
4491
4492 /* Pack LOD or sample index */
4493 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4494 address[count++] = coords[3];
4495 else if (opcode == TGSI_OPCODE_TXL2)
4496 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4497
4498 if (count > 16) {
4499 assert(!"Cannot handle more than 16 texture address parameters");
4500 count = 16;
4501 }
4502
4503 for (chan = 0; chan < count; chan++ ) {
4504 address[chan] = LLVMBuildBitCast(gallivm->builder,
4505 address[chan], ctx->i32, "");
4506 }
4507
4508 /* Adjust the sample index according to FMASK.
4509 *
4510 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4511 * which is the identity mapping. Each nibble says which physical sample
4512 * should be fetched to get that sample.
4513 *
4514 * For example, 0x11111100 means there are only 2 samples stored and
4515 * the second sample covers 3/4 of the pixel. When reading samples 0
4516 * and 1, return physical sample 0 (determined by the first two 0s
4517 * in FMASK), otherwise return physical sample 1.
4518 *
4519 * The sample index should be adjusted as follows:
4520 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4521 */
4522 if (target == TGSI_TEXTURE_2D_MSAA ||
4523 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4524 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4525 struct lp_build_emit_data txf_emit_data = *emit_data;
4526 LLVMValueRef txf_address[4];
4527 unsigned txf_count = count;
4528 struct tgsi_full_instruction inst = {};
4529
4530 memcpy(txf_address, address, sizeof(txf_address));
4531
4532 if (target == TGSI_TEXTURE_2D_MSAA) {
4533 txf_address[2] = bld_base->uint_bld.zero;
4534 }
4535 txf_address[3] = bld_base->uint_bld.zero;
4536
4537 /* Read FMASK using TXF. */
4538 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4539 inst.Texture.Texture = target;
4540 txf_emit_data.inst = &inst;
4541 txf_emit_data.chan = 0;
4542 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
4543 target, fmask_ptr, NULL,
4544 txf_address, txf_count, 0xf);
4545 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4546
4547 /* Initialize some constants. */
4548 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4549 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4550
4551 /* Apply the formula. */
4552 LLVMValueRef fmask =
4553 LLVMBuildExtractElement(gallivm->builder,
4554 txf_emit_data.output[0],
4555 uint_bld->zero, "");
4556
4557 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4558
4559 LLVMValueRef sample_index4 =
4560 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4561
4562 LLVMValueRef shifted_fmask =
4563 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4564
4565 LLVMValueRef final_sample =
4566 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4567
4568 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4569 * resource descriptor is 0 (invalid),
4570 */
4571 LLVMValueRef fmask_desc =
4572 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4573 ctx->v8i32, "");
4574
4575 LLVMValueRef fmask_word1 =
4576 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4577 uint_bld->one, "");
4578
4579 LLVMValueRef word1_is_nonzero =
4580 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4581 fmask_word1, uint_bld->zero, "");
4582
4583 /* Replace the MSAA sample index. */
4584 address[sample_chan] =
4585 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4586 final_sample, address[sample_chan], "");
4587 }
4588
4589 if (opcode == TGSI_OPCODE_TXF) {
4590 /* add tex offsets */
4591 if (inst->Texture.NumOffsets) {
4592 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4593 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
4594 const struct tgsi_texture_offset *off = inst->TexOffsets;
4595
4596 assert(inst->Texture.NumOffsets == 1);
4597
4598 switch (target) {
4599 case TGSI_TEXTURE_3D:
4600 address[2] = lp_build_add(uint_bld, address[2],
4601 bld->immediates[off->Index][off->SwizzleZ]);
4602 /* fall through */
4603 case TGSI_TEXTURE_2D:
4604 case TGSI_TEXTURE_SHADOW2D:
4605 case TGSI_TEXTURE_RECT:
4606 case TGSI_TEXTURE_SHADOWRECT:
4607 case TGSI_TEXTURE_2D_ARRAY:
4608 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4609 address[1] =
4610 lp_build_add(uint_bld, address[1],
4611 bld->immediates[off->Index][off->SwizzleY]);
4612 /* fall through */
4613 case TGSI_TEXTURE_1D:
4614 case TGSI_TEXTURE_SHADOW1D:
4615 case TGSI_TEXTURE_1D_ARRAY:
4616 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4617 address[0] =
4618 lp_build_add(uint_bld, address[0],
4619 bld->immediates[off->Index][off->SwizzleX]);
4620 break;
4621 /* texture offsets do not apply to other texture targets */
4622 }
4623 }
4624 }
4625
4626 if (opcode == TGSI_OPCODE_TG4) {
4627 unsigned gather_comp = 0;
4628
4629 /* DMASK was repurposed for GATHER4. 4 components are always
4630 * returned and DMASK works like a swizzle - it selects
4631 * the component to fetch. The only valid DMASK values are
4632 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4633 * (red,red,red,red) etc.) The ISA document doesn't mention
4634 * this.
4635 */
4636
4637 /* Get the component index from src1.x for Gather4. */
4638 if (!tgsi_is_shadow_target(target)) {
4639 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4640 LLVMValueRef comp_imm;
4641 struct tgsi_src_register src1 = inst->Src[1].Register;
4642
4643 assert(src1.File == TGSI_FILE_IMMEDIATE);
4644
4645 comp_imm = imms[src1.Index][src1.SwizzleX];
4646 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4647 gather_comp = CLAMP(gather_comp, 0, 3);
4648 }
4649
4650 dmask = 1 << gather_comp;
4651 }
4652
4653 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
4654 samp_ptr, address, count, dmask);
4655 }
4656
4657 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
4658 * incorrectly forces nearest filtering if the texture format is integer.
4659 * The only effect it has on Gather4, which always returns 4 texels for
4660 * bilinear filtering, is that the final coordinates are off by 0.5 of
4661 * the texel size.
4662 *
4663 * The workaround is to subtract 0.5 from the unnormalized coordinates,
4664 * or (0.5 / size) from the normalized coordinates.
4665 */
4666 static void si_lower_gather4_integer(struct si_shader_context *ctx,
4667 struct lp_build_emit_data *emit_data,
4668 const char *intr_name,
4669 unsigned coord_vgpr_index)
4670 {
4671 LLVMBuilderRef builder = ctx->gallivm.builder;
4672 LLVMValueRef coord = emit_data->args[0];
4673 LLVMValueRef half_texel[2];
4674 int c;
4675
4676 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_RECT ||
4677 emit_data->inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
4678 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
4679 } else {
4680 struct tgsi_full_instruction txq_inst = {};
4681 struct lp_build_emit_data txq_emit_data = {};
4682
4683 /* Query the texture size. */
4684 txq_inst.Texture.Texture = emit_data->inst->Texture.Texture;
4685 txq_emit_data.inst = &txq_inst;
4686 txq_emit_data.dst_type = ctx->v4i32;
4687 set_tex_fetch_args(ctx, &txq_emit_data, TGSI_OPCODE_TXQ,
4688 txq_inst.Texture.Texture,
4689 emit_data->args[1], NULL,
4690 &ctx->soa.bld_base.uint_bld.zero,
4691 1, 0xf);
4692 txq_emit(NULL, &ctx->soa.bld_base, &txq_emit_data);
4693
4694 /* Compute -0.5 / size. */
4695 for (c = 0; c < 2; c++) {
4696 half_texel[c] =
4697 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
4698 LLVMConstInt(ctx->i32, c, 0), "");
4699 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
4700 half_texel[c] =
4701 lp_build_emit_llvm_unary(&ctx->soa.bld_base,
4702 TGSI_OPCODE_RCP, half_texel[c]);
4703 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
4704 LLVMConstReal(ctx->f32, -0.5), "");
4705 }
4706 }
4707
4708 for (c = 0; c < 2; c++) {
4709 LLVMValueRef tmp;
4710 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
4711
4712 tmp = LLVMBuildExtractElement(builder, coord, index, "");
4713 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4714 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
4715 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4716 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
4717 }
4718
4719 emit_data->args[0] = coord;
4720 emit_data->output[emit_data->chan] =
4721 lp_build_intrinsic(builder, intr_name, emit_data->dst_type,
4722 emit_data->args, emit_data->arg_count,
4723 LP_FUNC_ATTR_READNONE);
4724 }
4725
4726 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4727 struct lp_build_tgsi_context *bld_base,
4728 struct lp_build_emit_data *emit_data)
4729 {
4730 struct si_shader_context *ctx = si_shader_context(bld_base);
4731 struct lp_build_context *base = &bld_base->base;
4732 const struct tgsi_full_instruction *inst = emit_data->inst;
4733 unsigned opcode = inst->Instruction.Opcode;
4734 unsigned target = inst->Texture.Texture;
4735 char intr_name[127];
4736 bool has_offset = inst->Texture.NumOffsets > 0;
4737 bool is_shadow = tgsi_is_shadow_target(target);
4738 char type[64];
4739 const char *name = "llvm.SI.image.sample";
4740 const char *infix = "";
4741
4742 if (target == TGSI_TEXTURE_BUFFER) {
4743 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4744 base->gallivm->builder,
4745 "llvm.SI.vs.load.input", emit_data->dst_type,
4746 emit_data->args, emit_data->arg_count,
4747 LP_FUNC_ATTR_READNONE);
4748 return;
4749 }
4750
4751 switch (opcode) {
4752 case TGSI_OPCODE_TXF:
4753 name = target == TGSI_TEXTURE_2D_MSAA ||
4754 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4755 "llvm.SI.image.load" :
4756 "llvm.SI.image.load.mip";
4757 is_shadow = false;
4758 has_offset = false;
4759 break;
4760 case TGSI_OPCODE_LODQ:
4761 name = "llvm.SI.getlod";
4762 is_shadow = false;
4763 has_offset = false;
4764 break;
4765 case TGSI_OPCODE_TEX:
4766 case TGSI_OPCODE_TEX2:
4767 case TGSI_OPCODE_TXP:
4768 if (ctx->type != PIPE_SHADER_FRAGMENT)
4769 infix = ".lz";
4770 break;
4771 case TGSI_OPCODE_TXB:
4772 case TGSI_OPCODE_TXB2:
4773 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4774 infix = ".b";
4775 break;
4776 case TGSI_OPCODE_TXL:
4777 case TGSI_OPCODE_TXL2:
4778 infix = ".l";
4779 break;
4780 case TGSI_OPCODE_TXD:
4781 infix = ".d";
4782 break;
4783 case TGSI_OPCODE_TG4:
4784 name = "llvm.SI.gather4";
4785 infix = ".lz";
4786 break;
4787 default:
4788 assert(0);
4789 return;
4790 }
4791
4792 /* Add the type and suffixes .c, .o if needed. */
4793 build_type_name_for_intr(LLVMTypeOf(emit_data->args[0]), type, sizeof(type));
4794 sprintf(intr_name, "%s%s%s%s.%s",
4795 name, is_shadow ? ".c" : "", infix,
4796 has_offset ? ".o" : "", type);
4797
4798 /* The hardware needs special lowering for Gather4 with integer formats. */
4799 if (opcode == TGSI_OPCODE_TG4) {
4800 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4801 /* This will also work with non-constant indexing because of how
4802 * glsl_to_tgsi works and we intent to preserve that behavior.
4803 */
4804 const unsigned src_idx = 2;
4805 unsigned sampler = inst->Src[src_idx].Register.Index;
4806
4807 assert(inst->Src[src_idx].Register.File == TGSI_FILE_SAMPLER);
4808
4809 if (info->sampler_type[sampler] == TGSI_RETURN_TYPE_SINT ||
4810 info->sampler_type[sampler] == TGSI_RETURN_TYPE_UINT) {
4811 /* Texture coordinates start after:
4812 * {offset, bias, z-compare, derivatives}
4813 * Only the offset and z-compare can occur here.
4814 */
4815 si_lower_gather4_integer(ctx, emit_data, intr_name,
4816 (int)has_offset + (int)is_shadow);
4817 return;
4818 }
4819 }
4820
4821 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4822 base->gallivm->builder, intr_name, emit_data->dst_type,
4823 emit_data->args, emit_data->arg_count,
4824 LP_FUNC_ATTR_READNONE);
4825 }
4826
4827 static void si_llvm_emit_txqs(
4828 const struct lp_build_tgsi_action *action,
4829 struct lp_build_tgsi_context *bld_base,
4830 struct lp_build_emit_data *emit_data)
4831 {
4832 struct si_shader_context *ctx = si_shader_context(bld_base);
4833 struct gallivm_state *gallivm = bld_base->base.gallivm;
4834 LLVMBuilderRef builder = gallivm->builder;
4835 LLVMValueRef res, samples;
4836 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4837
4838 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4839
4840
4841 /* Read the samples from the descriptor directly. */
4842 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4843 samples = LLVMBuildExtractElement(
4844 builder, res,
4845 lp_build_const_int32(gallivm, 3), "");
4846 samples = LLVMBuildLShr(builder, samples,
4847 lp_build_const_int32(gallivm, 16), "");
4848 samples = LLVMBuildAnd(builder, samples,
4849 lp_build_const_int32(gallivm, 0xf), "");
4850 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
4851 samples, "");
4852
4853 emit_data->output[emit_data->chan] = samples;
4854 }
4855
4856 /*
4857 * SI implements derivatives using the local data store (LDS)
4858 * All writes to the LDS happen in all executing threads at
4859 * the same time. TID is the Thread ID for the current
4860 * thread and is a value between 0 and 63, representing
4861 * the thread's position in the wavefront.
4862 *
4863 * For the pixel shader threads are grouped into quads of four pixels.
4864 * The TIDs of the pixels of a quad are:
4865 *
4866 * +------+------+
4867 * |4n + 0|4n + 1|
4868 * +------+------+
4869 * |4n + 2|4n + 3|
4870 * +------+------+
4871 *
4872 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
4873 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
4874 * the current pixel's column, and masking with 0xfffffffe yields the TID
4875 * of the left pixel of the current pixel's row.
4876 *
4877 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
4878 * adding 2 yields the TID of the pixel below the top pixel.
4879 */
4880 /* masks for thread ID. */
4881 #define TID_MASK_TOP_LEFT 0xfffffffc
4882 #define TID_MASK_TOP 0xfffffffd
4883 #define TID_MASK_LEFT 0xfffffffe
4884
4885 static void si_llvm_emit_ddxy(
4886 const struct lp_build_tgsi_action *action,
4887 struct lp_build_tgsi_context *bld_base,
4888 struct lp_build_emit_data *emit_data)
4889 {
4890 struct si_shader_context *ctx = si_shader_context(bld_base);
4891 struct gallivm_state *gallivm = bld_base->base.gallivm;
4892 unsigned opcode = emit_data->info->opcode;
4893 LLVMValueRef thread_id, tl, trbl, tl_tid, trbl_tid, val, args[2];
4894 int idx;
4895 unsigned mask;
4896
4897 thread_id = get_thread_id(ctx);
4898
4899 if (opcode == TGSI_OPCODE_DDX_FINE)
4900 mask = TID_MASK_LEFT;
4901 else if (opcode == TGSI_OPCODE_DDY_FINE)
4902 mask = TID_MASK_TOP;
4903 else
4904 mask = TID_MASK_TOP_LEFT;
4905
4906 tl_tid = LLVMBuildAnd(gallivm->builder, thread_id,
4907 lp_build_const_int32(gallivm, mask), "");
4908
4909 /* for DDX we want to next X pixel, DDY next Y pixel. */
4910 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
4911 trbl_tid = LLVMBuildAdd(gallivm->builder, tl_tid,
4912 lp_build_const_int32(gallivm, idx), "");
4913
4914 val = LLVMBuildBitCast(gallivm->builder, emit_data->args[0], ctx->i32, "");
4915
4916 if (ctx->screen->has_ds_bpermute) {
4917 args[0] = LLVMBuildMul(gallivm->builder, tl_tid,
4918 lp_build_const_int32(gallivm, 4), "");
4919 args[1] = val;
4920 tl = lp_build_intrinsic(gallivm->builder,
4921 "llvm.amdgcn.ds.bpermute", ctx->i32,
4922 args, 2, LP_FUNC_ATTR_READNONE);
4923
4924 args[0] = LLVMBuildMul(gallivm->builder, trbl_tid,
4925 lp_build_const_int32(gallivm, 4), "");
4926 trbl = lp_build_intrinsic(gallivm->builder,
4927 "llvm.amdgcn.ds.bpermute", ctx->i32,
4928 args, 2, LP_FUNC_ATTR_READNONE);
4929 } else {
4930 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
4931
4932 store_ptr = build_gep0(ctx, ctx->lds, thread_id);
4933 load_ptr0 = build_gep0(ctx, ctx->lds, tl_tid);
4934 load_ptr1 = build_gep0(ctx, ctx->lds, trbl_tid);
4935
4936 LLVMBuildStore(gallivm->builder, val, store_ptr);
4937 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
4938 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
4939 }
4940
4941 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
4942 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
4943
4944 emit_data->output[emit_data->chan] =
4945 LLVMBuildFSub(gallivm->builder, trbl, tl, "");
4946 }
4947
4948 /*
4949 * this takes an I,J coordinate pair,
4950 * and works out the X and Y derivatives.
4951 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
4952 */
4953 static LLVMValueRef si_llvm_emit_ddxy_interp(
4954 struct lp_build_tgsi_context *bld_base,
4955 LLVMValueRef interp_ij)
4956 {
4957 struct si_shader_context *ctx = si_shader_context(bld_base);
4958 struct gallivm_state *gallivm = bld_base->base.gallivm;
4959 LLVMValueRef result[4], a;
4960 unsigned i;
4961
4962 for (i = 0; i < 2; i++) {
4963 a = LLVMBuildExtractElement(gallivm->builder, interp_ij,
4964 LLVMConstInt(ctx->i32, i, 0), "");
4965 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
4966 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
4967 }
4968
4969 return lp_build_gather_values(gallivm, result, 4);
4970 }
4971
4972 static void interp_fetch_args(
4973 struct lp_build_tgsi_context *bld_base,
4974 struct lp_build_emit_data *emit_data)
4975 {
4976 struct si_shader_context *ctx = si_shader_context(bld_base);
4977 struct gallivm_state *gallivm = bld_base->base.gallivm;
4978 const struct tgsi_full_instruction *inst = emit_data->inst;
4979
4980 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
4981 /* offset is in second src, first two channels */
4982 emit_data->args[0] = lp_build_emit_fetch(bld_base,
4983 emit_data->inst, 1,
4984 TGSI_CHAN_X);
4985 emit_data->args[1] = lp_build_emit_fetch(bld_base,
4986 emit_data->inst, 1,
4987 TGSI_CHAN_Y);
4988 emit_data->arg_count = 2;
4989 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4990 LLVMValueRef sample_position;
4991 LLVMValueRef sample_id;
4992 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
4993
4994 /* fetch sample ID, then fetch its sample position,
4995 * and place into first two channels.
4996 */
4997 sample_id = lp_build_emit_fetch(bld_base,
4998 emit_data->inst, 1, TGSI_CHAN_X);
4999 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
5000 ctx->i32, "");
5001 sample_position = load_sample_position(ctx, sample_id);
5002
5003 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
5004 sample_position,
5005 lp_build_const_int32(gallivm, 0), "");
5006
5007 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
5008 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
5009 sample_position,
5010 lp_build_const_int32(gallivm, 1), "");
5011 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
5012 emit_data->arg_count = 2;
5013 }
5014 }
5015
5016 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
5017 struct lp_build_tgsi_context *bld_base,
5018 struct lp_build_emit_data *emit_data)
5019 {
5020 struct si_shader_context *ctx = si_shader_context(bld_base);
5021 struct si_shader *shader = ctx->shader;
5022 struct gallivm_state *gallivm = bld_base->base.gallivm;
5023 LLVMValueRef interp_param;
5024 const struct tgsi_full_instruction *inst = emit_data->inst;
5025 const char *intr_name;
5026 int input_index = inst->Src[0].Register.Index;
5027 int chan;
5028 int i;
5029 LLVMValueRef attr_number;
5030 LLVMValueRef params = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
5031 int interp_param_idx;
5032 unsigned interp = shader->selector->info.input_interpolate[input_index];
5033 unsigned location;
5034
5035 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5036
5037 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5038 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
5039 location = TGSI_INTERPOLATE_LOC_CENTER;
5040 else
5041 location = TGSI_INTERPOLATE_LOC_CENTROID;
5042
5043 interp_param_idx = lookup_interp_param_index(interp, location);
5044 if (interp_param_idx == -1)
5045 return;
5046 else if (interp_param_idx)
5047 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
5048 else
5049 interp_param = NULL;
5050
5051 attr_number = lp_build_const_int32(gallivm, input_index);
5052
5053 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5054 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5055 LLVMValueRef ij_out[2];
5056 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
5057
5058 /*
5059 * take the I then J parameters, and the DDX/Y for it, and
5060 * calculate the IJ inputs for the interpolator.
5061 * temp1 = ddx * offset/sample.x + I;
5062 * interp_param.I = ddy * offset/sample.y + temp1;
5063 * temp1 = ddx * offset/sample.x + J;
5064 * interp_param.J = ddy * offset/sample.y + temp1;
5065 */
5066 for (i = 0; i < 2; i++) {
5067 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
5068 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
5069 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
5070 ddxy_out, ix_ll, "");
5071 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
5072 ddxy_out, iy_ll, "");
5073 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5074 interp_param, ix_ll, "");
5075 LLVMValueRef temp1, temp2;
5076
5077 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5078 ctx->f32, "");
5079
5080 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5081
5082 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5083
5084 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5085
5086 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5087
5088 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
5089 temp2, ctx->i32, "");
5090 }
5091 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
5092 }
5093
5094 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
5095 for (chan = 0; chan < 4; chan++) {
5096 LLVMValueRef args[4];
5097 LLVMValueRef llvm_chan;
5098 unsigned schan;
5099
5100 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5101 llvm_chan = lp_build_const_int32(gallivm, schan);
5102
5103 args[0] = llvm_chan;
5104 args[1] = attr_number;
5105 args[2] = params;
5106 args[3] = interp_param;
5107
5108 emit_data->output[chan] =
5109 lp_build_intrinsic(gallivm->builder, intr_name,
5110 ctx->f32, args, args[3] ? 4 : 3,
5111 LP_FUNC_ATTR_READNONE);
5112 }
5113 }
5114
5115 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5116 struct lp_build_emit_data *emit_data)
5117 {
5118 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
5119 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5120 unsigned stream;
5121
5122 assert(src0.File == TGSI_FILE_IMMEDIATE);
5123
5124 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
5125 return stream;
5126 }
5127
5128 /* Emit one vertex from the geometry shader */
5129 static void si_llvm_emit_vertex(
5130 const struct lp_build_tgsi_action *action,
5131 struct lp_build_tgsi_context *bld_base,
5132 struct lp_build_emit_data *emit_data)
5133 {
5134 struct si_shader_context *ctx = si_shader_context(bld_base);
5135 struct lp_build_context *uint = &bld_base->uint_bld;
5136 struct si_shader *shader = ctx->shader;
5137 struct tgsi_shader_info *info = &shader->selector->info;
5138 struct gallivm_state *gallivm = bld_base->base.gallivm;
5139 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
5140 SI_PARAM_GS2VS_OFFSET);
5141 LLVMValueRef gs_next_vertex;
5142 LLVMValueRef can_emit, kill;
5143 LLVMValueRef args[2];
5144 unsigned chan;
5145 int i;
5146 unsigned stream;
5147
5148 stream = si_llvm_get_stream(bld_base, emit_data);
5149
5150 /* Write vertex attribute values to GSVS ring */
5151 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5152 ctx->gs_next_vertex[stream],
5153 "");
5154
5155 /* If this thread has already emitted the declared maximum number of
5156 * vertices, kill it: excessive vertex emissions are not supposed to
5157 * have any effect, and GS threads have no externally observable
5158 * effects other than emitting vertices.
5159 */
5160 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
5161 lp_build_const_int32(gallivm,
5162 shader->selector->gs_max_out_vertices), "");
5163 kill = lp_build_select(&bld_base->base, can_emit,
5164 lp_build_const_float(gallivm, 1.0f),
5165 lp_build_const_float(gallivm, -1.0f));
5166
5167 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
5168 ctx->voidt, &kill, 1, 0);
5169
5170 for (i = 0; i < info->num_outputs; i++) {
5171 LLVMValueRef *out_ptr =
5172 ctx->soa.outputs[i];
5173
5174 for (chan = 0; chan < 4; chan++) {
5175 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5176 LLVMValueRef voffset =
5177 lp_build_const_int32(gallivm, (i * 4 + chan) *
5178 shader->selector->gs_max_out_vertices);
5179
5180 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5181 voffset = lp_build_mul_imm(uint, voffset, 4);
5182
5183 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5184
5185 build_tbuffer_store(ctx,
5186 ctx->gsvs_ring[stream],
5187 out_val, 1,
5188 voffset, soffset, 0,
5189 V_008F0C_BUF_DATA_FORMAT_32,
5190 V_008F0C_BUF_NUM_FORMAT_UINT,
5191 1, 0, 1, 1, 0);
5192 }
5193 }
5194 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5195 lp_build_const_int32(gallivm, 1));
5196
5197 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5198
5199 /* Signal vertex emission */
5200 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
5201 args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID);
5202 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5203 ctx->voidt, args, 2, 0);
5204 }
5205
5206 /* Cut one primitive from the geometry shader */
5207 static void si_llvm_emit_primitive(
5208 const struct lp_build_tgsi_action *action,
5209 struct lp_build_tgsi_context *bld_base,
5210 struct lp_build_emit_data *emit_data)
5211 {
5212 struct si_shader_context *ctx = si_shader_context(bld_base);
5213 struct gallivm_state *gallivm = bld_base->base.gallivm;
5214 LLVMValueRef args[2];
5215 unsigned stream;
5216
5217 /* Signal primitive cut */
5218 stream = si_llvm_get_stream(bld_base, emit_data);
5219 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
5220 args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID);
5221 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5222 ctx->voidt, args, 2, 0);
5223 }
5224
5225 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5226 struct lp_build_tgsi_context *bld_base,
5227 struct lp_build_emit_data *emit_data)
5228 {
5229 struct si_shader_context *ctx = si_shader_context(bld_base);
5230 struct gallivm_state *gallivm = bld_base->base.gallivm;
5231
5232 /* The real barrier instruction isn’t needed, because an entire patch
5233 * always fits into a single wave.
5234 */
5235 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
5236 emit_optimization_barrier(ctx);
5237 return;
5238 }
5239
5240 lp_build_intrinsic(gallivm->builder,
5241 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5242 : "llvm.AMDGPU.barrier.local",
5243 ctx->voidt, NULL, 0, 0);
5244 }
5245
5246 static const struct lp_build_tgsi_action tex_action = {
5247 .fetch_args = tex_fetch_args,
5248 .emit = build_tex_intrinsic,
5249 };
5250
5251 static const struct lp_build_tgsi_action interp_action = {
5252 .fetch_args = interp_fetch_args,
5253 .emit = build_interp_intrinsic,
5254 };
5255
5256 static void si_create_function(struct si_shader_context *ctx,
5257 const char *name,
5258 LLVMTypeRef *returns, unsigned num_returns,
5259 LLVMTypeRef *params, unsigned num_params,
5260 int last_sgpr)
5261 {
5262 int i;
5263
5264 si_llvm_create_func(ctx, name, returns, num_returns,
5265 params, num_params);
5266 si_llvm_shader_type(ctx->main_fn, ctx->type);
5267 ctx->return_value = LLVMGetUndef(ctx->return_type);
5268
5269 for (i = 0; i <= last_sgpr; ++i) {
5270 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
5271
5272 /* The combination of:
5273 * - ByVal
5274 * - dereferenceable
5275 * - invariant.load
5276 * allows the optimization passes to move loads and reduces
5277 * SGPR spilling significantly.
5278 */
5279 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
5280 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
5281 lp_add_attr_dereferenceable(P, UINT64_MAX);
5282 } else
5283 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
5284 }
5285
5286 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5287 /* These were copied from some LLVM test. */
5288 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5289 "less-precise-fpmad",
5290 "true");
5291 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5292 "no-infs-fp-math",
5293 "true");
5294 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5295 "no-nans-fp-math",
5296 "true");
5297 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5298 "unsafe-fp-math",
5299 "true");
5300 }
5301 }
5302
5303 static void create_meta_data(struct si_shader_context *ctx)
5304 {
5305 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
5306
5307 ctx->invariant_load_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5308 "invariant.load", 14);
5309 ctx->range_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5310 "range", 5);
5311 ctx->uniform_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5312 "amdgpu.uniform", 14);
5313
5314 ctx->empty_md = LLVMMDNodeInContext(gallivm->context, NULL, 0);
5315 }
5316
5317 static void declare_streamout_params(struct si_shader_context *ctx,
5318 struct pipe_stream_output_info *so,
5319 LLVMTypeRef *params, LLVMTypeRef i32,
5320 unsigned *num_params)
5321 {
5322 int i;
5323
5324 /* Streamout SGPRs. */
5325 if (so->num_outputs) {
5326 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5327 params[ctx->param_streamout_config = (*num_params)++] = i32;
5328 else
5329 ctx->param_streamout_config = ctx->param_tess_offchip;
5330
5331 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5332 }
5333 /* A streamout buffer offset is loaded if the stride is non-zero. */
5334 for (i = 0; i < 4; i++) {
5335 if (!so->stride[i])
5336 continue;
5337
5338 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5339 }
5340 }
5341
5342 static unsigned llvm_get_type_size(LLVMTypeRef type)
5343 {
5344 LLVMTypeKind kind = LLVMGetTypeKind(type);
5345
5346 switch (kind) {
5347 case LLVMIntegerTypeKind:
5348 return LLVMGetIntTypeWidth(type) / 8;
5349 case LLVMFloatTypeKind:
5350 return 4;
5351 case LLVMPointerTypeKind:
5352 return 8;
5353 case LLVMVectorTypeKind:
5354 return LLVMGetVectorSize(type) *
5355 llvm_get_type_size(LLVMGetElementType(type));
5356 case LLVMArrayTypeKind:
5357 return LLVMGetArrayLength(type) *
5358 llvm_get_type_size(LLVMGetElementType(type));
5359 default:
5360 assert(0);
5361 return 0;
5362 }
5363 }
5364
5365 static void declare_tess_lds(struct si_shader_context *ctx)
5366 {
5367 struct gallivm_state *gallivm = &ctx->gallivm;
5368 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
5369 struct lp_build_context *uint = &bld_base->uint_bld;
5370
5371 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5372 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, uint->zero,
5373 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
5374 "tess_lds");
5375 }
5376
5377 static unsigned si_get_max_workgroup_size(struct si_shader *shader)
5378 {
5379 const unsigned *properties = shader->selector->info.properties;
5380 unsigned max_work_group_size =
5381 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5382 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5383 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5384
5385 if (!max_work_group_size) {
5386 /* This is a variable group size compute shader,
5387 * compile it for the maximum possible group size.
5388 */
5389 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
5390 }
5391 return max_work_group_size;
5392 }
5393
5394 static void create_function(struct si_shader_context *ctx)
5395 {
5396 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
5397 struct gallivm_state *gallivm = bld_base->base.gallivm;
5398 struct si_shader *shader = ctx->shader;
5399 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
5400 LLVMTypeRef returns[16+32*4];
5401 unsigned i, last_sgpr, num_params, num_return_sgprs;
5402 unsigned num_returns = 0;
5403 unsigned num_prolog_vgprs = 0;
5404
5405 v3i32 = LLVMVectorType(ctx->i32, 3);
5406
5407 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5408 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5409 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5410 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5411 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5412
5413 switch (ctx->type) {
5414 case PIPE_SHADER_VERTEX:
5415 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
5416 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5417 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5418 params[SI_PARAM_DRAWID] = ctx->i32;
5419 num_params = SI_PARAM_DRAWID+1;
5420
5421 if (shader->key.as_es) {
5422 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5423 } else if (shader->key.as_ls) {
5424 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
5425 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
5426 } else {
5427 if (shader->is_gs_copy_shader) {
5428 num_params = SI_PARAM_RW_BUFFERS+1;
5429 } else {
5430 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5431 num_params = SI_PARAM_VS_STATE_BITS+1;
5432 }
5433
5434 /* The locations of the other parameters are assigned dynamically. */
5435 declare_streamout_params(ctx, &shader->selector->so,
5436 params, ctx->i32, &num_params);
5437 }
5438
5439 last_sgpr = num_params-1;
5440
5441 /* VGPRs */
5442 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5443 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5444 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5445 params[ctx->param_instance_id = num_params++] = ctx->i32;
5446
5447 if (!shader->is_gs_copy_shader) {
5448 /* Vertex load indices. */
5449 ctx->param_vertex_index0 = num_params;
5450
5451 for (i = 0; i < shader->selector->info.num_inputs; i++)
5452 params[num_params++] = ctx->i32;
5453
5454 num_prolog_vgprs += shader->selector->info.num_inputs;
5455
5456 /* PrimitiveID output. */
5457 if (!shader->key.as_es && !shader->key.as_ls)
5458 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5459 returns[num_returns++] = ctx->f32;
5460 }
5461 break;
5462
5463 case PIPE_SHADER_TESS_CTRL:
5464 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5465 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5466 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5467 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5468 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5469 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5470 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5471
5472 /* VGPRs */
5473 params[SI_PARAM_PATCH_ID] = ctx->i32;
5474 params[SI_PARAM_REL_IDS] = ctx->i32;
5475 num_params = SI_PARAM_REL_IDS+1;
5476
5477 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5478 * placed after the user SGPRs.
5479 */
5480 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5481 returns[num_returns++] = ctx->i32; /* SGPRs */
5482
5483 for (i = 0; i < 3; i++)
5484 returns[num_returns++] = ctx->f32; /* VGPRs */
5485 break;
5486
5487 case PIPE_SHADER_TESS_EVAL:
5488 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5489 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5490
5491 if (shader->key.as_es) {
5492 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5493 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5494 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5495 } else {
5496 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5497 declare_streamout_params(ctx, &shader->selector->so,
5498 params, ctx->i32, &num_params);
5499 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5500 }
5501 last_sgpr = num_params - 1;
5502
5503 /* VGPRs */
5504 params[ctx->param_tes_u = num_params++] = ctx->f32;
5505 params[ctx->param_tes_v = num_params++] = ctx->f32;
5506 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5507 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5508
5509 /* PrimitiveID output. */
5510 if (!shader->key.as_es)
5511 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5512 returns[num_returns++] = ctx->f32;
5513 break;
5514
5515 case PIPE_SHADER_GEOMETRY:
5516 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5517 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5518 last_sgpr = SI_PARAM_GS_WAVE_ID;
5519
5520 /* VGPRs */
5521 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5522 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5523 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5524 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5525 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5526 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5527 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5528 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5529 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5530 break;
5531
5532 case PIPE_SHADER_FRAGMENT:
5533 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5534 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5535 last_sgpr = SI_PARAM_PRIM_MASK;
5536 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5537 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5538 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5539 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5540 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5541 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5542 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5543 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5544 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5545 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5546 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5547 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5548 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5549 shader->info.face_vgpr_index = 20;
5550 params[SI_PARAM_ANCILLARY] = ctx->i32;
5551 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5552 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5553 num_params = SI_PARAM_POS_FIXED_PT+1;
5554
5555 /* Color inputs from the prolog. */
5556 if (shader->selector->info.colors_read) {
5557 unsigned num_color_elements =
5558 util_bitcount(shader->selector->info.colors_read);
5559
5560 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5561 for (i = 0; i < num_color_elements; i++)
5562 params[num_params++] = ctx->f32;
5563
5564 num_prolog_vgprs += num_color_elements;
5565 }
5566
5567 /* Outputs for the epilog. */
5568 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5569 num_returns =
5570 num_return_sgprs +
5571 util_bitcount(shader->selector->info.colors_written) * 4 +
5572 shader->selector->info.writes_z +
5573 shader->selector->info.writes_stencil +
5574 shader->selector->info.writes_samplemask +
5575 1 /* SampleMaskIn */;
5576
5577 num_returns = MAX2(num_returns,
5578 num_return_sgprs +
5579 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5580
5581 for (i = 0; i < num_return_sgprs; i++)
5582 returns[i] = ctx->i32;
5583 for (; i < num_returns; i++)
5584 returns[i] = ctx->f32;
5585 break;
5586
5587 case PIPE_SHADER_COMPUTE:
5588 params[SI_PARAM_GRID_SIZE] = v3i32;
5589 params[SI_PARAM_BLOCK_SIZE] = v3i32;
5590 params[SI_PARAM_BLOCK_ID] = v3i32;
5591 last_sgpr = SI_PARAM_BLOCK_ID;
5592
5593 params[SI_PARAM_THREAD_ID] = v3i32;
5594 num_params = SI_PARAM_THREAD_ID + 1;
5595 break;
5596 default:
5597 assert(0 && "unimplemented shader");
5598 return;
5599 }
5600
5601 assert(num_params <= ARRAY_SIZE(params));
5602
5603 si_create_function(ctx, "main", returns, num_returns, params,
5604 num_params, last_sgpr);
5605
5606 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5607 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5608 ctx->separate_prolog) {
5609 si_llvm_add_attribute(ctx->main_fn,
5610 "InitialPSInputAddr",
5611 S_0286D0_PERSP_SAMPLE_ENA(1) |
5612 S_0286D0_PERSP_CENTER_ENA(1) |
5613 S_0286D0_PERSP_CENTROID_ENA(1) |
5614 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5615 S_0286D0_LINEAR_CENTER_ENA(1) |
5616 S_0286D0_LINEAR_CENTROID_ENA(1) |
5617 S_0286D0_FRONT_FACE_ENA(1) |
5618 S_0286D0_POS_FIXED_PT_ENA(1));
5619 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5620 si_llvm_add_attribute(ctx->main_fn,
5621 "amdgpu-max-work-group-size",
5622 si_get_max_workgroup_size(shader));
5623 }
5624
5625 shader->info.num_input_sgprs = 0;
5626 shader->info.num_input_vgprs = 0;
5627
5628 for (i = 0; i <= last_sgpr; ++i)
5629 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5630
5631 for (; i < num_params; ++i)
5632 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5633
5634 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5635 shader->info.num_input_vgprs -= num_prolog_vgprs;
5636
5637 if (!ctx->screen->has_ds_bpermute &&
5638 bld_base->info &&
5639 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5640 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5641 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5642 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5643 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5644 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5645 ctx->lds =
5646 LLVMAddGlobalInAddressSpace(gallivm->module,
5647 LLVMArrayType(ctx->i32, 64),
5648 "ddxy_lds",
5649 LOCAL_ADDR_SPACE);
5650
5651 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.as_ls) ||
5652 ctx->type == PIPE_SHADER_TESS_CTRL ||
5653 ctx->type == PIPE_SHADER_TESS_EVAL)
5654 declare_tess_lds(ctx);
5655 }
5656
5657 /**
5658 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5659 * for later use.
5660 */
5661 static void preload_ring_buffers(struct si_shader_context *ctx)
5662 {
5663 struct gallivm_state *gallivm =
5664 ctx->soa.bld_base.base.gallivm;
5665
5666 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5667 SI_PARAM_RW_BUFFERS);
5668
5669 if ((ctx->type == PIPE_SHADER_VERTEX &&
5670 ctx->shader->key.as_es) ||
5671 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5672 ctx->shader->key.as_es) ||
5673 ctx->type == PIPE_SHADER_GEOMETRY) {
5674 unsigned ring =
5675 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5676 : SI_ES_RING_ESGS;
5677 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5678
5679 ctx->esgs_ring =
5680 build_indexed_load_const(ctx, buf_ptr, offset);
5681 }
5682
5683 if (ctx->shader->is_gs_copy_shader) {
5684 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_VS_RING_GSVS);
5685
5686 ctx->gsvs_ring[0] =
5687 build_indexed_load_const(ctx, buf_ptr, offset);
5688 }
5689 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5690 int i;
5691 for (i = 0; i < 4; i++) {
5692 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_GS_RING_GSVS0 + i);
5693
5694 ctx->gsvs_ring[i] =
5695 build_indexed_load_const(ctx, buf_ptr, offset);
5696 }
5697 }
5698 }
5699
5700 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5701 LLVMValueRef param_rw_buffers,
5702 unsigned param_pos_fixed_pt)
5703 {
5704 struct lp_build_tgsi_context *bld_base =
5705 &ctx->soa.bld_base;
5706 struct gallivm_state *gallivm = bld_base->base.gallivm;
5707 LLVMBuilderRef builder = gallivm->builder;
5708 LLVMValueRef slot, desc, offset, row, bit, address[2];
5709
5710 /* Use the fixed-point gl_FragCoord input.
5711 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5712 * per coordinate to get the repeating effect.
5713 */
5714 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5715 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5716
5717 /* Load the buffer descriptor. */
5718 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
5719 desc = build_indexed_load_const(ctx, param_rw_buffers, slot);
5720
5721 /* The stipple pattern is 32x32, each row has 32 bits. */
5722 offset = LLVMBuildMul(builder, address[1],
5723 LLVMConstInt(ctx->i32, 4, 0), "");
5724 row = buffer_load_const(ctx, desc, offset);
5725 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
5726 bit = LLVMBuildLShr(builder, row, address[0], "");
5727 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5728
5729 /* The intrinsic kills the thread if arg < 0. */
5730 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
5731 LLVMConstReal(ctx->f32, -1), "");
5732 lp_build_intrinsic(builder, "llvm.AMDGPU.kill", ctx->voidt, &bit, 1, 0);
5733 }
5734
5735 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
5736 struct si_shader_config *conf,
5737 unsigned symbol_offset)
5738 {
5739 unsigned i;
5740 const unsigned char *config =
5741 radeon_shader_binary_config_start(binary, symbol_offset);
5742 bool really_needs_scratch = false;
5743
5744 /* LLVM adds SGPR spills to the scratch size.
5745 * Find out if we really need the scratch buffer.
5746 */
5747 for (i = 0; i < binary->reloc_count; i++) {
5748 const struct radeon_shader_reloc *reloc = &binary->relocs[i];
5749
5750 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5751 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5752 really_needs_scratch = true;
5753 break;
5754 }
5755 }
5756
5757 /* XXX: We may be able to emit some of these values directly rather than
5758 * extracting fields to be emitted later.
5759 */
5760
5761 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5762 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5763 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5764 switch (reg) {
5765 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5766 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5767 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5768 case R_00B848_COMPUTE_PGM_RSRC1:
5769 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5770 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5771 conf->float_mode = G_00B028_FLOAT_MODE(value);
5772 conf->rsrc1 = value;
5773 break;
5774 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5775 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5776 break;
5777 case R_00B84C_COMPUTE_PGM_RSRC2:
5778 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5779 conf->rsrc2 = value;
5780 break;
5781 case R_0286CC_SPI_PS_INPUT_ENA:
5782 conf->spi_ps_input_ena = value;
5783 break;
5784 case R_0286D0_SPI_PS_INPUT_ADDR:
5785 conf->spi_ps_input_addr = value;
5786 break;
5787 case R_0286E8_SPI_TMPRING_SIZE:
5788 case R_00B860_COMPUTE_TMPRING_SIZE:
5789 /* WAVESIZE is in units of 256 dwords. */
5790 if (really_needs_scratch)
5791 conf->scratch_bytes_per_wave =
5792 G_00B860_WAVESIZE(value) * 256 * 4;
5793 break;
5794 case 0x4: /* SPILLED_SGPRS */
5795 conf->spilled_sgprs = value;
5796 break;
5797 case 0x8: /* SPILLED_VGPRS */
5798 conf->spilled_vgprs = value;
5799 break;
5800 default:
5801 {
5802 static bool printed;
5803
5804 if (!printed) {
5805 fprintf(stderr, "Warning: LLVM emitted unknown "
5806 "config register: 0x%x\n", reg);
5807 printed = true;
5808 }
5809 }
5810 break;
5811 }
5812 }
5813
5814 if (!conf->spi_ps_input_addr)
5815 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5816 }
5817
5818 void si_shader_apply_scratch_relocs(struct si_context *sctx,
5819 struct si_shader *shader,
5820 struct si_shader_config *config,
5821 uint64_t scratch_va)
5822 {
5823 unsigned i;
5824 uint32_t scratch_rsrc_dword0 = scratch_va;
5825 uint32_t scratch_rsrc_dword1 =
5826 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5827
5828 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
5829 * correctly.
5830 */
5831 if (HAVE_LLVM >= 0x0309)
5832 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5833 else
5834 scratch_rsrc_dword1 |=
5835 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
5836
5837 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5838 const struct radeon_shader_reloc *reloc =
5839 &shader->binary.relocs[i];
5840 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5841 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5842 &scratch_rsrc_dword0, 4);
5843 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5844 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5845 &scratch_rsrc_dword1, 4);
5846 }
5847 }
5848 }
5849
5850 static unsigned si_get_shader_binary_size(struct si_shader *shader)
5851 {
5852 unsigned size = shader->binary.code_size;
5853
5854 if (shader->prolog)
5855 size += shader->prolog->binary.code_size;
5856 if (shader->epilog)
5857 size += shader->epilog->binary.code_size;
5858 return size;
5859 }
5860
5861 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5862 {
5863 const struct radeon_shader_binary *prolog =
5864 shader->prolog ? &shader->prolog->binary : NULL;
5865 const struct radeon_shader_binary *epilog =
5866 shader->epilog ? &shader->epilog->binary : NULL;
5867 const struct radeon_shader_binary *mainb = &shader->binary;
5868 unsigned bo_size = si_get_shader_binary_size(shader) +
5869 (!epilog ? mainb->rodata_size : 0);
5870 unsigned char *ptr;
5871
5872 assert(!prolog || !prolog->rodata_size);
5873 assert((!prolog && !epilog) || !mainb->rodata_size);
5874 assert(!epilog || !epilog->rodata_size);
5875
5876 r600_resource_reference(&shader->bo, NULL);
5877 shader->bo = (struct r600_resource*)
5878 pipe_buffer_create(&sscreen->b.b, 0,
5879 PIPE_USAGE_IMMUTABLE, bo_size);
5880 if (!shader->bo)
5881 return -ENOMEM;
5882
5883 /* Upload. */
5884 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
5885 PIPE_TRANSFER_READ_WRITE);
5886
5887 if (prolog) {
5888 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
5889 ptr += prolog->code_size;
5890 }
5891
5892 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
5893 ptr += mainb->code_size;
5894
5895 if (epilog)
5896 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
5897 else if (mainb->rodata_size > 0)
5898 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
5899
5900 sscreen->b.ws->buffer_unmap(shader->bo->buf);
5901 return 0;
5902 }
5903
5904 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
5905 struct pipe_debug_callback *debug,
5906 const char *name, FILE *file)
5907 {
5908 char *line, *p;
5909 unsigned i, count;
5910
5911 if (binary->disasm_string) {
5912 fprintf(file, "Shader %s disassembly:\n", name);
5913 fprintf(file, "%s", binary->disasm_string);
5914
5915 if (debug && debug->debug_message) {
5916 /* Very long debug messages are cut off, so send the
5917 * disassembly one line at a time. This causes more
5918 * overhead, but on the plus side it simplifies
5919 * parsing of resulting logs.
5920 */
5921 pipe_debug_message(debug, SHADER_INFO,
5922 "Shader Disassembly Begin");
5923
5924 line = binary->disasm_string;
5925 while (*line) {
5926 p = util_strchrnul(line, '\n');
5927 count = p - line;
5928
5929 if (count) {
5930 pipe_debug_message(debug, SHADER_INFO,
5931 "%.*s", count, line);
5932 }
5933
5934 if (!*p)
5935 break;
5936 line = p + 1;
5937 }
5938
5939 pipe_debug_message(debug, SHADER_INFO,
5940 "Shader Disassembly End");
5941 }
5942 } else {
5943 fprintf(file, "Shader %s binary:\n", name);
5944 for (i = 0; i < binary->code_size; i += 4) {
5945 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5946 binary->code[i + 3], binary->code[i + 2],
5947 binary->code[i + 1], binary->code[i]);
5948 }
5949 }
5950 }
5951
5952 static void si_shader_dump_stats(struct si_screen *sscreen,
5953 struct si_shader_config *conf,
5954 unsigned num_inputs,
5955 unsigned code_size,
5956 struct pipe_debug_callback *debug,
5957 unsigned processor,
5958 FILE *file)
5959 {
5960 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
5961 unsigned lds_per_wave = 0;
5962 unsigned max_simd_waves = 10;
5963
5964 /* Compute LDS usage for PS. */
5965 if (processor == PIPE_SHADER_FRAGMENT) {
5966 /* The minimum usage per wave is (num_inputs * 48). The maximum
5967 * usage is (num_inputs * 48 * 16).
5968 * We can get anything in between and it varies between waves.
5969 *
5970 * The 48 bytes per input for a single primitive is equal to
5971 * 4 bytes/component * 4 components/input * 3 points.
5972 *
5973 * Other stages don't know the size at compile time or don't
5974 * allocate LDS per wave, but instead they do it per thread group.
5975 */
5976 lds_per_wave = conf->lds_size * lds_increment +
5977 align(num_inputs * 48, lds_increment);
5978 }
5979
5980 /* Compute the per-SIMD wave counts. */
5981 if (conf->num_sgprs) {
5982 if (sscreen->b.chip_class >= VI)
5983 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5984 else
5985 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5986 }
5987
5988 if (conf->num_vgprs)
5989 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5990
5991 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
5992 * that PS can use.
5993 */
5994 if (lds_per_wave)
5995 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5996
5997 if (file != stderr ||
5998 r600_can_dump_shader(&sscreen->b, processor)) {
5999 if (processor == PIPE_SHADER_FRAGMENT) {
6000 fprintf(file, "*** SHADER CONFIG ***\n"
6001 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6002 "SPI_PS_INPUT_ENA = 0x%04x\n",
6003 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
6004 }
6005
6006 fprintf(file, "*** SHADER STATS ***\n"
6007 "SGPRS: %d\n"
6008 "VGPRS: %d\n"
6009 "Spilled SGPRs: %d\n"
6010 "Spilled VGPRs: %d\n"
6011 "Private memory VGPRs: %d\n"
6012 "Code Size: %d bytes\n"
6013 "LDS: %d blocks\n"
6014 "Scratch: %d bytes per wave\n"
6015 "Max Waves: %d\n"
6016 "********************\n\n\n",
6017 conf->num_sgprs, conf->num_vgprs,
6018 conf->spilled_sgprs, conf->spilled_vgprs,
6019 conf->private_mem_vgprs, code_size,
6020 conf->lds_size, conf->scratch_bytes_per_wave,
6021 max_simd_waves);
6022 }
6023
6024 pipe_debug_message(debug, SHADER_INFO,
6025 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6026 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
6027 "Spilled VGPRs: %d PrivMem VGPRs: %d",
6028 conf->num_sgprs, conf->num_vgprs, code_size,
6029 conf->lds_size, conf->scratch_bytes_per_wave,
6030 max_simd_waves, conf->spilled_sgprs,
6031 conf->spilled_vgprs, conf->private_mem_vgprs);
6032 }
6033
6034 static const char *si_get_shader_name(struct si_shader *shader,
6035 unsigned processor)
6036 {
6037 switch (processor) {
6038 case PIPE_SHADER_VERTEX:
6039 if (shader->key.as_es)
6040 return "Vertex Shader as ES";
6041 else if (shader->key.as_ls)
6042 return "Vertex Shader as LS";
6043 else
6044 return "Vertex Shader as VS";
6045 case PIPE_SHADER_TESS_CTRL:
6046 return "Tessellation Control Shader";
6047 case PIPE_SHADER_TESS_EVAL:
6048 if (shader->key.as_es)
6049 return "Tessellation Evaluation Shader as ES";
6050 else
6051 return "Tessellation Evaluation Shader as VS";
6052 case PIPE_SHADER_GEOMETRY:
6053 if (shader->is_gs_copy_shader)
6054 return "GS Copy Shader as VS";
6055 else
6056 return "Geometry Shader";
6057 case PIPE_SHADER_FRAGMENT:
6058 return "Pixel Shader";
6059 case PIPE_SHADER_COMPUTE:
6060 return "Compute Shader";
6061 default:
6062 return "Unknown Shader";
6063 }
6064 }
6065
6066 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6067 struct pipe_debug_callback *debug, unsigned processor,
6068 FILE *file)
6069 {
6070 if (file != stderr ||
6071 r600_can_dump_shader(&sscreen->b, processor))
6072 si_dump_shader_key(processor, &shader->key, file);
6073
6074 if (file != stderr && shader->binary.llvm_ir_string) {
6075 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
6076 si_get_shader_name(shader, processor));
6077 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
6078 }
6079
6080 if (file != stderr ||
6081 (r600_can_dump_shader(&sscreen->b, processor) &&
6082 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6083 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6084
6085 if (shader->prolog)
6086 si_shader_dump_disassembly(&shader->prolog->binary,
6087 debug, "prolog", file);
6088
6089 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6090
6091 if (shader->epilog)
6092 si_shader_dump_disassembly(&shader->epilog->binary,
6093 debug, "epilog", file);
6094 fprintf(file, "\n");
6095 }
6096
6097 si_shader_dump_stats(sscreen, &shader->config,
6098 shader->selector ? shader->selector->info.num_inputs : 0,
6099 si_get_shader_binary_size(shader), debug, processor,
6100 file);
6101 }
6102
6103 int si_compile_llvm(struct si_screen *sscreen,
6104 struct radeon_shader_binary *binary,
6105 struct si_shader_config *conf,
6106 LLVMTargetMachineRef tm,
6107 LLVMModuleRef mod,
6108 struct pipe_debug_callback *debug,
6109 unsigned processor,
6110 const char *name)
6111 {
6112 int r = 0;
6113 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6114
6115 if (r600_can_dump_shader(&sscreen->b, processor)) {
6116 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6117
6118 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6119 fprintf(stderr, "%s LLVM IR:\n\n", name);
6120 LLVMDumpModule(mod);
6121 fprintf(stderr, "\n");
6122 }
6123 }
6124
6125 if (sscreen->record_llvm_ir) {
6126 char *ir = LLVMPrintModuleToString(mod);
6127 binary->llvm_ir_string = strdup(ir);
6128 LLVMDisposeMessage(ir);
6129 }
6130
6131 if (!si_replace_shader(count, binary)) {
6132 r = si_llvm_compile(mod, binary, tm, debug);
6133 if (r)
6134 return r;
6135 }
6136
6137 si_shader_binary_read_config(binary, conf, 0);
6138
6139 /* Enable 64-bit and 16-bit denormals, because there is no performance
6140 * cost.
6141 *
6142 * If denormals are enabled, all floating-point output modifiers are
6143 * ignored.
6144 *
6145 * Don't enable denormals for 32-bit floats, because:
6146 * - Floating-point output modifiers would be ignored by the hw.
6147 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6148 * have to stop using those.
6149 * - SI & CI would be very slow.
6150 */
6151 conf->float_mode |= V_00B028_FP_64_DENORMS;
6152
6153 FREE(binary->config);
6154 FREE(binary->global_symbol_offsets);
6155 binary->config = NULL;
6156 binary->global_symbol_offsets = NULL;
6157
6158 /* Some shaders can't have rodata because their binaries can be
6159 * concatenated.
6160 */
6161 if (binary->rodata_size &&
6162 (processor == PIPE_SHADER_VERTEX ||
6163 processor == PIPE_SHADER_TESS_CTRL ||
6164 processor == PIPE_SHADER_TESS_EVAL ||
6165 processor == PIPE_SHADER_FRAGMENT)) {
6166 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6167 return -EINVAL;
6168 }
6169
6170 return r;
6171 }
6172
6173 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6174 {
6175 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6176 LLVMBuildRetVoid(ctx->gallivm.builder);
6177 else
6178 LLVMBuildRet(ctx->gallivm.builder, ret);
6179 }
6180
6181 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6182 struct si_shader *
6183 si_generate_gs_copy_shader(struct si_screen *sscreen,
6184 LLVMTargetMachineRef tm,
6185 struct si_shader_selector *gs_selector,
6186 struct pipe_debug_callback *debug)
6187 {
6188 struct si_shader_context ctx;
6189 struct si_shader *shader;
6190 struct gallivm_state *gallivm = &ctx.gallivm;
6191 struct lp_build_tgsi_context *bld_base = &ctx.soa.bld_base;
6192 struct lp_build_context *uint = &bld_base->uint_bld;
6193 struct si_shader_output_values *outputs;
6194 struct tgsi_shader_info *gsinfo = &gs_selector->info;
6195 LLVMValueRef args[9];
6196 int i, r;
6197
6198 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6199
6200 if (!outputs)
6201 return NULL;
6202
6203 shader = CALLOC_STRUCT(si_shader);
6204 if (!shader) {
6205 FREE(outputs);
6206 return NULL;
6207 }
6208
6209
6210 shader->selector = gs_selector;
6211 shader->is_gs_copy_shader = true;
6212
6213 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6214 ctx.type = PIPE_SHADER_VERTEX;
6215
6216 create_meta_data(&ctx);
6217 create_function(&ctx);
6218 preload_ring_buffers(&ctx);
6219
6220 args[0] = ctx.gsvs_ring[0];
6221 args[1] = lp_build_mul_imm(uint,
6222 LLVMGetParam(ctx.main_fn,
6223 ctx.param_vertex_id),
6224 4);
6225 args[3] = uint->zero;
6226 args[4] = uint->one; /* OFFEN */
6227 args[5] = uint->zero; /* IDXEN */
6228 args[6] = uint->one; /* GLC */
6229 args[7] = uint->one; /* SLC */
6230 args[8] = uint->zero; /* TFE */
6231
6232 /* Fetch vertex data from GSVS ring */
6233 for (i = 0; i < gsinfo->num_outputs; ++i) {
6234 unsigned chan;
6235
6236 outputs[i].name = gsinfo->output_semantic_name[i];
6237 outputs[i].sid = gsinfo->output_semantic_index[i];
6238
6239 for (chan = 0; chan < 4; chan++) {
6240 args[2] = lp_build_const_int32(gallivm,
6241 (i * 4 + chan) *
6242 gs_selector->gs_max_out_vertices * 16 * 4);
6243
6244 outputs[i].values[chan] =
6245 LLVMBuildBitCast(gallivm->builder,
6246 lp_build_intrinsic(gallivm->builder,
6247 "llvm.SI.buffer.load.dword.i32.i32",
6248 ctx.i32, args, 9,
6249 LP_FUNC_ATTR_READONLY),
6250 ctx.f32, "");
6251 }
6252 }
6253
6254 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6255
6256 LLVMBuildRetVoid(gallivm->builder);
6257
6258 /* Dump LLVM IR before any optimization passes */
6259 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6260 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6261 LLVMDumpModule(bld_base->base.gallivm->module);
6262
6263 si_llvm_finalize_module(&ctx,
6264 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_GEOMETRY));
6265
6266 r = si_compile_llvm(sscreen, &ctx.shader->binary,
6267 &ctx.shader->config, ctx.tm,
6268 bld_base->base.gallivm->module,
6269 debug, PIPE_SHADER_GEOMETRY,
6270 "GS Copy Shader");
6271 if (!r) {
6272 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6273 fprintf(stderr, "GS Copy Shader:\n");
6274 si_shader_dump(sscreen, ctx.shader, debug,
6275 PIPE_SHADER_GEOMETRY, stderr);
6276 r = si_shader_binary_upload(sscreen, ctx.shader);
6277 }
6278
6279 si_llvm_dispose(&ctx);
6280
6281 FREE(outputs);
6282
6283 if (r != 0) {
6284 FREE(shader);
6285 shader = NULL;
6286 }
6287 return shader;
6288 }
6289
6290 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
6291 FILE *f)
6292 {
6293 int i;
6294
6295 fprintf(f, "SHADER KEY\n");
6296
6297 switch (shader) {
6298 case PIPE_SHADER_VERTEX:
6299 fprintf(f, " part.vs.prolog.instance_divisors = {");
6300 for (i = 0; i < ARRAY_SIZE(key->part.vs.prolog.instance_divisors); i++)
6301 fprintf(f, !i ? "%u" : ", %u",
6302 key->part.vs.prolog.instance_divisors[i]);
6303 fprintf(f, "}\n");
6304 fprintf(f, " part.vs.epilog.export_prim_id = %u\n", key->part.vs.epilog.export_prim_id);
6305 fprintf(f, " as_es = %u\n", key->as_es);
6306 fprintf(f, " as_ls = %u\n", key->as_ls);
6307 fprintf(f, " mono.vs.fix_fetch = 0x%x\n", key->mono.vs.fix_fetch);
6308 break;
6309
6310 case PIPE_SHADER_TESS_CTRL:
6311 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
6312 fprintf(f, " mono.tcs.inputs_to_copy = 0x%"PRIx64"\n", key->mono.tcs.inputs_to_copy);
6313 break;
6314
6315 case PIPE_SHADER_TESS_EVAL:
6316 fprintf(f, " part.tes.epilog.export_prim_id = %u\n", key->part.tes.epilog.export_prim_id);
6317 fprintf(f, " as_es = %u\n", key->as_es);
6318 break;
6319
6320 case PIPE_SHADER_GEOMETRY:
6321 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
6322 break;
6323
6324 case PIPE_SHADER_COMPUTE:
6325 break;
6326
6327 case PIPE_SHADER_FRAGMENT:
6328 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
6329 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
6330 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
6331 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
6332 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
6333 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
6334 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
6335 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
6336 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
6337 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
6338 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
6339 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
6340 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
6341 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
6342 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
6343 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
6344 break;
6345
6346 default:
6347 assert(0);
6348 }
6349
6350 if ((shader == PIPE_SHADER_GEOMETRY ||
6351 shader == PIPE_SHADER_TESS_EVAL ||
6352 shader == PIPE_SHADER_VERTEX) &&
6353 !key->as_es && !key->as_ls) {
6354 fprintf(f, " opt.hw_vs.kill_outputs = 0x%"PRIx64"\n", key->opt.hw_vs.kill_outputs);
6355 fprintf(f, " opt.hw_vs.kill_outputs2 = 0x%x\n", key->opt.hw_vs.kill_outputs2);
6356 fprintf(f, " opt.hw_vs.clip_disable = %u\n", key->opt.hw_vs.clip_disable);
6357 }
6358 }
6359
6360 static void si_init_shader_ctx(struct si_shader_context *ctx,
6361 struct si_screen *sscreen,
6362 struct si_shader *shader,
6363 LLVMTargetMachineRef tm)
6364 {
6365 struct lp_build_tgsi_context *bld_base;
6366 struct lp_build_tgsi_action tmpl = {};
6367
6368 si_llvm_context_init(ctx, sscreen, shader, tm,
6369 (shader && shader->selector) ? &shader->selector->info : NULL,
6370 (shader && shader->selector) ? shader->selector->tokens : NULL);
6371
6372 bld_base = &ctx->soa.bld_base;
6373 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6374
6375 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6376 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6377 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6378
6379 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6380 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6381 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6382 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6383 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6384 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6385 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6386 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6387 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6388 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6389 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6390 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6391 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6392 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6393
6394 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6395 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6396 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6397 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6398 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6399 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6400
6401 tmpl.fetch_args = atomic_fetch_args;
6402 tmpl.emit = atomic_emit;
6403 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6404 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6405 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6406 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6407 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6408 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6409 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6410 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6411 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6412 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6413 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6414 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6415 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6416 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6417 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6418 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6419 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6420 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6421 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6422 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6423
6424 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6425
6426 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6427 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6428 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6429 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6430
6431 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6432 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6433 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6434 }
6435
6436 /* Return true if the PARAM export has been eliminated. */
6437 static bool si_eliminate_const_output(struct si_shader_context *ctx,
6438 LLVMValueRef inst, unsigned offset)
6439 {
6440 struct si_shader *shader = ctx->shader;
6441 unsigned num_outputs = shader->selector->info.num_outputs;
6442 unsigned i, default_val; /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL */
6443 bool is_zero[4] = {}, is_one[4] = {};
6444
6445 for (i = 0; i < 4; i++) {
6446 LLVMBool loses_info;
6447 LLVMValueRef p = LLVMGetOperand(inst, 5 + i);
6448
6449 /* It's a constant expression. Undef outputs are eliminated too. */
6450 if (LLVMIsUndef(p)) {
6451 is_zero[i] = true;
6452 is_one[i] = true;
6453 } else if (LLVMIsAConstantFP(p)) {
6454 double a = LLVMConstRealGetDouble(p, &loses_info);
6455
6456 if (a == 0)
6457 is_zero[i] = true;
6458 else if (a == 1)
6459 is_one[i] = true;
6460 else
6461 return false; /* other constant */
6462 } else
6463 return false;
6464 }
6465
6466 /* Only certain combinations of 0 and 1 can be eliminated. */
6467 if (is_zero[0] && is_zero[1] && is_zero[2])
6468 default_val = is_zero[3] ? 0 : 1;
6469 else if (is_one[0] && is_one[1] && is_one[2])
6470 default_val = is_zero[3] ? 2 : 3;
6471 else
6472 return false;
6473
6474 /* The PARAM export can be represented as DEFAULT_VAL. Kill it. */
6475 LLVMInstructionEraseFromParent(inst);
6476
6477 /* Change OFFSET to DEFAULT_VAL. */
6478 for (i = 0; i < num_outputs; i++) {
6479 if (shader->info.vs_output_param_offset[i] == offset) {
6480 shader->info.vs_output_param_offset[i] =
6481 EXP_PARAM_DEFAULT_VAL_0000 + default_val;
6482 break;
6483 }
6484 }
6485 return true;
6486 }
6487
6488 struct si_vs_exports {
6489 unsigned num;
6490 unsigned offset[SI_MAX_VS_OUTPUTS];
6491 LLVMValueRef inst[SI_MAX_VS_OUTPUTS];
6492 };
6493
6494 static void si_eliminate_const_vs_outputs(struct si_shader_context *ctx)
6495 {
6496 struct si_shader *shader = ctx->shader;
6497 struct tgsi_shader_info *info = &shader->selector->info;
6498 LLVMBasicBlockRef bb;
6499 struct si_vs_exports exports;
6500 bool removed_any = false;
6501
6502 exports.num = 0;
6503
6504 if (ctx->type == PIPE_SHADER_FRAGMENT ||
6505 ctx->type == PIPE_SHADER_COMPUTE ||
6506 shader->key.as_es ||
6507 shader->key.as_ls)
6508 return;
6509
6510 /* Process all LLVM instructions. */
6511 bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6512 while (bb) {
6513 LLVMValueRef inst = LLVMGetFirstInstruction(bb);
6514
6515 while (inst) {
6516 LLVMValueRef cur = inst;
6517 inst = LLVMGetNextInstruction(inst);
6518
6519 if (LLVMGetInstructionOpcode(cur) != LLVMCall)
6520 continue;
6521
6522 LLVMValueRef callee = lp_get_called_value(cur);
6523
6524 if (!lp_is_function(callee))
6525 continue;
6526
6527 const char *name = LLVMGetValueName(callee);
6528 unsigned num_args = LLVMCountParams(callee);
6529
6530 /* Check if this is an export instruction. */
6531 if (num_args != 9 || strcmp(name, "llvm.SI.export"))
6532 continue;
6533
6534 LLVMValueRef arg = LLVMGetOperand(cur, 3);
6535 unsigned target = LLVMConstIntGetZExtValue(arg);
6536
6537 if (target < V_008DFC_SQ_EXP_PARAM)
6538 continue;
6539
6540 target -= V_008DFC_SQ_EXP_PARAM;
6541
6542 /* Eliminate constant value PARAM exports. */
6543 if (si_eliminate_const_output(ctx, cur, target)) {
6544 removed_any = true;
6545 } else {
6546 exports.offset[exports.num] = target;
6547 exports.inst[exports.num] = cur;
6548 exports.num++;
6549 }
6550 }
6551 bb = LLVMGetNextBasicBlock(bb);
6552 }
6553
6554 /* Remove holes in export memory due to removed PARAM exports.
6555 * This is done by renumbering all PARAM exports.
6556 */
6557 if (removed_any) {
6558 ubyte current_offset[SI_MAX_VS_OUTPUTS];
6559 unsigned new_count = 0;
6560 unsigned out, i;
6561
6562 /* Make a copy of the offsets. We need the old version while
6563 * we are modifying some of them. */
6564 assert(sizeof(current_offset) ==
6565 sizeof(shader->info.vs_output_param_offset));
6566 memcpy(current_offset, shader->info.vs_output_param_offset,
6567 sizeof(current_offset));
6568
6569 for (i = 0; i < exports.num; i++) {
6570 unsigned offset = exports.offset[i];
6571
6572 for (out = 0; out < info->num_outputs; out++) {
6573 if (current_offset[out] != offset)
6574 continue;
6575
6576 LLVMSetOperand(exports.inst[i], 3,
6577 LLVMConstInt(ctx->i32,
6578 V_008DFC_SQ_EXP_PARAM + new_count, 0));
6579 shader->info.vs_output_param_offset[out] = new_count;
6580 new_count++;
6581 break;
6582 }
6583 }
6584 shader->info.nr_param_exports = new_count;
6585 }
6586 }
6587
6588 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
6589 {
6590 ctx->shader->config.private_mem_vgprs = 0;
6591
6592 /* Process all LLVM instructions. */
6593 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6594 while (bb) {
6595 LLVMValueRef next = LLVMGetFirstInstruction(bb);
6596
6597 while (next) {
6598 LLVMValueRef inst = next;
6599 next = LLVMGetNextInstruction(next);
6600
6601 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
6602 continue;
6603
6604 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
6605 /* No idea why LLVM aligns allocas to 4 elements. */
6606 unsigned alignment = LLVMGetAlignment(inst);
6607 unsigned dw_size = align(llvm_get_type_size(type) / 4, alignment);
6608 ctx->shader->config.private_mem_vgprs += dw_size;
6609 }
6610 bb = LLVMGetNextBasicBlock(bb);
6611 }
6612 }
6613
6614 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
6615 struct si_shader *shader)
6616 {
6617 struct si_shader_selector *sel = shader->selector;
6618 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
6619
6620 switch (ctx->type) {
6621 case PIPE_SHADER_VERTEX:
6622 ctx->load_input = declare_input_vs;
6623 if (shader->key.as_ls)
6624 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6625 else if (shader->key.as_es)
6626 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6627 else
6628 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6629 break;
6630 case PIPE_SHADER_TESS_CTRL:
6631 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6632 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6633 bld_base->emit_store = store_output_tcs;
6634 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6635 break;
6636 case PIPE_SHADER_TESS_EVAL:
6637 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6638 if (shader->key.as_es)
6639 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6640 else
6641 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6642 break;
6643 case PIPE_SHADER_GEOMETRY:
6644 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6645 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6646 break;
6647 case PIPE_SHADER_FRAGMENT:
6648 ctx->load_input = declare_input_fs;
6649 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6650 break;
6651 case PIPE_SHADER_COMPUTE:
6652 ctx->declare_memory_region = declare_compute_memory;
6653 break;
6654 default:
6655 assert(!"Unsupported shader type");
6656 return false;
6657 }
6658
6659 create_meta_data(ctx);
6660 create_function(ctx);
6661 preload_ring_buffers(ctx);
6662
6663 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6664 int i;
6665 for (i = 0; i < 4; i++) {
6666 ctx->gs_next_vertex[i] =
6667 lp_build_alloca(bld_base->base.gallivm,
6668 ctx->i32, "");
6669 }
6670 }
6671
6672 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6673 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6674 return false;
6675 }
6676
6677 si_llvm_build_ret(ctx, ctx->return_value);
6678 return true;
6679 }
6680
6681 /**
6682 * Compute the VS prolog key, which contains all the information needed to
6683 * build the VS prolog function, and set shader->info bits where needed.
6684 */
6685 static void si_get_vs_prolog_key(struct si_shader *shader,
6686 union si_shader_part_key *key)
6687 {
6688 struct tgsi_shader_info *info = &shader->selector->info;
6689
6690 memset(key, 0, sizeof(*key));
6691 key->vs_prolog.states = shader->key.part.vs.prolog;
6692 key->vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6693 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6694
6695 /* Set the instanceID flag. */
6696 for (unsigned i = 0; i < info->num_inputs; i++)
6697 if (key->vs_prolog.states.instance_divisors[i])
6698 shader->info.uses_instanceid = true;
6699 }
6700
6701 /**
6702 * Compute the VS epilog key, which contains all the information needed to
6703 * build the VS epilog function, and set the PrimitiveID output offset.
6704 */
6705 static void si_get_vs_epilog_key(struct si_shader *shader,
6706 struct si_vs_epilog_bits *states,
6707 union si_shader_part_key *key)
6708 {
6709 memset(key, 0, sizeof(*key));
6710 key->vs_epilog.states = *states;
6711
6712 /* Set up the PrimitiveID output. */
6713 if (shader->key.part.vs.epilog.export_prim_id) {
6714 unsigned index = shader->selector->info.num_outputs;
6715 unsigned offset = shader->info.nr_param_exports++;
6716
6717 key->vs_epilog.prim_id_param_offset = offset;
6718 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
6719 shader->info.vs_output_param_offset[index] = offset;
6720 }
6721 }
6722
6723 /**
6724 * Compute the PS prolog key, which contains all the information needed to
6725 * build the PS prolog function, and set related bits in shader->config.
6726 */
6727 static void si_get_ps_prolog_key(struct si_shader *shader,
6728 union si_shader_part_key *key,
6729 bool separate_prolog)
6730 {
6731 struct tgsi_shader_info *info = &shader->selector->info;
6732
6733 memset(key, 0, sizeof(*key));
6734 key->ps_prolog.states = shader->key.part.ps.prolog;
6735 key->ps_prolog.colors_read = info->colors_read;
6736 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6737 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6738 key->ps_prolog.wqm = info->uses_derivatives &&
6739 (key->ps_prolog.colors_read ||
6740 key->ps_prolog.states.force_persp_sample_interp ||
6741 key->ps_prolog.states.force_linear_sample_interp ||
6742 key->ps_prolog.states.force_persp_center_interp ||
6743 key->ps_prolog.states.force_linear_center_interp ||
6744 key->ps_prolog.states.bc_optimize_for_persp ||
6745 key->ps_prolog.states.bc_optimize_for_linear);
6746
6747 if (info->colors_read) {
6748 unsigned *color = shader->selector->color_attr_index;
6749
6750 if (shader->key.part.ps.prolog.color_two_side) {
6751 /* BCOLORs are stored after the last input. */
6752 key->ps_prolog.num_interp_inputs = info->num_inputs;
6753 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6754 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6755 }
6756
6757 for (unsigned i = 0; i < 2; i++) {
6758 unsigned interp = info->input_interpolate[color[i]];
6759 unsigned location = info->input_interpolate_loc[color[i]];
6760
6761 if (!(info->colors_read & (0xf << i*4)))
6762 continue;
6763
6764 key->ps_prolog.color_attr_index[i] = color[i];
6765
6766 if (shader->key.part.ps.prolog.flatshade_colors &&
6767 interp == TGSI_INTERPOLATE_COLOR)
6768 interp = TGSI_INTERPOLATE_CONSTANT;
6769
6770 switch (interp) {
6771 case TGSI_INTERPOLATE_CONSTANT:
6772 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6773 break;
6774 case TGSI_INTERPOLATE_PERSPECTIVE:
6775 case TGSI_INTERPOLATE_COLOR:
6776 /* Force the interpolation location for colors here. */
6777 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6778 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6779 if (shader->key.part.ps.prolog.force_persp_center_interp)
6780 location = TGSI_INTERPOLATE_LOC_CENTER;
6781
6782 switch (location) {
6783 case TGSI_INTERPOLATE_LOC_SAMPLE:
6784 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6785 shader->config.spi_ps_input_ena |=
6786 S_0286CC_PERSP_SAMPLE_ENA(1);
6787 break;
6788 case TGSI_INTERPOLATE_LOC_CENTER:
6789 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6790 shader->config.spi_ps_input_ena |=
6791 S_0286CC_PERSP_CENTER_ENA(1);
6792 break;
6793 case TGSI_INTERPOLATE_LOC_CENTROID:
6794 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6795 shader->config.spi_ps_input_ena |=
6796 S_0286CC_PERSP_CENTROID_ENA(1);
6797 break;
6798 default:
6799 assert(0);
6800 }
6801 break;
6802 case TGSI_INTERPOLATE_LINEAR:
6803 /* Force the interpolation location for colors here. */
6804 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6805 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6806 if (shader->key.part.ps.prolog.force_linear_center_interp)
6807 location = TGSI_INTERPOLATE_LOC_CENTER;
6808
6809 /* The VGPR assignment for non-monolithic shaders
6810 * works because InitialPSInputAddr is set on the
6811 * main shader and PERSP_PULL_MODEL is never used.
6812 */
6813 switch (location) {
6814 case TGSI_INTERPOLATE_LOC_SAMPLE:
6815 key->ps_prolog.color_interp_vgpr_index[i] =
6816 separate_prolog ? 6 : 9;
6817 shader->config.spi_ps_input_ena |=
6818 S_0286CC_LINEAR_SAMPLE_ENA(1);
6819 break;
6820 case TGSI_INTERPOLATE_LOC_CENTER:
6821 key->ps_prolog.color_interp_vgpr_index[i] =
6822 separate_prolog ? 8 : 11;
6823 shader->config.spi_ps_input_ena |=
6824 S_0286CC_LINEAR_CENTER_ENA(1);
6825 break;
6826 case TGSI_INTERPOLATE_LOC_CENTROID:
6827 key->ps_prolog.color_interp_vgpr_index[i] =
6828 separate_prolog ? 10 : 13;
6829 shader->config.spi_ps_input_ena |=
6830 S_0286CC_LINEAR_CENTROID_ENA(1);
6831 break;
6832 default:
6833 assert(0);
6834 }
6835 break;
6836 default:
6837 assert(0);
6838 }
6839 }
6840 }
6841 }
6842
6843 /**
6844 * Check whether a PS prolog is required based on the key.
6845 */
6846 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6847 {
6848 return key->ps_prolog.colors_read ||
6849 key->ps_prolog.states.force_persp_sample_interp ||
6850 key->ps_prolog.states.force_linear_sample_interp ||
6851 key->ps_prolog.states.force_persp_center_interp ||
6852 key->ps_prolog.states.force_linear_center_interp ||
6853 key->ps_prolog.states.bc_optimize_for_persp ||
6854 key->ps_prolog.states.bc_optimize_for_linear ||
6855 key->ps_prolog.states.poly_stipple;
6856 }
6857
6858 /**
6859 * Compute the PS epilog key, which contains all the information needed to
6860 * build the PS epilog function.
6861 */
6862 static void si_get_ps_epilog_key(struct si_shader *shader,
6863 union si_shader_part_key *key)
6864 {
6865 struct tgsi_shader_info *info = &shader->selector->info;
6866 memset(key, 0, sizeof(*key));
6867 key->ps_epilog.colors_written = info->colors_written;
6868 key->ps_epilog.writes_z = info->writes_z;
6869 key->ps_epilog.writes_stencil = info->writes_stencil;
6870 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6871 key->ps_epilog.states = shader->key.part.ps.epilog;
6872 }
6873
6874 /**
6875 * Build the GS prolog function. Rotate the input vertices for triangle strips
6876 * with adjacency.
6877 */
6878 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6879 union si_shader_part_key *key)
6880 {
6881 const unsigned num_sgprs = SI_GS_NUM_USER_SGPR + 2;
6882 const unsigned num_vgprs = 8;
6883 struct gallivm_state *gallivm = &ctx->gallivm;
6884 LLVMBuilderRef builder = gallivm->builder;
6885 LLVMTypeRef params[32];
6886 LLVMTypeRef returns[32];
6887 LLVMValueRef func, ret;
6888
6889 for (unsigned i = 0; i < num_sgprs; ++i) {
6890 params[i] = ctx->i32;
6891 returns[i] = ctx->i32;
6892 }
6893
6894 for (unsigned i = 0; i < num_vgprs; ++i) {
6895 params[num_sgprs + i] = ctx->i32;
6896 returns[num_sgprs + i] = ctx->f32;
6897 }
6898
6899 /* Create the function. */
6900 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6901 params, num_sgprs + num_vgprs, num_sgprs - 1);
6902 func = ctx->main_fn;
6903
6904 /* Copy inputs to outputs. This should be no-op, as the registers match,
6905 * but it will prevent the compiler from overwriting them unintentionally.
6906 */
6907 ret = ctx->return_value;
6908 for (unsigned i = 0; i < num_sgprs; i++) {
6909 LLVMValueRef p = LLVMGetParam(func, i);
6910 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6911 }
6912 for (unsigned i = 0; i < num_vgprs; i++) {
6913 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6914 p = LLVMBuildBitCast(builder, p, ctx->f32, "");
6915 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6916 }
6917
6918 if (key->gs_prolog.states.tri_strip_adj_fix) {
6919 /* Remap the input vertices for every other primitive. */
6920 const unsigned vtx_params[6] = {
6921 num_sgprs,
6922 num_sgprs + 1,
6923 num_sgprs + 3,
6924 num_sgprs + 4,
6925 num_sgprs + 5,
6926 num_sgprs + 6
6927 };
6928 LLVMValueRef prim_id, rotate;
6929
6930 prim_id = LLVMGetParam(func, num_sgprs + 2);
6931 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6932
6933 for (unsigned i = 0; i < 6; ++i) {
6934 LLVMValueRef base, rotated, actual;
6935 base = LLVMGetParam(func, vtx_params[i]);
6936 rotated = LLVMGetParam(func, vtx_params[(i + 4) % 6]);
6937 actual = LLVMBuildSelect(builder, rotate, rotated, base, "");
6938 actual = LLVMBuildBitCast(builder, actual, ctx->f32, "");
6939 ret = LLVMBuildInsertValue(builder, ret, actual, vtx_params[i], "");
6940 }
6941 }
6942
6943 LLVMBuildRet(builder, ret);
6944 }
6945
6946 /**
6947 * Given a list of shader part functions, build a wrapper function that
6948 * runs them in sequence to form a monolithic shader.
6949 */
6950 static void si_build_wrapper_function(struct si_shader_context *ctx,
6951 LLVMValueRef *parts,
6952 unsigned num_parts,
6953 unsigned main_part)
6954 {
6955 struct gallivm_state *gallivm = &ctx->gallivm;
6956 LLVMBuilderRef builder = ctx->gallivm.builder;
6957 /* PS epilog has one arg per color component */
6958 LLVMTypeRef param_types[48];
6959 LLVMValueRef out[48];
6960 LLVMTypeRef function_type;
6961 unsigned num_params;
6962 unsigned num_out;
6963 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6964 unsigned num_sgprs, num_vgprs;
6965 unsigned last_sgpr_param;
6966 unsigned gprs;
6967
6968 for (unsigned i = 0; i < num_parts; ++i) {
6969 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6970 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6971 }
6972
6973 /* The parameters of the wrapper function correspond to those of the
6974 * first part in terms of SGPRs and VGPRs, but we use the types of the
6975 * main part to get the right types. This is relevant for the
6976 * dereferenceable attribute on descriptor table pointers.
6977 */
6978 num_sgprs = 0;
6979 num_vgprs = 0;
6980
6981 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6982 num_params = LLVMCountParamTypes(function_type);
6983
6984 for (unsigned i = 0; i < num_params; ++i) {
6985 LLVMValueRef param = LLVMGetParam(parts[0], i);
6986
6987 if (ac_is_sgpr_param(param)) {
6988 assert(num_vgprs == 0);
6989 num_sgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
6990 } else {
6991 num_vgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
6992 }
6993 }
6994 assert(num_vgprs + num_sgprs <= ARRAY_SIZE(param_types));
6995
6996 num_params = 0;
6997 last_sgpr_param = 0;
6998 gprs = 0;
6999 while (gprs < num_sgprs + num_vgprs) {
7000 LLVMValueRef param = LLVMGetParam(parts[main_part], num_params);
7001 unsigned size;
7002
7003 param_types[num_params] = LLVMTypeOf(param);
7004 if (gprs < num_sgprs)
7005 last_sgpr_param = num_params;
7006 size = llvm_get_type_size(param_types[num_params]) / 4;
7007 num_params++;
7008
7009 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
7010 assert(gprs + size <= num_sgprs + num_vgprs &&
7011 (gprs >= num_sgprs || gprs + size <= num_sgprs));
7012
7013 gprs += size;
7014 }
7015
7016 si_create_function(ctx, "wrapper", NULL, 0, param_types, num_params, last_sgpr_param);
7017
7018 /* Record the arguments of the function as if they were an output of
7019 * a previous part.
7020 */
7021 num_out = 0;
7022 num_out_sgpr = 0;
7023
7024 for (unsigned i = 0; i < num_params; ++i) {
7025 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
7026 LLVMTypeRef param_type = LLVMTypeOf(param);
7027 LLVMTypeRef out_type = i <= last_sgpr_param ? ctx->i32 : ctx->f32;
7028 unsigned size = llvm_get_type_size(param_type) / 4;
7029
7030 if (size == 1) {
7031 if (param_type != out_type)
7032 param = LLVMBuildBitCast(builder, param, out_type, "");
7033 out[num_out++] = param;
7034 } else {
7035 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
7036
7037 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7038 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
7039 param_type = ctx->i64;
7040 }
7041
7042 if (param_type != vector_type)
7043 param = LLVMBuildBitCast(builder, param, vector_type, "");
7044
7045 for (unsigned j = 0; j < size; ++j)
7046 out[num_out++] = LLVMBuildExtractElement(
7047 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
7048 }
7049
7050 if (i <= last_sgpr_param)
7051 num_out_sgpr = num_out;
7052 }
7053
7054 /* Now chain the parts. */
7055 for (unsigned part = 0; part < num_parts; ++part) {
7056 LLVMValueRef in[48];
7057 LLVMValueRef ret;
7058 LLVMTypeRef ret_type;
7059 unsigned out_idx = 0;
7060
7061 num_params = LLVMCountParams(parts[part]);
7062 assert(num_params <= ARRAY_SIZE(param_types));
7063
7064 /* Derive arguments for the next part from outputs of the
7065 * previous one.
7066 */
7067 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
7068 LLVMValueRef param;
7069 LLVMTypeRef param_type;
7070 bool is_sgpr;
7071 unsigned param_size;
7072 LLVMValueRef arg = NULL;
7073
7074 param = LLVMGetParam(parts[part], param_idx);
7075 param_type = LLVMTypeOf(param);
7076 param_size = llvm_get_type_size(param_type) / 4;
7077 is_sgpr = ac_is_sgpr_param(param);
7078
7079 if (is_sgpr) {
7080 #if HAVE_LLVM < 0x0400
7081 LLVMRemoveAttribute(param, LLVMByValAttribute);
7082 #else
7083 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
7084 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
7085 #endif
7086 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
7087 }
7088
7089 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
7090 assert(is_sgpr || out_idx >= num_out_sgpr);
7091
7092 if (param_size == 1)
7093 arg = out[out_idx];
7094 else
7095 arg = lp_build_gather_values(gallivm, &out[out_idx], param_size);
7096
7097 if (LLVMTypeOf(arg) != param_type) {
7098 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7099 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
7100 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
7101 } else {
7102 arg = LLVMBuildBitCast(builder, arg, param_type, "");
7103 }
7104 }
7105
7106 in[param_idx] = arg;
7107 out_idx += param_size;
7108 }
7109
7110 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
7111 ret_type = LLVMTypeOf(ret);
7112
7113 /* Extract the returned GPRs. */
7114 num_out = 0;
7115 num_out_sgpr = 0;
7116
7117 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
7118 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
7119
7120 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
7121
7122 for (unsigned i = 0; i < ret_size; ++i) {
7123 LLVMValueRef val =
7124 LLVMBuildExtractValue(builder, ret, i, "");
7125
7126 out[num_out++] = val;
7127
7128 if (LLVMTypeOf(val) == ctx->i32) {
7129 assert(num_out_sgpr + 1 == num_out);
7130 num_out_sgpr = num_out;
7131 }
7132 }
7133 }
7134 }
7135
7136 LLVMBuildRetVoid(builder);
7137 }
7138
7139 int si_compile_tgsi_shader(struct si_screen *sscreen,
7140 LLVMTargetMachineRef tm,
7141 struct si_shader *shader,
7142 bool is_monolithic,
7143 struct pipe_debug_callback *debug)
7144 {
7145 struct si_shader_selector *sel = shader->selector;
7146 struct si_shader_context ctx;
7147 struct lp_build_tgsi_context *bld_base;
7148 LLVMModuleRef mod;
7149 int r = -1;
7150
7151 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
7152 * conversion fails. */
7153 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
7154 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
7155 tgsi_dump(sel->tokens, 0);
7156 si_dump_streamout(&sel->so);
7157 }
7158
7159 si_init_shader_ctx(&ctx, sscreen, shader, tm);
7160 ctx.separate_prolog = !is_monolithic;
7161
7162 memset(shader->info.vs_output_param_offset, EXP_PARAM_UNDEFINED,
7163 sizeof(shader->info.vs_output_param_offset));
7164
7165 shader->info.uses_instanceid = sel->info.uses_instanceid;
7166
7167 bld_base = &ctx.soa.bld_base;
7168 ctx.load_system_value = declare_system_value;
7169
7170 if (!si_compile_tgsi_main(&ctx, shader)) {
7171 si_llvm_dispose(&ctx);
7172 return -1;
7173 }
7174
7175 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
7176 LLVMValueRef parts[3];
7177 bool need_prolog;
7178 bool need_epilog;
7179
7180 need_prolog = sel->info.num_inputs;
7181 need_epilog = !shader->key.as_es && !shader->key.as_ls;
7182
7183 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7184
7185 if (need_prolog) {
7186 union si_shader_part_key prolog_key;
7187 si_get_vs_prolog_key(shader, &prolog_key);
7188 si_build_vs_prolog_function(&ctx, &prolog_key);
7189 parts[0] = ctx.main_fn;
7190 }
7191
7192 if (need_epilog) {
7193 union si_shader_part_key epilog_key;
7194 si_get_vs_epilog_key(shader, &shader->key.part.vs.epilog, &epilog_key);
7195 si_build_vs_epilog_function(&ctx, &epilog_key);
7196 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7197 }
7198
7199 si_build_wrapper_function(&ctx, parts, 1 + need_prolog + need_epilog,
7200 need_prolog ? 1 : 0);
7201 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
7202 LLVMValueRef parts[2];
7203 union si_shader_part_key epilog_key;
7204
7205 parts[0] = ctx.main_fn;
7206
7207 memset(&epilog_key, 0, sizeof(epilog_key));
7208 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7209 si_build_tcs_epilog_function(&ctx, &epilog_key);
7210 parts[1] = ctx.main_fn;
7211
7212 si_build_wrapper_function(&ctx, parts, 2, 0);
7213 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_EVAL &&
7214 !shader->key.as_es) {
7215 LLVMValueRef parts[2];
7216 union si_shader_part_key epilog_key;
7217
7218 parts[0] = ctx.main_fn;
7219
7220 si_get_vs_epilog_key(shader, &shader->key.part.tes.epilog, &epilog_key);
7221 si_build_vs_epilog_function(&ctx, &epilog_key);
7222 parts[1] = ctx.main_fn;
7223
7224 si_build_wrapper_function(&ctx, parts, 2, 0);
7225 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
7226 LLVMValueRef parts[2];
7227 union si_shader_part_key prolog_key;
7228
7229 parts[1] = ctx.main_fn;
7230
7231 memset(&prolog_key, 0, sizeof(prolog_key));
7232 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7233 si_build_gs_prolog_function(&ctx, &prolog_key);
7234 parts[0] = ctx.main_fn;
7235
7236 si_build_wrapper_function(&ctx, parts, 2, 1);
7237 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
7238 LLVMValueRef parts[3];
7239 union si_shader_part_key prolog_key;
7240 union si_shader_part_key epilog_key;
7241 bool need_prolog;
7242
7243 si_get_ps_prolog_key(shader, &prolog_key, false);
7244 need_prolog = si_need_ps_prolog(&prolog_key);
7245
7246 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7247
7248 if (need_prolog) {
7249 si_build_ps_prolog_function(&ctx, &prolog_key);
7250 parts[0] = ctx.main_fn;
7251 }
7252
7253 si_get_ps_epilog_key(shader, &epilog_key);
7254 si_build_ps_epilog_function(&ctx, &epilog_key);
7255 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7256
7257 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2, need_prolog ? 1 : 0);
7258 }
7259
7260 mod = bld_base->base.gallivm->module;
7261
7262 /* Dump LLVM IR before any optimization passes */
7263 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
7264 r600_can_dump_shader(&sscreen->b, ctx.type))
7265 LLVMDumpModule(mod);
7266
7267 si_llvm_finalize_module(&ctx,
7268 r600_extra_shader_checks(&sscreen->b, ctx.type));
7269
7270 /* Post-optimization transformations and analysis. */
7271 si_eliminate_const_vs_outputs(&ctx);
7272
7273 if ((debug && debug->debug_message) ||
7274 r600_can_dump_shader(&sscreen->b, ctx.type))
7275 si_count_scratch_private_memory(&ctx);
7276
7277 /* Compile to bytecode. */
7278 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
7279 mod, debug, ctx.type, "TGSI shader");
7280 si_llvm_dispose(&ctx);
7281 if (r) {
7282 fprintf(stderr, "LLVM failed to compile shader\n");
7283 return r;
7284 }
7285
7286 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
7287 * LLVM 3.9svn has this bug.
7288 */
7289 if (sel->type == PIPE_SHADER_COMPUTE) {
7290 unsigned wave_size = 64;
7291 unsigned max_vgprs = 256;
7292 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
7293 unsigned max_sgprs_per_wave = 128;
7294 unsigned max_block_threads = si_get_max_workgroup_size(shader);
7295 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
7296 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
7297
7298 max_vgprs = max_vgprs / min_waves_per_simd;
7299 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
7300
7301 if (shader->config.num_sgprs > max_sgprs ||
7302 shader->config.num_vgprs > max_vgprs) {
7303 fprintf(stderr, "LLVM failed to compile a shader correctly: "
7304 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7305 shader->config.num_sgprs, shader->config.num_vgprs,
7306 max_sgprs, max_vgprs);
7307
7308 /* Just terminate the process, because dependent
7309 * shaders can hang due to bad input data, but use
7310 * the env var to allow shader-db to work.
7311 */
7312 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7313 abort();
7314 }
7315 }
7316
7317 /* Add the scratch offset to input SGPRs. */
7318 if (shader->config.scratch_bytes_per_wave)
7319 shader->info.num_input_sgprs += 1; /* scratch byte offset */
7320
7321 /* Calculate the number of fragment input VGPRs. */
7322 if (ctx.type == PIPE_SHADER_FRAGMENT) {
7323 shader->info.num_input_vgprs = 0;
7324 shader->info.face_vgpr_index = -1;
7325
7326 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7327 shader->info.num_input_vgprs += 2;
7328 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
7329 shader->info.num_input_vgprs += 2;
7330 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
7331 shader->info.num_input_vgprs += 2;
7332 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
7333 shader->info.num_input_vgprs += 3;
7334 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7335 shader->info.num_input_vgprs += 2;
7336 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7337 shader->info.num_input_vgprs += 2;
7338 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7339 shader->info.num_input_vgprs += 2;
7340 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7341 shader->info.num_input_vgprs += 1;
7342 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7343 shader->info.num_input_vgprs += 1;
7344 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7345 shader->info.num_input_vgprs += 1;
7346 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7347 shader->info.num_input_vgprs += 1;
7348 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7349 shader->info.num_input_vgprs += 1;
7350 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7351 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7352 shader->info.num_input_vgprs += 1;
7353 }
7354 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
7355 shader->info.num_input_vgprs += 1;
7356 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7357 shader->info.num_input_vgprs += 1;
7358 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7359 shader->info.num_input_vgprs += 1;
7360 }
7361
7362 return 0;
7363 }
7364
7365 /**
7366 * Create, compile and return a shader part (prolog or epilog).
7367 *
7368 * \param sscreen screen
7369 * \param list list of shader parts of the same category
7370 * \param type shader type
7371 * \param key shader part key
7372 * \param prolog whether the part being requested is a prolog
7373 * \param tm LLVM target machine
7374 * \param debug debug callback
7375 * \param build the callback responsible for building the main function
7376 * \return non-NULL on success
7377 */
7378 static struct si_shader_part *
7379 si_get_shader_part(struct si_screen *sscreen,
7380 struct si_shader_part **list,
7381 enum pipe_shader_type type,
7382 bool prolog,
7383 union si_shader_part_key *key,
7384 LLVMTargetMachineRef tm,
7385 struct pipe_debug_callback *debug,
7386 void (*build)(struct si_shader_context *,
7387 union si_shader_part_key *),
7388 const char *name)
7389 {
7390 struct si_shader_part *result;
7391
7392 pipe_mutex_lock(sscreen->shader_parts_mutex);
7393
7394 /* Find existing. */
7395 for (result = *list; result; result = result->next) {
7396 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7397 pipe_mutex_unlock(sscreen->shader_parts_mutex);
7398 return result;
7399 }
7400 }
7401
7402 /* Compile a new one. */
7403 result = CALLOC_STRUCT(si_shader_part);
7404 result->key = *key;
7405
7406 struct si_shader shader = {};
7407 struct si_shader_context ctx;
7408 struct gallivm_state *gallivm = &ctx.gallivm;
7409
7410 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7411 ctx.type = type;
7412
7413 switch (type) {
7414 case PIPE_SHADER_VERTEX:
7415 break;
7416 case PIPE_SHADER_TESS_CTRL:
7417 assert(!prolog);
7418 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7419 break;
7420 case PIPE_SHADER_GEOMETRY:
7421 assert(prolog);
7422 break;
7423 case PIPE_SHADER_FRAGMENT:
7424 if (prolog)
7425 shader.key.part.ps.prolog = key->ps_prolog.states;
7426 else
7427 shader.key.part.ps.epilog = key->ps_epilog.states;
7428 break;
7429 default:
7430 unreachable("bad shader part");
7431 }
7432
7433 build(&ctx, key);
7434
7435 /* Compile. */
7436 si_llvm_finalize_module(&ctx,
7437 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT));
7438
7439 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7440 gallivm->module, debug, ctx.type, name)) {
7441 FREE(result);
7442 result = NULL;
7443 goto out;
7444 }
7445
7446 result->next = *list;
7447 *list = result;
7448
7449 out:
7450 si_llvm_dispose(&ctx);
7451 pipe_mutex_unlock(sscreen->shader_parts_mutex);
7452 return result;
7453 }
7454
7455 /**
7456 * Build the vertex shader prolog function.
7457 *
7458 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7459 * All inputs are returned unmodified. The vertex load indices are
7460 * stored after them, which will be used by the API VS for fetching inputs.
7461 *
7462 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7463 * input_v0,
7464 * input_v1,
7465 * input_v2,
7466 * input_v3,
7467 * (VertexID + BaseVertex),
7468 * (InstanceID + StartInstance),
7469 * (InstanceID / 2 + StartInstance)
7470 */
7471 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7472 union si_shader_part_key *key)
7473 {
7474 struct gallivm_state *gallivm = &ctx->gallivm;
7475 LLVMTypeRef *params, *returns;
7476 LLVMValueRef ret, func;
7477 int last_sgpr, num_params, num_returns, i;
7478
7479 ctx->param_vertex_id = key->vs_prolog.num_input_sgprs;
7480 ctx->param_instance_id = key->vs_prolog.num_input_sgprs + 3;
7481
7482 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7483 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
7484 sizeof(LLVMTypeRef));
7485 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
7486 key->vs_prolog.last_input + 1) *
7487 sizeof(LLVMTypeRef));
7488 num_params = 0;
7489 num_returns = 0;
7490
7491 /* Declare input and output SGPRs. */
7492 num_params = 0;
7493 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7494 params[num_params++] = ctx->i32;
7495 returns[num_returns++] = ctx->i32;
7496 }
7497 last_sgpr = num_params - 1;
7498
7499 /* 4 preloaded VGPRs (outputs must be floats) */
7500 for (i = 0; i < 4; i++) {
7501 params[num_params++] = ctx->i32;
7502 returns[num_returns++] = ctx->f32;
7503 }
7504
7505 /* Vertex load indices. */
7506 for (i = 0; i <= key->vs_prolog.last_input; i++)
7507 returns[num_returns++] = ctx->f32;
7508
7509 /* Create the function. */
7510 si_create_function(ctx, "vs_prolog", returns, num_returns, params,
7511 num_params, last_sgpr);
7512 func = ctx->main_fn;
7513
7514 /* Copy inputs to outputs. This should be no-op, as the registers match,
7515 * but it will prevent the compiler from overwriting them unintentionally.
7516 */
7517 ret = ctx->return_value;
7518 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7519 LLVMValueRef p = LLVMGetParam(func, i);
7520 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7521 }
7522 for (i = num_params - 4; i < num_params; i++) {
7523 LLVMValueRef p = LLVMGetParam(func, i);
7524 p = LLVMBuildBitCast(gallivm->builder, p, ctx->f32, "");
7525 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7526 }
7527
7528 /* Compute vertex load indices from instance divisors. */
7529 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7530 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
7531 LLVMValueRef index;
7532
7533 if (divisor) {
7534 /* InstanceID / Divisor + StartInstance */
7535 index = get_instance_index_for_fetch(ctx,
7536 SI_SGPR_START_INSTANCE,
7537 divisor);
7538 } else {
7539 /* VertexID + BaseVertex */
7540 index = LLVMBuildAdd(gallivm->builder,
7541 LLVMGetParam(func, ctx->param_vertex_id),
7542 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
7543 }
7544
7545 index = LLVMBuildBitCast(gallivm->builder, index, ctx->f32, "");
7546 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
7547 num_params++, "");
7548 }
7549
7550 si_llvm_build_ret(ctx, ret);
7551 }
7552
7553 /**
7554 * Build the vertex shader epilog function. This is also used by the tessellation
7555 * evaluation shader compiled as VS.
7556 *
7557 * The input is PrimitiveID.
7558 *
7559 * If PrimitiveID is required by the pixel shader, export it.
7560 * Otherwise, do nothing.
7561 */
7562 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
7563 union si_shader_part_key *key)
7564 {
7565 struct gallivm_state *gallivm = &ctx->gallivm;
7566 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
7567 LLVMTypeRef params[5];
7568 int num_params, i;
7569
7570 /* Declare input VGPRs. */
7571 num_params = key->vs_epilog.states.export_prim_id ?
7572 (VS_EPILOG_PRIMID_LOC + 1) : 0;
7573 assert(num_params <= ARRAY_SIZE(params));
7574
7575 for (i = 0; i < num_params; i++)
7576 params[i] = ctx->f32;
7577
7578 /* Create the function. */
7579 si_create_function(ctx, "vs_epilog", NULL, 0, params, num_params, -1);
7580
7581 /* Emit exports. */
7582 if (key->vs_epilog.states.export_prim_id) {
7583 struct lp_build_context *base = &bld_base->base;
7584 struct lp_build_context *uint = &bld_base->uint_bld;
7585 LLVMValueRef args[9];
7586
7587 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
7588 args[1] = uint->zero; /* whether the EXEC mask is valid */
7589 args[2] = uint->zero; /* DONE bit */
7590 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
7591 key->vs_epilog.prim_id_param_offset);
7592 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
7593 args[5] = LLVMGetParam(ctx->main_fn,
7594 VS_EPILOG_PRIMID_LOC); /* X */
7595 args[6] = base->undef; /* Y */
7596 args[7] = base->undef; /* Z */
7597 args[8] = base->undef; /* W */
7598
7599 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
7600 LLVMVoidTypeInContext(base->gallivm->context),
7601 args, 9, 0);
7602 }
7603
7604 LLVMBuildRetVoid(gallivm->builder);
7605 }
7606
7607 /**
7608 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7609 */
7610 static bool si_get_vs_epilog(struct si_screen *sscreen,
7611 LLVMTargetMachineRef tm,
7612 struct si_shader *shader,
7613 struct pipe_debug_callback *debug,
7614 struct si_vs_epilog_bits *states)
7615 {
7616 union si_shader_part_key epilog_key;
7617
7618 si_get_vs_epilog_key(shader, states, &epilog_key);
7619
7620 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
7621 PIPE_SHADER_VERTEX, true,
7622 &epilog_key, tm, debug,
7623 si_build_vs_epilog_function,
7624 "Vertex Shader Epilog");
7625 return shader->epilog != NULL;
7626 }
7627
7628 /**
7629 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7630 */
7631 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7632 LLVMTargetMachineRef tm,
7633 struct si_shader *shader,
7634 struct pipe_debug_callback *debug)
7635 {
7636 struct tgsi_shader_info *info = &shader->selector->info;
7637 union si_shader_part_key prolog_key;
7638
7639 /* Get the prolog. */
7640 si_get_vs_prolog_key(shader, &prolog_key);
7641
7642 /* The prolog is a no-op if there are no inputs. */
7643 if (info->num_inputs) {
7644 shader->prolog =
7645 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7646 PIPE_SHADER_VERTEX, true,
7647 &prolog_key, tm, debug,
7648 si_build_vs_prolog_function,
7649 "Vertex Shader Prolog");
7650 if (!shader->prolog)
7651 return false;
7652 }
7653
7654 /* Get the epilog. */
7655 if (!shader->key.as_es && !shader->key.as_ls &&
7656 !si_get_vs_epilog(sscreen, tm, shader, debug,
7657 &shader->key.part.vs.epilog))
7658 return false;
7659
7660 return true;
7661 }
7662
7663 /**
7664 * Select and compile (or reuse) TES parts (epilog).
7665 */
7666 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
7667 LLVMTargetMachineRef tm,
7668 struct si_shader *shader,
7669 struct pipe_debug_callback *debug)
7670 {
7671 if (shader->key.as_es)
7672 return true;
7673
7674 /* TES compiled as VS. */
7675 return si_get_vs_epilog(sscreen, tm, shader, debug,
7676 &shader->key.part.tes.epilog);
7677 }
7678
7679 /**
7680 * Compile the TCS epilog function. This writes tesselation factors to memory
7681 * based on the output primitive type of the tesselator (determined by TES).
7682 */
7683 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7684 union si_shader_part_key *key)
7685 {
7686 struct gallivm_state *gallivm = &ctx->gallivm;
7687 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
7688 LLVMTypeRef params[16];
7689 LLVMValueRef func;
7690 int last_sgpr, num_params;
7691
7692 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
7693 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
7694 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
7695 params[SI_PARAM_SAMPLERS] = ctx->i64;
7696 params[SI_PARAM_IMAGES] = ctx->i64;
7697 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
7698 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
7699 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
7700 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
7701 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
7702 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
7703 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
7704 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
7705 num_params = last_sgpr + 1;
7706
7707 params[num_params++] = ctx->i32; /* patch index within the wave (REL_PATCH_ID) */
7708 params[num_params++] = ctx->i32; /* invocation ID within the patch */
7709 params[num_params++] = ctx->i32; /* LDS offset where tess factors should be loaded from */
7710
7711 /* Create the function. */
7712 si_create_function(ctx, "tcs_epilog", NULL, 0, params, num_params, last_sgpr);
7713 declare_tess_lds(ctx);
7714 func = ctx->main_fn;
7715
7716 si_write_tess_factors(bld_base,
7717 LLVMGetParam(func, last_sgpr + 1),
7718 LLVMGetParam(func, last_sgpr + 2),
7719 LLVMGetParam(func, last_sgpr + 3));
7720
7721 LLVMBuildRetVoid(gallivm->builder);
7722 }
7723
7724 /**
7725 * Select and compile (or reuse) TCS parts (epilog).
7726 */
7727 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7728 LLVMTargetMachineRef tm,
7729 struct si_shader *shader,
7730 struct pipe_debug_callback *debug)
7731 {
7732 union si_shader_part_key epilog_key;
7733
7734 /* Get the epilog. */
7735 memset(&epilog_key, 0, sizeof(epilog_key));
7736 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7737
7738 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7739 PIPE_SHADER_TESS_CTRL, false,
7740 &epilog_key, tm, debug,
7741 si_build_tcs_epilog_function,
7742 "Tessellation Control Shader Epilog");
7743 return shader->epilog != NULL;
7744 }
7745
7746 /**
7747 * Select and compile (or reuse) GS parts (prolog).
7748 */
7749 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7750 LLVMTargetMachineRef tm,
7751 struct si_shader *shader,
7752 struct pipe_debug_callback *debug)
7753 {
7754 union si_shader_part_key prolog_key;
7755
7756 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7757 return true;
7758
7759 memset(&prolog_key, 0, sizeof(prolog_key));
7760 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7761
7762 shader->prolog = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7763 PIPE_SHADER_GEOMETRY, true,
7764 &prolog_key, tm, debug,
7765 si_build_gs_prolog_function,
7766 "Geometry Shader Prolog");
7767 return shader->prolog != NULL;
7768 }
7769
7770 /**
7771 * Build the pixel shader prolog function. This handles:
7772 * - two-side color selection and interpolation
7773 * - overriding interpolation parameters for the API PS
7774 * - polygon stippling
7775 *
7776 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7777 * overriden by other states. (e.g. per-sample interpolation)
7778 * Interpolated colors are stored after the preloaded VGPRs.
7779 */
7780 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7781 union si_shader_part_key *key)
7782 {
7783 struct gallivm_state *gallivm = &ctx->gallivm;
7784 LLVMTypeRef *params;
7785 LLVMValueRef ret, func;
7786 int last_sgpr, num_params, num_returns, i, num_color_channels;
7787
7788 assert(si_need_ps_prolog(key));
7789
7790 /* Number of inputs + 8 color elements. */
7791 params = alloca((key->ps_prolog.num_input_sgprs +
7792 key->ps_prolog.num_input_vgprs + 8) *
7793 sizeof(LLVMTypeRef));
7794
7795 /* Declare inputs. */
7796 num_params = 0;
7797 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7798 params[num_params++] = ctx->i32;
7799 last_sgpr = num_params - 1;
7800
7801 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7802 params[num_params++] = ctx->f32;
7803
7804 /* Declare outputs (same as inputs + add colors if needed) */
7805 num_returns = num_params;
7806 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7807 for (i = 0; i < num_color_channels; i++)
7808 params[num_returns++] = ctx->f32;
7809
7810 /* Create the function. */
7811 si_create_function(ctx, "ps_prolog", params, num_returns, params,
7812 num_params, last_sgpr);
7813 func = ctx->main_fn;
7814
7815 /* Copy inputs to outputs. This should be no-op, as the registers match,
7816 * but it will prevent the compiler from overwriting them unintentionally.
7817 */
7818 ret = ctx->return_value;
7819 for (i = 0; i < num_params; i++) {
7820 LLVMValueRef p = LLVMGetParam(func, i);
7821 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7822 }
7823
7824 /* Polygon stippling. */
7825 if (key->ps_prolog.states.poly_stipple) {
7826 /* POS_FIXED_PT is always last. */
7827 unsigned pos = key->ps_prolog.num_input_sgprs +
7828 key->ps_prolog.num_input_vgprs - 1;
7829 LLVMValueRef ptr[2], list;
7830
7831 /* Get the pointer to rw buffers. */
7832 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
7833 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
7834 list = lp_build_gather_values(gallivm, ptr, 2);
7835 list = LLVMBuildBitCast(gallivm->builder, list, ctx->i64, "");
7836 list = LLVMBuildIntToPtr(gallivm->builder, list,
7837 const_array(ctx->v16i8, SI_NUM_RW_BUFFERS), "");
7838
7839 si_llvm_emit_polygon_stipple(ctx, list, pos);
7840 }
7841
7842 if (key->ps_prolog.states.bc_optimize_for_persp ||
7843 key->ps_prolog.states.bc_optimize_for_linear) {
7844 unsigned i, base = key->ps_prolog.num_input_sgprs;
7845 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7846
7847 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7848 * The hw doesn't compute CENTROID if the whole wave only
7849 * contains fully-covered quads.
7850 *
7851 * PRIM_MASK is after user SGPRs.
7852 */
7853 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7854 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
7855 LLVMConstInt(ctx->i32, 31, 0), "");
7856 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
7857 ctx->i1, "");
7858
7859 if (key->ps_prolog.states.bc_optimize_for_persp) {
7860 /* Read PERSP_CENTER. */
7861 for (i = 0; i < 2; i++)
7862 center[i] = LLVMGetParam(func, base + 2 + i);
7863 /* Read PERSP_CENTROID. */
7864 for (i = 0; i < 2; i++)
7865 centroid[i] = LLVMGetParam(func, base + 4 + i);
7866 /* Select PERSP_CENTROID. */
7867 for (i = 0; i < 2; i++) {
7868 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7869 center[i], centroid[i], "");
7870 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7871 tmp, base + 4 + i, "");
7872 }
7873 }
7874 if (key->ps_prolog.states.bc_optimize_for_linear) {
7875 /* Read LINEAR_CENTER. */
7876 for (i = 0; i < 2; i++)
7877 center[i] = LLVMGetParam(func, base + 8 + i);
7878 /* Read LINEAR_CENTROID. */
7879 for (i = 0; i < 2; i++)
7880 centroid[i] = LLVMGetParam(func, base + 10 + i);
7881 /* Select LINEAR_CENTROID. */
7882 for (i = 0; i < 2; i++) {
7883 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7884 center[i], centroid[i], "");
7885 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7886 tmp, base + 10 + i, "");
7887 }
7888 }
7889 }
7890
7891 /* Force per-sample interpolation. */
7892 if (key->ps_prolog.states.force_persp_sample_interp) {
7893 unsigned i, base = key->ps_prolog.num_input_sgprs;
7894 LLVMValueRef persp_sample[2];
7895
7896 /* Read PERSP_SAMPLE. */
7897 for (i = 0; i < 2; i++)
7898 persp_sample[i] = LLVMGetParam(func, base + i);
7899 /* Overwrite PERSP_CENTER. */
7900 for (i = 0; i < 2; i++)
7901 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7902 persp_sample[i], base + 2 + i, "");
7903 /* Overwrite PERSP_CENTROID. */
7904 for (i = 0; i < 2; i++)
7905 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7906 persp_sample[i], base + 4 + i, "");
7907 }
7908 if (key->ps_prolog.states.force_linear_sample_interp) {
7909 unsigned i, base = key->ps_prolog.num_input_sgprs;
7910 LLVMValueRef linear_sample[2];
7911
7912 /* Read LINEAR_SAMPLE. */
7913 for (i = 0; i < 2; i++)
7914 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7915 /* Overwrite LINEAR_CENTER. */
7916 for (i = 0; i < 2; i++)
7917 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7918 linear_sample[i], base + 8 + i, "");
7919 /* Overwrite LINEAR_CENTROID. */
7920 for (i = 0; i < 2; i++)
7921 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7922 linear_sample[i], base + 10 + i, "");
7923 }
7924
7925 /* Force center interpolation. */
7926 if (key->ps_prolog.states.force_persp_center_interp) {
7927 unsigned i, base = key->ps_prolog.num_input_sgprs;
7928 LLVMValueRef persp_center[2];
7929
7930 /* Read PERSP_CENTER. */
7931 for (i = 0; i < 2; i++)
7932 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7933 /* Overwrite PERSP_SAMPLE. */
7934 for (i = 0; i < 2; i++)
7935 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7936 persp_center[i], base + i, "");
7937 /* Overwrite PERSP_CENTROID. */
7938 for (i = 0; i < 2; i++)
7939 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7940 persp_center[i], base + 4 + i, "");
7941 }
7942 if (key->ps_prolog.states.force_linear_center_interp) {
7943 unsigned i, base = key->ps_prolog.num_input_sgprs;
7944 LLVMValueRef linear_center[2];
7945
7946 /* Read LINEAR_CENTER. */
7947 for (i = 0; i < 2; i++)
7948 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7949 /* Overwrite LINEAR_SAMPLE. */
7950 for (i = 0; i < 2; i++)
7951 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7952 linear_center[i], base + 6 + i, "");
7953 /* Overwrite LINEAR_CENTROID. */
7954 for (i = 0; i < 2; i++)
7955 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7956 linear_center[i], base + 10 + i, "");
7957 }
7958
7959 /* Interpolate colors. */
7960 for (i = 0; i < 2; i++) {
7961 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7962 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7963 key->ps_prolog.face_vgpr_index;
7964 LLVMValueRef interp[2], color[4];
7965 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7966
7967 if (!writemask)
7968 continue;
7969
7970 /* If the interpolation qualifier is not CONSTANT (-1). */
7971 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7972 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7973 key->ps_prolog.color_interp_vgpr_index[i];
7974
7975 /* Get the (i,j) updated by bc_optimize handling. */
7976 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
7977 interp_vgpr, "");
7978 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
7979 interp_vgpr + 1, "");
7980 interp_ij = lp_build_gather_values(gallivm, interp, 2);
7981 interp_ij = LLVMBuildBitCast(gallivm->builder, interp_ij,
7982 ctx->v2i32, "");
7983 }
7984
7985 /* Use the absolute location of the input. */
7986 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7987
7988 if (key->ps_prolog.states.color_two_side) {
7989 face = LLVMGetParam(func, face_vgpr);
7990 face = LLVMBuildBitCast(gallivm->builder, face, ctx->i32, "");
7991 }
7992
7993 interp_fs_input(ctx,
7994 key->ps_prolog.color_attr_index[i],
7995 TGSI_SEMANTIC_COLOR, i,
7996 key->ps_prolog.num_interp_inputs,
7997 key->ps_prolog.colors_read, interp_ij,
7998 prim_mask, face, color);
7999
8000 while (writemask) {
8001 unsigned chan = u_bit_scan(&writemask);
8002 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
8003 num_params++, "");
8004 }
8005 }
8006
8007 /* Tell LLVM to insert WQM instruction sequence when needed. */
8008 if (key->ps_prolog.wqm) {
8009 LLVMAddTargetDependentFunctionAttr(func,
8010 "amdgpu-ps-wqm-outputs", "");
8011 }
8012
8013 si_llvm_build_ret(ctx, ret);
8014 }
8015
8016 /**
8017 * Build the pixel shader epilog function. This handles everything that must be
8018 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
8019 */
8020 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
8021 union si_shader_part_key *key)
8022 {
8023 struct gallivm_state *gallivm = &ctx->gallivm;
8024 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
8025 LLVMTypeRef params[16+8*4+3];
8026 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
8027 int last_sgpr, num_params, i;
8028 struct si_ps_exports exp = {};
8029
8030 /* Declare input SGPRs. */
8031 params[SI_PARAM_RW_BUFFERS] = ctx->i64;
8032 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
8033 params[SI_PARAM_SAMPLERS] = ctx->i64;
8034 params[SI_PARAM_IMAGES] = ctx->i64;
8035 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
8036 params[SI_PARAM_ALPHA_REF] = ctx->f32;
8037 last_sgpr = SI_PARAM_ALPHA_REF;
8038
8039 /* Declare input VGPRs. */
8040 num_params = (last_sgpr + 1) +
8041 util_bitcount(key->ps_epilog.colors_written) * 4 +
8042 key->ps_epilog.writes_z +
8043 key->ps_epilog.writes_stencil +
8044 key->ps_epilog.writes_samplemask;
8045
8046 num_params = MAX2(num_params,
8047 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
8048
8049 assert(num_params <= ARRAY_SIZE(params));
8050
8051 for (i = last_sgpr + 1; i < num_params; i++)
8052 params[i] = ctx->f32;
8053
8054 /* Create the function. */
8055 si_create_function(ctx, "ps_epilog", NULL, 0, params, num_params, last_sgpr);
8056 /* Disable elimination of unused inputs. */
8057 si_llvm_add_attribute(ctx->main_fn,
8058 "InitialPSInputAddr", 0xffffff);
8059
8060 /* Process colors. */
8061 unsigned vgpr = last_sgpr + 1;
8062 unsigned colors_written = key->ps_epilog.colors_written;
8063 int last_color_export = -1;
8064
8065 /* Find the last color export. */
8066 if (!key->ps_epilog.writes_z &&
8067 !key->ps_epilog.writes_stencil &&
8068 !key->ps_epilog.writes_samplemask) {
8069 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
8070
8071 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
8072 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
8073 /* Just set this if any of the colorbuffers are enabled. */
8074 if (spi_format &
8075 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
8076 last_color_export = 0;
8077 } else {
8078 for (i = 0; i < 8; i++)
8079 if (colors_written & (1 << i) &&
8080 (spi_format >> (i * 4)) & 0xf)
8081 last_color_export = i;
8082 }
8083 }
8084
8085 while (colors_written) {
8086 LLVMValueRef color[4];
8087 int mrt = u_bit_scan(&colors_written);
8088
8089 for (i = 0; i < 4; i++)
8090 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
8091
8092 si_export_mrt_color(bld_base, color, mrt,
8093 num_params - 1,
8094 mrt == last_color_export, &exp);
8095 }
8096
8097 /* Process depth, stencil, samplemask. */
8098 if (key->ps_epilog.writes_z)
8099 depth = LLVMGetParam(ctx->main_fn, vgpr++);
8100 if (key->ps_epilog.writes_stencil)
8101 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
8102 if (key->ps_epilog.writes_samplemask)
8103 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
8104
8105 if (depth || stencil || samplemask)
8106 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
8107 else if (last_color_export == -1)
8108 si_export_null(bld_base);
8109
8110 if (exp.num)
8111 si_emit_ps_exports(ctx, &exp);
8112
8113 /* Compile. */
8114 LLVMBuildRetVoid(gallivm->builder);
8115 }
8116
8117 /**
8118 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
8119 */
8120 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
8121 LLVMTargetMachineRef tm,
8122 struct si_shader *shader,
8123 struct pipe_debug_callback *debug)
8124 {
8125 union si_shader_part_key prolog_key;
8126 union si_shader_part_key epilog_key;
8127
8128 /* Get the prolog. */
8129 si_get_ps_prolog_key(shader, &prolog_key, true);
8130
8131 /* The prolog is a no-op if these aren't set. */
8132 if (si_need_ps_prolog(&prolog_key)) {
8133 shader->prolog =
8134 si_get_shader_part(sscreen, &sscreen->ps_prologs,
8135 PIPE_SHADER_FRAGMENT, true,
8136 &prolog_key, tm, debug,
8137 si_build_ps_prolog_function,
8138 "Fragment Shader Prolog");
8139 if (!shader->prolog)
8140 return false;
8141 }
8142
8143 /* Get the epilog. */
8144 si_get_ps_epilog_key(shader, &epilog_key);
8145
8146 shader->epilog =
8147 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
8148 PIPE_SHADER_FRAGMENT, false,
8149 &epilog_key, tm, debug,
8150 si_build_ps_epilog_function,
8151 "Fragment Shader Epilog");
8152 if (!shader->epilog)
8153 return false;
8154
8155 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
8156 if (shader->key.part.ps.prolog.poly_stipple) {
8157 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
8158 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
8159 }
8160
8161 /* Set up the enable bits for per-sample shading if needed. */
8162 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
8163 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8164 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8165 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
8166 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8167 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
8168 }
8169 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
8170 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8171 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8172 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
8173 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8174 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
8175 }
8176 if (shader->key.part.ps.prolog.force_persp_center_interp &&
8177 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8178 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8179 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
8180 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8181 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8182 }
8183 if (shader->key.part.ps.prolog.force_linear_center_interp &&
8184 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8185 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8186 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
8187 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8188 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8189 }
8190
8191 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
8192 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
8193 !(shader->config.spi_ps_input_ena & 0xf)) {
8194 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8195 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
8196 }
8197
8198 /* At least one pair of interpolation weights must be enabled. */
8199 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
8200 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8201 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
8202 }
8203
8204 /* The sample mask input is always enabled, because the API shader always
8205 * passes it through to the epilog. Disable it here if it's unused.
8206 */
8207 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
8208 !shader->selector->info.reads_samplemask)
8209 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
8210
8211 return true;
8212 }
8213
8214 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
8215 unsigned *lds_size)
8216 {
8217 /* SPI barrier management bug:
8218 * Make sure we have at least 4k of LDS in use to avoid the bug.
8219 * It applies to workgroup sizes of more than one wavefront.
8220 */
8221 if (sscreen->b.family == CHIP_BONAIRE ||
8222 sscreen->b.family == CHIP_KABINI ||
8223 sscreen->b.family == CHIP_MULLINS)
8224 *lds_size = MAX2(*lds_size, 8);
8225 }
8226
8227 static void si_fix_resource_usage(struct si_screen *sscreen,
8228 struct si_shader *shader)
8229 {
8230 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
8231
8232 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
8233
8234 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
8235 si_get_max_workgroup_size(shader) > 64) {
8236 si_multiwave_lds_size_workaround(sscreen,
8237 &shader->config.lds_size);
8238 }
8239 }
8240
8241 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
8242 struct si_shader *shader,
8243 struct pipe_debug_callback *debug)
8244 {
8245 struct si_shader_selector *sel = shader->selector;
8246 struct si_shader *mainp = sel->main_shader_part;
8247 int r;
8248
8249 /* LS, ES, VS are compiled on demand if the main part hasn't been
8250 * compiled for that stage.
8251 *
8252 * Vertex shaders are compiled on demand when a vertex fetch
8253 * workaround must be applied.
8254 */
8255 if (shader->is_monolithic) {
8256 /* Monolithic shader (compiled as a whole, has many variants,
8257 * may take a long time to compile).
8258 */
8259 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
8260 if (r)
8261 return r;
8262 } else {
8263 /* The shader consists of 2-3 parts:
8264 *
8265 * - the middle part is the user shader, it has 1 variant only
8266 * and it was compiled during the creation of the shader
8267 * selector
8268 * - the prolog part is inserted at the beginning
8269 * - the epilog part is inserted at the end
8270 *
8271 * The prolog and epilog have many (but simple) variants.
8272 */
8273
8274 /* Copy the compiled TGSI shader data over. */
8275 shader->is_binary_shared = true;
8276 shader->binary = mainp->binary;
8277 shader->config = mainp->config;
8278 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8279 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8280 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8281 memcpy(shader->info.vs_output_param_offset,
8282 mainp->info.vs_output_param_offset,
8283 sizeof(mainp->info.vs_output_param_offset));
8284 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8285 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8286 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8287
8288 /* Select prologs and/or epilogs. */
8289 switch (sel->type) {
8290 case PIPE_SHADER_VERTEX:
8291 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
8292 return -1;
8293 break;
8294 case PIPE_SHADER_TESS_CTRL:
8295 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
8296 return -1;
8297 break;
8298 case PIPE_SHADER_TESS_EVAL:
8299 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
8300 return -1;
8301 break;
8302 case PIPE_SHADER_GEOMETRY:
8303 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
8304 return -1;
8305 break;
8306 case PIPE_SHADER_FRAGMENT:
8307 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8308 return -1;
8309
8310 /* Make sure we have at least as many VGPRs as there
8311 * are allocated inputs.
8312 */
8313 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8314 shader->info.num_input_vgprs);
8315 break;
8316 }
8317
8318 /* Update SGPR and VGPR counts. */
8319 if (shader->prolog) {
8320 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8321 shader->prolog->config.num_sgprs);
8322 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8323 shader->prolog->config.num_vgprs);
8324 }
8325 if (shader->epilog) {
8326 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8327 shader->epilog->config.num_sgprs);
8328 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8329 shader->epilog->config.num_vgprs);
8330 }
8331 }
8332
8333 si_fix_resource_usage(sscreen, shader);
8334 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8335 stderr);
8336
8337 /* Upload. */
8338 r = si_shader_binary_upload(sscreen, shader);
8339 if (r) {
8340 fprintf(stderr, "LLVM failed to upload shader\n");
8341 return r;
8342 }
8343
8344 return 0;
8345 }
8346
8347 void si_shader_destroy(struct si_shader *shader)
8348 {
8349 if (shader->scratch_bo)
8350 r600_resource_reference(&shader->scratch_bo, NULL);
8351
8352 r600_resource_reference(&shader->bo, NULL);
8353
8354 if (!shader->is_binary_shared)
8355 radeon_shader_binary_clean(&shader->binary);
8356
8357 free(shader->shader_log);
8358 }