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radeonsi: wait for outstanding memory instructions in TCS barriers
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "radeon/radeon_elf_util.h"
37 #include "util/u_memory.h"
38 #include "util/u_string.h"
39 #include "tgsi/tgsi_build.h"
40 #include "tgsi/tgsi_util.h"
41 #include "tgsi/tgsi_dump.h"
42
43 #include "ac_llvm_util.h"
44 #include "si_shader_internal.h"
45 #include "si_pipe.h"
46 #include "sid.h"
47
48
49 static const char *scratch_rsrc_dword0_symbol =
50 "SCRATCH_RSRC_DWORD0";
51
52 static const char *scratch_rsrc_dword1_symbol =
53 "SCRATCH_RSRC_DWORD1";
54
55 struct si_shader_output_values
56 {
57 LLVMValueRef values[4];
58 unsigned name;
59 unsigned sid;
60 };
61
62 static void si_init_shader_ctx(struct si_shader_context *ctx,
63 struct si_screen *sscreen,
64 struct si_shader *shader,
65 LLVMTargetMachineRef tm);
66
67 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
68 struct lp_build_tgsi_context *bld_base,
69 struct lp_build_emit_data *emit_data);
70
71 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
72 FILE *f);
73
74 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
75 union si_shader_part_key *key);
76 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
77 union si_shader_part_key *key);
78 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
79 union si_shader_part_key *key);
80 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
81 union si_shader_part_key *key);
82 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
83 union si_shader_part_key *key);
84
85 /* Ideally pass the sample mask input to the PS epilog as v13, which
86 * is its usual location, so that the shader doesn't have to add v_mov.
87 */
88 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
89
90 /* The VS location of the PrimitiveID input is the same in the epilog,
91 * so that the main shader part doesn't have to move it.
92 */
93 #define VS_EPILOG_PRIMID_LOC 2
94
95 enum {
96 CONST_ADDR_SPACE = 2,
97 LOCAL_ADDR_SPACE = 3,
98 };
99
100 #define SENDMSG_GS 2
101 #define SENDMSG_GS_DONE 3
102
103 #define SENDMSG_GS_OP_NOP (0 << 4)
104 #define SENDMSG_GS_OP_CUT (1 << 4)
105 #define SENDMSG_GS_OP_EMIT (2 << 4)
106 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
107
108 /**
109 * Returns a unique index for a semantic name and index. The index must be
110 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
111 * calculated.
112 */
113 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
114 {
115 switch (semantic_name) {
116 case TGSI_SEMANTIC_POSITION:
117 return 0;
118 case TGSI_SEMANTIC_PSIZE:
119 return 1;
120 case TGSI_SEMANTIC_CLIPDIST:
121 assert(index <= 1);
122 return 2 + index;
123 case TGSI_SEMANTIC_GENERIC:
124 if (index <= 63-4)
125 return 4 + index;
126
127 assert(!"invalid generic index");
128 return 0;
129
130 /* patch indices are completely separate and thus start from 0 */
131 case TGSI_SEMANTIC_TESSOUTER:
132 return 0;
133 case TGSI_SEMANTIC_TESSINNER:
134 return 1;
135 case TGSI_SEMANTIC_PATCH:
136 return 2 + index;
137
138 default:
139 assert(!"invalid semantic name");
140 return 0;
141 }
142 }
143
144 unsigned si_shader_io_get_unique_index2(unsigned name, unsigned index)
145 {
146 switch (name) {
147 case TGSI_SEMANTIC_FOG:
148 return 0;
149 case TGSI_SEMANTIC_LAYER:
150 return 1;
151 case TGSI_SEMANTIC_VIEWPORT_INDEX:
152 return 2;
153 case TGSI_SEMANTIC_PRIMID:
154 return 3;
155 case TGSI_SEMANTIC_COLOR: /* these alias */
156 case TGSI_SEMANTIC_BCOLOR:
157 return 4 + index;
158 case TGSI_SEMANTIC_TEXCOORD:
159 return 6 + index;
160 default:
161 assert(!"invalid semantic name");
162 return 0;
163 }
164 }
165
166 /**
167 * Get the value of a shader input parameter and extract a bitfield.
168 */
169 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
170 unsigned param, unsigned rshift,
171 unsigned bitwidth)
172 {
173 struct gallivm_state *gallivm = &ctx->gallivm;
174 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
175 param);
176
177 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
178 value = bitcast(&ctx->soa.bld_base,
179 TGSI_TYPE_UNSIGNED, value);
180
181 if (rshift)
182 value = LLVMBuildLShr(gallivm->builder, value,
183 lp_build_const_int32(gallivm, rshift), "");
184
185 if (rshift + bitwidth < 32) {
186 unsigned mask = (1 << bitwidth) - 1;
187 value = LLVMBuildAnd(gallivm->builder, value,
188 lp_build_const_int32(gallivm, mask), "");
189 }
190
191 return value;
192 }
193
194 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
195 {
196 switch (ctx->type) {
197 case PIPE_SHADER_TESS_CTRL:
198 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
199
200 case PIPE_SHADER_TESS_EVAL:
201 return LLVMGetParam(ctx->main_fn,
202 ctx->param_tes_rel_patch_id);
203
204 default:
205 assert(0);
206 return NULL;
207 }
208 }
209
210 /* Tessellation shaders pass outputs to the next shader using LDS.
211 *
212 * LS outputs = TCS inputs
213 * TCS outputs = TES inputs
214 *
215 * The LDS layout is:
216 * - TCS inputs for patch 0
217 * - TCS inputs for patch 1
218 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
219 * - ...
220 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
221 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
222 * - TCS outputs for patch 1
223 * - Per-patch TCS outputs for patch 1
224 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
225 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
226 * - ...
227 *
228 * All three shaders VS(LS), TCS, TES share the same LDS space.
229 */
230
231 static LLVMValueRef
232 get_tcs_in_patch_stride(struct si_shader_context *ctx)
233 {
234 if (ctx->type == PIPE_SHADER_VERTEX)
235 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
236 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
237 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
238 else {
239 assert(0);
240 return NULL;
241 }
242 }
243
244 static LLVMValueRef
245 get_tcs_out_patch_stride(struct si_shader_context *ctx)
246 {
247 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
248 }
249
250 static LLVMValueRef
251 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
252 {
253 return lp_build_mul_imm(&ctx->soa.bld_base.uint_bld,
254 unpack_param(ctx,
255 SI_PARAM_TCS_OUT_OFFSETS,
256 0, 16),
257 4);
258 }
259
260 static LLVMValueRef
261 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
262 {
263 return lp_build_mul_imm(&ctx->soa.bld_base.uint_bld,
264 unpack_param(ctx,
265 SI_PARAM_TCS_OUT_OFFSETS,
266 16, 16),
267 4);
268 }
269
270 static LLVMValueRef
271 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
272 {
273 struct gallivm_state *gallivm = &ctx->gallivm;
274 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
275 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
276
277 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
278 }
279
280 static LLVMValueRef
281 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
282 {
283 struct gallivm_state *gallivm = &ctx->gallivm;
284 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
285 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
286 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
287
288 return LLVMBuildAdd(gallivm->builder, patch0_offset,
289 LLVMBuildMul(gallivm->builder, patch_stride,
290 rel_patch_id, ""),
291 "");
292 }
293
294 static LLVMValueRef
295 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
296 {
297 struct gallivm_state *gallivm = &ctx->gallivm;
298 LLVMValueRef patch0_patch_data_offset =
299 get_tcs_out_patch0_patch_data_offset(ctx);
300 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
301 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
302
303 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
304 LLVMBuildMul(gallivm->builder, patch_stride,
305 rel_patch_id, ""),
306 "");
307 }
308
309 static LLVMValueRef build_gep0(struct si_shader_context *ctx,
310 LLVMValueRef base_ptr, LLVMValueRef index)
311 {
312 LLVMValueRef indices[2] = {
313 LLVMConstInt(ctx->i32, 0, 0),
314 index,
315 };
316 return LLVMBuildGEP(ctx->gallivm.builder, base_ptr,
317 indices, 2, "");
318 }
319
320 static void build_indexed_store(struct si_shader_context *ctx,
321 LLVMValueRef base_ptr, LLVMValueRef index,
322 LLVMValueRef value)
323 {
324 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
325 struct gallivm_state *gallivm = bld_base->base.gallivm;
326
327 LLVMBuildStore(gallivm->builder, value,
328 build_gep0(ctx, base_ptr, index));
329 }
330
331 /**
332 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
333 * It's equivalent to doing a load from &base_ptr[index].
334 *
335 * \param base_ptr Where the array starts.
336 * \param index The element index into the array.
337 * \param uniform Whether the base_ptr and index can be assumed to be
338 * dynamically uniform
339 */
340 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
341 LLVMValueRef base_ptr, LLVMValueRef index,
342 bool uniform)
343 {
344 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
345 struct gallivm_state *gallivm = bld_base->base.gallivm;
346 LLVMValueRef pointer;
347
348 pointer = build_gep0(ctx, base_ptr, index);
349 if (uniform)
350 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
351 return LLVMBuildLoad(gallivm->builder, pointer, "");
352 }
353
354 /**
355 * Do a load from &base_ptr[index], but also add a flag that it's loading
356 * a constant from a dynamically uniform index.
357 */
358 static LLVMValueRef build_indexed_load_const(
359 struct si_shader_context *ctx,
360 LLVMValueRef base_ptr, LLVMValueRef index)
361 {
362 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
363 LLVMSetMetadata(result, ctx->invariant_load_md_kind, ctx->empty_md);
364 return result;
365 }
366
367 static LLVMValueRef get_instance_index_for_fetch(
368 struct si_shader_context *radeon_bld,
369 unsigned param_start_instance, unsigned divisor)
370 {
371 struct si_shader_context *ctx =
372 si_shader_context(&radeon_bld->soa.bld_base);
373 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
374
375 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
376 ctx->param_instance_id);
377
378 /* The division must be done before START_INSTANCE is added. */
379 if (divisor > 1)
380 result = LLVMBuildUDiv(gallivm->builder, result,
381 lp_build_const_int32(gallivm, divisor), "");
382
383 return LLVMBuildAdd(gallivm->builder, result,
384 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
385 }
386
387 static void declare_input_vs(
388 struct si_shader_context *ctx,
389 unsigned input_index,
390 const struct tgsi_full_declaration *decl,
391 LLVMValueRef out[4])
392 {
393 struct lp_build_context *base = &ctx->soa.bld_base.base;
394 struct gallivm_state *gallivm = base->gallivm;
395
396 unsigned chan;
397 unsigned fix_fetch;
398
399 LLVMValueRef t_list_ptr;
400 LLVMValueRef t_offset;
401 LLVMValueRef t_list;
402 LLVMValueRef attribute_offset;
403 LLVMValueRef buffer_index;
404 LLVMValueRef args[3];
405 LLVMValueRef input;
406
407 /* Load the T list */
408 t_list_ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_VERTEX_BUFFERS);
409
410 t_offset = lp_build_const_int32(gallivm, input_index);
411
412 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
413
414 /* Build the attribute offset */
415 attribute_offset = lp_build_const_int32(gallivm, 0);
416
417 buffer_index = LLVMGetParam(ctx->main_fn,
418 ctx->param_vertex_index0 +
419 input_index);
420
421 args[0] = t_list;
422 args[1] = attribute_offset;
423 args[2] = buffer_index;
424 input = lp_build_intrinsic(gallivm->builder,
425 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
426 LP_FUNC_ATTR_READNONE);
427
428 /* Break up the vec4 into individual components */
429 for (chan = 0; chan < 4; chan++) {
430 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
431 out[chan] = LLVMBuildExtractElement(gallivm->builder,
432 input, llvm_chan, "");
433 }
434
435 fix_fetch = (ctx->shader->key.mono.vs.fix_fetch >> (2 * input_index)) & 3;
436 if (fix_fetch) {
437 /* The hardware returns an unsigned value; convert it to a
438 * signed one.
439 */
440 LLVMValueRef tmp = out[3];
441 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
442
443 /* First, recover the sign-extended signed integer value. */
444 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
445 tmp = LLVMBuildFPToUI(gallivm->builder, tmp, ctx->i32, "");
446 else
447 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->i32, "");
448
449 /* For the integer-like cases, do a natural sign extension.
450 *
451 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
452 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
453 * exponent.
454 */
455 tmp = LLVMBuildShl(gallivm->builder, tmp,
456 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
457 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
458 tmp = LLVMBuildAShr(gallivm->builder, tmp, c30, "");
459
460 /* Convert back to the right type. */
461 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
462 LLVMValueRef clamp;
463 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
464 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
465 clamp = LLVMBuildFCmp(gallivm->builder, LLVMRealULT, tmp, neg_one, "");
466 tmp = LLVMBuildSelect(gallivm->builder, clamp, neg_one, tmp, "");
467 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
468 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
469 }
470
471 out[3] = tmp;
472 }
473 }
474
475 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
476 unsigned swizzle)
477 {
478 struct si_shader_context *ctx = si_shader_context(bld_base);
479
480 if (swizzle > 0)
481 return bld_base->uint_bld.zero;
482
483 switch (ctx->type) {
484 case PIPE_SHADER_VERTEX:
485 return LLVMGetParam(ctx->main_fn,
486 ctx->param_vs_prim_id);
487 case PIPE_SHADER_TESS_CTRL:
488 return LLVMGetParam(ctx->main_fn,
489 SI_PARAM_PATCH_ID);
490 case PIPE_SHADER_TESS_EVAL:
491 return LLVMGetParam(ctx->main_fn,
492 ctx->param_tes_patch_id);
493 case PIPE_SHADER_GEOMETRY:
494 return LLVMGetParam(ctx->main_fn,
495 SI_PARAM_PRIMITIVE_ID);
496 default:
497 assert(0);
498 return bld_base->uint_bld.zero;
499 }
500 }
501
502 /**
503 * Return the value of tgsi_ind_register for indexing.
504 * This is the indirect index with the constant offset added to it.
505 */
506 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
507 const struct tgsi_ind_register *ind,
508 int rel_index)
509 {
510 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
511 LLVMValueRef result;
512
513 result = ctx->soa.addr[ind->Index][ind->Swizzle];
514 result = LLVMBuildLoad(gallivm->builder, result, "");
515 result = LLVMBuildAdd(gallivm->builder, result,
516 lp_build_const_int32(gallivm, rel_index), "");
517 return result;
518 }
519
520 /**
521 * Like get_indirect_index, but restricts the return value to a (possibly
522 * undefined) value inside [0..num).
523 */
524 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
525 const struct tgsi_ind_register *ind,
526 int rel_index, unsigned num)
527 {
528 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
529
530 /* LLVM 3.8: If indirect resource indexing is used:
531 * - SI & CIK hang
532 * - VI crashes
533 */
534 if (HAVE_LLVM <= 0x0308)
535 return LLVMGetUndef(ctx->i32);
536
537 return si_llvm_bound_index(ctx, result, num);
538 }
539
540
541 /**
542 * Calculate a dword address given an input or output register and a stride.
543 */
544 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
545 const struct tgsi_full_dst_register *dst,
546 const struct tgsi_full_src_register *src,
547 LLVMValueRef vertex_dw_stride,
548 LLVMValueRef base_addr)
549 {
550 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
551 struct tgsi_shader_info *info = &ctx->shader->selector->info;
552 ubyte *name, *index, *array_first;
553 int first, param;
554 struct tgsi_full_dst_register reg;
555
556 /* Set the register description. The address computation is the same
557 * for sources and destinations. */
558 if (src) {
559 reg.Register.File = src->Register.File;
560 reg.Register.Index = src->Register.Index;
561 reg.Register.Indirect = src->Register.Indirect;
562 reg.Register.Dimension = src->Register.Dimension;
563 reg.Indirect = src->Indirect;
564 reg.Dimension = src->Dimension;
565 reg.DimIndirect = src->DimIndirect;
566 } else
567 reg = *dst;
568
569 /* If the register is 2-dimensional (e.g. an array of vertices
570 * in a primitive), calculate the base address of the vertex. */
571 if (reg.Register.Dimension) {
572 LLVMValueRef index;
573
574 if (reg.Dimension.Indirect)
575 index = get_indirect_index(ctx, &reg.DimIndirect,
576 reg.Dimension.Index);
577 else
578 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
579
580 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
581 LLVMBuildMul(gallivm->builder, index,
582 vertex_dw_stride, ""), "");
583 }
584
585 /* Get information about the register. */
586 if (reg.Register.File == TGSI_FILE_INPUT) {
587 name = info->input_semantic_name;
588 index = info->input_semantic_index;
589 array_first = info->input_array_first;
590 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
591 name = info->output_semantic_name;
592 index = info->output_semantic_index;
593 array_first = info->output_array_first;
594 } else {
595 assert(0);
596 return NULL;
597 }
598
599 if (reg.Register.Indirect) {
600 /* Add the relative address of the element. */
601 LLVMValueRef ind_index;
602
603 if (reg.Indirect.ArrayID)
604 first = array_first[reg.Indirect.ArrayID];
605 else
606 first = reg.Register.Index;
607
608 ind_index = get_indirect_index(ctx, &reg.Indirect,
609 reg.Register.Index - first);
610
611 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
612 LLVMBuildMul(gallivm->builder, ind_index,
613 lp_build_const_int32(gallivm, 4), ""), "");
614
615 param = si_shader_io_get_unique_index(name[first], index[first]);
616 } else {
617 param = si_shader_io_get_unique_index(name[reg.Register.Index],
618 index[reg.Register.Index]);
619 }
620
621 /* Add the base address of the element. */
622 return LLVMBuildAdd(gallivm->builder, base_addr,
623 lp_build_const_int32(gallivm, param * 4), "");
624 }
625
626 /* The offchip buffer layout for TCS->TES is
627 *
628 * - attribute 0 of patch 0 vertex 0
629 * - attribute 0 of patch 0 vertex 1
630 * - attribute 0 of patch 0 vertex 2
631 * ...
632 * - attribute 0 of patch 1 vertex 0
633 * - attribute 0 of patch 1 vertex 1
634 * ...
635 * - attribute 1 of patch 0 vertex 0
636 * - attribute 1 of patch 0 vertex 1
637 * ...
638 * - per patch attribute 0 of patch 0
639 * - per patch attribute 0 of patch 1
640 * ...
641 *
642 * Note that every attribute has 4 components.
643 */
644 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
645 LLVMValueRef vertex_index,
646 LLVMValueRef param_index)
647 {
648 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
649 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
650 LLVMValueRef param_stride, constant16;
651
652 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
653 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
654 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
655 num_patches, "");
656
657 constant16 = lp_build_const_int32(gallivm, 16);
658 if (vertex_index) {
659 base_addr = LLVMBuildMul(gallivm->builder, get_rel_patch_id(ctx),
660 vertices_per_patch, "");
661
662 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
663 vertex_index, "");
664
665 param_stride = total_vertices;
666 } else {
667 base_addr = get_rel_patch_id(ctx);
668 param_stride = num_patches;
669 }
670
671 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
672 LLVMBuildMul(gallivm->builder, param_index,
673 param_stride, ""), "");
674
675 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
676
677 if (!vertex_index) {
678 LLVMValueRef patch_data_offset =
679 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
680
681 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
682 patch_data_offset, "");
683 }
684 return base_addr;
685 }
686
687 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
688 struct si_shader_context *ctx,
689 const struct tgsi_full_dst_register *dst,
690 const struct tgsi_full_src_register *src)
691 {
692 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
693 struct tgsi_shader_info *info = &ctx->shader->selector->info;
694 ubyte *name, *index, *array_first;
695 struct tgsi_full_src_register reg;
696 LLVMValueRef vertex_index = NULL;
697 LLVMValueRef param_index = NULL;
698 unsigned param_index_base, param_base;
699
700 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
701
702 if (reg.Register.Dimension) {
703
704 if (reg.Dimension.Indirect)
705 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
706 reg.Dimension.Index);
707 else
708 vertex_index = lp_build_const_int32(gallivm,
709 reg.Dimension.Index);
710 }
711
712 /* Get information about the register. */
713 if (reg.Register.File == TGSI_FILE_INPUT) {
714 name = info->input_semantic_name;
715 index = info->input_semantic_index;
716 array_first = info->input_array_first;
717 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
718 name = info->output_semantic_name;
719 index = info->output_semantic_index;
720 array_first = info->output_array_first;
721 } else {
722 assert(0);
723 return NULL;
724 }
725
726 if (reg.Register.Indirect) {
727 if (reg.Indirect.ArrayID)
728 param_base = array_first[reg.Indirect.ArrayID];
729 else
730 param_base = reg.Register.Index;
731
732 param_index = get_indirect_index(ctx, &reg.Indirect,
733 reg.Register.Index - param_base);
734
735 } else {
736 param_base = reg.Register.Index;
737 param_index = lp_build_const_int32(gallivm, 0);
738 }
739
740 param_index_base = si_shader_io_get_unique_index(name[param_base],
741 index[param_base]);
742
743 param_index = LLVMBuildAdd(gallivm->builder, param_index,
744 lp_build_const_int32(gallivm, param_index_base),
745 "");
746
747 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
748 }
749
750 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
751 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
752 * or v4i32 (num_channels=3,4). */
753 static void build_tbuffer_store(struct si_shader_context *ctx,
754 LLVMValueRef rsrc,
755 LLVMValueRef vdata,
756 unsigned num_channels,
757 LLVMValueRef vaddr,
758 LLVMValueRef soffset,
759 unsigned inst_offset,
760 unsigned dfmt,
761 unsigned nfmt,
762 unsigned offen,
763 unsigned idxen,
764 unsigned glc,
765 unsigned slc,
766 unsigned tfe)
767 {
768 struct gallivm_state *gallivm = &ctx->gallivm;
769 LLVMValueRef args[] = {
770 rsrc,
771 vdata,
772 LLVMConstInt(ctx->i32, num_channels, 0),
773 vaddr,
774 soffset,
775 LLVMConstInt(ctx->i32, inst_offset, 0),
776 LLVMConstInt(ctx->i32, dfmt, 0),
777 LLVMConstInt(ctx->i32, nfmt, 0),
778 LLVMConstInt(ctx->i32, offen, 0),
779 LLVMConstInt(ctx->i32, idxen, 0),
780 LLVMConstInt(ctx->i32, glc, 0),
781 LLVMConstInt(ctx->i32, slc, 0),
782 LLVMConstInt(ctx->i32, tfe, 0)
783 };
784
785 /* The instruction offset field has 12 bits */
786 assert(offen || inst_offset < (1 << 12));
787
788 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
789 unsigned func = CLAMP(num_channels, 1, 3) - 1;
790 const char *types[] = {"i32", "v2i32", "v4i32"};
791 char name[256];
792 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
793
794 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
795 args, ARRAY_SIZE(args), 0);
796 }
797
798 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
799 LLVMValueRef rsrc,
800 LLVMValueRef vdata,
801 unsigned num_channels,
802 LLVMValueRef vaddr,
803 LLVMValueRef soffset,
804 unsigned inst_offset)
805 {
806 static unsigned dfmt[] = {
807 V_008F0C_BUF_DATA_FORMAT_32,
808 V_008F0C_BUF_DATA_FORMAT_32_32,
809 V_008F0C_BUF_DATA_FORMAT_32_32_32,
810 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
811 };
812 assert(num_channels >= 1 && num_channels <= 4);
813
814 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
815 inst_offset, dfmt[num_channels-1],
816 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
817 }
818
819 static LLVMValueRef build_buffer_load(struct si_shader_context *ctx,
820 LLVMValueRef rsrc,
821 int num_channels,
822 LLVMValueRef vindex,
823 LLVMValueRef voffset,
824 LLVMValueRef soffset,
825 unsigned inst_offset,
826 unsigned glc,
827 unsigned slc)
828 {
829 struct gallivm_state *gallivm = &ctx->gallivm;
830 unsigned func = CLAMP(num_channels, 1, 3) - 1;
831
832 if (HAVE_LLVM >= 0x309) {
833 LLVMValueRef args[] = {
834 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, ""),
835 vindex ? vindex : LLVMConstInt(ctx->i32, 0, 0),
836 LLVMConstInt(ctx->i32, inst_offset, 0),
837 LLVMConstInt(ctx->i1, glc, 0),
838 LLVMConstInt(ctx->i1, slc, 0)
839 };
840
841 LLVMTypeRef types[] = {ctx->f32, LLVMVectorType(ctx->f32, 2),
842 ctx->v4f32};
843 const char *type_names[] = {"f32", "v2f32", "v4f32"};
844 char name[256];
845
846 if (voffset) {
847 args[2] = LLVMBuildAdd(gallivm->builder, args[2], voffset,
848 "");
849 }
850
851 if (soffset) {
852 args[2] = LLVMBuildAdd(gallivm->builder, args[2], soffset,
853 "");
854 }
855
856 snprintf(name, sizeof(name), "llvm.amdgcn.buffer.load.%s",
857 type_names[func]);
858
859 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
860 ARRAY_SIZE(args), LP_FUNC_ATTR_READONLY);
861 } else {
862 LLVMValueRef args[] = {
863 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v16i8, ""),
864 voffset ? voffset : vindex,
865 soffset,
866 LLVMConstInt(ctx->i32, inst_offset, 0),
867 LLVMConstInt(ctx->i32, voffset ? 1 : 0, 0), // offen
868 LLVMConstInt(ctx->i32, vindex ? 1 : 0, 0), //idxen
869 LLVMConstInt(ctx->i32, glc, 0),
870 LLVMConstInt(ctx->i32, slc, 0),
871 LLVMConstInt(ctx->i32, 0, 0), // TFE
872 };
873
874 LLVMTypeRef types[] = {ctx->i32, LLVMVectorType(ctx->i32, 2),
875 ctx->v4i32};
876 const char *type_names[] = {"i32", "v2i32", "v4i32"};
877 const char *arg_type = "i32";
878 char name[256];
879
880 if (voffset && vindex) {
881 LLVMValueRef vaddr[] = {vindex, voffset};
882
883 arg_type = "v2i32";
884 args[1] = lp_build_gather_values(gallivm, vaddr, 2);
885 }
886
887 snprintf(name, sizeof(name), "llvm.SI.buffer.load.dword.%s.%s",
888 type_names[func], arg_type);
889
890 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
891 ARRAY_SIZE(args), LP_FUNC_ATTR_READONLY);
892 }
893 }
894
895 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
896 enum tgsi_opcode_type type, unsigned swizzle,
897 LLVMValueRef buffer, LLVMValueRef offset,
898 LLVMValueRef base)
899 {
900 struct si_shader_context *ctx = si_shader_context(bld_base);
901 struct gallivm_state *gallivm = bld_base->base.gallivm;
902 LLVMValueRef value, value2;
903 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
904 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
905
906 if (swizzle == ~0) {
907 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
908 0, 1, 0);
909
910 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
911 }
912
913 if (!tgsi_type_is_64bit(type)) {
914 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
915 0, 1, 0);
916
917 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
918 return LLVMBuildExtractElement(gallivm->builder, value,
919 lp_build_const_int32(gallivm, swizzle), "");
920 }
921
922 value = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
923 swizzle * 4, 1, 0);
924
925 value2 = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
926 swizzle * 4 + 4, 1, 0);
927
928 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
929 }
930
931 /**
932 * Load from LDS.
933 *
934 * \param type output value type
935 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
936 * \param dw_addr address in dwords
937 */
938 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
939 enum tgsi_opcode_type type, unsigned swizzle,
940 LLVMValueRef dw_addr)
941 {
942 struct si_shader_context *ctx = si_shader_context(bld_base);
943 struct gallivm_state *gallivm = bld_base->base.gallivm;
944 LLVMValueRef value;
945
946 if (swizzle == ~0) {
947 LLVMValueRef values[TGSI_NUM_CHANNELS];
948
949 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
950 values[chan] = lds_load(bld_base, type, chan, dw_addr);
951
952 return lp_build_gather_values(bld_base->base.gallivm, values,
953 TGSI_NUM_CHANNELS);
954 }
955
956 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
957 lp_build_const_int32(gallivm, swizzle));
958
959 value = build_indexed_load(ctx, ctx->lds, dw_addr, false);
960 if (tgsi_type_is_64bit(type)) {
961 LLVMValueRef value2;
962 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
963 lp_build_const_int32(gallivm, 1));
964 value2 = build_indexed_load(ctx, ctx->lds, dw_addr, false);
965 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
966 }
967
968 return LLVMBuildBitCast(gallivm->builder, value,
969 tgsi2llvmtype(bld_base, type), "");
970 }
971
972 /**
973 * Store to LDS.
974 *
975 * \param swizzle offset (typically 0..3)
976 * \param dw_addr address in dwords
977 * \param value value to store
978 */
979 static void lds_store(struct lp_build_tgsi_context *bld_base,
980 unsigned swizzle, LLVMValueRef dw_addr,
981 LLVMValueRef value)
982 {
983 struct si_shader_context *ctx = si_shader_context(bld_base);
984 struct gallivm_state *gallivm = bld_base->base.gallivm;
985
986 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
987 lp_build_const_int32(gallivm, swizzle));
988
989 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
990 build_indexed_store(ctx, ctx->lds,
991 dw_addr, value);
992 }
993
994 static LLVMValueRef fetch_input_tcs(
995 struct lp_build_tgsi_context *bld_base,
996 const struct tgsi_full_src_register *reg,
997 enum tgsi_opcode_type type, unsigned swizzle)
998 {
999 struct si_shader_context *ctx = si_shader_context(bld_base);
1000 LLVMValueRef dw_addr, stride;
1001
1002 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
1003 dw_addr = get_tcs_in_current_patch_offset(ctx);
1004 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1005
1006 return lds_load(bld_base, type, swizzle, dw_addr);
1007 }
1008
1009 static LLVMValueRef fetch_output_tcs(
1010 struct lp_build_tgsi_context *bld_base,
1011 const struct tgsi_full_src_register *reg,
1012 enum tgsi_opcode_type type, unsigned swizzle)
1013 {
1014 struct si_shader_context *ctx = si_shader_context(bld_base);
1015 LLVMValueRef dw_addr, stride;
1016
1017 if (reg->Register.Dimension) {
1018 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1019 dw_addr = get_tcs_out_current_patch_offset(ctx);
1020 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1021 } else {
1022 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1023 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1024 }
1025
1026 return lds_load(bld_base, type, swizzle, dw_addr);
1027 }
1028
1029 static LLVMValueRef fetch_input_tes(
1030 struct lp_build_tgsi_context *bld_base,
1031 const struct tgsi_full_src_register *reg,
1032 enum tgsi_opcode_type type, unsigned swizzle)
1033 {
1034 struct si_shader_context *ctx = si_shader_context(bld_base);
1035 struct gallivm_state *gallivm = bld_base->base.gallivm;
1036 LLVMValueRef rw_buffers, buffer, base, addr;
1037
1038 rw_buffers = LLVMGetParam(ctx->main_fn,
1039 SI_PARAM_RW_BUFFERS);
1040 buffer = build_indexed_load_const(ctx, rw_buffers,
1041 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1042
1043 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1044 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1045
1046 return buffer_load(bld_base, type, swizzle, buffer, base, addr);
1047 }
1048
1049 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1050 const struct tgsi_full_instruction *inst,
1051 const struct tgsi_opcode_info *info,
1052 LLVMValueRef dst[4])
1053 {
1054 struct si_shader_context *ctx = si_shader_context(bld_base);
1055 struct gallivm_state *gallivm = bld_base->base.gallivm;
1056 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
1057 unsigned chan_index;
1058 LLVMValueRef dw_addr, stride;
1059 LLVMValueRef rw_buffers, buffer, base, buf_addr;
1060 LLVMValueRef values[4];
1061
1062 /* Only handle per-patch and per-vertex outputs here.
1063 * Vectors will be lowered to scalars and this function will be called again.
1064 */
1065 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1066 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1067 si_llvm_emit_store(bld_base, inst, info, dst);
1068 return;
1069 }
1070
1071 if (reg->Register.Dimension) {
1072 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1073 dw_addr = get_tcs_out_current_patch_offset(ctx);
1074 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1075 } else {
1076 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1077 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1078 }
1079
1080 rw_buffers = LLVMGetParam(ctx->main_fn,
1081 SI_PARAM_RW_BUFFERS);
1082 buffer = build_indexed_load_const(ctx, rw_buffers,
1083 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1084
1085 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1086 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1087
1088
1089 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1090 LLVMValueRef value = dst[chan_index];
1091
1092 if (inst->Instruction.Saturate)
1093 value = si_llvm_saturate(bld_base, value);
1094
1095 lds_store(bld_base, chan_index, dw_addr, value);
1096
1097 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1098 values[chan_index] = value;
1099
1100 if (inst->Dst[0].Register.WriteMask != 0xF) {
1101 build_tbuffer_store_dwords(ctx, buffer, value, 1,
1102 buf_addr, base,
1103 4 * chan_index);
1104 }
1105 }
1106
1107 if (inst->Dst[0].Register.WriteMask == 0xF) {
1108 LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
1109 values, 4);
1110 build_tbuffer_store_dwords(ctx, buffer, value, 4, buf_addr,
1111 base, 0);
1112 }
1113 }
1114
1115 static LLVMValueRef fetch_input_gs(
1116 struct lp_build_tgsi_context *bld_base,
1117 const struct tgsi_full_src_register *reg,
1118 enum tgsi_opcode_type type,
1119 unsigned swizzle)
1120 {
1121 struct lp_build_context *base = &bld_base->base;
1122 struct si_shader_context *ctx = si_shader_context(bld_base);
1123 struct si_shader *shader = ctx->shader;
1124 struct lp_build_context *uint = &ctx->soa.bld_base.uint_bld;
1125 struct gallivm_state *gallivm = base->gallivm;
1126 LLVMValueRef vtx_offset;
1127 LLVMValueRef args[9];
1128 unsigned vtx_offset_param;
1129 struct tgsi_shader_info *info = &shader->selector->info;
1130 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1131 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1132 unsigned param;
1133 LLVMValueRef value;
1134
1135 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1136 return get_primitive_id(bld_base, swizzle);
1137
1138 if (!reg->Register.Dimension)
1139 return NULL;
1140
1141 if (swizzle == ~0) {
1142 LLVMValueRef values[TGSI_NUM_CHANNELS];
1143 unsigned chan;
1144 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1145 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1146 }
1147 return lp_build_gather_values(bld_base->base.gallivm, values,
1148 TGSI_NUM_CHANNELS);
1149 }
1150
1151 /* Get the vertex offset parameter */
1152 vtx_offset_param = reg->Dimension.Index;
1153 if (vtx_offset_param < 2) {
1154 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1155 } else {
1156 assert(vtx_offset_param < 6);
1157 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1158 }
1159 vtx_offset = lp_build_mul_imm(uint,
1160 LLVMGetParam(ctx->main_fn,
1161 vtx_offset_param),
1162 4);
1163
1164 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1165 args[0] = ctx->esgs_ring;
1166 args[1] = vtx_offset;
1167 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
1168 args[3] = uint->zero;
1169 args[4] = uint->one; /* OFFEN */
1170 args[5] = uint->zero; /* IDXEN */
1171 args[6] = uint->one; /* GLC */
1172 args[7] = uint->zero; /* SLC */
1173 args[8] = uint->zero; /* TFE */
1174
1175 value = lp_build_intrinsic(gallivm->builder,
1176 "llvm.SI.buffer.load.dword.i32.i32",
1177 ctx->i32, args, 9,
1178 LP_FUNC_ATTR_READONLY);
1179 if (tgsi_type_is_64bit(type)) {
1180 LLVMValueRef value2;
1181 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
1182 value2 = lp_build_intrinsic(gallivm->builder,
1183 "llvm.SI.buffer.load.dword.i32.i32",
1184 ctx->i32, args, 9,
1185 LP_FUNC_ATTR_READONLY);
1186 return si_llvm_emit_fetch_64bit(bld_base, type,
1187 value, value2);
1188 }
1189 return LLVMBuildBitCast(gallivm->builder,
1190 value,
1191 tgsi2llvmtype(bld_base, type), "");
1192 }
1193
1194 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1195 {
1196 switch (interpolate) {
1197 case TGSI_INTERPOLATE_CONSTANT:
1198 return 0;
1199
1200 case TGSI_INTERPOLATE_LINEAR:
1201 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1202 return SI_PARAM_LINEAR_SAMPLE;
1203 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1204 return SI_PARAM_LINEAR_CENTROID;
1205 else
1206 return SI_PARAM_LINEAR_CENTER;
1207 break;
1208 case TGSI_INTERPOLATE_COLOR:
1209 case TGSI_INTERPOLATE_PERSPECTIVE:
1210 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1211 return SI_PARAM_PERSP_SAMPLE;
1212 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1213 return SI_PARAM_PERSP_CENTROID;
1214 else
1215 return SI_PARAM_PERSP_CENTER;
1216 break;
1217 default:
1218 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1219 return -1;
1220 }
1221 }
1222
1223 static LLVMValueRef build_fs_interp(
1224 struct lp_build_tgsi_context *bld_base,
1225 LLVMValueRef llvm_chan,
1226 LLVMValueRef attr_number,
1227 LLVMValueRef params,
1228 LLVMValueRef i,
1229 LLVMValueRef j) {
1230
1231 struct si_shader_context *ctx = si_shader_context(bld_base);
1232 struct gallivm_state *gallivm = bld_base->base.gallivm;
1233 LLVMValueRef args[5];
1234 LLVMValueRef p1;
1235 if (HAVE_LLVM < 0x0400) {
1236 LLVMValueRef ij[2];
1237 ij[0] = LLVMBuildBitCast(gallivm->builder, i, ctx->i32, "");
1238 ij[1] = LLVMBuildBitCast(gallivm->builder, j, ctx->i32, "");
1239
1240 args[0] = llvm_chan;
1241 args[1] = attr_number;
1242 args[2] = params;
1243 args[3] = lp_build_gather_values(gallivm, ij, 2);
1244 return lp_build_intrinsic(gallivm->builder, "llvm.fs.interp",
1245 ctx->f32, args, 4,
1246 LP_FUNC_ATTR_READNONE);
1247 }
1248
1249 args[0] = i;
1250 args[1] = llvm_chan;
1251 args[2] = attr_number;
1252 args[3] = params;
1253
1254 p1 = lp_build_intrinsic(gallivm->builder, "llvm.amdgcn.interp.p1",
1255 ctx->f32, args, 4, LP_FUNC_ATTR_READNONE);
1256
1257 args[0] = p1;
1258 args[1] = j;
1259 args[2] = llvm_chan;
1260 args[3] = attr_number;
1261 args[4] = params;
1262
1263 return lp_build_intrinsic(gallivm->builder, "llvm.amdgcn.interp.p2",
1264 ctx->f32, args, 5, LP_FUNC_ATTR_READNONE);
1265 }
1266
1267 static LLVMValueRef build_fs_interp_mov(
1268 struct lp_build_tgsi_context *bld_base,
1269 LLVMValueRef parameter,
1270 LLVMValueRef llvm_chan,
1271 LLVMValueRef attr_number,
1272 LLVMValueRef params) {
1273
1274 struct si_shader_context *ctx = si_shader_context(bld_base);
1275 struct gallivm_state *gallivm = bld_base->base.gallivm;
1276 LLVMValueRef args[4];
1277 if (HAVE_LLVM < 0x0400) {
1278 args[0] = llvm_chan;
1279 args[1] = attr_number;
1280 args[2] = params;
1281
1282 return lp_build_intrinsic(gallivm->builder,
1283 "llvm.SI.fs.constant",
1284 ctx->f32, args, 3,
1285 LP_FUNC_ATTR_READNONE);
1286 }
1287
1288 args[0] = parameter;
1289 args[1] = llvm_chan;
1290 args[2] = attr_number;
1291 args[3] = params;
1292
1293 return lp_build_intrinsic(gallivm->builder, "llvm.amdgcn.interp.mov",
1294 ctx->f32, args, 4, LP_FUNC_ATTR_READNONE);
1295 }
1296
1297 /**
1298 * Interpolate a fragment shader input.
1299 *
1300 * @param ctx context
1301 * @param input_index index of the input in hardware
1302 * @param semantic_name TGSI_SEMANTIC_*
1303 * @param semantic_index semantic index
1304 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1305 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1306 * @param interp_param interpolation weights (i,j)
1307 * @param prim_mask SI_PARAM_PRIM_MASK
1308 * @param face SI_PARAM_FRONT_FACE
1309 * @param result the return value (4 components)
1310 */
1311 static void interp_fs_input(struct si_shader_context *ctx,
1312 unsigned input_index,
1313 unsigned semantic_name,
1314 unsigned semantic_index,
1315 unsigned num_interp_inputs,
1316 unsigned colors_read_mask,
1317 LLVMValueRef interp_param,
1318 LLVMValueRef prim_mask,
1319 LLVMValueRef face,
1320 LLVMValueRef result[4])
1321 {
1322 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
1323 struct lp_build_context *base = &bld_base->base;
1324 struct lp_build_context *uint = &bld_base->uint_bld;
1325 struct gallivm_state *gallivm = base->gallivm;
1326 LLVMValueRef attr_number;
1327 LLVMValueRef i, j;
1328
1329 unsigned chan;
1330
1331 /* fs.constant returns the param from the middle vertex, so it's not
1332 * really useful for flat shading. It's meant to be used for custom
1333 * interpolation (but the intrinsic can't fetch from the other two
1334 * vertices).
1335 *
1336 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1337 * to do the right thing. The only reason we use fs.constant is that
1338 * fs.interp cannot be used on integers, because they can be equal
1339 * to NaN.
1340 *
1341 * When interp is false we will use fs.constant or for newer llvm,
1342 * amdgcn.interp.mov.
1343 */
1344 bool interp = interp_param != NULL;
1345
1346 attr_number = lp_build_const_int32(gallivm, input_index);
1347
1348 if (interp) {
1349 interp_param = LLVMBuildBitCast(gallivm->builder, interp_param,
1350 LLVMVectorType(ctx->f32, 2), "");
1351
1352 i = LLVMBuildExtractElement(gallivm->builder, interp_param,
1353 uint->zero, "");
1354 j = LLVMBuildExtractElement(gallivm->builder, interp_param,
1355 uint->one, "");
1356 }
1357
1358 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1359 ctx->shader->key.part.ps.prolog.color_two_side) {
1360 LLVMValueRef is_face_positive;
1361 LLVMValueRef back_attr_number;
1362
1363 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1364 * otherwise it's at offset "num_inputs".
1365 */
1366 unsigned back_attr_offset = num_interp_inputs;
1367 if (semantic_index == 1 && colors_read_mask & 0xf)
1368 back_attr_offset += 1;
1369
1370 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1371
1372 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1373 face, uint->zero, "");
1374
1375 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1376 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1377 LLVMValueRef front, back;
1378
1379 if (interp) {
1380 front = build_fs_interp(bld_base, llvm_chan,
1381 attr_number, prim_mask,
1382 i, j);
1383 back = build_fs_interp(bld_base, llvm_chan,
1384 back_attr_number, prim_mask,
1385 i, j);
1386 } else {
1387 front = build_fs_interp_mov(bld_base,
1388 lp_build_const_int32(gallivm, 2), /* P0 */
1389 llvm_chan, attr_number, prim_mask);
1390 back = build_fs_interp_mov(bld_base,
1391 lp_build_const_int32(gallivm, 2), /* P0 */
1392 llvm_chan, back_attr_number, prim_mask);
1393 }
1394
1395 result[chan] = LLVMBuildSelect(gallivm->builder,
1396 is_face_positive,
1397 front,
1398 back,
1399 "");
1400 }
1401 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1402 if (interp) {
1403 result[0] = build_fs_interp(bld_base, uint->zero,
1404 attr_number, prim_mask, i, j);
1405 } else {
1406 result[0] = build_fs_interp_mov(bld_base, uint->zero,
1407 lp_build_const_int32(gallivm, 2), /* P0 */
1408 attr_number, prim_mask);
1409 }
1410 result[1] =
1411 result[2] = lp_build_const_float(gallivm, 0.0f);
1412 result[3] = lp_build_const_float(gallivm, 1.0f);
1413 } else {
1414 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1415 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1416
1417 if (interp) {
1418 result[chan] = build_fs_interp(bld_base,
1419 llvm_chan, attr_number, prim_mask, i, j);
1420 } else {
1421 result[chan] = build_fs_interp_mov(bld_base,
1422 lp_build_const_int32(gallivm, 2), /* P0 */
1423 llvm_chan, attr_number, prim_mask);
1424 }
1425 }
1426 }
1427 }
1428
1429 static void declare_input_fs(
1430 struct si_shader_context *radeon_bld,
1431 unsigned input_index,
1432 const struct tgsi_full_declaration *decl,
1433 LLVMValueRef out[4])
1434 {
1435 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
1436 struct si_shader_context *ctx =
1437 si_shader_context(&radeon_bld->soa.bld_base);
1438 struct si_shader *shader = ctx->shader;
1439 LLVMValueRef main_fn = radeon_bld->main_fn;
1440 LLVMValueRef interp_param = NULL;
1441 int interp_param_idx;
1442
1443 /* Get colors from input VGPRs (set by the prolog). */
1444 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1445 unsigned i = decl->Semantic.Index;
1446 unsigned colors_read = shader->selector->info.colors_read;
1447 unsigned mask = colors_read >> (i * 4);
1448 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1449 (i ? util_bitcount(colors_read & 0xf) : 0);
1450
1451 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1452 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1453 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1454 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1455 return;
1456 }
1457
1458 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1459 decl->Interp.Location);
1460 if (interp_param_idx == -1)
1461 return;
1462 else if (interp_param_idx) {
1463 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1464 }
1465
1466 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
1467 decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR &&
1468 ctx->shader->key.part.ps.prolog.flatshade_colors)
1469 interp_param = NULL; /* load the constant color */
1470
1471 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1472 decl->Semantic.Index, shader->selector->info.num_inputs,
1473 shader->selector->info.colors_read, interp_param,
1474 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1475 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1476 &out[0]);
1477 }
1478
1479 static LLVMValueRef get_sample_id(struct si_shader_context *radeon_bld)
1480 {
1481 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1482 SI_PARAM_ANCILLARY, 8, 4);
1483 }
1484
1485 /**
1486 * Set range metadata on an instruction. This can only be used on load and
1487 * call instructions. If you know an instruction can only produce the values
1488 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1489 * \p lo is the minimum value inclusive.
1490 * \p hi is the maximum value exclusive.
1491 */
1492 static void set_range_metadata(struct si_shader_context *ctx,
1493 LLVMValueRef value, unsigned lo, unsigned hi)
1494 {
1495 LLVMValueRef range_md, md_args[2];
1496 LLVMTypeRef type = LLVMTypeOf(value);
1497 LLVMContextRef context = LLVMGetTypeContext(type);
1498
1499 md_args[0] = LLVMConstInt(type, lo, false);
1500 md_args[1] = LLVMConstInt(type, hi, false);
1501 range_md = LLVMMDNodeInContext(context, md_args, 2);
1502 LLVMSetMetadata(value, ctx->range_md_kind, range_md);
1503 }
1504
1505 static LLVMValueRef get_thread_id(struct si_shader_context *ctx)
1506 {
1507 struct gallivm_state *gallivm = &ctx->gallivm;
1508 LLVMValueRef tid;
1509
1510 if (HAVE_LLVM < 0x0308) {
1511 tid = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid",
1512 ctx->i32, NULL, 0, LP_FUNC_ATTR_READNONE);
1513 } else {
1514 LLVMValueRef tid_args[2];
1515 tid_args[0] = lp_build_const_int32(gallivm, 0xffffffff);
1516 tid_args[1] = lp_build_const_int32(gallivm, 0);
1517 tid_args[1] = lp_build_intrinsic(gallivm->builder,
1518 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1519 tid_args, 2, LP_FUNC_ATTR_READNONE);
1520
1521 tid = lp_build_intrinsic(gallivm->builder,
1522 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1523 tid_args, 2, LP_FUNC_ATTR_READNONE);
1524 }
1525 set_range_metadata(ctx, tid, 0, 64);
1526 return tid;
1527 }
1528
1529 /**
1530 * Load a dword from a constant buffer.
1531 */
1532 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1533 LLVMValueRef resource,
1534 LLVMValueRef offset)
1535 {
1536 LLVMBuilderRef builder = ctx->gallivm.builder;
1537 LLVMValueRef args[2] = {resource, offset};
1538
1539 return lp_build_intrinsic(builder, "llvm.SI.load.const", ctx->f32, args, 2,
1540 LP_FUNC_ATTR_READNONE);
1541 }
1542
1543 static LLVMValueRef load_sample_position(struct si_shader_context *radeon_bld, LLVMValueRef sample_id)
1544 {
1545 struct si_shader_context *ctx =
1546 si_shader_context(&radeon_bld->soa.bld_base);
1547 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1548 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1549 LLVMBuilderRef builder = gallivm->builder;
1550 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1551 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1552 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1553
1554 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1555 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1556 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1557
1558 LLVMValueRef pos[4] = {
1559 buffer_load_const(ctx, resource, offset0),
1560 buffer_load_const(ctx, resource, offset1),
1561 lp_build_const_float(gallivm, 0),
1562 lp_build_const_float(gallivm, 0)
1563 };
1564
1565 return lp_build_gather_values(gallivm, pos, 4);
1566 }
1567
1568 static void declare_system_value(
1569 struct si_shader_context *radeon_bld,
1570 unsigned index,
1571 const struct tgsi_full_declaration *decl)
1572 {
1573 struct si_shader_context *ctx =
1574 si_shader_context(&radeon_bld->soa.bld_base);
1575 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1576 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1577 LLVMValueRef value = 0;
1578
1579 switch (decl->Semantic.Name) {
1580 case TGSI_SEMANTIC_INSTANCEID:
1581 value = LLVMGetParam(radeon_bld->main_fn,
1582 ctx->param_instance_id);
1583 break;
1584
1585 case TGSI_SEMANTIC_VERTEXID:
1586 value = LLVMBuildAdd(gallivm->builder,
1587 LLVMGetParam(radeon_bld->main_fn,
1588 ctx->param_vertex_id),
1589 LLVMGetParam(radeon_bld->main_fn,
1590 SI_PARAM_BASE_VERTEX), "");
1591 break;
1592
1593 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1594 value = LLVMGetParam(radeon_bld->main_fn,
1595 ctx->param_vertex_id);
1596 break;
1597
1598 case TGSI_SEMANTIC_BASEVERTEX:
1599 value = LLVMGetParam(radeon_bld->main_fn,
1600 SI_PARAM_BASE_VERTEX);
1601 break;
1602
1603 case TGSI_SEMANTIC_BASEINSTANCE:
1604 value = LLVMGetParam(radeon_bld->main_fn,
1605 SI_PARAM_START_INSTANCE);
1606 break;
1607
1608 case TGSI_SEMANTIC_DRAWID:
1609 value = LLVMGetParam(radeon_bld->main_fn,
1610 SI_PARAM_DRAWID);
1611 break;
1612
1613 case TGSI_SEMANTIC_INVOCATIONID:
1614 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1615 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1616 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1617 value = LLVMGetParam(radeon_bld->main_fn,
1618 SI_PARAM_GS_INSTANCE_ID);
1619 else
1620 assert(!"INVOCATIONID not implemented");
1621 break;
1622
1623 case TGSI_SEMANTIC_POSITION:
1624 {
1625 LLVMValueRef pos[4] = {
1626 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1627 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1628 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1629 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1630 LLVMGetParam(radeon_bld->main_fn,
1631 SI_PARAM_POS_W_FLOAT)),
1632 };
1633 value = lp_build_gather_values(gallivm, pos, 4);
1634 break;
1635 }
1636
1637 case TGSI_SEMANTIC_FACE:
1638 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1639 break;
1640
1641 case TGSI_SEMANTIC_SAMPLEID:
1642 value = get_sample_id(radeon_bld);
1643 break;
1644
1645 case TGSI_SEMANTIC_SAMPLEPOS: {
1646 LLVMValueRef pos[4] = {
1647 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1648 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1649 lp_build_const_float(gallivm, 0),
1650 lp_build_const_float(gallivm, 0)
1651 };
1652 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1653 TGSI_OPCODE_FRC, pos[0]);
1654 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1655 TGSI_OPCODE_FRC, pos[1]);
1656 value = lp_build_gather_values(gallivm, pos, 4);
1657 break;
1658 }
1659
1660 case TGSI_SEMANTIC_SAMPLEMASK:
1661 /* This can only occur with the OpenGL Core profile, which
1662 * doesn't support smoothing.
1663 */
1664 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1665 break;
1666
1667 case TGSI_SEMANTIC_TESSCOORD:
1668 {
1669 LLVMValueRef coord[4] = {
1670 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1671 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1672 bld->zero,
1673 bld->zero
1674 };
1675
1676 /* For triangles, the vector should be (u, v, 1-u-v). */
1677 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1678 PIPE_PRIM_TRIANGLES)
1679 coord[2] = lp_build_sub(bld, bld->one,
1680 lp_build_add(bld, coord[0], coord[1]));
1681
1682 value = lp_build_gather_values(gallivm, coord, 4);
1683 break;
1684 }
1685
1686 case TGSI_SEMANTIC_VERTICESIN:
1687 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1688 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1689 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1690 value = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 7);
1691 else
1692 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1693 break;
1694
1695 case TGSI_SEMANTIC_TESSINNER:
1696 case TGSI_SEMANTIC_TESSOUTER:
1697 {
1698 LLVMValueRef rw_buffers, buffer, base, addr;
1699 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1700
1701 rw_buffers = LLVMGetParam(ctx->main_fn,
1702 SI_PARAM_RW_BUFFERS);
1703 buffer = build_indexed_load_const(ctx, rw_buffers,
1704 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1705
1706 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1707 addr = get_tcs_tes_buffer_address(ctx, NULL,
1708 lp_build_const_int32(gallivm, param));
1709
1710 value = buffer_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1711 ~0, buffer, base, addr);
1712
1713 break;
1714 }
1715
1716 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1717 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1718 {
1719 LLVMValueRef buf, slot, val[4];
1720 int i, offset;
1721
1722 slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
1723 buf = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1724 buf = build_indexed_load_const(ctx, buf, slot);
1725 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1726
1727 for (i = 0; i < 4; i++)
1728 val[i] = buffer_load_const(ctx, buf,
1729 lp_build_const_int32(gallivm, (offset + i) * 4));
1730 value = lp_build_gather_values(gallivm, val, 4);
1731 break;
1732 }
1733
1734 case TGSI_SEMANTIC_PRIMID:
1735 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1736 break;
1737
1738 case TGSI_SEMANTIC_GRID_SIZE:
1739 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1740 break;
1741
1742 case TGSI_SEMANTIC_BLOCK_SIZE:
1743 {
1744 LLVMValueRef values[3];
1745 unsigned i;
1746 unsigned *properties = ctx->shader->selector->info.properties;
1747
1748 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1749 unsigned sizes[3] = {
1750 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1751 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1752 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1753 };
1754
1755 for (i = 0; i < 3; ++i)
1756 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1757
1758 value = lp_build_gather_values(gallivm, values, 3);
1759 } else {
1760 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_SIZE);
1761 }
1762 break;
1763 }
1764
1765 case TGSI_SEMANTIC_BLOCK_ID:
1766 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1767 break;
1768
1769 case TGSI_SEMANTIC_THREAD_ID:
1770 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1771 break;
1772
1773 #if HAVE_LLVM >= 0x0309
1774 case TGSI_SEMANTIC_HELPER_INVOCATION:
1775 value = lp_build_intrinsic(gallivm->builder,
1776 "llvm.amdgcn.ps.live",
1777 ctx->i1, NULL, 0,
1778 LP_FUNC_ATTR_READNONE);
1779 value = LLVMBuildNot(gallivm->builder, value, "");
1780 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1781 break;
1782 #endif
1783
1784 default:
1785 assert(!"unknown system value");
1786 return;
1787 }
1788
1789 radeon_bld->system_values[index] = value;
1790 }
1791
1792 static void declare_compute_memory(struct si_shader_context *radeon_bld,
1793 const struct tgsi_full_declaration *decl)
1794 {
1795 struct si_shader_context *ctx =
1796 si_shader_context(&radeon_bld->soa.bld_base);
1797 struct si_shader_selector *sel = ctx->shader->selector;
1798 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1799
1800 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1801 LLVMValueRef var;
1802
1803 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1804 assert(decl->Range.First == decl->Range.Last);
1805 assert(!ctx->shared_memory);
1806
1807 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1808 LLVMArrayType(ctx->i8, sel->local_size),
1809 "compute_lds",
1810 LOCAL_ADDR_SPACE);
1811 LLVMSetAlignment(var, 4);
1812
1813 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1814 }
1815
1816 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1817 {
1818 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1819 SI_PARAM_CONST_BUFFERS);
1820
1821 return build_indexed_load_const(ctx, list_ptr,
1822 LLVMConstInt(ctx->i32, i, 0));
1823 }
1824
1825 static LLVMValueRef fetch_constant(
1826 struct lp_build_tgsi_context *bld_base,
1827 const struct tgsi_full_src_register *reg,
1828 enum tgsi_opcode_type type,
1829 unsigned swizzle)
1830 {
1831 struct si_shader_context *ctx = si_shader_context(bld_base);
1832 struct lp_build_context *base = &bld_base->base;
1833 const struct tgsi_ind_register *ireg = &reg->Indirect;
1834 unsigned buf, idx;
1835
1836 LLVMValueRef addr, bufp;
1837 LLVMValueRef result;
1838
1839 if (swizzle == LP_CHAN_ALL) {
1840 unsigned chan;
1841 LLVMValueRef values[4];
1842 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1843 values[chan] = fetch_constant(bld_base, reg, type, chan);
1844
1845 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1846 }
1847
1848 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1849 idx = reg->Register.Index * 4 + swizzle;
1850
1851 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1852 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_CONST_BUFFERS);
1853 LLVMValueRef index;
1854 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1855 reg->Dimension.Index,
1856 SI_NUM_CONST_BUFFERS);
1857 bufp = build_indexed_load_const(ctx, ptr, index);
1858 } else
1859 bufp = load_const_buffer_desc(ctx, buf);
1860
1861 if (reg->Register.Indirect) {
1862 addr = ctx->soa.addr[ireg->Index][ireg->Swizzle];
1863 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1864 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1865 addr = lp_build_add(&bld_base->uint_bld, addr,
1866 lp_build_const_int32(base->gallivm, idx * 4));
1867 } else {
1868 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
1869 }
1870
1871 result = buffer_load_const(ctx, bufp, addr);
1872
1873 if (!tgsi_type_is_64bit(type))
1874 result = bitcast(bld_base, type, result);
1875 else {
1876 LLVMValueRef addr2, result2;
1877
1878 addr2 = lp_build_add(&bld_base->uint_bld, addr,
1879 LLVMConstInt(ctx->i32, 4, 0));
1880 result2 = buffer_load_const(ctx, bufp, addr2);
1881
1882 result = si_llvm_emit_fetch_64bit(bld_base, type,
1883 result, result2);
1884 }
1885 return result;
1886 }
1887
1888 /* Upper 16 bits must be zero. */
1889 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1890 LLVMValueRef val[2])
1891 {
1892 return LLVMBuildOr(gallivm->builder, val[0],
1893 LLVMBuildShl(gallivm->builder, val[1],
1894 lp_build_const_int32(gallivm, 16),
1895 ""), "");
1896 }
1897
1898 /* Upper 16 bits are ignored and will be dropped. */
1899 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1900 LLVMValueRef val[2])
1901 {
1902 LLVMValueRef v[2] = {
1903 LLVMBuildAnd(gallivm->builder, val[0],
1904 lp_build_const_int32(gallivm, 0xffff), ""),
1905 val[1],
1906 };
1907 return si_llvm_pack_two_int16(gallivm, v);
1908 }
1909
1910 /* Initialize arguments for the shader export intrinsic */
1911 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1912 LLVMValueRef *values,
1913 unsigned target,
1914 LLVMValueRef *args)
1915 {
1916 struct si_shader_context *ctx = si_shader_context(bld_base);
1917 struct lp_build_context *uint =
1918 &ctx->soa.bld_base.uint_bld;
1919 struct lp_build_context *base = &bld_base->base;
1920 struct gallivm_state *gallivm = base->gallivm;
1921 LLVMBuilderRef builder = base->gallivm->builder;
1922 LLVMValueRef val[4];
1923 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1924 unsigned chan;
1925 bool is_int8;
1926
1927 /* Default is 0xf. Adjusted below depending on the format. */
1928 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1929
1930 /* Specify whether the EXEC mask represents the valid mask */
1931 args[1] = uint->zero;
1932
1933 /* Specify whether this is the last export */
1934 args[2] = uint->zero;
1935
1936 /* Specify the target we are exporting */
1937 args[3] = lp_build_const_int32(base->gallivm, target);
1938
1939 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1940 const struct si_shader_key *key = &ctx->shader->key;
1941 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
1942 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1943
1944 assert(cbuf >= 0 && cbuf < 8);
1945 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1946 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
1947 }
1948
1949 args[4] = uint->zero; /* COMPR flag */
1950 args[5] = base->undef;
1951 args[6] = base->undef;
1952 args[7] = base->undef;
1953 args[8] = base->undef;
1954
1955 switch (spi_shader_col_format) {
1956 case V_028714_SPI_SHADER_ZERO:
1957 args[0] = uint->zero; /* writemask */
1958 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
1959 break;
1960
1961 case V_028714_SPI_SHADER_32_R:
1962 args[0] = uint->one; /* writemask */
1963 args[5] = values[0];
1964 break;
1965
1966 case V_028714_SPI_SHADER_32_GR:
1967 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
1968 args[5] = values[0];
1969 args[6] = values[1];
1970 break;
1971
1972 case V_028714_SPI_SHADER_32_AR:
1973 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
1974 args[5] = values[0];
1975 args[8] = values[3];
1976 break;
1977
1978 case V_028714_SPI_SHADER_FP16_ABGR:
1979 args[4] = uint->one; /* COMPR flag */
1980
1981 for (chan = 0; chan < 2; chan++) {
1982 LLVMValueRef pack_args[2] = {
1983 values[2 * chan],
1984 values[2 * chan + 1]
1985 };
1986 LLVMValueRef packed;
1987
1988 packed = lp_build_intrinsic(base->gallivm->builder,
1989 "llvm.SI.packf16",
1990 ctx->i32, pack_args, 2,
1991 LP_FUNC_ATTR_READNONE);
1992 args[chan + 5] =
1993 LLVMBuildBitCast(base->gallivm->builder,
1994 packed, ctx->f32, "");
1995 }
1996 break;
1997
1998 case V_028714_SPI_SHADER_UNORM16_ABGR:
1999 for (chan = 0; chan < 4; chan++) {
2000 val[chan] = si_llvm_saturate(bld_base, values[chan]);
2001 val[chan] = LLVMBuildFMul(builder, val[chan],
2002 lp_build_const_float(gallivm, 65535), "");
2003 val[chan] = LLVMBuildFAdd(builder, val[chan],
2004 lp_build_const_float(gallivm, 0.5), "");
2005 val[chan] = LLVMBuildFPToUI(builder, val[chan],
2006 ctx->i32, "");
2007 }
2008
2009 args[4] = uint->one; /* COMPR flag */
2010 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2011 si_llvm_pack_two_int16(gallivm, val));
2012 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2013 si_llvm_pack_two_int16(gallivm, val+2));
2014 break;
2015
2016 case V_028714_SPI_SHADER_SNORM16_ABGR:
2017 for (chan = 0; chan < 4; chan++) {
2018 /* Clamp between [-1, 1]. */
2019 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
2020 values[chan],
2021 lp_build_const_float(gallivm, 1));
2022 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
2023 val[chan],
2024 lp_build_const_float(gallivm, -1));
2025 /* Convert to a signed integer in [-32767, 32767]. */
2026 val[chan] = LLVMBuildFMul(builder, val[chan],
2027 lp_build_const_float(gallivm, 32767), "");
2028 /* If positive, add 0.5, else add -0.5. */
2029 val[chan] = LLVMBuildFAdd(builder, val[chan],
2030 LLVMBuildSelect(builder,
2031 LLVMBuildFCmp(builder, LLVMRealOGE,
2032 val[chan], base->zero, ""),
2033 lp_build_const_float(gallivm, 0.5),
2034 lp_build_const_float(gallivm, -0.5), ""), "");
2035 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2036 }
2037
2038 args[4] = uint->one; /* COMPR flag */
2039 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2040 si_llvm_pack_two_int32_as_int16(gallivm, val));
2041 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2042 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2043 break;
2044
2045 case V_028714_SPI_SHADER_UINT16_ABGR: {
2046 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2047 255 : 65535);
2048 /* Clamp. */
2049 for (chan = 0; chan < 4; chan++) {
2050 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2051 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
2052 val[chan], max);
2053 }
2054
2055 args[4] = uint->one; /* COMPR flag */
2056 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2057 si_llvm_pack_two_int16(gallivm, val));
2058 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2059 si_llvm_pack_two_int16(gallivm, val+2));
2060 break;
2061 }
2062
2063 case V_028714_SPI_SHADER_SINT16_ABGR: {
2064 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2065 127 : 32767);
2066 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
2067 -128 : -32768);
2068 /* Clamp. */
2069 for (chan = 0; chan < 4; chan++) {
2070 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2071 val[chan] = lp_build_emit_llvm_binary(bld_base,
2072 TGSI_OPCODE_IMIN,
2073 val[chan], max);
2074 val[chan] = lp_build_emit_llvm_binary(bld_base,
2075 TGSI_OPCODE_IMAX,
2076 val[chan], min);
2077 }
2078
2079 args[4] = uint->one; /* COMPR flag */
2080 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2081 si_llvm_pack_two_int32_as_int16(gallivm, val));
2082 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2083 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2084 break;
2085 }
2086
2087 case V_028714_SPI_SHADER_32_ABGR:
2088 memcpy(&args[5], values, sizeof(values[0]) * 4);
2089 break;
2090 }
2091 }
2092
2093 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2094 LLVMValueRef alpha)
2095 {
2096 struct si_shader_context *ctx = si_shader_context(bld_base);
2097 struct gallivm_state *gallivm = bld_base->base.gallivm;
2098
2099 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2100 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2101 SI_PARAM_ALPHA_REF);
2102
2103 LLVMValueRef alpha_pass =
2104 lp_build_cmp(&bld_base->base,
2105 ctx->shader->key.part.ps.epilog.alpha_func,
2106 alpha, alpha_ref);
2107 LLVMValueRef arg =
2108 lp_build_select(&bld_base->base,
2109 alpha_pass,
2110 lp_build_const_float(gallivm, 1.0f),
2111 lp_build_const_float(gallivm, -1.0f));
2112
2113 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2114 ctx->voidt, &arg, 1, 0);
2115 } else {
2116 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
2117 ctx->voidt, NULL, 0, 0);
2118 }
2119 }
2120
2121 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2122 LLVMValueRef alpha,
2123 unsigned samplemask_param)
2124 {
2125 struct si_shader_context *ctx = si_shader_context(bld_base);
2126 struct gallivm_state *gallivm = bld_base->base.gallivm;
2127 LLVMValueRef coverage;
2128
2129 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2130 coverage = LLVMGetParam(ctx->main_fn,
2131 samplemask_param);
2132 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
2133
2134 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
2135 ctx->i32,
2136 &coverage, 1, LP_FUNC_ATTR_READNONE);
2137
2138 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
2139 ctx->f32, "");
2140
2141 coverage = LLVMBuildFMul(gallivm->builder, coverage,
2142 lp_build_const_float(gallivm,
2143 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2144
2145 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
2146 }
2147
2148 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2149 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
2150 {
2151 struct si_shader_context *ctx = si_shader_context(bld_base);
2152 struct lp_build_context *base = &bld_base->base;
2153 struct lp_build_context *uint = &ctx->soa.bld_base.uint_bld;
2154 unsigned reg_index;
2155 unsigned chan;
2156 unsigned const_chan;
2157 LLVMValueRef base_elt;
2158 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2159 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
2160 SI_VS_CONST_CLIP_PLANES);
2161 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
2162
2163 for (reg_index = 0; reg_index < 2; reg_index ++) {
2164 LLVMValueRef *args = pos[2 + reg_index];
2165
2166 args[5] =
2167 args[6] =
2168 args[7] =
2169 args[8] = lp_build_const_float(base->gallivm, 0.0f);
2170
2171 /* Compute dot products of position and user clip plane vectors */
2172 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2173 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2174 args[1] = lp_build_const_int32(base->gallivm,
2175 ((reg_index * 4 + chan) * 4 +
2176 const_chan) * 4);
2177 base_elt = buffer_load_const(ctx, const_resource,
2178 args[1]);
2179 args[5 + chan] =
2180 lp_build_add(base, args[5 + chan],
2181 lp_build_mul(base, base_elt,
2182 out_elts[const_chan]));
2183 }
2184 }
2185
2186 args[0] = lp_build_const_int32(base->gallivm, 0xf);
2187 args[1] = uint->zero;
2188 args[2] = uint->zero;
2189 args[3] = lp_build_const_int32(base->gallivm,
2190 V_008DFC_SQ_EXP_POS + 2 + reg_index);
2191 args[4] = uint->zero;
2192 }
2193 }
2194
2195 static void si_dump_streamout(struct pipe_stream_output_info *so)
2196 {
2197 unsigned i;
2198
2199 if (so->num_outputs)
2200 fprintf(stderr, "STREAMOUT\n");
2201
2202 for (i = 0; i < so->num_outputs; i++) {
2203 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2204 so->output[i].start_component;
2205 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2206 i, so->output[i].output_buffer,
2207 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2208 so->output[i].register_index,
2209 mask & 1 ? "x" : "",
2210 mask & 2 ? "y" : "",
2211 mask & 4 ? "z" : "",
2212 mask & 8 ? "w" : "");
2213 }
2214 }
2215
2216 /* On SI, the vertex shader is responsible for writing streamout data
2217 * to buffers. */
2218 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2219 struct si_shader_output_values *outputs,
2220 unsigned noutput)
2221 {
2222 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
2223 struct gallivm_state *gallivm = &ctx->gallivm;
2224 LLVMBuilderRef builder = gallivm->builder;
2225 int i, j;
2226 struct lp_build_if_state if_ctx;
2227 LLVMValueRef so_buffers[4];
2228 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2229 SI_PARAM_RW_BUFFERS);
2230
2231 /* Load the descriptors. */
2232 for (i = 0; i < 4; ++i) {
2233 if (ctx->shader->selector->so.stride[i]) {
2234 LLVMValueRef offset = lp_build_const_int32(gallivm,
2235 SI_VS_STREAMOUT_BUF0 + i);
2236
2237 so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
2238 }
2239 }
2240
2241 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2242 LLVMValueRef so_vtx_count =
2243 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2244
2245 LLVMValueRef tid = get_thread_id(ctx);
2246
2247 /* can_emit = tid < so_vtx_count; */
2248 LLVMValueRef can_emit =
2249 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2250
2251 LLVMValueRef stream_id =
2252 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
2253
2254 /* Emit the streamout code conditionally. This actually avoids
2255 * out-of-bounds buffer access. The hw tells us via the SGPR
2256 * (so_vtx_count) which threads are allowed to emit streamout data. */
2257 lp_build_if(&if_ctx, gallivm, can_emit);
2258 {
2259 /* The buffer offset is computed as follows:
2260 * ByteOffset = streamout_offset[buffer_id]*4 +
2261 * (streamout_write_index + thread_id)*stride[buffer_id] +
2262 * attrib_offset
2263 */
2264
2265 LLVMValueRef so_write_index =
2266 LLVMGetParam(ctx->main_fn,
2267 ctx->param_streamout_write_index);
2268
2269 /* Compute (streamout_write_index + thread_id). */
2270 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2271
2272 /* Compute the write offset for each enabled buffer. */
2273 LLVMValueRef so_write_offset[4] = {};
2274 for (i = 0; i < 4; i++) {
2275 if (!so->stride[i])
2276 continue;
2277
2278 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2279 ctx->param_streamout_offset[i]);
2280 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2281
2282 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2283 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2284 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2285 }
2286
2287 /* Write streamout data. */
2288 for (i = 0; i < so->num_outputs; i++) {
2289 unsigned buf_idx = so->output[i].output_buffer;
2290 unsigned reg = so->output[i].register_index;
2291 unsigned start = so->output[i].start_component;
2292 unsigned num_comps = so->output[i].num_components;
2293 unsigned stream = so->output[i].stream;
2294 LLVMValueRef out[4];
2295 struct lp_build_if_state if_ctx_stream;
2296
2297 assert(num_comps && num_comps <= 4);
2298 if (!num_comps || num_comps > 4)
2299 continue;
2300
2301 if (reg >= noutput)
2302 continue;
2303
2304 /* Load the output as int. */
2305 for (j = 0; j < num_comps; j++) {
2306 out[j] = LLVMBuildBitCast(builder,
2307 outputs[reg].values[start+j],
2308 ctx->i32, "");
2309 }
2310
2311 /* Pack the output. */
2312 LLVMValueRef vdata = NULL;
2313
2314 switch (num_comps) {
2315 case 1: /* as i32 */
2316 vdata = out[0];
2317 break;
2318 case 2: /* as v2i32 */
2319 case 3: /* as v4i32 (aligned to 4) */
2320 case 4: /* as v4i32 */
2321 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2322 for (j = 0; j < num_comps; j++) {
2323 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2324 LLVMConstInt(ctx->i32, j, 0), "");
2325 }
2326 break;
2327 }
2328
2329 LLVMValueRef can_emit_stream =
2330 LLVMBuildICmp(builder, LLVMIntEQ,
2331 stream_id,
2332 lp_build_const_int32(gallivm, stream), "");
2333
2334 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
2335 build_tbuffer_store_dwords(ctx, so_buffers[buf_idx],
2336 vdata, num_comps,
2337 so_write_offset[buf_idx],
2338 LLVMConstInt(ctx->i32, 0, 0),
2339 so->output[i].dst_offset*4);
2340 lp_build_endif(&if_ctx_stream);
2341 }
2342 }
2343 lp_build_endif(&if_ctx);
2344 }
2345
2346
2347 /* Generate export instructions for hardware VS shader stage */
2348 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2349 struct si_shader_output_values *outputs,
2350 unsigned noutput)
2351 {
2352 struct si_shader_context *ctx = si_shader_context(bld_base);
2353 struct si_shader *shader = ctx->shader;
2354 struct lp_build_context *base = &bld_base->base;
2355 struct lp_build_context *uint =
2356 &ctx->soa.bld_base.uint_bld;
2357 LLVMValueRef args[9];
2358 LLVMValueRef pos_args[4][9] = { { 0 } };
2359 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2360 unsigned semantic_name, semantic_index;
2361 unsigned target;
2362 unsigned param_count = 0;
2363 unsigned pos_idx;
2364 int i;
2365
2366 if (outputs && ctx->shader->selector->so.num_outputs) {
2367 si_llvm_emit_streamout(ctx, outputs, noutput);
2368 }
2369
2370 for (i = 0; i < noutput; i++) {
2371 semantic_name = outputs[i].name;
2372 semantic_index = outputs[i].sid;
2373 bool export_param = true;
2374
2375 switch (semantic_name) {
2376 case TGSI_SEMANTIC_POSITION: /* ignore these */
2377 case TGSI_SEMANTIC_PSIZE:
2378 case TGSI_SEMANTIC_CLIPVERTEX:
2379 case TGSI_SEMANTIC_EDGEFLAG:
2380 break;
2381 case TGSI_SEMANTIC_GENERIC:
2382 case TGSI_SEMANTIC_CLIPDIST:
2383 if (shader->key.opt.hw_vs.kill_outputs &
2384 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2385 export_param = false;
2386 break;
2387 default:
2388 if (shader->key.opt.hw_vs.kill_outputs2 &
2389 (1u << si_shader_io_get_unique_index2(semantic_name, semantic_index)))
2390 export_param = false;
2391 break;
2392 }
2393
2394 handle_semantic:
2395 /* Select the correct target */
2396 switch(semantic_name) {
2397 case TGSI_SEMANTIC_PSIZE:
2398 psize_value = outputs[i].values[0];
2399 continue;
2400 case TGSI_SEMANTIC_EDGEFLAG:
2401 edgeflag_value = outputs[i].values[0];
2402 continue;
2403 case TGSI_SEMANTIC_LAYER:
2404 layer_value = outputs[i].values[0];
2405 semantic_name = TGSI_SEMANTIC_GENERIC;
2406 goto handle_semantic;
2407 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2408 viewport_index_value = outputs[i].values[0];
2409 semantic_name = TGSI_SEMANTIC_GENERIC;
2410 goto handle_semantic;
2411 case TGSI_SEMANTIC_POSITION:
2412 target = V_008DFC_SQ_EXP_POS;
2413 break;
2414 case TGSI_SEMANTIC_COLOR:
2415 case TGSI_SEMANTIC_BCOLOR:
2416 if (!export_param)
2417 continue;
2418 target = V_008DFC_SQ_EXP_PARAM + param_count;
2419 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2420 shader->info.vs_output_param_offset[i] = param_count;
2421 param_count++;
2422 break;
2423 case TGSI_SEMANTIC_CLIPDIST:
2424 if (shader->key.opt.hw_vs.clip_disable) {
2425 semantic_name = TGSI_SEMANTIC_GENERIC;
2426 goto handle_semantic;
2427 }
2428 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2429 break;
2430 case TGSI_SEMANTIC_CLIPVERTEX:
2431 if (shader->key.opt.hw_vs.clip_disable)
2432 continue;
2433 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2434 continue;
2435 case TGSI_SEMANTIC_PRIMID:
2436 case TGSI_SEMANTIC_FOG:
2437 case TGSI_SEMANTIC_TEXCOORD:
2438 case TGSI_SEMANTIC_GENERIC:
2439 if (!export_param)
2440 continue;
2441 target = V_008DFC_SQ_EXP_PARAM + param_count;
2442 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2443 shader->info.vs_output_param_offset[i] = param_count;
2444 param_count++;
2445 break;
2446 default:
2447 target = 0;
2448 fprintf(stderr,
2449 "Warning: SI unhandled vs output type:%d\n",
2450 semantic_name);
2451 }
2452
2453 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
2454
2455 if (target >= V_008DFC_SQ_EXP_POS &&
2456 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2457 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
2458 args, sizeof(args));
2459 } else {
2460 lp_build_intrinsic(base->gallivm->builder,
2461 "llvm.SI.export", ctx->voidt,
2462 args, 9, 0);
2463 }
2464
2465 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2466 semantic_name = TGSI_SEMANTIC_GENERIC;
2467 goto handle_semantic;
2468 }
2469 }
2470
2471 shader->info.nr_param_exports = param_count;
2472
2473 /* We need to add the position output manually if it's missing. */
2474 if (!pos_args[0][0]) {
2475 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
2476 pos_args[0][1] = uint->zero; /* EXEC mask */
2477 pos_args[0][2] = uint->zero; /* last export? */
2478 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
2479 pos_args[0][4] = uint->zero; /* COMPR flag */
2480 pos_args[0][5] = base->zero; /* X */
2481 pos_args[0][6] = base->zero; /* Y */
2482 pos_args[0][7] = base->zero; /* Z */
2483 pos_args[0][8] = base->one; /* W */
2484 }
2485
2486 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2487 if (shader->selector->info.writes_psize ||
2488 shader->selector->info.writes_edgeflag ||
2489 shader->selector->info.writes_viewport_index ||
2490 shader->selector->info.writes_layer) {
2491 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
2492 shader->selector->info.writes_psize |
2493 (shader->selector->info.writes_edgeflag << 1) |
2494 (shader->selector->info.writes_layer << 2) |
2495 (shader->selector->info.writes_viewport_index << 3));
2496 pos_args[1][1] = uint->zero; /* EXEC mask */
2497 pos_args[1][2] = uint->zero; /* last export? */
2498 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
2499 pos_args[1][4] = uint->zero; /* COMPR flag */
2500 pos_args[1][5] = base->zero; /* X */
2501 pos_args[1][6] = base->zero; /* Y */
2502 pos_args[1][7] = base->zero; /* Z */
2503 pos_args[1][8] = base->zero; /* W */
2504
2505 if (shader->selector->info.writes_psize)
2506 pos_args[1][5] = psize_value;
2507
2508 if (shader->selector->info.writes_edgeflag) {
2509 /* The output is a float, but the hw expects an integer
2510 * with the first bit containing the edge flag. */
2511 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2512 edgeflag_value,
2513 ctx->i32, "");
2514 edgeflag_value = lp_build_min(&bld_base->int_bld,
2515 edgeflag_value,
2516 bld_base->int_bld.one);
2517
2518 /* The LLVM intrinsic expects a float. */
2519 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
2520 edgeflag_value,
2521 ctx->f32, "");
2522 }
2523
2524 if (shader->selector->info.writes_layer)
2525 pos_args[1][7] = layer_value;
2526
2527 if (shader->selector->info.writes_viewport_index)
2528 pos_args[1][8] = viewport_index_value;
2529 }
2530
2531 for (i = 0; i < 4; i++)
2532 if (pos_args[i][0])
2533 shader->info.nr_pos_exports++;
2534
2535 pos_idx = 0;
2536 for (i = 0; i < 4; i++) {
2537 if (!pos_args[i][0])
2538 continue;
2539
2540 /* Specify the target we are exporting */
2541 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2542
2543 if (pos_idx == shader->info.nr_pos_exports)
2544 /* Specify that this is the last export */
2545 pos_args[i][2] = uint->one;
2546
2547 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2548 ctx->voidt, pos_args[i], 9, 0);
2549 }
2550 }
2551
2552 /**
2553 * Forward all outputs from the vertex shader to the TES. This is only used
2554 * for the fixed function TCS.
2555 */
2556 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2557 {
2558 struct si_shader_context *ctx = si_shader_context(bld_base);
2559 struct gallivm_state *gallivm = bld_base->base.gallivm;
2560 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2561 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2562 uint64_t inputs;
2563
2564 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2565
2566 rw_buffers = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2567 buffer = build_indexed_load_const(ctx, rw_buffers,
2568 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
2569
2570 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2571
2572 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
2573 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2574 lds_vertex_stride, "");
2575 lds_base = get_tcs_in_current_patch_offset(ctx);
2576 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2577
2578 inputs = ctx->shader->key.mono.tcs.inputs_to_copy;
2579 while (inputs) {
2580 unsigned i = u_bit_scan64(&inputs);
2581
2582 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2583 lp_build_const_int32(gallivm, 4 * i),
2584 "");
2585
2586 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2587 invocation_id,
2588 lp_build_const_int32(gallivm, i));
2589
2590 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2591 lds_ptr);
2592
2593 build_tbuffer_store_dwords(ctx, buffer, value, 4, buffer_addr,
2594 buffer_offset, 0);
2595 }
2596 }
2597
2598 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2599 LLVMValueRef rel_patch_id,
2600 LLVMValueRef invocation_id,
2601 LLVMValueRef tcs_out_current_patch_data_offset)
2602 {
2603 struct si_shader_context *ctx = si_shader_context(bld_base);
2604 struct gallivm_state *gallivm = bld_base->base.gallivm;
2605 struct si_shader *shader = ctx->shader;
2606 unsigned tess_inner_index, tess_outer_index;
2607 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2608 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2609 unsigned stride, outer_comps, inner_comps, i;
2610 struct lp_build_if_state if_ctx, inner_if_ctx;
2611
2612 si_llvm_emit_barrier(NULL, bld_base, NULL);
2613
2614 /* Do this only for invocation 0, because the tess levels are per-patch,
2615 * not per-vertex.
2616 *
2617 * This can't jump, because invocation 0 executes this. It should
2618 * at least mask out the loads and stores for other invocations.
2619 */
2620 lp_build_if(&if_ctx, gallivm,
2621 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2622 invocation_id, bld_base->uint_bld.zero, ""));
2623
2624 /* Determine the layout of one tess factor element in the buffer. */
2625 switch (shader->key.part.tcs.epilog.prim_mode) {
2626 case PIPE_PRIM_LINES:
2627 stride = 2; /* 2 dwords, 1 vec2 store */
2628 outer_comps = 2;
2629 inner_comps = 0;
2630 break;
2631 case PIPE_PRIM_TRIANGLES:
2632 stride = 4; /* 4 dwords, 1 vec4 store */
2633 outer_comps = 3;
2634 inner_comps = 1;
2635 break;
2636 case PIPE_PRIM_QUADS:
2637 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2638 outer_comps = 4;
2639 inner_comps = 2;
2640 break;
2641 default:
2642 assert(0);
2643 return;
2644 }
2645
2646 /* Load tess_inner and tess_outer from LDS.
2647 * Any invocation can write them, so we can't get them from a temporary.
2648 */
2649 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2650 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2651
2652 lds_base = tcs_out_current_patch_data_offset;
2653 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2654 lp_build_const_int32(gallivm,
2655 tess_inner_index * 4), "");
2656 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2657 lp_build_const_int32(gallivm,
2658 tess_outer_index * 4), "");
2659
2660 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2661 /* For isolines, the hardware expects tess factors in the
2662 * reverse order from what GLSL / TGSI specify.
2663 */
2664 out[0] = lds_load(bld_base, TGSI_TYPE_SIGNED, 1, lds_outer);
2665 out[1] = lds_load(bld_base, TGSI_TYPE_SIGNED, 0, lds_outer);
2666 } else {
2667 for (i = 0; i < outer_comps; i++)
2668 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2669 for (i = 0; i < inner_comps; i++)
2670 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2671 }
2672
2673 /* Convert the outputs to vectors for stores. */
2674 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2675 vec1 = NULL;
2676
2677 if (stride > 4)
2678 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2679
2680 /* Get the buffer. */
2681 rw_buffers = LLVMGetParam(ctx->main_fn,
2682 SI_PARAM_RW_BUFFERS);
2683 buffer = build_indexed_load_const(ctx, rw_buffers,
2684 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2685
2686 /* Get the offset. */
2687 tf_base = LLVMGetParam(ctx->main_fn,
2688 SI_PARAM_TESS_FACTOR_OFFSET);
2689 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2690 lp_build_const_int32(gallivm, 4 * stride), "");
2691
2692 lp_build_if(&inner_if_ctx, gallivm,
2693 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2694 rel_patch_id, bld_base->uint_bld.zero, ""));
2695
2696 /* Store the dynamic HS control word. */
2697 build_tbuffer_store_dwords(ctx, buffer,
2698 lp_build_const_int32(gallivm, 0x80000000),
2699 1, lp_build_const_int32(gallivm, 0), tf_base, 0);
2700
2701 lp_build_endif(&inner_if_ctx);
2702
2703 /* Store the tessellation factors. */
2704 build_tbuffer_store_dwords(ctx, buffer, vec0,
2705 MIN2(stride, 4), byteoffset, tf_base, 4);
2706 if (vec1)
2707 build_tbuffer_store_dwords(ctx, buffer, vec1,
2708 stride - 4, byteoffset, tf_base, 20);
2709 lp_build_endif(&if_ctx);
2710 }
2711
2712 /* This only writes the tessellation factor levels. */
2713 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2714 {
2715 struct si_shader_context *ctx = si_shader_context(bld_base);
2716 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2717
2718 si_copy_tcs_inputs(bld_base);
2719
2720 rel_patch_id = get_rel_patch_id(ctx);
2721 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2722 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2723
2724 /* Return epilog parameters from this function. */
2725 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2726 LLVMValueRef ret = ctx->return_value;
2727 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2728 unsigned vgpr;
2729
2730 /* RW_BUFFERS pointer */
2731 rw_buffers = LLVMGetParam(ctx->main_fn,
2732 SI_PARAM_RW_BUFFERS);
2733 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2734 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2735 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2736 bld_base->uint_bld.zero, "");
2737 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2738 bld_base->uint_bld.one, "");
2739 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2740 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2741
2742 /* Tess factor buffer soffset is after user SGPRs. */
2743 tf_soffset = LLVMGetParam(ctx->main_fn,
2744 SI_PARAM_TESS_FACTOR_OFFSET);
2745 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2746 SI_TCS_NUM_USER_SGPR + 1, "");
2747
2748 /* VGPRs */
2749 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2750 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2751 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2752
2753 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2754 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2755 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2756 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2757 ctx->return_value = ret;
2758 }
2759
2760 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2761 {
2762 struct si_shader_context *ctx = si_shader_context(bld_base);
2763 struct si_shader *shader = ctx->shader;
2764 struct tgsi_shader_info *info = &shader->selector->info;
2765 struct gallivm_state *gallivm = bld_base->base.gallivm;
2766 unsigned i, chan;
2767 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
2768 ctx->param_rel_auto_id);
2769 LLVMValueRef vertex_dw_stride =
2770 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2771 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2772 vertex_dw_stride, "");
2773
2774 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2775 * its inputs from it. */
2776 for (i = 0; i < info->num_outputs; i++) {
2777 LLVMValueRef *out_ptr = ctx->soa.outputs[i];
2778 unsigned name = info->output_semantic_name[i];
2779 unsigned index = info->output_semantic_index[i];
2780 int param = si_shader_io_get_unique_index(name, index);
2781 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2782 lp_build_const_int32(gallivm, param * 4), "");
2783
2784 for (chan = 0; chan < 4; chan++) {
2785 lds_store(bld_base, chan, dw_addr,
2786 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2787 }
2788 }
2789 }
2790
2791 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2792 {
2793 struct si_shader_context *ctx = si_shader_context(bld_base);
2794 struct gallivm_state *gallivm = bld_base->base.gallivm;
2795 struct si_shader *es = ctx->shader;
2796 struct tgsi_shader_info *info = &es->selector->info;
2797 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
2798 ctx->param_es2gs_offset);
2799 unsigned chan;
2800 int i;
2801
2802 for (i = 0; i < info->num_outputs; i++) {
2803 LLVMValueRef *out_ptr =
2804 ctx->soa.outputs[i];
2805 int param_index;
2806
2807 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2808 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2809 continue;
2810
2811 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2812 info->output_semantic_index[i]);
2813
2814 for (chan = 0; chan < 4; chan++) {
2815 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2816 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2817
2818 build_tbuffer_store(ctx,
2819 ctx->esgs_ring,
2820 out_val, 1,
2821 LLVMGetUndef(ctx->i32), soffset,
2822 (4 * param_index + chan) * 4,
2823 V_008F0C_BUF_DATA_FORMAT_32,
2824 V_008F0C_BUF_NUM_FORMAT_UINT,
2825 0, 0, 1, 1, 0);
2826 }
2827 }
2828 }
2829
2830 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2831 {
2832 struct si_shader_context *ctx = si_shader_context(bld_base);
2833 struct gallivm_state *gallivm = bld_base->base.gallivm;
2834 LLVMValueRef args[2];
2835
2836 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2837 args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID);
2838 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2839 ctx->voidt, args, 2, 0);
2840 }
2841
2842 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2843 {
2844 struct si_shader_context *ctx = si_shader_context(bld_base);
2845 struct gallivm_state *gallivm = bld_base->base.gallivm;
2846 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2847 struct si_shader_output_values *outputs = NULL;
2848 int i,j;
2849
2850 assert(!ctx->shader->is_gs_copy_shader);
2851
2852 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2853
2854 /* Vertex color clamping.
2855 *
2856 * This uses a state constant loaded in a user data SGPR and
2857 * an IF statement is added that clamps all colors if the constant
2858 * is true.
2859 */
2860 if (ctx->type == PIPE_SHADER_VERTEX) {
2861 struct lp_build_if_state if_ctx;
2862 LLVMValueRef cond = NULL;
2863 LLVMValueRef addr, val;
2864
2865 for (i = 0; i < info->num_outputs; i++) {
2866 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2867 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2868 continue;
2869
2870 /* We've found a color. */
2871 if (!cond) {
2872 /* The state is in the first bit of the user SGPR. */
2873 cond = LLVMGetParam(ctx->main_fn,
2874 SI_PARAM_VS_STATE_BITS);
2875 cond = LLVMBuildTrunc(gallivm->builder, cond,
2876 ctx->i1, "");
2877 lp_build_if(&if_ctx, gallivm, cond);
2878 }
2879
2880 for (j = 0; j < 4; j++) {
2881 addr = ctx->soa.outputs[i][j];
2882 val = LLVMBuildLoad(gallivm->builder, addr, "");
2883 val = si_llvm_saturate(bld_base, val);
2884 LLVMBuildStore(gallivm->builder, val, addr);
2885 }
2886 }
2887
2888 if (cond)
2889 lp_build_endif(&if_ctx);
2890 }
2891
2892 for (i = 0; i < info->num_outputs; i++) {
2893 outputs[i].name = info->output_semantic_name[i];
2894 outputs[i].sid = info->output_semantic_index[i];
2895
2896 for (j = 0; j < 4; j++)
2897 outputs[i].values[j] =
2898 LLVMBuildLoad(gallivm->builder,
2899 ctx->soa.outputs[i][j],
2900 "");
2901 }
2902
2903 /* Return the primitive ID from the LLVM function. */
2904 ctx->return_value =
2905 LLVMBuildInsertValue(gallivm->builder,
2906 ctx->return_value,
2907 bitcast(bld_base, TGSI_TYPE_FLOAT,
2908 get_primitive_id(bld_base, 0)),
2909 VS_EPILOG_PRIMID_LOC, "");
2910
2911 si_llvm_export_vs(bld_base, outputs, i);
2912 FREE(outputs);
2913 }
2914
2915 struct si_ps_exports {
2916 unsigned num;
2917 LLVMValueRef args[10][9];
2918 };
2919
2920 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
2921 bool writes_samplemask)
2922 {
2923 if (writes_z) {
2924 /* Z needs 32 bits. */
2925 if (writes_samplemask)
2926 return V_028710_SPI_SHADER_32_ABGR;
2927 else if (writes_stencil)
2928 return V_028710_SPI_SHADER_32_GR;
2929 else
2930 return V_028710_SPI_SHADER_32_R;
2931 } else if (writes_stencil || writes_samplemask) {
2932 /* Both stencil and sample mask need only 16 bits. */
2933 return V_028710_SPI_SHADER_UINT16_ABGR;
2934 } else {
2935 return V_028710_SPI_SHADER_ZERO;
2936 }
2937 }
2938
2939 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2940 LLVMValueRef depth, LLVMValueRef stencil,
2941 LLVMValueRef samplemask, struct si_ps_exports *exp)
2942 {
2943 struct si_shader_context *ctx = si_shader_context(bld_base);
2944 struct lp_build_context *base = &bld_base->base;
2945 struct lp_build_context *uint = &bld_base->uint_bld;
2946 LLVMValueRef args[9];
2947 unsigned mask = 0;
2948 unsigned format = si_get_spi_shader_z_format(depth != NULL,
2949 stencil != NULL,
2950 samplemask != NULL);
2951
2952 assert(depth || stencil || samplemask);
2953
2954 args[1] = uint->one; /* whether the EXEC mask is valid */
2955 args[2] = uint->one; /* DONE bit */
2956
2957 /* Specify the target we are exporting */
2958 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2959
2960 args[4] = uint->zero; /* COMP flag */
2961 args[5] = base->undef; /* R, depth */
2962 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2963 args[7] = base->undef; /* B, sample mask */
2964 args[8] = base->undef; /* A, alpha to mask */
2965
2966 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
2967 assert(!depth);
2968 args[4] = uint->one; /* COMPR flag */
2969
2970 if (stencil) {
2971 /* Stencil should be in X[23:16]. */
2972 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
2973 stencil = LLVMBuildShl(base->gallivm->builder, stencil,
2974 LLVMConstInt(ctx->i32, 16, 0), "");
2975 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
2976 mask |= 0x3;
2977 }
2978 if (samplemask) {
2979 /* SampleMask should be in Y[15:0]. */
2980 args[6] = samplemask;
2981 mask |= 0xc;
2982 }
2983 } else {
2984 if (depth) {
2985 args[5] = depth;
2986 mask |= 0x1;
2987 }
2988 if (stencil) {
2989 args[6] = stencil;
2990 mask |= 0x2;
2991 }
2992 if (samplemask) {
2993 args[7] = samplemask;
2994 mask |= 0x4;
2995 }
2996 }
2997
2998 /* SI (except OLAND and HAINAN) has a bug that it only looks
2999 * at the X writemask component. */
3000 if (ctx->screen->b.chip_class == SI &&
3001 ctx->screen->b.family != CHIP_OLAND &&
3002 ctx->screen->b.family != CHIP_HAINAN)
3003 mask |= 0x1;
3004
3005 /* Specify which components to enable */
3006 args[0] = lp_build_const_int32(base->gallivm, mask);
3007
3008 memcpy(exp->args[exp->num++], args, sizeof(args));
3009 }
3010
3011 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3012 LLVMValueRef *color, unsigned index,
3013 unsigned samplemask_param,
3014 bool is_last, struct si_ps_exports *exp)
3015 {
3016 struct si_shader_context *ctx = si_shader_context(bld_base);
3017 struct lp_build_context *base = &bld_base->base;
3018 int i;
3019
3020 /* Clamp color */
3021 if (ctx->shader->key.part.ps.epilog.clamp_color)
3022 for (i = 0; i < 4; i++)
3023 color[i] = si_llvm_saturate(bld_base, color[i]);
3024
3025 /* Alpha to one */
3026 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3027 color[3] = base->one;
3028
3029 /* Alpha test */
3030 if (index == 0 &&
3031 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3032 si_alpha_test(bld_base, color[3]);
3033
3034 /* Line & polygon smoothing */
3035 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3036 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3037 samplemask_param);
3038
3039 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3040 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3041 LLVMValueRef args[8][9];
3042 int c, last = -1;
3043
3044 /* Get the export arguments, also find out what the last one is. */
3045 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3046 si_llvm_init_export_args(bld_base, color,
3047 V_008DFC_SQ_EXP_MRT + c, args[c]);
3048 if (args[c][0] != bld_base->uint_bld.zero)
3049 last = c;
3050 }
3051
3052 /* Emit all exports. */
3053 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3054 if (is_last && last == c) {
3055 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3056 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
3057 } else if (args[c][0] == bld_base->uint_bld.zero)
3058 continue; /* unnecessary NULL export */
3059
3060 memcpy(exp->args[exp->num++], args[c], sizeof(args[c]));
3061 }
3062 } else {
3063 LLVMValueRef args[9];
3064
3065 /* Export */
3066 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
3067 args);
3068 if (is_last) {
3069 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3070 args[2] = bld_base->uint_bld.one; /* DONE bit */
3071 } else if (args[0] == bld_base->uint_bld.zero)
3072 return; /* unnecessary NULL export */
3073
3074 memcpy(exp->args[exp->num++], args, sizeof(args));
3075 }
3076 }
3077
3078 static void si_emit_ps_exports(struct si_shader_context *ctx,
3079 struct si_ps_exports *exp)
3080 {
3081 for (unsigned i = 0; i < exp->num; i++)
3082 lp_build_intrinsic(ctx->gallivm.builder,
3083 "llvm.SI.export", ctx->voidt,
3084 exp->args[i], 9, 0);
3085 }
3086
3087 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3088 {
3089 struct si_shader_context *ctx = si_shader_context(bld_base);
3090 struct lp_build_context *base = &bld_base->base;
3091 struct lp_build_context *uint = &bld_base->uint_bld;
3092 LLVMValueRef args[9];
3093
3094 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
3095 args[1] = uint->one; /* whether the EXEC mask is valid */
3096 args[2] = uint->one; /* DONE bit */
3097 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
3098 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
3099 args[5] = base->undef; /* R */
3100 args[6] = base->undef; /* G */
3101 args[7] = base->undef; /* B */
3102 args[8] = base->undef; /* A */
3103
3104 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
3105 ctx->voidt, args, 9, 0);
3106 }
3107
3108 /**
3109 * Return PS outputs in this order:
3110 *
3111 * v[0:3] = color0.xyzw
3112 * v[4:7] = color1.xyzw
3113 * ...
3114 * vN+0 = Depth
3115 * vN+1 = Stencil
3116 * vN+2 = SampleMask
3117 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3118 *
3119 * The alpha-ref SGPR is returned via its original location.
3120 */
3121 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
3122 {
3123 struct si_shader_context *ctx = si_shader_context(bld_base);
3124 struct si_shader *shader = ctx->shader;
3125 struct lp_build_context *base = &bld_base->base;
3126 struct tgsi_shader_info *info = &shader->selector->info;
3127 LLVMBuilderRef builder = base->gallivm->builder;
3128 unsigned i, j, first_vgpr, vgpr;
3129
3130 LLVMValueRef color[8][4] = {};
3131 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3132 LLVMValueRef ret;
3133
3134 /* Read the output values. */
3135 for (i = 0; i < info->num_outputs; i++) {
3136 unsigned semantic_name = info->output_semantic_name[i];
3137 unsigned semantic_index = info->output_semantic_index[i];
3138
3139 switch (semantic_name) {
3140 case TGSI_SEMANTIC_COLOR:
3141 assert(semantic_index < 8);
3142 for (j = 0; j < 4; j++) {
3143 LLVMValueRef ptr = ctx->soa.outputs[i][j];
3144 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3145 color[semantic_index][j] = result;
3146 }
3147 break;
3148 case TGSI_SEMANTIC_POSITION:
3149 depth = LLVMBuildLoad(builder,
3150 ctx->soa.outputs[i][2], "");
3151 break;
3152 case TGSI_SEMANTIC_STENCIL:
3153 stencil = LLVMBuildLoad(builder,
3154 ctx->soa.outputs[i][1], "");
3155 break;
3156 case TGSI_SEMANTIC_SAMPLEMASK:
3157 samplemask = LLVMBuildLoad(builder,
3158 ctx->soa.outputs[i][0], "");
3159 break;
3160 default:
3161 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3162 semantic_name);
3163 }
3164 }
3165
3166 /* Fill the return structure. */
3167 ret = ctx->return_value;
3168
3169 /* Set SGPRs. */
3170 ret = LLVMBuildInsertValue(builder, ret,
3171 bitcast(bld_base, TGSI_TYPE_SIGNED,
3172 LLVMGetParam(ctx->main_fn,
3173 SI_PARAM_ALPHA_REF)),
3174 SI_SGPR_ALPHA_REF, "");
3175
3176 /* Set VGPRs */
3177 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3178 for (i = 0; i < ARRAY_SIZE(color); i++) {
3179 if (!color[i][0])
3180 continue;
3181
3182 for (j = 0; j < 4; j++)
3183 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3184 }
3185 if (depth)
3186 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3187 if (stencil)
3188 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3189 if (samplemask)
3190 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3191
3192 /* Add the input sample mask for smoothing at the end. */
3193 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3194 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3195 ret = LLVMBuildInsertValue(builder, ret,
3196 LLVMGetParam(ctx->main_fn,
3197 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3198
3199 ctx->return_value = ret;
3200 }
3201
3202 /**
3203 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3204 * buffer in number of elements and return it as an i32.
3205 */
3206 static LLVMValueRef get_buffer_size(
3207 struct lp_build_tgsi_context *bld_base,
3208 LLVMValueRef descriptor)
3209 {
3210 struct si_shader_context *ctx = si_shader_context(bld_base);
3211 struct gallivm_state *gallivm = bld_base->base.gallivm;
3212 LLVMBuilderRef builder = gallivm->builder;
3213 LLVMValueRef size =
3214 LLVMBuildExtractElement(builder, descriptor,
3215 lp_build_const_int32(gallivm, 2), "");
3216
3217 if (ctx->screen->b.chip_class >= VI) {
3218 /* On VI, the descriptor contains the size in bytes,
3219 * but TXQ must return the size in elements.
3220 * The stride is always non-zero for resources using TXQ.
3221 */
3222 LLVMValueRef stride =
3223 LLVMBuildExtractElement(builder, descriptor,
3224 lp_build_const_int32(gallivm, 1), "");
3225 stride = LLVMBuildLShr(builder, stride,
3226 lp_build_const_int32(gallivm, 16), "");
3227 stride = LLVMBuildAnd(builder, stride,
3228 lp_build_const_int32(gallivm, 0x3FFF), "");
3229
3230 size = LLVMBuildUDiv(builder, size, stride, "");
3231 }
3232
3233 return size;
3234 }
3235
3236 /**
3237 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
3238 * intrinsic names).
3239 */
3240 static void build_type_name_for_intr(
3241 LLVMTypeRef type,
3242 char *buf, unsigned bufsize)
3243 {
3244 LLVMTypeRef elem_type = type;
3245
3246 assert(bufsize >= 8);
3247
3248 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
3249 int ret = snprintf(buf, bufsize, "v%u",
3250 LLVMGetVectorSize(type));
3251 if (ret < 0) {
3252 char *type_name = LLVMPrintTypeToString(type);
3253 fprintf(stderr, "Error building type name for: %s\n",
3254 type_name);
3255 return;
3256 }
3257 elem_type = LLVMGetElementType(type);
3258 buf += ret;
3259 bufsize -= ret;
3260 }
3261 switch (LLVMGetTypeKind(elem_type)) {
3262 default: break;
3263 case LLVMIntegerTypeKind:
3264 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
3265 break;
3266 case LLVMFloatTypeKind:
3267 snprintf(buf, bufsize, "f32");
3268 break;
3269 case LLVMDoubleTypeKind:
3270 snprintf(buf, bufsize, "f64");
3271 break;
3272 }
3273 }
3274
3275 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3276 struct lp_build_tgsi_context *bld_base,
3277 struct lp_build_emit_data *emit_data);
3278
3279 /* Prevent optimizations (at least of memory accesses) across the current
3280 * point in the program by emitting empty inline assembly that is marked as
3281 * having side effects.
3282 */
3283 #if 0 /* unused currently */
3284 static void emit_optimization_barrier(struct si_shader_context *ctx)
3285 {
3286 LLVMBuilderRef builder = ctx->gallivm.builder;
3287 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3288 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
3289 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3290 }
3291 #endif
3292
3293 /* Combine these with & instead of |. */
3294 #define LGKM_CNT 0x07f
3295 #define VM_CNT 0xf70
3296
3297 static void emit_waitcnt(struct si_shader_context *ctx, unsigned simm16)
3298 {
3299 struct gallivm_state *gallivm = &ctx->gallivm;
3300 LLVMBuilderRef builder = gallivm->builder;
3301 LLVMValueRef args[1] = {
3302 lp_build_const_int32(gallivm, simm16)
3303 };
3304 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3305 ctx->voidt, args, 1, 0);
3306 }
3307
3308 static void membar_emit(
3309 const struct lp_build_tgsi_action *action,
3310 struct lp_build_tgsi_context *bld_base,
3311 struct lp_build_emit_data *emit_data)
3312 {
3313 struct si_shader_context *ctx = si_shader_context(bld_base);
3314
3315 emit_waitcnt(ctx, VM_CNT);
3316 }
3317
3318 static LLVMValueRef
3319 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3320 const struct tgsi_full_src_register *reg)
3321 {
3322 LLVMValueRef index;
3323 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3324 SI_PARAM_SHADER_BUFFERS);
3325
3326 if (!reg->Register.Indirect)
3327 index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
3328 else
3329 index = get_bounded_indirect_index(ctx, &reg->Indirect,
3330 reg->Register.Index,
3331 SI_NUM_SHADER_BUFFERS);
3332
3333 return build_indexed_load_const(ctx, rsrc_ptr, index);
3334 }
3335
3336 static bool tgsi_is_array_sampler(unsigned target)
3337 {
3338 return target == TGSI_TEXTURE_1D_ARRAY ||
3339 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3340 target == TGSI_TEXTURE_2D_ARRAY ||
3341 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3342 target == TGSI_TEXTURE_CUBE_ARRAY ||
3343 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3344 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3345 }
3346
3347 static bool tgsi_is_array_image(unsigned target)
3348 {
3349 return target == TGSI_TEXTURE_3D ||
3350 target == TGSI_TEXTURE_CUBE ||
3351 target == TGSI_TEXTURE_1D_ARRAY ||
3352 target == TGSI_TEXTURE_2D_ARRAY ||
3353 target == TGSI_TEXTURE_CUBE_ARRAY ||
3354 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3355 }
3356
3357 /**
3358 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3359 *
3360 * At least on Tonga, executing image stores on images with DCC enabled and
3361 * non-trivial can eventually lead to lockups. This can occur when an
3362 * application binds an image as read-only but then uses a shader that writes
3363 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3364 * program termination) in this case, but it doesn't cost much to be a bit
3365 * nicer: disabling DCC in the shader still leads to undefined results but
3366 * avoids the lockup.
3367 */
3368 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3369 LLVMValueRef rsrc)
3370 {
3371 if (ctx->screen->b.chip_class <= CIK) {
3372 return rsrc;
3373 } else {
3374 LLVMBuilderRef builder = ctx->gallivm.builder;
3375 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3376 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3377 LLVMValueRef tmp;
3378
3379 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3380 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3381 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3382 }
3383 }
3384
3385 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3386 {
3387 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3388 CONST_ADDR_SPACE);
3389 }
3390
3391 /**
3392 * Load the resource descriptor for \p image.
3393 */
3394 static void
3395 image_fetch_rsrc(
3396 struct lp_build_tgsi_context *bld_base,
3397 const struct tgsi_full_src_register *image,
3398 bool is_store, unsigned target,
3399 LLVMValueRef *rsrc)
3400 {
3401 struct si_shader_context *ctx = si_shader_context(bld_base);
3402 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3403 SI_PARAM_IMAGES);
3404 LLVMValueRef index, tmp;
3405 bool dcc_off = target != TGSI_TEXTURE_BUFFER && is_store;
3406
3407 assert(image->Register.File == TGSI_FILE_IMAGE);
3408
3409 if (!image->Register.Indirect) {
3410 const struct tgsi_shader_info *info = bld_base->info;
3411
3412 index = LLVMConstInt(ctx->i32, image->Register.Index, 0);
3413
3414 if (info->images_writemask & (1 << image->Register.Index) &&
3415 target != TGSI_TEXTURE_BUFFER)
3416 dcc_off = true;
3417 } else {
3418 /* From the GL_ARB_shader_image_load_store extension spec:
3419 *
3420 * If a shader performs an image load, store, or atomic
3421 * operation using an image variable declared as an array,
3422 * and if the index used to select an individual element is
3423 * negative or greater than or equal to the size of the
3424 * array, the results of the operation are undefined but may
3425 * not lead to termination.
3426 */
3427 index = get_bounded_indirect_index(ctx, &image->Indirect,
3428 image->Register.Index,
3429 SI_NUM_IMAGES);
3430 }
3431
3432 if (target == TGSI_TEXTURE_BUFFER) {
3433 LLVMBuilderRef builder = ctx->gallivm.builder;
3434
3435 rsrc_ptr = LLVMBuildPointerCast(builder, rsrc_ptr,
3436 const_array(ctx->v4i32, 0), "");
3437 index = LLVMBuildMul(builder, index,
3438 LLVMConstInt(ctx->i32, 2, 0), "");
3439 index = LLVMBuildAdd(builder, index,
3440 LLVMConstInt(ctx->i32, 1, 0), "");
3441 *rsrc = build_indexed_load_const(ctx, rsrc_ptr, index);
3442 return;
3443 }
3444
3445 tmp = build_indexed_load_const(ctx, rsrc_ptr, index);
3446 if (dcc_off)
3447 tmp = force_dcc_off(ctx, tmp);
3448 *rsrc = tmp;
3449 }
3450
3451 static LLVMValueRef image_fetch_coords(
3452 struct lp_build_tgsi_context *bld_base,
3453 const struct tgsi_full_instruction *inst,
3454 unsigned src)
3455 {
3456 struct gallivm_state *gallivm = bld_base->base.gallivm;
3457 LLVMBuilderRef builder = gallivm->builder;
3458 unsigned target = inst->Memory.Texture;
3459 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3460 LLVMValueRef coords[4];
3461 LLVMValueRef tmp;
3462 int chan;
3463
3464 for (chan = 0; chan < num_coords; ++chan) {
3465 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3466 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3467 coords[chan] = tmp;
3468 }
3469
3470 if (num_coords == 1)
3471 return coords[0];
3472
3473 if (num_coords == 3) {
3474 /* LLVM has difficulties lowering 3-element vectors. */
3475 coords[3] = bld_base->uint_bld.undef;
3476 num_coords = 4;
3477 }
3478
3479 return lp_build_gather_values(gallivm, coords, num_coords);
3480 }
3481
3482 /**
3483 * Append the extra mode bits that are used by image load and store.
3484 */
3485 static void image_append_args(
3486 struct si_shader_context *ctx,
3487 struct lp_build_emit_data * emit_data,
3488 unsigned target,
3489 bool atomic,
3490 bool force_glc)
3491 {
3492 const struct tgsi_full_instruction *inst = emit_data->inst;
3493 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3494 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3495 LLVMValueRef r128 = i1false;
3496 LLVMValueRef da = tgsi_is_array_image(target) ? i1true : i1false;
3497 LLVMValueRef glc =
3498 force_glc ||
3499 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3500 i1true : i1false;
3501 LLVMValueRef slc = i1false;
3502 LLVMValueRef lwe = i1false;
3503
3504 if (atomic || (HAVE_LLVM <= 0x0309)) {
3505 emit_data->args[emit_data->arg_count++] = r128;
3506 emit_data->args[emit_data->arg_count++] = da;
3507 if (!atomic) {
3508 emit_data->args[emit_data->arg_count++] = glc;
3509 }
3510 emit_data->args[emit_data->arg_count++] = slc;
3511 return;
3512 }
3513
3514 /* HAVE_LLVM >= 0x0400 */
3515 emit_data->args[emit_data->arg_count++] = glc;
3516 emit_data->args[emit_data->arg_count++] = slc;
3517 emit_data->args[emit_data->arg_count++] = lwe;
3518 emit_data->args[emit_data->arg_count++] = da;
3519 }
3520
3521 /**
3522 * Append the resource and indexing arguments for buffer intrinsics.
3523 *
3524 * \param rsrc the v4i32 buffer resource
3525 * \param index index into the buffer (stride-based)
3526 * \param offset byte offset into the buffer
3527 */
3528 static void buffer_append_args(
3529 struct si_shader_context *ctx,
3530 struct lp_build_emit_data *emit_data,
3531 LLVMValueRef rsrc,
3532 LLVMValueRef index,
3533 LLVMValueRef offset,
3534 bool atomic,
3535 bool force_glc)
3536 {
3537 const struct tgsi_full_instruction *inst = emit_data->inst;
3538 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3539 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3540
3541 emit_data->args[emit_data->arg_count++] = rsrc;
3542 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3543 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3544 if (!atomic) {
3545 emit_data->args[emit_data->arg_count++] =
3546 force_glc ||
3547 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3548 i1true : i1false; /* glc */
3549 }
3550 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3551 }
3552
3553 static void load_fetch_args(
3554 struct lp_build_tgsi_context * bld_base,
3555 struct lp_build_emit_data * emit_data)
3556 {
3557 struct si_shader_context *ctx = si_shader_context(bld_base);
3558 struct gallivm_state *gallivm = bld_base->base.gallivm;
3559 const struct tgsi_full_instruction * inst = emit_data->inst;
3560 unsigned target = inst->Memory.Texture;
3561 LLVMValueRef rsrc;
3562
3563 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3564
3565 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3566 LLVMBuilderRef builder = gallivm->builder;
3567 LLVMValueRef offset;
3568 LLVMValueRef tmp;
3569
3570 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3571
3572 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3573 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3574
3575 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3576 offset, false, false);
3577 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3578 LLVMValueRef coords;
3579
3580 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
3581 coords = image_fetch_coords(bld_base, inst, 1);
3582
3583 if (target == TGSI_TEXTURE_BUFFER) {
3584 buffer_append_args(ctx, emit_data, rsrc, coords,
3585 bld_base->uint_bld.zero, false, false);
3586 } else {
3587 emit_data->args[0] = coords;
3588 emit_data->args[1] = rsrc;
3589 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3590 emit_data->arg_count = 3;
3591
3592 image_append_args(ctx, emit_data, target, false, false);
3593 }
3594 }
3595 }
3596
3597 static void load_emit_buffer(struct si_shader_context *ctx,
3598 struct lp_build_emit_data *emit_data)
3599 {
3600 const struct tgsi_full_instruction *inst = emit_data->inst;
3601 struct gallivm_state *gallivm = &ctx->gallivm;
3602 LLVMBuilderRef builder = gallivm->builder;
3603 uint writemask = inst->Dst[0].Register.WriteMask;
3604 uint count = util_last_bit(writemask);
3605 const char *intrinsic_name;
3606 LLVMTypeRef dst_type;
3607
3608 switch (count) {
3609 case 1:
3610 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3611 dst_type = ctx->f32;
3612 break;
3613 case 2:
3614 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3615 dst_type = LLVMVectorType(ctx->f32, 2);
3616 break;
3617 default: // 3 & 4
3618 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3619 dst_type = ctx->v4f32;
3620 count = 4;
3621 }
3622
3623 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3624 builder, intrinsic_name, dst_type,
3625 emit_data->args, emit_data->arg_count,
3626 LP_FUNC_ATTR_READONLY);
3627 }
3628
3629 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3630 const struct tgsi_full_instruction *inst,
3631 LLVMTypeRef type, int arg)
3632 {
3633 struct gallivm_state *gallivm = &ctx->gallivm;
3634 LLVMBuilderRef builder = gallivm->builder;
3635 LLVMValueRef offset, ptr;
3636 int addr_space;
3637
3638 offset = lp_build_emit_fetch(&ctx->soa.bld_base, inst, arg, 0);
3639 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3640
3641 ptr = ctx->shared_memory;
3642 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3643 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3644 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3645
3646 return ptr;
3647 }
3648
3649 static void load_emit_memory(
3650 struct si_shader_context *ctx,
3651 struct lp_build_emit_data *emit_data)
3652 {
3653 const struct tgsi_full_instruction *inst = emit_data->inst;
3654 struct lp_build_context *base = &ctx->soa.bld_base.base;
3655 struct gallivm_state *gallivm = &ctx->gallivm;
3656 LLVMBuilderRef builder = gallivm->builder;
3657 unsigned writemask = inst->Dst[0].Register.WriteMask;
3658 LLVMValueRef channels[4], ptr, derived_ptr, index;
3659 int chan;
3660
3661 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3662
3663 for (chan = 0; chan < 4; ++chan) {
3664 if (!(writemask & (1 << chan))) {
3665 channels[chan] = LLVMGetUndef(base->elem_type);
3666 continue;
3667 }
3668
3669 index = lp_build_const_int32(gallivm, chan);
3670 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3671 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3672 }
3673 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3674 }
3675
3676 static void get_image_intr_name(const char *base_name,
3677 LLVMTypeRef data_type,
3678 LLVMTypeRef coords_type,
3679 LLVMTypeRef rsrc_type,
3680 char *out_name, unsigned out_len)
3681 {
3682 char coords_type_name[8];
3683
3684 build_type_name_for_intr(coords_type, coords_type_name,
3685 sizeof(coords_type_name));
3686
3687 if (HAVE_LLVM <= 0x0309) {
3688 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
3689 } else {
3690 char data_type_name[8];
3691 char rsrc_type_name[8];
3692
3693 build_type_name_for_intr(data_type, data_type_name,
3694 sizeof(data_type_name));
3695 build_type_name_for_intr(rsrc_type, rsrc_type_name,
3696 sizeof(rsrc_type_name));
3697 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
3698 data_type_name, coords_type_name, rsrc_type_name);
3699 }
3700 }
3701
3702 static void load_emit(
3703 const struct lp_build_tgsi_action *action,
3704 struct lp_build_tgsi_context *bld_base,
3705 struct lp_build_emit_data *emit_data)
3706 {
3707 struct si_shader_context *ctx = si_shader_context(bld_base);
3708 struct gallivm_state *gallivm = bld_base->base.gallivm;
3709 LLVMBuilderRef builder = gallivm->builder;
3710 const struct tgsi_full_instruction * inst = emit_data->inst;
3711 char intrinsic_name[64];
3712
3713 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3714 load_emit_memory(ctx, emit_data);
3715 return;
3716 }
3717
3718 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3719 emit_waitcnt(ctx, VM_CNT);
3720
3721 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3722 load_emit_buffer(ctx, emit_data);
3723 return;
3724 }
3725
3726 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3727 emit_data->output[emit_data->chan] =
3728 lp_build_intrinsic(
3729 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3730 emit_data->args, emit_data->arg_count,
3731 LP_FUNC_ATTR_READONLY);
3732 } else {
3733 get_image_intr_name("llvm.amdgcn.image.load",
3734 emit_data->dst_type, /* vdata */
3735 LLVMTypeOf(emit_data->args[0]), /* coords */
3736 LLVMTypeOf(emit_data->args[1]), /* rsrc */
3737 intrinsic_name, sizeof(intrinsic_name));
3738
3739 emit_data->output[emit_data->chan] =
3740 lp_build_intrinsic(
3741 builder, intrinsic_name, emit_data->dst_type,
3742 emit_data->args, emit_data->arg_count,
3743 LP_FUNC_ATTR_READONLY);
3744 }
3745 }
3746
3747 static void store_fetch_args(
3748 struct lp_build_tgsi_context * bld_base,
3749 struct lp_build_emit_data * emit_data)
3750 {
3751 struct si_shader_context *ctx = si_shader_context(bld_base);
3752 struct gallivm_state *gallivm = bld_base->base.gallivm;
3753 LLVMBuilderRef builder = gallivm->builder;
3754 const struct tgsi_full_instruction * inst = emit_data->inst;
3755 struct tgsi_full_src_register memory;
3756 LLVMValueRef chans[4];
3757 LLVMValueRef data;
3758 LLVMValueRef rsrc;
3759 unsigned chan;
3760
3761 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3762
3763 for (chan = 0; chan < 4; ++chan) {
3764 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3765 }
3766 data = lp_build_gather_values(gallivm, chans, 4);
3767
3768 emit_data->args[emit_data->arg_count++] = data;
3769
3770 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3771
3772 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3773 LLVMValueRef offset;
3774 LLVMValueRef tmp;
3775
3776 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3777
3778 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3779 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3780
3781 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3782 offset, false, false);
3783 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3784 unsigned target = inst->Memory.Texture;
3785 LLVMValueRef coords;
3786
3787 /* 8bit/16bit TC L1 write corruption bug on SI.
3788 * All store opcodes not aligned to a dword are affected.
3789 *
3790 * The only way to get unaligned stores in radeonsi is through
3791 * shader images.
3792 */
3793 bool force_glc = ctx->screen->b.chip_class == SI;
3794
3795 coords = image_fetch_coords(bld_base, inst, 0);
3796
3797 if (target == TGSI_TEXTURE_BUFFER) {
3798 image_fetch_rsrc(bld_base, &memory, true, target, &rsrc);
3799 buffer_append_args(ctx, emit_data, rsrc, coords,
3800 bld_base->uint_bld.zero, false, force_glc);
3801 } else {
3802 emit_data->args[1] = coords;
3803 image_fetch_rsrc(bld_base, &memory, true, target,
3804 &emit_data->args[2]);
3805 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3806 emit_data->arg_count = 4;
3807
3808 image_append_args(ctx, emit_data, target, false, force_glc);
3809 }
3810 }
3811 }
3812
3813 static void store_emit_buffer(
3814 struct si_shader_context *ctx,
3815 struct lp_build_emit_data *emit_data)
3816 {
3817 const struct tgsi_full_instruction *inst = emit_data->inst;
3818 struct gallivm_state *gallivm = &ctx->gallivm;
3819 LLVMBuilderRef builder = gallivm->builder;
3820 struct lp_build_context *uint_bld = &ctx->soa.bld_base.uint_bld;
3821 LLVMValueRef base_data = emit_data->args[0];
3822 LLVMValueRef base_offset = emit_data->args[3];
3823 unsigned writemask = inst->Dst[0].Register.WriteMask;
3824
3825 while (writemask) {
3826 int start, count;
3827 const char *intrinsic_name;
3828 LLVMValueRef data;
3829 LLVMValueRef offset;
3830 LLVMValueRef tmp;
3831
3832 u_bit_scan_consecutive_range(&writemask, &start, &count);
3833
3834 /* Due to an LLVM limitation, split 3-element writes
3835 * into a 2-element and a 1-element write. */
3836 if (count == 3) {
3837 writemask |= 1 << (start + 2);
3838 count = 2;
3839 }
3840
3841 if (count == 4) {
3842 data = base_data;
3843 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3844 } else if (count == 2) {
3845 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3846
3847 tmp = LLVMBuildExtractElement(
3848 builder, base_data,
3849 lp_build_const_int32(gallivm, start), "");
3850 data = LLVMBuildInsertElement(
3851 builder, LLVMGetUndef(v2f32), tmp,
3852 uint_bld->zero, "");
3853
3854 tmp = LLVMBuildExtractElement(
3855 builder, base_data,
3856 lp_build_const_int32(gallivm, start + 1), "");
3857 data = LLVMBuildInsertElement(
3858 builder, data, tmp, uint_bld->one, "");
3859
3860 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3861 } else {
3862 assert(count == 1);
3863 data = LLVMBuildExtractElement(
3864 builder, base_data,
3865 lp_build_const_int32(gallivm, start), "");
3866 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3867 }
3868
3869 offset = base_offset;
3870 if (start != 0) {
3871 offset = LLVMBuildAdd(
3872 builder, offset,
3873 lp_build_const_int32(gallivm, start * 4), "");
3874 }
3875
3876 emit_data->args[0] = data;
3877 emit_data->args[3] = offset;
3878
3879 lp_build_intrinsic(
3880 builder, intrinsic_name, emit_data->dst_type,
3881 emit_data->args, emit_data->arg_count, 0);
3882 }
3883 }
3884
3885 static void store_emit_memory(
3886 struct si_shader_context *ctx,
3887 struct lp_build_emit_data *emit_data)
3888 {
3889 const struct tgsi_full_instruction *inst = emit_data->inst;
3890 struct gallivm_state *gallivm = &ctx->gallivm;
3891 struct lp_build_context *base = &ctx->soa.bld_base.base;
3892 LLVMBuilderRef builder = gallivm->builder;
3893 unsigned writemask = inst->Dst[0].Register.WriteMask;
3894 LLVMValueRef ptr, derived_ptr, data, index;
3895 int chan;
3896
3897 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3898
3899 for (chan = 0; chan < 4; ++chan) {
3900 if (!(writemask & (1 << chan))) {
3901 continue;
3902 }
3903 data = lp_build_emit_fetch(&ctx->soa.bld_base, inst, 1, chan);
3904 index = lp_build_const_int32(gallivm, chan);
3905 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3906 LLVMBuildStore(builder, data, derived_ptr);
3907 }
3908 }
3909
3910 static void store_emit(
3911 const struct lp_build_tgsi_action *action,
3912 struct lp_build_tgsi_context *bld_base,
3913 struct lp_build_emit_data *emit_data)
3914 {
3915 struct si_shader_context *ctx = si_shader_context(bld_base);
3916 struct gallivm_state *gallivm = bld_base->base.gallivm;
3917 LLVMBuilderRef builder = gallivm->builder;
3918 const struct tgsi_full_instruction * inst = emit_data->inst;
3919 unsigned target = inst->Memory.Texture;
3920 char intrinsic_name[64];
3921
3922 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3923 store_emit_memory(ctx, emit_data);
3924 return;
3925 }
3926
3927 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3928 emit_waitcnt(ctx, VM_CNT);
3929
3930 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3931 store_emit_buffer(ctx, emit_data);
3932 return;
3933 }
3934
3935 if (target == TGSI_TEXTURE_BUFFER) {
3936 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3937 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3938 emit_data->dst_type, emit_data->args,
3939 emit_data->arg_count, 0);
3940 } else {
3941 get_image_intr_name("llvm.amdgcn.image.store",
3942 LLVMTypeOf(emit_data->args[0]), /* vdata */
3943 LLVMTypeOf(emit_data->args[1]), /* coords */
3944 LLVMTypeOf(emit_data->args[2]), /* rsrc */
3945 intrinsic_name, sizeof(intrinsic_name));
3946
3947 emit_data->output[emit_data->chan] =
3948 lp_build_intrinsic(
3949 builder, intrinsic_name, emit_data->dst_type,
3950 emit_data->args, emit_data->arg_count, 0);
3951 }
3952 }
3953
3954 static void atomic_fetch_args(
3955 struct lp_build_tgsi_context * bld_base,
3956 struct lp_build_emit_data * emit_data)
3957 {
3958 struct si_shader_context *ctx = si_shader_context(bld_base);
3959 struct gallivm_state *gallivm = bld_base->base.gallivm;
3960 LLVMBuilderRef builder = gallivm->builder;
3961 const struct tgsi_full_instruction * inst = emit_data->inst;
3962 LLVMValueRef data1, data2;
3963 LLVMValueRef rsrc;
3964 LLVMValueRef tmp;
3965
3966 emit_data->dst_type = bld_base->base.elem_type;
3967
3968 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
3969 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3970
3971 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3972 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
3973 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3974 }
3975
3976 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3977 * of arguments, which is reversed relative to TGSI (and GLSL)
3978 */
3979 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3980 emit_data->args[emit_data->arg_count++] = data2;
3981 emit_data->args[emit_data->arg_count++] = data1;
3982
3983 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3984 LLVMValueRef offset;
3985
3986 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3987
3988 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3989 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3990
3991 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3992 offset, true, false);
3993 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3994 unsigned target = inst->Memory.Texture;
3995 LLVMValueRef coords;
3996
3997 image_fetch_rsrc(bld_base, &inst->Src[0], true, target, &rsrc);
3998 coords = image_fetch_coords(bld_base, inst, 1);
3999
4000 if (target == TGSI_TEXTURE_BUFFER) {
4001 buffer_append_args(ctx, emit_data, rsrc, coords,
4002 bld_base->uint_bld.zero, true, false);
4003 } else {
4004 emit_data->args[emit_data->arg_count++] = coords;
4005 emit_data->args[emit_data->arg_count++] = rsrc;
4006
4007 image_append_args(ctx, emit_data, target, true, false);
4008 }
4009 }
4010 }
4011
4012 static void atomic_emit_memory(struct si_shader_context *ctx,
4013 struct lp_build_emit_data *emit_data) {
4014 struct gallivm_state *gallivm = &ctx->gallivm;
4015 LLVMBuilderRef builder = gallivm->builder;
4016 const struct tgsi_full_instruction * inst = emit_data->inst;
4017 LLVMValueRef ptr, result, arg;
4018
4019 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
4020
4021 arg = lp_build_emit_fetch(&ctx->soa.bld_base, inst, 2, 0);
4022 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
4023
4024 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4025 LLVMValueRef new_data;
4026 new_data = lp_build_emit_fetch(&ctx->soa.bld_base,
4027 inst, 3, 0);
4028
4029 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
4030
4031 #if HAVE_LLVM >= 0x309
4032 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
4033 LLVMAtomicOrderingSequentiallyConsistent,
4034 LLVMAtomicOrderingSequentiallyConsistent,
4035 false);
4036 #endif
4037
4038 result = LLVMBuildExtractValue(builder, result, 0, "");
4039 } else {
4040 LLVMAtomicRMWBinOp op;
4041
4042 switch(inst->Instruction.Opcode) {
4043 case TGSI_OPCODE_ATOMUADD:
4044 op = LLVMAtomicRMWBinOpAdd;
4045 break;
4046 case TGSI_OPCODE_ATOMXCHG:
4047 op = LLVMAtomicRMWBinOpXchg;
4048 break;
4049 case TGSI_OPCODE_ATOMAND:
4050 op = LLVMAtomicRMWBinOpAnd;
4051 break;
4052 case TGSI_OPCODE_ATOMOR:
4053 op = LLVMAtomicRMWBinOpOr;
4054 break;
4055 case TGSI_OPCODE_ATOMXOR:
4056 op = LLVMAtomicRMWBinOpXor;
4057 break;
4058 case TGSI_OPCODE_ATOMUMIN:
4059 op = LLVMAtomicRMWBinOpUMin;
4060 break;
4061 case TGSI_OPCODE_ATOMUMAX:
4062 op = LLVMAtomicRMWBinOpUMax;
4063 break;
4064 case TGSI_OPCODE_ATOMIMIN:
4065 op = LLVMAtomicRMWBinOpMin;
4066 break;
4067 case TGSI_OPCODE_ATOMIMAX:
4068 op = LLVMAtomicRMWBinOpMax;
4069 break;
4070 default:
4071 unreachable("unknown atomic opcode");
4072 }
4073
4074 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
4075 LLVMAtomicOrderingSequentiallyConsistent,
4076 false);
4077 }
4078 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
4079 }
4080
4081 static void atomic_emit(
4082 const struct lp_build_tgsi_action *action,
4083 struct lp_build_tgsi_context *bld_base,
4084 struct lp_build_emit_data *emit_data)
4085 {
4086 struct si_shader_context *ctx = si_shader_context(bld_base);
4087 struct gallivm_state *gallivm = bld_base->base.gallivm;
4088 LLVMBuilderRef builder = gallivm->builder;
4089 const struct tgsi_full_instruction * inst = emit_data->inst;
4090 char intrinsic_name[40];
4091 LLVMValueRef tmp;
4092
4093 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
4094 atomic_emit_memory(ctx, emit_data);
4095 return;
4096 }
4097
4098 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
4099 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4100 snprintf(intrinsic_name, sizeof(intrinsic_name),
4101 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
4102 } else {
4103 LLVMValueRef coords;
4104 char coords_type[8];
4105
4106 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4107 coords = emit_data->args[2];
4108 else
4109 coords = emit_data->args[1];
4110
4111 build_type_name_for_intr(LLVMTypeOf(coords), coords_type, sizeof(coords_type));
4112 snprintf(intrinsic_name, sizeof(intrinsic_name),
4113 "llvm.amdgcn.image.atomic.%s.%s",
4114 action->intr_name, coords_type);
4115 }
4116
4117 tmp = lp_build_intrinsic(
4118 builder, intrinsic_name, bld_base->uint_bld.elem_type,
4119 emit_data->args, emit_data->arg_count, 0);
4120 emit_data->output[emit_data->chan] =
4121 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
4122 }
4123
4124 static void resq_fetch_args(
4125 struct lp_build_tgsi_context * bld_base,
4126 struct lp_build_emit_data * emit_data)
4127 {
4128 struct si_shader_context *ctx = si_shader_context(bld_base);
4129 struct gallivm_state *gallivm = bld_base->base.gallivm;
4130 const struct tgsi_full_instruction *inst = emit_data->inst;
4131 const struct tgsi_full_src_register *reg = &inst->Src[0];
4132
4133 emit_data->dst_type = ctx->v4i32;
4134
4135 if (reg->Register.File == TGSI_FILE_BUFFER) {
4136 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4137 emit_data->arg_count = 1;
4138 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4139 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4140 &emit_data->args[0]);
4141 emit_data->arg_count = 1;
4142 } else {
4143 emit_data->args[0] = bld_base->uint_bld.zero; /* mip level */
4144 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4145 &emit_data->args[1]);
4146 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
4147 emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
4148 emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
4149 emit_data->args[5] = tgsi_is_array_image(inst->Memory.Texture) ?
4150 bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da */
4151 emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
4152 emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
4153 emit_data->args[8] = bld_base->uint_bld.zero; /* tfe */
4154 emit_data->args[9] = bld_base->uint_bld.zero; /* lwe */
4155 emit_data->arg_count = 10;
4156 }
4157 }
4158
4159 static void resq_emit(
4160 const struct lp_build_tgsi_action *action,
4161 struct lp_build_tgsi_context *bld_base,
4162 struct lp_build_emit_data *emit_data)
4163 {
4164 struct gallivm_state *gallivm = bld_base->base.gallivm;
4165 LLVMBuilderRef builder = gallivm->builder;
4166 const struct tgsi_full_instruction *inst = emit_data->inst;
4167 LLVMValueRef out;
4168
4169 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4170 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4171 lp_build_const_int32(gallivm, 2), "");
4172 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4173 out = get_buffer_size(bld_base, emit_data->args[0]);
4174 } else {
4175 out = lp_build_intrinsic(
4176 builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
4177 emit_data->args, emit_data->arg_count,
4178 LP_FUNC_ATTR_READNONE);
4179
4180 /* Divide the number of layers by 6 to get the number of cubes. */
4181 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
4182 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
4183 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
4184
4185 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4186 z = LLVMBuildSDiv(builder, z, imm6, "");
4187 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4188 }
4189 }
4190
4191 emit_data->output[emit_data->chan] = out;
4192 }
4193
4194 static void set_tex_fetch_args(struct si_shader_context *ctx,
4195 struct lp_build_emit_data *emit_data,
4196 unsigned opcode, unsigned target,
4197 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4198 LLVMValueRef *param, unsigned count,
4199 unsigned dmask)
4200 {
4201 struct gallivm_state *gallivm = &ctx->gallivm;
4202 unsigned num_args;
4203 unsigned is_rect = target == TGSI_TEXTURE_RECT;
4204
4205 /* Pad to power of two vector */
4206 while (count < util_next_power_of_two(count))
4207 param[count++] = LLVMGetUndef(ctx->i32);
4208
4209 /* Texture coordinates. */
4210 if (count > 1)
4211 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
4212 else
4213 emit_data->args[0] = param[0];
4214
4215 /* Resource. */
4216 emit_data->args[1] = res_ptr;
4217 num_args = 2;
4218
4219 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
4220 emit_data->dst_type = ctx->v4i32;
4221 else {
4222 emit_data->dst_type = ctx->v4f32;
4223
4224 emit_data->args[num_args++] = samp_ptr;
4225 }
4226
4227 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
4228 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
4229 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
4230 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
4231 tgsi_is_array_sampler(target)); /* da */
4232 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
4233 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
4234 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
4235 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
4236
4237 emit_data->arg_count = num_args;
4238 }
4239
4240 static const struct lp_build_tgsi_action tex_action;
4241
4242 enum desc_type {
4243 DESC_IMAGE,
4244 DESC_BUFFER,
4245 DESC_FMASK,
4246 DESC_SAMPLER,
4247 };
4248
4249 /**
4250 * Load an image view, fmask view. or sampler state descriptor.
4251 */
4252 static LLVMValueRef load_sampler_desc_custom(struct si_shader_context *ctx,
4253 LLVMValueRef list, LLVMValueRef index,
4254 enum desc_type type)
4255 {
4256 struct gallivm_state *gallivm = &ctx->gallivm;
4257 LLVMBuilderRef builder = gallivm->builder;
4258
4259 switch (type) {
4260 case DESC_IMAGE:
4261 /* The image is at [0:7]. */
4262 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4263 break;
4264 case DESC_BUFFER:
4265 /* The buffer is in [4:7]. */
4266 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4267 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4268 list = LLVMBuildPointerCast(builder, list,
4269 const_array(ctx->v4i32, 0), "");
4270 break;
4271 case DESC_FMASK:
4272 /* The FMASK is at [8:15]. */
4273 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4274 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4275 break;
4276 case DESC_SAMPLER:
4277 /* The sampler state is at [12:15]. */
4278 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4279 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4280 list = LLVMBuildPointerCast(builder, list,
4281 const_array(ctx->v4i32, 0), "");
4282 break;
4283 }
4284
4285 return build_indexed_load_const(ctx, list, index);
4286 }
4287
4288 static LLVMValueRef load_sampler_desc(struct si_shader_context *ctx,
4289 LLVMValueRef index, enum desc_type type)
4290 {
4291 LLVMValueRef list = LLVMGetParam(ctx->main_fn,
4292 SI_PARAM_SAMPLERS);
4293
4294 return load_sampler_desc_custom(ctx, list, index, type);
4295 }
4296
4297 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4298 *
4299 * SI-CI:
4300 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4301 * filtering manually. The driver sets img7 to a mask clearing
4302 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4303 * s_and_b32 samp0, samp0, img7
4304 *
4305 * VI:
4306 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4307 */
4308 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4309 LLVMValueRef res, LLVMValueRef samp)
4310 {
4311 LLVMBuilderRef builder = ctx->gallivm.builder;
4312 LLVMValueRef img7, samp0;
4313
4314 if (ctx->screen->b.chip_class >= VI)
4315 return samp;
4316
4317 img7 = LLVMBuildExtractElement(builder, res,
4318 LLVMConstInt(ctx->i32, 7, 0), "");
4319 samp0 = LLVMBuildExtractElement(builder, samp,
4320 LLVMConstInt(ctx->i32, 0, 0), "");
4321 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4322 return LLVMBuildInsertElement(builder, samp, samp0,
4323 LLVMConstInt(ctx->i32, 0, 0), "");
4324 }
4325
4326 static void tex_fetch_ptrs(
4327 struct lp_build_tgsi_context *bld_base,
4328 struct lp_build_emit_data *emit_data,
4329 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4330 {
4331 struct si_shader_context *ctx = si_shader_context(bld_base);
4332 const struct tgsi_full_instruction *inst = emit_data->inst;
4333 unsigned target = inst->Texture.Texture;
4334 unsigned sampler_src;
4335 unsigned sampler_index;
4336 LLVMValueRef index;
4337
4338 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4339 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
4340
4341 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
4342 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
4343
4344 index = get_bounded_indirect_index(ctx,
4345 &reg->Indirect,
4346 reg->Register.Index,
4347 SI_NUM_SAMPLERS);
4348 } else {
4349 index = LLVMConstInt(ctx->i32, sampler_index, 0);
4350 }
4351
4352 if (target == TGSI_TEXTURE_BUFFER)
4353 *res_ptr = load_sampler_desc(ctx, index, DESC_BUFFER);
4354 else
4355 *res_ptr = load_sampler_desc(ctx, index, DESC_IMAGE);
4356
4357 if (samp_ptr)
4358 *samp_ptr = NULL;
4359 if (fmask_ptr)
4360 *fmask_ptr = NULL;
4361
4362 if (target == TGSI_TEXTURE_2D_MSAA ||
4363 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4364 if (fmask_ptr)
4365 *fmask_ptr = load_sampler_desc(ctx, index, DESC_FMASK);
4366 } else if (target != TGSI_TEXTURE_BUFFER) {
4367 if (samp_ptr) {
4368 *samp_ptr = load_sampler_desc(ctx, index, DESC_SAMPLER);
4369 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4370 }
4371 }
4372 }
4373
4374 static void txq_fetch_args(
4375 struct lp_build_tgsi_context *bld_base,
4376 struct lp_build_emit_data *emit_data)
4377 {
4378 struct si_shader_context *ctx = si_shader_context(bld_base);
4379 const struct tgsi_full_instruction *inst = emit_data->inst;
4380 unsigned target = inst->Texture.Texture;
4381 LLVMValueRef res_ptr;
4382 LLVMValueRef address;
4383
4384 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4385
4386 if (target == TGSI_TEXTURE_BUFFER) {
4387 /* Read the size from the buffer descriptor directly. */
4388 emit_data->args[0] = get_buffer_size(bld_base, res_ptr);
4389 return;
4390 }
4391
4392 /* Textures - set the mip level. */
4393 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4394
4395 set_tex_fetch_args(ctx, emit_data, TGSI_OPCODE_TXQ, target, res_ptr,
4396 NULL, &address, 1, 0xf);
4397 }
4398
4399 static void txq_emit(const struct lp_build_tgsi_action *action,
4400 struct lp_build_tgsi_context *bld_base,
4401 struct lp_build_emit_data *emit_data)
4402 {
4403 struct lp_build_context *base = &bld_base->base;
4404 unsigned target = emit_data->inst->Texture.Texture;
4405
4406 if (target == TGSI_TEXTURE_BUFFER) {
4407 /* Just return the buffer size. */
4408 emit_data->output[emit_data->chan] = emit_data->args[0];
4409 return;
4410 }
4411
4412 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4413 base->gallivm->builder, "llvm.SI.getresinfo.i32",
4414 emit_data->dst_type, emit_data->args, emit_data->arg_count,
4415 LP_FUNC_ATTR_READNONE);
4416
4417 /* Divide the number of layers by 6 to get the number of cubes. */
4418 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4419 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4420 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4421 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4422 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4423
4424 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4425 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4426 z = LLVMBuildSDiv(builder, z, six, "");
4427
4428 emit_data->output[emit_data->chan] =
4429 LLVMBuildInsertElement(builder, v4, z, two, "");
4430 }
4431 }
4432
4433 static void tex_fetch_args(
4434 struct lp_build_tgsi_context *bld_base,
4435 struct lp_build_emit_data *emit_data)
4436 {
4437 struct si_shader_context *ctx = si_shader_context(bld_base);
4438 struct gallivm_state *gallivm = bld_base->base.gallivm;
4439 const struct tgsi_full_instruction *inst = emit_data->inst;
4440 unsigned opcode = inst->Instruction.Opcode;
4441 unsigned target = inst->Texture.Texture;
4442 LLVMValueRef coords[5], derivs[6];
4443 LLVMValueRef address[16];
4444 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4445 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4446 unsigned count = 0;
4447 unsigned chan;
4448 unsigned num_deriv_channels = 0;
4449 bool has_offset = inst->Texture.NumOffsets > 0;
4450 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4451 unsigned dmask = 0xf;
4452
4453 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4454
4455 if (target == TGSI_TEXTURE_BUFFER) {
4456 emit_data->dst_type = ctx->v4f32;
4457 emit_data->args[0] = LLVMBuildBitCast(gallivm->builder, res_ptr,
4458 ctx->v16i8, "");
4459 emit_data->args[1] = bld_base->uint_bld.zero;
4460 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4461 emit_data->arg_count = 3;
4462 return;
4463 }
4464
4465 /* Fetch and project texture coordinates */
4466 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4467 for (chan = 0; chan < 3; chan++ ) {
4468 coords[chan] = lp_build_emit_fetch(bld_base,
4469 emit_data->inst, 0,
4470 chan);
4471 if (opcode == TGSI_OPCODE_TXP)
4472 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4473 TGSI_OPCODE_DIV,
4474 coords[chan],
4475 coords[3]);
4476 }
4477
4478 if (opcode == TGSI_OPCODE_TXP)
4479 coords[3] = bld_base->base.one;
4480
4481 /* Pack offsets. */
4482 if (has_offset && opcode != TGSI_OPCODE_TXF) {
4483 /* The offsets are six-bit signed integers packed like this:
4484 * X=[5:0], Y=[13:8], and Z=[21:16].
4485 */
4486 LLVMValueRef offset[3], pack;
4487
4488 assert(inst->Texture.NumOffsets == 1);
4489
4490 for (chan = 0; chan < 3; chan++) {
4491 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4492 emit_data->inst, 0, chan);
4493 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4494 lp_build_const_int32(gallivm, 0x3f), "");
4495 if (chan)
4496 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4497 lp_build_const_int32(gallivm, chan*8), "");
4498 }
4499
4500 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4501 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4502 address[count++] = pack;
4503 }
4504
4505 /* Pack LOD bias value */
4506 if (opcode == TGSI_OPCODE_TXB)
4507 address[count++] = coords[3];
4508 if (opcode == TGSI_OPCODE_TXB2)
4509 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4510
4511 /* Pack depth comparison value */
4512 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4513 LLVMValueRef z;
4514
4515 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4516 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4517 } else {
4518 assert(ref_pos >= 0);
4519 z = coords[ref_pos];
4520 }
4521
4522 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4523 * so the depth comparison value isn't clamped for Z16 and
4524 * Z24 anymore. Do it manually here.
4525 *
4526 * It's unnecessary if the original texture format was
4527 * Z32_FLOAT, but we don't know that here.
4528 */
4529 if (ctx->screen->b.chip_class == VI)
4530 z = si_llvm_saturate(bld_base, z);
4531
4532 address[count++] = z;
4533 }
4534
4535 /* Pack user derivatives */
4536 if (opcode == TGSI_OPCODE_TXD) {
4537 int param, num_src_deriv_channels;
4538
4539 switch (target) {
4540 case TGSI_TEXTURE_3D:
4541 num_src_deriv_channels = 3;
4542 num_deriv_channels = 3;
4543 break;
4544 case TGSI_TEXTURE_2D:
4545 case TGSI_TEXTURE_SHADOW2D:
4546 case TGSI_TEXTURE_RECT:
4547 case TGSI_TEXTURE_SHADOWRECT:
4548 case TGSI_TEXTURE_2D_ARRAY:
4549 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4550 num_src_deriv_channels = 2;
4551 num_deriv_channels = 2;
4552 break;
4553 case TGSI_TEXTURE_CUBE:
4554 case TGSI_TEXTURE_SHADOWCUBE:
4555 case TGSI_TEXTURE_CUBE_ARRAY:
4556 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4557 /* Cube derivatives will be converted to 2D. */
4558 num_src_deriv_channels = 3;
4559 num_deriv_channels = 2;
4560 break;
4561 case TGSI_TEXTURE_1D:
4562 case TGSI_TEXTURE_SHADOW1D:
4563 case TGSI_TEXTURE_1D_ARRAY:
4564 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4565 num_src_deriv_channels = 1;
4566 num_deriv_channels = 1;
4567 break;
4568 default:
4569 unreachable("invalid target");
4570 }
4571
4572 for (param = 0; param < 2; param++)
4573 for (chan = 0; chan < num_src_deriv_channels; chan++)
4574 derivs[param * num_src_deriv_channels + chan] =
4575 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4576 }
4577
4578 if (target == TGSI_TEXTURE_CUBE ||
4579 target == TGSI_TEXTURE_CUBE_ARRAY ||
4580 target == TGSI_TEXTURE_SHADOWCUBE ||
4581 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4582 si_prepare_cube_coords(bld_base, emit_data, coords, derivs);
4583
4584 if (opcode == TGSI_OPCODE_TXD)
4585 for (int i = 0; i < num_deriv_channels * 2; i++)
4586 address[count++] = derivs[i];
4587
4588 /* Pack texture coordinates */
4589 address[count++] = coords[0];
4590 if (num_coords > 1)
4591 address[count++] = coords[1];
4592 if (num_coords > 2)
4593 address[count++] = coords[2];
4594
4595 /* Pack LOD or sample index */
4596 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4597 address[count++] = coords[3];
4598 else if (opcode == TGSI_OPCODE_TXL2)
4599 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4600
4601 if (count > 16) {
4602 assert(!"Cannot handle more than 16 texture address parameters");
4603 count = 16;
4604 }
4605
4606 for (chan = 0; chan < count; chan++ ) {
4607 address[chan] = LLVMBuildBitCast(gallivm->builder,
4608 address[chan], ctx->i32, "");
4609 }
4610
4611 /* Adjust the sample index according to FMASK.
4612 *
4613 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4614 * which is the identity mapping. Each nibble says which physical sample
4615 * should be fetched to get that sample.
4616 *
4617 * For example, 0x11111100 means there are only 2 samples stored and
4618 * the second sample covers 3/4 of the pixel. When reading samples 0
4619 * and 1, return physical sample 0 (determined by the first two 0s
4620 * in FMASK), otherwise return physical sample 1.
4621 *
4622 * The sample index should be adjusted as follows:
4623 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4624 */
4625 if (target == TGSI_TEXTURE_2D_MSAA ||
4626 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4627 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4628 struct lp_build_emit_data txf_emit_data = *emit_data;
4629 LLVMValueRef txf_address[4];
4630 unsigned txf_count = count;
4631 struct tgsi_full_instruction inst = {};
4632
4633 memcpy(txf_address, address, sizeof(txf_address));
4634
4635 if (target == TGSI_TEXTURE_2D_MSAA) {
4636 txf_address[2] = bld_base->uint_bld.zero;
4637 }
4638 txf_address[3] = bld_base->uint_bld.zero;
4639
4640 /* Read FMASK using TXF. */
4641 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4642 inst.Texture.Texture = target;
4643 txf_emit_data.inst = &inst;
4644 txf_emit_data.chan = 0;
4645 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
4646 target, fmask_ptr, NULL,
4647 txf_address, txf_count, 0xf);
4648 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4649
4650 /* Initialize some constants. */
4651 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4652 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4653
4654 /* Apply the formula. */
4655 LLVMValueRef fmask =
4656 LLVMBuildExtractElement(gallivm->builder,
4657 txf_emit_data.output[0],
4658 uint_bld->zero, "");
4659
4660 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4661
4662 LLVMValueRef sample_index4 =
4663 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4664
4665 LLVMValueRef shifted_fmask =
4666 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4667
4668 LLVMValueRef final_sample =
4669 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4670
4671 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4672 * resource descriptor is 0 (invalid),
4673 */
4674 LLVMValueRef fmask_desc =
4675 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4676 ctx->v8i32, "");
4677
4678 LLVMValueRef fmask_word1 =
4679 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4680 uint_bld->one, "");
4681
4682 LLVMValueRef word1_is_nonzero =
4683 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4684 fmask_word1, uint_bld->zero, "");
4685
4686 /* Replace the MSAA sample index. */
4687 address[sample_chan] =
4688 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4689 final_sample, address[sample_chan], "");
4690 }
4691
4692 if (opcode == TGSI_OPCODE_TXF) {
4693 /* add tex offsets */
4694 if (inst->Texture.NumOffsets) {
4695 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4696 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
4697 const struct tgsi_texture_offset *off = inst->TexOffsets;
4698
4699 assert(inst->Texture.NumOffsets == 1);
4700
4701 switch (target) {
4702 case TGSI_TEXTURE_3D:
4703 address[2] = lp_build_add(uint_bld, address[2],
4704 bld->immediates[off->Index][off->SwizzleZ]);
4705 /* fall through */
4706 case TGSI_TEXTURE_2D:
4707 case TGSI_TEXTURE_SHADOW2D:
4708 case TGSI_TEXTURE_RECT:
4709 case TGSI_TEXTURE_SHADOWRECT:
4710 case TGSI_TEXTURE_2D_ARRAY:
4711 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4712 address[1] =
4713 lp_build_add(uint_bld, address[1],
4714 bld->immediates[off->Index][off->SwizzleY]);
4715 /* fall through */
4716 case TGSI_TEXTURE_1D:
4717 case TGSI_TEXTURE_SHADOW1D:
4718 case TGSI_TEXTURE_1D_ARRAY:
4719 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4720 address[0] =
4721 lp_build_add(uint_bld, address[0],
4722 bld->immediates[off->Index][off->SwizzleX]);
4723 break;
4724 /* texture offsets do not apply to other texture targets */
4725 }
4726 }
4727 }
4728
4729 if (opcode == TGSI_OPCODE_TG4) {
4730 unsigned gather_comp = 0;
4731
4732 /* DMASK was repurposed for GATHER4. 4 components are always
4733 * returned and DMASK works like a swizzle - it selects
4734 * the component to fetch. The only valid DMASK values are
4735 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4736 * (red,red,red,red) etc.) The ISA document doesn't mention
4737 * this.
4738 */
4739
4740 /* Get the component index from src1.x for Gather4. */
4741 if (!tgsi_is_shadow_target(target)) {
4742 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4743 LLVMValueRef comp_imm;
4744 struct tgsi_src_register src1 = inst->Src[1].Register;
4745
4746 assert(src1.File == TGSI_FILE_IMMEDIATE);
4747
4748 comp_imm = imms[src1.Index][src1.SwizzleX];
4749 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4750 gather_comp = CLAMP(gather_comp, 0, 3);
4751 }
4752
4753 dmask = 1 << gather_comp;
4754 }
4755
4756 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
4757 samp_ptr, address, count, dmask);
4758 }
4759
4760 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
4761 * incorrectly forces nearest filtering if the texture format is integer.
4762 * The only effect it has on Gather4, which always returns 4 texels for
4763 * bilinear filtering, is that the final coordinates are off by 0.5 of
4764 * the texel size.
4765 *
4766 * The workaround is to subtract 0.5 from the unnormalized coordinates,
4767 * or (0.5 / size) from the normalized coordinates.
4768 */
4769 static void si_lower_gather4_integer(struct si_shader_context *ctx,
4770 struct lp_build_emit_data *emit_data,
4771 const char *intr_name,
4772 unsigned coord_vgpr_index)
4773 {
4774 LLVMBuilderRef builder = ctx->gallivm.builder;
4775 LLVMValueRef coord = emit_data->args[0];
4776 LLVMValueRef half_texel[2];
4777 int c;
4778
4779 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_RECT ||
4780 emit_data->inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
4781 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
4782 } else {
4783 struct tgsi_full_instruction txq_inst = {};
4784 struct lp_build_emit_data txq_emit_data = {};
4785
4786 /* Query the texture size. */
4787 txq_inst.Texture.Texture = emit_data->inst->Texture.Texture;
4788 txq_emit_data.inst = &txq_inst;
4789 txq_emit_data.dst_type = ctx->v4i32;
4790 set_tex_fetch_args(ctx, &txq_emit_data, TGSI_OPCODE_TXQ,
4791 txq_inst.Texture.Texture,
4792 emit_data->args[1], NULL,
4793 &ctx->soa.bld_base.uint_bld.zero,
4794 1, 0xf);
4795 txq_emit(NULL, &ctx->soa.bld_base, &txq_emit_data);
4796
4797 /* Compute -0.5 / size. */
4798 for (c = 0; c < 2; c++) {
4799 half_texel[c] =
4800 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
4801 LLVMConstInt(ctx->i32, c, 0), "");
4802 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
4803 half_texel[c] =
4804 lp_build_emit_llvm_unary(&ctx->soa.bld_base,
4805 TGSI_OPCODE_RCP, half_texel[c]);
4806 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
4807 LLVMConstReal(ctx->f32, -0.5), "");
4808 }
4809 }
4810
4811 for (c = 0; c < 2; c++) {
4812 LLVMValueRef tmp;
4813 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
4814
4815 tmp = LLVMBuildExtractElement(builder, coord, index, "");
4816 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4817 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
4818 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4819 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
4820 }
4821
4822 emit_data->args[0] = coord;
4823 emit_data->output[emit_data->chan] =
4824 lp_build_intrinsic(builder, intr_name, emit_data->dst_type,
4825 emit_data->args, emit_data->arg_count,
4826 LP_FUNC_ATTR_READNONE);
4827 }
4828
4829 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4830 struct lp_build_tgsi_context *bld_base,
4831 struct lp_build_emit_data *emit_data)
4832 {
4833 struct si_shader_context *ctx = si_shader_context(bld_base);
4834 struct lp_build_context *base = &bld_base->base;
4835 const struct tgsi_full_instruction *inst = emit_data->inst;
4836 unsigned opcode = inst->Instruction.Opcode;
4837 unsigned target = inst->Texture.Texture;
4838 char intr_name[127];
4839 bool has_offset = inst->Texture.NumOffsets > 0;
4840 bool is_shadow = tgsi_is_shadow_target(target);
4841 char type[64];
4842 const char *name = "llvm.SI.image.sample";
4843 const char *infix = "";
4844
4845 if (target == TGSI_TEXTURE_BUFFER) {
4846 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4847 base->gallivm->builder,
4848 "llvm.SI.vs.load.input", emit_data->dst_type,
4849 emit_data->args, emit_data->arg_count,
4850 LP_FUNC_ATTR_READNONE);
4851 return;
4852 }
4853
4854 switch (opcode) {
4855 case TGSI_OPCODE_TXF:
4856 name = target == TGSI_TEXTURE_2D_MSAA ||
4857 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4858 "llvm.SI.image.load" :
4859 "llvm.SI.image.load.mip";
4860 is_shadow = false;
4861 has_offset = false;
4862 break;
4863 case TGSI_OPCODE_LODQ:
4864 name = "llvm.SI.getlod";
4865 is_shadow = false;
4866 has_offset = false;
4867 break;
4868 case TGSI_OPCODE_TEX:
4869 case TGSI_OPCODE_TEX2:
4870 case TGSI_OPCODE_TXP:
4871 if (ctx->type != PIPE_SHADER_FRAGMENT)
4872 infix = ".lz";
4873 break;
4874 case TGSI_OPCODE_TXB:
4875 case TGSI_OPCODE_TXB2:
4876 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4877 infix = ".b";
4878 break;
4879 case TGSI_OPCODE_TXL:
4880 case TGSI_OPCODE_TXL2:
4881 infix = ".l";
4882 break;
4883 case TGSI_OPCODE_TXD:
4884 infix = ".d";
4885 break;
4886 case TGSI_OPCODE_TG4:
4887 name = "llvm.SI.gather4";
4888 infix = ".lz";
4889 break;
4890 default:
4891 assert(0);
4892 return;
4893 }
4894
4895 /* Add the type and suffixes .c, .o if needed. */
4896 build_type_name_for_intr(LLVMTypeOf(emit_data->args[0]), type, sizeof(type));
4897 sprintf(intr_name, "%s%s%s%s.%s",
4898 name, is_shadow ? ".c" : "", infix,
4899 has_offset ? ".o" : "", type);
4900
4901 /* The hardware needs special lowering for Gather4 with integer formats. */
4902 if (opcode == TGSI_OPCODE_TG4) {
4903 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4904 /* This will also work with non-constant indexing because of how
4905 * glsl_to_tgsi works and we intent to preserve that behavior.
4906 */
4907 const unsigned src_idx = 2;
4908 unsigned sampler = inst->Src[src_idx].Register.Index;
4909
4910 assert(inst->Src[src_idx].Register.File == TGSI_FILE_SAMPLER);
4911
4912 if (info->sampler_type[sampler] == TGSI_RETURN_TYPE_SINT ||
4913 info->sampler_type[sampler] == TGSI_RETURN_TYPE_UINT) {
4914 /* Texture coordinates start after:
4915 * {offset, bias, z-compare, derivatives}
4916 * Only the offset and z-compare can occur here.
4917 */
4918 si_lower_gather4_integer(ctx, emit_data, intr_name,
4919 (int)has_offset + (int)is_shadow);
4920 return;
4921 }
4922 }
4923
4924 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4925 base->gallivm->builder, intr_name, emit_data->dst_type,
4926 emit_data->args, emit_data->arg_count,
4927 LP_FUNC_ATTR_READNONE);
4928 }
4929
4930 static void si_llvm_emit_txqs(
4931 const struct lp_build_tgsi_action *action,
4932 struct lp_build_tgsi_context *bld_base,
4933 struct lp_build_emit_data *emit_data)
4934 {
4935 struct si_shader_context *ctx = si_shader_context(bld_base);
4936 struct gallivm_state *gallivm = bld_base->base.gallivm;
4937 LLVMBuilderRef builder = gallivm->builder;
4938 LLVMValueRef res, samples;
4939 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4940
4941 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4942
4943
4944 /* Read the samples from the descriptor directly. */
4945 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4946 samples = LLVMBuildExtractElement(
4947 builder, res,
4948 lp_build_const_int32(gallivm, 3), "");
4949 samples = LLVMBuildLShr(builder, samples,
4950 lp_build_const_int32(gallivm, 16), "");
4951 samples = LLVMBuildAnd(builder, samples,
4952 lp_build_const_int32(gallivm, 0xf), "");
4953 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
4954 samples, "");
4955
4956 emit_data->output[emit_data->chan] = samples;
4957 }
4958
4959 /*
4960 * SI implements derivatives using the local data store (LDS)
4961 * All writes to the LDS happen in all executing threads at
4962 * the same time. TID is the Thread ID for the current
4963 * thread and is a value between 0 and 63, representing
4964 * the thread's position in the wavefront.
4965 *
4966 * For the pixel shader threads are grouped into quads of four pixels.
4967 * The TIDs of the pixels of a quad are:
4968 *
4969 * +------+------+
4970 * |4n + 0|4n + 1|
4971 * +------+------+
4972 * |4n + 2|4n + 3|
4973 * +------+------+
4974 *
4975 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
4976 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
4977 * the current pixel's column, and masking with 0xfffffffe yields the TID
4978 * of the left pixel of the current pixel's row.
4979 *
4980 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
4981 * adding 2 yields the TID of the pixel below the top pixel.
4982 */
4983 /* masks for thread ID. */
4984 #define TID_MASK_TOP_LEFT 0xfffffffc
4985 #define TID_MASK_TOP 0xfffffffd
4986 #define TID_MASK_LEFT 0xfffffffe
4987
4988 static void si_llvm_emit_ddxy(
4989 const struct lp_build_tgsi_action *action,
4990 struct lp_build_tgsi_context *bld_base,
4991 struct lp_build_emit_data *emit_data)
4992 {
4993 struct si_shader_context *ctx = si_shader_context(bld_base);
4994 struct gallivm_state *gallivm = bld_base->base.gallivm;
4995 unsigned opcode = emit_data->info->opcode;
4996 LLVMValueRef thread_id, tl, trbl, tl_tid, trbl_tid, val, args[2];
4997 int idx;
4998 unsigned mask;
4999
5000 thread_id = get_thread_id(ctx);
5001
5002 if (opcode == TGSI_OPCODE_DDX_FINE)
5003 mask = TID_MASK_LEFT;
5004 else if (opcode == TGSI_OPCODE_DDY_FINE)
5005 mask = TID_MASK_TOP;
5006 else
5007 mask = TID_MASK_TOP_LEFT;
5008
5009 tl_tid = LLVMBuildAnd(gallivm->builder, thread_id,
5010 lp_build_const_int32(gallivm, mask), "");
5011
5012 /* for DDX we want to next X pixel, DDY next Y pixel. */
5013 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
5014 trbl_tid = LLVMBuildAdd(gallivm->builder, tl_tid,
5015 lp_build_const_int32(gallivm, idx), "");
5016
5017 val = LLVMBuildBitCast(gallivm->builder, emit_data->args[0], ctx->i32, "");
5018
5019 if (ctx->screen->has_ds_bpermute) {
5020 args[0] = LLVMBuildMul(gallivm->builder, tl_tid,
5021 lp_build_const_int32(gallivm, 4), "");
5022 args[1] = val;
5023 tl = lp_build_intrinsic(gallivm->builder,
5024 "llvm.amdgcn.ds.bpermute", ctx->i32,
5025 args, 2, LP_FUNC_ATTR_READNONE);
5026
5027 args[0] = LLVMBuildMul(gallivm->builder, trbl_tid,
5028 lp_build_const_int32(gallivm, 4), "");
5029 trbl = lp_build_intrinsic(gallivm->builder,
5030 "llvm.amdgcn.ds.bpermute", ctx->i32,
5031 args, 2, LP_FUNC_ATTR_READNONE);
5032 } else {
5033 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
5034
5035 store_ptr = build_gep0(ctx, ctx->lds, thread_id);
5036 load_ptr0 = build_gep0(ctx, ctx->lds, tl_tid);
5037 load_ptr1 = build_gep0(ctx, ctx->lds, trbl_tid);
5038
5039 LLVMBuildStore(gallivm->builder, val, store_ptr);
5040 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
5041 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
5042 }
5043
5044 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
5045 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
5046
5047 emit_data->output[emit_data->chan] =
5048 LLVMBuildFSub(gallivm->builder, trbl, tl, "");
5049 }
5050
5051 /*
5052 * this takes an I,J coordinate pair,
5053 * and works out the X and Y derivatives.
5054 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
5055 */
5056 static LLVMValueRef si_llvm_emit_ddxy_interp(
5057 struct lp_build_tgsi_context *bld_base,
5058 LLVMValueRef interp_ij)
5059 {
5060 struct si_shader_context *ctx = si_shader_context(bld_base);
5061 struct gallivm_state *gallivm = bld_base->base.gallivm;
5062 LLVMValueRef result[4], a;
5063 unsigned i;
5064
5065 for (i = 0; i < 2; i++) {
5066 a = LLVMBuildExtractElement(gallivm->builder, interp_ij,
5067 LLVMConstInt(ctx->i32, i, 0), "");
5068 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
5069 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
5070 }
5071
5072 return lp_build_gather_values(gallivm, result, 4);
5073 }
5074
5075 static void interp_fetch_args(
5076 struct lp_build_tgsi_context *bld_base,
5077 struct lp_build_emit_data *emit_data)
5078 {
5079 struct si_shader_context *ctx = si_shader_context(bld_base);
5080 struct gallivm_state *gallivm = bld_base->base.gallivm;
5081 const struct tgsi_full_instruction *inst = emit_data->inst;
5082
5083 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
5084 /* offset is in second src, first two channels */
5085 emit_data->args[0] = lp_build_emit_fetch(bld_base,
5086 emit_data->inst, 1,
5087 TGSI_CHAN_X);
5088 emit_data->args[1] = lp_build_emit_fetch(bld_base,
5089 emit_data->inst, 1,
5090 TGSI_CHAN_Y);
5091 emit_data->arg_count = 2;
5092 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5093 LLVMValueRef sample_position;
5094 LLVMValueRef sample_id;
5095 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
5096
5097 /* fetch sample ID, then fetch its sample position,
5098 * and place into first two channels.
5099 */
5100 sample_id = lp_build_emit_fetch(bld_base,
5101 emit_data->inst, 1, TGSI_CHAN_X);
5102 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
5103 ctx->i32, "");
5104 sample_position = load_sample_position(ctx, sample_id);
5105
5106 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
5107 sample_position,
5108 lp_build_const_int32(gallivm, 0), "");
5109
5110 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
5111 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
5112 sample_position,
5113 lp_build_const_int32(gallivm, 1), "");
5114 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
5115 emit_data->arg_count = 2;
5116 }
5117 }
5118
5119 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
5120 struct lp_build_tgsi_context *bld_base,
5121 struct lp_build_emit_data *emit_data)
5122 {
5123 struct si_shader_context *ctx = si_shader_context(bld_base);
5124 struct si_shader *shader = ctx->shader;
5125 struct gallivm_state *gallivm = bld_base->base.gallivm;
5126 struct lp_build_context *uint = &bld_base->uint_bld;
5127 LLVMValueRef interp_param;
5128 const struct tgsi_full_instruction *inst = emit_data->inst;
5129 int input_index = inst->Src[0].Register.Index;
5130 int chan;
5131 int i;
5132 LLVMValueRef attr_number;
5133 LLVMValueRef params = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
5134 int interp_param_idx;
5135 unsigned interp = shader->selector->info.input_interpolate[input_index];
5136 unsigned location;
5137
5138 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5139
5140 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5141 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
5142 location = TGSI_INTERPOLATE_LOC_CENTER;
5143 else
5144 location = TGSI_INTERPOLATE_LOC_CENTROID;
5145
5146 interp_param_idx = lookup_interp_param_index(interp, location);
5147 if (interp_param_idx == -1)
5148 return;
5149 else if (interp_param_idx)
5150 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
5151 else
5152 interp_param = NULL;
5153
5154 attr_number = lp_build_const_int32(gallivm, input_index);
5155
5156 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5157 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5158 LLVMValueRef ij_out[2];
5159 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
5160
5161 /*
5162 * take the I then J parameters, and the DDX/Y for it, and
5163 * calculate the IJ inputs for the interpolator.
5164 * temp1 = ddx * offset/sample.x + I;
5165 * interp_param.I = ddy * offset/sample.y + temp1;
5166 * temp1 = ddx * offset/sample.x + J;
5167 * interp_param.J = ddy * offset/sample.y + temp1;
5168 */
5169 for (i = 0; i < 2; i++) {
5170 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
5171 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
5172 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
5173 ddxy_out, ix_ll, "");
5174 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
5175 ddxy_out, iy_ll, "");
5176 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5177 interp_param, ix_ll, "");
5178 LLVMValueRef temp1, temp2;
5179
5180 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5181 ctx->f32, "");
5182
5183 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5184
5185 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5186
5187 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5188
5189 ij_out[i] = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5190 }
5191 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
5192 }
5193
5194 for (chan = 0; chan < 4; chan++) {
5195 LLVMValueRef llvm_chan;
5196 unsigned schan;
5197
5198 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5199 llvm_chan = lp_build_const_int32(gallivm, schan);
5200
5201 if (interp_param) {
5202 interp_param = LLVMBuildBitCast(gallivm->builder,
5203 interp_param, LLVMVectorType(ctx->f32, 2), "");
5204 LLVMValueRef i = LLVMBuildExtractElement(
5205 gallivm->builder, interp_param, uint->zero, "");
5206 LLVMValueRef j = LLVMBuildExtractElement(
5207 gallivm->builder, interp_param, uint->one, "");
5208 emit_data->output[chan] = build_fs_interp(bld_base,
5209 llvm_chan, attr_number, params,
5210 i, j);
5211 } else {
5212 emit_data->output[chan] = build_fs_interp_mov(bld_base,
5213 lp_build_const_int32(gallivm, 2), /* P0 */
5214 llvm_chan, attr_number, params);
5215 }
5216 }
5217 }
5218
5219 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5220 struct lp_build_emit_data *emit_data)
5221 {
5222 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
5223 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5224 unsigned stream;
5225
5226 assert(src0.File == TGSI_FILE_IMMEDIATE);
5227
5228 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
5229 return stream;
5230 }
5231
5232 /* Emit one vertex from the geometry shader */
5233 static void si_llvm_emit_vertex(
5234 const struct lp_build_tgsi_action *action,
5235 struct lp_build_tgsi_context *bld_base,
5236 struct lp_build_emit_data *emit_data)
5237 {
5238 struct si_shader_context *ctx = si_shader_context(bld_base);
5239 struct lp_build_context *uint = &bld_base->uint_bld;
5240 struct si_shader *shader = ctx->shader;
5241 struct tgsi_shader_info *info = &shader->selector->info;
5242 struct gallivm_state *gallivm = bld_base->base.gallivm;
5243 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
5244 SI_PARAM_GS2VS_OFFSET);
5245 LLVMValueRef gs_next_vertex;
5246 LLVMValueRef can_emit, kill;
5247 LLVMValueRef args[2];
5248 unsigned chan;
5249 int i;
5250 unsigned stream;
5251
5252 stream = si_llvm_get_stream(bld_base, emit_data);
5253
5254 /* Write vertex attribute values to GSVS ring */
5255 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5256 ctx->gs_next_vertex[stream],
5257 "");
5258
5259 /* If this thread has already emitted the declared maximum number of
5260 * vertices, kill it: excessive vertex emissions are not supposed to
5261 * have any effect, and GS threads have no externally observable
5262 * effects other than emitting vertices.
5263 */
5264 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
5265 lp_build_const_int32(gallivm,
5266 shader->selector->gs_max_out_vertices), "");
5267 kill = lp_build_select(&bld_base->base, can_emit,
5268 lp_build_const_float(gallivm, 1.0f),
5269 lp_build_const_float(gallivm, -1.0f));
5270
5271 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
5272 ctx->voidt, &kill, 1, 0);
5273
5274 for (i = 0; i < info->num_outputs; i++) {
5275 LLVMValueRef *out_ptr =
5276 ctx->soa.outputs[i];
5277
5278 for (chan = 0; chan < 4; chan++) {
5279 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5280 LLVMValueRef voffset =
5281 lp_build_const_int32(gallivm, (i * 4 + chan) *
5282 shader->selector->gs_max_out_vertices);
5283
5284 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5285 voffset = lp_build_mul_imm(uint, voffset, 4);
5286
5287 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5288
5289 build_tbuffer_store(ctx,
5290 ctx->gsvs_ring[stream],
5291 out_val, 1,
5292 voffset, soffset, 0,
5293 V_008F0C_BUF_DATA_FORMAT_32,
5294 V_008F0C_BUF_NUM_FORMAT_UINT,
5295 1, 0, 1, 1, 0);
5296 }
5297 }
5298 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5299 lp_build_const_int32(gallivm, 1));
5300
5301 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5302
5303 /* Signal vertex emission */
5304 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
5305 args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID);
5306 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5307 ctx->voidt, args, 2, 0);
5308 }
5309
5310 /* Cut one primitive from the geometry shader */
5311 static void si_llvm_emit_primitive(
5312 const struct lp_build_tgsi_action *action,
5313 struct lp_build_tgsi_context *bld_base,
5314 struct lp_build_emit_data *emit_data)
5315 {
5316 struct si_shader_context *ctx = si_shader_context(bld_base);
5317 struct gallivm_state *gallivm = bld_base->base.gallivm;
5318 LLVMValueRef args[2];
5319 unsigned stream;
5320
5321 /* Signal primitive cut */
5322 stream = si_llvm_get_stream(bld_base, emit_data);
5323 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
5324 args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID);
5325 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5326 ctx->voidt, args, 2, 0);
5327 }
5328
5329 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5330 struct lp_build_tgsi_context *bld_base,
5331 struct lp_build_emit_data *emit_data)
5332 {
5333 struct si_shader_context *ctx = si_shader_context(bld_base);
5334 struct gallivm_state *gallivm = bld_base->base.gallivm;
5335
5336 /* The real barrier instruction isn’t needed, because an entire patch
5337 * always fits into a single wave.
5338 */
5339 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
5340 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
5341 return;
5342 }
5343
5344 lp_build_intrinsic(gallivm->builder,
5345 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5346 : "llvm.AMDGPU.barrier.local",
5347 ctx->voidt, NULL, 0, 0);
5348 }
5349
5350 static const struct lp_build_tgsi_action tex_action = {
5351 .fetch_args = tex_fetch_args,
5352 .emit = build_tex_intrinsic,
5353 };
5354
5355 static const struct lp_build_tgsi_action interp_action = {
5356 .fetch_args = interp_fetch_args,
5357 .emit = build_interp_intrinsic,
5358 };
5359
5360 static void si_create_function(struct si_shader_context *ctx,
5361 const char *name,
5362 LLVMTypeRef *returns, unsigned num_returns,
5363 LLVMTypeRef *params, unsigned num_params,
5364 int last_sgpr)
5365 {
5366 int i;
5367
5368 si_llvm_create_func(ctx, name, returns, num_returns,
5369 params, num_params);
5370 si_llvm_shader_type(ctx->main_fn, ctx->type);
5371 ctx->return_value = LLVMGetUndef(ctx->return_type);
5372
5373 for (i = 0; i <= last_sgpr; ++i) {
5374 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
5375
5376 /* The combination of:
5377 * - ByVal
5378 * - dereferenceable
5379 * - invariant.load
5380 * allows the optimization passes to move loads and reduces
5381 * SGPR spilling significantly.
5382 */
5383 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
5384 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
5385 lp_add_attr_dereferenceable(P, UINT64_MAX);
5386 } else
5387 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
5388 }
5389
5390 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5391 /* These were copied from some LLVM test. */
5392 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5393 "less-precise-fpmad",
5394 "true");
5395 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5396 "no-infs-fp-math",
5397 "true");
5398 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5399 "no-nans-fp-math",
5400 "true");
5401 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5402 "unsafe-fp-math",
5403 "true");
5404 }
5405 }
5406
5407 static void create_meta_data(struct si_shader_context *ctx)
5408 {
5409 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
5410
5411 ctx->invariant_load_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5412 "invariant.load", 14);
5413 ctx->range_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5414 "range", 5);
5415 ctx->uniform_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5416 "amdgpu.uniform", 14);
5417
5418 ctx->empty_md = LLVMMDNodeInContext(gallivm->context, NULL, 0);
5419 }
5420
5421 static void declare_streamout_params(struct si_shader_context *ctx,
5422 struct pipe_stream_output_info *so,
5423 LLVMTypeRef *params, LLVMTypeRef i32,
5424 unsigned *num_params)
5425 {
5426 int i;
5427
5428 /* Streamout SGPRs. */
5429 if (so->num_outputs) {
5430 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5431 params[ctx->param_streamout_config = (*num_params)++] = i32;
5432 else
5433 ctx->param_streamout_config = ctx->param_tess_offchip;
5434
5435 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5436 }
5437 /* A streamout buffer offset is loaded if the stride is non-zero. */
5438 for (i = 0; i < 4; i++) {
5439 if (!so->stride[i])
5440 continue;
5441
5442 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5443 }
5444 }
5445
5446 static unsigned llvm_get_type_size(LLVMTypeRef type)
5447 {
5448 LLVMTypeKind kind = LLVMGetTypeKind(type);
5449
5450 switch (kind) {
5451 case LLVMIntegerTypeKind:
5452 return LLVMGetIntTypeWidth(type) / 8;
5453 case LLVMFloatTypeKind:
5454 return 4;
5455 case LLVMPointerTypeKind:
5456 return 8;
5457 case LLVMVectorTypeKind:
5458 return LLVMGetVectorSize(type) *
5459 llvm_get_type_size(LLVMGetElementType(type));
5460 case LLVMArrayTypeKind:
5461 return LLVMGetArrayLength(type) *
5462 llvm_get_type_size(LLVMGetElementType(type));
5463 default:
5464 assert(0);
5465 return 0;
5466 }
5467 }
5468
5469 static void declare_tess_lds(struct si_shader_context *ctx)
5470 {
5471 struct gallivm_state *gallivm = &ctx->gallivm;
5472 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
5473 struct lp_build_context *uint = &bld_base->uint_bld;
5474
5475 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5476 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, uint->zero,
5477 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
5478 "tess_lds");
5479 }
5480
5481 static unsigned si_get_max_workgroup_size(struct si_shader *shader)
5482 {
5483 const unsigned *properties = shader->selector->info.properties;
5484 unsigned max_work_group_size =
5485 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5486 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5487 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5488
5489 if (!max_work_group_size) {
5490 /* This is a variable group size compute shader,
5491 * compile it for the maximum possible group size.
5492 */
5493 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
5494 }
5495 return max_work_group_size;
5496 }
5497
5498 static void create_function(struct si_shader_context *ctx)
5499 {
5500 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
5501 struct gallivm_state *gallivm = bld_base->base.gallivm;
5502 struct si_shader *shader = ctx->shader;
5503 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
5504 LLVMTypeRef returns[16+32*4];
5505 unsigned i, last_sgpr, num_params, num_return_sgprs;
5506 unsigned num_returns = 0;
5507 unsigned num_prolog_vgprs = 0;
5508
5509 v3i32 = LLVMVectorType(ctx->i32, 3);
5510
5511 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5512 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5513 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5514 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5515 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5516
5517 switch (ctx->type) {
5518 case PIPE_SHADER_VERTEX:
5519 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
5520 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5521 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5522 params[SI_PARAM_DRAWID] = ctx->i32;
5523 num_params = SI_PARAM_DRAWID+1;
5524
5525 if (shader->key.as_es) {
5526 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5527 } else if (shader->key.as_ls) {
5528 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
5529 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
5530 } else {
5531 if (shader->is_gs_copy_shader) {
5532 num_params = SI_PARAM_RW_BUFFERS+1;
5533 } else {
5534 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5535 num_params = SI_PARAM_VS_STATE_BITS+1;
5536 }
5537
5538 /* The locations of the other parameters are assigned dynamically. */
5539 declare_streamout_params(ctx, &shader->selector->so,
5540 params, ctx->i32, &num_params);
5541 }
5542
5543 last_sgpr = num_params-1;
5544
5545 /* VGPRs */
5546 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5547 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5548 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5549 params[ctx->param_instance_id = num_params++] = ctx->i32;
5550
5551 if (!shader->is_gs_copy_shader) {
5552 /* Vertex load indices. */
5553 ctx->param_vertex_index0 = num_params;
5554
5555 for (i = 0; i < shader->selector->info.num_inputs; i++)
5556 params[num_params++] = ctx->i32;
5557
5558 num_prolog_vgprs += shader->selector->info.num_inputs;
5559
5560 /* PrimitiveID output. */
5561 if (!shader->key.as_es && !shader->key.as_ls)
5562 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5563 returns[num_returns++] = ctx->f32;
5564 }
5565 break;
5566
5567 case PIPE_SHADER_TESS_CTRL:
5568 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5569 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5570 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5571 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5572 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5573 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5574 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5575
5576 /* VGPRs */
5577 params[SI_PARAM_PATCH_ID] = ctx->i32;
5578 params[SI_PARAM_REL_IDS] = ctx->i32;
5579 num_params = SI_PARAM_REL_IDS+1;
5580
5581 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5582 * placed after the user SGPRs.
5583 */
5584 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5585 returns[num_returns++] = ctx->i32; /* SGPRs */
5586
5587 for (i = 0; i < 3; i++)
5588 returns[num_returns++] = ctx->f32; /* VGPRs */
5589 break;
5590
5591 case PIPE_SHADER_TESS_EVAL:
5592 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5593 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5594
5595 if (shader->key.as_es) {
5596 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5597 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5598 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5599 } else {
5600 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5601 declare_streamout_params(ctx, &shader->selector->so,
5602 params, ctx->i32, &num_params);
5603 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5604 }
5605 last_sgpr = num_params - 1;
5606
5607 /* VGPRs */
5608 params[ctx->param_tes_u = num_params++] = ctx->f32;
5609 params[ctx->param_tes_v = num_params++] = ctx->f32;
5610 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5611 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5612
5613 /* PrimitiveID output. */
5614 if (!shader->key.as_es)
5615 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5616 returns[num_returns++] = ctx->f32;
5617 break;
5618
5619 case PIPE_SHADER_GEOMETRY:
5620 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5621 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5622 last_sgpr = SI_PARAM_GS_WAVE_ID;
5623
5624 /* VGPRs */
5625 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5626 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5627 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5628 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5629 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5630 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5631 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5632 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5633 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5634 break;
5635
5636 case PIPE_SHADER_FRAGMENT:
5637 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5638 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5639 last_sgpr = SI_PARAM_PRIM_MASK;
5640 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5641 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5642 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5643 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5644 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5645 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5646 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5647 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5648 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5649 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5650 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5651 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5652 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5653 shader->info.face_vgpr_index = 20;
5654 params[SI_PARAM_ANCILLARY] = ctx->i32;
5655 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5656 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5657 num_params = SI_PARAM_POS_FIXED_PT+1;
5658
5659 /* Color inputs from the prolog. */
5660 if (shader->selector->info.colors_read) {
5661 unsigned num_color_elements =
5662 util_bitcount(shader->selector->info.colors_read);
5663
5664 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5665 for (i = 0; i < num_color_elements; i++)
5666 params[num_params++] = ctx->f32;
5667
5668 num_prolog_vgprs += num_color_elements;
5669 }
5670
5671 /* Outputs for the epilog. */
5672 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5673 num_returns =
5674 num_return_sgprs +
5675 util_bitcount(shader->selector->info.colors_written) * 4 +
5676 shader->selector->info.writes_z +
5677 shader->selector->info.writes_stencil +
5678 shader->selector->info.writes_samplemask +
5679 1 /* SampleMaskIn */;
5680
5681 num_returns = MAX2(num_returns,
5682 num_return_sgprs +
5683 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5684
5685 for (i = 0; i < num_return_sgprs; i++)
5686 returns[i] = ctx->i32;
5687 for (; i < num_returns; i++)
5688 returns[i] = ctx->f32;
5689 break;
5690
5691 case PIPE_SHADER_COMPUTE:
5692 params[SI_PARAM_GRID_SIZE] = v3i32;
5693 params[SI_PARAM_BLOCK_SIZE] = v3i32;
5694 params[SI_PARAM_BLOCK_ID] = v3i32;
5695 last_sgpr = SI_PARAM_BLOCK_ID;
5696
5697 params[SI_PARAM_THREAD_ID] = v3i32;
5698 num_params = SI_PARAM_THREAD_ID + 1;
5699 break;
5700 default:
5701 assert(0 && "unimplemented shader");
5702 return;
5703 }
5704
5705 assert(num_params <= ARRAY_SIZE(params));
5706
5707 si_create_function(ctx, "main", returns, num_returns, params,
5708 num_params, last_sgpr);
5709
5710 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5711 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5712 ctx->separate_prolog) {
5713 si_llvm_add_attribute(ctx->main_fn,
5714 "InitialPSInputAddr",
5715 S_0286D0_PERSP_SAMPLE_ENA(1) |
5716 S_0286D0_PERSP_CENTER_ENA(1) |
5717 S_0286D0_PERSP_CENTROID_ENA(1) |
5718 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5719 S_0286D0_LINEAR_CENTER_ENA(1) |
5720 S_0286D0_LINEAR_CENTROID_ENA(1) |
5721 S_0286D0_FRONT_FACE_ENA(1) |
5722 S_0286D0_POS_FIXED_PT_ENA(1));
5723 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5724 si_llvm_add_attribute(ctx->main_fn,
5725 "amdgpu-max-work-group-size",
5726 si_get_max_workgroup_size(shader));
5727 }
5728
5729 shader->info.num_input_sgprs = 0;
5730 shader->info.num_input_vgprs = 0;
5731
5732 for (i = 0; i <= last_sgpr; ++i)
5733 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5734
5735 for (; i < num_params; ++i)
5736 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5737
5738 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5739 shader->info.num_input_vgprs -= num_prolog_vgprs;
5740
5741 if (!ctx->screen->has_ds_bpermute &&
5742 bld_base->info &&
5743 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5744 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5745 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5746 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5747 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5748 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5749 ctx->lds =
5750 LLVMAddGlobalInAddressSpace(gallivm->module,
5751 LLVMArrayType(ctx->i32, 64),
5752 "ddxy_lds",
5753 LOCAL_ADDR_SPACE);
5754
5755 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.as_ls) ||
5756 ctx->type == PIPE_SHADER_TESS_CTRL ||
5757 ctx->type == PIPE_SHADER_TESS_EVAL)
5758 declare_tess_lds(ctx);
5759 }
5760
5761 /**
5762 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5763 * for later use.
5764 */
5765 static void preload_ring_buffers(struct si_shader_context *ctx)
5766 {
5767 struct gallivm_state *gallivm =
5768 ctx->soa.bld_base.base.gallivm;
5769
5770 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5771 SI_PARAM_RW_BUFFERS);
5772
5773 if ((ctx->type == PIPE_SHADER_VERTEX &&
5774 ctx->shader->key.as_es) ||
5775 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5776 ctx->shader->key.as_es) ||
5777 ctx->type == PIPE_SHADER_GEOMETRY) {
5778 unsigned ring =
5779 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5780 : SI_ES_RING_ESGS;
5781 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5782
5783 ctx->esgs_ring =
5784 build_indexed_load_const(ctx, buf_ptr, offset);
5785 }
5786
5787 if (ctx->shader->is_gs_copy_shader) {
5788 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_VS_RING_GSVS);
5789
5790 ctx->gsvs_ring[0] =
5791 build_indexed_load_const(ctx, buf_ptr, offset);
5792 }
5793 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5794 int i;
5795 for (i = 0; i < 4; i++) {
5796 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_GS_RING_GSVS0 + i);
5797
5798 ctx->gsvs_ring[i] =
5799 build_indexed_load_const(ctx, buf_ptr, offset);
5800 }
5801 }
5802 }
5803
5804 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5805 LLVMValueRef param_rw_buffers,
5806 unsigned param_pos_fixed_pt)
5807 {
5808 struct lp_build_tgsi_context *bld_base =
5809 &ctx->soa.bld_base;
5810 struct gallivm_state *gallivm = bld_base->base.gallivm;
5811 LLVMBuilderRef builder = gallivm->builder;
5812 LLVMValueRef slot, desc, offset, row, bit, address[2];
5813
5814 /* Use the fixed-point gl_FragCoord input.
5815 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5816 * per coordinate to get the repeating effect.
5817 */
5818 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5819 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5820
5821 /* Load the buffer descriptor. */
5822 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
5823 desc = build_indexed_load_const(ctx, param_rw_buffers, slot);
5824
5825 /* The stipple pattern is 32x32, each row has 32 bits. */
5826 offset = LLVMBuildMul(builder, address[1],
5827 LLVMConstInt(ctx->i32, 4, 0), "");
5828 row = buffer_load_const(ctx, desc, offset);
5829 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
5830 bit = LLVMBuildLShr(builder, row, address[0], "");
5831 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5832
5833 /* The intrinsic kills the thread if arg < 0. */
5834 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
5835 LLVMConstReal(ctx->f32, -1), "");
5836 lp_build_intrinsic(builder, "llvm.AMDGPU.kill", ctx->voidt, &bit, 1, 0);
5837 }
5838
5839 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
5840 struct si_shader_config *conf,
5841 unsigned symbol_offset)
5842 {
5843 unsigned i;
5844 const unsigned char *config =
5845 radeon_shader_binary_config_start(binary, symbol_offset);
5846 bool really_needs_scratch = false;
5847
5848 /* LLVM adds SGPR spills to the scratch size.
5849 * Find out if we really need the scratch buffer.
5850 */
5851 for (i = 0; i < binary->reloc_count; i++) {
5852 const struct radeon_shader_reloc *reloc = &binary->relocs[i];
5853
5854 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5855 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5856 really_needs_scratch = true;
5857 break;
5858 }
5859 }
5860
5861 /* XXX: We may be able to emit some of these values directly rather than
5862 * extracting fields to be emitted later.
5863 */
5864
5865 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5866 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5867 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5868 switch (reg) {
5869 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5870 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5871 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5872 case R_00B848_COMPUTE_PGM_RSRC1:
5873 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5874 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5875 conf->float_mode = G_00B028_FLOAT_MODE(value);
5876 conf->rsrc1 = value;
5877 break;
5878 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5879 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5880 break;
5881 case R_00B84C_COMPUTE_PGM_RSRC2:
5882 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5883 conf->rsrc2 = value;
5884 break;
5885 case R_0286CC_SPI_PS_INPUT_ENA:
5886 conf->spi_ps_input_ena = value;
5887 break;
5888 case R_0286D0_SPI_PS_INPUT_ADDR:
5889 conf->spi_ps_input_addr = value;
5890 break;
5891 case R_0286E8_SPI_TMPRING_SIZE:
5892 case R_00B860_COMPUTE_TMPRING_SIZE:
5893 /* WAVESIZE is in units of 256 dwords. */
5894 if (really_needs_scratch)
5895 conf->scratch_bytes_per_wave =
5896 G_00B860_WAVESIZE(value) * 256 * 4;
5897 break;
5898 case 0x4: /* SPILLED_SGPRS */
5899 conf->spilled_sgprs = value;
5900 break;
5901 case 0x8: /* SPILLED_VGPRS */
5902 conf->spilled_vgprs = value;
5903 break;
5904 default:
5905 {
5906 static bool printed;
5907
5908 if (!printed) {
5909 fprintf(stderr, "Warning: LLVM emitted unknown "
5910 "config register: 0x%x\n", reg);
5911 printed = true;
5912 }
5913 }
5914 break;
5915 }
5916 }
5917
5918 if (!conf->spi_ps_input_addr)
5919 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5920 }
5921
5922 void si_shader_apply_scratch_relocs(struct si_context *sctx,
5923 struct si_shader *shader,
5924 struct si_shader_config *config,
5925 uint64_t scratch_va)
5926 {
5927 unsigned i;
5928 uint32_t scratch_rsrc_dword0 = scratch_va;
5929 uint32_t scratch_rsrc_dword1 =
5930 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5931
5932 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
5933 * correctly.
5934 */
5935 if (HAVE_LLVM >= 0x0309)
5936 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5937 else
5938 scratch_rsrc_dword1 |=
5939 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
5940
5941 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5942 const struct radeon_shader_reloc *reloc =
5943 &shader->binary.relocs[i];
5944 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5945 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5946 &scratch_rsrc_dword0, 4);
5947 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5948 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5949 &scratch_rsrc_dword1, 4);
5950 }
5951 }
5952 }
5953
5954 static unsigned si_get_shader_binary_size(struct si_shader *shader)
5955 {
5956 unsigned size = shader->binary.code_size;
5957
5958 if (shader->prolog)
5959 size += shader->prolog->binary.code_size;
5960 if (shader->epilog)
5961 size += shader->epilog->binary.code_size;
5962 return size;
5963 }
5964
5965 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5966 {
5967 const struct radeon_shader_binary *prolog =
5968 shader->prolog ? &shader->prolog->binary : NULL;
5969 const struct radeon_shader_binary *epilog =
5970 shader->epilog ? &shader->epilog->binary : NULL;
5971 const struct radeon_shader_binary *mainb = &shader->binary;
5972 unsigned bo_size = si_get_shader_binary_size(shader) +
5973 (!epilog ? mainb->rodata_size : 0);
5974 unsigned char *ptr;
5975
5976 assert(!prolog || !prolog->rodata_size);
5977 assert((!prolog && !epilog) || !mainb->rodata_size);
5978 assert(!epilog || !epilog->rodata_size);
5979
5980 r600_resource_reference(&shader->bo, NULL);
5981 shader->bo = (struct r600_resource*)
5982 pipe_buffer_create(&sscreen->b.b, 0,
5983 PIPE_USAGE_IMMUTABLE, bo_size);
5984 if (!shader->bo)
5985 return -ENOMEM;
5986
5987 /* Upload. */
5988 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
5989 PIPE_TRANSFER_READ_WRITE);
5990
5991 if (prolog) {
5992 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
5993 ptr += prolog->code_size;
5994 }
5995
5996 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
5997 ptr += mainb->code_size;
5998
5999 if (epilog)
6000 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
6001 else if (mainb->rodata_size > 0)
6002 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
6003
6004 sscreen->b.ws->buffer_unmap(shader->bo->buf);
6005 return 0;
6006 }
6007
6008 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
6009 struct pipe_debug_callback *debug,
6010 const char *name, FILE *file)
6011 {
6012 char *line, *p;
6013 unsigned i, count;
6014
6015 if (binary->disasm_string) {
6016 fprintf(file, "Shader %s disassembly:\n", name);
6017 fprintf(file, "%s", binary->disasm_string);
6018
6019 if (debug && debug->debug_message) {
6020 /* Very long debug messages are cut off, so send the
6021 * disassembly one line at a time. This causes more
6022 * overhead, but on the plus side it simplifies
6023 * parsing of resulting logs.
6024 */
6025 pipe_debug_message(debug, SHADER_INFO,
6026 "Shader Disassembly Begin");
6027
6028 line = binary->disasm_string;
6029 while (*line) {
6030 p = util_strchrnul(line, '\n');
6031 count = p - line;
6032
6033 if (count) {
6034 pipe_debug_message(debug, SHADER_INFO,
6035 "%.*s", count, line);
6036 }
6037
6038 if (!*p)
6039 break;
6040 line = p + 1;
6041 }
6042
6043 pipe_debug_message(debug, SHADER_INFO,
6044 "Shader Disassembly End");
6045 }
6046 } else {
6047 fprintf(file, "Shader %s binary:\n", name);
6048 for (i = 0; i < binary->code_size; i += 4) {
6049 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
6050 binary->code[i + 3], binary->code[i + 2],
6051 binary->code[i + 1], binary->code[i]);
6052 }
6053 }
6054 }
6055
6056 static void si_shader_dump_stats(struct si_screen *sscreen,
6057 struct si_shader *shader,
6058 struct pipe_debug_callback *debug,
6059 unsigned processor,
6060 FILE *file)
6061 {
6062 struct si_shader_config *conf = &shader->config;
6063 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
6064 unsigned code_size = si_get_shader_binary_size(shader);
6065 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
6066 unsigned lds_per_wave = 0;
6067 unsigned max_simd_waves = 10;
6068
6069 /* Compute LDS usage for PS. */
6070 switch (processor) {
6071 case PIPE_SHADER_FRAGMENT:
6072 /* The minimum usage per wave is (num_inputs * 48). The maximum
6073 * usage is (num_inputs * 48 * 16).
6074 * We can get anything in between and it varies between waves.
6075 *
6076 * The 48 bytes per input for a single primitive is equal to
6077 * 4 bytes/component * 4 components/input * 3 points.
6078 *
6079 * Other stages don't know the size at compile time or don't
6080 * allocate LDS per wave, but instead they do it per thread group.
6081 */
6082 lds_per_wave = conf->lds_size * lds_increment +
6083 align(num_inputs * 48, lds_increment);
6084 break;
6085 case PIPE_SHADER_COMPUTE:
6086 if (shader->selector) {
6087 unsigned max_workgroup_size =
6088 si_get_max_workgroup_size(shader);
6089 lds_per_wave = (conf->lds_size * lds_increment) /
6090 DIV_ROUND_UP(max_workgroup_size, 64);
6091 }
6092 break;
6093 }
6094
6095 /* Compute the per-SIMD wave counts. */
6096 if (conf->num_sgprs) {
6097 if (sscreen->b.chip_class >= VI)
6098 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
6099 else
6100 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
6101 }
6102
6103 if (conf->num_vgprs)
6104 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
6105
6106 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
6107 * 16KB makes some SIMDs unoccupied). */
6108 if (lds_per_wave)
6109 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
6110
6111 if (file != stderr ||
6112 r600_can_dump_shader(&sscreen->b, processor)) {
6113 if (processor == PIPE_SHADER_FRAGMENT) {
6114 fprintf(file, "*** SHADER CONFIG ***\n"
6115 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6116 "SPI_PS_INPUT_ENA = 0x%04x\n",
6117 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
6118 }
6119
6120 fprintf(file, "*** SHADER STATS ***\n"
6121 "SGPRS: %d\n"
6122 "VGPRS: %d\n"
6123 "Spilled SGPRs: %d\n"
6124 "Spilled VGPRs: %d\n"
6125 "Private memory VGPRs: %d\n"
6126 "Code Size: %d bytes\n"
6127 "LDS: %d blocks\n"
6128 "Scratch: %d bytes per wave\n"
6129 "Max Waves: %d\n"
6130 "********************\n\n\n",
6131 conf->num_sgprs, conf->num_vgprs,
6132 conf->spilled_sgprs, conf->spilled_vgprs,
6133 conf->private_mem_vgprs, code_size,
6134 conf->lds_size, conf->scratch_bytes_per_wave,
6135 max_simd_waves);
6136 }
6137
6138 pipe_debug_message(debug, SHADER_INFO,
6139 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6140 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
6141 "Spilled VGPRs: %d PrivMem VGPRs: %d",
6142 conf->num_sgprs, conf->num_vgprs, code_size,
6143 conf->lds_size, conf->scratch_bytes_per_wave,
6144 max_simd_waves, conf->spilled_sgprs,
6145 conf->spilled_vgprs, conf->private_mem_vgprs);
6146 }
6147
6148 static const char *si_get_shader_name(struct si_shader *shader,
6149 unsigned processor)
6150 {
6151 switch (processor) {
6152 case PIPE_SHADER_VERTEX:
6153 if (shader->key.as_es)
6154 return "Vertex Shader as ES";
6155 else if (shader->key.as_ls)
6156 return "Vertex Shader as LS";
6157 else
6158 return "Vertex Shader as VS";
6159 case PIPE_SHADER_TESS_CTRL:
6160 return "Tessellation Control Shader";
6161 case PIPE_SHADER_TESS_EVAL:
6162 if (shader->key.as_es)
6163 return "Tessellation Evaluation Shader as ES";
6164 else
6165 return "Tessellation Evaluation Shader as VS";
6166 case PIPE_SHADER_GEOMETRY:
6167 if (shader->is_gs_copy_shader)
6168 return "GS Copy Shader as VS";
6169 else
6170 return "Geometry Shader";
6171 case PIPE_SHADER_FRAGMENT:
6172 return "Pixel Shader";
6173 case PIPE_SHADER_COMPUTE:
6174 return "Compute Shader";
6175 default:
6176 return "Unknown Shader";
6177 }
6178 }
6179
6180 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6181 struct pipe_debug_callback *debug, unsigned processor,
6182 FILE *file)
6183 {
6184 if (file != stderr ||
6185 r600_can_dump_shader(&sscreen->b, processor))
6186 si_dump_shader_key(processor, &shader->key, file);
6187
6188 if (file != stderr && shader->binary.llvm_ir_string) {
6189 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
6190 si_get_shader_name(shader, processor));
6191 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
6192 }
6193
6194 if (file != stderr ||
6195 (r600_can_dump_shader(&sscreen->b, processor) &&
6196 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6197 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6198
6199 if (shader->prolog)
6200 si_shader_dump_disassembly(&shader->prolog->binary,
6201 debug, "prolog", file);
6202
6203 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6204
6205 if (shader->epilog)
6206 si_shader_dump_disassembly(&shader->epilog->binary,
6207 debug, "epilog", file);
6208 fprintf(file, "\n");
6209 }
6210
6211 si_shader_dump_stats(sscreen, shader, debug, processor, file);
6212 }
6213
6214 int si_compile_llvm(struct si_screen *sscreen,
6215 struct radeon_shader_binary *binary,
6216 struct si_shader_config *conf,
6217 LLVMTargetMachineRef tm,
6218 LLVMModuleRef mod,
6219 struct pipe_debug_callback *debug,
6220 unsigned processor,
6221 const char *name)
6222 {
6223 int r = 0;
6224 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6225
6226 if (r600_can_dump_shader(&sscreen->b, processor)) {
6227 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6228
6229 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6230 fprintf(stderr, "%s LLVM IR:\n\n", name);
6231 LLVMDumpModule(mod);
6232 fprintf(stderr, "\n");
6233 }
6234 }
6235
6236 if (sscreen->record_llvm_ir) {
6237 char *ir = LLVMPrintModuleToString(mod);
6238 binary->llvm_ir_string = strdup(ir);
6239 LLVMDisposeMessage(ir);
6240 }
6241
6242 if (!si_replace_shader(count, binary)) {
6243 r = si_llvm_compile(mod, binary, tm, debug);
6244 if (r)
6245 return r;
6246 }
6247
6248 si_shader_binary_read_config(binary, conf, 0);
6249
6250 /* Enable 64-bit and 16-bit denormals, because there is no performance
6251 * cost.
6252 *
6253 * If denormals are enabled, all floating-point output modifiers are
6254 * ignored.
6255 *
6256 * Don't enable denormals for 32-bit floats, because:
6257 * - Floating-point output modifiers would be ignored by the hw.
6258 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6259 * have to stop using those.
6260 * - SI & CI would be very slow.
6261 */
6262 conf->float_mode |= V_00B028_FP_64_DENORMS;
6263
6264 FREE(binary->config);
6265 FREE(binary->global_symbol_offsets);
6266 binary->config = NULL;
6267 binary->global_symbol_offsets = NULL;
6268
6269 /* Some shaders can't have rodata because their binaries can be
6270 * concatenated.
6271 */
6272 if (binary->rodata_size &&
6273 (processor == PIPE_SHADER_VERTEX ||
6274 processor == PIPE_SHADER_TESS_CTRL ||
6275 processor == PIPE_SHADER_TESS_EVAL ||
6276 processor == PIPE_SHADER_FRAGMENT)) {
6277 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6278 return -EINVAL;
6279 }
6280
6281 return r;
6282 }
6283
6284 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6285 {
6286 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6287 LLVMBuildRetVoid(ctx->gallivm.builder);
6288 else
6289 LLVMBuildRet(ctx->gallivm.builder, ret);
6290 }
6291
6292 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6293 struct si_shader *
6294 si_generate_gs_copy_shader(struct si_screen *sscreen,
6295 LLVMTargetMachineRef tm,
6296 struct si_shader_selector *gs_selector,
6297 struct pipe_debug_callback *debug)
6298 {
6299 struct si_shader_context ctx;
6300 struct si_shader *shader;
6301 struct gallivm_state *gallivm = &ctx.gallivm;
6302 struct lp_build_tgsi_context *bld_base = &ctx.soa.bld_base;
6303 struct lp_build_context *uint = &bld_base->uint_bld;
6304 struct si_shader_output_values *outputs;
6305 struct tgsi_shader_info *gsinfo = &gs_selector->info;
6306 LLVMValueRef args[9];
6307 int i, r;
6308
6309 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6310
6311 if (!outputs)
6312 return NULL;
6313
6314 shader = CALLOC_STRUCT(si_shader);
6315 if (!shader) {
6316 FREE(outputs);
6317 return NULL;
6318 }
6319
6320
6321 shader->selector = gs_selector;
6322 shader->is_gs_copy_shader = true;
6323
6324 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6325 ctx.type = PIPE_SHADER_VERTEX;
6326
6327 create_meta_data(&ctx);
6328 create_function(&ctx);
6329 preload_ring_buffers(&ctx);
6330
6331 args[0] = ctx.gsvs_ring[0];
6332 args[1] = lp_build_mul_imm(uint,
6333 LLVMGetParam(ctx.main_fn,
6334 ctx.param_vertex_id),
6335 4);
6336 args[3] = uint->zero;
6337 args[4] = uint->one; /* OFFEN */
6338 args[5] = uint->zero; /* IDXEN */
6339 args[6] = uint->one; /* GLC */
6340 args[7] = uint->one; /* SLC */
6341 args[8] = uint->zero; /* TFE */
6342
6343 /* Fetch vertex data from GSVS ring */
6344 for (i = 0; i < gsinfo->num_outputs; ++i) {
6345 unsigned chan;
6346
6347 outputs[i].name = gsinfo->output_semantic_name[i];
6348 outputs[i].sid = gsinfo->output_semantic_index[i];
6349
6350 for (chan = 0; chan < 4; chan++) {
6351 args[2] = lp_build_const_int32(gallivm,
6352 (i * 4 + chan) *
6353 gs_selector->gs_max_out_vertices * 16 * 4);
6354
6355 outputs[i].values[chan] =
6356 LLVMBuildBitCast(gallivm->builder,
6357 lp_build_intrinsic(gallivm->builder,
6358 "llvm.SI.buffer.load.dword.i32.i32",
6359 ctx.i32, args, 9,
6360 LP_FUNC_ATTR_READONLY),
6361 ctx.f32, "");
6362 }
6363 }
6364
6365 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6366
6367 LLVMBuildRetVoid(gallivm->builder);
6368
6369 /* Dump LLVM IR before any optimization passes */
6370 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6371 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6372 LLVMDumpModule(bld_base->base.gallivm->module);
6373
6374 si_llvm_finalize_module(&ctx,
6375 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_GEOMETRY));
6376
6377 r = si_compile_llvm(sscreen, &ctx.shader->binary,
6378 &ctx.shader->config, ctx.tm,
6379 bld_base->base.gallivm->module,
6380 debug, PIPE_SHADER_GEOMETRY,
6381 "GS Copy Shader");
6382 if (!r) {
6383 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6384 fprintf(stderr, "GS Copy Shader:\n");
6385 si_shader_dump(sscreen, ctx.shader, debug,
6386 PIPE_SHADER_GEOMETRY, stderr);
6387 r = si_shader_binary_upload(sscreen, ctx.shader);
6388 }
6389
6390 si_llvm_dispose(&ctx);
6391
6392 FREE(outputs);
6393
6394 if (r != 0) {
6395 FREE(shader);
6396 shader = NULL;
6397 }
6398 return shader;
6399 }
6400
6401 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
6402 FILE *f)
6403 {
6404 int i;
6405
6406 fprintf(f, "SHADER KEY\n");
6407
6408 switch (shader) {
6409 case PIPE_SHADER_VERTEX:
6410 fprintf(f, " part.vs.prolog.instance_divisors = {");
6411 for (i = 0; i < ARRAY_SIZE(key->part.vs.prolog.instance_divisors); i++)
6412 fprintf(f, !i ? "%u" : ", %u",
6413 key->part.vs.prolog.instance_divisors[i]);
6414 fprintf(f, "}\n");
6415 fprintf(f, " part.vs.epilog.export_prim_id = %u\n", key->part.vs.epilog.export_prim_id);
6416 fprintf(f, " as_es = %u\n", key->as_es);
6417 fprintf(f, " as_ls = %u\n", key->as_ls);
6418 fprintf(f, " mono.vs.fix_fetch = 0x%x\n", key->mono.vs.fix_fetch);
6419 break;
6420
6421 case PIPE_SHADER_TESS_CTRL:
6422 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
6423 fprintf(f, " mono.tcs.inputs_to_copy = 0x%"PRIx64"\n", key->mono.tcs.inputs_to_copy);
6424 break;
6425
6426 case PIPE_SHADER_TESS_EVAL:
6427 fprintf(f, " part.tes.epilog.export_prim_id = %u\n", key->part.tes.epilog.export_prim_id);
6428 fprintf(f, " as_es = %u\n", key->as_es);
6429 break;
6430
6431 case PIPE_SHADER_GEOMETRY:
6432 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
6433 break;
6434
6435 case PIPE_SHADER_COMPUTE:
6436 break;
6437
6438 case PIPE_SHADER_FRAGMENT:
6439 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
6440 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
6441 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
6442 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
6443 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
6444 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
6445 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
6446 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
6447 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
6448 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
6449 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
6450 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
6451 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
6452 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
6453 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
6454 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
6455 break;
6456
6457 default:
6458 assert(0);
6459 }
6460
6461 if ((shader == PIPE_SHADER_GEOMETRY ||
6462 shader == PIPE_SHADER_TESS_EVAL ||
6463 shader == PIPE_SHADER_VERTEX) &&
6464 !key->as_es && !key->as_ls) {
6465 fprintf(f, " opt.hw_vs.kill_outputs = 0x%"PRIx64"\n", key->opt.hw_vs.kill_outputs);
6466 fprintf(f, " opt.hw_vs.kill_outputs2 = 0x%x\n", key->opt.hw_vs.kill_outputs2);
6467 fprintf(f, " opt.hw_vs.clip_disable = %u\n", key->opt.hw_vs.clip_disable);
6468 }
6469 }
6470
6471 static void si_init_shader_ctx(struct si_shader_context *ctx,
6472 struct si_screen *sscreen,
6473 struct si_shader *shader,
6474 LLVMTargetMachineRef tm)
6475 {
6476 struct lp_build_tgsi_context *bld_base;
6477 struct lp_build_tgsi_action tmpl = {};
6478
6479 si_llvm_context_init(ctx, sscreen, shader, tm,
6480 (shader && shader->selector) ? &shader->selector->info : NULL,
6481 (shader && shader->selector) ? shader->selector->tokens : NULL);
6482
6483 bld_base = &ctx->soa.bld_base;
6484 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6485
6486 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6487 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6488 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6489
6490 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6491 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6492 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6493 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6494 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6495 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6496 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6497 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6498 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6499 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6500 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6501 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6502 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6503 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6504
6505 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6506 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6507 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6508 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6509 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6510 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6511
6512 tmpl.fetch_args = atomic_fetch_args;
6513 tmpl.emit = atomic_emit;
6514 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6515 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6516 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6517 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6518 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6519 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6520 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6521 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6522 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6523 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6524 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6525 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6526 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6527 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6528 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6529 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6530 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6531 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6532 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6533 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6534
6535 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6536
6537 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6538 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6539 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6540 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6541
6542 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6543 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6544 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6545 }
6546
6547 /* Return true if the PARAM export has been eliminated. */
6548 static bool si_eliminate_const_output(struct si_shader_context *ctx,
6549 LLVMValueRef inst, unsigned offset)
6550 {
6551 struct si_shader *shader = ctx->shader;
6552 unsigned num_outputs = shader->selector->info.num_outputs;
6553 unsigned i, default_val; /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL */
6554 bool is_zero[4] = {}, is_one[4] = {};
6555
6556 for (i = 0; i < 4; i++) {
6557 LLVMBool loses_info;
6558 LLVMValueRef p = LLVMGetOperand(inst, 5 + i);
6559
6560 /* It's a constant expression. Undef outputs are eliminated too. */
6561 if (LLVMIsUndef(p)) {
6562 is_zero[i] = true;
6563 is_one[i] = true;
6564 } else if (LLVMIsAConstantFP(p)) {
6565 double a = LLVMConstRealGetDouble(p, &loses_info);
6566
6567 if (a == 0)
6568 is_zero[i] = true;
6569 else if (a == 1)
6570 is_one[i] = true;
6571 else
6572 return false; /* other constant */
6573 } else
6574 return false;
6575 }
6576
6577 /* Only certain combinations of 0 and 1 can be eliminated. */
6578 if (is_zero[0] && is_zero[1] && is_zero[2])
6579 default_val = is_zero[3] ? 0 : 1;
6580 else if (is_one[0] && is_one[1] && is_one[2])
6581 default_val = is_zero[3] ? 2 : 3;
6582 else
6583 return false;
6584
6585 /* The PARAM export can be represented as DEFAULT_VAL. Kill it. */
6586 LLVMInstructionEraseFromParent(inst);
6587
6588 /* Change OFFSET to DEFAULT_VAL. */
6589 for (i = 0; i < num_outputs; i++) {
6590 if (shader->info.vs_output_param_offset[i] == offset) {
6591 shader->info.vs_output_param_offset[i] =
6592 EXP_PARAM_DEFAULT_VAL_0000 + default_val;
6593 break;
6594 }
6595 }
6596 return true;
6597 }
6598
6599 struct si_vs_exports {
6600 unsigned num;
6601 unsigned offset[SI_MAX_VS_OUTPUTS];
6602 LLVMValueRef inst[SI_MAX_VS_OUTPUTS];
6603 };
6604
6605 static void si_eliminate_const_vs_outputs(struct si_shader_context *ctx)
6606 {
6607 struct si_shader *shader = ctx->shader;
6608 struct tgsi_shader_info *info = &shader->selector->info;
6609 LLVMBasicBlockRef bb;
6610 struct si_vs_exports exports;
6611 bool removed_any = false;
6612
6613 exports.num = 0;
6614
6615 if (ctx->type == PIPE_SHADER_FRAGMENT ||
6616 ctx->type == PIPE_SHADER_COMPUTE ||
6617 shader->key.as_es ||
6618 shader->key.as_ls)
6619 return;
6620
6621 /* Process all LLVM instructions. */
6622 bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6623 while (bb) {
6624 LLVMValueRef inst = LLVMGetFirstInstruction(bb);
6625
6626 while (inst) {
6627 LLVMValueRef cur = inst;
6628 inst = LLVMGetNextInstruction(inst);
6629
6630 if (LLVMGetInstructionOpcode(cur) != LLVMCall)
6631 continue;
6632
6633 LLVMValueRef callee = lp_get_called_value(cur);
6634
6635 if (!lp_is_function(callee))
6636 continue;
6637
6638 const char *name = LLVMGetValueName(callee);
6639 unsigned num_args = LLVMCountParams(callee);
6640
6641 /* Check if this is an export instruction. */
6642 if (num_args != 9 || strcmp(name, "llvm.SI.export"))
6643 continue;
6644
6645 LLVMValueRef arg = LLVMGetOperand(cur, 3);
6646 unsigned target = LLVMConstIntGetZExtValue(arg);
6647
6648 if (target < V_008DFC_SQ_EXP_PARAM)
6649 continue;
6650
6651 target -= V_008DFC_SQ_EXP_PARAM;
6652
6653 /* Eliminate constant value PARAM exports. */
6654 if (si_eliminate_const_output(ctx, cur, target)) {
6655 removed_any = true;
6656 } else {
6657 exports.offset[exports.num] = target;
6658 exports.inst[exports.num] = cur;
6659 exports.num++;
6660 }
6661 }
6662 bb = LLVMGetNextBasicBlock(bb);
6663 }
6664
6665 /* Remove holes in export memory due to removed PARAM exports.
6666 * This is done by renumbering all PARAM exports.
6667 */
6668 if (removed_any) {
6669 ubyte current_offset[SI_MAX_VS_OUTPUTS];
6670 unsigned new_count = 0;
6671 unsigned out, i;
6672
6673 /* Make a copy of the offsets. We need the old version while
6674 * we are modifying some of them. */
6675 assert(sizeof(current_offset) ==
6676 sizeof(shader->info.vs_output_param_offset));
6677 memcpy(current_offset, shader->info.vs_output_param_offset,
6678 sizeof(current_offset));
6679
6680 for (i = 0; i < exports.num; i++) {
6681 unsigned offset = exports.offset[i];
6682
6683 for (out = 0; out < info->num_outputs; out++) {
6684 if (current_offset[out] != offset)
6685 continue;
6686
6687 LLVMSetOperand(exports.inst[i], 3,
6688 LLVMConstInt(ctx->i32,
6689 V_008DFC_SQ_EXP_PARAM + new_count, 0));
6690 shader->info.vs_output_param_offset[out] = new_count;
6691 new_count++;
6692 break;
6693 }
6694 }
6695 shader->info.nr_param_exports = new_count;
6696 }
6697 }
6698
6699 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
6700 {
6701 ctx->shader->config.private_mem_vgprs = 0;
6702
6703 /* Process all LLVM instructions. */
6704 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6705 while (bb) {
6706 LLVMValueRef next = LLVMGetFirstInstruction(bb);
6707
6708 while (next) {
6709 LLVMValueRef inst = next;
6710 next = LLVMGetNextInstruction(next);
6711
6712 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
6713 continue;
6714
6715 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
6716 /* No idea why LLVM aligns allocas to 4 elements. */
6717 unsigned alignment = LLVMGetAlignment(inst);
6718 unsigned dw_size = align(llvm_get_type_size(type) / 4, alignment);
6719 ctx->shader->config.private_mem_vgprs += dw_size;
6720 }
6721 bb = LLVMGetNextBasicBlock(bb);
6722 }
6723 }
6724
6725 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
6726 struct si_shader *shader)
6727 {
6728 struct si_shader_selector *sel = shader->selector;
6729 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
6730
6731 switch (ctx->type) {
6732 case PIPE_SHADER_VERTEX:
6733 ctx->load_input = declare_input_vs;
6734 if (shader->key.as_ls)
6735 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6736 else if (shader->key.as_es)
6737 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6738 else
6739 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6740 break;
6741 case PIPE_SHADER_TESS_CTRL:
6742 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6743 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6744 bld_base->emit_store = store_output_tcs;
6745 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6746 break;
6747 case PIPE_SHADER_TESS_EVAL:
6748 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6749 if (shader->key.as_es)
6750 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6751 else
6752 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6753 break;
6754 case PIPE_SHADER_GEOMETRY:
6755 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6756 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6757 break;
6758 case PIPE_SHADER_FRAGMENT:
6759 ctx->load_input = declare_input_fs;
6760 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6761 break;
6762 case PIPE_SHADER_COMPUTE:
6763 ctx->declare_memory_region = declare_compute_memory;
6764 break;
6765 default:
6766 assert(!"Unsupported shader type");
6767 return false;
6768 }
6769
6770 create_meta_data(ctx);
6771 create_function(ctx);
6772 preload_ring_buffers(ctx);
6773
6774 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6775 int i;
6776 for (i = 0; i < 4; i++) {
6777 ctx->gs_next_vertex[i] =
6778 lp_build_alloca(bld_base->base.gallivm,
6779 ctx->i32, "");
6780 }
6781 }
6782
6783 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6784 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6785 return false;
6786 }
6787
6788 si_llvm_build_ret(ctx, ctx->return_value);
6789 return true;
6790 }
6791
6792 /**
6793 * Compute the VS prolog key, which contains all the information needed to
6794 * build the VS prolog function, and set shader->info bits where needed.
6795 */
6796 static void si_get_vs_prolog_key(struct si_shader *shader,
6797 union si_shader_part_key *key)
6798 {
6799 struct tgsi_shader_info *info = &shader->selector->info;
6800
6801 memset(key, 0, sizeof(*key));
6802 key->vs_prolog.states = shader->key.part.vs.prolog;
6803 key->vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6804 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6805
6806 /* Set the instanceID flag. */
6807 for (unsigned i = 0; i < info->num_inputs; i++)
6808 if (key->vs_prolog.states.instance_divisors[i])
6809 shader->info.uses_instanceid = true;
6810 }
6811
6812 /**
6813 * Compute the VS epilog key, which contains all the information needed to
6814 * build the VS epilog function, and set the PrimitiveID output offset.
6815 */
6816 static void si_get_vs_epilog_key(struct si_shader *shader,
6817 struct si_vs_epilog_bits *states,
6818 union si_shader_part_key *key)
6819 {
6820 memset(key, 0, sizeof(*key));
6821 key->vs_epilog.states = *states;
6822
6823 /* Set up the PrimitiveID output. */
6824 if (shader->key.part.vs.epilog.export_prim_id) {
6825 unsigned index = shader->selector->info.num_outputs;
6826 unsigned offset = shader->info.nr_param_exports++;
6827
6828 key->vs_epilog.prim_id_param_offset = offset;
6829 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
6830 shader->info.vs_output_param_offset[index] = offset;
6831 }
6832 }
6833
6834 /**
6835 * Compute the PS prolog key, which contains all the information needed to
6836 * build the PS prolog function, and set related bits in shader->config.
6837 */
6838 static void si_get_ps_prolog_key(struct si_shader *shader,
6839 union si_shader_part_key *key,
6840 bool separate_prolog)
6841 {
6842 struct tgsi_shader_info *info = &shader->selector->info;
6843
6844 memset(key, 0, sizeof(*key));
6845 key->ps_prolog.states = shader->key.part.ps.prolog;
6846 key->ps_prolog.colors_read = info->colors_read;
6847 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6848 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6849 key->ps_prolog.wqm = info->uses_derivatives &&
6850 (key->ps_prolog.colors_read ||
6851 key->ps_prolog.states.force_persp_sample_interp ||
6852 key->ps_prolog.states.force_linear_sample_interp ||
6853 key->ps_prolog.states.force_persp_center_interp ||
6854 key->ps_prolog.states.force_linear_center_interp ||
6855 key->ps_prolog.states.bc_optimize_for_persp ||
6856 key->ps_prolog.states.bc_optimize_for_linear);
6857
6858 if (info->colors_read) {
6859 unsigned *color = shader->selector->color_attr_index;
6860
6861 if (shader->key.part.ps.prolog.color_two_side) {
6862 /* BCOLORs are stored after the last input. */
6863 key->ps_prolog.num_interp_inputs = info->num_inputs;
6864 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6865 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6866 }
6867
6868 for (unsigned i = 0; i < 2; i++) {
6869 unsigned interp = info->input_interpolate[color[i]];
6870 unsigned location = info->input_interpolate_loc[color[i]];
6871
6872 if (!(info->colors_read & (0xf << i*4)))
6873 continue;
6874
6875 key->ps_prolog.color_attr_index[i] = color[i];
6876
6877 if (shader->key.part.ps.prolog.flatshade_colors &&
6878 interp == TGSI_INTERPOLATE_COLOR)
6879 interp = TGSI_INTERPOLATE_CONSTANT;
6880
6881 switch (interp) {
6882 case TGSI_INTERPOLATE_CONSTANT:
6883 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6884 break;
6885 case TGSI_INTERPOLATE_PERSPECTIVE:
6886 case TGSI_INTERPOLATE_COLOR:
6887 /* Force the interpolation location for colors here. */
6888 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6889 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6890 if (shader->key.part.ps.prolog.force_persp_center_interp)
6891 location = TGSI_INTERPOLATE_LOC_CENTER;
6892
6893 switch (location) {
6894 case TGSI_INTERPOLATE_LOC_SAMPLE:
6895 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6896 shader->config.spi_ps_input_ena |=
6897 S_0286CC_PERSP_SAMPLE_ENA(1);
6898 break;
6899 case TGSI_INTERPOLATE_LOC_CENTER:
6900 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6901 shader->config.spi_ps_input_ena |=
6902 S_0286CC_PERSP_CENTER_ENA(1);
6903 break;
6904 case TGSI_INTERPOLATE_LOC_CENTROID:
6905 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6906 shader->config.spi_ps_input_ena |=
6907 S_0286CC_PERSP_CENTROID_ENA(1);
6908 break;
6909 default:
6910 assert(0);
6911 }
6912 break;
6913 case TGSI_INTERPOLATE_LINEAR:
6914 /* Force the interpolation location for colors here. */
6915 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6916 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6917 if (shader->key.part.ps.prolog.force_linear_center_interp)
6918 location = TGSI_INTERPOLATE_LOC_CENTER;
6919
6920 /* The VGPR assignment for non-monolithic shaders
6921 * works because InitialPSInputAddr is set on the
6922 * main shader and PERSP_PULL_MODEL is never used.
6923 */
6924 switch (location) {
6925 case TGSI_INTERPOLATE_LOC_SAMPLE:
6926 key->ps_prolog.color_interp_vgpr_index[i] =
6927 separate_prolog ? 6 : 9;
6928 shader->config.spi_ps_input_ena |=
6929 S_0286CC_LINEAR_SAMPLE_ENA(1);
6930 break;
6931 case TGSI_INTERPOLATE_LOC_CENTER:
6932 key->ps_prolog.color_interp_vgpr_index[i] =
6933 separate_prolog ? 8 : 11;
6934 shader->config.spi_ps_input_ena |=
6935 S_0286CC_LINEAR_CENTER_ENA(1);
6936 break;
6937 case TGSI_INTERPOLATE_LOC_CENTROID:
6938 key->ps_prolog.color_interp_vgpr_index[i] =
6939 separate_prolog ? 10 : 13;
6940 shader->config.spi_ps_input_ena |=
6941 S_0286CC_LINEAR_CENTROID_ENA(1);
6942 break;
6943 default:
6944 assert(0);
6945 }
6946 break;
6947 default:
6948 assert(0);
6949 }
6950 }
6951 }
6952 }
6953
6954 /**
6955 * Check whether a PS prolog is required based on the key.
6956 */
6957 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6958 {
6959 return key->ps_prolog.colors_read ||
6960 key->ps_prolog.states.force_persp_sample_interp ||
6961 key->ps_prolog.states.force_linear_sample_interp ||
6962 key->ps_prolog.states.force_persp_center_interp ||
6963 key->ps_prolog.states.force_linear_center_interp ||
6964 key->ps_prolog.states.bc_optimize_for_persp ||
6965 key->ps_prolog.states.bc_optimize_for_linear ||
6966 key->ps_prolog.states.poly_stipple;
6967 }
6968
6969 /**
6970 * Compute the PS epilog key, which contains all the information needed to
6971 * build the PS epilog function.
6972 */
6973 static void si_get_ps_epilog_key(struct si_shader *shader,
6974 union si_shader_part_key *key)
6975 {
6976 struct tgsi_shader_info *info = &shader->selector->info;
6977 memset(key, 0, sizeof(*key));
6978 key->ps_epilog.colors_written = info->colors_written;
6979 key->ps_epilog.writes_z = info->writes_z;
6980 key->ps_epilog.writes_stencil = info->writes_stencil;
6981 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6982 key->ps_epilog.states = shader->key.part.ps.epilog;
6983 }
6984
6985 /**
6986 * Build the GS prolog function. Rotate the input vertices for triangle strips
6987 * with adjacency.
6988 */
6989 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6990 union si_shader_part_key *key)
6991 {
6992 const unsigned num_sgprs = SI_GS_NUM_USER_SGPR + 2;
6993 const unsigned num_vgprs = 8;
6994 struct gallivm_state *gallivm = &ctx->gallivm;
6995 LLVMBuilderRef builder = gallivm->builder;
6996 LLVMTypeRef params[32];
6997 LLVMTypeRef returns[32];
6998 LLVMValueRef func, ret;
6999
7000 for (unsigned i = 0; i < num_sgprs; ++i) {
7001 params[i] = ctx->i32;
7002 returns[i] = ctx->i32;
7003 }
7004
7005 for (unsigned i = 0; i < num_vgprs; ++i) {
7006 params[num_sgprs + i] = ctx->i32;
7007 returns[num_sgprs + i] = ctx->f32;
7008 }
7009
7010 /* Create the function. */
7011 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
7012 params, num_sgprs + num_vgprs, num_sgprs - 1);
7013 func = ctx->main_fn;
7014
7015 /* Copy inputs to outputs. This should be no-op, as the registers match,
7016 * but it will prevent the compiler from overwriting them unintentionally.
7017 */
7018 ret = ctx->return_value;
7019 for (unsigned i = 0; i < num_sgprs; i++) {
7020 LLVMValueRef p = LLVMGetParam(func, i);
7021 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
7022 }
7023 for (unsigned i = 0; i < num_vgprs; i++) {
7024 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
7025 p = LLVMBuildBitCast(builder, p, ctx->f32, "");
7026 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
7027 }
7028
7029 if (key->gs_prolog.states.tri_strip_adj_fix) {
7030 /* Remap the input vertices for every other primitive. */
7031 const unsigned vtx_params[6] = {
7032 num_sgprs,
7033 num_sgprs + 1,
7034 num_sgprs + 3,
7035 num_sgprs + 4,
7036 num_sgprs + 5,
7037 num_sgprs + 6
7038 };
7039 LLVMValueRef prim_id, rotate;
7040
7041 prim_id = LLVMGetParam(func, num_sgprs + 2);
7042 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
7043
7044 for (unsigned i = 0; i < 6; ++i) {
7045 LLVMValueRef base, rotated, actual;
7046 base = LLVMGetParam(func, vtx_params[i]);
7047 rotated = LLVMGetParam(func, vtx_params[(i + 4) % 6]);
7048 actual = LLVMBuildSelect(builder, rotate, rotated, base, "");
7049 actual = LLVMBuildBitCast(builder, actual, ctx->f32, "");
7050 ret = LLVMBuildInsertValue(builder, ret, actual, vtx_params[i], "");
7051 }
7052 }
7053
7054 LLVMBuildRet(builder, ret);
7055 }
7056
7057 /**
7058 * Given a list of shader part functions, build a wrapper function that
7059 * runs them in sequence to form a monolithic shader.
7060 */
7061 static void si_build_wrapper_function(struct si_shader_context *ctx,
7062 LLVMValueRef *parts,
7063 unsigned num_parts,
7064 unsigned main_part)
7065 {
7066 struct gallivm_state *gallivm = &ctx->gallivm;
7067 LLVMBuilderRef builder = ctx->gallivm.builder;
7068 /* PS epilog has one arg per color component */
7069 LLVMTypeRef param_types[48];
7070 LLVMValueRef out[48];
7071 LLVMTypeRef function_type;
7072 unsigned num_params;
7073 unsigned num_out;
7074 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
7075 unsigned num_sgprs, num_vgprs;
7076 unsigned last_sgpr_param;
7077 unsigned gprs;
7078
7079 for (unsigned i = 0; i < num_parts; ++i) {
7080 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
7081 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
7082 }
7083
7084 /* The parameters of the wrapper function correspond to those of the
7085 * first part in terms of SGPRs and VGPRs, but we use the types of the
7086 * main part to get the right types. This is relevant for the
7087 * dereferenceable attribute on descriptor table pointers.
7088 */
7089 num_sgprs = 0;
7090 num_vgprs = 0;
7091
7092 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
7093 num_params = LLVMCountParamTypes(function_type);
7094
7095 for (unsigned i = 0; i < num_params; ++i) {
7096 LLVMValueRef param = LLVMGetParam(parts[0], i);
7097
7098 if (ac_is_sgpr_param(param)) {
7099 assert(num_vgprs == 0);
7100 num_sgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
7101 } else {
7102 num_vgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
7103 }
7104 }
7105 assert(num_vgprs + num_sgprs <= ARRAY_SIZE(param_types));
7106
7107 num_params = 0;
7108 last_sgpr_param = 0;
7109 gprs = 0;
7110 while (gprs < num_sgprs + num_vgprs) {
7111 LLVMValueRef param = LLVMGetParam(parts[main_part], num_params);
7112 unsigned size;
7113
7114 param_types[num_params] = LLVMTypeOf(param);
7115 if (gprs < num_sgprs)
7116 last_sgpr_param = num_params;
7117 size = llvm_get_type_size(param_types[num_params]) / 4;
7118 num_params++;
7119
7120 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
7121 assert(gprs + size <= num_sgprs + num_vgprs &&
7122 (gprs >= num_sgprs || gprs + size <= num_sgprs));
7123
7124 gprs += size;
7125 }
7126
7127 si_create_function(ctx, "wrapper", NULL, 0, param_types, num_params, last_sgpr_param);
7128
7129 /* Record the arguments of the function as if they were an output of
7130 * a previous part.
7131 */
7132 num_out = 0;
7133 num_out_sgpr = 0;
7134
7135 for (unsigned i = 0; i < num_params; ++i) {
7136 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
7137 LLVMTypeRef param_type = LLVMTypeOf(param);
7138 LLVMTypeRef out_type = i <= last_sgpr_param ? ctx->i32 : ctx->f32;
7139 unsigned size = llvm_get_type_size(param_type) / 4;
7140
7141 if (size == 1) {
7142 if (param_type != out_type)
7143 param = LLVMBuildBitCast(builder, param, out_type, "");
7144 out[num_out++] = param;
7145 } else {
7146 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
7147
7148 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7149 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
7150 param_type = ctx->i64;
7151 }
7152
7153 if (param_type != vector_type)
7154 param = LLVMBuildBitCast(builder, param, vector_type, "");
7155
7156 for (unsigned j = 0; j < size; ++j)
7157 out[num_out++] = LLVMBuildExtractElement(
7158 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
7159 }
7160
7161 if (i <= last_sgpr_param)
7162 num_out_sgpr = num_out;
7163 }
7164
7165 /* Now chain the parts. */
7166 for (unsigned part = 0; part < num_parts; ++part) {
7167 LLVMValueRef in[48];
7168 LLVMValueRef ret;
7169 LLVMTypeRef ret_type;
7170 unsigned out_idx = 0;
7171
7172 num_params = LLVMCountParams(parts[part]);
7173 assert(num_params <= ARRAY_SIZE(param_types));
7174
7175 /* Derive arguments for the next part from outputs of the
7176 * previous one.
7177 */
7178 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
7179 LLVMValueRef param;
7180 LLVMTypeRef param_type;
7181 bool is_sgpr;
7182 unsigned param_size;
7183 LLVMValueRef arg = NULL;
7184
7185 param = LLVMGetParam(parts[part], param_idx);
7186 param_type = LLVMTypeOf(param);
7187 param_size = llvm_get_type_size(param_type) / 4;
7188 is_sgpr = ac_is_sgpr_param(param);
7189
7190 if (is_sgpr) {
7191 #if HAVE_LLVM < 0x0400
7192 LLVMRemoveAttribute(param, LLVMByValAttribute);
7193 #else
7194 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
7195 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
7196 #endif
7197 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
7198 }
7199
7200 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
7201 assert(is_sgpr || out_idx >= num_out_sgpr);
7202
7203 if (param_size == 1)
7204 arg = out[out_idx];
7205 else
7206 arg = lp_build_gather_values(gallivm, &out[out_idx], param_size);
7207
7208 if (LLVMTypeOf(arg) != param_type) {
7209 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7210 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
7211 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
7212 } else {
7213 arg = LLVMBuildBitCast(builder, arg, param_type, "");
7214 }
7215 }
7216
7217 in[param_idx] = arg;
7218 out_idx += param_size;
7219 }
7220
7221 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
7222 ret_type = LLVMTypeOf(ret);
7223
7224 /* Extract the returned GPRs. */
7225 num_out = 0;
7226 num_out_sgpr = 0;
7227
7228 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
7229 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
7230
7231 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
7232
7233 for (unsigned i = 0; i < ret_size; ++i) {
7234 LLVMValueRef val =
7235 LLVMBuildExtractValue(builder, ret, i, "");
7236
7237 out[num_out++] = val;
7238
7239 if (LLVMTypeOf(val) == ctx->i32) {
7240 assert(num_out_sgpr + 1 == num_out);
7241 num_out_sgpr = num_out;
7242 }
7243 }
7244 }
7245 }
7246
7247 LLVMBuildRetVoid(builder);
7248 }
7249
7250 int si_compile_tgsi_shader(struct si_screen *sscreen,
7251 LLVMTargetMachineRef tm,
7252 struct si_shader *shader,
7253 bool is_monolithic,
7254 struct pipe_debug_callback *debug)
7255 {
7256 struct si_shader_selector *sel = shader->selector;
7257 struct si_shader_context ctx;
7258 struct lp_build_tgsi_context *bld_base;
7259 LLVMModuleRef mod;
7260 int r = -1;
7261
7262 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
7263 * conversion fails. */
7264 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
7265 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
7266 tgsi_dump(sel->tokens, 0);
7267 si_dump_streamout(&sel->so);
7268 }
7269
7270 si_init_shader_ctx(&ctx, sscreen, shader, tm);
7271 ctx.separate_prolog = !is_monolithic;
7272
7273 memset(shader->info.vs_output_param_offset, EXP_PARAM_UNDEFINED,
7274 sizeof(shader->info.vs_output_param_offset));
7275
7276 shader->info.uses_instanceid = sel->info.uses_instanceid;
7277
7278 bld_base = &ctx.soa.bld_base;
7279 ctx.load_system_value = declare_system_value;
7280
7281 if (!si_compile_tgsi_main(&ctx, shader)) {
7282 si_llvm_dispose(&ctx);
7283 return -1;
7284 }
7285
7286 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
7287 LLVMValueRef parts[3];
7288 bool need_prolog;
7289 bool need_epilog;
7290
7291 need_prolog = sel->info.num_inputs;
7292 need_epilog = !shader->key.as_es && !shader->key.as_ls;
7293
7294 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7295
7296 if (need_prolog) {
7297 union si_shader_part_key prolog_key;
7298 si_get_vs_prolog_key(shader, &prolog_key);
7299 si_build_vs_prolog_function(&ctx, &prolog_key);
7300 parts[0] = ctx.main_fn;
7301 }
7302
7303 if (need_epilog) {
7304 union si_shader_part_key epilog_key;
7305 si_get_vs_epilog_key(shader, &shader->key.part.vs.epilog, &epilog_key);
7306 si_build_vs_epilog_function(&ctx, &epilog_key);
7307 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7308 }
7309
7310 si_build_wrapper_function(&ctx, parts, 1 + need_prolog + need_epilog,
7311 need_prolog ? 1 : 0);
7312 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
7313 LLVMValueRef parts[2];
7314 union si_shader_part_key epilog_key;
7315
7316 parts[0] = ctx.main_fn;
7317
7318 memset(&epilog_key, 0, sizeof(epilog_key));
7319 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7320 si_build_tcs_epilog_function(&ctx, &epilog_key);
7321 parts[1] = ctx.main_fn;
7322
7323 si_build_wrapper_function(&ctx, parts, 2, 0);
7324 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_EVAL &&
7325 !shader->key.as_es) {
7326 LLVMValueRef parts[2];
7327 union si_shader_part_key epilog_key;
7328
7329 parts[0] = ctx.main_fn;
7330
7331 si_get_vs_epilog_key(shader, &shader->key.part.tes.epilog, &epilog_key);
7332 si_build_vs_epilog_function(&ctx, &epilog_key);
7333 parts[1] = ctx.main_fn;
7334
7335 si_build_wrapper_function(&ctx, parts, 2, 0);
7336 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
7337 LLVMValueRef parts[2];
7338 union si_shader_part_key prolog_key;
7339
7340 parts[1] = ctx.main_fn;
7341
7342 memset(&prolog_key, 0, sizeof(prolog_key));
7343 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7344 si_build_gs_prolog_function(&ctx, &prolog_key);
7345 parts[0] = ctx.main_fn;
7346
7347 si_build_wrapper_function(&ctx, parts, 2, 1);
7348 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
7349 LLVMValueRef parts[3];
7350 union si_shader_part_key prolog_key;
7351 union si_shader_part_key epilog_key;
7352 bool need_prolog;
7353
7354 si_get_ps_prolog_key(shader, &prolog_key, false);
7355 need_prolog = si_need_ps_prolog(&prolog_key);
7356
7357 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7358
7359 if (need_prolog) {
7360 si_build_ps_prolog_function(&ctx, &prolog_key);
7361 parts[0] = ctx.main_fn;
7362 }
7363
7364 si_get_ps_epilog_key(shader, &epilog_key);
7365 si_build_ps_epilog_function(&ctx, &epilog_key);
7366 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7367
7368 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2, need_prolog ? 1 : 0);
7369 }
7370
7371 mod = bld_base->base.gallivm->module;
7372
7373 /* Dump LLVM IR before any optimization passes */
7374 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
7375 r600_can_dump_shader(&sscreen->b, ctx.type))
7376 LLVMDumpModule(mod);
7377
7378 si_llvm_finalize_module(&ctx,
7379 r600_extra_shader_checks(&sscreen->b, ctx.type));
7380
7381 /* Post-optimization transformations and analysis. */
7382 si_eliminate_const_vs_outputs(&ctx);
7383
7384 if ((debug && debug->debug_message) ||
7385 r600_can_dump_shader(&sscreen->b, ctx.type))
7386 si_count_scratch_private_memory(&ctx);
7387
7388 /* Compile to bytecode. */
7389 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
7390 mod, debug, ctx.type, "TGSI shader");
7391 si_llvm_dispose(&ctx);
7392 if (r) {
7393 fprintf(stderr, "LLVM failed to compile shader\n");
7394 return r;
7395 }
7396
7397 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
7398 * LLVM 3.9svn has this bug.
7399 */
7400 if (sel->type == PIPE_SHADER_COMPUTE) {
7401 unsigned wave_size = 64;
7402 unsigned max_vgprs = 256;
7403 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
7404 unsigned max_sgprs_per_wave = 128;
7405 unsigned max_block_threads = si_get_max_workgroup_size(shader);
7406 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
7407 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
7408
7409 max_vgprs = max_vgprs / min_waves_per_simd;
7410 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
7411
7412 if (shader->config.num_sgprs > max_sgprs ||
7413 shader->config.num_vgprs > max_vgprs) {
7414 fprintf(stderr, "LLVM failed to compile a shader correctly: "
7415 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7416 shader->config.num_sgprs, shader->config.num_vgprs,
7417 max_sgprs, max_vgprs);
7418
7419 /* Just terminate the process, because dependent
7420 * shaders can hang due to bad input data, but use
7421 * the env var to allow shader-db to work.
7422 */
7423 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7424 abort();
7425 }
7426 }
7427
7428 /* Add the scratch offset to input SGPRs. */
7429 if (shader->config.scratch_bytes_per_wave)
7430 shader->info.num_input_sgprs += 1; /* scratch byte offset */
7431
7432 /* Calculate the number of fragment input VGPRs. */
7433 if (ctx.type == PIPE_SHADER_FRAGMENT) {
7434 shader->info.num_input_vgprs = 0;
7435 shader->info.face_vgpr_index = -1;
7436
7437 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7438 shader->info.num_input_vgprs += 2;
7439 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
7440 shader->info.num_input_vgprs += 2;
7441 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
7442 shader->info.num_input_vgprs += 2;
7443 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
7444 shader->info.num_input_vgprs += 3;
7445 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7446 shader->info.num_input_vgprs += 2;
7447 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7448 shader->info.num_input_vgprs += 2;
7449 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7450 shader->info.num_input_vgprs += 2;
7451 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7452 shader->info.num_input_vgprs += 1;
7453 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7454 shader->info.num_input_vgprs += 1;
7455 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7456 shader->info.num_input_vgprs += 1;
7457 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7458 shader->info.num_input_vgprs += 1;
7459 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7460 shader->info.num_input_vgprs += 1;
7461 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7462 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7463 shader->info.num_input_vgprs += 1;
7464 }
7465 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
7466 shader->info.num_input_vgprs += 1;
7467 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7468 shader->info.num_input_vgprs += 1;
7469 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7470 shader->info.num_input_vgprs += 1;
7471 }
7472
7473 return 0;
7474 }
7475
7476 /**
7477 * Create, compile and return a shader part (prolog or epilog).
7478 *
7479 * \param sscreen screen
7480 * \param list list of shader parts of the same category
7481 * \param type shader type
7482 * \param key shader part key
7483 * \param prolog whether the part being requested is a prolog
7484 * \param tm LLVM target machine
7485 * \param debug debug callback
7486 * \param build the callback responsible for building the main function
7487 * \return non-NULL on success
7488 */
7489 static struct si_shader_part *
7490 si_get_shader_part(struct si_screen *sscreen,
7491 struct si_shader_part **list,
7492 enum pipe_shader_type type,
7493 bool prolog,
7494 union si_shader_part_key *key,
7495 LLVMTargetMachineRef tm,
7496 struct pipe_debug_callback *debug,
7497 void (*build)(struct si_shader_context *,
7498 union si_shader_part_key *),
7499 const char *name)
7500 {
7501 struct si_shader_part *result;
7502
7503 pipe_mutex_lock(sscreen->shader_parts_mutex);
7504
7505 /* Find existing. */
7506 for (result = *list; result; result = result->next) {
7507 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7508 pipe_mutex_unlock(sscreen->shader_parts_mutex);
7509 return result;
7510 }
7511 }
7512
7513 /* Compile a new one. */
7514 result = CALLOC_STRUCT(si_shader_part);
7515 result->key = *key;
7516
7517 struct si_shader shader = {};
7518 struct si_shader_context ctx;
7519 struct gallivm_state *gallivm = &ctx.gallivm;
7520
7521 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7522 ctx.type = type;
7523
7524 switch (type) {
7525 case PIPE_SHADER_VERTEX:
7526 break;
7527 case PIPE_SHADER_TESS_CTRL:
7528 assert(!prolog);
7529 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7530 break;
7531 case PIPE_SHADER_GEOMETRY:
7532 assert(prolog);
7533 break;
7534 case PIPE_SHADER_FRAGMENT:
7535 if (prolog)
7536 shader.key.part.ps.prolog = key->ps_prolog.states;
7537 else
7538 shader.key.part.ps.epilog = key->ps_epilog.states;
7539 break;
7540 default:
7541 unreachable("bad shader part");
7542 }
7543
7544 build(&ctx, key);
7545
7546 /* Compile. */
7547 si_llvm_finalize_module(&ctx,
7548 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT));
7549
7550 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7551 gallivm->module, debug, ctx.type, name)) {
7552 FREE(result);
7553 result = NULL;
7554 goto out;
7555 }
7556
7557 result->next = *list;
7558 *list = result;
7559
7560 out:
7561 si_llvm_dispose(&ctx);
7562 pipe_mutex_unlock(sscreen->shader_parts_mutex);
7563 return result;
7564 }
7565
7566 /**
7567 * Build the vertex shader prolog function.
7568 *
7569 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7570 * All inputs are returned unmodified. The vertex load indices are
7571 * stored after them, which will be used by the API VS for fetching inputs.
7572 *
7573 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7574 * input_v0,
7575 * input_v1,
7576 * input_v2,
7577 * input_v3,
7578 * (VertexID + BaseVertex),
7579 * (InstanceID + StartInstance),
7580 * (InstanceID / 2 + StartInstance)
7581 */
7582 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7583 union si_shader_part_key *key)
7584 {
7585 struct gallivm_state *gallivm = &ctx->gallivm;
7586 LLVMTypeRef *params, *returns;
7587 LLVMValueRef ret, func;
7588 int last_sgpr, num_params, num_returns, i;
7589
7590 ctx->param_vertex_id = key->vs_prolog.num_input_sgprs;
7591 ctx->param_instance_id = key->vs_prolog.num_input_sgprs + 3;
7592
7593 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7594 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
7595 sizeof(LLVMTypeRef));
7596 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
7597 key->vs_prolog.last_input + 1) *
7598 sizeof(LLVMTypeRef));
7599 num_params = 0;
7600 num_returns = 0;
7601
7602 /* Declare input and output SGPRs. */
7603 num_params = 0;
7604 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7605 params[num_params++] = ctx->i32;
7606 returns[num_returns++] = ctx->i32;
7607 }
7608 last_sgpr = num_params - 1;
7609
7610 /* 4 preloaded VGPRs (outputs must be floats) */
7611 for (i = 0; i < 4; i++) {
7612 params[num_params++] = ctx->i32;
7613 returns[num_returns++] = ctx->f32;
7614 }
7615
7616 /* Vertex load indices. */
7617 for (i = 0; i <= key->vs_prolog.last_input; i++)
7618 returns[num_returns++] = ctx->f32;
7619
7620 /* Create the function. */
7621 si_create_function(ctx, "vs_prolog", returns, num_returns, params,
7622 num_params, last_sgpr);
7623 func = ctx->main_fn;
7624
7625 /* Copy inputs to outputs. This should be no-op, as the registers match,
7626 * but it will prevent the compiler from overwriting them unintentionally.
7627 */
7628 ret = ctx->return_value;
7629 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7630 LLVMValueRef p = LLVMGetParam(func, i);
7631 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7632 }
7633 for (i = num_params - 4; i < num_params; i++) {
7634 LLVMValueRef p = LLVMGetParam(func, i);
7635 p = LLVMBuildBitCast(gallivm->builder, p, ctx->f32, "");
7636 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7637 }
7638
7639 /* Compute vertex load indices from instance divisors. */
7640 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7641 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
7642 LLVMValueRef index;
7643
7644 if (divisor) {
7645 /* InstanceID / Divisor + StartInstance */
7646 index = get_instance_index_for_fetch(ctx,
7647 SI_SGPR_START_INSTANCE,
7648 divisor);
7649 } else {
7650 /* VertexID + BaseVertex */
7651 index = LLVMBuildAdd(gallivm->builder,
7652 LLVMGetParam(func, ctx->param_vertex_id),
7653 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
7654 }
7655
7656 index = LLVMBuildBitCast(gallivm->builder, index, ctx->f32, "");
7657 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
7658 num_params++, "");
7659 }
7660
7661 si_llvm_build_ret(ctx, ret);
7662 }
7663
7664 /**
7665 * Build the vertex shader epilog function. This is also used by the tessellation
7666 * evaluation shader compiled as VS.
7667 *
7668 * The input is PrimitiveID.
7669 *
7670 * If PrimitiveID is required by the pixel shader, export it.
7671 * Otherwise, do nothing.
7672 */
7673 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
7674 union si_shader_part_key *key)
7675 {
7676 struct gallivm_state *gallivm = &ctx->gallivm;
7677 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
7678 LLVMTypeRef params[5];
7679 int num_params, i;
7680
7681 /* Declare input VGPRs. */
7682 num_params = key->vs_epilog.states.export_prim_id ?
7683 (VS_EPILOG_PRIMID_LOC + 1) : 0;
7684 assert(num_params <= ARRAY_SIZE(params));
7685
7686 for (i = 0; i < num_params; i++)
7687 params[i] = ctx->f32;
7688
7689 /* Create the function. */
7690 si_create_function(ctx, "vs_epilog", NULL, 0, params, num_params, -1);
7691
7692 /* Emit exports. */
7693 if (key->vs_epilog.states.export_prim_id) {
7694 struct lp_build_context *base = &bld_base->base;
7695 struct lp_build_context *uint = &bld_base->uint_bld;
7696 LLVMValueRef args[9];
7697
7698 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
7699 args[1] = uint->zero; /* whether the EXEC mask is valid */
7700 args[2] = uint->zero; /* DONE bit */
7701 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
7702 key->vs_epilog.prim_id_param_offset);
7703 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
7704 args[5] = LLVMGetParam(ctx->main_fn,
7705 VS_EPILOG_PRIMID_LOC); /* X */
7706 args[6] = base->undef; /* Y */
7707 args[7] = base->undef; /* Z */
7708 args[8] = base->undef; /* W */
7709
7710 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
7711 LLVMVoidTypeInContext(base->gallivm->context),
7712 args, 9, 0);
7713 }
7714
7715 LLVMBuildRetVoid(gallivm->builder);
7716 }
7717
7718 /**
7719 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7720 */
7721 static bool si_get_vs_epilog(struct si_screen *sscreen,
7722 LLVMTargetMachineRef tm,
7723 struct si_shader *shader,
7724 struct pipe_debug_callback *debug,
7725 struct si_vs_epilog_bits *states)
7726 {
7727 union si_shader_part_key epilog_key;
7728
7729 si_get_vs_epilog_key(shader, states, &epilog_key);
7730
7731 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
7732 PIPE_SHADER_VERTEX, true,
7733 &epilog_key, tm, debug,
7734 si_build_vs_epilog_function,
7735 "Vertex Shader Epilog");
7736 return shader->epilog != NULL;
7737 }
7738
7739 /**
7740 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7741 */
7742 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7743 LLVMTargetMachineRef tm,
7744 struct si_shader *shader,
7745 struct pipe_debug_callback *debug)
7746 {
7747 struct tgsi_shader_info *info = &shader->selector->info;
7748 union si_shader_part_key prolog_key;
7749
7750 /* Get the prolog. */
7751 si_get_vs_prolog_key(shader, &prolog_key);
7752
7753 /* The prolog is a no-op if there are no inputs. */
7754 if (info->num_inputs) {
7755 shader->prolog =
7756 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7757 PIPE_SHADER_VERTEX, true,
7758 &prolog_key, tm, debug,
7759 si_build_vs_prolog_function,
7760 "Vertex Shader Prolog");
7761 if (!shader->prolog)
7762 return false;
7763 }
7764
7765 /* Get the epilog. */
7766 if (!shader->key.as_es && !shader->key.as_ls &&
7767 !si_get_vs_epilog(sscreen, tm, shader, debug,
7768 &shader->key.part.vs.epilog))
7769 return false;
7770
7771 return true;
7772 }
7773
7774 /**
7775 * Select and compile (or reuse) TES parts (epilog).
7776 */
7777 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
7778 LLVMTargetMachineRef tm,
7779 struct si_shader *shader,
7780 struct pipe_debug_callback *debug)
7781 {
7782 if (shader->key.as_es)
7783 return true;
7784
7785 /* TES compiled as VS. */
7786 return si_get_vs_epilog(sscreen, tm, shader, debug,
7787 &shader->key.part.tes.epilog);
7788 }
7789
7790 /**
7791 * Compile the TCS epilog function. This writes tesselation factors to memory
7792 * based on the output primitive type of the tesselator (determined by TES).
7793 */
7794 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7795 union si_shader_part_key *key)
7796 {
7797 struct gallivm_state *gallivm = &ctx->gallivm;
7798 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
7799 LLVMTypeRef params[16];
7800 LLVMValueRef func;
7801 int last_sgpr, num_params;
7802
7803 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
7804 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
7805 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
7806 params[SI_PARAM_SAMPLERS] = ctx->i64;
7807 params[SI_PARAM_IMAGES] = ctx->i64;
7808 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
7809 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
7810 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
7811 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
7812 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
7813 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
7814 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
7815 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
7816 num_params = last_sgpr + 1;
7817
7818 params[num_params++] = ctx->i32; /* patch index within the wave (REL_PATCH_ID) */
7819 params[num_params++] = ctx->i32; /* invocation ID within the patch */
7820 params[num_params++] = ctx->i32; /* LDS offset where tess factors should be loaded from */
7821
7822 /* Create the function. */
7823 si_create_function(ctx, "tcs_epilog", NULL, 0, params, num_params, last_sgpr);
7824 declare_tess_lds(ctx);
7825 func = ctx->main_fn;
7826
7827 si_write_tess_factors(bld_base,
7828 LLVMGetParam(func, last_sgpr + 1),
7829 LLVMGetParam(func, last_sgpr + 2),
7830 LLVMGetParam(func, last_sgpr + 3));
7831
7832 LLVMBuildRetVoid(gallivm->builder);
7833 }
7834
7835 /**
7836 * Select and compile (or reuse) TCS parts (epilog).
7837 */
7838 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7839 LLVMTargetMachineRef tm,
7840 struct si_shader *shader,
7841 struct pipe_debug_callback *debug)
7842 {
7843 union si_shader_part_key epilog_key;
7844
7845 /* Get the epilog. */
7846 memset(&epilog_key, 0, sizeof(epilog_key));
7847 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7848
7849 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7850 PIPE_SHADER_TESS_CTRL, false,
7851 &epilog_key, tm, debug,
7852 si_build_tcs_epilog_function,
7853 "Tessellation Control Shader Epilog");
7854 return shader->epilog != NULL;
7855 }
7856
7857 /**
7858 * Select and compile (or reuse) GS parts (prolog).
7859 */
7860 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7861 LLVMTargetMachineRef tm,
7862 struct si_shader *shader,
7863 struct pipe_debug_callback *debug)
7864 {
7865 union si_shader_part_key prolog_key;
7866
7867 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7868 return true;
7869
7870 memset(&prolog_key, 0, sizeof(prolog_key));
7871 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7872
7873 shader->prolog = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7874 PIPE_SHADER_GEOMETRY, true,
7875 &prolog_key, tm, debug,
7876 si_build_gs_prolog_function,
7877 "Geometry Shader Prolog");
7878 return shader->prolog != NULL;
7879 }
7880
7881 /**
7882 * Build the pixel shader prolog function. This handles:
7883 * - two-side color selection and interpolation
7884 * - overriding interpolation parameters for the API PS
7885 * - polygon stippling
7886 *
7887 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7888 * overriden by other states. (e.g. per-sample interpolation)
7889 * Interpolated colors are stored after the preloaded VGPRs.
7890 */
7891 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7892 union si_shader_part_key *key)
7893 {
7894 struct gallivm_state *gallivm = &ctx->gallivm;
7895 LLVMTypeRef *params;
7896 LLVMValueRef ret, func;
7897 int last_sgpr, num_params, num_returns, i, num_color_channels;
7898
7899 assert(si_need_ps_prolog(key));
7900
7901 /* Number of inputs + 8 color elements. */
7902 params = alloca((key->ps_prolog.num_input_sgprs +
7903 key->ps_prolog.num_input_vgprs + 8) *
7904 sizeof(LLVMTypeRef));
7905
7906 /* Declare inputs. */
7907 num_params = 0;
7908 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7909 params[num_params++] = ctx->i32;
7910 last_sgpr = num_params - 1;
7911
7912 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7913 params[num_params++] = ctx->f32;
7914
7915 /* Declare outputs (same as inputs + add colors if needed) */
7916 num_returns = num_params;
7917 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7918 for (i = 0; i < num_color_channels; i++)
7919 params[num_returns++] = ctx->f32;
7920
7921 /* Create the function. */
7922 si_create_function(ctx, "ps_prolog", params, num_returns, params,
7923 num_params, last_sgpr);
7924 func = ctx->main_fn;
7925
7926 /* Copy inputs to outputs. This should be no-op, as the registers match,
7927 * but it will prevent the compiler from overwriting them unintentionally.
7928 */
7929 ret = ctx->return_value;
7930 for (i = 0; i < num_params; i++) {
7931 LLVMValueRef p = LLVMGetParam(func, i);
7932 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7933 }
7934
7935 /* Polygon stippling. */
7936 if (key->ps_prolog.states.poly_stipple) {
7937 /* POS_FIXED_PT is always last. */
7938 unsigned pos = key->ps_prolog.num_input_sgprs +
7939 key->ps_prolog.num_input_vgprs - 1;
7940 LLVMValueRef ptr[2], list;
7941
7942 /* Get the pointer to rw buffers. */
7943 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
7944 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
7945 list = lp_build_gather_values(gallivm, ptr, 2);
7946 list = LLVMBuildBitCast(gallivm->builder, list, ctx->i64, "");
7947 list = LLVMBuildIntToPtr(gallivm->builder, list,
7948 const_array(ctx->v16i8, SI_NUM_RW_BUFFERS), "");
7949
7950 si_llvm_emit_polygon_stipple(ctx, list, pos);
7951 }
7952
7953 if (key->ps_prolog.states.bc_optimize_for_persp ||
7954 key->ps_prolog.states.bc_optimize_for_linear) {
7955 unsigned i, base = key->ps_prolog.num_input_sgprs;
7956 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7957
7958 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7959 * The hw doesn't compute CENTROID if the whole wave only
7960 * contains fully-covered quads.
7961 *
7962 * PRIM_MASK is after user SGPRs.
7963 */
7964 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7965 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
7966 LLVMConstInt(ctx->i32, 31, 0), "");
7967 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
7968 ctx->i1, "");
7969
7970 if (key->ps_prolog.states.bc_optimize_for_persp) {
7971 /* Read PERSP_CENTER. */
7972 for (i = 0; i < 2; i++)
7973 center[i] = LLVMGetParam(func, base + 2 + i);
7974 /* Read PERSP_CENTROID. */
7975 for (i = 0; i < 2; i++)
7976 centroid[i] = LLVMGetParam(func, base + 4 + i);
7977 /* Select PERSP_CENTROID. */
7978 for (i = 0; i < 2; i++) {
7979 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7980 center[i], centroid[i], "");
7981 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7982 tmp, base + 4 + i, "");
7983 }
7984 }
7985 if (key->ps_prolog.states.bc_optimize_for_linear) {
7986 /* Read LINEAR_CENTER. */
7987 for (i = 0; i < 2; i++)
7988 center[i] = LLVMGetParam(func, base + 8 + i);
7989 /* Read LINEAR_CENTROID. */
7990 for (i = 0; i < 2; i++)
7991 centroid[i] = LLVMGetParam(func, base + 10 + i);
7992 /* Select LINEAR_CENTROID. */
7993 for (i = 0; i < 2; i++) {
7994 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7995 center[i], centroid[i], "");
7996 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7997 tmp, base + 10 + i, "");
7998 }
7999 }
8000 }
8001
8002 /* Force per-sample interpolation. */
8003 if (key->ps_prolog.states.force_persp_sample_interp) {
8004 unsigned i, base = key->ps_prolog.num_input_sgprs;
8005 LLVMValueRef persp_sample[2];
8006
8007 /* Read PERSP_SAMPLE. */
8008 for (i = 0; i < 2; i++)
8009 persp_sample[i] = LLVMGetParam(func, base + i);
8010 /* Overwrite PERSP_CENTER. */
8011 for (i = 0; i < 2; i++)
8012 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8013 persp_sample[i], base + 2 + i, "");
8014 /* Overwrite PERSP_CENTROID. */
8015 for (i = 0; i < 2; i++)
8016 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8017 persp_sample[i], base + 4 + i, "");
8018 }
8019 if (key->ps_prolog.states.force_linear_sample_interp) {
8020 unsigned i, base = key->ps_prolog.num_input_sgprs;
8021 LLVMValueRef linear_sample[2];
8022
8023 /* Read LINEAR_SAMPLE. */
8024 for (i = 0; i < 2; i++)
8025 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
8026 /* Overwrite LINEAR_CENTER. */
8027 for (i = 0; i < 2; i++)
8028 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8029 linear_sample[i], base + 8 + i, "");
8030 /* Overwrite LINEAR_CENTROID. */
8031 for (i = 0; i < 2; i++)
8032 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8033 linear_sample[i], base + 10 + i, "");
8034 }
8035
8036 /* Force center interpolation. */
8037 if (key->ps_prolog.states.force_persp_center_interp) {
8038 unsigned i, base = key->ps_prolog.num_input_sgprs;
8039 LLVMValueRef persp_center[2];
8040
8041 /* Read PERSP_CENTER. */
8042 for (i = 0; i < 2; i++)
8043 persp_center[i] = LLVMGetParam(func, base + 2 + i);
8044 /* Overwrite PERSP_SAMPLE. */
8045 for (i = 0; i < 2; i++)
8046 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8047 persp_center[i], base + i, "");
8048 /* Overwrite PERSP_CENTROID. */
8049 for (i = 0; i < 2; i++)
8050 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8051 persp_center[i], base + 4 + i, "");
8052 }
8053 if (key->ps_prolog.states.force_linear_center_interp) {
8054 unsigned i, base = key->ps_prolog.num_input_sgprs;
8055 LLVMValueRef linear_center[2];
8056
8057 /* Read LINEAR_CENTER. */
8058 for (i = 0; i < 2; i++)
8059 linear_center[i] = LLVMGetParam(func, base + 8 + i);
8060 /* Overwrite LINEAR_SAMPLE. */
8061 for (i = 0; i < 2; i++)
8062 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8063 linear_center[i], base + 6 + i, "");
8064 /* Overwrite LINEAR_CENTROID. */
8065 for (i = 0; i < 2; i++)
8066 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8067 linear_center[i], base + 10 + i, "");
8068 }
8069
8070 /* Interpolate colors. */
8071 for (i = 0; i < 2; i++) {
8072 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
8073 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
8074 key->ps_prolog.face_vgpr_index;
8075 LLVMValueRef interp[2], color[4];
8076 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
8077
8078 if (!writemask)
8079 continue;
8080
8081 /* If the interpolation qualifier is not CONSTANT (-1). */
8082 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
8083 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
8084 key->ps_prolog.color_interp_vgpr_index[i];
8085
8086 /* Get the (i,j) updated by bc_optimize handling. */
8087 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
8088 interp_vgpr, "");
8089 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
8090 interp_vgpr + 1, "");
8091 interp_ij = lp_build_gather_values(gallivm, interp, 2);
8092 }
8093
8094 /* Use the absolute location of the input. */
8095 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
8096
8097 if (key->ps_prolog.states.color_two_side) {
8098 face = LLVMGetParam(func, face_vgpr);
8099 face = LLVMBuildBitCast(gallivm->builder, face, ctx->i32, "");
8100 }
8101
8102 interp_fs_input(ctx,
8103 key->ps_prolog.color_attr_index[i],
8104 TGSI_SEMANTIC_COLOR, i,
8105 key->ps_prolog.num_interp_inputs,
8106 key->ps_prolog.colors_read, interp_ij,
8107 prim_mask, face, color);
8108
8109 while (writemask) {
8110 unsigned chan = u_bit_scan(&writemask);
8111 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
8112 num_params++, "");
8113 }
8114 }
8115
8116 /* Tell LLVM to insert WQM instruction sequence when needed. */
8117 if (key->ps_prolog.wqm) {
8118 LLVMAddTargetDependentFunctionAttr(func,
8119 "amdgpu-ps-wqm-outputs", "");
8120 }
8121
8122 si_llvm_build_ret(ctx, ret);
8123 }
8124
8125 /**
8126 * Build the pixel shader epilog function. This handles everything that must be
8127 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
8128 */
8129 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
8130 union si_shader_part_key *key)
8131 {
8132 struct gallivm_state *gallivm = &ctx->gallivm;
8133 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
8134 LLVMTypeRef params[16+8*4+3];
8135 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
8136 int last_sgpr, num_params, i;
8137 struct si_ps_exports exp = {};
8138
8139 /* Declare input SGPRs. */
8140 params[SI_PARAM_RW_BUFFERS] = ctx->i64;
8141 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
8142 params[SI_PARAM_SAMPLERS] = ctx->i64;
8143 params[SI_PARAM_IMAGES] = ctx->i64;
8144 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
8145 params[SI_PARAM_ALPHA_REF] = ctx->f32;
8146 last_sgpr = SI_PARAM_ALPHA_REF;
8147
8148 /* Declare input VGPRs. */
8149 num_params = (last_sgpr + 1) +
8150 util_bitcount(key->ps_epilog.colors_written) * 4 +
8151 key->ps_epilog.writes_z +
8152 key->ps_epilog.writes_stencil +
8153 key->ps_epilog.writes_samplemask;
8154
8155 num_params = MAX2(num_params,
8156 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
8157
8158 assert(num_params <= ARRAY_SIZE(params));
8159
8160 for (i = last_sgpr + 1; i < num_params; i++)
8161 params[i] = ctx->f32;
8162
8163 /* Create the function. */
8164 si_create_function(ctx, "ps_epilog", NULL, 0, params, num_params, last_sgpr);
8165 /* Disable elimination of unused inputs. */
8166 si_llvm_add_attribute(ctx->main_fn,
8167 "InitialPSInputAddr", 0xffffff);
8168
8169 /* Process colors. */
8170 unsigned vgpr = last_sgpr + 1;
8171 unsigned colors_written = key->ps_epilog.colors_written;
8172 int last_color_export = -1;
8173
8174 /* Find the last color export. */
8175 if (!key->ps_epilog.writes_z &&
8176 !key->ps_epilog.writes_stencil &&
8177 !key->ps_epilog.writes_samplemask) {
8178 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
8179
8180 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
8181 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
8182 /* Just set this if any of the colorbuffers are enabled. */
8183 if (spi_format &
8184 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
8185 last_color_export = 0;
8186 } else {
8187 for (i = 0; i < 8; i++)
8188 if (colors_written & (1 << i) &&
8189 (spi_format >> (i * 4)) & 0xf)
8190 last_color_export = i;
8191 }
8192 }
8193
8194 while (colors_written) {
8195 LLVMValueRef color[4];
8196 int mrt = u_bit_scan(&colors_written);
8197
8198 for (i = 0; i < 4; i++)
8199 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
8200
8201 si_export_mrt_color(bld_base, color, mrt,
8202 num_params - 1,
8203 mrt == last_color_export, &exp);
8204 }
8205
8206 /* Process depth, stencil, samplemask. */
8207 if (key->ps_epilog.writes_z)
8208 depth = LLVMGetParam(ctx->main_fn, vgpr++);
8209 if (key->ps_epilog.writes_stencil)
8210 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
8211 if (key->ps_epilog.writes_samplemask)
8212 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
8213
8214 if (depth || stencil || samplemask)
8215 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
8216 else if (last_color_export == -1)
8217 si_export_null(bld_base);
8218
8219 if (exp.num)
8220 si_emit_ps_exports(ctx, &exp);
8221
8222 /* Compile. */
8223 LLVMBuildRetVoid(gallivm->builder);
8224 }
8225
8226 /**
8227 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
8228 */
8229 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
8230 LLVMTargetMachineRef tm,
8231 struct si_shader *shader,
8232 struct pipe_debug_callback *debug)
8233 {
8234 union si_shader_part_key prolog_key;
8235 union si_shader_part_key epilog_key;
8236
8237 /* Get the prolog. */
8238 si_get_ps_prolog_key(shader, &prolog_key, true);
8239
8240 /* The prolog is a no-op if these aren't set. */
8241 if (si_need_ps_prolog(&prolog_key)) {
8242 shader->prolog =
8243 si_get_shader_part(sscreen, &sscreen->ps_prologs,
8244 PIPE_SHADER_FRAGMENT, true,
8245 &prolog_key, tm, debug,
8246 si_build_ps_prolog_function,
8247 "Fragment Shader Prolog");
8248 if (!shader->prolog)
8249 return false;
8250 }
8251
8252 /* Get the epilog. */
8253 si_get_ps_epilog_key(shader, &epilog_key);
8254
8255 shader->epilog =
8256 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
8257 PIPE_SHADER_FRAGMENT, false,
8258 &epilog_key, tm, debug,
8259 si_build_ps_epilog_function,
8260 "Fragment Shader Epilog");
8261 if (!shader->epilog)
8262 return false;
8263
8264 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
8265 if (shader->key.part.ps.prolog.poly_stipple) {
8266 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
8267 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
8268 }
8269
8270 /* Set up the enable bits for per-sample shading if needed. */
8271 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
8272 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8273 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8274 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
8275 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8276 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
8277 }
8278 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
8279 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8280 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8281 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
8282 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8283 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
8284 }
8285 if (shader->key.part.ps.prolog.force_persp_center_interp &&
8286 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8287 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8288 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
8289 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8290 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8291 }
8292 if (shader->key.part.ps.prolog.force_linear_center_interp &&
8293 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8294 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8295 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
8296 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8297 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8298 }
8299
8300 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
8301 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
8302 !(shader->config.spi_ps_input_ena & 0xf)) {
8303 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8304 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
8305 }
8306
8307 /* At least one pair of interpolation weights must be enabled. */
8308 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
8309 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8310 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
8311 }
8312
8313 /* The sample mask input is always enabled, because the API shader always
8314 * passes it through to the epilog. Disable it here if it's unused.
8315 */
8316 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
8317 !shader->selector->info.reads_samplemask)
8318 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
8319
8320 return true;
8321 }
8322
8323 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
8324 unsigned *lds_size)
8325 {
8326 /* SPI barrier management bug:
8327 * Make sure we have at least 4k of LDS in use to avoid the bug.
8328 * It applies to workgroup sizes of more than one wavefront.
8329 */
8330 if (sscreen->b.family == CHIP_BONAIRE ||
8331 sscreen->b.family == CHIP_KABINI ||
8332 sscreen->b.family == CHIP_MULLINS)
8333 *lds_size = MAX2(*lds_size, 8);
8334 }
8335
8336 static void si_fix_resource_usage(struct si_screen *sscreen,
8337 struct si_shader *shader)
8338 {
8339 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
8340
8341 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
8342
8343 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
8344 si_get_max_workgroup_size(shader) > 64) {
8345 si_multiwave_lds_size_workaround(sscreen,
8346 &shader->config.lds_size);
8347 }
8348 }
8349
8350 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
8351 struct si_shader *shader,
8352 struct pipe_debug_callback *debug)
8353 {
8354 struct si_shader_selector *sel = shader->selector;
8355 struct si_shader *mainp = sel->main_shader_part;
8356 int r;
8357
8358 /* LS, ES, VS are compiled on demand if the main part hasn't been
8359 * compiled for that stage.
8360 *
8361 * Vertex shaders are compiled on demand when a vertex fetch
8362 * workaround must be applied.
8363 */
8364 if (shader->is_monolithic) {
8365 /* Monolithic shader (compiled as a whole, has many variants,
8366 * may take a long time to compile).
8367 */
8368 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
8369 if (r)
8370 return r;
8371 } else {
8372 /* The shader consists of 2-3 parts:
8373 *
8374 * - the middle part is the user shader, it has 1 variant only
8375 * and it was compiled during the creation of the shader
8376 * selector
8377 * - the prolog part is inserted at the beginning
8378 * - the epilog part is inserted at the end
8379 *
8380 * The prolog and epilog have many (but simple) variants.
8381 */
8382
8383 /* Copy the compiled TGSI shader data over. */
8384 shader->is_binary_shared = true;
8385 shader->binary = mainp->binary;
8386 shader->config = mainp->config;
8387 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8388 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8389 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8390 memcpy(shader->info.vs_output_param_offset,
8391 mainp->info.vs_output_param_offset,
8392 sizeof(mainp->info.vs_output_param_offset));
8393 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8394 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8395 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8396
8397 /* Select prologs and/or epilogs. */
8398 switch (sel->type) {
8399 case PIPE_SHADER_VERTEX:
8400 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
8401 return -1;
8402 break;
8403 case PIPE_SHADER_TESS_CTRL:
8404 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
8405 return -1;
8406 break;
8407 case PIPE_SHADER_TESS_EVAL:
8408 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
8409 return -1;
8410 break;
8411 case PIPE_SHADER_GEOMETRY:
8412 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
8413 return -1;
8414 break;
8415 case PIPE_SHADER_FRAGMENT:
8416 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8417 return -1;
8418
8419 /* Make sure we have at least as many VGPRs as there
8420 * are allocated inputs.
8421 */
8422 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8423 shader->info.num_input_vgprs);
8424 break;
8425 }
8426
8427 /* Update SGPR and VGPR counts. */
8428 if (shader->prolog) {
8429 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8430 shader->prolog->config.num_sgprs);
8431 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8432 shader->prolog->config.num_vgprs);
8433 }
8434 if (shader->epilog) {
8435 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8436 shader->epilog->config.num_sgprs);
8437 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8438 shader->epilog->config.num_vgprs);
8439 }
8440 }
8441
8442 si_fix_resource_usage(sscreen, shader);
8443 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8444 stderr);
8445
8446 /* Upload. */
8447 r = si_shader_binary_upload(sscreen, shader);
8448 if (r) {
8449 fprintf(stderr, "LLVM failed to upload shader\n");
8450 return r;
8451 }
8452
8453 return 0;
8454 }
8455
8456 void si_shader_destroy(struct si_shader *shader)
8457 {
8458 if (shader->scratch_bo)
8459 r600_resource_reference(&shader->scratch_bo, NULL);
8460
8461 r600_resource_reference(&shader->bo, NULL);
8462
8463 if (!shader->is_binary_shared)
8464 radeon_shader_binary_clean(&shader->binary);
8465
8466 free(shader->shader_log);
8467 }