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radeonsi: set correct num_input_sgprs for VS prolog in merged shaders
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "gallivm/lp_bld_const.h"
25 #include "gallivm/lp_bld_gather.h"
26 #include "gallivm/lp_bld_intr.h"
27 #include "gallivm/lp_bld_logic.h"
28 #include "gallivm/lp_bld_arit.h"
29 #include "gallivm/lp_bld_flow.h"
30 #include "gallivm/lp_bld_misc.h"
31 #include "util/u_memory.h"
32 #include "util/u_string.h"
33 #include "tgsi/tgsi_build.h"
34 #include "tgsi/tgsi_util.h"
35 #include "tgsi/tgsi_dump.h"
36
37 #include "ac_binary.h"
38 #include "ac_llvm_util.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41 #include "si_shader_internal.h"
42 #include "si_pipe.h"
43 #include "sid.h"
44
45 #include "compiler/nir/nir.h"
46
47 static const char *scratch_rsrc_dword0_symbol =
48 "SCRATCH_RSRC_DWORD0";
49
50 static const char *scratch_rsrc_dword1_symbol =
51 "SCRATCH_RSRC_DWORD1";
52
53 struct si_shader_output_values
54 {
55 LLVMValueRef values[4];
56 unsigned semantic_name;
57 unsigned semantic_index;
58 ubyte vertex_stream[4];
59 };
60
61 /**
62 * Used to collect types and other info about arguments of the LLVM function
63 * before the function is created.
64 */
65 struct si_function_info {
66 LLVMTypeRef types[100];
67 LLVMValueRef *assign[100];
68 unsigned num_sgpr_params;
69 unsigned num_params;
70 };
71
72 enum si_arg_regfile {
73 ARG_SGPR,
74 ARG_VGPR
75 };
76
77 static void si_init_shader_ctx(struct si_shader_context *ctx,
78 struct si_screen *sscreen,
79 LLVMTargetMachineRef tm);
80
81 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
82 struct lp_build_tgsi_context *bld_base,
83 struct lp_build_emit_data *emit_data);
84
85 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
86 FILE *f);
87
88 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
89 union si_shader_part_key *key);
90 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
91 union si_shader_part_key *key);
92 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
93 union si_shader_part_key *key);
94 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
95 union si_shader_part_key *key);
96
97 /* Ideally pass the sample mask input to the PS epilog as v14, which
98 * is its usual location, so that the shader doesn't have to add v_mov.
99 */
100 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
101
102 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
103 LLVMTypeRef type)
104 {
105 if (type == ctx->ac.i64 || type == ctx->ac.f64)
106 return true;
107
108 return false;
109 }
110
111 static bool is_merged_shader(struct si_shader *shader)
112 {
113 if (shader->selector->screen->info.chip_class <= VI)
114 return false;
115
116 return shader->key.as_ls ||
117 shader->key.as_es ||
118 shader->selector->type == PIPE_SHADER_TESS_CTRL ||
119 shader->selector->type == PIPE_SHADER_GEOMETRY;
120 }
121
122 static void si_init_function_info(struct si_function_info *fninfo)
123 {
124 fninfo->num_params = 0;
125 fninfo->num_sgpr_params = 0;
126 }
127
128 static unsigned add_arg_assign(struct si_function_info *fninfo,
129 enum si_arg_regfile regfile, LLVMTypeRef type,
130 LLVMValueRef *assign)
131 {
132 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
133
134 unsigned idx = fninfo->num_params++;
135 assert(idx < ARRAY_SIZE(fninfo->types));
136
137 if (regfile == ARG_SGPR)
138 fninfo->num_sgpr_params = fninfo->num_params;
139
140 fninfo->types[idx] = type;
141 fninfo->assign[idx] = assign;
142 return idx;
143 }
144
145 static unsigned add_arg(struct si_function_info *fninfo,
146 enum si_arg_regfile regfile, LLVMTypeRef type)
147 {
148 return add_arg_assign(fninfo, regfile, type, NULL);
149 }
150
151 static void add_arg_assign_checked(struct si_function_info *fninfo,
152 enum si_arg_regfile regfile, LLVMTypeRef type,
153 LLVMValueRef *assign, unsigned idx)
154 {
155 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
156 assert(actual == idx);
157 }
158
159 static void add_arg_checked(struct si_function_info *fninfo,
160 enum si_arg_regfile regfile, LLVMTypeRef type,
161 unsigned idx)
162 {
163 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
164 }
165
166 /**
167 * Returns a unique index for a per-patch semantic name and index. The index
168 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
169 * can be calculated.
170 */
171 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
172 {
173 switch (semantic_name) {
174 case TGSI_SEMANTIC_TESSOUTER:
175 return 0;
176 case TGSI_SEMANTIC_TESSINNER:
177 return 1;
178 case TGSI_SEMANTIC_PATCH:
179 assert(index < 30);
180 return 2 + index;
181
182 default:
183 assert(!"invalid semantic name");
184 return 0;
185 }
186 }
187
188 /**
189 * Returns a unique index for a semantic name and index. The index must be
190 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
191 * calculated.
192 */
193 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
194 {
195 switch (semantic_name) {
196 case TGSI_SEMANTIC_POSITION:
197 return 0;
198 case TGSI_SEMANTIC_GENERIC:
199 /* Since some shader stages use the the highest used IO index
200 * to determine the size to allocate for inputs/outputs
201 * (in LDS, tess and GS rings). GENERIC should be placed right
202 * after POSITION to make that size as small as possible.
203 */
204 if (index < SI_MAX_IO_GENERIC)
205 return 1 + index;
206
207 assert(!"invalid generic index");
208 return 0;
209 case TGSI_SEMANTIC_PSIZE:
210 return SI_MAX_IO_GENERIC + 1;
211 case TGSI_SEMANTIC_CLIPDIST:
212 assert(index <= 1);
213 return SI_MAX_IO_GENERIC + 2 + index;
214 case TGSI_SEMANTIC_FOG:
215 return SI_MAX_IO_GENERIC + 4;
216 case TGSI_SEMANTIC_LAYER:
217 return SI_MAX_IO_GENERIC + 5;
218 case TGSI_SEMANTIC_VIEWPORT_INDEX:
219 return SI_MAX_IO_GENERIC + 6;
220 case TGSI_SEMANTIC_PRIMID:
221 return SI_MAX_IO_GENERIC + 7;
222 case TGSI_SEMANTIC_COLOR: /* these alias */
223 case TGSI_SEMANTIC_BCOLOR:
224 assert(index < 2);
225 return SI_MAX_IO_GENERIC + 8 + index;
226 case TGSI_SEMANTIC_TEXCOORD:
227 assert(index < 8);
228 assert(SI_MAX_IO_GENERIC + 10 + index < 64);
229 return SI_MAX_IO_GENERIC + 10 + index;
230 default:
231 assert(!"invalid semantic name");
232 return 0;
233 }
234 }
235
236 /**
237 * Get the value of a shader input parameter and extract a bitfield.
238 */
239 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
240 LLVMValueRef value, unsigned rshift,
241 unsigned bitwidth)
242 {
243 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
244 value = ac_to_integer(&ctx->ac, value);
245
246 if (rshift)
247 value = LLVMBuildLShr(ctx->ac.builder, value,
248 LLVMConstInt(ctx->i32, rshift, 0), "");
249
250 if (rshift + bitwidth < 32) {
251 unsigned mask = (1 << bitwidth) - 1;
252 value = LLVMBuildAnd(ctx->ac.builder, value,
253 LLVMConstInt(ctx->i32, mask, 0), "");
254 }
255
256 return value;
257 }
258
259 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
260 unsigned param, unsigned rshift,
261 unsigned bitwidth)
262 {
263 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
264
265 return unpack_llvm_param(ctx, value, rshift, bitwidth);
266 }
267
268 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
269 {
270 switch (ctx->type) {
271 case PIPE_SHADER_TESS_CTRL:
272 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
273
274 case PIPE_SHADER_TESS_EVAL:
275 return LLVMGetParam(ctx->main_fn,
276 ctx->param_tes_rel_patch_id);
277
278 default:
279 assert(0);
280 return NULL;
281 }
282 }
283
284 /* Tessellation shaders pass outputs to the next shader using LDS.
285 *
286 * LS outputs = TCS inputs
287 * TCS outputs = TES inputs
288 *
289 * The LDS layout is:
290 * - TCS inputs for patch 0
291 * - TCS inputs for patch 1
292 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
293 * - ...
294 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
295 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
296 * - TCS outputs for patch 1
297 * - Per-patch TCS outputs for patch 1
298 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
299 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
300 * - ...
301 *
302 * All three shaders VS(LS), TCS, TES share the same LDS space.
303 */
304
305 static LLVMValueRef
306 get_tcs_in_patch_stride(struct si_shader_context *ctx)
307 {
308 return unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
309 }
310
311 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
312 {
313 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
314
315 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
316 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
317
318 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
319 }
320
321 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
322 {
323 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
324
325 return LLVMConstInt(ctx->i32, stride, 0);
326 }
327
328 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
329 {
330 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
331 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
332
333 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
334 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
335 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
336 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
337 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
338 num_patch_outputs * 4;
339 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
340 }
341
342 static LLVMValueRef
343 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
344 {
345 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
346 unpack_param(ctx,
347 ctx->param_tcs_out_lds_offsets,
348 0, 16),
349 4);
350 }
351
352 static LLVMValueRef
353 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
354 {
355 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
356 unpack_param(ctx,
357 ctx->param_tcs_out_lds_offsets,
358 16, 16),
359 4);
360 }
361
362 static LLVMValueRef
363 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
364 {
365 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
366 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
367
368 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
369 }
370
371 static LLVMValueRef
372 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
373 {
374 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
375 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
376 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
377
378 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
379 LLVMBuildMul(ctx->ac.builder, patch_stride,
380 rel_patch_id, ""),
381 "");
382 }
383
384 static LLVMValueRef
385 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
386 {
387 LLVMValueRef patch0_patch_data_offset =
388 get_tcs_out_patch0_patch_data_offset(ctx);
389 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
390 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
391
392 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
393 LLVMBuildMul(ctx->ac.builder, patch_stride,
394 rel_patch_id, ""),
395 "");
396 }
397
398 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
399 {
400 unsigned tcs_out_vertices =
401 ctx->shader->selector ?
402 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
403
404 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
405 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
406 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
407
408 return unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
409 }
410
411 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
412 {
413 unsigned stride;
414
415 switch (ctx->type) {
416 case PIPE_SHADER_VERTEX:
417 stride = util_last_bit64(ctx->shader->selector->outputs_written);
418 return LLVMConstInt(ctx->i32, stride * 4, 0);
419
420 case PIPE_SHADER_TESS_CTRL:
421 if (ctx->screen->info.chip_class >= GFX9 &&
422 ctx->shader->is_monolithic) {
423 stride = util_last_bit64(ctx->shader->key.part.tcs.ls->outputs_written);
424 return LLVMConstInt(ctx->i32, stride * 4, 0);
425 }
426 return unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
427
428 default:
429 assert(0);
430 return NULL;
431 }
432 }
433
434 static LLVMValueRef get_instance_index_for_fetch(
435 struct si_shader_context *ctx,
436 unsigned param_start_instance, LLVMValueRef divisor)
437 {
438 LLVMValueRef result = ctx->abi.instance_id;
439
440 /* The division must be done before START_INSTANCE is added. */
441 if (divisor != ctx->i32_1)
442 result = LLVMBuildUDiv(ctx->ac.builder, result, divisor, "");
443
444 return LLVMBuildAdd(ctx->ac.builder, result,
445 LLVMGetParam(ctx->main_fn, param_start_instance), "");
446 }
447
448 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
449 * to float. */
450 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
451 LLVMValueRef vec4,
452 unsigned double_index)
453 {
454 LLVMBuilderRef builder = ctx->ac.builder;
455 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->ac.context);
456 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
457 LLVMVectorType(f64, 2), "");
458 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
459 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
460 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
461 }
462
463 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
464 LLVMValueRef i32, unsigned index)
465 {
466 assert(index <= 1);
467
468 if (index == 1)
469 return LLVMBuildAShr(ctx->ac.builder, i32,
470 LLVMConstInt(ctx->i32, 16, 0), "");
471
472 return LLVMBuildSExt(ctx->ac.builder,
473 LLVMBuildTrunc(ctx->ac.builder, i32,
474 ctx->ac.i16, ""),
475 ctx->i32, "");
476 }
477
478 void si_llvm_load_input_vs(
479 struct si_shader_context *ctx,
480 unsigned input_index,
481 LLVMValueRef out[4])
482 {
483 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
484 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
485
486 if (vs_blit_property) {
487 LLVMValueRef vertex_id = ctx->abi.vertex_id;
488 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
489 LLVMIntULE, vertex_id,
490 ctx->i32_1, "");
491 /* Use LLVMIntNE, because we have 3 vertices and only
492 * the middle one should use y2.
493 */
494 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
495 LLVMIntNE, vertex_id,
496 ctx->i32_1, "");
497
498 if (input_index == 0) {
499 /* Position: */
500 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
501 ctx->param_vs_blit_inputs);
502 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
503 ctx->param_vs_blit_inputs + 1);
504
505 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
506 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
507 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
508 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
509
510 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
511 x1, x2, "");
512 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
513 y1, y2, "");
514
515 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
516 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
517 out[2] = LLVMGetParam(ctx->main_fn,
518 ctx->param_vs_blit_inputs + 2);
519 out[3] = ctx->ac.f32_1;
520 return;
521 }
522
523 /* Color or texture coordinates: */
524 assert(input_index == 1);
525
526 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
527 for (int i = 0; i < 4; i++) {
528 out[i] = LLVMGetParam(ctx->main_fn,
529 ctx->param_vs_blit_inputs + 3 + i);
530 }
531 } else {
532 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
533 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
534 ctx->param_vs_blit_inputs + 3);
535 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
536 ctx->param_vs_blit_inputs + 4);
537 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
538 ctx->param_vs_blit_inputs + 5);
539 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
540 ctx->param_vs_blit_inputs + 6);
541
542 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
543 x1, x2, "");
544 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
545 y1, y2, "");
546 out[2] = LLVMGetParam(ctx->main_fn,
547 ctx->param_vs_blit_inputs + 7);
548 out[3] = LLVMGetParam(ctx->main_fn,
549 ctx->param_vs_blit_inputs + 8);
550 }
551 return;
552 }
553
554 unsigned chan;
555 unsigned fix_fetch;
556 unsigned num_fetches;
557 unsigned fetch_stride;
558 unsigned num_channels;
559
560 LLVMValueRef t_list_ptr;
561 LLVMValueRef t_offset;
562 LLVMValueRef t_list;
563 LLVMValueRef vertex_index;
564 LLVMValueRef input[3];
565
566 /* Load the T list */
567 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
568
569 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
570
571 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
572
573 vertex_index = LLVMGetParam(ctx->main_fn,
574 ctx->param_vertex_index0 +
575 input_index);
576
577 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
578
579 /* Do multiple loads for special formats. */
580 switch (fix_fetch) {
581 case SI_FIX_FETCH_RGB_64_FLOAT:
582 num_fetches = 3; /* 3 2-dword loads */
583 fetch_stride = 8;
584 num_channels = 2;
585 break;
586 case SI_FIX_FETCH_RGBA_64_FLOAT:
587 num_fetches = 2; /* 2 4-dword loads */
588 fetch_stride = 16;
589 num_channels = 4;
590 break;
591 case SI_FIX_FETCH_RGB_8:
592 case SI_FIX_FETCH_RGB_8_INT:
593 num_fetches = 3;
594 fetch_stride = 1;
595 num_channels = 1;
596 break;
597 case SI_FIX_FETCH_RGB_16:
598 case SI_FIX_FETCH_RGB_16_INT:
599 num_fetches = 3;
600 fetch_stride = 2;
601 num_channels = 1;
602 break;
603 default:
604 num_fetches = 1;
605 fetch_stride = 0;
606 num_channels = util_last_bit(info->input_usage_mask[input_index]);
607 }
608
609 for (unsigned i = 0; i < num_fetches; i++) {
610 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
611
612 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
613 vertex_index, voffset,
614 num_channels, false, true);
615 input[i] = ac_build_expand_to_vec4(&ctx->ac, input[i], num_channels);
616 }
617
618 /* Break up the vec4 into individual components */
619 for (chan = 0; chan < 4; chan++) {
620 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
621 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
622 input[0], llvm_chan, "");
623 }
624
625 switch (fix_fetch) {
626 case SI_FIX_FETCH_A2_SNORM:
627 case SI_FIX_FETCH_A2_SSCALED:
628 case SI_FIX_FETCH_A2_SINT: {
629 /* The hardware returns an unsigned value; convert it to a
630 * signed one.
631 */
632 LLVMValueRef tmp = out[3];
633 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
634
635 /* First, recover the sign-extended signed integer value. */
636 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
637 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
638 else
639 tmp = ac_to_integer(&ctx->ac, tmp);
640
641 /* For the integer-like cases, do a natural sign extension.
642 *
643 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
644 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
645 * exponent.
646 */
647 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
648 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
649 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
650 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
651
652 /* Convert back to the right type. */
653 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
654 LLVMValueRef clamp;
655 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
656 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
657 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
658 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
659 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
660 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
661 }
662
663 out[3] = tmp;
664 break;
665 }
666 case SI_FIX_FETCH_RGBA_32_UNORM:
667 case SI_FIX_FETCH_RGBX_32_UNORM:
668 for (chan = 0; chan < 4; chan++) {
669 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
670 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
671 out[chan], ctx->f32, "");
672 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
673 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
674 }
675 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
676 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
677 out[3] = LLVMConstReal(ctx->f32, 1);
678 break;
679 case SI_FIX_FETCH_RGBA_32_SNORM:
680 case SI_FIX_FETCH_RGBX_32_SNORM:
681 case SI_FIX_FETCH_RGBA_32_FIXED:
682 case SI_FIX_FETCH_RGBX_32_FIXED: {
683 double scale;
684 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
685 scale = 1.0 / 0x10000;
686 else
687 scale = 1.0 / INT_MAX;
688
689 for (chan = 0; chan < 4; chan++) {
690 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
691 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
692 out[chan], ctx->f32, "");
693 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
694 LLVMConstReal(ctx->f32, scale), "");
695 }
696 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
697 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
698 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
699 out[3] = LLVMConstReal(ctx->f32, 1);
700 break;
701 }
702 case SI_FIX_FETCH_RGBA_32_USCALED:
703 for (chan = 0; chan < 4; chan++) {
704 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
705 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
706 out[chan], ctx->f32, "");
707 }
708 break;
709 case SI_FIX_FETCH_RGBA_32_SSCALED:
710 for (chan = 0; chan < 4; chan++) {
711 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
712 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
713 out[chan], ctx->f32, "");
714 }
715 break;
716 case SI_FIX_FETCH_RG_64_FLOAT:
717 for (chan = 0; chan < 2; chan++)
718 out[chan] = extract_double_to_float(ctx, input[0], chan);
719
720 out[2] = LLVMConstReal(ctx->f32, 0);
721 out[3] = LLVMConstReal(ctx->f32, 1);
722 break;
723 case SI_FIX_FETCH_RGB_64_FLOAT:
724 for (chan = 0; chan < 3; chan++)
725 out[chan] = extract_double_to_float(ctx, input[chan], 0);
726
727 out[3] = LLVMConstReal(ctx->f32, 1);
728 break;
729 case SI_FIX_FETCH_RGBA_64_FLOAT:
730 for (chan = 0; chan < 4; chan++) {
731 out[chan] = extract_double_to_float(ctx, input[chan / 2],
732 chan % 2);
733 }
734 break;
735 case SI_FIX_FETCH_RGB_8:
736 case SI_FIX_FETCH_RGB_8_INT:
737 case SI_FIX_FETCH_RGB_16:
738 case SI_FIX_FETCH_RGB_16_INT:
739 for (chan = 0; chan < 3; chan++) {
740 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
741 input[chan],
742 ctx->i32_0, "");
743 }
744 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
745 fix_fetch == SI_FIX_FETCH_RGB_16) {
746 out[3] = LLVMConstReal(ctx->f32, 1);
747 } else {
748 out[3] = ac_to_float(&ctx->ac, ctx->i32_1);
749 }
750 break;
751 }
752 }
753
754 static void declare_input_vs(
755 struct si_shader_context *ctx,
756 unsigned input_index,
757 const struct tgsi_full_declaration *decl,
758 LLVMValueRef out[4])
759 {
760 si_llvm_load_input_vs(ctx, input_index, out);
761 }
762
763 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
764 unsigned swizzle)
765 {
766 if (swizzle > 0)
767 return ctx->i32_0;
768
769 switch (ctx->type) {
770 case PIPE_SHADER_VERTEX:
771 return LLVMGetParam(ctx->main_fn,
772 ctx->param_vs_prim_id);
773 case PIPE_SHADER_TESS_CTRL:
774 return ctx->abi.tcs_patch_id;
775 case PIPE_SHADER_TESS_EVAL:
776 return ctx->abi.tes_patch_id;
777 case PIPE_SHADER_GEOMETRY:
778 return ctx->abi.gs_prim_id;
779 default:
780 assert(0);
781 return ctx->i32_0;
782 }
783 }
784
785 /**
786 * Return the value of tgsi_ind_register for indexing.
787 * This is the indirect index with the constant offset added to it.
788 */
789 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
790 const struct tgsi_ind_register *ind,
791 unsigned addr_mul,
792 int rel_index)
793 {
794 LLVMValueRef result;
795
796 if (ind->File == TGSI_FILE_ADDRESS) {
797 result = ctx->addrs[ind->Index][ind->Swizzle];
798 result = LLVMBuildLoad(ctx->ac.builder, result, "");
799 } else {
800 struct tgsi_full_src_register src = {};
801
802 src.Register.File = ind->File;
803 src.Register.Index = ind->Index;
804
805 /* Set the second index to 0 for constants. */
806 if (ind->File == TGSI_FILE_CONSTANT)
807 src.Register.Dimension = 1;
808
809 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
810 TGSI_TYPE_SIGNED,
811 ind->Swizzle);
812 result = ac_to_integer(&ctx->ac, result);
813 }
814
815 if (addr_mul != 1)
816 result = LLVMBuildMul(ctx->ac.builder, result,
817 LLVMConstInt(ctx->i32, addr_mul, 0), "");
818 result = LLVMBuildAdd(ctx->ac.builder, result,
819 LLVMConstInt(ctx->i32, rel_index, 0), "");
820 return result;
821 }
822
823 /**
824 * Like si_get_indirect_index, but restricts the return value to a (possibly
825 * undefined) value inside [0..num).
826 */
827 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
828 const struct tgsi_ind_register *ind,
829 int rel_index, unsigned num)
830 {
831 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
832
833 return si_llvm_bound_index(ctx, result, num);
834 }
835
836 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
837 LLVMValueRef vertex_dw_stride,
838 LLVMValueRef base_addr,
839 LLVMValueRef vertex_index,
840 LLVMValueRef param_index,
841 unsigned input_index,
842 ubyte *name,
843 ubyte *index,
844 bool is_patch)
845 {
846 if (vertex_dw_stride) {
847 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
848 LLVMBuildMul(ctx->ac.builder, vertex_index,
849 vertex_dw_stride, ""), "");
850 }
851
852 if (param_index) {
853 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
854 LLVMBuildMul(ctx->ac.builder, param_index,
855 LLVMConstInt(ctx->i32, 4, 0), ""), "");
856 }
857
858 int param = is_patch ?
859 si_shader_io_get_unique_index_patch(name[input_index],
860 index[input_index]) :
861 si_shader_io_get_unique_index(name[input_index],
862 index[input_index]);
863
864 /* Add the base address of the element. */
865 return LLVMBuildAdd(ctx->ac.builder, base_addr,
866 LLVMConstInt(ctx->i32, param * 4, 0), "");
867 }
868
869 /**
870 * Calculate a dword address given an input or output register and a stride.
871 */
872 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
873 const struct tgsi_full_dst_register *dst,
874 const struct tgsi_full_src_register *src,
875 LLVMValueRef vertex_dw_stride,
876 LLVMValueRef base_addr)
877 {
878 struct tgsi_shader_info *info = &ctx->shader->selector->info;
879 ubyte *name, *index, *array_first;
880 int input_index;
881 struct tgsi_full_dst_register reg;
882 LLVMValueRef vertex_index = NULL;
883 LLVMValueRef ind_index = NULL;
884
885 /* Set the register description. The address computation is the same
886 * for sources and destinations. */
887 if (src) {
888 reg.Register.File = src->Register.File;
889 reg.Register.Index = src->Register.Index;
890 reg.Register.Indirect = src->Register.Indirect;
891 reg.Register.Dimension = src->Register.Dimension;
892 reg.Indirect = src->Indirect;
893 reg.Dimension = src->Dimension;
894 reg.DimIndirect = src->DimIndirect;
895 } else
896 reg = *dst;
897
898 /* If the register is 2-dimensional (e.g. an array of vertices
899 * in a primitive), calculate the base address of the vertex. */
900 if (reg.Register.Dimension) {
901 if (reg.Dimension.Indirect)
902 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
903 1, reg.Dimension.Index);
904 else
905 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
906 }
907
908 /* Get information about the register. */
909 if (reg.Register.File == TGSI_FILE_INPUT) {
910 name = info->input_semantic_name;
911 index = info->input_semantic_index;
912 array_first = info->input_array_first;
913 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
914 name = info->output_semantic_name;
915 index = info->output_semantic_index;
916 array_first = info->output_array_first;
917 } else {
918 assert(0);
919 return NULL;
920 }
921
922 if (reg.Register.Indirect) {
923 /* Add the relative address of the element. */
924 if (reg.Indirect.ArrayID)
925 input_index = array_first[reg.Indirect.ArrayID];
926 else
927 input_index = reg.Register.Index;
928
929 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
930 1, reg.Register.Index - input_index);
931 } else {
932 input_index = reg.Register.Index;
933 }
934
935 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
936 base_addr, vertex_index,
937 ind_index, input_index,
938 name, index,
939 !reg.Register.Dimension);
940 }
941
942 /* The offchip buffer layout for TCS->TES is
943 *
944 * - attribute 0 of patch 0 vertex 0
945 * - attribute 0 of patch 0 vertex 1
946 * - attribute 0 of patch 0 vertex 2
947 * ...
948 * - attribute 0 of patch 1 vertex 0
949 * - attribute 0 of patch 1 vertex 1
950 * ...
951 * - attribute 1 of patch 0 vertex 0
952 * - attribute 1 of patch 0 vertex 1
953 * ...
954 * - per patch attribute 0 of patch 0
955 * - per patch attribute 0 of patch 1
956 * ...
957 *
958 * Note that every attribute has 4 components.
959 */
960 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
961 LLVMValueRef rel_patch_id,
962 LLVMValueRef vertex_index,
963 LLVMValueRef param_index)
964 {
965 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
966 LLVMValueRef param_stride, constant16;
967
968 vertices_per_patch = get_num_tcs_out_vertices(ctx);
969 num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
970 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
971 num_patches, "");
972
973 constant16 = LLVMConstInt(ctx->i32, 16, 0);
974 if (vertex_index) {
975 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
976 vertices_per_patch, "");
977
978 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
979 vertex_index, "");
980
981 param_stride = total_vertices;
982 } else {
983 base_addr = rel_patch_id;
984 param_stride = num_patches;
985 }
986
987 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
988 LLVMBuildMul(ctx->ac.builder, param_index,
989 param_stride, ""), "");
990
991 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
992
993 if (!vertex_index) {
994 LLVMValueRef patch_data_offset =
995 unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
996
997 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
998 patch_data_offset, "");
999 }
1000 return base_addr;
1001 }
1002
1003 /* This is a generic helper that can be shared by the NIR and TGSI backends */
1004 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
1005 struct si_shader_context *ctx,
1006 LLVMValueRef vertex_index,
1007 LLVMValueRef param_index,
1008 unsigned param_base,
1009 ubyte *name,
1010 ubyte *index,
1011 bool is_patch)
1012 {
1013 unsigned param_index_base;
1014
1015 param_index_base = is_patch ?
1016 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
1017 si_shader_io_get_unique_index(name[param_base], index[param_base]);
1018
1019 if (param_index) {
1020 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1021 LLVMConstInt(ctx->i32, param_index_base, 0),
1022 "");
1023 } else {
1024 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
1025 }
1026
1027 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
1028 vertex_index, param_index);
1029 }
1030
1031 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
1032 struct si_shader_context *ctx,
1033 const struct tgsi_full_dst_register *dst,
1034 const struct tgsi_full_src_register *src)
1035 {
1036 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1037 ubyte *name, *index, *array_first;
1038 struct tgsi_full_src_register reg;
1039 LLVMValueRef vertex_index = NULL;
1040 LLVMValueRef param_index = NULL;
1041 unsigned param_base;
1042
1043 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
1044
1045 if (reg.Register.Dimension) {
1046
1047 if (reg.Dimension.Indirect)
1048 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
1049 1, reg.Dimension.Index);
1050 else
1051 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
1052 }
1053
1054 /* Get information about the register. */
1055 if (reg.Register.File == TGSI_FILE_INPUT) {
1056 name = info->input_semantic_name;
1057 index = info->input_semantic_index;
1058 array_first = info->input_array_first;
1059 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1060 name = info->output_semantic_name;
1061 index = info->output_semantic_index;
1062 array_first = info->output_array_first;
1063 } else {
1064 assert(0);
1065 return NULL;
1066 }
1067
1068 if (reg.Register.Indirect) {
1069 if (reg.Indirect.ArrayID)
1070 param_base = array_first[reg.Indirect.ArrayID];
1071 else
1072 param_base = reg.Register.Index;
1073
1074 param_index = si_get_indirect_index(ctx, &reg.Indirect,
1075 1, reg.Register.Index - param_base);
1076
1077 } else {
1078 param_base = reg.Register.Index;
1079 }
1080
1081 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1082 param_index, param_base,
1083 name, index, !reg.Register.Dimension);
1084 }
1085
1086 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
1087 LLVMTypeRef type, unsigned swizzle,
1088 LLVMValueRef buffer, LLVMValueRef offset,
1089 LLVMValueRef base, bool can_speculate)
1090 {
1091 struct si_shader_context *ctx = si_shader_context(bld_base);
1092 LLVMValueRef value, value2;
1093 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
1094
1095 if (swizzle == ~0) {
1096 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1097 0, 1, 0, can_speculate, false);
1098
1099 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1100 }
1101
1102 if (!llvm_type_is_64bit(ctx, type)) {
1103 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1104 0, 1, 0, can_speculate, false);
1105
1106 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1107 return LLVMBuildExtractElement(ctx->ac.builder, value,
1108 LLVMConstInt(ctx->i32, swizzle, 0), "");
1109 }
1110
1111 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1112 swizzle * 4, 1, 0, can_speculate, false);
1113
1114 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1115 swizzle * 4 + 4, 1, 0, can_speculate, false);
1116
1117 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1118 }
1119
1120 /**
1121 * Load from LDS.
1122 *
1123 * \param type output value type
1124 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1125 * \param dw_addr address in dwords
1126 */
1127 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1128 LLVMTypeRef type, unsigned swizzle,
1129 LLVMValueRef dw_addr)
1130 {
1131 struct si_shader_context *ctx = si_shader_context(bld_base);
1132 LLVMValueRef value;
1133
1134 if (swizzle == ~0) {
1135 LLVMValueRef values[TGSI_NUM_CHANNELS];
1136
1137 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1138 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1139
1140 return lp_build_gather_values(&ctx->gallivm, values,
1141 TGSI_NUM_CHANNELS);
1142 }
1143
1144 /* Split 64-bit loads. */
1145 if (llvm_type_is_64bit(ctx, type)) {
1146 LLVMValueRef lo, hi;
1147
1148 lo = lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1149 hi = lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1150 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1151 }
1152
1153 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1154 LLVMConstInt(ctx->i32, swizzle, 0));
1155
1156 value = ac_lds_load(&ctx->ac, dw_addr);
1157
1158 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1159 }
1160
1161 /**
1162 * Store to LDS.
1163 *
1164 * \param swizzle offset (typically 0..3)
1165 * \param dw_addr address in dwords
1166 * \param value value to store
1167 */
1168 static void lds_store(struct si_shader_context *ctx,
1169 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1170 LLVMValueRef value)
1171 {
1172 dw_addr = lp_build_add(&ctx->bld_base.uint_bld, dw_addr,
1173 LLVMConstInt(ctx->i32, dw_offset_imm, 0));
1174
1175 ac_lds_store(&ctx->ac, dw_addr, value);
1176 }
1177
1178 enum si_tess_ring {
1179 TCS_FACTOR_RING,
1180 TESS_OFFCHIP_RING_TCS,
1181 TESS_OFFCHIP_RING_TES,
1182 };
1183
1184 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
1185 enum si_tess_ring ring)
1186 {
1187 LLVMBuilderRef builder = ctx->ac.builder;
1188 unsigned param = ring == TESS_OFFCHIP_RING_TES ? ctx->param_tes_offchip_addr :
1189 ctx->param_tcs_out_lds_layout;
1190 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1191
1192 /* TCS only receives high 13 bits of the address. */
1193 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
1194 addr = LLVMBuildAnd(builder, addr,
1195 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
1196 }
1197
1198 if (ring == TCS_FACTOR_RING) {
1199 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
1200 addr = LLVMBuildAdd(builder, addr,
1201 LLVMConstInt(ctx->i32, tf_offset, 0), "");
1202 }
1203
1204 LLVMValueRef desc[4];
1205 desc[0] = addr;
1206 desc[1] = LLVMConstInt(ctx->i32,
1207 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1208 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
1209 desc[3] = LLVMConstInt(ctx->i32,
1210 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1211 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1212 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1213 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1214 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1215 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0);
1216
1217 return ac_build_gather_values(&ctx->ac, desc, 4);
1218 }
1219
1220 static LLVMValueRef fetch_input_tcs(
1221 struct lp_build_tgsi_context *bld_base,
1222 const struct tgsi_full_src_register *reg,
1223 enum tgsi_opcode_type type, unsigned swizzle)
1224 {
1225 struct si_shader_context *ctx = si_shader_context(bld_base);
1226 LLVMValueRef dw_addr, stride;
1227
1228 stride = get_tcs_in_vertex_dw_stride(ctx);
1229 dw_addr = get_tcs_in_current_patch_offset(ctx);
1230 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1231
1232 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1233 }
1234
1235 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1236 LLVMTypeRef type,
1237 LLVMValueRef vertex_index,
1238 LLVMValueRef param_index,
1239 unsigned const_index,
1240 unsigned location,
1241 unsigned driver_location,
1242 unsigned component,
1243 unsigned num_components,
1244 bool is_patch,
1245 bool is_compact,
1246 bool load_input)
1247 {
1248 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1249 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1250 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1251 LLVMValueRef dw_addr, stride;
1252
1253 driver_location = driver_location / 4;
1254
1255 if (load_input) {
1256 stride = get_tcs_in_vertex_dw_stride(ctx);
1257 dw_addr = get_tcs_in_current_patch_offset(ctx);
1258 } else {
1259 if (is_patch) {
1260 stride = NULL;
1261 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1262 } else {
1263 stride = get_tcs_out_vertex_dw_stride(ctx);
1264 dw_addr = get_tcs_out_current_patch_offset(ctx);
1265 }
1266 }
1267
1268 if (param_index) {
1269 /* Add the constant index to the indirect index */
1270 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1271 LLVMConstInt(ctx->i32, const_index, 0), "");
1272 } else {
1273 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1274 }
1275
1276 ubyte *names;
1277 ubyte *indices;
1278 if (load_input) {
1279 names = info->input_semantic_name;
1280 indices = info->input_semantic_index;
1281 } else {
1282 names = info->output_semantic_name;
1283 indices = info->output_semantic_index;
1284 }
1285
1286 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1287 vertex_index, param_index,
1288 driver_location,
1289 names, indices,
1290 is_patch);
1291
1292 LLVMValueRef value[4];
1293 for (unsigned i = 0; i < num_components + component; i++) {
1294 unsigned offset = i;
1295 if (llvm_type_is_64bit(ctx, type))
1296 offset *= 2;
1297
1298 value[i] = lds_load(bld_base, type, offset, dw_addr);
1299 }
1300
1301 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1302 }
1303
1304 static LLVMValueRef fetch_output_tcs(
1305 struct lp_build_tgsi_context *bld_base,
1306 const struct tgsi_full_src_register *reg,
1307 enum tgsi_opcode_type type, unsigned swizzle)
1308 {
1309 struct si_shader_context *ctx = si_shader_context(bld_base);
1310 LLVMValueRef dw_addr, stride;
1311
1312 if (reg->Register.Dimension) {
1313 stride = get_tcs_out_vertex_dw_stride(ctx);
1314 dw_addr = get_tcs_out_current_patch_offset(ctx);
1315 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1316 } else {
1317 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1318 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1319 }
1320
1321 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1322 }
1323
1324 static LLVMValueRef fetch_input_tes(
1325 struct lp_build_tgsi_context *bld_base,
1326 const struct tgsi_full_src_register *reg,
1327 enum tgsi_opcode_type type, unsigned swizzle)
1328 {
1329 struct si_shader_context *ctx = si_shader_context(bld_base);
1330 LLVMValueRef base, addr;
1331
1332 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1333 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1334
1335 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1336 ctx->tess_offchip_ring, base, addr, true);
1337 }
1338
1339 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1340 LLVMTypeRef type,
1341 LLVMValueRef vertex_index,
1342 LLVMValueRef param_index,
1343 unsigned const_index,
1344 unsigned location,
1345 unsigned driver_location,
1346 unsigned component,
1347 unsigned num_components,
1348 bool is_patch,
1349 bool is_compact,
1350 bool load_input)
1351 {
1352 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1353 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1354 LLVMValueRef base, addr;
1355
1356 driver_location = driver_location / 4;
1357
1358 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1359
1360 if (param_index) {
1361 /* Add the constant index to the indirect index */
1362 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1363 LLVMConstInt(ctx->i32, const_index, 0), "");
1364 } else {
1365 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1366 }
1367
1368 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1369 param_index, driver_location,
1370 info->input_semantic_name,
1371 info->input_semantic_index,
1372 is_patch);
1373
1374 /* TODO: This will generate rather ordinary llvm code, although it
1375 * should be easy for the optimiser to fix up. In future we might want
1376 * to refactor buffer_load(), but for now this maximises code sharing
1377 * between the NIR and TGSI backends.
1378 */
1379 LLVMValueRef value[4];
1380 for (unsigned i = component; i < num_components + component; i++) {
1381 unsigned offset = i;
1382 if (llvm_type_is_64bit(ctx, type))
1383 offset *= 2;
1384
1385 value[i] = buffer_load(&ctx->bld_base, type, offset,
1386 ctx->tess_offchip_ring, base, addr, true);
1387 }
1388
1389 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1390 }
1391
1392 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1393 const struct tgsi_full_instruction *inst,
1394 const struct tgsi_opcode_info *info,
1395 unsigned index,
1396 LLVMValueRef dst[4])
1397 {
1398 struct si_shader_context *ctx = si_shader_context(bld_base);
1399 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1400 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1401 unsigned chan_index;
1402 LLVMValueRef dw_addr, stride;
1403 LLVMValueRef buffer, base, buf_addr;
1404 LLVMValueRef values[4];
1405 bool skip_lds_store;
1406 bool is_tess_factor = false, is_tess_inner = false;
1407
1408 /* Only handle per-patch and per-vertex outputs here.
1409 * Vectors will be lowered to scalars and this function will be called again.
1410 */
1411 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1412 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1413 si_llvm_emit_store(bld_base, inst, info, index, dst);
1414 return;
1415 }
1416
1417 if (reg->Register.Dimension) {
1418 stride = get_tcs_out_vertex_dw_stride(ctx);
1419 dw_addr = get_tcs_out_current_patch_offset(ctx);
1420 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1421 skip_lds_store = !sh_info->reads_pervertex_outputs;
1422 } else {
1423 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1424 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1425 skip_lds_store = !sh_info->reads_perpatch_outputs;
1426
1427 if (!reg->Register.Indirect) {
1428 int name = sh_info->output_semantic_name[reg->Register.Index];
1429
1430 /* Always write tess factors into LDS for the TCS epilog. */
1431 if (name == TGSI_SEMANTIC_TESSINNER ||
1432 name == TGSI_SEMANTIC_TESSOUTER) {
1433 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1434 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1435 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1436 is_tess_factor = true;
1437 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1438 }
1439 }
1440 }
1441
1442 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1443
1444 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1445 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1446
1447 uint32_t writemask = reg->Register.WriteMask;
1448 while (writemask) {
1449 chan_index = u_bit_scan(&writemask);
1450 LLVMValueRef value = dst[chan_index];
1451
1452 if (inst->Instruction.Saturate)
1453 value = ac_build_clamp(&ctx->ac, value);
1454
1455 /* Skip LDS stores if there is no LDS read of this output. */
1456 if (!skip_lds_store)
1457 lds_store(ctx, chan_index, dw_addr, value);
1458
1459 value = ac_to_integer(&ctx->ac, value);
1460 values[chan_index] = value;
1461
1462 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1463 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1464 buf_addr, base,
1465 4 * chan_index, 1, 0, true, false);
1466 }
1467
1468 /* Write tess factors into VGPRs for the epilog. */
1469 if (is_tess_factor &&
1470 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1471 if (!is_tess_inner) {
1472 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1473 ctx->invoc0_tess_factors[chan_index]);
1474 } else if (chan_index < 2) {
1475 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1476 ctx->invoc0_tess_factors[4 + chan_index]);
1477 }
1478 }
1479 }
1480
1481 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1482 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1483 values, 4);
1484 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1485 base, 0, 1, 0, true, false);
1486 }
1487 }
1488
1489 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1490 LLVMValueRef vertex_index,
1491 LLVMValueRef param_index,
1492 unsigned const_index,
1493 unsigned location,
1494 unsigned driver_location,
1495 LLVMValueRef src,
1496 unsigned component,
1497 bool is_patch,
1498 bool is_compact,
1499 unsigned writemask)
1500 {
1501 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1502 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1503 LLVMValueRef dw_addr, stride;
1504 LLVMValueRef buffer, base, addr;
1505 LLVMValueRef values[4];
1506 bool skip_lds_store;
1507 bool is_tess_factor = false, is_tess_inner = false;
1508
1509 driver_location = driver_location / 4;
1510
1511 if (param_index) {
1512 /* Add the constant index to the indirect index */
1513 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1514 LLVMConstInt(ctx->i32, const_index, 0), "");
1515 } else {
1516 if (const_index != 0)
1517 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1518 }
1519
1520 if (!is_patch) {
1521 stride = get_tcs_out_vertex_dw_stride(ctx);
1522 dw_addr = get_tcs_out_current_patch_offset(ctx);
1523 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1524 vertex_index, param_index,
1525 driver_location,
1526 info->output_semantic_name,
1527 info->output_semantic_index,
1528 is_patch);
1529
1530 skip_lds_store = !info->reads_pervertex_outputs;
1531 } else {
1532 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1533 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1534 vertex_index, param_index,
1535 driver_location,
1536 info->output_semantic_name,
1537 info->output_semantic_index,
1538 is_patch);
1539
1540 skip_lds_store = !info->reads_perpatch_outputs;
1541
1542 if (!param_index) {
1543 int name = info->output_semantic_name[driver_location];
1544
1545 /* Always write tess factors into LDS for the TCS epilog. */
1546 if (name == TGSI_SEMANTIC_TESSINNER ||
1547 name == TGSI_SEMANTIC_TESSOUTER) {
1548 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1549 skip_lds_store = !info->reads_tessfactor_outputs &&
1550 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1551 is_tess_factor = true;
1552 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1553 }
1554 }
1555 }
1556
1557 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1558
1559 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1560
1561 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1562 param_index, driver_location,
1563 info->output_semantic_name,
1564 info->output_semantic_index,
1565 is_patch);
1566
1567 for (unsigned chan = 0; chan < 4; chan++) {
1568 if (!(writemask & (1 << chan)))
1569 continue;
1570 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1571
1572 /* Skip LDS stores if there is no LDS read of this output. */
1573 if (!skip_lds_store)
1574 lds_store(ctx, chan, dw_addr, value);
1575
1576 value = ac_to_integer(&ctx->ac, value);
1577 values[chan] = value;
1578
1579 if (writemask != 0xF && !is_tess_factor) {
1580 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1581 addr, base,
1582 4 * chan, 1, 0, true, false);
1583 }
1584
1585 /* Write tess factors into VGPRs for the epilog. */
1586 if (is_tess_factor &&
1587 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1588 if (!is_tess_inner) {
1589 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1590 ctx->invoc0_tess_factors[chan]);
1591 } else if (chan < 2) {
1592 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1593 ctx->invoc0_tess_factors[4 + chan]);
1594 }
1595 }
1596 }
1597
1598 if (writemask == 0xF && !is_tess_factor) {
1599 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1600 values, 4);
1601 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1602 base, 0, 1, 0, true, false);
1603 }
1604 }
1605
1606 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1607 unsigned input_index,
1608 unsigned vtx_offset_param,
1609 LLVMTypeRef type,
1610 unsigned swizzle)
1611 {
1612 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1613 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1614 struct si_shader *shader = ctx->shader;
1615 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1616 LLVMValueRef vtx_offset, soffset;
1617 struct tgsi_shader_info *info = &shader->selector->info;
1618 unsigned semantic_name = info->input_semantic_name[input_index];
1619 unsigned semantic_index = info->input_semantic_index[input_index];
1620 unsigned param;
1621 LLVMValueRef value;
1622
1623 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1624
1625 /* GFX9 has the ESGS ring in LDS. */
1626 if (ctx->screen->info.chip_class >= GFX9) {
1627 unsigned index = vtx_offset_param;
1628
1629 switch (index / 2) {
1630 case 0:
1631 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx01_offset,
1632 index % 2 ? 16 : 0, 16);
1633 break;
1634 case 1:
1635 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx23_offset,
1636 index % 2 ? 16 : 0, 16);
1637 break;
1638 case 2:
1639 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx45_offset,
1640 index % 2 ? 16 : 0, 16);
1641 break;
1642 default:
1643 assert(0);
1644 return NULL;
1645 }
1646
1647 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1648 LLVMConstInt(ctx->i32, param * 4, 0), "");
1649 return lds_load(bld_base, type, swizzle, vtx_offset);
1650 }
1651
1652 /* GFX6: input load from the ESGS ring in memory. */
1653 if (swizzle == ~0) {
1654 LLVMValueRef values[TGSI_NUM_CHANNELS];
1655 unsigned chan;
1656 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1657 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1658 type, chan);
1659 }
1660 return lp_build_gather_values(&ctx->gallivm, values,
1661 TGSI_NUM_CHANNELS);
1662 }
1663
1664 /* Get the vertex offset parameter on GFX6. */
1665 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1666
1667 vtx_offset = lp_build_mul_imm(uint, gs_vtx_offset, 4);
1668
1669 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1670
1671 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1672 vtx_offset, soffset, 0, 1, 0, true, false);
1673 if (llvm_type_is_64bit(ctx, type)) {
1674 LLVMValueRef value2;
1675 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1676
1677 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1678 ctx->i32_0, vtx_offset, soffset,
1679 0, 1, 0, true, false);
1680 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1681 }
1682 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1683 }
1684
1685 static LLVMValueRef fetch_input_gs(
1686 struct lp_build_tgsi_context *bld_base,
1687 const struct tgsi_full_src_register *reg,
1688 enum tgsi_opcode_type type,
1689 unsigned swizzle)
1690 {
1691 struct si_shader_context *ctx = si_shader_context(bld_base);
1692 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1693
1694 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1695 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1696 return get_primitive_id(ctx, swizzle);
1697
1698 if (!reg->Register.Dimension)
1699 return NULL;
1700
1701 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1702 reg->Dimension.Index,
1703 tgsi2llvmtype(bld_base, type),
1704 swizzle);
1705 }
1706
1707 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1708 {
1709 switch (interpolate) {
1710 case TGSI_INTERPOLATE_CONSTANT:
1711 return 0;
1712
1713 case TGSI_INTERPOLATE_LINEAR:
1714 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1715 return SI_PARAM_LINEAR_SAMPLE;
1716 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1717 return SI_PARAM_LINEAR_CENTROID;
1718 else
1719 return SI_PARAM_LINEAR_CENTER;
1720 break;
1721 case TGSI_INTERPOLATE_COLOR:
1722 case TGSI_INTERPOLATE_PERSPECTIVE:
1723 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1724 return SI_PARAM_PERSP_SAMPLE;
1725 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1726 return SI_PARAM_PERSP_CENTROID;
1727 else
1728 return SI_PARAM_PERSP_CENTER;
1729 break;
1730 default:
1731 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1732 return -1;
1733 }
1734 }
1735
1736 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1737 unsigned attr_index, unsigned chan,
1738 LLVMValueRef prim_mask,
1739 LLVMValueRef i, LLVMValueRef j)
1740 {
1741 if (i || j) {
1742 return ac_build_fs_interp(&ctx->ac,
1743 LLVMConstInt(ctx->i32, chan, 0),
1744 LLVMConstInt(ctx->i32, attr_index, 0),
1745 prim_mask, i, j);
1746 }
1747 return ac_build_fs_interp_mov(&ctx->ac,
1748 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1749 LLVMConstInt(ctx->i32, chan, 0),
1750 LLVMConstInt(ctx->i32, attr_index, 0),
1751 prim_mask);
1752 }
1753
1754 /**
1755 * Interpolate a fragment shader input.
1756 *
1757 * @param ctx context
1758 * @param input_index index of the input in hardware
1759 * @param semantic_name TGSI_SEMANTIC_*
1760 * @param semantic_index semantic index
1761 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1762 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1763 * @param interp_param interpolation weights (i,j)
1764 * @param prim_mask SI_PARAM_PRIM_MASK
1765 * @param face SI_PARAM_FRONT_FACE
1766 * @param result the return value (4 components)
1767 */
1768 static void interp_fs_input(struct si_shader_context *ctx,
1769 unsigned input_index,
1770 unsigned semantic_name,
1771 unsigned semantic_index,
1772 unsigned num_interp_inputs,
1773 unsigned colors_read_mask,
1774 LLVMValueRef interp_param,
1775 LLVMValueRef prim_mask,
1776 LLVMValueRef face,
1777 LLVMValueRef result[4])
1778 {
1779 LLVMValueRef i = NULL, j = NULL;
1780 unsigned chan;
1781
1782 /* fs.constant returns the param from the middle vertex, so it's not
1783 * really useful for flat shading. It's meant to be used for custom
1784 * interpolation (but the intrinsic can't fetch from the other two
1785 * vertices).
1786 *
1787 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1788 * to do the right thing. The only reason we use fs.constant is that
1789 * fs.interp cannot be used on integers, because they can be equal
1790 * to NaN.
1791 *
1792 * When interp is false we will use fs.constant or for newer llvm,
1793 * amdgcn.interp.mov.
1794 */
1795 bool interp = interp_param != NULL;
1796
1797 if (interp) {
1798 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1799 LLVMVectorType(ctx->f32, 2), "");
1800
1801 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1802 ctx->i32_0, "");
1803 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1804 ctx->i32_1, "");
1805 }
1806
1807 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1808 ctx->shader->key.part.ps.prolog.color_two_side) {
1809 LLVMValueRef is_face_positive;
1810
1811 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1812 * otherwise it's at offset "num_inputs".
1813 */
1814 unsigned back_attr_offset = num_interp_inputs;
1815 if (semantic_index == 1 && colors_read_mask & 0xf)
1816 back_attr_offset += 1;
1817
1818 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1819 face, ctx->i32_0, "");
1820
1821 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1822 LLVMValueRef front, back;
1823
1824 front = si_build_fs_interp(ctx,
1825 input_index, chan,
1826 prim_mask, i, j);
1827 back = si_build_fs_interp(ctx,
1828 back_attr_offset, chan,
1829 prim_mask, i, j);
1830
1831 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1832 is_face_positive,
1833 front,
1834 back,
1835 "");
1836 }
1837 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1838 result[0] = si_build_fs_interp(ctx, input_index,
1839 0, prim_mask, i, j);
1840 result[1] =
1841 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1842 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1843 } else {
1844 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1845 result[chan] = si_build_fs_interp(ctx,
1846 input_index, chan,
1847 prim_mask, i, j);
1848 }
1849 }
1850 }
1851
1852 void si_llvm_load_input_fs(
1853 struct si_shader_context *ctx,
1854 unsigned input_index,
1855 LLVMValueRef out[4])
1856 {
1857 struct lp_build_context *base = &ctx->bld_base.base;
1858 struct si_shader *shader = ctx->shader;
1859 struct tgsi_shader_info *info = &shader->selector->info;
1860 LLVMValueRef main_fn = ctx->main_fn;
1861 LLVMValueRef interp_param = NULL;
1862 int interp_param_idx;
1863 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1864 unsigned semantic_index = info->input_semantic_index[input_index];
1865 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1866 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1867
1868 /* Get colors from input VGPRs (set by the prolog). */
1869 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1870 unsigned colors_read = shader->selector->info.colors_read;
1871 unsigned mask = colors_read >> (semantic_index * 4);
1872 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1873 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1874
1875 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1876 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1877 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1878 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1879 return;
1880 }
1881
1882 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1883 if (interp_param_idx == -1)
1884 return;
1885 else if (interp_param_idx) {
1886 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1887 }
1888
1889 interp_fs_input(ctx, input_index, semantic_name,
1890 semantic_index, 0, /* this param is unused */
1891 shader->selector->info.colors_read, interp_param,
1892 ctx->abi.prim_mask,
1893 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1894 &out[0]);
1895 }
1896
1897 static void declare_input_fs(
1898 struct si_shader_context *ctx,
1899 unsigned input_index,
1900 const struct tgsi_full_declaration *decl,
1901 LLVMValueRef out[4])
1902 {
1903 si_llvm_load_input_fs(ctx, input_index, out);
1904 }
1905
1906 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1907 {
1908 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1909 }
1910
1911 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1912 {
1913 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1914
1915 LLVMValueRef values[3];
1916 LLVMValueRef result;
1917 unsigned i;
1918 unsigned *properties = ctx->shader->selector->info.properties;
1919
1920 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1921 unsigned sizes[3] = {
1922 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1923 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1924 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1925 };
1926
1927 for (i = 0; i < 3; ++i)
1928 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1929
1930 result = lp_build_gather_values(&ctx->gallivm, values, 3);
1931 } else {
1932 result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1933 }
1934
1935 return result;
1936 }
1937
1938 /**
1939 * Load a dword from a constant buffer.
1940 */
1941 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1942 LLVMValueRef resource,
1943 LLVMValueRef offset)
1944 {
1945 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1946 0, 0, 0, true, true);
1947 }
1948
1949 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1950 {
1951 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1952 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1953 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1954 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1955 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1956
1957 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1958 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1959 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1960
1961 LLVMValueRef pos[4] = {
1962 buffer_load_const(ctx, resource, offset0),
1963 buffer_load_const(ctx, resource, offset1),
1964 LLVMConstReal(ctx->f32, 0),
1965 LLVMConstReal(ctx->f32, 0)
1966 };
1967
1968 return lp_build_gather_values(&ctx->gallivm, pos, 4);
1969 }
1970
1971 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1972 {
1973 return abi->sample_coverage;
1974 }
1975
1976 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
1977 {
1978 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1979 struct lp_build_context *bld = &ctx->bld_base.base;
1980
1981 LLVMValueRef coord[4] = {
1982 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1983 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1984 ctx->ac.f32_0,
1985 ctx->ac.f32_0
1986 };
1987
1988 /* For triangles, the vector should be (u, v, 1-u-v). */
1989 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1990 PIPE_PRIM_TRIANGLES)
1991 coord[2] = lp_build_sub(bld, ctx->ac.f32_1,
1992 lp_build_add(bld, coord[0], coord[1]));
1993
1994 return lp_build_gather_values(&ctx->gallivm, coord, 4);
1995 }
1996
1997 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
1998 unsigned semantic_name)
1999 {
2000 LLVMValueRef base, addr;
2001
2002 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
2003
2004 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2005 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
2006 LLVMConstInt(ctx->i32, param, 0));
2007
2008 return buffer_load(&ctx->bld_base, ctx->f32,
2009 ~0, ctx->tess_offchip_ring, base, addr, true);
2010
2011 }
2012
2013 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
2014 unsigned varying_id)
2015 {
2016 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2017 unsigned semantic_name;
2018
2019 switch (varying_id) {
2020 case VARYING_SLOT_TESS_LEVEL_INNER:
2021 semantic_name = TGSI_SEMANTIC_TESSINNER;
2022 break;
2023 case VARYING_SLOT_TESS_LEVEL_OUTER:
2024 semantic_name = TGSI_SEMANTIC_TESSOUTER;
2025 break;
2026 default:
2027 unreachable("unknown tess level");
2028 }
2029
2030 return load_tess_level(ctx, semantic_name);
2031
2032 }
2033
2034 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
2035 {
2036 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2037 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2038 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
2039 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
2040 return get_num_tcs_out_vertices(ctx);
2041 else
2042 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2043 }
2044
2045 void si_load_system_value(struct si_shader_context *ctx,
2046 unsigned index,
2047 const struct tgsi_full_declaration *decl)
2048 {
2049 LLVMValueRef value = 0;
2050
2051 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
2052
2053 switch (decl->Semantic.Name) {
2054 case TGSI_SEMANTIC_INSTANCEID:
2055 value = ctx->abi.instance_id;
2056 break;
2057
2058 case TGSI_SEMANTIC_VERTEXID:
2059 value = LLVMBuildAdd(ctx->ac.builder,
2060 ctx->abi.vertex_id,
2061 ctx->abi.base_vertex, "");
2062 break;
2063
2064 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2065 /* Unused. Clarify the meaning in indexed vs. non-indexed
2066 * draws if this is ever used again. */
2067 assert(false);
2068 break;
2069
2070 case TGSI_SEMANTIC_BASEVERTEX:
2071 {
2072 /* For non-indexed draws, the base vertex set by the driver
2073 * (for direct draws) or the CP (for indirect draws) is the
2074 * first vertex ID, but GLSL expects 0 to be returned.
2075 */
2076 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
2077 LLVMValueRef indexed;
2078
2079 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
2080 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
2081
2082 value = LLVMBuildSelect(ctx->ac.builder, indexed,
2083 ctx->abi.base_vertex, ctx->i32_0, "");
2084 break;
2085 }
2086
2087 case TGSI_SEMANTIC_BASEINSTANCE:
2088 value = ctx->abi.start_instance;
2089 break;
2090
2091 case TGSI_SEMANTIC_DRAWID:
2092 value = ctx->abi.draw_id;
2093 break;
2094
2095 case TGSI_SEMANTIC_INVOCATIONID:
2096 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2097 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2098 else if (ctx->type == PIPE_SHADER_GEOMETRY)
2099 value = ctx->abi.gs_invocation_id;
2100 else
2101 assert(!"INVOCATIONID not implemented");
2102 break;
2103
2104 case TGSI_SEMANTIC_POSITION:
2105 {
2106 LLVMValueRef pos[4] = {
2107 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2108 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2109 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2110 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
2111 LLVMGetParam(ctx->main_fn,
2112 SI_PARAM_POS_W_FLOAT)),
2113 };
2114 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
2115 break;
2116 }
2117
2118 case TGSI_SEMANTIC_FACE:
2119 value = ctx->abi.front_face;
2120 break;
2121
2122 case TGSI_SEMANTIC_SAMPLEID:
2123 value = get_sample_id(ctx);
2124 break;
2125
2126 case TGSI_SEMANTIC_SAMPLEPOS: {
2127 LLVMValueRef pos[4] = {
2128 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2129 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2130 LLVMConstReal(ctx->f32, 0),
2131 LLVMConstReal(ctx->f32, 0)
2132 };
2133 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
2134 TGSI_OPCODE_FRC, pos[0]);
2135 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
2136 TGSI_OPCODE_FRC, pos[1]);
2137 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
2138 break;
2139 }
2140
2141 case TGSI_SEMANTIC_SAMPLEMASK:
2142 /* This can only occur with the OpenGL Core profile, which
2143 * doesn't support smoothing.
2144 */
2145 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2146 break;
2147
2148 case TGSI_SEMANTIC_TESSCOORD:
2149 value = si_load_tess_coord(&ctx->abi);
2150 break;
2151
2152 case TGSI_SEMANTIC_VERTICESIN:
2153 value = si_load_patch_vertices_in(&ctx->abi);
2154 break;
2155
2156 case TGSI_SEMANTIC_TESSINNER:
2157 case TGSI_SEMANTIC_TESSOUTER:
2158 value = load_tess_level(ctx, decl->Semantic.Name);
2159 break;
2160
2161 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
2162 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
2163 {
2164 LLVMValueRef buf, slot, val[4];
2165 int i, offset;
2166
2167 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
2168 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2169 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
2170 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
2171
2172 for (i = 0; i < 4; i++)
2173 val[i] = buffer_load_const(ctx, buf,
2174 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
2175 value = lp_build_gather_values(&ctx->gallivm, val, 4);
2176 break;
2177 }
2178
2179 case TGSI_SEMANTIC_PRIMID:
2180 value = get_primitive_id(ctx, 0);
2181 break;
2182
2183 case TGSI_SEMANTIC_GRID_SIZE:
2184 value = ctx->abi.num_work_groups;
2185 break;
2186
2187 case TGSI_SEMANTIC_BLOCK_SIZE:
2188 value = get_block_size(&ctx->abi);
2189 break;
2190
2191 case TGSI_SEMANTIC_BLOCK_ID:
2192 {
2193 LLVMValueRef values[3];
2194
2195 for (int i = 0; i < 3; i++) {
2196 values[i] = ctx->i32_0;
2197 if (ctx->abi.workgroup_ids[i]) {
2198 values[i] = ctx->abi.workgroup_ids[i];
2199 }
2200 }
2201 value = lp_build_gather_values(&ctx->gallivm, values, 3);
2202 break;
2203 }
2204
2205 case TGSI_SEMANTIC_THREAD_ID:
2206 value = ctx->abi.local_invocation_ids;
2207 break;
2208
2209 case TGSI_SEMANTIC_HELPER_INVOCATION:
2210 value = lp_build_intrinsic(ctx->ac.builder,
2211 "llvm.amdgcn.ps.live",
2212 ctx->i1, NULL, 0,
2213 LP_FUNC_ATTR_READNONE);
2214 value = LLVMBuildNot(ctx->ac.builder, value, "");
2215 value = LLVMBuildSExt(ctx->ac.builder, value, ctx->i32, "");
2216 break;
2217
2218 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2219 value = LLVMConstInt(ctx->i32, 64, 0);
2220 break;
2221
2222 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2223 value = ac_get_thread_id(&ctx->ac);
2224 break;
2225
2226 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2227 {
2228 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2229 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2230 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
2231 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2232 break;
2233 }
2234
2235 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2236 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2237 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2238 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2239 {
2240 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2241 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2242 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2243 /* All bits set except LSB */
2244 value = LLVMConstInt(ctx->i64, -2, 0);
2245 } else {
2246 /* All bits set */
2247 value = LLVMConstInt(ctx->i64, -1, 0);
2248 }
2249 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2250 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2251 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2252 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2253 value = LLVMBuildNot(ctx->ac.builder, value, "");
2254 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2255 break;
2256 }
2257
2258 default:
2259 assert(!"unknown system value");
2260 return;
2261 }
2262
2263 ctx->system_values[index] = value;
2264 }
2265
2266 void si_declare_compute_memory(struct si_shader_context *ctx)
2267 {
2268 struct si_shader_selector *sel = ctx->shader->selector;
2269
2270 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_LOCAL_ADDR_SPACE);
2271 LLVMValueRef var;
2272
2273 assert(!ctx->ac.lds);
2274
2275 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2276 LLVMArrayType(ctx->i8, sel->local_size),
2277 "compute_lds",
2278 AC_LOCAL_ADDR_SPACE);
2279 LLVMSetAlignment(var, 4);
2280
2281 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2282 }
2283
2284 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
2285 const struct tgsi_full_declaration *decl)
2286 {
2287 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2288 assert(decl->Range.First == decl->Range.Last);
2289
2290 si_declare_compute_memory(ctx);
2291 }
2292
2293 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2294 {
2295 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2296 ctx->param_const_and_shader_buffers);
2297
2298 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2299 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2300 }
2301
2302 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2303 {
2304 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2305 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2306
2307 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2308 index = LLVMBuildAdd(ctx->ac.builder, index,
2309 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2310
2311 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2312 }
2313
2314 static LLVMValueRef
2315 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2316 {
2317 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2318 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2319 ctx->param_const_and_shader_buffers);
2320
2321 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2322 index = LLVMBuildSub(ctx->ac.builder,
2323 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2324 index, "");
2325
2326 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2327 }
2328
2329 static LLVMValueRef fetch_constant(
2330 struct lp_build_tgsi_context *bld_base,
2331 const struct tgsi_full_src_register *reg,
2332 enum tgsi_opcode_type type,
2333 unsigned swizzle)
2334 {
2335 struct si_shader_context *ctx = si_shader_context(bld_base);
2336 struct si_shader_selector *sel = ctx->shader->selector;
2337 const struct tgsi_ind_register *ireg = &reg->Indirect;
2338 unsigned buf, idx;
2339
2340 LLVMValueRef addr, bufp;
2341
2342 if (swizzle == LP_CHAN_ALL) {
2343 unsigned chan;
2344 LLVMValueRef values[4];
2345 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2346 values[chan] = fetch_constant(bld_base, reg, type, chan);
2347
2348 return lp_build_gather_values(&ctx->gallivm, values, 4);
2349 }
2350
2351 /* Split 64-bit loads. */
2352 if (tgsi_type_is_64bit(type)) {
2353 LLVMValueRef lo, hi;
2354
2355 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2356 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle + 1);
2357 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2358 lo, hi);
2359 }
2360
2361 idx = reg->Register.Index * 4 + swizzle;
2362 if (reg->Register.Indirect) {
2363 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2364 } else {
2365 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2366 }
2367
2368 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2369 if (sel->info.const_buffers_declared == 1 &&
2370 sel->info.shader_buffers_declared == 0) {
2371 LLVMValueRef ptr =
2372 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2373
2374 /* This enables use of s_load_dword and flat_load_dword for const buffer 0
2375 * loads, and up to x4 load opcode merging. However, it leads to horrible
2376 * code reducing SIMD wave occupancy from 8 to 2 in many cases.
2377 *
2378 * Using s_buffer_load_dword (x1) seems to be the best option right now.
2379 *
2380 * LLVM 5.0 on SI doesn't insert a required s_nop between SALU setting
2381 * a descriptor and s_buffer_load_dword using it, so we can't expand
2382 * the pointer into a full descriptor like below. We have to use
2383 * s_load_dword instead. The only case when LLVM 5.0 would select
2384 * s_buffer_load_dword (that we have to prevent) is when we use use
2385 * a literal offset where we don't need bounds checking.
2386 */
2387 if (ctx->screen->info.chip_class == SI &&
2388 HAVE_LLVM < 0x0600 &&
2389 !reg->Register.Indirect) {
2390 addr = LLVMBuildLShr(ctx->ac.builder, addr, LLVMConstInt(ctx->i32, 2, 0), "");
2391 LLVMValueRef result = ac_build_load_invariant(&ctx->ac, ptr, addr);
2392 return bitcast(bld_base, type, result);
2393 }
2394
2395 /* Do the bounds checking with a descriptor, because
2396 * doing computation and manual bounds checking of 64-bit
2397 * addresses generates horrible VALU code with very high
2398 * VGPR usage and very low SIMD occupancy.
2399 */
2400 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->i64, "");
2401 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ctx->v2i32, "");
2402
2403 LLVMValueRef desc_elems[] = {
2404 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_0, ""),
2405 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_1, ""),
2406 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2407 LLVMConstInt(ctx->i32,
2408 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2409 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2410 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2411 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2412 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2413 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2414 };
2415 LLVMValueRef desc = ac_build_gather_values(&ctx->ac, desc_elems, 4);
2416 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2417 return bitcast(bld_base, type, result);
2418 }
2419
2420 assert(reg->Register.Dimension);
2421 buf = reg->Dimension.Index;
2422
2423 if (reg->Dimension.Indirect) {
2424 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2425 LLVMValueRef index;
2426 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2427 reg->Dimension.Index,
2428 ctx->num_const_buffers);
2429 index = LLVMBuildAdd(ctx->ac.builder, index,
2430 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2431 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2432 } else
2433 bufp = load_const_buffer_desc(ctx, buf);
2434
2435 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2436 }
2437
2438 /* Initialize arguments for the shader export intrinsic */
2439 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2440 LLVMValueRef *values,
2441 unsigned target,
2442 struct ac_export_args *args)
2443 {
2444 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2445 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2446 unsigned chan;
2447 bool is_int8, is_int10;
2448
2449 /* Default is 0xf. Adjusted below depending on the format. */
2450 args->enabled_channels = 0xf; /* writemask */
2451
2452 /* Specify whether the EXEC mask represents the valid mask */
2453 args->valid_mask = 0;
2454
2455 /* Specify whether this is the last export */
2456 args->done = 0;
2457
2458 /* Specify the target we are exporting */
2459 args->target = target;
2460
2461 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2462 const struct si_shader_key *key = &ctx->shader->key;
2463 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2464 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2465
2466 assert(cbuf >= 0 && cbuf < 8);
2467 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2468 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2469 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2470 }
2471
2472 args->compr = false;
2473 args->out[0] = f32undef;
2474 args->out[1] = f32undef;
2475 args->out[2] = f32undef;
2476 args->out[3] = f32undef;
2477
2478 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2479 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2480 unsigned bits, bool hi) = NULL;
2481
2482 switch (spi_shader_col_format) {
2483 case V_028714_SPI_SHADER_ZERO:
2484 args->enabled_channels = 0; /* writemask */
2485 args->target = V_008DFC_SQ_EXP_NULL;
2486 break;
2487
2488 case V_028714_SPI_SHADER_32_R:
2489 args->enabled_channels = 1; /* writemask */
2490 args->out[0] = values[0];
2491 break;
2492
2493 case V_028714_SPI_SHADER_32_GR:
2494 args->enabled_channels = 0x3; /* writemask */
2495 args->out[0] = values[0];
2496 args->out[1] = values[1];
2497 break;
2498
2499 case V_028714_SPI_SHADER_32_AR:
2500 args->enabled_channels = 0x9; /* writemask */
2501 args->out[0] = values[0];
2502 args->out[3] = values[3];
2503 break;
2504
2505 case V_028714_SPI_SHADER_FP16_ABGR:
2506 packf = ac_build_cvt_pkrtz_f16;
2507 break;
2508
2509 case V_028714_SPI_SHADER_UNORM16_ABGR:
2510 packf = ac_build_cvt_pknorm_u16;
2511 break;
2512
2513 case V_028714_SPI_SHADER_SNORM16_ABGR:
2514 packf = ac_build_cvt_pknorm_i16;
2515 break;
2516
2517 case V_028714_SPI_SHADER_UINT16_ABGR:
2518 packi = ac_build_cvt_pk_u16;
2519 break;
2520
2521 case V_028714_SPI_SHADER_SINT16_ABGR:
2522 packi = ac_build_cvt_pk_i16;
2523 break;
2524
2525 case V_028714_SPI_SHADER_32_ABGR:
2526 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2527 break;
2528 }
2529
2530 /* Pack f16 or norm_i16/u16. */
2531 if (packf) {
2532 for (chan = 0; chan < 2; chan++) {
2533 LLVMValueRef pack_args[2] = {
2534 values[2 * chan],
2535 values[2 * chan + 1]
2536 };
2537 LLVMValueRef packed;
2538
2539 packed = packf(&ctx->ac, pack_args);
2540 args->out[chan] = ac_to_float(&ctx->ac, packed);
2541 }
2542 args->compr = 1; /* COMPR flag */
2543 }
2544 /* Pack i16/u16. */
2545 if (packi) {
2546 for (chan = 0; chan < 2; chan++) {
2547 LLVMValueRef pack_args[2] = {
2548 ac_to_integer(&ctx->ac, values[2 * chan]),
2549 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2550 };
2551 LLVMValueRef packed;
2552
2553 packed = packi(&ctx->ac, pack_args,
2554 is_int8 ? 8 : is_int10 ? 10 : 16,
2555 chan == 1);
2556 args->out[chan] = ac_to_float(&ctx->ac, packed);
2557 }
2558 args->compr = 1; /* COMPR flag */
2559 }
2560 }
2561
2562 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2563 LLVMValueRef alpha)
2564 {
2565 struct si_shader_context *ctx = si_shader_context(bld_base);
2566
2567 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2568 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2569 [PIPE_FUNC_LESS] = LLVMRealOLT,
2570 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2571 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2572 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2573 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2574 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2575 };
2576 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2577 assert(cond);
2578
2579 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2580 SI_PARAM_ALPHA_REF);
2581 LLVMValueRef alpha_pass =
2582 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2583 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2584 } else {
2585 ac_build_kill_if_false(&ctx->ac, LLVMConstInt(ctx->i1, 0, 0));
2586 }
2587 }
2588
2589 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2590 LLVMValueRef alpha,
2591 unsigned samplemask_param)
2592 {
2593 struct si_shader_context *ctx = si_shader_context(bld_base);
2594 LLVMValueRef coverage;
2595
2596 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2597 coverage = LLVMGetParam(ctx->main_fn,
2598 samplemask_param);
2599 coverage = ac_to_integer(&ctx->ac, coverage);
2600
2601 coverage = lp_build_intrinsic(ctx->ac.builder, "llvm.ctpop.i32",
2602 ctx->i32,
2603 &coverage, 1, LP_FUNC_ATTR_READNONE);
2604
2605 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2606 ctx->f32, "");
2607
2608 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2609 LLVMConstReal(ctx->f32,
2610 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2611
2612 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2613 }
2614
2615 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2616 struct ac_export_args *pos, LLVMValueRef *out_elts)
2617 {
2618 unsigned reg_index;
2619 unsigned chan;
2620 unsigned const_chan;
2621 LLVMValueRef base_elt;
2622 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2623 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2624 SI_VS_CONST_CLIP_PLANES, 0);
2625 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2626
2627 for (reg_index = 0; reg_index < 2; reg_index ++) {
2628 struct ac_export_args *args = &pos[2 + reg_index];
2629
2630 args->out[0] =
2631 args->out[1] =
2632 args->out[2] =
2633 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2634
2635 /* Compute dot products of position and user clip plane vectors */
2636 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2637 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2638 LLVMValueRef addr =
2639 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2640 const_chan) * 4, 0);
2641 base_elt = buffer_load_const(ctx, const_resource,
2642 addr);
2643 args->out[chan] =
2644 lp_build_add(&ctx->bld_base.base, args->out[chan],
2645 lp_build_mul(&ctx->bld_base.base, base_elt,
2646 out_elts[const_chan]));
2647 }
2648 }
2649
2650 args->enabled_channels = 0xf;
2651 args->valid_mask = 0;
2652 args->done = 0;
2653 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2654 args->compr = 0;
2655 }
2656 }
2657
2658 static void si_dump_streamout(struct pipe_stream_output_info *so)
2659 {
2660 unsigned i;
2661
2662 if (so->num_outputs)
2663 fprintf(stderr, "STREAMOUT\n");
2664
2665 for (i = 0; i < so->num_outputs; i++) {
2666 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2667 so->output[i].start_component;
2668 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2669 i, so->output[i].output_buffer,
2670 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2671 so->output[i].register_index,
2672 mask & 1 ? "x" : "",
2673 mask & 2 ? "y" : "",
2674 mask & 4 ? "z" : "",
2675 mask & 8 ? "w" : "");
2676 }
2677 }
2678
2679 static void emit_streamout_output(struct si_shader_context *ctx,
2680 LLVMValueRef const *so_buffers,
2681 LLVMValueRef const *so_write_offsets,
2682 struct pipe_stream_output *stream_out,
2683 struct si_shader_output_values *shader_out)
2684 {
2685 unsigned buf_idx = stream_out->output_buffer;
2686 unsigned start = stream_out->start_component;
2687 unsigned num_comps = stream_out->num_components;
2688 LLVMValueRef out[4];
2689
2690 assert(num_comps && num_comps <= 4);
2691 if (!num_comps || num_comps > 4)
2692 return;
2693
2694 /* Load the output as int. */
2695 for (int j = 0; j < num_comps; j++) {
2696 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2697
2698 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2699 }
2700
2701 /* Pack the output. */
2702 LLVMValueRef vdata = NULL;
2703
2704 switch (num_comps) {
2705 case 1: /* as i32 */
2706 vdata = out[0];
2707 break;
2708 case 2: /* as v2i32 */
2709 case 3: /* as v4i32 (aligned to 4) */
2710 case 4: /* as v4i32 */
2711 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2712 for (int j = 0; j < num_comps; j++) {
2713 vdata = LLVMBuildInsertElement(ctx->ac.builder, vdata, out[j],
2714 LLVMConstInt(ctx->i32, j, 0), "");
2715 }
2716 break;
2717 }
2718
2719 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2720 vdata, num_comps,
2721 so_write_offsets[buf_idx],
2722 ctx->i32_0,
2723 stream_out->dst_offset * 4, 1, 1, true, false);
2724 }
2725
2726 /**
2727 * Write streamout data to buffers for vertex stream @p stream (different
2728 * vertex streams can occur for GS copy shaders).
2729 */
2730 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2731 struct si_shader_output_values *outputs,
2732 unsigned noutput, unsigned stream)
2733 {
2734 struct si_shader_selector *sel = ctx->shader->selector;
2735 struct pipe_stream_output_info *so = &sel->so;
2736 LLVMBuilderRef builder = ctx->ac.builder;
2737 int i;
2738 struct lp_build_if_state if_ctx;
2739
2740 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2741 LLVMValueRef so_vtx_count =
2742 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2743
2744 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2745
2746 /* can_emit = tid < so_vtx_count; */
2747 LLVMValueRef can_emit =
2748 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2749
2750 /* Emit the streamout code conditionally. This actually avoids
2751 * out-of-bounds buffer access. The hw tells us via the SGPR
2752 * (so_vtx_count) which threads are allowed to emit streamout data. */
2753 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2754 {
2755 /* The buffer offset is computed as follows:
2756 * ByteOffset = streamout_offset[buffer_id]*4 +
2757 * (streamout_write_index + thread_id)*stride[buffer_id] +
2758 * attrib_offset
2759 */
2760
2761 LLVMValueRef so_write_index =
2762 LLVMGetParam(ctx->main_fn,
2763 ctx->param_streamout_write_index);
2764
2765 /* Compute (streamout_write_index + thread_id). */
2766 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2767
2768 /* Load the descriptor and compute the write offset for each
2769 * enabled buffer. */
2770 LLVMValueRef so_write_offset[4] = {};
2771 LLVMValueRef so_buffers[4];
2772 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2773 ctx->param_rw_buffers);
2774
2775 for (i = 0; i < 4; i++) {
2776 if (!so->stride[i])
2777 continue;
2778
2779 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2780 SI_VS_STREAMOUT_BUF0 + i, 0);
2781
2782 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2783
2784 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2785 ctx->param_streamout_offset[i]);
2786 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2787
2788 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2789 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2790 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2791 }
2792
2793 /* Write streamout data. */
2794 for (i = 0; i < so->num_outputs; i++) {
2795 unsigned reg = so->output[i].register_index;
2796
2797 if (reg >= noutput)
2798 continue;
2799
2800 if (stream != so->output[i].stream)
2801 continue;
2802
2803 emit_streamout_output(ctx, so_buffers, so_write_offset,
2804 &so->output[i], &outputs[reg]);
2805 }
2806 }
2807 lp_build_endif(&if_ctx);
2808 }
2809
2810 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2811 LLVMValueRef *values)
2812 {
2813 struct ac_export_args args;
2814
2815 si_llvm_init_export_args(ctx, values,
2816 V_008DFC_SQ_EXP_PARAM + index, &args);
2817 ac_build_export(&ctx->ac, &args);
2818 }
2819
2820 static void si_build_param_exports(struct si_shader_context *ctx,
2821 struct si_shader_output_values *outputs,
2822 unsigned noutput)
2823 {
2824 struct si_shader *shader = ctx->shader;
2825 unsigned param_count = 0;
2826
2827 for (unsigned i = 0; i < noutput; i++) {
2828 unsigned semantic_name = outputs[i].semantic_name;
2829 unsigned semantic_index = outputs[i].semantic_index;
2830
2831 if (outputs[i].vertex_stream[0] != 0 &&
2832 outputs[i].vertex_stream[1] != 0 &&
2833 outputs[i].vertex_stream[2] != 0 &&
2834 outputs[i].vertex_stream[3] != 0)
2835 continue;
2836
2837 switch (semantic_name) {
2838 case TGSI_SEMANTIC_LAYER:
2839 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2840 case TGSI_SEMANTIC_CLIPDIST:
2841 case TGSI_SEMANTIC_COLOR:
2842 case TGSI_SEMANTIC_BCOLOR:
2843 case TGSI_SEMANTIC_PRIMID:
2844 case TGSI_SEMANTIC_FOG:
2845 case TGSI_SEMANTIC_TEXCOORD:
2846 case TGSI_SEMANTIC_GENERIC:
2847 break;
2848 default:
2849 continue;
2850 }
2851
2852 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2853 semantic_index < SI_MAX_IO_GENERIC) &&
2854 shader->key.opt.kill_outputs &
2855 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2856 continue;
2857
2858 si_export_param(ctx, param_count, outputs[i].values);
2859
2860 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2861 shader->info.vs_output_param_offset[i] = param_count++;
2862 }
2863
2864 shader->info.nr_param_exports = param_count;
2865 }
2866
2867 /* Generate export instructions for hardware VS shader stage */
2868 static void si_llvm_export_vs(struct si_shader_context *ctx,
2869 struct si_shader_output_values *outputs,
2870 unsigned noutput)
2871 {
2872 struct si_shader *shader = ctx->shader;
2873 struct ac_export_args pos_args[4] = {};
2874 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2875 unsigned pos_idx;
2876 int i;
2877
2878 /* Build position exports. */
2879 for (i = 0; i < noutput; i++) {
2880 switch (outputs[i].semantic_name) {
2881 case TGSI_SEMANTIC_POSITION:
2882 si_llvm_init_export_args(ctx, outputs[i].values,
2883 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2884 break;
2885 case TGSI_SEMANTIC_PSIZE:
2886 psize_value = outputs[i].values[0];
2887 break;
2888 case TGSI_SEMANTIC_LAYER:
2889 layer_value = outputs[i].values[0];
2890 break;
2891 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2892 viewport_index_value = outputs[i].values[0];
2893 break;
2894 case TGSI_SEMANTIC_EDGEFLAG:
2895 edgeflag_value = outputs[i].values[0];
2896 break;
2897 case TGSI_SEMANTIC_CLIPDIST:
2898 if (!shader->key.opt.clip_disable) {
2899 unsigned index = 2 + outputs[i].semantic_index;
2900 si_llvm_init_export_args(ctx, outputs[i].values,
2901 V_008DFC_SQ_EXP_POS + index,
2902 &pos_args[index]);
2903 }
2904 break;
2905 case TGSI_SEMANTIC_CLIPVERTEX:
2906 if (!shader->key.opt.clip_disable) {
2907 si_llvm_emit_clipvertex(ctx, pos_args,
2908 outputs[i].values);
2909 }
2910 break;
2911 }
2912 }
2913
2914 /* We need to add the position output manually if it's missing. */
2915 if (!pos_args[0].out[0]) {
2916 pos_args[0].enabled_channels = 0xf; /* writemask */
2917 pos_args[0].valid_mask = 0; /* EXEC mask */
2918 pos_args[0].done = 0; /* last export? */
2919 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2920 pos_args[0].compr = 0; /* COMPR flag */
2921 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2922 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2923 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2924 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2925 }
2926
2927 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2928 if (shader->selector->info.writes_psize ||
2929 shader->selector->info.writes_edgeflag ||
2930 shader->selector->info.writes_viewport_index ||
2931 shader->selector->info.writes_layer) {
2932 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2933 (shader->selector->info.writes_edgeflag << 1) |
2934 (shader->selector->info.writes_layer << 2);
2935
2936 pos_args[1].valid_mask = 0; /* EXEC mask */
2937 pos_args[1].done = 0; /* last export? */
2938 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2939 pos_args[1].compr = 0; /* COMPR flag */
2940 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2941 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2942 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2943 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2944
2945 if (shader->selector->info.writes_psize)
2946 pos_args[1].out[0] = psize_value;
2947
2948 if (shader->selector->info.writes_edgeflag) {
2949 /* The output is a float, but the hw expects an integer
2950 * with the first bit containing the edge flag. */
2951 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2952 edgeflag_value,
2953 ctx->i32, "");
2954 edgeflag_value = ac_build_umin(&ctx->ac,
2955 edgeflag_value,
2956 ctx->i32_1);
2957
2958 /* The LLVM intrinsic expects a float. */
2959 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2960 }
2961
2962 if (ctx->screen->info.chip_class >= GFX9) {
2963 /* GFX9 has the layer in out.z[10:0] and the viewport
2964 * index in out.z[19:16].
2965 */
2966 if (shader->selector->info.writes_layer)
2967 pos_args[1].out[2] = layer_value;
2968
2969 if (shader->selector->info.writes_viewport_index) {
2970 LLVMValueRef v = viewport_index_value;
2971
2972 v = ac_to_integer(&ctx->ac, v);
2973 v = LLVMBuildShl(ctx->ac.builder, v,
2974 LLVMConstInt(ctx->i32, 16, 0), "");
2975 v = LLVMBuildOr(ctx->ac.builder, v,
2976 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2977 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2978 pos_args[1].enabled_channels |= 1 << 2;
2979 }
2980 } else {
2981 if (shader->selector->info.writes_layer)
2982 pos_args[1].out[2] = layer_value;
2983
2984 if (shader->selector->info.writes_viewport_index) {
2985 pos_args[1].out[3] = viewport_index_value;
2986 pos_args[1].enabled_channels |= 1 << 3;
2987 }
2988 }
2989 }
2990
2991 for (i = 0; i < 4; i++)
2992 if (pos_args[i].out[0])
2993 shader->info.nr_pos_exports++;
2994
2995 pos_idx = 0;
2996 for (i = 0; i < 4; i++) {
2997 if (!pos_args[i].out[0])
2998 continue;
2999
3000 /* Specify the target we are exporting */
3001 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
3002
3003 if (pos_idx == shader->info.nr_pos_exports)
3004 /* Specify that this is the last export */
3005 pos_args[i].done = 1;
3006
3007 ac_build_export(&ctx->ac, &pos_args[i]);
3008 }
3009
3010 /* Build parameter exports. */
3011 si_build_param_exports(ctx, outputs, noutput);
3012 }
3013
3014 /**
3015 * Forward all outputs from the vertex shader to the TES. This is only used
3016 * for the fixed function TCS.
3017 */
3018 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
3019 {
3020 struct si_shader_context *ctx = si_shader_context(bld_base);
3021 LLVMValueRef invocation_id, buffer, buffer_offset;
3022 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
3023 uint64_t inputs;
3024
3025 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3026 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3027 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3028
3029 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
3030 lds_vertex_offset = LLVMBuildMul(ctx->ac.builder, invocation_id,
3031 lds_vertex_stride, "");
3032 lds_base = get_tcs_in_current_patch_offset(ctx);
3033 lds_base = LLVMBuildAdd(ctx->ac.builder, lds_base, lds_vertex_offset, "");
3034
3035 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
3036 while (inputs) {
3037 unsigned i = u_bit_scan64(&inputs);
3038
3039 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
3040 LLVMConstInt(ctx->i32, 4 * i, 0),
3041 "");
3042
3043 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
3044 get_rel_patch_id(ctx),
3045 invocation_id,
3046 LLVMConstInt(ctx->i32, i, 0));
3047
3048 LLVMValueRef value = lds_load(bld_base, ctx->ac.i32, ~0,
3049 lds_ptr);
3050
3051 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
3052 buffer_offset, 0, 1, 0, true, false);
3053 }
3054 }
3055
3056 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
3057 LLVMValueRef rel_patch_id,
3058 LLVMValueRef invocation_id,
3059 LLVMValueRef tcs_out_current_patch_data_offset,
3060 LLVMValueRef invoc0_tf_outer[4],
3061 LLVMValueRef invoc0_tf_inner[2])
3062 {
3063 struct si_shader_context *ctx = si_shader_context(bld_base);
3064 struct si_shader *shader = ctx->shader;
3065 unsigned tess_inner_index, tess_outer_index;
3066 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
3067 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3068 unsigned stride, outer_comps, inner_comps, i, offset;
3069 struct lp_build_if_state if_ctx, inner_if_ctx;
3070
3071 /* Add a barrier before loading tess factors from LDS. */
3072 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
3073 si_llvm_emit_barrier(NULL, bld_base, NULL);
3074
3075 /* Do this only for invocation 0, because the tess levels are per-patch,
3076 * not per-vertex.
3077 *
3078 * This can't jump, because invocation 0 executes this. It should
3079 * at least mask out the loads and stores for other invocations.
3080 */
3081 lp_build_if(&if_ctx, &ctx->gallivm,
3082 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3083 invocation_id, ctx->i32_0, ""));
3084
3085 /* Determine the layout of one tess factor element in the buffer. */
3086 switch (shader->key.part.tcs.epilog.prim_mode) {
3087 case PIPE_PRIM_LINES:
3088 stride = 2; /* 2 dwords, 1 vec2 store */
3089 outer_comps = 2;
3090 inner_comps = 0;
3091 break;
3092 case PIPE_PRIM_TRIANGLES:
3093 stride = 4; /* 4 dwords, 1 vec4 store */
3094 outer_comps = 3;
3095 inner_comps = 1;
3096 break;
3097 case PIPE_PRIM_QUADS:
3098 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3099 outer_comps = 4;
3100 inner_comps = 2;
3101 break;
3102 default:
3103 assert(0);
3104 return;
3105 }
3106
3107 for (i = 0; i < 4; i++) {
3108 inner[i] = LLVMGetUndef(ctx->i32);
3109 outer[i] = LLVMGetUndef(ctx->i32);
3110 }
3111
3112 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3113 /* Tess factors are in VGPRs. */
3114 for (i = 0; i < outer_comps; i++)
3115 outer[i] = out[i] = invoc0_tf_outer[i];
3116 for (i = 0; i < inner_comps; i++)
3117 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3118 } else {
3119 /* Load tess_inner and tess_outer from LDS.
3120 * Any invocation can write them, so we can't get them from a temporary.
3121 */
3122 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3123 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3124
3125 lds_base = tcs_out_current_patch_data_offset;
3126 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3127 LLVMConstInt(ctx->i32,
3128 tess_inner_index * 4, 0), "");
3129 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3130 LLVMConstInt(ctx->i32,
3131 tess_outer_index * 4, 0), "");
3132
3133 for (i = 0; i < outer_comps; i++) {
3134 outer[i] = out[i] =
3135 lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3136 }
3137 for (i = 0; i < inner_comps; i++) {
3138 inner[i] = out[outer_comps+i] =
3139 lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3140 }
3141 }
3142
3143 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3144 /* For isolines, the hardware expects tess factors in the
3145 * reverse order from what GLSL / TGSI specify.
3146 */
3147 LLVMValueRef tmp = out[0];
3148 out[0] = out[1];
3149 out[1] = tmp;
3150 }
3151
3152 /* Convert the outputs to vectors for stores. */
3153 vec0 = lp_build_gather_values(&ctx->gallivm, out, MIN2(stride, 4));
3154 vec1 = NULL;
3155
3156 if (stride > 4)
3157 vec1 = lp_build_gather_values(&ctx->gallivm, out+4, stride - 4);
3158
3159 /* Get the buffer. */
3160 buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
3161
3162 /* Get the offset. */
3163 tf_base = LLVMGetParam(ctx->main_fn,
3164 ctx->param_tcs_factor_offset);
3165 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3166 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3167
3168 lp_build_if(&inner_if_ctx, &ctx->gallivm,
3169 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3170 rel_patch_id, ctx->i32_0, ""));
3171
3172 /* Store the dynamic HS control word. */
3173 offset = 0;
3174 if (ctx->screen->info.chip_class <= VI) {
3175 ac_build_buffer_store_dword(&ctx->ac, buffer,
3176 LLVMConstInt(ctx->i32, 0x80000000, 0),
3177 1, ctx->i32_0, tf_base,
3178 offset, 1, 0, true, false);
3179 offset += 4;
3180 }
3181
3182 lp_build_endif(&inner_if_ctx);
3183
3184 /* Store the tessellation factors. */
3185 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3186 MIN2(stride, 4), byteoffset, tf_base,
3187 offset, 1, 0, true, false);
3188 offset += 16;
3189 if (vec1)
3190 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3191 stride - 4, byteoffset, tf_base,
3192 offset, 1, 0, true, false);
3193
3194 /* Store the tess factors into the offchip buffer if TES reads them. */
3195 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3196 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3197 LLVMValueRef tf_inner_offset;
3198 unsigned param_outer, param_inner;
3199
3200 buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3201 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3202
3203 param_outer = si_shader_io_get_unique_index_patch(
3204 TGSI_SEMANTIC_TESSOUTER, 0);
3205 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3206 LLVMConstInt(ctx->i32, param_outer, 0));
3207
3208 outer_vec = lp_build_gather_values(&ctx->gallivm, outer,
3209 util_next_power_of_two(outer_comps));
3210
3211 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3212 outer_comps, tf_outer_offset,
3213 base, 0, 1, 0, true, false);
3214 if (inner_comps) {
3215 param_inner = si_shader_io_get_unique_index_patch(
3216 TGSI_SEMANTIC_TESSINNER, 0);
3217 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3218 LLVMConstInt(ctx->i32, param_inner, 0));
3219
3220 inner_vec = inner_comps == 1 ? inner[0] :
3221 lp_build_gather_values(&ctx->gallivm, inner, inner_comps);
3222 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3223 inner_comps, tf_inner_offset,
3224 base, 0, 1, 0, true, false);
3225 }
3226 }
3227
3228 lp_build_endif(&if_ctx);
3229 }
3230
3231 static LLVMValueRef
3232 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3233 unsigned param, unsigned return_index)
3234 {
3235 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3236 LLVMGetParam(ctx->main_fn, param),
3237 return_index, "");
3238 }
3239
3240 static LLVMValueRef
3241 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3242 unsigned param, unsigned return_index)
3243 {
3244 LLVMBuilderRef builder = ctx->ac.builder;
3245 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3246
3247 return LLVMBuildInsertValue(builder, ret,
3248 ac_to_float(&ctx->ac, p),
3249 return_index, "");
3250 }
3251
3252 static LLVMValueRef
3253 si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret,
3254 unsigned param, unsigned return_index)
3255 {
3256 LLVMBuilderRef builder = ctx->ac.builder;
3257 LLVMValueRef ptr, lo, hi;
3258
3259 if (HAVE_32BIT_POINTERS) {
3260 ptr = LLVMGetParam(ctx->main_fn, param);
3261 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i32, "");
3262 return LLVMBuildInsertValue(builder, ret, ptr, return_index, "");
3263 }
3264
3265 ptr = LLVMGetParam(ctx->main_fn, param);
3266 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
3267 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
3268 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
3269 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
3270 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
3271 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
3272 }
3273
3274 /* This only writes the tessellation factor levels. */
3275 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
3276 unsigned max_outputs,
3277 LLVMValueRef *addrs)
3278 {
3279 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3280 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
3281 LLVMBuilderRef builder = ctx->ac.builder;
3282 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3283
3284 si_copy_tcs_inputs(bld_base);
3285
3286 rel_patch_id = get_rel_patch_id(ctx);
3287 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3288 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3289
3290 if (ctx->screen->info.chip_class >= GFX9) {
3291 LLVMBasicBlockRef blocks[2] = {
3292 LLVMGetInsertBlock(builder),
3293 ctx->merged_wrap_if_state.entry_block
3294 };
3295 LLVMValueRef values[2];
3296
3297 lp_build_endif(&ctx->merged_wrap_if_state);
3298
3299 values[0] = rel_patch_id;
3300 values[1] = LLVMGetUndef(ctx->i32);
3301 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3302
3303 values[0] = tf_lds_offset;
3304 values[1] = LLVMGetUndef(ctx->i32);
3305 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3306
3307 values[0] = invocation_id;
3308 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3309 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3310 }
3311
3312 /* Return epilog parameters from this function. */
3313 LLVMValueRef ret = ctx->return_value;
3314 unsigned vgpr;
3315
3316 if (ctx->screen->info.chip_class >= GFX9) {
3317 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3318 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3319 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3320 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3321 /* Tess offchip and tess factor offsets are at the beginning. */
3322 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3323 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3324 vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
3325 } else {
3326 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3327 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3328 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3329 GFX6_SGPR_TCS_OUT_LAYOUT);
3330 /* Tess offchip and tess factor offsets are after user SGPRs. */
3331 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3332 GFX6_TCS_NUM_USER_SGPR);
3333 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3334 GFX6_TCS_NUM_USER_SGPR + 1);
3335 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3336 }
3337
3338 /* VGPRs */
3339 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3340 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3341 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3342
3343 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3344 * the invocation_id output does not alias the tcs_rel_ids input,
3345 * which saves a V_MOV on gfx9.
3346 */
3347 vgpr += 2;
3348
3349 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3350 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3351
3352 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3353 vgpr++; /* skip the tess factor LDS offset */
3354 for (unsigned i = 0; i < 6; i++) {
3355 LLVMValueRef value =
3356 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3357 value = ac_to_float(&ctx->ac, value);
3358 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3359 }
3360 } else {
3361 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3362 }
3363 ctx->return_value = ret;
3364 }
3365
3366 /* Pass TCS inputs from LS to TCS on GFX9. */
3367 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3368 {
3369 LLVMValueRef ret = ctx->return_value;
3370
3371 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3372 if (HAVE_32BIT_POINTERS)
3373 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3374 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3375 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3376 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3377 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3378
3379 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3380 8 + SI_SGPR_RW_BUFFERS);
3381 ret = si_insert_input_ptr(ctx, ret,
3382 ctx->param_bindless_samplers_and_images,
3383 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3384
3385 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3386 8 + SI_SGPR_VS_STATE_BITS);
3387
3388 #if !HAVE_32BIT_POINTERS
3389 ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 1,
3390 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
3391 #endif
3392
3393 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3394 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3395 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3396 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3397 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3398 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3399
3400 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3401 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3402 ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
3403 vgpr++, "");
3404 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3405 ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
3406 vgpr++, "");
3407 ctx->return_value = ret;
3408 }
3409
3410 /* Pass GS inputs from ES to GS on GFX9. */
3411 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3412 {
3413 LLVMValueRef ret = ctx->return_value;
3414
3415 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3416 if (HAVE_32BIT_POINTERS)
3417 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3418 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3419 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3420 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3421
3422 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3423 8 + SI_SGPR_RW_BUFFERS);
3424 ret = si_insert_input_ptr(ctx, ret,
3425 ctx->param_bindless_samplers_and_images,
3426 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3427
3428 #if !HAVE_32BIT_POINTERS
3429 ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 1,
3430 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
3431 #endif
3432
3433 unsigned vgpr = 8 + GFX9_GS_NUM_USER_SGPR;
3434 for (unsigned i = 0; i < 5; i++) {
3435 unsigned param = ctx->param_gs_vtx01_offset + i;
3436 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3437 }
3438 ctx->return_value = ret;
3439 }
3440
3441 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3442 unsigned max_outputs,
3443 LLVMValueRef *addrs)
3444 {
3445 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3446 struct si_shader *shader = ctx->shader;
3447 struct tgsi_shader_info *info = &shader->selector->info;
3448 unsigned i, chan;
3449 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3450 ctx->param_rel_auto_id);
3451 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3452 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3453 vertex_dw_stride, "");
3454
3455 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3456 * its inputs from it. */
3457 for (i = 0; i < info->num_outputs; i++) {
3458 unsigned name = info->output_semantic_name[i];
3459 unsigned index = info->output_semantic_index[i];
3460
3461 /* The ARB_shader_viewport_layer_array spec contains the
3462 * following issue:
3463 *
3464 * 2) What happens if gl_ViewportIndex or gl_Layer is
3465 * written in the vertex shader and a geometry shader is
3466 * present?
3467 *
3468 * RESOLVED: The value written by the last vertex processing
3469 * stage is used. If the last vertex processing stage
3470 * (vertex, tessellation evaluation or geometry) does not
3471 * statically assign to gl_ViewportIndex or gl_Layer, index
3472 * or layer zero is assumed.
3473 *
3474 * So writes to those outputs in VS-as-LS are simply ignored.
3475 */
3476 if (name == TGSI_SEMANTIC_LAYER ||
3477 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3478 continue;
3479
3480 int param = si_shader_io_get_unique_index(name, index);
3481 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3482 LLVMConstInt(ctx->i32, param * 4, 0), "");
3483
3484 for (chan = 0; chan < 4; chan++) {
3485 if (!(info->output_usagemask[i] & (1 << chan)))
3486 continue;
3487
3488 lds_store(ctx, chan, dw_addr,
3489 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3490 }
3491 }
3492
3493 if (ctx->screen->info.chip_class >= GFX9)
3494 si_set_ls_return_value_for_tcs(ctx);
3495 }
3496
3497 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3498 unsigned max_outputs,
3499 LLVMValueRef *addrs)
3500 {
3501 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3502 struct si_shader *es = ctx->shader;
3503 struct tgsi_shader_info *info = &es->selector->info;
3504 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3505 ctx->param_es2gs_offset);
3506 LLVMValueRef lds_base = NULL;
3507 unsigned chan;
3508 int i;
3509
3510 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3511 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3512 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3513 LLVMValueRef wave_idx = unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3514 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3515 LLVMBuildMul(ctx->ac.builder, wave_idx,
3516 LLVMConstInt(ctx->i32, 64, false), ""), "");
3517 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3518 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3519 }
3520
3521 for (i = 0; i < info->num_outputs; i++) {
3522 int param;
3523
3524 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3525 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3526 continue;
3527
3528 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3529 info->output_semantic_index[i]);
3530
3531 for (chan = 0; chan < 4; chan++) {
3532 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3533 out_val = ac_to_integer(&ctx->ac, out_val);
3534
3535 /* GFX9 has the ESGS ring in LDS. */
3536 if (ctx->screen->info.chip_class >= GFX9) {
3537 lds_store(ctx, param * 4 + chan, lds_base, out_val);
3538 continue;
3539 }
3540
3541 ac_build_buffer_store_dword(&ctx->ac,
3542 ctx->esgs_ring,
3543 out_val, 1, NULL, soffset,
3544 (4 * param + chan) * 4,
3545 1, 1, true, true);
3546 }
3547 }
3548
3549 if (ctx->screen->info.chip_class >= GFX9)
3550 si_set_es_return_value_for_gs(ctx);
3551 }
3552
3553 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3554 {
3555 if (ctx->screen->info.chip_class >= GFX9)
3556 return unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3557 else
3558 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3559 }
3560
3561 static void emit_gs_epilogue(struct si_shader_context *ctx)
3562 {
3563 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3564 si_get_gs_wave_id(ctx));
3565
3566 if (ctx->screen->info.chip_class >= GFX9)
3567 lp_build_endif(&ctx->merged_wrap_if_state);
3568 }
3569
3570 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3571 unsigned max_outputs,
3572 LLVMValueRef *addrs)
3573 {
3574 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3575 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3576
3577 assert(info->num_outputs <= max_outputs);
3578
3579 emit_gs_epilogue(ctx);
3580 }
3581
3582 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3583 {
3584 struct si_shader_context *ctx = si_shader_context(bld_base);
3585 emit_gs_epilogue(ctx);
3586 }
3587
3588 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3589 unsigned max_outputs,
3590 LLVMValueRef *addrs)
3591 {
3592 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3593 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3594 struct si_shader_output_values *outputs = NULL;
3595 int i,j;
3596
3597 assert(!ctx->shader->is_gs_copy_shader);
3598 assert(info->num_outputs <= max_outputs);
3599
3600 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3601
3602 /* Vertex color clamping.
3603 *
3604 * This uses a state constant loaded in a user data SGPR and
3605 * an IF statement is added that clamps all colors if the constant
3606 * is true.
3607 */
3608 if (ctx->type == PIPE_SHADER_VERTEX) {
3609 struct lp_build_if_state if_ctx;
3610 LLVMValueRef cond = NULL;
3611 LLVMValueRef addr, val;
3612
3613 for (i = 0; i < info->num_outputs; i++) {
3614 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3615 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3616 continue;
3617
3618 /* We've found a color. */
3619 if (!cond) {
3620 /* The state is in the first bit of the user SGPR. */
3621 cond = LLVMGetParam(ctx->main_fn,
3622 ctx->param_vs_state_bits);
3623 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3624 ctx->i1, "");
3625 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3626 }
3627
3628 for (j = 0; j < 4; j++) {
3629 addr = addrs[4 * i + j];
3630 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3631 val = ac_build_clamp(&ctx->ac, val);
3632 LLVMBuildStore(ctx->ac.builder, val, addr);
3633 }
3634 }
3635
3636 if (cond)
3637 lp_build_endif(&if_ctx);
3638 }
3639
3640 for (i = 0; i < info->num_outputs; i++) {
3641 outputs[i].semantic_name = info->output_semantic_name[i];
3642 outputs[i].semantic_index = info->output_semantic_index[i];
3643
3644 for (j = 0; j < 4; j++) {
3645 outputs[i].values[j] =
3646 LLVMBuildLoad(ctx->ac.builder,
3647 addrs[4 * i + j],
3648 "");
3649 outputs[i].vertex_stream[j] =
3650 (info->output_streams[i] >> (2 * j)) & 3;
3651 }
3652 }
3653
3654 if (ctx->shader->selector->so.num_outputs)
3655 si_llvm_emit_streamout(ctx, outputs, i, 0);
3656
3657 /* Export PrimitiveID. */
3658 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3659 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3660 outputs[i].semantic_index = 0;
3661 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3662 for (j = 1; j < 4; j++)
3663 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3664
3665 memset(outputs[i].vertex_stream, 0,
3666 sizeof(outputs[i].vertex_stream));
3667 i++;
3668 }
3669
3670 si_llvm_export_vs(ctx, outputs, i);
3671 FREE(outputs);
3672 }
3673
3674 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3675 {
3676 struct si_shader_context *ctx = si_shader_context(bld_base);
3677
3678 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3679 &ctx->outputs[0][0]);
3680 }
3681
3682 struct si_ps_exports {
3683 unsigned num;
3684 struct ac_export_args args[10];
3685 };
3686
3687 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3688 LLVMValueRef depth, LLVMValueRef stencil,
3689 LLVMValueRef samplemask, struct si_ps_exports *exp)
3690 {
3691 struct si_shader_context *ctx = si_shader_context(bld_base);
3692 struct ac_export_args args;
3693
3694 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3695
3696 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3697 }
3698
3699 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3700 LLVMValueRef *color, unsigned index,
3701 unsigned samplemask_param,
3702 bool is_last, struct si_ps_exports *exp)
3703 {
3704 struct si_shader_context *ctx = si_shader_context(bld_base);
3705 int i;
3706
3707 /* Clamp color */
3708 if (ctx->shader->key.part.ps.epilog.clamp_color)
3709 for (i = 0; i < 4; i++)
3710 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3711
3712 /* Alpha to one */
3713 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3714 color[3] = ctx->ac.f32_1;
3715
3716 /* Alpha test */
3717 if (index == 0 &&
3718 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3719 si_alpha_test(bld_base, color[3]);
3720
3721 /* Line & polygon smoothing */
3722 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3723 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3724 samplemask_param);
3725
3726 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3727 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3728 struct ac_export_args args[8];
3729 int c, last = -1;
3730
3731 /* Get the export arguments, also find out what the last one is. */
3732 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3733 si_llvm_init_export_args(ctx, color,
3734 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3735 if (args[c].enabled_channels)
3736 last = c;
3737 }
3738
3739 /* Emit all exports. */
3740 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3741 if (is_last && last == c) {
3742 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3743 args[c].done = 1; /* DONE bit */
3744 } else if (!args[c].enabled_channels)
3745 continue; /* unnecessary NULL export */
3746
3747 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3748 }
3749 } else {
3750 struct ac_export_args args;
3751
3752 /* Export */
3753 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3754 &args);
3755 if (is_last) {
3756 args.valid_mask = 1; /* whether the EXEC mask is valid */
3757 args.done = 1; /* DONE bit */
3758 } else if (!args.enabled_channels)
3759 return; /* unnecessary NULL export */
3760
3761 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3762 }
3763 }
3764
3765 static void si_emit_ps_exports(struct si_shader_context *ctx,
3766 struct si_ps_exports *exp)
3767 {
3768 for (unsigned i = 0; i < exp->num; i++)
3769 ac_build_export(&ctx->ac, &exp->args[i]);
3770 }
3771
3772 /**
3773 * Return PS outputs in this order:
3774 *
3775 * v[0:3] = color0.xyzw
3776 * v[4:7] = color1.xyzw
3777 * ...
3778 * vN+0 = Depth
3779 * vN+1 = Stencil
3780 * vN+2 = SampleMask
3781 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3782 *
3783 * The alpha-ref SGPR is returned via its original location.
3784 */
3785 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3786 unsigned max_outputs,
3787 LLVMValueRef *addrs)
3788 {
3789 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3790 struct si_shader *shader = ctx->shader;
3791 struct tgsi_shader_info *info = &shader->selector->info;
3792 LLVMBuilderRef builder = ctx->ac.builder;
3793 unsigned i, j, first_vgpr, vgpr;
3794
3795 LLVMValueRef color[8][4] = {};
3796 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3797 LLVMValueRef ret;
3798
3799 if (ctx->postponed_kill)
3800 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3801
3802 /* Read the output values. */
3803 for (i = 0; i < info->num_outputs; i++) {
3804 unsigned semantic_name = info->output_semantic_name[i];
3805 unsigned semantic_index = info->output_semantic_index[i];
3806
3807 switch (semantic_name) {
3808 case TGSI_SEMANTIC_COLOR:
3809 assert(semantic_index < 8);
3810 for (j = 0; j < 4; j++) {
3811 LLVMValueRef ptr = addrs[4 * i + j];
3812 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3813 color[semantic_index][j] = result;
3814 }
3815 break;
3816 case TGSI_SEMANTIC_POSITION:
3817 depth = LLVMBuildLoad(builder,
3818 addrs[4 * i + 2], "");
3819 break;
3820 case TGSI_SEMANTIC_STENCIL:
3821 stencil = LLVMBuildLoad(builder,
3822 addrs[4 * i + 1], "");
3823 break;
3824 case TGSI_SEMANTIC_SAMPLEMASK:
3825 samplemask = LLVMBuildLoad(builder,
3826 addrs[4 * i + 0], "");
3827 break;
3828 default:
3829 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3830 semantic_name);
3831 }
3832 }
3833
3834 /* Fill the return structure. */
3835 ret = ctx->return_value;
3836
3837 /* Set SGPRs. */
3838 ret = LLVMBuildInsertValue(builder, ret,
3839 ac_to_integer(&ctx->ac,
3840 LLVMGetParam(ctx->main_fn,
3841 SI_PARAM_ALPHA_REF)),
3842 SI_SGPR_ALPHA_REF, "");
3843
3844 /* Set VGPRs */
3845 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3846 for (i = 0; i < ARRAY_SIZE(color); i++) {
3847 if (!color[i][0])
3848 continue;
3849
3850 for (j = 0; j < 4; j++)
3851 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3852 }
3853 if (depth)
3854 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3855 if (stencil)
3856 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3857 if (samplemask)
3858 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3859
3860 /* Add the input sample mask for smoothing at the end. */
3861 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3862 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3863 ret = LLVMBuildInsertValue(builder, ret,
3864 LLVMGetParam(ctx->main_fn,
3865 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3866
3867 ctx->return_value = ret;
3868 }
3869
3870 static void membar_emit(
3871 const struct lp_build_tgsi_action *action,
3872 struct lp_build_tgsi_context *bld_base,
3873 struct lp_build_emit_data *emit_data)
3874 {
3875 struct si_shader_context *ctx = si_shader_context(bld_base);
3876 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3877 unsigned flags = LLVMConstIntGetZExtValue(src0);
3878 unsigned waitcnt = NOOP_WAITCNT;
3879
3880 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3881 waitcnt &= VM_CNT & LGKM_CNT;
3882
3883 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3884 TGSI_MEMBAR_SHADER_BUFFER |
3885 TGSI_MEMBAR_SHADER_IMAGE))
3886 waitcnt &= VM_CNT;
3887
3888 if (flags & TGSI_MEMBAR_SHARED)
3889 waitcnt &= LGKM_CNT;
3890
3891 if (waitcnt != NOOP_WAITCNT)
3892 ac_build_waitcnt(&ctx->ac, waitcnt);
3893 }
3894
3895 static void clock_emit(
3896 const struct lp_build_tgsi_action *action,
3897 struct lp_build_tgsi_context *bld_base,
3898 struct lp_build_emit_data *emit_data)
3899 {
3900 struct si_shader_context *ctx = si_shader_context(bld_base);
3901 LLVMValueRef tmp = ac_build_shader_clock(&ctx->ac);
3902
3903 emit_data->output[0] =
3904 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3905 emit_data->output[1] =
3906 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3907 }
3908
3909 static void si_llvm_emit_ddxy(
3910 const struct lp_build_tgsi_action *action,
3911 struct lp_build_tgsi_context *bld_base,
3912 struct lp_build_emit_data *emit_data)
3913 {
3914 struct si_shader_context *ctx = si_shader_context(bld_base);
3915 unsigned opcode = emit_data->info->opcode;
3916 LLVMValueRef val;
3917 int idx;
3918 unsigned mask;
3919
3920 if (opcode == TGSI_OPCODE_DDX_FINE)
3921 mask = AC_TID_MASK_LEFT;
3922 else if (opcode == TGSI_OPCODE_DDY_FINE)
3923 mask = AC_TID_MASK_TOP;
3924 else
3925 mask = AC_TID_MASK_TOP_LEFT;
3926
3927 /* for DDX we want to next X pixel, DDY next Y pixel. */
3928 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3929
3930 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3931 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3932 emit_data->output[emit_data->chan] = val;
3933 }
3934
3935 /*
3936 * this takes an I,J coordinate pair,
3937 * and works out the X and Y derivatives.
3938 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3939 */
3940 static LLVMValueRef si_llvm_emit_ddxy_interp(
3941 struct lp_build_tgsi_context *bld_base,
3942 LLVMValueRef interp_ij)
3943 {
3944 struct si_shader_context *ctx = si_shader_context(bld_base);
3945 LLVMValueRef result[4], a;
3946 unsigned i;
3947
3948 for (i = 0; i < 2; i++) {
3949 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
3950 LLVMConstInt(ctx->i32, i, 0), "");
3951 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
3952 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
3953 }
3954
3955 return lp_build_gather_values(&ctx->gallivm, result, 4);
3956 }
3957
3958 static void interp_fetch_args(
3959 struct lp_build_tgsi_context *bld_base,
3960 struct lp_build_emit_data *emit_data)
3961 {
3962 struct si_shader_context *ctx = si_shader_context(bld_base);
3963 const struct tgsi_full_instruction *inst = emit_data->inst;
3964
3965 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3966 /* offset is in second src, first two channels */
3967 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3968 emit_data->inst, 1,
3969 TGSI_CHAN_X);
3970 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3971 emit_data->inst, 1,
3972 TGSI_CHAN_Y);
3973 emit_data->arg_count = 2;
3974 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3975 LLVMValueRef sample_position;
3976 LLVMValueRef sample_id;
3977 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3978
3979 /* fetch sample ID, then fetch its sample position,
3980 * and place into first two channels.
3981 */
3982 sample_id = lp_build_emit_fetch(bld_base,
3983 emit_data->inst, 1, TGSI_CHAN_X);
3984 sample_id = ac_to_integer(&ctx->ac, sample_id);
3985
3986 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
3987 * Language 4.50 spec says about interpolateAtSample:
3988 *
3989 * "Returns the value of the input interpolant variable at
3990 * the location of sample number sample. If multisample
3991 * buffers are not available, the input variable will be
3992 * evaluated at the center of the pixel. If sample sample
3993 * does not exist, the position used to interpolate the
3994 * input variable is undefined."
3995 *
3996 * This means that sample_id values outside of the valid are
3997 * in fact valid input, and the usual mechanism for loading the
3998 * sample position doesn't work.
3999 */
4000 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
4001 LLVMValueRef center[4] = {
4002 LLVMConstReal(ctx->f32, 0.5),
4003 LLVMConstReal(ctx->f32, 0.5),
4004 ctx->ac.f32_0,
4005 ctx->ac.f32_0,
4006 };
4007
4008 sample_position = lp_build_gather_values(&ctx->gallivm, center, 4);
4009 } else {
4010 sample_position = load_sample_position(&ctx->abi, sample_id);
4011 }
4012
4013 emit_data->args[0] = LLVMBuildExtractElement(ctx->ac.builder,
4014 sample_position,
4015 ctx->i32_0, "");
4016
4017 emit_data->args[0] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[0], halfval, "");
4018 emit_data->args[1] = LLVMBuildExtractElement(ctx->ac.builder,
4019 sample_position,
4020 ctx->i32_1, "");
4021 emit_data->args[1] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[1], halfval, "");
4022 emit_data->arg_count = 2;
4023 }
4024 }
4025
4026 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
4027 struct lp_build_tgsi_context *bld_base,
4028 struct lp_build_emit_data *emit_data)
4029 {
4030 struct si_shader_context *ctx = si_shader_context(bld_base);
4031 struct si_shader *shader = ctx->shader;
4032 const struct tgsi_shader_info *info = &shader->selector->info;
4033 LLVMValueRef interp_param;
4034 const struct tgsi_full_instruction *inst = emit_data->inst;
4035 const struct tgsi_full_src_register *input = &inst->Src[0];
4036 int input_base, input_array_size;
4037 int chan;
4038 int i;
4039 LLVMValueRef prim_mask = ctx->abi.prim_mask;
4040 LLVMValueRef array_idx;
4041 int interp_param_idx;
4042 unsigned interp;
4043 unsigned location;
4044
4045 assert(input->Register.File == TGSI_FILE_INPUT);
4046
4047 if (input->Register.Indirect) {
4048 unsigned array_id = input->Indirect.ArrayID;
4049
4050 if (array_id) {
4051 input_base = info->input_array_first[array_id];
4052 input_array_size = info->input_array_last[array_id] - input_base + 1;
4053 } else {
4054 input_base = inst->Src[0].Register.Index;
4055 input_array_size = info->num_inputs - input_base;
4056 }
4057
4058 array_idx = si_get_indirect_index(ctx, &input->Indirect,
4059 1, input->Register.Index - input_base);
4060 } else {
4061 input_base = inst->Src[0].Register.Index;
4062 input_array_size = 1;
4063 array_idx = ctx->i32_0;
4064 }
4065
4066 interp = shader->selector->info.input_interpolate[input_base];
4067
4068 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4069 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4070 location = TGSI_INTERPOLATE_LOC_CENTER;
4071 else
4072 location = TGSI_INTERPOLATE_LOC_CENTROID;
4073
4074 interp_param_idx = lookup_interp_param_index(interp, location);
4075 if (interp_param_idx == -1)
4076 return;
4077 else if (interp_param_idx)
4078 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4079 else
4080 interp_param = NULL;
4081
4082 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4083 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4084 LLVMValueRef ij_out[2];
4085 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
4086
4087 /*
4088 * take the I then J parameters, and the DDX/Y for it, and
4089 * calculate the IJ inputs for the interpolator.
4090 * temp1 = ddx * offset/sample.x + I;
4091 * interp_param.I = ddy * offset/sample.y + temp1;
4092 * temp1 = ddx * offset/sample.x + J;
4093 * interp_param.J = ddy * offset/sample.y + temp1;
4094 */
4095 for (i = 0; i < 2; i++) {
4096 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
4097 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
4098 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4099 ddxy_out, ix_ll, "");
4100 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4101 ddxy_out, iy_ll, "");
4102 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4103 interp_param, ix_ll, "");
4104 LLVMValueRef temp1, temp2;
4105
4106 interp_el = ac_to_float(&ctx->ac, interp_el);
4107
4108 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, emit_data->args[0], "");
4109
4110 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4111
4112 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, emit_data->args[1], "");
4113
4114 ij_out[i] = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4115 }
4116 interp_param = lp_build_gather_values(&ctx->gallivm, ij_out, 2);
4117 }
4118
4119 if (interp_param)
4120 interp_param = ac_to_float(&ctx->ac, interp_param);
4121
4122 for (chan = 0; chan < 4; chan++) {
4123 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
4124 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4125
4126 for (unsigned idx = 0; idx < input_array_size; ++idx) {
4127 LLVMValueRef v, i = NULL, j = NULL;
4128
4129 if (interp_param) {
4130 i = LLVMBuildExtractElement(
4131 ctx->ac.builder, interp_param, ctx->i32_0, "");
4132 j = LLVMBuildExtractElement(
4133 ctx->ac.builder, interp_param, ctx->i32_1, "");
4134 }
4135 v = si_build_fs_interp(ctx, input_base + idx, schan,
4136 prim_mask, i, j);
4137
4138 gather = LLVMBuildInsertElement(ctx->ac.builder,
4139 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
4140 }
4141
4142 emit_data->output[chan] = LLVMBuildExtractElement(
4143 ctx->ac.builder, gather, array_idx, "");
4144 }
4145 }
4146
4147 static void vote_all_emit(
4148 const struct lp_build_tgsi_action *action,
4149 struct lp_build_tgsi_context *bld_base,
4150 struct lp_build_emit_data *emit_data)
4151 {
4152 struct si_shader_context *ctx = si_shader_context(bld_base);
4153
4154 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
4155 emit_data->output[emit_data->chan] =
4156 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4157 }
4158
4159 static void vote_any_emit(
4160 const struct lp_build_tgsi_action *action,
4161 struct lp_build_tgsi_context *bld_base,
4162 struct lp_build_emit_data *emit_data)
4163 {
4164 struct si_shader_context *ctx = si_shader_context(bld_base);
4165
4166 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
4167 emit_data->output[emit_data->chan] =
4168 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4169 }
4170
4171 static void vote_eq_emit(
4172 const struct lp_build_tgsi_action *action,
4173 struct lp_build_tgsi_context *bld_base,
4174 struct lp_build_emit_data *emit_data)
4175 {
4176 struct si_shader_context *ctx = si_shader_context(bld_base);
4177
4178 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4179 emit_data->output[emit_data->chan] =
4180 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4181 }
4182
4183 static void ballot_emit(
4184 const struct lp_build_tgsi_action *action,
4185 struct lp_build_tgsi_context *bld_base,
4186 struct lp_build_emit_data *emit_data)
4187 {
4188 struct si_shader_context *ctx = si_shader_context(bld_base);
4189 LLVMBuilderRef builder = ctx->ac.builder;
4190 LLVMValueRef tmp;
4191
4192 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4193 tmp = ac_build_ballot(&ctx->ac, tmp);
4194 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4195
4196 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4197 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4198 }
4199
4200 static void read_invoc_fetch_args(
4201 struct lp_build_tgsi_context *bld_base,
4202 struct lp_build_emit_data *emit_data)
4203 {
4204 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4205 0, emit_data->src_chan);
4206
4207 /* Always read the source invocation (= lane) from the X channel. */
4208 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4209 1, TGSI_CHAN_X);
4210 emit_data->arg_count = 2;
4211 }
4212
4213 static void read_lane_emit(
4214 const struct lp_build_tgsi_action *action,
4215 struct lp_build_tgsi_context *bld_base,
4216 struct lp_build_emit_data *emit_data)
4217 {
4218 struct si_shader_context *ctx = si_shader_context(bld_base);
4219
4220 /* We currently have no other way to prevent LLVM from lifting the icmp
4221 * calls to a dominating basic block.
4222 */
4223 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4224
4225 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4226 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4227
4228 emit_data->output[emit_data->chan] =
4229 ac_build_intrinsic(&ctx->ac, action->intr_name,
4230 ctx->i32, emit_data->args, emit_data->arg_count,
4231 AC_FUNC_ATTR_READNONE |
4232 AC_FUNC_ATTR_CONVERGENT);
4233 }
4234
4235 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4236 struct lp_build_emit_data *emit_data)
4237 {
4238 struct si_shader_context *ctx = si_shader_context(bld_base);
4239 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4240 LLVMValueRef imm;
4241 unsigned stream;
4242
4243 assert(src0.File == TGSI_FILE_IMMEDIATE);
4244
4245 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4246 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4247 return stream;
4248 }
4249
4250 /* Emit one vertex from the geometry shader */
4251 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4252 unsigned stream,
4253 LLVMValueRef *addrs)
4254 {
4255 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4256 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4257 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
4258 struct si_shader *shader = ctx->shader;
4259 struct lp_build_if_state if_state;
4260 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4261 ctx->param_gs2vs_offset);
4262 LLVMValueRef gs_next_vertex;
4263 LLVMValueRef can_emit;
4264 unsigned chan, offset;
4265 int i;
4266
4267 /* Write vertex attribute values to GSVS ring */
4268 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4269 ctx->gs_next_vertex[stream],
4270 "");
4271
4272 /* If this thread has already emitted the declared maximum number of
4273 * vertices, skip the write: excessive vertex emissions are not
4274 * supposed to have any effect.
4275 *
4276 * If the shader has no writes to memory, kill it instead. This skips
4277 * further memory loads and may allow LLVM to skip to the end
4278 * altogether.
4279 */
4280 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4281 LLVMConstInt(ctx->i32,
4282 shader->selector->gs_max_out_vertices, 0), "");
4283
4284 bool use_kill = !info->writes_memory;
4285 if (use_kill) {
4286 ac_build_kill_if_false(&ctx->ac, can_emit);
4287 } else {
4288 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4289 }
4290
4291 offset = 0;
4292 for (i = 0; i < info->num_outputs; i++) {
4293 for (chan = 0; chan < 4; chan++) {
4294 if (!(info->output_usagemask[i] & (1 << chan)) ||
4295 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4296 continue;
4297
4298 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4299 LLVMValueRef voffset =
4300 LLVMConstInt(ctx->i32, offset *
4301 shader->selector->gs_max_out_vertices, 0);
4302 offset++;
4303
4304 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4305 voffset = lp_build_mul_imm(uint, voffset, 4);
4306
4307 out_val = ac_to_integer(&ctx->ac, out_val);
4308
4309 ac_build_buffer_store_dword(&ctx->ac,
4310 ctx->gsvs_ring[stream],
4311 out_val, 1,
4312 voffset, soffset, 0,
4313 1, 1, true, true);
4314 }
4315 }
4316
4317 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4318 ctx->i32_1);
4319
4320 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4321
4322 /* Signal vertex emission */
4323 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4324 si_get_gs_wave_id(ctx));
4325 if (!use_kill)
4326 lp_build_endif(&if_state);
4327 }
4328
4329 /* Emit one vertex from the geometry shader */
4330 static void si_tgsi_emit_vertex(
4331 const struct lp_build_tgsi_action *action,
4332 struct lp_build_tgsi_context *bld_base,
4333 struct lp_build_emit_data *emit_data)
4334 {
4335 struct si_shader_context *ctx = si_shader_context(bld_base);
4336 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4337
4338 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4339 }
4340
4341 /* Cut one primitive from the geometry shader */
4342 static void si_llvm_emit_primitive(struct ac_shader_abi *abi,
4343 unsigned stream)
4344 {
4345 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4346
4347 /* Signal primitive cut */
4348 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4349 si_get_gs_wave_id(ctx));
4350 }
4351
4352 /* Cut one primitive from the geometry shader */
4353 static void si_tgsi_emit_primitive(
4354 const struct lp_build_tgsi_action *action,
4355 struct lp_build_tgsi_context *bld_base,
4356 struct lp_build_emit_data *emit_data)
4357 {
4358 struct si_shader_context *ctx = si_shader_context(bld_base);
4359
4360 si_llvm_emit_primitive(&ctx->abi, si_llvm_get_stream(bld_base, emit_data));
4361 }
4362
4363 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4364 struct lp_build_tgsi_context *bld_base,
4365 struct lp_build_emit_data *emit_data)
4366 {
4367 struct si_shader_context *ctx = si_shader_context(bld_base);
4368
4369 /* SI only (thanks to a hw bug workaround):
4370 * The real barrier instruction isn’t needed, because an entire patch
4371 * always fits into a single wave.
4372 */
4373 if (ctx->screen->info.chip_class == SI &&
4374 ctx->type == PIPE_SHADER_TESS_CTRL) {
4375 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
4376 return;
4377 }
4378
4379 lp_build_intrinsic(ctx->ac.builder,
4380 "llvm.amdgcn.s.barrier",
4381 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
4382 }
4383
4384 static const struct lp_build_tgsi_action interp_action = {
4385 .fetch_args = interp_fetch_args,
4386 .emit = build_interp_intrinsic,
4387 };
4388
4389 static void si_create_function(struct si_shader_context *ctx,
4390 const char *name,
4391 LLVMTypeRef *returns, unsigned num_returns,
4392 struct si_function_info *fninfo,
4393 unsigned max_workgroup_size)
4394 {
4395 int i;
4396
4397 si_llvm_create_func(ctx, name, returns, num_returns,
4398 fninfo->types, fninfo->num_params);
4399 ctx->return_value = LLVMGetUndef(ctx->return_type);
4400
4401 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4402 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4403
4404 /* The combination of:
4405 * - noalias
4406 * - dereferenceable
4407 * - invariant.load
4408 * allows the optimization passes to move loads and reduces
4409 * SGPR spilling significantly.
4410 */
4411 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
4412
4413 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4414 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
4415 ac_add_attr_dereferenceable(P, UINT64_MAX);
4416 }
4417 }
4418
4419 for (i = 0; i < fninfo->num_params; ++i) {
4420 if (fninfo->assign[i])
4421 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4422 }
4423
4424 si_llvm_add_attribute(ctx->main_fn, "amdgpu-32bit-address-high-bits",
4425 ctx->screen->info.address32_hi);
4426
4427 if (max_workgroup_size) {
4428 si_llvm_add_attribute(ctx->main_fn, "amdgpu-max-work-group-size",
4429 max_workgroup_size);
4430 }
4431 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4432 "no-signed-zeros-fp-math",
4433 "true");
4434
4435 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4436 /* These were copied from some LLVM test. */
4437 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4438 "less-precise-fpmad",
4439 "true");
4440 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4441 "no-infs-fp-math",
4442 "true");
4443 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4444 "no-nans-fp-math",
4445 "true");
4446 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4447 "unsafe-fp-math",
4448 "true");
4449 }
4450 }
4451
4452 static void declare_streamout_params(struct si_shader_context *ctx,
4453 struct pipe_stream_output_info *so,
4454 struct si_function_info *fninfo)
4455 {
4456 int i;
4457
4458 /* Streamout SGPRs. */
4459 if (so->num_outputs) {
4460 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4461 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4462 else
4463 ctx->param_streamout_config = fninfo->num_params - 1;
4464
4465 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4466 }
4467 /* A streamout buffer offset is loaded if the stride is non-zero. */
4468 for (i = 0; i < 4; i++) {
4469 if (!so->stride[i])
4470 continue;
4471
4472 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4473 }
4474 }
4475
4476 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4477 {
4478 switch (shader->selector->type) {
4479 case PIPE_SHADER_TESS_CTRL:
4480 /* Return this so that LLVM doesn't remove s_barrier
4481 * instructions on chips where we use s_barrier. */
4482 return shader->selector->screen->info.chip_class >= CIK ? 128 : 64;
4483
4484 case PIPE_SHADER_GEOMETRY:
4485 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4486
4487 case PIPE_SHADER_COMPUTE:
4488 break; /* see below */
4489
4490 default:
4491 return 0;
4492 }
4493
4494 const unsigned *properties = shader->selector->info.properties;
4495 unsigned max_work_group_size =
4496 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4497 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4498 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4499
4500 if (!max_work_group_size) {
4501 /* This is a variable group size compute shader,
4502 * compile it for the maximum possible group size.
4503 */
4504 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4505 }
4506 return max_work_group_size;
4507 }
4508
4509 static void declare_const_and_shader_buffers(struct si_shader_context *ctx,
4510 struct si_function_info *fninfo,
4511 bool assign_params)
4512 {
4513 LLVMTypeRef const_shader_buf_type;
4514
4515 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4516 ctx->shader->selector->info.shader_buffers_declared == 0)
4517 const_shader_buf_type = ctx->f32;
4518 else
4519 const_shader_buf_type = ctx->v4i32;
4520
4521 unsigned const_and_shader_buffers =
4522 add_arg(fninfo, ARG_SGPR,
4523 ac_array_in_const32_addr_space(const_shader_buf_type));
4524
4525 if (assign_params)
4526 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4527 }
4528
4529 static void declare_samplers_and_images(struct si_shader_context *ctx,
4530 struct si_function_info *fninfo,
4531 bool assign_params)
4532 {
4533 unsigned samplers_and_images =
4534 add_arg(fninfo, ARG_SGPR,
4535 ac_array_in_const32_addr_space(ctx->v8i32));
4536
4537 if (assign_params)
4538 ctx->param_samplers_and_images = samplers_and_images;
4539 }
4540
4541 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4542 struct si_function_info *fninfo,
4543 bool assign_params)
4544 {
4545 declare_const_and_shader_buffers(ctx, fninfo, assign_params);
4546 declare_samplers_and_images(ctx, fninfo, assign_params);
4547 }
4548
4549 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4550 struct si_function_info *fninfo)
4551 {
4552 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4553 ac_array_in_const32_addr_space(ctx->v4i32));
4554 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4555 ac_array_in_const32_addr_space(ctx->v8i32));
4556 }
4557
4558 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4559 struct si_function_info *fninfo)
4560 {
4561 ctx->param_vertex_buffers = add_arg(fninfo, ARG_SGPR,
4562 ac_array_in_const32_addr_space(ctx->v4i32));
4563 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4564 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4565 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4566 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4567 }
4568
4569 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4570 struct si_function_info *fninfo,
4571 unsigned *num_prolog_vgprs)
4572 {
4573 struct si_shader *shader = ctx->shader;
4574
4575 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4576 if (shader->key.as_ls) {
4577 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4578 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4579 } else {
4580 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4581 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4582 }
4583 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4584
4585 if (!shader->is_gs_copy_shader) {
4586 /* Vertex load indices. */
4587 ctx->param_vertex_index0 = fninfo->num_params;
4588 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4589 add_arg(fninfo, ARG_VGPR, ctx->i32);
4590 *num_prolog_vgprs += shader->selector->info.num_inputs;
4591 }
4592 }
4593
4594 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4595 struct si_function_info *fninfo)
4596 {
4597 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4598 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4599 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4600 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
4601 }
4602
4603 enum {
4604 /* Convenient merged shader definitions. */
4605 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4606 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4607 };
4608
4609 static void create_function(struct si_shader_context *ctx)
4610 {
4611 struct si_shader *shader = ctx->shader;
4612 struct si_function_info fninfo;
4613 LLVMTypeRef returns[16+32*4];
4614 unsigned i, num_return_sgprs;
4615 unsigned num_returns = 0;
4616 unsigned num_prolog_vgprs = 0;
4617 unsigned type = ctx->type;
4618 unsigned vs_blit_property =
4619 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4620
4621 si_init_function_info(&fninfo);
4622
4623 /* Set MERGED shaders. */
4624 if (ctx->screen->info.chip_class >= GFX9) {
4625 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4626 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4627 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4628 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4629 }
4630
4631 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4632
4633 switch (type) {
4634 case PIPE_SHADER_VERTEX:
4635 declare_global_desc_pointers(ctx, &fninfo);
4636
4637 if (vs_blit_property) {
4638 ctx->param_vs_blit_inputs = fninfo.num_params;
4639 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4640 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4641 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* depth */
4642
4643 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4644 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color0 */
4645 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color1 */
4646 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color2 */
4647 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color3 */
4648 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4649 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4650 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4651 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4652 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4653 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4654 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4655 }
4656
4657 /* VGPRs */
4658 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4659 break;
4660 }
4661
4662 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4663 declare_vs_specific_input_sgprs(ctx, &fninfo);
4664
4665 if (shader->key.as_es) {
4666 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4667 } else if (shader->key.as_ls) {
4668 /* no extra parameters */
4669 } else {
4670 if (shader->is_gs_copy_shader) {
4671 fninfo.num_params = ctx->param_rw_buffers + 1;
4672 fninfo.num_sgpr_params = fninfo.num_params;
4673 }
4674
4675 /* The locations of the other parameters are assigned dynamically. */
4676 declare_streamout_params(ctx, &shader->selector->so,
4677 &fninfo);
4678 }
4679
4680 /* VGPRs */
4681 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4682 break;
4683
4684 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4685 declare_global_desc_pointers(ctx, &fninfo);
4686 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4687 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4688 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4689 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4690 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4691 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4692 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4693
4694 /* VGPRs */
4695 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4696 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4697
4698 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4699 * placed after the user SGPRs.
4700 */
4701 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4702 returns[num_returns++] = ctx->i32; /* SGPRs */
4703 for (i = 0; i < 11; i++)
4704 returns[num_returns++] = ctx->f32; /* VGPRs */
4705 break;
4706
4707 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4708 /* Merged stages have 8 system SGPRs at the beginning. */
4709 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
4710 if (HAVE_32BIT_POINTERS) {
4711 declare_per_stage_desc_pointers(ctx, &fninfo,
4712 ctx->type == PIPE_SHADER_TESS_CTRL);
4713 } else {
4714 declare_const_and_shader_buffers(ctx, &fninfo,
4715 ctx->type == PIPE_SHADER_TESS_CTRL);
4716 }
4717 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4718 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4719 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4720 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4721 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4722 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4723
4724 declare_global_desc_pointers(ctx, &fninfo);
4725 declare_per_stage_desc_pointers(ctx, &fninfo,
4726 ctx->type == PIPE_SHADER_VERTEX);
4727 declare_vs_specific_input_sgprs(ctx, &fninfo);
4728
4729 if (!HAVE_32BIT_POINTERS) {
4730 declare_samplers_and_images(ctx, &fninfo,
4731 ctx->type == PIPE_SHADER_TESS_CTRL);
4732 }
4733 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4734 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4735 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4736
4737 /* VGPRs (first TCS, then VS) */
4738 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4739 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4740
4741 if (ctx->type == PIPE_SHADER_VERTEX) {
4742 declare_vs_input_vgprs(ctx, &fninfo,
4743 &num_prolog_vgprs);
4744
4745 /* LS return values are inputs to the TCS main shader part. */
4746 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4747 returns[num_returns++] = ctx->i32; /* SGPRs */
4748 for (i = 0; i < 2; i++)
4749 returns[num_returns++] = ctx->f32; /* VGPRs */
4750 } else {
4751 /* TCS return values are inputs to the TCS epilog.
4752 *
4753 * param_tcs_offchip_offset, param_tcs_factor_offset,
4754 * param_tcs_offchip_layout, and param_rw_buffers
4755 * should be passed to the epilog.
4756 */
4757 for (i = 0; i <= 8 + GFX9_SGPR_TCS_OUT_LAYOUT; i++)
4758 returns[num_returns++] = ctx->i32; /* SGPRs */
4759 for (i = 0; i < 11; i++)
4760 returns[num_returns++] = ctx->f32; /* VGPRs */
4761 }
4762 break;
4763
4764 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4765 /* Merged stages have 8 system SGPRs at the beginning. */
4766 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
4767 if (HAVE_32BIT_POINTERS) {
4768 declare_per_stage_desc_pointers(ctx, &fninfo,
4769 ctx->type == PIPE_SHADER_GEOMETRY);
4770 } else {
4771 declare_const_and_shader_buffers(ctx, &fninfo,
4772 ctx->type == PIPE_SHADER_GEOMETRY);
4773 }
4774 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4775 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4776 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4777 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4778 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4779 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4780
4781 declare_global_desc_pointers(ctx, &fninfo);
4782 declare_per_stage_desc_pointers(ctx, &fninfo,
4783 (ctx->type == PIPE_SHADER_VERTEX ||
4784 ctx->type == PIPE_SHADER_TESS_EVAL));
4785 if (ctx->type == PIPE_SHADER_VERTEX) {
4786 declare_vs_specific_input_sgprs(ctx, &fninfo);
4787 } else {
4788 /* TESS_EVAL (and also GEOMETRY):
4789 * Declare as many input SGPRs as the VS has. */
4790 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4791 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4792 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4793 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4794 if (!HAVE_32BIT_POINTERS)
4795 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4796 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4797 }
4798
4799 if (!HAVE_32BIT_POINTERS) {
4800 declare_samplers_and_images(ctx, &fninfo,
4801 ctx->type == PIPE_SHADER_GEOMETRY);
4802 }
4803
4804 /* VGPRs (first GS, then VS/TES) */
4805 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4806 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4807 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4808 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4809 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4810
4811 if (ctx->type == PIPE_SHADER_VERTEX) {
4812 declare_vs_input_vgprs(ctx, &fninfo,
4813 &num_prolog_vgprs);
4814 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4815 declare_tes_input_vgprs(ctx, &fninfo);
4816 }
4817
4818 if (ctx->type == PIPE_SHADER_VERTEX ||
4819 ctx->type == PIPE_SHADER_TESS_EVAL) {
4820 /* ES return values are inputs to GS. */
4821 for (i = 0; i < 8 + GFX9_GS_NUM_USER_SGPR; i++)
4822 returns[num_returns++] = ctx->i32; /* SGPRs */
4823 for (i = 0; i < 5; i++)
4824 returns[num_returns++] = ctx->f32; /* VGPRs */
4825 }
4826 break;
4827
4828 case PIPE_SHADER_TESS_EVAL:
4829 declare_global_desc_pointers(ctx, &fninfo);
4830 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4831 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4832 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4833
4834 if (shader->key.as_es) {
4835 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4836 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4837 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4838 } else {
4839 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4840 declare_streamout_params(ctx, &shader->selector->so,
4841 &fninfo);
4842 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4843 }
4844
4845 /* VGPRs */
4846 declare_tes_input_vgprs(ctx, &fninfo);
4847 break;
4848
4849 case PIPE_SHADER_GEOMETRY:
4850 declare_global_desc_pointers(ctx, &fninfo);
4851 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4852 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4853 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4854
4855 /* VGPRs */
4856 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4857 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4858 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4859 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4860 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4861 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4862 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4863 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4864 break;
4865
4866 case PIPE_SHADER_FRAGMENT:
4867 declare_global_desc_pointers(ctx, &fninfo);
4868 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4869 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4870 add_arg_assign_checked(&fninfo, ARG_SGPR, ctx->i32,
4871 &ctx->abi.prim_mask, SI_PARAM_PRIM_MASK);
4872
4873 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4874 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4875 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4876 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4877 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4878 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4879 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4880 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4881 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4882 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4883 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4884 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4885 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4886 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4887 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4888 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4889 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4890 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4891 shader->info.face_vgpr_index = 20;
4892 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4893 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4894 shader->info.ancillary_vgpr_index = 21;
4895 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4896 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4897 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4898
4899 /* Color inputs from the prolog. */
4900 if (shader->selector->info.colors_read) {
4901 unsigned num_color_elements =
4902 util_bitcount(shader->selector->info.colors_read);
4903
4904 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4905 for (i = 0; i < num_color_elements; i++)
4906 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4907
4908 num_prolog_vgprs += num_color_elements;
4909 }
4910
4911 /* Outputs for the epilog. */
4912 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4913 num_returns =
4914 num_return_sgprs +
4915 util_bitcount(shader->selector->info.colors_written) * 4 +
4916 shader->selector->info.writes_z +
4917 shader->selector->info.writes_stencil +
4918 shader->selector->info.writes_samplemask +
4919 1 /* SampleMaskIn */;
4920
4921 num_returns = MAX2(num_returns,
4922 num_return_sgprs +
4923 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4924
4925 for (i = 0; i < num_return_sgprs; i++)
4926 returns[i] = ctx->i32;
4927 for (; i < num_returns; i++)
4928 returns[i] = ctx->f32;
4929 break;
4930
4931 case PIPE_SHADER_COMPUTE:
4932 declare_global_desc_pointers(ctx, &fninfo);
4933 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4934 if (shader->selector->info.uses_grid_size)
4935 add_arg_assign(&fninfo, ARG_SGPR, v3i32, &ctx->abi.num_work_groups);
4936 if (shader->selector->info.uses_block_size)
4937 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4938
4939 for (i = 0; i < 3; i++) {
4940 ctx->abi.workgroup_ids[i] = NULL;
4941 if (shader->selector->info.uses_block_id[i])
4942 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->abi.workgroup_ids[i]);
4943 }
4944
4945 add_arg_assign(&fninfo, ARG_VGPR, v3i32, &ctx->abi.local_invocation_ids);
4946 break;
4947 default:
4948 assert(0 && "unimplemented shader");
4949 return;
4950 }
4951
4952 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4953 si_get_max_workgroup_size(shader));
4954
4955 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4956 if (ctx->type == PIPE_SHADER_FRAGMENT &&
4957 ctx->separate_prolog) {
4958 si_llvm_add_attribute(ctx->main_fn,
4959 "InitialPSInputAddr",
4960 S_0286D0_PERSP_SAMPLE_ENA(1) |
4961 S_0286D0_PERSP_CENTER_ENA(1) |
4962 S_0286D0_PERSP_CENTROID_ENA(1) |
4963 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4964 S_0286D0_LINEAR_CENTER_ENA(1) |
4965 S_0286D0_LINEAR_CENTROID_ENA(1) |
4966 S_0286D0_FRONT_FACE_ENA(1) |
4967 S_0286D0_ANCILLARY_ENA(1) |
4968 S_0286D0_POS_FIXED_PT_ENA(1));
4969 }
4970
4971 shader->info.num_input_sgprs = 0;
4972 shader->info.num_input_vgprs = 0;
4973
4974 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4975 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
4976
4977 for (; i < fninfo.num_params; ++i)
4978 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
4979
4980 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4981 shader->info.num_input_vgprs -= num_prolog_vgprs;
4982
4983 if (shader->key.as_ls ||
4984 ctx->type == PIPE_SHADER_TESS_CTRL ||
4985 /* GFX9 has the ESGS ring buffer in LDS. */
4986 type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY)
4987 ac_declare_lds_as_pointer(&ctx->ac);
4988 }
4989
4990 /**
4991 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4992 * for later use.
4993 */
4994 static void preload_ring_buffers(struct si_shader_context *ctx)
4995 {
4996 LLVMBuilderRef builder = ctx->ac.builder;
4997
4998 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
4999 ctx->param_rw_buffers);
5000
5001 if (ctx->screen->info.chip_class <= VI &&
5002 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
5003 unsigned ring =
5004 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5005 : SI_ES_RING_ESGS;
5006 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
5007
5008 ctx->esgs_ring =
5009 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5010 }
5011
5012 if (ctx->shader->is_gs_copy_shader) {
5013 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5014
5015 ctx->gsvs_ring[0] =
5016 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5017 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5018 const struct si_shader_selector *sel = ctx->shader->selector;
5019 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5020 LLVMValueRef base_ring;
5021
5022 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5023
5024 /* The conceptual layout of the GSVS ring is
5025 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5026 * but the real memory layout is swizzled across
5027 * threads:
5028 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5029 * t16v0c0 ..
5030 * Override the buffer descriptor accordingly.
5031 */
5032 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5033 uint64_t stream_offset = 0;
5034
5035 for (unsigned stream = 0; stream < 4; ++stream) {
5036 unsigned num_components;
5037 unsigned stride;
5038 unsigned num_records;
5039 LLVMValueRef ring, tmp;
5040
5041 num_components = sel->info.num_stream_output_components[stream];
5042 if (!num_components)
5043 continue;
5044
5045 stride = 4 * num_components * sel->gs_max_out_vertices;
5046
5047 /* Limit on the stride field for <= CIK. */
5048 assert(stride < (1 << 14));
5049
5050 num_records = 64;
5051
5052 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5053 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
5054 tmp = LLVMBuildAdd(builder, tmp,
5055 LLVMConstInt(ctx->i64,
5056 stream_offset, 0), "");
5057 stream_offset += stride * 64;
5058
5059 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5060 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5061 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5062 tmp = LLVMBuildOr(builder, tmp,
5063 LLVMConstInt(ctx->i32,
5064 S_008F04_STRIDE(stride) |
5065 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5066 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5067 ring = LLVMBuildInsertElement(builder, ring,
5068 LLVMConstInt(ctx->i32, num_records, 0),
5069 LLVMConstInt(ctx->i32, 2, 0), "");
5070 ring = LLVMBuildInsertElement(builder, ring,
5071 LLVMConstInt(ctx->i32,
5072 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5073 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5074 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5075 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5076 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5077 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5078 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5079 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5080 S_008F0C_ADD_TID_ENABLE(1),
5081 0),
5082 LLVMConstInt(ctx->i32, 3, 0), "");
5083
5084 ctx->gsvs_ring[stream] = ring;
5085 }
5086 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
5087 ctx->tess_offchip_ring = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TES);
5088 }
5089 }
5090
5091 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5092 LLVMValueRef param_rw_buffers,
5093 unsigned param_pos_fixed_pt)
5094 {
5095 LLVMBuilderRef builder = ctx->ac.builder;
5096 LLVMValueRef slot, desc, offset, row, bit, address[2];
5097
5098 /* Use the fixed-point gl_FragCoord input.
5099 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5100 * per coordinate to get the repeating effect.
5101 */
5102 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5103 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5104
5105 /* Load the buffer descriptor. */
5106 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5107 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
5108
5109 /* The stipple pattern is 32x32, each row has 32 bits. */
5110 offset = LLVMBuildMul(builder, address[1],
5111 LLVMConstInt(ctx->i32, 4, 0), "");
5112 row = buffer_load_const(ctx, desc, offset);
5113 row = ac_to_integer(&ctx->ac, row);
5114 bit = LLVMBuildLShr(builder, row, address[0], "");
5115 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5116 ac_build_kill_if_false(&ctx->ac, bit);
5117 }
5118
5119 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5120 struct si_shader_config *conf,
5121 unsigned symbol_offset)
5122 {
5123 unsigned i;
5124 const unsigned char *config =
5125 ac_shader_binary_config_start(binary, symbol_offset);
5126 bool really_needs_scratch = false;
5127
5128 /* LLVM adds SGPR spills to the scratch size.
5129 * Find out if we really need the scratch buffer.
5130 */
5131 for (i = 0; i < binary->reloc_count; i++) {
5132 const struct ac_shader_reloc *reloc = &binary->relocs[i];
5133
5134 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5135 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5136 really_needs_scratch = true;
5137 break;
5138 }
5139 }
5140
5141 /* XXX: We may be able to emit some of these values directly rather than
5142 * extracting fields to be emitted later.
5143 */
5144
5145 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5146 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5147 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5148 switch (reg) {
5149 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5150 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5151 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5152 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
5153 case R_00B848_COMPUTE_PGM_RSRC1:
5154 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5155 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5156 conf->float_mode = G_00B028_FLOAT_MODE(value);
5157 conf->rsrc1 = value;
5158 break;
5159 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5160 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5161 break;
5162 case R_00B84C_COMPUTE_PGM_RSRC2:
5163 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5164 conf->rsrc2 = value;
5165 break;
5166 case R_0286CC_SPI_PS_INPUT_ENA:
5167 conf->spi_ps_input_ena = value;
5168 break;
5169 case R_0286D0_SPI_PS_INPUT_ADDR:
5170 conf->spi_ps_input_addr = value;
5171 break;
5172 case R_0286E8_SPI_TMPRING_SIZE:
5173 case R_00B860_COMPUTE_TMPRING_SIZE:
5174 /* WAVESIZE is in units of 256 dwords. */
5175 if (really_needs_scratch)
5176 conf->scratch_bytes_per_wave =
5177 G_00B860_WAVESIZE(value) * 256 * 4;
5178 break;
5179 case 0x4: /* SPILLED_SGPRS */
5180 conf->spilled_sgprs = value;
5181 break;
5182 case 0x8: /* SPILLED_VGPRS */
5183 conf->spilled_vgprs = value;
5184 break;
5185 default:
5186 {
5187 static bool printed;
5188
5189 if (!printed) {
5190 fprintf(stderr, "Warning: LLVM emitted unknown "
5191 "config register: 0x%x\n", reg);
5192 printed = true;
5193 }
5194 }
5195 break;
5196 }
5197 }
5198
5199 if (!conf->spi_ps_input_addr)
5200 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5201 }
5202
5203 void si_shader_apply_scratch_relocs(struct si_shader *shader,
5204 uint64_t scratch_va)
5205 {
5206 unsigned i;
5207 uint32_t scratch_rsrc_dword0 = scratch_va;
5208 uint32_t scratch_rsrc_dword1 =
5209 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5210
5211 /* Enable scratch coalescing. */
5212 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5213
5214 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5215 const struct ac_shader_reloc *reloc =
5216 &shader->binary.relocs[i];
5217 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5218 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5219 &scratch_rsrc_dword0, 4);
5220 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5221 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5222 &scratch_rsrc_dword1, 4);
5223 }
5224 }
5225 }
5226
5227 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
5228 {
5229 unsigned size = shader->binary.code_size;
5230
5231 if (shader->prolog)
5232 size += shader->prolog->binary.code_size;
5233 if (shader->previous_stage)
5234 size += shader->previous_stage->binary.code_size;
5235 if (shader->prolog2)
5236 size += shader->prolog2->binary.code_size;
5237 if (shader->epilog)
5238 size += shader->epilog->binary.code_size;
5239 return size;
5240 }
5241
5242 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5243 {
5244 const struct ac_shader_binary *prolog =
5245 shader->prolog ? &shader->prolog->binary : NULL;
5246 const struct ac_shader_binary *previous_stage =
5247 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5248 const struct ac_shader_binary *prolog2 =
5249 shader->prolog2 ? &shader->prolog2->binary : NULL;
5250 const struct ac_shader_binary *epilog =
5251 shader->epilog ? &shader->epilog->binary : NULL;
5252 const struct ac_shader_binary *mainb = &shader->binary;
5253 unsigned bo_size = si_get_shader_binary_size(shader) +
5254 (!epilog ? mainb->rodata_size : 0);
5255 unsigned char *ptr;
5256
5257 assert(!prolog || !prolog->rodata_size);
5258 assert(!previous_stage || !previous_stage->rodata_size);
5259 assert(!prolog2 || !prolog2->rodata_size);
5260 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5261 !mainb->rodata_size);
5262 assert(!epilog || !epilog->rodata_size);
5263
5264 r600_resource_reference(&shader->bo, NULL);
5265 shader->bo = (struct r600_resource*)
5266 si_aligned_buffer_create(&sscreen->b,
5267 sscreen->cpdma_prefetch_writes_memory ?
5268 0 : R600_RESOURCE_FLAG_READ_ONLY,
5269 PIPE_USAGE_IMMUTABLE,
5270 align(bo_size, SI_CPDMA_ALIGNMENT),
5271 256);
5272 if (!shader->bo)
5273 return -ENOMEM;
5274
5275 /* Upload. */
5276 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5277 PIPE_TRANSFER_READ_WRITE |
5278 PIPE_TRANSFER_UNSYNCHRONIZED);
5279
5280 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5281 * endian-independent. */
5282 if (prolog) {
5283 memcpy(ptr, prolog->code, prolog->code_size);
5284 ptr += prolog->code_size;
5285 }
5286 if (previous_stage) {
5287 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5288 ptr += previous_stage->code_size;
5289 }
5290 if (prolog2) {
5291 memcpy(ptr, prolog2->code, prolog2->code_size);
5292 ptr += prolog2->code_size;
5293 }
5294
5295 memcpy(ptr, mainb->code, mainb->code_size);
5296 ptr += mainb->code_size;
5297
5298 if (epilog)
5299 memcpy(ptr, epilog->code, epilog->code_size);
5300 else if (mainb->rodata_size > 0)
5301 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5302
5303 sscreen->ws->buffer_unmap(shader->bo->buf);
5304 return 0;
5305 }
5306
5307 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5308 struct pipe_debug_callback *debug,
5309 const char *name, FILE *file)
5310 {
5311 char *line, *p;
5312 unsigned i, count;
5313
5314 if (binary->disasm_string) {
5315 fprintf(file, "Shader %s disassembly:\n", name);
5316 fprintf(file, "%s", binary->disasm_string);
5317
5318 if (debug && debug->debug_message) {
5319 /* Very long debug messages are cut off, so send the
5320 * disassembly one line at a time. This causes more
5321 * overhead, but on the plus side it simplifies
5322 * parsing of resulting logs.
5323 */
5324 pipe_debug_message(debug, SHADER_INFO,
5325 "Shader Disassembly Begin");
5326
5327 line = binary->disasm_string;
5328 while (*line) {
5329 p = util_strchrnul(line, '\n');
5330 count = p - line;
5331
5332 if (count) {
5333 pipe_debug_message(debug, SHADER_INFO,
5334 "%.*s", count, line);
5335 }
5336
5337 if (!*p)
5338 break;
5339 line = p + 1;
5340 }
5341
5342 pipe_debug_message(debug, SHADER_INFO,
5343 "Shader Disassembly End");
5344 }
5345 } else {
5346 fprintf(file, "Shader %s binary:\n", name);
5347 for (i = 0; i < binary->code_size; i += 4) {
5348 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5349 binary->code[i + 3], binary->code[i + 2],
5350 binary->code[i + 1], binary->code[i]);
5351 }
5352 }
5353 }
5354
5355 static void si_calculate_max_simd_waves(struct si_shader *shader)
5356 {
5357 struct si_screen *sscreen = shader->selector->screen;
5358 struct si_shader_config *conf = &shader->config;
5359 unsigned num_inputs = shader->selector->info.num_inputs;
5360 unsigned lds_increment = sscreen->info.chip_class >= CIK ? 512 : 256;
5361 unsigned lds_per_wave = 0;
5362 unsigned max_simd_waves;
5363
5364 switch (sscreen->info.family) {
5365 /* These always have 8 waves: */
5366 case CHIP_POLARIS10:
5367 case CHIP_POLARIS11:
5368 case CHIP_POLARIS12:
5369 max_simd_waves = 8;
5370 break;
5371 default:
5372 max_simd_waves = 10;
5373 }
5374
5375 /* Compute LDS usage for PS. */
5376 switch (shader->selector->type) {
5377 case PIPE_SHADER_FRAGMENT:
5378 /* The minimum usage per wave is (num_inputs * 48). The maximum
5379 * usage is (num_inputs * 48 * 16).
5380 * We can get anything in between and it varies between waves.
5381 *
5382 * The 48 bytes per input for a single primitive is equal to
5383 * 4 bytes/component * 4 components/input * 3 points.
5384 *
5385 * Other stages don't know the size at compile time or don't
5386 * allocate LDS per wave, but instead they do it per thread group.
5387 */
5388 lds_per_wave = conf->lds_size * lds_increment +
5389 align(num_inputs * 48, lds_increment);
5390 break;
5391 case PIPE_SHADER_COMPUTE:
5392 if (shader->selector) {
5393 unsigned max_workgroup_size =
5394 si_get_max_workgroup_size(shader);
5395 lds_per_wave = (conf->lds_size * lds_increment) /
5396 DIV_ROUND_UP(max_workgroup_size, 64);
5397 }
5398 break;
5399 }
5400
5401 /* Compute the per-SIMD wave counts. */
5402 if (conf->num_sgprs) {
5403 if (sscreen->info.chip_class >= VI)
5404 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5405 else
5406 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5407 }
5408
5409 if (conf->num_vgprs)
5410 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5411
5412 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5413 * 16KB makes some SIMDs unoccupied). */
5414 if (lds_per_wave)
5415 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5416
5417 conf->max_simd_waves = max_simd_waves;
5418 }
5419
5420 void si_shader_dump_stats_for_shader_db(const struct si_shader *shader,
5421 struct pipe_debug_callback *debug)
5422 {
5423 const struct si_shader_config *conf = &shader->config;
5424
5425 pipe_debug_message(debug, SHADER_INFO,
5426 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5427 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5428 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5429 conf->num_sgprs, conf->num_vgprs,
5430 si_get_shader_binary_size(shader),
5431 conf->lds_size, conf->scratch_bytes_per_wave,
5432 conf->max_simd_waves, conf->spilled_sgprs,
5433 conf->spilled_vgprs, conf->private_mem_vgprs);
5434 }
5435
5436 static void si_shader_dump_stats(struct si_screen *sscreen,
5437 const struct si_shader *shader,
5438 unsigned processor,
5439 FILE *file,
5440 bool check_debug_option)
5441 {
5442 const struct si_shader_config *conf = &shader->config;
5443
5444 if (!check_debug_option ||
5445 si_can_dump_shader(sscreen, processor)) {
5446 if (processor == PIPE_SHADER_FRAGMENT) {
5447 fprintf(file, "*** SHADER CONFIG ***\n"
5448 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5449 "SPI_PS_INPUT_ENA = 0x%04x\n",
5450 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5451 }
5452
5453 fprintf(file, "*** SHADER STATS ***\n"
5454 "SGPRS: %d\n"
5455 "VGPRS: %d\n"
5456 "Spilled SGPRs: %d\n"
5457 "Spilled VGPRs: %d\n"
5458 "Private memory VGPRs: %d\n"
5459 "Code Size: %d bytes\n"
5460 "LDS: %d blocks\n"
5461 "Scratch: %d bytes per wave\n"
5462 "Max Waves: %d\n"
5463 "********************\n\n\n",
5464 conf->num_sgprs, conf->num_vgprs,
5465 conf->spilled_sgprs, conf->spilled_vgprs,
5466 conf->private_mem_vgprs,
5467 si_get_shader_binary_size(shader),
5468 conf->lds_size, conf->scratch_bytes_per_wave,
5469 conf->max_simd_waves);
5470 }
5471 }
5472
5473 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5474 {
5475 switch (processor) {
5476 case PIPE_SHADER_VERTEX:
5477 if (shader->key.as_es)
5478 return "Vertex Shader as ES";
5479 else if (shader->key.as_ls)
5480 return "Vertex Shader as LS";
5481 else
5482 return "Vertex Shader as VS";
5483 case PIPE_SHADER_TESS_CTRL:
5484 return "Tessellation Control Shader";
5485 case PIPE_SHADER_TESS_EVAL:
5486 if (shader->key.as_es)
5487 return "Tessellation Evaluation Shader as ES";
5488 else
5489 return "Tessellation Evaluation Shader as VS";
5490 case PIPE_SHADER_GEOMETRY:
5491 if (shader->is_gs_copy_shader)
5492 return "GS Copy Shader as VS";
5493 else
5494 return "Geometry Shader";
5495 case PIPE_SHADER_FRAGMENT:
5496 return "Pixel Shader";
5497 case PIPE_SHADER_COMPUTE:
5498 return "Compute Shader";
5499 default:
5500 return "Unknown Shader";
5501 }
5502 }
5503
5504 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5505 struct pipe_debug_callback *debug, unsigned processor,
5506 FILE *file, bool check_debug_option)
5507 {
5508 if (!check_debug_option ||
5509 si_can_dump_shader(sscreen, processor))
5510 si_dump_shader_key(processor, shader, file);
5511
5512 if (!check_debug_option && shader->binary.llvm_ir_string) {
5513 if (shader->previous_stage &&
5514 shader->previous_stage->binary.llvm_ir_string) {
5515 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5516 si_get_shader_name(shader, processor));
5517 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5518 }
5519
5520 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5521 si_get_shader_name(shader, processor));
5522 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5523 }
5524
5525 if (!check_debug_option ||
5526 (si_can_dump_shader(sscreen, processor) &&
5527 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5528 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5529
5530 if (shader->prolog)
5531 si_shader_dump_disassembly(&shader->prolog->binary,
5532 debug, "prolog", file);
5533 if (shader->previous_stage)
5534 si_shader_dump_disassembly(&shader->previous_stage->binary,
5535 debug, "previous stage", file);
5536 if (shader->prolog2)
5537 si_shader_dump_disassembly(&shader->prolog2->binary,
5538 debug, "prolog2", file);
5539
5540 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5541
5542 if (shader->epilog)
5543 si_shader_dump_disassembly(&shader->epilog->binary,
5544 debug, "epilog", file);
5545 fprintf(file, "\n");
5546 }
5547
5548 si_shader_dump_stats(sscreen, shader, processor, file,
5549 check_debug_option);
5550 }
5551
5552 static int si_compile_llvm(struct si_screen *sscreen,
5553 struct ac_shader_binary *binary,
5554 struct si_shader_config *conf,
5555 LLVMTargetMachineRef tm,
5556 LLVMModuleRef mod,
5557 struct pipe_debug_callback *debug,
5558 unsigned processor,
5559 const char *name)
5560 {
5561 int r = 0;
5562 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5563
5564 if (si_can_dump_shader(sscreen, processor)) {
5565 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5566
5567 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5568 fprintf(stderr, "%s LLVM IR:\n\n", name);
5569 ac_dump_module(mod);
5570 fprintf(stderr, "\n");
5571 }
5572 }
5573
5574 if (sscreen->record_llvm_ir) {
5575 char *ir = LLVMPrintModuleToString(mod);
5576 binary->llvm_ir_string = strdup(ir);
5577 LLVMDisposeMessage(ir);
5578 }
5579
5580 if (!si_replace_shader(count, binary)) {
5581 r = si_llvm_compile(mod, binary, tm, debug);
5582 if (r)
5583 return r;
5584 }
5585
5586 si_shader_binary_read_config(binary, conf, 0);
5587
5588 /* Enable 64-bit and 16-bit denormals, because there is no performance
5589 * cost.
5590 *
5591 * If denormals are enabled, all floating-point output modifiers are
5592 * ignored.
5593 *
5594 * Don't enable denormals for 32-bit floats, because:
5595 * - Floating-point output modifiers would be ignored by the hw.
5596 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5597 * have to stop using those.
5598 * - SI & CI would be very slow.
5599 */
5600 conf->float_mode |= V_00B028_FP_64_DENORMS;
5601
5602 FREE(binary->config);
5603 FREE(binary->global_symbol_offsets);
5604 binary->config = NULL;
5605 binary->global_symbol_offsets = NULL;
5606
5607 /* Some shaders can't have rodata because their binaries can be
5608 * concatenated.
5609 */
5610 if (binary->rodata_size &&
5611 (processor == PIPE_SHADER_VERTEX ||
5612 processor == PIPE_SHADER_TESS_CTRL ||
5613 processor == PIPE_SHADER_TESS_EVAL ||
5614 processor == PIPE_SHADER_FRAGMENT)) {
5615 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5616 return -EINVAL;
5617 }
5618
5619 return r;
5620 }
5621
5622 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5623 {
5624 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5625 LLVMBuildRetVoid(ctx->ac.builder);
5626 else
5627 LLVMBuildRet(ctx->ac.builder, ret);
5628 }
5629
5630 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5631 struct si_shader *
5632 si_generate_gs_copy_shader(struct si_screen *sscreen,
5633 LLVMTargetMachineRef tm,
5634 struct si_shader_selector *gs_selector,
5635 struct pipe_debug_callback *debug)
5636 {
5637 struct si_shader_context ctx;
5638 struct si_shader *shader;
5639 LLVMBuilderRef builder;
5640 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
5641 struct lp_build_context *uint = &bld_base->uint_bld;
5642 struct si_shader_output_values *outputs;
5643 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5644 int i, r;
5645
5646 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5647
5648 if (!outputs)
5649 return NULL;
5650
5651 shader = CALLOC_STRUCT(si_shader);
5652 if (!shader) {
5653 FREE(outputs);
5654 return NULL;
5655 }
5656
5657 /* We can leave the fence as permanently signaled because the GS copy
5658 * shader only becomes visible globally after it has been compiled. */
5659 util_queue_fence_init(&shader->ready);
5660
5661 shader->selector = gs_selector;
5662 shader->is_gs_copy_shader = true;
5663
5664 si_init_shader_ctx(&ctx, sscreen, tm);
5665 ctx.shader = shader;
5666 ctx.type = PIPE_SHADER_VERTEX;
5667
5668 builder = ctx.ac.builder;
5669
5670 create_function(&ctx);
5671 preload_ring_buffers(&ctx);
5672
5673 LLVMValueRef voffset =
5674 lp_build_mul_imm(uint, ctx.abi.vertex_id, 4);
5675
5676 /* Fetch the vertex stream ID.*/
5677 LLVMValueRef stream_id;
5678
5679 if (gs_selector->so.num_outputs)
5680 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5681 else
5682 stream_id = ctx.i32_0;
5683
5684 /* Fill in output information. */
5685 for (i = 0; i < gsinfo->num_outputs; ++i) {
5686 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5687 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5688
5689 for (int chan = 0; chan < 4; chan++) {
5690 outputs[i].vertex_stream[chan] =
5691 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5692 }
5693 }
5694
5695 LLVMBasicBlockRef end_bb;
5696 LLVMValueRef switch_inst;
5697
5698 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5699 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5700
5701 for (int stream = 0; stream < 4; stream++) {
5702 LLVMBasicBlockRef bb;
5703 unsigned offset;
5704
5705 if (!gsinfo->num_stream_output_components[stream])
5706 continue;
5707
5708 if (stream > 0 && !gs_selector->so.num_outputs)
5709 continue;
5710
5711 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5712 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5713 LLVMPositionBuilderAtEnd(builder, bb);
5714
5715 /* Fetch vertex data from GSVS ring */
5716 offset = 0;
5717 for (i = 0; i < gsinfo->num_outputs; ++i) {
5718 for (unsigned chan = 0; chan < 4; chan++) {
5719 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5720 outputs[i].vertex_stream[chan] != stream) {
5721 outputs[i].values[chan] = ctx.bld_base.base.undef;
5722 continue;
5723 }
5724
5725 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5726 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5727 offset++;
5728
5729 outputs[i].values[chan] =
5730 ac_build_buffer_load(&ctx.ac,
5731 ctx.gsvs_ring[0], 1,
5732 ctx.i32_0, voffset,
5733 soffset, 0, 1, 1,
5734 true, false);
5735 }
5736 }
5737
5738 /* Streamout and exports. */
5739 if (gs_selector->so.num_outputs) {
5740 si_llvm_emit_streamout(&ctx, outputs,
5741 gsinfo->num_outputs,
5742 stream);
5743 }
5744
5745 if (stream == 0)
5746 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5747
5748 LLVMBuildBr(builder, end_bb);
5749 }
5750
5751 LLVMPositionBuilderAtEnd(builder, end_bb);
5752
5753 LLVMBuildRetVoid(ctx.ac.builder);
5754
5755 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5756 si_llvm_optimize_module(&ctx);
5757
5758 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5759 &ctx.shader->config, ctx.tm,
5760 ctx.gallivm.module,
5761 debug, PIPE_SHADER_GEOMETRY,
5762 "GS Copy Shader");
5763 if (!r) {
5764 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5765 fprintf(stderr, "GS Copy Shader:\n");
5766 si_shader_dump(sscreen, ctx.shader, debug,
5767 PIPE_SHADER_GEOMETRY, stderr, true);
5768 r = si_shader_binary_upload(sscreen, ctx.shader);
5769 }
5770
5771 si_llvm_dispose(&ctx);
5772
5773 FREE(outputs);
5774
5775 if (r != 0) {
5776 FREE(shader);
5777 shader = NULL;
5778 }
5779 return shader;
5780 }
5781
5782 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5783 const struct si_vs_prolog_bits *prolog,
5784 const char *prefix, FILE *f)
5785 {
5786 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5787 prefix, prolog->instance_divisor_is_one);
5788 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5789 prefix, prolog->instance_divisor_is_fetched);
5790 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5791 prefix, prolog->ls_vgpr_fix);
5792
5793 fprintf(f, " mono.vs.fix_fetch = {");
5794 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5795 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5796 fprintf(f, "}\n");
5797 }
5798
5799 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5800 FILE *f)
5801 {
5802 const struct si_shader_key *key = &shader->key;
5803
5804 fprintf(f, "SHADER KEY\n");
5805
5806 switch (processor) {
5807 case PIPE_SHADER_VERTEX:
5808 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5809 "part.vs.prolog", f);
5810 fprintf(f, " as_es = %u\n", key->as_es);
5811 fprintf(f, " as_ls = %u\n", key->as_ls);
5812 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5813 key->mono.u.vs_export_prim_id);
5814 break;
5815
5816 case PIPE_SHADER_TESS_CTRL:
5817 if (shader->selector->screen->info.chip_class >= GFX9) {
5818 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5819 "part.tcs.ls_prolog", f);
5820 }
5821 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5822 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5823 break;
5824
5825 case PIPE_SHADER_TESS_EVAL:
5826 fprintf(f, " as_es = %u\n", key->as_es);
5827 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5828 key->mono.u.vs_export_prim_id);
5829 break;
5830
5831 case PIPE_SHADER_GEOMETRY:
5832 if (shader->is_gs_copy_shader)
5833 break;
5834
5835 if (shader->selector->screen->info.chip_class >= GFX9 &&
5836 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5837 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5838 "part.gs.vs_prolog", f);
5839 }
5840 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5841 break;
5842
5843 case PIPE_SHADER_COMPUTE:
5844 break;
5845
5846 case PIPE_SHADER_FRAGMENT:
5847 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5848 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5849 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5850 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5851 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5852 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5853 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5854 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5855 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5856 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5857 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5858 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5859 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5860 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5861 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5862 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5863 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5864 break;
5865
5866 default:
5867 assert(0);
5868 }
5869
5870 if ((processor == PIPE_SHADER_GEOMETRY ||
5871 processor == PIPE_SHADER_TESS_EVAL ||
5872 processor == PIPE_SHADER_VERTEX) &&
5873 !key->as_es && !key->as_ls) {
5874 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5875 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5876 }
5877 }
5878
5879 static void si_init_shader_ctx(struct si_shader_context *ctx,
5880 struct si_screen *sscreen,
5881 LLVMTargetMachineRef tm)
5882 {
5883 struct lp_build_tgsi_context *bld_base;
5884
5885 si_llvm_context_init(ctx, sscreen, tm);
5886
5887 bld_base = &ctx->bld_base;
5888 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5889
5890 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5891 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5892 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5893
5894 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5895
5896 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5897
5898 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5899 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5900 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5901 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5902
5903 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5904 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5905 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5906 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5907 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5908 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5909 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5910 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
5911 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5912
5913 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5914 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_tgsi_emit_primitive;
5915 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5916 }
5917
5918 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5919 {
5920 struct si_shader *shader = ctx->shader;
5921 struct tgsi_shader_info *info = &shader->selector->info;
5922
5923 if ((ctx->type != PIPE_SHADER_VERTEX &&
5924 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5925 shader->key.as_ls ||
5926 shader->key.as_es)
5927 return;
5928
5929 ac_optimize_vs_outputs(&ctx->ac,
5930 ctx->main_fn,
5931 shader->info.vs_output_param_offset,
5932 info->num_outputs,
5933 &shader->info.nr_param_exports);
5934 }
5935
5936 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
5937 {
5938 ctx->shader->config.private_mem_vgprs = 0;
5939
5940 /* Process all LLVM instructions. */
5941 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
5942 while (bb) {
5943 LLVMValueRef next = LLVMGetFirstInstruction(bb);
5944
5945 while (next) {
5946 LLVMValueRef inst = next;
5947 next = LLVMGetNextInstruction(next);
5948
5949 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
5950 continue;
5951
5952 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
5953 /* No idea why LLVM aligns allocas to 4 elements. */
5954 unsigned alignment = LLVMGetAlignment(inst);
5955 unsigned dw_size = align(ac_get_type_size(type) / 4, alignment);
5956 ctx->shader->config.private_mem_vgprs += dw_size;
5957 }
5958 bb = LLVMGetNextBasicBlock(bb);
5959 }
5960 }
5961
5962 static void si_init_exec_from_input(struct si_shader_context *ctx,
5963 unsigned param, unsigned bitoffset)
5964 {
5965 LLVMValueRef args[] = {
5966 LLVMGetParam(ctx->main_fn, param),
5967 LLVMConstInt(ctx->i32, bitoffset, 0),
5968 };
5969 lp_build_intrinsic(ctx->ac.builder,
5970 "llvm.amdgcn.init.exec.from.input",
5971 ctx->voidt, args, 2, LP_FUNC_ATTR_CONVERGENT);
5972 }
5973
5974 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
5975 const struct si_vs_prolog_bits *key)
5976 {
5977 /* VGPR initialization fixup for Vega10 and Raven is always done in the
5978 * VS prolog. */
5979 return sel->vs_needs_prolog || key->ls_vgpr_fix;
5980 }
5981
5982 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
5983 bool is_monolithic)
5984 {
5985 struct si_shader *shader = ctx->shader;
5986 struct si_shader_selector *sel = shader->selector;
5987 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5988
5989 // TODO clean all this up!
5990 switch (ctx->type) {
5991 case PIPE_SHADER_VERTEX:
5992 ctx->load_input = declare_input_vs;
5993 if (shader->key.as_ls)
5994 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
5995 else if (shader->key.as_es)
5996 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5997 else
5998 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5999 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6000 break;
6001 case PIPE_SHADER_TESS_CTRL:
6002 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6003 ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
6004 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6005 bld_base->emit_store = store_output_tcs;
6006 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
6007 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
6008 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6009 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6010 break;
6011 case PIPE_SHADER_TESS_EVAL:
6012 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6013 ctx->abi.load_tess_varyings = si_nir_load_input_tes;
6014 ctx->abi.load_tess_coord = si_load_tess_coord;
6015 ctx->abi.load_tess_level = si_load_tess_level;
6016 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6017 if (shader->key.as_es)
6018 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6019 else
6020 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6021 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6022 break;
6023 case PIPE_SHADER_GEOMETRY:
6024 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6025 ctx->abi.load_inputs = si_nir_load_input_gs;
6026 ctx->abi.emit_vertex = si_llvm_emit_vertex;
6027 ctx->abi.emit_primitive = si_llvm_emit_primitive;
6028 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
6029 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
6030 break;
6031 case PIPE_SHADER_FRAGMENT:
6032 ctx->load_input = declare_input_fs;
6033 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
6034 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6035 ctx->abi.lookup_interp_param = si_nir_lookup_interp_param;
6036 ctx->abi.load_sample_position = load_sample_position;
6037 ctx->abi.load_sample_mask_in = load_sample_mask_in;
6038 break;
6039 case PIPE_SHADER_COMPUTE:
6040 ctx->abi.load_local_group_size = get_block_size;
6041 break;
6042 default:
6043 assert(!"Unsupported shader type");
6044 return false;
6045 }
6046
6047 ctx->abi.load_ubo = load_ubo;
6048 ctx->abi.load_ssbo = load_ssbo;
6049
6050 create_function(ctx);
6051 preload_ring_buffers(ctx);
6052
6053 /* For GFX9 merged shaders:
6054 * - Set EXEC for the first shader. If the prolog is present, set
6055 * EXEC there instead.
6056 * - Add a barrier before the second shader.
6057 * - In the second shader, reset EXEC to ~0 and wrap the main part in
6058 * an if-statement. This is required for correctness in geometry
6059 * shaders, to ensure that empty GS waves do not send GS_EMIT and
6060 * GS_CUT messages.
6061 *
6062 * For monolithic merged shaders, the first shader is wrapped in an
6063 * if-block together with its prolog in si_build_wrapper_function.
6064 */
6065 if (ctx->screen->info.chip_class >= GFX9) {
6066 if (!is_monolithic &&
6067 sel->info.num_instructions > 1 && /* not empty shader */
6068 (shader->key.as_es || shader->key.as_ls) &&
6069 (ctx->type == PIPE_SHADER_TESS_EVAL ||
6070 (ctx->type == PIPE_SHADER_VERTEX &&
6071 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
6072 si_init_exec_from_input(ctx,
6073 ctx->param_merged_wave_info, 0);
6074 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6075 ctx->type == PIPE_SHADER_GEOMETRY) {
6076 if (!is_monolithic)
6077 ac_init_exec_full_mask(&ctx->ac);
6078
6079 /* The barrier must execute for all shaders in a
6080 * threadgroup.
6081 */
6082 si_llvm_emit_barrier(NULL, bld_base, NULL);
6083
6084 LLVMValueRef num_threads = unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
6085 LLVMValueRef ena =
6086 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
6087 ac_get_thread_id(&ctx->ac), num_threads, "");
6088 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
6089 }
6090 }
6091
6092 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
6093 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
6094 for (unsigned i = 0; i < 6; i++) {
6095 ctx->invoc0_tess_factors[i] =
6096 lp_build_alloca_undef(&ctx->gallivm, ctx->i32, "");
6097 }
6098 }
6099
6100 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6101 int i;
6102 for (i = 0; i < 4; i++) {
6103 ctx->gs_next_vertex[i] =
6104 lp_build_alloca(&ctx->gallivm,
6105 ctx->i32, "");
6106 }
6107 }
6108
6109 if (sel->force_correct_derivs_after_kill) {
6110 ctx->postponed_kill = lp_build_alloca_undef(&ctx->gallivm, ctx->i1, "");
6111 /* true = don't kill. */
6112 LLVMBuildStore(ctx->ac.builder, LLVMConstInt(ctx->i1, 1, 0),
6113 ctx->postponed_kill);
6114 }
6115
6116 if (sel->tokens) {
6117 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6118 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6119 return false;
6120 }
6121 } else {
6122 if (!si_nir_build_llvm(ctx, sel->nir)) {
6123 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
6124 return false;
6125 }
6126 }
6127
6128 si_llvm_build_ret(ctx, ctx->return_value);
6129 return true;
6130 }
6131
6132 /**
6133 * Compute the VS prolog key, which contains all the information needed to
6134 * build the VS prolog function, and set shader->info bits where needed.
6135 *
6136 * \param info Shader info of the vertex shader.
6137 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6138 * \param prolog_key Key of the VS prolog
6139 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6140 * \param key Output shader part key.
6141 */
6142 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
6143 unsigned num_input_sgprs,
6144 const struct si_vs_prolog_bits *prolog_key,
6145 struct si_shader *shader_out,
6146 union si_shader_part_key *key)
6147 {
6148 memset(key, 0, sizeof(*key));
6149 key->vs_prolog.states = *prolog_key;
6150 key->vs_prolog.num_input_sgprs = num_input_sgprs;
6151 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6152 key->vs_prolog.as_ls = shader_out->key.as_ls;
6153 key->vs_prolog.as_es = shader_out->key.as_es;
6154
6155 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
6156 key->vs_prolog.as_ls = 1;
6157 key->vs_prolog.num_merged_next_stage_vgprs = 2;
6158 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
6159 key->vs_prolog.as_es = 1;
6160 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6161 }
6162
6163 /* Enable loading the InstanceID VGPR. */
6164 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
6165
6166 if ((key->vs_prolog.states.instance_divisor_is_one |
6167 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
6168 shader_out->info.uses_instanceid = true;
6169 }
6170
6171 /**
6172 * Compute the PS prolog key, which contains all the information needed to
6173 * build the PS prolog function, and set related bits in shader->config.
6174 */
6175 static void si_get_ps_prolog_key(struct si_shader *shader,
6176 union si_shader_part_key *key,
6177 bool separate_prolog)
6178 {
6179 struct tgsi_shader_info *info = &shader->selector->info;
6180
6181 memset(key, 0, sizeof(*key));
6182 key->ps_prolog.states = shader->key.part.ps.prolog;
6183 key->ps_prolog.colors_read = info->colors_read;
6184 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6185 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6186 key->ps_prolog.wqm = info->uses_derivatives &&
6187 (key->ps_prolog.colors_read ||
6188 key->ps_prolog.states.force_persp_sample_interp ||
6189 key->ps_prolog.states.force_linear_sample_interp ||
6190 key->ps_prolog.states.force_persp_center_interp ||
6191 key->ps_prolog.states.force_linear_center_interp ||
6192 key->ps_prolog.states.bc_optimize_for_persp ||
6193 key->ps_prolog.states.bc_optimize_for_linear);
6194 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
6195
6196 if (info->colors_read) {
6197 unsigned *color = shader->selector->color_attr_index;
6198
6199 if (shader->key.part.ps.prolog.color_two_side) {
6200 /* BCOLORs are stored after the last input. */
6201 key->ps_prolog.num_interp_inputs = info->num_inputs;
6202 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6203 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6204 }
6205
6206 for (unsigned i = 0; i < 2; i++) {
6207 unsigned interp = info->input_interpolate[color[i]];
6208 unsigned location = info->input_interpolate_loc[color[i]];
6209
6210 if (!(info->colors_read & (0xf << i*4)))
6211 continue;
6212
6213 key->ps_prolog.color_attr_index[i] = color[i];
6214
6215 if (shader->key.part.ps.prolog.flatshade_colors &&
6216 interp == TGSI_INTERPOLATE_COLOR)
6217 interp = TGSI_INTERPOLATE_CONSTANT;
6218
6219 switch (interp) {
6220 case TGSI_INTERPOLATE_CONSTANT:
6221 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6222 break;
6223 case TGSI_INTERPOLATE_PERSPECTIVE:
6224 case TGSI_INTERPOLATE_COLOR:
6225 /* Force the interpolation location for colors here. */
6226 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6227 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6228 if (shader->key.part.ps.prolog.force_persp_center_interp)
6229 location = TGSI_INTERPOLATE_LOC_CENTER;
6230
6231 switch (location) {
6232 case TGSI_INTERPOLATE_LOC_SAMPLE:
6233 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6234 shader->config.spi_ps_input_ena |=
6235 S_0286CC_PERSP_SAMPLE_ENA(1);
6236 break;
6237 case TGSI_INTERPOLATE_LOC_CENTER:
6238 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6239 shader->config.spi_ps_input_ena |=
6240 S_0286CC_PERSP_CENTER_ENA(1);
6241 break;
6242 case TGSI_INTERPOLATE_LOC_CENTROID:
6243 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6244 shader->config.spi_ps_input_ena |=
6245 S_0286CC_PERSP_CENTROID_ENA(1);
6246 break;
6247 default:
6248 assert(0);
6249 }
6250 break;
6251 case TGSI_INTERPOLATE_LINEAR:
6252 /* Force the interpolation location for colors here. */
6253 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6254 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6255 if (shader->key.part.ps.prolog.force_linear_center_interp)
6256 location = TGSI_INTERPOLATE_LOC_CENTER;
6257
6258 /* The VGPR assignment for non-monolithic shaders
6259 * works because InitialPSInputAddr is set on the
6260 * main shader and PERSP_PULL_MODEL is never used.
6261 */
6262 switch (location) {
6263 case TGSI_INTERPOLATE_LOC_SAMPLE:
6264 key->ps_prolog.color_interp_vgpr_index[i] =
6265 separate_prolog ? 6 : 9;
6266 shader->config.spi_ps_input_ena |=
6267 S_0286CC_LINEAR_SAMPLE_ENA(1);
6268 break;
6269 case TGSI_INTERPOLATE_LOC_CENTER:
6270 key->ps_prolog.color_interp_vgpr_index[i] =
6271 separate_prolog ? 8 : 11;
6272 shader->config.spi_ps_input_ena |=
6273 S_0286CC_LINEAR_CENTER_ENA(1);
6274 break;
6275 case TGSI_INTERPOLATE_LOC_CENTROID:
6276 key->ps_prolog.color_interp_vgpr_index[i] =
6277 separate_prolog ? 10 : 13;
6278 shader->config.spi_ps_input_ena |=
6279 S_0286CC_LINEAR_CENTROID_ENA(1);
6280 break;
6281 default:
6282 assert(0);
6283 }
6284 break;
6285 default:
6286 assert(0);
6287 }
6288 }
6289 }
6290 }
6291
6292 /**
6293 * Check whether a PS prolog is required based on the key.
6294 */
6295 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6296 {
6297 return key->ps_prolog.colors_read ||
6298 key->ps_prolog.states.force_persp_sample_interp ||
6299 key->ps_prolog.states.force_linear_sample_interp ||
6300 key->ps_prolog.states.force_persp_center_interp ||
6301 key->ps_prolog.states.force_linear_center_interp ||
6302 key->ps_prolog.states.bc_optimize_for_persp ||
6303 key->ps_prolog.states.bc_optimize_for_linear ||
6304 key->ps_prolog.states.poly_stipple ||
6305 key->ps_prolog.states.samplemask_log_ps_iter;
6306 }
6307
6308 /**
6309 * Compute the PS epilog key, which contains all the information needed to
6310 * build the PS epilog function.
6311 */
6312 static void si_get_ps_epilog_key(struct si_shader *shader,
6313 union si_shader_part_key *key)
6314 {
6315 struct tgsi_shader_info *info = &shader->selector->info;
6316 memset(key, 0, sizeof(*key));
6317 key->ps_epilog.colors_written = info->colors_written;
6318 key->ps_epilog.writes_z = info->writes_z;
6319 key->ps_epilog.writes_stencil = info->writes_stencil;
6320 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6321 key->ps_epilog.states = shader->key.part.ps.epilog;
6322 }
6323
6324 /**
6325 * Build the GS prolog function. Rotate the input vertices for triangle strips
6326 * with adjacency.
6327 */
6328 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6329 union si_shader_part_key *key)
6330 {
6331 unsigned num_sgprs, num_vgprs;
6332 struct si_function_info fninfo;
6333 LLVMBuilderRef builder = ctx->ac.builder;
6334 LLVMTypeRef returns[48];
6335 LLVMValueRef func, ret;
6336
6337 si_init_function_info(&fninfo);
6338
6339 if (ctx->screen->info.chip_class >= GFX9) {
6340 num_sgprs = 8 + GFX9_GS_NUM_USER_SGPR;
6341 num_vgprs = 5; /* ES inputs are not needed by GS */
6342 } else {
6343 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6344 num_vgprs = 8;
6345 }
6346
6347 for (unsigned i = 0; i < num_sgprs; ++i) {
6348 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6349 returns[i] = ctx->i32;
6350 }
6351
6352 for (unsigned i = 0; i < num_vgprs; ++i) {
6353 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6354 returns[num_sgprs + i] = ctx->f32;
6355 }
6356
6357 /* Create the function. */
6358 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6359 &fninfo, 0);
6360 func = ctx->main_fn;
6361
6362 /* Set the full EXEC mask for the prolog, because we are only fiddling
6363 * with registers here. The main shader part will set the correct EXEC
6364 * mask.
6365 */
6366 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6367 ac_init_exec_full_mask(&ctx->ac);
6368
6369 /* Copy inputs to outputs. This should be no-op, as the registers match,
6370 * but it will prevent the compiler from overwriting them unintentionally.
6371 */
6372 ret = ctx->return_value;
6373 for (unsigned i = 0; i < num_sgprs; i++) {
6374 LLVMValueRef p = LLVMGetParam(func, i);
6375 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6376 }
6377 for (unsigned i = 0; i < num_vgprs; i++) {
6378 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6379 p = ac_to_float(&ctx->ac, p);
6380 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6381 }
6382
6383 if (key->gs_prolog.states.tri_strip_adj_fix) {
6384 /* Remap the input vertices for every other primitive. */
6385 const unsigned gfx6_vtx_params[6] = {
6386 num_sgprs,
6387 num_sgprs + 1,
6388 num_sgprs + 3,
6389 num_sgprs + 4,
6390 num_sgprs + 5,
6391 num_sgprs + 6
6392 };
6393 const unsigned gfx9_vtx_params[3] = {
6394 num_sgprs,
6395 num_sgprs + 1,
6396 num_sgprs + 4,
6397 };
6398 LLVMValueRef vtx_in[6], vtx_out[6];
6399 LLVMValueRef prim_id, rotate;
6400
6401 if (ctx->screen->info.chip_class >= GFX9) {
6402 for (unsigned i = 0; i < 3; i++) {
6403 vtx_in[i*2] = unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6404 vtx_in[i*2+1] = unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6405 }
6406 } else {
6407 for (unsigned i = 0; i < 6; i++)
6408 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6409 }
6410
6411 prim_id = LLVMGetParam(func, num_sgprs + 2);
6412 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6413
6414 for (unsigned i = 0; i < 6; ++i) {
6415 LLVMValueRef base, rotated;
6416 base = vtx_in[i];
6417 rotated = vtx_in[(i + 4) % 6];
6418 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6419 }
6420
6421 if (ctx->screen->info.chip_class >= GFX9) {
6422 for (unsigned i = 0; i < 3; i++) {
6423 LLVMValueRef hi, out;
6424
6425 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6426 LLVMConstInt(ctx->i32, 16, 0), "");
6427 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6428 out = ac_to_float(&ctx->ac, out);
6429 ret = LLVMBuildInsertValue(builder, ret, out,
6430 gfx9_vtx_params[i], "");
6431 }
6432 } else {
6433 for (unsigned i = 0; i < 6; i++) {
6434 LLVMValueRef out;
6435
6436 out = ac_to_float(&ctx->ac, vtx_out[i]);
6437 ret = LLVMBuildInsertValue(builder, ret, out,
6438 gfx6_vtx_params[i], "");
6439 }
6440 }
6441 }
6442
6443 LLVMBuildRet(builder, ret);
6444 }
6445
6446 /**
6447 * Given a list of shader part functions, build a wrapper function that
6448 * runs them in sequence to form a monolithic shader.
6449 */
6450 static void si_build_wrapper_function(struct si_shader_context *ctx,
6451 LLVMValueRef *parts,
6452 unsigned num_parts,
6453 unsigned main_part,
6454 unsigned next_shader_first_part)
6455 {
6456 LLVMBuilderRef builder = ctx->ac.builder;
6457 /* PS epilog has one arg per color component; gfx9 merged shader
6458 * prologs need to forward 32 user SGPRs.
6459 */
6460 struct si_function_info fninfo;
6461 LLVMValueRef initial[64], out[64];
6462 LLVMTypeRef function_type;
6463 unsigned num_first_params;
6464 unsigned num_out, initial_num_out;
6465 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6466 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6467 unsigned num_sgprs, num_vgprs;
6468 unsigned gprs;
6469 struct lp_build_if_state if_state;
6470
6471 si_init_function_info(&fninfo);
6472
6473 for (unsigned i = 0; i < num_parts; ++i) {
6474 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6475 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6476 }
6477
6478 /* The parameters of the wrapper function correspond to those of the
6479 * first part in terms of SGPRs and VGPRs, but we use the types of the
6480 * main part to get the right types. This is relevant for the
6481 * dereferenceable attribute on descriptor table pointers.
6482 */
6483 num_sgprs = 0;
6484 num_vgprs = 0;
6485
6486 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6487 num_first_params = LLVMCountParamTypes(function_type);
6488
6489 for (unsigned i = 0; i < num_first_params; ++i) {
6490 LLVMValueRef param = LLVMGetParam(parts[0], i);
6491
6492 if (ac_is_sgpr_param(param)) {
6493 assert(num_vgprs == 0);
6494 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6495 } else {
6496 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6497 }
6498 }
6499
6500 gprs = 0;
6501 while (gprs < num_sgprs + num_vgprs) {
6502 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6503 LLVMTypeRef type = LLVMTypeOf(param);
6504 unsigned size = ac_get_type_size(type) / 4;
6505
6506 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6507
6508 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6509 assert(gprs + size <= num_sgprs + num_vgprs &&
6510 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6511
6512 gprs += size;
6513 }
6514
6515 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6516 si_get_max_workgroup_size(ctx->shader));
6517
6518 if (is_merged_shader(ctx->shader))
6519 ac_init_exec_full_mask(&ctx->ac);
6520
6521 /* Record the arguments of the function as if they were an output of
6522 * a previous part.
6523 */
6524 num_out = 0;
6525 num_out_sgpr = 0;
6526
6527 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6528 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6529 LLVMTypeRef param_type = LLVMTypeOf(param);
6530 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6531 unsigned size = ac_get_type_size(param_type) / 4;
6532
6533 if (size == 1) {
6534 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6535 param = LLVMBuildPtrToInt(builder, param, ctx->i32, "");
6536 param_type = ctx->i32;
6537 }
6538
6539 if (param_type != out_type)
6540 param = LLVMBuildBitCast(builder, param, out_type, "");
6541 out[num_out++] = param;
6542 } else {
6543 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6544
6545 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6546 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6547 param_type = ctx->i64;
6548 }
6549
6550 if (param_type != vector_type)
6551 param = LLVMBuildBitCast(builder, param, vector_type, "");
6552
6553 for (unsigned j = 0; j < size; ++j)
6554 out[num_out++] = LLVMBuildExtractElement(
6555 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6556 }
6557
6558 if (i < fninfo.num_sgpr_params)
6559 num_out_sgpr = num_out;
6560 }
6561
6562 memcpy(initial, out, sizeof(out));
6563 initial_num_out = num_out;
6564 initial_num_out_sgpr = num_out_sgpr;
6565
6566 /* Now chain the parts. */
6567 for (unsigned part = 0; part < num_parts; ++part) {
6568 LLVMValueRef in[48];
6569 LLVMValueRef ret;
6570 LLVMTypeRef ret_type;
6571 unsigned out_idx = 0;
6572 unsigned num_params = LLVMCountParams(parts[part]);
6573
6574 /* Merged shaders are executed conditionally depending
6575 * on the number of enabled threads passed in the input SGPRs. */
6576 if (is_merged_shader(ctx->shader) && part == 0) {
6577 LLVMValueRef ena, count = initial[3];
6578
6579 count = LLVMBuildAnd(builder, count,
6580 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6581 ena = LLVMBuildICmp(builder, LLVMIntULT,
6582 ac_get_thread_id(&ctx->ac), count, "");
6583 lp_build_if(&if_state, &ctx->gallivm, ena);
6584 }
6585
6586 /* Derive arguments for the next part from outputs of the
6587 * previous one.
6588 */
6589 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6590 LLVMValueRef param;
6591 LLVMTypeRef param_type;
6592 bool is_sgpr;
6593 unsigned param_size;
6594 LLVMValueRef arg = NULL;
6595
6596 param = LLVMGetParam(parts[part], param_idx);
6597 param_type = LLVMTypeOf(param);
6598 param_size = ac_get_type_size(param_type) / 4;
6599 is_sgpr = ac_is_sgpr_param(param);
6600
6601 if (is_sgpr)
6602 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
6603 else if (out_idx < num_out_sgpr) {
6604 /* Skip returned SGPRs the current part doesn't
6605 * declare on the input. */
6606 out_idx = num_out_sgpr;
6607 }
6608
6609 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6610
6611 if (param_size == 1)
6612 arg = out[out_idx];
6613 else
6614 arg = lp_build_gather_values(&ctx->gallivm, &out[out_idx], param_size);
6615
6616 if (LLVMTypeOf(arg) != param_type) {
6617 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6618 if (LLVMGetPointerAddressSpace(param_type) ==
6619 AC_CONST_32BIT_ADDR_SPACE) {
6620 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
6621 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6622 } else {
6623 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6624 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6625 }
6626 } else {
6627 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6628 }
6629 }
6630
6631 in[param_idx] = arg;
6632 out_idx += param_size;
6633 }
6634
6635 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6636
6637 if (is_merged_shader(ctx->shader) &&
6638 part + 1 == next_shader_first_part) {
6639 lp_build_endif(&if_state);
6640
6641 /* The second half of the merged shader should use
6642 * the inputs from the toplevel (wrapper) function,
6643 * not the return value from the last call.
6644 *
6645 * That's because the last call was executed condi-
6646 * tionally, so we can't consume it in the main
6647 * block.
6648 */
6649 memcpy(out, initial, sizeof(initial));
6650 num_out = initial_num_out;
6651 num_out_sgpr = initial_num_out_sgpr;
6652 continue;
6653 }
6654
6655 /* Extract the returned GPRs. */
6656 ret_type = LLVMTypeOf(ret);
6657 num_out = 0;
6658 num_out_sgpr = 0;
6659
6660 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6661 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6662
6663 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6664
6665 for (unsigned i = 0; i < ret_size; ++i) {
6666 LLVMValueRef val =
6667 LLVMBuildExtractValue(builder, ret, i, "");
6668
6669 assert(num_out < ARRAY_SIZE(out));
6670 out[num_out++] = val;
6671
6672 if (LLVMTypeOf(val) == ctx->i32) {
6673 assert(num_out_sgpr + 1 == num_out);
6674 num_out_sgpr = num_out;
6675 }
6676 }
6677 }
6678 }
6679
6680 LLVMBuildRetVoid(builder);
6681 }
6682
6683 int si_compile_tgsi_shader(struct si_screen *sscreen,
6684 LLVMTargetMachineRef tm,
6685 struct si_shader *shader,
6686 bool is_monolithic,
6687 struct pipe_debug_callback *debug)
6688 {
6689 struct si_shader_selector *sel = shader->selector;
6690 struct si_shader_context ctx;
6691 int r = -1;
6692
6693 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6694 * conversion fails. */
6695 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6696 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6697 if (sel->tokens)
6698 tgsi_dump(sel->tokens, 0);
6699 else
6700 nir_print_shader(sel->nir, stderr);
6701 si_dump_streamout(&sel->so);
6702 }
6703
6704 si_init_shader_ctx(&ctx, sscreen, tm);
6705 si_llvm_context_set_tgsi(&ctx, shader);
6706 ctx.separate_prolog = !is_monolithic;
6707
6708 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6709 sizeof(shader->info.vs_output_param_offset));
6710
6711 shader->info.uses_instanceid = sel->info.uses_instanceid;
6712
6713 if (!si_compile_tgsi_main(&ctx, is_monolithic)) {
6714 si_llvm_dispose(&ctx);
6715 return -1;
6716 }
6717
6718 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6719 LLVMValueRef parts[2];
6720 bool need_prolog = sel->vs_needs_prolog;
6721
6722 parts[1] = ctx.main_fn;
6723
6724 if (need_prolog) {
6725 union si_shader_part_key prolog_key;
6726 si_get_vs_prolog_key(&sel->info,
6727 shader->info.num_input_sgprs,
6728 &shader->key.part.vs.prolog,
6729 shader, &prolog_key);
6730 si_build_vs_prolog_function(&ctx, &prolog_key);
6731 parts[0] = ctx.main_fn;
6732 }
6733
6734 si_build_wrapper_function(&ctx, parts + !need_prolog,
6735 1 + need_prolog, need_prolog, 0);
6736 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6737 if (sscreen->info.chip_class >= GFX9) {
6738 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6739 LLVMValueRef parts[4];
6740 bool vs_needs_prolog =
6741 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6742
6743 /* TCS main part */
6744 parts[2] = ctx.main_fn;
6745
6746 /* TCS epilog */
6747 union si_shader_part_key tcs_epilog_key;
6748 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6749 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6750 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6751 parts[3] = ctx.main_fn;
6752
6753 /* VS as LS main part */
6754 struct si_shader shader_ls = {};
6755 shader_ls.selector = ls;
6756 shader_ls.key.as_ls = 1;
6757 shader_ls.key.mono = shader->key.mono;
6758 shader_ls.key.opt = shader->key.opt;
6759 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6760
6761 if (!si_compile_tgsi_main(&ctx, true)) {
6762 si_llvm_dispose(&ctx);
6763 return -1;
6764 }
6765 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6766 parts[1] = ctx.main_fn;
6767
6768 /* LS prolog */
6769 if (vs_needs_prolog) {
6770 union si_shader_part_key vs_prolog_key;
6771 si_get_vs_prolog_key(&ls->info,
6772 shader_ls.info.num_input_sgprs,
6773 &shader->key.part.tcs.ls_prolog,
6774 shader, &vs_prolog_key);
6775 vs_prolog_key.vs_prolog.is_monolithic = true;
6776 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6777 parts[0] = ctx.main_fn;
6778 }
6779
6780 /* Reset the shader context. */
6781 ctx.shader = shader;
6782 ctx.type = PIPE_SHADER_TESS_CTRL;
6783
6784 si_build_wrapper_function(&ctx,
6785 parts + !vs_needs_prolog,
6786 4 - !vs_needs_prolog, 0,
6787 vs_needs_prolog ? 2 : 1);
6788 } else {
6789 LLVMValueRef parts[2];
6790 union si_shader_part_key epilog_key;
6791
6792 parts[0] = ctx.main_fn;
6793
6794 memset(&epilog_key, 0, sizeof(epilog_key));
6795 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6796 si_build_tcs_epilog_function(&ctx, &epilog_key);
6797 parts[1] = ctx.main_fn;
6798
6799 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6800 }
6801 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6802 if (ctx.screen->info.chip_class >= GFX9) {
6803 struct si_shader_selector *es = shader->key.part.gs.es;
6804 LLVMValueRef es_prolog = NULL;
6805 LLVMValueRef es_main = NULL;
6806 LLVMValueRef gs_prolog = NULL;
6807 LLVMValueRef gs_main = ctx.main_fn;
6808
6809 /* GS prolog */
6810 union si_shader_part_key gs_prolog_key;
6811 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6812 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6813 gs_prolog_key.gs_prolog.is_monolithic = true;
6814 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6815 gs_prolog = ctx.main_fn;
6816
6817 /* ES main part */
6818 struct si_shader shader_es = {};
6819 shader_es.selector = es;
6820 shader_es.key.as_es = 1;
6821 shader_es.key.mono = shader->key.mono;
6822 shader_es.key.opt = shader->key.opt;
6823 si_llvm_context_set_tgsi(&ctx, &shader_es);
6824
6825 if (!si_compile_tgsi_main(&ctx, true)) {
6826 si_llvm_dispose(&ctx);
6827 return -1;
6828 }
6829 shader->info.uses_instanceid |= es->info.uses_instanceid;
6830 es_main = ctx.main_fn;
6831
6832 /* ES prolog */
6833 if (es->vs_needs_prolog) {
6834 union si_shader_part_key vs_prolog_key;
6835 si_get_vs_prolog_key(&es->info,
6836 shader_es.info.num_input_sgprs,
6837 &shader->key.part.gs.vs_prolog,
6838 shader, &vs_prolog_key);
6839 vs_prolog_key.vs_prolog.is_monolithic = true;
6840 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6841 es_prolog = ctx.main_fn;
6842 }
6843
6844 /* Reset the shader context. */
6845 ctx.shader = shader;
6846 ctx.type = PIPE_SHADER_GEOMETRY;
6847
6848 /* Prepare the array of shader parts. */
6849 LLVMValueRef parts[4];
6850 unsigned num_parts = 0, main_part, next_first_part;
6851
6852 if (es_prolog)
6853 parts[num_parts++] = es_prolog;
6854
6855 parts[main_part = num_parts++] = es_main;
6856 parts[next_first_part = num_parts++] = gs_prolog;
6857 parts[num_parts++] = gs_main;
6858
6859 si_build_wrapper_function(&ctx, parts, num_parts,
6860 main_part, next_first_part);
6861 } else {
6862 LLVMValueRef parts[2];
6863 union si_shader_part_key prolog_key;
6864
6865 parts[1] = ctx.main_fn;
6866
6867 memset(&prolog_key, 0, sizeof(prolog_key));
6868 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6869 si_build_gs_prolog_function(&ctx, &prolog_key);
6870 parts[0] = ctx.main_fn;
6871
6872 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6873 }
6874 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6875 LLVMValueRef parts[3];
6876 union si_shader_part_key prolog_key;
6877 union si_shader_part_key epilog_key;
6878 bool need_prolog;
6879
6880 si_get_ps_prolog_key(shader, &prolog_key, false);
6881 need_prolog = si_need_ps_prolog(&prolog_key);
6882
6883 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6884
6885 if (need_prolog) {
6886 si_build_ps_prolog_function(&ctx, &prolog_key);
6887 parts[0] = ctx.main_fn;
6888 }
6889
6890 si_get_ps_epilog_key(shader, &epilog_key);
6891 si_build_ps_epilog_function(&ctx, &epilog_key);
6892 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6893
6894 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6895 need_prolog ? 1 : 0, 0);
6896 }
6897
6898 si_llvm_optimize_module(&ctx);
6899
6900 /* Post-optimization transformations and analysis. */
6901 si_optimize_vs_outputs(&ctx);
6902
6903 if ((debug && debug->debug_message) ||
6904 si_can_dump_shader(sscreen, ctx.type))
6905 si_count_scratch_private_memory(&ctx);
6906
6907 /* Compile to bytecode. */
6908 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6909 ctx.gallivm.module, debug, ctx.type, "TGSI shader");
6910 si_llvm_dispose(&ctx);
6911 if (r) {
6912 fprintf(stderr, "LLVM failed to compile shader\n");
6913 return r;
6914 }
6915
6916 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6917 * LLVM 3.9svn has this bug.
6918 */
6919 if (sel->type == PIPE_SHADER_COMPUTE) {
6920 unsigned wave_size = 64;
6921 unsigned max_vgprs = 256;
6922 unsigned max_sgprs = sscreen->info.chip_class >= VI ? 800 : 512;
6923 unsigned max_sgprs_per_wave = 128;
6924 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6925 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6926 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6927
6928 max_vgprs = max_vgprs / min_waves_per_simd;
6929 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6930
6931 if (shader->config.num_sgprs > max_sgprs ||
6932 shader->config.num_vgprs > max_vgprs) {
6933 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6934 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6935 shader->config.num_sgprs, shader->config.num_vgprs,
6936 max_sgprs, max_vgprs);
6937
6938 /* Just terminate the process, because dependent
6939 * shaders can hang due to bad input data, but use
6940 * the env var to allow shader-db to work.
6941 */
6942 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6943 abort();
6944 }
6945 }
6946
6947 /* Add the scratch offset to input SGPRs. */
6948 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(shader))
6949 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6950
6951 /* Calculate the number of fragment input VGPRs. */
6952 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6953 shader->info.num_input_vgprs = 0;
6954 shader->info.face_vgpr_index = -1;
6955 shader->info.ancillary_vgpr_index = -1;
6956
6957 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6958 shader->info.num_input_vgprs += 2;
6959 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6960 shader->info.num_input_vgprs += 2;
6961 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6962 shader->info.num_input_vgprs += 2;
6963 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6964 shader->info.num_input_vgprs += 3;
6965 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6966 shader->info.num_input_vgprs += 2;
6967 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6968 shader->info.num_input_vgprs += 2;
6969 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6970 shader->info.num_input_vgprs += 2;
6971 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6972 shader->info.num_input_vgprs += 1;
6973 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6974 shader->info.num_input_vgprs += 1;
6975 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6976 shader->info.num_input_vgprs += 1;
6977 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6978 shader->info.num_input_vgprs += 1;
6979 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6980 shader->info.num_input_vgprs += 1;
6981 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6982 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6983 shader->info.num_input_vgprs += 1;
6984 }
6985 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
6986 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
6987 shader->info.num_input_vgprs += 1;
6988 }
6989 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6990 shader->info.num_input_vgprs += 1;
6991 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6992 shader->info.num_input_vgprs += 1;
6993 }
6994
6995 si_calculate_max_simd_waves(shader);
6996 si_shader_dump_stats_for_shader_db(shader, debug);
6997 return 0;
6998 }
6999
7000 /**
7001 * Create, compile and return a shader part (prolog or epilog).
7002 *
7003 * \param sscreen screen
7004 * \param list list of shader parts of the same category
7005 * \param type shader type
7006 * \param key shader part key
7007 * \param prolog whether the part being requested is a prolog
7008 * \param tm LLVM target machine
7009 * \param debug debug callback
7010 * \param build the callback responsible for building the main function
7011 * \return non-NULL on success
7012 */
7013 static struct si_shader_part *
7014 si_get_shader_part(struct si_screen *sscreen,
7015 struct si_shader_part **list,
7016 enum pipe_shader_type type,
7017 bool prolog,
7018 union si_shader_part_key *key,
7019 LLVMTargetMachineRef tm,
7020 struct pipe_debug_callback *debug,
7021 void (*build)(struct si_shader_context *,
7022 union si_shader_part_key *),
7023 const char *name)
7024 {
7025 struct si_shader_part *result;
7026
7027 mtx_lock(&sscreen->shader_parts_mutex);
7028
7029 /* Find existing. */
7030 for (result = *list; result; result = result->next) {
7031 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7032 mtx_unlock(&sscreen->shader_parts_mutex);
7033 return result;
7034 }
7035 }
7036
7037 /* Compile a new one. */
7038 result = CALLOC_STRUCT(si_shader_part);
7039 result->key = *key;
7040
7041 struct si_shader shader = {};
7042 struct si_shader_context ctx;
7043
7044 si_init_shader_ctx(&ctx, sscreen, tm);
7045 ctx.shader = &shader;
7046 ctx.type = type;
7047
7048 switch (type) {
7049 case PIPE_SHADER_VERTEX:
7050 shader.key.as_ls = key->vs_prolog.as_ls;
7051 shader.key.as_es = key->vs_prolog.as_es;
7052 break;
7053 case PIPE_SHADER_TESS_CTRL:
7054 assert(!prolog);
7055 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7056 break;
7057 case PIPE_SHADER_GEOMETRY:
7058 assert(prolog);
7059 break;
7060 case PIPE_SHADER_FRAGMENT:
7061 if (prolog)
7062 shader.key.part.ps.prolog = key->ps_prolog.states;
7063 else
7064 shader.key.part.ps.epilog = key->ps_epilog.states;
7065 break;
7066 default:
7067 unreachable("bad shader part");
7068 }
7069
7070 build(&ctx, key);
7071
7072 /* Compile. */
7073 si_llvm_optimize_module(&ctx);
7074
7075 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7076 ctx.ac.module, debug, ctx.type, name)) {
7077 FREE(result);
7078 result = NULL;
7079 goto out;
7080 }
7081
7082 result->next = *list;
7083 *list = result;
7084
7085 out:
7086 si_llvm_dispose(&ctx);
7087 mtx_unlock(&sscreen->shader_parts_mutex);
7088 return result;
7089 }
7090
7091 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
7092 {
7093 LLVMValueRef ptr[2], list;
7094 bool is_merged_shader =
7095 ctx->screen->info.chip_class >= GFX9 &&
7096 (ctx->type == PIPE_SHADER_TESS_CTRL ||
7097 ctx->type == PIPE_SHADER_GEOMETRY ||
7098 ctx->shader->key.as_ls || ctx->shader->key.as_es);
7099
7100 if (HAVE_32BIT_POINTERS) {
7101 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7102 list = LLVMBuildIntToPtr(ctx->ac.builder, ptr[0],
7103 ac_array_in_const32_addr_space(ctx->v4i32), "");
7104 return list;
7105 }
7106
7107 /* Get the pointer to rw buffers. */
7108 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7109 ptr[1] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS + 1);
7110 list = lp_build_gather_values(&ctx->gallivm, ptr, 2);
7111 list = LLVMBuildBitCast(ctx->ac.builder, list, ctx->i64, "");
7112 list = LLVMBuildIntToPtr(ctx->ac.builder, list,
7113 ac_array_in_const_addr_space(ctx->v4i32), "");
7114 return list;
7115 }
7116
7117 /**
7118 * Build the vertex shader prolog function.
7119 *
7120 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7121 * All inputs are returned unmodified. The vertex load indices are
7122 * stored after them, which will be used by the API VS for fetching inputs.
7123 *
7124 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7125 * input_v0,
7126 * input_v1,
7127 * input_v2,
7128 * input_v3,
7129 * (VertexID + BaseVertex),
7130 * (InstanceID + StartInstance),
7131 * (InstanceID / 2 + StartInstance)
7132 */
7133 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7134 union si_shader_part_key *key)
7135 {
7136 struct si_function_info fninfo;
7137 LLVMTypeRef *returns;
7138 LLVMValueRef ret, func;
7139 int num_returns, i;
7140 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
7141 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
7142 LLVMValueRef input_vgprs[9];
7143 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
7144 num_input_vgprs;
7145 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
7146
7147 si_init_function_info(&fninfo);
7148
7149 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7150 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
7151 sizeof(LLVMTypeRef));
7152 num_returns = 0;
7153
7154 /* Declare input and output SGPRs. */
7155 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7156 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7157 returns[num_returns++] = ctx->i32;
7158 }
7159
7160 /* Preloaded VGPRs (outputs must be floats) */
7161 for (i = 0; i < num_input_vgprs; i++) {
7162 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
7163 returns[num_returns++] = ctx->f32;
7164 }
7165
7166 /* Vertex load indices. */
7167 for (i = 0; i <= key->vs_prolog.last_input; i++)
7168 returns[num_returns++] = ctx->f32;
7169
7170 /* Create the function. */
7171 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
7172 func = ctx->main_fn;
7173
7174 if (key->vs_prolog.num_merged_next_stage_vgprs) {
7175 if (!key->vs_prolog.is_monolithic)
7176 si_init_exec_from_input(ctx, 3, 0);
7177
7178 if (key->vs_prolog.as_ls &&
7179 ctx->screen->has_ls_vgpr_init_bug) {
7180 /* If there are no HS threads, SPI loads the LS VGPRs
7181 * starting at VGPR 0. Shift them back to where they
7182 * belong.
7183 */
7184 LLVMValueRef has_hs_threads =
7185 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
7186 unpack_param(ctx, 3, 8, 8),
7187 ctx->i32_0, "");
7188
7189 for (i = 4; i > 0; --i) {
7190 input_vgprs[i + 1] =
7191 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
7192 input_vgprs[i + 1],
7193 input_vgprs[i - 1], "");
7194 }
7195 }
7196 }
7197
7198 ctx->abi.vertex_id = input_vgprs[first_vs_vgpr];
7199 ctx->abi.instance_id = input_vgprs[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)];
7200
7201 /* Copy inputs to outputs. This should be no-op, as the registers match,
7202 * but it will prevent the compiler from overwriting them unintentionally.
7203 */
7204 ret = ctx->return_value;
7205 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7206 LLVMValueRef p = LLVMGetParam(func, i);
7207 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7208 }
7209 for (i = 0; i < num_input_vgprs; i++) {
7210 LLVMValueRef p = input_vgprs[i];
7211 p = ac_to_float(&ctx->ac, p);
7212 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
7213 key->vs_prolog.num_input_sgprs + i, "");
7214 }
7215
7216 /* Compute vertex load indices from instance divisors. */
7217 LLVMValueRef instance_divisor_constbuf = NULL;
7218
7219 if (key->vs_prolog.states.instance_divisor_is_fetched) {
7220 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7221 LLVMValueRef buf_index =
7222 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
7223 instance_divisor_constbuf =
7224 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
7225 }
7226
7227 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7228 bool divisor_is_one =
7229 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
7230 bool divisor_is_fetched =
7231 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
7232 LLVMValueRef index;
7233
7234 if (divisor_is_one || divisor_is_fetched) {
7235 LLVMValueRef divisor = ctx->i32_1;
7236
7237 if (divisor_is_fetched) {
7238 divisor = buffer_load_const(ctx, instance_divisor_constbuf,
7239 LLVMConstInt(ctx->i32, i * 4, 0));
7240 divisor = ac_to_integer(&ctx->ac, divisor);
7241 }
7242
7243 /* InstanceID / Divisor + StartInstance */
7244 index = get_instance_index_for_fetch(ctx,
7245 user_sgpr_base +
7246 SI_SGPR_START_INSTANCE,
7247 divisor);
7248 } else {
7249 /* VertexID + BaseVertex */
7250 index = LLVMBuildAdd(ctx->ac.builder,
7251 ctx->abi.vertex_id,
7252 LLVMGetParam(func, user_sgpr_base +
7253 SI_SGPR_BASE_VERTEX), "");
7254 }
7255
7256 index = ac_to_float(&ctx->ac, index);
7257 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7258 fninfo.num_params + i, "");
7259 }
7260
7261 si_llvm_build_ret(ctx, ret);
7262 }
7263
7264 static bool si_get_vs_prolog(struct si_screen *sscreen,
7265 LLVMTargetMachineRef tm,
7266 struct si_shader *shader,
7267 struct pipe_debug_callback *debug,
7268 struct si_shader *main_part,
7269 const struct si_vs_prolog_bits *key)
7270 {
7271 struct si_shader_selector *vs = main_part->selector;
7272
7273 if (!si_vs_needs_prolog(vs, key))
7274 return true;
7275
7276 /* Get the prolog. */
7277 union si_shader_part_key prolog_key;
7278 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7279 key, shader, &prolog_key);
7280
7281 shader->prolog =
7282 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7283 PIPE_SHADER_VERTEX, true, &prolog_key, tm,
7284 debug, si_build_vs_prolog_function,
7285 "Vertex Shader Prolog");
7286 return shader->prolog != NULL;
7287 }
7288
7289 /**
7290 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7291 */
7292 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7293 LLVMTargetMachineRef tm,
7294 struct si_shader *shader,
7295 struct pipe_debug_callback *debug)
7296 {
7297 return si_get_vs_prolog(sscreen, tm, shader, debug, shader,
7298 &shader->key.part.vs.prolog);
7299 }
7300
7301 /**
7302 * Compile the TCS epilog function. This writes tesselation factors to memory
7303 * based on the output primitive type of the tesselator (determined by TES).
7304 */
7305 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7306 union si_shader_part_key *key)
7307 {
7308 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7309 struct si_function_info fninfo;
7310 LLVMValueRef func;
7311
7312 si_init_function_info(&fninfo);
7313
7314 if (ctx->screen->info.chip_class >= GFX9) {
7315 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7316 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7317 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7318 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7319 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7320 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7321 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7322 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7323 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7324 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7325 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7326 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7327 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7328 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7329 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7330 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7331 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7332 if (!HAVE_32BIT_POINTERS)
7333 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7334 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7335 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7336 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7337 } else {
7338 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7339 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7340 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7341 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7342 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7343 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7344 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7345 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7346 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7347 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7348 }
7349
7350 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7351 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7352 unsigned tess_factors_idx =
7353 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7354 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7355 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7356
7357 for (unsigned i = 0; i < 6; i++)
7358 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7359
7360 /* Create the function. */
7361 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7362 ctx->screen->info.chip_class >= CIK ? 128 : 64);
7363 ac_declare_lds_as_pointer(&ctx->ac);
7364 func = ctx->main_fn;
7365
7366 LLVMValueRef invoc0_tess_factors[6];
7367 for (unsigned i = 0; i < 6; i++)
7368 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7369
7370 si_write_tess_factors(bld_base,
7371 LLVMGetParam(func, tess_factors_idx),
7372 LLVMGetParam(func, tess_factors_idx + 1),
7373 LLVMGetParam(func, tess_factors_idx + 2),
7374 invoc0_tess_factors, invoc0_tess_factors + 4);
7375
7376 LLVMBuildRetVoid(ctx->ac.builder);
7377 }
7378
7379 /**
7380 * Select and compile (or reuse) TCS parts (epilog).
7381 */
7382 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7383 LLVMTargetMachineRef tm,
7384 struct si_shader *shader,
7385 struct pipe_debug_callback *debug)
7386 {
7387 if (sscreen->info.chip_class >= GFX9) {
7388 struct si_shader *ls_main_part =
7389 shader->key.part.tcs.ls->main_shader_part_ls;
7390
7391 if (!si_get_vs_prolog(sscreen, tm, shader, debug, ls_main_part,
7392 &shader->key.part.tcs.ls_prolog))
7393 return false;
7394
7395 shader->previous_stage = ls_main_part;
7396 }
7397
7398 /* Get the epilog. */
7399 union si_shader_part_key epilog_key;
7400 memset(&epilog_key, 0, sizeof(epilog_key));
7401 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7402
7403 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7404 PIPE_SHADER_TESS_CTRL, false,
7405 &epilog_key, tm, debug,
7406 si_build_tcs_epilog_function,
7407 "Tessellation Control Shader Epilog");
7408 return shader->epilog != NULL;
7409 }
7410
7411 /**
7412 * Select and compile (or reuse) GS parts (prolog).
7413 */
7414 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7415 LLVMTargetMachineRef tm,
7416 struct si_shader *shader,
7417 struct pipe_debug_callback *debug)
7418 {
7419 if (sscreen->info.chip_class >= GFX9) {
7420 struct si_shader *es_main_part =
7421 shader->key.part.gs.es->main_shader_part_es;
7422
7423 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7424 !si_get_vs_prolog(sscreen, tm, shader, debug, es_main_part,
7425 &shader->key.part.gs.vs_prolog))
7426 return false;
7427
7428 shader->previous_stage = es_main_part;
7429 }
7430
7431 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7432 return true;
7433
7434 union si_shader_part_key prolog_key;
7435 memset(&prolog_key, 0, sizeof(prolog_key));
7436 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7437
7438 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7439 PIPE_SHADER_GEOMETRY, true,
7440 &prolog_key, tm, debug,
7441 si_build_gs_prolog_function,
7442 "Geometry Shader Prolog");
7443 return shader->prolog2 != NULL;
7444 }
7445
7446 /**
7447 * Build the pixel shader prolog function. This handles:
7448 * - two-side color selection and interpolation
7449 * - overriding interpolation parameters for the API PS
7450 * - polygon stippling
7451 *
7452 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7453 * overriden by other states. (e.g. per-sample interpolation)
7454 * Interpolated colors are stored after the preloaded VGPRs.
7455 */
7456 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7457 union si_shader_part_key *key)
7458 {
7459 struct si_function_info fninfo;
7460 LLVMValueRef ret, func;
7461 int num_returns, i, num_color_channels;
7462
7463 assert(si_need_ps_prolog(key));
7464
7465 si_init_function_info(&fninfo);
7466
7467 /* Declare inputs. */
7468 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7469 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7470
7471 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7472 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7473
7474 /* Declare outputs (same as inputs + add colors if needed) */
7475 num_returns = fninfo.num_params;
7476 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7477 for (i = 0; i < num_color_channels; i++)
7478 fninfo.types[num_returns++] = ctx->f32;
7479
7480 /* Create the function. */
7481 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7482 &fninfo, 0);
7483 func = ctx->main_fn;
7484
7485 /* Copy inputs to outputs. This should be no-op, as the registers match,
7486 * but it will prevent the compiler from overwriting them unintentionally.
7487 */
7488 ret = ctx->return_value;
7489 for (i = 0; i < fninfo.num_params; i++) {
7490 LLVMValueRef p = LLVMGetParam(func, i);
7491 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7492 }
7493
7494 /* Polygon stippling. */
7495 if (key->ps_prolog.states.poly_stipple) {
7496 /* POS_FIXED_PT is always last. */
7497 unsigned pos = key->ps_prolog.num_input_sgprs +
7498 key->ps_prolog.num_input_vgprs - 1;
7499 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7500
7501 si_llvm_emit_polygon_stipple(ctx, list, pos);
7502 }
7503
7504 if (key->ps_prolog.states.bc_optimize_for_persp ||
7505 key->ps_prolog.states.bc_optimize_for_linear) {
7506 unsigned i, base = key->ps_prolog.num_input_sgprs;
7507 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7508
7509 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7510 * The hw doesn't compute CENTROID if the whole wave only
7511 * contains fully-covered quads.
7512 *
7513 * PRIM_MASK is after user SGPRs.
7514 */
7515 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7516 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7517 LLVMConstInt(ctx->i32, 31, 0), "");
7518 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7519 ctx->i1, "");
7520
7521 if (key->ps_prolog.states.bc_optimize_for_persp) {
7522 /* Read PERSP_CENTER. */
7523 for (i = 0; i < 2; i++)
7524 center[i] = LLVMGetParam(func, base + 2 + i);
7525 /* Read PERSP_CENTROID. */
7526 for (i = 0; i < 2; i++)
7527 centroid[i] = LLVMGetParam(func, base + 4 + i);
7528 /* Select PERSP_CENTROID. */
7529 for (i = 0; i < 2; i++) {
7530 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7531 center[i], centroid[i], "");
7532 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7533 tmp, base + 4 + i, "");
7534 }
7535 }
7536 if (key->ps_prolog.states.bc_optimize_for_linear) {
7537 /* Read LINEAR_CENTER. */
7538 for (i = 0; i < 2; i++)
7539 center[i] = LLVMGetParam(func, base + 8 + i);
7540 /* Read LINEAR_CENTROID. */
7541 for (i = 0; i < 2; i++)
7542 centroid[i] = LLVMGetParam(func, base + 10 + i);
7543 /* Select LINEAR_CENTROID. */
7544 for (i = 0; i < 2; i++) {
7545 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7546 center[i], centroid[i], "");
7547 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7548 tmp, base + 10 + i, "");
7549 }
7550 }
7551 }
7552
7553 /* Force per-sample interpolation. */
7554 if (key->ps_prolog.states.force_persp_sample_interp) {
7555 unsigned i, base = key->ps_prolog.num_input_sgprs;
7556 LLVMValueRef persp_sample[2];
7557
7558 /* Read PERSP_SAMPLE. */
7559 for (i = 0; i < 2; i++)
7560 persp_sample[i] = LLVMGetParam(func, base + i);
7561 /* Overwrite PERSP_CENTER. */
7562 for (i = 0; i < 2; i++)
7563 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7564 persp_sample[i], base + 2 + i, "");
7565 /* Overwrite PERSP_CENTROID. */
7566 for (i = 0; i < 2; i++)
7567 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7568 persp_sample[i], base + 4 + i, "");
7569 }
7570 if (key->ps_prolog.states.force_linear_sample_interp) {
7571 unsigned i, base = key->ps_prolog.num_input_sgprs;
7572 LLVMValueRef linear_sample[2];
7573
7574 /* Read LINEAR_SAMPLE. */
7575 for (i = 0; i < 2; i++)
7576 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7577 /* Overwrite LINEAR_CENTER. */
7578 for (i = 0; i < 2; i++)
7579 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7580 linear_sample[i], base + 8 + i, "");
7581 /* Overwrite LINEAR_CENTROID. */
7582 for (i = 0; i < 2; i++)
7583 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7584 linear_sample[i], base + 10 + i, "");
7585 }
7586
7587 /* Force center interpolation. */
7588 if (key->ps_prolog.states.force_persp_center_interp) {
7589 unsigned i, base = key->ps_prolog.num_input_sgprs;
7590 LLVMValueRef persp_center[2];
7591
7592 /* Read PERSP_CENTER. */
7593 for (i = 0; i < 2; i++)
7594 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7595 /* Overwrite PERSP_SAMPLE. */
7596 for (i = 0; i < 2; i++)
7597 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7598 persp_center[i], base + i, "");
7599 /* Overwrite PERSP_CENTROID. */
7600 for (i = 0; i < 2; i++)
7601 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7602 persp_center[i], base + 4 + i, "");
7603 }
7604 if (key->ps_prolog.states.force_linear_center_interp) {
7605 unsigned i, base = key->ps_prolog.num_input_sgprs;
7606 LLVMValueRef linear_center[2];
7607
7608 /* Read LINEAR_CENTER. */
7609 for (i = 0; i < 2; i++)
7610 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7611 /* Overwrite LINEAR_SAMPLE. */
7612 for (i = 0; i < 2; i++)
7613 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7614 linear_center[i], base + 6 + i, "");
7615 /* Overwrite LINEAR_CENTROID. */
7616 for (i = 0; i < 2; i++)
7617 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7618 linear_center[i], base + 10 + i, "");
7619 }
7620
7621 /* Interpolate colors. */
7622 unsigned color_out_idx = 0;
7623 for (i = 0; i < 2; i++) {
7624 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7625 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7626 key->ps_prolog.face_vgpr_index;
7627 LLVMValueRef interp[2], color[4];
7628 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7629
7630 if (!writemask)
7631 continue;
7632
7633 /* If the interpolation qualifier is not CONSTANT (-1). */
7634 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7635 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7636 key->ps_prolog.color_interp_vgpr_index[i];
7637
7638 /* Get the (i,j) updated by bc_optimize handling. */
7639 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7640 interp_vgpr, "");
7641 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7642 interp_vgpr + 1, "");
7643 interp_ij = lp_build_gather_values(&ctx->gallivm, interp, 2);
7644 }
7645
7646 /* Use the absolute location of the input. */
7647 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7648
7649 if (key->ps_prolog.states.color_two_side) {
7650 face = LLVMGetParam(func, face_vgpr);
7651 face = ac_to_integer(&ctx->ac, face);
7652 }
7653
7654 interp_fs_input(ctx,
7655 key->ps_prolog.color_attr_index[i],
7656 TGSI_SEMANTIC_COLOR, i,
7657 key->ps_prolog.num_interp_inputs,
7658 key->ps_prolog.colors_read, interp_ij,
7659 prim_mask, face, color);
7660
7661 while (writemask) {
7662 unsigned chan = u_bit_scan(&writemask);
7663 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7664 fninfo.num_params + color_out_idx++, "");
7665 }
7666 }
7667
7668 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7669 * says:
7670 *
7671 * "When per-sample shading is active due to the use of a fragment
7672 * input qualified by sample or due to the use of the gl_SampleID
7673 * or gl_SamplePosition variables, only the bit for the current
7674 * sample is set in gl_SampleMaskIn. When state specifies multiple
7675 * fragment shader invocations for a given fragment, the sample
7676 * mask for any single fragment shader invocation may specify a
7677 * subset of the covered samples for the fragment. In this case,
7678 * the bit corresponding to each covered sample will be set in
7679 * exactly one fragment shader invocation."
7680 *
7681 * The samplemask loaded by hardware is always the coverage of the
7682 * entire pixel/fragment, so mask bits out based on the sample ID.
7683 */
7684 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7685 /* The bit pattern matches that used by fixed function fragment
7686 * processing. */
7687 static const uint16_t ps_iter_masks[] = {
7688 0xffff, /* not used */
7689 0x5555,
7690 0x1111,
7691 0x0101,
7692 0x0001,
7693 };
7694 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7695
7696 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7697 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7698 key->ps_prolog.ancillary_vgpr_index;
7699 LLVMValueRef sampleid = unpack_param(ctx, ancillary_vgpr, 8, 4);
7700 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7701
7702 samplemask = ac_to_integer(&ctx->ac, samplemask);
7703 samplemask = LLVMBuildAnd(
7704 ctx->ac.builder,
7705 samplemask,
7706 LLVMBuildShl(ctx->ac.builder,
7707 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7708 sampleid, ""),
7709 "");
7710 samplemask = ac_to_float(&ctx->ac, samplemask);
7711
7712 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7713 ancillary_vgpr + 1, "");
7714 }
7715
7716 /* Tell LLVM to insert WQM instruction sequence when needed. */
7717 if (key->ps_prolog.wqm) {
7718 LLVMAddTargetDependentFunctionAttr(func,
7719 "amdgpu-ps-wqm-outputs", "");
7720 }
7721
7722 si_llvm_build_ret(ctx, ret);
7723 }
7724
7725 /**
7726 * Build the pixel shader epilog function. This handles everything that must be
7727 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7728 */
7729 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7730 union si_shader_part_key *key)
7731 {
7732 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7733 struct si_function_info fninfo;
7734 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7735 int i;
7736 struct si_ps_exports exp = {};
7737
7738 si_init_function_info(&fninfo);
7739
7740 /* Declare input SGPRs. */
7741 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7742 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7743 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7744 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7745 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7746
7747 /* Declare input VGPRs. */
7748 unsigned required_num_params =
7749 fninfo.num_sgpr_params +
7750 util_bitcount(key->ps_epilog.colors_written) * 4 +
7751 key->ps_epilog.writes_z +
7752 key->ps_epilog.writes_stencil +
7753 key->ps_epilog.writes_samplemask;
7754
7755 required_num_params = MAX2(required_num_params,
7756 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7757
7758 while (fninfo.num_params < required_num_params)
7759 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7760
7761 /* Create the function. */
7762 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7763 /* Disable elimination of unused inputs. */
7764 si_llvm_add_attribute(ctx->main_fn,
7765 "InitialPSInputAddr", 0xffffff);
7766
7767 /* Process colors. */
7768 unsigned vgpr = fninfo.num_sgpr_params;
7769 unsigned colors_written = key->ps_epilog.colors_written;
7770 int last_color_export = -1;
7771
7772 /* Find the last color export. */
7773 if (!key->ps_epilog.writes_z &&
7774 !key->ps_epilog.writes_stencil &&
7775 !key->ps_epilog.writes_samplemask) {
7776 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7777
7778 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7779 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7780 /* Just set this if any of the colorbuffers are enabled. */
7781 if (spi_format &
7782 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7783 last_color_export = 0;
7784 } else {
7785 for (i = 0; i < 8; i++)
7786 if (colors_written & (1 << i) &&
7787 (spi_format >> (i * 4)) & 0xf)
7788 last_color_export = i;
7789 }
7790 }
7791
7792 while (colors_written) {
7793 LLVMValueRef color[4];
7794 int mrt = u_bit_scan(&colors_written);
7795
7796 for (i = 0; i < 4; i++)
7797 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7798
7799 si_export_mrt_color(bld_base, color, mrt,
7800 fninfo.num_params - 1,
7801 mrt == last_color_export, &exp);
7802 }
7803
7804 /* Process depth, stencil, samplemask. */
7805 if (key->ps_epilog.writes_z)
7806 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7807 if (key->ps_epilog.writes_stencil)
7808 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7809 if (key->ps_epilog.writes_samplemask)
7810 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7811
7812 if (depth || stencil || samplemask)
7813 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7814 else if (last_color_export == -1)
7815 ac_build_export_null(&ctx->ac);
7816
7817 if (exp.num)
7818 si_emit_ps_exports(ctx, &exp);
7819
7820 /* Compile. */
7821 LLVMBuildRetVoid(ctx->ac.builder);
7822 }
7823
7824 /**
7825 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7826 */
7827 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7828 LLVMTargetMachineRef tm,
7829 struct si_shader *shader,
7830 struct pipe_debug_callback *debug)
7831 {
7832 union si_shader_part_key prolog_key;
7833 union si_shader_part_key epilog_key;
7834
7835 /* Get the prolog. */
7836 si_get_ps_prolog_key(shader, &prolog_key, true);
7837
7838 /* The prolog is a no-op if these aren't set. */
7839 if (si_need_ps_prolog(&prolog_key)) {
7840 shader->prolog =
7841 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7842 PIPE_SHADER_FRAGMENT, true,
7843 &prolog_key, tm, debug,
7844 si_build_ps_prolog_function,
7845 "Fragment Shader Prolog");
7846 if (!shader->prolog)
7847 return false;
7848 }
7849
7850 /* Get the epilog. */
7851 si_get_ps_epilog_key(shader, &epilog_key);
7852
7853 shader->epilog =
7854 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7855 PIPE_SHADER_FRAGMENT, false,
7856 &epilog_key, tm, debug,
7857 si_build_ps_epilog_function,
7858 "Fragment Shader Epilog");
7859 if (!shader->epilog)
7860 return false;
7861
7862 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7863 if (shader->key.part.ps.prolog.poly_stipple) {
7864 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7865 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7866 }
7867
7868 /* Set up the enable bits for per-sample shading if needed. */
7869 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7870 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7871 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7872 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7873 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7874 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7875 }
7876 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7877 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7878 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7879 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7880 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7881 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7882 }
7883 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7884 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7885 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7886 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7887 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7888 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7889 }
7890 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7891 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7892 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7893 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7894 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7895 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7896 }
7897
7898 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7899 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7900 !(shader->config.spi_ps_input_ena & 0xf)) {
7901 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7902 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7903 }
7904
7905 /* At least one pair of interpolation weights must be enabled. */
7906 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7907 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7908 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7909 }
7910
7911 /* Samplemask fixup requires the sample ID. */
7912 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7913 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7914 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7915 }
7916
7917 /* The sample mask input is always enabled, because the API shader always
7918 * passes it through to the epilog. Disable it here if it's unused.
7919 */
7920 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7921 !shader->selector->info.reads_samplemask)
7922 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7923
7924 return true;
7925 }
7926
7927 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7928 unsigned *lds_size)
7929 {
7930 /* SPI barrier management bug:
7931 * Make sure we have at least 4k of LDS in use to avoid the bug.
7932 * It applies to workgroup sizes of more than one wavefront.
7933 */
7934 if (sscreen->info.family == CHIP_BONAIRE ||
7935 sscreen->info.family == CHIP_KABINI ||
7936 sscreen->info.family == CHIP_MULLINS)
7937 *lds_size = MAX2(*lds_size, 8);
7938 }
7939
7940 static void si_fix_resource_usage(struct si_screen *sscreen,
7941 struct si_shader *shader)
7942 {
7943 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7944
7945 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7946
7947 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7948 si_get_max_workgroup_size(shader) > 64) {
7949 si_multiwave_lds_size_workaround(sscreen,
7950 &shader->config.lds_size);
7951 }
7952 }
7953
7954 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7955 struct si_shader *shader,
7956 struct pipe_debug_callback *debug)
7957 {
7958 struct si_shader_selector *sel = shader->selector;
7959 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7960 int r;
7961
7962 /* LS, ES, VS are compiled on demand if the main part hasn't been
7963 * compiled for that stage.
7964 *
7965 * Vertex shaders are compiled on demand when a vertex fetch
7966 * workaround must be applied.
7967 */
7968 if (shader->is_monolithic) {
7969 /* Monolithic shader (compiled as a whole, has many variants,
7970 * may take a long time to compile).
7971 */
7972 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7973 if (r)
7974 return r;
7975 } else {
7976 /* The shader consists of several parts:
7977 *
7978 * - the middle part is the user shader, it has 1 variant only
7979 * and it was compiled during the creation of the shader
7980 * selector
7981 * - the prolog part is inserted at the beginning
7982 * - the epilog part is inserted at the end
7983 *
7984 * The prolog and epilog have many (but simple) variants.
7985 *
7986 * Starting with gfx9, geometry and tessellation control
7987 * shaders also contain the prolog and user shader parts of
7988 * the previous shader stage.
7989 */
7990
7991 if (!mainp)
7992 return -1;
7993
7994 /* Copy the compiled TGSI shader data over. */
7995 shader->is_binary_shared = true;
7996 shader->binary = mainp->binary;
7997 shader->config = mainp->config;
7998 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7999 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8000 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8001 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
8002 memcpy(shader->info.vs_output_param_offset,
8003 mainp->info.vs_output_param_offset,
8004 sizeof(mainp->info.vs_output_param_offset));
8005 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8006 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8007 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8008
8009 /* Select prologs and/or epilogs. */
8010 switch (sel->type) {
8011 case PIPE_SHADER_VERTEX:
8012 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
8013 return -1;
8014 break;
8015 case PIPE_SHADER_TESS_CTRL:
8016 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
8017 return -1;
8018 break;
8019 case PIPE_SHADER_TESS_EVAL:
8020 break;
8021 case PIPE_SHADER_GEOMETRY:
8022 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
8023 return -1;
8024 break;
8025 case PIPE_SHADER_FRAGMENT:
8026 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8027 return -1;
8028
8029 /* Make sure we have at least as many VGPRs as there
8030 * are allocated inputs.
8031 */
8032 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8033 shader->info.num_input_vgprs);
8034 break;
8035 }
8036
8037 /* Update SGPR and VGPR counts. */
8038 if (shader->prolog) {
8039 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8040 shader->prolog->config.num_sgprs);
8041 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8042 shader->prolog->config.num_vgprs);
8043 }
8044 if (shader->previous_stage) {
8045 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8046 shader->previous_stage->config.num_sgprs);
8047 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8048 shader->previous_stage->config.num_vgprs);
8049 shader->config.spilled_sgprs =
8050 MAX2(shader->config.spilled_sgprs,
8051 shader->previous_stage->config.spilled_sgprs);
8052 shader->config.spilled_vgprs =
8053 MAX2(shader->config.spilled_vgprs,
8054 shader->previous_stage->config.spilled_vgprs);
8055 shader->config.private_mem_vgprs =
8056 MAX2(shader->config.private_mem_vgprs,
8057 shader->previous_stage->config.private_mem_vgprs);
8058 shader->config.scratch_bytes_per_wave =
8059 MAX2(shader->config.scratch_bytes_per_wave,
8060 shader->previous_stage->config.scratch_bytes_per_wave);
8061 shader->info.uses_instanceid |=
8062 shader->previous_stage->info.uses_instanceid;
8063 }
8064 if (shader->prolog2) {
8065 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8066 shader->prolog2->config.num_sgprs);
8067 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8068 shader->prolog2->config.num_vgprs);
8069 }
8070 if (shader->epilog) {
8071 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8072 shader->epilog->config.num_sgprs);
8073 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8074 shader->epilog->config.num_vgprs);
8075 }
8076 si_calculate_max_simd_waves(shader);
8077 }
8078
8079 si_fix_resource_usage(sscreen, shader);
8080 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8081 stderr, true);
8082
8083 /* Upload. */
8084 r = si_shader_binary_upload(sscreen, shader);
8085 if (r) {
8086 fprintf(stderr, "LLVM failed to upload shader\n");
8087 return r;
8088 }
8089
8090 return 0;
8091 }
8092
8093 void si_shader_destroy(struct si_shader *shader)
8094 {
8095 if (shader->scratch_bo)
8096 r600_resource_reference(&shader->scratch_bo, NULL);
8097
8098 r600_resource_reference(&shader->bo, NULL);
8099
8100 if (!shader->is_binary_shared)
8101 ac_shader_binary_clean(&shader->binary);
8102
8103 free(shader->shader_log);
8104 }