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radeonsi: extract writing of a single streamout output
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "radeon/radeon_elf_util.h"
37 #include "util/u_memory.h"
38 #include "util/u_string.h"
39 #include "tgsi/tgsi_build.h"
40 #include "tgsi/tgsi_util.h"
41 #include "tgsi/tgsi_dump.h"
42
43 #include "ac_llvm_util.h"
44 #include "si_shader_internal.h"
45 #include "si_pipe.h"
46 #include "sid.h"
47
48
49 static const char *scratch_rsrc_dword0_symbol =
50 "SCRATCH_RSRC_DWORD0";
51
52 static const char *scratch_rsrc_dword1_symbol =
53 "SCRATCH_RSRC_DWORD1";
54
55 struct si_shader_output_values
56 {
57 LLVMValueRef values[4];
58 unsigned semantic_name;
59 unsigned semantic_index;
60 ubyte vertex_stream[4];
61 };
62
63 static void si_init_shader_ctx(struct si_shader_context *ctx,
64 struct si_screen *sscreen,
65 struct si_shader *shader,
66 LLVMTargetMachineRef tm);
67
68 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
69 struct lp_build_tgsi_context *bld_base,
70 struct lp_build_emit_data *emit_data);
71
72 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
73 FILE *f);
74
75 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
76 union si_shader_part_key *key);
77 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
78 union si_shader_part_key *key);
79 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
80 union si_shader_part_key *key);
81 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
82 union si_shader_part_key *key);
83 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
84 union si_shader_part_key *key);
85
86 /* Ideally pass the sample mask input to the PS epilog as v13, which
87 * is its usual location, so that the shader doesn't have to add v_mov.
88 */
89 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
90
91 /* The VS location of the PrimitiveID input is the same in the epilog,
92 * so that the main shader part doesn't have to move it.
93 */
94 #define VS_EPILOG_PRIMID_LOC 2
95
96 enum {
97 CONST_ADDR_SPACE = 2,
98 LOCAL_ADDR_SPACE = 3,
99 };
100
101 #define SENDMSG_GS 2
102 #define SENDMSG_GS_DONE 3
103
104 #define SENDMSG_GS_OP_NOP (0 << 4)
105 #define SENDMSG_GS_OP_CUT (1 << 4)
106 #define SENDMSG_GS_OP_EMIT (2 << 4)
107 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
108
109 /**
110 * Returns a unique index for a semantic name and index. The index must be
111 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
112 * calculated.
113 */
114 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
115 {
116 switch (semantic_name) {
117 case TGSI_SEMANTIC_POSITION:
118 return 0;
119 case TGSI_SEMANTIC_PSIZE:
120 return 1;
121 case TGSI_SEMANTIC_CLIPDIST:
122 assert(index <= 1);
123 return 2 + index;
124 case TGSI_SEMANTIC_GENERIC:
125 if (index <= 63-4)
126 return 4 + index;
127
128 assert(!"invalid generic index");
129 return 0;
130
131 /* patch indices are completely separate and thus start from 0 */
132 case TGSI_SEMANTIC_TESSOUTER:
133 return 0;
134 case TGSI_SEMANTIC_TESSINNER:
135 return 1;
136 case TGSI_SEMANTIC_PATCH:
137 return 2 + index;
138
139 default:
140 assert(!"invalid semantic name");
141 return 0;
142 }
143 }
144
145 unsigned si_shader_io_get_unique_index2(unsigned name, unsigned index)
146 {
147 switch (name) {
148 case TGSI_SEMANTIC_FOG:
149 return 0;
150 case TGSI_SEMANTIC_LAYER:
151 return 1;
152 case TGSI_SEMANTIC_VIEWPORT_INDEX:
153 return 2;
154 case TGSI_SEMANTIC_PRIMID:
155 return 3;
156 case TGSI_SEMANTIC_COLOR: /* these alias */
157 case TGSI_SEMANTIC_BCOLOR:
158 return 4 + index;
159 case TGSI_SEMANTIC_TEXCOORD:
160 return 6 + index;
161 default:
162 assert(!"invalid semantic name");
163 return 0;
164 }
165 }
166
167 /**
168 * Get the value of a shader input parameter and extract a bitfield.
169 */
170 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
171 unsigned param, unsigned rshift,
172 unsigned bitwidth)
173 {
174 struct gallivm_state *gallivm = &ctx->gallivm;
175 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
176 param);
177
178 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
179 value = bitcast(&ctx->soa.bld_base,
180 TGSI_TYPE_UNSIGNED, value);
181
182 if (rshift)
183 value = LLVMBuildLShr(gallivm->builder, value,
184 lp_build_const_int32(gallivm, rshift), "");
185
186 if (rshift + bitwidth < 32) {
187 unsigned mask = (1 << bitwidth) - 1;
188 value = LLVMBuildAnd(gallivm->builder, value,
189 lp_build_const_int32(gallivm, mask), "");
190 }
191
192 return value;
193 }
194
195 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
196 {
197 switch (ctx->type) {
198 case PIPE_SHADER_TESS_CTRL:
199 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
200
201 case PIPE_SHADER_TESS_EVAL:
202 return LLVMGetParam(ctx->main_fn,
203 ctx->param_tes_rel_patch_id);
204
205 default:
206 assert(0);
207 return NULL;
208 }
209 }
210
211 /* Tessellation shaders pass outputs to the next shader using LDS.
212 *
213 * LS outputs = TCS inputs
214 * TCS outputs = TES inputs
215 *
216 * The LDS layout is:
217 * - TCS inputs for patch 0
218 * - TCS inputs for patch 1
219 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
220 * - ...
221 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
222 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
223 * - TCS outputs for patch 1
224 * - Per-patch TCS outputs for patch 1
225 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
226 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
227 * - ...
228 *
229 * All three shaders VS(LS), TCS, TES share the same LDS space.
230 */
231
232 static LLVMValueRef
233 get_tcs_in_patch_stride(struct si_shader_context *ctx)
234 {
235 if (ctx->type == PIPE_SHADER_VERTEX)
236 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
237 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
238 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
239 else {
240 assert(0);
241 return NULL;
242 }
243 }
244
245 static LLVMValueRef
246 get_tcs_out_patch_stride(struct si_shader_context *ctx)
247 {
248 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
249 }
250
251 static LLVMValueRef
252 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
253 {
254 return lp_build_mul_imm(&ctx->soa.bld_base.uint_bld,
255 unpack_param(ctx,
256 SI_PARAM_TCS_OUT_OFFSETS,
257 0, 16),
258 4);
259 }
260
261 static LLVMValueRef
262 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
263 {
264 return lp_build_mul_imm(&ctx->soa.bld_base.uint_bld,
265 unpack_param(ctx,
266 SI_PARAM_TCS_OUT_OFFSETS,
267 16, 16),
268 4);
269 }
270
271 static LLVMValueRef
272 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
273 {
274 struct gallivm_state *gallivm = &ctx->gallivm;
275 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
276 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
277
278 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
279 }
280
281 static LLVMValueRef
282 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
283 {
284 struct gallivm_state *gallivm = &ctx->gallivm;
285 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
286 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
287 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
288
289 return LLVMBuildAdd(gallivm->builder, patch0_offset,
290 LLVMBuildMul(gallivm->builder, patch_stride,
291 rel_patch_id, ""),
292 "");
293 }
294
295 static LLVMValueRef
296 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
297 {
298 struct gallivm_state *gallivm = &ctx->gallivm;
299 LLVMValueRef patch0_patch_data_offset =
300 get_tcs_out_patch0_patch_data_offset(ctx);
301 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
302 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
303
304 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
305 LLVMBuildMul(gallivm->builder, patch_stride,
306 rel_patch_id, ""),
307 "");
308 }
309
310 static LLVMValueRef build_gep0(struct si_shader_context *ctx,
311 LLVMValueRef base_ptr, LLVMValueRef index)
312 {
313 LLVMValueRef indices[2] = {
314 LLVMConstInt(ctx->i32, 0, 0),
315 index,
316 };
317 return LLVMBuildGEP(ctx->gallivm.builder, base_ptr,
318 indices, 2, "");
319 }
320
321 static void build_indexed_store(struct si_shader_context *ctx,
322 LLVMValueRef base_ptr, LLVMValueRef index,
323 LLVMValueRef value)
324 {
325 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
326 struct gallivm_state *gallivm = bld_base->base.gallivm;
327
328 LLVMBuildStore(gallivm->builder, value,
329 build_gep0(ctx, base_ptr, index));
330 }
331
332 /**
333 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
334 * It's equivalent to doing a load from &base_ptr[index].
335 *
336 * \param base_ptr Where the array starts.
337 * \param index The element index into the array.
338 * \param uniform Whether the base_ptr and index can be assumed to be
339 * dynamically uniform
340 */
341 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
342 LLVMValueRef base_ptr, LLVMValueRef index,
343 bool uniform)
344 {
345 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
346 struct gallivm_state *gallivm = bld_base->base.gallivm;
347 LLVMValueRef pointer;
348
349 pointer = build_gep0(ctx, base_ptr, index);
350 if (uniform)
351 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
352 return LLVMBuildLoad(gallivm->builder, pointer, "");
353 }
354
355 /**
356 * Do a load from &base_ptr[index], but also add a flag that it's loading
357 * a constant from a dynamically uniform index.
358 */
359 static LLVMValueRef build_indexed_load_const(
360 struct si_shader_context *ctx,
361 LLVMValueRef base_ptr, LLVMValueRef index)
362 {
363 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
364 LLVMSetMetadata(result, ctx->invariant_load_md_kind, ctx->empty_md);
365 return result;
366 }
367
368 static LLVMValueRef get_instance_index_for_fetch(
369 struct si_shader_context *radeon_bld,
370 unsigned param_start_instance, unsigned divisor)
371 {
372 struct si_shader_context *ctx =
373 si_shader_context(&radeon_bld->soa.bld_base);
374 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
375
376 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
377 ctx->param_instance_id);
378
379 /* The division must be done before START_INSTANCE is added. */
380 if (divisor > 1)
381 result = LLVMBuildUDiv(gallivm->builder, result,
382 lp_build_const_int32(gallivm, divisor), "");
383
384 return LLVMBuildAdd(gallivm->builder, result,
385 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
386 }
387
388 static void declare_input_vs(
389 struct si_shader_context *ctx,
390 unsigned input_index,
391 const struct tgsi_full_declaration *decl,
392 LLVMValueRef out[4])
393 {
394 struct lp_build_context *base = &ctx->soa.bld_base.base;
395 struct gallivm_state *gallivm = base->gallivm;
396
397 unsigned chan;
398 unsigned fix_fetch;
399
400 LLVMValueRef t_list_ptr;
401 LLVMValueRef t_offset;
402 LLVMValueRef t_list;
403 LLVMValueRef attribute_offset;
404 LLVMValueRef buffer_index;
405 LLVMValueRef args[3];
406 LLVMValueRef input;
407
408 /* Load the T list */
409 t_list_ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_VERTEX_BUFFERS);
410
411 t_offset = lp_build_const_int32(gallivm, input_index);
412
413 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
414
415 /* Build the attribute offset */
416 attribute_offset = lp_build_const_int32(gallivm, 0);
417
418 buffer_index = LLVMGetParam(ctx->main_fn,
419 ctx->param_vertex_index0 +
420 input_index);
421
422 args[0] = t_list;
423 args[1] = attribute_offset;
424 args[2] = buffer_index;
425 input = lp_build_intrinsic(gallivm->builder,
426 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
427 LP_FUNC_ATTR_READNONE);
428
429 /* Break up the vec4 into individual components */
430 for (chan = 0; chan < 4; chan++) {
431 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
432 out[chan] = LLVMBuildExtractElement(gallivm->builder,
433 input, llvm_chan, "");
434 }
435
436 fix_fetch = (ctx->shader->key.mono.vs.fix_fetch >> (2 * input_index)) & 3;
437 if (fix_fetch) {
438 /* The hardware returns an unsigned value; convert it to a
439 * signed one.
440 */
441 LLVMValueRef tmp = out[3];
442 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
443
444 /* First, recover the sign-extended signed integer value. */
445 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
446 tmp = LLVMBuildFPToUI(gallivm->builder, tmp, ctx->i32, "");
447 else
448 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->i32, "");
449
450 /* For the integer-like cases, do a natural sign extension.
451 *
452 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
453 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
454 * exponent.
455 */
456 tmp = LLVMBuildShl(gallivm->builder, tmp,
457 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
458 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
459 tmp = LLVMBuildAShr(gallivm->builder, tmp, c30, "");
460
461 /* Convert back to the right type. */
462 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
463 LLVMValueRef clamp;
464 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
465 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
466 clamp = LLVMBuildFCmp(gallivm->builder, LLVMRealULT, tmp, neg_one, "");
467 tmp = LLVMBuildSelect(gallivm->builder, clamp, neg_one, tmp, "");
468 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
469 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
470 }
471
472 out[3] = tmp;
473 }
474 }
475
476 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
477 unsigned swizzle)
478 {
479 struct si_shader_context *ctx = si_shader_context(bld_base);
480
481 if (swizzle > 0)
482 return bld_base->uint_bld.zero;
483
484 switch (ctx->type) {
485 case PIPE_SHADER_VERTEX:
486 return LLVMGetParam(ctx->main_fn,
487 ctx->param_vs_prim_id);
488 case PIPE_SHADER_TESS_CTRL:
489 return LLVMGetParam(ctx->main_fn,
490 SI_PARAM_PATCH_ID);
491 case PIPE_SHADER_TESS_EVAL:
492 return LLVMGetParam(ctx->main_fn,
493 ctx->param_tes_patch_id);
494 case PIPE_SHADER_GEOMETRY:
495 return LLVMGetParam(ctx->main_fn,
496 SI_PARAM_PRIMITIVE_ID);
497 default:
498 assert(0);
499 return bld_base->uint_bld.zero;
500 }
501 }
502
503 /**
504 * Return the value of tgsi_ind_register for indexing.
505 * This is the indirect index with the constant offset added to it.
506 */
507 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
508 const struct tgsi_ind_register *ind,
509 int rel_index)
510 {
511 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
512 LLVMValueRef result;
513
514 result = ctx->soa.addr[ind->Index][ind->Swizzle];
515 result = LLVMBuildLoad(gallivm->builder, result, "");
516 result = LLVMBuildAdd(gallivm->builder, result,
517 lp_build_const_int32(gallivm, rel_index), "");
518 return result;
519 }
520
521 /**
522 * Like get_indirect_index, but restricts the return value to a (possibly
523 * undefined) value inside [0..num).
524 */
525 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
526 const struct tgsi_ind_register *ind,
527 int rel_index, unsigned num)
528 {
529 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
530
531 /* LLVM 3.8: If indirect resource indexing is used:
532 * - SI & CIK hang
533 * - VI crashes
534 */
535 if (HAVE_LLVM <= 0x0308)
536 return LLVMGetUndef(ctx->i32);
537
538 return si_llvm_bound_index(ctx, result, num);
539 }
540
541
542 /**
543 * Calculate a dword address given an input or output register and a stride.
544 */
545 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
546 const struct tgsi_full_dst_register *dst,
547 const struct tgsi_full_src_register *src,
548 LLVMValueRef vertex_dw_stride,
549 LLVMValueRef base_addr)
550 {
551 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
552 struct tgsi_shader_info *info = &ctx->shader->selector->info;
553 ubyte *name, *index, *array_first;
554 int first, param;
555 struct tgsi_full_dst_register reg;
556
557 /* Set the register description. The address computation is the same
558 * for sources and destinations. */
559 if (src) {
560 reg.Register.File = src->Register.File;
561 reg.Register.Index = src->Register.Index;
562 reg.Register.Indirect = src->Register.Indirect;
563 reg.Register.Dimension = src->Register.Dimension;
564 reg.Indirect = src->Indirect;
565 reg.Dimension = src->Dimension;
566 reg.DimIndirect = src->DimIndirect;
567 } else
568 reg = *dst;
569
570 /* If the register is 2-dimensional (e.g. an array of vertices
571 * in a primitive), calculate the base address of the vertex. */
572 if (reg.Register.Dimension) {
573 LLVMValueRef index;
574
575 if (reg.Dimension.Indirect)
576 index = get_indirect_index(ctx, &reg.DimIndirect,
577 reg.Dimension.Index);
578 else
579 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
580
581 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
582 LLVMBuildMul(gallivm->builder, index,
583 vertex_dw_stride, ""), "");
584 }
585
586 /* Get information about the register. */
587 if (reg.Register.File == TGSI_FILE_INPUT) {
588 name = info->input_semantic_name;
589 index = info->input_semantic_index;
590 array_first = info->input_array_first;
591 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
592 name = info->output_semantic_name;
593 index = info->output_semantic_index;
594 array_first = info->output_array_first;
595 } else {
596 assert(0);
597 return NULL;
598 }
599
600 if (reg.Register.Indirect) {
601 /* Add the relative address of the element. */
602 LLVMValueRef ind_index;
603
604 if (reg.Indirect.ArrayID)
605 first = array_first[reg.Indirect.ArrayID];
606 else
607 first = reg.Register.Index;
608
609 ind_index = get_indirect_index(ctx, &reg.Indirect,
610 reg.Register.Index - first);
611
612 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
613 LLVMBuildMul(gallivm->builder, ind_index,
614 lp_build_const_int32(gallivm, 4), ""), "");
615
616 param = si_shader_io_get_unique_index(name[first], index[first]);
617 } else {
618 param = si_shader_io_get_unique_index(name[reg.Register.Index],
619 index[reg.Register.Index]);
620 }
621
622 /* Add the base address of the element. */
623 return LLVMBuildAdd(gallivm->builder, base_addr,
624 lp_build_const_int32(gallivm, param * 4), "");
625 }
626
627 /* The offchip buffer layout for TCS->TES is
628 *
629 * - attribute 0 of patch 0 vertex 0
630 * - attribute 0 of patch 0 vertex 1
631 * - attribute 0 of patch 0 vertex 2
632 * ...
633 * - attribute 0 of patch 1 vertex 0
634 * - attribute 0 of patch 1 vertex 1
635 * ...
636 * - attribute 1 of patch 0 vertex 0
637 * - attribute 1 of patch 0 vertex 1
638 * ...
639 * - per patch attribute 0 of patch 0
640 * - per patch attribute 0 of patch 1
641 * ...
642 *
643 * Note that every attribute has 4 components.
644 */
645 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
646 LLVMValueRef vertex_index,
647 LLVMValueRef param_index)
648 {
649 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
650 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
651 LLVMValueRef param_stride, constant16;
652
653 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
654 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
655 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
656 num_patches, "");
657
658 constant16 = lp_build_const_int32(gallivm, 16);
659 if (vertex_index) {
660 base_addr = LLVMBuildMul(gallivm->builder, get_rel_patch_id(ctx),
661 vertices_per_patch, "");
662
663 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
664 vertex_index, "");
665
666 param_stride = total_vertices;
667 } else {
668 base_addr = get_rel_patch_id(ctx);
669 param_stride = num_patches;
670 }
671
672 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
673 LLVMBuildMul(gallivm->builder, param_index,
674 param_stride, ""), "");
675
676 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
677
678 if (!vertex_index) {
679 LLVMValueRef patch_data_offset =
680 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
681
682 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
683 patch_data_offset, "");
684 }
685 return base_addr;
686 }
687
688 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
689 struct si_shader_context *ctx,
690 const struct tgsi_full_dst_register *dst,
691 const struct tgsi_full_src_register *src)
692 {
693 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
694 struct tgsi_shader_info *info = &ctx->shader->selector->info;
695 ubyte *name, *index, *array_first;
696 struct tgsi_full_src_register reg;
697 LLVMValueRef vertex_index = NULL;
698 LLVMValueRef param_index = NULL;
699 unsigned param_index_base, param_base;
700
701 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
702
703 if (reg.Register.Dimension) {
704
705 if (reg.Dimension.Indirect)
706 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
707 reg.Dimension.Index);
708 else
709 vertex_index = lp_build_const_int32(gallivm,
710 reg.Dimension.Index);
711 }
712
713 /* Get information about the register. */
714 if (reg.Register.File == TGSI_FILE_INPUT) {
715 name = info->input_semantic_name;
716 index = info->input_semantic_index;
717 array_first = info->input_array_first;
718 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
719 name = info->output_semantic_name;
720 index = info->output_semantic_index;
721 array_first = info->output_array_first;
722 } else {
723 assert(0);
724 return NULL;
725 }
726
727 if (reg.Register.Indirect) {
728 if (reg.Indirect.ArrayID)
729 param_base = array_first[reg.Indirect.ArrayID];
730 else
731 param_base = reg.Register.Index;
732
733 param_index = get_indirect_index(ctx, &reg.Indirect,
734 reg.Register.Index - param_base);
735
736 } else {
737 param_base = reg.Register.Index;
738 param_index = lp_build_const_int32(gallivm, 0);
739 }
740
741 param_index_base = si_shader_io_get_unique_index(name[param_base],
742 index[param_base]);
743
744 param_index = LLVMBuildAdd(gallivm->builder, param_index,
745 lp_build_const_int32(gallivm, param_index_base),
746 "");
747
748 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
749 }
750
751 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
752 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
753 * or v4i32 (num_channels=3,4). */
754 static void build_tbuffer_store(struct si_shader_context *ctx,
755 LLVMValueRef rsrc,
756 LLVMValueRef vdata,
757 unsigned num_channels,
758 LLVMValueRef vaddr,
759 LLVMValueRef soffset,
760 unsigned inst_offset,
761 unsigned dfmt,
762 unsigned nfmt,
763 unsigned offen,
764 unsigned idxen,
765 unsigned glc,
766 unsigned slc,
767 unsigned tfe)
768 {
769 struct gallivm_state *gallivm = &ctx->gallivm;
770 LLVMValueRef args[] = {
771 rsrc,
772 vdata,
773 LLVMConstInt(ctx->i32, num_channels, 0),
774 vaddr,
775 soffset,
776 LLVMConstInt(ctx->i32, inst_offset, 0),
777 LLVMConstInt(ctx->i32, dfmt, 0),
778 LLVMConstInt(ctx->i32, nfmt, 0),
779 LLVMConstInt(ctx->i32, offen, 0),
780 LLVMConstInt(ctx->i32, idxen, 0),
781 LLVMConstInt(ctx->i32, glc, 0),
782 LLVMConstInt(ctx->i32, slc, 0),
783 LLVMConstInt(ctx->i32, tfe, 0)
784 };
785
786 /* The instruction offset field has 12 bits */
787 assert(offen || inst_offset < (1 << 12));
788
789 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
790 unsigned func = CLAMP(num_channels, 1, 3) - 1;
791 const char *types[] = {"i32", "v2i32", "v4i32"};
792 char name[256];
793 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
794
795 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
796 args, ARRAY_SIZE(args), 0);
797 }
798
799 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
800 LLVMValueRef rsrc,
801 LLVMValueRef vdata,
802 unsigned num_channels,
803 LLVMValueRef vaddr,
804 LLVMValueRef soffset,
805 unsigned inst_offset)
806 {
807 static unsigned dfmt[] = {
808 V_008F0C_BUF_DATA_FORMAT_32,
809 V_008F0C_BUF_DATA_FORMAT_32_32,
810 V_008F0C_BUF_DATA_FORMAT_32_32_32,
811 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
812 };
813 assert(num_channels >= 1 && num_channels <= 4);
814
815 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
816 inst_offset, dfmt[num_channels-1],
817 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
818 }
819
820 static LLVMValueRef build_buffer_load(struct si_shader_context *ctx,
821 LLVMValueRef rsrc,
822 int num_channels,
823 LLVMValueRef vindex,
824 LLVMValueRef voffset,
825 LLVMValueRef soffset,
826 unsigned inst_offset,
827 unsigned glc,
828 unsigned slc)
829 {
830 struct gallivm_state *gallivm = &ctx->gallivm;
831 unsigned func = CLAMP(num_channels, 1, 3) - 1;
832
833 if (HAVE_LLVM >= 0x309) {
834 LLVMValueRef args[] = {
835 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, ""),
836 vindex ? vindex : LLVMConstInt(ctx->i32, 0, 0),
837 LLVMConstInt(ctx->i32, inst_offset, 0),
838 LLVMConstInt(ctx->i1, glc, 0),
839 LLVMConstInt(ctx->i1, slc, 0)
840 };
841
842 LLVMTypeRef types[] = {ctx->f32, LLVMVectorType(ctx->f32, 2),
843 ctx->v4f32};
844 const char *type_names[] = {"f32", "v2f32", "v4f32"};
845 char name[256];
846
847 if (voffset) {
848 args[2] = LLVMBuildAdd(gallivm->builder, args[2], voffset,
849 "");
850 }
851
852 if (soffset) {
853 args[2] = LLVMBuildAdd(gallivm->builder, args[2], soffset,
854 "");
855 }
856
857 snprintf(name, sizeof(name), "llvm.amdgcn.buffer.load.%s",
858 type_names[func]);
859
860 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
861 ARRAY_SIZE(args), LP_FUNC_ATTR_READONLY);
862 } else {
863 LLVMValueRef args[] = {
864 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v16i8, ""),
865 voffset ? voffset : vindex,
866 soffset,
867 LLVMConstInt(ctx->i32, inst_offset, 0),
868 LLVMConstInt(ctx->i32, voffset ? 1 : 0, 0), // offen
869 LLVMConstInt(ctx->i32, vindex ? 1 : 0, 0), //idxen
870 LLVMConstInt(ctx->i32, glc, 0),
871 LLVMConstInt(ctx->i32, slc, 0),
872 LLVMConstInt(ctx->i32, 0, 0), // TFE
873 };
874
875 LLVMTypeRef types[] = {ctx->i32, LLVMVectorType(ctx->i32, 2),
876 ctx->v4i32};
877 const char *type_names[] = {"i32", "v2i32", "v4i32"};
878 const char *arg_type = "i32";
879 char name[256];
880
881 if (voffset && vindex) {
882 LLVMValueRef vaddr[] = {vindex, voffset};
883
884 arg_type = "v2i32";
885 args[1] = lp_build_gather_values(gallivm, vaddr, 2);
886 }
887
888 snprintf(name, sizeof(name), "llvm.SI.buffer.load.dword.%s.%s",
889 type_names[func], arg_type);
890
891 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
892 ARRAY_SIZE(args), LP_FUNC_ATTR_READONLY);
893 }
894 }
895
896 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
897 enum tgsi_opcode_type type, unsigned swizzle,
898 LLVMValueRef buffer, LLVMValueRef offset,
899 LLVMValueRef base)
900 {
901 struct si_shader_context *ctx = si_shader_context(bld_base);
902 struct gallivm_state *gallivm = bld_base->base.gallivm;
903 LLVMValueRef value, value2;
904 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
905 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
906
907 if (swizzle == ~0) {
908 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
909 0, 1, 0);
910
911 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
912 }
913
914 if (!tgsi_type_is_64bit(type)) {
915 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
916 0, 1, 0);
917
918 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
919 return LLVMBuildExtractElement(gallivm->builder, value,
920 lp_build_const_int32(gallivm, swizzle), "");
921 }
922
923 value = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
924 swizzle * 4, 1, 0);
925
926 value2 = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
927 swizzle * 4 + 4, 1, 0);
928
929 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
930 }
931
932 /**
933 * Load from LDS.
934 *
935 * \param type output value type
936 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
937 * \param dw_addr address in dwords
938 */
939 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
940 enum tgsi_opcode_type type, unsigned swizzle,
941 LLVMValueRef dw_addr)
942 {
943 struct si_shader_context *ctx = si_shader_context(bld_base);
944 struct gallivm_state *gallivm = bld_base->base.gallivm;
945 LLVMValueRef value;
946
947 if (swizzle == ~0) {
948 LLVMValueRef values[TGSI_NUM_CHANNELS];
949
950 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
951 values[chan] = lds_load(bld_base, type, chan, dw_addr);
952
953 return lp_build_gather_values(bld_base->base.gallivm, values,
954 TGSI_NUM_CHANNELS);
955 }
956
957 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
958 lp_build_const_int32(gallivm, swizzle));
959
960 value = build_indexed_load(ctx, ctx->lds, dw_addr, false);
961 if (tgsi_type_is_64bit(type)) {
962 LLVMValueRef value2;
963 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
964 lp_build_const_int32(gallivm, 1));
965 value2 = build_indexed_load(ctx, ctx->lds, dw_addr, false);
966 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
967 }
968
969 return LLVMBuildBitCast(gallivm->builder, value,
970 tgsi2llvmtype(bld_base, type), "");
971 }
972
973 /**
974 * Store to LDS.
975 *
976 * \param swizzle offset (typically 0..3)
977 * \param dw_addr address in dwords
978 * \param value value to store
979 */
980 static void lds_store(struct lp_build_tgsi_context *bld_base,
981 unsigned swizzle, LLVMValueRef dw_addr,
982 LLVMValueRef value)
983 {
984 struct si_shader_context *ctx = si_shader_context(bld_base);
985 struct gallivm_state *gallivm = bld_base->base.gallivm;
986
987 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
988 lp_build_const_int32(gallivm, swizzle));
989
990 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
991 build_indexed_store(ctx, ctx->lds,
992 dw_addr, value);
993 }
994
995 static LLVMValueRef fetch_input_tcs(
996 struct lp_build_tgsi_context *bld_base,
997 const struct tgsi_full_src_register *reg,
998 enum tgsi_opcode_type type, unsigned swizzle)
999 {
1000 struct si_shader_context *ctx = si_shader_context(bld_base);
1001 LLVMValueRef dw_addr, stride;
1002
1003 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
1004 dw_addr = get_tcs_in_current_patch_offset(ctx);
1005 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1006
1007 return lds_load(bld_base, type, swizzle, dw_addr);
1008 }
1009
1010 static LLVMValueRef fetch_output_tcs(
1011 struct lp_build_tgsi_context *bld_base,
1012 const struct tgsi_full_src_register *reg,
1013 enum tgsi_opcode_type type, unsigned swizzle)
1014 {
1015 struct si_shader_context *ctx = si_shader_context(bld_base);
1016 LLVMValueRef dw_addr, stride;
1017
1018 if (reg->Register.Dimension) {
1019 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1020 dw_addr = get_tcs_out_current_patch_offset(ctx);
1021 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1022 } else {
1023 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1024 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1025 }
1026
1027 return lds_load(bld_base, type, swizzle, dw_addr);
1028 }
1029
1030 static LLVMValueRef fetch_input_tes(
1031 struct lp_build_tgsi_context *bld_base,
1032 const struct tgsi_full_src_register *reg,
1033 enum tgsi_opcode_type type, unsigned swizzle)
1034 {
1035 struct si_shader_context *ctx = si_shader_context(bld_base);
1036 struct gallivm_state *gallivm = bld_base->base.gallivm;
1037 LLVMValueRef rw_buffers, buffer, base, addr;
1038
1039 rw_buffers = LLVMGetParam(ctx->main_fn,
1040 SI_PARAM_RW_BUFFERS);
1041 buffer = build_indexed_load_const(ctx, rw_buffers,
1042 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1043
1044 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1045 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1046
1047 return buffer_load(bld_base, type, swizzle, buffer, base, addr);
1048 }
1049
1050 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1051 const struct tgsi_full_instruction *inst,
1052 const struct tgsi_opcode_info *info,
1053 LLVMValueRef dst[4])
1054 {
1055 struct si_shader_context *ctx = si_shader_context(bld_base);
1056 struct gallivm_state *gallivm = bld_base->base.gallivm;
1057 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
1058 unsigned chan_index;
1059 LLVMValueRef dw_addr, stride;
1060 LLVMValueRef rw_buffers, buffer, base, buf_addr;
1061 LLVMValueRef values[4];
1062
1063 /* Only handle per-patch and per-vertex outputs here.
1064 * Vectors will be lowered to scalars and this function will be called again.
1065 */
1066 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1067 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1068 si_llvm_emit_store(bld_base, inst, info, dst);
1069 return;
1070 }
1071
1072 if (reg->Register.Dimension) {
1073 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1074 dw_addr = get_tcs_out_current_patch_offset(ctx);
1075 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1076 } else {
1077 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1078 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1079 }
1080
1081 rw_buffers = LLVMGetParam(ctx->main_fn,
1082 SI_PARAM_RW_BUFFERS);
1083 buffer = build_indexed_load_const(ctx, rw_buffers,
1084 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1085
1086 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1087 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1088
1089
1090 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1091 LLVMValueRef value = dst[chan_index];
1092
1093 if (inst->Instruction.Saturate)
1094 value = si_llvm_saturate(bld_base, value);
1095
1096 lds_store(bld_base, chan_index, dw_addr, value);
1097
1098 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1099 values[chan_index] = value;
1100
1101 if (inst->Dst[0].Register.WriteMask != 0xF) {
1102 build_tbuffer_store_dwords(ctx, buffer, value, 1,
1103 buf_addr, base,
1104 4 * chan_index);
1105 }
1106 }
1107
1108 if (inst->Dst[0].Register.WriteMask == 0xF) {
1109 LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
1110 values, 4);
1111 build_tbuffer_store_dwords(ctx, buffer, value, 4, buf_addr,
1112 base, 0);
1113 }
1114 }
1115
1116 static LLVMValueRef fetch_input_gs(
1117 struct lp_build_tgsi_context *bld_base,
1118 const struct tgsi_full_src_register *reg,
1119 enum tgsi_opcode_type type,
1120 unsigned swizzle)
1121 {
1122 struct lp_build_context *base = &bld_base->base;
1123 struct si_shader_context *ctx = si_shader_context(bld_base);
1124 struct si_shader *shader = ctx->shader;
1125 struct lp_build_context *uint = &ctx->soa.bld_base.uint_bld;
1126 struct gallivm_state *gallivm = base->gallivm;
1127 LLVMValueRef vtx_offset;
1128 LLVMValueRef args[9];
1129 unsigned vtx_offset_param;
1130 struct tgsi_shader_info *info = &shader->selector->info;
1131 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1132 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1133 unsigned param;
1134 LLVMValueRef value;
1135
1136 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1137 return get_primitive_id(bld_base, swizzle);
1138
1139 if (!reg->Register.Dimension)
1140 return NULL;
1141
1142 if (swizzle == ~0) {
1143 LLVMValueRef values[TGSI_NUM_CHANNELS];
1144 unsigned chan;
1145 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1146 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1147 }
1148 return lp_build_gather_values(bld_base->base.gallivm, values,
1149 TGSI_NUM_CHANNELS);
1150 }
1151
1152 /* Get the vertex offset parameter */
1153 vtx_offset_param = reg->Dimension.Index;
1154 if (vtx_offset_param < 2) {
1155 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1156 } else {
1157 assert(vtx_offset_param < 6);
1158 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1159 }
1160 vtx_offset = lp_build_mul_imm(uint,
1161 LLVMGetParam(ctx->main_fn,
1162 vtx_offset_param),
1163 4);
1164
1165 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1166 args[0] = ctx->esgs_ring;
1167 args[1] = vtx_offset;
1168 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
1169 args[3] = uint->zero;
1170 args[4] = uint->one; /* OFFEN */
1171 args[5] = uint->zero; /* IDXEN */
1172 args[6] = uint->one; /* GLC */
1173 args[7] = uint->zero; /* SLC */
1174 args[8] = uint->zero; /* TFE */
1175
1176 value = lp_build_intrinsic(gallivm->builder,
1177 "llvm.SI.buffer.load.dword.i32.i32",
1178 ctx->i32, args, 9,
1179 LP_FUNC_ATTR_READONLY);
1180 if (tgsi_type_is_64bit(type)) {
1181 LLVMValueRef value2;
1182 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
1183 value2 = lp_build_intrinsic(gallivm->builder,
1184 "llvm.SI.buffer.load.dword.i32.i32",
1185 ctx->i32, args, 9,
1186 LP_FUNC_ATTR_READONLY);
1187 return si_llvm_emit_fetch_64bit(bld_base, type,
1188 value, value2);
1189 }
1190 return LLVMBuildBitCast(gallivm->builder,
1191 value,
1192 tgsi2llvmtype(bld_base, type), "");
1193 }
1194
1195 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1196 {
1197 switch (interpolate) {
1198 case TGSI_INTERPOLATE_CONSTANT:
1199 return 0;
1200
1201 case TGSI_INTERPOLATE_LINEAR:
1202 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1203 return SI_PARAM_LINEAR_SAMPLE;
1204 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1205 return SI_PARAM_LINEAR_CENTROID;
1206 else
1207 return SI_PARAM_LINEAR_CENTER;
1208 break;
1209 case TGSI_INTERPOLATE_COLOR:
1210 case TGSI_INTERPOLATE_PERSPECTIVE:
1211 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1212 return SI_PARAM_PERSP_SAMPLE;
1213 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1214 return SI_PARAM_PERSP_CENTROID;
1215 else
1216 return SI_PARAM_PERSP_CENTER;
1217 break;
1218 default:
1219 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1220 return -1;
1221 }
1222 }
1223
1224 static LLVMValueRef build_fs_interp(
1225 struct lp_build_tgsi_context *bld_base,
1226 LLVMValueRef llvm_chan,
1227 LLVMValueRef attr_number,
1228 LLVMValueRef params,
1229 LLVMValueRef i,
1230 LLVMValueRef j) {
1231
1232 struct si_shader_context *ctx = si_shader_context(bld_base);
1233 struct gallivm_state *gallivm = bld_base->base.gallivm;
1234 LLVMValueRef args[5];
1235 LLVMValueRef p1;
1236 if (HAVE_LLVM < 0x0400) {
1237 LLVMValueRef ij[2];
1238 ij[0] = LLVMBuildBitCast(gallivm->builder, i, ctx->i32, "");
1239 ij[1] = LLVMBuildBitCast(gallivm->builder, j, ctx->i32, "");
1240
1241 args[0] = llvm_chan;
1242 args[1] = attr_number;
1243 args[2] = params;
1244 args[3] = lp_build_gather_values(gallivm, ij, 2);
1245 return lp_build_intrinsic(gallivm->builder, "llvm.SI.fs.interp",
1246 ctx->f32, args, 4,
1247 LP_FUNC_ATTR_READNONE);
1248 }
1249
1250 args[0] = i;
1251 args[1] = llvm_chan;
1252 args[2] = attr_number;
1253 args[3] = params;
1254
1255 p1 = lp_build_intrinsic(gallivm->builder, "llvm.amdgcn.interp.p1",
1256 ctx->f32, args, 4, LP_FUNC_ATTR_READNONE);
1257
1258 args[0] = p1;
1259 args[1] = j;
1260 args[2] = llvm_chan;
1261 args[3] = attr_number;
1262 args[4] = params;
1263
1264 return lp_build_intrinsic(gallivm->builder, "llvm.amdgcn.interp.p2",
1265 ctx->f32, args, 5, LP_FUNC_ATTR_READNONE);
1266 }
1267
1268 static LLVMValueRef build_fs_interp_mov(
1269 struct lp_build_tgsi_context *bld_base,
1270 LLVMValueRef parameter,
1271 LLVMValueRef llvm_chan,
1272 LLVMValueRef attr_number,
1273 LLVMValueRef params) {
1274
1275 struct si_shader_context *ctx = si_shader_context(bld_base);
1276 struct gallivm_state *gallivm = bld_base->base.gallivm;
1277 LLVMValueRef args[4];
1278 if (HAVE_LLVM < 0x0400) {
1279 args[0] = llvm_chan;
1280 args[1] = attr_number;
1281 args[2] = params;
1282
1283 return lp_build_intrinsic(gallivm->builder,
1284 "llvm.SI.fs.constant",
1285 ctx->f32, args, 3,
1286 LP_FUNC_ATTR_READNONE);
1287 }
1288
1289 args[0] = parameter;
1290 args[1] = llvm_chan;
1291 args[2] = attr_number;
1292 args[3] = params;
1293
1294 return lp_build_intrinsic(gallivm->builder, "llvm.amdgcn.interp.mov",
1295 ctx->f32, args, 4, LP_FUNC_ATTR_READNONE);
1296 }
1297
1298 /**
1299 * Interpolate a fragment shader input.
1300 *
1301 * @param ctx context
1302 * @param input_index index of the input in hardware
1303 * @param semantic_name TGSI_SEMANTIC_*
1304 * @param semantic_index semantic index
1305 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1306 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1307 * @param interp_param interpolation weights (i,j)
1308 * @param prim_mask SI_PARAM_PRIM_MASK
1309 * @param face SI_PARAM_FRONT_FACE
1310 * @param result the return value (4 components)
1311 */
1312 static void interp_fs_input(struct si_shader_context *ctx,
1313 unsigned input_index,
1314 unsigned semantic_name,
1315 unsigned semantic_index,
1316 unsigned num_interp_inputs,
1317 unsigned colors_read_mask,
1318 LLVMValueRef interp_param,
1319 LLVMValueRef prim_mask,
1320 LLVMValueRef face,
1321 LLVMValueRef result[4])
1322 {
1323 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
1324 struct lp_build_context *base = &bld_base->base;
1325 struct lp_build_context *uint = &bld_base->uint_bld;
1326 struct gallivm_state *gallivm = base->gallivm;
1327 LLVMValueRef attr_number;
1328 LLVMValueRef i, j;
1329
1330 unsigned chan;
1331
1332 /* fs.constant returns the param from the middle vertex, so it's not
1333 * really useful for flat shading. It's meant to be used for custom
1334 * interpolation (but the intrinsic can't fetch from the other two
1335 * vertices).
1336 *
1337 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1338 * to do the right thing. The only reason we use fs.constant is that
1339 * fs.interp cannot be used on integers, because they can be equal
1340 * to NaN.
1341 *
1342 * When interp is false we will use fs.constant or for newer llvm,
1343 * amdgcn.interp.mov.
1344 */
1345 bool interp = interp_param != NULL;
1346
1347 attr_number = lp_build_const_int32(gallivm, input_index);
1348
1349 if (interp) {
1350 interp_param = LLVMBuildBitCast(gallivm->builder, interp_param,
1351 LLVMVectorType(ctx->f32, 2), "");
1352
1353 i = LLVMBuildExtractElement(gallivm->builder, interp_param,
1354 uint->zero, "");
1355 j = LLVMBuildExtractElement(gallivm->builder, interp_param,
1356 uint->one, "");
1357 }
1358
1359 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1360 ctx->shader->key.part.ps.prolog.color_two_side) {
1361 LLVMValueRef is_face_positive;
1362 LLVMValueRef back_attr_number;
1363
1364 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1365 * otherwise it's at offset "num_inputs".
1366 */
1367 unsigned back_attr_offset = num_interp_inputs;
1368 if (semantic_index == 1 && colors_read_mask & 0xf)
1369 back_attr_offset += 1;
1370
1371 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1372
1373 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1374 face, uint->zero, "");
1375
1376 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1377 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1378 LLVMValueRef front, back;
1379
1380 if (interp) {
1381 front = build_fs_interp(bld_base, llvm_chan,
1382 attr_number, prim_mask,
1383 i, j);
1384 back = build_fs_interp(bld_base, llvm_chan,
1385 back_attr_number, prim_mask,
1386 i, j);
1387 } else {
1388 front = build_fs_interp_mov(bld_base,
1389 lp_build_const_int32(gallivm, 2), /* P0 */
1390 llvm_chan, attr_number, prim_mask);
1391 back = build_fs_interp_mov(bld_base,
1392 lp_build_const_int32(gallivm, 2), /* P0 */
1393 llvm_chan, back_attr_number, prim_mask);
1394 }
1395
1396 result[chan] = LLVMBuildSelect(gallivm->builder,
1397 is_face_positive,
1398 front,
1399 back,
1400 "");
1401 }
1402 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1403 if (interp) {
1404 result[0] = build_fs_interp(bld_base, uint->zero,
1405 attr_number, prim_mask, i, j);
1406 } else {
1407 result[0] = build_fs_interp_mov(bld_base, uint->zero,
1408 lp_build_const_int32(gallivm, 2), /* P0 */
1409 attr_number, prim_mask);
1410 }
1411 result[1] =
1412 result[2] = lp_build_const_float(gallivm, 0.0f);
1413 result[3] = lp_build_const_float(gallivm, 1.0f);
1414 } else {
1415 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1416 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1417
1418 if (interp) {
1419 result[chan] = build_fs_interp(bld_base,
1420 llvm_chan, attr_number, prim_mask, i, j);
1421 } else {
1422 result[chan] = build_fs_interp_mov(bld_base,
1423 lp_build_const_int32(gallivm, 2), /* P0 */
1424 llvm_chan, attr_number, prim_mask);
1425 }
1426 }
1427 }
1428 }
1429
1430 static void declare_input_fs(
1431 struct si_shader_context *radeon_bld,
1432 unsigned input_index,
1433 const struct tgsi_full_declaration *decl,
1434 LLVMValueRef out[4])
1435 {
1436 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
1437 struct si_shader_context *ctx =
1438 si_shader_context(&radeon_bld->soa.bld_base);
1439 struct si_shader *shader = ctx->shader;
1440 LLVMValueRef main_fn = radeon_bld->main_fn;
1441 LLVMValueRef interp_param = NULL;
1442 int interp_param_idx;
1443
1444 /* Get colors from input VGPRs (set by the prolog). */
1445 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1446 unsigned i = decl->Semantic.Index;
1447 unsigned colors_read = shader->selector->info.colors_read;
1448 unsigned mask = colors_read >> (i * 4);
1449 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1450 (i ? util_bitcount(colors_read & 0xf) : 0);
1451
1452 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1453 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1454 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1455 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1456 return;
1457 }
1458
1459 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1460 decl->Interp.Location);
1461 if (interp_param_idx == -1)
1462 return;
1463 else if (interp_param_idx) {
1464 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1465 }
1466
1467 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
1468 decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR &&
1469 ctx->shader->key.part.ps.prolog.flatshade_colors)
1470 interp_param = NULL; /* load the constant color */
1471
1472 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1473 decl->Semantic.Index, shader->selector->info.num_inputs,
1474 shader->selector->info.colors_read, interp_param,
1475 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1476 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1477 &out[0]);
1478 }
1479
1480 static LLVMValueRef get_sample_id(struct si_shader_context *radeon_bld)
1481 {
1482 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1483 SI_PARAM_ANCILLARY, 8, 4);
1484 }
1485
1486 /**
1487 * Set range metadata on an instruction. This can only be used on load and
1488 * call instructions. If you know an instruction can only produce the values
1489 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1490 * \p lo is the minimum value inclusive.
1491 * \p hi is the maximum value exclusive.
1492 */
1493 static void set_range_metadata(struct si_shader_context *ctx,
1494 LLVMValueRef value, unsigned lo, unsigned hi)
1495 {
1496 LLVMValueRef range_md, md_args[2];
1497 LLVMTypeRef type = LLVMTypeOf(value);
1498 LLVMContextRef context = LLVMGetTypeContext(type);
1499
1500 md_args[0] = LLVMConstInt(type, lo, false);
1501 md_args[1] = LLVMConstInt(type, hi, false);
1502 range_md = LLVMMDNodeInContext(context, md_args, 2);
1503 LLVMSetMetadata(value, ctx->range_md_kind, range_md);
1504 }
1505
1506 static LLVMValueRef get_thread_id(struct si_shader_context *ctx)
1507 {
1508 struct gallivm_state *gallivm = &ctx->gallivm;
1509 LLVMValueRef tid;
1510
1511 if (HAVE_LLVM < 0x0308) {
1512 tid = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid",
1513 ctx->i32, NULL, 0, LP_FUNC_ATTR_READNONE);
1514 } else {
1515 LLVMValueRef tid_args[2];
1516 tid_args[0] = lp_build_const_int32(gallivm, 0xffffffff);
1517 tid_args[1] = lp_build_const_int32(gallivm, 0);
1518 tid_args[1] = lp_build_intrinsic(gallivm->builder,
1519 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1520 tid_args, 2, LP_FUNC_ATTR_READNONE);
1521
1522 tid = lp_build_intrinsic(gallivm->builder,
1523 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1524 tid_args, 2, LP_FUNC_ATTR_READNONE);
1525 }
1526 set_range_metadata(ctx, tid, 0, 64);
1527 return tid;
1528 }
1529
1530 /**
1531 * Load a dword from a constant buffer.
1532 */
1533 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1534 LLVMValueRef resource,
1535 LLVMValueRef offset)
1536 {
1537 LLVMBuilderRef builder = ctx->gallivm.builder;
1538 LLVMValueRef args[2] = {resource, offset};
1539
1540 return lp_build_intrinsic(builder, "llvm.SI.load.const", ctx->f32, args, 2,
1541 LP_FUNC_ATTR_READNONE);
1542 }
1543
1544 static LLVMValueRef load_sample_position(struct si_shader_context *radeon_bld, LLVMValueRef sample_id)
1545 {
1546 struct si_shader_context *ctx =
1547 si_shader_context(&radeon_bld->soa.bld_base);
1548 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1549 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1550 LLVMBuilderRef builder = gallivm->builder;
1551 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1552 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1553 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1554
1555 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1556 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1557 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1558
1559 LLVMValueRef pos[4] = {
1560 buffer_load_const(ctx, resource, offset0),
1561 buffer_load_const(ctx, resource, offset1),
1562 lp_build_const_float(gallivm, 0),
1563 lp_build_const_float(gallivm, 0)
1564 };
1565
1566 return lp_build_gather_values(gallivm, pos, 4);
1567 }
1568
1569 static void declare_system_value(
1570 struct si_shader_context *radeon_bld,
1571 unsigned index,
1572 const struct tgsi_full_declaration *decl)
1573 {
1574 struct si_shader_context *ctx =
1575 si_shader_context(&radeon_bld->soa.bld_base);
1576 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1577 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1578 LLVMValueRef value = 0;
1579
1580 switch (decl->Semantic.Name) {
1581 case TGSI_SEMANTIC_INSTANCEID:
1582 value = LLVMGetParam(radeon_bld->main_fn,
1583 ctx->param_instance_id);
1584 break;
1585
1586 case TGSI_SEMANTIC_VERTEXID:
1587 value = LLVMBuildAdd(gallivm->builder,
1588 LLVMGetParam(radeon_bld->main_fn,
1589 ctx->param_vertex_id),
1590 LLVMGetParam(radeon_bld->main_fn,
1591 SI_PARAM_BASE_VERTEX), "");
1592 break;
1593
1594 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1595 value = LLVMGetParam(radeon_bld->main_fn,
1596 ctx->param_vertex_id);
1597 break;
1598
1599 case TGSI_SEMANTIC_BASEVERTEX:
1600 value = LLVMGetParam(radeon_bld->main_fn,
1601 SI_PARAM_BASE_VERTEX);
1602 break;
1603
1604 case TGSI_SEMANTIC_BASEINSTANCE:
1605 value = LLVMGetParam(radeon_bld->main_fn,
1606 SI_PARAM_START_INSTANCE);
1607 break;
1608
1609 case TGSI_SEMANTIC_DRAWID:
1610 value = LLVMGetParam(radeon_bld->main_fn,
1611 SI_PARAM_DRAWID);
1612 break;
1613
1614 case TGSI_SEMANTIC_INVOCATIONID:
1615 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1616 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1617 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1618 value = LLVMGetParam(radeon_bld->main_fn,
1619 SI_PARAM_GS_INSTANCE_ID);
1620 else
1621 assert(!"INVOCATIONID not implemented");
1622 break;
1623
1624 case TGSI_SEMANTIC_POSITION:
1625 {
1626 LLVMValueRef pos[4] = {
1627 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1628 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1629 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1630 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1631 LLVMGetParam(radeon_bld->main_fn,
1632 SI_PARAM_POS_W_FLOAT)),
1633 };
1634 value = lp_build_gather_values(gallivm, pos, 4);
1635 break;
1636 }
1637
1638 case TGSI_SEMANTIC_FACE:
1639 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1640 break;
1641
1642 case TGSI_SEMANTIC_SAMPLEID:
1643 value = get_sample_id(radeon_bld);
1644 break;
1645
1646 case TGSI_SEMANTIC_SAMPLEPOS: {
1647 LLVMValueRef pos[4] = {
1648 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1649 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1650 lp_build_const_float(gallivm, 0),
1651 lp_build_const_float(gallivm, 0)
1652 };
1653 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1654 TGSI_OPCODE_FRC, pos[0]);
1655 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1656 TGSI_OPCODE_FRC, pos[1]);
1657 value = lp_build_gather_values(gallivm, pos, 4);
1658 break;
1659 }
1660
1661 case TGSI_SEMANTIC_SAMPLEMASK:
1662 /* This can only occur with the OpenGL Core profile, which
1663 * doesn't support smoothing.
1664 */
1665 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1666 break;
1667
1668 case TGSI_SEMANTIC_TESSCOORD:
1669 {
1670 LLVMValueRef coord[4] = {
1671 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1672 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1673 bld->zero,
1674 bld->zero
1675 };
1676
1677 /* For triangles, the vector should be (u, v, 1-u-v). */
1678 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1679 PIPE_PRIM_TRIANGLES)
1680 coord[2] = lp_build_sub(bld, bld->one,
1681 lp_build_add(bld, coord[0], coord[1]));
1682
1683 value = lp_build_gather_values(gallivm, coord, 4);
1684 break;
1685 }
1686
1687 case TGSI_SEMANTIC_VERTICESIN:
1688 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1689 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1690 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1691 value = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 7);
1692 else
1693 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1694 break;
1695
1696 case TGSI_SEMANTIC_TESSINNER:
1697 case TGSI_SEMANTIC_TESSOUTER:
1698 {
1699 LLVMValueRef rw_buffers, buffer, base, addr;
1700 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1701
1702 rw_buffers = LLVMGetParam(ctx->main_fn,
1703 SI_PARAM_RW_BUFFERS);
1704 buffer = build_indexed_load_const(ctx, rw_buffers,
1705 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1706
1707 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1708 addr = get_tcs_tes_buffer_address(ctx, NULL,
1709 lp_build_const_int32(gallivm, param));
1710
1711 value = buffer_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1712 ~0, buffer, base, addr);
1713
1714 break;
1715 }
1716
1717 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1718 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1719 {
1720 LLVMValueRef buf, slot, val[4];
1721 int i, offset;
1722
1723 slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
1724 buf = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1725 buf = build_indexed_load_const(ctx, buf, slot);
1726 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1727
1728 for (i = 0; i < 4; i++)
1729 val[i] = buffer_load_const(ctx, buf,
1730 lp_build_const_int32(gallivm, (offset + i) * 4));
1731 value = lp_build_gather_values(gallivm, val, 4);
1732 break;
1733 }
1734
1735 case TGSI_SEMANTIC_PRIMID:
1736 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1737 break;
1738
1739 case TGSI_SEMANTIC_GRID_SIZE:
1740 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1741 break;
1742
1743 case TGSI_SEMANTIC_BLOCK_SIZE:
1744 {
1745 LLVMValueRef values[3];
1746 unsigned i;
1747 unsigned *properties = ctx->shader->selector->info.properties;
1748
1749 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1750 unsigned sizes[3] = {
1751 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1752 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1753 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1754 };
1755
1756 for (i = 0; i < 3; ++i)
1757 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1758
1759 value = lp_build_gather_values(gallivm, values, 3);
1760 } else {
1761 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_SIZE);
1762 }
1763 break;
1764 }
1765
1766 case TGSI_SEMANTIC_BLOCK_ID:
1767 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1768 break;
1769
1770 case TGSI_SEMANTIC_THREAD_ID:
1771 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1772 break;
1773
1774 #if HAVE_LLVM >= 0x0309
1775 case TGSI_SEMANTIC_HELPER_INVOCATION:
1776 value = lp_build_intrinsic(gallivm->builder,
1777 "llvm.amdgcn.ps.live",
1778 ctx->i1, NULL, 0,
1779 LP_FUNC_ATTR_READNONE);
1780 value = LLVMBuildNot(gallivm->builder, value, "");
1781 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1782 break;
1783 #endif
1784
1785 default:
1786 assert(!"unknown system value");
1787 return;
1788 }
1789
1790 radeon_bld->system_values[index] = value;
1791 }
1792
1793 static void declare_compute_memory(struct si_shader_context *radeon_bld,
1794 const struct tgsi_full_declaration *decl)
1795 {
1796 struct si_shader_context *ctx =
1797 si_shader_context(&radeon_bld->soa.bld_base);
1798 struct si_shader_selector *sel = ctx->shader->selector;
1799 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1800
1801 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1802 LLVMValueRef var;
1803
1804 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1805 assert(decl->Range.First == decl->Range.Last);
1806 assert(!ctx->shared_memory);
1807
1808 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1809 LLVMArrayType(ctx->i8, sel->local_size),
1810 "compute_lds",
1811 LOCAL_ADDR_SPACE);
1812 LLVMSetAlignment(var, 4);
1813
1814 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1815 }
1816
1817 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1818 {
1819 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1820 SI_PARAM_CONST_BUFFERS);
1821
1822 return build_indexed_load_const(ctx, list_ptr,
1823 LLVMConstInt(ctx->i32, i, 0));
1824 }
1825
1826 static LLVMValueRef fetch_constant(
1827 struct lp_build_tgsi_context *bld_base,
1828 const struct tgsi_full_src_register *reg,
1829 enum tgsi_opcode_type type,
1830 unsigned swizzle)
1831 {
1832 struct si_shader_context *ctx = si_shader_context(bld_base);
1833 struct lp_build_context *base = &bld_base->base;
1834 const struct tgsi_ind_register *ireg = &reg->Indirect;
1835 unsigned buf, idx;
1836
1837 LLVMValueRef addr, bufp;
1838 LLVMValueRef result;
1839
1840 if (swizzle == LP_CHAN_ALL) {
1841 unsigned chan;
1842 LLVMValueRef values[4];
1843 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1844 values[chan] = fetch_constant(bld_base, reg, type, chan);
1845
1846 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1847 }
1848
1849 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1850 idx = reg->Register.Index * 4 + swizzle;
1851
1852 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1853 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_CONST_BUFFERS);
1854 LLVMValueRef index;
1855 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1856 reg->Dimension.Index,
1857 SI_NUM_CONST_BUFFERS);
1858 bufp = build_indexed_load_const(ctx, ptr, index);
1859 } else
1860 bufp = load_const_buffer_desc(ctx, buf);
1861
1862 if (reg->Register.Indirect) {
1863 addr = ctx->soa.addr[ireg->Index][ireg->Swizzle];
1864 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1865 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1866 addr = lp_build_add(&bld_base->uint_bld, addr,
1867 lp_build_const_int32(base->gallivm, idx * 4));
1868 } else {
1869 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
1870 }
1871
1872 result = buffer_load_const(ctx, bufp, addr);
1873
1874 if (!tgsi_type_is_64bit(type))
1875 result = bitcast(bld_base, type, result);
1876 else {
1877 LLVMValueRef addr2, result2;
1878
1879 addr2 = lp_build_add(&bld_base->uint_bld, addr,
1880 LLVMConstInt(ctx->i32, 4, 0));
1881 result2 = buffer_load_const(ctx, bufp, addr2);
1882
1883 result = si_llvm_emit_fetch_64bit(bld_base, type,
1884 result, result2);
1885 }
1886 return result;
1887 }
1888
1889 /* Upper 16 bits must be zero. */
1890 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1891 LLVMValueRef val[2])
1892 {
1893 return LLVMBuildOr(gallivm->builder, val[0],
1894 LLVMBuildShl(gallivm->builder, val[1],
1895 lp_build_const_int32(gallivm, 16),
1896 ""), "");
1897 }
1898
1899 /* Upper 16 bits are ignored and will be dropped. */
1900 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1901 LLVMValueRef val[2])
1902 {
1903 LLVMValueRef v[2] = {
1904 LLVMBuildAnd(gallivm->builder, val[0],
1905 lp_build_const_int32(gallivm, 0xffff), ""),
1906 val[1],
1907 };
1908 return si_llvm_pack_two_int16(gallivm, v);
1909 }
1910
1911 /* Initialize arguments for the shader export intrinsic */
1912 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1913 LLVMValueRef *values,
1914 unsigned target,
1915 LLVMValueRef *args)
1916 {
1917 struct si_shader_context *ctx = si_shader_context(bld_base);
1918 struct lp_build_context *uint =
1919 &ctx->soa.bld_base.uint_bld;
1920 struct lp_build_context *base = &bld_base->base;
1921 struct gallivm_state *gallivm = base->gallivm;
1922 LLVMBuilderRef builder = base->gallivm->builder;
1923 LLVMValueRef val[4];
1924 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1925 unsigned chan;
1926 bool is_int8;
1927
1928 /* Default is 0xf. Adjusted below depending on the format. */
1929 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1930
1931 /* Specify whether the EXEC mask represents the valid mask */
1932 args[1] = uint->zero;
1933
1934 /* Specify whether this is the last export */
1935 args[2] = uint->zero;
1936
1937 /* Specify the target we are exporting */
1938 args[3] = lp_build_const_int32(base->gallivm, target);
1939
1940 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1941 const struct si_shader_key *key = &ctx->shader->key;
1942 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
1943 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1944
1945 assert(cbuf >= 0 && cbuf < 8);
1946 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1947 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
1948 }
1949
1950 args[4] = uint->zero; /* COMPR flag */
1951 args[5] = base->undef;
1952 args[6] = base->undef;
1953 args[7] = base->undef;
1954 args[8] = base->undef;
1955
1956 switch (spi_shader_col_format) {
1957 case V_028714_SPI_SHADER_ZERO:
1958 args[0] = uint->zero; /* writemask */
1959 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
1960 break;
1961
1962 case V_028714_SPI_SHADER_32_R:
1963 args[0] = uint->one; /* writemask */
1964 args[5] = values[0];
1965 break;
1966
1967 case V_028714_SPI_SHADER_32_GR:
1968 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
1969 args[5] = values[0];
1970 args[6] = values[1];
1971 break;
1972
1973 case V_028714_SPI_SHADER_32_AR:
1974 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
1975 args[5] = values[0];
1976 args[8] = values[3];
1977 break;
1978
1979 case V_028714_SPI_SHADER_FP16_ABGR:
1980 args[4] = uint->one; /* COMPR flag */
1981
1982 for (chan = 0; chan < 2; chan++) {
1983 LLVMValueRef pack_args[2] = {
1984 values[2 * chan],
1985 values[2 * chan + 1]
1986 };
1987 LLVMValueRef packed;
1988
1989 packed = lp_build_intrinsic(base->gallivm->builder,
1990 "llvm.SI.packf16",
1991 ctx->i32, pack_args, 2,
1992 LP_FUNC_ATTR_READNONE);
1993 args[chan + 5] =
1994 LLVMBuildBitCast(base->gallivm->builder,
1995 packed, ctx->f32, "");
1996 }
1997 break;
1998
1999 case V_028714_SPI_SHADER_UNORM16_ABGR:
2000 for (chan = 0; chan < 4; chan++) {
2001 val[chan] = si_llvm_saturate(bld_base, values[chan]);
2002 val[chan] = LLVMBuildFMul(builder, val[chan],
2003 lp_build_const_float(gallivm, 65535), "");
2004 val[chan] = LLVMBuildFAdd(builder, val[chan],
2005 lp_build_const_float(gallivm, 0.5), "");
2006 val[chan] = LLVMBuildFPToUI(builder, val[chan],
2007 ctx->i32, "");
2008 }
2009
2010 args[4] = uint->one; /* COMPR flag */
2011 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2012 si_llvm_pack_two_int16(gallivm, val));
2013 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2014 si_llvm_pack_two_int16(gallivm, val+2));
2015 break;
2016
2017 case V_028714_SPI_SHADER_SNORM16_ABGR:
2018 for (chan = 0; chan < 4; chan++) {
2019 /* Clamp between [-1, 1]. */
2020 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
2021 values[chan],
2022 lp_build_const_float(gallivm, 1));
2023 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
2024 val[chan],
2025 lp_build_const_float(gallivm, -1));
2026 /* Convert to a signed integer in [-32767, 32767]. */
2027 val[chan] = LLVMBuildFMul(builder, val[chan],
2028 lp_build_const_float(gallivm, 32767), "");
2029 /* If positive, add 0.5, else add -0.5. */
2030 val[chan] = LLVMBuildFAdd(builder, val[chan],
2031 LLVMBuildSelect(builder,
2032 LLVMBuildFCmp(builder, LLVMRealOGE,
2033 val[chan], base->zero, ""),
2034 lp_build_const_float(gallivm, 0.5),
2035 lp_build_const_float(gallivm, -0.5), ""), "");
2036 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2037 }
2038
2039 args[4] = uint->one; /* COMPR flag */
2040 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2041 si_llvm_pack_two_int32_as_int16(gallivm, val));
2042 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2043 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2044 break;
2045
2046 case V_028714_SPI_SHADER_UINT16_ABGR: {
2047 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2048 255 : 65535);
2049 /* Clamp. */
2050 for (chan = 0; chan < 4; chan++) {
2051 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2052 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
2053 val[chan], max);
2054 }
2055
2056 args[4] = uint->one; /* COMPR flag */
2057 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2058 si_llvm_pack_two_int16(gallivm, val));
2059 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2060 si_llvm_pack_two_int16(gallivm, val+2));
2061 break;
2062 }
2063
2064 case V_028714_SPI_SHADER_SINT16_ABGR: {
2065 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2066 127 : 32767);
2067 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
2068 -128 : -32768);
2069 /* Clamp. */
2070 for (chan = 0; chan < 4; chan++) {
2071 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2072 val[chan] = lp_build_emit_llvm_binary(bld_base,
2073 TGSI_OPCODE_IMIN,
2074 val[chan], max);
2075 val[chan] = lp_build_emit_llvm_binary(bld_base,
2076 TGSI_OPCODE_IMAX,
2077 val[chan], min);
2078 }
2079
2080 args[4] = uint->one; /* COMPR flag */
2081 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2082 si_llvm_pack_two_int32_as_int16(gallivm, val));
2083 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2084 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2085 break;
2086 }
2087
2088 case V_028714_SPI_SHADER_32_ABGR:
2089 memcpy(&args[5], values, sizeof(values[0]) * 4);
2090 break;
2091 }
2092 }
2093
2094 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2095 LLVMValueRef alpha)
2096 {
2097 struct si_shader_context *ctx = si_shader_context(bld_base);
2098 struct gallivm_state *gallivm = bld_base->base.gallivm;
2099
2100 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2101 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2102 SI_PARAM_ALPHA_REF);
2103
2104 LLVMValueRef alpha_pass =
2105 lp_build_cmp(&bld_base->base,
2106 ctx->shader->key.part.ps.epilog.alpha_func,
2107 alpha, alpha_ref);
2108 LLVMValueRef arg =
2109 lp_build_select(&bld_base->base,
2110 alpha_pass,
2111 lp_build_const_float(gallivm, 1.0f),
2112 lp_build_const_float(gallivm, -1.0f));
2113
2114 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2115 ctx->voidt, &arg, 1, 0);
2116 } else {
2117 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
2118 ctx->voidt, NULL, 0, 0);
2119 }
2120 }
2121
2122 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2123 LLVMValueRef alpha,
2124 unsigned samplemask_param)
2125 {
2126 struct si_shader_context *ctx = si_shader_context(bld_base);
2127 struct gallivm_state *gallivm = bld_base->base.gallivm;
2128 LLVMValueRef coverage;
2129
2130 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2131 coverage = LLVMGetParam(ctx->main_fn,
2132 samplemask_param);
2133 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
2134
2135 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
2136 ctx->i32,
2137 &coverage, 1, LP_FUNC_ATTR_READNONE);
2138
2139 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
2140 ctx->f32, "");
2141
2142 coverage = LLVMBuildFMul(gallivm->builder, coverage,
2143 lp_build_const_float(gallivm,
2144 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2145
2146 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
2147 }
2148
2149 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2150 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
2151 {
2152 struct si_shader_context *ctx = si_shader_context(bld_base);
2153 struct lp_build_context *base = &bld_base->base;
2154 struct lp_build_context *uint = &ctx->soa.bld_base.uint_bld;
2155 unsigned reg_index;
2156 unsigned chan;
2157 unsigned const_chan;
2158 LLVMValueRef base_elt;
2159 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2160 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
2161 SI_VS_CONST_CLIP_PLANES);
2162 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
2163
2164 for (reg_index = 0; reg_index < 2; reg_index ++) {
2165 LLVMValueRef *args = pos[2 + reg_index];
2166
2167 args[5] =
2168 args[6] =
2169 args[7] =
2170 args[8] = lp_build_const_float(base->gallivm, 0.0f);
2171
2172 /* Compute dot products of position and user clip plane vectors */
2173 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2174 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2175 args[1] = lp_build_const_int32(base->gallivm,
2176 ((reg_index * 4 + chan) * 4 +
2177 const_chan) * 4);
2178 base_elt = buffer_load_const(ctx, const_resource,
2179 args[1]);
2180 args[5 + chan] =
2181 lp_build_add(base, args[5 + chan],
2182 lp_build_mul(base, base_elt,
2183 out_elts[const_chan]));
2184 }
2185 }
2186
2187 args[0] = lp_build_const_int32(base->gallivm, 0xf);
2188 args[1] = uint->zero;
2189 args[2] = uint->zero;
2190 args[3] = lp_build_const_int32(base->gallivm,
2191 V_008DFC_SQ_EXP_POS + 2 + reg_index);
2192 args[4] = uint->zero;
2193 }
2194 }
2195
2196 static void si_dump_streamout(struct pipe_stream_output_info *so)
2197 {
2198 unsigned i;
2199
2200 if (so->num_outputs)
2201 fprintf(stderr, "STREAMOUT\n");
2202
2203 for (i = 0; i < so->num_outputs; i++) {
2204 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2205 so->output[i].start_component;
2206 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2207 i, so->output[i].output_buffer,
2208 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2209 so->output[i].register_index,
2210 mask & 1 ? "x" : "",
2211 mask & 2 ? "y" : "",
2212 mask & 4 ? "z" : "",
2213 mask & 8 ? "w" : "");
2214 }
2215 }
2216
2217 static void emit_streamout_output(struct si_shader_context *ctx,
2218 LLVMValueRef const *so_buffers,
2219 LLVMValueRef const *so_write_offsets,
2220 struct pipe_stream_output *stream_out,
2221 struct si_shader_output_values *shader_out)
2222 {
2223 struct gallivm_state *gallivm = &ctx->gallivm;
2224 LLVMBuilderRef builder = gallivm->builder;
2225 unsigned buf_idx = stream_out->output_buffer;
2226 unsigned start = stream_out->start_component;
2227 unsigned num_comps = stream_out->num_components;
2228 LLVMValueRef out[4];
2229
2230 assert(num_comps && num_comps <= 4);
2231 if (!num_comps || num_comps > 4)
2232 return;
2233
2234 /* Load the output as int. */
2235 for (int j = 0; j < num_comps; j++) {
2236 out[j] = LLVMBuildBitCast(builder,
2237 shader_out->values[start + j],
2238 ctx->i32, "");
2239 }
2240
2241 /* Pack the output. */
2242 LLVMValueRef vdata = NULL;
2243
2244 switch (num_comps) {
2245 case 1: /* as i32 */
2246 vdata = out[0];
2247 break;
2248 case 2: /* as v2i32 */
2249 case 3: /* as v4i32 (aligned to 4) */
2250 case 4: /* as v4i32 */
2251 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2252 for (int j = 0; j < num_comps; j++) {
2253 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2254 LLVMConstInt(ctx->i32, j, 0), "");
2255 }
2256 break;
2257 }
2258
2259 build_tbuffer_store_dwords(ctx, so_buffers[buf_idx],
2260 vdata, num_comps,
2261 so_write_offsets[buf_idx],
2262 LLVMConstInt(ctx->i32, 0, 0),
2263 stream_out->dst_offset * 4);
2264 }
2265
2266 /* On SI, the vertex shader is responsible for writing streamout data
2267 * to buffers. */
2268 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2269 struct si_shader_output_values *outputs,
2270 unsigned noutput)
2271 {
2272 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
2273 struct gallivm_state *gallivm = &ctx->gallivm;
2274 LLVMBuilderRef builder = gallivm->builder;
2275 int i;
2276 struct lp_build_if_state if_ctx;
2277 LLVMValueRef so_buffers[4];
2278 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2279 SI_PARAM_RW_BUFFERS);
2280
2281 /* Load the descriptors. */
2282 for (i = 0; i < 4; ++i) {
2283 if (ctx->shader->selector->so.stride[i]) {
2284 LLVMValueRef offset = lp_build_const_int32(gallivm,
2285 SI_VS_STREAMOUT_BUF0 + i);
2286
2287 so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
2288 }
2289 }
2290
2291 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2292 LLVMValueRef so_vtx_count =
2293 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2294
2295 LLVMValueRef tid = get_thread_id(ctx);
2296
2297 /* can_emit = tid < so_vtx_count; */
2298 LLVMValueRef can_emit =
2299 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2300
2301 LLVMValueRef stream_id =
2302 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
2303
2304 /* Emit the streamout code conditionally. This actually avoids
2305 * out-of-bounds buffer access. The hw tells us via the SGPR
2306 * (so_vtx_count) which threads are allowed to emit streamout data. */
2307 lp_build_if(&if_ctx, gallivm, can_emit);
2308 {
2309 /* The buffer offset is computed as follows:
2310 * ByteOffset = streamout_offset[buffer_id]*4 +
2311 * (streamout_write_index + thread_id)*stride[buffer_id] +
2312 * attrib_offset
2313 */
2314
2315 LLVMValueRef so_write_index =
2316 LLVMGetParam(ctx->main_fn,
2317 ctx->param_streamout_write_index);
2318
2319 /* Compute (streamout_write_index + thread_id). */
2320 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2321
2322 /* Compute the write offset for each enabled buffer. */
2323 LLVMValueRef so_write_offset[4] = {};
2324 for (i = 0; i < 4; i++) {
2325 if (!so->stride[i])
2326 continue;
2327
2328 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2329 ctx->param_streamout_offset[i]);
2330 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2331
2332 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2333 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2334 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2335 }
2336
2337 /* Write streamout data. */
2338 for (i = 0; i < so->num_outputs; i++) {
2339 unsigned reg = so->output[i].register_index;
2340 unsigned stream = so->output[i].stream;
2341 struct lp_build_if_state if_ctx_stream;
2342
2343 if (reg >= noutput)
2344 continue;
2345
2346 LLVMValueRef can_emit_stream =
2347 LLVMBuildICmp(builder, LLVMIntEQ,
2348 stream_id,
2349 lp_build_const_int32(gallivm, stream), "");
2350
2351 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
2352 emit_streamout_output(ctx, so_buffers, so_write_offset,
2353 &so->output[i], &outputs[reg]);
2354 lp_build_endif(&if_ctx_stream);
2355 }
2356 }
2357 lp_build_endif(&if_ctx);
2358 }
2359
2360
2361 /* Generate export instructions for hardware VS shader stage */
2362 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2363 struct si_shader_output_values *outputs,
2364 unsigned noutput)
2365 {
2366 struct si_shader_context *ctx = si_shader_context(bld_base);
2367 struct si_shader *shader = ctx->shader;
2368 struct lp_build_context *base = &bld_base->base;
2369 struct lp_build_context *uint =
2370 &ctx->soa.bld_base.uint_bld;
2371 LLVMValueRef args[9];
2372 LLVMValueRef pos_args[4][9] = { { 0 } };
2373 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2374 unsigned semantic_name, semantic_index;
2375 unsigned target;
2376 unsigned param_count = 0;
2377 unsigned pos_idx;
2378 int i;
2379
2380 for (i = 0; i < noutput; i++) {
2381 semantic_name = outputs[i].semantic_name;
2382 semantic_index = outputs[i].semantic_index;
2383 bool export_param = true;
2384
2385 switch (semantic_name) {
2386 case TGSI_SEMANTIC_POSITION: /* ignore these */
2387 case TGSI_SEMANTIC_PSIZE:
2388 case TGSI_SEMANTIC_CLIPVERTEX:
2389 case TGSI_SEMANTIC_EDGEFLAG:
2390 break;
2391 case TGSI_SEMANTIC_GENERIC:
2392 case TGSI_SEMANTIC_CLIPDIST:
2393 if (shader->key.opt.hw_vs.kill_outputs &
2394 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2395 export_param = false;
2396 break;
2397 default:
2398 if (shader->key.opt.hw_vs.kill_outputs2 &
2399 (1u << si_shader_io_get_unique_index2(semantic_name, semantic_index)))
2400 export_param = false;
2401 break;
2402 }
2403
2404 handle_semantic:
2405 /* Select the correct target */
2406 switch(semantic_name) {
2407 case TGSI_SEMANTIC_PSIZE:
2408 psize_value = outputs[i].values[0];
2409 continue;
2410 case TGSI_SEMANTIC_EDGEFLAG:
2411 edgeflag_value = outputs[i].values[0];
2412 continue;
2413 case TGSI_SEMANTIC_LAYER:
2414 layer_value = outputs[i].values[0];
2415 semantic_name = TGSI_SEMANTIC_GENERIC;
2416 goto handle_semantic;
2417 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2418 viewport_index_value = outputs[i].values[0];
2419 semantic_name = TGSI_SEMANTIC_GENERIC;
2420 goto handle_semantic;
2421 case TGSI_SEMANTIC_POSITION:
2422 target = V_008DFC_SQ_EXP_POS;
2423 break;
2424 case TGSI_SEMANTIC_COLOR:
2425 case TGSI_SEMANTIC_BCOLOR:
2426 if (!export_param)
2427 continue;
2428 target = V_008DFC_SQ_EXP_PARAM + param_count;
2429 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2430 shader->info.vs_output_param_offset[i] = param_count;
2431 param_count++;
2432 break;
2433 case TGSI_SEMANTIC_CLIPDIST:
2434 if (shader->key.opt.hw_vs.clip_disable) {
2435 semantic_name = TGSI_SEMANTIC_GENERIC;
2436 goto handle_semantic;
2437 }
2438 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2439 break;
2440 case TGSI_SEMANTIC_CLIPVERTEX:
2441 if (shader->key.opt.hw_vs.clip_disable)
2442 continue;
2443 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2444 continue;
2445 case TGSI_SEMANTIC_PRIMID:
2446 case TGSI_SEMANTIC_FOG:
2447 case TGSI_SEMANTIC_TEXCOORD:
2448 case TGSI_SEMANTIC_GENERIC:
2449 if (!export_param)
2450 continue;
2451 target = V_008DFC_SQ_EXP_PARAM + param_count;
2452 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2453 shader->info.vs_output_param_offset[i] = param_count;
2454 param_count++;
2455 break;
2456 default:
2457 target = 0;
2458 fprintf(stderr,
2459 "Warning: SI unhandled vs output type:%d\n",
2460 semantic_name);
2461 }
2462
2463 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
2464
2465 if (target >= V_008DFC_SQ_EXP_POS &&
2466 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2467 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
2468 args, sizeof(args));
2469 } else {
2470 lp_build_intrinsic(base->gallivm->builder,
2471 "llvm.SI.export", ctx->voidt,
2472 args, 9, 0);
2473 }
2474
2475 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2476 semantic_name = TGSI_SEMANTIC_GENERIC;
2477 goto handle_semantic;
2478 }
2479 }
2480
2481 shader->info.nr_param_exports = param_count;
2482
2483 /* We need to add the position output manually if it's missing. */
2484 if (!pos_args[0][0]) {
2485 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
2486 pos_args[0][1] = uint->zero; /* EXEC mask */
2487 pos_args[0][2] = uint->zero; /* last export? */
2488 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
2489 pos_args[0][4] = uint->zero; /* COMPR flag */
2490 pos_args[0][5] = base->zero; /* X */
2491 pos_args[0][6] = base->zero; /* Y */
2492 pos_args[0][7] = base->zero; /* Z */
2493 pos_args[0][8] = base->one; /* W */
2494 }
2495
2496 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2497 if (shader->selector->info.writes_psize ||
2498 shader->selector->info.writes_edgeflag ||
2499 shader->selector->info.writes_viewport_index ||
2500 shader->selector->info.writes_layer) {
2501 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
2502 shader->selector->info.writes_psize |
2503 (shader->selector->info.writes_edgeflag << 1) |
2504 (shader->selector->info.writes_layer << 2) |
2505 (shader->selector->info.writes_viewport_index << 3));
2506 pos_args[1][1] = uint->zero; /* EXEC mask */
2507 pos_args[1][2] = uint->zero; /* last export? */
2508 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
2509 pos_args[1][4] = uint->zero; /* COMPR flag */
2510 pos_args[1][5] = base->zero; /* X */
2511 pos_args[1][6] = base->zero; /* Y */
2512 pos_args[1][7] = base->zero; /* Z */
2513 pos_args[1][8] = base->zero; /* W */
2514
2515 if (shader->selector->info.writes_psize)
2516 pos_args[1][5] = psize_value;
2517
2518 if (shader->selector->info.writes_edgeflag) {
2519 /* The output is a float, but the hw expects an integer
2520 * with the first bit containing the edge flag. */
2521 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2522 edgeflag_value,
2523 ctx->i32, "");
2524 edgeflag_value = lp_build_min(&bld_base->int_bld,
2525 edgeflag_value,
2526 bld_base->int_bld.one);
2527
2528 /* The LLVM intrinsic expects a float. */
2529 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
2530 edgeflag_value,
2531 ctx->f32, "");
2532 }
2533
2534 if (shader->selector->info.writes_layer)
2535 pos_args[1][7] = layer_value;
2536
2537 if (shader->selector->info.writes_viewport_index)
2538 pos_args[1][8] = viewport_index_value;
2539 }
2540
2541 for (i = 0; i < 4; i++)
2542 if (pos_args[i][0])
2543 shader->info.nr_pos_exports++;
2544
2545 pos_idx = 0;
2546 for (i = 0; i < 4; i++) {
2547 if (!pos_args[i][0])
2548 continue;
2549
2550 /* Specify the target we are exporting */
2551 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2552
2553 if (pos_idx == shader->info.nr_pos_exports)
2554 /* Specify that this is the last export */
2555 pos_args[i][2] = uint->one;
2556
2557 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2558 ctx->voidt, pos_args[i], 9, 0);
2559 }
2560 }
2561
2562 /**
2563 * Forward all outputs from the vertex shader to the TES. This is only used
2564 * for the fixed function TCS.
2565 */
2566 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2567 {
2568 struct si_shader_context *ctx = si_shader_context(bld_base);
2569 struct gallivm_state *gallivm = bld_base->base.gallivm;
2570 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2571 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2572 uint64_t inputs;
2573
2574 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2575
2576 rw_buffers = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2577 buffer = build_indexed_load_const(ctx, rw_buffers,
2578 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
2579
2580 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2581
2582 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
2583 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2584 lds_vertex_stride, "");
2585 lds_base = get_tcs_in_current_patch_offset(ctx);
2586 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2587
2588 inputs = ctx->shader->key.mono.tcs.inputs_to_copy;
2589 while (inputs) {
2590 unsigned i = u_bit_scan64(&inputs);
2591
2592 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2593 lp_build_const_int32(gallivm, 4 * i),
2594 "");
2595
2596 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2597 invocation_id,
2598 lp_build_const_int32(gallivm, i));
2599
2600 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2601 lds_ptr);
2602
2603 build_tbuffer_store_dwords(ctx, buffer, value, 4, buffer_addr,
2604 buffer_offset, 0);
2605 }
2606 }
2607
2608 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2609 LLVMValueRef rel_patch_id,
2610 LLVMValueRef invocation_id,
2611 LLVMValueRef tcs_out_current_patch_data_offset)
2612 {
2613 struct si_shader_context *ctx = si_shader_context(bld_base);
2614 struct gallivm_state *gallivm = bld_base->base.gallivm;
2615 struct si_shader *shader = ctx->shader;
2616 unsigned tess_inner_index, tess_outer_index;
2617 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2618 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2619 unsigned stride, outer_comps, inner_comps, i;
2620 struct lp_build_if_state if_ctx, inner_if_ctx;
2621
2622 si_llvm_emit_barrier(NULL, bld_base, NULL);
2623
2624 /* Do this only for invocation 0, because the tess levels are per-patch,
2625 * not per-vertex.
2626 *
2627 * This can't jump, because invocation 0 executes this. It should
2628 * at least mask out the loads and stores for other invocations.
2629 */
2630 lp_build_if(&if_ctx, gallivm,
2631 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2632 invocation_id, bld_base->uint_bld.zero, ""));
2633
2634 /* Determine the layout of one tess factor element in the buffer. */
2635 switch (shader->key.part.tcs.epilog.prim_mode) {
2636 case PIPE_PRIM_LINES:
2637 stride = 2; /* 2 dwords, 1 vec2 store */
2638 outer_comps = 2;
2639 inner_comps = 0;
2640 break;
2641 case PIPE_PRIM_TRIANGLES:
2642 stride = 4; /* 4 dwords, 1 vec4 store */
2643 outer_comps = 3;
2644 inner_comps = 1;
2645 break;
2646 case PIPE_PRIM_QUADS:
2647 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2648 outer_comps = 4;
2649 inner_comps = 2;
2650 break;
2651 default:
2652 assert(0);
2653 return;
2654 }
2655
2656 /* Load tess_inner and tess_outer from LDS.
2657 * Any invocation can write them, so we can't get them from a temporary.
2658 */
2659 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2660 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2661
2662 lds_base = tcs_out_current_patch_data_offset;
2663 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2664 lp_build_const_int32(gallivm,
2665 tess_inner_index * 4), "");
2666 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2667 lp_build_const_int32(gallivm,
2668 tess_outer_index * 4), "");
2669
2670 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2671 /* For isolines, the hardware expects tess factors in the
2672 * reverse order from what GLSL / TGSI specify.
2673 */
2674 out[0] = lds_load(bld_base, TGSI_TYPE_SIGNED, 1, lds_outer);
2675 out[1] = lds_load(bld_base, TGSI_TYPE_SIGNED, 0, lds_outer);
2676 } else {
2677 for (i = 0; i < outer_comps; i++)
2678 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2679 for (i = 0; i < inner_comps; i++)
2680 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2681 }
2682
2683 /* Convert the outputs to vectors for stores. */
2684 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2685 vec1 = NULL;
2686
2687 if (stride > 4)
2688 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2689
2690 /* Get the buffer. */
2691 rw_buffers = LLVMGetParam(ctx->main_fn,
2692 SI_PARAM_RW_BUFFERS);
2693 buffer = build_indexed_load_const(ctx, rw_buffers,
2694 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2695
2696 /* Get the offset. */
2697 tf_base = LLVMGetParam(ctx->main_fn,
2698 SI_PARAM_TESS_FACTOR_OFFSET);
2699 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2700 lp_build_const_int32(gallivm, 4 * stride), "");
2701
2702 lp_build_if(&inner_if_ctx, gallivm,
2703 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2704 rel_patch_id, bld_base->uint_bld.zero, ""));
2705
2706 /* Store the dynamic HS control word. */
2707 build_tbuffer_store_dwords(ctx, buffer,
2708 lp_build_const_int32(gallivm, 0x80000000),
2709 1, lp_build_const_int32(gallivm, 0), tf_base, 0);
2710
2711 lp_build_endif(&inner_if_ctx);
2712
2713 /* Store the tessellation factors. */
2714 build_tbuffer_store_dwords(ctx, buffer, vec0,
2715 MIN2(stride, 4), byteoffset, tf_base, 4);
2716 if (vec1)
2717 build_tbuffer_store_dwords(ctx, buffer, vec1,
2718 stride - 4, byteoffset, tf_base, 20);
2719 lp_build_endif(&if_ctx);
2720 }
2721
2722 /* This only writes the tessellation factor levels. */
2723 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2724 {
2725 struct si_shader_context *ctx = si_shader_context(bld_base);
2726 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2727
2728 si_copy_tcs_inputs(bld_base);
2729
2730 rel_patch_id = get_rel_patch_id(ctx);
2731 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2732 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2733
2734 /* Return epilog parameters from this function. */
2735 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2736 LLVMValueRef ret = ctx->return_value;
2737 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2738 unsigned vgpr;
2739
2740 /* RW_BUFFERS pointer */
2741 rw_buffers = LLVMGetParam(ctx->main_fn,
2742 SI_PARAM_RW_BUFFERS);
2743 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2744 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2745 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2746 bld_base->uint_bld.zero, "");
2747 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2748 bld_base->uint_bld.one, "");
2749 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2750 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2751
2752 /* Tess factor buffer soffset is after user SGPRs. */
2753 tf_soffset = LLVMGetParam(ctx->main_fn,
2754 SI_PARAM_TESS_FACTOR_OFFSET);
2755 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2756 SI_TCS_NUM_USER_SGPR + 1, "");
2757
2758 /* VGPRs */
2759 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2760 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2761 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2762
2763 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2764 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2765 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2766 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2767 ctx->return_value = ret;
2768 }
2769
2770 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2771 {
2772 struct si_shader_context *ctx = si_shader_context(bld_base);
2773 struct si_shader *shader = ctx->shader;
2774 struct tgsi_shader_info *info = &shader->selector->info;
2775 struct gallivm_state *gallivm = bld_base->base.gallivm;
2776 unsigned i, chan;
2777 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
2778 ctx->param_rel_auto_id);
2779 LLVMValueRef vertex_dw_stride =
2780 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2781 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2782 vertex_dw_stride, "");
2783
2784 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2785 * its inputs from it. */
2786 for (i = 0; i < info->num_outputs; i++) {
2787 LLVMValueRef *out_ptr = ctx->soa.outputs[i];
2788 unsigned name = info->output_semantic_name[i];
2789 unsigned index = info->output_semantic_index[i];
2790 int param = si_shader_io_get_unique_index(name, index);
2791 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2792 lp_build_const_int32(gallivm, param * 4), "");
2793
2794 for (chan = 0; chan < 4; chan++) {
2795 lds_store(bld_base, chan, dw_addr,
2796 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2797 }
2798 }
2799 }
2800
2801 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2802 {
2803 struct si_shader_context *ctx = si_shader_context(bld_base);
2804 struct gallivm_state *gallivm = bld_base->base.gallivm;
2805 struct si_shader *es = ctx->shader;
2806 struct tgsi_shader_info *info = &es->selector->info;
2807 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
2808 ctx->param_es2gs_offset);
2809 unsigned chan;
2810 int i;
2811
2812 for (i = 0; i < info->num_outputs; i++) {
2813 LLVMValueRef *out_ptr =
2814 ctx->soa.outputs[i];
2815 int param_index;
2816
2817 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2818 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2819 continue;
2820
2821 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2822 info->output_semantic_index[i]);
2823
2824 for (chan = 0; chan < 4; chan++) {
2825 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2826 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2827
2828 build_tbuffer_store(ctx,
2829 ctx->esgs_ring,
2830 out_val, 1,
2831 LLVMGetUndef(ctx->i32), soffset,
2832 (4 * param_index + chan) * 4,
2833 V_008F0C_BUF_DATA_FORMAT_32,
2834 V_008F0C_BUF_NUM_FORMAT_UINT,
2835 0, 0, 1, 1, 0);
2836 }
2837 }
2838 }
2839
2840 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2841 {
2842 struct si_shader_context *ctx = si_shader_context(bld_base);
2843 struct gallivm_state *gallivm = bld_base->base.gallivm;
2844 LLVMValueRef args[2];
2845
2846 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2847 args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID);
2848 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2849 ctx->voidt, args, 2, 0);
2850 }
2851
2852 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2853 {
2854 struct si_shader_context *ctx = si_shader_context(bld_base);
2855 struct gallivm_state *gallivm = bld_base->base.gallivm;
2856 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2857 struct si_shader_output_values *outputs = NULL;
2858 int i,j;
2859
2860 assert(!ctx->shader->is_gs_copy_shader);
2861
2862 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2863
2864 /* Vertex color clamping.
2865 *
2866 * This uses a state constant loaded in a user data SGPR and
2867 * an IF statement is added that clamps all colors if the constant
2868 * is true.
2869 */
2870 if (ctx->type == PIPE_SHADER_VERTEX) {
2871 struct lp_build_if_state if_ctx;
2872 LLVMValueRef cond = NULL;
2873 LLVMValueRef addr, val;
2874
2875 for (i = 0; i < info->num_outputs; i++) {
2876 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2877 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2878 continue;
2879
2880 /* We've found a color. */
2881 if (!cond) {
2882 /* The state is in the first bit of the user SGPR. */
2883 cond = LLVMGetParam(ctx->main_fn,
2884 SI_PARAM_VS_STATE_BITS);
2885 cond = LLVMBuildTrunc(gallivm->builder, cond,
2886 ctx->i1, "");
2887 lp_build_if(&if_ctx, gallivm, cond);
2888 }
2889
2890 for (j = 0; j < 4; j++) {
2891 addr = ctx->soa.outputs[i][j];
2892 val = LLVMBuildLoad(gallivm->builder, addr, "");
2893 val = si_llvm_saturate(bld_base, val);
2894 LLVMBuildStore(gallivm->builder, val, addr);
2895 }
2896 }
2897
2898 if (cond)
2899 lp_build_endif(&if_ctx);
2900 }
2901
2902 for (i = 0; i < info->num_outputs; i++) {
2903 outputs[i].semantic_name = info->output_semantic_name[i];
2904 outputs[i].semantic_index = info->output_semantic_index[i];
2905
2906 for (j = 0; j < 4; j++) {
2907 outputs[i].values[j] =
2908 LLVMBuildLoad(gallivm->builder,
2909 ctx->soa.outputs[i][j],
2910 "");
2911 outputs[i].vertex_stream[j] =
2912 (info->output_streams[i] >> (2 * j)) & 3;
2913 }
2914
2915 }
2916
2917 /* Return the primitive ID from the LLVM function. */
2918 ctx->return_value =
2919 LLVMBuildInsertValue(gallivm->builder,
2920 ctx->return_value,
2921 bitcast(bld_base, TGSI_TYPE_FLOAT,
2922 get_primitive_id(bld_base, 0)),
2923 VS_EPILOG_PRIMID_LOC, "");
2924
2925 if (ctx->shader->selector->so.num_outputs)
2926 si_llvm_emit_streamout(ctx, outputs, i);
2927 si_llvm_export_vs(bld_base, outputs, i);
2928 FREE(outputs);
2929 }
2930
2931 struct si_ps_exports {
2932 unsigned num;
2933 LLVMValueRef args[10][9];
2934 };
2935
2936 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
2937 bool writes_samplemask)
2938 {
2939 if (writes_z) {
2940 /* Z needs 32 bits. */
2941 if (writes_samplemask)
2942 return V_028710_SPI_SHADER_32_ABGR;
2943 else if (writes_stencil)
2944 return V_028710_SPI_SHADER_32_GR;
2945 else
2946 return V_028710_SPI_SHADER_32_R;
2947 } else if (writes_stencil || writes_samplemask) {
2948 /* Both stencil and sample mask need only 16 bits. */
2949 return V_028710_SPI_SHADER_UINT16_ABGR;
2950 } else {
2951 return V_028710_SPI_SHADER_ZERO;
2952 }
2953 }
2954
2955 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2956 LLVMValueRef depth, LLVMValueRef stencil,
2957 LLVMValueRef samplemask, struct si_ps_exports *exp)
2958 {
2959 struct si_shader_context *ctx = si_shader_context(bld_base);
2960 struct lp_build_context *base = &bld_base->base;
2961 struct lp_build_context *uint = &bld_base->uint_bld;
2962 LLVMValueRef args[9];
2963 unsigned mask = 0;
2964 unsigned format = si_get_spi_shader_z_format(depth != NULL,
2965 stencil != NULL,
2966 samplemask != NULL);
2967
2968 assert(depth || stencil || samplemask);
2969
2970 args[1] = uint->one; /* whether the EXEC mask is valid */
2971 args[2] = uint->one; /* DONE bit */
2972
2973 /* Specify the target we are exporting */
2974 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2975
2976 args[4] = uint->zero; /* COMP flag */
2977 args[5] = base->undef; /* R, depth */
2978 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2979 args[7] = base->undef; /* B, sample mask */
2980 args[8] = base->undef; /* A, alpha to mask */
2981
2982 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
2983 assert(!depth);
2984 args[4] = uint->one; /* COMPR flag */
2985
2986 if (stencil) {
2987 /* Stencil should be in X[23:16]. */
2988 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
2989 stencil = LLVMBuildShl(base->gallivm->builder, stencil,
2990 LLVMConstInt(ctx->i32, 16, 0), "");
2991 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
2992 mask |= 0x3;
2993 }
2994 if (samplemask) {
2995 /* SampleMask should be in Y[15:0]. */
2996 args[6] = samplemask;
2997 mask |= 0xc;
2998 }
2999 } else {
3000 if (depth) {
3001 args[5] = depth;
3002 mask |= 0x1;
3003 }
3004 if (stencil) {
3005 args[6] = stencil;
3006 mask |= 0x2;
3007 }
3008 if (samplemask) {
3009 args[7] = samplemask;
3010 mask |= 0x4;
3011 }
3012 }
3013
3014 /* SI (except OLAND and HAINAN) has a bug that it only looks
3015 * at the X writemask component. */
3016 if (ctx->screen->b.chip_class == SI &&
3017 ctx->screen->b.family != CHIP_OLAND &&
3018 ctx->screen->b.family != CHIP_HAINAN)
3019 mask |= 0x1;
3020
3021 /* Specify which components to enable */
3022 args[0] = lp_build_const_int32(base->gallivm, mask);
3023
3024 memcpy(exp->args[exp->num++], args, sizeof(args));
3025 }
3026
3027 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3028 LLVMValueRef *color, unsigned index,
3029 unsigned samplemask_param,
3030 bool is_last, struct si_ps_exports *exp)
3031 {
3032 struct si_shader_context *ctx = si_shader_context(bld_base);
3033 struct lp_build_context *base = &bld_base->base;
3034 int i;
3035
3036 /* Clamp color */
3037 if (ctx->shader->key.part.ps.epilog.clamp_color)
3038 for (i = 0; i < 4; i++)
3039 color[i] = si_llvm_saturate(bld_base, color[i]);
3040
3041 /* Alpha to one */
3042 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3043 color[3] = base->one;
3044
3045 /* Alpha test */
3046 if (index == 0 &&
3047 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3048 si_alpha_test(bld_base, color[3]);
3049
3050 /* Line & polygon smoothing */
3051 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3052 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3053 samplemask_param);
3054
3055 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3056 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3057 LLVMValueRef args[8][9];
3058 int c, last = -1;
3059
3060 /* Get the export arguments, also find out what the last one is. */
3061 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3062 si_llvm_init_export_args(bld_base, color,
3063 V_008DFC_SQ_EXP_MRT + c, args[c]);
3064 if (args[c][0] != bld_base->uint_bld.zero)
3065 last = c;
3066 }
3067
3068 /* Emit all exports. */
3069 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3070 if (is_last && last == c) {
3071 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3072 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
3073 } else if (args[c][0] == bld_base->uint_bld.zero)
3074 continue; /* unnecessary NULL export */
3075
3076 memcpy(exp->args[exp->num++], args[c], sizeof(args[c]));
3077 }
3078 } else {
3079 LLVMValueRef args[9];
3080
3081 /* Export */
3082 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
3083 args);
3084 if (is_last) {
3085 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3086 args[2] = bld_base->uint_bld.one; /* DONE bit */
3087 } else if (args[0] == bld_base->uint_bld.zero)
3088 return; /* unnecessary NULL export */
3089
3090 memcpy(exp->args[exp->num++], args, sizeof(args));
3091 }
3092 }
3093
3094 static void si_emit_ps_exports(struct si_shader_context *ctx,
3095 struct si_ps_exports *exp)
3096 {
3097 for (unsigned i = 0; i < exp->num; i++)
3098 lp_build_intrinsic(ctx->gallivm.builder,
3099 "llvm.SI.export", ctx->voidt,
3100 exp->args[i], 9, 0);
3101 }
3102
3103 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3104 {
3105 struct si_shader_context *ctx = si_shader_context(bld_base);
3106 struct lp_build_context *base = &bld_base->base;
3107 struct lp_build_context *uint = &bld_base->uint_bld;
3108 LLVMValueRef args[9];
3109
3110 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
3111 args[1] = uint->one; /* whether the EXEC mask is valid */
3112 args[2] = uint->one; /* DONE bit */
3113 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
3114 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
3115 args[5] = base->undef; /* R */
3116 args[6] = base->undef; /* G */
3117 args[7] = base->undef; /* B */
3118 args[8] = base->undef; /* A */
3119
3120 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
3121 ctx->voidt, args, 9, 0);
3122 }
3123
3124 /**
3125 * Return PS outputs in this order:
3126 *
3127 * v[0:3] = color0.xyzw
3128 * v[4:7] = color1.xyzw
3129 * ...
3130 * vN+0 = Depth
3131 * vN+1 = Stencil
3132 * vN+2 = SampleMask
3133 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3134 *
3135 * The alpha-ref SGPR is returned via its original location.
3136 */
3137 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
3138 {
3139 struct si_shader_context *ctx = si_shader_context(bld_base);
3140 struct si_shader *shader = ctx->shader;
3141 struct lp_build_context *base = &bld_base->base;
3142 struct tgsi_shader_info *info = &shader->selector->info;
3143 LLVMBuilderRef builder = base->gallivm->builder;
3144 unsigned i, j, first_vgpr, vgpr;
3145
3146 LLVMValueRef color[8][4] = {};
3147 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3148 LLVMValueRef ret;
3149
3150 /* Read the output values. */
3151 for (i = 0; i < info->num_outputs; i++) {
3152 unsigned semantic_name = info->output_semantic_name[i];
3153 unsigned semantic_index = info->output_semantic_index[i];
3154
3155 switch (semantic_name) {
3156 case TGSI_SEMANTIC_COLOR:
3157 assert(semantic_index < 8);
3158 for (j = 0; j < 4; j++) {
3159 LLVMValueRef ptr = ctx->soa.outputs[i][j];
3160 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3161 color[semantic_index][j] = result;
3162 }
3163 break;
3164 case TGSI_SEMANTIC_POSITION:
3165 depth = LLVMBuildLoad(builder,
3166 ctx->soa.outputs[i][2], "");
3167 break;
3168 case TGSI_SEMANTIC_STENCIL:
3169 stencil = LLVMBuildLoad(builder,
3170 ctx->soa.outputs[i][1], "");
3171 break;
3172 case TGSI_SEMANTIC_SAMPLEMASK:
3173 samplemask = LLVMBuildLoad(builder,
3174 ctx->soa.outputs[i][0], "");
3175 break;
3176 default:
3177 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3178 semantic_name);
3179 }
3180 }
3181
3182 /* Fill the return structure. */
3183 ret = ctx->return_value;
3184
3185 /* Set SGPRs. */
3186 ret = LLVMBuildInsertValue(builder, ret,
3187 bitcast(bld_base, TGSI_TYPE_SIGNED,
3188 LLVMGetParam(ctx->main_fn,
3189 SI_PARAM_ALPHA_REF)),
3190 SI_SGPR_ALPHA_REF, "");
3191
3192 /* Set VGPRs */
3193 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3194 for (i = 0; i < ARRAY_SIZE(color); i++) {
3195 if (!color[i][0])
3196 continue;
3197
3198 for (j = 0; j < 4; j++)
3199 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3200 }
3201 if (depth)
3202 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3203 if (stencil)
3204 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3205 if (samplemask)
3206 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3207
3208 /* Add the input sample mask for smoothing at the end. */
3209 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3210 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3211 ret = LLVMBuildInsertValue(builder, ret,
3212 LLVMGetParam(ctx->main_fn,
3213 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3214
3215 ctx->return_value = ret;
3216 }
3217
3218 /**
3219 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3220 * buffer in number of elements and return it as an i32.
3221 */
3222 static LLVMValueRef get_buffer_size(
3223 struct lp_build_tgsi_context *bld_base,
3224 LLVMValueRef descriptor)
3225 {
3226 struct si_shader_context *ctx = si_shader_context(bld_base);
3227 struct gallivm_state *gallivm = bld_base->base.gallivm;
3228 LLVMBuilderRef builder = gallivm->builder;
3229 LLVMValueRef size =
3230 LLVMBuildExtractElement(builder, descriptor,
3231 lp_build_const_int32(gallivm, 2), "");
3232
3233 if (ctx->screen->b.chip_class >= VI) {
3234 /* On VI, the descriptor contains the size in bytes,
3235 * but TXQ must return the size in elements.
3236 * The stride is always non-zero for resources using TXQ.
3237 */
3238 LLVMValueRef stride =
3239 LLVMBuildExtractElement(builder, descriptor,
3240 lp_build_const_int32(gallivm, 1), "");
3241 stride = LLVMBuildLShr(builder, stride,
3242 lp_build_const_int32(gallivm, 16), "");
3243 stride = LLVMBuildAnd(builder, stride,
3244 lp_build_const_int32(gallivm, 0x3FFF), "");
3245
3246 size = LLVMBuildUDiv(builder, size, stride, "");
3247 }
3248
3249 return size;
3250 }
3251
3252 /**
3253 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
3254 * intrinsic names).
3255 */
3256 static void build_type_name_for_intr(
3257 LLVMTypeRef type,
3258 char *buf, unsigned bufsize)
3259 {
3260 LLVMTypeRef elem_type = type;
3261
3262 assert(bufsize >= 8);
3263
3264 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
3265 int ret = snprintf(buf, bufsize, "v%u",
3266 LLVMGetVectorSize(type));
3267 if (ret < 0) {
3268 char *type_name = LLVMPrintTypeToString(type);
3269 fprintf(stderr, "Error building type name for: %s\n",
3270 type_name);
3271 return;
3272 }
3273 elem_type = LLVMGetElementType(type);
3274 buf += ret;
3275 bufsize -= ret;
3276 }
3277 switch (LLVMGetTypeKind(elem_type)) {
3278 default: break;
3279 case LLVMIntegerTypeKind:
3280 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
3281 break;
3282 case LLVMFloatTypeKind:
3283 snprintf(buf, bufsize, "f32");
3284 break;
3285 case LLVMDoubleTypeKind:
3286 snprintf(buf, bufsize, "f64");
3287 break;
3288 }
3289 }
3290
3291 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3292 struct lp_build_tgsi_context *bld_base,
3293 struct lp_build_emit_data *emit_data);
3294
3295 /* Prevent optimizations (at least of memory accesses) across the current
3296 * point in the program by emitting empty inline assembly that is marked as
3297 * having side effects.
3298 */
3299 #if 0 /* unused currently */
3300 static void emit_optimization_barrier(struct si_shader_context *ctx)
3301 {
3302 LLVMBuilderRef builder = ctx->gallivm.builder;
3303 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3304 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
3305 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3306 }
3307 #endif
3308
3309 /* Combine these with & instead of |. */
3310 #define NOOP_WAITCNT 0xf7f
3311 #define LGKM_CNT 0x07f
3312 #define VM_CNT 0xf70
3313
3314 static void emit_waitcnt(struct si_shader_context *ctx, unsigned simm16)
3315 {
3316 struct gallivm_state *gallivm = &ctx->gallivm;
3317 LLVMBuilderRef builder = gallivm->builder;
3318 LLVMValueRef args[1] = {
3319 lp_build_const_int32(gallivm, simm16)
3320 };
3321 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3322 ctx->voidt, args, 1, 0);
3323 }
3324
3325 static void membar_emit(
3326 const struct lp_build_tgsi_action *action,
3327 struct lp_build_tgsi_context *bld_base,
3328 struct lp_build_emit_data *emit_data)
3329 {
3330 struct si_shader_context *ctx = si_shader_context(bld_base);
3331 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3332 unsigned flags = LLVMConstIntGetZExtValue(src0);
3333 unsigned waitcnt = NOOP_WAITCNT;
3334
3335 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3336 waitcnt &= VM_CNT & LGKM_CNT;
3337
3338 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3339 TGSI_MEMBAR_SHADER_BUFFER |
3340 TGSI_MEMBAR_SHADER_IMAGE))
3341 waitcnt &= VM_CNT;
3342
3343 if (flags & TGSI_MEMBAR_SHARED)
3344 waitcnt &= LGKM_CNT;
3345
3346 if (waitcnt != NOOP_WAITCNT)
3347 emit_waitcnt(ctx, waitcnt);
3348 }
3349
3350 static LLVMValueRef
3351 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3352 const struct tgsi_full_src_register *reg)
3353 {
3354 LLVMValueRef index;
3355 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3356 SI_PARAM_SHADER_BUFFERS);
3357
3358 if (!reg->Register.Indirect)
3359 index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
3360 else
3361 index = get_bounded_indirect_index(ctx, &reg->Indirect,
3362 reg->Register.Index,
3363 SI_NUM_SHADER_BUFFERS);
3364
3365 return build_indexed_load_const(ctx, rsrc_ptr, index);
3366 }
3367
3368 static bool tgsi_is_array_sampler(unsigned target)
3369 {
3370 return target == TGSI_TEXTURE_1D_ARRAY ||
3371 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3372 target == TGSI_TEXTURE_2D_ARRAY ||
3373 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3374 target == TGSI_TEXTURE_CUBE_ARRAY ||
3375 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3376 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3377 }
3378
3379 static bool tgsi_is_array_image(unsigned target)
3380 {
3381 return target == TGSI_TEXTURE_3D ||
3382 target == TGSI_TEXTURE_CUBE ||
3383 target == TGSI_TEXTURE_1D_ARRAY ||
3384 target == TGSI_TEXTURE_2D_ARRAY ||
3385 target == TGSI_TEXTURE_CUBE_ARRAY ||
3386 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3387 }
3388
3389 /**
3390 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3391 *
3392 * At least on Tonga, executing image stores on images with DCC enabled and
3393 * non-trivial can eventually lead to lockups. This can occur when an
3394 * application binds an image as read-only but then uses a shader that writes
3395 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3396 * program termination) in this case, but it doesn't cost much to be a bit
3397 * nicer: disabling DCC in the shader still leads to undefined results but
3398 * avoids the lockup.
3399 */
3400 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3401 LLVMValueRef rsrc)
3402 {
3403 if (ctx->screen->b.chip_class <= CIK) {
3404 return rsrc;
3405 } else {
3406 LLVMBuilderRef builder = ctx->gallivm.builder;
3407 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3408 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3409 LLVMValueRef tmp;
3410
3411 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3412 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3413 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3414 }
3415 }
3416
3417 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3418 {
3419 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3420 CONST_ADDR_SPACE);
3421 }
3422
3423 /**
3424 * Load the resource descriptor for \p image.
3425 */
3426 static void
3427 image_fetch_rsrc(
3428 struct lp_build_tgsi_context *bld_base,
3429 const struct tgsi_full_src_register *image,
3430 bool is_store, unsigned target,
3431 LLVMValueRef *rsrc)
3432 {
3433 struct si_shader_context *ctx = si_shader_context(bld_base);
3434 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3435 SI_PARAM_IMAGES);
3436 LLVMValueRef index, tmp;
3437 bool dcc_off = target != TGSI_TEXTURE_BUFFER && is_store;
3438
3439 assert(image->Register.File == TGSI_FILE_IMAGE);
3440
3441 if (!image->Register.Indirect) {
3442 const struct tgsi_shader_info *info = bld_base->info;
3443
3444 index = LLVMConstInt(ctx->i32, image->Register.Index, 0);
3445
3446 if (info->images_writemask & (1 << image->Register.Index) &&
3447 target != TGSI_TEXTURE_BUFFER)
3448 dcc_off = true;
3449 } else {
3450 /* From the GL_ARB_shader_image_load_store extension spec:
3451 *
3452 * If a shader performs an image load, store, or atomic
3453 * operation using an image variable declared as an array,
3454 * and if the index used to select an individual element is
3455 * negative or greater than or equal to the size of the
3456 * array, the results of the operation are undefined but may
3457 * not lead to termination.
3458 */
3459 index = get_bounded_indirect_index(ctx, &image->Indirect,
3460 image->Register.Index,
3461 SI_NUM_IMAGES);
3462 }
3463
3464 if (target == TGSI_TEXTURE_BUFFER) {
3465 LLVMBuilderRef builder = ctx->gallivm.builder;
3466
3467 rsrc_ptr = LLVMBuildPointerCast(builder, rsrc_ptr,
3468 const_array(ctx->v4i32, 0), "");
3469 index = LLVMBuildMul(builder, index,
3470 LLVMConstInt(ctx->i32, 2, 0), "");
3471 index = LLVMBuildAdd(builder, index,
3472 LLVMConstInt(ctx->i32, 1, 0), "");
3473 *rsrc = build_indexed_load_const(ctx, rsrc_ptr, index);
3474 return;
3475 }
3476
3477 tmp = build_indexed_load_const(ctx, rsrc_ptr, index);
3478 if (dcc_off)
3479 tmp = force_dcc_off(ctx, tmp);
3480 *rsrc = tmp;
3481 }
3482
3483 static LLVMValueRef image_fetch_coords(
3484 struct lp_build_tgsi_context *bld_base,
3485 const struct tgsi_full_instruction *inst,
3486 unsigned src)
3487 {
3488 struct gallivm_state *gallivm = bld_base->base.gallivm;
3489 LLVMBuilderRef builder = gallivm->builder;
3490 unsigned target = inst->Memory.Texture;
3491 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3492 LLVMValueRef coords[4];
3493 LLVMValueRef tmp;
3494 int chan;
3495
3496 for (chan = 0; chan < num_coords; ++chan) {
3497 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3498 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3499 coords[chan] = tmp;
3500 }
3501
3502 if (num_coords == 1)
3503 return coords[0];
3504
3505 if (num_coords == 3) {
3506 /* LLVM has difficulties lowering 3-element vectors. */
3507 coords[3] = bld_base->uint_bld.undef;
3508 num_coords = 4;
3509 }
3510
3511 return lp_build_gather_values(gallivm, coords, num_coords);
3512 }
3513
3514 /**
3515 * Append the extra mode bits that are used by image load and store.
3516 */
3517 static void image_append_args(
3518 struct si_shader_context *ctx,
3519 struct lp_build_emit_data * emit_data,
3520 unsigned target,
3521 bool atomic,
3522 bool force_glc)
3523 {
3524 const struct tgsi_full_instruction *inst = emit_data->inst;
3525 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3526 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3527 LLVMValueRef r128 = i1false;
3528 LLVMValueRef da = tgsi_is_array_image(target) ? i1true : i1false;
3529 LLVMValueRef glc =
3530 force_glc ||
3531 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3532 i1true : i1false;
3533 LLVMValueRef slc = i1false;
3534 LLVMValueRef lwe = i1false;
3535
3536 if (atomic || (HAVE_LLVM <= 0x0309)) {
3537 emit_data->args[emit_data->arg_count++] = r128;
3538 emit_data->args[emit_data->arg_count++] = da;
3539 if (!atomic) {
3540 emit_data->args[emit_data->arg_count++] = glc;
3541 }
3542 emit_data->args[emit_data->arg_count++] = slc;
3543 return;
3544 }
3545
3546 /* HAVE_LLVM >= 0x0400 */
3547 emit_data->args[emit_data->arg_count++] = glc;
3548 emit_data->args[emit_data->arg_count++] = slc;
3549 emit_data->args[emit_data->arg_count++] = lwe;
3550 emit_data->args[emit_data->arg_count++] = da;
3551 }
3552
3553 /**
3554 * Append the resource and indexing arguments for buffer intrinsics.
3555 *
3556 * \param rsrc the v4i32 buffer resource
3557 * \param index index into the buffer (stride-based)
3558 * \param offset byte offset into the buffer
3559 */
3560 static void buffer_append_args(
3561 struct si_shader_context *ctx,
3562 struct lp_build_emit_data *emit_data,
3563 LLVMValueRef rsrc,
3564 LLVMValueRef index,
3565 LLVMValueRef offset,
3566 bool atomic,
3567 bool force_glc)
3568 {
3569 const struct tgsi_full_instruction *inst = emit_data->inst;
3570 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3571 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3572
3573 emit_data->args[emit_data->arg_count++] = rsrc;
3574 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3575 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3576 if (!atomic) {
3577 emit_data->args[emit_data->arg_count++] =
3578 force_glc ||
3579 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3580 i1true : i1false; /* glc */
3581 }
3582 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3583 }
3584
3585 static void load_fetch_args(
3586 struct lp_build_tgsi_context * bld_base,
3587 struct lp_build_emit_data * emit_data)
3588 {
3589 struct si_shader_context *ctx = si_shader_context(bld_base);
3590 struct gallivm_state *gallivm = bld_base->base.gallivm;
3591 const struct tgsi_full_instruction * inst = emit_data->inst;
3592 unsigned target = inst->Memory.Texture;
3593 LLVMValueRef rsrc;
3594
3595 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3596
3597 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3598 LLVMBuilderRef builder = gallivm->builder;
3599 LLVMValueRef offset;
3600 LLVMValueRef tmp;
3601
3602 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3603
3604 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3605 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3606
3607 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3608 offset, false, false);
3609 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3610 LLVMValueRef coords;
3611
3612 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
3613 coords = image_fetch_coords(bld_base, inst, 1);
3614
3615 if (target == TGSI_TEXTURE_BUFFER) {
3616 buffer_append_args(ctx, emit_data, rsrc, coords,
3617 bld_base->uint_bld.zero, false, false);
3618 } else {
3619 emit_data->args[0] = coords;
3620 emit_data->args[1] = rsrc;
3621 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3622 emit_data->arg_count = 3;
3623
3624 image_append_args(ctx, emit_data, target, false, false);
3625 }
3626 }
3627 }
3628
3629 static void load_emit_buffer(struct si_shader_context *ctx,
3630 struct lp_build_emit_data *emit_data)
3631 {
3632 const struct tgsi_full_instruction *inst = emit_data->inst;
3633 struct gallivm_state *gallivm = &ctx->gallivm;
3634 LLVMBuilderRef builder = gallivm->builder;
3635 uint writemask = inst->Dst[0].Register.WriteMask;
3636 uint count = util_last_bit(writemask);
3637 const char *intrinsic_name;
3638 LLVMTypeRef dst_type;
3639
3640 switch (count) {
3641 case 1:
3642 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3643 dst_type = ctx->f32;
3644 break;
3645 case 2:
3646 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3647 dst_type = LLVMVectorType(ctx->f32, 2);
3648 break;
3649 default: // 3 & 4
3650 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3651 dst_type = ctx->v4f32;
3652 count = 4;
3653 }
3654
3655 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3656 builder, intrinsic_name, dst_type,
3657 emit_data->args, emit_data->arg_count,
3658 LP_FUNC_ATTR_READONLY);
3659 }
3660
3661 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3662 const struct tgsi_full_instruction *inst,
3663 LLVMTypeRef type, int arg)
3664 {
3665 struct gallivm_state *gallivm = &ctx->gallivm;
3666 LLVMBuilderRef builder = gallivm->builder;
3667 LLVMValueRef offset, ptr;
3668 int addr_space;
3669
3670 offset = lp_build_emit_fetch(&ctx->soa.bld_base, inst, arg, 0);
3671 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3672
3673 ptr = ctx->shared_memory;
3674 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3675 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3676 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3677
3678 return ptr;
3679 }
3680
3681 static void load_emit_memory(
3682 struct si_shader_context *ctx,
3683 struct lp_build_emit_data *emit_data)
3684 {
3685 const struct tgsi_full_instruction *inst = emit_data->inst;
3686 struct lp_build_context *base = &ctx->soa.bld_base.base;
3687 struct gallivm_state *gallivm = &ctx->gallivm;
3688 LLVMBuilderRef builder = gallivm->builder;
3689 unsigned writemask = inst->Dst[0].Register.WriteMask;
3690 LLVMValueRef channels[4], ptr, derived_ptr, index;
3691 int chan;
3692
3693 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3694
3695 for (chan = 0; chan < 4; ++chan) {
3696 if (!(writemask & (1 << chan))) {
3697 channels[chan] = LLVMGetUndef(base->elem_type);
3698 continue;
3699 }
3700
3701 index = lp_build_const_int32(gallivm, chan);
3702 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3703 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3704 }
3705 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3706 }
3707
3708 static void get_image_intr_name(const char *base_name,
3709 LLVMTypeRef data_type,
3710 LLVMTypeRef coords_type,
3711 LLVMTypeRef rsrc_type,
3712 char *out_name, unsigned out_len)
3713 {
3714 char coords_type_name[8];
3715
3716 build_type_name_for_intr(coords_type, coords_type_name,
3717 sizeof(coords_type_name));
3718
3719 if (HAVE_LLVM <= 0x0309) {
3720 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
3721 } else {
3722 char data_type_name[8];
3723 char rsrc_type_name[8];
3724
3725 build_type_name_for_intr(data_type, data_type_name,
3726 sizeof(data_type_name));
3727 build_type_name_for_intr(rsrc_type, rsrc_type_name,
3728 sizeof(rsrc_type_name));
3729 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
3730 data_type_name, coords_type_name, rsrc_type_name);
3731 }
3732 }
3733
3734 static void load_emit(
3735 const struct lp_build_tgsi_action *action,
3736 struct lp_build_tgsi_context *bld_base,
3737 struct lp_build_emit_data *emit_data)
3738 {
3739 struct si_shader_context *ctx = si_shader_context(bld_base);
3740 struct gallivm_state *gallivm = bld_base->base.gallivm;
3741 LLVMBuilderRef builder = gallivm->builder;
3742 const struct tgsi_full_instruction * inst = emit_data->inst;
3743 char intrinsic_name[64];
3744
3745 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3746 load_emit_memory(ctx, emit_data);
3747 return;
3748 }
3749
3750 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3751 emit_waitcnt(ctx, VM_CNT);
3752
3753 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3754 load_emit_buffer(ctx, emit_data);
3755 return;
3756 }
3757
3758 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3759 emit_data->output[emit_data->chan] =
3760 lp_build_intrinsic(
3761 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3762 emit_data->args, emit_data->arg_count,
3763 LP_FUNC_ATTR_READONLY);
3764 } else {
3765 get_image_intr_name("llvm.amdgcn.image.load",
3766 emit_data->dst_type, /* vdata */
3767 LLVMTypeOf(emit_data->args[0]), /* coords */
3768 LLVMTypeOf(emit_data->args[1]), /* rsrc */
3769 intrinsic_name, sizeof(intrinsic_name));
3770
3771 emit_data->output[emit_data->chan] =
3772 lp_build_intrinsic(
3773 builder, intrinsic_name, emit_data->dst_type,
3774 emit_data->args, emit_data->arg_count,
3775 LP_FUNC_ATTR_READONLY);
3776 }
3777 }
3778
3779 static void store_fetch_args(
3780 struct lp_build_tgsi_context * bld_base,
3781 struct lp_build_emit_data * emit_data)
3782 {
3783 struct si_shader_context *ctx = si_shader_context(bld_base);
3784 struct gallivm_state *gallivm = bld_base->base.gallivm;
3785 LLVMBuilderRef builder = gallivm->builder;
3786 const struct tgsi_full_instruction * inst = emit_data->inst;
3787 struct tgsi_full_src_register memory;
3788 LLVMValueRef chans[4];
3789 LLVMValueRef data;
3790 LLVMValueRef rsrc;
3791 unsigned chan;
3792
3793 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3794
3795 for (chan = 0; chan < 4; ++chan) {
3796 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3797 }
3798 data = lp_build_gather_values(gallivm, chans, 4);
3799
3800 emit_data->args[emit_data->arg_count++] = data;
3801
3802 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3803
3804 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3805 LLVMValueRef offset;
3806 LLVMValueRef tmp;
3807
3808 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3809
3810 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3811 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3812
3813 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3814 offset, false, false);
3815 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3816 unsigned target = inst->Memory.Texture;
3817 LLVMValueRef coords;
3818
3819 /* 8bit/16bit TC L1 write corruption bug on SI.
3820 * All store opcodes not aligned to a dword are affected.
3821 *
3822 * The only way to get unaligned stores in radeonsi is through
3823 * shader images.
3824 */
3825 bool force_glc = ctx->screen->b.chip_class == SI;
3826
3827 coords = image_fetch_coords(bld_base, inst, 0);
3828
3829 if (target == TGSI_TEXTURE_BUFFER) {
3830 image_fetch_rsrc(bld_base, &memory, true, target, &rsrc);
3831 buffer_append_args(ctx, emit_data, rsrc, coords,
3832 bld_base->uint_bld.zero, false, force_glc);
3833 } else {
3834 emit_data->args[1] = coords;
3835 image_fetch_rsrc(bld_base, &memory, true, target,
3836 &emit_data->args[2]);
3837 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3838 emit_data->arg_count = 4;
3839
3840 image_append_args(ctx, emit_data, target, false, force_glc);
3841 }
3842 }
3843 }
3844
3845 static void store_emit_buffer(
3846 struct si_shader_context *ctx,
3847 struct lp_build_emit_data *emit_data)
3848 {
3849 const struct tgsi_full_instruction *inst = emit_data->inst;
3850 struct gallivm_state *gallivm = &ctx->gallivm;
3851 LLVMBuilderRef builder = gallivm->builder;
3852 struct lp_build_context *uint_bld = &ctx->soa.bld_base.uint_bld;
3853 LLVMValueRef base_data = emit_data->args[0];
3854 LLVMValueRef base_offset = emit_data->args[3];
3855 unsigned writemask = inst->Dst[0].Register.WriteMask;
3856
3857 while (writemask) {
3858 int start, count;
3859 const char *intrinsic_name;
3860 LLVMValueRef data;
3861 LLVMValueRef offset;
3862 LLVMValueRef tmp;
3863
3864 u_bit_scan_consecutive_range(&writemask, &start, &count);
3865
3866 /* Due to an LLVM limitation, split 3-element writes
3867 * into a 2-element and a 1-element write. */
3868 if (count == 3) {
3869 writemask |= 1 << (start + 2);
3870 count = 2;
3871 }
3872
3873 if (count == 4) {
3874 data = base_data;
3875 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3876 } else if (count == 2) {
3877 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3878
3879 tmp = LLVMBuildExtractElement(
3880 builder, base_data,
3881 lp_build_const_int32(gallivm, start), "");
3882 data = LLVMBuildInsertElement(
3883 builder, LLVMGetUndef(v2f32), tmp,
3884 uint_bld->zero, "");
3885
3886 tmp = LLVMBuildExtractElement(
3887 builder, base_data,
3888 lp_build_const_int32(gallivm, start + 1), "");
3889 data = LLVMBuildInsertElement(
3890 builder, data, tmp, uint_bld->one, "");
3891
3892 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3893 } else {
3894 assert(count == 1);
3895 data = LLVMBuildExtractElement(
3896 builder, base_data,
3897 lp_build_const_int32(gallivm, start), "");
3898 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3899 }
3900
3901 offset = base_offset;
3902 if (start != 0) {
3903 offset = LLVMBuildAdd(
3904 builder, offset,
3905 lp_build_const_int32(gallivm, start * 4), "");
3906 }
3907
3908 emit_data->args[0] = data;
3909 emit_data->args[3] = offset;
3910
3911 lp_build_intrinsic(
3912 builder, intrinsic_name, emit_data->dst_type,
3913 emit_data->args, emit_data->arg_count, 0);
3914 }
3915 }
3916
3917 static void store_emit_memory(
3918 struct si_shader_context *ctx,
3919 struct lp_build_emit_data *emit_data)
3920 {
3921 const struct tgsi_full_instruction *inst = emit_data->inst;
3922 struct gallivm_state *gallivm = &ctx->gallivm;
3923 struct lp_build_context *base = &ctx->soa.bld_base.base;
3924 LLVMBuilderRef builder = gallivm->builder;
3925 unsigned writemask = inst->Dst[0].Register.WriteMask;
3926 LLVMValueRef ptr, derived_ptr, data, index;
3927 int chan;
3928
3929 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3930
3931 for (chan = 0; chan < 4; ++chan) {
3932 if (!(writemask & (1 << chan))) {
3933 continue;
3934 }
3935 data = lp_build_emit_fetch(&ctx->soa.bld_base, inst, 1, chan);
3936 index = lp_build_const_int32(gallivm, chan);
3937 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3938 LLVMBuildStore(builder, data, derived_ptr);
3939 }
3940 }
3941
3942 static void store_emit(
3943 const struct lp_build_tgsi_action *action,
3944 struct lp_build_tgsi_context *bld_base,
3945 struct lp_build_emit_data *emit_data)
3946 {
3947 struct si_shader_context *ctx = si_shader_context(bld_base);
3948 struct gallivm_state *gallivm = bld_base->base.gallivm;
3949 LLVMBuilderRef builder = gallivm->builder;
3950 const struct tgsi_full_instruction * inst = emit_data->inst;
3951 unsigned target = inst->Memory.Texture;
3952 char intrinsic_name[64];
3953
3954 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3955 store_emit_memory(ctx, emit_data);
3956 return;
3957 }
3958
3959 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3960 emit_waitcnt(ctx, VM_CNT);
3961
3962 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3963 store_emit_buffer(ctx, emit_data);
3964 return;
3965 }
3966
3967 if (target == TGSI_TEXTURE_BUFFER) {
3968 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3969 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3970 emit_data->dst_type, emit_data->args,
3971 emit_data->arg_count, 0);
3972 } else {
3973 get_image_intr_name("llvm.amdgcn.image.store",
3974 LLVMTypeOf(emit_data->args[0]), /* vdata */
3975 LLVMTypeOf(emit_data->args[1]), /* coords */
3976 LLVMTypeOf(emit_data->args[2]), /* rsrc */
3977 intrinsic_name, sizeof(intrinsic_name));
3978
3979 emit_data->output[emit_data->chan] =
3980 lp_build_intrinsic(
3981 builder, intrinsic_name, emit_data->dst_type,
3982 emit_data->args, emit_data->arg_count, 0);
3983 }
3984 }
3985
3986 static void atomic_fetch_args(
3987 struct lp_build_tgsi_context * bld_base,
3988 struct lp_build_emit_data * emit_data)
3989 {
3990 struct si_shader_context *ctx = si_shader_context(bld_base);
3991 struct gallivm_state *gallivm = bld_base->base.gallivm;
3992 LLVMBuilderRef builder = gallivm->builder;
3993 const struct tgsi_full_instruction * inst = emit_data->inst;
3994 LLVMValueRef data1, data2;
3995 LLVMValueRef rsrc;
3996 LLVMValueRef tmp;
3997
3998 emit_data->dst_type = bld_base->base.elem_type;
3999
4000 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
4001 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
4002
4003 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4004 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
4005 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
4006 }
4007
4008 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
4009 * of arguments, which is reversed relative to TGSI (and GLSL)
4010 */
4011 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4012 emit_data->args[emit_data->arg_count++] = data2;
4013 emit_data->args[emit_data->arg_count++] = data1;
4014
4015 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4016 LLVMValueRef offset;
4017
4018 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
4019
4020 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
4021 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
4022
4023 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
4024 offset, true, false);
4025 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
4026 unsigned target = inst->Memory.Texture;
4027 LLVMValueRef coords;
4028
4029 image_fetch_rsrc(bld_base, &inst->Src[0], true, target, &rsrc);
4030 coords = image_fetch_coords(bld_base, inst, 1);
4031
4032 if (target == TGSI_TEXTURE_BUFFER) {
4033 buffer_append_args(ctx, emit_data, rsrc, coords,
4034 bld_base->uint_bld.zero, true, false);
4035 } else {
4036 emit_data->args[emit_data->arg_count++] = coords;
4037 emit_data->args[emit_data->arg_count++] = rsrc;
4038
4039 image_append_args(ctx, emit_data, target, true, false);
4040 }
4041 }
4042 }
4043
4044 static void atomic_emit_memory(struct si_shader_context *ctx,
4045 struct lp_build_emit_data *emit_data) {
4046 struct gallivm_state *gallivm = &ctx->gallivm;
4047 LLVMBuilderRef builder = gallivm->builder;
4048 const struct tgsi_full_instruction * inst = emit_data->inst;
4049 LLVMValueRef ptr, result, arg;
4050
4051 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
4052
4053 arg = lp_build_emit_fetch(&ctx->soa.bld_base, inst, 2, 0);
4054 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
4055
4056 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4057 LLVMValueRef new_data;
4058 new_data = lp_build_emit_fetch(&ctx->soa.bld_base,
4059 inst, 3, 0);
4060
4061 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
4062
4063 #if HAVE_LLVM >= 0x309
4064 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
4065 LLVMAtomicOrderingSequentiallyConsistent,
4066 LLVMAtomicOrderingSequentiallyConsistent,
4067 false);
4068 #endif
4069
4070 result = LLVMBuildExtractValue(builder, result, 0, "");
4071 } else {
4072 LLVMAtomicRMWBinOp op;
4073
4074 switch(inst->Instruction.Opcode) {
4075 case TGSI_OPCODE_ATOMUADD:
4076 op = LLVMAtomicRMWBinOpAdd;
4077 break;
4078 case TGSI_OPCODE_ATOMXCHG:
4079 op = LLVMAtomicRMWBinOpXchg;
4080 break;
4081 case TGSI_OPCODE_ATOMAND:
4082 op = LLVMAtomicRMWBinOpAnd;
4083 break;
4084 case TGSI_OPCODE_ATOMOR:
4085 op = LLVMAtomicRMWBinOpOr;
4086 break;
4087 case TGSI_OPCODE_ATOMXOR:
4088 op = LLVMAtomicRMWBinOpXor;
4089 break;
4090 case TGSI_OPCODE_ATOMUMIN:
4091 op = LLVMAtomicRMWBinOpUMin;
4092 break;
4093 case TGSI_OPCODE_ATOMUMAX:
4094 op = LLVMAtomicRMWBinOpUMax;
4095 break;
4096 case TGSI_OPCODE_ATOMIMIN:
4097 op = LLVMAtomicRMWBinOpMin;
4098 break;
4099 case TGSI_OPCODE_ATOMIMAX:
4100 op = LLVMAtomicRMWBinOpMax;
4101 break;
4102 default:
4103 unreachable("unknown atomic opcode");
4104 }
4105
4106 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
4107 LLVMAtomicOrderingSequentiallyConsistent,
4108 false);
4109 }
4110 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
4111 }
4112
4113 static void atomic_emit(
4114 const struct lp_build_tgsi_action *action,
4115 struct lp_build_tgsi_context *bld_base,
4116 struct lp_build_emit_data *emit_data)
4117 {
4118 struct si_shader_context *ctx = si_shader_context(bld_base);
4119 struct gallivm_state *gallivm = bld_base->base.gallivm;
4120 LLVMBuilderRef builder = gallivm->builder;
4121 const struct tgsi_full_instruction * inst = emit_data->inst;
4122 char intrinsic_name[40];
4123 LLVMValueRef tmp;
4124
4125 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
4126 atomic_emit_memory(ctx, emit_data);
4127 return;
4128 }
4129
4130 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
4131 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4132 snprintf(intrinsic_name, sizeof(intrinsic_name),
4133 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
4134 } else {
4135 LLVMValueRef coords;
4136 char coords_type[8];
4137
4138 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4139 coords = emit_data->args[2];
4140 else
4141 coords = emit_data->args[1];
4142
4143 build_type_name_for_intr(LLVMTypeOf(coords), coords_type, sizeof(coords_type));
4144 snprintf(intrinsic_name, sizeof(intrinsic_name),
4145 "llvm.amdgcn.image.atomic.%s.%s",
4146 action->intr_name, coords_type);
4147 }
4148
4149 tmp = lp_build_intrinsic(
4150 builder, intrinsic_name, bld_base->uint_bld.elem_type,
4151 emit_data->args, emit_data->arg_count, 0);
4152 emit_data->output[emit_data->chan] =
4153 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
4154 }
4155
4156 static void resq_fetch_args(
4157 struct lp_build_tgsi_context * bld_base,
4158 struct lp_build_emit_data * emit_data)
4159 {
4160 struct si_shader_context *ctx = si_shader_context(bld_base);
4161 struct gallivm_state *gallivm = bld_base->base.gallivm;
4162 const struct tgsi_full_instruction *inst = emit_data->inst;
4163 const struct tgsi_full_src_register *reg = &inst->Src[0];
4164
4165 emit_data->dst_type = ctx->v4i32;
4166
4167 if (reg->Register.File == TGSI_FILE_BUFFER) {
4168 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4169 emit_data->arg_count = 1;
4170 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4171 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4172 &emit_data->args[0]);
4173 emit_data->arg_count = 1;
4174 } else {
4175 emit_data->args[0] = bld_base->uint_bld.zero; /* mip level */
4176 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4177 &emit_data->args[1]);
4178 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
4179 emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
4180 emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
4181 emit_data->args[5] = tgsi_is_array_image(inst->Memory.Texture) ?
4182 bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da */
4183 emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
4184 emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
4185 emit_data->args[8] = bld_base->uint_bld.zero; /* tfe */
4186 emit_data->args[9] = bld_base->uint_bld.zero; /* lwe */
4187 emit_data->arg_count = 10;
4188 }
4189 }
4190
4191 static void resq_emit(
4192 const struct lp_build_tgsi_action *action,
4193 struct lp_build_tgsi_context *bld_base,
4194 struct lp_build_emit_data *emit_data)
4195 {
4196 struct gallivm_state *gallivm = bld_base->base.gallivm;
4197 LLVMBuilderRef builder = gallivm->builder;
4198 const struct tgsi_full_instruction *inst = emit_data->inst;
4199 LLVMValueRef out;
4200
4201 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4202 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4203 lp_build_const_int32(gallivm, 2), "");
4204 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4205 out = get_buffer_size(bld_base, emit_data->args[0]);
4206 } else {
4207 out = lp_build_intrinsic(
4208 builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
4209 emit_data->args, emit_data->arg_count,
4210 LP_FUNC_ATTR_READNONE);
4211
4212 /* Divide the number of layers by 6 to get the number of cubes. */
4213 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
4214 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
4215 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
4216
4217 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4218 z = LLVMBuildSDiv(builder, z, imm6, "");
4219 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4220 }
4221 }
4222
4223 emit_data->output[emit_data->chan] = out;
4224 }
4225
4226 static void set_tex_fetch_args(struct si_shader_context *ctx,
4227 struct lp_build_emit_data *emit_data,
4228 unsigned opcode, unsigned target,
4229 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4230 LLVMValueRef *param, unsigned count,
4231 unsigned dmask)
4232 {
4233 struct gallivm_state *gallivm = &ctx->gallivm;
4234 unsigned num_args;
4235 unsigned is_rect = target == TGSI_TEXTURE_RECT;
4236
4237 /* Pad to power of two vector */
4238 while (count < util_next_power_of_two(count))
4239 param[count++] = LLVMGetUndef(ctx->i32);
4240
4241 /* Texture coordinates. */
4242 if (count > 1)
4243 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
4244 else
4245 emit_data->args[0] = param[0];
4246
4247 /* Resource. */
4248 emit_data->args[1] = res_ptr;
4249 num_args = 2;
4250
4251 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
4252 emit_data->dst_type = ctx->v4i32;
4253 else {
4254 emit_data->dst_type = ctx->v4f32;
4255
4256 emit_data->args[num_args++] = samp_ptr;
4257 }
4258
4259 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
4260 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
4261 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
4262 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
4263 tgsi_is_array_sampler(target)); /* da */
4264 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
4265 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
4266 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
4267 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
4268
4269 emit_data->arg_count = num_args;
4270 }
4271
4272 static const struct lp_build_tgsi_action tex_action;
4273
4274 enum desc_type {
4275 DESC_IMAGE,
4276 DESC_BUFFER,
4277 DESC_FMASK,
4278 DESC_SAMPLER,
4279 };
4280
4281 /**
4282 * Load an image view, fmask view. or sampler state descriptor.
4283 */
4284 static LLVMValueRef load_sampler_desc_custom(struct si_shader_context *ctx,
4285 LLVMValueRef list, LLVMValueRef index,
4286 enum desc_type type)
4287 {
4288 struct gallivm_state *gallivm = &ctx->gallivm;
4289 LLVMBuilderRef builder = gallivm->builder;
4290
4291 switch (type) {
4292 case DESC_IMAGE:
4293 /* The image is at [0:7]. */
4294 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4295 break;
4296 case DESC_BUFFER:
4297 /* The buffer is in [4:7]. */
4298 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4299 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4300 list = LLVMBuildPointerCast(builder, list,
4301 const_array(ctx->v4i32, 0), "");
4302 break;
4303 case DESC_FMASK:
4304 /* The FMASK is at [8:15]. */
4305 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4306 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4307 break;
4308 case DESC_SAMPLER:
4309 /* The sampler state is at [12:15]. */
4310 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4311 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4312 list = LLVMBuildPointerCast(builder, list,
4313 const_array(ctx->v4i32, 0), "");
4314 break;
4315 }
4316
4317 return build_indexed_load_const(ctx, list, index);
4318 }
4319
4320 static LLVMValueRef load_sampler_desc(struct si_shader_context *ctx,
4321 LLVMValueRef index, enum desc_type type)
4322 {
4323 LLVMValueRef list = LLVMGetParam(ctx->main_fn,
4324 SI_PARAM_SAMPLERS);
4325
4326 return load_sampler_desc_custom(ctx, list, index, type);
4327 }
4328
4329 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4330 *
4331 * SI-CI:
4332 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4333 * filtering manually. The driver sets img7 to a mask clearing
4334 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4335 * s_and_b32 samp0, samp0, img7
4336 *
4337 * VI:
4338 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4339 */
4340 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4341 LLVMValueRef res, LLVMValueRef samp)
4342 {
4343 LLVMBuilderRef builder = ctx->gallivm.builder;
4344 LLVMValueRef img7, samp0;
4345
4346 if (ctx->screen->b.chip_class >= VI)
4347 return samp;
4348
4349 img7 = LLVMBuildExtractElement(builder, res,
4350 LLVMConstInt(ctx->i32, 7, 0), "");
4351 samp0 = LLVMBuildExtractElement(builder, samp,
4352 LLVMConstInt(ctx->i32, 0, 0), "");
4353 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4354 return LLVMBuildInsertElement(builder, samp, samp0,
4355 LLVMConstInt(ctx->i32, 0, 0), "");
4356 }
4357
4358 static void tex_fetch_ptrs(
4359 struct lp_build_tgsi_context *bld_base,
4360 struct lp_build_emit_data *emit_data,
4361 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4362 {
4363 struct si_shader_context *ctx = si_shader_context(bld_base);
4364 const struct tgsi_full_instruction *inst = emit_data->inst;
4365 unsigned target = inst->Texture.Texture;
4366 unsigned sampler_src;
4367 unsigned sampler_index;
4368 LLVMValueRef index;
4369
4370 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4371 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
4372
4373 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
4374 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
4375
4376 index = get_bounded_indirect_index(ctx,
4377 &reg->Indirect,
4378 reg->Register.Index,
4379 SI_NUM_SAMPLERS);
4380 } else {
4381 index = LLVMConstInt(ctx->i32, sampler_index, 0);
4382 }
4383
4384 if (target == TGSI_TEXTURE_BUFFER)
4385 *res_ptr = load_sampler_desc(ctx, index, DESC_BUFFER);
4386 else
4387 *res_ptr = load_sampler_desc(ctx, index, DESC_IMAGE);
4388
4389 if (samp_ptr)
4390 *samp_ptr = NULL;
4391 if (fmask_ptr)
4392 *fmask_ptr = NULL;
4393
4394 if (target == TGSI_TEXTURE_2D_MSAA ||
4395 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4396 if (fmask_ptr)
4397 *fmask_ptr = load_sampler_desc(ctx, index, DESC_FMASK);
4398 } else if (target != TGSI_TEXTURE_BUFFER) {
4399 if (samp_ptr) {
4400 *samp_ptr = load_sampler_desc(ctx, index, DESC_SAMPLER);
4401 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4402 }
4403 }
4404 }
4405
4406 static void txq_fetch_args(
4407 struct lp_build_tgsi_context *bld_base,
4408 struct lp_build_emit_data *emit_data)
4409 {
4410 struct si_shader_context *ctx = si_shader_context(bld_base);
4411 const struct tgsi_full_instruction *inst = emit_data->inst;
4412 unsigned target = inst->Texture.Texture;
4413 LLVMValueRef res_ptr;
4414 LLVMValueRef address;
4415
4416 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4417
4418 if (target == TGSI_TEXTURE_BUFFER) {
4419 /* Read the size from the buffer descriptor directly. */
4420 emit_data->args[0] = get_buffer_size(bld_base, res_ptr);
4421 return;
4422 }
4423
4424 /* Textures - set the mip level. */
4425 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4426
4427 set_tex_fetch_args(ctx, emit_data, TGSI_OPCODE_TXQ, target, res_ptr,
4428 NULL, &address, 1, 0xf);
4429 }
4430
4431 static void txq_emit(const struct lp_build_tgsi_action *action,
4432 struct lp_build_tgsi_context *bld_base,
4433 struct lp_build_emit_data *emit_data)
4434 {
4435 struct lp_build_context *base = &bld_base->base;
4436 unsigned target = emit_data->inst->Texture.Texture;
4437
4438 if (target == TGSI_TEXTURE_BUFFER) {
4439 /* Just return the buffer size. */
4440 emit_data->output[emit_data->chan] = emit_data->args[0];
4441 return;
4442 }
4443
4444 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4445 base->gallivm->builder, "llvm.SI.getresinfo.i32",
4446 emit_data->dst_type, emit_data->args, emit_data->arg_count,
4447 LP_FUNC_ATTR_READNONE);
4448
4449 /* Divide the number of layers by 6 to get the number of cubes. */
4450 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4451 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4452 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4453 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4454 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4455
4456 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4457 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4458 z = LLVMBuildSDiv(builder, z, six, "");
4459
4460 emit_data->output[emit_data->chan] =
4461 LLVMBuildInsertElement(builder, v4, z, two, "");
4462 }
4463 }
4464
4465 static void tex_fetch_args(
4466 struct lp_build_tgsi_context *bld_base,
4467 struct lp_build_emit_data *emit_data)
4468 {
4469 struct si_shader_context *ctx = si_shader_context(bld_base);
4470 struct gallivm_state *gallivm = bld_base->base.gallivm;
4471 const struct tgsi_full_instruction *inst = emit_data->inst;
4472 unsigned opcode = inst->Instruction.Opcode;
4473 unsigned target = inst->Texture.Texture;
4474 LLVMValueRef coords[5], derivs[6];
4475 LLVMValueRef address[16];
4476 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4477 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4478 unsigned count = 0;
4479 unsigned chan;
4480 unsigned num_deriv_channels = 0;
4481 bool has_offset = inst->Texture.NumOffsets > 0;
4482 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4483 unsigned dmask = 0xf;
4484
4485 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4486
4487 if (target == TGSI_TEXTURE_BUFFER) {
4488 emit_data->dst_type = ctx->v4f32;
4489 emit_data->args[0] = LLVMBuildBitCast(gallivm->builder, res_ptr,
4490 ctx->v16i8, "");
4491 emit_data->args[1] = bld_base->uint_bld.zero;
4492 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4493 emit_data->arg_count = 3;
4494 return;
4495 }
4496
4497 /* Fetch and project texture coordinates */
4498 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4499 for (chan = 0; chan < 3; chan++ ) {
4500 coords[chan] = lp_build_emit_fetch(bld_base,
4501 emit_data->inst, 0,
4502 chan);
4503 if (opcode == TGSI_OPCODE_TXP)
4504 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4505 TGSI_OPCODE_DIV,
4506 coords[chan],
4507 coords[3]);
4508 }
4509
4510 if (opcode == TGSI_OPCODE_TXP)
4511 coords[3] = bld_base->base.one;
4512
4513 /* Pack offsets. */
4514 if (has_offset && opcode != TGSI_OPCODE_TXF) {
4515 /* The offsets are six-bit signed integers packed like this:
4516 * X=[5:0], Y=[13:8], and Z=[21:16].
4517 */
4518 LLVMValueRef offset[3], pack;
4519
4520 assert(inst->Texture.NumOffsets == 1);
4521
4522 for (chan = 0; chan < 3; chan++) {
4523 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4524 emit_data->inst, 0, chan);
4525 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4526 lp_build_const_int32(gallivm, 0x3f), "");
4527 if (chan)
4528 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4529 lp_build_const_int32(gallivm, chan*8), "");
4530 }
4531
4532 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4533 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4534 address[count++] = pack;
4535 }
4536
4537 /* Pack LOD bias value */
4538 if (opcode == TGSI_OPCODE_TXB)
4539 address[count++] = coords[3];
4540 if (opcode == TGSI_OPCODE_TXB2)
4541 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4542
4543 /* Pack depth comparison value */
4544 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4545 LLVMValueRef z;
4546
4547 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4548 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4549 } else {
4550 assert(ref_pos >= 0);
4551 z = coords[ref_pos];
4552 }
4553
4554 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4555 * so the depth comparison value isn't clamped for Z16 and
4556 * Z24 anymore. Do it manually here.
4557 *
4558 * It's unnecessary if the original texture format was
4559 * Z32_FLOAT, but we don't know that here.
4560 */
4561 if (ctx->screen->b.chip_class == VI)
4562 z = si_llvm_saturate(bld_base, z);
4563
4564 address[count++] = z;
4565 }
4566
4567 /* Pack user derivatives */
4568 if (opcode == TGSI_OPCODE_TXD) {
4569 int param, num_src_deriv_channels;
4570
4571 switch (target) {
4572 case TGSI_TEXTURE_3D:
4573 num_src_deriv_channels = 3;
4574 num_deriv_channels = 3;
4575 break;
4576 case TGSI_TEXTURE_2D:
4577 case TGSI_TEXTURE_SHADOW2D:
4578 case TGSI_TEXTURE_RECT:
4579 case TGSI_TEXTURE_SHADOWRECT:
4580 case TGSI_TEXTURE_2D_ARRAY:
4581 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4582 num_src_deriv_channels = 2;
4583 num_deriv_channels = 2;
4584 break;
4585 case TGSI_TEXTURE_CUBE:
4586 case TGSI_TEXTURE_SHADOWCUBE:
4587 case TGSI_TEXTURE_CUBE_ARRAY:
4588 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4589 /* Cube derivatives will be converted to 2D. */
4590 num_src_deriv_channels = 3;
4591 num_deriv_channels = 2;
4592 break;
4593 case TGSI_TEXTURE_1D:
4594 case TGSI_TEXTURE_SHADOW1D:
4595 case TGSI_TEXTURE_1D_ARRAY:
4596 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4597 num_src_deriv_channels = 1;
4598 num_deriv_channels = 1;
4599 break;
4600 default:
4601 unreachable("invalid target");
4602 }
4603
4604 for (param = 0; param < 2; param++)
4605 for (chan = 0; chan < num_src_deriv_channels; chan++)
4606 derivs[param * num_src_deriv_channels + chan] =
4607 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4608 }
4609
4610 if (target == TGSI_TEXTURE_CUBE ||
4611 target == TGSI_TEXTURE_CUBE_ARRAY ||
4612 target == TGSI_TEXTURE_SHADOWCUBE ||
4613 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4614 si_prepare_cube_coords(bld_base, emit_data, coords, derivs);
4615
4616 if (opcode == TGSI_OPCODE_TXD)
4617 for (int i = 0; i < num_deriv_channels * 2; i++)
4618 address[count++] = derivs[i];
4619
4620 /* Pack texture coordinates */
4621 address[count++] = coords[0];
4622 if (num_coords > 1)
4623 address[count++] = coords[1];
4624 if (num_coords > 2)
4625 address[count++] = coords[2];
4626
4627 /* Pack LOD or sample index */
4628 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4629 address[count++] = coords[3];
4630 else if (opcode == TGSI_OPCODE_TXL2)
4631 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4632
4633 if (count > 16) {
4634 assert(!"Cannot handle more than 16 texture address parameters");
4635 count = 16;
4636 }
4637
4638 for (chan = 0; chan < count; chan++ ) {
4639 address[chan] = LLVMBuildBitCast(gallivm->builder,
4640 address[chan], ctx->i32, "");
4641 }
4642
4643 /* Adjust the sample index according to FMASK.
4644 *
4645 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4646 * which is the identity mapping. Each nibble says which physical sample
4647 * should be fetched to get that sample.
4648 *
4649 * For example, 0x11111100 means there are only 2 samples stored and
4650 * the second sample covers 3/4 of the pixel. When reading samples 0
4651 * and 1, return physical sample 0 (determined by the first two 0s
4652 * in FMASK), otherwise return physical sample 1.
4653 *
4654 * The sample index should be adjusted as follows:
4655 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4656 */
4657 if (target == TGSI_TEXTURE_2D_MSAA ||
4658 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4659 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4660 struct lp_build_emit_data txf_emit_data = *emit_data;
4661 LLVMValueRef txf_address[4];
4662 unsigned txf_count = count;
4663 struct tgsi_full_instruction inst = {};
4664
4665 memcpy(txf_address, address, sizeof(txf_address));
4666
4667 if (target == TGSI_TEXTURE_2D_MSAA) {
4668 txf_address[2] = bld_base->uint_bld.zero;
4669 }
4670 txf_address[3] = bld_base->uint_bld.zero;
4671
4672 /* Read FMASK using TXF. */
4673 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4674 inst.Texture.Texture = target;
4675 txf_emit_data.inst = &inst;
4676 txf_emit_data.chan = 0;
4677 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
4678 target, fmask_ptr, NULL,
4679 txf_address, txf_count, 0xf);
4680 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4681
4682 /* Initialize some constants. */
4683 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4684 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4685
4686 /* Apply the formula. */
4687 LLVMValueRef fmask =
4688 LLVMBuildExtractElement(gallivm->builder,
4689 txf_emit_data.output[0],
4690 uint_bld->zero, "");
4691
4692 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4693
4694 LLVMValueRef sample_index4 =
4695 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4696
4697 LLVMValueRef shifted_fmask =
4698 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4699
4700 LLVMValueRef final_sample =
4701 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4702
4703 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4704 * resource descriptor is 0 (invalid),
4705 */
4706 LLVMValueRef fmask_desc =
4707 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4708 ctx->v8i32, "");
4709
4710 LLVMValueRef fmask_word1 =
4711 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4712 uint_bld->one, "");
4713
4714 LLVMValueRef word1_is_nonzero =
4715 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4716 fmask_word1, uint_bld->zero, "");
4717
4718 /* Replace the MSAA sample index. */
4719 address[sample_chan] =
4720 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4721 final_sample, address[sample_chan], "");
4722 }
4723
4724 if (opcode == TGSI_OPCODE_TXF) {
4725 /* add tex offsets */
4726 if (inst->Texture.NumOffsets) {
4727 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4728 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
4729 const struct tgsi_texture_offset *off = inst->TexOffsets;
4730
4731 assert(inst->Texture.NumOffsets == 1);
4732
4733 switch (target) {
4734 case TGSI_TEXTURE_3D:
4735 address[2] = lp_build_add(uint_bld, address[2],
4736 bld->immediates[off->Index][off->SwizzleZ]);
4737 /* fall through */
4738 case TGSI_TEXTURE_2D:
4739 case TGSI_TEXTURE_SHADOW2D:
4740 case TGSI_TEXTURE_RECT:
4741 case TGSI_TEXTURE_SHADOWRECT:
4742 case TGSI_TEXTURE_2D_ARRAY:
4743 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4744 address[1] =
4745 lp_build_add(uint_bld, address[1],
4746 bld->immediates[off->Index][off->SwizzleY]);
4747 /* fall through */
4748 case TGSI_TEXTURE_1D:
4749 case TGSI_TEXTURE_SHADOW1D:
4750 case TGSI_TEXTURE_1D_ARRAY:
4751 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4752 address[0] =
4753 lp_build_add(uint_bld, address[0],
4754 bld->immediates[off->Index][off->SwizzleX]);
4755 break;
4756 /* texture offsets do not apply to other texture targets */
4757 }
4758 }
4759 }
4760
4761 if (opcode == TGSI_OPCODE_TG4) {
4762 unsigned gather_comp = 0;
4763
4764 /* DMASK was repurposed for GATHER4. 4 components are always
4765 * returned and DMASK works like a swizzle - it selects
4766 * the component to fetch. The only valid DMASK values are
4767 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4768 * (red,red,red,red) etc.) The ISA document doesn't mention
4769 * this.
4770 */
4771
4772 /* Get the component index from src1.x for Gather4. */
4773 if (!tgsi_is_shadow_target(target)) {
4774 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4775 LLVMValueRef comp_imm;
4776 struct tgsi_src_register src1 = inst->Src[1].Register;
4777
4778 assert(src1.File == TGSI_FILE_IMMEDIATE);
4779
4780 comp_imm = imms[src1.Index][src1.SwizzleX];
4781 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4782 gather_comp = CLAMP(gather_comp, 0, 3);
4783 }
4784
4785 dmask = 1 << gather_comp;
4786 }
4787
4788 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
4789 samp_ptr, address, count, dmask);
4790 }
4791
4792 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
4793 * incorrectly forces nearest filtering if the texture format is integer.
4794 * The only effect it has on Gather4, which always returns 4 texels for
4795 * bilinear filtering, is that the final coordinates are off by 0.5 of
4796 * the texel size.
4797 *
4798 * The workaround is to subtract 0.5 from the unnormalized coordinates,
4799 * or (0.5 / size) from the normalized coordinates.
4800 */
4801 static void si_lower_gather4_integer(struct si_shader_context *ctx,
4802 struct lp_build_emit_data *emit_data,
4803 const char *intr_name,
4804 unsigned coord_vgpr_index)
4805 {
4806 LLVMBuilderRef builder = ctx->gallivm.builder;
4807 LLVMValueRef coord = emit_data->args[0];
4808 LLVMValueRef half_texel[2];
4809 int c;
4810
4811 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_RECT ||
4812 emit_data->inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
4813 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
4814 } else {
4815 struct tgsi_full_instruction txq_inst = {};
4816 struct lp_build_emit_data txq_emit_data = {};
4817
4818 /* Query the texture size. */
4819 txq_inst.Texture.Texture = emit_data->inst->Texture.Texture;
4820 txq_emit_data.inst = &txq_inst;
4821 txq_emit_data.dst_type = ctx->v4i32;
4822 set_tex_fetch_args(ctx, &txq_emit_data, TGSI_OPCODE_TXQ,
4823 txq_inst.Texture.Texture,
4824 emit_data->args[1], NULL,
4825 &ctx->soa.bld_base.uint_bld.zero,
4826 1, 0xf);
4827 txq_emit(NULL, &ctx->soa.bld_base, &txq_emit_data);
4828
4829 /* Compute -0.5 / size. */
4830 for (c = 0; c < 2; c++) {
4831 half_texel[c] =
4832 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
4833 LLVMConstInt(ctx->i32, c, 0), "");
4834 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
4835 half_texel[c] =
4836 lp_build_emit_llvm_unary(&ctx->soa.bld_base,
4837 TGSI_OPCODE_RCP, half_texel[c]);
4838 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
4839 LLVMConstReal(ctx->f32, -0.5), "");
4840 }
4841 }
4842
4843 for (c = 0; c < 2; c++) {
4844 LLVMValueRef tmp;
4845 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
4846
4847 tmp = LLVMBuildExtractElement(builder, coord, index, "");
4848 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4849 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
4850 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4851 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
4852 }
4853
4854 emit_data->args[0] = coord;
4855 emit_data->output[emit_data->chan] =
4856 lp_build_intrinsic(builder, intr_name, emit_data->dst_type,
4857 emit_data->args, emit_data->arg_count,
4858 LP_FUNC_ATTR_READNONE);
4859 }
4860
4861 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4862 struct lp_build_tgsi_context *bld_base,
4863 struct lp_build_emit_data *emit_data)
4864 {
4865 struct si_shader_context *ctx = si_shader_context(bld_base);
4866 struct lp_build_context *base = &bld_base->base;
4867 const struct tgsi_full_instruction *inst = emit_data->inst;
4868 unsigned opcode = inst->Instruction.Opcode;
4869 unsigned target = inst->Texture.Texture;
4870 char intr_name[127];
4871 bool has_offset = inst->Texture.NumOffsets > 0;
4872 bool is_shadow = tgsi_is_shadow_target(target);
4873 char type[64];
4874 const char *name = "llvm.SI.image.sample";
4875 const char *infix = "";
4876
4877 if (target == TGSI_TEXTURE_BUFFER) {
4878 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4879 base->gallivm->builder,
4880 "llvm.SI.vs.load.input", emit_data->dst_type,
4881 emit_data->args, emit_data->arg_count,
4882 LP_FUNC_ATTR_READNONE);
4883 return;
4884 }
4885
4886 switch (opcode) {
4887 case TGSI_OPCODE_TXF:
4888 name = target == TGSI_TEXTURE_2D_MSAA ||
4889 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4890 "llvm.SI.image.load" :
4891 "llvm.SI.image.load.mip";
4892 is_shadow = false;
4893 has_offset = false;
4894 break;
4895 case TGSI_OPCODE_LODQ:
4896 name = "llvm.SI.getlod";
4897 is_shadow = false;
4898 has_offset = false;
4899 break;
4900 case TGSI_OPCODE_TEX:
4901 case TGSI_OPCODE_TEX2:
4902 case TGSI_OPCODE_TXP:
4903 if (ctx->type != PIPE_SHADER_FRAGMENT)
4904 infix = ".lz";
4905 break;
4906 case TGSI_OPCODE_TXB:
4907 case TGSI_OPCODE_TXB2:
4908 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4909 infix = ".b";
4910 break;
4911 case TGSI_OPCODE_TXL:
4912 case TGSI_OPCODE_TXL2:
4913 infix = ".l";
4914 break;
4915 case TGSI_OPCODE_TXD:
4916 infix = ".d";
4917 break;
4918 case TGSI_OPCODE_TG4:
4919 name = "llvm.SI.gather4";
4920 infix = ".lz";
4921 break;
4922 default:
4923 assert(0);
4924 return;
4925 }
4926
4927 /* Add the type and suffixes .c, .o if needed. */
4928 build_type_name_for_intr(LLVMTypeOf(emit_data->args[0]), type, sizeof(type));
4929 sprintf(intr_name, "%s%s%s%s.%s",
4930 name, is_shadow ? ".c" : "", infix,
4931 has_offset ? ".o" : "", type);
4932
4933 /* The hardware needs special lowering for Gather4 with integer formats. */
4934 if (opcode == TGSI_OPCODE_TG4) {
4935 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4936 /* This will also work with non-constant indexing because of how
4937 * glsl_to_tgsi works and we intent to preserve that behavior.
4938 */
4939 const unsigned src_idx = 2;
4940 unsigned sampler = inst->Src[src_idx].Register.Index;
4941
4942 assert(inst->Src[src_idx].Register.File == TGSI_FILE_SAMPLER);
4943
4944 if (info->sampler_type[sampler] == TGSI_RETURN_TYPE_SINT ||
4945 info->sampler_type[sampler] == TGSI_RETURN_TYPE_UINT) {
4946 /* Texture coordinates start after:
4947 * {offset, bias, z-compare, derivatives}
4948 * Only the offset and z-compare can occur here.
4949 */
4950 si_lower_gather4_integer(ctx, emit_data, intr_name,
4951 (int)has_offset + (int)is_shadow);
4952 return;
4953 }
4954 }
4955
4956 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4957 base->gallivm->builder, intr_name, emit_data->dst_type,
4958 emit_data->args, emit_data->arg_count,
4959 LP_FUNC_ATTR_READNONE);
4960 }
4961
4962 static void si_llvm_emit_txqs(
4963 const struct lp_build_tgsi_action *action,
4964 struct lp_build_tgsi_context *bld_base,
4965 struct lp_build_emit_data *emit_data)
4966 {
4967 struct si_shader_context *ctx = si_shader_context(bld_base);
4968 struct gallivm_state *gallivm = bld_base->base.gallivm;
4969 LLVMBuilderRef builder = gallivm->builder;
4970 LLVMValueRef res, samples;
4971 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4972
4973 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4974
4975
4976 /* Read the samples from the descriptor directly. */
4977 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4978 samples = LLVMBuildExtractElement(
4979 builder, res,
4980 lp_build_const_int32(gallivm, 3), "");
4981 samples = LLVMBuildLShr(builder, samples,
4982 lp_build_const_int32(gallivm, 16), "");
4983 samples = LLVMBuildAnd(builder, samples,
4984 lp_build_const_int32(gallivm, 0xf), "");
4985 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
4986 samples, "");
4987
4988 emit_data->output[emit_data->chan] = samples;
4989 }
4990
4991 /*
4992 * SI implements derivatives using the local data store (LDS)
4993 * All writes to the LDS happen in all executing threads at
4994 * the same time. TID is the Thread ID for the current
4995 * thread and is a value between 0 and 63, representing
4996 * the thread's position in the wavefront.
4997 *
4998 * For the pixel shader threads are grouped into quads of four pixels.
4999 * The TIDs of the pixels of a quad are:
5000 *
5001 * +------+------+
5002 * |4n + 0|4n + 1|
5003 * +------+------+
5004 * |4n + 2|4n + 3|
5005 * +------+------+
5006 *
5007 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
5008 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
5009 * the current pixel's column, and masking with 0xfffffffe yields the TID
5010 * of the left pixel of the current pixel's row.
5011 *
5012 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
5013 * adding 2 yields the TID of the pixel below the top pixel.
5014 */
5015 /* masks for thread ID. */
5016 #define TID_MASK_TOP_LEFT 0xfffffffc
5017 #define TID_MASK_TOP 0xfffffffd
5018 #define TID_MASK_LEFT 0xfffffffe
5019
5020 static void si_llvm_emit_ddxy(
5021 const struct lp_build_tgsi_action *action,
5022 struct lp_build_tgsi_context *bld_base,
5023 struct lp_build_emit_data *emit_data)
5024 {
5025 struct si_shader_context *ctx = si_shader_context(bld_base);
5026 struct gallivm_state *gallivm = bld_base->base.gallivm;
5027 unsigned opcode = emit_data->info->opcode;
5028 LLVMValueRef thread_id, tl, trbl, tl_tid, trbl_tid, val, args[2];
5029 int idx;
5030 unsigned mask;
5031
5032 thread_id = get_thread_id(ctx);
5033
5034 if (opcode == TGSI_OPCODE_DDX_FINE)
5035 mask = TID_MASK_LEFT;
5036 else if (opcode == TGSI_OPCODE_DDY_FINE)
5037 mask = TID_MASK_TOP;
5038 else
5039 mask = TID_MASK_TOP_LEFT;
5040
5041 tl_tid = LLVMBuildAnd(gallivm->builder, thread_id,
5042 lp_build_const_int32(gallivm, mask), "");
5043
5044 /* for DDX we want to next X pixel, DDY next Y pixel. */
5045 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
5046 trbl_tid = LLVMBuildAdd(gallivm->builder, tl_tid,
5047 lp_build_const_int32(gallivm, idx), "");
5048
5049 val = LLVMBuildBitCast(gallivm->builder, emit_data->args[0], ctx->i32, "");
5050
5051 if (ctx->screen->has_ds_bpermute) {
5052 args[0] = LLVMBuildMul(gallivm->builder, tl_tid,
5053 lp_build_const_int32(gallivm, 4), "");
5054 args[1] = val;
5055 tl = lp_build_intrinsic(gallivm->builder,
5056 "llvm.amdgcn.ds.bpermute", ctx->i32,
5057 args, 2, LP_FUNC_ATTR_READNONE);
5058
5059 args[0] = LLVMBuildMul(gallivm->builder, trbl_tid,
5060 lp_build_const_int32(gallivm, 4), "");
5061 trbl = lp_build_intrinsic(gallivm->builder,
5062 "llvm.amdgcn.ds.bpermute", ctx->i32,
5063 args, 2, LP_FUNC_ATTR_READNONE);
5064 } else {
5065 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
5066
5067 store_ptr = build_gep0(ctx, ctx->lds, thread_id);
5068 load_ptr0 = build_gep0(ctx, ctx->lds, tl_tid);
5069 load_ptr1 = build_gep0(ctx, ctx->lds, trbl_tid);
5070
5071 LLVMBuildStore(gallivm->builder, val, store_ptr);
5072 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
5073 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
5074 }
5075
5076 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
5077 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
5078
5079 emit_data->output[emit_data->chan] =
5080 LLVMBuildFSub(gallivm->builder, trbl, tl, "");
5081 }
5082
5083 /*
5084 * this takes an I,J coordinate pair,
5085 * and works out the X and Y derivatives.
5086 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
5087 */
5088 static LLVMValueRef si_llvm_emit_ddxy_interp(
5089 struct lp_build_tgsi_context *bld_base,
5090 LLVMValueRef interp_ij)
5091 {
5092 struct si_shader_context *ctx = si_shader_context(bld_base);
5093 struct gallivm_state *gallivm = bld_base->base.gallivm;
5094 LLVMValueRef result[4], a;
5095 unsigned i;
5096
5097 for (i = 0; i < 2; i++) {
5098 a = LLVMBuildExtractElement(gallivm->builder, interp_ij,
5099 LLVMConstInt(ctx->i32, i, 0), "");
5100 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
5101 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
5102 }
5103
5104 return lp_build_gather_values(gallivm, result, 4);
5105 }
5106
5107 static void interp_fetch_args(
5108 struct lp_build_tgsi_context *bld_base,
5109 struct lp_build_emit_data *emit_data)
5110 {
5111 struct si_shader_context *ctx = si_shader_context(bld_base);
5112 struct gallivm_state *gallivm = bld_base->base.gallivm;
5113 const struct tgsi_full_instruction *inst = emit_data->inst;
5114
5115 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
5116 /* offset is in second src, first two channels */
5117 emit_data->args[0] = lp_build_emit_fetch(bld_base,
5118 emit_data->inst, 1,
5119 TGSI_CHAN_X);
5120 emit_data->args[1] = lp_build_emit_fetch(bld_base,
5121 emit_data->inst, 1,
5122 TGSI_CHAN_Y);
5123 emit_data->arg_count = 2;
5124 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5125 LLVMValueRef sample_position;
5126 LLVMValueRef sample_id;
5127 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
5128
5129 /* fetch sample ID, then fetch its sample position,
5130 * and place into first two channels.
5131 */
5132 sample_id = lp_build_emit_fetch(bld_base,
5133 emit_data->inst, 1, TGSI_CHAN_X);
5134 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
5135 ctx->i32, "");
5136 sample_position = load_sample_position(ctx, sample_id);
5137
5138 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
5139 sample_position,
5140 lp_build_const_int32(gallivm, 0), "");
5141
5142 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
5143 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
5144 sample_position,
5145 lp_build_const_int32(gallivm, 1), "");
5146 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
5147 emit_data->arg_count = 2;
5148 }
5149 }
5150
5151 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
5152 struct lp_build_tgsi_context *bld_base,
5153 struct lp_build_emit_data *emit_data)
5154 {
5155 struct si_shader_context *ctx = si_shader_context(bld_base);
5156 struct si_shader *shader = ctx->shader;
5157 struct gallivm_state *gallivm = bld_base->base.gallivm;
5158 struct lp_build_context *uint = &bld_base->uint_bld;
5159 LLVMValueRef interp_param;
5160 const struct tgsi_full_instruction *inst = emit_data->inst;
5161 int input_index = inst->Src[0].Register.Index;
5162 int chan;
5163 int i;
5164 LLVMValueRef attr_number;
5165 LLVMValueRef params = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
5166 int interp_param_idx;
5167 unsigned interp = shader->selector->info.input_interpolate[input_index];
5168 unsigned location;
5169
5170 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5171
5172 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5173 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
5174 location = TGSI_INTERPOLATE_LOC_CENTER;
5175 else
5176 location = TGSI_INTERPOLATE_LOC_CENTROID;
5177
5178 interp_param_idx = lookup_interp_param_index(interp, location);
5179 if (interp_param_idx == -1)
5180 return;
5181 else if (interp_param_idx)
5182 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
5183 else
5184 interp_param = NULL;
5185
5186 attr_number = lp_build_const_int32(gallivm, input_index);
5187
5188 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5189 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5190 LLVMValueRef ij_out[2];
5191 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
5192
5193 /*
5194 * take the I then J parameters, and the DDX/Y for it, and
5195 * calculate the IJ inputs for the interpolator.
5196 * temp1 = ddx * offset/sample.x + I;
5197 * interp_param.I = ddy * offset/sample.y + temp1;
5198 * temp1 = ddx * offset/sample.x + J;
5199 * interp_param.J = ddy * offset/sample.y + temp1;
5200 */
5201 for (i = 0; i < 2; i++) {
5202 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
5203 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
5204 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
5205 ddxy_out, ix_ll, "");
5206 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
5207 ddxy_out, iy_ll, "");
5208 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5209 interp_param, ix_ll, "");
5210 LLVMValueRef temp1, temp2;
5211
5212 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5213 ctx->f32, "");
5214
5215 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5216
5217 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5218
5219 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5220
5221 ij_out[i] = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5222 }
5223 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
5224 }
5225
5226 for (chan = 0; chan < 4; chan++) {
5227 LLVMValueRef llvm_chan;
5228 unsigned schan;
5229
5230 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5231 llvm_chan = lp_build_const_int32(gallivm, schan);
5232
5233 if (interp_param) {
5234 interp_param = LLVMBuildBitCast(gallivm->builder,
5235 interp_param, LLVMVectorType(ctx->f32, 2), "");
5236 LLVMValueRef i = LLVMBuildExtractElement(
5237 gallivm->builder, interp_param, uint->zero, "");
5238 LLVMValueRef j = LLVMBuildExtractElement(
5239 gallivm->builder, interp_param, uint->one, "");
5240 emit_data->output[chan] = build_fs_interp(bld_base,
5241 llvm_chan, attr_number, params,
5242 i, j);
5243 } else {
5244 emit_data->output[chan] = build_fs_interp_mov(bld_base,
5245 lp_build_const_int32(gallivm, 2), /* P0 */
5246 llvm_chan, attr_number, params);
5247 }
5248 }
5249 }
5250
5251 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5252 struct lp_build_emit_data *emit_data)
5253 {
5254 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
5255 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5256 unsigned stream;
5257
5258 assert(src0.File == TGSI_FILE_IMMEDIATE);
5259
5260 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
5261 return stream;
5262 }
5263
5264 /* Emit one vertex from the geometry shader */
5265 static void si_llvm_emit_vertex(
5266 const struct lp_build_tgsi_action *action,
5267 struct lp_build_tgsi_context *bld_base,
5268 struct lp_build_emit_data *emit_data)
5269 {
5270 struct si_shader_context *ctx = si_shader_context(bld_base);
5271 struct lp_build_context *uint = &bld_base->uint_bld;
5272 struct si_shader *shader = ctx->shader;
5273 struct tgsi_shader_info *info = &shader->selector->info;
5274 struct gallivm_state *gallivm = bld_base->base.gallivm;
5275 struct lp_build_if_state if_state;
5276 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
5277 SI_PARAM_GS2VS_OFFSET);
5278 LLVMValueRef gs_next_vertex;
5279 LLVMValueRef can_emit, kill;
5280 LLVMValueRef args[2];
5281 unsigned chan;
5282 int i;
5283 unsigned stream;
5284
5285 stream = si_llvm_get_stream(bld_base, emit_data);
5286
5287 /* Write vertex attribute values to GSVS ring */
5288 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5289 ctx->gs_next_vertex[stream],
5290 "");
5291
5292 /* If this thread has already emitted the declared maximum number of
5293 * vertices, skip the write: excessive vertex emissions are not
5294 * supposed to have any effect.
5295 *
5296 * If the shader has no writes to memory, kill it instead. This skips
5297 * further memory loads and may allow LLVM to skip to the end
5298 * altogether.
5299 */
5300 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULT, gs_next_vertex,
5301 lp_build_const_int32(gallivm,
5302 shader->selector->gs_max_out_vertices), "");
5303
5304 bool use_kill = !info->writes_memory;
5305 if (use_kill) {
5306 kill = lp_build_select(&bld_base->base, can_emit,
5307 lp_build_const_float(gallivm, 1.0f),
5308 lp_build_const_float(gallivm, -1.0f));
5309
5310 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
5311 ctx->voidt, &kill, 1, 0);
5312 } else {
5313 lp_build_if(&if_state, gallivm, can_emit);
5314 }
5315
5316 for (i = 0; i < info->num_outputs; i++) {
5317 LLVMValueRef *out_ptr =
5318 ctx->soa.outputs[i];
5319
5320 for (chan = 0; chan < 4; chan++) {
5321 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5322 LLVMValueRef voffset =
5323 lp_build_const_int32(gallivm, (i * 4 + chan) *
5324 shader->selector->gs_max_out_vertices);
5325
5326 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5327 voffset = lp_build_mul_imm(uint, voffset, 4);
5328
5329 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5330
5331 build_tbuffer_store(ctx,
5332 ctx->gsvs_ring[stream],
5333 out_val, 1,
5334 voffset, soffset, 0,
5335 V_008F0C_BUF_DATA_FORMAT_32,
5336 V_008F0C_BUF_NUM_FORMAT_UINT,
5337 1, 0, 1, 1, 0);
5338 }
5339 }
5340
5341 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5342 lp_build_const_int32(gallivm, 1));
5343
5344 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5345
5346 /* Signal vertex emission */
5347 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
5348 args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID);
5349 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5350 ctx->voidt, args, 2, 0);
5351
5352 if (!use_kill)
5353 lp_build_endif(&if_state);
5354 }
5355
5356 /* Cut one primitive from the geometry shader */
5357 static void si_llvm_emit_primitive(
5358 const struct lp_build_tgsi_action *action,
5359 struct lp_build_tgsi_context *bld_base,
5360 struct lp_build_emit_data *emit_data)
5361 {
5362 struct si_shader_context *ctx = si_shader_context(bld_base);
5363 struct gallivm_state *gallivm = bld_base->base.gallivm;
5364 LLVMValueRef args[2];
5365 unsigned stream;
5366
5367 /* Signal primitive cut */
5368 stream = si_llvm_get_stream(bld_base, emit_data);
5369 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
5370 args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID);
5371 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5372 ctx->voidt, args, 2, 0);
5373 }
5374
5375 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5376 struct lp_build_tgsi_context *bld_base,
5377 struct lp_build_emit_data *emit_data)
5378 {
5379 struct si_shader_context *ctx = si_shader_context(bld_base);
5380 struct gallivm_state *gallivm = bld_base->base.gallivm;
5381
5382 /* The real barrier instruction isn’t needed, because an entire patch
5383 * always fits into a single wave.
5384 */
5385 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
5386 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
5387 return;
5388 }
5389
5390 lp_build_intrinsic(gallivm->builder,
5391 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5392 : "llvm.AMDGPU.barrier.local",
5393 ctx->voidt, NULL, 0, 0);
5394 }
5395
5396 static const struct lp_build_tgsi_action tex_action = {
5397 .fetch_args = tex_fetch_args,
5398 .emit = build_tex_intrinsic,
5399 };
5400
5401 static const struct lp_build_tgsi_action interp_action = {
5402 .fetch_args = interp_fetch_args,
5403 .emit = build_interp_intrinsic,
5404 };
5405
5406 static void si_create_function(struct si_shader_context *ctx,
5407 const char *name,
5408 LLVMTypeRef *returns, unsigned num_returns,
5409 LLVMTypeRef *params, unsigned num_params,
5410 int last_sgpr)
5411 {
5412 int i;
5413
5414 si_llvm_create_func(ctx, name, returns, num_returns,
5415 params, num_params);
5416 si_llvm_shader_type(ctx->main_fn, ctx->type);
5417 ctx->return_value = LLVMGetUndef(ctx->return_type);
5418
5419 for (i = 0; i <= last_sgpr; ++i) {
5420 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
5421
5422 /* The combination of:
5423 * - ByVal
5424 * - dereferenceable
5425 * - invariant.load
5426 * allows the optimization passes to move loads and reduces
5427 * SGPR spilling significantly.
5428 */
5429 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
5430 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
5431 lp_add_attr_dereferenceable(P, UINT64_MAX);
5432 } else
5433 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
5434 }
5435
5436 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5437 /* These were copied from some LLVM test. */
5438 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5439 "less-precise-fpmad",
5440 "true");
5441 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5442 "no-infs-fp-math",
5443 "true");
5444 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5445 "no-nans-fp-math",
5446 "true");
5447 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5448 "unsafe-fp-math",
5449 "true");
5450 }
5451 }
5452
5453 static void create_meta_data(struct si_shader_context *ctx)
5454 {
5455 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
5456
5457 ctx->invariant_load_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5458 "invariant.load", 14);
5459 ctx->range_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5460 "range", 5);
5461 ctx->uniform_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5462 "amdgpu.uniform", 14);
5463
5464 ctx->empty_md = LLVMMDNodeInContext(gallivm->context, NULL, 0);
5465 }
5466
5467 static void declare_streamout_params(struct si_shader_context *ctx,
5468 struct pipe_stream_output_info *so,
5469 LLVMTypeRef *params, LLVMTypeRef i32,
5470 unsigned *num_params)
5471 {
5472 int i;
5473
5474 /* Streamout SGPRs. */
5475 if (so->num_outputs) {
5476 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5477 params[ctx->param_streamout_config = (*num_params)++] = i32;
5478 else
5479 ctx->param_streamout_config = ctx->param_tess_offchip;
5480
5481 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5482 }
5483 /* A streamout buffer offset is loaded if the stride is non-zero. */
5484 for (i = 0; i < 4; i++) {
5485 if (!so->stride[i])
5486 continue;
5487
5488 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5489 }
5490 }
5491
5492 static unsigned llvm_get_type_size(LLVMTypeRef type)
5493 {
5494 LLVMTypeKind kind = LLVMGetTypeKind(type);
5495
5496 switch (kind) {
5497 case LLVMIntegerTypeKind:
5498 return LLVMGetIntTypeWidth(type) / 8;
5499 case LLVMFloatTypeKind:
5500 return 4;
5501 case LLVMPointerTypeKind:
5502 return 8;
5503 case LLVMVectorTypeKind:
5504 return LLVMGetVectorSize(type) *
5505 llvm_get_type_size(LLVMGetElementType(type));
5506 case LLVMArrayTypeKind:
5507 return LLVMGetArrayLength(type) *
5508 llvm_get_type_size(LLVMGetElementType(type));
5509 default:
5510 assert(0);
5511 return 0;
5512 }
5513 }
5514
5515 static void declare_tess_lds(struct si_shader_context *ctx)
5516 {
5517 struct gallivm_state *gallivm = &ctx->gallivm;
5518 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
5519 struct lp_build_context *uint = &bld_base->uint_bld;
5520
5521 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5522 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, uint->zero,
5523 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
5524 "tess_lds");
5525 }
5526
5527 static unsigned si_get_max_workgroup_size(struct si_shader *shader)
5528 {
5529 const unsigned *properties = shader->selector->info.properties;
5530 unsigned max_work_group_size =
5531 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5532 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5533 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5534
5535 if (!max_work_group_size) {
5536 /* This is a variable group size compute shader,
5537 * compile it for the maximum possible group size.
5538 */
5539 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
5540 }
5541 return max_work_group_size;
5542 }
5543
5544 static void create_function(struct si_shader_context *ctx)
5545 {
5546 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
5547 struct gallivm_state *gallivm = bld_base->base.gallivm;
5548 struct si_shader *shader = ctx->shader;
5549 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
5550 LLVMTypeRef returns[16+32*4];
5551 unsigned i, last_sgpr, num_params, num_return_sgprs;
5552 unsigned num_returns = 0;
5553 unsigned num_prolog_vgprs = 0;
5554
5555 v3i32 = LLVMVectorType(ctx->i32, 3);
5556
5557 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5558 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5559 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5560 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5561 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5562
5563 switch (ctx->type) {
5564 case PIPE_SHADER_VERTEX:
5565 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
5566 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5567 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5568 params[SI_PARAM_DRAWID] = ctx->i32;
5569 num_params = SI_PARAM_DRAWID+1;
5570
5571 if (shader->key.as_es) {
5572 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5573 } else if (shader->key.as_ls) {
5574 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
5575 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
5576 } else {
5577 if (shader->is_gs_copy_shader) {
5578 num_params = SI_PARAM_RW_BUFFERS+1;
5579 } else {
5580 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5581 num_params = SI_PARAM_VS_STATE_BITS+1;
5582 }
5583
5584 /* The locations of the other parameters are assigned dynamically. */
5585 declare_streamout_params(ctx, &shader->selector->so,
5586 params, ctx->i32, &num_params);
5587 }
5588
5589 last_sgpr = num_params-1;
5590
5591 /* VGPRs */
5592 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5593 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5594 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5595 params[ctx->param_instance_id = num_params++] = ctx->i32;
5596
5597 if (!shader->is_gs_copy_shader) {
5598 /* Vertex load indices. */
5599 ctx->param_vertex_index0 = num_params;
5600
5601 for (i = 0; i < shader->selector->info.num_inputs; i++)
5602 params[num_params++] = ctx->i32;
5603
5604 num_prolog_vgprs += shader->selector->info.num_inputs;
5605
5606 /* PrimitiveID output. */
5607 if (!shader->key.as_es && !shader->key.as_ls)
5608 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5609 returns[num_returns++] = ctx->f32;
5610 }
5611 break;
5612
5613 case PIPE_SHADER_TESS_CTRL:
5614 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5615 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5616 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5617 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5618 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5619 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5620 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5621
5622 /* VGPRs */
5623 params[SI_PARAM_PATCH_ID] = ctx->i32;
5624 params[SI_PARAM_REL_IDS] = ctx->i32;
5625 num_params = SI_PARAM_REL_IDS+1;
5626
5627 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5628 * placed after the user SGPRs.
5629 */
5630 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5631 returns[num_returns++] = ctx->i32; /* SGPRs */
5632
5633 for (i = 0; i < 3; i++)
5634 returns[num_returns++] = ctx->f32; /* VGPRs */
5635 break;
5636
5637 case PIPE_SHADER_TESS_EVAL:
5638 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5639 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5640
5641 if (shader->key.as_es) {
5642 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5643 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5644 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5645 } else {
5646 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5647 declare_streamout_params(ctx, &shader->selector->so,
5648 params, ctx->i32, &num_params);
5649 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5650 }
5651 last_sgpr = num_params - 1;
5652
5653 /* VGPRs */
5654 params[ctx->param_tes_u = num_params++] = ctx->f32;
5655 params[ctx->param_tes_v = num_params++] = ctx->f32;
5656 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5657 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5658
5659 /* PrimitiveID output. */
5660 if (!shader->key.as_es)
5661 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5662 returns[num_returns++] = ctx->f32;
5663 break;
5664
5665 case PIPE_SHADER_GEOMETRY:
5666 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5667 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5668 last_sgpr = SI_PARAM_GS_WAVE_ID;
5669
5670 /* VGPRs */
5671 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5672 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5673 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5674 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5675 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5676 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5677 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5678 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5679 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5680 break;
5681
5682 case PIPE_SHADER_FRAGMENT:
5683 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5684 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5685 last_sgpr = SI_PARAM_PRIM_MASK;
5686 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5687 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5688 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5689 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5690 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5691 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5692 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5693 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5694 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5695 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5696 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5697 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5698 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5699 shader->info.face_vgpr_index = 20;
5700 params[SI_PARAM_ANCILLARY] = ctx->i32;
5701 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5702 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5703 num_params = SI_PARAM_POS_FIXED_PT+1;
5704
5705 /* Color inputs from the prolog. */
5706 if (shader->selector->info.colors_read) {
5707 unsigned num_color_elements =
5708 util_bitcount(shader->selector->info.colors_read);
5709
5710 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5711 for (i = 0; i < num_color_elements; i++)
5712 params[num_params++] = ctx->f32;
5713
5714 num_prolog_vgprs += num_color_elements;
5715 }
5716
5717 /* Outputs for the epilog. */
5718 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5719 num_returns =
5720 num_return_sgprs +
5721 util_bitcount(shader->selector->info.colors_written) * 4 +
5722 shader->selector->info.writes_z +
5723 shader->selector->info.writes_stencil +
5724 shader->selector->info.writes_samplemask +
5725 1 /* SampleMaskIn */;
5726
5727 num_returns = MAX2(num_returns,
5728 num_return_sgprs +
5729 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5730
5731 for (i = 0; i < num_return_sgprs; i++)
5732 returns[i] = ctx->i32;
5733 for (; i < num_returns; i++)
5734 returns[i] = ctx->f32;
5735 break;
5736
5737 case PIPE_SHADER_COMPUTE:
5738 params[SI_PARAM_GRID_SIZE] = v3i32;
5739 params[SI_PARAM_BLOCK_SIZE] = v3i32;
5740 params[SI_PARAM_BLOCK_ID] = v3i32;
5741 last_sgpr = SI_PARAM_BLOCK_ID;
5742
5743 params[SI_PARAM_THREAD_ID] = v3i32;
5744 num_params = SI_PARAM_THREAD_ID + 1;
5745 break;
5746 default:
5747 assert(0 && "unimplemented shader");
5748 return;
5749 }
5750
5751 assert(num_params <= ARRAY_SIZE(params));
5752
5753 si_create_function(ctx, "main", returns, num_returns, params,
5754 num_params, last_sgpr);
5755
5756 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5757 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5758 ctx->separate_prolog) {
5759 si_llvm_add_attribute(ctx->main_fn,
5760 "InitialPSInputAddr",
5761 S_0286D0_PERSP_SAMPLE_ENA(1) |
5762 S_0286D0_PERSP_CENTER_ENA(1) |
5763 S_0286D0_PERSP_CENTROID_ENA(1) |
5764 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5765 S_0286D0_LINEAR_CENTER_ENA(1) |
5766 S_0286D0_LINEAR_CENTROID_ENA(1) |
5767 S_0286D0_FRONT_FACE_ENA(1) |
5768 S_0286D0_POS_FIXED_PT_ENA(1));
5769 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5770 si_llvm_add_attribute(ctx->main_fn,
5771 "amdgpu-max-work-group-size",
5772 si_get_max_workgroup_size(shader));
5773 }
5774
5775 shader->info.num_input_sgprs = 0;
5776 shader->info.num_input_vgprs = 0;
5777
5778 for (i = 0; i <= last_sgpr; ++i)
5779 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5780
5781 for (; i < num_params; ++i)
5782 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5783
5784 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5785 shader->info.num_input_vgprs -= num_prolog_vgprs;
5786
5787 if (!ctx->screen->has_ds_bpermute &&
5788 bld_base->info &&
5789 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5790 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5791 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5792 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5793 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5794 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5795 ctx->lds =
5796 LLVMAddGlobalInAddressSpace(gallivm->module,
5797 LLVMArrayType(ctx->i32, 64),
5798 "ddxy_lds",
5799 LOCAL_ADDR_SPACE);
5800
5801 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.as_ls) ||
5802 ctx->type == PIPE_SHADER_TESS_CTRL ||
5803 ctx->type == PIPE_SHADER_TESS_EVAL)
5804 declare_tess_lds(ctx);
5805 }
5806
5807 /**
5808 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5809 * for later use.
5810 */
5811 static void preload_ring_buffers(struct si_shader_context *ctx)
5812 {
5813 struct gallivm_state *gallivm =
5814 ctx->soa.bld_base.base.gallivm;
5815
5816 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5817 SI_PARAM_RW_BUFFERS);
5818
5819 if ((ctx->type == PIPE_SHADER_VERTEX &&
5820 ctx->shader->key.as_es) ||
5821 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5822 ctx->shader->key.as_es) ||
5823 ctx->type == PIPE_SHADER_GEOMETRY) {
5824 unsigned ring =
5825 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5826 : SI_ES_RING_ESGS;
5827 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5828
5829 ctx->esgs_ring =
5830 build_indexed_load_const(ctx, buf_ptr, offset);
5831 }
5832
5833 if (ctx->shader->is_gs_copy_shader) {
5834 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_VS_RING_GSVS);
5835
5836 ctx->gsvs_ring[0] =
5837 build_indexed_load_const(ctx, buf_ptr, offset);
5838 }
5839 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5840 int i;
5841 for (i = 0; i < 4; i++) {
5842 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_GS_RING_GSVS0 + i);
5843
5844 ctx->gsvs_ring[i] =
5845 build_indexed_load_const(ctx, buf_ptr, offset);
5846 }
5847 }
5848 }
5849
5850 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5851 LLVMValueRef param_rw_buffers,
5852 unsigned param_pos_fixed_pt)
5853 {
5854 struct lp_build_tgsi_context *bld_base =
5855 &ctx->soa.bld_base;
5856 struct gallivm_state *gallivm = bld_base->base.gallivm;
5857 LLVMBuilderRef builder = gallivm->builder;
5858 LLVMValueRef slot, desc, offset, row, bit, address[2];
5859
5860 /* Use the fixed-point gl_FragCoord input.
5861 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5862 * per coordinate to get the repeating effect.
5863 */
5864 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5865 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5866
5867 /* Load the buffer descriptor. */
5868 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
5869 desc = build_indexed_load_const(ctx, param_rw_buffers, slot);
5870
5871 /* The stipple pattern is 32x32, each row has 32 bits. */
5872 offset = LLVMBuildMul(builder, address[1],
5873 LLVMConstInt(ctx->i32, 4, 0), "");
5874 row = buffer_load_const(ctx, desc, offset);
5875 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
5876 bit = LLVMBuildLShr(builder, row, address[0], "");
5877 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5878
5879 /* The intrinsic kills the thread if arg < 0. */
5880 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
5881 LLVMConstReal(ctx->f32, -1), "");
5882 lp_build_intrinsic(builder, "llvm.AMDGPU.kill", ctx->voidt, &bit, 1, 0);
5883 }
5884
5885 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
5886 struct si_shader_config *conf,
5887 unsigned symbol_offset)
5888 {
5889 unsigned i;
5890 const unsigned char *config =
5891 radeon_shader_binary_config_start(binary, symbol_offset);
5892 bool really_needs_scratch = false;
5893
5894 /* LLVM adds SGPR spills to the scratch size.
5895 * Find out if we really need the scratch buffer.
5896 */
5897 for (i = 0; i < binary->reloc_count; i++) {
5898 const struct radeon_shader_reloc *reloc = &binary->relocs[i];
5899
5900 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5901 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5902 really_needs_scratch = true;
5903 break;
5904 }
5905 }
5906
5907 /* XXX: We may be able to emit some of these values directly rather than
5908 * extracting fields to be emitted later.
5909 */
5910
5911 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5912 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5913 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5914 switch (reg) {
5915 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5916 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5917 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5918 case R_00B848_COMPUTE_PGM_RSRC1:
5919 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5920 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5921 conf->float_mode = G_00B028_FLOAT_MODE(value);
5922 conf->rsrc1 = value;
5923 break;
5924 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5925 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5926 break;
5927 case R_00B84C_COMPUTE_PGM_RSRC2:
5928 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5929 conf->rsrc2 = value;
5930 break;
5931 case R_0286CC_SPI_PS_INPUT_ENA:
5932 conf->spi_ps_input_ena = value;
5933 break;
5934 case R_0286D0_SPI_PS_INPUT_ADDR:
5935 conf->spi_ps_input_addr = value;
5936 break;
5937 case R_0286E8_SPI_TMPRING_SIZE:
5938 case R_00B860_COMPUTE_TMPRING_SIZE:
5939 /* WAVESIZE is in units of 256 dwords. */
5940 if (really_needs_scratch)
5941 conf->scratch_bytes_per_wave =
5942 G_00B860_WAVESIZE(value) * 256 * 4;
5943 break;
5944 case 0x4: /* SPILLED_SGPRS */
5945 conf->spilled_sgprs = value;
5946 break;
5947 case 0x8: /* SPILLED_VGPRS */
5948 conf->spilled_vgprs = value;
5949 break;
5950 default:
5951 {
5952 static bool printed;
5953
5954 if (!printed) {
5955 fprintf(stderr, "Warning: LLVM emitted unknown "
5956 "config register: 0x%x\n", reg);
5957 printed = true;
5958 }
5959 }
5960 break;
5961 }
5962 }
5963
5964 if (!conf->spi_ps_input_addr)
5965 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5966 }
5967
5968 void si_shader_apply_scratch_relocs(struct si_context *sctx,
5969 struct si_shader *shader,
5970 struct si_shader_config *config,
5971 uint64_t scratch_va)
5972 {
5973 unsigned i;
5974 uint32_t scratch_rsrc_dword0 = scratch_va;
5975 uint32_t scratch_rsrc_dword1 =
5976 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5977
5978 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
5979 * correctly.
5980 */
5981 if (HAVE_LLVM >= 0x0309)
5982 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5983 else
5984 scratch_rsrc_dword1 |=
5985 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
5986
5987 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5988 const struct radeon_shader_reloc *reloc =
5989 &shader->binary.relocs[i];
5990 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5991 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5992 &scratch_rsrc_dword0, 4);
5993 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5994 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5995 &scratch_rsrc_dword1, 4);
5996 }
5997 }
5998 }
5999
6000 static unsigned si_get_shader_binary_size(struct si_shader *shader)
6001 {
6002 unsigned size = shader->binary.code_size;
6003
6004 if (shader->prolog)
6005 size += shader->prolog->binary.code_size;
6006 if (shader->epilog)
6007 size += shader->epilog->binary.code_size;
6008 return size;
6009 }
6010
6011 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
6012 {
6013 const struct radeon_shader_binary *prolog =
6014 shader->prolog ? &shader->prolog->binary : NULL;
6015 const struct radeon_shader_binary *epilog =
6016 shader->epilog ? &shader->epilog->binary : NULL;
6017 const struct radeon_shader_binary *mainb = &shader->binary;
6018 unsigned bo_size = si_get_shader_binary_size(shader) +
6019 (!epilog ? mainb->rodata_size : 0);
6020 unsigned char *ptr;
6021
6022 assert(!prolog || !prolog->rodata_size);
6023 assert((!prolog && !epilog) || !mainb->rodata_size);
6024 assert(!epilog || !epilog->rodata_size);
6025
6026 r600_resource_reference(&shader->bo, NULL);
6027 shader->bo = (struct r600_resource*)
6028 pipe_buffer_create(&sscreen->b.b, 0,
6029 PIPE_USAGE_IMMUTABLE, bo_size);
6030 if (!shader->bo)
6031 return -ENOMEM;
6032
6033 /* Upload. */
6034 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
6035 PIPE_TRANSFER_READ_WRITE);
6036
6037 if (prolog) {
6038 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
6039 ptr += prolog->code_size;
6040 }
6041
6042 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
6043 ptr += mainb->code_size;
6044
6045 if (epilog)
6046 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
6047 else if (mainb->rodata_size > 0)
6048 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
6049
6050 sscreen->b.ws->buffer_unmap(shader->bo->buf);
6051 return 0;
6052 }
6053
6054 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
6055 struct pipe_debug_callback *debug,
6056 const char *name, FILE *file)
6057 {
6058 char *line, *p;
6059 unsigned i, count;
6060
6061 if (binary->disasm_string) {
6062 fprintf(file, "Shader %s disassembly:\n", name);
6063 fprintf(file, "%s", binary->disasm_string);
6064
6065 if (debug && debug->debug_message) {
6066 /* Very long debug messages are cut off, so send the
6067 * disassembly one line at a time. This causes more
6068 * overhead, but on the plus side it simplifies
6069 * parsing of resulting logs.
6070 */
6071 pipe_debug_message(debug, SHADER_INFO,
6072 "Shader Disassembly Begin");
6073
6074 line = binary->disasm_string;
6075 while (*line) {
6076 p = util_strchrnul(line, '\n');
6077 count = p - line;
6078
6079 if (count) {
6080 pipe_debug_message(debug, SHADER_INFO,
6081 "%.*s", count, line);
6082 }
6083
6084 if (!*p)
6085 break;
6086 line = p + 1;
6087 }
6088
6089 pipe_debug_message(debug, SHADER_INFO,
6090 "Shader Disassembly End");
6091 }
6092 } else {
6093 fprintf(file, "Shader %s binary:\n", name);
6094 for (i = 0; i < binary->code_size; i += 4) {
6095 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
6096 binary->code[i + 3], binary->code[i + 2],
6097 binary->code[i + 1], binary->code[i]);
6098 }
6099 }
6100 }
6101
6102 static void si_shader_dump_stats(struct si_screen *sscreen,
6103 struct si_shader *shader,
6104 struct pipe_debug_callback *debug,
6105 unsigned processor,
6106 FILE *file)
6107 {
6108 struct si_shader_config *conf = &shader->config;
6109 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
6110 unsigned code_size = si_get_shader_binary_size(shader);
6111 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
6112 unsigned lds_per_wave = 0;
6113 unsigned max_simd_waves = 10;
6114
6115 /* Compute LDS usage for PS. */
6116 switch (processor) {
6117 case PIPE_SHADER_FRAGMENT:
6118 /* The minimum usage per wave is (num_inputs * 48). The maximum
6119 * usage is (num_inputs * 48 * 16).
6120 * We can get anything in between and it varies between waves.
6121 *
6122 * The 48 bytes per input for a single primitive is equal to
6123 * 4 bytes/component * 4 components/input * 3 points.
6124 *
6125 * Other stages don't know the size at compile time or don't
6126 * allocate LDS per wave, but instead they do it per thread group.
6127 */
6128 lds_per_wave = conf->lds_size * lds_increment +
6129 align(num_inputs * 48, lds_increment);
6130 break;
6131 case PIPE_SHADER_COMPUTE:
6132 if (shader->selector) {
6133 unsigned max_workgroup_size =
6134 si_get_max_workgroup_size(shader);
6135 lds_per_wave = (conf->lds_size * lds_increment) /
6136 DIV_ROUND_UP(max_workgroup_size, 64);
6137 }
6138 break;
6139 }
6140
6141 /* Compute the per-SIMD wave counts. */
6142 if (conf->num_sgprs) {
6143 if (sscreen->b.chip_class >= VI)
6144 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
6145 else
6146 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
6147 }
6148
6149 if (conf->num_vgprs)
6150 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
6151
6152 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
6153 * 16KB makes some SIMDs unoccupied). */
6154 if (lds_per_wave)
6155 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
6156
6157 if (file != stderr ||
6158 r600_can_dump_shader(&sscreen->b, processor)) {
6159 if (processor == PIPE_SHADER_FRAGMENT) {
6160 fprintf(file, "*** SHADER CONFIG ***\n"
6161 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6162 "SPI_PS_INPUT_ENA = 0x%04x\n",
6163 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
6164 }
6165
6166 fprintf(file, "*** SHADER STATS ***\n"
6167 "SGPRS: %d\n"
6168 "VGPRS: %d\n"
6169 "Spilled SGPRs: %d\n"
6170 "Spilled VGPRs: %d\n"
6171 "Private memory VGPRs: %d\n"
6172 "Code Size: %d bytes\n"
6173 "LDS: %d blocks\n"
6174 "Scratch: %d bytes per wave\n"
6175 "Max Waves: %d\n"
6176 "********************\n\n\n",
6177 conf->num_sgprs, conf->num_vgprs,
6178 conf->spilled_sgprs, conf->spilled_vgprs,
6179 conf->private_mem_vgprs, code_size,
6180 conf->lds_size, conf->scratch_bytes_per_wave,
6181 max_simd_waves);
6182 }
6183
6184 pipe_debug_message(debug, SHADER_INFO,
6185 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6186 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
6187 "Spilled VGPRs: %d PrivMem VGPRs: %d",
6188 conf->num_sgprs, conf->num_vgprs, code_size,
6189 conf->lds_size, conf->scratch_bytes_per_wave,
6190 max_simd_waves, conf->spilled_sgprs,
6191 conf->spilled_vgprs, conf->private_mem_vgprs);
6192 }
6193
6194 static const char *si_get_shader_name(struct si_shader *shader,
6195 unsigned processor)
6196 {
6197 switch (processor) {
6198 case PIPE_SHADER_VERTEX:
6199 if (shader->key.as_es)
6200 return "Vertex Shader as ES";
6201 else if (shader->key.as_ls)
6202 return "Vertex Shader as LS";
6203 else
6204 return "Vertex Shader as VS";
6205 case PIPE_SHADER_TESS_CTRL:
6206 return "Tessellation Control Shader";
6207 case PIPE_SHADER_TESS_EVAL:
6208 if (shader->key.as_es)
6209 return "Tessellation Evaluation Shader as ES";
6210 else
6211 return "Tessellation Evaluation Shader as VS";
6212 case PIPE_SHADER_GEOMETRY:
6213 if (shader->is_gs_copy_shader)
6214 return "GS Copy Shader as VS";
6215 else
6216 return "Geometry Shader";
6217 case PIPE_SHADER_FRAGMENT:
6218 return "Pixel Shader";
6219 case PIPE_SHADER_COMPUTE:
6220 return "Compute Shader";
6221 default:
6222 return "Unknown Shader";
6223 }
6224 }
6225
6226 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6227 struct pipe_debug_callback *debug, unsigned processor,
6228 FILE *file)
6229 {
6230 if (file != stderr ||
6231 r600_can_dump_shader(&sscreen->b, processor))
6232 si_dump_shader_key(processor, &shader->key, file);
6233
6234 if (file != stderr && shader->binary.llvm_ir_string) {
6235 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
6236 si_get_shader_name(shader, processor));
6237 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
6238 }
6239
6240 if (file != stderr ||
6241 (r600_can_dump_shader(&sscreen->b, processor) &&
6242 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6243 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6244
6245 if (shader->prolog)
6246 si_shader_dump_disassembly(&shader->prolog->binary,
6247 debug, "prolog", file);
6248
6249 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6250
6251 if (shader->epilog)
6252 si_shader_dump_disassembly(&shader->epilog->binary,
6253 debug, "epilog", file);
6254 fprintf(file, "\n");
6255 }
6256
6257 si_shader_dump_stats(sscreen, shader, debug, processor, file);
6258 }
6259
6260 int si_compile_llvm(struct si_screen *sscreen,
6261 struct radeon_shader_binary *binary,
6262 struct si_shader_config *conf,
6263 LLVMTargetMachineRef tm,
6264 LLVMModuleRef mod,
6265 struct pipe_debug_callback *debug,
6266 unsigned processor,
6267 const char *name)
6268 {
6269 int r = 0;
6270 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6271
6272 if (r600_can_dump_shader(&sscreen->b, processor)) {
6273 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6274
6275 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6276 fprintf(stderr, "%s LLVM IR:\n\n", name);
6277 LLVMDumpModule(mod);
6278 fprintf(stderr, "\n");
6279 }
6280 }
6281
6282 if (sscreen->record_llvm_ir) {
6283 char *ir = LLVMPrintModuleToString(mod);
6284 binary->llvm_ir_string = strdup(ir);
6285 LLVMDisposeMessage(ir);
6286 }
6287
6288 if (!si_replace_shader(count, binary)) {
6289 r = si_llvm_compile(mod, binary, tm, debug);
6290 if (r)
6291 return r;
6292 }
6293
6294 si_shader_binary_read_config(binary, conf, 0);
6295
6296 /* Enable 64-bit and 16-bit denormals, because there is no performance
6297 * cost.
6298 *
6299 * If denormals are enabled, all floating-point output modifiers are
6300 * ignored.
6301 *
6302 * Don't enable denormals for 32-bit floats, because:
6303 * - Floating-point output modifiers would be ignored by the hw.
6304 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6305 * have to stop using those.
6306 * - SI & CI would be very slow.
6307 */
6308 conf->float_mode |= V_00B028_FP_64_DENORMS;
6309
6310 FREE(binary->config);
6311 FREE(binary->global_symbol_offsets);
6312 binary->config = NULL;
6313 binary->global_symbol_offsets = NULL;
6314
6315 /* Some shaders can't have rodata because their binaries can be
6316 * concatenated.
6317 */
6318 if (binary->rodata_size &&
6319 (processor == PIPE_SHADER_VERTEX ||
6320 processor == PIPE_SHADER_TESS_CTRL ||
6321 processor == PIPE_SHADER_TESS_EVAL ||
6322 processor == PIPE_SHADER_FRAGMENT)) {
6323 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6324 return -EINVAL;
6325 }
6326
6327 return r;
6328 }
6329
6330 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6331 {
6332 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6333 LLVMBuildRetVoid(ctx->gallivm.builder);
6334 else
6335 LLVMBuildRet(ctx->gallivm.builder, ret);
6336 }
6337
6338 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6339 struct si_shader *
6340 si_generate_gs_copy_shader(struct si_screen *sscreen,
6341 LLVMTargetMachineRef tm,
6342 struct si_shader_selector *gs_selector,
6343 struct pipe_debug_callback *debug)
6344 {
6345 struct si_shader_context ctx;
6346 struct si_shader *shader;
6347 struct gallivm_state *gallivm = &ctx.gallivm;
6348 struct lp_build_tgsi_context *bld_base = &ctx.soa.bld_base;
6349 struct lp_build_context *uint = &bld_base->uint_bld;
6350 struct si_shader_output_values *outputs;
6351 struct tgsi_shader_info *gsinfo = &gs_selector->info;
6352 LLVMValueRef args[9];
6353 int i, r;
6354
6355 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6356
6357 if (!outputs)
6358 return NULL;
6359
6360 shader = CALLOC_STRUCT(si_shader);
6361 if (!shader) {
6362 FREE(outputs);
6363 return NULL;
6364 }
6365
6366
6367 shader->selector = gs_selector;
6368 shader->is_gs_copy_shader = true;
6369
6370 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6371 ctx.type = PIPE_SHADER_VERTEX;
6372
6373 create_meta_data(&ctx);
6374 create_function(&ctx);
6375 preload_ring_buffers(&ctx);
6376
6377 args[0] = ctx.gsvs_ring[0];
6378 args[1] = lp_build_mul_imm(uint,
6379 LLVMGetParam(ctx.main_fn,
6380 ctx.param_vertex_id),
6381 4);
6382 args[3] = uint->zero;
6383 args[4] = uint->one; /* OFFEN */
6384 args[5] = uint->zero; /* IDXEN */
6385 args[6] = uint->one; /* GLC */
6386 args[7] = uint->one; /* SLC */
6387 args[8] = uint->zero; /* TFE */
6388
6389 /* Fetch vertex data from GSVS ring */
6390 for (i = 0; i < gsinfo->num_outputs; ++i) {
6391 unsigned chan;
6392
6393 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
6394 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
6395
6396 for (chan = 0; chan < 4; chan++) {
6397 outputs[i].vertex_stream[chan] =
6398 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
6399
6400 args[2] = lp_build_const_int32(gallivm,
6401 (i * 4 + chan) *
6402 gs_selector->gs_max_out_vertices * 16 * 4);
6403
6404 outputs[i].values[chan] =
6405 LLVMBuildBitCast(gallivm->builder,
6406 lp_build_intrinsic(gallivm->builder,
6407 "llvm.SI.buffer.load.dword.i32.i32",
6408 ctx.i32, args, 9,
6409 LP_FUNC_ATTR_READONLY),
6410 ctx.f32, "");
6411 }
6412 }
6413
6414 if (gs_selector->so.num_outputs)
6415 si_llvm_emit_streamout(&ctx, outputs, gsinfo->num_outputs);
6416 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6417
6418 LLVMBuildRetVoid(gallivm->builder);
6419
6420 /* Dump LLVM IR before any optimization passes */
6421 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6422 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6423 LLVMDumpModule(bld_base->base.gallivm->module);
6424
6425 si_llvm_finalize_module(&ctx,
6426 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_GEOMETRY));
6427
6428 r = si_compile_llvm(sscreen, &ctx.shader->binary,
6429 &ctx.shader->config, ctx.tm,
6430 bld_base->base.gallivm->module,
6431 debug, PIPE_SHADER_GEOMETRY,
6432 "GS Copy Shader");
6433 if (!r) {
6434 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6435 fprintf(stderr, "GS Copy Shader:\n");
6436 si_shader_dump(sscreen, ctx.shader, debug,
6437 PIPE_SHADER_GEOMETRY, stderr);
6438 r = si_shader_binary_upload(sscreen, ctx.shader);
6439 }
6440
6441 si_llvm_dispose(&ctx);
6442
6443 FREE(outputs);
6444
6445 if (r != 0) {
6446 FREE(shader);
6447 shader = NULL;
6448 }
6449 return shader;
6450 }
6451
6452 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
6453 FILE *f)
6454 {
6455 int i;
6456
6457 fprintf(f, "SHADER KEY\n");
6458
6459 switch (shader) {
6460 case PIPE_SHADER_VERTEX:
6461 fprintf(f, " part.vs.prolog.instance_divisors = {");
6462 for (i = 0; i < ARRAY_SIZE(key->part.vs.prolog.instance_divisors); i++)
6463 fprintf(f, !i ? "%u" : ", %u",
6464 key->part.vs.prolog.instance_divisors[i]);
6465 fprintf(f, "}\n");
6466 fprintf(f, " part.vs.epilog.export_prim_id = %u\n", key->part.vs.epilog.export_prim_id);
6467 fprintf(f, " as_es = %u\n", key->as_es);
6468 fprintf(f, " as_ls = %u\n", key->as_ls);
6469 fprintf(f, " mono.vs.fix_fetch = 0x%x\n", key->mono.vs.fix_fetch);
6470 break;
6471
6472 case PIPE_SHADER_TESS_CTRL:
6473 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
6474 fprintf(f, " mono.tcs.inputs_to_copy = 0x%"PRIx64"\n", key->mono.tcs.inputs_to_copy);
6475 break;
6476
6477 case PIPE_SHADER_TESS_EVAL:
6478 fprintf(f, " part.tes.epilog.export_prim_id = %u\n", key->part.tes.epilog.export_prim_id);
6479 fprintf(f, " as_es = %u\n", key->as_es);
6480 break;
6481
6482 case PIPE_SHADER_GEOMETRY:
6483 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
6484 break;
6485
6486 case PIPE_SHADER_COMPUTE:
6487 break;
6488
6489 case PIPE_SHADER_FRAGMENT:
6490 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
6491 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
6492 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
6493 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
6494 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
6495 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
6496 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
6497 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
6498 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
6499 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
6500 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
6501 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
6502 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
6503 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
6504 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
6505 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
6506 break;
6507
6508 default:
6509 assert(0);
6510 }
6511
6512 if ((shader == PIPE_SHADER_GEOMETRY ||
6513 shader == PIPE_SHADER_TESS_EVAL ||
6514 shader == PIPE_SHADER_VERTEX) &&
6515 !key->as_es && !key->as_ls) {
6516 fprintf(f, " opt.hw_vs.kill_outputs = 0x%"PRIx64"\n", key->opt.hw_vs.kill_outputs);
6517 fprintf(f, " opt.hw_vs.kill_outputs2 = 0x%x\n", key->opt.hw_vs.kill_outputs2);
6518 fprintf(f, " opt.hw_vs.clip_disable = %u\n", key->opt.hw_vs.clip_disable);
6519 }
6520 }
6521
6522 static void si_init_shader_ctx(struct si_shader_context *ctx,
6523 struct si_screen *sscreen,
6524 struct si_shader *shader,
6525 LLVMTargetMachineRef tm)
6526 {
6527 struct lp_build_tgsi_context *bld_base;
6528 struct lp_build_tgsi_action tmpl = {};
6529
6530 si_llvm_context_init(ctx, sscreen, shader, tm,
6531 (shader && shader->selector) ? &shader->selector->info : NULL,
6532 (shader && shader->selector) ? shader->selector->tokens : NULL);
6533
6534 bld_base = &ctx->soa.bld_base;
6535 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6536
6537 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6538 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6539 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6540
6541 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6542 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6543 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6544 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6545 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6546 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6547 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6548 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6549 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6550 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6551 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6552 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6553 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6554 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6555
6556 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6557 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6558 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6559 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6560 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6561 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6562
6563 tmpl.fetch_args = atomic_fetch_args;
6564 tmpl.emit = atomic_emit;
6565 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6566 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6567 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6568 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6569 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6570 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6571 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6572 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6573 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6574 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6575 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6576 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6577 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6578 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6579 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6580 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6581 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6582 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6583 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6584 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6585
6586 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6587
6588 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6589 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6590 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6591 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6592
6593 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6594 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6595 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6596 }
6597
6598 /* Return true if the PARAM export has been eliminated. */
6599 static bool si_eliminate_const_output(struct si_shader_context *ctx,
6600 LLVMValueRef inst, unsigned offset)
6601 {
6602 struct si_shader *shader = ctx->shader;
6603 unsigned num_outputs = shader->selector->info.num_outputs;
6604 unsigned i, default_val; /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL */
6605 bool is_zero[4] = {}, is_one[4] = {};
6606
6607 for (i = 0; i < 4; i++) {
6608 LLVMBool loses_info;
6609 LLVMValueRef p = LLVMGetOperand(inst, 5 + i);
6610
6611 /* It's a constant expression. Undef outputs are eliminated too. */
6612 if (LLVMIsUndef(p)) {
6613 is_zero[i] = true;
6614 is_one[i] = true;
6615 } else if (LLVMIsAConstantFP(p)) {
6616 double a = LLVMConstRealGetDouble(p, &loses_info);
6617
6618 if (a == 0)
6619 is_zero[i] = true;
6620 else if (a == 1)
6621 is_one[i] = true;
6622 else
6623 return false; /* other constant */
6624 } else
6625 return false;
6626 }
6627
6628 /* Only certain combinations of 0 and 1 can be eliminated. */
6629 if (is_zero[0] && is_zero[1] && is_zero[2])
6630 default_val = is_zero[3] ? 0 : 1;
6631 else if (is_one[0] && is_one[1] && is_one[2])
6632 default_val = is_zero[3] ? 2 : 3;
6633 else
6634 return false;
6635
6636 /* The PARAM export can be represented as DEFAULT_VAL. Kill it. */
6637 LLVMInstructionEraseFromParent(inst);
6638
6639 /* Change OFFSET to DEFAULT_VAL. */
6640 for (i = 0; i < num_outputs; i++) {
6641 if (shader->info.vs_output_param_offset[i] == offset) {
6642 shader->info.vs_output_param_offset[i] =
6643 EXP_PARAM_DEFAULT_VAL_0000 + default_val;
6644 break;
6645 }
6646 }
6647 return true;
6648 }
6649
6650 struct si_vs_exports {
6651 unsigned num;
6652 unsigned offset[SI_MAX_VS_OUTPUTS];
6653 LLVMValueRef inst[SI_MAX_VS_OUTPUTS];
6654 };
6655
6656 static void si_eliminate_const_vs_outputs(struct si_shader_context *ctx)
6657 {
6658 struct si_shader *shader = ctx->shader;
6659 struct tgsi_shader_info *info = &shader->selector->info;
6660 LLVMBasicBlockRef bb;
6661 struct si_vs_exports exports;
6662 bool removed_any = false;
6663
6664 exports.num = 0;
6665
6666 if (ctx->type == PIPE_SHADER_FRAGMENT ||
6667 ctx->type == PIPE_SHADER_COMPUTE ||
6668 shader->key.as_es ||
6669 shader->key.as_ls)
6670 return;
6671
6672 /* Process all LLVM instructions. */
6673 bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6674 while (bb) {
6675 LLVMValueRef inst = LLVMGetFirstInstruction(bb);
6676
6677 while (inst) {
6678 LLVMValueRef cur = inst;
6679 inst = LLVMGetNextInstruction(inst);
6680
6681 if (LLVMGetInstructionOpcode(cur) != LLVMCall)
6682 continue;
6683
6684 LLVMValueRef callee = lp_get_called_value(cur);
6685
6686 if (!lp_is_function(callee))
6687 continue;
6688
6689 const char *name = LLVMGetValueName(callee);
6690 unsigned num_args = LLVMCountParams(callee);
6691
6692 /* Check if this is an export instruction. */
6693 if (num_args != 9 || strcmp(name, "llvm.SI.export"))
6694 continue;
6695
6696 LLVMValueRef arg = LLVMGetOperand(cur, 3);
6697 unsigned target = LLVMConstIntGetZExtValue(arg);
6698
6699 if (target < V_008DFC_SQ_EXP_PARAM)
6700 continue;
6701
6702 target -= V_008DFC_SQ_EXP_PARAM;
6703
6704 /* Eliminate constant value PARAM exports. */
6705 if (si_eliminate_const_output(ctx, cur, target)) {
6706 removed_any = true;
6707 } else {
6708 exports.offset[exports.num] = target;
6709 exports.inst[exports.num] = cur;
6710 exports.num++;
6711 }
6712 }
6713 bb = LLVMGetNextBasicBlock(bb);
6714 }
6715
6716 /* Remove holes in export memory due to removed PARAM exports.
6717 * This is done by renumbering all PARAM exports.
6718 */
6719 if (removed_any) {
6720 ubyte current_offset[SI_MAX_VS_OUTPUTS];
6721 unsigned new_count = 0;
6722 unsigned out, i;
6723
6724 /* Make a copy of the offsets. We need the old version while
6725 * we are modifying some of them. */
6726 assert(sizeof(current_offset) ==
6727 sizeof(shader->info.vs_output_param_offset));
6728 memcpy(current_offset, shader->info.vs_output_param_offset,
6729 sizeof(current_offset));
6730
6731 for (i = 0; i < exports.num; i++) {
6732 unsigned offset = exports.offset[i];
6733
6734 for (out = 0; out < info->num_outputs; out++) {
6735 if (current_offset[out] != offset)
6736 continue;
6737
6738 LLVMSetOperand(exports.inst[i], 3,
6739 LLVMConstInt(ctx->i32,
6740 V_008DFC_SQ_EXP_PARAM + new_count, 0));
6741 shader->info.vs_output_param_offset[out] = new_count;
6742 new_count++;
6743 break;
6744 }
6745 }
6746 shader->info.nr_param_exports = new_count;
6747 }
6748 }
6749
6750 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
6751 {
6752 ctx->shader->config.private_mem_vgprs = 0;
6753
6754 /* Process all LLVM instructions. */
6755 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6756 while (bb) {
6757 LLVMValueRef next = LLVMGetFirstInstruction(bb);
6758
6759 while (next) {
6760 LLVMValueRef inst = next;
6761 next = LLVMGetNextInstruction(next);
6762
6763 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
6764 continue;
6765
6766 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
6767 /* No idea why LLVM aligns allocas to 4 elements. */
6768 unsigned alignment = LLVMGetAlignment(inst);
6769 unsigned dw_size = align(llvm_get_type_size(type) / 4, alignment);
6770 ctx->shader->config.private_mem_vgprs += dw_size;
6771 }
6772 bb = LLVMGetNextBasicBlock(bb);
6773 }
6774 }
6775
6776 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
6777 struct si_shader *shader)
6778 {
6779 struct si_shader_selector *sel = shader->selector;
6780 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
6781
6782 switch (ctx->type) {
6783 case PIPE_SHADER_VERTEX:
6784 ctx->load_input = declare_input_vs;
6785 if (shader->key.as_ls)
6786 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6787 else if (shader->key.as_es)
6788 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6789 else
6790 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6791 break;
6792 case PIPE_SHADER_TESS_CTRL:
6793 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6794 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6795 bld_base->emit_store = store_output_tcs;
6796 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6797 break;
6798 case PIPE_SHADER_TESS_EVAL:
6799 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6800 if (shader->key.as_es)
6801 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6802 else
6803 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6804 break;
6805 case PIPE_SHADER_GEOMETRY:
6806 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6807 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6808 break;
6809 case PIPE_SHADER_FRAGMENT:
6810 ctx->load_input = declare_input_fs;
6811 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6812 break;
6813 case PIPE_SHADER_COMPUTE:
6814 ctx->declare_memory_region = declare_compute_memory;
6815 break;
6816 default:
6817 assert(!"Unsupported shader type");
6818 return false;
6819 }
6820
6821 create_meta_data(ctx);
6822 create_function(ctx);
6823 preload_ring_buffers(ctx);
6824
6825 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6826 int i;
6827 for (i = 0; i < 4; i++) {
6828 ctx->gs_next_vertex[i] =
6829 lp_build_alloca(bld_base->base.gallivm,
6830 ctx->i32, "");
6831 }
6832 }
6833
6834 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6835 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6836 return false;
6837 }
6838
6839 si_llvm_build_ret(ctx, ctx->return_value);
6840 return true;
6841 }
6842
6843 /**
6844 * Compute the VS prolog key, which contains all the information needed to
6845 * build the VS prolog function, and set shader->info bits where needed.
6846 */
6847 static void si_get_vs_prolog_key(struct si_shader *shader,
6848 union si_shader_part_key *key)
6849 {
6850 struct tgsi_shader_info *info = &shader->selector->info;
6851
6852 memset(key, 0, sizeof(*key));
6853 key->vs_prolog.states = shader->key.part.vs.prolog;
6854 key->vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6855 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6856
6857 /* Set the instanceID flag. */
6858 for (unsigned i = 0; i < info->num_inputs; i++)
6859 if (key->vs_prolog.states.instance_divisors[i])
6860 shader->info.uses_instanceid = true;
6861 }
6862
6863 /**
6864 * Compute the VS epilog key, which contains all the information needed to
6865 * build the VS epilog function, and set the PrimitiveID output offset.
6866 */
6867 static void si_get_vs_epilog_key(struct si_shader *shader,
6868 struct si_vs_epilog_bits *states,
6869 union si_shader_part_key *key)
6870 {
6871 memset(key, 0, sizeof(*key));
6872 key->vs_epilog.states = *states;
6873
6874 /* Set up the PrimitiveID output. */
6875 if (shader->key.part.vs.epilog.export_prim_id) {
6876 unsigned index = shader->selector->info.num_outputs;
6877 unsigned offset = shader->info.nr_param_exports++;
6878
6879 key->vs_epilog.prim_id_param_offset = offset;
6880 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
6881 shader->info.vs_output_param_offset[index] = offset;
6882 }
6883 }
6884
6885 /**
6886 * Compute the PS prolog key, which contains all the information needed to
6887 * build the PS prolog function, and set related bits in shader->config.
6888 */
6889 static void si_get_ps_prolog_key(struct si_shader *shader,
6890 union si_shader_part_key *key,
6891 bool separate_prolog)
6892 {
6893 struct tgsi_shader_info *info = &shader->selector->info;
6894
6895 memset(key, 0, sizeof(*key));
6896 key->ps_prolog.states = shader->key.part.ps.prolog;
6897 key->ps_prolog.colors_read = info->colors_read;
6898 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6899 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6900 key->ps_prolog.wqm = info->uses_derivatives &&
6901 (key->ps_prolog.colors_read ||
6902 key->ps_prolog.states.force_persp_sample_interp ||
6903 key->ps_prolog.states.force_linear_sample_interp ||
6904 key->ps_prolog.states.force_persp_center_interp ||
6905 key->ps_prolog.states.force_linear_center_interp ||
6906 key->ps_prolog.states.bc_optimize_for_persp ||
6907 key->ps_prolog.states.bc_optimize_for_linear);
6908
6909 if (info->colors_read) {
6910 unsigned *color = shader->selector->color_attr_index;
6911
6912 if (shader->key.part.ps.prolog.color_two_side) {
6913 /* BCOLORs are stored after the last input. */
6914 key->ps_prolog.num_interp_inputs = info->num_inputs;
6915 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6916 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6917 }
6918
6919 for (unsigned i = 0; i < 2; i++) {
6920 unsigned interp = info->input_interpolate[color[i]];
6921 unsigned location = info->input_interpolate_loc[color[i]];
6922
6923 if (!(info->colors_read & (0xf << i*4)))
6924 continue;
6925
6926 key->ps_prolog.color_attr_index[i] = color[i];
6927
6928 if (shader->key.part.ps.prolog.flatshade_colors &&
6929 interp == TGSI_INTERPOLATE_COLOR)
6930 interp = TGSI_INTERPOLATE_CONSTANT;
6931
6932 switch (interp) {
6933 case TGSI_INTERPOLATE_CONSTANT:
6934 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6935 break;
6936 case TGSI_INTERPOLATE_PERSPECTIVE:
6937 case TGSI_INTERPOLATE_COLOR:
6938 /* Force the interpolation location for colors here. */
6939 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6940 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6941 if (shader->key.part.ps.prolog.force_persp_center_interp)
6942 location = TGSI_INTERPOLATE_LOC_CENTER;
6943
6944 switch (location) {
6945 case TGSI_INTERPOLATE_LOC_SAMPLE:
6946 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6947 shader->config.spi_ps_input_ena |=
6948 S_0286CC_PERSP_SAMPLE_ENA(1);
6949 break;
6950 case TGSI_INTERPOLATE_LOC_CENTER:
6951 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6952 shader->config.spi_ps_input_ena |=
6953 S_0286CC_PERSP_CENTER_ENA(1);
6954 break;
6955 case TGSI_INTERPOLATE_LOC_CENTROID:
6956 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6957 shader->config.spi_ps_input_ena |=
6958 S_0286CC_PERSP_CENTROID_ENA(1);
6959 break;
6960 default:
6961 assert(0);
6962 }
6963 break;
6964 case TGSI_INTERPOLATE_LINEAR:
6965 /* Force the interpolation location for colors here. */
6966 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6967 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6968 if (shader->key.part.ps.prolog.force_linear_center_interp)
6969 location = TGSI_INTERPOLATE_LOC_CENTER;
6970
6971 /* The VGPR assignment for non-monolithic shaders
6972 * works because InitialPSInputAddr is set on the
6973 * main shader and PERSP_PULL_MODEL is never used.
6974 */
6975 switch (location) {
6976 case TGSI_INTERPOLATE_LOC_SAMPLE:
6977 key->ps_prolog.color_interp_vgpr_index[i] =
6978 separate_prolog ? 6 : 9;
6979 shader->config.spi_ps_input_ena |=
6980 S_0286CC_LINEAR_SAMPLE_ENA(1);
6981 break;
6982 case TGSI_INTERPOLATE_LOC_CENTER:
6983 key->ps_prolog.color_interp_vgpr_index[i] =
6984 separate_prolog ? 8 : 11;
6985 shader->config.spi_ps_input_ena |=
6986 S_0286CC_LINEAR_CENTER_ENA(1);
6987 break;
6988 case TGSI_INTERPOLATE_LOC_CENTROID:
6989 key->ps_prolog.color_interp_vgpr_index[i] =
6990 separate_prolog ? 10 : 13;
6991 shader->config.spi_ps_input_ena |=
6992 S_0286CC_LINEAR_CENTROID_ENA(1);
6993 break;
6994 default:
6995 assert(0);
6996 }
6997 break;
6998 default:
6999 assert(0);
7000 }
7001 }
7002 }
7003 }
7004
7005 /**
7006 * Check whether a PS prolog is required based on the key.
7007 */
7008 static bool si_need_ps_prolog(const union si_shader_part_key *key)
7009 {
7010 return key->ps_prolog.colors_read ||
7011 key->ps_prolog.states.force_persp_sample_interp ||
7012 key->ps_prolog.states.force_linear_sample_interp ||
7013 key->ps_prolog.states.force_persp_center_interp ||
7014 key->ps_prolog.states.force_linear_center_interp ||
7015 key->ps_prolog.states.bc_optimize_for_persp ||
7016 key->ps_prolog.states.bc_optimize_for_linear ||
7017 key->ps_prolog.states.poly_stipple;
7018 }
7019
7020 /**
7021 * Compute the PS epilog key, which contains all the information needed to
7022 * build the PS epilog function.
7023 */
7024 static void si_get_ps_epilog_key(struct si_shader *shader,
7025 union si_shader_part_key *key)
7026 {
7027 struct tgsi_shader_info *info = &shader->selector->info;
7028 memset(key, 0, sizeof(*key));
7029 key->ps_epilog.colors_written = info->colors_written;
7030 key->ps_epilog.writes_z = info->writes_z;
7031 key->ps_epilog.writes_stencil = info->writes_stencil;
7032 key->ps_epilog.writes_samplemask = info->writes_samplemask;
7033 key->ps_epilog.states = shader->key.part.ps.epilog;
7034 }
7035
7036 /**
7037 * Build the GS prolog function. Rotate the input vertices for triangle strips
7038 * with adjacency.
7039 */
7040 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
7041 union si_shader_part_key *key)
7042 {
7043 const unsigned num_sgprs = SI_GS_NUM_USER_SGPR + 2;
7044 const unsigned num_vgprs = 8;
7045 struct gallivm_state *gallivm = &ctx->gallivm;
7046 LLVMBuilderRef builder = gallivm->builder;
7047 LLVMTypeRef params[32];
7048 LLVMTypeRef returns[32];
7049 LLVMValueRef func, ret;
7050
7051 for (unsigned i = 0; i < num_sgprs; ++i) {
7052 params[i] = ctx->i32;
7053 returns[i] = ctx->i32;
7054 }
7055
7056 for (unsigned i = 0; i < num_vgprs; ++i) {
7057 params[num_sgprs + i] = ctx->i32;
7058 returns[num_sgprs + i] = ctx->f32;
7059 }
7060
7061 /* Create the function. */
7062 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
7063 params, num_sgprs + num_vgprs, num_sgprs - 1);
7064 func = ctx->main_fn;
7065
7066 /* Copy inputs to outputs. This should be no-op, as the registers match,
7067 * but it will prevent the compiler from overwriting them unintentionally.
7068 */
7069 ret = ctx->return_value;
7070 for (unsigned i = 0; i < num_sgprs; i++) {
7071 LLVMValueRef p = LLVMGetParam(func, i);
7072 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
7073 }
7074 for (unsigned i = 0; i < num_vgprs; i++) {
7075 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
7076 p = LLVMBuildBitCast(builder, p, ctx->f32, "");
7077 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
7078 }
7079
7080 if (key->gs_prolog.states.tri_strip_adj_fix) {
7081 /* Remap the input vertices for every other primitive. */
7082 const unsigned vtx_params[6] = {
7083 num_sgprs,
7084 num_sgprs + 1,
7085 num_sgprs + 3,
7086 num_sgprs + 4,
7087 num_sgprs + 5,
7088 num_sgprs + 6
7089 };
7090 LLVMValueRef prim_id, rotate;
7091
7092 prim_id = LLVMGetParam(func, num_sgprs + 2);
7093 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
7094
7095 for (unsigned i = 0; i < 6; ++i) {
7096 LLVMValueRef base, rotated, actual;
7097 base = LLVMGetParam(func, vtx_params[i]);
7098 rotated = LLVMGetParam(func, vtx_params[(i + 4) % 6]);
7099 actual = LLVMBuildSelect(builder, rotate, rotated, base, "");
7100 actual = LLVMBuildBitCast(builder, actual, ctx->f32, "");
7101 ret = LLVMBuildInsertValue(builder, ret, actual, vtx_params[i], "");
7102 }
7103 }
7104
7105 LLVMBuildRet(builder, ret);
7106 }
7107
7108 /**
7109 * Given a list of shader part functions, build a wrapper function that
7110 * runs them in sequence to form a monolithic shader.
7111 */
7112 static void si_build_wrapper_function(struct si_shader_context *ctx,
7113 LLVMValueRef *parts,
7114 unsigned num_parts,
7115 unsigned main_part)
7116 {
7117 struct gallivm_state *gallivm = &ctx->gallivm;
7118 LLVMBuilderRef builder = ctx->gallivm.builder;
7119 /* PS epilog has one arg per color component */
7120 LLVMTypeRef param_types[48];
7121 LLVMValueRef out[48];
7122 LLVMTypeRef function_type;
7123 unsigned num_params;
7124 unsigned num_out;
7125 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
7126 unsigned num_sgprs, num_vgprs;
7127 unsigned last_sgpr_param;
7128 unsigned gprs;
7129
7130 for (unsigned i = 0; i < num_parts; ++i) {
7131 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
7132 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
7133 }
7134
7135 /* The parameters of the wrapper function correspond to those of the
7136 * first part in terms of SGPRs and VGPRs, but we use the types of the
7137 * main part to get the right types. This is relevant for the
7138 * dereferenceable attribute on descriptor table pointers.
7139 */
7140 num_sgprs = 0;
7141 num_vgprs = 0;
7142
7143 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
7144 num_params = LLVMCountParamTypes(function_type);
7145
7146 for (unsigned i = 0; i < num_params; ++i) {
7147 LLVMValueRef param = LLVMGetParam(parts[0], i);
7148
7149 if (ac_is_sgpr_param(param)) {
7150 assert(num_vgprs == 0);
7151 num_sgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
7152 } else {
7153 num_vgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
7154 }
7155 }
7156 assert(num_vgprs + num_sgprs <= ARRAY_SIZE(param_types));
7157
7158 num_params = 0;
7159 last_sgpr_param = 0;
7160 gprs = 0;
7161 while (gprs < num_sgprs + num_vgprs) {
7162 LLVMValueRef param = LLVMGetParam(parts[main_part], num_params);
7163 unsigned size;
7164
7165 param_types[num_params] = LLVMTypeOf(param);
7166 if (gprs < num_sgprs)
7167 last_sgpr_param = num_params;
7168 size = llvm_get_type_size(param_types[num_params]) / 4;
7169 num_params++;
7170
7171 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
7172 assert(gprs + size <= num_sgprs + num_vgprs &&
7173 (gprs >= num_sgprs || gprs + size <= num_sgprs));
7174
7175 gprs += size;
7176 }
7177
7178 si_create_function(ctx, "wrapper", NULL, 0, param_types, num_params, last_sgpr_param);
7179
7180 /* Record the arguments of the function as if they were an output of
7181 * a previous part.
7182 */
7183 num_out = 0;
7184 num_out_sgpr = 0;
7185
7186 for (unsigned i = 0; i < num_params; ++i) {
7187 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
7188 LLVMTypeRef param_type = LLVMTypeOf(param);
7189 LLVMTypeRef out_type = i <= last_sgpr_param ? ctx->i32 : ctx->f32;
7190 unsigned size = llvm_get_type_size(param_type) / 4;
7191
7192 if (size == 1) {
7193 if (param_type != out_type)
7194 param = LLVMBuildBitCast(builder, param, out_type, "");
7195 out[num_out++] = param;
7196 } else {
7197 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
7198
7199 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7200 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
7201 param_type = ctx->i64;
7202 }
7203
7204 if (param_type != vector_type)
7205 param = LLVMBuildBitCast(builder, param, vector_type, "");
7206
7207 for (unsigned j = 0; j < size; ++j)
7208 out[num_out++] = LLVMBuildExtractElement(
7209 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
7210 }
7211
7212 if (i <= last_sgpr_param)
7213 num_out_sgpr = num_out;
7214 }
7215
7216 /* Now chain the parts. */
7217 for (unsigned part = 0; part < num_parts; ++part) {
7218 LLVMValueRef in[48];
7219 LLVMValueRef ret;
7220 LLVMTypeRef ret_type;
7221 unsigned out_idx = 0;
7222
7223 num_params = LLVMCountParams(parts[part]);
7224 assert(num_params <= ARRAY_SIZE(param_types));
7225
7226 /* Derive arguments for the next part from outputs of the
7227 * previous one.
7228 */
7229 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
7230 LLVMValueRef param;
7231 LLVMTypeRef param_type;
7232 bool is_sgpr;
7233 unsigned param_size;
7234 LLVMValueRef arg = NULL;
7235
7236 param = LLVMGetParam(parts[part], param_idx);
7237 param_type = LLVMTypeOf(param);
7238 param_size = llvm_get_type_size(param_type) / 4;
7239 is_sgpr = ac_is_sgpr_param(param);
7240
7241 if (is_sgpr) {
7242 #if HAVE_LLVM < 0x0400
7243 LLVMRemoveAttribute(param, LLVMByValAttribute);
7244 #else
7245 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
7246 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
7247 #endif
7248 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
7249 }
7250
7251 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
7252 assert(is_sgpr || out_idx >= num_out_sgpr);
7253
7254 if (param_size == 1)
7255 arg = out[out_idx];
7256 else
7257 arg = lp_build_gather_values(gallivm, &out[out_idx], param_size);
7258
7259 if (LLVMTypeOf(arg) != param_type) {
7260 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7261 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
7262 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
7263 } else {
7264 arg = LLVMBuildBitCast(builder, arg, param_type, "");
7265 }
7266 }
7267
7268 in[param_idx] = arg;
7269 out_idx += param_size;
7270 }
7271
7272 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
7273 ret_type = LLVMTypeOf(ret);
7274
7275 /* Extract the returned GPRs. */
7276 num_out = 0;
7277 num_out_sgpr = 0;
7278
7279 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
7280 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
7281
7282 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
7283
7284 for (unsigned i = 0; i < ret_size; ++i) {
7285 LLVMValueRef val =
7286 LLVMBuildExtractValue(builder, ret, i, "");
7287
7288 out[num_out++] = val;
7289
7290 if (LLVMTypeOf(val) == ctx->i32) {
7291 assert(num_out_sgpr + 1 == num_out);
7292 num_out_sgpr = num_out;
7293 }
7294 }
7295 }
7296 }
7297
7298 LLVMBuildRetVoid(builder);
7299 }
7300
7301 int si_compile_tgsi_shader(struct si_screen *sscreen,
7302 LLVMTargetMachineRef tm,
7303 struct si_shader *shader,
7304 bool is_monolithic,
7305 struct pipe_debug_callback *debug)
7306 {
7307 struct si_shader_selector *sel = shader->selector;
7308 struct si_shader_context ctx;
7309 struct lp_build_tgsi_context *bld_base;
7310 LLVMModuleRef mod;
7311 int r = -1;
7312
7313 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
7314 * conversion fails. */
7315 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
7316 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
7317 tgsi_dump(sel->tokens, 0);
7318 si_dump_streamout(&sel->so);
7319 }
7320
7321 si_init_shader_ctx(&ctx, sscreen, shader, tm);
7322 ctx.separate_prolog = !is_monolithic;
7323
7324 memset(shader->info.vs_output_param_offset, EXP_PARAM_UNDEFINED,
7325 sizeof(shader->info.vs_output_param_offset));
7326
7327 shader->info.uses_instanceid = sel->info.uses_instanceid;
7328
7329 bld_base = &ctx.soa.bld_base;
7330 ctx.load_system_value = declare_system_value;
7331
7332 if (!si_compile_tgsi_main(&ctx, shader)) {
7333 si_llvm_dispose(&ctx);
7334 return -1;
7335 }
7336
7337 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
7338 LLVMValueRef parts[3];
7339 bool need_prolog;
7340 bool need_epilog;
7341
7342 need_prolog = sel->info.num_inputs;
7343 need_epilog = !shader->key.as_es && !shader->key.as_ls;
7344
7345 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7346
7347 if (need_prolog) {
7348 union si_shader_part_key prolog_key;
7349 si_get_vs_prolog_key(shader, &prolog_key);
7350 si_build_vs_prolog_function(&ctx, &prolog_key);
7351 parts[0] = ctx.main_fn;
7352 }
7353
7354 if (need_epilog) {
7355 union si_shader_part_key epilog_key;
7356 si_get_vs_epilog_key(shader, &shader->key.part.vs.epilog, &epilog_key);
7357 si_build_vs_epilog_function(&ctx, &epilog_key);
7358 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7359 }
7360
7361 si_build_wrapper_function(&ctx, parts, 1 + need_prolog + need_epilog,
7362 need_prolog ? 1 : 0);
7363 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
7364 LLVMValueRef parts[2];
7365 union si_shader_part_key epilog_key;
7366
7367 parts[0] = ctx.main_fn;
7368
7369 memset(&epilog_key, 0, sizeof(epilog_key));
7370 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7371 si_build_tcs_epilog_function(&ctx, &epilog_key);
7372 parts[1] = ctx.main_fn;
7373
7374 si_build_wrapper_function(&ctx, parts, 2, 0);
7375 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_EVAL &&
7376 !shader->key.as_es) {
7377 LLVMValueRef parts[2];
7378 union si_shader_part_key epilog_key;
7379
7380 parts[0] = ctx.main_fn;
7381
7382 si_get_vs_epilog_key(shader, &shader->key.part.tes.epilog, &epilog_key);
7383 si_build_vs_epilog_function(&ctx, &epilog_key);
7384 parts[1] = ctx.main_fn;
7385
7386 si_build_wrapper_function(&ctx, parts, 2, 0);
7387 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
7388 LLVMValueRef parts[2];
7389 union si_shader_part_key prolog_key;
7390
7391 parts[1] = ctx.main_fn;
7392
7393 memset(&prolog_key, 0, sizeof(prolog_key));
7394 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7395 si_build_gs_prolog_function(&ctx, &prolog_key);
7396 parts[0] = ctx.main_fn;
7397
7398 si_build_wrapper_function(&ctx, parts, 2, 1);
7399 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
7400 LLVMValueRef parts[3];
7401 union si_shader_part_key prolog_key;
7402 union si_shader_part_key epilog_key;
7403 bool need_prolog;
7404
7405 si_get_ps_prolog_key(shader, &prolog_key, false);
7406 need_prolog = si_need_ps_prolog(&prolog_key);
7407
7408 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7409
7410 if (need_prolog) {
7411 si_build_ps_prolog_function(&ctx, &prolog_key);
7412 parts[0] = ctx.main_fn;
7413 }
7414
7415 si_get_ps_epilog_key(shader, &epilog_key);
7416 si_build_ps_epilog_function(&ctx, &epilog_key);
7417 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7418
7419 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2, need_prolog ? 1 : 0);
7420 }
7421
7422 mod = bld_base->base.gallivm->module;
7423
7424 /* Dump LLVM IR before any optimization passes */
7425 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
7426 r600_can_dump_shader(&sscreen->b, ctx.type))
7427 LLVMDumpModule(mod);
7428
7429 si_llvm_finalize_module(&ctx,
7430 r600_extra_shader_checks(&sscreen->b, ctx.type));
7431
7432 /* Post-optimization transformations and analysis. */
7433 si_eliminate_const_vs_outputs(&ctx);
7434
7435 if ((debug && debug->debug_message) ||
7436 r600_can_dump_shader(&sscreen->b, ctx.type))
7437 si_count_scratch_private_memory(&ctx);
7438
7439 /* Compile to bytecode. */
7440 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
7441 mod, debug, ctx.type, "TGSI shader");
7442 si_llvm_dispose(&ctx);
7443 if (r) {
7444 fprintf(stderr, "LLVM failed to compile shader\n");
7445 return r;
7446 }
7447
7448 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
7449 * LLVM 3.9svn has this bug.
7450 */
7451 if (sel->type == PIPE_SHADER_COMPUTE) {
7452 unsigned wave_size = 64;
7453 unsigned max_vgprs = 256;
7454 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
7455 unsigned max_sgprs_per_wave = 128;
7456 unsigned max_block_threads = si_get_max_workgroup_size(shader);
7457 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
7458 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
7459
7460 max_vgprs = max_vgprs / min_waves_per_simd;
7461 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
7462
7463 if (shader->config.num_sgprs > max_sgprs ||
7464 shader->config.num_vgprs > max_vgprs) {
7465 fprintf(stderr, "LLVM failed to compile a shader correctly: "
7466 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7467 shader->config.num_sgprs, shader->config.num_vgprs,
7468 max_sgprs, max_vgprs);
7469
7470 /* Just terminate the process, because dependent
7471 * shaders can hang due to bad input data, but use
7472 * the env var to allow shader-db to work.
7473 */
7474 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7475 abort();
7476 }
7477 }
7478
7479 /* Add the scratch offset to input SGPRs. */
7480 if (shader->config.scratch_bytes_per_wave)
7481 shader->info.num_input_sgprs += 1; /* scratch byte offset */
7482
7483 /* Calculate the number of fragment input VGPRs. */
7484 if (ctx.type == PIPE_SHADER_FRAGMENT) {
7485 shader->info.num_input_vgprs = 0;
7486 shader->info.face_vgpr_index = -1;
7487
7488 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7489 shader->info.num_input_vgprs += 2;
7490 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
7491 shader->info.num_input_vgprs += 2;
7492 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
7493 shader->info.num_input_vgprs += 2;
7494 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
7495 shader->info.num_input_vgprs += 3;
7496 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7497 shader->info.num_input_vgprs += 2;
7498 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7499 shader->info.num_input_vgprs += 2;
7500 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7501 shader->info.num_input_vgprs += 2;
7502 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7503 shader->info.num_input_vgprs += 1;
7504 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7505 shader->info.num_input_vgprs += 1;
7506 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7507 shader->info.num_input_vgprs += 1;
7508 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7509 shader->info.num_input_vgprs += 1;
7510 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7511 shader->info.num_input_vgprs += 1;
7512 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7513 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7514 shader->info.num_input_vgprs += 1;
7515 }
7516 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
7517 shader->info.num_input_vgprs += 1;
7518 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7519 shader->info.num_input_vgprs += 1;
7520 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7521 shader->info.num_input_vgprs += 1;
7522 }
7523
7524 return 0;
7525 }
7526
7527 /**
7528 * Create, compile and return a shader part (prolog or epilog).
7529 *
7530 * \param sscreen screen
7531 * \param list list of shader parts of the same category
7532 * \param type shader type
7533 * \param key shader part key
7534 * \param prolog whether the part being requested is a prolog
7535 * \param tm LLVM target machine
7536 * \param debug debug callback
7537 * \param build the callback responsible for building the main function
7538 * \return non-NULL on success
7539 */
7540 static struct si_shader_part *
7541 si_get_shader_part(struct si_screen *sscreen,
7542 struct si_shader_part **list,
7543 enum pipe_shader_type type,
7544 bool prolog,
7545 union si_shader_part_key *key,
7546 LLVMTargetMachineRef tm,
7547 struct pipe_debug_callback *debug,
7548 void (*build)(struct si_shader_context *,
7549 union si_shader_part_key *),
7550 const char *name)
7551 {
7552 struct si_shader_part *result;
7553
7554 pipe_mutex_lock(sscreen->shader_parts_mutex);
7555
7556 /* Find existing. */
7557 for (result = *list; result; result = result->next) {
7558 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7559 pipe_mutex_unlock(sscreen->shader_parts_mutex);
7560 return result;
7561 }
7562 }
7563
7564 /* Compile a new one. */
7565 result = CALLOC_STRUCT(si_shader_part);
7566 result->key = *key;
7567
7568 struct si_shader shader = {};
7569 struct si_shader_context ctx;
7570 struct gallivm_state *gallivm = &ctx.gallivm;
7571
7572 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7573 ctx.type = type;
7574
7575 switch (type) {
7576 case PIPE_SHADER_VERTEX:
7577 break;
7578 case PIPE_SHADER_TESS_CTRL:
7579 assert(!prolog);
7580 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7581 break;
7582 case PIPE_SHADER_GEOMETRY:
7583 assert(prolog);
7584 break;
7585 case PIPE_SHADER_FRAGMENT:
7586 if (prolog)
7587 shader.key.part.ps.prolog = key->ps_prolog.states;
7588 else
7589 shader.key.part.ps.epilog = key->ps_epilog.states;
7590 break;
7591 default:
7592 unreachable("bad shader part");
7593 }
7594
7595 build(&ctx, key);
7596
7597 /* Compile. */
7598 si_llvm_finalize_module(&ctx,
7599 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT));
7600
7601 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7602 gallivm->module, debug, ctx.type, name)) {
7603 FREE(result);
7604 result = NULL;
7605 goto out;
7606 }
7607
7608 result->next = *list;
7609 *list = result;
7610
7611 out:
7612 si_llvm_dispose(&ctx);
7613 pipe_mutex_unlock(sscreen->shader_parts_mutex);
7614 return result;
7615 }
7616
7617 /**
7618 * Build the vertex shader prolog function.
7619 *
7620 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7621 * All inputs are returned unmodified. The vertex load indices are
7622 * stored after them, which will be used by the API VS for fetching inputs.
7623 *
7624 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7625 * input_v0,
7626 * input_v1,
7627 * input_v2,
7628 * input_v3,
7629 * (VertexID + BaseVertex),
7630 * (InstanceID + StartInstance),
7631 * (InstanceID / 2 + StartInstance)
7632 */
7633 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7634 union si_shader_part_key *key)
7635 {
7636 struct gallivm_state *gallivm = &ctx->gallivm;
7637 LLVMTypeRef *params, *returns;
7638 LLVMValueRef ret, func;
7639 int last_sgpr, num_params, num_returns, i;
7640
7641 ctx->param_vertex_id = key->vs_prolog.num_input_sgprs;
7642 ctx->param_instance_id = key->vs_prolog.num_input_sgprs + 3;
7643
7644 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7645 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
7646 sizeof(LLVMTypeRef));
7647 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
7648 key->vs_prolog.last_input + 1) *
7649 sizeof(LLVMTypeRef));
7650 num_params = 0;
7651 num_returns = 0;
7652
7653 /* Declare input and output SGPRs. */
7654 num_params = 0;
7655 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7656 params[num_params++] = ctx->i32;
7657 returns[num_returns++] = ctx->i32;
7658 }
7659 last_sgpr = num_params - 1;
7660
7661 /* 4 preloaded VGPRs (outputs must be floats) */
7662 for (i = 0; i < 4; i++) {
7663 params[num_params++] = ctx->i32;
7664 returns[num_returns++] = ctx->f32;
7665 }
7666
7667 /* Vertex load indices. */
7668 for (i = 0; i <= key->vs_prolog.last_input; i++)
7669 returns[num_returns++] = ctx->f32;
7670
7671 /* Create the function. */
7672 si_create_function(ctx, "vs_prolog", returns, num_returns, params,
7673 num_params, last_sgpr);
7674 func = ctx->main_fn;
7675
7676 /* Copy inputs to outputs. This should be no-op, as the registers match,
7677 * but it will prevent the compiler from overwriting them unintentionally.
7678 */
7679 ret = ctx->return_value;
7680 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7681 LLVMValueRef p = LLVMGetParam(func, i);
7682 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7683 }
7684 for (i = num_params - 4; i < num_params; i++) {
7685 LLVMValueRef p = LLVMGetParam(func, i);
7686 p = LLVMBuildBitCast(gallivm->builder, p, ctx->f32, "");
7687 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7688 }
7689
7690 /* Compute vertex load indices from instance divisors. */
7691 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7692 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
7693 LLVMValueRef index;
7694
7695 if (divisor) {
7696 /* InstanceID / Divisor + StartInstance */
7697 index = get_instance_index_for_fetch(ctx,
7698 SI_SGPR_START_INSTANCE,
7699 divisor);
7700 } else {
7701 /* VertexID + BaseVertex */
7702 index = LLVMBuildAdd(gallivm->builder,
7703 LLVMGetParam(func, ctx->param_vertex_id),
7704 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
7705 }
7706
7707 index = LLVMBuildBitCast(gallivm->builder, index, ctx->f32, "");
7708 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
7709 num_params++, "");
7710 }
7711
7712 si_llvm_build_ret(ctx, ret);
7713 }
7714
7715 /**
7716 * Build the vertex shader epilog function. This is also used by the tessellation
7717 * evaluation shader compiled as VS.
7718 *
7719 * The input is PrimitiveID.
7720 *
7721 * If PrimitiveID is required by the pixel shader, export it.
7722 * Otherwise, do nothing.
7723 */
7724 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
7725 union si_shader_part_key *key)
7726 {
7727 struct gallivm_state *gallivm = &ctx->gallivm;
7728 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
7729 LLVMTypeRef params[5];
7730 int num_params, i;
7731
7732 /* Declare input VGPRs. */
7733 num_params = key->vs_epilog.states.export_prim_id ?
7734 (VS_EPILOG_PRIMID_LOC + 1) : 0;
7735 assert(num_params <= ARRAY_SIZE(params));
7736
7737 for (i = 0; i < num_params; i++)
7738 params[i] = ctx->f32;
7739
7740 /* Create the function. */
7741 si_create_function(ctx, "vs_epilog", NULL, 0, params, num_params, -1);
7742
7743 /* Emit exports. */
7744 if (key->vs_epilog.states.export_prim_id) {
7745 struct lp_build_context *base = &bld_base->base;
7746 struct lp_build_context *uint = &bld_base->uint_bld;
7747 LLVMValueRef args[9];
7748
7749 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
7750 args[1] = uint->zero; /* whether the EXEC mask is valid */
7751 args[2] = uint->zero; /* DONE bit */
7752 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
7753 key->vs_epilog.prim_id_param_offset);
7754 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
7755 args[5] = LLVMGetParam(ctx->main_fn,
7756 VS_EPILOG_PRIMID_LOC); /* X */
7757 args[6] = base->undef; /* Y */
7758 args[7] = base->undef; /* Z */
7759 args[8] = base->undef; /* W */
7760
7761 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
7762 LLVMVoidTypeInContext(base->gallivm->context),
7763 args, 9, 0);
7764 }
7765
7766 LLVMBuildRetVoid(gallivm->builder);
7767 }
7768
7769 /**
7770 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7771 */
7772 static bool si_get_vs_epilog(struct si_screen *sscreen,
7773 LLVMTargetMachineRef tm,
7774 struct si_shader *shader,
7775 struct pipe_debug_callback *debug,
7776 struct si_vs_epilog_bits *states)
7777 {
7778 union si_shader_part_key epilog_key;
7779
7780 si_get_vs_epilog_key(shader, states, &epilog_key);
7781
7782 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
7783 PIPE_SHADER_VERTEX, true,
7784 &epilog_key, tm, debug,
7785 si_build_vs_epilog_function,
7786 "Vertex Shader Epilog");
7787 return shader->epilog != NULL;
7788 }
7789
7790 /**
7791 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7792 */
7793 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7794 LLVMTargetMachineRef tm,
7795 struct si_shader *shader,
7796 struct pipe_debug_callback *debug)
7797 {
7798 struct tgsi_shader_info *info = &shader->selector->info;
7799 union si_shader_part_key prolog_key;
7800
7801 /* Get the prolog. */
7802 si_get_vs_prolog_key(shader, &prolog_key);
7803
7804 /* The prolog is a no-op if there are no inputs. */
7805 if (info->num_inputs) {
7806 shader->prolog =
7807 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7808 PIPE_SHADER_VERTEX, true,
7809 &prolog_key, tm, debug,
7810 si_build_vs_prolog_function,
7811 "Vertex Shader Prolog");
7812 if (!shader->prolog)
7813 return false;
7814 }
7815
7816 /* Get the epilog. */
7817 if (!shader->key.as_es && !shader->key.as_ls &&
7818 !si_get_vs_epilog(sscreen, tm, shader, debug,
7819 &shader->key.part.vs.epilog))
7820 return false;
7821
7822 return true;
7823 }
7824
7825 /**
7826 * Select and compile (or reuse) TES parts (epilog).
7827 */
7828 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
7829 LLVMTargetMachineRef tm,
7830 struct si_shader *shader,
7831 struct pipe_debug_callback *debug)
7832 {
7833 if (shader->key.as_es)
7834 return true;
7835
7836 /* TES compiled as VS. */
7837 return si_get_vs_epilog(sscreen, tm, shader, debug,
7838 &shader->key.part.tes.epilog);
7839 }
7840
7841 /**
7842 * Compile the TCS epilog function. This writes tesselation factors to memory
7843 * based on the output primitive type of the tesselator (determined by TES).
7844 */
7845 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7846 union si_shader_part_key *key)
7847 {
7848 struct gallivm_state *gallivm = &ctx->gallivm;
7849 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
7850 LLVMTypeRef params[16];
7851 LLVMValueRef func;
7852 int last_sgpr, num_params;
7853
7854 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
7855 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
7856 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
7857 params[SI_PARAM_SAMPLERS] = ctx->i64;
7858 params[SI_PARAM_IMAGES] = ctx->i64;
7859 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
7860 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
7861 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
7862 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
7863 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
7864 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
7865 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
7866 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
7867 num_params = last_sgpr + 1;
7868
7869 params[num_params++] = ctx->i32; /* patch index within the wave (REL_PATCH_ID) */
7870 params[num_params++] = ctx->i32; /* invocation ID within the patch */
7871 params[num_params++] = ctx->i32; /* LDS offset where tess factors should be loaded from */
7872
7873 /* Create the function. */
7874 si_create_function(ctx, "tcs_epilog", NULL, 0, params, num_params, last_sgpr);
7875 declare_tess_lds(ctx);
7876 func = ctx->main_fn;
7877
7878 si_write_tess_factors(bld_base,
7879 LLVMGetParam(func, last_sgpr + 1),
7880 LLVMGetParam(func, last_sgpr + 2),
7881 LLVMGetParam(func, last_sgpr + 3));
7882
7883 LLVMBuildRetVoid(gallivm->builder);
7884 }
7885
7886 /**
7887 * Select and compile (or reuse) TCS parts (epilog).
7888 */
7889 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7890 LLVMTargetMachineRef tm,
7891 struct si_shader *shader,
7892 struct pipe_debug_callback *debug)
7893 {
7894 union si_shader_part_key epilog_key;
7895
7896 /* Get the epilog. */
7897 memset(&epilog_key, 0, sizeof(epilog_key));
7898 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7899
7900 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7901 PIPE_SHADER_TESS_CTRL, false,
7902 &epilog_key, tm, debug,
7903 si_build_tcs_epilog_function,
7904 "Tessellation Control Shader Epilog");
7905 return shader->epilog != NULL;
7906 }
7907
7908 /**
7909 * Select and compile (or reuse) GS parts (prolog).
7910 */
7911 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7912 LLVMTargetMachineRef tm,
7913 struct si_shader *shader,
7914 struct pipe_debug_callback *debug)
7915 {
7916 union si_shader_part_key prolog_key;
7917
7918 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7919 return true;
7920
7921 memset(&prolog_key, 0, sizeof(prolog_key));
7922 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7923
7924 shader->prolog = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7925 PIPE_SHADER_GEOMETRY, true,
7926 &prolog_key, tm, debug,
7927 si_build_gs_prolog_function,
7928 "Geometry Shader Prolog");
7929 return shader->prolog != NULL;
7930 }
7931
7932 /**
7933 * Build the pixel shader prolog function. This handles:
7934 * - two-side color selection and interpolation
7935 * - overriding interpolation parameters for the API PS
7936 * - polygon stippling
7937 *
7938 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7939 * overriden by other states. (e.g. per-sample interpolation)
7940 * Interpolated colors are stored after the preloaded VGPRs.
7941 */
7942 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7943 union si_shader_part_key *key)
7944 {
7945 struct gallivm_state *gallivm = &ctx->gallivm;
7946 LLVMTypeRef *params;
7947 LLVMValueRef ret, func;
7948 int last_sgpr, num_params, num_returns, i, num_color_channels;
7949
7950 assert(si_need_ps_prolog(key));
7951
7952 /* Number of inputs + 8 color elements. */
7953 params = alloca((key->ps_prolog.num_input_sgprs +
7954 key->ps_prolog.num_input_vgprs + 8) *
7955 sizeof(LLVMTypeRef));
7956
7957 /* Declare inputs. */
7958 num_params = 0;
7959 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7960 params[num_params++] = ctx->i32;
7961 last_sgpr = num_params - 1;
7962
7963 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7964 params[num_params++] = ctx->f32;
7965
7966 /* Declare outputs (same as inputs + add colors if needed) */
7967 num_returns = num_params;
7968 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7969 for (i = 0; i < num_color_channels; i++)
7970 params[num_returns++] = ctx->f32;
7971
7972 /* Create the function. */
7973 si_create_function(ctx, "ps_prolog", params, num_returns, params,
7974 num_params, last_sgpr);
7975 func = ctx->main_fn;
7976
7977 /* Copy inputs to outputs. This should be no-op, as the registers match,
7978 * but it will prevent the compiler from overwriting them unintentionally.
7979 */
7980 ret = ctx->return_value;
7981 for (i = 0; i < num_params; i++) {
7982 LLVMValueRef p = LLVMGetParam(func, i);
7983 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7984 }
7985
7986 /* Polygon stippling. */
7987 if (key->ps_prolog.states.poly_stipple) {
7988 /* POS_FIXED_PT is always last. */
7989 unsigned pos = key->ps_prolog.num_input_sgprs +
7990 key->ps_prolog.num_input_vgprs - 1;
7991 LLVMValueRef ptr[2], list;
7992
7993 /* Get the pointer to rw buffers. */
7994 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
7995 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
7996 list = lp_build_gather_values(gallivm, ptr, 2);
7997 list = LLVMBuildBitCast(gallivm->builder, list, ctx->i64, "");
7998 list = LLVMBuildIntToPtr(gallivm->builder, list,
7999 const_array(ctx->v16i8, SI_NUM_RW_BUFFERS), "");
8000
8001 si_llvm_emit_polygon_stipple(ctx, list, pos);
8002 }
8003
8004 if (key->ps_prolog.states.bc_optimize_for_persp ||
8005 key->ps_prolog.states.bc_optimize_for_linear) {
8006 unsigned i, base = key->ps_prolog.num_input_sgprs;
8007 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
8008
8009 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
8010 * The hw doesn't compute CENTROID if the whole wave only
8011 * contains fully-covered quads.
8012 *
8013 * PRIM_MASK is after user SGPRs.
8014 */
8015 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
8016 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
8017 LLVMConstInt(ctx->i32, 31, 0), "");
8018 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
8019 ctx->i1, "");
8020
8021 if (key->ps_prolog.states.bc_optimize_for_persp) {
8022 /* Read PERSP_CENTER. */
8023 for (i = 0; i < 2; i++)
8024 center[i] = LLVMGetParam(func, base + 2 + i);
8025 /* Read PERSP_CENTROID. */
8026 for (i = 0; i < 2; i++)
8027 centroid[i] = LLVMGetParam(func, base + 4 + i);
8028 /* Select PERSP_CENTROID. */
8029 for (i = 0; i < 2; i++) {
8030 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
8031 center[i], centroid[i], "");
8032 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8033 tmp, base + 4 + i, "");
8034 }
8035 }
8036 if (key->ps_prolog.states.bc_optimize_for_linear) {
8037 /* Read LINEAR_CENTER. */
8038 for (i = 0; i < 2; i++)
8039 center[i] = LLVMGetParam(func, base + 8 + i);
8040 /* Read LINEAR_CENTROID. */
8041 for (i = 0; i < 2; i++)
8042 centroid[i] = LLVMGetParam(func, base + 10 + i);
8043 /* Select LINEAR_CENTROID. */
8044 for (i = 0; i < 2; i++) {
8045 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
8046 center[i], centroid[i], "");
8047 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8048 tmp, base + 10 + i, "");
8049 }
8050 }
8051 }
8052
8053 /* Force per-sample interpolation. */
8054 if (key->ps_prolog.states.force_persp_sample_interp) {
8055 unsigned i, base = key->ps_prolog.num_input_sgprs;
8056 LLVMValueRef persp_sample[2];
8057
8058 /* Read PERSP_SAMPLE. */
8059 for (i = 0; i < 2; i++)
8060 persp_sample[i] = LLVMGetParam(func, base + i);
8061 /* Overwrite PERSP_CENTER. */
8062 for (i = 0; i < 2; i++)
8063 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8064 persp_sample[i], base + 2 + i, "");
8065 /* Overwrite PERSP_CENTROID. */
8066 for (i = 0; i < 2; i++)
8067 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8068 persp_sample[i], base + 4 + i, "");
8069 }
8070 if (key->ps_prolog.states.force_linear_sample_interp) {
8071 unsigned i, base = key->ps_prolog.num_input_sgprs;
8072 LLVMValueRef linear_sample[2];
8073
8074 /* Read LINEAR_SAMPLE. */
8075 for (i = 0; i < 2; i++)
8076 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
8077 /* Overwrite LINEAR_CENTER. */
8078 for (i = 0; i < 2; i++)
8079 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8080 linear_sample[i], base + 8 + i, "");
8081 /* Overwrite LINEAR_CENTROID. */
8082 for (i = 0; i < 2; i++)
8083 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8084 linear_sample[i], base + 10 + i, "");
8085 }
8086
8087 /* Force center interpolation. */
8088 if (key->ps_prolog.states.force_persp_center_interp) {
8089 unsigned i, base = key->ps_prolog.num_input_sgprs;
8090 LLVMValueRef persp_center[2];
8091
8092 /* Read PERSP_CENTER. */
8093 for (i = 0; i < 2; i++)
8094 persp_center[i] = LLVMGetParam(func, base + 2 + i);
8095 /* Overwrite PERSP_SAMPLE. */
8096 for (i = 0; i < 2; i++)
8097 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8098 persp_center[i], base + i, "");
8099 /* Overwrite PERSP_CENTROID. */
8100 for (i = 0; i < 2; i++)
8101 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8102 persp_center[i], base + 4 + i, "");
8103 }
8104 if (key->ps_prolog.states.force_linear_center_interp) {
8105 unsigned i, base = key->ps_prolog.num_input_sgprs;
8106 LLVMValueRef linear_center[2];
8107
8108 /* Read LINEAR_CENTER. */
8109 for (i = 0; i < 2; i++)
8110 linear_center[i] = LLVMGetParam(func, base + 8 + i);
8111 /* Overwrite LINEAR_SAMPLE. */
8112 for (i = 0; i < 2; i++)
8113 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8114 linear_center[i], base + 6 + i, "");
8115 /* Overwrite LINEAR_CENTROID. */
8116 for (i = 0; i < 2; i++)
8117 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8118 linear_center[i], base + 10 + i, "");
8119 }
8120
8121 /* Interpolate colors. */
8122 for (i = 0; i < 2; i++) {
8123 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
8124 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
8125 key->ps_prolog.face_vgpr_index;
8126 LLVMValueRef interp[2], color[4];
8127 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
8128
8129 if (!writemask)
8130 continue;
8131
8132 /* If the interpolation qualifier is not CONSTANT (-1). */
8133 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
8134 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
8135 key->ps_prolog.color_interp_vgpr_index[i];
8136
8137 /* Get the (i,j) updated by bc_optimize handling. */
8138 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
8139 interp_vgpr, "");
8140 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
8141 interp_vgpr + 1, "");
8142 interp_ij = lp_build_gather_values(gallivm, interp, 2);
8143 }
8144
8145 /* Use the absolute location of the input. */
8146 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
8147
8148 if (key->ps_prolog.states.color_two_side) {
8149 face = LLVMGetParam(func, face_vgpr);
8150 face = LLVMBuildBitCast(gallivm->builder, face, ctx->i32, "");
8151 }
8152
8153 interp_fs_input(ctx,
8154 key->ps_prolog.color_attr_index[i],
8155 TGSI_SEMANTIC_COLOR, i,
8156 key->ps_prolog.num_interp_inputs,
8157 key->ps_prolog.colors_read, interp_ij,
8158 prim_mask, face, color);
8159
8160 while (writemask) {
8161 unsigned chan = u_bit_scan(&writemask);
8162 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
8163 num_params++, "");
8164 }
8165 }
8166
8167 /* Tell LLVM to insert WQM instruction sequence when needed. */
8168 if (key->ps_prolog.wqm) {
8169 LLVMAddTargetDependentFunctionAttr(func,
8170 "amdgpu-ps-wqm-outputs", "");
8171 }
8172
8173 si_llvm_build_ret(ctx, ret);
8174 }
8175
8176 /**
8177 * Build the pixel shader epilog function. This handles everything that must be
8178 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
8179 */
8180 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
8181 union si_shader_part_key *key)
8182 {
8183 struct gallivm_state *gallivm = &ctx->gallivm;
8184 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
8185 LLVMTypeRef params[16+8*4+3];
8186 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
8187 int last_sgpr, num_params, i;
8188 struct si_ps_exports exp = {};
8189
8190 /* Declare input SGPRs. */
8191 params[SI_PARAM_RW_BUFFERS] = ctx->i64;
8192 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
8193 params[SI_PARAM_SAMPLERS] = ctx->i64;
8194 params[SI_PARAM_IMAGES] = ctx->i64;
8195 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
8196 params[SI_PARAM_ALPHA_REF] = ctx->f32;
8197 last_sgpr = SI_PARAM_ALPHA_REF;
8198
8199 /* Declare input VGPRs. */
8200 num_params = (last_sgpr + 1) +
8201 util_bitcount(key->ps_epilog.colors_written) * 4 +
8202 key->ps_epilog.writes_z +
8203 key->ps_epilog.writes_stencil +
8204 key->ps_epilog.writes_samplemask;
8205
8206 num_params = MAX2(num_params,
8207 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
8208
8209 assert(num_params <= ARRAY_SIZE(params));
8210
8211 for (i = last_sgpr + 1; i < num_params; i++)
8212 params[i] = ctx->f32;
8213
8214 /* Create the function. */
8215 si_create_function(ctx, "ps_epilog", NULL, 0, params, num_params, last_sgpr);
8216 /* Disable elimination of unused inputs. */
8217 si_llvm_add_attribute(ctx->main_fn,
8218 "InitialPSInputAddr", 0xffffff);
8219
8220 /* Process colors. */
8221 unsigned vgpr = last_sgpr + 1;
8222 unsigned colors_written = key->ps_epilog.colors_written;
8223 int last_color_export = -1;
8224
8225 /* Find the last color export. */
8226 if (!key->ps_epilog.writes_z &&
8227 !key->ps_epilog.writes_stencil &&
8228 !key->ps_epilog.writes_samplemask) {
8229 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
8230
8231 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
8232 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
8233 /* Just set this if any of the colorbuffers are enabled. */
8234 if (spi_format &
8235 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
8236 last_color_export = 0;
8237 } else {
8238 for (i = 0; i < 8; i++)
8239 if (colors_written & (1 << i) &&
8240 (spi_format >> (i * 4)) & 0xf)
8241 last_color_export = i;
8242 }
8243 }
8244
8245 while (colors_written) {
8246 LLVMValueRef color[4];
8247 int mrt = u_bit_scan(&colors_written);
8248
8249 for (i = 0; i < 4; i++)
8250 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
8251
8252 si_export_mrt_color(bld_base, color, mrt,
8253 num_params - 1,
8254 mrt == last_color_export, &exp);
8255 }
8256
8257 /* Process depth, stencil, samplemask. */
8258 if (key->ps_epilog.writes_z)
8259 depth = LLVMGetParam(ctx->main_fn, vgpr++);
8260 if (key->ps_epilog.writes_stencil)
8261 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
8262 if (key->ps_epilog.writes_samplemask)
8263 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
8264
8265 if (depth || stencil || samplemask)
8266 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
8267 else if (last_color_export == -1)
8268 si_export_null(bld_base);
8269
8270 if (exp.num)
8271 si_emit_ps_exports(ctx, &exp);
8272
8273 /* Compile. */
8274 LLVMBuildRetVoid(gallivm->builder);
8275 }
8276
8277 /**
8278 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
8279 */
8280 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
8281 LLVMTargetMachineRef tm,
8282 struct si_shader *shader,
8283 struct pipe_debug_callback *debug)
8284 {
8285 union si_shader_part_key prolog_key;
8286 union si_shader_part_key epilog_key;
8287
8288 /* Get the prolog. */
8289 si_get_ps_prolog_key(shader, &prolog_key, true);
8290
8291 /* The prolog is a no-op if these aren't set. */
8292 if (si_need_ps_prolog(&prolog_key)) {
8293 shader->prolog =
8294 si_get_shader_part(sscreen, &sscreen->ps_prologs,
8295 PIPE_SHADER_FRAGMENT, true,
8296 &prolog_key, tm, debug,
8297 si_build_ps_prolog_function,
8298 "Fragment Shader Prolog");
8299 if (!shader->prolog)
8300 return false;
8301 }
8302
8303 /* Get the epilog. */
8304 si_get_ps_epilog_key(shader, &epilog_key);
8305
8306 shader->epilog =
8307 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
8308 PIPE_SHADER_FRAGMENT, false,
8309 &epilog_key, tm, debug,
8310 si_build_ps_epilog_function,
8311 "Fragment Shader Epilog");
8312 if (!shader->epilog)
8313 return false;
8314
8315 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
8316 if (shader->key.part.ps.prolog.poly_stipple) {
8317 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
8318 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
8319 }
8320
8321 /* Set up the enable bits for per-sample shading if needed. */
8322 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
8323 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8324 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8325 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
8326 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8327 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
8328 }
8329 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
8330 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8331 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8332 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
8333 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8334 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
8335 }
8336 if (shader->key.part.ps.prolog.force_persp_center_interp &&
8337 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8338 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8339 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
8340 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8341 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8342 }
8343 if (shader->key.part.ps.prolog.force_linear_center_interp &&
8344 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8345 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8346 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
8347 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8348 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8349 }
8350
8351 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
8352 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
8353 !(shader->config.spi_ps_input_ena & 0xf)) {
8354 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8355 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
8356 }
8357
8358 /* At least one pair of interpolation weights must be enabled. */
8359 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
8360 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8361 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
8362 }
8363
8364 /* The sample mask input is always enabled, because the API shader always
8365 * passes it through to the epilog. Disable it here if it's unused.
8366 */
8367 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
8368 !shader->selector->info.reads_samplemask)
8369 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
8370
8371 return true;
8372 }
8373
8374 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
8375 unsigned *lds_size)
8376 {
8377 /* SPI barrier management bug:
8378 * Make sure we have at least 4k of LDS in use to avoid the bug.
8379 * It applies to workgroup sizes of more than one wavefront.
8380 */
8381 if (sscreen->b.family == CHIP_BONAIRE ||
8382 sscreen->b.family == CHIP_KABINI ||
8383 sscreen->b.family == CHIP_MULLINS)
8384 *lds_size = MAX2(*lds_size, 8);
8385 }
8386
8387 static void si_fix_resource_usage(struct si_screen *sscreen,
8388 struct si_shader *shader)
8389 {
8390 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
8391
8392 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
8393
8394 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
8395 si_get_max_workgroup_size(shader) > 64) {
8396 si_multiwave_lds_size_workaround(sscreen,
8397 &shader->config.lds_size);
8398 }
8399 }
8400
8401 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
8402 struct si_shader *shader,
8403 struct pipe_debug_callback *debug)
8404 {
8405 struct si_shader_selector *sel = shader->selector;
8406 struct si_shader *mainp = sel->main_shader_part;
8407 int r;
8408
8409 /* LS, ES, VS are compiled on demand if the main part hasn't been
8410 * compiled for that stage.
8411 *
8412 * Vertex shaders are compiled on demand when a vertex fetch
8413 * workaround must be applied.
8414 */
8415 if (shader->is_monolithic) {
8416 /* Monolithic shader (compiled as a whole, has many variants,
8417 * may take a long time to compile).
8418 */
8419 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
8420 if (r)
8421 return r;
8422 } else {
8423 /* The shader consists of 2-3 parts:
8424 *
8425 * - the middle part is the user shader, it has 1 variant only
8426 * and it was compiled during the creation of the shader
8427 * selector
8428 * - the prolog part is inserted at the beginning
8429 * - the epilog part is inserted at the end
8430 *
8431 * The prolog and epilog have many (but simple) variants.
8432 */
8433
8434 /* Copy the compiled TGSI shader data over. */
8435 shader->is_binary_shared = true;
8436 shader->binary = mainp->binary;
8437 shader->config = mainp->config;
8438 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8439 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8440 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8441 memcpy(shader->info.vs_output_param_offset,
8442 mainp->info.vs_output_param_offset,
8443 sizeof(mainp->info.vs_output_param_offset));
8444 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8445 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8446 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8447
8448 /* Select prologs and/or epilogs. */
8449 switch (sel->type) {
8450 case PIPE_SHADER_VERTEX:
8451 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
8452 return -1;
8453 break;
8454 case PIPE_SHADER_TESS_CTRL:
8455 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
8456 return -1;
8457 break;
8458 case PIPE_SHADER_TESS_EVAL:
8459 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
8460 return -1;
8461 break;
8462 case PIPE_SHADER_GEOMETRY:
8463 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
8464 return -1;
8465 break;
8466 case PIPE_SHADER_FRAGMENT:
8467 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8468 return -1;
8469
8470 /* Make sure we have at least as many VGPRs as there
8471 * are allocated inputs.
8472 */
8473 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8474 shader->info.num_input_vgprs);
8475 break;
8476 }
8477
8478 /* Update SGPR and VGPR counts. */
8479 if (shader->prolog) {
8480 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8481 shader->prolog->config.num_sgprs);
8482 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8483 shader->prolog->config.num_vgprs);
8484 }
8485 if (shader->epilog) {
8486 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8487 shader->epilog->config.num_sgprs);
8488 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8489 shader->epilog->config.num_vgprs);
8490 }
8491 }
8492
8493 si_fix_resource_usage(sscreen, shader);
8494 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8495 stderr);
8496
8497 /* Upload. */
8498 r = si_shader_binary_upload(sscreen, shader);
8499 if (r) {
8500 fprintf(stderr, "LLVM failed to upload shader\n");
8501 return r;
8502 }
8503
8504 return 0;
8505 }
8506
8507 void si_shader_destroy(struct si_shader *shader)
8508 {
8509 if (shader->scratch_bo)
8510 r600_resource_reference(&shader->scratch_bo, NULL);
8511
8512 r600_resource_reference(&shader->bo, NULL);
8513
8514 if (!shader->is_binary_shared)
8515 radeon_shader_binary_clean(&shader->binary);
8516
8517 free(shader->shader_log);
8518 }