2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "gallivm/lp_bld_const.h"
25 #include "gallivm/lp_bld_gather.h"
26 #include "gallivm/lp_bld_intr.h"
27 #include "gallivm/lp_bld_logic.h"
28 #include "gallivm/lp_bld_arit.h"
29 #include "gallivm/lp_bld_flow.h"
30 #include "gallivm/lp_bld_misc.h"
31 #include "util/u_memory.h"
32 #include "util/u_string.h"
33 #include "tgsi/tgsi_build.h"
34 #include "tgsi/tgsi_util.h"
35 #include "tgsi/tgsi_dump.h"
37 #include "ac_binary.h"
38 #include "ac_llvm_util.h"
39 #include "ac_exp_param.h"
40 #include "si_shader_internal.h"
44 #include "compiler/nir/nir.h"
46 static const char *scratch_rsrc_dword0_symbol
=
47 "SCRATCH_RSRC_DWORD0";
49 static const char *scratch_rsrc_dword1_symbol
=
50 "SCRATCH_RSRC_DWORD1";
52 struct si_shader_output_values
54 LLVMValueRef values
[4];
55 unsigned semantic_name
;
56 unsigned semantic_index
;
57 ubyte vertex_stream
[4];
61 * Used to collect types and other info about arguments of the LLVM function
62 * before the function is created.
64 struct si_function_info
{
65 LLVMTypeRef types
[100];
66 LLVMValueRef
*assign
[100];
67 unsigned num_sgpr_params
;
76 static void si_init_shader_ctx(struct si_shader_context
*ctx
,
77 struct si_screen
*sscreen
,
78 LLVMTargetMachineRef tm
);
80 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action
*action
,
81 struct lp_build_tgsi_context
*bld_base
,
82 struct lp_build_emit_data
*emit_data
);
84 static void si_dump_shader_key(unsigned processor
, const struct si_shader
*shader
,
87 static void si_build_vs_prolog_function(struct si_shader_context
*ctx
,
88 union si_shader_part_key
*key
);
89 static void si_build_tcs_epilog_function(struct si_shader_context
*ctx
,
90 union si_shader_part_key
*key
);
91 static void si_build_ps_prolog_function(struct si_shader_context
*ctx
,
92 union si_shader_part_key
*key
);
93 static void si_build_ps_epilog_function(struct si_shader_context
*ctx
,
94 union si_shader_part_key
*key
);
96 /* Ideally pass the sample mask input to the PS epilog as v14, which
97 * is its usual location, so that the shader doesn't have to add v_mov.
99 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
102 CONST_ADDR_SPACE
= 2,
103 LOCAL_ADDR_SPACE
= 3,
106 static bool llvm_type_is_64bit(struct si_shader_context
*ctx
,
109 if (type
== ctx
->ac
.i64
|| type
== ctx
->ac
.f64
)
115 static bool is_merged_shader(struct si_shader
*shader
)
117 if (shader
->selector
->screen
->info
.chip_class
<= VI
)
120 return shader
->key
.as_ls
||
122 shader
->selector
->type
== PIPE_SHADER_TESS_CTRL
||
123 shader
->selector
->type
== PIPE_SHADER_GEOMETRY
;
126 static void si_init_function_info(struct si_function_info
*fninfo
)
128 fninfo
->num_params
= 0;
129 fninfo
->num_sgpr_params
= 0;
132 static unsigned add_arg_assign(struct si_function_info
*fninfo
,
133 enum si_arg_regfile regfile
, LLVMTypeRef type
,
134 LLVMValueRef
*assign
)
136 assert(regfile
!= ARG_SGPR
|| fninfo
->num_sgpr_params
== fninfo
->num_params
);
138 unsigned idx
= fninfo
->num_params
++;
139 assert(idx
< ARRAY_SIZE(fninfo
->types
));
141 if (regfile
== ARG_SGPR
)
142 fninfo
->num_sgpr_params
= fninfo
->num_params
;
144 fninfo
->types
[idx
] = type
;
145 fninfo
->assign
[idx
] = assign
;
149 static unsigned add_arg(struct si_function_info
*fninfo
,
150 enum si_arg_regfile regfile
, LLVMTypeRef type
)
152 return add_arg_assign(fninfo
, regfile
, type
, NULL
);
155 static void add_arg_assign_checked(struct si_function_info
*fninfo
,
156 enum si_arg_regfile regfile
, LLVMTypeRef type
,
157 LLVMValueRef
*assign
, unsigned idx
)
159 MAYBE_UNUSED
unsigned actual
= add_arg_assign(fninfo
, regfile
, type
, assign
);
160 assert(actual
== idx
);
163 static void add_arg_checked(struct si_function_info
*fninfo
,
164 enum si_arg_regfile regfile
, LLVMTypeRef type
,
167 add_arg_assign_checked(fninfo
, regfile
, type
, NULL
, idx
);
171 * Returns a unique index for a per-patch semantic name and index. The index
172 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
175 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name
, unsigned index
)
177 switch (semantic_name
) {
178 case TGSI_SEMANTIC_TESSOUTER
:
180 case TGSI_SEMANTIC_TESSINNER
:
182 case TGSI_SEMANTIC_PATCH
:
187 assert(!"invalid semantic name");
193 * Returns a unique index for a semantic name and index. The index must be
194 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
197 unsigned si_shader_io_get_unique_index(unsigned semantic_name
, unsigned index
)
199 switch (semantic_name
) {
200 case TGSI_SEMANTIC_POSITION
:
202 case TGSI_SEMANTIC_GENERIC
:
203 /* Since some shader stages use the the highest used IO index
204 * to determine the size to allocate for inputs/outputs
205 * (in LDS, tess and GS rings). GENERIC should be placed right
206 * after POSITION to make that size as small as possible.
208 if (index
< SI_MAX_IO_GENERIC
)
211 assert(!"invalid generic index");
213 case TGSI_SEMANTIC_PSIZE
:
214 return SI_MAX_IO_GENERIC
+ 1;
215 case TGSI_SEMANTIC_CLIPDIST
:
217 return SI_MAX_IO_GENERIC
+ 2 + index
;
218 case TGSI_SEMANTIC_FOG
:
219 return SI_MAX_IO_GENERIC
+ 4;
220 case TGSI_SEMANTIC_LAYER
:
221 return SI_MAX_IO_GENERIC
+ 5;
222 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
223 return SI_MAX_IO_GENERIC
+ 6;
224 case TGSI_SEMANTIC_PRIMID
:
225 return SI_MAX_IO_GENERIC
+ 7;
226 case TGSI_SEMANTIC_COLOR
: /* these alias */
227 case TGSI_SEMANTIC_BCOLOR
:
229 return SI_MAX_IO_GENERIC
+ 8 + index
;
230 case TGSI_SEMANTIC_TEXCOORD
:
232 assert(SI_MAX_IO_GENERIC
+ 10 + index
< 64);
233 return SI_MAX_IO_GENERIC
+ 10 + index
;
235 assert(!"invalid semantic name");
241 * Get the value of a shader input parameter and extract a bitfield.
243 static LLVMValueRef
unpack_param(struct si_shader_context
*ctx
,
244 unsigned param
, unsigned rshift
,
247 LLVMValueRef value
= LLVMGetParam(ctx
->main_fn
,
250 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMFloatTypeKind
)
251 value
= ac_to_integer(&ctx
->ac
, value
);
254 value
= LLVMBuildLShr(ctx
->ac
.builder
, value
,
255 LLVMConstInt(ctx
->i32
, rshift
, 0), "");
257 if (rshift
+ bitwidth
< 32) {
258 unsigned mask
= (1 << bitwidth
) - 1;
259 value
= LLVMBuildAnd(ctx
->ac
.builder
, value
,
260 LLVMConstInt(ctx
->i32
, mask
, 0), "");
266 static LLVMValueRef
get_rel_patch_id(struct si_shader_context
*ctx
)
269 case PIPE_SHADER_TESS_CTRL
:
270 return unpack_param(ctx
, ctx
->param_tcs_rel_ids
, 0, 8);
272 case PIPE_SHADER_TESS_EVAL
:
273 return LLVMGetParam(ctx
->main_fn
,
274 ctx
->param_tes_rel_patch_id
);
282 /* Tessellation shaders pass outputs to the next shader using LDS.
284 * LS outputs = TCS inputs
285 * TCS outputs = TES inputs
288 * - TCS inputs for patch 0
289 * - TCS inputs for patch 1
290 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
292 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
293 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
294 * - TCS outputs for patch 1
295 * - Per-patch TCS outputs for patch 1
296 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
297 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
300 * All three shaders VS(LS), TCS, TES share the same LDS space.
304 get_tcs_in_patch_stride(struct si_shader_context
*ctx
)
306 return unpack_param(ctx
, ctx
->param_vs_state_bits
, 8, 13);
309 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context
*ctx
)
311 assert(ctx
->type
== PIPE_SHADER_TESS_CTRL
);
313 if (ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
)
314 return util_last_bit64(ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
) * 4;
316 return util_last_bit64(ctx
->shader
->selector
->outputs_written
) * 4;
319 static LLVMValueRef
get_tcs_out_vertex_dw_stride(struct si_shader_context
*ctx
)
321 unsigned stride
= get_tcs_out_vertex_dw_stride_constant(ctx
);
323 return LLVMConstInt(ctx
->i32
, stride
, 0);
326 static LLVMValueRef
get_tcs_out_patch_stride(struct si_shader_context
*ctx
)
328 if (ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
)
329 return unpack_param(ctx
, ctx
->param_tcs_out_lds_layout
, 0, 13);
331 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
332 unsigned tcs_out_vertices
= info
->properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
333 unsigned vertex_dw_stride
= get_tcs_out_vertex_dw_stride_constant(ctx
);
334 unsigned num_patch_outputs
= util_last_bit64(ctx
->shader
->selector
->patch_outputs_written
);
335 unsigned patch_dw_stride
= tcs_out_vertices
* vertex_dw_stride
+
336 num_patch_outputs
* 4;
337 return LLVMConstInt(ctx
->i32
, patch_dw_stride
, 0);
341 get_tcs_out_patch0_offset(struct si_shader_context
*ctx
)
343 return lp_build_mul_imm(&ctx
->bld_base
.uint_bld
,
345 ctx
->param_tcs_out_lds_offsets
,
351 get_tcs_out_patch0_patch_data_offset(struct si_shader_context
*ctx
)
353 return lp_build_mul_imm(&ctx
->bld_base
.uint_bld
,
355 ctx
->param_tcs_out_lds_offsets
,
361 get_tcs_in_current_patch_offset(struct si_shader_context
*ctx
)
363 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
364 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
366 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
370 get_tcs_out_current_patch_offset(struct si_shader_context
*ctx
)
372 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
373 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
374 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
376 return LLVMBuildAdd(ctx
->ac
.builder
, patch0_offset
,
377 LLVMBuildMul(ctx
->ac
.builder
, patch_stride
,
383 get_tcs_out_current_patch_data_offset(struct si_shader_context
*ctx
)
385 LLVMValueRef patch0_patch_data_offset
=
386 get_tcs_out_patch0_patch_data_offset(ctx
);
387 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
388 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
390 return LLVMBuildAdd(ctx
->ac
.builder
, patch0_patch_data_offset
,
391 LLVMBuildMul(ctx
->ac
.builder
, patch_stride
,
396 static LLVMValueRef
get_num_tcs_out_vertices(struct si_shader_context
*ctx
)
398 unsigned tcs_out_vertices
=
399 ctx
->shader
->selector
?
400 ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
] : 0;
402 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
403 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&& tcs_out_vertices
)
404 return LLVMConstInt(ctx
->i32
, tcs_out_vertices
, 0);
406 return unpack_param(ctx
, ctx
->param_tcs_offchip_layout
, 6, 6);
409 static LLVMValueRef
get_tcs_in_vertex_dw_stride(struct si_shader_context
*ctx
)
414 case PIPE_SHADER_VERTEX
:
415 stride
= util_last_bit64(ctx
->shader
->selector
->outputs_written
);
416 return LLVMConstInt(ctx
->i32
, stride
* 4, 0);
418 case PIPE_SHADER_TESS_CTRL
:
419 if (ctx
->screen
->info
.chip_class
>= GFX9
&&
420 ctx
->shader
->is_monolithic
) {
421 stride
= util_last_bit64(ctx
->shader
->key
.part
.tcs
.ls
->outputs_written
);
422 return LLVMConstInt(ctx
->i32
, stride
* 4, 0);
424 return unpack_param(ctx
, ctx
->param_vs_state_bits
, 24, 8);
432 static LLVMValueRef
get_instance_index_for_fetch(
433 struct si_shader_context
*ctx
,
434 unsigned param_start_instance
, LLVMValueRef divisor
)
436 LLVMValueRef result
= ctx
->abi
.instance_id
;
438 /* The division must be done before START_INSTANCE is added. */
439 if (divisor
!= ctx
->i32_1
)
440 result
= LLVMBuildUDiv(ctx
->ac
.builder
, result
, divisor
, "");
442 return LLVMBuildAdd(ctx
->ac
.builder
, result
,
443 LLVMGetParam(ctx
->main_fn
, param_start_instance
), "");
446 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
448 static LLVMValueRef
extract_double_to_float(struct si_shader_context
*ctx
,
450 unsigned double_index
)
452 LLVMBuilderRef builder
= ctx
->ac
.builder
;
453 LLVMTypeRef f64
= LLVMDoubleTypeInContext(ctx
->ac
.context
);
454 LLVMValueRef dvec2
= LLVMBuildBitCast(builder
, vec4
,
455 LLVMVectorType(f64
, 2), "");
456 LLVMValueRef index
= LLVMConstInt(ctx
->i32
, double_index
, 0);
457 LLVMValueRef value
= LLVMBuildExtractElement(builder
, dvec2
, index
, "");
458 return LLVMBuildFPTrunc(builder
, value
, ctx
->f32
, "");
461 static LLVMValueRef
unpack_sint16(struct si_shader_context
*ctx
,
462 LLVMValueRef i32
, unsigned index
)
467 return LLVMBuildAShr(ctx
->ac
.builder
, i32
,
468 LLVMConstInt(ctx
->i32
, 16, 0), "");
470 return LLVMBuildSExt(ctx
->ac
.builder
,
471 LLVMBuildTrunc(ctx
->ac
.builder
, i32
,
476 void si_llvm_load_input_vs(
477 struct si_shader_context
*ctx
,
478 unsigned input_index
,
481 unsigned vs_blit_property
=
482 ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
484 if (vs_blit_property
) {
485 LLVMValueRef vertex_id
= ctx
->abi
.vertex_id
;
486 LLVMValueRef sel_x1
= LLVMBuildICmp(ctx
->ac
.builder
,
487 LLVMIntULE
, vertex_id
,
489 /* Use LLVMIntNE, because we have 3 vertices and only
490 * the middle one should use y2.
492 LLVMValueRef sel_y1
= LLVMBuildICmp(ctx
->ac
.builder
,
493 LLVMIntNE
, vertex_id
,
496 if (input_index
== 0) {
498 LLVMValueRef x1y1
= LLVMGetParam(ctx
->main_fn
,
499 ctx
->param_vs_blit_inputs
);
500 LLVMValueRef x2y2
= LLVMGetParam(ctx
->main_fn
,
501 ctx
->param_vs_blit_inputs
+ 1);
503 LLVMValueRef x1
= unpack_sint16(ctx
, x1y1
, 0);
504 LLVMValueRef y1
= unpack_sint16(ctx
, x1y1
, 1);
505 LLVMValueRef x2
= unpack_sint16(ctx
, x2y2
, 0);
506 LLVMValueRef y2
= unpack_sint16(ctx
, x2y2
, 1);
508 LLVMValueRef x
= LLVMBuildSelect(ctx
->ac
.builder
, sel_x1
,
510 LLVMValueRef y
= LLVMBuildSelect(ctx
->ac
.builder
, sel_y1
,
513 out
[0] = LLVMBuildSIToFP(ctx
->ac
.builder
, x
, ctx
->f32
, "");
514 out
[1] = LLVMBuildSIToFP(ctx
->ac
.builder
, y
, ctx
->f32
, "");
515 out
[2] = LLVMGetParam(ctx
->main_fn
,
516 ctx
->param_vs_blit_inputs
+ 2);
517 out
[3] = ctx
->ac
.f32_1
;
521 /* Color or texture coordinates: */
522 assert(input_index
== 1);
524 if (vs_blit_property
== SI_VS_BLIT_SGPRS_POS_COLOR
) {
525 for (int i
= 0; i
< 4; i
++) {
526 out
[i
] = LLVMGetParam(ctx
->main_fn
,
527 ctx
->param_vs_blit_inputs
+ 3 + i
);
530 assert(vs_blit_property
== SI_VS_BLIT_SGPRS_POS_TEXCOORD
);
531 LLVMValueRef x1
= LLVMGetParam(ctx
->main_fn
,
532 ctx
->param_vs_blit_inputs
+ 3);
533 LLVMValueRef y1
= LLVMGetParam(ctx
->main_fn
,
534 ctx
->param_vs_blit_inputs
+ 4);
535 LLVMValueRef x2
= LLVMGetParam(ctx
->main_fn
,
536 ctx
->param_vs_blit_inputs
+ 5);
537 LLVMValueRef y2
= LLVMGetParam(ctx
->main_fn
,
538 ctx
->param_vs_blit_inputs
+ 6);
540 out
[0] = LLVMBuildSelect(ctx
->ac
.builder
, sel_x1
,
542 out
[1] = LLVMBuildSelect(ctx
->ac
.builder
, sel_y1
,
544 out
[2] = LLVMGetParam(ctx
->main_fn
,
545 ctx
->param_vs_blit_inputs
+ 7);
546 out
[3] = LLVMGetParam(ctx
->main_fn
,
547 ctx
->param_vs_blit_inputs
+ 8);
554 unsigned num_fetches
;
555 unsigned fetch_stride
;
557 LLVMValueRef t_list_ptr
;
558 LLVMValueRef t_offset
;
560 LLVMValueRef vertex_index
;
561 LLVMValueRef input
[3];
563 /* Load the T list */
564 t_list_ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_vertex_buffers
);
566 t_offset
= LLVMConstInt(ctx
->i32
, input_index
, 0);
568 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
570 vertex_index
= LLVMGetParam(ctx
->main_fn
,
571 ctx
->param_vertex_index0
+
574 fix_fetch
= ctx
->shader
->key
.mono
.vs_fix_fetch
[input_index
];
576 /* Do multiple loads for special formats. */
578 case SI_FIX_FETCH_RGB_64_FLOAT
:
579 num_fetches
= 3; /* 3 2-dword loads */
582 case SI_FIX_FETCH_RGBA_64_FLOAT
:
583 num_fetches
= 2; /* 2 4-dword loads */
586 case SI_FIX_FETCH_RGB_8
:
587 case SI_FIX_FETCH_RGB_8_INT
:
591 case SI_FIX_FETCH_RGB_16
:
592 case SI_FIX_FETCH_RGB_16_INT
:
601 for (unsigned i
= 0; i
< num_fetches
; i
++) {
602 LLVMValueRef voffset
= LLVMConstInt(ctx
->i32
, fetch_stride
* i
, 0);
604 input
[i
] = ac_build_buffer_load_format(&ctx
->ac
, t_list
,
605 vertex_index
, voffset
,
609 /* Break up the vec4 into individual components */
610 for (chan
= 0; chan
< 4; chan
++) {
611 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->i32
, chan
, 0);
612 out
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
613 input
[0], llvm_chan
, "");
617 case SI_FIX_FETCH_A2_SNORM
:
618 case SI_FIX_FETCH_A2_SSCALED
:
619 case SI_FIX_FETCH_A2_SINT
: {
620 /* The hardware returns an unsigned value; convert it to a
623 LLVMValueRef tmp
= out
[3];
624 LLVMValueRef c30
= LLVMConstInt(ctx
->i32
, 30, 0);
626 /* First, recover the sign-extended signed integer value. */
627 if (fix_fetch
== SI_FIX_FETCH_A2_SSCALED
)
628 tmp
= LLVMBuildFPToUI(ctx
->ac
.builder
, tmp
, ctx
->i32
, "");
630 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
632 /* For the integer-like cases, do a natural sign extension.
634 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
635 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
638 tmp
= LLVMBuildShl(ctx
->ac
.builder
, tmp
,
639 fix_fetch
== SI_FIX_FETCH_A2_SNORM
?
640 LLVMConstInt(ctx
->i32
, 7, 0) : c30
, "");
641 tmp
= LLVMBuildAShr(ctx
->ac
.builder
, tmp
, c30
, "");
643 /* Convert back to the right type. */
644 if (fix_fetch
== SI_FIX_FETCH_A2_SNORM
) {
646 LLVMValueRef neg_one
= LLVMConstReal(ctx
->f32
, -1.0);
647 tmp
= LLVMBuildSIToFP(ctx
->ac
.builder
, tmp
, ctx
->f32
, "");
648 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, tmp
, neg_one
, "");
649 tmp
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, tmp
, "");
650 } else if (fix_fetch
== SI_FIX_FETCH_A2_SSCALED
) {
651 tmp
= LLVMBuildSIToFP(ctx
->ac
.builder
, tmp
, ctx
->f32
, "");
657 case SI_FIX_FETCH_RGBA_32_UNORM
:
658 case SI_FIX_FETCH_RGBX_32_UNORM
:
659 for (chan
= 0; chan
< 4; chan
++) {
660 out
[chan
] = ac_to_integer(&ctx
->ac
, out
[chan
]);
661 out
[chan
] = LLVMBuildUIToFP(ctx
->ac
.builder
,
662 out
[chan
], ctx
->f32
, "");
663 out
[chan
] = LLVMBuildFMul(ctx
->ac
.builder
, out
[chan
],
664 LLVMConstReal(ctx
->f32
, 1.0 / UINT_MAX
), "");
666 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
667 if (fix_fetch
== SI_FIX_FETCH_RGBX_32_UNORM
)
668 out
[3] = LLVMConstReal(ctx
->f32
, 1);
670 case SI_FIX_FETCH_RGBA_32_SNORM
:
671 case SI_FIX_FETCH_RGBX_32_SNORM
:
672 case SI_FIX_FETCH_RGBA_32_FIXED
:
673 case SI_FIX_FETCH_RGBX_32_FIXED
: {
675 if (fix_fetch
>= SI_FIX_FETCH_RGBA_32_FIXED
)
676 scale
= 1.0 / 0x10000;
678 scale
= 1.0 / INT_MAX
;
680 for (chan
= 0; chan
< 4; chan
++) {
681 out
[chan
] = ac_to_integer(&ctx
->ac
, out
[chan
]);
682 out
[chan
] = LLVMBuildSIToFP(ctx
->ac
.builder
,
683 out
[chan
], ctx
->f32
, "");
684 out
[chan
] = LLVMBuildFMul(ctx
->ac
.builder
, out
[chan
],
685 LLVMConstReal(ctx
->f32
, scale
), "");
687 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
688 if (fix_fetch
== SI_FIX_FETCH_RGBX_32_SNORM
||
689 fix_fetch
== SI_FIX_FETCH_RGBX_32_FIXED
)
690 out
[3] = LLVMConstReal(ctx
->f32
, 1);
693 case SI_FIX_FETCH_RGBA_32_USCALED
:
694 for (chan
= 0; chan
< 4; chan
++) {
695 out
[chan
] = ac_to_integer(&ctx
->ac
, out
[chan
]);
696 out
[chan
] = LLVMBuildUIToFP(ctx
->ac
.builder
,
697 out
[chan
], ctx
->f32
, "");
700 case SI_FIX_FETCH_RGBA_32_SSCALED
:
701 for (chan
= 0; chan
< 4; chan
++) {
702 out
[chan
] = ac_to_integer(&ctx
->ac
, out
[chan
]);
703 out
[chan
] = LLVMBuildSIToFP(ctx
->ac
.builder
,
704 out
[chan
], ctx
->f32
, "");
707 case SI_FIX_FETCH_RG_64_FLOAT
:
708 for (chan
= 0; chan
< 2; chan
++)
709 out
[chan
] = extract_double_to_float(ctx
, input
[0], chan
);
711 out
[2] = LLVMConstReal(ctx
->f32
, 0);
712 out
[3] = LLVMConstReal(ctx
->f32
, 1);
714 case SI_FIX_FETCH_RGB_64_FLOAT
:
715 for (chan
= 0; chan
< 3; chan
++)
716 out
[chan
] = extract_double_to_float(ctx
, input
[chan
], 0);
718 out
[3] = LLVMConstReal(ctx
->f32
, 1);
720 case SI_FIX_FETCH_RGBA_64_FLOAT
:
721 for (chan
= 0; chan
< 4; chan
++) {
722 out
[chan
] = extract_double_to_float(ctx
, input
[chan
/ 2],
726 case SI_FIX_FETCH_RGB_8
:
727 case SI_FIX_FETCH_RGB_8_INT
:
728 case SI_FIX_FETCH_RGB_16
:
729 case SI_FIX_FETCH_RGB_16_INT
:
730 for (chan
= 0; chan
< 3; chan
++) {
731 out
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
735 if (fix_fetch
== SI_FIX_FETCH_RGB_8
||
736 fix_fetch
== SI_FIX_FETCH_RGB_16
) {
737 out
[3] = LLVMConstReal(ctx
->f32
, 1);
739 out
[3] = ac_to_float(&ctx
->ac
, ctx
->i32_1
);
745 static void declare_input_vs(
746 struct si_shader_context
*ctx
,
747 unsigned input_index
,
748 const struct tgsi_full_declaration
*decl
,
751 si_llvm_load_input_vs(ctx
, input_index
, out
);
754 static LLVMValueRef
get_primitive_id(struct si_shader_context
*ctx
,
761 case PIPE_SHADER_VERTEX
:
762 return LLVMGetParam(ctx
->main_fn
,
763 ctx
->param_vs_prim_id
);
764 case PIPE_SHADER_TESS_CTRL
:
765 return LLVMGetParam(ctx
->main_fn
,
766 ctx
->param_tcs_patch_id
);
767 case PIPE_SHADER_TESS_EVAL
:
768 return LLVMGetParam(ctx
->main_fn
,
769 ctx
->param_tes_patch_id
);
770 case PIPE_SHADER_GEOMETRY
:
771 return ctx
->abi
.gs_prim_id
;
779 * Return the value of tgsi_ind_register for indexing.
780 * This is the indirect index with the constant offset added to it.
782 LLVMValueRef
si_get_indirect_index(struct si_shader_context
*ctx
,
783 const struct tgsi_ind_register
*ind
,
789 if (ind
->File
== TGSI_FILE_ADDRESS
) {
790 result
= ctx
->addrs
[ind
->Index
][ind
->Swizzle
];
791 result
= LLVMBuildLoad(ctx
->ac
.builder
, result
, "");
793 struct tgsi_full_src_register src
= {};
795 src
.Register
.File
= ind
->File
;
796 src
.Register
.Index
= ind
->Index
;
798 /* Set the second index to 0 for constants. */
799 if (ind
->File
== TGSI_FILE_CONSTANT
)
800 src
.Register
.Dimension
= 1;
802 result
= ctx
->bld_base
.emit_fetch_funcs
[ind
->File
](&ctx
->bld_base
, &src
,
805 result
= ac_to_integer(&ctx
->ac
, result
);
809 result
= LLVMBuildMul(ctx
->ac
.builder
, result
,
810 LLVMConstInt(ctx
->i32
, addr_mul
, 0), "");
811 result
= LLVMBuildAdd(ctx
->ac
.builder
, result
,
812 LLVMConstInt(ctx
->i32
, rel_index
, 0), "");
817 * Like si_get_indirect_index, but restricts the return value to a (possibly
818 * undefined) value inside [0..num).
820 LLVMValueRef
si_get_bounded_indirect_index(struct si_shader_context
*ctx
,
821 const struct tgsi_ind_register
*ind
,
822 int rel_index
, unsigned num
)
824 LLVMValueRef result
= si_get_indirect_index(ctx
, ind
, 1, rel_index
);
826 return si_llvm_bound_index(ctx
, result
, num
);
831 * Calculate a dword address given an input or output register and a stride.
833 static LLVMValueRef
get_dw_address(struct si_shader_context
*ctx
,
834 const struct tgsi_full_dst_register
*dst
,
835 const struct tgsi_full_src_register
*src
,
836 LLVMValueRef vertex_dw_stride
,
837 LLVMValueRef base_addr
)
839 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
840 ubyte
*name
, *index
, *array_first
;
842 struct tgsi_full_dst_register reg
;
844 /* Set the register description. The address computation is the same
845 * for sources and destinations. */
847 reg
.Register
.File
= src
->Register
.File
;
848 reg
.Register
.Index
= src
->Register
.Index
;
849 reg
.Register
.Indirect
= src
->Register
.Indirect
;
850 reg
.Register
.Dimension
= src
->Register
.Dimension
;
851 reg
.Indirect
= src
->Indirect
;
852 reg
.Dimension
= src
->Dimension
;
853 reg
.DimIndirect
= src
->DimIndirect
;
857 /* If the register is 2-dimensional (e.g. an array of vertices
858 * in a primitive), calculate the base address of the vertex. */
859 if (reg
.Register
.Dimension
) {
862 if (reg
.Dimension
.Indirect
)
863 index
= si_get_indirect_index(ctx
, ®
.DimIndirect
,
864 1, reg
.Dimension
.Index
);
866 index
= LLVMConstInt(ctx
->i32
, reg
.Dimension
.Index
, 0);
868 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
869 LLVMBuildMul(ctx
->ac
.builder
, index
,
870 vertex_dw_stride
, ""), "");
873 /* Get information about the register. */
874 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
875 name
= info
->input_semantic_name
;
876 index
= info
->input_semantic_index
;
877 array_first
= info
->input_array_first
;
878 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
879 name
= info
->output_semantic_name
;
880 index
= info
->output_semantic_index
;
881 array_first
= info
->output_array_first
;
887 if (reg
.Register
.Indirect
) {
888 /* Add the relative address of the element. */
889 LLVMValueRef ind_index
;
891 if (reg
.Indirect
.ArrayID
)
892 first
= array_first
[reg
.Indirect
.ArrayID
];
894 first
= reg
.Register
.Index
;
896 ind_index
= si_get_indirect_index(ctx
, ®
.Indirect
,
897 1, reg
.Register
.Index
- first
);
899 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
900 LLVMBuildMul(ctx
->ac
.builder
, ind_index
,
901 LLVMConstInt(ctx
->i32
, 4, 0), ""), "");
903 param
= reg
.Register
.Dimension
?
904 si_shader_io_get_unique_index(name
[first
], index
[first
]) :
905 si_shader_io_get_unique_index_patch(name
[first
], index
[first
]);
907 param
= reg
.Register
.Dimension
?
908 si_shader_io_get_unique_index(name
[reg
.Register
.Index
],
909 index
[reg
.Register
.Index
]) :
910 si_shader_io_get_unique_index_patch(name
[reg
.Register
.Index
],
911 index
[reg
.Register
.Index
]);
914 /* Add the base address of the element. */
915 return LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
916 LLVMConstInt(ctx
->i32
, param
* 4, 0), "");
919 /* The offchip buffer layout for TCS->TES is
921 * - attribute 0 of patch 0 vertex 0
922 * - attribute 0 of patch 0 vertex 1
923 * - attribute 0 of patch 0 vertex 2
925 * - attribute 0 of patch 1 vertex 0
926 * - attribute 0 of patch 1 vertex 1
928 * - attribute 1 of patch 0 vertex 0
929 * - attribute 1 of patch 0 vertex 1
931 * - per patch attribute 0 of patch 0
932 * - per patch attribute 0 of patch 1
935 * Note that every attribute has 4 components.
937 static LLVMValueRef
get_tcs_tes_buffer_address(struct si_shader_context
*ctx
,
938 LLVMValueRef rel_patch_id
,
939 LLVMValueRef vertex_index
,
940 LLVMValueRef param_index
)
942 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
, total_vertices
;
943 LLVMValueRef param_stride
, constant16
;
945 vertices_per_patch
= get_num_tcs_out_vertices(ctx
);
946 num_patches
= unpack_param(ctx
, ctx
->param_tcs_offchip_layout
, 0, 6);
947 total_vertices
= LLVMBuildMul(ctx
->ac
.builder
, vertices_per_patch
,
950 constant16
= LLVMConstInt(ctx
->i32
, 16, 0);
952 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
953 vertices_per_patch
, "");
955 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
958 param_stride
= total_vertices
;
960 base_addr
= rel_patch_id
;
961 param_stride
= num_patches
;
964 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
965 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
966 param_stride
, ""), "");
968 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
971 LLVMValueRef patch_data_offset
=
972 unpack_param(ctx
, ctx
->param_tcs_offchip_layout
, 12, 20);
974 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
975 patch_data_offset
, "");
980 static LLVMValueRef
get_tcs_tes_buffer_address_from_reg(
981 struct si_shader_context
*ctx
,
982 const struct tgsi_full_dst_register
*dst
,
983 const struct tgsi_full_src_register
*src
)
985 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
986 ubyte
*name
, *index
, *array_first
;
987 struct tgsi_full_src_register reg
;
988 LLVMValueRef vertex_index
= NULL
;
989 LLVMValueRef param_index
= NULL
;
990 unsigned param_index_base
, param_base
;
992 reg
= src
? *src
: tgsi_full_src_register_from_dst(dst
);
994 if (reg
.Register
.Dimension
) {
996 if (reg
.Dimension
.Indirect
)
997 vertex_index
= si_get_indirect_index(ctx
, ®
.DimIndirect
,
998 1, reg
.Dimension
.Index
);
1000 vertex_index
= LLVMConstInt(ctx
->i32
, reg
.Dimension
.Index
, 0);
1003 /* Get information about the register. */
1004 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
1005 name
= info
->input_semantic_name
;
1006 index
= info
->input_semantic_index
;
1007 array_first
= info
->input_array_first
;
1008 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
1009 name
= info
->output_semantic_name
;
1010 index
= info
->output_semantic_index
;
1011 array_first
= info
->output_array_first
;
1017 if (reg
.Register
.Indirect
) {
1018 if (reg
.Indirect
.ArrayID
)
1019 param_base
= array_first
[reg
.Indirect
.ArrayID
];
1021 param_base
= reg
.Register
.Index
;
1023 param_index
= si_get_indirect_index(ctx
, ®
.Indirect
,
1024 1, reg
.Register
.Index
- param_base
);
1027 param_base
= reg
.Register
.Index
;
1028 param_index
= ctx
->i32_0
;
1031 param_index_base
= reg
.Register
.Dimension
?
1032 si_shader_io_get_unique_index(name
[param_base
], index
[param_base
]) :
1033 si_shader_io_get_unique_index_patch(name
[param_base
], index
[param_base
]);
1035 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, param_index
,
1036 LLVMConstInt(ctx
->i32
, param_index_base
, 0),
1039 return get_tcs_tes_buffer_address(ctx
, get_rel_patch_id(ctx
),
1040 vertex_index
, param_index
);
1043 static LLVMValueRef
buffer_load(struct lp_build_tgsi_context
*bld_base
,
1044 enum tgsi_opcode_type type
, unsigned swizzle
,
1045 LLVMValueRef buffer
, LLVMValueRef offset
,
1046 LLVMValueRef base
, bool can_speculate
)
1048 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1049 LLVMValueRef value
, value2
;
1050 LLVMTypeRef llvm_type
= tgsi2llvmtype(bld_base
, type
);
1051 LLVMTypeRef vec_type
= LLVMVectorType(llvm_type
, 4);
1053 if (swizzle
== ~0) {
1054 value
= ac_build_buffer_load(&ctx
->ac
, buffer
, 4, NULL
, base
, offset
,
1055 0, 1, 0, can_speculate
, false);
1057 return LLVMBuildBitCast(ctx
->ac
.builder
, value
, vec_type
, "");
1060 if (!tgsi_type_is_64bit(type
)) {
1061 value
= ac_build_buffer_load(&ctx
->ac
, buffer
, 4, NULL
, base
, offset
,
1062 0, 1, 0, can_speculate
, false);
1064 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, vec_type
, "");
1065 return LLVMBuildExtractElement(ctx
->ac
.builder
, value
,
1066 LLVMConstInt(ctx
->i32
, swizzle
, 0), "");
1069 value
= ac_build_buffer_load(&ctx
->ac
, buffer
, 1, NULL
, base
, offset
,
1070 swizzle
* 4, 1, 0, can_speculate
, false);
1072 value2
= ac_build_buffer_load(&ctx
->ac
, buffer
, 1, NULL
, base
, offset
,
1073 swizzle
* 4 + 4, 1, 0, can_speculate
, false);
1075 return si_llvm_emit_fetch_64bit(bld_base
, tgsi2llvmtype(bld_base
, type
),
1082 * \param type output value type
1083 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1084 * \param dw_addr address in dwords
1086 static LLVMValueRef
lds_load(struct lp_build_tgsi_context
*bld_base
,
1087 enum tgsi_opcode_type type
, unsigned swizzle
,
1088 LLVMValueRef dw_addr
)
1090 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1093 if (swizzle
== ~0) {
1094 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
1096 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++)
1097 values
[chan
] = lds_load(bld_base
, type
, chan
, dw_addr
);
1099 return lp_build_gather_values(&ctx
->gallivm
, values
,
1103 /* Split 64-bit loads. */
1104 if (tgsi_type_is_64bit(type
)) {
1105 LLVMValueRef lo
, hi
;
1107 lo
= lds_load(bld_base
, TGSI_TYPE_UNSIGNED
, swizzle
, dw_addr
);
1108 hi
= lds_load(bld_base
, TGSI_TYPE_UNSIGNED
, swizzle
+ 1, dw_addr
);
1109 return si_llvm_emit_fetch_64bit(bld_base
, tgsi2llvmtype(bld_base
, type
),
1113 dw_addr
= lp_build_add(&bld_base
->uint_bld
, dw_addr
,
1114 LLVMConstInt(ctx
->i32
, swizzle
, 0));
1116 value
= ac_lds_load(&ctx
->ac
, dw_addr
);
1118 return bitcast(bld_base
, type
, value
);
1124 * \param swizzle offset (typically 0..3)
1125 * \param dw_addr address in dwords
1126 * \param value value to store
1128 static void lds_store(struct si_shader_context
*ctx
,
1129 unsigned dw_offset_imm
, LLVMValueRef dw_addr
,
1132 dw_addr
= lp_build_add(&ctx
->bld_base
.uint_bld
, dw_addr
,
1133 LLVMConstInt(ctx
->i32
, dw_offset_imm
, 0));
1135 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
1138 static LLVMValueRef
desc_from_addr_base64k(struct si_shader_context
*ctx
,
1141 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1143 LLVMValueRef addr
= LLVMGetParam(ctx
->main_fn
, param
);
1144 addr
= LLVMBuildZExt(builder
, addr
, ctx
->i64
, "");
1145 addr
= LLVMBuildShl(builder
, addr
, LLVMConstInt(ctx
->i64
, 16, 0), "");
1147 uint64_t desc2
= 0xffffffff;
1148 uint64_t desc3
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1149 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1150 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1151 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1152 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1153 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1154 LLVMValueRef hi
= LLVMConstInt(ctx
->i64
, desc2
| (desc3
<< 32), 0);
1156 LLVMValueRef desc
= LLVMGetUndef(LLVMVectorType(ctx
->i64
, 2));
1157 desc
= LLVMBuildInsertElement(builder
, desc
, addr
, ctx
->i32_0
, "");
1158 desc
= LLVMBuildInsertElement(builder
, desc
, hi
, ctx
->i32_1
, "");
1159 return LLVMBuildBitCast(builder
, desc
, ctx
->v4i32
, "");
1162 static LLVMValueRef
fetch_input_tcs(
1163 struct lp_build_tgsi_context
*bld_base
,
1164 const struct tgsi_full_src_register
*reg
,
1165 enum tgsi_opcode_type type
, unsigned swizzle
)
1167 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1168 LLVMValueRef dw_addr
, stride
;
1170 stride
= get_tcs_in_vertex_dw_stride(ctx
);
1171 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1172 dw_addr
= get_dw_address(ctx
, NULL
, reg
, stride
, dw_addr
);
1174 return lds_load(bld_base
, type
, swizzle
, dw_addr
);
1177 static LLVMValueRef
fetch_output_tcs(
1178 struct lp_build_tgsi_context
*bld_base
,
1179 const struct tgsi_full_src_register
*reg
,
1180 enum tgsi_opcode_type type
, unsigned swizzle
)
1182 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1183 LLVMValueRef dw_addr
, stride
;
1185 if (reg
->Register
.Dimension
) {
1186 stride
= get_tcs_out_vertex_dw_stride(ctx
);
1187 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1188 dw_addr
= get_dw_address(ctx
, NULL
, reg
, stride
, dw_addr
);
1190 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1191 dw_addr
= get_dw_address(ctx
, NULL
, reg
, NULL
, dw_addr
);
1194 return lds_load(bld_base
, type
, swizzle
, dw_addr
);
1197 static LLVMValueRef
fetch_input_tes(
1198 struct lp_build_tgsi_context
*bld_base
,
1199 const struct tgsi_full_src_register
*reg
,
1200 enum tgsi_opcode_type type
, unsigned swizzle
)
1202 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1203 LLVMValueRef buffer
, base
, addr
;
1205 buffer
= desc_from_addr_base64k(ctx
, ctx
->param_tcs_offchip_addr_base64k
);
1207 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1208 addr
= get_tcs_tes_buffer_address_from_reg(ctx
, NULL
, reg
);
1210 return buffer_load(bld_base
, type
, swizzle
, buffer
, base
, addr
, true);
1213 static void store_output_tcs(struct lp_build_tgsi_context
*bld_base
,
1214 const struct tgsi_full_instruction
*inst
,
1215 const struct tgsi_opcode_info
*info
,
1217 LLVMValueRef dst
[4])
1219 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1220 const struct tgsi_full_dst_register
*reg
= &inst
->Dst
[index
];
1221 const struct tgsi_shader_info
*sh_info
= &ctx
->shader
->selector
->info
;
1222 unsigned chan_index
;
1223 LLVMValueRef dw_addr
, stride
;
1224 LLVMValueRef buffer
, base
, buf_addr
;
1225 LLVMValueRef values
[4];
1226 bool skip_lds_store
;
1227 bool is_tess_factor
= false, is_tess_inner
= false;
1229 /* Only handle per-patch and per-vertex outputs here.
1230 * Vectors will be lowered to scalars and this function will be called again.
1232 if (reg
->Register
.File
!= TGSI_FILE_OUTPUT
||
1233 (dst
[0] && LLVMGetTypeKind(LLVMTypeOf(dst
[0])) == LLVMVectorTypeKind
)) {
1234 si_llvm_emit_store(bld_base
, inst
, info
, index
, dst
);
1238 if (reg
->Register
.Dimension
) {
1239 stride
= get_tcs_out_vertex_dw_stride(ctx
);
1240 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1241 dw_addr
= get_dw_address(ctx
, reg
, NULL
, stride
, dw_addr
);
1242 skip_lds_store
= !sh_info
->reads_pervertex_outputs
;
1244 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1245 dw_addr
= get_dw_address(ctx
, reg
, NULL
, NULL
, dw_addr
);
1246 skip_lds_store
= !sh_info
->reads_perpatch_outputs
;
1248 if (!reg
->Register
.Indirect
) {
1249 int name
= sh_info
->output_semantic_name
[reg
->Register
.Index
];
1251 /* Always write tess factors into LDS for the TCS epilog. */
1252 if (name
== TGSI_SEMANTIC_TESSINNER
||
1253 name
== TGSI_SEMANTIC_TESSOUTER
) {
1254 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1255 skip_lds_store
= !sh_info
->reads_tessfactor_outputs
&&
1256 ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1257 is_tess_factor
= true;
1258 is_tess_inner
= name
== TGSI_SEMANTIC_TESSINNER
;
1263 buffer
= desc_from_addr_base64k(ctx
, ctx
->param_tcs_offchip_addr_base64k
);
1265 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1266 buf_addr
= get_tcs_tes_buffer_address_from_reg(ctx
, reg
, NULL
);
1268 uint32_t writemask
= reg
->Register
.WriteMask
;
1270 chan_index
= u_bit_scan(&writemask
);
1271 LLVMValueRef value
= dst
[chan_index
];
1273 if (inst
->Instruction
.Saturate
)
1274 value
= ac_build_clamp(&ctx
->ac
, value
);
1276 /* Skip LDS stores if there is no LDS read of this output. */
1277 if (!skip_lds_store
)
1278 lds_store(ctx
, chan_index
, dw_addr
, value
);
1280 value
= ac_to_integer(&ctx
->ac
, value
);
1281 values
[chan_index
] = value
;
1283 if (reg
->Register
.WriteMask
!= 0xF && !is_tess_factor
) {
1284 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 1,
1286 4 * chan_index
, 1, 0, true, false);
1289 /* Write tess factors into VGPRs for the epilog. */
1290 if (is_tess_factor
&&
1291 ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
) {
1292 if (!is_tess_inner
) {
1293 LLVMBuildStore(ctx
->ac
.builder
, value
, /* outer */
1294 ctx
->invoc0_tess_factors
[chan_index
]);
1295 } else if (chan_index
< 2) {
1296 LLVMBuildStore(ctx
->ac
.builder
, value
, /* inner */
1297 ctx
->invoc0_tess_factors
[4 + chan_index
]);
1302 if (reg
->Register
.WriteMask
== 0xF && !is_tess_factor
) {
1303 LLVMValueRef value
= lp_build_gather_values(&ctx
->gallivm
,
1305 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 4, buf_addr
,
1306 base
, 0, 1, 0, true, false);
1310 static LLVMValueRef
fetch_input_gs(
1311 struct lp_build_tgsi_context
*bld_base
,
1312 const struct tgsi_full_src_register
*reg
,
1313 enum tgsi_opcode_type type
,
1316 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1317 struct si_shader
*shader
= ctx
->shader
;
1318 struct lp_build_context
*uint
= &ctx
->bld_base
.uint_bld
;
1319 LLVMValueRef vtx_offset
, soffset
;
1320 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1321 unsigned semantic_name
= info
->input_semantic_name
[reg
->Register
.Index
];
1322 unsigned semantic_index
= info
->input_semantic_index
[reg
->Register
.Index
];
1326 if (swizzle
!= ~0 && semantic_name
== TGSI_SEMANTIC_PRIMID
)
1327 return get_primitive_id(ctx
, swizzle
);
1329 if (!reg
->Register
.Dimension
)
1332 param
= si_shader_io_get_unique_index(semantic_name
, semantic_index
);
1334 /* GFX9 has the ESGS ring in LDS. */
1335 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
1336 unsigned index
= reg
->Dimension
.Index
;
1338 switch (index
/ 2) {
1340 vtx_offset
= unpack_param(ctx
, ctx
->param_gs_vtx01_offset
,
1341 index
% 2 ? 16 : 0, 16);
1344 vtx_offset
= unpack_param(ctx
, ctx
->param_gs_vtx23_offset
,
1345 index
% 2 ? 16 : 0, 16);
1348 vtx_offset
= unpack_param(ctx
, ctx
->param_gs_vtx45_offset
,
1349 index
% 2 ? 16 : 0, 16);
1356 vtx_offset
= LLVMBuildAdd(ctx
->ac
.builder
, vtx_offset
,
1357 LLVMConstInt(ctx
->i32
, param
* 4, 0), "");
1358 return lds_load(bld_base
, type
, swizzle
, vtx_offset
);
1361 /* GFX6: input load from the ESGS ring in memory. */
1362 if (swizzle
== ~0) {
1363 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
1365 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1366 values
[chan
] = fetch_input_gs(bld_base
, reg
, type
, chan
);
1368 return lp_build_gather_values(&ctx
->gallivm
, values
,
1372 /* Get the vertex offset parameter on GFX6. */
1373 unsigned vtx_offset_param
= reg
->Dimension
.Index
;
1374 LLVMValueRef gs_vtx_offset
= ctx
->gs_vtx_offset
[vtx_offset_param
];
1376 vtx_offset
= lp_build_mul_imm(uint
, gs_vtx_offset
, 4);
1378 soffset
= LLVMConstInt(ctx
->i32
, (param
* 4 + swizzle
) * 256, 0);
1380 value
= ac_build_buffer_load(&ctx
->ac
, ctx
->esgs_ring
, 1, ctx
->i32_0
,
1381 vtx_offset
, soffset
, 0, 1, 0, true, false);
1382 if (tgsi_type_is_64bit(type
)) {
1383 LLVMValueRef value2
;
1384 soffset
= LLVMConstInt(ctx
->i32
, (param
* 4 + swizzle
+ 1) * 256, 0);
1386 value2
= ac_build_buffer_load(&ctx
->ac
, ctx
->esgs_ring
, 1,
1387 ctx
->i32_0
, vtx_offset
, soffset
,
1388 0, 1, 0, true, false);
1389 return si_llvm_emit_fetch_64bit(bld_base
, tgsi2llvmtype(bld_base
, type
),
1392 return bitcast(bld_base
, type
, value
);
1395 static int lookup_interp_param_index(unsigned interpolate
, unsigned location
)
1397 switch (interpolate
) {
1398 case TGSI_INTERPOLATE_CONSTANT
:
1401 case TGSI_INTERPOLATE_LINEAR
:
1402 if (location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
1403 return SI_PARAM_LINEAR_SAMPLE
;
1404 else if (location
== TGSI_INTERPOLATE_LOC_CENTROID
)
1405 return SI_PARAM_LINEAR_CENTROID
;
1407 return SI_PARAM_LINEAR_CENTER
;
1409 case TGSI_INTERPOLATE_COLOR
:
1410 case TGSI_INTERPOLATE_PERSPECTIVE
:
1411 if (location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
1412 return SI_PARAM_PERSP_SAMPLE
;
1413 else if (location
== TGSI_INTERPOLATE_LOC_CENTROID
)
1414 return SI_PARAM_PERSP_CENTROID
;
1416 return SI_PARAM_PERSP_CENTER
;
1419 fprintf(stderr
, "Warning: Unhandled interpolation mode.\n");
1424 static LLVMValueRef
si_build_fs_interp(struct si_shader_context
*ctx
,
1425 unsigned attr_index
, unsigned chan
,
1426 LLVMValueRef prim_mask
,
1427 LLVMValueRef i
, LLVMValueRef j
)
1430 return ac_build_fs_interp(&ctx
->ac
,
1431 LLVMConstInt(ctx
->i32
, chan
, 0),
1432 LLVMConstInt(ctx
->i32
, attr_index
, 0),
1435 return ac_build_fs_interp_mov(&ctx
->ac
,
1436 LLVMConstInt(ctx
->i32
, 2, 0), /* P0 */
1437 LLVMConstInt(ctx
->i32
, chan
, 0),
1438 LLVMConstInt(ctx
->i32
, attr_index
, 0),
1443 * Interpolate a fragment shader input.
1445 * @param ctx context
1446 * @param input_index index of the input in hardware
1447 * @param semantic_name TGSI_SEMANTIC_*
1448 * @param semantic_index semantic index
1449 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1450 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1451 * @param interp_param interpolation weights (i,j)
1452 * @param prim_mask SI_PARAM_PRIM_MASK
1453 * @param face SI_PARAM_FRONT_FACE
1454 * @param result the return value (4 components)
1456 static void interp_fs_input(struct si_shader_context
*ctx
,
1457 unsigned input_index
,
1458 unsigned semantic_name
,
1459 unsigned semantic_index
,
1460 unsigned num_interp_inputs
,
1461 unsigned colors_read_mask
,
1462 LLVMValueRef interp_param
,
1463 LLVMValueRef prim_mask
,
1465 LLVMValueRef result
[4])
1467 LLVMValueRef i
= NULL
, j
= NULL
;
1470 /* fs.constant returns the param from the middle vertex, so it's not
1471 * really useful for flat shading. It's meant to be used for custom
1472 * interpolation (but the intrinsic can't fetch from the other two
1475 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1476 * to do the right thing. The only reason we use fs.constant is that
1477 * fs.interp cannot be used on integers, because they can be equal
1480 * When interp is false we will use fs.constant or for newer llvm,
1481 * amdgcn.interp.mov.
1483 bool interp
= interp_param
!= NULL
;
1486 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_param
,
1487 LLVMVectorType(ctx
->f32
, 2), "");
1489 i
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
1491 j
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
1495 if (semantic_name
== TGSI_SEMANTIC_COLOR
&&
1496 ctx
->shader
->key
.part
.ps
.prolog
.color_two_side
) {
1497 LLVMValueRef is_face_positive
;
1499 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1500 * otherwise it's at offset "num_inputs".
1502 unsigned back_attr_offset
= num_interp_inputs
;
1503 if (semantic_index
== 1 && colors_read_mask
& 0xf)
1504 back_attr_offset
+= 1;
1506 is_face_positive
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
,
1507 face
, ctx
->i32_0
, "");
1509 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1510 LLVMValueRef front
, back
;
1512 front
= si_build_fs_interp(ctx
,
1515 back
= si_build_fs_interp(ctx
,
1516 back_attr_offset
, chan
,
1519 result
[chan
] = LLVMBuildSelect(ctx
->ac
.builder
,
1525 } else if (semantic_name
== TGSI_SEMANTIC_FOG
) {
1526 result
[0] = si_build_fs_interp(ctx
, input_index
,
1527 0, prim_mask
, i
, j
);
1529 result
[2] = LLVMConstReal(ctx
->f32
, 0.0f
);
1530 result
[3] = LLVMConstReal(ctx
->f32
, 1.0f
);
1532 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1533 result
[chan
] = si_build_fs_interp(ctx
,
1540 void si_llvm_load_input_fs(
1541 struct si_shader_context
*ctx
,
1542 unsigned input_index
,
1543 LLVMValueRef out
[4])
1545 struct lp_build_context
*base
= &ctx
->bld_base
.base
;
1546 struct si_shader
*shader
= ctx
->shader
;
1547 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1548 LLVMValueRef main_fn
= ctx
->main_fn
;
1549 LLVMValueRef interp_param
= NULL
;
1550 int interp_param_idx
;
1551 enum tgsi_semantic semantic_name
= info
->input_semantic_name
[input_index
];
1552 unsigned semantic_index
= info
->input_semantic_index
[input_index
];
1553 enum tgsi_interpolate_mode interp_mode
= info
->input_interpolate
[input_index
];
1554 enum tgsi_interpolate_loc interp_loc
= info
->input_interpolate_loc
[input_index
];
1556 /* Get colors from input VGPRs (set by the prolog). */
1557 if (semantic_name
== TGSI_SEMANTIC_COLOR
) {
1558 unsigned colors_read
= shader
->selector
->info
.colors_read
;
1559 unsigned mask
= colors_read
>> (semantic_index
* 4);
1560 unsigned offset
= SI_PARAM_POS_FIXED_PT
+ 1 +
1561 (semantic_index
? util_bitcount(colors_read
& 0xf) : 0);
1563 out
[0] = mask
& 0x1 ? LLVMGetParam(main_fn
, offset
++) : base
->undef
;
1564 out
[1] = mask
& 0x2 ? LLVMGetParam(main_fn
, offset
++) : base
->undef
;
1565 out
[2] = mask
& 0x4 ? LLVMGetParam(main_fn
, offset
++) : base
->undef
;
1566 out
[3] = mask
& 0x8 ? LLVMGetParam(main_fn
, offset
++) : base
->undef
;
1570 interp_param_idx
= lookup_interp_param_index(interp_mode
, interp_loc
);
1571 if (interp_param_idx
== -1)
1573 else if (interp_param_idx
) {
1574 interp_param
= LLVMGetParam(ctx
->main_fn
, interp_param_idx
);
1577 interp_fs_input(ctx
, input_index
, semantic_name
,
1578 semantic_index
, 0, /* this param is unused */
1579 shader
->selector
->info
.colors_read
, interp_param
,
1580 LLVMGetParam(main_fn
, SI_PARAM_PRIM_MASK
),
1581 LLVMGetParam(main_fn
, SI_PARAM_FRONT_FACE
),
1585 static void declare_input_fs(
1586 struct si_shader_context
*ctx
,
1587 unsigned input_index
,
1588 const struct tgsi_full_declaration
*decl
,
1589 LLVMValueRef out
[4])
1591 si_llvm_load_input_fs(ctx
, input_index
, out
);
1594 static LLVMValueRef
get_sample_id(struct si_shader_context
*ctx
)
1596 return unpack_param(ctx
, SI_PARAM_ANCILLARY
, 8, 4);
1601 * Load a dword from a constant buffer.
1603 static LLVMValueRef
buffer_load_const(struct si_shader_context
*ctx
,
1604 LLVMValueRef resource
,
1605 LLVMValueRef offset
)
1607 return ac_build_buffer_load(&ctx
->ac
, resource
, 1, NULL
, offset
, NULL
,
1608 0, 0, 0, true, true);
1611 static LLVMValueRef
load_sample_position(struct si_shader_context
*ctx
, LLVMValueRef sample_id
)
1613 struct lp_build_context
*uint_bld
= &ctx
->bld_base
.uint_bld
;
1614 LLVMValueRef desc
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
1615 LLVMValueRef buf_index
= LLVMConstInt(ctx
->i32
, SI_PS_CONST_SAMPLE_POSITIONS
, 0);
1616 LLVMValueRef resource
= ac_build_load_to_sgpr(&ctx
->ac
, desc
, buf_index
);
1618 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1619 LLVMValueRef offset0
= lp_build_mul_imm(uint_bld
, sample_id
, 8);
1620 LLVMValueRef offset1
= LLVMBuildAdd(ctx
->ac
.builder
, offset0
, LLVMConstInt(ctx
->i32
, 4, 0), "");
1622 LLVMValueRef pos
[4] = {
1623 buffer_load_const(ctx
, resource
, offset0
),
1624 buffer_load_const(ctx
, resource
, offset1
),
1625 LLVMConstReal(ctx
->f32
, 0),
1626 LLVMConstReal(ctx
->f32
, 0)
1629 return lp_build_gather_values(&ctx
->gallivm
, pos
, 4);
1632 void si_load_system_value(struct si_shader_context
*ctx
,
1634 const struct tgsi_full_declaration
*decl
)
1636 struct lp_build_context
*bld
= &ctx
->bld_base
.base
;
1637 LLVMValueRef value
= 0;
1639 assert(index
< RADEON_LLVM_MAX_SYSTEM_VALUES
);
1641 switch (decl
->Semantic
.Name
) {
1642 case TGSI_SEMANTIC_INSTANCEID
:
1643 value
= ctx
->abi
.instance_id
;
1646 case TGSI_SEMANTIC_VERTEXID
:
1647 value
= LLVMBuildAdd(ctx
->ac
.builder
,
1649 ctx
->abi
.base_vertex
, "");
1652 case TGSI_SEMANTIC_VERTEXID_NOBASE
:
1653 /* Unused. Clarify the meaning in indexed vs. non-indexed
1654 * draws if this is ever used again. */
1658 case TGSI_SEMANTIC_BASEVERTEX
:
1660 /* For non-indexed draws, the base vertex set by the driver
1661 * (for direct draws) or the CP (for indirect draws) is the
1662 * first vertex ID, but GLSL expects 0 to be returned.
1664 LLVMValueRef vs_state
= LLVMGetParam(ctx
->main_fn
, ctx
->param_vs_state_bits
);
1665 LLVMValueRef indexed
;
1667 indexed
= LLVMBuildLShr(ctx
->ac
.builder
, vs_state
, ctx
->i32_1
, "");
1668 indexed
= LLVMBuildTrunc(ctx
->ac
.builder
, indexed
, ctx
->i1
, "");
1670 value
= LLVMBuildSelect(ctx
->ac
.builder
, indexed
,
1671 ctx
->abi
.base_vertex
, ctx
->i32_0
, "");
1675 case TGSI_SEMANTIC_BASEINSTANCE
:
1676 value
= ctx
->abi
.start_instance
;
1679 case TGSI_SEMANTIC_DRAWID
:
1680 value
= ctx
->abi
.draw_id
;
1683 case TGSI_SEMANTIC_INVOCATIONID
:
1684 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
1685 value
= unpack_param(ctx
, ctx
->param_tcs_rel_ids
, 8, 5);
1686 else if (ctx
->type
== PIPE_SHADER_GEOMETRY
)
1687 value
= ctx
->abi
.gs_invocation_id
;
1689 assert(!"INVOCATIONID not implemented");
1692 case TGSI_SEMANTIC_POSITION
:
1694 LLVMValueRef pos
[4] = {
1695 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_X_FLOAT
),
1696 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Y_FLOAT
),
1697 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Z_FLOAT
),
1698 lp_build_emit_llvm_unary(&ctx
->bld_base
, TGSI_OPCODE_RCP
,
1699 LLVMGetParam(ctx
->main_fn
,
1700 SI_PARAM_POS_W_FLOAT
)),
1702 value
= lp_build_gather_values(&ctx
->gallivm
, pos
, 4);
1706 case TGSI_SEMANTIC_FACE
:
1707 value
= ctx
->abi
.front_face
;
1710 case TGSI_SEMANTIC_SAMPLEID
:
1711 value
= get_sample_id(ctx
);
1714 case TGSI_SEMANTIC_SAMPLEPOS
: {
1715 LLVMValueRef pos
[4] = {
1716 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_X_FLOAT
),
1717 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Y_FLOAT
),
1718 LLVMConstReal(ctx
->f32
, 0),
1719 LLVMConstReal(ctx
->f32
, 0)
1721 pos
[0] = lp_build_emit_llvm_unary(&ctx
->bld_base
,
1722 TGSI_OPCODE_FRC
, pos
[0]);
1723 pos
[1] = lp_build_emit_llvm_unary(&ctx
->bld_base
,
1724 TGSI_OPCODE_FRC
, pos
[1]);
1725 value
= lp_build_gather_values(&ctx
->gallivm
, pos
, 4);
1729 case TGSI_SEMANTIC_SAMPLEMASK
:
1730 /* This can only occur with the OpenGL Core profile, which
1731 * doesn't support smoothing.
1733 value
= LLVMGetParam(ctx
->main_fn
, SI_PARAM_SAMPLE_COVERAGE
);
1736 case TGSI_SEMANTIC_TESSCOORD
:
1738 LLVMValueRef coord
[4] = {
1739 LLVMGetParam(ctx
->main_fn
, ctx
->param_tes_u
),
1740 LLVMGetParam(ctx
->main_fn
, ctx
->param_tes_v
),
1745 /* For triangles, the vector should be (u, v, 1-u-v). */
1746 if (ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] ==
1747 PIPE_PRIM_TRIANGLES
)
1748 coord
[2] = lp_build_sub(bld
, ctx
->ac
.f32_1
,
1749 lp_build_add(bld
, coord
[0], coord
[1]));
1751 value
= lp_build_gather_values(&ctx
->gallivm
, coord
, 4);
1755 case TGSI_SEMANTIC_VERTICESIN
:
1756 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
1757 value
= unpack_param(ctx
, ctx
->param_tcs_out_lds_layout
, 26, 6);
1758 else if (ctx
->type
== PIPE_SHADER_TESS_EVAL
)
1759 value
= get_num_tcs_out_vertices(ctx
);
1761 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1764 case TGSI_SEMANTIC_TESSINNER
:
1765 case TGSI_SEMANTIC_TESSOUTER
:
1767 LLVMValueRef buffer
, base
, addr
;
1768 int param
= si_shader_io_get_unique_index_patch(decl
->Semantic
.Name
, 0);
1770 buffer
= desc_from_addr_base64k(ctx
, ctx
->param_tcs_offchip_addr_base64k
);
1772 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1773 addr
= get_tcs_tes_buffer_address(ctx
, get_rel_patch_id(ctx
), NULL
,
1774 LLVMConstInt(ctx
->i32
, param
, 0));
1776 value
= buffer_load(&ctx
->bld_base
, TGSI_TYPE_FLOAT
,
1777 ~0, buffer
, base
, addr
, true);
1782 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
:
1783 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
:
1785 LLVMValueRef buf
, slot
, val
[4];
1788 slot
= LLVMConstInt(ctx
->i32
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, 0);
1789 buf
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
1790 buf
= ac_build_load_to_sgpr(&ctx
->ac
, buf
, slot
);
1791 offset
= decl
->Semantic
.Name
== TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
? 4 : 0;
1793 for (i
= 0; i
< 4; i
++)
1794 val
[i
] = buffer_load_const(ctx
, buf
,
1795 LLVMConstInt(ctx
->i32
, (offset
+ i
) * 4, 0));
1796 value
= lp_build_gather_values(&ctx
->gallivm
, val
, 4);
1800 case TGSI_SEMANTIC_PRIMID
:
1801 value
= get_primitive_id(ctx
, 0);
1804 case TGSI_SEMANTIC_GRID_SIZE
:
1805 value
= LLVMGetParam(ctx
->main_fn
, ctx
->param_grid_size
);
1808 case TGSI_SEMANTIC_BLOCK_SIZE
:
1810 LLVMValueRef values
[3];
1812 unsigned *properties
= ctx
->shader
->selector
->info
.properties
;
1814 if (properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] != 0) {
1815 unsigned sizes
[3] = {
1816 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
],
1817 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
],
1818 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
]
1821 for (i
= 0; i
< 3; ++i
)
1822 values
[i
] = LLVMConstInt(ctx
->i32
, sizes
[i
], 0);
1824 value
= lp_build_gather_values(&ctx
->gallivm
, values
, 3);
1826 value
= LLVMGetParam(ctx
->main_fn
, ctx
->param_block_size
);
1831 case TGSI_SEMANTIC_BLOCK_ID
:
1833 LLVMValueRef values
[3];
1835 for (int i
= 0; i
< 3; i
++) {
1836 values
[i
] = ctx
->i32_0
;
1837 if (ctx
->param_block_id
[i
] >= 0) {
1838 values
[i
] = LLVMGetParam(ctx
->main_fn
,
1839 ctx
->param_block_id
[i
]);
1842 value
= lp_build_gather_values(&ctx
->gallivm
, values
, 3);
1846 case TGSI_SEMANTIC_THREAD_ID
:
1847 value
= LLVMGetParam(ctx
->main_fn
, ctx
->param_thread_id
);
1850 case TGSI_SEMANTIC_HELPER_INVOCATION
:
1851 value
= lp_build_intrinsic(ctx
->ac
.builder
,
1852 "llvm.amdgcn.ps.live",
1854 LP_FUNC_ATTR_READNONE
);
1855 value
= LLVMBuildNot(ctx
->ac
.builder
, value
, "");
1856 value
= LLVMBuildSExt(ctx
->ac
.builder
, value
, ctx
->i32
, "");
1859 case TGSI_SEMANTIC_SUBGROUP_SIZE
:
1860 value
= LLVMConstInt(ctx
->i32
, 64, 0);
1863 case TGSI_SEMANTIC_SUBGROUP_INVOCATION
:
1864 value
= ac_get_thread_id(&ctx
->ac
);
1867 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK
:
1869 LLVMValueRef id
= ac_get_thread_id(&ctx
->ac
);
1870 id
= LLVMBuildZExt(ctx
->ac
.builder
, id
, ctx
->i64
, "");
1871 value
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->i64
, 1, 0), id
, "");
1872 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->v2i32
, "");
1876 case TGSI_SEMANTIC_SUBGROUP_GE_MASK
:
1877 case TGSI_SEMANTIC_SUBGROUP_GT_MASK
:
1878 case TGSI_SEMANTIC_SUBGROUP_LE_MASK
:
1879 case TGSI_SEMANTIC_SUBGROUP_LT_MASK
:
1881 LLVMValueRef id
= ac_get_thread_id(&ctx
->ac
);
1882 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_GT_MASK
||
1883 decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_LE_MASK
) {
1884 /* All bits set except LSB */
1885 value
= LLVMConstInt(ctx
->i64
, -2, 0);
1888 value
= LLVMConstInt(ctx
->i64
, -1, 0);
1890 id
= LLVMBuildZExt(ctx
->ac
.builder
, id
, ctx
->i64
, "");
1891 value
= LLVMBuildShl(ctx
->ac
.builder
, value
, id
, "");
1892 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_LE_MASK
||
1893 decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_LT_MASK
)
1894 value
= LLVMBuildNot(ctx
->ac
.builder
, value
, "");
1895 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->v2i32
, "");
1900 assert(!"unknown system value");
1904 ctx
->system_values
[index
] = value
;
1907 void si_declare_compute_memory(struct si_shader_context
*ctx
,
1908 const struct tgsi_full_declaration
*decl
)
1910 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
1912 LLVMTypeRef i8p
= LLVMPointerType(ctx
->i8
, LOCAL_ADDR_SPACE
);
1915 assert(decl
->Declaration
.MemType
== TGSI_MEMORY_TYPE_SHARED
);
1916 assert(decl
->Range
.First
== decl
->Range
.Last
);
1917 assert(!ctx
->ac
.lds
);
1919 var
= LLVMAddGlobalInAddressSpace(ctx
->ac
.module
,
1920 LLVMArrayType(ctx
->i8
, sel
->local_size
),
1923 LLVMSetAlignment(var
, 4);
1925 ctx
->ac
.lds
= LLVMBuildBitCast(ctx
->ac
.builder
, var
, i8p
, "");
1928 static LLVMValueRef
load_const_buffer_desc(struct si_shader_context
*ctx
, int i
)
1930 LLVMValueRef list_ptr
= LLVMGetParam(ctx
->main_fn
,
1931 ctx
->param_const_and_shader_buffers
);
1933 return ac_build_load_to_sgpr(&ctx
->ac
, list_ptr
,
1934 LLVMConstInt(ctx
->i32
, si_get_constbuf_slot(i
), 0));
1937 static LLVMValueRef
load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef index
)
1939 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1940 LLVMValueRef ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_const_and_shader_buffers
);
1942 index
= si_llvm_bound_index(ctx
, index
, ctx
->num_const_buffers
);
1943 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
1944 LLVMConstInt(ctx
->i32
, SI_NUM_SHADER_BUFFERS
, 0), "");
1946 return ac_build_load_to_sgpr(&ctx
->ac
, ptr
, index
);
1950 load_ssbo(struct ac_shader_abi
*abi
, LLVMValueRef index
, bool write
)
1952 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1953 LLVMValueRef rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
1954 ctx
->param_const_and_shader_buffers
);
1956 index
= si_llvm_bound_index(ctx
, index
, ctx
->num_shader_buffers
);
1957 index
= LLVMBuildSub(ctx
->ac
.builder
,
1958 LLVMConstInt(ctx
->i32
, SI_NUM_SHADER_BUFFERS
- 1, 0),
1961 return ac_build_load_to_sgpr(&ctx
->ac
, rsrc_ptr
, index
);
1964 static LLVMValueRef
fetch_constant(
1965 struct lp_build_tgsi_context
*bld_base
,
1966 const struct tgsi_full_src_register
*reg
,
1967 enum tgsi_opcode_type type
,
1970 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1971 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
1972 const struct tgsi_ind_register
*ireg
= ®
->Indirect
;
1975 LLVMValueRef addr
, bufp
;
1977 if (swizzle
== LP_CHAN_ALL
) {
1979 LLVMValueRef values
[4];
1980 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; ++chan
)
1981 values
[chan
] = fetch_constant(bld_base
, reg
, type
, chan
);
1983 return lp_build_gather_values(&ctx
->gallivm
, values
, 4);
1986 /* Split 64-bit loads. */
1987 if (tgsi_type_is_64bit(type
)) {
1988 LLVMValueRef lo
, hi
;
1990 lo
= fetch_constant(bld_base
, reg
, TGSI_TYPE_UNSIGNED
, swizzle
);
1991 hi
= fetch_constant(bld_base
, reg
, TGSI_TYPE_UNSIGNED
, swizzle
+ 1);
1992 return si_llvm_emit_fetch_64bit(bld_base
, tgsi2llvmtype(bld_base
, type
),
1996 idx
= reg
->Register
.Index
* 4 + swizzle
;
1997 if (reg
->Register
.Indirect
) {
1998 addr
= si_get_indirect_index(ctx
, ireg
, 16, idx
* 4);
2000 addr
= LLVMConstInt(ctx
->i32
, idx
* 4, 0);
2003 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2004 if (sel
->info
.const_buffers_declared
== 1 &&
2005 sel
->info
.shader_buffers_declared
== 0) {
2007 LLVMGetParam(ctx
->main_fn
, ctx
->param_const_and_shader_buffers
);
2009 /* This enables use of s_load_dword and flat_load_dword for const buffer 0
2010 * loads, and up to x4 load opcode merging. However, it leads to horrible
2011 * code reducing SIMD wave occupancy from 8 to 2 in many cases.
2013 * Using s_buffer_load_dword (x1) seems to be the best option right now.
2015 * LLVM 5.0 on SI doesn't insert a required s_nop between SALU setting
2016 * a descriptor and s_buffer_load_dword using it, so we can't expand
2017 * the pointer into a full descriptor like below. We have to use
2018 * s_load_dword instead. The only case when LLVM 5.0 would select
2019 * s_buffer_load_dword (that we have to prevent) is when we use use
2020 * a literal offset where we don't need bounds checking.
2022 if (ctx
->screen
->info
.chip_class
== SI
&&
2023 HAVE_LLVM
< 0x0600 &&
2024 !reg
->Register
.Indirect
) {
2025 addr
= LLVMBuildLShr(ctx
->ac
.builder
, addr
, LLVMConstInt(ctx
->i32
, 2, 0), "");
2026 LLVMValueRef result
= ac_build_load_invariant(&ctx
->ac
, ptr
, addr
);
2027 return bitcast(bld_base
, type
, result
);
2030 /* Do the bounds checking with a descriptor, because
2031 * doing computation and manual bounds checking of 64-bit
2032 * addresses generates horrible VALU code with very high
2033 * VGPR usage and very low SIMD occupancy.
2035 ptr
= LLVMBuildPtrToInt(ctx
->ac
.builder
, ptr
, ctx
->i64
, "");
2036 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
, ctx
->v2i32
, "");
2038 LLVMValueRef desc_elems
[] = {
2039 LLVMBuildExtractElement(ctx
->ac
.builder
, ptr
, ctx
->i32_0
, ""),
2040 LLVMBuildExtractElement(ctx
->ac
.builder
, ptr
, ctx
->i32_1
, ""),
2041 LLVMConstInt(ctx
->i32
, (sel
->info
.const_file_max
[0] + 1) * 16, 0),
2042 LLVMConstInt(ctx
->i32
,
2043 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2044 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2045 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2046 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2047 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2048 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
), 0)
2050 LLVMValueRef desc
= ac_build_gather_values(&ctx
->ac
, desc_elems
, 4);
2051 LLVMValueRef result
= buffer_load_const(ctx
, desc
, addr
);
2052 return bitcast(bld_base
, type
, result
);
2055 assert(reg
->Register
.Dimension
);
2056 buf
= reg
->Dimension
.Index
;
2058 if (reg
->Dimension
.Indirect
) {
2059 LLVMValueRef ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_const_and_shader_buffers
);
2061 index
= si_get_bounded_indirect_index(ctx
, ®
->DimIndirect
,
2062 reg
->Dimension
.Index
,
2063 ctx
->num_const_buffers
);
2064 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
2065 LLVMConstInt(ctx
->i32
, SI_NUM_SHADER_BUFFERS
, 0), "");
2066 bufp
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
, index
);
2068 bufp
= load_const_buffer_desc(ctx
, buf
);
2070 return bitcast(bld_base
, type
, buffer_load_const(ctx
, bufp
, addr
));
2073 /* Upper 16 bits must be zero. */
2074 static LLVMValueRef
si_llvm_pack_two_int16(struct si_shader_context
*ctx
,
2075 LLVMValueRef val
[2])
2077 return LLVMBuildOr(ctx
->ac
.builder
, val
[0],
2078 LLVMBuildShl(ctx
->ac
.builder
, val
[1],
2079 LLVMConstInt(ctx
->i32
, 16, 0),
2083 /* Upper 16 bits are ignored and will be dropped. */
2084 static LLVMValueRef
si_llvm_pack_two_int32_as_int16(struct si_shader_context
*ctx
,
2085 LLVMValueRef val
[2])
2087 LLVMValueRef v
[2] = {
2088 LLVMBuildAnd(ctx
->ac
.builder
, val
[0],
2089 LLVMConstInt(ctx
->i32
, 0xffff, 0), ""),
2092 return si_llvm_pack_two_int16(ctx
, v
);
2095 /* Initialize arguments for the shader export intrinsic */
2096 static void si_llvm_init_export_args(struct si_shader_context
*ctx
,
2097 LLVMValueRef
*values
,
2099 struct ac_export_args
*args
)
2101 LLVMValueRef f32undef
= LLVMGetUndef(ctx
->ac
.f32
);
2102 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2103 LLVMValueRef val
[4];
2104 unsigned spi_shader_col_format
= V_028714_SPI_SHADER_32_ABGR
;
2106 bool is_int8
, is_int10
;
2108 /* Default is 0xf. Adjusted below depending on the format. */
2109 args
->enabled_channels
= 0xf; /* writemask */
2111 /* Specify whether the EXEC mask represents the valid mask */
2112 args
->valid_mask
= 0;
2114 /* Specify whether this is the last export */
2117 /* Specify the target we are exporting */
2118 args
->target
= target
;
2120 if (ctx
->type
== PIPE_SHADER_FRAGMENT
) {
2121 const struct si_shader_key
*key
= &ctx
->shader
->key
;
2122 unsigned col_formats
= key
->part
.ps
.epilog
.spi_shader_col_format
;
2123 int cbuf
= target
- V_008DFC_SQ_EXP_MRT
;
2125 assert(cbuf
>= 0 && cbuf
< 8);
2126 spi_shader_col_format
= (col_formats
>> (cbuf
* 4)) & 0xf;
2127 is_int8
= (key
->part
.ps
.epilog
.color_is_int8
>> cbuf
) & 0x1;
2128 is_int10
= (key
->part
.ps
.epilog
.color_is_int10
>> cbuf
) & 0x1;
2131 args
->compr
= false;
2132 args
->out
[0] = f32undef
;
2133 args
->out
[1] = f32undef
;
2134 args
->out
[2] = f32undef
;
2135 args
->out
[3] = f32undef
;
2137 switch (spi_shader_col_format
) {
2138 case V_028714_SPI_SHADER_ZERO
:
2139 args
->enabled_channels
= 0; /* writemask */
2140 args
->target
= V_008DFC_SQ_EXP_NULL
;
2143 case V_028714_SPI_SHADER_32_R
:
2144 args
->enabled_channels
= 1; /* writemask */
2145 args
->out
[0] = values
[0];
2148 case V_028714_SPI_SHADER_32_GR
:
2149 args
->enabled_channels
= 0x3; /* writemask */
2150 args
->out
[0] = values
[0];
2151 args
->out
[1] = values
[1];
2154 case V_028714_SPI_SHADER_32_AR
:
2155 args
->enabled_channels
= 0x9; /* writemask */
2156 args
->out
[0] = values
[0];
2157 args
->out
[3] = values
[3];
2160 case V_028714_SPI_SHADER_FP16_ABGR
:
2161 args
->compr
= 1; /* COMPR flag */
2163 for (chan
= 0; chan
< 2; chan
++) {
2164 LLVMValueRef pack_args
[2] = {
2166 values
[2 * chan
+ 1]
2168 LLVMValueRef packed
;
2170 packed
= ac_build_cvt_pkrtz_f16(&ctx
->ac
, pack_args
);
2171 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2175 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2176 for (chan
= 0; chan
< 4; chan
++) {
2177 val
[chan
] = ac_build_clamp(&ctx
->ac
, values
[chan
]);
2178 val
[chan
] = LLVMBuildFMul(builder
, val
[chan
],
2179 LLVMConstReal(ctx
->f32
, 65535), "");
2180 val
[chan
] = LLVMBuildFAdd(builder
, val
[chan
],
2181 LLVMConstReal(ctx
->f32
, 0.5), "");
2182 val
[chan
] = LLVMBuildFPToUI(builder
, val
[chan
],
2186 args
->compr
= 1; /* COMPR flag */
2187 args
->out
[0] = ac_to_float(&ctx
->ac
, si_llvm_pack_two_int16(ctx
, val
));
2188 args
->out
[1] = ac_to_float(&ctx
->ac
, si_llvm_pack_two_int16(ctx
, val
+2));
2191 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2192 for (chan
= 0; chan
< 4; chan
++) {
2193 /* Clamp between [-1, 1]. */
2194 val
[chan
] = lp_build_emit_llvm_binary(&ctx
->bld_base
, TGSI_OPCODE_MIN
,
2196 LLVMConstReal(ctx
->f32
, 1));
2197 val
[chan
] = lp_build_emit_llvm_binary(&ctx
->bld_base
, TGSI_OPCODE_MAX
,
2199 LLVMConstReal(ctx
->f32
, -1));
2200 /* Convert to a signed integer in [-32767, 32767]. */
2201 val
[chan
] = LLVMBuildFMul(builder
, val
[chan
],
2202 LLVMConstReal(ctx
->f32
, 32767), "");
2203 /* If positive, add 0.5, else add -0.5. */
2204 val
[chan
] = LLVMBuildFAdd(builder
, val
[chan
],
2205 LLVMBuildSelect(builder
,
2206 LLVMBuildFCmp(builder
, LLVMRealOGE
,
2207 val
[chan
], ctx
->ac
.f32_0
, ""),
2208 LLVMConstReal(ctx
->f32
, 0.5),
2209 LLVMConstReal(ctx
->f32
, -0.5), ""), "");
2210 val
[chan
] = LLVMBuildFPToSI(builder
, val
[chan
], ctx
->i32
, "");
2213 args
->compr
= 1; /* COMPR flag */
2214 args
->out
[0] = ac_to_float(&ctx
->ac
, si_llvm_pack_two_int32_as_int16(ctx
, val
));
2215 args
->out
[1] = ac_to_float(&ctx
->ac
, si_llvm_pack_two_int32_as_int16(ctx
, val
+2));
2218 case V_028714_SPI_SHADER_UINT16_ABGR
: {
2219 LLVMValueRef max_rgb
= LLVMConstInt(ctx
->i32
,
2220 is_int8
? 255 : is_int10
? 1023 : 65535, 0);
2221 LLVMValueRef max_alpha
=
2222 !is_int10
? max_rgb
: LLVMConstInt(ctx
->i32
, 3, 0);
2225 for (chan
= 0; chan
< 4; chan
++) {
2226 val
[chan
] = ac_to_integer(&ctx
->ac
, values
[chan
]);
2227 val
[chan
] = lp_build_emit_llvm_binary(&ctx
->bld_base
, TGSI_OPCODE_UMIN
,
2229 chan
== 3 ? max_alpha
: max_rgb
);
2232 args
->compr
= 1; /* COMPR flag */
2233 args
->out
[0] = ac_to_float(&ctx
->ac
, si_llvm_pack_two_int16(ctx
, val
));
2234 args
->out
[1] = ac_to_float(&ctx
->ac
, si_llvm_pack_two_int16(ctx
, val
+2));
2238 case V_028714_SPI_SHADER_SINT16_ABGR
: {
2239 LLVMValueRef max_rgb
= LLVMConstInt(ctx
->i32
,
2240 is_int8
? 127 : is_int10
? 511 : 32767, 0);
2241 LLVMValueRef min_rgb
= LLVMConstInt(ctx
->i32
,
2242 is_int8
? -128 : is_int10
? -512 : -32768, 0);
2243 LLVMValueRef max_alpha
=
2244 !is_int10
? max_rgb
: ctx
->i32_1
;
2245 LLVMValueRef min_alpha
=
2246 !is_int10
? min_rgb
: LLVMConstInt(ctx
->i32
, -2, 0);
2249 for (chan
= 0; chan
< 4; chan
++) {
2250 val
[chan
] = ac_to_integer(&ctx
->ac
, values
[chan
]);
2251 val
[chan
] = lp_build_emit_llvm_binary(&ctx
->bld_base
,
2253 val
[chan
], chan
== 3 ? max_alpha
: max_rgb
);
2254 val
[chan
] = lp_build_emit_llvm_binary(&ctx
->bld_base
,
2256 val
[chan
], chan
== 3 ? min_alpha
: min_rgb
);
2259 args
->compr
= 1; /* COMPR flag */
2260 args
->out
[0] = ac_to_float(&ctx
->ac
, si_llvm_pack_two_int32_as_int16(ctx
, val
));
2261 args
->out
[1] = ac_to_float(&ctx
->ac
, si_llvm_pack_two_int32_as_int16(ctx
, val
+2));
2265 case V_028714_SPI_SHADER_32_ABGR
:
2266 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2271 static void si_alpha_test(struct lp_build_tgsi_context
*bld_base
,
2274 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2276 if (ctx
->shader
->key
.part
.ps
.epilog
.alpha_func
!= PIPE_FUNC_NEVER
) {
2277 static LLVMRealPredicate cond_map
[PIPE_FUNC_ALWAYS
+ 1] = {
2278 [PIPE_FUNC_LESS
] = LLVMRealOLT
,
2279 [PIPE_FUNC_EQUAL
] = LLVMRealOEQ
,
2280 [PIPE_FUNC_LEQUAL
] = LLVMRealOLE
,
2281 [PIPE_FUNC_GREATER
] = LLVMRealOGT
,
2282 [PIPE_FUNC_NOTEQUAL
] = LLVMRealONE
,
2283 [PIPE_FUNC_GEQUAL
] = LLVMRealOGE
,
2285 LLVMRealPredicate cond
= cond_map
[ctx
->shader
->key
.part
.ps
.epilog
.alpha_func
];
2288 LLVMValueRef alpha_ref
= LLVMGetParam(ctx
->main_fn
,
2289 SI_PARAM_ALPHA_REF
);
2290 LLVMValueRef alpha_pass
=
2291 LLVMBuildFCmp(ctx
->ac
.builder
, cond
, alpha
, alpha_ref
, "");
2292 ac_build_kill_if_false(&ctx
->ac
, alpha_pass
);
2294 ac_build_kill_if_false(&ctx
->ac
, LLVMConstInt(ctx
->i1
, 0, 0));
2298 static LLVMValueRef
si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context
*bld_base
,
2300 unsigned samplemask_param
)
2302 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2303 LLVMValueRef coverage
;
2305 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2306 coverage
= LLVMGetParam(ctx
->main_fn
,
2308 coverage
= ac_to_integer(&ctx
->ac
, coverage
);
2310 coverage
= lp_build_intrinsic(ctx
->ac
.builder
, "llvm.ctpop.i32",
2312 &coverage
, 1, LP_FUNC_ATTR_READNONE
);
2314 coverage
= LLVMBuildUIToFP(ctx
->ac
.builder
, coverage
,
2317 coverage
= LLVMBuildFMul(ctx
->ac
.builder
, coverage
,
2318 LLVMConstReal(ctx
->f32
,
2319 1.0 / SI_NUM_SMOOTH_AA_SAMPLES
), "");
2321 return LLVMBuildFMul(ctx
->ac
.builder
, alpha
, coverage
, "");
2324 static void si_llvm_emit_clipvertex(struct si_shader_context
*ctx
,
2325 struct ac_export_args
*pos
, LLVMValueRef
*out_elts
)
2329 unsigned const_chan
;
2330 LLVMValueRef base_elt
;
2331 LLVMValueRef ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
2332 LLVMValueRef constbuf_index
= LLVMConstInt(ctx
->i32
,
2333 SI_VS_CONST_CLIP_PLANES
, 0);
2334 LLVMValueRef const_resource
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
, constbuf_index
);
2336 for (reg_index
= 0; reg_index
< 2; reg_index
++) {
2337 struct ac_export_args
*args
= &pos
[2 + reg_index
];
2342 args
->out
[3] = LLVMConstReal(ctx
->f32
, 0.0f
);
2344 /* Compute dot products of position and user clip plane vectors */
2345 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2346 for (const_chan
= 0; const_chan
< TGSI_NUM_CHANNELS
; const_chan
++) {
2348 LLVMConstInt(ctx
->i32
, ((reg_index
* 4 + chan
) * 4 +
2349 const_chan
) * 4, 0);
2350 base_elt
= buffer_load_const(ctx
, const_resource
,
2353 lp_build_add(&ctx
->bld_base
.base
, args
->out
[chan
],
2354 lp_build_mul(&ctx
->bld_base
.base
, base_elt
,
2355 out_elts
[const_chan
]));
2359 args
->enabled_channels
= 0xf;
2360 args
->valid_mask
= 0;
2362 args
->target
= V_008DFC_SQ_EXP_POS
+ 2 + reg_index
;
2367 static void si_dump_streamout(struct pipe_stream_output_info
*so
)
2371 if (so
->num_outputs
)
2372 fprintf(stderr
, "STREAMOUT\n");
2374 for (i
= 0; i
< so
->num_outputs
; i
++) {
2375 unsigned mask
= ((1 << so
->output
[i
].num_components
) - 1) <<
2376 so
->output
[i
].start_component
;
2377 fprintf(stderr
, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2378 i
, so
->output
[i
].output_buffer
,
2379 so
->output
[i
].dst_offset
, so
->output
[i
].dst_offset
+ so
->output
[i
].num_components
- 1,
2380 so
->output
[i
].register_index
,
2381 mask
& 1 ? "x" : "",
2382 mask
& 2 ? "y" : "",
2383 mask
& 4 ? "z" : "",
2384 mask
& 8 ? "w" : "");
2388 static void emit_streamout_output(struct si_shader_context
*ctx
,
2389 LLVMValueRef
const *so_buffers
,
2390 LLVMValueRef
const *so_write_offsets
,
2391 struct pipe_stream_output
*stream_out
,
2392 struct si_shader_output_values
*shader_out
)
2394 unsigned buf_idx
= stream_out
->output_buffer
;
2395 unsigned start
= stream_out
->start_component
;
2396 unsigned num_comps
= stream_out
->num_components
;
2397 LLVMValueRef out
[4];
2399 assert(num_comps
&& num_comps
<= 4);
2400 if (!num_comps
|| num_comps
> 4)
2403 /* Load the output as int. */
2404 for (int j
= 0; j
< num_comps
; j
++) {
2405 assert(stream_out
->stream
== shader_out
->vertex_stream
[start
+ j
]);
2407 out
[j
] = ac_to_integer(&ctx
->ac
, shader_out
->values
[start
+ j
]);
2410 /* Pack the output. */
2411 LLVMValueRef vdata
= NULL
;
2413 switch (num_comps
) {
2414 case 1: /* as i32 */
2417 case 2: /* as v2i32 */
2418 case 3: /* as v4i32 (aligned to 4) */
2419 case 4: /* as v4i32 */
2420 vdata
= LLVMGetUndef(LLVMVectorType(ctx
->i32
, util_next_power_of_two(num_comps
)));
2421 for (int j
= 0; j
< num_comps
; j
++) {
2422 vdata
= LLVMBuildInsertElement(ctx
->ac
.builder
, vdata
, out
[j
],
2423 LLVMConstInt(ctx
->i32
, j
, 0), "");
2428 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf_idx
],
2430 so_write_offsets
[buf_idx
],
2432 stream_out
->dst_offset
* 4, 1, 1, true, false);
2436 * Write streamout data to buffers for vertex stream @p stream (different
2437 * vertex streams can occur for GS copy shaders).
2439 static void si_llvm_emit_streamout(struct si_shader_context
*ctx
,
2440 struct si_shader_output_values
*outputs
,
2441 unsigned noutput
, unsigned stream
)
2443 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2444 struct pipe_stream_output_info
*so
= &sel
->so
;
2445 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2447 struct lp_build_if_state if_ctx
;
2449 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2450 LLVMValueRef so_vtx_count
=
2451 unpack_param(ctx
, ctx
->param_streamout_config
, 16, 7);
2453 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
2455 /* can_emit = tid < so_vtx_count; */
2456 LLVMValueRef can_emit
=
2457 LLVMBuildICmp(builder
, LLVMIntULT
, tid
, so_vtx_count
, "");
2459 /* Emit the streamout code conditionally. This actually avoids
2460 * out-of-bounds buffer access. The hw tells us via the SGPR
2461 * (so_vtx_count) which threads are allowed to emit streamout data. */
2462 lp_build_if(&if_ctx
, &ctx
->gallivm
, can_emit
);
2464 /* The buffer offset is computed as follows:
2465 * ByteOffset = streamout_offset[buffer_id]*4 +
2466 * (streamout_write_index + thread_id)*stride[buffer_id] +
2470 LLVMValueRef so_write_index
=
2471 LLVMGetParam(ctx
->main_fn
,
2472 ctx
->param_streamout_write_index
);
2474 /* Compute (streamout_write_index + thread_id). */
2475 so_write_index
= LLVMBuildAdd(builder
, so_write_index
, tid
, "");
2477 /* Load the descriptor and compute the write offset for each
2478 * enabled buffer. */
2479 LLVMValueRef so_write_offset
[4] = {};
2480 LLVMValueRef so_buffers
[4];
2481 LLVMValueRef buf_ptr
= LLVMGetParam(ctx
->main_fn
,
2482 ctx
->param_rw_buffers
);
2484 for (i
= 0; i
< 4; i
++) {
2488 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
,
2489 SI_VS_STREAMOUT_BUF0
+ i
, 0);
2491 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
, offset
);
2493 LLVMValueRef so_offset
= LLVMGetParam(ctx
->main_fn
,
2494 ctx
->param_streamout_offset
[i
]);
2495 so_offset
= LLVMBuildMul(builder
, so_offset
, LLVMConstInt(ctx
->i32
, 4, 0), "");
2497 so_write_offset
[i
] = LLVMBuildMul(builder
, so_write_index
,
2498 LLVMConstInt(ctx
->i32
, so
->stride
[i
]*4, 0), "");
2499 so_write_offset
[i
] = LLVMBuildAdd(builder
, so_write_offset
[i
], so_offset
, "");
2502 /* Write streamout data. */
2503 for (i
= 0; i
< so
->num_outputs
; i
++) {
2504 unsigned reg
= so
->output
[i
].register_index
;
2509 if (stream
!= so
->output
[i
].stream
)
2512 emit_streamout_output(ctx
, so_buffers
, so_write_offset
,
2513 &so
->output
[i
], &outputs
[reg
]);
2516 lp_build_endif(&if_ctx
);
2519 static void si_export_param(struct si_shader_context
*ctx
, unsigned index
,
2520 LLVMValueRef
*values
)
2522 struct ac_export_args args
;
2524 si_llvm_init_export_args(ctx
, values
,
2525 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
2526 ac_build_export(&ctx
->ac
, &args
);
2529 static void si_build_param_exports(struct si_shader_context
*ctx
,
2530 struct si_shader_output_values
*outputs
,
2533 struct si_shader
*shader
= ctx
->shader
;
2534 unsigned param_count
= 0;
2536 for (unsigned i
= 0; i
< noutput
; i
++) {
2537 unsigned semantic_name
= outputs
[i
].semantic_name
;
2538 unsigned semantic_index
= outputs
[i
].semantic_index
;
2540 if (outputs
[i
].vertex_stream
[0] != 0 &&
2541 outputs
[i
].vertex_stream
[1] != 0 &&
2542 outputs
[i
].vertex_stream
[2] != 0 &&
2543 outputs
[i
].vertex_stream
[3] != 0)
2546 switch (semantic_name
) {
2547 case TGSI_SEMANTIC_LAYER
:
2548 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
2549 case TGSI_SEMANTIC_CLIPDIST
:
2550 case TGSI_SEMANTIC_COLOR
:
2551 case TGSI_SEMANTIC_BCOLOR
:
2552 case TGSI_SEMANTIC_PRIMID
:
2553 case TGSI_SEMANTIC_FOG
:
2554 case TGSI_SEMANTIC_TEXCOORD
:
2555 case TGSI_SEMANTIC_GENERIC
:
2561 if ((semantic_name
!= TGSI_SEMANTIC_GENERIC
||
2562 semantic_index
< SI_MAX_IO_GENERIC
) &&
2563 shader
->key
.opt
.kill_outputs
&
2564 (1ull << si_shader_io_get_unique_index(semantic_name
, semantic_index
)))
2567 si_export_param(ctx
, param_count
, outputs
[i
].values
);
2569 assert(i
< ARRAY_SIZE(shader
->info
.vs_output_param_offset
));
2570 shader
->info
.vs_output_param_offset
[i
] = param_count
++;
2573 shader
->info
.nr_param_exports
= param_count
;
2576 /* Generate export instructions for hardware VS shader stage */
2577 static void si_llvm_export_vs(struct si_shader_context
*ctx
,
2578 struct si_shader_output_values
*outputs
,
2581 struct si_shader
*shader
= ctx
->shader
;
2582 struct ac_export_args pos_args
[4] = {};
2583 LLVMValueRef psize_value
= NULL
, edgeflag_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
2587 /* Build position exports. */
2588 for (i
= 0; i
< noutput
; i
++) {
2589 switch (outputs
[i
].semantic_name
) {
2590 case TGSI_SEMANTIC_POSITION
:
2591 si_llvm_init_export_args(ctx
, outputs
[i
].values
,
2592 V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
2594 case TGSI_SEMANTIC_PSIZE
:
2595 psize_value
= outputs
[i
].values
[0];
2597 case TGSI_SEMANTIC_LAYER
:
2598 layer_value
= outputs
[i
].values
[0];
2600 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
2601 viewport_index_value
= outputs
[i
].values
[0];
2603 case TGSI_SEMANTIC_EDGEFLAG
:
2604 edgeflag_value
= outputs
[i
].values
[0];
2606 case TGSI_SEMANTIC_CLIPDIST
:
2607 if (!shader
->key
.opt
.clip_disable
) {
2608 unsigned index
= 2 + outputs
[i
].semantic_index
;
2609 si_llvm_init_export_args(ctx
, outputs
[i
].values
,
2610 V_008DFC_SQ_EXP_POS
+ index
,
2614 case TGSI_SEMANTIC_CLIPVERTEX
:
2615 if (!shader
->key
.opt
.clip_disable
) {
2616 si_llvm_emit_clipvertex(ctx
, pos_args
,
2623 /* We need to add the position output manually if it's missing. */
2624 if (!pos_args
[0].out
[0]) {
2625 pos_args
[0].enabled_channels
= 0xf; /* writemask */
2626 pos_args
[0].valid_mask
= 0; /* EXEC mask */
2627 pos_args
[0].done
= 0; /* last export? */
2628 pos_args
[0].target
= V_008DFC_SQ_EXP_POS
;
2629 pos_args
[0].compr
= 0; /* COMPR flag */
2630 pos_args
[0].out
[0] = ctx
->ac
.f32_0
; /* X */
2631 pos_args
[0].out
[1] = ctx
->ac
.f32_0
; /* Y */
2632 pos_args
[0].out
[2] = ctx
->ac
.f32_0
; /* Z */
2633 pos_args
[0].out
[3] = ctx
->ac
.f32_1
; /* W */
2636 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2637 if (shader
->selector
->info
.writes_psize
||
2638 shader
->selector
->info
.writes_edgeflag
||
2639 shader
->selector
->info
.writes_viewport_index
||
2640 shader
->selector
->info
.writes_layer
) {
2641 pos_args
[1].enabled_channels
= shader
->selector
->info
.writes_psize
|
2642 (shader
->selector
->info
.writes_edgeflag
<< 1) |
2643 (shader
->selector
->info
.writes_layer
<< 2);
2645 pos_args
[1].valid_mask
= 0; /* EXEC mask */
2646 pos_args
[1].done
= 0; /* last export? */
2647 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
2648 pos_args
[1].compr
= 0; /* COMPR flag */
2649 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
2650 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
2651 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
2652 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
2654 if (shader
->selector
->info
.writes_psize
)
2655 pos_args
[1].out
[0] = psize_value
;
2657 if (shader
->selector
->info
.writes_edgeflag
) {
2658 /* The output is a float, but the hw expects an integer
2659 * with the first bit containing the edge flag. */
2660 edgeflag_value
= LLVMBuildFPToUI(ctx
->ac
.builder
,
2663 edgeflag_value
= ac_build_umin(&ctx
->ac
,
2667 /* The LLVM intrinsic expects a float. */
2668 pos_args
[1].out
[1] = ac_to_float(&ctx
->ac
, edgeflag_value
);
2671 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
2672 /* GFX9 has the layer in out.z[10:0] and the viewport
2673 * index in out.z[19:16].
2675 if (shader
->selector
->info
.writes_layer
)
2676 pos_args
[1].out
[2] = layer_value
;
2678 if (shader
->selector
->info
.writes_viewport_index
) {
2679 LLVMValueRef v
= viewport_index_value
;
2681 v
= ac_to_integer(&ctx
->ac
, v
);
2682 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
2683 LLVMConstInt(ctx
->i32
, 16, 0), "");
2684 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
2685 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
2686 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
2687 pos_args
[1].enabled_channels
|= 1 << 2;
2690 if (shader
->selector
->info
.writes_layer
)
2691 pos_args
[1].out
[2] = layer_value
;
2693 if (shader
->selector
->info
.writes_viewport_index
) {
2694 pos_args
[1].out
[3] = viewport_index_value
;
2695 pos_args
[1].enabled_channels
|= 1 << 3;
2700 for (i
= 0; i
< 4; i
++)
2701 if (pos_args
[i
].out
[0])
2702 shader
->info
.nr_pos_exports
++;
2705 for (i
= 0; i
< 4; i
++) {
2706 if (!pos_args
[i
].out
[0])
2709 /* Specify the target we are exporting */
2710 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
2712 if (pos_idx
== shader
->info
.nr_pos_exports
)
2713 /* Specify that this is the last export */
2714 pos_args
[i
].done
= 1;
2716 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
2719 /* Build parameter exports. */
2720 si_build_param_exports(ctx
, outputs
, noutput
);
2724 * Forward all outputs from the vertex shader to the TES. This is only used
2725 * for the fixed function TCS.
2727 static void si_copy_tcs_inputs(struct lp_build_tgsi_context
*bld_base
)
2729 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2730 LLVMValueRef invocation_id
, buffer
, buffer_offset
;
2731 LLVMValueRef lds_vertex_stride
, lds_vertex_offset
, lds_base
;
2734 invocation_id
= unpack_param(ctx
, ctx
->param_tcs_rel_ids
, 8, 5);
2735 buffer
= desc_from_addr_base64k(ctx
, ctx
->param_tcs_offchip_addr_base64k
);
2736 buffer_offset
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
2738 lds_vertex_stride
= get_tcs_in_vertex_dw_stride(ctx
);
2739 lds_vertex_offset
= LLVMBuildMul(ctx
->ac
.builder
, invocation_id
,
2740 lds_vertex_stride
, "");
2741 lds_base
= get_tcs_in_current_patch_offset(ctx
);
2742 lds_base
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
, lds_vertex_offset
, "");
2744 inputs
= ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
;
2746 unsigned i
= u_bit_scan64(&inputs
);
2748 LLVMValueRef lds_ptr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2749 LLVMConstInt(ctx
->i32
, 4 * i
, 0),
2752 LLVMValueRef buffer_addr
= get_tcs_tes_buffer_address(ctx
,
2753 get_rel_patch_id(ctx
),
2755 LLVMConstInt(ctx
->i32
, i
, 0));
2757 LLVMValueRef value
= lds_load(bld_base
, TGSI_TYPE_SIGNED
, ~0,
2760 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 4, buffer_addr
,
2761 buffer_offset
, 0, 1, 0, true, false);
2765 static void si_write_tess_factors(struct lp_build_tgsi_context
*bld_base
,
2766 LLVMValueRef rel_patch_id
,
2767 LLVMValueRef invocation_id
,
2768 LLVMValueRef tcs_out_current_patch_data_offset
,
2769 LLVMValueRef invoc0_tf_outer
[4],
2770 LLVMValueRef invoc0_tf_inner
[2])
2772 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2773 struct si_shader
*shader
= ctx
->shader
;
2774 unsigned tess_inner_index
, tess_outer_index
;
2775 LLVMValueRef lds_base
, lds_inner
, lds_outer
, byteoffset
, buffer
;
2776 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
2777 unsigned stride
, outer_comps
, inner_comps
, i
, offset
;
2778 struct lp_build_if_state if_ctx
, inner_if_ctx
;
2780 /* Add a barrier before loading tess factors from LDS. */
2781 if (!shader
->key
.part
.tcs
.epilog
.invoc0_tess_factors_are_def
)
2782 si_llvm_emit_barrier(NULL
, bld_base
, NULL
);
2784 /* Do this only for invocation 0, because the tess levels are per-patch,
2787 * This can't jump, because invocation 0 executes this. It should
2788 * at least mask out the loads and stores for other invocations.
2790 lp_build_if(&if_ctx
, &ctx
->gallivm
,
2791 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
2792 invocation_id
, ctx
->i32_0
, ""));
2794 /* Determine the layout of one tess factor element in the buffer. */
2795 switch (shader
->key
.part
.tcs
.epilog
.prim_mode
) {
2796 case PIPE_PRIM_LINES
:
2797 stride
= 2; /* 2 dwords, 1 vec2 store */
2801 case PIPE_PRIM_TRIANGLES
:
2802 stride
= 4; /* 4 dwords, 1 vec4 store */
2806 case PIPE_PRIM_QUADS
:
2807 stride
= 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2816 for (i
= 0; i
< 4; i
++) {
2817 inner
[i
] = LLVMGetUndef(ctx
->i32
);
2818 outer
[i
] = LLVMGetUndef(ctx
->i32
);
2821 if (shader
->key
.part
.tcs
.epilog
.invoc0_tess_factors_are_def
) {
2822 /* Tess factors are in VGPRs. */
2823 for (i
= 0; i
< outer_comps
; i
++)
2824 outer
[i
] = out
[i
] = invoc0_tf_outer
[i
];
2825 for (i
= 0; i
< inner_comps
; i
++)
2826 inner
[i
] = out
[outer_comps
+i
] = invoc0_tf_inner
[i
];
2828 /* Load tess_inner and tess_outer from LDS.
2829 * Any invocation can write them, so we can't get them from a temporary.
2831 tess_inner_index
= si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0);
2832 tess_outer_index
= si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0);
2834 lds_base
= tcs_out_current_patch_data_offset
;
2835 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2836 LLVMConstInt(ctx
->i32
,
2837 tess_inner_index
* 4, 0), "");
2838 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2839 LLVMConstInt(ctx
->i32
,
2840 tess_outer_index
* 4, 0), "");
2842 for (i
= 0; i
< outer_comps
; i
++) {
2844 lds_load(bld_base
, TGSI_TYPE_SIGNED
, i
, lds_outer
);
2846 for (i
= 0; i
< inner_comps
; i
++) {
2847 inner
[i
] = out
[outer_comps
+i
] =
2848 lds_load(bld_base
, TGSI_TYPE_SIGNED
, i
, lds_inner
);
2852 if (shader
->key
.part
.tcs
.epilog
.prim_mode
== PIPE_PRIM_LINES
) {
2853 /* For isolines, the hardware expects tess factors in the
2854 * reverse order from what GLSL / TGSI specify.
2856 LLVMValueRef tmp
= out
[0];
2861 /* Convert the outputs to vectors for stores. */
2862 vec0
= lp_build_gather_values(&ctx
->gallivm
, out
, MIN2(stride
, 4));
2866 vec1
= lp_build_gather_values(&ctx
->gallivm
, out
+4, stride
- 4);
2868 /* Get the buffer. */
2869 buffer
= desc_from_addr_base64k(ctx
, ctx
->param_tcs_factor_addr_base64k
);
2871 /* Get the offset. */
2872 tf_base
= LLVMGetParam(ctx
->main_fn
,
2873 ctx
->param_tcs_factor_offset
);
2874 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
2875 LLVMConstInt(ctx
->i32
, 4 * stride
, 0), "");
2877 lp_build_if(&inner_if_ctx
, &ctx
->gallivm
,
2878 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
2879 rel_patch_id
, ctx
->i32_0
, ""));
2881 /* Store the dynamic HS control word. */
2883 if (ctx
->screen
->info
.chip_class
<= VI
) {
2884 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
2885 LLVMConstInt(ctx
->i32
, 0x80000000, 0),
2886 1, ctx
->i32_0
, tf_base
,
2887 offset
, 1, 0, true, false);
2891 lp_build_endif(&inner_if_ctx
);
2893 /* Store the tessellation factors. */
2894 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
2895 MIN2(stride
, 4), byteoffset
, tf_base
,
2896 offset
, 1, 0, true, false);
2899 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
2900 stride
- 4, byteoffset
, tf_base
,
2901 offset
, 1, 0, true, false);
2903 /* Store the tess factors into the offchip buffer if TES reads them. */
2904 if (shader
->key
.part
.tcs
.epilog
.tes_reads_tess_factors
) {
2905 LLVMValueRef buf
, base
, inner_vec
, outer_vec
, tf_outer_offset
;
2906 LLVMValueRef tf_inner_offset
;
2907 unsigned param_outer
, param_inner
;
2909 buf
= desc_from_addr_base64k(ctx
, ctx
->param_tcs_offchip_addr_base64k
);
2910 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
2912 param_outer
= si_shader_io_get_unique_index_patch(
2913 TGSI_SEMANTIC_TESSOUTER
, 0);
2914 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, rel_patch_id
, NULL
,
2915 LLVMConstInt(ctx
->i32
, param_outer
, 0));
2917 outer_vec
= lp_build_gather_values(&ctx
->gallivm
, outer
,
2918 util_next_power_of_two(outer_comps
));
2920 ac_build_buffer_store_dword(&ctx
->ac
, buf
, outer_vec
,
2921 outer_comps
, tf_outer_offset
,
2922 base
, 0, 1, 0, true, false);
2924 param_inner
= si_shader_io_get_unique_index_patch(
2925 TGSI_SEMANTIC_TESSINNER
, 0);
2926 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, rel_patch_id
, NULL
,
2927 LLVMConstInt(ctx
->i32
, param_inner
, 0));
2929 inner_vec
= inner_comps
== 1 ? inner
[0] :
2930 lp_build_gather_values(&ctx
->gallivm
, inner
, inner_comps
);
2931 ac_build_buffer_store_dword(&ctx
->ac
, buf
, inner_vec
,
2932 inner_comps
, tf_inner_offset
,
2933 base
, 0, 1, 0, true, false);
2937 lp_build_endif(&if_ctx
);
2941 si_insert_input_ret(struct si_shader_context
*ctx
, LLVMValueRef ret
,
2942 unsigned param
, unsigned return_index
)
2944 return LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
2945 LLVMGetParam(ctx
->main_fn
, param
),
2950 si_insert_input_ret_float(struct si_shader_context
*ctx
, LLVMValueRef ret
,
2951 unsigned param
, unsigned return_index
)
2953 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2954 LLVMValueRef p
= LLVMGetParam(ctx
->main_fn
, param
);
2956 return LLVMBuildInsertValue(builder
, ret
,
2957 ac_to_float(&ctx
->ac
, p
),
2962 si_insert_input_ptr_as_2xi32(struct si_shader_context
*ctx
, LLVMValueRef ret
,
2963 unsigned param
, unsigned return_index
)
2965 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2966 LLVMValueRef ptr
, lo
, hi
;
2968 ptr
= LLVMGetParam(ctx
->main_fn
, param
);
2969 ptr
= LLVMBuildPtrToInt(builder
, ptr
, ctx
->i64
, "");
2970 ptr
= LLVMBuildBitCast(builder
, ptr
, ctx
->v2i32
, "");
2971 lo
= LLVMBuildExtractElement(builder
, ptr
, ctx
->i32_0
, "");
2972 hi
= LLVMBuildExtractElement(builder
, ptr
, ctx
->i32_1
, "");
2973 ret
= LLVMBuildInsertValue(builder
, ret
, lo
, return_index
, "");
2974 return LLVMBuildInsertValue(builder
, ret
, hi
, return_index
+ 1, "");
2977 /* This only writes the tessellation factor levels. */
2978 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context
*bld_base
)
2980 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2981 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2982 LLVMValueRef rel_patch_id
, invocation_id
, tf_lds_offset
;
2984 si_copy_tcs_inputs(bld_base
);
2986 rel_patch_id
= get_rel_patch_id(ctx
);
2987 invocation_id
= unpack_param(ctx
, ctx
->param_tcs_rel_ids
, 8, 5);
2988 tf_lds_offset
= get_tcs_out_current_patch_data_offset(ctx
);
2990 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
2991 LLVMBasicBlockRef blocks
[2] = {
2992 LLVMGetInsertBlock(builder
),
2993 ctx
->merged_wrap_if_state
.entry_block
2995 LLVMValueRef values
[2];
2997 lp_build_endif(&ctx
->merged_wrap_if_state
);
2999 values
[0] = rel_patch_id
;
3000 values
[1] = LLVMGetUndef(ctx
->i32
);
3001 rel_patch_id
= ac_build_phi(&ctx
->ac
, ctx
->i32
, 2, values
, blocks
);
3003 values
[0] = tf_lds_offset
;
3004 values
[1] = LLVMGetUndef(ctx
->i32
);
3005 tf_lds_offset
= ac_build_phi(&ctx
->ac
, ctx
->i32
, 2, values
, blocks
);
3007 values
[0] = invocation_id
;
3008 values
[1] = ctx
->i32_1
; /* cause the epilog to skip threads */
3009 invocation_id
= ac_build_phi(&ctx
->ac
, ctx
->i32
, 2, values
, blocks
);
3012 /* Return epilog parameters from this function. */
3013 LLVMValueRef ret
= ctx
->return_value
;
3016 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
3017 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_layout
,
3018 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT
);
3019 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_addr_base64k
,
3020 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K
);
3021 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_factor_addr_base64k
,
3022 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K
);
3023 /* Tess offchip and tess factor offsets are at the beginning. */
3024 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_offset
, 2);
3025 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_factor_offset
, 4);
3026 vgpr
= 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K
+ 1;
3028 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_layout
,
3029 GFX6_SGPR_TCS_OFFCHIP_LAYOUT
);
3030 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_addr_base64k
,
3031 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K
);
3032 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_factor_addr_base64k
,
3033 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K
);
3034 /* Tess offchip and tess factor offsets are after user SGPRs. */
3035 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_offset
,
3036 GFX6_TCS_NUM_USER_SGPR
);
3037 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_factor_offset
,
3038 GFX6_TCS_NUM_USER_SGPR
+ 1);
3039 vgpr
= GFX6_TCS_NUM_USER_SGPR
+ 2;
3043 rel_patch_id
= ac_to_float(&ctx
->ac
, rel_patch_id
);
3044 invocation_id
= ac_to_float(&ctx
->ac
, invocation_id
);
3045 tf_lds_offset
= ac_to_float(&ctx
->ac
, tf_lds_offset
);
3047 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3048 * the invocation_id output does not alias the param_tcs_rel_ids input,
3049 * which saves a V_MOV on gfx9.
3053 ret
= LLVMBuildInsertValue(builder
, ret
, rel_patch_id
, vgpr
++, "");
3054 ret
= LLVMBuildInsertValue(builder
, ret
, invocation_id
, vgpr
++, "");
3056 if (ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
) {
3057 vgpr
++; /* skip the tess factor LDS offset */
3058 for (unsigned i
= 0; i
< 6; i
++) {
3059 LLVMValueRef value
=
3060 LLVMBuildLoad(builder
, ctx
->invoc0_tess_factors
[i
], "");
3061 value
= ac_to_float(&ctx
->ac
, value
);
3062 ret
= LLVMBuildInsertValue(builder
, ret
, value
, vgpr
++, "");
3065 ret
= LLVMBuildInsertValue(builder
, ret
, tf_lds_offset
, vgpr
++, "");
3067 ctx
->return_value
= ret
;
3070 /* Pass TCS inputs from LS to TCS on GFX9. */
3071 static void si_set_ls_return_value_for_tcs(struct si_shader_context
*ctx
)
3073 LLVMValueRef ret
= ctx
->return_value
;
3075 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_offset
, 2);
3076 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_merged_wave_info
, 3);
3077 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_factor_offset
, 4);
3078 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_merged_scratch_offset
, 5);
3080 ret
= si_insert_input_ptr_as_2xi32(ctx
, ret
, ctx
->param_rw_buffers
,
3081 8 + SI_SGPR_RW_BUFFERS
);
3082 ret
= si_insert_input_ptr_as_2xi32(ctx
, ret
,
3083 ctx
->param_bindless_samplers_and_images
,
3084 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
);
3086 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_vs_state_bits
,
3087 8 + SI_SGPR_VS_STATE_BITS
);
3088 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_layout
,
3089 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT
);
3090 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_out_lds_offsets
,
3091 8 + GFX9_SGPR_TCS_OUT_OFFSETS
);
3092 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_out_lds_layout
,
3093 8 + GFX9_SGPR_TCS_OUT_LAYOUT
);
3094 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_addr_base64k
,
3095 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K
);
3096 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_factor_addr_base64k
,
3097 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K
);
3099 unsigned desc_param
= ctx
->param_tcs_factor_addr_base64k
+ 2;
3100 ret
= si_insert_input_ptr_as_2xi32(ctx
, ret
, desc_param
,
3101 8 + GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS
);
3102 ret
= si_insert_input_ptr_as_2xi32(ctx
, ret
, desc_param
+ 1,
3103 8 + GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES
);
3105 unsigned vgpr
= 8 + GFX9_TCS_NUM_USER_SGPR
;
3106 ret
= si_insert_input_ret_float(ctx
, ret
,
3107 ctx
->param_tcs_patch_id
, vgpr
++);
3108 ret
= si_insert_input_ret_float(ctx
, ret
,
3109 ctx
->param_tcs_rel_ids
, vgpr
++);
3110 ctx
->return_value
= ret
;
3113 /* Pass GS inputs from ES to GS on GFX9. */
3114 static void si_set_es_return_value_for_gs(struct si_shader_context
*ctx
)
3116 LLVMValueRef ret
= ctx
->return_value
;
3118 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_gs2vs_offset
, 2);
3119 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_merged_wave_info
, 3);
3120 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_merged_scratch_offset
, 5);
3122 ret
= si_insert_input_ptr_as_2xi32(ctx
, ret
, ctx
->param_rw_buffers
,
3123 8 + SI_SGPR_RW_BUFFERS
);
3124 ret
= si_insert_input_ptr_as_2xi32(ctx
, ret
,
3125 ctx
->param_bindless_samplers_and_images
,
3126 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
);
3128 unsigned desc_param
= ctx
->param_vs_state_bits
+ 1;
3129 ret
= si_insert_input_ptr_as_2xi32(ctx
, ret
, desc_param
,
3130 8 + GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS
);
3131 ret
= si_insert_input_ptr_as_2xi32(ctx
, ret
, desc_param
+ 1,
3132 8 + GFX9_SGPR_GS_SAMPLERS_AND_IMAGES
);
3134 unsigned vgpr
= 8 + GFX9_GS_NUM_USER_SGPR
;
3135 for (unsigned i
= 0; i
< 5; i
++) {
3136 unsigned param
= ctx
->param_gs_vtx01_offset
+ i
;
3137 ret
= si_insert_input_ret_float(ctx
, ret
, param
, vgpr
++);
3139 ctx
->return_value
= ret
;
3142 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi
*abi
,
3143 unsigned max_outputs
,
3144 LLVMValueRef
*addrs
)
3146 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3147 struct si_shader
*shader
= ctx
->shader
;
3148 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
3150 LLVMValueRef vertex_id
= LLVMGetParam(ctx
->main_fn
,
3151 ctx
->param_rel_auto_id
);
3152 LLVMValueRef vertex_dw_stride
= get_tcs_in_vertex_dw_stride(ctx
);
3153 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
3154 vertex_dw_stride
, "");
3156 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3157 * its inputs from it. */
3158 for (i
= 0; i
< info
->num_outputs
; i
++) {
3159 unsigned name
= info
->output_semantic_name
[i
];
3160 unsigned index
= info
->output_semantic_index
[i
];
3162 /* The ARB_shader_viewport_layer_array spec contains the
3165 * 2) What happens if gl_ViewportIndex or gl_Layer is
3166 * written in the vertex shader and a geometry shader is
3169 * RESOLVED: The value written by the last vertex processing
3170 * stage is used. If the last vertex processing stage
3171 * (vertex, tessellation evaluation or geometry) does not
3172 * statically assign to gl_ViewportIndex or gl_Layer, index
3173 * or layer zero is assumed.
3175 * So writes to those outputs in VS-as-LS are simply ignored.
3177 if (name
== TGSI_SEMANTIC_LAYER
||
3178 name
== TGSI_SEMANTIC_VIEWPORT_INDEX
)
3181 int param
= si_shader_io_get_unique_index(name
, index
);
3182 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
3183 LLVMConstInt(ctx
->i32
, param
* 4, 0), "");
3185 for (chan
= 0; chan
< 4; chan
++) {
3186 if (!(info
->output_usagemask
[i
] & (1 << chan
)))
3189 lds_store(ctx
, chan
, dw_addr
,
3190 LLVMBuildLoad(ctx
->ac
.builder
, addrs
[4 * i
+ chan
], ""));
3194 if (ctx
->screen
->info
.chip_class
>= GFX9
)
3195 si_set_ls_return_value_for_tcs(ctx
);
3198 static void si_llvm_emit_es_epilogue(struct ac_shader_abi
*abi
,
3199 unsigned max_outputs
,
3200 LLVMValueRef
*addrs
)
3202 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3203 struct si_shader
*es
= ctx
->shader
;
3204 struct tgsi_shader_info
*info
= &es
->selector
->info
;
3205 LLVMValueRef soffset
= LLVMGetParam(ctx
->main_fn
,
3206 ctx
->param_es2gs_offset
);
3207 LLVMValueRef lds_base
= NULL
;
3211 if (ctx
->screen
->info
.chip_class
>= GFX9
&& info
->num_outputs
) {
3212 unsigned itemsize_dw
= es
->selector
->esgs_itemsize
/ 4;
3213 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
3214 LLVMValueRef wave_idx
= unpack_param(ctx
, ctx
->param_merged_wave_info
, 24, 4);
3215 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
3216 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
3217 LLVMConstInt(ctx
->i32
, 64, false), ""), "");
3218 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
3219 LLVMConstInt(ctx
->i32
, itemsize_dw
, 0), "");
3222 for (i
= 0; i
< info
->num_outputs
; i
++) {
3225 if (info
->output_semantic_name
[i
] == TGSI_SEMANTIC_VIEWPORT_INDEX
||
3226 info
->output_semantic_name
[i
] == TGSI_SEMANTIC_LAYER
)
3229 param
= si_shader_io_get_unique_index(info
->output_semantic_name
[i
],
3230 info
->output_semantic_index
[i
]);
3232 for (chan
= 0; chan
< 4; chan
++) {
3233 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, addrs
[4 * i
+ chan
], "");
3234 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
3236 /* GFX9 has the ESGS ring in LDS. */
3237 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
3238 lds_store(ctx
, param
* 4 + chan
, lds_base
, out_val
);
3242 ac_build_buffer_store_dword(&ctx
->ac
,
3244 out_val
, 1, NULL
, soffset
,
3245 (4 * param
+ chan
) * 4,
3250 if (ctx
->screen
->info
.chip_class
>= GFX9
)
3251 si_set_es_return_value_for_gs(ctx
);
3254 static LLVMValueRef
si_get_gs_wave_id(struct si_shader_context
*ctx
)
3256 if (ctx
->screen
->info
.chip_class
>= GFX9
)
3257 return unpack_param(ctx
, ctx
->param_merged_wave_info
, 16, 8);
3259 return LLVMGetParam(ctx
->main_fn
, ctx
->param_gs_wave_id
);
3262 static void emit_gs_epilogue(struct si_shader_context
*ctx
)
3264 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
,
3265 si_get_gs_wave_id(ctx
));
3267 if (ctx
->screen
->info
.chip_class
>= GFX9
)
3268 lp_build_endif(&ctx
->merged_wrap_if_state
);
3271 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi
*abi
,
3272 unsigned max_outputs
,
3273 LLVMValueRef
*addrs
)
3275 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3276 struct tgsi_shader_info UNUSED
*info
= &ctx
->shader
->selector
->info
;
3278 assert(info
->num_outputs
<= max_outputs
);
3280 emit_gs_epilogue(ctx
);
3283 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context
*bld_base
)
3285 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3286 emit_gs_epilogue(ctx
);
3289 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi
*abi
,
3290 unsigned max_outputs
,
3291 LLVMValueRef
*addrs
)
3293 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3294 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
3295 struct si_shader_output_values
*outputs
= NULL
;
3298 assert(!ctx
->shader
->is_gs_copy_shader
);
3299 assert(info
->num_outputs
<= max_outputs
);
3301 outputs
= MALLOC((info
->num_outputs
+ 1) * sizeof(outputs
[0]));
3303 /* Vertex color clamping.
3305 * This uses a state constant loaded in a user data SGPR and
3306 * an IF statement is added that clamps all colors if the constant
3309 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
3310 struct lp_build_if_state if_ctx
;
3311 LLVMValueRef cond
= NULL
;
3312 LLVMValueRef addr
, val
;
3314 for (i
= 0; i
< info
->num_outputs
; i
++) {
3315 if (info
->output_semantic_name
[i
] != TGSI_SEMANTIC_COLOR
&&
3316 info
->output_semantic_name
[i
] != TGSI_SEMANTIC_BCOLOR
)
3319 /* We've found a color. */
3321 /* The state is in the first bit of the user SGPR. */
3322 cond
= LLVMGetParam(ctx
->main_fn
,
3323 ctx
->param_vs_state_bits
);
3324 cond
= LLVMBuildTrunc(ctx
->ac
.builder
, cond
,
3326 lp_build_if(&if_ctx
, &ctx
->gallivm
, cond
);
3329 for (j
= 0; j
< 4; j
++) {
3330 addr
= addrs
[4 * i
+ j
];
3331 val
= LLVMBuildLoad(ctx
->ac
.builder
, addr
, "");
3332 val
= ac_build_clamp(&ctx
->ac
, val
);
3333 LLVMBuildStore(ctx
->ac
.builder
, val
, addr
);
3338 lp_build_endif(&if_ctx
);
3341 for (i
= 0; i
< info
->num_outputs
; i
++) {
3342 outputs
[i
].semantic_name
= info
->output_semantic_name
[i
];
3343 outputs
[i
].semantic_index
= info
->output_semantic_index
[i
];
3345 for (j
= 0; j
< 4; j
++) {
3346 outputs
[i
].values
[j
] =
3347 LLVMBuildLoad(ctx
->ac
.builder
,
3350 outputs
[i
].vertex_stream
[j
] =
3351 (info
->output_streams
[i
] >> (2 * j
)) & 3;
3355 if (ctx
->shader
->selector
->so
.num_outputs
)
3356 si_llvm_emit_streamout(ctx
, outputs
, i
, 0);
3358 /* Export PrimitiveID. */
3359 if (ctx
->shader
->key
.mono
.u
.vs_export_prim_id
) {
3360 outputs
[i
].semantic_name
= TGSI_SEMANTIC_PRIMID
;
3361 outputs
[i
].semantic_index
= 0;
3362 outputs
[i
].values
[0] = ac_to_float(&ctx
->ac
, get_primitive_id(ctx
, 0));
3363 for (j
= 1; j
< 4; j
++)
3364 outputs
[i
].values
[j
] = LLVMConstReal(ctx
->f32
, 0);
3366 memset(outputs
[i
].vertex_stream
, 0,
3367 sizeof(outputs
[i
].vertex_stream
));
3371 si_llvm_export_vs(ctx
, outputs
, i
);
3375 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context
*bld_base
)
3377 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3379 ctx
->abi
.emit_outputs(&ctx
->abi
, RADEON_LLVM_MAX_OUTPUTS
,
3380 &ctx
->outputs
[0][0]);
3383 struct si_ps_exports
{
3385 struct ac_export_args args
[10];
3388 unsigned si_get_spi_shader_z_format(bool writes_z
, bool writes_stencil
,
3389 bool writes_samplemask
)
3392 /* Z needs 32 bits. */
3393 if (writes_samplemask
)
3394 return V_028710_SPI_SHADER_32_ABGR
;
3395 else if (writes_stencil
)
3396 return V_028710_SPI_SHADER_32_GR
;
3398 return V_028710_SPI_SHADER_32_R
;
3399 } else if (writes_stencil
|| writes_samplemask
) {
3400 /* Both stencil and sample mask need only 16 bits. */
3401 return V_028710_SPI_SHADER_UINT16_ABGR
;
3403 return V_028710_SPI_SHADER_ZERO
;
3407 static void si_export_mrt_z(struct lp_build_tgsi_context
*bld_base
,
3408 LLVMValueRef depth
, LLVMValueRef stencil
,
3409 LLVMValueRef samplemask
, struct si_ps_exports
*exp
)
3411 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3412 struct lp_build_context
*base
= &bld_base
->base
;
3413 struct ac_export_args args
;
3415 unsigned format
= si_get_spi_shader_z_format(depth
!= NULL
,
3417 samplemask
!= NULL
);
3419 assert(depth
|| stencil
|| samplemask
);
3421 args
.valid_mask
= 1; /* whether the EXEC mask is valid */
3422 args
.done
= 1; /* DONE bit */
3424 /* Specify the target we are exporting */
3425 args
.target
= V_008DFC_SQ_EXP_MRTZ
;
3427 args
.compr
= 0; /* COMP flag */
3428 args
.out
[0] = base
->undef
; /* R, depth */
3429 args
.out
[1] = base
->undef
; /* G, stencil test value[0:7], stencil op value[8:15] */
3430 args
.out
[2] = base
->undef
; /* B, sample mask */
3431 args
.out
[3] = base
->undef
; /* A, alpha to mask */
3433 if (format
== V_028710_SPI_SHADER_UINT16_ABGR
) {
3435 args
.compr
= 1; /* COMPR flag */
3438 /* Stencil should be in X[23:16]. */
3439 stencil
= ac_to_integer(&ctx
->ac
, stencil
);
3440 stencil
= LLVMBuildShl(ctx
->ac
.builder
, stencil
,
3441 LLVMConstInt(ctx
->i32
, 16, 0), "");
3442 args
.out
[0] = ac_to_float(&ctx
->ac
, stencil
);
3446 /* SampleMask should be in Y[15:0]. */
3447 args
.out
[1] = samplemask
;
3452 args
.out
[0] = depth
;
3456 args
.out
[1] = stencil
;
3460 args
.out
[2] = samplemask
;
3465 /* SI (except OLAND and HAINAN) has a bug that it only looks
3466 * at the X writemask component. */
3467 if (ctx
->screen
->info
.chip_class
== SI
&&
3468 ctx
->screen
->info
.family
!= CHIP_OLAND
&&
3469 ctx
->screen
->info
.family
!= CHIP_HAINAN
)
3472 /* Specify which components to enable */
3473 args
.enabled_channels
= mask
;
3475 memcpy(&exp
->args
[exp
->num
++], &args
, sizeof(args
));
3478 static void si_export_mrt_color(struct lp_build_tgsi_context
*bld_base
,
3479 LLVMValueRef
*color
, unsigned index
,
3480 unsigned samplemask_param
,
3481 bool is_last
, struct si_ps_exports
*exp
)
3483 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3487 if (ctx
->shader
->key
.part
.ps
.epilog
.clamp_color
)
3488 for (i
= 0; i
< 4; i
++)
3489 color
[i
] = ac_build_clamp(&ctx
->ac
, color
[i
]);
3492 if (ctx
->shader
->key
.part
.ps
.epilog
.alpha_to_one
)
3493 color
[3] = ctx
->ac
.f32_1
;
3497 ctx
->shader
->key
.part
.ps
.epilog
.alpha_func
!= PIPE_FUNC_ALWAYS
)
3498 si_alpha_test(bld_base
, color
[3]);
3500 /* Line & polygon smoothing */
3501 if (ctx
->shader
->key
.part
.ps
.epilog
.poly_line_smoothing
)
3502 color
[3] = si_scale_alpha_by_sample_mask(bld_base
, color
[3],
3505 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3506 if (ctx
->shader
->key
.part
.ps
.epilog
.last_cbuf
> 0) {
3507 struct ac_export_args args
[8];
3510 /* Get the export arguments, also find out what the last one is. */
3511 for (c
= 0; c
<= ctx
->shader
->key
.part
.ps
.epilog
.last_cbuf
; c
++) {
3512 si_llvm_init_export_args(ctx
, color
,
3513 V_008DFC_SQ_EXP_MRT
+ c
, &args
[c
]);
3514 if (args
[c
].enabled_channels
)
3518 /* Emit all exports. */
3519 for (c
= 0; c
<= ctx
->shader
->key
.part
.ps
.epilog
.last_cbuf
; c
++) {
3520 if (is_last
&& last
== c
) {
3521 args
[c
].valid_mask
= 1; /* whether the EXEC mask is valid */
3522 args
[c
].done
= 1; /* DONE bit */
3523 } else if (!args
[c
].enabled_channels
)
3524 continue; /* unnecessary NULL export */
3526 memcpy(&exp
->args
[exp
->num
++], &args
[c
], sizeof(args
[c
]));
3529 struct ac_export_args args
;
3532 si_llvm_init_export_args(ctx
, color
, V_008DFC_SQ_EXP_MRT
+ index
,
3535 args
.valid_mask
= 1; /* whether the EXEC mask is valid */
3536 args
.done
= 1; /* DONE bit */
3537 } else if (!args
.enabled_channels
)
3538 return; /* unnecessary NULL export */
3540 memcpy(&exp
->args
[exp
->num
++], &args
, sizeof(args
));
3544 static void si_emit_ps_exports(struct si_shader_context
*ctx
,
3545 struct si_ps_exports
*exp
)
3547 for (unsigned i
= 0; i
< exp
->num
; i
++)
3548 ac_build_export(&ctx
->ac
, &exp
->args
[i
]);
3551 static void si_export_null(struct lp_build_tgsi_context
*bld_base
)
3553 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3554 struct lp_build_context
*base
= &bld_base
->base
;
3555 struct ac_export_args args
;
3557 args
.enabled_channels
= 0x0; /* enabled channels */
3558 args
.valid_mask
= 1; /* whether the EXEC mask is valid */
3559 args
.done
= 1; /* DONE bit */
3560 args
.target
= V_008DFC_SQ_EXP_NULL
;
3561 args
.compr
= 0; /* COMPR flag (0 = 32-bit export) */
3562 args
.out
[0] = base
->undef
; /* R */
3563 args
.out
[1] = base
->undef
; /* G */
3564 args
.out
[2] = base
->undef
; /* B */
3565 args
.out
[3] = base
->undef
; /* A */
3567 ac_build_export(&ctx
->ac
, &args
);
3571 * Return PS outputs in this order:
3573 * v[0:3] = color0.xyzw
3574 * v[4:7] = color1.xyzw
3579 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3581 * The alpha-ref SGPR is returned via its original location.
3583 static void si_llvm_return_fs_outputs(struct ac_shader_abi
*abi
,
3584 unsigned max_outputs
,
3585 LLVMValueRef
*addrs
)
3587 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3588 struct si_shader
*shader
= ctx
->shader
;
3589 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
3590 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3591 unsigned i
, j
, first_vgpr
, vgpr
;
3593 LLVMValueRef color
[8][4] = {};
3594 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3597 if (ctx
->postponed_kill
)
3598 ac_build_kill_if_false(&ctx
->ac
, LLVMBuildLoad(builder
, ctx
->postponed_kill
, ""));
3600 /* Read the output values. */
3601 for (i
= 0; i
< info
->num_outputs
; i
++) {
3602 unsigned semantic_name
= info
->output_semantic_name
[i
];
3603 unsigned semantic_index
= info
->output_semantic_index
[i
];
3605 switch (semantic_name
) {
3606 case TGSI_SEMANTIC_COLOR
:
3607 assert(semantic_index
< 8);
3608 for (j
= 0; j
< 4; j
++) {
3609 LLVMValueRef ptr
= addrs
[4 * i
+ j
];
3610 LLVMValueRef result
= LLVMBuildLoad(builder
, ptr
, "");
3611 color
[semantic_index
][j
] = result
;
3614 case TGSI_SEMANTIC_POSITION
:
3615 depth
= LLVMBuildLoad(builder
,
3616 addrs
[4 * i
+ 2], "");
3618 case TGSI_SEMANTIC_STENCIL
:
3619 stencil
= LLVMBuildLoad(builder
,
3620 addrs
[4 * i
+ 1], "");
3622 case TGSI_SEMANTIC_SAMPLEMASK
:
3623 samplemask
= LLVMBuildLoad(builder
,
3624 addrs
[4 * i
+ 0], "");
3627 fprintf(stderr
, "Warning: SI unhandled fs output type:%d\n",
3632 /* Fill the return structure. */
3633 ret
= ctx
->return_value
;
3636 ret
= LLVMBuildInsertValue(builder
, ret
,
3637 ac_to_integer(&ctx
->ac
,
3638 LLVMGetParam(ctx
->main_fn
,
3639 SI_PARAM_ALPHA_REF
)),
3640 SI_SGPR_ALPHA_REF
, "");
3643 first_vgpr
= vgpr
= SI_SGPR_ALPHA_REF
+ 1;
3644 for (i
= 0; i
< ARRAY_SIZE(color
); i
++) {
3648 for (j
= 0; j
< 4; j
++)
3649 ret
= LLVMBuildInsertValue(builder
, ret
, color
[i
][j
], vgpr
++, "");
3652 ret
= LLVMBuildInsertValue(builder
, ret
, depth
, vgpr
++, "");
3654 ret
= LLVMBuildInsertValue(builder
, ret
, stencil
, vgpr
++, "");
3656 ret
= LLVMBuildInsertValue(builder
, ret
, samplemask
, vgpr
++, "");
3658 /* Add the input sample mask for smoothing at the end. */
3659 if (vgpr
< first_vgpr
+ PS_EPILOG_SAMPLEMASK_MIN_LOC
)
3660 vgpr
= first_vgpr
+ PS_EPILOG_SAMPLEMASK_MIN_LOC
;
3661 ret
= LLVMBuildInsertValue(builder
, ret
,
3662 LLVMGetParam(ctx
->main_fn
,
3663 SI_PARAM_SAMPLE_COVERAGE
), vgpr
++, "");
3665 ctx
->return_value
= ret
;
3668 void si_emit_waitcnt(struct si_shader_context
*ctx
, unsigned simm16
)
3670 LLVMValueRef args
[1] = {
3671 LLVMConstInt(ctx
->i32
, simm16
, 0)
3673 lp_build_intrinsic(ctx
->ac
.builder
, "llvm.amdgcn.s.waitcnt",
3674 ctx
->voidt
, args
, 1, 0);
3677 static void membar_emit(
3678 const struct lp_build_tgsi_action
*action
,
3679 struct lp_build_tgsi_context
*bld_base
,
3680 struct lp_build_emit_data
*emit_data
)
3682 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3683 LLVMValueRef src0
= lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, 0);
3684 unsigned flags
= LLVMConstIntGetZExtValue(src0
);
3685 unsigned waitcnt
= NOOP_WAITCNT
;
3687 if (flags
& TGSI_MEMBAR_THREAD_GROUP
)
3688 waitcnt
&= VM_CNT
& LGKM_CNT
;
3690 if (flags
& (TGSI_MEMBAR_ATOMIC_BUFFER
|
3691 TGSI_MEMBAR_SHADER_BUFFER
|
3692 TGSI_MEMBAR_SHADER_IMAGE
))
3695 if (flags
& TGSI_MEMBAR_SHARED
)
3696 waitcnt
&= LGKM_CNT
;
3698 if (waitcnt
!= NOOP_WAITCNT
)
3699 si_emit_waitcnt(ctx
, waitcnt
);
3702 static void clock_emit(
3703 const struct lp_build_tgsi_action
*action
,
3704 struct lp_build_tgsi_context
*bld_base
,
3705 struct lp_build_emit_data
*emit_data
)
3707 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3710 tmp
= lp_build_intrinsic(ctx
->ac
.builder
, "llvm.readcyclecounter",
3711 ctx
->i64
, NULL
, 0, 0);
3712 tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, tmp
, ctx
->v2i32
, "");
3714 emit_data
->output
[0] =
3715 LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
, ctx
->i32_0
, "");
3716 emit_data
->output
[1] =
3717 LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
, ctx
->i32_1
, "");
3720 LLVMTypeRef
si_const_array(LLVMTypeRef elem_type
, int num_elements
)
3722 return LLVMPointerType(LLVMArrayType(elem_type
, num_elements
),
3726 static void si_llvm_emit_ddxy(
3727 const struct lp_build_tgsi_action
*action
,
3728 struct lp_build_tgsi_context
*bld_base
,
3729 struct lp_build_emit_data
*emit_data
)
3731 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3732 unsigned opcode
= emit_data
->info
->opcode
;
3737 if (opcode
== TGSI_OPCODE_DDX_FINE
)
3738 mask
= AC_TID_MASK_LEFT
;
3739 else if (opcode
== TGSI_OPCODE_DDY_FINE
)
3740 mask
= AC_TID_MASK_TOP
;
3742 mask
= AC_TID_MASK_TOP_LEFT
;
3744 /* for DDX we want to next X pixel, DDY next Y pixel. */
3745 idx
= (opcode
== TGSI_OPCODE_DDX
|| opcode
== TGSI_OPCODE_DDX_FINE
) ? 1 : 2;
3747 val
= ac_to_integer(&ctx
->ac
, emit_data
->args
[0]);
3748 val
= ac_build_ddxy(&ctx
->ac
, mask
, idx
, val
);
3749 emit_data
->output
[emit_data
->chan
] = val
;
3753 * this takes an I,J coordinate pair,
3754 * and works out the X and Y derivatives.
3755 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3757 static LLVMValueRef
si_llvm_emit_ddxy_interp(
3758 struct lp_build_tgsi_context
*bld_base
,
3759 LLVMValueRef interp_ij
)
3761 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3762 LLVMValueRef result
[4], a
;
3765 for (i
= 0; i
< 2; i
++) {
3766 a
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_ij
,
3767 LLVMConstInt(ctx
->i32
, i
, 0), "");
3768 result
[i
] = lp_build_emit_llvm_unary(bld_base
, TGSI_OPCODE_DDX
, a
);
3769 result
[2+i
] = lp_build_emit_llvm_unary(bld_base
, TGSI_OPCODE_DDY
, a
);
3772 return lp_build_gather_values(&ctx
->gallivm
, result
, 4);
3775 static void interp_fetch_args(
3776 struct lp_build_tgsi_context
*bld_base
,
3777 struct lp_build_emit_data
*emit_data
)
3779 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3780 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3782 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
3783 /* offset is in second src, first two channels */
3784 emit_data
->args
[0] = lp_build_emit_fetch(bld_base
,
3787 emit_data
->args
[1] = lp_build_emit_fetch(bld_base
,
3790 emit_data
->arg_count
= 2;
3791 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
3792 LLVMValueRef sample_position
;
3793 LLVMValueRef sample_id
;
3794 LLVMValueRef halfval
= LLVMConstReal(ctx
->f32
, 0.5f
);
3796 /* fetch sample ID, then fetch its sample position,
3797 * and place into first two channels.
3799 sample_id
= lp_build_emit_fetch(bld_base
,
3800 emit_data
->inst
, 1, TGSI_CHAN_X
);
3801 sample_id
= ac_to_integer(&ctx
->ac
, sample_id
);
3803 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
3804 * Language 4.50 spec says about interpolateAtSample:
3806 * "Returns the value of the input interpolant variable at
3807 * the location of sample number sample. If multisample
3808 * buffers are not available, the input variable will be
3809 * evaluated at the center of the pixel. If sample sample
3810 * does not exist, the position used to interpolate the
3811 * input variable is undefined."
3813 * This means that sample_id values outside of the valid are
3814 * in fact valid input, and the usual mechanism for loading the
3815 * sample position doesn't work.
3817 if (ctx
->shader
->key
.mono
.u
.ps
.interpolate_at_sample_force_center
) {
3818 LLVMValueRef center
[4] = {
3819 LLVMConstReal(ctx
->f32
, 0.5),
3820 LLVMConstReal(ctx
->f32
, 0.5),
3825 sample_position
= lp_build_gather_values(&ctx
->gallivm
, center
, 4);
3827 sample_position
= load_sample_position(ctx
, sample_id
);
3830 emit_data
->args
[0] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3834 emit_data
->args
[0] = LLVMBuildFSub(ctx
->ac
.builder
, emit_data
->args
[0], halfval
, "");
3835 emit_data
->args
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3838 emit_data
->args
[1] = LLVMBuildFSub(ctx
->ac
.builder
, emit_data
->args
[1], halfval
, "");
3839 emit_data
->arg_count
= 2;
3843 static void build_interp_intrinsic(const struct lp_build_tgsi_action
*action
,
3844 struct lp_build_tgsi_context
*bld_base
,
3845 struct lp_build_emit_data
*emit_data
)
3847 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3848 struct si_shader
*shader
= ctx
->shader
;
3849 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
3850 LLVMValueRef interp_param
;
3851 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3852 const struct tgsi_full_src_register
*input
= &inst
->Src
[0];
3853 int input_base
, input_array_size
;
3856 LLVMValueRef prim_mask
= LLVMGetParam(ctx
->main_fn
, SI_PARAM_PRIM_MASK
);
3857 LLVMValueRef array_idx
;
3858 int interp_param_idx
;
3862 assert(input
->Register
.File
== TGSI_FILE_INPUT
);
3864 if (input
->Register
.Indirect
) {
3865 unsigned array_id
= input
->Indirect
.ArrayID
;
3868 input_base
= info
->input_array_first
[array_id
];
3869 input_array_size
= info
->input_array_last
[array_id
] - input_base
+ 1;
3871 input_base
= inst
->Src
[0].Register
.Index
;
3872 input_array_size
= info
->num_inputs
- input_base
;
3875 array_idx
= si_get_indirect_index(ctx
, &input
->Indirect
,
3876 1, input
->Register
.Index
- input_base
);
3878 input_base
= inst
->Src
[0].Register
.Index
;
3879 input_array_size
= 1;
3880 array_idx
= ctx
->i32_0
;
3883 interp
= shader
->selector
->info
.input_interpolate
[input_base
];
3885 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
3886 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
)
3887 location
= TGSI_INTERPOLATE_LOC_CENTER
;
3889 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
3891 interp_param_idx
= lookup_interp_param_index(interp
, location
);
3892 if (interp_param_idx
== -1)
3894 else if (interp_param_idx
)
3895 interp_param
= LLVMGetParam(ctx
->main_fn
, interp_param_idx
);
3897 interp_param
= NULL
;
3899 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
3900 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
3901 LLVMValueRef ij_out
[2];
3902 LLVMValueRef ddxy_out
= si_llvm_emit_ddxy_interp(bld_base
, interp_param
);
3905 * take the I then J parameters, and the DDX/Y for it, and
3906 * calculate the IJ inputs for the interpolator.
3907 * temp1 = ddx * offset/sample.x + I;
3908 * interp_param.I = ddy * offset/sample.y + temp1;
3909 * temp1 = ddx * offset/sample.x + J;
3910 * interp_param.J = ddy * offset/sample.y + temp1;
3912 for (i
= 0; i
< 2; i
++) {
3913 LLVMValueRef ix_ll
= LLVMConstInt(ctx
->i32
, i
, 0);
3914 LLVMValueRef iy_ll
= LLVMConstInt(ctx
->i32
, i
+ 2, 0);
3915 LLVMValueRef ddx_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
3916 ddxy_out
, ix_ll
, "");
3917 LLVMValueRef ddy_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
3918 ddxy_out
, iy_ll
, "");
3919 LLVMValueRef interp_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
3920 interp_param
, ix_ll
, "");
3921 LLVMValueRef temp1
, temp2
;
3923 interp_el
= ac_to_float(&ctx
->ac
, interp_el
);
3925 temp1
= LLVMBuildFMul(ctx
->ac
.builder
, ddx_el
, emit_data
->args
[0], "");
3927 temp1
= LLVMBuildFAdd(ctx
->ac
.builder
, temp1
, interp_el
, "");
3929 temp2
= LLVMBuildFMul(ctx
->ac
.builder
, ddy_el
, emit_data
->args
[1], "");
3931 ij_out
[i
] = LLVMBuildFAdd(ctx
->ac
.builder
, temp2
, temp1
, "");
3933 interp_param
= lp_build_gather_values(&ctx
->gallivm
, ij_out
, 2);
3937 interp_param
= ac_to_float(&ctx
->ac
, interp_param
);
3939 for (chan
= 0; chan
< 4; chan
++) {
3940 LLVMValueRef gather
= LLVMGetUndef(LLVMVectorType(ctx
->f32
, input_array_size
));
3941 unsigned schan
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[0], chan
);
3943 for (unsigned idx
= 0; idx
< input_array_size
; ++idx
) {
3944 LLVMValueRef v
, i
= NULL
, j
= NULL
;
3947 i
= LLVMBuildExtractElement(
3948 ctx
->ac
.builder
, interp_param
, ctx
->i32_0
, "");
3949 j
= LLVMBuildExtractElement(
3950 ctx
->ac
.builder
, interp_param
, ctx
->i32_1
, "");
3952 v
= si_build_fs_interp(ctx
, input_base
+ idx
, schan
,
3955 gather
= LLVMBuildInsertElement(ctx
->ac
.builder
,
3956 gather
, v
, LLVMConstInt(ctx
->i32
, idx
, false), "");
3959 emit_data
->output
[chan
] = LLVMBuildExtractElement(
3960 ctx
->ac
.builder
, gather
, array_idx
, "");
3964 static void vote_all_emit(
3965 const struct lp_build_tgsi_action
*action
,
3966 struct lp_build_tgsi_context
*bld_base
,
3967 struct lp_build_emit_data
*emit_data
)
3969 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3971 LLVMValueRef tmp
= ac_build_vote_all(&ctx
->ac
, emit_data
->args
[0]);
3972 emit_data
->output
[emit_data
->chan
] =
3973 LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->i32
, "");
3976 static void vote_any_emit(
3977 const struct lp_build_tgsi_action
*action
,
3978 struct lp_build_tgsi_context
*bld_base
,
3979 struct lp_build_emit_data
*emit_data
)
3981 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3983 LLVMValueRef tmp
= ac_build_vote_any(&ctx
->ac
, emit_data
->args
[0]);
3984 emit_data
->output
[emit_data
->chan
] =
3985 LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->i32
, "");
3988 static void vote_eq_emit(
3989 const struct lp_build_tgsi_action
*action
,
3990 struct lp_build_tgsi_context
*bld_base
,
3991 struct lp_build_emit_data
*emit_data
)
3993 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3995 LLVMValueRef tmp
= ac_build_vote_eq(&ctx
->ac
, emit_data
->args
[0]);
3996 emit_data
->output
[emit_data
->chan
] =
3997 LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->i32
, "");
4000 static void ballot_emit(
4001 const struct lp_build_tgsi_action
*action
,
4002 struct lp_build_tgsi_context
*bld_base
,
4003 struct lp_build_emit_data
*emit_data
)
4005 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4006 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4009 tmp
= lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_X
);
4010 tmp
= ac_build_ballot(&ctx
->ac
, tmp
);
4011 tmp
= LLVMBuildBitCast(builder
, tmp
, ctx
->v2i32
, "");
4013 emit_data
->output
[0] = LLVMBuildExtractElement(builder
, tmp
, ctx
->i32_0
, "");
4014 emit_data
->output
[1] = LLVMBuildExtractElement(builder
, tmp
, ctx
->i32_1
, "");
4017 static void read_invoc_fetch_args(
4018 struct lp_build_tgsi_context
*bld_base
,
4019 struct lp_build_emit_data
*emit_data
)
4021 emit_data
->args
[0] = lp_build_emit_fetch(bld_base
, emit_data
->inst
,
4022 0, emit_data
->src_chan
);
4024 /* Always read the source invocation (= lane) from the X channel. */
4025 emit_data
->args
[1] = lp_build_emit_fetch(bld_base
, emit_data
->inst
,
4027 emit_data
->arg_count
= 2;
4030 static void read_lane_emit(
4031 const struct lp_build_tgsi_action
*action
,
4032 struct lp_build_tgsi_context
*bld_base
,
4033 struct lp_build_emit_data
*emit_data
)
4035 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4037 /* We currently have no other way to prevent LLVM from lifting the icmp
4038 * calls to a dominating basic block.
4040 ac_build_optimization_barrier(&ctx
->ac
, &emit_data
->args
[0]);
4042 for (unsigned i
= 0; i
< emit_data
->arg_count
; ++i
)
4043 emit_data
->args
[i
] = ac_to_integer(&ctx
->ac
, emit_data
->args
[i
]);
4045 emit_data
->output
[emit_data
->chan
] =
4046 ac_build_intrinsic(&ctx
->ac
, action
->intr_name
,
4047 ctx
->i32
, emit_data
->args
, emit_data
->arg_count
,
4048 AC_FUNC_ATTR_READNONE
|
4049 AC_FUNC_ATTR_CONVERGENT
);
4052 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context
*bld_base
,
4053 struct lp_build_emit_data
*emit_data
)
4055 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4056 struct tgsi_src_register src0
= emit_data
->inst
->Src
[0].Register
;
4060 assert(src0
.File
== TGSI_FILE_IMMEDIATE
);
4062 imm
= ctx
->imms
[src0
.Index
* TGSI_NUM_CHANNELS
+ src0
.SwizzleX
];
4063 stream
= LLVMConstIntGetZExtValue(imm
) & 0x3;
4067 /* Emit one vertex from the geometry shader */
4068 static void si_llvm_emit_vertex(struct ac_shader_abi
*abi
,
4070 LLVMValueRef
*addrs
)
4072 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
4073 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
4074 struct lp_build_context
*uint
= &ctx
->bld_base
.uint_bld
;
4075 struct si_shader
*shader
= ctx
->shader
;
4076 struct lp_build_if_state if_state
;
4077 LLVMValueRef soffset
= LLVMGetParam(ctx
->main_fn
,
4078 ctx
->param_gs2vs_offset
);
4079 LLVMValueRef gs_next_vertex
;
4080 LLVMValueRef can_emit
;
4081 unsigned chan
, offset
;
4084 /* Write vertex attribute values to GSVS ring */
4085 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
4086 ctx
->gs_next_vertex
[stream
],
4089 /* If this thread has already emitted the declared maximum number of
4090 * vertices, skip the write: excessive vertex emissions are not
4091 * supposed to have any effect.
4093 * If the shader has no writes to memory, kill it instead. This skips
4094 * further memory loads and may allow LLVM to skip to the end
4097 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
4098 LLVMConstInt(ctx
->i32
,
4099 shader
->selector
->gs_max_out_vertices
, 0), "");
4101 bool use_kill
= !info
->writes_memory
;
4103 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
4105 lp_build_if(&if_state
, &ctx
->gallivm
, can_emit
);
4109 for (i
= 0; i
< info
->num_outputs
; i
++) {
4110 for (chan
= 0; chan
< 4; chan
++) {
4111 if (!(info
->output_usagemask
[i
] & (1 << chan
)) ||
4112 ((info
->output_streams
[i
] >> (2 * chan
)) & 3) != stream
)
4115 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, addrs
[4 * i
+ chan
], "");
4116 LLVMValueRef voffset
=
4117 LLVMConstInt(ctx
->i32
, offset
*
4118 shader
->selector
->gs_max_out_vertices
, 0);
4121 voffset
= lp_build_add(uint
, voffset
, gs_next_vertex
);
4122 voffset
= lp_build_mul_imm(uint
, voffset
, 4);
4124 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
4126 ac_build_buffer_store_dword(&ctx
->ac
,
4127 ctx
->gsvs_ring
[stream
],
4129 voffset
, soffset
, 0,
4134 gs_next_vertex
= lp_build_add(uint
, gs_next_vertex
,
4137 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
4139 /* Signal vertex emission */
4140 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
4141 si_get_gs_wave_id(ctx
));
4143 lp_build_endif(&if_state
);
4146 /* Emit one vertex from the geometry shader */
4147 static void si_tgsi_emit_vertex(
4148 const struct lp_build_tgsi_action
*action
,
4149 struct lp_build_tgsi_context
*bld_base
,
4150 struct lp_build_emit_data
*emit_data
)
4152 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4153 unsigned stream
= si_llvm_get_stream(bld_base
, emit_data
);
4155 si_llvm_emit_vertex(&ctx
->abi
, stream
, ctx
->outputs
[0]);
4158 /* Cut one primitive from the geometry shader */
4159 static void si_llvm_emit_primitive(
4160 const struct lp_build_tgsi_action
*action
,
4161 struct lp_build_tgsi_context
*bld_base
,
4162 struct lp_build_emit_data
*emit_data
)
4164 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4167 /* Signal primitive cut */
4168 stream
= si_llvm_get_stream(bld_base
, emit_data
);
4169 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8),
4170 si_get_gs_wave_id(ctx
));
4173 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action
*action
,
4174 struct lp_build_tgsi_context
*bld_base
,
4175 struct lp_build_emit_data
*emit_data
)
4177 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4179 /* SI only (thanks to a hw bug workaround):
4180 * The real barrier instruction isn’t needed, because an entire patch
4181 * always fits into a single wave.
4183 if (ctx
->screen
->info
.chip_class
== SI
&&
4184 ctx
->type
== PIPE_SHADER_TESS_CTRL
) {
4185 si_emit_waitcnt(ctx
, LGKM_CNT
& VM_CNT
);
4189 lp_build_intrinsic(ctx
->ac
.builder
,
4190 "llvm.amdgcn.s.barrier",
4191 ctx
->voidt
, NULL
, 0, LP_FUNC_ATTR_CONVERGENT
);
4194 static const struct lp_build_tgsi_action interp_action
= {
4195 .fetch_args
= interp_fetch_args
,
4196 .emit
= build_interp_intrinsic
,
4199 static void si_create_function(struct si_shader_context
*ctx
,
4201 LLVMTypeRef
*returns
, unsigned num_returns
,
4202 struct si_function_info
*fninfo
,
4203 unsigned max_workgroup_size
)
4207 si_llvm_create_func(ctx
, name
, returns
, num_returns
,
4208 fninfo
->types
, fninfo
->num_params
);
4209 ctx
->return_value
= LLVMGetUndef(ctx
->return_type
);
4211 for (i
= 0; i
< fninfo
->num_sgpr_params
; ++i
) {
4212 LLVMValueRef P
= LLVMGetParam(ctx
->main_fn
, i
);
4214 /* The combination of:
4218 * allows the optimization passes to move loads and reduces
4219 * SGPR spilling significantly.
4221 if (LLVMGetTypeKind(LLVMTypeOf(P
)) == LLVMPointerTypeKind
) {
4222 lp_add_function_attr(ctx
->main_fn
, i
+ 1, LP_FUNC_ATTR_BYVAL
);
4223 lp_add_function_attr(ctx
->main_fn
, i
+ 1, LP_FUNC_ATTR_NOALIAS
);
4224 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
4226 lp_add_function_attr(ctx
->main_fn
, i
+ 1, LP_FUNC_ATTR_INREG
);
4229 for (i
= 0; i
< fninfo
->num_params
; ++i
) {
4230 if (fninfo
->assign
[i
])
4231 *fninfo
->assign
[i
] = LLVMGetParam(ctx
->main_fn
, i
);
4234 if (max_workgroup_size
) {
4235 si_llvm_add_attribute(ctx
->main_fn
, "amdgpu-max-work-group-size",
4236 max_workgroup_size
);
4238 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4239 "no-signed-zeros-fp-math",
4242 if (ctx
->screen
->debug_flags
& DBG(UNSAFE_MATH
)) {
4243 /* These were copied from some LLVM test. */
4244 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4245 "less-precise-fpmad",
4247 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4250 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4253 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4259 static void declare_streamout_params(struct si_shader_context
*ctx
,
4260 struct pipe_stream_output_info
*so
,
4261 struct si_function_info
*fninfo
)
4265 /* Streamout SGPRs. */
4266 if (so
->num_outputs
) {
4267 if (ctx
->type
!= PIPE_SHADER_TESS_EVAL
)
4268 ctx
->param_streamout_config
= add_arg(fninfo
, ARG_SGPR
, ctx
->ac
.i32
);
4270 ctx
->param_streamout_config
= fninfo
->num_params
- 1;
4272 ctx
->param_streamout_write_index
= add_arg(fninfo
, ARG_SGPR
, ctx
->ac
.i32
);
4274 /* A streamout buffer offset is loaded if the stride is non-zero. */
4275 for (i
= 0; i
< 4; i
++) {
4279 ctx
->param_streamout_offset
[i
] = add_arg(fninfo
, ARG_SGPR
, ctx
->ac
.i32
);
4283 static unsigned si_get_max_workgroup_size(const struct si_shader
*shader
)
4285 switch (shader
->selector
->type
) {
4286 case PIPE_SHADER_TESS_CTRL
:
4287 /* Return this so that LLVM doesn't remove s_barrier
4288 * instructions on chips where we use s_barrier. */
4289 return shader
->selector
->screen
->info
.chip_class
>= CIK
? 128 : 64;
4291 case PIPE_SHADER_GEOMETRY
:
4292 return shader
->selector
->screen
->info
.chip_class
>= GFX9
? 128 : 64;
4294 case PIPE_SHADER_COMPUTE
:
4295 break; /* see below */
4301 const unsigned *properties
= shader
->selector
->info
.properties
;
4302 unsigned max_work_group_size
=
4303 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] *
4304 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
] *
4305 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
];
4307 if (!max_work_group_size
) {
4308 /* This is a variable group size compute shader,
4309 * compile it for the maximum possible group size.
4311 max_work_group_size
= SI_MAX_VARIABLE_THREADS_PER_BLOCK
;
4313 return max_work_group_size
;
4316 static void declare_per_stage_desc_pointers(struct si_shader_context
*ctx
,
4317 struct si_function_info
*fninfo
,
4320 LLVMTypeRef const_shader_buf_type
;
4322 if (ctx
->shader
->selector
->info
.const_buffers_declared
== 1 &&
4323 ctx
->shader
->selector
->info
.shader_buffers_declared
== 0)
4324 const_shader_buf_type
= ctx
->f32
;
4326 const_shader_buf_type
= ctx
->v4i32
;
4328 unsigned const_and_shader_buffers
=
4329 add_arg(fninfo
, ARG_SGPR
,
4330 si_const_array(const_shader_buf_type
, 0));
4332 unsigned samplers_and_images
=
4333 add_arg(fninfo
, ARG_SGPR
,
4334 si_const_array(ctx
->v8i32
,
4335 SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2));
4337 if (assign_params
) {
4338 ctx
->param_const_and_shader_buffers
= const_and_shader_buffers
;
4339 ctx
->param_samplers_and_images
= samplers_and_images
;
4343 static void declare_global_desc_pointers(struct si_shader_context
*ctx
,
4344 struct si_function_info
*fninfo
)
4346 ctx
->param_rw_buffers
= add_arg(fninfo
, ARG_SGPR
,
4347 si_const_array(ctx
->v4i32
, SI_NUM_RW_BUFFERS
));
4348 ctx
->param_bindless_samplers_and_images
= add_arg(fninfo
, ARG_SGPR
,
4349 si_const_array(ctx
->v8i32
, 0));
4352 static void declare_vs_specific_input_sgprs(struct si_shader_context
*ctx
,
4353 struct si_function_info
*fninfo
)
4355 ctx
->param_vertex_buffers
= add_arg(fninfo
, ARG_SGPR
,
4356 si_const_array(ctx
->v4i32
, SI_NUM_VERTEX_BUFFERS
));
4357 add_arg_assign(fninfo
, ARG_SGPR
, ctx
->i32
, &ctx
->abi
.base_vertex
);
4358 add_arg_assign(fninfo
, ARG_SGPR
, ctx
->i32
, &ctx
->abi
.start_instance
);
4359 add_arg_assign(fninfo
, ARG_SGPR
, ctx
->i32
, &ctx
->abi
.draw_id
);
4360 ctx
->param_vs_state_bits
= add_arg(fninfo
, ARG_SGPR
, ctx
->i32
);
4363 static void declare_vs_input_vgprs(struct si_shader_context
*ctx
,
4364 struct si_function_info
*fninfo
,
4365 unsigned *num_prolog_vgprs
)
4367 struct si_shader
*shader
= ctx
->shader
;
4369 add_arg_assign(fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.vertex_id
);
4370 if (shader
->key
.as_ls
) {
4371 ctx
->param_rel_auto_id
= add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4372 add_arg_assign(fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.instance_id
);
4374 add_arg_assign(fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.instance_id
);
4375 ctx
->param_vs_prim_id
= add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4377 add_arg(fninfo
, ARG_VGPR
, ctx
->i32
); /* unused */
4379 if (!shader
->is_gs_copy_shader
) {
4380 /* Vertex load indices. */
4381 ctx
->param_vertex_index0
= fninfo
->num_params
;
4382 for (unsigned i
= 0; i
< shader
->selector
->info
.num_inputs
; i
++)
4383 add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4384 *num_prolog_vgprs
+= shader
->selector
->info
.num_inputs
;
4388 static void declare_tes_input_vgprs(struct si_shader_context
*ctx
,
4389 struct si_function_info
*fninfo
)
4391 ctx
->param_tes_u
= add_arg(fninfo
, ARG_VGPR
, ctx
->f32
);
4392 ctx
->param_tes_v
= add_arg(fninfo
, ARG_VGPR
, ctx
->f32
);
4393 ctx
->param_tes_rel_patch_id
= add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4394 ctx
->param_tes_patch_id
= add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4398 /* Convenient merged shader definitions. */
4399 SI_SHADER_MERGED_VERTEX_TESSCTRL
= PIPE_SHADER_TYPES
,
4400 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY
,
4403 static void create_function(struct si_shader_context
*ctx
)
4405 struct si_shader
*shader
= ctx
->shader
;
4406 struct si_function_info fninfo
;
4407 LLVMTypeRef returns
[16+32*4];
4408 unsigned i
, num_return_sgprs
;
4409 unsigned num_returns
= 0;
4410 unsigned num_prolog_vgprs
= 0;
4411 unsigned type
= ctx
->type
;
4412 unsigned vs_blit_property
=
4413 shader
->selector
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
4415 si_init_function_info(&fninfo
);
4417 /* Set MERGED shaders. */
4418 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
4419 if (shader
->key
.as_ls
|| type
== PIPE_SHADER_TESS_CTRL
)
4420 type
= SI_SHADER_MERGED_VERTEX_TESSCTRL
; /* LS or HS */
4421 else if (shader
->key
.as_es
|| type
== PIPE_SHADER_GEOMETRY
)
4422 type
= SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY
;
4425 LLVMTypeRef v3i32
= LLVMVectorType(ctx
->i32
, 3);
4428 case PIPE_SHADER_VERTEX
:
4429 declare_global_desc_pointers(ctx
, &fninfo
);
4431 if (vs_blit_property
) {
4432 ctx
->param_vs_blit_inputs
= fninfo
.num_params
;
4433 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* i16 x1, y1 */
4434 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* i16 x2, y2 */
4435 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* depth */
4437 if (vs_blit_property
== SI_VS_BLIT_SGPRS_POS_COLOR
) {
4438 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* color0 */
4439 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* color1 */
4440 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* color2 */
4441 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* color3 */
4442 } else if (vs_blit_property
== SI_VS_BLIT_SGPRS_POS_TEXCOORD
) {
4443 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.x1 */
4444 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.y1 */
4445 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.x2 */
4446 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.y2 */
4447 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.z */
4448 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.w */
4452 declare_vs_input_vgprs(ctx
, &fninfo
, &num_prolog_vgprs
);
4456 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4457 declare_vs_specific_input_sgprs(ctx
, &fninfo
);
4459 if (shader
->key
.as_es
) {
4460 ctx
->param_es2gs_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4461 } else if (shader
->key
.as_ls
) {
4462 /* no extra parameters */
4464 if (shader
->is_gs_copy_shader
) {
4465 fninfo
.num_params
= ctx
->param_rw_buffers
+ 1;
4466 fninfo
.num_sgpr_params
= fninfo
.num_params
;
4469 /* The locations of the other parameters are assigned dynamically. */
4470 declare_streamout_params(ctx
, &shader
->selector
->so
,
4475 declare_vs_input_vgprs(ctx
, &fninfo
, &num_prolog_vgprs
);
4478 case PIPE_SHADER_TESS_CTRL
: /* SI-CI-VI */
4479 declare_global_desc_pointers(ctx
, &fninfo
);
4480 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4481 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4482 ctx
->param_tcs_out_lds_offsets
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4483 ctx
->param_tcs_out_lds_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4484 ctx
->param_vs_state_bits
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4485 ctx
->param_tcs_offchip_addr_base64k
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4486 ctx
->param_tcs_factor_addr_base64k
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4487 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4488 ctx
->param_tcs_factor_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4491 ctx
->param_tcs_patch_id
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4492 ctx
->param_tcs_rel_ids
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4494 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4495 * placed after the user SGPRs.
4497 for (i
= 0; i
< GFX6_TCS_NUM_USER_SGPR
+ 2; i
++)
4498 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
4499 for (i
= 0; i
< 11; i
++)
4500 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
4503 case SI_SHADER_MERGED_VERTEX_TESSCTRL
:
4504 /* Merged stages have 8 system SGPRs at the beginning. */
4505 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* SPI_SHADER_USER_DATA_ADDR_LO_HS */
4506 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* SPI_SHADER_USER_DATA_ADDR_HI_HS */
4507 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4508 ctx
->param_merged_wave_info
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4509 ctx
->param_tcs_factor_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4510 ctx
->param_merged_scratch_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4511 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4512 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4514 declare_global_desc_pointers(ctx
, &fninfo
);
4515 declare_per_stage_desc_pointers(ctx
, &fninfo
,
4516 ctx
->type
== PIPE_SHADER_VERTEX
);
4517 declare_vs_specific_input_sgprs(ctx
, &fninfo
);
4519 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4520 ctx
->param_tcs_out_lds_offsets
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4521 ctx
->param_tcs_out_lds_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4522 ctx
->param_tcs_offchip_addr_base64k
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4523 ctx
->param_tcs_factor_addr_base64k
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4524 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4526 declare_per_stage_desc_pointers(ctx
, &fninfo
,
4527 ctx
->type
== PIPE_SHADER_TESS_CTRL
);
4529 /* VGPRs (first TCS, then VS) */
4530 ctx
->param_tcs_patch_id
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4531 ctx
->param_tcs_rel_ids
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4533 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
4534 declare_vs_input_vgprs(ctx
, &fninfo
,
4537 /* LS return values are inputs to the TCS main shader part. */
4538 for (i
= 0; i
< 8 + GFX9_TCS_NUM_USER_SGPR
; i
++)
4539 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
4540 for (i
= 0; i
< 2; i
++)
4541 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
4543 /* TCS return values are inputs to the TCS epilog.
4545 * param_tcs_offchip_offset, param_tcs_factor_offset,
4546 * param_tcs_offchip_layout, and param_rw_buffers
4547 * should be passed to the epilog.
4549 for (i
= 0; i
<= 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K
; i
++)
4550 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
4551 for (i
= 0; i
< 11; i
++)
4552 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
4556 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY
:
4557 /* Merged stages have 8 system SGPRs at the beginning. */
4558 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused (SPI_SHADER_USER_DATA_ADDR_LO_GS) */
4559 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused (SPI_SHADER_USER_DATA_ADDR_HI_GS) */
4560 ctx
->param_gs2vs_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4561 ctx
->param_merged_wave_info
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4562 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4563 ctx
->param_merged_scratch_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4564 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4565 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4567 declare_global_desc_pointers(ctx
, &fninfo
);
4568 declare_per_stage_desc_pointers(ctx
, &fninfo
,
4569 (ctx
->type
== PIPE_SHADER_VERTEX
||
4570 ctx
->type
== PIPE_SHADER_TESS_EVAL
));
4571 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
4572 declare_vs_specific_input_sgprs(ctx
, &fninfo
);
4574 /* TESS_EVAL (and also GEOMETRY):
4575 * Declare as many input SGPRs as the VS has. */
4576 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4577 ctx
->param_tcs_offchip_addr_base64k
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4578 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4579 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4580 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4581 ctx
->param_vs_state_bits
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4584 declare_per_stage_desc_pointers(ctx
, &fninfo
,
4585 ctx
->type
== PIPE_SHADER_GEOMETRY
);
4587 /* VGPRs (first GS, then VS/TES) */
4588 ctx
->param_gs_vtx01_offset
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4589 ctx
->param_gs_vtx23_offset
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4590 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.gs_prim_id
);
4591 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.gs_invocation_id
);
4592 ctx
->param_gs_vtx45_offset
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4594 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
4595 declare_vs_input_vgprs(ctx
, &fninfo
,
4597 } else if (ctx
->type
== PIPE_SHADER_TESS_EVAL
) {
4598 declare_tes_input_vgprs(ctx
, &fninfo
);
4601 if (ctx
->type
== PIPE_SHADER_VERTEX
||
4602 ctx
->type
== PIPE_SHADER_TESS_EVAL
) {
4603 /* ES return values are inputs to GS. */
4604 for (i
= 0; i
< 8 + GFX9_GS_NUM_USER_SGPR
; i
++)
4605 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
4606 for (i
= 0; i
< 5; i
++)
4607 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
4611 case PIPE_SHADER_TESS_EVAL
:
4612 declare_global_desc_pointers(ctx
, &fninfo
);
4613 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4614 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4615 ctx
->param_tcs_offchip_addr_base64k
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4617 if (shader
->key
.as_es
) {
4618 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4619 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4620 ctx
->param_es2gs_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4622 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4623 declare_streamout_params(ctx
, &shader
->selector
->so
,
4625 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4629 declare_tes_input_vgprs(ctx
, &fninfo
);
4632 case PIPE_SHADER_GEOMETRY
:
4633 declare_global_desc_pointers(ctx
, &fninfo
);
4634 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4635 ctx
->param_gs2vs_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4636 ctx
->param_gs_wave_id
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4639 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[0]);
4640 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[1]);
4641 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.gs_prim_id
);
4642 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[2]);
4643 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[3]);
4644 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[4]);
4645 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[5]);
4646 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.gs_invocation_id
);
4649 case PIPE_SHADER_FRAGMENT
:
4650 declare_global_desc_pointers(ctx
, &fninfo
);
4651 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4652 add_arg_checked(&fninfo
, ARG_SGPR
, ctx
->f32
, SI_PARAM_ALPHA_REF
);
4653 add_arg_checked(&fninfo
, ARG_SGPR
, ctx
->i32
, SI_PARAM_PRIM_MASK
);
4655 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_PERSP_SAMPLE
);
4656 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_PERSP_CENTER
);
4657 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_PERSP_CENTROID
);
4658 add_arg_checked(&fninfo
, ARG_VGPR
, v3i32
, SI_PARAM_PERSP_PULL_MODEL
);
4659 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_LINEAR_SAMPLE
);
4660 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_LINEAR_CENTER
);
4661 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_LINEAR_CENTROID
);
4662 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->f32
, SI_PARAM_LINE_STIPPLE_TEX
);
4663 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4664 &ctx
->abi
.frag_pos
[0], SI_PARAM_POS_X_FLOAT
);
4665 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4666 &ctx
->abi
.frag_pos
[1], SI_PARAM_POS_Y_FLOAT
);
4667 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4668 &ctx
->abi
.frag_pos
[2], SI_PARAM_POS_Z_FLOAT
);
4669 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4670 &ctx
->abi
.frag_pos
[3], SI_PARAM_POS_W_FLOAT
);
4671 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->i32
,
4672 &ctx
->abi
.front_face
, SI_PARAM_FRONT_FACE
);
4673 shader
->info
.face_vgpr_index
= 20;
4674 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->i32
,
4675 &ctx
->abi
.ancillary
, SI_PARAM_ANCILLARY
);
4676 shader
->info
.ancillary_vgpr_index
= 21;
4677 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4678 &ctx
->abi
.sample_coverage
, SI_PARAM_SAMPLE_COVERAGE
);
4679 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->i32
, SI_PARAM_POS_FIXED_PT
);
4681 /* Color inputs from the prolog. */
4682 if (shader
->selector
->info
.colors_read
) {
4683 unsigned num_color_elements
=
4684 util_bitcount(shader
->selector
->info
.colors_read
);
4686 assert(fninfo
.num_params
+ num_color_elements
<= ARRAY_SIZE(fninfo
.types
));
4687 for (i
= 0; i
< num_color_elements
; i
++)
4688 add_arg(&fninfo
, ARG_VGPR
, ctx
->f32
);
4690 num_prolog_vgprs
+= num_color_elements
;
4693 /* Outputs for the epilog. */
4694 num_return_sgprs
= SI_SGPR_ALPHA_REF
+ 1;
4697 util_bitcount(shader
->selector
->info
.colors_written
) * 4 +
4698 shader
->selector
->info
.writes_z
+
4699 shader
->selector
->info
.writes_stencil
+
4700 shader
->selector
->info
.writes_samplemask
+
4701 1 /* SampleMaskIn */;
4703 num_returns
= MAX2(num_returns
,
4705 PS_EPILOG_SAMPLEMASK_MIN_LOC
+ 1);
4707 for (i
= 0; i
< num_return_sgprs
; i
++)
4708 returns
[i
] = ctx
->i32
;
4709 for (; i
< num_returns
; i
++)
4710 returns
[i
] = ctx
->f32
;
4713 case PIPE_SHADER_COMPUTE
:
4714 declare_global_desc_pointers(ctx
, &fninfo
);
4715 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4716 if (shader
->selector
->info
.uses_grid_size
)
4717 ctx
->param_grid_size
= add_arg(&fninfo
, ARG_SGPR
, v3i32
);
4718 if (shader
->selector
->info
.uses_block_size
)
4719 ctx
->param_block_size
= add_arg(&fninfo
, ARG_SGPR
, v3i32
);
4721 for (i
= 0; i
< 3; i
++) {
4722 ctx
->param_block_id
[i
] = -1;
4723 if (shader
->selector
->info
.uses_block_id
[i
])
4724 ctx
->param_block_id
[i
] = add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4727 ctx
->param_thread_id
= add_arg(&fninfo
, ARG_VGPR
, v3i32
);
4730 assert(0 && "unimplemented shader");
4734 si_create_function(ctx
, "main", returns
, num_returns
, &fninfo
,
4735 si_get_max_workgroup_size(shader
));
4737 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4738 if (ctx
->type
== PIPE_SHADER_FRAGMENT
&&
4739 ctx
->separate_prolog
) {
4740 si_llvm_add_attribute(ctx
->main_fn
,
4741 "InitialPSInputAddr",
4742 S_0286D0_PERSP_SAMPLE_ENA(1) |
4743 S_0286D0_PERSP_CENTER_ENA(1) |
4744 S_0286D0_PERSP_CENTROID_ENA(1) |
4745 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4746 S_0286D0_LINEAR_CENTER_ENA(1) |
4747 S_0286D0_LINEAR_CENTROID_ENA(1) |
4748 S_0286D0_FRONT_FACE_ENA(1) |
4749 S_0286D0_ANCILLARY_ENA(1) |
4750 S_0286D0_POS_FIXED_PT_ENA(1));
4753 shader
->info
.num_input_sgprs
= 0;
4754 shader
->info
.num_input_vgprs
= 0;
4756 for (i
= 0; i
< fninfo
.num_sgpr_params
; ++i
)
4757 shader
->info
.num_input_sgprs
+= ac_get_type_size(fninfo
.types
[i
]) / 4;
4759 for (; i
< fninfo
.num_params
; ++i
)
4760 shader
->info
.num_input_vgprs
+= ac_get_type_size(fninfo
.types
[i
]) / 4;
4762 assert(shader
->info
.num_input_vgprs
>= num_prolog_vgprs
);
4763 shader
->info
.num_input_vgprs
-= num_prolog_vgprs
;
4765 if (shader
->key
.as_ls
||
4766 ctx
->type
== PIPE_SHADER_TESS_CTRL
||
4767 /* GFX9 has the ESGS ring buffer in LDS. */
4768 type
== SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY
)
4769 ac_declare_lds_as_pointer(&ctx
->ac
);
4773 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4776 static void preload_ring_buffers(struct si_shader_context
*ctx
)
4778 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4780 LLVMValueRef buf_ptr
= LLVMGetParam(ctx
->main_fn
,
4781 ctx
->param_rw_buffers
);
4783 if (ctx
->screen
->info
.chip_class
<= VI
&&
4784 (ctx
->shader
->key
.as_es
|| ctx
->type
== PIPE_SHADER_GEOMETRY
)) {
4786 ctx
->type
== PIPE_SHADER_GEOMETRY
? SI_GS_RING_ESGS
4788 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
, ring
, 0);
4791 ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
, offset
);
4794 if (ctx
->shader
->is_gs_copy_shader
) {
4795 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
, SI_RING_GSVS
, 0);
4798 ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
, offset
);
4799 } else if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
4800 const struct si_shader_selector
*sel
= ctx
->shader
->selector
;
4801 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
, SI_RING_GSVS
, 0);
4802 LLVMValueRef base_ring
;
4804 base_ring
= ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
, offset
);
4806 /* The conceptual layout of the GSVS ring is
4807 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4808 * but the real memory layout is swizzled across
4810 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4812 * Override the buffer descriptor accordingly.
4814 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->i64
, 2);
4815 uint64_t stream_offset
= 0;
4817 for (unsigned stream
= 0; stream
< 4; ++stream
) {
4818 unsigned num_components
;
4820 unsigned num_records
;
4821 LLVMValueRef ring
, tmp
;
4823 num_components
= sel
->info
.num_stream_output_components
[stream
];
4824 if (!num_components
)
4827 stride
= 4 * num_components
* sel
->gs_max_out_vertices
;
4829 /* Limit on the stride field for <= CIK. */
4830 assert(stride
< (1 << 14));
4834 ring
= LLVMBuildBitCast(builder
, base_ring
, v2i64
, "");
4835 tmp
= LLVMBuildExtractElement(builder
, ring
, ctx
->i32_0
, "");
4836 tmp
= LLVMBuildAdd(builder
, tmp
,
4837 LLVMConstInt(ctx
->i64
,
4838 stream_offset
, 0), "");
4839 stream_offset
+= stride
* 64;
4841 ring
= LLVMBuildInsertElement(builder
, ring
, tmp
, ctx
->i32_0
, "");
4842 ring
= LLVMBuildBitCast(builder
, ring
, ctx
->v4i32
, "");
4843 tmp
= LLVMBuildExtractElement(builder
, ring
, ctx
->i32_1
, "");
4844 tmp
= LLVMBuildOr(builder
, tmp
,
4845 LLVMConstInt(ctx
->i32
,
4846 S_008F04_STRIDE(stride
) |
4847 S_008F04_SWIZZLE_ENABLE(1), 0), "");
4848 ring
= LLVMBuildInsertElement(builder
, ring
, tmp
, ctx
->i32_1
, "");
4849 ring
= LLVMBuildInsertElement(builder
, ring
,
4850 LLVMConstInt(ctx
->i32
, num_records
, 0),
4851 LLVMConstInt(ctx
->i32
, 2, 0), "");
4852 ring
= LLVMBuildInsertElement(builder
, ring
,
4853 LLVMConstInt(ctx
->i32
,
4854 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4855 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4856 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4857 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
4858 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4859 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
4860 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
4861 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
4862 S_008F0C_ADD_TID_ENABLE(1),
4864 LLVMConstInt(ctx
->i32
, 3, 0), "");
4866 ctx
->gsvs_ring
[stream
] = ring
;
4871 static void si_llvm_emit_polygon_stipple(struct si_shader_context
*ctx
,
4872 LLVMValueRef param_rw_buffers
,
4873 unsigned param_pos_fixed_pt
)
4875 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4876 LLVMValueRef slot
, desc
, offset
, row
, bit
, address
[2];
4878 /* Use the fixed-point gl_FragCoord input.
4879 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
4880 * per coordinate to get the repeating effect.
4882 address
[0] = unpack_param(ctx
, param_pos_fixed_pt
, 0, 5);
4883 address
[1] = unpack_param(ctx
, param_pos_fixed_pt
, 16, 5);
4885 /* Load the buffer descriptor. */
4886 slot
= LLVMConstInt(ctx
->i32
, SI_PS_CONST_POLY_STIPPLE
, 0);
4887 desc
= ac_build_load_to_sgpr(&ctx
->ac
, param_rw_buffers
, slot
);
4889 /* The stipple pattern is 32x32, each row has 32 bits. */
4890 offset
= LLVMBuildMul(builder
, address
[1],
4891 LLVMConstInt(ctx
->i32
, 4, 0), "");
4892 row
= buffer_load_const(ctx
, desc
, offset
);
4893 row
= ac_to_integer(&ctx
->ac
, row
);
4894 bit
= LLVMBuildLShr(builder
, row
, address
[0], "");
4895 bit
= LLVMBuildTrunc(builder
, bit
, ctx
->i1
, "");
4896 ac_build_kill_if_false(&ctx
->ac
, bit
);
4899 void si_shader_binary_read_config(struct ac_shader_binary
*binary
,
4900 struct si_shader_config
*conf
,
4901 unsigned symbol_offset
)
4904 const unsigned char *config
=
4905 ac_shader_binary_config_start(binary
, symbol_offset
);
4906 bool really_needs_scratch
= false;
4908 /* LLVM adds SGPR spills to the scratch size.
4909 * Find out if we really need the scratch buffer.
4911 for (i
= 0; i
< binary
->reloc_count
; i
++) {
4912 const struct ac_shader_reloc
*reloc
= &binary
->relocs
[i
];
4914 if (!strcmp(scratch_rsrc_dword0_symbol
, reloc
->name
) ||
4915 !strcmp(scratch_rsrc_dword1_symbol
, reloc
->name
)) {
4916 really_needs_scratch
= true;
4921 /* XXX: We may be able to emit some of these values directly rather than
4922 * extracting fields to be emitted later.
4925 for (i
= 0; i
< binary
->config_size_per_symbol
; i
+= 8) {
4926 unsigned reg
= util_le32_to_cpu(*(uint32_t*)(config
+ i
));
4927 unsigned value
= util_le32_to_cpu(*(uint32_t*)(config
+ i
+ 4));
4929 case R_00B028_SPI_SHADER_PGM_RSRC1_PS
:
4930 case R_00B128_SPI_SHADER_PGM_RSRC1_VS
:
4931 case R_00B228_SPI_SHADER_PGM_RSRC1_GS
:
4932 case R_00B428_SPI_SHADER_PGM_RSRC1_HS
:
4933 case R_00B848_COMPUTE_PGM_RSRC1
:
4934 conf
->num_sgprs
= MAX2(conf
->num_sgprs
, (G_00B028_SGPRS(value
) + 1) * 8);
4935 conf
->num_vgprs
= MAX2(conf
->num_vgprs
, (G_00B028_VGPRS(value
) + 1) * 4);
4936 conf
->float_mode
= G_00B028_FLOAT_MODE(value
);
4937 conf
->rsrc1
= value
;
4939 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS
:
4940 conf
->lds_size
= MAX2(conf
->lds_size
, G_00B02C_EXTRA_LDS_SIZE(value
));
4942 case R_00B84C_COMPUTE_PGM_RSRC2
:
4943 conf
->lds_size
= MAX2(conf
->lds_size
, G_00B84C_LDS_SIZE(value
));
4944 conf
->rsrc2
= value
;
4946 case R_0286CC_SPI_PS_INPUT_ENA
:
4947 conf
->spi_ps_input_ena
= value
;
4949 case R_0286D0_SPI_PS_INPUT_ADDR
:
4950 conf
->spi_ps_input_addr
= value
;
4952 case R_0286E8_SPI_TMPRING_SIZE
:
4953 case R_00B860_COMPUTE_TMPRING_SIZE
:
4954 /* WAVESIZE is in units of 256 dwords. */
4955 if (really_needs_scratch
)
4956 conf
->scratch_bytes_per_wave
=
4957 G_00B860_WAVESIZE(value
) * 256 * 4;
4959 case 0x4: /* SPILLED_SGPRS */
4960 conf
->spilled_sgprs
= value
;
4962 case 0x8: /* SPILLED_VGPRS */
4963 conf
->spilled_vgprs
= value
;
4967 static bool printed
;
4970 fprintf(stderr
, "Warning: LLVM emitted unknown "
4971 "config register: 0x%x\n", reg
);
4979 if (!conf
->spi_ps_input_addr
)
4980 conf
->spi_ps_input_addr
= conf
->spi_ps_input_ena
;
4983 void si_shader_apply_scratch_relocs(struct si_shader
*shader
,
4984 uint64_t scratch_va
)
4987 uint32_t scratch_rsrc_dword0
= scratch_va
;
4988 uint32_t scratch_rsrc_dword1
=
4989 S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32);
4991 /* Enable scratch coalescing. */
4992 scratch_rsrc_dword1
|= S_008F04_SWIZZLE_ENABLE(1);
4994 for (i
= 0 ; i
< shader
->binary
.reloc_count
; i
++) {
4995 const struct ac_shader_reloc
*reloc
=
4996 &shader
->binary
.relocs
[i
];
4997 if (!strcmp(scratch_rsrc_dword0_symbol
, reloc
->name
)) {
4998 util_memcpy_cpu_to_le32(shader
->binary
.code
+ reloc
->offset
,
4999 &scratch_rsrc_dword0
, 4);
5000 } else if (!strcmp(scratch_rsrc_dword1_symbol
, reloc
->name
)) {
5001 util_memcpy_cpu_to_le32(shader
->binary
.code
+ reloc
->offset
,
5002 &scratch_rsrc_dword1
, 4);
5007 static unsigned si_get_shader_binary_size(const struct si_shader
*shader
)
5009 unsigned size
= shader
->binary
.code_size
;
5012 size
+= shader
->prolog
->binary
.code_size
;
5013 if (shader
->previous_stage
)
5014 size
+= shader
->previous_stage
->binary
.code_size
;
5015 if (shader
->prolog2
)
5016 size
+= shader
->prolog2
->binary
.code_size
;
5018 size
+= shader
->epilog
->binary
.code_size
;
5022 int si_shader_binary_upload(struct si_screen
*sscreen
, struct si_shader
*shader
)
5024 const struct ac_shader_binary
*prolog
=
5025 shader
->prolog
? &shader
->prolog
->binary
: NULL
;
5026 const struct ac_shader_binary
*previous_stage
=
5027 shader
->previous_stage
? &shader
->previous_stage
->binary
: NULL
;
5028 const struct ac_shader_binary
*prolog2
=
5029 shader
->prolog2
? &shader
->prolog2
->binary
: NULL
;
5030 const struct ac_shader_binary
*epilog
=
5031 shader
->epilog
? &shader
->epilog
->binary
: NULL
;
5032 const struct ac_shader_binary
*mainb
= &shader
->binary
;
5033 unsigned bo_size
= si_get_shader_binary_size(shader
) +
5034 (!epilog
? mainb
->rodata_size
: 0);
5037 assert(!prolog
|| !prolog
->rodata_size
);
5038 assert(!previous_stage
|| !previous_stage
->rodata_size
);
5039 assert(!prolog2
|| !prolog2
->rodata_size
);
5040 assert((!prolog
&& !previous_stage
&& !prolog2
&& !epilog
) ||
5041 !mainb
->rodata_size
);
5042 assert(!epilog
|| !epilog
->rodata_size
);
5044 r600_resource_reference(&shader
->bo
, NULL
);
5045 shader
->bo
= (struct r600_resource
*)
5046 pipe_buffer_create(&sscreen
->b
, 0,
5047 PIPE_USAGE_IMMUTABLE
,
5048 align(bo_size
, SI_CPDMA_ALIGNMENT
));
5053 ptr
= sscreen
->ws
->buffer_map(shader
->bo
->buf
, NULL
,
5054 PIPE_TRANSFER_READ_WRITE
|
5055 PIPE_TRANSFER_UNSYNCHRONIZED
);
5057 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5058 * endian-independent. */
5060 memcpy(ptr
, prolog
->code
, prolog
->code_size
);
5061 ptr
+= prolog
->code_size
;
5063 if (previous_stage
) {
5064 memcpy(ptr
, previous_stage
->code
, previous_stage
->code_size
);
5065 ptr
+= previous_stage
->code_size
;
5068 memcpy(ptr
, prolog2
->code
, prolog2
->code_size
);
5069 ptr
+= prolog2
->code_size
;
5072 memcpy(ptr
, mainb
->code
, mainb
->code_size
);
5073 ptr
+= mainb
->code_size
;
5076 memcpy(ptr
, epilog
->code
, epilog
->code_size
);
5077 else if (mainb
->rodata_size
> 0)
5078 memcpy(ptr
, mainb
->rodata
, mainb
->rodata_size
);
5080 sscreen
->ws
->buffer_unmap(shader
->bo
->buf
);
5084 static void si_shader_dump_disassembly(const struct ac_shader_binary
*binary
,
5085 struct pipe_debug_callback
*debug
,
5086 const char *name
, FILE *file
)
5091 if (binary
->disasm_string
) {
5092 fprintf(file
, "Shader %s disassembly:\n", name
);
5093 fprintf(file
, "%s", binary
->disasm_string
);
5095 if (debug
&& debug
->debug_message
) {
5096 /* Very long debug messages are cut off, so send the
5097 * disassembly one line at a time. This causes more
5098 * overhead, but on the plus side it simplifies
5099 * parsing of resulting logs.
5101 pipe_debug_message(debug
, SHADER_INFO
,
5102 "Shader Disassembly Begin");
5104 line
= binary
->disasm_string
;
5106 p
= util_strchrnul(line
, '\n');
5110 pipe_debug_message(debug
, SHADER_INFO
,
5111 "%.*s", count
, line
);
5119 pipe_debug_message(debug
, SHADER_INFO
,
5120 "Shader Disassembly End");
5123 fprintf(file
, "Shader %s binary:\n", name
);
5124 for (i
= 0; i
< binary
->code_size
; i
+= 4) {
5125 fprintf(file
, "@0x%x: %02x%02x%02x%02x\n", i
,
5126 binary
->code
[i
+ 3], binary
->code
[i
+ 2],
5127 binary
->code
[i
+ 1], binary
->code
[i
]);
5132 static void si_shader_dump_stats(struct si_screen
*sscreen
,
5133 const struct si_shader
*shader
,
5134 struct pipe_debug_callback
*debug
,
5137 bool check_debug_option
)
5139 const struct si_shader_config
*conf
= &shader
->config
;
5140 unsigned num_inputs
= shader
->selector
? shader
->selector
->info
.num_inputs
: 0;
5141 unsigned code_size
= si_get_shader_binary_size(shader
);
5142 unsigned lds_increment
= sscreen
->info
.chip_class
>= CIK
? 512 : 256;
5143 unsigned lds_per_wave
= 0;
5144 unsigned max_simd_waves
;
5146 switch (sscreen
->info
.family
) {
5147 /* These always have 8 waves: */
5148 case CHIP_POLARIS10
:
5149 case CHIP_POLARIS11
:
5150 case CHIP_POLARIS12
:
5154 max_simd_waves
= 10;
5157 /* Compute LDS usage for PS. */
5158 switch (processor
) {
5159 case PIPE_SHADER_FRAGMENT
:
5160 /* The minimum usage per wave is (num_inputs * 48). The maximum
5161 * usage is (num_inputs * 48 * 16).
5162 * We can get anything in between and it varies between waves.
5164 * The 48 bytes per input for a single primitive is equal to
5165 * 4 bytes/component * 4 components/input * 3 points.
5167 * Other stages don't know the size at compile time or don't
5168 * allocate LDS per wave, but instead they do it per thread group.
5170 lds_per_wave
= conf
->lds_size
* lds_increment
+
5171 align(num_inputs
* 48, lds_increment
);
5173 case PIPE_SHADER_COMPUTE
:
5174 if (shader
->selector
) {
5175 unsigned max_workgroup_size
=
5176 si_get_max_workgroup_size(shader
);
5177 lds_per_wave
= (conf
->lds_size
* lds_increment
) /
5178 DIV_ROUND_UP(max_workgroup_size
, 64);
5183 /* Compute the per-SIMD wave counts. */
5184 if (conf
->num_sgprs
) {
5185 if (sscreen
->info
.chip_class
>= VI
)
5186 max_simd_waves
= MIN2(max_simd_waves
, 800 / conf
->num_sgprs
);
5188 max_simd_waves
= MIN2(max_simd_waves
, 512 / conf
->num_sgprs
);
5191 if (conf
->num_vgprs
)
5192 max_simd_waves
= MIN2(max_simd_waves
, 256 / conf
->num_vgprs
);
5194 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5195 * 16KB makes some SIMDs unoccupied). */
5197 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
5199 if (!check_debug_option
||
5200 si_can_dump_shader(sscreen
, processor
)) {
5201 if (processor
== PIPE_SHADER_FRAGMENT
) {
5202 fprintf(file
, "*** SHADER CONFIG ***\n"
5203 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5204 "SPI_PS_INPUT_ENA = 0x%04x\n",
5205 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
5208 fprintf(file
, "*** SHADER STATS ***\n"
5211 "Spilled SGPRs: %d\n"
5212 "Spilled VGPRs: %d\n"
5213 "Private memory VGPRs: %d\n"
5214 "Code Size: %d bytes\n"
5216 "Scratch: %d bytes per wave\n"
5218 "********************\n\n\n",
5219 conf
->num_sgprs
, conf
->num_vgprs
,
5220 conf
->spilled_sgprs
, conf
->spilled_vgprs
,
5221 conf
->private_mem_vgprs
, code_size
,
5222 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
5226 pipe_debug_message(debug
, SHADER_INFO
,
5227 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5228 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5229 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5230 conf
->num_sgprs
, conf
->num_vgprs
, code_size
,
5231 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
5232 max_simd_waves
, conf
->spilled_sgprs
,
5233 conf
->spilled_vgprs
, conf
->private_mem_vgprs
);
5236 const char *si_get_shader_name(const struct si_shader
*shader
, unsigned processor
)
5238 switch (processor
) {
5239 case PIPE_SHADER_VERTEX
:
5240 if (shader
->key
.as_es
)
5241 return "Vertex Shader as ES";
5242 else if (shader
->key
.as_ls
)
5243 return "Vertex Shader as LS";
5245 return "Vertex Shader as VS";
5246 case PIPE_SHADER_TESS_CTRL
:
5247 return "Tessellation Control Shader";
5248 case PIPE_SHADER_TESS_EVAL
:
5249 if (shader
->key
.as_es
)
5250 return "Tessellation Evaluation Shader as ES";
5252 return "Tessellation Evaluation Shader as VS";
5253 case PIPE_SHADER_GEOMETRY
:
5254 if (shader
->is_gs_copy_shader
)
5255 return "GS Copy Shader as VS";
5257 return "Geometry Shader";
5258 case PIPE_SHADER_FRAGMENT
:
5259 return "Pixel Shader";
5260 case PIPE_SHADER_COMPUTE
:
5261 return "Compute Shader";
5263 return "Unknown Shader";
5267 void si_shader_dump(struct si_screen
*sscreen
, const struct si_shader
*shader
,
5268 struct pipe_debug_callback
*debug
, unsigned processor
,
5269 FILE *file
, bool check_debug_option
)
5271 if (!check_debug_option
||
5272 si_can_dump_shader(sscreen
, processor
))
5273 si_dump_shader_key(processor
, shader
, file
);
5275 if (!check_debug_option
&& shader
->binary
.llvm_ir_string
) {
5276 if (shader
->previous_stage
&&
5277 shader
->previous_stage
->binary
.llvm_ir_string
) {
5278 fprintf(file
, "\n%s - previous stage - LLVM IR:\n\n",
5279 si_get_shader_name(shader
, processor
));
5280 fprintf(file
, "%s\n", shader
->previous_stage
->binary
.llvm_ir_string
);
5283 fprintf(file
, "\n%s - main shader part - LLVM IR:\n\n",
5284 si_get_shader_name(shader
, processor
));
5285 fprintf(file
, "%s\n", shader
->binary
.llvm_ir_string
);
5288 if (!check_debug_option
||
5289 (si_can_dump_shader(sscreen
, processor
) &&
5290 !(sscreen
->debug_flags
& DBG(NO_ASM
)))) {
5291 fprintf(file
, "\n%s:\n", si_get_shader_name(shader
, processor
));
5294 si_shader_dump_disassembly(&shader
->prolog
->binary
,
5295 debug
, "prolog", file
);
5296 if (shader
->previous_stage
)
5297 si_shader_dump_disassembly(&shader
->previous_stage
->binary
,
5298 debug
, "previous stage", file
);
5299 if (shader
->prolog2
)
5300 si_shader_dump_disassembly(&shader
->prolog2
->binary
,
5301 debug
, "prolog2", file
);
5303 si_shader_dump_disassembly(&shader
->binary
, debug
, "main", file
);
5306 si_shader_dump_disassembly(&shader
->epilog
->binary
,
5307 debug
, "epilog", file
);
5308 fprintf(file
, "\n");
5311 si_shader_dump_stats(sscreen
, shader
, debug
, processor
, file
,
5312 check_debug_option
);
5315 static int si_compile_llvm(struct si_screen
*sscreen
,
5316 struct ac_shader_binary
*binary
,
5317 struct si_shader_config
*conf
,
5318 LLVMTargetMachineRef tm
,
5320 struct pipe_debug_callback
*debug
,
5325 unsigned count
= p_atomic_inc_return(&sscreen
->num_compilations
);
5327 if (si_can_dump_shader(sscreen
, processor
)) {
5328 fprintf(stderr
, "radeonsi: Compiling shader %d\n", count
);
5330 if (!(sscreen
->debug_flags
& (DBG(NO_IR
) | DBG(PREOPT_IR
)))) {
5331 fprintf(stderr
, "%s LLVM IR:\n\n", name
);
5332 ac_dump_module(mod
);
5333 fprintf(stderr
, "\n");
5337 if (sscreen
->record_llvm_ir
) {
5338 char *ir
= LLVMPrintModuleToString(mod
);
5339 binary
->llvm_ir_string
= strdup(ir
);
5340 LLVMDisposeMessage(ir
);
5343 if (!si_replace_shader(count
, binary
)) {
5344 r
= si_llvm_compile(mod
, binary
, tm
, debug
);
5349 si_shader_binary_read_config(binary
, conf
, 0);
5351 /* Enable 64-bit and 16-bit denormals, because there is no performance
5354 * If denormals are enabled, all floating-point output modifiers are
5357 * Don't enable denormals for 32-bit floats, because:
5358 * - Floating-point output modifiers would be ignored by the hw.
5359 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5360 * have to stop using those.
5361 * - SI & CI would be very slow.
5363 conf
->float_mode
|= V_00B028_FP_64_DENORMS
;
5365 FREE(binary
->config
);
5366 FREE(binary
->global_symbol_offsets
);
5367 binary
->config
= NULL
;
5368 binary
->global_symbol_offsets
= NULL
;
5370 /* Some shaders can't have rodata because their binaries can be
5373 if (binary
->rodata_size
&&
5374 (processor
== PIPE_SHADER_VERTEX
||
5375 processor
== PIPE_SHADER_TESS_CTRL
||
5376 processor
== PIPE_SHADER_TESS_EVAL
||
5377 processor
== PIPE_SHADER_FRAGMENT
)) {
5378 fprintf(stderr
, "radeonsi: The shader can't have rodata.");
5385 static void si_llvm_build_ret(struct si_shader_context
*ctx
, LLVMValueRef ret
)
5387 if (LLVMGetTypeKind(LLVMTypeOf(ret
)) == LLVMVoidTypeKind
)
5388 LLVMBuildRetVoid(ctx
->ac
.builder
);
5390 LLVMBuildRet(ctx
->ac
.builder
, ret
);
5393 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5395 si_generate_gs_copy_shader(struct si_screen
*sscreen
,
5396 LLVMTargetMachineRef tm
,
5397 struct si_shader_selector
*gs_selector
,
5398 struct pipe_debug_callback
*debug
)
5400 struct si_shader_context ctx
;
5401 struct si_shader
*shader
;
5402 LLVMBuilderRef builder
;
5403 struct lp_build_tgsi_context
*bld_base
= &ctx
.bld_base
;
5404 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
5405 struct si_shader_output_values
*outputs
;
5406 struct tgsi_shader_info
*gsinfo
= &gs_selector
->info
;
5409 outputs
= MALLOC(gsinfo
->num_outputs
* sizeof(outputs
[0]));
5414 shader
= CALLOC_STRUCT(si_shader
);
5420 /* We can leave the fence as permanently signaled because the GS copy
5421 * shader only becomes visible globally after it has been compiled. */
5422 util_queue_fence_init(&shader
->ready
);
5424 shader
->selector
= gs_selector
;
5425 shader
->is_gs_copy_shader
= true;
5427 si_init_shader_ctx(&ctx
, sscreen
, tm
);
5428 ctx
.shader
= shader
;
5429 ctx
.type
= PIPE_SHADER_VERTEX
;
5431 builder
= ctx
.ac
.builder
;
5433 create_function(&ctx
);
5434 preload_ring_buffers(&ctx
);
5436 LLVMValueRef voffset
=
5437 lp_build_mul_imm(uint
, ctx
.abi
.vertex_id
, 4);
5439 /* Fetch the vertex stream ID.*/
5440 LLVMValueRef stream_id
;
5442 if (gs_selector
->so
.num_outputs
)
5443 stream_id
= unpack_param(&ctx
, ctx
.param_streamout_config
, 24, 2);
5445 stream_id
= ctx
.i32_0
;
5447 /* Fill in output information. */
5448 for (i
= 0; i
< gsinfo
->num_outputs
; ++i
) {
5449 outputs
[i
].semantic_name
= gsinfo
->output_semantic_name
[i
];
5450 outputs
[i
].semantic_index
= gsinfo
->output_semantic_index
[i
];
5452 for (int chan
= 0; chan
< 4; chan
++) {
5453 outputs
[i
].vertex_stream
[chan
] =
5454 (gsinfo
->output_streams
[i
] >> (2 * chan
)) & 3;
5458 LLVMBasicBlockRef end_bb
;
5459 LLVMValueRef switch_inst
;
5461 end_bb
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, ctx
.main_fn
, "end");
5462 switch_inst
= LLVMBuildSwitch(builder
, stream_id
, end_bb
, 4);
5464 for (int stream
= 0; stream
< 4; stream
++) {
5465 LLVMBasicBlockRef bb
;
5468 if (!gsinfo
->num_stream_output_components
[stream
])
5471 if (stream
> 0 && !gs_selector
->so
.num_outputs
)
5474 bb
= LLVMInsertBasicBlockInContext(ctx
.ac
.context
, end_bb
, "out");
5475 LLVMAddCase(switch_inst
, LLVMConstInt(ctx
.i32
, stream
, 0), bb
);
5476 LLVMPositionBuilderAtEnd(builder
, bb
);
5478 /* Fetch vertex data from GSVS ring */
5480 for (i
= 0; i
< gsinfo
->num_outputs
; ++i
) {
5481 for (unsigned chan
= 0; chan
< 4; chan
++) {
5482 if (!(gsinfo
->output_usagemask
[i
] & (1 << chan
)) ||
5483 outputs
[i
].vertex_stream
[chan
] != stream
) {
5484 outputs
[i
].values
[chan
] = ctx
.bld_base
.base
.undef
;
5488 LLVMValueRef soffset
= LLVMConstInt(ctx
.i32
,
5489 offset
* gs_selector
->gs_max_out_vertices
* 16 * 4, 0);
5492 outputs
[i
].values
[chan
] =
5493 ac_build_buffer_load(&ctx
.ac
,
5494 ctx
.gsvs_ring
[0], 1,
5501 /* Streamout and exports. */
5502 if (gs_selector
->so
.num_outputs
) {
5503 si_llvm_emit_streamout(&ctx
, outputs
,
5504 gsinfo
->num_outputs
,
5509 si_llvm_export_vs(&ctx
, outputs
, gsinfo
->num_outputs
);
5511 LLVMBuildBr(builder
, end_bb
);
5514 LLVMPositionBuilderAtEnd(builder
, end_bb
);
5516 LLVMBuildRetVoid(ctx
.ac
.builder
);
5518 ctx
.type
= PIPE_SHADER_GEOMETRY
; /* override for shader dumping */
5519 si_llvm_optimize_module(&ctx
);
5521 r
= si_compile_llvm(sscreen
, &ctx
.shader
->binary
,
5522 &ctx
.shader
->config
, ctx
.tm
,
5524 debug
, PIPE_SHADER_GEOMETRY
,
5527 if (si_can_dump_shader(sscreen
, PIPE_SHADER_GEOMETRY
))
5528 fprintf(stderr
, "GS Copy Shader:\n");
5529 si_shader_dump(sscreen
, ctx
.shader
, debug
,
5530 PIPE_SHADER_GEOMETRY
, stderr
, true);
5531 r
= si_shader_binary_upload(sscreen
, ctx
.shader
);
5534 si_llvm_dispose(&ctx
);
5545 static void si_dump_shader_key_vs(const struct si_shader_key
*key
,
5546 const struct si_vs_prolog_bits
*prolog
,
5547 const char *prefix
, FILE *f
)
5549 fprintf(f
, " %s.instance_divisor_is_one = %u\n",
5550 prefix
, prolog
->instance_divisor_is_one
);
5551 fprintf(f
, " %s.instance_divisor_is_fetched = %u\n",
5552 prefix
, prolog
->instance_divisor_is_fetched
);
5553 fprintf(f
, " %s.ls_vgpr_fix = %u\n",
5554 prefix
, prolog
->ls_vgpr_fix
);
5556 fprintf(f
, " mono.vs.fix_fetch = {");
5557 for (int i
= 0; i
< SI_MAX_ATTRIBS
; i
++)
5558 fprintf(f
, !i
? "%u" : ", %u", key
->mono
.vs_fix_fetch
[i
]);
5562 static void si_dump_shader_key(unsigned processor
, const struct si_shader
*shader
,
5565 const struct si_shader_key
*key
= &shader
->key
;
5567 fprintf(f
, "SHADER KEY\n");
5569 switch (processor
) {
5570 case PIPE_SHADER_VERTEX
:
5571 si_dump_shader_key_vs(key
, &key
->part
.vs
.prolog
,
5572 "part.vs.prolog", f
);
5573 fprintf(f
, " as_es = %u\n", key
->as_es
);
5574 fprintf(f
, " as_ls = %u\n", key
->as_ls
);
5575 fprintf(f
, " mono.u.vs_export_prim_id = %u\n",
5576 key
->mono
.u
.vs_export_prim_id
);
5579 case PIPE_SHADER_TESS_CTRL
:
5580 if (shader
->selector
->screen
->info
.chip_class
>= GFX9
) {
5581 si_dump_shader_key_vs(key
, &key
->part
.tcs
.ls_prolog
,
5582 "part.tcs.ls_prolog", f
);
5584 fprintf(f
, " part.tcs.epilog.prim_mode = %u\n", key
->part
.tcs
.epilog
.prim_mode
);
5585 fprintf(f
, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64
"\n", key
->mono
.u
.ff_tcs_inputs_to_copy
);
5588 case PIPE_SHADER_TESS_EVAL
:
5589 fprintf(f
, " as_es = %u\n", key
->as_es
);
5590 fprintf(f
, " mono.u.vs_export_prim_id = %u\n",
5591 key
->mono
.u
.vs_export_prim_id
);
5594 case PIPE_SHADER_GEOMETRY
:
5595 if (shader
->is_gs_copy_shader
)
5598 if (shader
->selector
->screen
->info
.chip_class
>= GFX9
&&
5599 key
->part
.gs
.es
->type
== PIPE_SHADER_VERTEX
) {
5600 si_dump_shader_key_vs(key
, &key
->part
.gs
.vs_prolog
,
5601 "part.gs.vs_prolog", f
);
5603 fprintf(f
, " part.gs.prolog.tri_strip_adj_fix = %u\n", key
->part
.gs
.prolog
.tri_strip_adj_fix
);
5606 case PIPE_SHADER_COMPUTE
:
5609 case PIPE_SHADER_FRAGMENT
:
5610 fprintf(f
, " part.ps.prolog.color_two_side = %u\n", key
->part
.ps
.prolog
.color_two_side
);
5611 fprintf(f
, " part.ps.prolog.flatshade_colors = %u\n", key
->part
.ps
.prolog
.flatshade_colors
);
5612 fprintf(f
, " part.ps.prolog.poly_stipple = %u\n", key
->part
.ps
.prolog
.poly_stipple
);
5613 fprintf(f
, " part.ps.prolog.force_persp_sample_interp = %u\n", key
->part
.ps
.prolog
.force_persp_sample_interp
);
5614 fprintf(f
, " part.ps.prolog.force_linear_sample_interp = %u\n", key
->part
.ps
.prolog
.force_linear_sample_interp
);
5615 fprintf(f
, " part.ps.prolog.force_persp_center_interp = %u\n", key
->part
.ps
.prolog
.force_persp_center_interp
);
5616 fprintf(f
, " part.ps.prolog.force_linear_center_interp = %u\n", key
->part
.ps
.prolog
.force_linear_center_interp
);
5617 fprintf(f
, " part.ps.prolog.bc_optimize_for_persp = %u\n", key
->part
.ps
.prolog
.bc_optimize_for_persp
);
5618 fprintf(f
, " part.ps.prolog.bc_optimize_for_linear = %u\n", key
->part
.ps
.prolog
.bc_optimize_for_linear
);
5619 fprintf(f
, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key
->part
.ps
.epilog
.spi_shader_col_format
);
5620 fprintf(f
, " part.ps.epilog.color_is_int8 = 0x%X\n", key
->part
.ps
.epilog
.color_is_int8
);
5621 fprintf(f
, " part.ps.epilog.color_is_int10 = 0x%X\n", key
->part
.ps
.epilog
.color_is_int10
);
5622 fprintf(f
, " part.ps.epilog.last_cbuf = %u\n", key
->part
.ps
.epilog
.last_cbuf
);
5623 fprintf(f
, " part.ps.epilog.alpha_func = %u\n", key
->part
.ps
.epilog
.alpha_func
);
5624 fprintf(f
, " part.ps.epilog.alpha_to_one = %u\n", key
->part
.ps
.epilog
.alpha_to_one
);
5625 fprintf(f
, " part.ps.epilog.poly_line_smoothing = %u\n", key
->part
.ps
.epilog
.poly_line_smoothing
);
5626 fprintf(f
, " part.ps.epilog.clamp_color = %u\n", key
->part
.ps
.epilog
.clamp_color
);
5633 if ((processor
== PIPE_SHADER_GEOMETRY
||
5634 processor
== PIPE_SHADER_TESS_EVAL
||
5635 processor
== PIPE_SHADER_VERTEX
) &&
5636 !key
->as_es
&& !key
->as_ls
) {
5637 fprintf(f
, " opt.kill_outputs = 0x%"PRIx64
"\n", key
->opt
.kill_outputs
);
5638 fprintf(f
, " opt.clip_disable = %u\n", key
->opt
.clip_disable
);
5642 static void si_init_shader_ctx(struct si_shader_context
*ctx
,
5643 struct si_screen
*sscreen
,
5644 LLVMTargetMachineRef tm
)
5646 struct lp_build_tgsi_context
*bld_base
;
5648 si_llvm_context_init(ctx
, sscreen
, tm
);
5650 bld_base
= &ctx
->bld_base
;
5651 bld_base
->emit_fetch_funcs
[TGSI_FILE_CONSTANT
] = fetch_constant
;
5653 bld_base
->op_actions
[TGSI_OPCODE_INTERP_CENTROID
] = interp_action
;
5654 bld_base
->op_actions
[TGSI_OPCODE_INTERP_SAMPLE
] = interp_action
;
5655 bld_base
->op_actions
[TGSI_OPCODE_INTERP_OFFSET
] = interp_action
;
5657 bld_base
->op_actions
[TGSI_OPCODE_MEMBAR
].emit
= membar_emit
;
5659 bld_base
->op_actions
[TGSI_OPCODE_CLOCK
].emit
= clock_emit
;
5661 bld_base
->op_actions
[TGSI_OPCODE_DDX
].emit
= si_llvm_emit_ddxy
;
5662 bld_base
->op_actions
[TGSI_OPCODE_DDY
].emit
= si_llvm_emit_ddxy
;
5663 bld_base
->op_actions
[TGSI_OPCODE_DDX_FINE
].emit
= si_llvm_emit_ddxy
;
5664 bld_base
->op_actions
[TGSI_OPCODE_DDY_FINE
].emit
= si_llvm_emit_ddxy
;
5666 bld_base
->op_actions
[TGSI_OPCODE_VOTE_ALL
].emit
= vote_all_emit
;
5667 bld_base
->op_actions
[TGSI_OPCODE_VOTE_ANY
].emit
= vote_any_emit
;
5668 bld_base
->op_actions
[TGSI_OPCODE_VOTE_EQ
].emit
= vote_eq_emit
;
5669 bld_base
->op_actions
[TGSI_OPCODE_BALLOT
].emit
= ballot_emit
;
5670 bld_base
->op_actions
[TGSI_OPCODE_READ_FIRST
].intr_name
= "llvm.amdgcn.readfirstlane";
5671 bld_base
->op_actions
[TGSI_OPCODE_READ_FIRST
].emit
= read_lane_emit
;
5672 bld_base
->op_actions
[TGSI_OPCODE_READ_INVOC
].intr_name
= "llvm.amdgcn.readlane";
5673 bld_base
->op_actions
[TGSI_OPCODE_READ_INVOC
].fetch_args
= read_invoc_fetch_args
;
5674 bld_base
->op_actions
[TGSI_OPCODE_READ_INVOC
].emit
= read_lane_emit
;
5676 bld_base
->op_actions
[TGSI_OPCODE_EMIT
].emit
= si_tgsi_emit_vertex
;
5677 bld_base
->op_actions
[TGSI_OPCODE_ENDPRIM
].emit
= si_llvm_emit_primitive
;
5678 bld_base
->op_actions
[TGSI_OPCODE_BARRIER
].emit
= si_llvm_emit_barrier
;
5681 static void si_optimize_vs_outputs(struct si_shader_context
*ctx
)
5683 struct si_shader
*shader
= ctx
->shader
;
5684 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
5686 if ((ctx
->type
!= PIPE_SHADER_VERTEX
&&
5687 ctx
->type
!= PIPE_SHADER_TESS_EVAL
) ||
5688 shader
->key
.as_ls
||
5692 ac_optimize_vs_outputs(&ctx
->ac
,
5694 shader
->info
.vs_output_param_offset
,
5696 &shader
->info
.nr_param_exports
);
5699 static void si_count_scratch_private_memory(struct si_shader_context
*ctx
)
5701 ctx
->shader
->config
.private_mem_vgprs
= 0;
5703 /* Process all LLVM instructions. */
5704 LLVMBasicBlockRef bb
= LLVMGetFirstBasicBlock(ctx
->main_fn
);
5706 LLVMValueRef next
= LLVMGetFirstInstruction(bb
);
5709 LLVMValueRef inst
= next
;
5710 next
= LLVMGetNextInstruction(next
);
5712 if (LLVMGetInstructionOpcode(inst
) != LLVMAlloca
)
5715 LLVMTypeRef type
= LLVMGetElementType(LLVMTypeOf(inst
));
5716 /* No idea why LLVM aligns allocas to 4 elements. */
5717 unsigned alignment
= LLVMGetAlignment(inst
);
5718 unsigned dw_size
= align(ac_get_type_size(type
) / 4, alignment
);
5719 ctx
->shader
->config
.private_mem_vgprs
+= dw_size
;
5721 bb
= LLVMGetNextBasicBlock(bb
);
5725 static void si_init_exec_full_mask(struct si_shader_context
*ctx
)
5727 LLVMValueRef full_mask
= LLVMConstInt(ctx
->i64
, ~0ull, 0);
5728 lp_build_intrinsic(ctx
->ac
.builder
,
5729 "llvm.amdgcn.init.exec", ctx
->voidt
,
5730 &full_mask
, 1, LP_FUNC_ATTR_CONVERGENT
);
5733 static void si_init_exec_from_input(struct si_shader_context
*ctx
,
5734 unsigned param
, unsigned bitoffset
)
5736 LLVMValueRef args
[] = {
5737 LLVMGetParam(ctx
->main_fn
, param
),
5738 LLVMConstInt(ctx
->i32
, bitoffset
, 0),
5740 lp_build_intrinsic(ctx
->ac
.builder
,
5741 "llvm.amdgcn.init.exec.from.input",
5742 ctx
->voidt
, args
, 2, LP_FUNC_ATTR_CONVERGENT
);
5745 static bool si_vs_needs_prolog(const struct si_shader_selector
*sel
,
5746 const struct si_vs_prolog_bits
*key
)
5748 /* VGPR initialization fixup for Vega10 and Raven is always done in the
5750 return sel
->vs_needs_prolog
|| key
->ls_vgpr_fix
;
5753 static bool si_compile_tgsi_main(struct si_shader_context
*ctx
,
5756 struct si_shader
*shader
= ctx
->shader
;
5757 struct si_shader_selector
*sel
= shader
->selector
;
5758 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
5760 // TODO clean all this up!
5761 switch (ctx
->type
) {
5762 case PIPE_SHADER_VERTEX
:
5763 ctx
->load_input
= declare_input_vs
;
5764 if (shader
->key
.as_ls
)
5765 ctx
->abi
.emit_outputs
= si_llvm_emit_ls_epilogue
;
5766 else if (shader
->key
.as_es
)
5767 ctx
->abi
.emit_outputs
= si_llvm_emit_es_epilogue
;
5769 ctx
->abi
.emit_outputs
= si_llvm_emit_vs_epilogue
;
5770 bld_base
->emit_epilogue
= si_tgsi_emit_epilogue
;
5772 case PIPE_SHADER_TESS_CTRL
:
5773 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_tcs
;
5774 bld_base
->emit_fetch_funcs
[TGSI_FILE_OUTPUT
] = fetch_output_tcs
;
5775 bld_base
->emit_store
= store_output_tcs
;
5776 bld_base
->emit_epilogue
= si_llvm_emit_tcs_epilogue
;
5778 case PIPE_SHADER_TESS_EVAL
:
5779 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_tes
;
5780 if (shader
->key
.as_es
)
5781 ctx
->abi
.emit_outputs
= si_llvm_emit_es_epilogue
;
5783 ctx
->abi
.emit_outputs
= si_llvm_emit_vs_epilogue
;
5784 bld_base
->emit_epilogue
= si_tgsi_emit_epilogue
;
5786 case PIPE_SHADER_GEOMETRY
:
5787 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_gs
;
5788 ctx
->abi
.emit_vertex
= si_llvm_emit_vertex
;
5789 ctx
->abi
.emit_outputs
= si_llvm_emit_gs_epilogue
;
5790 bld_base
->emit_epilogue
= si_tgsi_emit_gs_epilogue
;
5792 case PIPE_SHADER_FRAGMENT
:
5793 ctx
->load_input
= declare_input_fs
;
5794 ctx
->abi
.emit_outputs
= si_llvm_return_fs_outputs
;
5795 bld_base
->emit_epilogue
= si_tgsi_emit_epilogue
;
5797 case PIPE_SHADER_COMPUTE
:
5800 assert(!"Unsupported shader type");
5804 ctx
->abi
.load_ubo
= load_ubo
;
5805 ctx
->abi
.load_ssbo
= load_ssbo
;
5807 create_function(ctx
);
5808 preload_ring_buffers(ctx
);
5810 /* For GFX9 merged shaders:
5811 * - Set EXEC for the first shader. If the prolog is present, set
5812 * EXEC there instead.
5813 * - Add a barrier before the second shader.
5814 * - In the second shader, reset EXEC to ~0 and wrap the main part in
5815 * an if-statement. This is required for correctness in geometry
5816 * shaders, to ensure that empty GS waves do not send GS_EMIT and
5819 * For monolithic merged shaders, the first shader is wrapped in an
5820 * if-block together with its prolog in si_build_wrapper_function.
5822 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
5823 if (!is_monolithic
&&
5824 sel
->info
.num_instructions
> 1 && /* not empty shader */
5825 (shader
->key
.as_es
|| shader
->key
.as_ls
) &&
5826 (ctx
->type
== PIPE_SHADER_TESS_EVAL
||
5827 (ctx
->type
== PIPE_SHADER_VERTEX
&&
5828 !si_vs_needs_prolog(sel
, &shader
->key
.part
.vs
.prolog
)))) {
5829 si_init_exec_from_input(ctx
,
5830 ctx
->param_merged_wave_info
, 0);
5831 } else if (ctx
->type
== PIPE_SHADER_TESS_CTRL
||
5832 ctx
->type
== PIPE_SHADER_GEOMETRY
) {
5834 si_init_exec_full_mask(ctx
);
5836 /* The barrier must execute for all shaders in a
5839 si_llvm_emit_barrier(NULL
, bld_base
, NULL
);
5841 LLVMValueRef num_threads
= unpack_param(ctx
, ctx
->param_merged_wave_info
, 8, 8);
5843 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
5844 ac_get_thread_id(&ctx
->ac
), num_threads
, "");
5845 lp_build_if(&ctx
->merged_wrap_if_state
, &ctx
->gallivm
, ena
);
5849 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&&
5850 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
) {
5851 for (unsigned i
= 0; i
< 6; i
++) {
5852 ctx
->invoc0_tess_factors
[i
] =
5853 lp_build_alloca_undef(&ctx
->gallivm
, ctx
->i32
, "");
5857 if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
5859 for (i
= 0; i
< 4; i
++) {
5860 ctx
->gs_next_vertex
[i
] =
5861 lp_build_alloca(&ctx
->gallivm
,
5866 if (sel
->force_correct_derivs_after_kill
) {
5867 ctx
->postponed_kill
= lp_build_alloca_undef(&ctx
->gallivm
, ctx
->i1
, "");
5868 /* true = don't kill. */
5869 LLVMBuildStore(ctx
->ac
.builder
, LLVMConstInt(ctx
->i1
, 1, 0),
5870 ctx
->postponed_kill
);
5874 if (!lp_build_tgsi_llvm(bld_base
, sel
->tokens
)) {
5875 fprintf(stderr
, "Failed to translate shader from TGSI to LLVM\n");
5879 if (!si_nir_build_llvm(ctx
, sel
->nir
)) {
5880 fprintf(stderr
, "Failed to translate shader from NIR to LLVM\n");
5885 si_llvm_build_ret(ctx
, ctx
->return_value
);
5890 * Compute the VS prolog key, which contains all the information needed to
5891 * build the VS prolog function, and set shader->info bits where needed.
5893 * \param info Shader info of the vertex shader.
5894 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
5895 * \param prolog_key Key of the VS prolog
5896 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
5897 * \param key Output shader part key.
5899 static void si_get_vs_prolog_key(const struct tgsi_shader_info
*info
,
5900 unsigned num_input_sgprs
,
5901 const struct si_vs_prolog_bits
*prolog_key
,
5902 struct si_shader
*shader_out
,
5903 union si_shader_part_key
*key
)
5905 memset(key
, 0, sizeof(*key
));
5906 key
->vs_prolog
.states
= *prolog_key
;
5907 key
->vs_prolog
.num_input_sgprs
= num_input_sgprs
;
5908 key
->vs_prolog
.last_input
= MAX2(1, info
->num_inputs
) - 1;
5909 key
->vs_prolog
.as_ls
= shader_out
->key
.as_ls
;
5910 key
->vs_prolog
.as_es
= shader_out
->key
.as_es
;
5912 if (shader_out
->selector
->type
== PIPE_SHADER_TESS_CTRL
) {
5913 key
->vs_prolog
.as_ls
= 1;
5914 key
->vs_prolog
.num_merged_next_stage_vgprs
= 2;
5915 } else if (shader_out
->selector
->type
== PIPE_SHADER_GEOMETRY
) {
5916 key
->vs_prolog
.as_es
= 1;
5917 key
->vs_prolog
.num_merged_next_stage_vgprs
= 5;
5920 /* Enable loading the InstanceID VGPR. */
5921 uint16_t input_mask
= u_bit_consecutive(0, info
->num_inputs
);
5923 if ((key
->vs_prolog
.states
.instance_divisor_is_one
|
5924 key
->vs_prolog
.states
.instance_divisor_is_fetched
) & input_mask
)
5925 shader_out
->info
.uses_instanceid
= true;
5929 * Compute the PS prolog key, which contains all the information needed to
5930 * build the PS prolog function, and set related bits in shader->config.
5932 static void si_get_ps_prolog_key(struct si_shader
*shader
,
5933 union si_shader_part_key
*key
,
5934 bool separate_prolog
)
5936 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
5938 memset(key
, 0, sizeof(*key
));
5939 key
->ps_prolog
.states
= shader
->key
.part
.ps
.prolog
;
5940 key
->ps_prolog
.colors_read
= info
->colors_read
;
5941 key
->ps_prolog
.num_input_sgprs
= shader
->info
.num_input_sgprs
;
5942 key
->ps_prolog
.num_input_vgprs
= shader
->info
.num_input_vgprs
;
5943 key
->ps_prolog
.wqm
= info
->uses_derivatives
&&
5944 (key
->ps_prolog
.colors_read
||
5945 key
->ps_prolog
.states
.force_persp_sample_interp
||
5946 key
->ps_prolog
.states
.force_linear_sample_interp
||
5947 key
->ps_prolog
.states
.force_persp_center_interp
||
5948 key
->ps_prolog
.states
.force_linear_center_interp
||
5949 key
->ps_prolog
.states
.bc_optimize_for_persp
||
5950 key
->ps_prolog
.states
.bc_optimize_for_linear
);
5951 key
->ps_prolog
.ancillary_vgpr_index
= shader
->info
.ancillary_vgpr_index
;
5953 if (info
->colors_read
) {
5954 unsigned *color
= shader
->selector
->color_attr_index
;
5956 if (shader
->key
.part
.ps
.prolog
.color_two_side
) {
5957 /* BCOLORs are stored after the last input. */
5958 key
->ps_prolog
.num_interp_inputs
= info
->num_inputs
;
5959 key
->ps_prolog
.face_vgpr_index
= shader
->info
.face_vgpr_index
;
5960 shader
->config
.spi_ps_input_ena
|= S_0286CC_FRONT_FACE_ENA(1);
5963 for (unsigned i
= 0; i
< 2; i
++) {
5964 unsigned interp
= info
->input_interpolate
[color
[i
]];
5965 unsigned location
= info
->input_interpolate_loc
[color
[i
]];
5967 if (!(info
->colors_read
& (0xf << i
*4)))
5970 key
->ps_prolog
.color_attr_index
[i
] = color
[i
];
5972 if (shader
->key
.part
.ps
.prolog
.flatshade_colors
&&
5973 interp
== TGSI_INTERPOLATE_COLOR
)
5974 interp
= TGSI_INTERPOLATE_CONSTANT
;
5977 case TGSI_INTERPOLATE_CONSTANT
:
5978 key
->ps_prolog
.color_interp_vgpr_index
[i
] = -1;
5980 case TGSI_INTERPOLATE_PERSPECTIVE
:
5981 case TGSI_INTERPOLATE_COLOR
:
5982 /* Force the interpolation location for colors here. */
5983 if (shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
)
5984 location
= TGSI_INTERPOLATE_LOC_SAMPLE
;
5985 if (shader
->key
.part
.ps
.prolog
.force_persp_center_interp
)
5986 location
= TGSI_INTERPOLATE_LOC_CENTER
;
5989 case TGSI_INTERPOLATE_LOC_SAMPLE
:
5990 key
->ps_prolog
.color_interp_vgpr_index
[i
] = 0;
5991 shader
->config
.spi_ps_input_ena
|=
5992 S_0286CC_PERSP_SAMPLE_ENA(1);
5994 case TGSI_INTERPOLATE_LOC_CENTER
:
5995 key
->ps_prolog
.color_interp_vgpr_index
[i
] = 2;
5996 shader
->config
.spi_ps_input_ena
|=
5997 S_0286CC_PERSP_CENTER_ENA(1);
5999 case TGSI_INTERPOLATE_LOC_CENTROID
:
6000 key
->ps_prolog
.color_interp_vgpr_index
[i
] = 4;
6001 shader
->config
.spi_ps_input_ena
|=
6002 S_0286CC_PERSP_CENTROID_ENA(1);
6008 case TGSI_INTERPOLATE_LINEAR
:
6009 /* Force the interpolation location for colors here. */
6010 if (shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
)
6011 location
= TGSI_INTERPOLATE_LOC_SAMPLE
;
6012 if (shader
->key
.part
.ps
.prolog
.force_linear_center_interp
)
6013 location
= TGSI_INTERPOLATE_LOC_CENTER
;
6015 /* The VGPR assignment for non-monolithic shaders
6016 * works because InitialPSInputAddr is set on the
6017 * main shader and PERSP_PULL_MODEL is never used.
6020 case TGSI_INTERPOLATE_LOC_SAMPLE
:
6021 key
->ps_prolog
.color_interp_vgpr_index
[i
] =
6022 separate_prolog
? 6 : 9;
6023 shader
->config
.spi_ps_input_ena
|=
6024 S_0286CC_LINEAR_SAMPLE_ENA(1);
6026 case TGSI_INTERPOLATE_LOC_CENTER
:
6027 key
->ps_prolog
.color_interp_vgpr_index
[i
] =
6028 separate_prolog
? 8 : 11;
6029 shader
->config
.spi_ps_input_ena
|=
6030 S_0286CC_LINEAR_CENTER_ENA(1);
6032 case TGSI_INTERPOLATE_LOC_CENTROID
:
6033 key
->ps_prolog
.color_interp_vgpr_index
[i
] =
6034 separate_prolog
? 10 : 13;
6035 shader
->config
.spi_ps_input_ena
|=
6036 S_0286CC_LINEAR_CENTROID_ENA(1);
6050 * Check whether a PS prolog is required based on the key.
6052 static bool si_need_ps_prolog(const union si_shader_part_key
*key
)
6054 return key
->ps_prolog
.colors_read
||
6055 key
->ps_prolog
.states
.force_persp_sample_interp
||
6056 key
->ps_prolog
.states
.force_linear_sample_interp
||
6057 key
->ps_prolog
.states
.force_persp_center_interp
||
6058 key
->ps_prolog
.states
.force_linear_center_interp
||
6059 key
->ps_prolog
.states
.bc_optimize_for_persp
||
6060 key
->ps_prolog
.states
.bc_optimize_for_linear
||
6061 key
->ps_prolog
.states
.poly_stipple
||
6062 key
->ps_prolog
.states
.samplemask_log_ps_iter
;
6066 * Compute the PS epilog key, which contains all the information needed to
6067 * build the PS epilog function.
6069 static void si_get_ps_epilog_key(struct si_shader
*shader
,
6070 union si_shader_part_key
*key
)
6072 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
6073 memset(key
, 0, sizeof(*key
));
6074 key
->ps_epilog
.colors_written
= info
->colors_written
;
6075 key
->ps_epilog
.writes_z
= info
->writes_z
;
6076 key
->ps_epilog
.writes_stencil
= info
->writes_stencil
;
6077 key
->ps_epilog
.writes_samplemask
= info
->writes_samplemask
;
6078 key
->ps_epilog
.states
= shader
->key
.part
.ps
.epilog
;
6082 * Build the GS prolog function. Rotate the input vertices for triangle strips
6085 static void si_build_gs_prolog_function(struct si_shader_context
*ctx
,
6086 union si_shader_part_key
*key
)
6088 unsigned num_sgprs
, num_vgprs
;
6089 struct si_function_info fninfo
;
6090 LLVMBuilderRef builder
= ctx
->ac
.builder
;
6091 LLVMTypeRef returns
[48];
6092 LLVMValueRef func
, ret
;
6094 si_init_function_info(&fninfo
);
6096 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
6097 num_sgprs
= 8 + GFX9_GS_NUM_USER_SGPR
;
6098 num_vgprs
= 5; /* ES inputs are not needed by GS */
6100 num_sgprs
= GFX6_GS_NUM_USER_SGPR
+ 2;
6104 for (unsigned i
= 0; i
< num_sgprs
; ++i
) {
6105 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
6106 returns
[i
] = ctx
->i32
;
6109 for (unsigned i
= 0; i
< num_vgprs
; ++i
) {
6110 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
6111 returns
[num_sgprs
+ i
] = ctx
->f32
;
6114 /* Create the function. */
6115 si_create_function(ctx
, "gs_prolog", returns
, num_sgprs
+ num_vgprs
,
6117 func
= ctx
->main_fn
;
6119 /* Set the full EXEC mask for the prolog, because we are only fiddling
6120 * with registers here. The main shader part will set the correct EXEC
6123 if (ctx
->screen
->info
.chip_class
>= GFX9
&& !key
->gs_prolog
.is_monolithic
)
6124 si_init_exec_full_mask(ctx
);
6126 /* Copy inputs to outputs. This should be no-op, as the registers match,
6127 * but it will prevent the compiler from overwriting them unintentionally.
6129 ret
= ctx
->return_value
;
6130 for (unsigned i
= 0; i
< num_sgprs
; i
++) {
6131 LLVMValueRef p
= LLVMGetParam(func
, i
);
6132 ret
= LLVMBuildInsertValue(builder
, ret
, p
, i
, "");
6134 for (unsigned i
= 0; i
< num_vgprs
; i
++) {
6135 LLVMValueRef p
= LLVMGetParam(func
, num_sgprs
+ i
);
6136 p
= ac_to_float(&ctx
->ac
, p
);
6137 ret
= LLVMBuildInsertValue(builder
, ret
, p
, num_sgprs
+ i
, "");
6140 if (key
->gs_prolog
.states
.tri_strip_adj_fix
) {
6141 /* Remap the input vertices for every other primitive. */
6142 const unsigned gfx6_vtx_params
[6] = {
6150 const unsigned gfx9_vtx_params
[3] = {
6155 LLVMValueRef vtx_in
[6], vtx_out
[6];
6156 LLVMValueRef prim_id
, rotate
;
6158 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
6159 for (unsigned i
= 0; i
< 3; i
++) {
6160 vtx_in
[i
*2] = unpack_param(ctx
, gfx9_vtx_params
[i
], 0, 16);
6161 vtx_in
[i
*2+1] = unpack_param(ctx
, gfx9_vtx_params
[i
], 16, 16);
6164 for (unsigned i
= 0; i
< 6; i
++)
6165 vtx_in
[i
] = LLVMGetParam(func
, gfx6_vtx_params
[i
]);
6168 prim_id
= LLVMGetParam(func
, num_sgprs
+ 2);
6169 rotate
= LLVMBuildTrunc(builder
, prim_id
, ctx
->i1
, "");
6171 for (unsigned i
= 0; i
< 6; ++i
) {
6172 LLVMValueRef base
, rotated
;
6174 rotated
= vtx_in
[(i
+ 4) % 6];
6175 vtx_out
[i
] = LLVMBuildSelect(builder
, rotate
, rotated
, base
, "");
6178 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
6179 for (unsigned i
= 0; i
< 3; i
++) {
6180 LLVMValueRef hi
, out
;
6182 hi
= LLVMBuildShl(builder
, vtx_out
[i
*2+1],
6183 LLVMConstInt(ctx
->i32
, 16, 0), "");
6184 out
= LLVMBuildOr(builder
, vtx_out
[i
*2], hi
, "");
6185 out
= ac_to_float(&ctx
->ac
, out
);
6186 ret
= LLVMBuildInsertValue(builder
, ret
, out
,
6187 gfx9_vtx_params
[i
], "");
6190 for (unsigned i
= 0; i
< 6; i
++) {
6193 out
= ac_to_float(&ctx
->ac
, vtx_out
[i
]);
6194 ret
= LLVMBuildInsertValue(builder
, ret
, out
,
6195 gfx6_vtx_params
[i
], "");
6200 LLVMBuildRet(builder
, ret
);
6204 * Given a list of shader part functions, build a wrapper function that
6205 * runs them in sequence to form a monolithic shader.
6207 static void si_build_wrapper_function(struct si_shader_context
*ctx
,
6208 LLVMValueRef
*parts
,
6211 unsigned next_shader_first_part
)
6213 LLVMBuilderRef builder
= ctx
->ac
.builder
;
6214 /* PS epilog has one arg per color component; gfx9 merged shader
6215 * prologs need to forward 32 user SGPRs.
6217 struct si_function_info fninfo
;
6218 LLVMValueRef initial
[64], out
[64];
6219 LLVMTypeRef function_type
;
6220 unsigned num_first_params
;
6221 unsigned num_out
, initial_num_out
;
6222 MAYBE_UNUSED
unsigned num_out_sgpr
; /* used in debug checks */
6223 MAYBE_UNUSED
unsigned initial_num_out_sgpr
; /* used in debug checks */
6224 unsigned num_sgprs
, num_vgprs
;
6226 struct lp_build_if_state if_state
;
6228 si_init_function_info(&fninfo
);
6230 for (unsigned i
= 0; i
< num_parts
; ++i
) {
6231 lp_add_function_attr(parts
[i
], -1, LP_FUNC_ATTR_ALWAYSINLINE
);
6232 LLVMSetLinkage(parts
[i
], LLVMPrivateLinkage
);
6235 /* The parameters of the wrapper function correspond to those of the
6236 * first part in terms of SGPRs and VGPRs, but we use the types of the
6237 * main part to get the right types. This is relevant for the
6238 * dereferenceable attribute on descriptor table pointers.
6243 function_type
= LLVMGetElementType(LLVMTypeOf(parts
[0]));
6244 num_first_params
= LLVMCountParamTypes(function_type
);
6246 for (unsigned i
= 0; i
< num_first_params
; ++i
) {
6247 LLVMValueRef param
= LLVMGetParam(parts
[0], i
);
6249 if (ac_is_sgpr_param(param
)) {
6250 assert(num_vgprs
== 0);
6251 num_sgprs
+= ac_get_type_size(LLVMTypeOf(param
)) / 4;
6253 num_vgprs
+= ac_get_type_size(LLVMTypeOf(param
)) / 4;
6258 while (gprs
< num_sgprs
+ num_vgprs
) {
6259 LLVMValueRef param
= LLVMGetParam(parts
[main_part
], fninfo
.num_params
);
6260 LLVMTypeRef type
= LLVMTypeOf(param
);
6261 unsigned size
= ac_get_type_size(type
) / 4;
6263 add_arg(&fninfo
, gprs
< num_sgprs
? ARG_SGPR
: ARG_VGPR
, type
);
6265 assert(ac_is_sgpr_param(param
) == (gprs
< num_sgprs
));
6266 assert(gprs
+ size
<= num_sgprs
+ num_vgprs
&&
6267 (gprs
>= num_sgprs
|| gprs
+ size
<= num_sgprs
));
6272 si_create_function(ctx
, "wrapper", NULL
, 0, &fninfo
,
6273 si_get_max_workgroup_size(ctx
->shader
));
6275 if (is_merged_shader(ctx
->shader
))
6276 si_init_exec_full_mask(ctx
);
6278 /* Record the arguments of the function as if they were an output of
6284 for (unsigned i
= 0; i
< fninfo
.num_params
; ++i
) {
6285 LLVMValueRef param
= LLVMGetParam(ctx
->main_fn
, i
);
6286 LLVMTypeRef param_type
= LLVMTypeOf(param
);
6287 LLVMTypeRef out_type
= i
< fninfo
.num_sgpr_params
? ctx
->i32
: ctx
->f32
;
6288 unsigned size
= ac_get_type_size(param_type
) / 4;
6291 if (param_type
!= out_type
)
6292 param
= LLVMBuildBitCast(builder
, param
, out_type
, "");
6293 out
[num_out
++] = param
;
6295 LLVMTypeRef vector_type
= LLVMVectorType(out_type
, size
);
6297 if (LLVMGetTypeKind(param_type
) == LLVMPointerTypeKind
) {
6298 param
= LLVMBuildPtrToInt(builder
, param
, ctx
->i64
, "");
6299 param_type
= ctx
->i64
;
6302 if (param_type
!= vector_type
)
6303 param
= LLVMBuildBitCast(builder
, param
, vector_type
, "");
6305 for (unsigned j
= 0; j
< size
; ++j
)
6306 out
[num_out
++] = LLVMBuildExtractElement(
6307 builder
, param
, LLVMConstInt(ctx
->i32
, j
, 0), "");
6310 if (i
< fninfo
.num_sgpr_params
)
6311 num_out_sgpr
= num_out
;
6314 memcpy(initial
, out
, sizeof(out
));
6315 initial_num_out
= num_out
;
6316 initial_num_out_sgpr
= num_out_sgpr
;
6318 /* Now chain the parts. */
6319 for (unsigned part
= 0; part
< num_parts
; ++part
) {
6320 LLVMValueRef in
[48];
6322 LLVMTypeRef ret_type
;
6323 unsigned out_idx
= 0;
6324 unsigned num_params
= LLVMCountParams(parts
[part
]);
6326 /* Merged shaders are executed conditionally depending
6327 * on the number of enabled threads passed in the input SGPRs. */
6328 if (is_merged_shader(ctx
->shader
) && part
== 0) {
6329 LLVMValueRef ena
, count
= initial
[3];
6331 count
= LLVMBuildAnd(builder
, count
,
6332 LLVMConstInt(ctx
->i32
, 0x7f, 0), "");
6333 ena
= LLVMBuildICmp(builder
, LLVMIntULT
,
6334 ac_get_thread_id(&ctx
->ac
), count
, "");
6335 lp_build_if(&if_state
, &ctx
->gallivm
, ena
);
6338 /* Derive arguments for the next part from outputs of the
6341 for (unsigned param_idx
= 0; param_idx
< num_params
; ++param_idx
) {
6343 LLVMTypeRef param_type
;
6345 unsigned param_size
;
6346 LLVMValueRef arg
= NULL
;
6348 param
= LLVMGetParam(parts
[part
], param_idx
);
6349 param_type
= LLVMTypeOf(param
);
6350 param_size
= ac_get_type_size(param_type
) / 4;
6351 is_sgpr
= ac_is_sgpr_param(param
);
6354 #if HAVE_LLVM < 0x0400
6355 LLVMRemoveAttribute(param
, LLVMByValAttribute
);
6357 unsigned kind_id
= LLVMGetEnumAttributeKindForName("byval", 5);
6358 LLVMRemoveEnumAttributeAtIndex(parts
[part
], param_idx
+ 1, kind_id
);
6360 lp_add_function_attr(parts
[part
], param_idx
+ 1, LP_FUNC_ATTR_INREG
);
6363 assert(out_idx
+ param_size
<= (is_sgpr
? num_out_sgpr
: num_out
));
6364 assert(is_sgpr
|| out_idx
>= num_out_sgpr
);
6366 if (param_size
== 1)
6369 arg
= lp_build_gather_values(&ctx
->gallivm
, &out
[out_idx
], param_size
);
6371 if (LLVMTypeOf(arg
) != param_type
) {
6372 if (LLVMGetTypeKind(param_type
) == LLVMPointerTypeKind
) {
6373 arg
= LLVMBuildBitCast(builder
, arg
, ctx
->i64
, "");
6374 arg
= LLVMBuildIntToPtr(builder
, arg
, param_type
, "");
6376 arg
= LLVMBuildBitCast(builder
, arg
, param_type
, "");
6380 in
[param_idx
] = arg
;
6381 out_idx
+= param_size
;
6384 ret
= LLVMBuildCall(builder
, parts
[part
], in
, num_params
, "");
6386 if (is_merged_shader(ctx
->shader
) &&
6387 part
+ 1 == next_shader_first_part
) {
6388 lp_build_endif(&if_state
);
6390 /* The second half of the merged shader should use
6391 * the inputs from the toplevel (wrapper) function,
6392 * not the return value from the last call.
6394 * That's because the last call was executed condi-
6395 * tionally, so we can't consume it in the main
6398 memcpy(out
, initial
, sizeof(initial
));
6399 num_out
= initial_num_out
;
6400 num_out_sgpr
= initial_num_out_sgpr
;
6404 /* Extract the returned GPRs. */
6405 ret_type
= LLVMTypeOf(ret
);
6409 if (LLVMGetTypeKind(ret_type
) != LLVMVoidTypeKind
) {
6410 assert(LLVMGetTypeKind(ret_type
) == LLVMStructTypeKind
);
6412 unsigned ret_size
= LLVMCountStructElementTypes(ret_type
);
6414 for (unsigned i
= 0; i
< ret_size
; ++i
) {
6416 LLVMBuildExtractValue(builder
, ret
, i
, "");
6418 assert(num_out
< ARRAY_SIZE(out
));
6419 out
[num_out
++] = val
;
6421 if (LLVMTypeOf(val
) == ctx
->i32
) {
6422 assert(num_out_sgpr
+ 1 == num_out
);
6423 num_out_sgpr
= num_out
;
6429 LLVMBuildRetVoid(builder
);
6432 int si_compile_tgsi_shader(struct si_screen
*sscreen
,
6433 LLVMTargetMachineRef tm
,
6434 struct si_shader
*shader
,
6436 struct pipe_debug_callback
*debug
)
6438 struct si_shader_selector
*sel
= shader
->selector
;
6439 struct si_shader_context ctx
;
6442 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6443 * conversion fails. */
6444 if (si_can_dump_shader(sscreen
, sel
->info
.processor
) &&
6445 !(sscreen
->debug_flags
& DBG(NO_TGSI
))) {
6447 tgsi_dump(sel
->tokens
, 0);
6449 nir_print_shader(sel
->nir
, stderr
);
6450 si_dump_streamout(&sel
->so
);
6453 si_init_shader_ctx(&ctx
, sscreen
, tm
);
6454 si_llvm_context_set_tgsi(&ctx
, shader
);
6455 ctx
.separate_prolog
= !is_monolithic
;
6457 memset(shader
->info
.vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
6458 sizeof(shader
->info
.vs_output_param_offset
));
6460 shader
->info
.uses_instanceid
= sel
->info
.uses_instanceid
;
6462 if (!si_compile_tgsi_main(&ctx
, is_monolithic
)) {
6463 si_llvm_dispose(&ctx
);
6467 if (is_monolithic
&& ctx
.type
== PIPE_SHADER_VERTEX
) {
6468 LLVMValueRef parts
[2];
6469 bool need_prolog
= sel
->vs_needs_prolog
;
6471 parts
[1] = ctx
.main_fn
;
6474 union si_shader_part_key prolog_key
;
6475 si_get_vs_prolog_key(&sel
->info
,
6476 shader
->info
.num_input_sgprs
,
6477 &shader
->key
.part
.vs
.prolog
,
6478 shader
, &prolog_key
);
6479 si_build_vs_prolog_function(&ctx
, &prolog_key
);
6480 parts
[0] = ctx
.main_fn
;
6483 si_build_wrapper_function(&ctx
, parts
+ !need_prolog
,
6484 1 + need_prolog
, need_prolog
, 0);
6485 } else if (is_monolithic
&& ctx
.type
== PIPE_SHADER_TESS_CTRL
) {
6486 if (sscreen
->info
.chip_class
>= GFX9
) {
6487 struct si_shader_selector
*ls
= shader
->key
.part
.tcs
.ls
;
6488 LLVMValueRef parts
[4];
6489 bool vs_needs_prolog
=
6490 si_vs_needs_prolog(ls
, &shader
->key
.part
.tcs
.ls_prolog
);
6493 parts
[2] = ctx
.main_fn
;
6496 union si_shader_part_key tcs_epilog_key
;
6497 memset(&tcs_epilog_key
, 0, sizeof(tcs_epilog_key
));
6498 tcs_epilog_key
.tcs_epilog
.states
= shader
->key
.part
.tcs
.epilog
;
6499 si_build_tcs_epilog_function(&ctx
, &tcs_epilog_key
);
6500 parts
[3] = ctx
.main_fn
;
6503 if (vs_needs_prolog
) {
6504 union si_shader_part_key vs_prolog_key
;
6505 si_get_vs_prolog_key(&ls
->info
,
6506 shader
->info
.num_input_sgprs
,
6507 &shader
->key
.part
.tcs
.ls_prolog
,
6508 shader
, &vs_prolog_key
);
6509 vs_prolog_key
.vs_prolog
.is_monolithic
= true;
6510 si_build_vs_prolog_function(&ctx
, &vs_prolog_key
);
6511 parts
[0] = ctx
.main_fn
;
6514 /* VS as LS main part */
6515 struct si_shader shader_ls
= {};
6516 shader_ls
.selector
= ls
;
6517 shader_ls
.key
.as_ls
= 1;
6518 shader_ls
.key
.mono
= shader
->key
.mono
;
6519 shader_ls
.key
.opt
= shader
->key
.opt
;
6520 si_llvm_context_set_tgsi(&ctx
, &shader_ls
);
6522 if (!si_compile_tgsi_main(&ctx
, true)) {
6523 si_llvm_dispose(&ctx
);
6526 shader
->info
.uses_instanceid
|= ls
->info
.uses_instanceid
;
6527 parts
[1] = ctx
.main_fn
;
6529 /* Reset the shader context. */
6530 ctx
.shader
= shader
;
6531 ctx
.type
= PIPE_SHADER_TESS_CTRL
;
6533 si_build_wrapper_function(&ctx
,
6534 parts
+ !vs_needs_prolog
,
6535 4 - !vs_needs_prolog
, 0,
6536 vs_needs_prolog
? 2 : 1);
6538 LLVMValueRef parts
[2];
6539 union si_shader_part_key epilog_key
;
6541 parts
[0] = ctx
.main_fn
;
6543 memset(&epilog_key
, 0, sizeof(epilog_key
));
6544 epilog_key
.tcs_epilog
.states
= shader
->key
.part
.tcs
.epilog
;
6545 si_build_tcs_epilog_function(&ctx
, &epilog_key
);
6546 parts
[1] = ctx
.main_fn
;
6548 si_build_wrapper_function(&ctx
, parts
, 2, 0, 0);
6550 } else if (is_monolithic
&& ctx
.type
== PIPE_SHADER_GEOMETRY
) {
6551 if (ctx
.screen
->info
.chip_class
>= GFX9
) {
6552 struct si_shader_selector
*es
= shader
->key
.part
.gs
.es
;
6553 LLVMValueRef es_prolog
= NULL
;
6554 LLVMValueRef es_main
= NULL
;
6555 LLVMValueRef gs_prolog
= NULL
;
6556 LLVMValueRef gs_main
= ctx
.main_fn
;
6559 union si_shader_part_key gs_prolog_key
;
6560 memset(&gs_prolog_key
, 0, sizeof(gs_prolog_key
));
6561 gs_prolog_key
.gs_prolog
.states
= shader
->key
.part
.gs
.prolog
;
6562 gs_prolog_key
.gs_prolog
.is_monolithic
= true;
6563 si_build_gs_prolog_function(&ctx
, &gs_prolog_key
);
6564 gs_prolog
= ctx
.main_fn
;
6567 if (es
->vs_needs_prolog
) {
6568 union si_shader_part_key vs_prolog_key
;
6569 si_get_vs_prolog_key(&es
->info
,
6570 shader
->info
.num_input_sgprs
,
6571 &shader
->key
.part
.gs
.vs_prolog
,
6572 shader
, &vs_prolog_key
);
6573 vs_prolog_key
.vs_prolog
.is_monolithic
= true;
6574 si_build_vs_prolog_function(&ctx
, &vs_prolog_key
);
6575 es_prolog
= ctx
.main_fn
;
6579 struct si_shader shader_es
= {};
6580 shader_es
.selector
= es
;
6581 shader_es
.key
.as_es
= 1;
6582 shader_es
.key
.mono
= shader
->key
.mono
;
6583 shader_es
.key
.opt
= shader
->key
.opt
;
6584 si_llvm_context_set_tgsi(&ctx
, &shader_es
);
6586 if (!si_compile_tgsi_main(&ctx
, true)) {
6587 si_llvm_dispose(&ctx
);
6590 shader
->info
.uses_instanceid
|= es
->info
.uses_instanceid
;
6591 es_main
= ctx
.main_fn
;
6593 /* Reset the shader context. */
6594 ctx
.shader
= shader
;
6595 ctx
.type
= PIPE_SHADER_GEOMETRY
;
6597 /* Prepare the array of shader parts. */
6598 LLVMValueRef parts
[4];
6599 unsigned num_parts
= 0, main_part
, next_first_part
;
6602 parts
[num_parts
++] = es_prolog
;
6604 parts
[main_part
= num_parts
++] = es_main
;
6605 parts
[next_first_part
= num_parts
++] = gs_prolog
;
6606 parts
[num_parts
++] = gs_main
;
6608 si_build_wrapper_function(&ctx
, parts
, num_parts
,
6609 main_part
, next_first_part
);
6611 LLVMValueRef parts
[2];
6612 union si_shader_part_key prolog_key
;
6614 parts
[1] = ctx
.main_fn
;
6616 memset(&prolog_key
, 0, sizeof(prolog_key
));
6617 prolog_key
.gs_prolog
.states
= shader
->key
.part
.gs
.prolog
;
6618 si_build_gs_prolog_function(&ctx
, &prolog_key
);
6619 parts
[0] = ctx
.main_fn
;
6621 si_build_wrapper_function(&ctx
, parts
, 2, 1, 0);
6623 } else if (is_monolithic
&& ctx
.type
== PIPE_SHADER_FRAGMENT
) {
6624 LLVMValueRef parts
[3];
6625 union si_shader_part_key prolog_key
;
6626 union si_shader_part_key epilog_key
;
6629 si_get_ps_prolog_key(shader
, &prolog_key
, false);
6630 need_prolog
= si_need_ps_prolog(&prolog_key
);
6632 parts
[need_prolog
? 1 : 0] = ctx
.main_fn
;
6635 si_build_ps_prolog_function(&ctx
, &prolog_key
);
6636 parts
[0] = ctx
.main_fn
;
6639 si_get_ps_epilog_key(shader
, &epilog_key
);
6640 si_build_ps_epilog_function(&ctx
, &epilog_key
);
6641 parts
[need_prolog
? 2 : 1] = ctx
.main_fn
;
6643 si_build_wrapper_function(&ctx
, parts
, need_prolog
? 3 : 2,
6644 need_prolog
? 1 : 0, 0);
6647 si_llvm_optimize_module(&ctx
);
6649 /* Post-optimization transformations and analysis. */
6650 si_optimize_vs_outputs(&ctx
);
6652 if ((debug
&& debug
->debug_message
) ||
6653 si_can_dump_shader(sscreen
, ctx
.type
))
6654 si_count_scratch_private_memory(&ctx
);
6656 /* Compile to bytecode. */
6657 r
= si_compile_llvm(sscreen
, &shader
->binary
, &shader
->config
, tm
,
6658 ctx
.gallivm
.module
, debug
, ctx
.type
, "TGSI shader");
6659 si_llvm_dispose(&ctx
);
6661 fprintf(stderr
, "LLVM failed to compile shader\n");
6665 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6666 * LLVM 3.9svn has this bug.
6668 if (sel
->type
== PIPE_SHADER_COMPUTE
) {
6669 unsigned wave_size
= 64;
6670 unsigned max_vgprs
= 256;
6671 unsigned max_sgprs
= sscreen
->info
.chip_class
>= VI
? 800 : 512;
6672 unsigned max_sgprs_per_wave
= 128;
6673 unsigned max_block_threads
= si_get_max_workgroup_size(shader
);
6674 unsigned min_waves_per_cu
= DIV_ROUND_UP(max_block_threads
, wave_size
);
6675 unsigned min_waves_per_simd
= DIV_ROUND_UP(min_waves_per_cu
, 4);
6677 max_vgprs
= max_vgprs
/ min_waves_per_simd
;
6678 max_sgprs
= MIN2(max_sgprs
/ min_waves_per_simd
, max_sgprs_per_wave
);
6680 if (shader
->config
.num_sgprs
> max_sgprs
||
6681 shader
->config
.num_vgprs
> max_vgprs
) {
6682 fprintf(stderr
, "LLVM failed to compile a shader correctly: "
6683 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6684 shader
->config
.num_sgprs
, shader
->config
.num_vgprs
,
6685 max_sgprs
, max_vgprs
);
6687 /* Just terminate the process, because dependent
6688 * shaders can hang due to bad input data, but use
6689 * the env var to allow shader-db to work.
6691 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6696 /* Add the scratch offset to input SGPRs. */
6697 if (shader
->config
.scratch_bytes_per_wave
&& !is_merged_shader(shader
))
6698 shader
->info
.num_input_sgprs
+= 1; /* scratch byte offset */
6700 /* Calculate the number of fragment input VGPRs. */
6701 if (ctx
.type
== PIPE_SHADER_FRAGMENT
) {
6702 shader
->info
.num_input_vgprs
= 0;
6703 shader
->info
.face_vgpr_index
= -1;
6704 shader
->info
.ancillary_vgpr_index
= -1;
6706 if (G_0286CC_PERSP_SAMPLE_ENA(shader
->config
.spi_ps_input_addr
))
6707 shader
->info
.num_input_vgprs
+= 2;
6708 if (G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_addr
))
6709 shader
->info
.num_input_vgprs
+= 2;
6710 if (G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_addr
))
6711 shader
->info
.num_input_vgprs
+= 2;
6712 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader
->config
.spi_ps_input_addr
))
6713 shader
->info
.num_input_vgprs
+= 3;
6714 if (G_0286CC_LINEAR_SAMPLE_ENA(shader
->config
.spi_ps_input_addr
))
6715 shader
->info
.num_input_vgprs
+= 2;
6716 if (G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_addr
))
6717 shader
->info
.num_input_vgprs
+= 2;
6718 if (G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_addr
))
6719 shader
->info
.num_input_vgprs
+= 2;
6720 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader
->config
.spi_ps_input_addr
))
6721 shader
->info
.num_input_vgprs
+= 1;
6722 if (G_0286CC_POS_X_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
6723 shader
->info
.num_input_vgprs
+= 1;
6724 if (G_0286CC_POS_Y_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
6725 shader
->info
.num_input_vgprs
+= 1;
6726 if (G_0286CC_POS_Z_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
6727 shader
->info
.num_input_vgprs
+= 1;
6728 if (G_0286CC_POS_W_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
6729 shader
->info
.num_input_vgprs
+= 1;
6730 if (G_0286CC_FRONT_FACE_ENA(shader
->config
.spi_ps_input_addr
)) {
6731 shader
->info
.face_vgpr_index
= shader
->info
.num_input_vgprs
;
6732 shader
->info
.num_input_vgprs
+= 1;
6734 if (G_0286CC_ANCILLARY_ENA(shader
->config
.spi_ps_input_addr
)) {
6735 shader
->info
.ancillary_vgpr_index
= shader
->info
.num_input_vgprs
;
6736 shader
->info
.num_input_vgprs
+= 1;
6738 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader
->config
.spi_ps_input_addr
))
6739 shader
->info
.num_input_vgprs
+= 1;
6740 if (G_0286CC_POS_FIXED_PT_ENA(shader
->config
.spi_ps_input_addr
))
6741 shader
->info
.num_input_vgprs
+= 1;
6748 * Create, compile and return a shader part (prolog or epilog).
6750 * \param sscreen screen
6751 * \param list list of shader parts of the same category
6752 * \param type shader type
6753 * \param key shader part key
6754 * \param prolog whether the part being requested is a prolog
6755 * \param tm LLVM target machine
6756 * \param debug debug callback
6757 * \param build the callback responsible for building the main function
6758 * \return non-NULL on success
6760 static struct si_shader_part
*
6761 si_get_shader_part(struct si_screen
*sscreen
,
6762 struct si_shader_part
**list
,
6763 enum pipe_shader_type type
,
6765 union si_shader_part_key
*key
,
6766 LLVMTargetMachineRef tm
,
6767 struct pipe_debug_callback
*debug
,
6768 void (*build
)(struct si_shader_context
*,
6769 union si_shader_part_key
*),
6772 struct si_shader_part
*result
;
6774 mtx_lock(&sscreen
->shader_parts_mutex
);
6776 /* Find existing. */
6777 for (result
= *list
; result
; result
= result
->next
) {
6778 if (memcmp(&result
->key
, key
, sizeof(*key
)) == 0) {
6779 mtx_unlock(&sscreen
->shader_parts_mutex
);
6784 /* Compile a new one. */
6785 result
= CALLOC_STRUCT(si_shader_part
);
6788 struct si_shader shader
= {};
6789 struct si_shader_context ctx
;
6791 si_init_shader_ctx(&ctx
, sscreen
, tm
);
6792 ctx
.shader
= &shader
;
6796 case PIPE_SHADER_VERTEX
:
6797 shader
.key
.as_ls
= key
->vs_prolog
.as_ls
;
6798 shader
.key
.as_es
= key
->vs_prolog
.as_es
;
6800 case PIPE_SHADER_TESS_CTRL
:
6802 shader
.key
.part
.tcs
.epilog
= key
->tcs_epilog
.states
;
6804 case PIPE_SHADER_GEOMETRY
:
6807 case PIPE_SHADER_FRAGMENT
:
6809 shader
.key
.part
.ps
.prolog
= key
->ps_prolog
.states
;
6811 shader
.key
.part
.ps
.epilog
= key
->ps_epilog
.states
;
6814 unreachable("bad shader part");
6820 si_llvm_optimize_module(&ctx
);
6822 if (si_compile_llvm(sscreen
, &result
->binary
, &result
->config
, tm
,
6823 ctx
.ac
.module
, debug
, ctx
.type
, name
)) {
6829 result
->next
= *list
;
6833 si_llvm_dispose(&ctx
);
6834 mtx_unlock(&sscreen
->shader_parts_mutex
);
6838 static LLVMValueRef
si_prolog_get_rw_buffers(struct si_shader_context
*ctx
)
6840 LLVMValueRef ptr
[2], list
;
6841 bool is_merged_shader
=
6842 ctx
->screen
->info
.chip_class
>= GFX9
&&
6843 (ctx
->type
== PIPE_SHADER_TESS_CTRL
||
6844 ctx
->type
== PIPE_SHADER_GEOMETRY
||
6845 ctx
->shader
->key
.as_ls
|| ctx
->shader
->key
.as_es
);
6847 /* Get the pointer to rw buffers. */
6848 ptr
[0] = LLVMGetParam(ctx
->main_fn
, (is_merged_shader
? 8 : 0) + SI_SGPR_RW_BUFFERS
);
6849 ptr
[1] = LLVMGetParam(ctx
->main_fn
, (is_merged_shader
? 8 : 0) + SI_SGPR_RW_BUFFERS_HI
);
6850 list
= lp_build_gather_values(&ctx
->gallivm
, ptr
, 2);
6851 list
= LLVMBuildBitCast(ctx
->ac
.builder
, list
, ctx
->i64
, "");
6852 list
= LLVMBuildIntToPtr(ctx
->ac
.builder
, list
,
6853 si_const_array(ctx
->v4i32
, SI_NUM_RW_BUFFERS
), "");
6858 * Build the vertex shader prolog function.
6860 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6861 * All inputs are returned unmodified. The vertex load indices are
6862 * stored after them, which will be used by the API VS for fetching inputs.
6864 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6869 * (VertexID + BaseVertex),
6870 * (InstanceID + StartInstance),
6871 * (InstanceID / 2 + StartInstance)
6873 static void si_build_vs_prolog_function(struct si_shader_context
*ctx
,
6874 union si_shader_part_key
*key
)
6876 struct si_function_info fninfo
;
6877 LLVMTypeRef
*returns
;
6878 LLVMValueRef ret
, func
;
6880 unsigned first_vs_vgpr
= key
->vs_prolog
.num_merged_next_stage_vgprs
;
6881 unsigned num_input_vgprs
= key
->vs_prolog
.num_merged_next_stage_vgprs
+ 4;
6882 LLVMValueRef input_vgprs
[9];
6883 unsigned num_all_input_regs
= key
->vs_prolog
.num_input_sgprs
+
6885 unsigned user_sgpr_base
= key
->vs_prolog
.num_merged_next_stage_vgprs
? 8 : 0;
6887 si_init_function_info(&fninfo
);
6889 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6890 returns
= alloca((num_all_input_regs
+ key
->vs_prolog
.last_input
+ 1) *
6891 sizeof(LLVMTypeRef
));
6894 /* Declare input and output SGPRs. */
6895 for (i
= 0; i
< key
->vs_prolog
.num_input_sgprs
; i
++) {
6896 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
6897 returns
[num_returns
++] = ctx
->i32
;
6900 /* Preloaded VGPRs (outputs must be floats) */
6901 for (i
= 0; i
< num_input_vgprs
; i
++) {
6902 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &input_vgprs
[i
]);
6903 returns
[num_returns
++] = ctx
->f32
;
6906 /* Vertex load indices. */
6907 for (i
= 0; i
<= key
->vs_prolog
.last_input
; i
++)
6908 returns
[num_returns
++] = ctx
->f32
;
6910 /* Create the function. */
6911 si_create_function(ctx
, "vs_prolog", returns
, num_returns
, &fninfo
, 0);
6912 func
= ctx
->main_fn
;
6914 if (key
->vs_prolog
.num_merged_next_stage_vgprs
) {
6915 if (!key
->vs_prolog
.is_monolithic
)
6916 si_init_exec_from_input(ctx
, 3, 0);
6918 if (key
->vs_prolog
.as_ls
&&
6919 ctx
->screen
->has_ls_vgpr_init_bug
) {
6920 /* If there are no HS threads, SPI loads the LS VGPRs
6921 * starting at VGPR 0. Shift them back to where they
6924 LLVMValueRef has_hs_threads
=
6925 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
,
6926 unpack_param(ctx
, 3, 8, 8),
6929 for (i
= 4; i
> 0; --i
) {
6930 input_vgprs
[i
+ 1] =
6931 LLVMBuildSelect(ctx
->ac
.builder
, has_hs_threads
,
6933 input_vgprs
[i
- 1], "");
6938 ctx
->abi
.vertex_id
= input_vgprs
[first_vs_vgpr
];
6939 ctx
->abi
.instance_id
= input_vgprs
[first_vs_vgpr
+ (key
->vs_prolog
.as_ls
? 2 : 1)];
6941 /* Copy inputs to outputs. This should be no-op, as the registers match,
6942 * but it will prevent the compiler from overwriting them unintentionally.
6944 ret
= ctx
->return_value
;
6945 for (i
= 0; i
< key
->vs_prolog
.num_input_sgprs
; i
++) {
6946 LLVMValueRef p
= LLVMGetParam(func
, i
);
6947 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, p
, i
, "");
6949 for (i
= 0; i
< num_input_vgprs
; i
++) {
6950 LLVMValueRef p
= input_vgprs
[i
];
6951 p
= ac_to_float(&ctx
->ac
, p
);
6952 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, p
,
6953 key
->vs_prolog
.num_input_sgprs
+ i
, "");
6956 /* Compute vertex load indices from instance divisors. */
6957 LLVMValueRef instance_divisor_constbuf
= NULL
;
6959 if (key
->vs_prolog
.states
.instance_divisor_is_fetched
) {
6960 LLVMValueRef list
= si_prolog_get_rw_buffers(ctx
);
6961 LLVMValueRef buf_index
=
6962 LLVMConstInt(ctx
->i32
, SI_VS_CONST_INSTANCE_DIVISORS
, 0);
6963 instance_divisor_constbuf
=
6964 ac_build_load_to_sgpr(&ctx
->ac
, list
, buf_index
);
6967 for (i
= 0; i
<= key
->vs_prolog
.last_input
; i
++) {
6968 bool divisor_is_one
=
6969 key
->vs_prolog
.states
.instance_divisor_is_one
& (1u << i
);
6970 bool divisor_is_fetched
=
6971 key
->vs_prolog
.states
.instance_divisor_is_fetched
& (1u << i
);
6974 if (divisor_is_one
|| divisor_is_fetched
) {
6975 LLVMValueRef divisor
= ctx
->i32_1
;
6977 if (divisor_is_fetched
) {
6978 divisor
= buffer_load_const(ctx
, instance_divisor_constbuf
,
6979 LLVMConstInt(ctx
->i32
, i
* 4, 0));
6980 divisor
= ac_to_integer(&ctx
->ac
, divisor
);
6983 /* InstanceID / Divisor + StartInstance */
6984 index
= get_instance_index_for_fetch(ctx
,
6986 SI_SGPR_START_INSTANCE
,
6989 /* VertexID + BaseVertex */
6990 index
= LLVMBuildAdd(ctx
->ac
.builder
,
6992 LLVMGetParam(func
, user_sgpr_base
+
6993 SI_SGPR_BASE_VERTEX
), "");
6996 index
= ac_to_float(&ctx
->ac
, index
);
6997 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, index
,
6998 fninfo
.num_params
+ i
, "");
7001 si_llvm_build_ret(ctx
, ret
);
7004 static bool si_get_vs_prolog(struct si_screen
*sscreen
,
7005 LLVMTargetMachineRef tm
,
7006 struct si_shader
*shader
,
7007 struct pipe_debug_callback
*debug
,
7008 struct si_shader
*main_part
,
7009 const struct si_vs_prolog_bits
*key
)
7011 struct si_shader_selector
*vs
= main_part
->selector
;
7013 if (!si_vs_needs_prolog(vs
, key
))
7016 /* Get the prolog. */
7017 union si_shader_part_key prolog_key
;
7018 si_get_vs_prolog_key(&vs
->info
, main_part
->info
.num_input_sgprs
,
7019 key
, shader
, &prolog_key
);
7022 si_get_shader_part(sscreen
, &sscreen
->vs_prologs
,
7023 PIPE_SHADER_VERTEX
, true, &prolog_key
, tm
,
7024 debug
, si_build_vs_prolog_function
,
7025 "Vertex Shader Prolog");
7026 return shader
->prolog
!= NULL
;
7030 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7032 static bool si_shader_select_vs_parts(struct si_screen
*sscreen
,
7033 LLVMTargetMachineRef tm
,
7034 struct si_shader
*shader
,
7035 struct pipe_debug_callback
*debug
)
7037 return si_get_vs_prolog(sscreen
, tm
, shader
, debug
, shader
,
7038 &shader
->key
.part
.vs
.prolog
);
7042 * Compile the TCS epilog function. This writes tesselation factors to memory
7043 * based on the output primitive type of the tesselator (determined by TES).
7045 static void si_build_tcs_epilog_function(struct si_shader_context
*ctx
,
7046 union si_shader_part_key
*key
)
7048 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
7049 struct si_function_info fninfo
;
7052 si_init_function_info(&fninfo
);
7054 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
7055 add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7056 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7057 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* wave info */
7058 ctx
->param_tcs_factor_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7059 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7060 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7061 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7062 add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7063 add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7064 add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7065 add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7066 add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7067 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7068 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7069 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7070 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7071 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7072 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7073 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7074 ctx
->param_tcs_offchip_addr_base64k
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7075 ctx
->param_tcs_factor_addr_base64k
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7077 add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7078 add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7079 add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7080 add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7081 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7082 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7083 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7084 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7085 ctx
->param_tcs_offchip_addr_base64k
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7086 ctx
->param_tcs_factor_addr_base64k
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7087 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7088 ctx
->param_tcs_factor_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7091 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* VGPR gap */
7092 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* VGPR gap */
7093 unsigned tess_factors_idx
=
7094 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* patch index within the wave (REL_PATCH_ID) */
7095 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* invocation ID within the patch */
7096 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* LDS offset where tess factors should be loaded from */
7098 for (unsigned i
= 0; i
< 6; i
++)
7099 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* tess factors */
7101 /* Create the function. */
7102 si_create_function(ctx
, "tcs_epilog", NULL
, 0, &fninfo
,
7103 ctx
->screen
->info
.chip_class
>= CIK
? 128 : 64);
7104 ac_declare_lds_as_pointer(&ctx
->ac
);
7105 func
= ctx
->main_fn
;
7107 LLVMValueRef invoc0_tess_factors
[6];
7108 for (unsigned i
= 0; i
< 6; i
++)
7109 invoc0_tess_factors
[i
] = LLVMGetParam(func
, tess_factors_idx
+ 3 + i
);
7111 si_write_tess_factors(bld_base
,
7112 LLVMGetParam(func
, tess_factors_idx
),
7113 LLVMGetParam(func
, tess_factors_idx
+ 1),
7114 LLVMGetParam(func
, tess_factors_idx
+ 2),
7115 invoc0_tess_factors
, invoc0_tess_factors
+ 4);
7117 LLVMBuildRetVoid(ctx
->ac
.builder
);
7121 * Select and compile (or reuse) TCS parts (epilog).
7123 static bool si_shader_select_tcs_parts(struct si_screen
*sscreen
,
7124 LLVMTargetMachineRef tm
,
7125 struct si_shader
*shader
,
7126 struct pipe_debug_callback
*debug
)
7128 if (sscreen
->info
.chip_class
>= GFX9
) {
7129 struct si_shader
*ls_main_part
=
7130 shader
->key
.part
.tcs
.ls
->main_shader_part_ls
;
7132 if (!si_get_vs_prolog(sscreen
, tm
, shader
, debug
, ls_main_part
,
7133 &shader
->key
.part
.tcs
.ls_prolog
))
7136 shader
->previous_stage
= ls_main_part
;
7139 /* Get the epilog. */
7140 union si_shader_part_key epilog_key
;
7141 memset(&epilog_key
, 0, sizeof(epilog_key
));
7142 epilog_key
.tcs_epilog
.states
= shader
->key
.part
.tcs
.epilog
;
7144 shader
->epilog
= si_get_shader_part(sscreen
, &sscreen
->tcs_epilogs
,
7145 PIPE_SHADER_TESS_CTRL
, false,
7146 &epilog_key
, tm
, debug
,
7147 si_build_tcs_epilog_function
,
7148 "Tessellation Control Shader Epilog");
7149 return shader
->epilog
!= NULL
;
7153 * Select and compile (or reuse) GS parts (prolog).
7155 static bool si_shader_select_gs_parts(struct si_screen
*sscreen
,
7156 LLVMTargetMachineRef tm
,
7157 struct si_shader
*shader
,
7158 struct pipe_debug_callback
*debug
)
7160 if (sscreen
->info
.chip_class
>= GFX9
) {
7161 struct si_shader
*es_main_part
=
7162 shader
->key
.part
.gs
.es
->main_shader_part_es
;
7164 if (shader
->key
.part
.gs
.es
->type
== PIPE_SHADER_VERTEX
&&
7165 !si_get_vs_prolog(sscreen
, tm
, shader
, debug
, es_main_part
,
7166 &shader
->key
.part
.gs
.vs_prolog
))
7169 shader
->previous_stage
= es_main_part
;
7172 if (!shader
->key
.part
.gs
.prolog
.tri_strip_adj_fix
)
7175 union si_shader_part_key prolog_key
;
7176 memset(&prolog_key
, 0, sizeof(prolog_key
));
7177 prolog_key
.gs_prolog
.states
= shader
->key
.part
.gs
.prolog
;
7179 shader
->prolog2
= si_get_shader_part(sscreen
, &sscreen
->gs_prologs
,
7180 PIPE_SHADER_GEOMETRY
, true,
7181 &prolog_key
, tm
, debug
,
7182 si_build_gs_prolog_function
,
7183 "Geometry Shader Prolog");
7184 return shader
->prolog2
!= NULL
;
7188 * Build the pixel shader prolog function. This handles:
7189 * - two-side color selection and interpolation
7190 * - overriding interpolation parameters for the API PS
7191 * - polygon stippling
7193 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7194 * overriden by other states. (e.g. per-sample interpolation)
7195 * Interpolated colors are stored after the preloaded VGPRs.
7197 static void si_build_ps_prolog_function(struct si_shader_context
*ctx
,
7198 union si_shader_part_key
*key
)
7200 struct si_function_info fninfo
;
7201 LLVMValueRef ret
, func
;
7202 int num_returns
, i
, num_color_channels
;
7204 assert(si_need_ps_prolog(key
));
7206 si_init_function_info(&fninfo
);
7208 /* Declare inputs. */
7209 for (i
= 0; i
< key
->ps_prolog
.num_input_sgprs
; i
++)
7210 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7212 for (i
= 0; i
< key
->ps_prolog
.num_input_vgprs
; i
++)
7213 add_arg(&fninfo
, ARG_VGPR
, ctx
->f32
);
7215 /* Declare outputs (same as inputs + add colors if needed) */
7216 num_returns
= fninfo
.num_params
;
7217 num_color_channels
= util_bitcount(key
->ps_prolog
.colors_read
);
7218 for (i
= 0; i
< num_color_channels
; i
++)
7219 fninfo
.types
[num_returns
++] = ctx
->f32
;
7221 /* Create the function. */
7222 si_create_function(ctx
, "ps_prolog", fninfo
.types
, num_returns
,
7224 func
= ctx
->main_fn
;
7226 /* Copy inputs to outputs. This should be no-op, as the registers match,
7227 * but it will prevent the compiler from overwriting them unintentionally.
7229 ret
= ctx
->return_value
;
7230 for (i
= 0; i
< fninfo
.num_params
; i
++) {
7231 LLVMValueRef p
= LLVMGetParam(func
, i
);
7232 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, p
, i
, "");
7235 /* Polygon stippling. */
7236 if (key
->ps_prolog
.states
.poly_stipple
) {
7237 /* POS_FIXED_PT is always last. */
7238 unsigned pos
= key
->ps_prolog
.num_input_sgprs
+
7239 key
->ps_prolog
.num_input_vgprs
- 1;
7240 LLVMValueRef list
= si_prolog_get_rw_buffers(ctx
);
7242 si_llvm_emit_polygon_stipple(ctx
, list
, pos
);
7245 if (key
->ps_prolog
.states
.bc_optimize_for_persp
||
7246 key
->ps_prolog
.states
.bc_optimize_for_linear
) {
7247 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7248 LLVMValueRef center
[2], centroid
[2], tmp
, bc_optimize
;
7250 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7251 * The hw doesn't compute CENTROID if the whole wave only
7252 * contains fully-covered quads.
7254 * PRIM_MASK is after user SGPRs.
7256 bc_optimize
= LLVMGetParam(func
, SI_PS_NUM_USER_SGPR
);
7257 bc_optimize
= LLVMBuildLShr(ctx
->ac
.builder
, bc_optimize
,
7258 LLVMConstInt(ctx
->i32
, 31, 0), "");
7259 bc_optimize
= LLVMBuildTrunc(ctx
->ac
.builder
, bc_optimize
,
7262 if (key
->ps_prolog
.states
.bc_optimize_for_persp
) {
7263 /* Read PERSP_CENTER. */
7264 for (i
= 0; i
< 2; i
++)
7265 center
[i
] = LLVMGetParam(func
, base
+ 2 + i
);
7266 /* Read PERSP_CENTROID. */
7267 for (i
= 0; i
< 2; i
++)
7268 centroid
[i
] = LLVMGetParam(func
, base
+ 4 + i
);
7269 /* Select PERSP_CENTROID. */
7270 for (i
= 0; i
< 2; i
++) {
7271 tmp
= LLVMBuildSelect(ctx
->ac
.builder
, bc_optimize
,
7272 center
[i
], centroid
[i
], "");
7273 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7274 tmp
, base
+ 4 + i
, "");
7277 if (key
->ps_prolog
.states
.bc_optimize_for_linear
) {
7278 /* Read LINEAR_CENTER. */
7279 for (i
= 0; i
< 2; i
++)
7280 center
[i
] = LLVMGetParam(func
, base
+ 8 + i
);
7281 /* Read LINEAR_CENTROID. */
7282 for (i
= 0; i
< 2; i
++)
7283 centroid
[i
] = LLVMGetParam(func
, base
+ 10 + i
);
7284 /* Select LINEAR_CENTROID. */
7285 for (i
= 0; i
< 2; i
++) {
7286 tmp
= LLVMBuildSelect(ctx
->ac
.builder
, bc_optimize
,
7287 center
[i
], centroid
[i
], "");
7288 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7289 tmp
, base
+ 10 + i
, "");
7294 /* Force per-sample interpolation. */
7295 if (key
->ps_prolog
.states
.force_persp_sample_interp
) {
7296 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7297 LLVMValueRef persp_sample
[2];
7299 /* Read PERSP_SAMPLE. */
7300 for (i
= 0; i
< 2; i
++)
7301 persp_sample
[i
] = LLVMGetParam(func
, base
+ i
);
7302 /* Overwrite PERSP_CENTER. */
7303 for (i
= 0; i
< 2; i
++)
7304 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7305 persp_sample
[i
], base
+ 2 + i
, "");
7306 /* Overwrite PERSP_CENTROID. */
7307 for (i
= 0; i
< 2; i
++)
7308 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7309 persp_sample
[i
], base
+ 4 + i
, "");
7311 if (key
->ps_prolog
.states
.force_linear_sample_interp
) {
7312 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7313 LLVMValueRef linear_sample
[2];
7315 /* Read LINEAR_SAMPLE. */
7316 for (i
= 0; i
< 2; i
++)
7317 linear_sample
[i
] = LLVMGetParam(func
, base
+ 6 + i
);
7318 /* Overwrite LINEAR_CENTER. */
7319 for (i
= 0; i
< 2; i
++)
7320 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7321 linear_sample
[i
], base
+ 8 + i
, "");
7322 /* Overwrite LINEAR_CENTROID. */
7323 for (i
= 0; i
< 2; i
++)
7324 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7325 linear_sample
[i
], base
+ 10 + i
, "");
7328 /* Force center interpolation. */
7329 if (key
->ps_prolog
.states
.force_persp_center_interp
) {
7330 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7331 LLVMValueRef persp_center
[2];
7333 /* Read PERSP_CENTER. */
7334 for (i
= 0; i
< 2; i
++)
7335 persp_center
[i
] = LLVMGetParam(func
, base
+ 2 + i
);
7336 /* Overwrite PERSP_SAMPLE. */
7337 for (i
= 0; i
< 2; i
++)
7338 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7339 persp_center
[i
], base
+ i
, "");
7340 /* Overwrite PERSP_CENTROID. */
7341 for (i
= 0; i
< 2; i
++)
7342 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7343 persp_center
[i
], base
+ 4 + i
, "");
7345 if (key
->ps_prolog
.states
.force_linear_center_interp
) {
7346 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7347 LLVMValueRef linear_center
[2];
7349 /* Read LINEAR_CENTER. */
7350 for (i
= 0; i
< 2; i
++)
7351 linear_center
[i
] = LLVMGetParam(func
, base
+ 8 + i
);
7352 /* Overwrite LINEAR_SAMPLE. */
7353 for (i
= 0; i
< 2; i
++)
7354 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7355 linear_center
[i
], base
+ 6 + i
, "");
7356 /* Overwrite LINEAR_CENTROID. */
7357 for (i
= 0; i
< 2; i
++)
7358 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7359 linear_center
[i
], base
+ 10 + i
, "");
7362 /* Interpolate colors. */
7363 unsigned color_out_idx
= 0;
7364 for (i
= 0; i
< 2; i
++) {
7365 unsigned writemask
= (key
->ps_prolog
.colors_read
>> (i
* 4)) & 0xf;
7366 unsigned face_vgpr
= key
->ps_prolog
.num_input_sgprs
+
7367 key
->ps_prolog
.face_vgpr_index
;
7368 LLVMValueRef interp
[2], color
[4];
7369 LLVMValueRef interp_ij
= NULL
, prim_mask
= NULL
, face
= NULL
;
7374 /* If the interpolation qualifier is not CONSTANT (-1). */
7375 if (key
->ps_prolog
.color_interp_vgpr_index
[i
] != -1) {
7376 unsigned interp_vgpr
= key
->ps_prolog
.num_input_sgprs
+
7377 key
->ps_prolog
.color_interp_vgpr_index
[i
];
7379 /* Get the (i,j) updated by bc_optimize handling. */
7380 interp
[0] = LLVMBuildExtractValue(ctx
->ac
.builder
, ret
,
7382 interp
[1] = LLVMBuildExtractValue(ctx
->ac
.builder
, ret
,
7383 interp_vgpr
+ 1, "");
7384 interp_ij
= lp_build_gather_values(&ctx
->gallivm
, interp
, 2);
7387 /* Use the absolute location of the input. */
7388 prim_mask
= LLVMGetParam(func
, SI_PS_NUM_USER_SGPR
);
7390 if (key
->ps_prolog
.states
.color_two_side
) {
7391 face
= LLVMGetParam(func
, face_vgpr
);
7392 face
= ac_to_integer(&ctx
->ac
, face
);
7395 interp_fs_input(ctx
,
7396 key
->ps_prolog
.color_attr_index
[i
],
7397 TGSI_SEMANTIC_COLOR
, i
,
7398 key
->ps_prolog
.num_interp_inputs
,
7399 key
->ps_prolog
.colors_read
, interp_ij
,
7400 prim_mask
, face
, color
);
7403 unsigned chan
= u_bit_scan(&writemask
);
7404 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, color
[chan
],
7405 fninfo
.num_params
+ color_out_idx
++, "");
7409 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7412 * "When per-sample shading is active due to the use of a fragment
7413 * input qualified by sample or due to the use of the gl_SampleID
7414 * or gl_SamplePosition variables, only the bit for the current
7415 * sample is set in gl_SampleMaskIn. When state specifies multiple
7416 * fragment shader invocations for a given fragment, the sample
7417 * mask for any single fragment shader invocation may specify a
7418 * subset of the covered samples for the fragment. In this case,
7419 * the bit corresponding to each covered sample will be set in
7420 * exactly one fragment shader invocation."
7422 * The samplemask loaded by hardware is always the coverage of the
7423 * entire pixel/fragment, so mask bits out based on the sample ID.
7425 if (key
->ps_prolog
.states
.samplemask_log_ps_iter
) {
7426 /* The bit pattern matches that used by fixed function fragment
7428 static const uint16_t ps_iter_masks
[] = {
7429 0xffff, /* not used */
7435 assert(key
->ps_prolog
.states
.samplemask_log_ps_iter
< ARRAY_SIZE(ps_iter_masks
));
7437 uint32_t ps_iter_mask
= ps_iter_masks
[key
->ps_prolog
.states
.samplemask_log_ps_iter
];
7438 unsigned ancillary_vgpr
= key
->ps_prolog
.num_input_sgprs
+
7439 key
->ps_prolog
.ancillary_vgpr_index
;
7440 LLVMValueRef sampleid
= unpack_param(ctx
, ancillary_vgpr
, 8, 4);
7441 LLVMValueRef samplemask
= LLVMGetParam(func
, ancillary_vgpr
+ 1);
7443 samplemask
= ac_to_integer(&ctx
->ac
, samplemask
);
7444 samplemask
= LLVMBuildAnd(
7447 LLVMBuildShl(ctx
->ac
.builder
,
7448 LLVMConstInt(ctx
->i32
, ps_iter_mask
, false),
7451 samplemask
= ac_to_float(&ctx
->ac
, samplemask
);
7453 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, samplemask
,
7454 ancillary_vgpr
+ 1, "");
7457 /* Tell LLVM to insert WQM instruction sequence when needed. */
7458 if (key
->ps_prolog
.wqm
) {
7459 LLVMAddTargetDependentFunctionAttr(func
,
7460 "amdgpu-ps-wqm-outputs", "");
7463 si_llvm_build_ret(ctx
, ret
);
7467 * Build the pixel shader epilog function. This handles everything that must be
7468 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7470 static void si_build_ps_epilog_function(struct si_shader_context
*ctx
,
7471 union si_shader_part_key
*key
)
7473 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
7474 struct si_function_info fninfo
;
7475 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
7477 struct si_ps_exports exp
= {};
7479 si_init_function_info(&fninfo
);
7481 /* Declare input SGPRs. */
7482 ctx
->param_rw_buffers
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7483 ctx
->param_bindless_samplers_and_images
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7484 ctx
->param_const_and_shader_buffers
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7485 ctx
->param_samplers_and_images
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7486 add_arg_checked(&fninfo
, ARG_SGPR
, ctx
->f32
, SI_PARAM_ALPHA_REF
);
7488 /* Declare input VGPRs. */
7489 unsigned required_num_params
=
7490 fninfo
.num_sgpr_params
+
7491 util_bitcount(key
->ps_epilog
.colors_written
) * 4 +
7492 key
->ps_epilog
.writes_z
+
7493 key
->ps_epilog
.writes_stencil
+
7494 key
->ps_epilog
.writes_samplemask
;
7496 required_num_params
= MAX2(required_num_params
,
7497 fninfo
.num_sgpr_params
+ PS_EPILOG_SAMPLEMASK_MIN_LOC
+ 1);
7499 while (fninfo
.num_params
< required_num_params
)
7500 add_arg(&fninfo
, ARG_VGPR
, ctx
->f32
);
7502 /* Create the function. */
7503 si_create_function(ctx
, "ps_epilog", NULL
, 0, &fninfo
, 0);
7504 /* Disable elimination of unused inputs. */
7505 si_llvm_add_attribute(ctx
->main_fn
,
7506 "InitialPSInputAddr", 0xffffff);
7508 /* Process colors. */
7509 unsigned vgpr
= fninfo
.num_sgpr_params
;
7510 unsigned colors_written
= key
->ps_epilog
.colors_written
;
7511 int last_color_export
= -1;
7513 /* Find the last color export. */
7514 if (!key
->ps_epilog
.writes_z
&&
7515 !key
->ps_epilog
.writes_stencil
&&
7516 !key
->ps_epilog
.writes_samplemask
) {
7517 unsigned spi_format
= key
->ps_epilog
.states
.spi_shader_col_format
;
7519 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7520 if (colors_written
== 0x1 && key
->ps_epilog
.states
.last_cbuf
> 0) {
7521 /* Just set this if any of the colorbuffers are enabled. */
7523 ((1ull << (4 * (key
->ps_epilog
.states
.last_cbuf
+ 1))) - 1))
7524 last_color_export
= 0;
7526 for (i
= 0; i
< 8; i
++)
7527 if (colors_written
& (1 << i
) &&
7528 (spi_format
>> (i
* 4)) & 0xf)
7529 last_color_export
= i
;
7533 while (colors_written
) {
7534 LLVMValueRef color
[4];
7535 int mrt
= u_bit_scan(&colors_written
);
7537 for (i
= 0; i
< 4; i
++)
7538 color
[i
] = LLVMGetParam(ctx
->main_fn
, vgpr
++);
7540 si_export_mrt_color(bld_base
, color
, mrt
,
7541 fninfo
.num_params
- 1,
7542 mrt
== last_color_export
, &exp
);
7545 /* Process depth, stencil, samplemask. */
7546 if (key
->ps_epilog
.writes_z
)
7547 depth
= LLVMGetParam(ctx
->main_fn
, vgpr
++);
7548 if (key
->ps_epilog
.writes_stencil
)
7549 stencil
= LLVMGetParam(ctx
->main_fn
, vgpr
++);
7550 if (key
->ps_epilog
.writes_samplemask
)
7551 samplemask
= LLVMGetParam(ctx
->main_fn
, vgpr
++);
7553 if (depth
|| stencil
|| samplemask
)
7554 si_export_mrt_z(bld_base
, depth
, stencil
, samplemask
, &exp
);
7555 else if (last_color_export
== -1)
7556 si_export_null(bld_base
);
7559 si_emit_ps_exports(ctx
, &exp
);
7562 LLVMBuildRetVoid(ctx
->ac
.builder
);
7566 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7568 static bool si_shader_select_ps_parts(struct si_screen
*sscreen
,
7569 LLVMTargetMachineRef tm
,
7570 struct si_shader
*shader
,
7571 struct pipe_debug_callback
*debug
)
7573 union si_shader_part_key prolog_key
;
7574 union si_shader_part_key epilog_key
;
7576 /* Get the prolog. */
7577 si_get_ps_prolog_key(shader
, &prolog_key
, true);
7579 /* The prolog is a no-op if these aren't set. */
7580 if (si_need_ps_prolog(&prolog_key
)) {
7582 si_get_shader_part(sscreen
, &sscreen
->ps_prologs
,
7583 PIPE_SHADER_FRAGMENT
, true,
7584 &prolog_key
, tm
, debug
,
7585 si_build_ps_prolog_function
,
7586 "Fragment Shader Prolog");
7587 if (!shader
->prolog
)
7591 /* Get the epilog. */
7592 si_get_ps_epilog_key(shader
, &epilog_key
);
7595 si_get_shader_part(sscreen
, &sscreen
->ps_epilogs
,
7596 PIPE_SHADER_FRAGMENT
, false,
7597 &epilog_key
, tm
, debug
,
7598 si_build_ps_epilog_function
,
7599 "Fragment Shader Epilog");
7600 if (!shader
->epilog
)
7603 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7604 if (shader
->key
.part
.ps
.prolog
.poly_stipple
) {
7605 shader
->config
.spi_ps_input_ena
|= S_0286CC_POS_FIXED_PT_ENA(1);
7606 assert(G_0286CC_POS_FIXED_PT_ENA(shader
->config
.spi_ps_input_addr
));
7609 /* Set up the enable bits for per-sample shading if needed. */
7610 if (shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
&&
7611 (G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_ena
) ||
7612 G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7613 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTER_ENA
;
7614 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTROID_ENA
;
7615 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_SAMPLE_ENA(1);
7617 if (shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
&&
7618 (G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_ena
) ||
7619 G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7620 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTER_ENA
;
7621 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTROID_ENA
;
7622 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_SAMPLE_ENA(1);
7624 if (shader
->key
.part
.ps
.prolog
.force_persp_center_interp
&&
7625 (G_0286CC_PERSP_SAMPLE_ENA(shader
->config
.spi_ps_input_ena
) ||
7626 G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7627 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_SAMPLE_ENA
;
7628 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTROID_ENA
;
7629 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_CENTER_ENA(1);
7631 if (shader
->key
.part
.ps
.prolog
.force_linear_center_interp
&&
7632 (G_0286CC_LINEAR_SAMPLE_ENA(shader
->config
.spi_ps_input_ena
) ||
7633 G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7634 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_SAMPLE_ENA
;
7635 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTROID_ENA
;
7636 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_CENTER_ENA(1);
7639 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7640 if (G_0286CC_POS_W_FLOAT_ENA(shader
->config
.spi_ps_input_ena
) &&
7641 !(shader
->config
.spi_ps_input_ena
& 0xf)) {
7642 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_CENTER_ENA(1);
7643 assert(G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_addr
));
7646 /* At least one pair of interpolation weights must be enabled. */
7647 if (!(shader
->config
.spi_ps_input_ena
& 0x7f)) {
7648 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_CENTER_ENA(1);
7649 assert(G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_addr
));
7652 /* Samplemask fixup requires the sample ID. */
7653 if (shader
->key
.part
.ps
.prolog
.samplemask_log_ps_iter
) {
7654 shader
->config
.spi_ps_input_ena
|= S_0286CC_ANCILLARY_ENA(1);
7655 assert(G_0286CC_ANCILLARY_ENA(shader
->config
.spi_ps_input_addr
));
7658 /* The sample mask input is always enabled, because the API shader always
7659 * passes it through to the epilog. Disable it here if it's unused.
7661 if (!shader
->key
.part
.ps
.epilog
.poly_line_smoothing
&&
7662 !shader
->selector
->info
.reads_samplemask
)
7663 shader
->config
.spi_ps_input_ena
&= C_0286CC_SAMPLE_COVERAGE_ENA
;
7668 void si_multiwave_lds_size_workaround(struct si_screen
*sscreen
,
7671 /* SPI barrier management bug:
7672 * Make sure we have at least 4k of LDS in use to avoid the bug.
7673 * It applies to workgroup sizes of more than one wavefront.
7675 if (sscreen
->info
.family
== CHIP_BONAIRE
||
7676 sscreen
->info
.family
== CHIP_KABINI
||
7677 sscreen
->info
.family
== CHIP_MULLINS
)
7678 *lds_size
= MAX2(*lds_size
, 8);
7681 static void si_fix_resource_usage(struct si_screen
*sscreen
,
7682 struct si_shader
*shader
)
7684 unsigned min_sgprs
= shader
->info
.num_input_sgprs
+ 2; /* VCC */
7686 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
, min_sgprs
);
7688 if (shader
->selector
->type
== PIPE_SHADER_COMPUTE
&&
7689 si_get_max_workgroup_size(shader
) > 64) {
7690 si_multiwave_lds_size_workaround(sscreen
,
7691 &shader
->config
.lds_size
);
7695 int si_shader_create(struct si_screen
*sscreen
, LLVMTargetMachineRef tm
,
7696 struct si_shader
*shader
,
7697 struct pipe_debug_callback
*debug
)
7699 struct si_shader_selector
*sel
= shader
->selector
;
7700 struct si_shader
*mainp
= *si_get_main_shader_part(sel
, &shader
->key
);
7703 /* LS, ES, VS are compiled on demand if the main part hasn't been
7704 * compiled for that stage.
7706 * Vertex shaders are compiled on demand when a vertex fetch
7707 * workaround must be applied.
7709 if (shader
->is_monolithic
) {
7710 /* Monolithic shader (compiled as a whole, has many variants,
7711 * may take a long time to compile).
7713 r
= si_compile_tgsi_shader(sscreen
, tm
, shader
, true, debug
);
7717 /* The shader consists of several parts:
7719 * - the middle part is the user shader, it has 1 variant only
7720 * and it was compiled during the creation of the shader
7722 * - the prolog part is inserted at the beginning
7723 * - the epilog part is inserted at the end
7725 * The prolog and epilog have many (but simple) variants.
7727 * Starting with gfx9, geometry and tessellation control
7728 * shaders also contain the prolog and user shader parts of
7729 * the previous shader stage.
7735 /* Copy the compiled TGSI shader data over. */
7736 shader
->is_binary_shared
= true;
7737 shader
->binary
= mainp
->binary
;
7738 shader
->config
= mainp
->config
;
7739 shader
->info
.num_input_sgprs
= mainp
->info
.num_input_sgprs
;
7740 shader
->info
.num_input_vgprs
= mainp
->info
.num_input_vgprs
;
7741 shader
->info
.face_vgpr_index
= mainp
->info
.face_vgpr_index
;
7742 shader
->info
.ancillary_vgpr_index
= mainp
->info
.ancillary_vgpr_index
;
7743 memcpy(shader
->info
.vs_output_param_offset
,
7744 mainp
->info
.vs_output_param_offset
,
7745 sizeof(mainp
->info
.vs_output_param_offset
));
7746 shader
->info
.uses_instanceid
= mainp
->info
.uses_instanceid
;
7747 shader
->info
.nr_pos_exports
= mainp
->info
.nr_pos_exports
;
7748 shader
->info
.nr_param_exports
= mainp
->info
.nr_param_exports
;
7750 /* Select prologs and/or epilogs. */
7751 switch (sel
->type
) {
7752 case PIPE_SHADER_VERTEX
:
7753 if (!si_shader_select_vs_parts(sscreen
, tm
, shader
, debug
))
7756 case PIPE_SHADER_TESS_CTRL
:
7757 if (!si_shader_select_tcs_parts(sscreen
, tm
, shader
, debug
))
7760 case PIPE_SHADER_TESS_EVAL
:
7762 case PIPE_SHADER_GEOMETRY
:
7763 if (!si_shader_select_gs_parts(sscreen
, tm
, shader
, debug
))
7766 case PIPE_SHADER_FRAGMENT
:
7767 if (!si_shader_select_ps_parts(sscreen
, tm
, shader
, debug
))
7770 /* Make sure we have at least as many VGPRs as there
7771 * are allocated inputs.
7773 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
7774 shader
->info
.num_input_vgprs
);
7778 /* Update SGPR and VGPR counts. */
7779 if (shader
->prolog
) {
7780 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
7781 shader
->prolog
->config
.num_sgprs
);
7782 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
7783 shader
->prolog
->config
.num_vgprs
);
7785 if (shader
->previous_stage
) {
7786 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
7787 shader
->previous_stage
->config
.num_sgprs
);
7788 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
7789 shader
->previous_stage
->config
.num_vgprs
);
7790 shader
->config
.spilled_sgprs
=
7791 MAX2(shader
->config
.spilled_sgprs
,
7792 shader
->previous_stage
->config
.spilled_sgprs
);
7793 shader
->config
.spilled_vgprs
=
7794 MAX2(shader
->config
.spilled_vgprs
,
7795 shader
->previous_stage
->config
.spilled_vgprs
);
7796 shader
->config
.private_mem_vgprs
=
7797 MAX2(shader
->config
.private_mem_vgprs
,
7798 shader
->previous_stage
->config
.private_mem_vgprs
);
7799 shader
->config
.scratch_bytes_per_wave
=
7800 MAX2(shader
->config
.scratch_bytes_per_wave
,
7801 shader
->previous_stage
->config
.scratch_bytes_per_wave
);
7802 shader
->info
.uses_instanceid
|=
7803 shader
->previous_stage
->info
.uses_instanceid
;
7805 if (shader
->prolog2
) {
7806 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
7807 shader
->prolog2
->config
.num_sgprs
);
7808 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
7809 shader
->prolog2
->config
.num_vgprs
);
7811 if (shader
->epilog
) {
7812 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
7813 shader
->epilog
->config
.num_sgprs
);
7814 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
7815 shader
->epilog
->config
.num_vgprs
);
7819 si_fix_resource_usage(sscreen
, shader
);
7820 si_shader_dump(sscreen
, shader
, debug
, sel
->info
.processor
,
7824 r
= si_shader_binary_upload(sscreen
, shader
);
7826 fprintf(stderr
, "LLVM failed to upload shader\n");
7833 void si_shader_destroy(struct si_shader
*shader
)
7835 if (shader
->scratch_bo
)
7836 r600_resource_reference(&shader
->scratch_bo
, NULL
);
7838 r600_resource_reference(&shader
->bo
, NULL
);
7840 if (!shader
->is_binary_shared
)
7841 ac_shader_binary_clean(&shader
->binary
);
7843 free(shader
->shader_log
);