3 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Tom Stellard <thomas.stellard@amd.com>
26 * Michel Dänzer <michel.daenzer@amd.com>
27 * Christian König <christian.koenig@amd.com>
30 #include "gallivm/lp_bld_tgsi_action.h"
31 #include "gallivm/lp_bld_const.h"
32 #include "gallivm/lp_bld_gather.h"
33 #include "gallivm/lp_bld_intr.h"
34 #include "gallivm/lp_bld_logic.h"
35 #include "gallivm/lp_bld_tgsi.h"
36 #include "gallivm/lp_bld_arit.h"
37 #include "gallivm/lp_bld_flow.h"
38 #include "radeon_llvm.h"
39 #include "radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "tgsi/tgsi_info.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_scan.h"
44 #include "tgsi/tgsi_util.h"
45 #include "tgsi/tgsi_dump.h"
48 #include "si_shader.h"
56 struct si_shader_context
58 struct radeon_llvm_context radeon_bld
;
59 struct tgsi_parse_context parse
;
60 struct tgsi_token
* tokens
;
61 struct si_pipe_shader
*shader
;
62 unsigned type
; /* TGSI_PROCESSOR_* specifies the type of shader. */
63 int param_streamout_config
;
64 int param_streamout_write_index
;
65 int param_streamout_offset
[4];
67 int param_instance_id
;
68 LLVMValueRef const_md
;
69 LLVMValueRef const_resource
[NUM_CONST_BUFFERS
];
70 #if HAVE_LLVM >= 0x0304
71 LLVMValueRef ddxy_lds
;
73 LLVMValueRef
*constants
[NUM_CONST_BUFFERS
];
74 LLVMValueRef
*resources
;
75 LLVMValueRef
*samplers
;
76 LLVMValueRef so_buffers
[4];
79 static struct si_shader_context
* si_shader_context(
80 struct lp_build_tgsi_context
* bld_base
)
82 return (struct si_shader_context
*)bld_base
;
86 #define PERSPECTIVE_BASE 0
89 #define SAMPLE_OFFSET 0
90 #define CENTER_OFFSET 2
91 #define CENTROID_OFSET 4
93 #define USE_SGPR_MAX_SUFFIX_LEN 5
94 #define CONST_ADDR_SPACE 2
95 #define LOCAL_ADDR_SPACE 3
96 #define USER_SGPR_ADDR_SPACE 8
99 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
101 * @param offset The offset parameter specifies the number of
102 * elements to offset, not the number of bytes or dwords. An element is the
103 * the type pointed to by the base_ptr parameter (e.g. int is the element of
106 * When LLVM lowers the load instruction, it will convert the element offset
107 * into a dword offset automatically.
110 static LLVMValueRef
build_indexed_load(
111 struct si_shader_context
* si_shader_ctx
,
112 LLVMValueRef base_ptr
,
115 struct lp_build_context
* base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
.base
;
117 LLVMValueRef indices
[2] = {
118 LLVMConstInt(LLVMInt64TypeInContext(base
->gallivm
->context
), 0, false),
121 LLVMValueRef computed_ptr
= LLVMBuildGEP(
122 base
->gallivm
->builder
, base_ptr
, indices
, 2, "");
124 LLVMValueRef result
= LLVMBuildLoad(base
->gallivm
->builder
, computed_ptr
, "");
125 LLVMSetMetadata(result
, 1, si_shader_ctx
->const_md
);
129 static LLVMValueRef
get_instance_index_for_fetch(
130 struct radeon_llvm_context
* radeon_bld
,
133 struct si_shader_context
*si_shader_ctx
=
134 si_shader_context(&radeon_bld
->soa
.bld_base
);
135 struct gallivm_state
* gallivm
= radeon_bld
->soa
.bld_base
.base
.gallivm
;
137 LLVMValueRef result
= LLVMGetParam(radeon_bld
->main_fn
,
138 si_shader_ctx
->param_instance_id
);
139 result
= LLVMBuildAdd(gallivm
->builder
, result
, LLVMGetParam(
140 radeon_bld
->main_fn
, SI_PARAM_START_INSTANCE
), "");
143 result
= LLVMBuildUDiv(gallivm
->builder
, result
,
144 lp_build_const_int32(gallivm
, divisor
), "");
149 static void declare_input_vs(
150 struct si_shader_context
* si_shader_ctx
,
151 unsigned input_index
,
152 const struct tgsi_full_declaration
*decl
)
154 struct lp_build_context
* base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
.base
;
155 unsigned divisor
= si_shader_ctx
->shader
->key
.vs
.instance_divisors
[input_index
];
159 LLVMValueRef t_list_ptr
;
160 LLVMValueRef t_offset
;
162 LLVMValueRef attribute_offset
;
163 LLVMValueRef buffer_index
;
164 LLVMValueRef args
[3];
165 LLVMTypeRef vec4_type
;
168 /* Load the T list */
169 t_list_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_VERTEX_BUFFER
);
171 t_offset
= lp_build_const_int32(base
->gallivm
, input_index
);
173 t_list
= build_indexed_load(si_shader_ctx
, t_list_ptr
, t_offset
);
175 /* Build the attribute offset */
176 attribute_offset
= lp_build_const_int32(base
->gallivm
, 0);
179 /* Build index from instance ID, start instance and divisor */
180 si_shader_ctx
->shader
->shader
.uses_instanceid
= true;
181 buffer_index
= get_instance_index_for_fetch(&si_shader_ctx
->radeon_bld
, divisor
);
183 /* Load the buffer index, which is always stored in VGPR0
184 * for Vertex Shaders */
185 buffer_index
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
186 si_shader_ctx
->param_vertex_id
);
189 vec4_type
= LLVMVectorType(base
->elem_type
, 4);
191 args
[1] = attribute_offset
;
192 args
[2] = buffer_index
;
193 input
= build_intrinsic(base
->gallivm
->builder
,
194 "llvm.SI.vs.load.input", vec4_type
, args
, 3,
195 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
197 /* Break up the vec4 into individual components */
198 for (chan
= 0; chan
< 4; chan
++) {
199 LLVMValueRef llvm_chan
= lp_build_const_int32(base
->gallivm
, chan
);
200 /* XXX: Use a helper function for this. There is one in
202 si_shader_ctx
->radeon_bld
.inputs
[radeon_llvm_reg_index_soa(input_index
, chan
)] =
203 LLVMBuildExtractElement(base
->gallivm
->builder
,
204 input
, llvm_chan
, "");
208 static void declare_input_fs(
209 struct si_shader_context
* si_shader_ctx
,
210 unsigned input_index
,
211 const struct tgsi_full_declaration
*decl
)
213 struct si_shader
*shader
= &si_shader_ctx
->shader
->shader
;
214 struct lp_build_context
* base
=
215 &si_shader_ctx
->radeon_bld
.soa
.bld_base
.base
;
216 struct lp_build_context
*uint
=
217 &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
218 struct gallivm_state
* gallivm
= base
->gallivm
;
219 LLVMTypeRef input_type
= LLVMFloatTypeInContext(gallivm
->context
);
220 LLVMValueRef main_fn
= si_shader_ctx
->radeon_bld
.main_fn
;
222 LLVMValueRef interp_param
;
223 const char * intr_name
;
226 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
227 * quad begins a new primitive. Bit 0 always needs
229 * [32:16] ParamOffset
232 LLVMValueRef params
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_PRIM_MASK
);
233 LLVMValueRef attr_number
;
237 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_POSITION
) {
238 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
240 radeon_llvm_reg_index_soa(input_index
, chan
);
241 si_shader_ctx
->radeon_bld
.inputs
[soa_index
] =
242 LLVMGetParam(main_fn
, SI_PARAM_POS_X_FLOAT
+ chan
);
245 /* RCP for fragcoord.w */
246 si_shader_ctx
->radeon_bld
.inputs
[soa_index
] =
247 LLVMBuildFDiv(gallivm
->builder
,
248 lp_build_const_float(gallivm
, 1.0f
),
249 si_shader_ctx
->radeon_bld
.inputs
[soa_index
],
255 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
256 LLVMValueRef face
, is_face_positive
;
258 face
= LLVMGetParam(main_fn
, SI_PARAM_FRONT_FACE
);
260 is_face_positive
= LLVMBuildFCmp(gallivm
->builder
,
262 lp_build_const_float(gallivm
, 0.0f
),
265 si_shader_ctx
->radeon_bld
.inputs
[radeon_llvm_reg_index_soa(input_index
, 0)] =
266 LLVMBuildSelect(gallivm
->builder
,
268 lp_build_const_float(gallivm
, 1.0f
),
269 lp_build_const_float(gallivm
, 0.0f
),
271 si_shader_ctx
->radeon_bld
.inputs
[radeon_llvm_reg_index_soa(input_index
, 1)] =
272 si_shader_ctx
->radeon_bld
.inputs
[radeon_llvm_reg_index_soa(input_index
, 2)] =
273 lp_build_const_float(gallivm
, 0.0f
);
274 si_shader_ctx
->radeon_bld
.inputs
[radeon_llvm_reg_index_soa(input_index
, 3)] =
275 lp_build_const_float(gallivm
, 1.0f
);
280 shader
->input
[input_index
].param_offset
= shader
->ninterp
++;
281 attr_number
= lp_build_const_int32(gallivm
,
282 shader
->input
[input_index
].param_offset
);
284 switch (decl
->Interp
.Interpolate
) {
285 case TGSI_INTERPOLATE_COLOR
:
286 if (si_shader_ctx
->shader
->key
.ps
.flatshade
) {
289 if (decl
->Interp
.Centroid
)
290 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_PERSP_CENTROID
);
292 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_PERSP_CENTER
);
295 case TGSI_INTERPOLATE_CONSTANT
:
298 case TGSI_INTERPOLATE_LINEAR
:
299 if (decl
->Interp
.Centroid
)
300 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_LINEAR_CENTROID
);
302 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_LINEAR_CENTER
);
304 case TGSI_INTERPOLATE_PERSPECTIVE
:
305 if (decl
->Interp
.Centroid
)
306 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_PERSP_CENTROID
);
308 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_PERSP_CENTER
);
311 fprintf(stderr
, "Warning: Unhandled interpolation mode.\n");
315 intr_name
= interp_param
? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
317 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
318 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_COLOR
&&
319 si_shader_ctx
->shader
->key
.ps
.color_two_side
) {
320 LLVMValueRef args
[4];
321 LLVMValueRef face
, is_face_positive
;
322 LLVMValueRef back_attr_number
=
323 lp_build_const_int32(gallivm
,
324 shader
->input
[input_index
].param_offset
+ 1);
326 face
= LLVMGetParam(main_fn
, SI_PARAM_FRONT_FACE
);
328 is_face_positive
= LLVMBuildFCmp(gallivm
->builder
,
330 lp_build_const_float(gallivm
, 0.0f
),
334 args
[3] = interp_param
;
335 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
336 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
337 unsigned soa_index
= radeon_llvm_reg_index_soa(input_index
, chan
);
338 LLVMValueRef front
, back
;
341 args
[1] = attr_number
;
342 front
= build_intrinsic(base
->gallivm
->builder
, intr_name
,
343 input_type
, args
, args
[3] ? 4 : 3,
344 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
346 args
[1] = back_attr_number
;
347 back
= build_intrinsic(base
->gallivm
->builder
, intr_name
,
348 input_type
, args
, args
[3] ? 4 : 3,
349 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
351 si_shader_ctx
->radeon_bld
.inputs
[soa_index
] =
352 LLVMBuildSelect(gallivm
->builder
,
360 } else if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FOG
) {
361 LLVMValueRef args
[4];
363 args
[0] = uint
->zero
;
364 args
[1] = attr_number
;
366 args
[3] = interp_param
;
367 si_shader_ctx
->radeon_bld
.inputs
[radeon_llvm_reg_index_soa(input_index
, 0)] =
368 build_intrinsic(base
->gallivm
->builder
, intr_name
,
369 input_type
, args
, args
[3] ? 4 : 3,
370 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
371 si_shader_ctx
->radeon_bld
.inputs
[radeon_llvm_reg_index_soa(input_index
, 1)] =
372 si_shader_ctx
->radeon_bld
.inputs
[radeon_llvm_reg_index_soa(input_index
, 2)] =
373 lp_build_const_float(gallivm
, 0.0f
);
374 si_shader_ctx
->radeon_bld
.inputs
[radeon_llvm_reg_index_soa(input_index
, 3)] =
375 lp_build_const_float(gallivm
, 1.0f
);
377 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
378 LLVMValueRef args
[4];
379 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
380 unsigned soa_index
= radeon_llvm_reg_index_soa(input_index
, chan
);
382 args
[1] = attr_number
;
384 args
[3] = interp_param
;
385 si_shader_ctx
->radeon_bld
.inputs
[soa_index
] =
386 build_intrinsic(base
->gallivm
->builder
, intr_name
,
387 input_type
, args
, args
[3] ? 4 : 3,
388 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
393 static void declare_input(
394 struct radeon_llvm_context
* radeon_bld
,
395 unsigned input_index
,
396 const struct tgsi_full_declaration
*decl
)
398 struct si_shader_context
* si_shader_ctx
=
399 si_shader_context(&radeon_bld
->soa
.bld_base
);
400 if (si_shader_ctx
->type
== TGSI_PROCESSOR_VERTEX
) {
401 declare_input_vs(si_shader_ctx
, input_index
, decl
);
402 } else if (si_shader_ctx
->type
== TGSI_PROCESSOR_FRAGMENT
) {
403 declare_input_fs(si_shader_ctx
, input_index
, decl
);
405 fprintf(stderr
, "Warning: Unsupported shader type,\n");
409 static void declare_system_value(
410 struct radeon_llvm_context
* radeon_bld
,
412 const struct tgsi_full_declaration
*decl
)
414 struct si_shader_context
*si_shader_ctx
=
415 si_shader_context(&radeon_bld
->soa
.bld_base
);
416 LLVMValueRef value
= 0;
418 switch (decl
->Semantic
.Name
) {
419 case TGSI_SEMANTIC_INSTANCEID
:
420 value
= LLVMGetParam(radeon_bld
->main_fn
,
421 si_shader_ctx
->param_instance_id
);
424 case TGSI_SEMANTIC_VERTEXID
:
425 value
= LLVMGetParam(radeon_bld
->main_fn
,
426 si_shader_ctx
->param_vertex_id
);
430 assert(!"unknown system value");
434 radeon_bld
->system_values
[index
] = value
;
437 static LLVMValueRef
fetch_constant(
438 struct lp_build_tgsi_context
* bld_base
,
439 const struct tgsi_full_src_register
*reg
,
440 enum tgsi_opcode_type type
,
443 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
444 struct lp_build_context
* base
= &bld_base
->base
;
445 const struct tgsi_ind_register
*ireg
= ®
->Indirect
;
448 LLVMValueRef args
[2];
452 if (swizzle
== LP_CHAN_ALL
) {
454 LLVMValueRef values
[4];
455 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; ++chan
)
456 values
[chan
] = fetch_constant(bld_base
, reg
, type
, chan
);
458 return lp_build_gather_values(bld_base
->base
.gallivm
, values
, 4);
461 buf
= reg
->Register
.Dimension
? reg
->Dimension
.Index
: 0;
462 idx
= reg
->Register
.Index
* 4 + swizzle
;
464 if (!reg
->Register
.Indirect
)
465 return bitcast(bld_base
, type
, si_shader_ctx
->constants
[buf
][idx
]);
467 args
[0] = si_shader_ctx
->const_resource
[buf
];
468 args
[1] = lp_build_const_int32(base
->gallivm
, idx
* 4);
469 addr
= si_shader_ctx
->radeon_bld
.soa
.addr
[ireg
->Index
][ireg
->Swizzle
];
470 addr
= LLVMBuildLoad(base
->gallivm
->builder
, addr
, "load addr reg");
471 addr
= lp_build_mul_imm(&bld_base
->uint_bld
, addr
, 16);
472 args
[1] = lp_build_add(&bld_base
->uint_bld
, addr
, args
[1]);
474 result
= build_intrinsic(base
->gallivm
->builder
, "llvm.SI.load.const", base
->elem_type
,
475 args
, 2, LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
477 return bitcast(bld_base
, type
, result
);
480 /* Initialize arguments for the shader export intrinsic */
481 static void si_llvm_init_export_args(struct lp_build_tgsi_context
*bld_base
,
482 struct tgsi_full_declaration
*d
,
487 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
488 struct lp_build_context
*uint
=
489 &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
490 struct lp_build_context
*base
= &bld_base
->base
;
491 unsigned compressed
= 0;
494 if (si_shader_ctx
->type
== TGSI_PROCESSOR_FRAGMENT
) {
495 int cbuf
= target
- V_008DFC_SQ_EXP_MRT
;
497 if (cbuf
>= 0 && cbuf
< 8) {
498 compressed
= (si_shader_ctx
->shader
->key
.ps
.export_16bpc
>> cbuf
) & 0x1;
501 si_shader_ctx
->shader
->spi_shader_col_format
|=
502 V_028714_SPI_SHADER_FP16_ABGR
<< (4 * cbuf
);
504 si_shader_ctx
->shader
->spi_shader_col_format
|=
505 V_028714_SPI_SHADER_32_ABGR
<< (4 * cbuf
);
507 si_shader_ctx
->shader
->cb_shader_mask
|= 0xf << (4 * cbuf
);
512 /* Pixel shader needs to pack output values before export */
513 for (chan
= 0; chan
< 2; chan
++ ) {
514 LLVMValueRef
*out_ptr
=
515 si_shader_ctx
->radeon_bld
.soa
.outputs
[index
];
516 args
[0] = LLVMBuildLoad(base
->gallivm
->builder
,
517 out_ptr
[2 * chan
], "");
518 args
[1] = LLVMBuildLoad(base
->gallivm
->builder
,
519 out_ptr
[2 * chan
+ 1], "");
521 build_intrinsic(base
->gallivm
->builder
,
523 LLVMInt32TypeInContext(base
->gallivm
->context
),
525 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
526 args
[chan
+ 7] = args
[chan
+ 5] =
527 LLVMBuildBitCast(base
->gallivm
->builder
,
529 LLVMFloatTypeInContext(base
->gallivm
->context
),
536 for (chan
= 0; chan
< 4; chan
++ ) {
537 LLVMValueRef out_ptr
=
538 si_shader_ctx
->radeon_bld
.soa
.outputs
[index
][chan
];
539 /* +5 because the first output value will be
540 * the 6th argument to the intrinsic. */
541 args
[chan
+ 5] = LLVMBuildLoad(base
->gallivm
->builder
,
545 /* Clear COMPR flag */
546 args
[4] = uint
->zero
;
549 /* XXX: This controls which components of the output
550 * registers actually get exported. (e.g bit 0 means export
551 * X component, bit 1 means export Y component, etc.) I'm
552 * hard coding this to 0xf for now. In the future, we might
553 * want to do something else. */
554 args
[0] = lp_build_const_int32(base
->gallivm
, 0xf);
556 /* Specify whether the EXEC mask represents the valid mask */
557 args
[1] = uint
->zero
;
559 /* Specify whether this is the last export */
560 args
[2] = uint
->zero
;
562 /* Specify the target we are exporting */
563 args
[3] = lp_build_const_int32(base
->gallivm
, target
);
565 /* XXX: We probably need to keep track of the output
566 * values, so we know what we are passing to the next
570 static void si_alpha_test(struct lp_build_tgsi_context
*bld_base
,
573 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
574 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
576 if (si_shader_ctx
->shader
->key
.ps
.alpha_func
!= PIPE_FUNC_NEVER
) {
577 LLVMValueRef out_ptr
= si_shader_ctx
->radeon_bld
.soa
.outputs
[index
][3];
578 LLVMValueRef alpha_ref
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
581 LLVMValueRef alpha_pass
=
582 lp_build_cmp(&bld_base
->base
,
583 si_shader_ctx
->shader
->key
.ps
.alpha_func
,
584 LLVMBuildLoad(gallivm
->builder
, out_ptr
, ""),
587 lp_build_select(&bld_base
->base
,
589 lp_build_const_float(gallivm
, 1.0f
),
590 lp_build_const_float(gallivm
, -1.0f
));
592 build_intrinsic(gallivm
->builder
,
594 LLVMVoidTypeInContext(gallivm
->context
),
597 build_intrinsic(gallivm
->builder
,
599 LLVMVoidTypeInContext(gallivm
->context
),
604 static void si_alpha_to_one(struct lp_build_tgsi_context
*bld_base
,
607 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
609 /* set alpha to one */
610 LLVMBuildStore(bld_base
->base
.gallivm
->builder
,
612 si_shader_ctx
->radeon_bld
.soa
.outputs
[index
][3]);
615 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context
* bld_base
,
616 LLVMValueRef (*pos
)[9], unsigned index
)
618 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
619 struct si_pipe_shader
*shader
= si_shader_ctx
->shader
;
620 struct lp_build_context
*base
= &bld_base
->base
;
621 struct lp_build_context
*uint
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
625 LLVMValueRef out_elts
[4];
626 LLVMValueRef base_elt
;
627 LLVMValueRef ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_CONST
);
628 LLVMValueRef constbuf_index
= lp_build_const_int32(base
->gallivm
, NUM_PIPE_CONST_BUFFERS
);
629 LLVMValueRef const_resource
= build_indexed_load(si_shader_ctx
, ptr
, constbuf_index
);
631 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
632 LLVMValueRef out_ptr
= si_shader_ctx
->radeon_bld
.soa
.outputs
[index
][chan
];
633 out_elts
[chan
] = LLVMBuildLoad(base
->gallivm
->builder
, out_ptr
, "");
636 for (reg_index
= 0; reg_index
< 2; reg_index
++) {
637 LLVMValueRef
*args
= pos
[2 + reg_index
];
639 if (!(shader
->key
.vs
.ucps_enabled
& (1 << reg_index
)))
642 shader
->shader
.clip_dist_write
|= 0xf << (4 * reg_index
);
647 args
[8] = lp_build_const_float(base
->gallivm
, 0.0f
);
649 /* Compute dot products of position and user clip plane vectors */
650 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
651 for (const_chan
= 0; const_chan
< TGSI_NUM_CHANNELS
; const_chan
++) {
652 args
[0] = const_resource
;
653 args
[1] = lp_build_const_int32(base
->gallivm
,
654 ((reg_index
* 4 + chan
) * 4 +
656 base_elt
= build_intrinsic(base
->gallivm
->builder
,
657 "llvm.SI.load.const",
660 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
662 lp_build_add(base
, args
[5 + chan
],
663 lp_build_mul(base
, base_elt
,
664 out_elts
[const_chan
]));
668 args
[0] = lp_build_const_int32(base
->gallivm
, 0xf);
669 args
[1] = uint
->zero
;
670 args
[2] = uint
->zero
;
671 args
[3] = lp_build_const_int32(base
->gallivm
,
672 V_008DFC_SQ_EXP_POS
+ 2 + reg_index
);
673 args
[4] = uint
->zero
;
677 static void si_dump_streamout(struct pipe_stream_output_info
*so
)
682 fprintf(stderr
, "STREAMOUT\n");
684 for (i
= 0; i
< so
->num_outputs
; i
++) {
685 unsigned mask
= ((1 << so
->output
[i
].num_components
) - 1) <<
686 so
->output
[i
].start_component
;
687 fprintf(stderr
, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
688 i
, so
->output
[i
].output_buffer
,
689 so
->output
[i
].dst_offset
, so
->output
[i
].dst_offset
+ so
->output
[i
].num_components
- 1,
690 so
->output
[i
].register_index
,
694 mask
& 8 ? "w" : "");
698 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
699 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
700 * or v4i32 (num_channels=3,4). */
701 static void build_tbuffer_store(struct si_shader_context
*shader
,
704 unsigned num_channels
,
706 LLVMValueRef soffset
,
707 unsigned inst_offset
,
716 struct gallivm_state
*gallivm
= &shader
->radeon_bld
.gallivm
;
717 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
718 LLVMValueRef args
[] = {
721 LLVMConstInt(i32
, num_channels
, 0),
724 LLVMConstInt(i32
, inst_offset
, 0),
725 LLVMConstInt(i32
, dfmt
, 0),
726 LLVMConstInt(i32
, nfmt
, 0),
727 LLVMConstInt(i32
, offen
, 0),
728 LLVMConstInt(i32
, idxen
, 0),
729 LLVMConstInt(i32
, glc
, 0),
730 LLVMConstInt(i32
, slc
, 0),
731 LLVMConstInt(i32
, tfe
, 0)
734 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
735 unsigned func
= CLAMP(num_channels
, 1, 3) - 1;
736 const char *types
[] = {"i32", "v2i32", "v4i32"};
738 snprintf(name
, sizeof(name
), "llvm.SI.tbuffer.store.%s", types
[func
]);
740 lp_build_intrinsic(gallivm
->builder
, name
,
741 LLVMVoidTypeInContext(gallivm
->context
),
742 args
, Elements(args
));
745 static void build_streamout_store(struct si_shader_context
*shader
,
748 unsigned num_channels
,
750 LLVMValueRef soffset
,
751 unsigned inst_offset
)
753 static unsigned dfmt
[] = {
754 V_008F0C_BUF_DATA_FORMAT_32
,
755 V_008F0C_BUF_DATA_FORMAT_32_32
,
756 V_008F0C_BUF_DATA_FORMAT_32_32_32
,
757 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
759 assert(num_channels
>= 1 && num_channels
<= 4);
761 build_tbuffer_store(shader
, rsrc
, vdata
, num_channels
, vaddr
, soffset
,
762 inst_offset
, dfmt
[num_channels
-1],
763 V_008F0C_BUF_NUM_FORMAT_UINT
, 1, 0, 1, 1, 0);
766 /* On SI, the vertex shader is responsible for writing streamout data
768 static void si_llvm_emit_streamout(struct si_shader_context
*shader
)
770 struct pipe_stream_output_info
*so
= &shader
->shader
->selector
->so
;
771 struct gallivm_state
*gallivm
= &shader
->radeon_bld
.gallivm
;
772 LLVMBuilderRef builder
= gallivm
->builder
;
774 struct lp_build_if_state if_ctx
;
776 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
778 LLVMValueRef so_param
=
779 LLVMGetParam(shader
->radeon_bld
.main_fn
,
780 shader
->param_streamout_config
);
782 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
783 LLVMValueRef so_vtx_count
=
784 LLVMBuildAnd(builder
,
785 LLVMBuildLShr(builder
, so_param
,
786 LLVMConstInt(i32
, 16, 0), ""),
787 LLVMConstInt(i32
, 127, 0), "");
789 LLVMValueRef tid
= build_intrinsic(builder
, "llvm.SI.tid", i32
,
790 NULL
, 0, LLVMReadNoneAttribute
);
792 /* can_emit = tid < so_vtx_count; */
793 LLVMValueRef can_emit
=
794 LLVMBuildICmp(builder
, LLVMIntULT
, tid
, so_vtx_count
, "");
796 /* Emit the streamout code conditionally. This actually avoids
797 * out-of-bounds buffer access. The hw tells us via the SGPR
798 * (so_vtx_count) which threads are allowed to emit streamout data. */
799 lp_build_if(&if_ctx
, gallivm
, can_emit
);
801 /* The buffer offset is computed as follows:
802 * ByteOffset = streamout_offset[buffer_id]*4 +
803 * (streamout_write_index + thread_id)*stride[buffer_id] +
807 LLVMValueRef so_write_index
=
808 LLVMGetParam(shader
->radeon_bld
.main_fn
,
809 shader
->param_streamout_write_index
);
811 /* Compute (streamout_write_index + thread_id). */
812 so_write_index
= LLVMBuildAdd(builder
, so_write_index
, tid
, "");
814 /* Compute the write offset for each enabled buffer. */
815 LLVMValueRef so_write_offset
[4] = {};
816 for (i
= 0; i
< 4; i
++) {
820 LLVMValueRef so_offset
= LLVMGetParam(shader
->radeon_bld
.main_fn
,
821 shader
->param_streamout_offset
[i
]);
822 so_offset
= LLVMBuildMul(builder
, so_offset
, LLVMConstInt(i32
, 4, 0), "");
824 so_write_offset
[i
] = LLVMBuildMul(builder
, so_write_index
,
825 LLVMConstInt(i32
, so
->stride
[i
]*4, 0), "");
826 so_write_offset
[i
] = LLVMBuildAdd(builder
, so_write_offset
[i
], so_offset
, "");
829 LLVMValueRef (*outputs
)[TGSI_NUM_CHANNELS
] = shader
->radeon_bld
.soa
.outputs
;
831 /* Write streamout data. */
832 for (i
= 0; i
< so
->num_outputs
; i
++) {
833 unsigned buf_idx
= so
->output
[i
].output_buffer
;
834 unsigned reg
= so
->output
[i
].register_index
;
835 unsigned start
= so
->output
[i
].start_component
;
836 unsigned num_comps
= so
->output
[i
].num_components
;
839 assert(num_comps
&& num_comps
<= 4);
840 if (!num_comps
|| num_comps
> 4)
843 /* Load the output as int. */
844 for (j
= 0; j
< num_comps
; j
++) {
845 out
[j
] = LLVMBuildLoad(builder
, outputs
[reg
][start
+j
], "");
846 out
[j
] = LLVMBuildBitCast(builder
, out
[j
], i32
, "");
849 /* Pack the output. */
850 LLVMValueRef vdata
= NULL
;
856 case 2: /* as v2i32 */
857 case 3: /* as v4i32 (aligned to 4) */
858 case 4: /* as v4i32 */
859 vdata
= LLVMGetUndef(LLVMVectorType(i32
, util_next_power_of_two(num_comps
)));
860 for (j
= 0; j
< num_comps
; j
++) {
861 vdata
= LLVMBuildInsertElement(builder
, vdata
, out
[j
],
862 LLVMConstInt(i32
, j
, 0), "");
867 build_streamout_store(shader
, shader
->so_buffers
[buf_idx
],
869 so_write_offset
[buf_idx
],
870 LLVMConstInt(i32
, 0, 0),
871 so
->output
[i
].dst_offset
*4);
874 lp_build_endif(&if_ctx
);
878 static void si_llvm_emit_epilogue(struct lp_build_tgsi_context
* bld_base
)
880 struct si_shader_context
* si_shader_ctx
= si_shader_context(bld_base
);
881 struct si_shader
* shader
= &si_shader_ctx
->shader
->shader
;
882 struct lp_build_context
* base
= &bld_base
->base
;
883 struct lp_build_context
* uint
=
884 &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
885 struct tgsi_parse_context
*parse
= &si_shader_ctx
->parse
;
886 LLVMValueRef args
[9];
887 LLVMValueRef last_args
[9] = { 0 };
888 LLVMValueRef pos_args
[4][9] = { { 0 } };
889 unsigned semantic_name
;
890 unsigned param_count
= 0;
891 int depth_index
= -1, stencil_index
= -1, psize_index
= -1, edgeflag_index
= -1;
892 int layer_index
= -1;
895 if (si_shader_ctx
->shader
->selector
->so
.num_outputs
) {
896 si_llvm_emit_streamout(si_shader_ctx
);
899 while (!tgsi_parse_end_of_tokens(parse
)) {
900 struct tgsi_full_declaration
*d
=
901 &parse
->FullToken
.FullDeclaration
;
905 tgsi_parse_token(parse
);
907 if (parse
->FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_PROPERTY
&&
908 parse
->FullToken
.FullProperty
.Property
.PropertyName
==
909 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
)
910 shader
->fs_write_all
= TRUE
;
912 if (parse
->FullToken
.Token
.Type
!= TGSI_TOKEN_TYPE_DECLARATION
)
915 switch (d
->Declaration
.File
) {
916 case TGSI_FILE_INPUT
:
917 i
= shader
->ninput
++;
918 assert(i
< Elements(shader
->input
));
919 shader
->input
[i
].name
= d
->Semantic
.Name
;
920 shader
->input
[i
].sid
= d
->Semantic
.Index
;
921 shader
->input
[i
].interpolate
= d
->Interp
.Interpolate
;
922 shader
->input
[i
].centroid
= d
->Interp
.Centroid
;
925 case TGSI_FILE_OUTPUT
:
926 i
= shader
->noutput
++;
927 assert(i
< Elements(shader
->output
));
928 shader
->output
[i
].name
= d
->Semantic
.Name
;
929 shader
->output
[i
].sid
= d
->Semantic
.Index
;
930 shader
->output
[i
].interpolate
= d
->Interp
.Interpolate
;
937 semantic_name
= d
->Semantic
.Name
;
939 for (index
= d
->Range
.First
; index
<= d
->Range
.Last
; index
++) {
940 /* Select the correct target */
941 switch(semantic_name
) {
942 case TGSI_SEMANTIC_PSIZE
:
943 shader
->vs_out_misc_write
= true;
944 shader
->vs_out_point_size
= true;
947 case TGSI_SEMANTIC_EDGEFLAG
:
948 shader
->vs_out_misc_write
= true;
949 shader
->vs_out_edgeflag
= true;
950 edgeflag_index
= index
;
952 case TGSI_SEMANTIC_LAYER
:
953 shader
->vs_out_misc_write
= true;
954 shader
->vs_out_layer
= true;
957 case TGSI_SEMANTIC_POSITION
:
958 if (si_shader_ctx
->type
== TGSI_PROCESSOR_VERTEX
) {
959 target
= V_008DFC_SQ_EXP_POS
;
965 case TGSI_SEMANTIC_STENCIL
:
966 stencil_index
= index
;
968 case TGSI_SEMANTIC_COLOR
:
969 if (si_shader_ctx
->type
== TGSI_PROCESSOR_VERTEX
) {
970 case TGSI_SEMANTIC_BCOLOR
:
971 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
972 shader
->output
[i
].param_offset
= param_count
;
975 target
= V_008DFC_SQ_EXP_MRT
+ shader
->output
[i
].sid
;
976 if (si_shader_ctx
->shader
->key
.ps
.alpha_to_one
) {
977 si_alpha_to_one(bld_base
, index
);
979 if (shader
->output
[i
].sid
== 0 &&
980 si_shader_ctx
->shader
->key
.ps
.alpha_func
!= PIPE_FUNC_ALWAYS
)
981 si_alpha_test(bld_base
, index
);
984 case TGSI_SEMANTIC_CLIPDIST
:
985 if (!(si_shader_ctx
->shader
->key
.vs
.ucps_enabled
&
986 (1 << d
->Semantic
.Index
)))
988 shader
->clip_dist_write
|=
989 d
->Declaration
.UsageMask
<< (d
->Semantic
.Index
<< 2);
990 target
= V_008DFC_SQ_EXP_POS
+ 2 + d
->Semantic
.Index
;
992 case TGSI_SEMANTIC_CLIPVERTEX
:
993 si_llvm_emit_clipvertex(bld_base
, pos_args
, index
);
995 case TGSI_SEMANTIC_FOG
:
996 case TGSI_SEMANTIC_GENERIC
:
997 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
998 shader
->output
[i
].param_offset
= param_count
;
1004 "Warning: SI unhandled output type:%d\n",
1008 si_llvm_init_export_args(bld_base
, d
, index
, target
, args
);
1010 if (si_shader_ctx
->type
== TGSI_PROCESSOR_VERTEX
&&
1011 target
>= V_008DFC_SQ_EXP_POS
&&
1012 target
<= (V_008DFC_SQ_EXP_POS
+ 3)) {
1013 memcpy(pos_args
[target
- V_008DFC_SQ_EXP_POS
],
1014 args
, sizeof(args
));
1015 } else if (si_shader_ctx
->type
== TGSI_PROCESSOR_FRAGMENT
&&
1016 semantic_name
== TGSI_SEMANTIC_COLOR
) {
1017 /* If there is an export instruction waiting to be emitted, do so now. */
1019 lp_build_intrinsic(base
->gallivm
->builder
,
1021 LLVMVoidTypeInContext(base
->gallivm
->context
),
1025 /* This instruction will be emitted at the end of the shader. */
1026 memcpy(last_args
, args
, sizeof(args
));
1028 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
1029 if (shader
->fs_write_all
&& shader
->output
[i
].sid
== 0 &&
1030 si_shader_ctx
->shader
->key
.ps
.nr_cbufs
> 1) {
1031 for (int c
= 1; c
< si_shader_ctx
->shader
->key
.ps
.nr_cbufs
; c
++) {
1032 si_llvm_init_export_args(bld_base
, d
, index
,
1033 V_008DFC_SQ_EXP_MRT
+ c
, args
);
1034 lp_build_intrinsic(base
->gallivm
->builder
,
1036 LLVMVoidTypeInContext(base
->gallivm
->context
),
1041 lp_build_intrinsic(base
->gallivm
->builder
,
1043 LLVMVoidTypeInContext(base
->gallivm
->context
),
1048 if (semantic_name
== TGSI_SEMANTIC_CLIPDIST
) {
1049 semantic_name
= TGSI_SEMANTIC_GENERIC
;
1050 goto handle_semantic
;
1054 if (depth_index
>= 0 || stencil_index
>= 0) {
1055 LLVMValueRef out_ptr
;
1058 /* Specify the target we are exporting */
1059 args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_MRTZ
);
1061 if (depth_index
>= 0) {
1062 out_ptr
= si_shader_ctx
->radeon_bld
.soa
.outputs
[depth_index
][2];
1063 args
[5] = LLVMBuildLoad(base
->gallivm
->builder
, out_ptr
, "");
1066 if (stencil_index
< 0) {
1073 if (stencil_index
>= 0) {
1074 out_ptr
= si_shader_ctx
->radeon_bld
.soa
.outputs
[stencil_index
][1];
1077 args
[6] = LLVMBuildLoad(base
->gallivm
->builder
, out_ptr
, "");
1078 /* Only setting the stencil component bit (0x2) here
1079 * breaks some stencil piglit tests
1083 if (depth_index
< 0)
1087 /* Specify which components to enable */
1088 args
[0] = lp_build_const_int32(base
->gallivm
, mask
);
1092 args
[4] = uint
->zero
;
1095 lp_build_intrinsic(base
->gallivm
->builder
,
1097 LLVMVoidTypeInContext(base
->gallivm
->context
),
1100 memcpy(last_args
, args
, sizeof(args
));
1103 if (si_shader_ctx
->type
== TGSI_PROCESSOR_VERTEX
) {
1104 unsigned pos_idx
= 0;
1106 /* We need to add the position output manually if it's missing. */
1107 if (!pos_args
[0][0]) {
1108 pos_args
[0][0] = lp_build_const_int32(base
->gallivm
, 0xf); /* writemask */
1109 pos_args
[0][1] = uint
->zero
; /* EXEC mask */
1110 pos_args
[0][2] = uint
->zero
; /* last export? */
1111 pos_args
[0][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
);
1112 pos_args
[0][4] = uint
->zero
; /* COMPR flag */
1113 pos_args
[0][5] = base
->zero
; /* X */
1114 pos_args
[0][6] = base
->zero
; /* Y */
1115 pos_args
[0][7] = base
->zero
; /* Z */
1116 pos_args
[0][8] = base
->one
; /* W */
1119 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1120 if (shader
->vs_out_misc_write
) {
1121 pos_args
[1][0] = lp_build_const_int32(base
->gallivm
, /* writemask */
1122 shader
->vs_out_point_size
|
1123 (shader
->vs_out_edgeflag
<< 1) |
1124 (shader
->vs_out_layer
<< 2));
1125 pos_args
[1][1] = uint
->zero
; /* EXEC mask */
1126 pos_args
[1][2] = uint
->zero
; /* last export? */
1127 pos_args
[1][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
+ 1);
1128 pos_args
[1][4] = uint
->zero
; /* COMPR flag */
1129 pos_args
[1][5] = base
->zero
; /* X */
1130 pos_args
[1][6] = base
->zero
; /* Y */
1131 pos_args
[1][7] = base
->zero
; /* Z */
1132 pos_args
[1][8] = base
->zero
; /* W */
1134 if (shader
->vs_out_point_size
) {
1135 pos_args
[1][5] = LLVMBuildLoad(base
->gallivm
->builder
,
1136 si_shader_ctx
->radeon_bld
.soa
.outputs
[psize_index
][0], "");
1139 if (shader
->vs_out_edgeflag
) {
1140 LLVMValueRef output
= LLVMBuildLoad(base
->gallivm
->builder
,
1141 si_shader_ctx
->radeon_bld
.soa
.outputs
[edgeflag_index
][0], "");
1143 /* The output is a float, but the hw expects an integer
1144 * with the first bit containing the edge flag. */
1145 output
= LLVMBuildFPToUI(base
->gallivm
->builder
, output
,
1146 bld_base
->uint_bld
.elem_type
, "");
1148 output
= lp_build_min(&bld_base
->int_bld
, output
, bld_base
->int_bld
.one
);
1150 /* The LLVM intrinsic expects a float. */
1151 pos_args
[1][6] = LLVMBuildBitCast(base
->gallivm
->builder
, output
,
1152 base
->elem_type
, "");
1155 if (shader
->vs_out_layer
) {
1156 pos_args
[1][7] = LLVMBuildLoad(base
->gallivm
->builder
,
1157 si_shader_ctx
->radeon_bld
.soa
.outputs
[layer_index
][0], "");
1161 for (i
= 0; i
< 4; i
++)
1163 shader
->nr_pos_exports
++;
1165 for (i
= 0; i
< 4; i
++) {
1166 if (!pos_args
[i
][0])
1169 /* Specify the target we are exporting */
1170 pos_args
[i
][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
+ pos_idx
++);
1172 if (pos_idx
== shader
->nr_pos_exports
)
1173 /* Specify that this is the last export */
1174 pos_args
[i
][2] = uint
->one
;
1176 lp_build_intrinsic(base
->gallivm
->builder
,
1178 LLVMVoidTypeInContext(base
->gallivm
->context
),
1182 if (!last_args
[0]) {
1183 /* Specify which components to enable */
1184 last_args
[0] = lp_build_const_int32(base
->gallivm
, 0x0);
1186 /* Specify the target we are exporting */
1187 last_args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_MRT
);
1189 /* Set COMPR flag to zero to export data as 32-bit */
1190 last_args
[4] = uint
->zero
;
1193 last_args
[5]= uint
->zero
;
1194 last_args
[6]= uint
->zero
;
1195 last_args
[7]= uint
->zero
;
1196 last_args
[8]= uint
->zero
;
1198 si_shader_ctx
->shader
->spi_shader_col_format
|=
1199 V_028714_SPI_SHADER_32_ABGR
;
1200 si_shader_ctx
->shader
->cb_shader_mask
|= S_02823C_OUTPUT0_ENABLE(0xf);
1203 /* Specify whether the EXEC mask represents the valid mask */
1204 last_args
[1] = uint
->one
;
1206 /* Specify that this is the last export */
1207 last_args
[2] = lp_build_const_int32(base
->gallivm
, 1);
1209 lp_build_intrinsic(base
->gallivm
->builder
,
1211 LLVMVoidTypeInContext(base
->gallivm
->context
),
1216 static const struct lp_build_tgsi_action txf_action
;
1218 static void build_tex_intrinsic(const struct lp_build_tgsi_action
* action
,
1219 struct lp_build_tgsi_context
* bld_base
,
1220 struct lp_build_emit_data
* emit_data
);
1222 static void tex_fetch_args(
1223 struct lp_build_tgsi_context
* bld_base
,
1224 struct lp_build_emit_data
* emit_data
)
1226 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
1227 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1228 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
1229 unsigned opcode
= inst
->Instruction
.Opcode
;
1230 unsigned target
= inst
->Texture
.Texture
;
1231 LLVMValueRef coords
[4];
1232 LLVMValueRef address
[16];
1234 unsigned num_coords
= tgsi_util_get_texture_coord_dim(target
, &ref_pos
);
1237 unsigned sampler_src
= emit_data
->inst
->Instruction
.NumSrcRegs
- 1;
1238 unsigned sampler_index
= emit_data
->inst
->Src
[sampler_src
].Register
.Index
;
1240 if (target
== TGSI_TEXTURE_BUFFER
) {
1241 LLVMTypeRef i128
= LLVMIntTypeInContext(gallivm
->context
, 128);
1242 LLVMTypeRef v2i128
= LLVMVectorType(i128
, 2);
1243 LLVMTypeRef i8
= LLVMInt8TypeInContext(gallivm
->context
);
1244 LLVMTypeRef v16i8
= LLVMVectorType(i8
, 16);
1246 /* Truncate v32i8 to v16i8. */
1247 LLVMValueRef res
= si_shader_ctx
->resources
[sampler_index
];
1248 res
= LLVMBuildBitCast(gallivm
->builder
, res
, v2i128
, "");
1249 res
= LLVMBuildExtractElement(gallivm
->builder
, res
, bld_base
->uint_bld
.zero
, "");
1250 res
= LLVMBuildBitCast(gallivm
->builder
, res
, v16i8
, "");
1252 emit_data
->dst_type
= LLVMVectorType(bld_base
->base
.elem_type
, 4);
1253 emit_data
->args
[0] = res
;
1254 emit_data
->args
[1] = bld_base
->uint_bld
.zero
;
1255 emit_data
->args
[2] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, 0);
1256 emit_data
->arg_count
= 3;
1260 /* Fetch and project texture coordinates */
1261 coords
[3] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_W
);
1262 for (chan
= 0; chan
< 3; chan
++ ) {
1263 coords
[chan
] = lp_build_emit_fetch(bld_base
,
1266 if (opcode
== TGSI_OPCODE_TXP
)
1267 coords
[chan
] = lp_build_emit_llvm_binary(bld_base
,
1273 if (opcode
== TGSI_OPCODE_TXP
)
1274 coords
[3] = bld_base
->base
.one
;
1276 /* Pack LOD bias value */
1277 if (opcode
== TGSI_OPCODE_TXB
)
1278 address
[count
++] = coords
[3];
1280 if (target
== TGSI_TEXTURE_CUBE
|| target
== TGSI_TEXTURE_SHADOWCUBE
)
1281 radeon_llvm_emit_prepare_cube_coords(bld_base
, emit_data
, coords
);
1283 /* Pack depth comparison value */
1285 case TGSI_TEXTURE_SHADOW1D
:
1286 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1287 case TGSI_TEXTURE_SHADOW2D
:
1288 case TGSI_TEXTURE_SHADOWRECT
:
1289 case TGSI_TEXTURE_SHADOWCUBE
:
1290 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1291 assert(ref_pos
>= 0);
1292 address
[count
++] = coords
[ref_pos
];
1294 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
1295 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, 0);
1298 /* Pack user derivatives */
1299 if (opcode
== TGSI_OPCODE_TXD
) {
1300 for (chan
= 0; chan
< 2; chan
++) {
1301 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, chan
);
1303 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 2, chan
);
1307 /* Pack texture coordinates */
1308 address
[count
++] = coords
[0];
1310 address
[count
++] = coords
[1];
1312 address
[count
++] = coords
[2];
1314 /* Pack LOD or sample index */
1315 if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXF
)
1316 address
[count
++] = coords
[3];
1319 assert(!"Cannot handle more than 16 texture address parameters");
1323 for (chan
= 0; chan
< count
; chan
++ ) {
1324 address
[chan
] = LLVMBuildBitCast(gallivm
->builder
,
1326 LLVMInt32TypeInContext(gallivm
->context
),
1330 /* Adjust the sample index according to FMASK.
1332 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1333 * which is the identity mapping. Each nibble says which physical sample
1334 * should be fetched to get that sample.
1336 * For example, 0x11111100 means there are only 2 samples stored and
1337 * the second sample covers 3/4 of the pixel. When reading samples 0
1338 * and 1, return physical sample 0 (determined by the first two 0s
1339 * in FMASK), otherwise return physical sample 1.
1341 * The sample index should be adjusted as follows:
1342 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1344 if (target
== TGSI_TEXTURE_2D_MSAA
||
1345 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1346 struct lp_build_context
*uint_bld
= &bld_base
->uint_bld
;
1347 struct lp_build_emit_data txf_emit_data
= *emit_data
;
1348 LLVMValueRef txf_address
[4];
1349 unsigned txf_count
= count
;
1351 memcpy(txf_address
, address
, sizeof(txf_address
));
1353 if (target
== TGSI_TEXTURE_2D_MSAA
) {
1354 txf_address
[2] = bld_base
->uint_bld
.zero
;
1356 txf_address
[3] = bld_base
->uint_bld
.zero
;
1358 /* Pad to a power-of-two size. */
1359 while (txf_count
< util_next_power_of_two(txf_count
))
1360 txf_address
[txf_count
++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm
->context
));
1362 /* Read FMASK using TXF. */
1363 txf_emit_data
.chan
= 0;
1364 txf_emit_data
.dst_type
= LLVMVectorType(
1365 LLVMInt32TypeInContext(bld_base
->base
.gallivm
->context
), 4);
1366 txf_emit_data
.args
[0] = lp_build_gather_values(gallivm
, txf_address
, txf_count
);
1367 txf_emit_data
.args
[1] = si_shader_ctx
->resources
[FMASK_TEX_OFFSET
+ sampler_index
];
1368 txf_emit_data
.args
[2] = lp_build_const_int32(bld_base
->base
.gallivm
,
1369 target
== TGSI_TEXTURE_2D_MSAA
? TGSI_TEXTURE_2D
: TGSI_TEXTURE_2D_ARRAY
);
1370 txf_emit_data
.arg_count
= 3;
1372 build_tex_intrinsic(&txf_action
, bld_base
, &txf_emit_data
);
1374 /* Initialize some constants. */
1375 LLVMValueRef four
= LLVMConstInt(uint_bld
->elem_type
, 4, 0);
1376 LLVMValueRef F
= LLVMConstInt(uint_bld
->elem_type
, 0xF, 0);
1378 /* Apply the formula. */
1379 LLVMValueRef fmask
=
1380 LLVMBuildExtractElement(gallivm
->builder
,
1381 txf_emit_data
.output
[0],
1382 uint_bld
->zero
, "");
1384 unsigned sample_chan
= target
== TGSI_TEXTURE_2D_MSAA
? 2 : 3;
1386 LLVMValueRef sample_index4
=
1387 LLVMBuildMul(gallivm
->builder
, address
[sample_chan
], four
, "");
1389 LLVMValueRef shifted_fmask
=
1390 LLVMBuildLShr(gallivm
->builder
, fmask
, sample_index4
, "");
1392 LLVMValueRef final_sample
=
1393 LLVMBuildAnd(gallivm
->builder
, shifted_fmask
, F
, "");
1395 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1396 * resource descriptor is 0 (invalid),
1398 LLVMValueRef fmask_desc
=
1399 LLVMBuildBitCast(gallivm
->builder
,
1400 si_shader_ctx
->resources
[FMASK_TEX_OFFSET
+ sampler_index
],
1401 LLVMVectorType(uint_bld
->elem_type
, 8), "");
1403 LLVMValueRef fmask_word1
=
1404 LLVMBuildExtractElement(gallivm
->builder
, fmask_desc
,
1407 LLVMValueRef word1_is_nonzero
=
1408 LLVMBuildICmp(gallivm
->builder
, LLVMIntNE
,
1409 fmask_word1
, uint_bld
->zero
, "");
1411 /* Replace the MSAA sample index. */
1412 address
[sample_chan
] =
1413 LLVMBuildSelect(gallivm
->builder
, word1_is_nonzero
,
1414 final_sample
, address
[sample_chan
], "");
1418 emit_data
->args
[1] = si_shader_ctx
->resources
[sampler_index
];
1420 if (opcode
== TGSI_OPCODE_TXF
) {
1421 /* add tex offsets */
1422 if (inst
->Texture
.NumOffsets
) {
1423 struct lp_build_context
*uint_bld
= &bld_base
->uint_bld
;
1424 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
1425 const struct tgsi_texture_offset
* off
= inst
->TexOffsets
;
1427 assert(inst
->Texture
.NumOffsets
== 1);
1430 case TGSI_TEXTURE_3D
:
1431 address
[2] = lp_build_add(uint_bld
, address
[2],
1432 bld
->immediates
[off
->Index
][off
->SwizzleZ
]);
1434 case TGSI_TEXTURE_2D
:
1435 case TGSI_TEXTURE_SHADOW2D
:
1436 case TGSI_TEXTURE_RECT
:
1437 case TGSI_TEXTURE_SHADOWRECT
:
1438 case TGSI_TEXTURE_2D_ARRAY
:
1439 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1441 lp_build_add(uint_bld
, address
[1],
1442 bld
->immediates
[off
->Index
][off
->SwizzleY
]);
1444 case TGSI_TEXTURE_1D
:
1445 case TGSI_TEXTURE_SHADOW1D
:
1446 case TGSI_TEXTURE_1D_ARRAY
:
1447 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1449 lp_build_add(uint_bld
, address
[0],
1450 bld
->immediates
[off
->Index
][off
->SwizzleX
]);
1452 /* texture offsets do not apply to other texture targets */
1456 emit_data
->dst_type
= LLVMVectorType(
1457 LLVMInt32TypeInContext(bld_base
->base
.gallivm
->context
),
1460 emit_data
->arg_count
= 3;
1463 emit_data
->args
[2] = si_shader_ctx
->samplers
[sampler_index
];
1465 emit_data
->dst_type
= LLVMVectorType(
1466 LLVMFloatTypeInContext(bld_base
->base
.gallivm
->context
),
1469 emit_data
->arg_count
= 4;
1473 emit_data
->args
[emit_data
->arg_count
- 1] =
1474 lp_build_const_int32(bld_base
->base
.gallivm
, target
);
1476 /* Pad to power of two vector */
1477 while (count
< util_next_power_of_two(count
))
1478 address
[count
++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm
->context
));
1480 emit_data
->args
[0] = lp_build_gather_values(gallivm
, address
, count
);
1483 static void build_tex_intrinsic(const struct lp_build_tgsi_action
* action
,
1484 struct lp_build_tgsi_context
* bld_base
,
1485 struct lp_build_emit_data
* emit_data
)
1487 struct lp_build_context
* base
= &bld_base
->base
;
1488 char intr_name
[127];
1490 if (emit_data
->inst
->Texture
.Texture
== TGSI_TEXTURE_BUFFER
) {
1491 emit_data
->output
[emit_data
->chan
] = build_intrinsic(
1492 base
->gallivm
->builder
,
1493 "llvm.SI.vs.load.input", emit_data
->dst_type
,
1494 emit_data
->args
, emit_data
->arg_count
,
1495 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
1499 sprintf(intr_name
, "%sv%ui32", action
->intr_name
,
1500 LLVMGetVectorSize(LLVMTypeOf(emit_data
->args
[0])));
1502 emit_data
->output
[emit_data
->chan
] = build_intrinsic(
1503 base
->gallivm
->builder
, intr_name
, emit_data
->dst_type
,
1504 emit_data
->args
, emit_data
->arg_count
,
1505 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
1508 static void txq_fetch_args(
1509 struct lp_build_tgsi_context
* bld_base
,
1510 struct lp_build_emit_data
* emit_data
)
1512 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
1513 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1514 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1516 if (inst
->Texture
.Texture
== TGSI_TEXTURE_BUFFER
) {
1517 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
1518 LLVMTypeRef v8i32
= LLVMVectorType(i32
, 8);
1520 /* Read the size from the buffer descriptor directly. */
1521 LLVMValueRef size
= si_shader_ctx
->resources
[inst
->Src
[1].Register
.Index
];
1522 size
= LLVMBuildBitCast(gallivm
->builder
, size
, v8i32
, "");
1523 size
= LLVMBuildExtractElement(gallivm
->builder
, size
,
1524 lp_build_const_int32(gallivm
, 2), "");
1525 emit_data
->args
[0] = size
;
1530 emit_data
->args
[0] = lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_X
);
1533 emit_data
->args
[1] = si_shader_ctx
->resources
[inst
->Src
[1].Register
.Index
];
1536 emit_data
->args
[2] = lp_build_const_int32(bld_base
->base
.gallivm
,
1537 inst
->Texture
.Texture
);
1539 emit_data
->arg_count
= 3;
1541 emit_data
->dst_type
= LLVMVectorType(
1542 LLVMInt32TypeInContext(bld_base
->base
.gallivm
->context
),
1546 static void build_txq_intrinsic(const struct lp_build_tgsi_action
* action
,
1547 struct lp_build_tgsi_context
* bld_base
,
1548 struct lp_build_emit_data
* emit_data
)
1550 if (emit_data
->inst
->Texture
.Texture
== TGSI_TEXTURE_BUFFER
) {
1551 /* Just return the buffer size. */
1552 emit_data
->output
[emit_data
->chan
] = emit_data
->args
[0];
1556 build_tgsi_intrinsic_nomem(action
, bld_base
, emit_data
);
1559 #if HAVE_LLVM >= 0x0304
1561 static void si_llvm_emit_ddxy(
1562 const struct lp_build_tgsi_action
* action
,
1563 struct lp_build_tgsi_context
* bld_base
,
1564 struct lp_build_emit_data
* emit_data
)
1566 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
1567 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1568 struct lp_build_context
* base
= &bld_base
->base
;
1569 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1570 unsigned opcode
= inst
->Instruction
.Opcode
;
1571 LLVMValueRef indices
[2];
1572 LLVMValueRef store_ptr
, load_ptr0
, load_ptr1
;
1573 LLVMValueRef tl
, trbl
, result
[4];
1575 unsigned swizzle
[4];
1578 i32
= LLVMInt32TypeInContext(gallivm
->context
);
1580 indices
[0] = bld_base
->uint_bld
.zero
;
1581 indices
[1] = build_intrinsic(gallivm
->builder
, "llvm.SI.tid", i32
,
1582 NULL
, 0, LLVMReadNoneAttribute
);
1583 store_ptr
= LLVMBuildGEP(gallivm
->builder
, si_shader_ctx
->ddxy_lds
,
1586 indices
[1] = LLVMBuildAnd(gallivm
->builder
, indices
[1],
1587 lp_build_const_int32(gallivm
, 0xfffffffc), "");
1588 load_ptr0
= LLVMBuildGEP(gallivm
->builder
, si_shader_ctx
->ddxy_lds
,
1591 indices
[1] = LLVMBuildAdd(gallivm
->builder
, indices
[1],
1592 lp_build_const_int32(gallivm
,
1593 opcode
== TGSI_OPCODE_DDX
? 1 : 2),
1595 load_ptr1
= LLVMBuildGEP(gallivm
->builder
, si_shader_ctx
->ddxy_lds
,
1598 for (c
= 0; c
< 4; ++c
) {
1601 swizzle
[c
] = tgsi_util_get_full_src_register_swizzle(&inst
->Src
[0], c
);
1602 for (i
= 0; i
< c
; ++i
) {
1603 if (swizzle
[i
] == swizzle
[c
]) {
1604 result
[c
] = result
[i
];
1611 LLVMBuildStore(gallivm
->builder
,
1612 LLVMBuildBitCast(gallivm
->builder
,
1613 lp_build_emit_fetch(bld_base
, inst
, 0, c
),
1617 tl
= LLVMBuildLoad(gallivm
->builder
, load_ptr0
, "");
1618 tl
= LLVMBuildBitCast(gallivm
->builder
, tl
, base
->elem_type
, "");
1620 trbl
= LLVMBuildLoad(gallivm
->builder
, load_ptr1
, "");
1621 trbl
= LLVMBuildBitCast(gallivm
->builder
, trbl
, base
->elem_type
, "");
1623 result
[c
] = LLVMBuildFSub(gallivm
->builder
, trbl
, tl
, "");
1626 emit_data
->output
[0] = lp_build_gather_values(gallivm
, result
, 4);
1629 #endif /* HAVE_LLVM >= 0x0304 */
1631 static const struct lp_build_tgsi_action tex_action
= {
1632 .fetch_args
= tex_fetch_args
,
1633 .emit
= build_tex_intrinsic
,
1634 .intr_name
= "llvm.SI.sample."
1637 static const struct lp_build_tgsi_action txb_action
= {
1638 .fetch_args
= tex_fetch_args
,
1639 .emit
= build_tex_intrinsic
,
1640 .intr_name
= "llvm.SI.sampleb."
1643 #if HAVE_LLVM >= 0x0304
1644 static const struct lp_build_tgsi_action txd_action
= {
1645 .fetch_args
= tex_fetch_args
,
1646 .emit
= build_tex_intrinsic
,
1647 .intr_name
= "llvm.SI.sampled."
1651 static const struct lp_build_tgsi_action txf_action
= {
1652 .fetch_args
= tex_fetch_args
,
1653 .emit
= build_tex_intrinsic
,
1654 .intr_name
= "llvm.SI.imageload."
1657 static const struct lp_build_tgsi_action txl_action
= {
1658 .fetch_args
= tex_fetch_args
,
1659 .emit
= build_tex_intrinsic
,
1660 .intr_name
= "llvm.SI.samplel."
1663 static const struct lp_build_tgsi_action txq_action
= {
1664 .fetch_args
= txq_fetch_args
,
1665 .emit
= build_txq_intrinsic
,
1666 .intr_name
= "llvm.SI.resinfo"
1669 static void create_meta_data(struct si_shader_context
*si_shader_ctx
)
1671 struct gallivm_state
*gallivm
= si_shader_ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
1672 LLVMValueRef args
[3];
1674 args
[0] = LLVMMDStringInContext(gallivm
->context
, "const", 5);
1676 args
[2] = lp_build_const_int32(gallivm
, 1);
1678 si_shader_ctx
->const_md
= LLVMMDNodeInContext(gallivm
->context
, args
, 3);
1681 static void create_function(struct si_shader_context
*si_shader_ctx
)
1683 struct lp_build_tgsi_context
*bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
1684 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1685 LLVMTypeRef params
[21], f32
, i8
, i32
, v2i32
, v3i32
;
1686 unsigned i
, last_sgpr
, num_params
;
1688 i8
= LLVMInt8TypeInContext(gallivm
->context
);
1689 i32
= LLVMInt32TypeInContext(gallivm
->context
);
1690 f32
= LLVMFloatTypeInContext(gallivm
->context
);
1691 v2i32
= LLVMVectorType(i32
, 2);
1692 v3i32
= LLVMVectorType(i32
, 3);
1694 params
[SI_PARAM_CONST
] = LLVMPointerType(
1695 LLVMArrayType(LLVMVectorType(i8
, 16), NUM_CONST_BUFFERS
), CONST_ADDR_SPACE
);
1696 /* We assume at most 16 textures per program at the moment.
1697 * This need probably need to be changed to support bindless textures */
1698 params
[SI_PARAM_SAMPLER
] = LLVMPointerType(
1699 LLVMArrayType(LLVMVectorType(i8
, 16), NUM_SAMPLER_VIEWS
), CONST_ADDR_SPACE
);
1700 params
[SI_PARAM_RESOURCE
] = LLVMPointerType(
1701 LLVMArrayType(LLVMVectorType(i8
, 32), NUM_SAMPLER_STATES
), CONST_ADDR_SPACE
);
1703 switch (si_shader_ctx
->type
) {
1704 case TGSI_PROCESSOR_VERTEX
:
1705 params
[SI_PARAM_VERTEX_BUFFER
] = params
[SI_PARAM_CONST
];
1706 params
[SI_PARAM_SO_BUFFER
] = params
[SI_PARAM_CONST
];
1707 params
[SI_PARAM_START_INSTANCE
] = i32
;
1708 num_params
= SI_PARAM_START_INSTANCE
+1;
1710 /* The locations of the other parameters are assigned dynamically. */
1712 /* Streamout SGPRs. */
1713 if (si_shader_ctx
->shader
->selector
->so
.num_outputs
) {
1714 params
[si_shader_ctx
->param_streamout_config
= num_params
++] = i32
;
1715 params
[si_shader_ctx
->param_streamout_write_index
= num_params
++] = i32
;
1717 /* A streamout buffer offset is loaded if the stride is non-zero. */
1718 for (i
= 0; i
< 4; i
++) {
1719 if (!si_shader_ctx
->shader
->selector
->so
.stride
[i
])
1722 params
[si_shader_ctx
->param_streamout_offset
[i
] = num_params
++] = i32
;
1725 last_sgpr
= num_params
-1;
1728 params
[si_shader_ctx
->param_vertex_id
= num_params
++] = i32
;
1729 params
[num_params
++] = i32
; /* unused*/
1730 params
[num_params
++] = i32
; /* unused */
1731 params
[si_shader_ctx
->param_instance_id
= num_params
++] = i32
;
1734 case TGSI_PROCESSOR_FRAGMENT
:
1735 params
[SI_PARAM_ALPHA_REF
] = f32
;
1736 params
[SI_PARAM_PRIM_MASK
] = i32
;
1737 last_sgpr
= SI_PARAM_PRIM_MASK
;
1738 params
[SI_PARAM_PERSP_SAMPLE
] = v2i32
;
1739 params
[SI_PARAM_PERSP_CENTER
] = v2i32
;
1740 params
[SI_PARAM_PERSP_CENTROID
] = v2i32
;
1741 params
[SI_PARAM_PERSP_PULL_MODEL
] = v3i32
;
1742 params
[SI_PARAM_LINEAR_SAMPLE
] = v2i32
;
1743 params
[SI_PARAM_LINEAR_CENTER
] = v2i32
;
1744 params
[SI_PARAM_LINEAR_CENTROID
] = v2i32
;
1745 params
[SI_PARAM_LINE_STIPPLE_TEX
] = f32
;
1746 params
[SI_PARAM_POS_X_FLOAT
] = f32
;
1747 params
[SI_PARAM_POS_Y_FLOAT
] = f32
;
1748 params
[SI_PARAM_POS_Z_FLOAT
] = f32
;
1749 params
[SI_PARAM_POS_W_FLOAT
] = f32
;
1750 params
[SI_PARAM_FRONT_FACE
] = f32
;
1751 params
[SI_PARAM_ANCILLARY
] = f32
;
1752 params
[SI_PARAM_SAMPLE_COVERAGE
] = f32
;
1753 params
[SI_PARAM_POS_FIXED_PT
] = f32
;
1754 num_params
= SI_PARAM_POS_FIXED_PT
+1;
1758 assert(0 && "unimplemented shader");
1762 assert(num_params
<= Elements(params
));
1763 radeon_llvm_create_func(&si_shader_ctx
->radeon_bld
, params
, num_params
);
1764 radeon_llvm_shader_type(si_shader_ctx
->radeon_bld
.main_fn
, si_shader_ctx
->type
);
1766 for (i
= 0; i
<= last_sgpr
; ++i
) {
1767 LLVMValueRef P
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, i
);
1770 LLVMAddAttribute(P
, LLVMInRegAttribute
);
1772 #if HAVE_LLVM >= 0x0304
1773 /* We tell llvm that array inputs are passed by value to allow Sinking pass
1774 * to move load. Inputs are constant so this is fine. */
1775 case SI_PARAM_CONST
:
1776 case SI_PARAM_SAMPLER
:
1777 case SI_PARAM_RESOURCE
:
1778 LLVMAddAttribute(P
, LLVMByValAttribute
);
1784 #if HAVE_LLVM >= 0x0304
1785 if (bld_base
->info
->opcode_count
[TGSI_OPCODE_DDX
] > 0 ||
1786 bld_base
->info
->opcode_count
[TGSI_OPCODE_DDY
] > 0)
1787 si_shader_ctx
->ddxy_lds
=
1788 LLVMAddGlobalInAddressSpace(gallivm
->module
,
1789 LLVMArrayType(i32
, 64),
1795 static void preload_constants(struct si_shader_context
*si_shader_ctx
)
1797 struct lp_build_tgsi_context
* bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
1798 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
1799 const struct tgsi_shader_info
* info
= bld_base
->info
;
1801 LLVMValueRef ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_CONST
);
1803 for (buf
= 0; buf
< NUM_CONST_BUFFERS
; buf
++) {
1804 unsigned i
, num_const
= info
->const_file_max
[buf
] + 1;
1809 /* Allocate space for the constant values */
1810 si_shader_ctx
->constants
[buf
] = CALLOC(num_const
* 4, sizeof(LLVMValueRef
));
1812 /* Load the resource descriptor */
1813 si_shader_ctx
->const_resource
[buf
] =
1814 build_indexed_load(si_shader_ctx
, ptr
, lp_build_const_int32(gallivm
, buf
));
1816 /* Load the constants, we rely on the code sinking to do the rest */
1817 for (i
= 0; i
< num_const
* 4; ++i
) {
1818 LLVMValueRef args
[2] = {
1819 si_shader_ctx
->const_resource
[buf
],
1820 lp_build_const_int32(gallivm
, i
* 4)
1822 si_shader_ctx
->constants
[buf
][i
] =
1823 build_intrinsic(gallivm
->builder
, "llvm.SI.load.const",
1824 bld_base
->base
.elem_type
, args
, 2,
1825 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
1830 static void preload_samplers(struct si_shader_context
*si_shader_ctx
)
1832 struct lp_build_tgsi_context
* bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
1833 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
1834 const struct tgsi_shader_info
* info
= bld_base
->info
;
1836 unsigned i
, num_samplers
= info
->file_max
[TGSI_FILE_SAMPLER
] + 1;
1838 LLVMValueRef res_ptr
, samp_ptr
;
1839 LLVMValueRef offset
;
1841 if (num_samplers
== 0)
1844 /* Allocate space for the values */
1845 si_shader_ctx
->resources
= CALLOC(NUM_SAMPLER_VIEWS
, sizeof(LLVMValueRef
));
1846 si_shader_ctx
->samplers
= CALLOC(num_samplers
, sizeof(LLVMValueRef
));
1848 res_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_RESOURCE
);
1849 samp_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_SAMPLER
);
1851 /* Load the resources and samplers, we rely on the code sinking to do the rest */
1852 for (i
= 0; i
< num_samplers
; ++i
) {
1854 offset
= lp_build_const_int32(gallivm
, i
);
1855 si_shader_ctx
->resources
[i
] = build_indexed_load(si_shader_ctx
, res_ptr
, offset
);
1858 offset
= lp_build_const_int32(gallivm
, i
);
1859 si_shader_ctx
->samplers
[i
] = build_indexed_load(si_shader_ctx
, samp_ptr
, offset
);
1861 /* FMASK resource */
1862 if (info
->is_msaa_sampler
[i
]) {
1863 offset
= lp_build_const_int32(gallivm
, FMASK_TEX_OFFSET
+ i
);
1864 si_shader_ctx
->resources
[FMASK_TEX_OFFSET
+ i
] =
1865 build_indexed_load(si_shader_ctx
, res_ptr
, offset
);
1870 static void preload_streamout_buffers(struct si_shader_context
*si_shader_ctx
)
1872 struct lp_build_tgsi_context
* bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
1873 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
1876 if (!si_shader_ctx
->shader
->selector
->so
.num_outputs
)
1879 LLVMValueRef buf_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
1880 SI_PARAM_SO_BUFFER
);
1882 /* Load the resources, we rely on the code sinking to do the rest */
1883 for (i
= 0; i
< 4; ++i
) {
1884 if (si_shader_ctx
->shader
->selector
->so
.stride
[i
]) {
1885 LLVMValueRef offset
= lp_build_const_int32(gallivm
, i
);
1887 si_shader_ctx
->so_buffers
[i
] = build_indexed_load(si_shader_ctx
, buf_ptr
, offset
);
1892 int si_compile_llvm(struct si_context
*sctx
, struct si_pipe_shader
*shader
,
1897 struct radeon_llvm_binary binary
;
1898 bool dump
= r600_can_dump_shader(&sctx
->screen
->b
,
1899 shader
->selector
? shader
->selector
->tokens
: NULL
);
1900 memset(&binary
, 0, sizeof(binary
));
1901 radeon_llvm_compile(mod
, &binary
,
1902 si_get_llvm_processor_name(sctx
->screen
->b
.family
), dump
);
1903 if (dump
&& ! binary
.disassembled
) {
1904 fprintf(stderr
, "SI CODE:\n");
1905 for (i
= 0; i
< binary
.code_size
; i
+=4 ) {
1906 fprintf(stderr
, "%02x%02x%02x%02x\n", binary
.code
[i
+ 3],
1907 binary
.code
[i
+ 2], binary
.code
[i
+ 1],
1912 /* XXX: We may be able to emit some of these values directly rather than
1913 * extracting fields to be emitted later.
1915 for (i
= 0; i
< binary
.config_size
; i
+= 8) {
1916 unsigned reg
= util_le32_to_cpu(*(uint32_t*)(binary
.config
+ i
));
1917 unsigned value
= util_le32_to_cpu(*(uint32_t*)(binary
.config
+ i
+ 4));
1919 case R_00B028_SPI_SHADER_PGM_RSRC1_PS
:
1920 case R_00B128_SPI_SHADER_PGM_RSRC1_VS
:
1921 case R_00B228_SPI_SHADER_PGM_RSRC1_GS
:
1922 case R_00B848_COMPUTE_PGM_RSRC1
:
1923 shader
->num_sgprs
= (G_00B028_SGPRS(value
) + 1) * 8;
1924 shader
->num_vgprs
= (G_00B028_VGPRS(value
) + 1) * 4;
1926 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS
:
1927 shader
->lds_size
= G_00B02C_EXTRA_LDS_SIZE(value
);
1929 case R_00B84C_COMPUTE_PGM_RSRC2
:
1930 shader
->lds_size
= G_00B84C_LDS_SIZE(value
);
1932 case R_0286CC_SPI_PS_INPUT_ENA
:
1933 shader
->spi_ps_input_ena
= value
;
1936 fprintf(stderr
, "Warning: Compiler emitted unknown "
1937 "config register: 0x%x\n", reg
);
1942 /* copy new shader */
1943 r600_resource_reference(&shader
->bo
, NULL
);
1944 shader
->bo
= si_resource_create_custom(sctx
->b
.b
.screen
, PIPE_USAGE_IMMUTABLE
,
1946 if (shader
->bo
== NULL
) {
1950 ptr
= (uint32_t*)sctx
->b
.ws
->buffer_map(shader
->bo
->cs_buf
, sctx
->b
.rings
.gfx
.cs
, PIPE_TRANSFER_WRITE
);
1951 if (0 /*SI_BIG_ENDIAN*/) {
1952 for (i
= 0; i
< binary
.code_size
/ 4; ++i
) {
1953 ptr
[i
] = util_bswap32(*(uint32_t*)(binary
.code
+ i
*4));
1956 memcpy(ptr
, binary
.code
, binary
.code_size
);
1958 sctx
->b
.ws
->buffer_unmap(shader
->bo
->cs_buf
);
1961 free(binary
.config
);
1966 int si_pipe_shader_create(
1967 struct pipe_context
*ctx
,
1968 struct si_pipe_shader
*shader
)
1970 struct si_context
*sctx
= (struct si_context
*)ctx
;
1971 struct si_pipe_shader_selector
*sel
= shader
->selector
;
1972 struct si_shader_context si_shader_ctx
;
1973 struct tgsi_shader_info shader_info
;
1974 struct lp_build_tgsi_context
* bld_base
;
1977 bool dump
= r600_can_dump_shader(&sctx
->screen
->b
, shader
->selector
->tokens
);
1979 assert(shader
->shader
.noutput
== 0);
1980 assert(shader
->shader
.ninterp
== 0);
1981 assert(shader
->shader
.ninput
== 0);
1983 memset(&si_shader_ctx
, 0, sizeof(si_shader_ctx
));
1984 radeon_llvm_context_init(&si_shader_ctx
.radeon_bld
);
1985 bld_base
= &si_shader_ctx
.radeon_bld
.soa
.bld_base
;
1987 tgsi_scan_shader(sel
->tokens
, &shader_info
);
1989 shader
->shader
.uses_kill
= shader_info
.uses_kill
;
1990 shader
->shader
.uses_instanceid
= shader_info
.uses_instanceid
;
1991 bld_base
->info
= &shader_info
;
1992 bld_base
->emit_fetch_funcs
[TGSI_FILE_CONSTANT
] = fetch_constant
;
1993 bld_base
->emit_epilogue
= si_llvm_emit_epilogue
;
1995 bld_base
->op_actions
[TGSI_OPCODE_TEX
] = tex_action
;
1996 bld_base
->op_actions
[TGSI_OPCODE_TXB
] = txb_action
;
1997 #if HAVE_LLVM >= 0x0304
1998 bld_base
->op_actions
[TGSI_OPCODE_TXD
] = txd_action
;
2000 bld_base
->op_actions
[TGSI_OPCODE_TXF
] = txf_action
;
2001 bld_base
->op_actions
[TGSI_OPCODE_TXL
] = txl_action
;
2002 bld_base
->op_actions
[TGSI_OPCODE_TXP
] = tex_action
;
2003 bld_base
->op_actions
[TGSI_OPCODE_TXQ
] = txq_action
;
2005 #if HAVE_LLVM >= 0x0304
2006 bld_base
->op_actions
[TGSI_OPCODE_DDX
].emit
= si_llvm_emit_ddxy
;
2007 bld_base
->op_actions
[TGSI_OPCODE_DDY
].emit
= si_llvm_emit_ddxy
;
2010 si_shader_ctx
.radeon_bld
.load_input
= declare_input
;
2011 si_shader_ctx
.radeon_bld
.load_system_value
= declare_system_value
;
2012 si_shader_ctx
.tokens
= sel
->tokens
;
2013 tgsi_parse_init(&si_shader_ctx
.parse
, si_shader_ctx
.tokens
);
2014 si_shader_ctx
.shader
= shader
;
2015 si_shader_ctx
.type
= si_shader_ctx
.parse
.FullHeader
.Processor
.Processor
;
2017 create_meta_data(&si_shader_ctx
);
2018 create_function(&si_shader_ctx
);
2019 preload_constants(&si_shader_ctx
);
2020 preload_samplers(&si_shader_ctx
);
2021 preload_streamout_buffers(&si_shader_ctx
);
2023 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2024 * conversion fails. */
2026 tgsi_dump(sel
->tokens
, 0);
2027 si_dump_streamout(&sel
->so
);
2030 if (!lp_build_tgsi_llvm(bld_base
, sel
->tokens
)) {
2031 fprintf(stderr
, "Failed to translate shader from TGSI to LLVM\n");
2032 for (int i
= 0; i
< NUM_CONST_BUFFERS
; i
++)
2033 FREE(si_shader_ctx
.constants
[i
]);
2034 FREE(si_shader_ctx
.resources
);
2035 FREE(si_shader_ctx
.samplers
);
2039 radeon_llvm_finalize_module(&si_shader_ctx
.radeon_bld
);
2041 mod
= bld_base
->base
.gallivm
->module
;
2042 r
= si_compile_llvm(sctx
, shader
, mod
);
2044 radeon_llvm_dispose(&si_shader_ctx
.radeon_bld
);
2045 tgsi_parse_free(&si_shader_ctx
.parse
);
2047 for (int i
= 0; i
< NUM_CONST_BUFFERS
; i
++)
2048 FREE(si_shader_ctx
.constants
[i
]);
2049 FREE(si_shader_ctx
.resources
);
2050 FREE(si_shader_ctx
.samplers
);
2055 void si_pipe_shader_destroy(struct pipe_context
*ctx
, struct si_pipe_shader
*shader
)
2057 r600_resource_reference(&shader
->bo
, NULL
);