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radeonsi/nir: emit FS outputs
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "util/u_memory.h"
37 #include "util/u_string.h"
38 #include "tgsi/tgsi_build.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_exp_param.h"
45 #include "si_shader_internal.h"
46 #include "si_pipe.h"
47 #include "sid.h"
48
49 #include "compiler/nir/nir.h"
50
51 static const char *scratch_rsrc_dword0_symbol =
52 "SCRATCH_RSRC_DWORD0";
53
54 static const char *scratch_rsrc_dword1_symbol =
55 "SCRATCH_RSRC_DWORD1";
56
57 struct si_shader_output_values
58 {
59 LLVMValueRef values[4];
60 unsigned semantic_name;
61 unsigned semantic_index;
62 ubyte vertex_stream[4];
63 };
64
65 /**
66 * Used to collect types and other info about arguments of the LLVM function
67 * before the function is created.
68 */
69 struct si_function_info {
70 LLVMTypeRef types[100];
71 LLVMValueRef *assign[100];
72 unsigned num_sgpr_params;
73 unsigned num_params;
74 };
75
76 enum si_arg_regfile {
77 ARG_SGPR,
78 ARG_VGPR
79 };
80
81 static void si_init_shader_ctx(struct si_shader_context *ctx,
82 struct si_screen *sscreen,
83 LLVMTargetMachineRef tm);
84
85 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
86 struct lp_build_tgsi_context *bld_base,
87 struct lp_build_emit_data *emit_data);
88
89 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
90 FILE *f);
91
92 static unsigned llvm_get_type_size(LLVMTypeRef type);
93
94 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
95 union si_shader_part_key *key);
96 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
97 union si_shader_part_key *key);
98 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
99 union si_shader_part_key *key);
100 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
101 union si_shader_part_key *key);
102
103 /* Ideally pass the sample mask input to the PS epilog as v13, which
104 * is its usual location, so that the shader doesn't have to add v_mov.
105 */
106 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
107
108 enum {
109 CONST_ADDR_SPACE = 2,
110 LOCAL_ADDR_SPACE = 3,
111 };
112
113 static bool is_merged_shader(struct si_shader *shader)
114 {
115 if (shader->selector->screen->b.chip_class <= VI)
116 return false;
117
118 return shader->key.as_ls ||
119 shader->key.as_es ||
120 shader->selector->type == PIPE_SHADER_TESS_CTRL ||
121 shader->selector->type == PIPE_SHADER_GEOMETRY;
122 }
123
124 static void si_init_function_info(struct si_function_info *fninfo)
125 {
126 fninfo->num_params = 0;
127 fninfo->num_sgpr_params = 0;
128 }
129
130 static unsigned add_arg_assign(struct si_function_info *fninfo,
131 enum si_arg_regfile regfile, LLVMTypeRef type,
132 LLVMValueRef *assign)
133 {
134 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
135
136 unsigned idx = fninfo->num_params++;
137 assert(idx < ARRAY_SIZE(fninfo->types));
138
139 if (regfile == ARG_SGPR)
140 fninfo->num_sgpr_params = fninfo->num_params;
141
142 fninfo->types[idx] = type;
143 fninfo->assign[idx] = assign;
144 return idx;
145 }
146
147 static unsigned add_arg(struct si_function_info *fninfo,
148 enum si_arg_regfile regfile, LLVMTypeRef type)
149 {
150 return add_arg_assign(fninfo, regfile, type, NULL);
151 }
152
153 static void add_arg_checked(struct si_function_info *fninfo,
154 enum si_arg_regfile regfile, LLVMTypeRef type,
155 unsigned idx)
156 {
157 MAYBE_UNUSED unsigned actual = add_arg(fninfo, regfile, type);
158 assert(actual == idx);
159 }
160
161 /**
162 * Returns a unique index for a per-patch semantic name and index. The index
163 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
164 * can be calculated.
165 */
166 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
167 {
168 switch (semantic_name) {
169 case TGSI_SEMANTIC_TESSOUTER:
170 return 0;
171 case TGSI_SEMANTIC_TESSINNER:
172 return 1;
173 case TGSI_SEMANTIC_PATCH:
174 assert(index < 30);
175 return 2 + index;
176
177 default:
178 assert(!"invalid semantic name");
179 return 0;
180 }
181 }
182
183 /**
184 * Returns a unique index for a semantic name and index. The index must be
185 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
186 * calculated.
187 */
188 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
189 {
190 switch (semantic_name) {
191 case TGSI_SEMANTIC_POSITION:
192 return 0;
193 case TGSI_SEMANTIC_GENERIC:
194 /* Since some shader stages use the the highest used IO index
195 * to determine the size to allocate for inputs/outputs
196 * (in LDS, tess and GS rings). GENERIC should be placed right
197 * after POSITION to make that size as small as possible.
198 */
199 if (index < SI_MAX_IO_GENERIC)
200 return 1 + index;
201
202 assert(!"invalid generic index");
203 return 0;
204 case TGSI_SEMANTIC_PSIZE:
205 return SI_MAX_IO_GENERIC + 1;
206 case TGSI_SEMANTIC_CLIPDIST:
207 assert(index <= 1);
208 return SI_MAX_IO_GENERIC + 2 + index;
209 case TGSI_SEMANTIC_FOG:
210 return SI_MAX_IO_GENERIC + 4;
211 case TGSI_SEMANTIC_LAYER:
212 return SI_MAX_IO_GENERIC + 5;
213 case TGSI_SEMANTIC_VIEWPORT_INDEX:
214 return SI_MAX_IO_GENERIC + 6;
215 case TGSI_SEMANTIC_PRIMID:
216 return SI_MAX_IO_GENERIC + 7;
217 case TGSI_SEMANTIC_COLOR: /* these alias */
218 case TGSI_SEMANTIC_BCOLOR:
219 assert(index < 2);
220 return SI_MAX_IO_GENERIC + 8 + index;
221 case TGSI_SEMANTIC_TEXCOORD:
222 assert(index < 8);
223 assert(SI_MAX_IO_GENERIC + 10 + index < 64);
224 return SI_MAX_IO_GENERIC + 10 + index;
225 default:
226 assert(!"invalid semantic name");
227 return 0;
228 }
229 }
230
231 /**
232 * Helper function that builds an LLVM IR PHI node and immediately adds
233 * incoming edges.
234 */
235 static LLVMValueRef
236 build_phi(struct ac_llvm_context *ctx, LLVMTypeRef type,
237 unsigned count_incoming, LLVMValueRef *values,
238 LLVMBasicBlockRef *blocks)
239 {
240 LLVMValueRef phi = LLVMBuildPhi(ctx->builder, type, "");
241 LLVMAddIncoming(phi, values, blocks, count_incoming);
242 return phi;
243 }
244
245 /**
246 * Get the value of a shader input parameter and extract a bitfield.
247 */
248 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
249 unsigned param, unsigned rshift,
250 unsigned bitwidth)
251 {
252 struct gallivm_state *gallivm = &ctx->gallivm;
253 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
254 param);
255
256 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
257 value = bitcast(&ctx->bld_base,
258 TGSI_TYPE_UNSIGNED, value);
259
260 if (rshift)
261 value = LLVMBuildLShr(gallivm->builder, value,
262 LLVMConstInt(ctx->i32, rshift, 0), "");
263
264 if (rshift + bitwidth < 32) {
265 unsigned mask = (1 << bitwidth) - 1;
266 value = LLVMBuildAnd(gallivm->builder, value,
267 LLVMConstInt(ctx->i32, mask, 0), "");
268 }
269
270 return value;
271 }
272
273 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
274 {
275 switch (ctx->type) {
276 case PIPE_SHADER_TESS_CTRL:
277 return unpack_param(ctx, ctx->param_tcs_rel_ids, 0, 8);
278
279 case PIPE_SHADER_TESS_EVAL:
280 return LLVMGetParam(ctx->main_fn,
281 ctx->param_tes_rel_patch_id);
282
283 default:
284 assert(0);
285 return NULL;
286 }
287 }
288
289 /* Tessellation shaders pass outputs to the next shader using LDS.
290 *
291 * LS outputs = TCS inputs
292 * TCS outputs = TES inputs
293 *
294 * The LDS layout is:
295 * - TCS inputs for patch 0
296 * - TCS inputs for patch 1
297 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
298 * - ...
299 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
300 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
301 * - TCS outputs for patch 1
302 * - Per-patch TCS outputs for patch 1
303 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
304 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
305 * - ...
306 *
307 * All three shaders VS(LS), TCS, TES share the same LDS space.
308 */
309
310 static LLVMValueRef
311 get_tcs_in_patch_stride(struct si_shader_context *ctx)
312 {
313 return unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
314 }
315
316 static LLVMValueRef
317 get_tcs_out_patch_stride(struct si_shader_context *ctx)
318 {
319 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
320 }
321
322 static LLVMValueRef
323 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
324 {
325 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
326 unpack_param(ctx,
327 ctx->param_tcs_out_lds_offsets,
328 0, 16),
329 4);
330 }
331
332 static LLVMValueRef
333 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
334 {
335 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
336 unpack_param(ctx,
337 ctx->param_tcs_out_lds_offsets,
338 16, 16),
339 4);
340 }
341
342 static LLVMValueRef
343 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
344 {
345 struct gallivm_state *gallivm = &ctx->gallivm;
346 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
347 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
348
349 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
350 }
351
352 static LLVMValueRef
353 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
354 {
355 struct gallivm_state *gallivm = &ctx->gallivm;
356 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
357 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
358 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
359
360 return LLVMBuildAdd(gallivm->builder, patch0_offset,
361 LLVMBuildMul(gallivm->builder, patch_stride,
362 rel_patch_id, ""),
363 "");
364 }
365
366 static LLVMValueRef
367 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
368 {
369 struct gallivm_state *gallivm = &ctx->gallivm;
370 LLVMValueRef patch0_patch_data_offset =
371 get_tcs_out_patch0_patch_data_offset(ctx);
372 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
373 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
374
375 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
376 LLVMBuildMul(gallivm->builder, patch_stride,
377 rel_patch_id, ""),
378 "");
379 }
380
381 static LLVMValueRef get_instance_index_for_fetch(
382 struct si_shader_context *ctx,
383 unsigned param_start_instance, LLVMValueRef divisor)
384 {
385 struct gallivm_state *gallivm = &ctx->gallivm;
386
387 LLVMValueRef result = ctx->abi.instance_id;
388
389 /* The division must be done before START_INSTANCE is added. */
390 if (divisor != ctx->i32_1)
391 result = LLVMBuildUDiv(gallivm->builder, result, divisor, "");
392
393 return LLVMBuildAdd(gallivm->builder, result,
394 LLVMGetParam(ctx->main_fn, param_start_instance), "");
395 }
396
397 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
398 * to float. */
399 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
400 LLVMValueRef vec4,
401 unsigned double_index)
402 {
403 LLVMBuilderRef builder = ctx->gallivm.builder;
404 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->gallivm.context);
405 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
406 LLVMVectorType(f64, 2), "");
407 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
408 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
409 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
410 }
411
412 void si_llvm_load_input_vs(
413 struct si_shader_context *ctx,
414 unsigned input_index,
415 LLVMValueRef out[4])
416 {
417 struct gallivm_state *gallivm = &ctx->gallivm;
418
419 unsigned chan;
420 unsigned fix_fetch;
421 unsigned num_fetches;
422 unsigned fetch_stride;
423
424 LLVMValueRef t_list_ptr;
425 LLVMValueRef t_offset;
426 LLVMValueRef t_list;
427 LLVMValueRef vertex_index;
428 LLVMValueRef input[3];
429
430 /* Load the T list */
431 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
432
433 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
434
435 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
436
437 vertex_index = LLVMGetParam(ctx->main_fn,
438 ctx->param_vertex_index0 +
439 input_index);
440
441 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
442
443 /* Do multiple loads for special formats. */
444 switch (fix_fetch) {
445 case SI_FIX_FETCH_RGB_64_FLOAT:
446 num_fetches = 3; /* 3 2-dword loads */
447 fetch_stride = 8;
448 break;
449 case SI_FIX_FETCH_RGBA_64_FLOAT:
450 num_fetches = 2; /* 2 4-dword loads */
451 fetch_stride = 16;
452 break;
453 case SI_FIX_FETCH_RGB_8:
454 case SI_FIX_FETCH_RGB_8_INT:
455 num_fetches = 3;
456 fetch_stride = 1;
457 break;
458 case SI_FIX_FETCH_RGB_16:
459 case SI_FIX_FETCH_RGB_16_INT:
460 num_fetches = 3;
461 fetch_stride = 2;
462 break;
463 default:
464 num_fetches = 1;
465 fetch_stride = 0;
466 }
467
468 for (unsigned i = 0; i < num_fetches; i++) {
469 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
470
471 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
472 vertex_index, voffset,
473 true);
474 }
475
476 /* Break up the vec4 into individual components */
477 for (chan = 0; chan < 4; chan++) {
478 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
479 out[chan] = LLVMBuildExtractElement(gallivm->builder,
480 input[0], llvm_chan, "");
481 }
482
483 switch (fix_fetch) {
484 case SI_FIX_FETCH_A2_SNORM:
485 case SI_FIX_FETCH_A2_SSCALED:
486 case SI_FIX_FETCH_A2_SINT: {
487 /* The hardware returns an unsigned value; convert it to a
488 * signed one.
489 */
490 LLVMValueRef tmp = out[3];
491 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
492
493 /* First, recover the sign-extended signed integer value. */
494 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
495 tmp = LLVMBuildFPToUI(gallivm->builder, tmp, ctx->i32, "");
496 else
497 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->i32, "");
498
499 /* For the integer-like cases, do a natural sign extension.
500 *
501 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
502 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
503 * exponent.
504 */
505 tmp = LLVMBuildShl(gallivm->builder, tmp,
506 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
507 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
508 tmp = LLVMBuildAShr(gallivm->builder, tmp, c30, "");
509
510 /* Convert back to the right type. */
511 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
512 LLVMValueRef clamp;
513 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
514 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
515 clamp = LLVMBuildFCmp(gallivm->builder, LLVMRealULT, tmp, neg_one, "");
516 tmp = LLVMBuildSelect(gallivm->builder, clamp, neg_one, tmp, "");
517 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
518 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
519 }
520
521 out[3] = tmp;
522 break;
523 }
524 case SI_FIX_FETCH_RGBA_32_UNORM:
525 case SI_FIX_FETCH_RGBX_32_UNORM:
526 for (chan = 0; chan < 4; chan++) {
527 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
528 ctx->i32, "");
529 out[chan] = LLVMBuildUIToFP(gallivm->builder,
530 out[chan], ctx->f32, "");
531 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
532 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
533 }
534 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
535 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
536 out[3] = LLVMConstReal(ctx->f32, 1);
537 break;
538 case SI_FIX_FETCH_RGBA_32_SNORM:
539 case SI_FIX_FETCH_RGBX_32_SNORM:
540 case SI_FIX_FETCH_RGBA_32_FIXED:
541 case SI_FIX_FETCH_RGBX_32_FIXED: {
542 double scale;
543 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
544 scale = 1.0 / 0x10000;
545 else
546 scale = 1.0 / INT_MAX;
547
548 for (chan = 0; chan < 4; chan++) {
549 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
550 ctx->i32, "");
551 out[chan] = LLVMBuildSIToFP(gallivm->builder,
552 out[chan], ctx->f32, "");
553 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
554 LLVMConstReal(ctx->f32, scale), "");
555 }
556 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
557 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
558 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
559 out[3] = LLVMConstReal(ctx->f32, 1);
560 break;
561 }
562 case SI_FIX_FETCH_RGBA_32_USCALED:
563 for (chan = 0; chan < 4; chan++) {
564 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
565 ctx->i32, "");
566 out[chan] = LLVMBuildUIToFP(gallivm->builder,
567 out[chan], ctx->f32, "");
568 }
569 break;
570 case SI_FIX_FETCH_RGBA_32_SSCALED:
571 for (chan = 0; chan < 4; chan++) {
572 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
573 ctx->i32, "");
574 out[chan] = LLVMBuildSIToFP(gallivm->builder,
575 out[chan], ctx->f32, "");
576 }
577 break;
578 case SI_FIX_FETCH_RG_64_FLOAT:
579 for (chan = 0; chan < 2; chan++)
580 out[chan] = extract_double_to_float(ctx, input[0], chan);
581
582 out[2] = LLVMConstReal(ctx->f32, 0);
583 out[3] = LLVMConstReal(ctx->f32, 1);
584 break;
585 case SI_FIX_FETCH_RGB_64_FLOAT:
586 for (chan = 0; chan < 3; chan++)
587 out[chan] = extract_double_to_float(ctx, input[chan], 0);
588
589 out[3] = LLVMConstReal(ctx->f32, 1);
590 break;
591 case SI_FIX_FETCH_RGBA_64_FLOAT:
592 for (chan = 0; chan < 4; chan++) {
593 out[chan] = extract_double_to_float(ctx, input[chan / 2],
594 chan % 2);
595 }
596 break;
597 case SI_FIX_FETCH_RGB_8:
598 case SI_FIX_FETCH_RGB_8_INT:
599 case SI_FIX_FETCH_RGB_16:
600 case SI_FIX_FETCH_RGB_16_INT:
601 for (chan = 0; chan < 3; chan++) {
602 out[chan] = LLVMBuildExtractElement(gallivm->builder,
603 input[chan],
604 ctx->i32_0, "");
605 }
606 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
607 fix_fetch == SI_FIX_FETCH_RGB_16) {
608 out[3] = LLVMConstReal(ctx->f32, 1);
609 } else {
610 out[3] = LLVMBuildBitCast(gallivm->builder, ctx->i32_1,
611 ctx->f32, "");
612 }
613 break;
614 }
615 }
616
617 static void declare_input_vs(
618 struct si_shader_context *ctx,
619 unsigned input_index,
620 const struct tgsi_full_declaration *decl,
621 LLVMValueRef out[4])
622 {
623 si_llvm_load_input_vs(ctx, input_index, out);
624 }
625
626 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
627 unsigned swizzle)
628 {
629 if (swizzle > 0)
630 return ctx->i32_0;
631
632 switch (ctx->type) {
633 case PIPE_SHADER_VERTEX:
634 return LLVMGetParam(ctx->main_fn,
635 ctx->param_vs_prim_id);
636 case PIPE_SHADER_TESS_CTRL:
637 return LLVMGetParam(ctx->main_fn,
638 ctx->param_tcs_patch_id);
639 case PIPE_SHADER_TESS_EVAL:
640 return LLVMGetParam(ctx->main_fn,
641 ctx->param_tes_patch_id);
642 case PIPE_SHADER_GEOMETRY:
643 return LLVMGetParam(ctx->main_fn,
644 ctx->param_gs_prim_id);
645 default:
646 assert(0);
647 return ctx->i32_0;
648 }
649 }
650
651 /**
652 * Return the value of tgsi_ind_register for indexing.
653 * This is the indirect index with the constant offset added to it.
654 */
655 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
656 const struct tgsi_ind_register *ind,
657 int rel_index)
658 {
659 struct gallivm_state *gallivm = &ctx->gallivm;
660 LLVMValueRef result;
661
662 result = ctx->addrs[ind->Index][ind->Swizzle];
663 result = LLVMBuildLoad(gallivm->builder, result, "");
664 result = LLVMBuildAdd(gallivm->builder, result,
665 LLVMConstInt(ctx->i32, rel_index, 0), "");
666 return result;
667 }
668
669 /**
670 * Like get_indirect_index, but restricts the return value to a (possibly
671 * undefined) value inside [0..num).
672 */
673 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
674 const struct tgsi_ind_register *ind,
675 int rel_index, unsigned num)
676 {
677 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
678
679 return si_llvm_bound_index(ctx, result, num);
680 }
681
682
683 /**
684 * Calculate a dword address given an input or output register and a stride.
685 */
686 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
687 const struct tgsi_full_dst_register *dst,
688 const struct tgsi_full_src_register *src,
689 LLVMValueRef vertex_dw_stride,
690 LLVMValueRef base_addr)
691 {
692 struct gallivm_state *gallivm = &ctx->gallivm;
693 struct tgsi_shader_info *info = &ctx->shader->selector->info;
694 ubyte *name, *index, *array_first;
695 int first, param;
696 struct tgsi_full_dst_register reg;
697
698 /* Set the register description. The address computation is the same
699 * for sources and destinations. */
700 if (src) {
701 reg.Register.File = src->Register.File;
702 reg.Register.Index = src->Register.Index;
703 reg.Register.Indirect = src->Register.Indirect;
704 reg.Register.Dimension = src->Register.Dimension;
705 reg.Indirect = src->Indirect;
706 reg.Dimension = src->Dimension;
707 reg.DimIndirect = src->DimIndirect;
708 } else
709 reg = *dst;
710
711 /* If the register is 2-dimensional (e.g. an array of vertices
712 * in a primitive), calculate the base address of the vertex. */
713 if (reg.Register.Dimension) {
714 LLVMValueRef index;
715
716 if (reg.Dimension.Indirect)
717 index = get_indirect_index(ctx, &reg.DimIndirect,
718 reg.Dimension.Index);
719 else
720 index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
721
722 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
723 LLVMBuildMul(gallivm->builder, index,
724 vertex_dw_stride, ""), "");
725 }
726
727 /* Get information about the register. */
728 if (reg.Register.File == TGSI_FILE_INPUT) {
729 name = info->input_semantic_name;
730 index = info->input_semantic_index;
731 array_first = info->input_array_first;
732 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
733 name = info->output_semantic_name;
734 index = info->output_semantic_index;
735 array_first = info->output_array_first;
736 } else {
737 assert(0);
738 return NULL;
739 }
740
741 if (reg.Register.Indirect) {
742 /* Add the relative address of the element. */
743 LLVMValueRef ind_index;
744
745 if (reg.Indirect.ArrayID)
746 first = array_first[reg.Indirect.ArrayID];
747 else
748 first = reg.Register.Index;
749
750 ind_index = get_indirect_index(ctx, &reg.Indirect,
751 reg.Register.Index - first);
752
753 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
754 LLVMBuildMul(gallivm->builder, ind_index,
755 LLVMConstInt(ctx->i32, 4, 0), ""), "");
756
757 param = reg.Register.Dimension ?
758 si_shader_io_get_unique_index(name[first], index[first]) :
759 si_shader_io_get_unique_index_patch(name[first], index[first]);
760 } else {
761 param = reg.Register.Dimension ?
762 si_shader_io_get_unique_index(name[reg.Register.Index],
763 index[reg.Register.Index]) :
764 si_shader_io_get_unique_index_patch(name[reg.Register.Index],
765 index[reg.Register.Index]);
766 }
767
768 /* Add the base address of the element. */
769 return LLVMBuildAdd(gallivm->builder, base_addr,
770 LLVMConstInt(ctx->i32, param * 4, 0), "");
771 }
772
773 /* The offchip buffer layout for TCS->TES is
774 *
775 * - attribute 0 of patch 0 vertex 0
776 * - attribute 0 of patch 0 vertex 1
777 * - attribute 0 of patch 0 vertex 2
778 * ...
779 * - attribute 0 of patch 1 vertex 0
780 * - attribute 0 of patch 1 vertex 1
781 * ...
782 * - attribute 1 of patch 0 vertex 0
783 * - attribute 1 of patch 0 vertex 1
784 * ...
785 * - per patch attribute 0 of patch 0
786 * - per patch attribute 0 of patch 1
787 * ...
788 *
789 * Note that every attribute has 4 components.
790 */
791 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
792 LLVMValueRef rel_patch_id,
793 LLVMValueRef vertex_index,
794 LLVMValueRef param_index)
795 {
796 struct gallivm_state *gallivm = &ctx->gallivm;
797 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
798 LLVMValueRef param_stride, constant16;
799
800 vertices_per_patch = unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
801 num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
802 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
803 num_patches, "");
804
805 constant16 = LLVMConstInt(ctx->i32, 16, 0);
806 if (vertex_index) {
807 base_addr = LLVMBuildMul(gallivm->builder, rel_patch_id,
808 vertices_per_patch, "");
809
810 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
811 vertex_index, "");
812
813 param_stride = total_vertices;
814 } else {
815 base_addr = rel_patch_id;
816 param_stride = num_patches;
817 }
818
819 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
820 LLVMBuildMul(gallivm->builder, param_index,
821 param_stride, ""), "");
822
823 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
824
825 if (!vertex_index) {
826 LLVMValueRef patch_data_offset =
827 unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
828
829 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
830 patch_data_offset, "");
831 }
832 return base_addr;
833 }
834
835 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
836 struct si_shader_context *ctx,
837 const struct tgsi_full_dst_register *dst,
838 const struct tgsi_full_src_register *src)
839 {
840 struct gallivm_state *gallivm = &ctx->gallivm;
841 struct tgsi_shader_info *info = &ctx->shader->selector->info;
842 ubyte *name, *index, *array_first;
843 struct tgsi_full_src_register reg;
844 LLVMValueRef vertex_index = NULL;
845 LLVMValueRef param_index = NULL;
846 unsigned param_index_base, param_base;
847
848 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
849
850 if (reg.Register.Dimension) {
851
852 if (reg.Dimension.Indirect)
853 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
854 reg.Dimension.Index);
855 else
856 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
857 }
858
859 /* Get information about the register. */
860 if (reg.Register.File == TGSI_FILE_INPUT) {
861 name = info->input_semantic_name;
862 index = info->input_semantic_index;
863 array_first = info->input_array_first;
864 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
865 name = info->output_semantic_name;
866 index = info->output_semantic_index;
867 array_first = info->output_array_first;
868 } else {
869 assert(0);
870 return NULL;
871 }
872
873 if (reg.Register.Indirect) {
874 if (reg.Indirect.ArrayID)
875 param_base = array_first[reg.Indirect.ArrayID];
876 else
877 param_base = reg.Register.Index;
878
879 param_index = get_indirect_index(ctx, &reg.Indirect,
880 reg.Register.Index - param_base);
881
882 } else {
883 param_base = reg.Register.Index;
884 param_index = ctx->i32_0;
885 }
886
887 param_index_base = reg.Register.Dimension ?
888 si_shader_io_get_unique_index(name[param_base], index[param_base]) :
889 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]);
890
891 param_index = LLVMBuildAdd(gallivm->builder, param_index,
892 LLVMConstInt(ctx->i32, param_index_base, 0),
893 "");
894
895 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
896 vertex_index, param_index);
897 }
898
899 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
900 enum tgsi_opcode_type type, unsigned swizzle,
901 LLVMValueRef buffer, LLVMValueRef offset,
902 LLVMValueRef base, bool can_speculate)
903 {
904 struct si_shader_context *ctx = si_shader_context(bld_base);
905 struct gallivm_state *gallivm = &ctx->gallivm;
906 LLVMValueRef value, value2;
907 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
908 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
909
910 if (swizzle == ~0) {
911 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
912 0, 1, 0, can_speculate, false);
913
914 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
915 }
916
917 if (!tgsi_type_is_64bit(type)) {
918 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
919 0, 1, 0, can_speculate, false);
920
921 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
922 return LLVMBuildExtractElement(gallivm->builder, value,
923 LLVMConstInt(ctx->i32, swizzle, 0), "");
924 }
925
926 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
927 swizzle * 4, 1, 0, can_speculate, false);
928
929 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
930 swizzle * 4 + 4, 1, 0, can_speculate, false);
931
932 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
933 }
934
935 /**
936 * Load from LDS.
937 *
938 * \param type output value type
939 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
940 * \param dw_addr address in dwords
941 */
942 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
943 enum tgsi_opcode_type type, unsigned swizzle,
944 LLVMValueRef dw_addr)
945 {
946 struct si_shader_context *ctx = si_shader_context(bld_base);
947 struct gallivm_state *gallivm = &ctx->gallivm;
948 LLVMValueRef value;
949
950 if (swizzle == ~0) {
951 LLVMValueRef values[TGSI_NUM_CHANNELS];
952
953 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
954 values[chan] = lds_load(bld_base, type, chan, dw_addr);
955
956 return lp_build_gather_values(gallivm, values,
957 TGSI_NUM_CHANNELS);
958 }
959
960 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
961 LLVMConstInt(ctx->i32, swizzle, 0));
962
963 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
964 if (tgsi_type_is_64bit(type)) {
965 LLVMValueRef value2;
966 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
967 ctx->i32_1);
968 value2 = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
969 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
970 }
971
972 return LLVMBuildBitCast(gallivm->builder, value,
973 tgsi2llvmtype(bld_base, type), "");
974 }
975
976 /**
977 * Store to LDS.
978 *
979 * \param swizzle offset (typically 0..3)
980 * \param dw_addr address in dwords
981 * \param value value to store
982 */
983 static void lds_store(struct lp_build_tgsi_context *bld_base,
984 unsigned dw_offset_imm, LLVMValueRef dw_addr,
985 LLVMValueRef value)
986 {
987 struct si_shader_context *ctx = si_shader_context(bld_base);
988 struct gallivm_state *gallivm = &ctx->gallivm;
989
990 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
991 LLVMConstInt(ctx->i32, dw_offset_imm, 0));
992
993 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
994 ac_build_indexed_store(&ctx->ac, ctx->lds,
995 dw_addr, value);
996 }
997
998 static LLVMValueRef desc_from_addr_base64k(struct si_shader_context *ctx,
999 unsigned param)
1000 {
1001 LLVMBuilderRef builder = ctx->gallivm.builder;
1002
1003 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1004 addr = LLVMBuildZExt(builder, addr, ctx->i64, "");
1005 addr = LLVMBuildShl(builder, addr, LLVMConstInt(ctx->i64, 16, 0), "");
1006
1007 uint64_t desc2 = 0xffffffff;
1008 uint64_t desc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1009 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1010 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1011 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1012 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1013 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1014 LLVMValueRef hi = LLVMConstInt(ctx->i64, desc2 | (desc3 << 32), 0);
1015
1016 LLVMValueRef desc = LLVMGetUndef(LLVMVectorType(ctx->i64, 2));
1017 desc = LLVMBuildInsertElement(builder, desc, addr, ctx->i32_0, "");
1018 desc = LLVMBuildInsertElement(builder, desc, hi, ctx->i32_1, "");
1019 return LLVMBuildBitCast(builder, desc, ctx->v4i32, "");
1020 }
1021
1022 static LLVMValueRef fetch_input_tcs(
1023 struct lp_build_tgsi_context *bld_base,
1024 const struct tgsi_full_src_register *reg,
1025 enum tgsi_opcode_type type, unsigned swizzle)
1026 {
1027 struct si_shader_context *ctx = si_shader_context(bld_base);
1028 LLVMValueRef dw_addr, stride;
1029
1030 stride = unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
1031 dw_addr = get_tcs_in_current_patch_offset(ctx);
1032 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1033
1034 return lds_load(bld_base, type, swizzle, dw_addr);
1035 }
1036
1037 static LLVMValueRef fetch_output_tcs(
1038 struct lp_build_tgsi_context *bld_base,
1039 const struct tgsi_full_src_register *reg,
1040 enum tgsi_opcode_type type, unsigned swizzle)
1041 {
1042 struct si_shader_context *ctx = si_shader_context(bld_base);
1043 LLVMValueRef dw_addr, stride;
1044
1045 if (reg->Register.Dimension) {
1046 stride = unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 8);
1047 dw_addr = get_tcs_out_current_patch_offset(ctx);
1048 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1049 } else {
1050 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1051 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1052 }
1053
1054 return lds_load(bld_base, type, swizzle, dw_addr);
1055 }
1056
1057 static LLVMValueRef fetch_input_tes(
1058 struct lp_build_tgsi_context *bld_base,
1059 const struct tgsi_full_src_register *reg,
1060 enum tgsi_opcode_type type, unsigned swizzle)
1061 {
1062 struct si_shader_context *ctx = si_shader_context(bld_base);
1063 LLVMValueRef buffer, base, addr;
1064
1065 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1066
1067 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1068 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1069
1070 return buffer_load(bld_base, type, swizzle, buffer, base, addr, true);
1071 }
1072
1073 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1074 const struct tgsi_full_instruction *inst,
1075 const struct tgsi_opcode_info *info,
1076 LLVMValueRef dst[4])
1077 {
1078 struct si_shader_context *ctx = si_shader_context(bld_base);
1079 struct gallivm_state *gallivm = &ctx->gallivm;
1080 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
1081 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1082 unsigned chan_index;
1083 LLVMValueRef dw_addr, stride;
1084 LLVMValueRef buffer, base, buf_addr;
1085 LLVMValueRef values[4];
1086 bool skip_lds_store;
1087 bool is_tess_factor = false;
1088
1089 /* Only handle per-patch and per-vertex outputs here.
1090 * Vectors will be lowered to scalars and this function will be called again.
1091 */
1092 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1093 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1094 si_llvm_emit_store(bld_base, inst, info, dst);
1095 return;
1096 }
1097
1098 if (reg->Register.Dimension) {
1099 stride = unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 8);
1100 dw_addr = get_tcs_out_current_patch_offset(ctx);
1101 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1102 skip_lds_store = !sh_info->reads_pervertex_outputs;
1103 } else {
1104 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1105 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1106 skip_lds_store = !sh_info->reads_perpatch_outputs;
1107
1108 if (!reg->Register.Indirect) {
1109 int name = sh_info->output_semantic_name[reg->Register.Index];
1110
1111 /* Always write tess factors into LDS for the TCS epilog. */
1112 if (name == TGSI_SEMANTIC_TESSINNER ||
1113 name == TGSI_SEMANTIC_TESSOUTER) {
1114 skip_lds_store = false;
1115 is_tess_factor = true;
1116 }
1117 }
1118 }
1119
1120 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1121
1122 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1123 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1124
1125
1126 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1127 LLVMValueRef value = dst[chan_index];
1128
1129 if (inst->Instruction.Saturate)
1130 value = ac_build_clamp(&ctx->ac, value);
1131
1132 /* Skip LDS stores if there is no LDS read of this output. */
1133 if (!skip_lds_store)
1134 lds_store(bld_base, chan_index, dw_addr, value);
1135
1136 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1137 values[chan_index] = value;
1138
1139 if (inst->Dst[0].Register.WriteMask != 0xF && !is_tess_factor) {
1140 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1141 buf_addr, base,
1142 4 * chan_index, 1, 0, true, false);
1143 }
1144 }
1145
1146 if (inst->Dst[0].Register.WriteMask == 0xF && !is_tess_factor) {
1147 LLVMValueRef value = lp_build_gather_values(gallivm,
1148 values, 4);
1149 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1150 base, 0, 1, 0, true, false);
1151 }
1152 }
1153
1154 static LLVMValueRef fetch_input_gs(
1155 struct lp_build_tgsi_context *bld_base,
1156 const struct tgsi_full_src_register *reg,
1157 enum tgsi_opcode_type type,
1158 unsigned swizzle)
1159 {
1160 struct si_shader_context *ctx = si_shader_context(bld_base);
1161 struct si_shader *shader = ctx->shader;
1162 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1163 struct gallivm_state *gallivm = &ctx->gallivm;
1164 LLVMValueRef vtx_offset, soffset;
1165 struct tgsi_shader_info *info = &shader->selector->info;
1166 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1167 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1168 unsigned param;
1169 LLVMValueRef value;
1170
1171 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1172 return get_primitive_id(ctx, swizzle);
1173
1174 if (!reg->Register.Dimension)
1175 return NULL;
1176
1177 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1178
1179 /* GFX9 has the ESGS ring in LDS. */
1180 if (ctx->screen->b.chip_class >= GFX9) {
1181 unsigned index = reg->Dimension.Index;
1182
1183 switch (index / 2) {
1184 case 0:
1185 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx01_offset,
1186 index % 2 ? 16 : 0, 16);
1187 break;
1188 case 1:
1189 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx23_offset,
1190 index % 2 ? 16 : 0, 16);
1191 break;
1192 case 2:
1193 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx45_offset,
1194 index % 2 ? 16 : 0, 16);
1195 break;
1196 default:
1197 assert(0);
1198 return NULL;
1199 }
1200
1201 vtx_offset = LLVMBuildAdd(gallivm->builder, vtx_offset,
1202 LLVMConstInt(ctx->i32, param * 4, 0), "");
1203 return lds_load(bld_base, type, swizzle, vtx_offset);
1204 }
1205
1206 /* GFX6: input load from the ESGS ring in memory. */
1207 if (swizzle == ~0) {
1208 LLVMValueRef values[TGSI_NUM_CHANNELS];
1209 unsigned chan;
1210 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1211 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1212 }
1213 return lp_build_gather_values(gallivm, values,
1214 TGSI_NUM_CHANNELS);
1215 }
1216
1217 /* Get the vertex offset parameter on GFX6. */
1218 unsigned vtx_offset_param = reg->Dimension.Index;
1219 if (vtx_offset_param < 2) {
1220 vtx_offset_param += ctx->param_gs_vtx0_offset;
1221 } else {
1222 assert(vtx_offset_param < 6);
1223 vtx_offset_param += ctx->param_gs_vtx2_offset - 2;
1224 }
1225 vtx_offset = lp_build_mul_imm(uint,
1226 LLVMGetParam(ctx->main_fn,
1227 vtx_offset_param),
1228 4);
1229
1230 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1231
1232 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1233 vtx_offset, soffset, 0, 1, 0, true, false);
1234 if (tgsi_type_is_64bit(type)) {
1235 LLVMValueRef value2;
1236 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1237
1238 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1239 ctx->i32_0, vtx_offset, soffset,
1240 0, 1, 0, true, false);
1241 return si_llvm_emit_fetch_64bit(bld_base, type,
1242 value, value2);
1243 }
1244 return LLVMBuildBitCast(gallivm->builder,
1245 value,
1246 tgsi2llvmtype(bld_base, type), "");
1247 }
1248
1249 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1250 {
1251 switch (interpolate) {
1252 case TGSI_INTERPOLATE_CONSTANT:
1253 return 0;
1254
1255 case TGSI_INTERPOLATE_LINEAR:
1256 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1257 return SI_PARAM_LINEAR_SAMPLE;
1258 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1259 return SI_PARAM_LINEAR_CENTROID;
1260 else
1261 return SI_PARAM_LINEAR_CENTER;
1262 break;
1263 case TGSI_INTERPOLATE_COLOR:
1264 case TGSI_INTERPOLATE_PERSPECTIVE:
1265 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1266 return SI_PARAM_PERSP_SAMPLE;
1267 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1268 return SI_PARAM_PERSP_CENTROID;
1269 else
1270 return SI_PARAM_PERSP_CENTER;
1271 break;
1272 default:
1273 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1274 return -1;
1275 }
1276 }
1277
1278 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1279 unsigned attr_index, unsigned chan,
1280 LLVMValueRef prim_mask,
1281 LLVMValueRef i, LLVMValueRef j)
1282 {
1283 if (i || j) {
1284 return ac_build_fs_interp(&ctx->ac,
1285 LLVMConstInt(ctx->i32, chan, 0),
1286 LLVMConstInt(ctx->i32, attr_index, 0),
1287 prim_mask, i, j);
1288 }
1289 return ac_build_fs_interp_mov(&ctx->ac,
1290 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1291 LLVMConstInt(ctx->i32, chan, 0),
1292 LLVMConstInt(ctx->i32, attr_index, 0),
1293 prim_mask);
1294 }
1295
1296 /**
1297 * Interpolate a fragment shader input.
1298 *
1299 * @param ctx context
1300 * @param input_index index of the input in hardware
1301 * @param semantic_name TGSI_SEMANTIC_*
1302 * @param semantic_index semantic index
1303 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1304 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1305 * @param interp_param interpolation weights (i,j)
1306 * @param prim_mask SI_PARAM_PRIM_MASK
1307 * @param face SI_PARAM_FRONT_FACE
1308 * @param result the return value (4 components)
1309 */
1310 static void interp_fs_input(struct si_shader_context *ctx,
1311 unsigned input_index,
1312 unsigned semantic_name,
1313 unsigned semantic_index,
1314 unsigned num_interp_inputs,
1315 unsigned colors_read_mask,
1316 LLVMValueRef interp_param,
1317 LLVMValueRef prim_mask,
1318 LLVMValueRef face,
1319 LLVMValueRef result[4])
1320 {
1321 struct gallivm_state *gallivm = &ctx->gallivm;
1322 LLVMValueRef i = NULL, j = NULL;
1323 unsigned chan;
1324
1325 /* fs.constant returns the param from the middle vertex, so it's not
1326 * really useful for flat shading. It's meant to be used for custom
1327 * interpolation (but the intrinsic can't fetch from the other two
1328 * vertices).
1329 *
1330 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1331 * to do the right thing. The only reason we use fs.constant is that
1332 * fs.interp cannot be used on integers, because they can be equal
1333 * to NaN.
1334 *
1335 * When interp is false we will use fs.constant or for newer llvm,
1336 * amdgcn.interp.mov.
1337 */
1338 bool interp = interp_param != NULL;
1339
1340 if (interp) {
1341 interp_param = LLVMBuildBitCast(gallivm->builder, interp_param,
1342 LLVMVectorType(ctx->f32, 2), "");
1343
1344 i = LLVMBuildExtractElement(gallivm->builder, interp_param,
1345 ctx->i32_0, "");
1346 j = LLVMBuildExtractElement(gallivm->builder, interp_param,
1347 ctx->i32_1, "");
1348 }
1349
1350 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1351 ctx->shader->key.part.ps.prolog.color_two_side) {
1352 LLVMValueRef is_face_positive;
1353
1354 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1355 * otherwise it's at offset "num_inputs".
1356 */
1357 unsigned back_attr_offset = num_interp_inputs;
1358 if (semantic_index == 1 && colors_read_mask & 0xf)
1359 back_attr_offset += 1;
1360
1361 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1362 face, ctx->i32_0, "");
1363
1364 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1365 LLVMValueRef front, back;
1366
1367 front = si_build_fs_interp(ctx,
1368 input_index, chan,
1369 prim_mask, i, j);
1370 back = si_build_fs_interp(ctx,
1371 back_attr_offset, chan,
1372 prim_mask, i, j);
1373
1374 result[chan] = LLVMBuildSelect(gallivm->builder,
1375 is_face_positive,
1376 front,
1377 back,
1378 "");
1379 }
1380 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1381 result[0] = si_build_fs_interp(ctx, input_index,
1382 0, prim_mask, i, j);
1383 result[1] =
1384 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1385 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1386 } else {
1387 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1388 result[chan] = si_build_fs_interp(ctx,
1389 input_index, chan,
1390 prim_mask, i, j);
1391 }
1392 }
1393 }
1394
1395 void si_llvm_load_input_fs(
1396 struct si_shader_context *ctx,
1397 unsigned input_index,
1398 LLVMValueRef out[4])
1399 {
1400 struct lp_build_context *base = &ctx->bld_base.base;
1401 struct si_shader *shader = ctx->shader;
1402 struct tgsi_shader_info *info = &shader->selector->info;
1403 LLVMValueRef main_fn = ctx->main_fn;
1404 LLVMValueRef interp_param = NULL;
1405 int interp_param_idx;
1406 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1407 unsigned semantic_index = info->input_semantic_index[input_index];
1408 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1409 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1410
1411 /* Get colors from input VGPRs (set by the prolog). */
1412 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1413 unsigned colors_read = shader->selector->info.colors_read;
1414 unsigned mask = colors_read >> (semantic_index * 4);
1415 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1416 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1417
1418 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1419 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1420 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1421 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1422 return;
1423 }
1424
1425 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1426 if (interp_param_idx == -1)
1427 return;
1428 else if (interp_param_idx) {
1429 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1430 }
1431
1432 interp_fs_input(ctx, input_index, semantic_name,
1433 semantic_index, 0, /* this param is unused */
1434 shader->selector->info.colors_read, interp_param,
1435 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1436 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1437 &out[0]);
1438 }
1439
1440 static void declare_input_fs(
1441 struct si_shader_context *ctx,
1442 unsigned input_index,
1443 const struct tgsi_full_declaration *decl,
1444 LLVMValueRef out[4])
1445 {
1446 si_llvm_load_input_fs(ctx, input_index, out);
1447 }
1448
1449 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1450 {
1451 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1452 }
1453
1454
1455 /**
1456 * Load a dword from a constant buffer.
1457 */
1458 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1459 LLVMValueRef resource,
1460 LLVMValueRef offset)
1461 {
1462 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1463 0, 0, 0, true, true);
1464 }
1465
1466 static LLVMValueRef load_sample_position(struct si_shader_context *ctx, LLVMValueRef sample_id)
1467 {
1468 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1469 struct gallivm_state *gallivm = &ctx->gallivm;
1470 LLVMBuilderRef builder = gallivm->builder;
1471 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1472 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1473 LLVMValueRef resource = ac_build_indexed_load_const(&ctx->ac, desc, buf_index);
1474
1475 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1476 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1477 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1478
1479 LLVMValueRef pos[4] = {
1480 buffer_load_const(ctx, resource, offset0),
1481 buffer_load_const(ctx, resource, offset1),
1482 LLVMConstReal(ctx->f32, 0),
1483 LLVMConstReal(ctx->f32, 0)
1484 };
1485
1486 return lp_build_gather_values(gallivm, pos, 4);
1487 }
1488
1489 static void declare_system_value(struct si_shader_context *ctx,
1490 unsigned index,
1491 const struct tgsi_full_declaration *decl)
1492 {
1493 struct lp_build_context *bld = &ctx->bld_base.base;
1494 struct gallivm_state *gallivm = &ctx->gallivm;
1495 LLVMValueRef value = 0;
1496
1497 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
1498
1499 switch (decl->Semantic.Name) {
1500 case TGSI_SEMANTIC_INSTANCEID:
1501 value = ctx->abi.instance_id;
1502 break;
1503
1504 case TGSI_SEMANTIC_VERTEXID:
1505 value = LLVMBuildAdd(gallivm->builder,
1506 ctx->abi.vertex_id,
1507 ctx->abi.base_vertex, "");
1508 break;
1509
1510 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1511 /* Unused. Clarify the meaning in indexed vs. non-indexed
1512 * draws if this is ever used again. */
1513 assert(false);
1514 break;
1515
1516 case TGSI_SEMANTIC_BASEVERTEX:
1517 {
1518 /* For non-indexed draws, the base vertex set by the driver
1519 * (for direct draws) or the CP (for indirect draws) is the
1520 * first vertex ID, but GLSL expects 0 to be returned.
1521 */
1522 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
1523 LLVMValueRef indexed;
1524
1525 indexed = LLVMBuildLShr(gallivm->builder, vs_state, ctx->i32_1, "");
1526 indexed = LLVMBuildTrunc(gallivm->builder, indexed, ctx->i1, "");
1527
1528 value = LLVMBuildSelect(gallivm->builder, indexed,
1529 ctx->abi.base_vertex, ctx->i32_0, "");
1530 break;
1531 }
1532
1533 case TGSI_SEMANTIC_BASEINSTANCE:
1534 value = ctx->abi.start_instance;
1535 break;
1536
1537 case TGSI_SEMANTIC_DRAWID:
1538 value = ctx->abi.draw_id;
1539 break;
1540
1541 case TGSI_SEMANTIC_INVOCATIONID:
1542 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1543 value = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
1544 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1545 value = LLVMGetParam(ctx->main_fn,
1546 ctx->param_gs_instance_id);
1547 else
1548 assert(!"INVOCATIONID not implemented");
1549 break;
1550
1551 case TGSI_SEMANTIC_POSITION:
1552 {
1553 LLVMValueRef pos[4] = {
1554 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1555 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1556 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
1557 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
1558 LLVMGetParam(ctx->main_fn,
1559 SI_PARAM_POS_W_FLOAT)),
1560 };
1561 value = lp_build_gather_values(gallivm, pos, 4);
1562 break;
1563 }
1564
1565 case TGSI_SEMANTIC_FACE:
1566 value = LLVMGetParam(ctx->main_fn, SI_PARAM_FRONT_FACE);
1567 break;
1568
1569 case TGSI_SEMANTIC_SAMPLEID:
1570 value = get_sample_id(ctx);
1571 break;
1572
1573 case TGSI_SEMANTIC_SAMPLEPOS: {
1574 LLVMValueRef pos[4] = {
1575 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1576 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1577 LLVMConstReal(ctx->f32, 0),
1578 LLVMConstReal(ctx->f32, 0)
1579 };
1580 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
1581 TGSI_OPCODE_FRC, pos[0]);
1582 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
1583 TGSI_OPCODE_FRC, pos[1]);
1584 value = lp_build_gather_values(gallivm, pos, 4);
1585 break;
1586 }
1587
1588 case TGSI_SEMANTIC_SAMPLEMASK:
1589 /* This can only occur with the OpenGL Core profile, which
1590 * doesn't support smoothing.
1591 */
1592 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1593 break;
1594
1595 case TGSI_SEMANTIC_TESSCOORD:
1596 {
1597 LLVMValueRef coord[4] = {
1598 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1599 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1600 bld->zero,
1601 bld->zero
1602 };
1603
1604 /* For triangles, the vector should be (u, v, 1-u-v). */
1605 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1606 PIPE_PRIM_TRIANGLES)
1607 coord[2] = lp_build_sub(bld, bld->one,
1608 lp_build_add(bld, coord[0], coord[1]));
1609
1610 value = lp_build_gather_values(gallivm, coord, 4);
1611 break;
1612 }
1613
1614 case TGSI_SEMANTIC_VERTICESIN:
1615 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1616 value = unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6);
1617 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1618 value = unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
1619 else
1620 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1621 break;
1622
1623 case TGSI_SEMANTIC_TESSINNER:
1624 case TGSI_SEMANTIC_TESSOUTER:
1625 {
1626 LLVMValueRef buffer, base, addr;
1627 int param = si_shader_io_get_unique_index_patch(decl->Semantic.Name, 0);
1628
1629 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1630
1631 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1632 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1633 LLVMConstInt(ctx->i32, param, 0));
1634
1635 value = buffer_load(&ctx->bld_base, TGSI_TYPE_FLOAT,
1636 ~0, buffer, base, addr, true);
1637
1638 break;
1639 }
1640
1641 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1642 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1643 {
1644 LLVMValueRef buf, slot, val[4];
1645 int i, offset;
1646
1647 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
1648 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1649 buf = ac_build_indexed_load_const(&ctx->ac, buf, slot);
1650 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1651
1652 for (i = 0; i < 4; i++)
1653 val[i] = buffer_load_const(ctx, buf,
1654 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
1655 value = lp_build_gather_values(gallivm, val, 4);
1656 break;
1657 }
1658
1659 case TGSI_SEMANTIC_PRIMID:
1660 value = get_primitive_id(ctx, 0);
1661 break;
1662
1663 case TGSI_SEMANTIC_GRID_SIZE:
1664 value = LLVMGetParam(ctx->main_fn, ctx->param_grid_size);
1665 break;
1666
1667 case TGSI_SEMANTIC_BLOCK_SIZE:
1668 {
1669 LLVMValueRef values[3];
1670 unsigned i;
1671 unsigned *properties = ctx->shader->selector->info.properties;
1672
1673 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1674 unsigned sizes[3] = {
1675 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1676 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1677 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1678 };
1679
1680 for (i = 0; i < 3; ++i)
1681 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1682
1683 value = lp_build_gather_values(gallivm, values, 3);
1684 } else {
1685 value = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1686 }
1687 break;
1688 }
1689
1690 case TGSI_SEMANTIC_BLOCK_ID:
1691 {
1692 LLVMValueRef values[3];
1693
1694 for (int i = 0; i < 3; i++) {
1695 values[i] = ctx->i32_0;
1696 if (ctx->param_block_id[i] >= 0) {
1697 values[i] = LLVMGetParam(ctx->main_fn,
1698 ctx->param_block_id[i]);
1699 }
1700 }
1701 value = lp_build_gather_values(gallivm, values, 3);
1702 break;
1703 }
1704
1705 case TGSI_SEMANTIC_THREAD_ID:
1706 value = LLVMGetParam(ctx->main_fn, ctx->param_thread_id);
1707 break;
1708
1709 case TGSI_SEMANTIC_HELPER_INVOCATION:
1710 value = lp_build_intrinsic(gallivm->builder,
1711 "llvm.amdgcn.ps.live",
1712 ctx->i1, NULL, 0,
1713 LP_FUNC_ATTR_READNONE);
1714 value = LLVMBuildNot(gallivm->builder, value, "");
1715 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1716 break;
1717
1718 case TGSI_SEMANTIC_SUBGROUP_SIZE:
1719 value = LLVMConstInt(ctx->i32, 64, 0);
1720 break;
1721
1722 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
1723 value = ac_get_thread_id(&ctx->ac);
1724 break;
1725
1726 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
1727 {
1728 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1729 id = LLVMBuildZExt(gallivm->builder, id, ctx->i64, "");
1730 value = LLVMBuildShl(gallivm->builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
1731 value = LLVMBuildBitCast(gallivm->builder, value, ctx->v2i32, "");
1732 break;
1733 }
1734
1735 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
1736 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
1737 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
1738 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
1739 {
1740 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1741 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
1742 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
1743 /* All bits set except LSB */
1744 value = LLVMConstInt(ctx->i64, -2, 0);
1745 } else {
1746 /* All bits set */
1747 value = LLVMConstInt(ctx->i64, -1, 0);
1748 }
1749 id = LLVMBuildZExt(gallivm->builder, id, ctx->i64, "");
1750 value = LLVMBuildShl(gallivm->builder, value, id, "");
1751 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
1752 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
1753 value = LLVMBuildNot(gallivm->builder, value, "");
1754 value = LLVMBuildBitCast(gallivm->builder, value, ctx->v2i32, "");
1755 break;
1756 }
1757
1758 default:
1759 assert(!"unknown system value");
1760 return;
1761 }
1762
1763 ctx->system_values[index] = value;
1764 }
1765
1766 static void declare_compute_memory(struct si_shader_context *ctx,
1767 const struct tgsi_full_declaration *decl)
1768 {
1769 struct si_shader_selector *sel = ctx->shader->selector;
1770 struct gallivm_state *gallivm = &ctx->gallivm;
1771
1772 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1773 LLVMValueRef var;
1774
1775 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1776 assert(decl->Range.First == decl->Range.Last);
1777 assert(!ctx->shared_memory);
1778
1779 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1780 LLVMArrayType(ctx->i8, sel->local_size),
1781 "compute_lds",
1782 LOCAL_ADDR_SPACE);
1783 LLVMSetAlignment(var, 4);
1784
1785 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1786 }
1787
1788 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1789 {
1790 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1791 ctx->param_const_and_shader_buffers);
1792
1793 return ac_build_indexed_load_const(&ctx->ac, list_ptr,
1794 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
1795 }
1796
1797 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
1798 {
1799 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1800 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
1801
1802 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
1803 index = LLVMBuildAdd(ctx->gallivm.builder, index,
1804 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
1805
1806 return ac_build_indexed_load_const(&ctx->ac, ptr, index);
1807 }
1808
1809 static LLVMValueRef fetch_constant(
1810 struct lp_build_tgsi_context *bld_base,
1811 const struct tgsi_full_src_register *reg,
1812 enum tgsi_opcode_type type,
1813 unsigned swizzle)
1814 {
1815 struct si_shader_context *ctx = si_shader_context(bld_base);
1816 struct lp_build_context *base = &bld_base->base;
1817 const struct tgsi_ind_register *ireg = &reg->Indirect;
1818 unsigned buf, idx;
1819
1820 LLVMValueRef addr, bufp;
1821 LLVMValueRef result;
1822
1823 if (swizzle == LP_CHAN_ALL) {
1824 unsigned chan;
1825 LLVMValueRef values[4];
1826 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1827 values[chan] = fetch_constant(bld_base, reg, type, chan);
1828
1829 return lp_build_gather_values(&ctx->gallivm, values, 4);
1830 }
1831
1832 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1833 idx = reg->Register.Index * 4 + swizzle;
1834
1835 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1836 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
1837 LLVMValueRef index;
1838 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
1839 reg->Dimension.Index,
1840 ctx->num_const_buffers);
1841 index = LLVMBuildAdd(ctx->gallivm.builder, index,
1842 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
1843 bufp = ac_build_indexed_load_const(&ctx->ac, ptr, index);
1844 } else
1845 bufp = load_const_buffer_desc(ctx, buf);
1846
1847 if (reg->Register.Indirect) {
1848 addr = ctx->addrs[ireg->Index][ireg->Swizzle];
1849 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1850 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1851 addr = lp_build_add(&bld_base->uint_bld, addr,
1852 LLVMConstInt(ctx->i32, idx * 4, 0));
1853 } else {
1854 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
1855 }
1856
1857 result = buffer_load_const(ctx, bufp, addr);
1858
1859 if (!tgsi_type_is_64bit(type))
1860 result = bitcast(bld_base, type, result);
1861 else {
1862 LLVMValueRef addr2, result2;
1863
1864 addr2 = lp_build_add(&bld_base->uint_bld, addr,
1865 LLVMConstInt(ctx->i32, 4, 0));
1866 result2 = buffer_load_const(ctx, bufp, addr2);
1867
1868 result = si_llvm_emit_fetch_64bit(bld_base, type,
1869 result, result2);
1870 }
1871 return result;
1872 }
1873
1874 /* Upper 16 bits must be zero. */
1875 static LLVMValueRef si_llvm_pack_two_int16(struct si_shader_context *ctx,
1876 LLVMValueRef val[2])
1877 {
1878 return LLVMBuildOr(ctx->gallivm.builder, val[0],
1879 LLVMBuildShl(ctx->gallivm.builder, val[1],
1880 LLVMConstInt(ctx->i32, 16, 0),
1881 ""), "");
1882 }
1883
1884 /* Upper 16 bits are ignored and will be dropped. */
1885 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct si_shader_context *ctx,
1886 LLVMValueRef val[2])
1887 {
1888 LLVMValueRef v[2] = {
1889 LLVMBuildAnd(ctx->gallivm.builder, val[0],
1890 LLVMConstInt(ctx->i32, 0xffff, 0), ""),
1891 val[1],
1892 };
1893 return si_llvm_pack_two_int16(ctx, v);
1894 }
1895
1896 /* Initialize arguments for the shader export intrinsic */
1897 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1898 LLVMValueRef *values,
1899 unsigned target,
1900 struct ac_export_args *args)
1901 {
1902 struct si_shader_context *ctx = si_shader_context(bld_base);
1903 struct lp_build_context *base = &bld_base->base;
1904 LLVMBuilderRef builder = ctx->gallivm.builder;
1905 LLVMValueRef val[4];
1906 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1907 unsigned chan;
1908 bool is_int8, is_int10;
1909
1910 /* Default is 0xf. Adjusted below depending on the format. */
1911 args->enabled_channels = 0xf; /* writemask */
1912
1913 /* Specify whether the EXEC mask represents the valid mask */
1914 args->valid_mask = 0;
1915
1916 /* Specify whether this is the last export */
1917 args->done = 0;
1918
1919 /* Specify the target we are exporting */
1920 args->target = target;
1921
1922 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1923 const struct si_shader_key *key = &ctx->shader->key;
1924 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
1925 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1926
1927 assert(cbuf >= 0 && cbuf < 8);
1928 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1929 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
1930 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
1931 }
1932
1933 args->compr = false;
1934 args->out[0] = base->undef;
1935 args->out[1] = base->undef;
1936 args->out[2] = base->undef;
1937 args->out[3] = base->undef;
1938
1939 switch (spi_shader_col_format) {
1940 case V_028714_SPI_SHADER_ZERO:
1941 args->enabled_channels = 0; /* writemask */
1942 args->target = V_008DFC_SQ_EXP_NULL;
1943 break;
1944
1945 case V_028714_SPI_SHADER_32_R:
1946 args->enabled_channels = 1; /* writemask */
1947 args->out[0] = values[0];
1948 break;
1949
1950 case V_028714_SPI_SHADER_32_GR:
1951 args->enabled_channels = 0x3; /* writemask */
1952 args->out[0] = values[0];
1953 args->out[1] = values[1];
1954 break;
1955
1956 case V_028714_SPI_SHADER_32_AR:
1957 args->enabled_channels = 0x9; /* writemask */
1958 args->out[0] = values[0];
1959 args->out[3] = values[3];
1960 break;
1961
1962 case V_028714_SPI_SHADER_FP16_ABGR:
1963 args->compr = 1; /* COMPR flag */
1964
1965 for (chan = 0; chan < 2; chan++) {
1966 LLVMValueRef pack_args[2] = {
1967 values[2 * chan],
1968 values[2 * chan + 1]
1969 };
1970 LLVMValueRef packed;
1971
1972 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
1973 args->out[chan] =
1974 LLVMBuildBitCast(ctx->gallivm.builder,
1975 packed, ctx->f32, "");
1976 }
1977 break;
1978
1979 case V_028714_SPI_SHADER_UNORM16_ABGR:
1980 for (chan = 0; chan < 4; chan++) {
1981 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
1982 val[chan] = LLVMBuildFMul(builder, val[chan],
1983 LLVMConstReal(ctx->f32, 65535), "");
1984 val[chan] = LLVMBuildFAdd(builder, val[chan],
1985 LLVMConstReal(ctx->f32, 0.5), "");
1986 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1987 ctx->i32, "");
1988 }
1989
1990 args->compr = 1; /* COMPR flag */
1991 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1992 si_llvm_pack_two_int16(ctx, val));
1993 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1994 si_llvm_pack_two_int16(ctx, val+2));
1995 break;
1996
1997 case V_028714_SPI_SHADER_SNORM16_ABGR:
1998 for (chan = 0; chan < 4; chan++) {
1999 /* Clamp between [-1, 1]. */
2000 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
2001 values[chan],
2002 LLVMConstReal(ctx->f32, 1));
2003 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
2004 val[chan],
2005 LLVMConstReal(ctx->f32, -1));
2006 /* Convert to a signed integer in [-32767, 32767]. */
2007 val[chan] = LLVMBuildFMul(builder, val[chan],
2008 LLVMConstReal(ctx->f32, 32767), "");
2009 /* If positive, add 0.5, else add -0.5. */
2010 val[chan] = LLVMBuildFAdd(builder, val[chan],
2011 LLVMBuildSelect(builder,
2012 LLVMBuildFCmp(builder, LLVMRealOGE,
2013 val[chan], base->zero, ""),
2014 LLVMConstReal(ctx->f32, 0.5),
2015 LLVMConstReal(ctx->f32, -0.5), ""), "");
2016 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2017 }
2018
2019 args->compr = 1; /* COMPR flag */
2020 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2021 si_llvm_pack_two_int32_as_int16(ctx, val));
2022 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2023 si_llvm_pack_two_int32_as_int16(ctx, val+2));
2024 break;
2025
2026 case V_028714_SPI_SHADER_UINT16_ABGR: {
2027 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2028 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
2029 LLVMValueRef max_alpha =
2030 !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
2031
2032 /* Clamp. */
2033 for (chan = 0; chan < 4; chan++) {
2034 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2035 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
2036 val[chan],
2037 chan == 3 ? max_alpha : max_rgb);
2038 }
2039
2040 args->compr = 1; /* COMPR flag */
2041 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2042 si_llvm_pack_two_int16(ctx, val));
2043 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2044 si_llvm_pack_two_int16(ctx, val+2));
2045 break;
2046 }
2047
2048 case V_028714_SPI_SHADER_SINT16_ABGR: {
2049 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2050 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
2051 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
2052 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
2053 LLVMValueRef max_alpha =
2054 !is_int10 ? max_rgb : ctx->i32_1;
2055 LLVMValueRef min_alpha =
2056 !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
2057
2058 /* Clamp. */
2059 for (chan = 0; chan < 4; chan++) {
2060 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2061 val[chan] = lp_build_emit_llvm_binary(bld_base,
2062 TGSI_OPCODE_IMIN,
2063 val[chan], chan == 3 ? max_alpha : max_rgb);
2064 val[chan] = lp_build_emit_llvm_binary(bld_base,
2065 TGSI_OPCODE_IMAX,
2066 val[chan], chan == 3 ? min_alpha : min_rgb);
2067 }
2068
2069 args->compr = 1; /* COMPR flag */
2070 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2071 si_llvm_pack_two_int32_as_int16(ctx, val));
2072 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2073 si_llvm_pack_two_int32_as_int16(ctx, val+2));
2074 break;
2075 }
2076
2077 case V_028714_SPI_SHADER_32_ABGR:
2078 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2079 break;
2080 }
2081 }
2082
2083 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2084 LLVMValueRef alpha)
2085 {
2086 struct si_shader_context *ctx = si_shader_context(bld_base);
2087
2088 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2089 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2090 SI_PARAM_ALPHA_REF);
2091
2092 LLVMValueRef alpha_pass =
2093 lp_build_cmp(&bld_base->base,
2094 ctx->shader->key.part.ps.epilog.alpha_func,
2095 alpha, alpha_ref);
2096 LLVMValueRef arg =
2097 lp_build_select(&bld_base->base,
2098 alpha_pass,
2099 LLVMConstReal(ctx->f32, 1.0f),
2100 LLVMConstReal(ctx->f32, -1.0f));
2101
2102 ac_build_kill(&ctx->ac, arg);
2103 } else {
2104 ac_build_kill(&ctx->ac, NULL);
2105 }
2106 }
2107
2108 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2109 LLVMValueRef alpha,
2110 unsigned samplemask_param)
2111 {
2112 struct si_shader_context *ctx = si_shader_context(bld_base);
2113 struct gallivm_state *gallivm = &ctx->gallivm;
2114 LLVMValueRef coverage;
2115
2116 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2117 coverage = LLVMGetParam(ctx->main_fn,
2118 samplemask_param);
2119 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
2120
2121 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
2122 ctx->i32,
2123 &coverage, 1, LP_FUNC_ATTR_READNONE);
2124
2125 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
2126 ctx->f32, "");
2127
2128 coverage = LLVMBuildFMul(gallivm->builder, coverage,
2129 LLVMConstReal(ctx->f32,
2130 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2131
2132 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
2133 }
2134
2135 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2136 struct ac_export_args *pos, LLVMValueRef *out_elts)
2137 {
2138 struct si_shader_context *ctx = si_shader_context(bld_base);
2139 struct lp_build_context *base = &bld_base->base;
2140 unsigned reg_index;
2141 unsigned chan;
2142 unsigned const_chan;
2143 LLVMValueRef base_elt;
2144 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2145 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2146 SI_VS_CONST_CLIP_PLANES, 0);
2147 LLVMValueRef const_resource = ac_build_indexed_load_const(&ctx->ac, ptr, constbuf_index);
2148
2149 for (reg_index = 0; reg_index < 2; reg_index ++) {
2150 struct ac_export_args *args = &pos[2 + reg_index];
2151
2152 args->out[0] =
2153 args->out[1] =
2154 args->out[2] =
2155 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2156
2157 /* Compute dot products of position and user clip plane vectors */
2158 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2159 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2160 LLVMValueRef addr =
2161 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2162 const_chan) * 4, 0);
2163 base_elt = buffer_load_const(ctx, const_resource,
2164 addr);
2165 args->out[chan] =
2166 lp_build_add(base, args->out[chan],
2167 lp_build_mul(base, base_elt,
2168 out_elts[const_chan]));
2169 }
2170 }
2171
2172 args->enabled_channels = 0xf;
2173 args->valid_mask = 0;
2174 args->done = 0;
2175 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2176 args->compr = 0;
2177 }
2178 }
2179
2180 static void si_dump_streamout(struct pipe_stream_output_info *so)
2181 {
2182 unsigned i;
2183
2184 if (so->num_outputs)
2185 fprintf(stderr, "STREAMOUT\n");
2186
2187 for (i = 0; i < so->num_outputs; i++) {
2188 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2189 so->output[i].start_component;
2190 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2191 i, so->output[i].output_buffer,
2192 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2193 so->output[i].register_index,
2194 mask & 1 ? "x" : "",
2195 mask & 2 ? "y" : "",
2196 mask & 4 ? "z" : "",
2197 mask & 8 ? "w" : "");
2198 }
2199 }
2200
2201 static void emit_streamout_output(struct si_shader_context *ctx,
2202 LLVMValueRef const *so_buffers,
2203 LLVMValueRef const *so_write_offsets,
2204 struct pipe_stream_output *stream_out,
2205 struct si_shader_output_values *shader_out)
2206 {
2207 struct gallivm_state *gallivm = &ctx->gallivm;
2208 LLVMBuilderRef builder = gallivm->builder;
2209 unsigned buf_idx = stream_out->output_buffer;
2210 unsigned start = stream_out->start_component;
2211 unsigned num_comps = stream_out->num_components;
2212 LLVMValueRef out[4];
2213
2214 assert(num_comps && num_comps <= 4);
2215 if (!num_comps || num_comps > 4)
2216 return;
2217
2218 /* Load the output as int. */
2219 for (int j = 0; j < num_comps; j++) {
2220 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2221
2222 out[j] = LLVMBuildBitCast(builder,
2223 shader_out->values[start + j],
2224 ctx->i32, "");
2225 }
2226
2227 /* Pack the output. */
2228 LLVMValueRef vdata = NULL;
2229
2230 switch (num_comps) {
2231 case 1: /* as i32 */
2232 vdata = out[0];
2233 break;
2234 case 2: /* as v2i32 */
2235 case 3: /* as v4i32 (aligned to 4) */
2236 case 4: /* as v4i32 */
2237 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2238 for (int j = 0; j < num_comps; j++) {
2239 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2240 LLVMConstInt(ctx->i32, j, 0), "");
2241 }
2242 break;
2243 }
2244
2245 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2246 vdata, num_comps,
2247 so_write_offsets[buf_idx],
2248 ctx->i32_0,
2249 stream_out->dst_offset * 4, 1, 1, true, false);
2250 }
2251
2252 /**
2253 * Write streamout data to buffers for vertex stream @p stream (different
2254 * vertex streams can occur for GS copy shaders).
2255 */
2256 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2257 struct si_shader_output_values *outputs,
2258 unsigned noutput, unsigned stream)
2259 {
2260 struct si_shader_selector *sel = ctx->shader->selector;
2261 struct pipe_stream_output_info *so = &sel->so;
2262 struct gallivm_state *gallivm = &ctx->gallivm;
2263 LLVMBuilderRef builder = gallivm->builder;
2264 int i;
2265 struct lp_build_if_state if_ctx;
2266
2267 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2268 LLVMValueRef so_vtx_count =
2269 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2270
2271 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2272
2273 /* can_emit = tid < so_vtx_count; */
2274 LLVMValueRef can_emit =
2275 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2276
2277 /* Emit the streamout code conditionally. This actually avoids
2278 * out-of-bounds buffer access. The hw tells us via the SGPR
2279 * (so_vtx_count) which threads are allowed to emit streamout data. */
2280 lp_build_if(&if_ctx, gallivm, can_emit);
2281 {
2282 /* The buffer offset is computed as follows:
2283 * ByteOffset = streamout_offset[buffer_id]*4 +
2284 * (streamout_write_index + thread_id)*stride[buffer_id] +
2285 * attrib_offset
2286 */
2287
2288 LLVMValueRef so_write_index =
2289 LLVMGetParam(ctx->main_fn,
2290 ctx->param_streamout_write_index);
2291
2292 /* Compute (streamout_write_index + thread_id). */
2293 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2294
2295 /* Load the descriptor and compute the write offset for each
2296 * enabled buffer. */
2297 LLVMValueRef so_write_offset[4] = {};
2298 LLVMValueRef so_buffers[4];
2299 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2300 ctx->param_rw_buffers);
2301
2302 for (i = 0; i < 4; i++) {
2303 if (!so->stride[i])
2304 continue;
2305
2306 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2307 SI_VS_STREAMOUT_BUF0 + i, 0);
2308
2309 so_buffers[i] = ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
2310
2311 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2312 ctx->param_streamout_offset[i]);
2313 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2314
2315 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2316 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2317 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2318 }
2319
2320 /* Write streamout data. */
2321 for (i = 0; i < so->num_outputs; i++) {
2322 unsigned reg = so->output[i].register_index;
2323
2324 if (reg >= noutput)
2325 continue;
2326
2327 if (stream != so->output[i].stream)
2328 continue;
2329
2330 emit_streamout_output(ctx, so_buffers, so_write_offset,
2331 &so->output[i], &outputs[reg]);
2332 }
2333 }
2334 lp_build_endif(&if_ctx);
2335 }
2336
2337 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2338 LLVMValueRef *values)
2339 {
2340 struct ac_export_args args;
2341
2342 si_llvm_init_export_args(&ctx->bld_base, values,
2343 V_008DFC_SQ_EXP_PARAM + index, &args);
2344 ac_build_export(&ctx->ac, &args);
2345 }
2346
2347 static void si_build_param_exports(struct si_shader_context *ctx,
2348 struct si_shader_output_values *outputs,
2349 unsigned noutput)
2350 {
2351 struct si_shader *shader = ctx->shader;
2352 unsigned param_count = 0;
2353
2354 for (unsigned i = 0; i < noutput; i++) {
2355 unsigned semantic_name = outputs[i].semantic_name;
2356 unsigned semantic_index = outputs[i].semantic_index;
2357
2358 if (outputs[i].vertex_stream[0] != 0 &&
2359 outputs[i].vertex_stream[1] != 0 &&
2360 outputs[i].vertex_stream[2] != 0 &&
2361 outputs[i].vertex_stream[3] != 0)
2362 continue;
2363
2364 switch (semantic_name) {
2365 case TGSI_SEMANTIC_LAYER:
2366 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2367 case TGSI_SEMANTIC_CLIPDIST:
2368 case TGSI_SEMANTIC_COLOR:
2369 case TGSI_SEMANTIC_BCOLOR:
2370 case TGSI_SEMANTIC_PRIMID:
2371 case TGSI_SEMANTIC_FOG:
2372 case TGSI_SEMANTIC_TEXCOORD:
2373 case TGSI_SEMANTIC_GENERIC:
2374 break;
2375 default:
2376 continue;
2377 }
2378
2379 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2380 semantic_index < SI_MAX_IO_GENERIC) &&
2381 shader->key.opt.kill_outputs &
2382 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2383 continue;
2384
2385 si_export_param(ctx, param_count, outputs[i].values);
2386
2387 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2388 shader->info.vs_output_param_offset[i] = param_count++;
2389 }
2390
2391 shader->info.nr_param_exports = param_count;
2392 }
2393
2394 /* Generate export instructions for hardware VS shader stage */
2395 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2396 struct si_shader_output_values *outputs,
2397 unsigned noutput)
2398 {
2399 struct si_shader_context *ctx = si_shader_context(bld_base);
2400 struct si_shader *shader = ctx->shader;
2401 struct lp_build_context *base = &bld_base->base;
2402 struct ac_export_args pos_args[4] = {};
2403 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2404 unsigned pos_idx;
2405 int i;
2406
2407 /* Build position exports. */
2408 for (i = 0; i < noutput; i++) {
2409 switch (outputs[i].semantic_name) {
2410 case TGSI_SEMANTIC_POSITION:
2411 si_llvm_init_export_args(bld_base, outputs[i].values,
2412 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2413 break;
2414 case TGSI_SEMANTIC_PSIZE:
2415 psize_value = outputs[i].values[0];
2416 break;
2417 case TGSI_SEMANTIC_LAYER:
2418 layer_value = outputs[i].values[0];
2419 break;
2420 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2421 viewport_index_value = outputs[i].values[0];
2422 break;
2423 case TGSI_SEMANTIC_EDGEFLAG:
2424 edgeflag_value = outputs[i].values[0];
2425 break;
2426 case TGSI_SEMANTIC_CLIPDIST:
2427 if (!shader->key.opt.clip_disable) {
2428 unsigned index = 2 + outputs[i].semantic_index;
2429 si_llvm_init_export_args(bld_base, outputs[i].values,
2430 V_008DFC_SQ_EXP_POS + index,
2431 &pos_args[index]);
2432 }
2433 break;
2434 case TGSI_SEMANTIC_CLIPVERTEX:
2435 if (!shader->key.opt.clip_disable) {
2436 si_llvm_emit_clipvertex(bld_base, pos_args,
2437 outputs[i].values);
2438 }
2439 break;
2440 }
2441 }
2442
2443 /* We need to add the position output manually if it's missing. */
2444 if (!pos_args[0].out[0]) {
2445 pos_args[0].enabled_channels = 0xf; /* writemask */
2446 pos_args[0].valid_mask = 0; /* EXEC mask */
2447 pos_args[0].done = 0; /* last export? */
2448 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2449 pos_args[0].compr = 0; /* COMPR flag */
2450 pos_args[0].out[0] = base->zero; /* X */
2451 pos_args[0].out[1] = base->zero; /* Y */
2452 pos_args[0].out[2] = base->zero; /* Z */
2453 pos_args[0].out[3] = base->one; /* W */
2454 }
2455
2456 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2457 if (shader->selector->info.writes_psize ||
2458 shader->selector->info.writes_edgeflag ||
2459 shader->selector->info.writes_viewport_index ||
2460 shader->selector->info.writes_layer) {
2461 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2462 (shader->selector->info.writes_edgeflag << 1) |
2463 (shader->selector->info.writes_layer << 2);
2464
2465 pos_args[1].valid_mask = 0; /* EXEC mask */
2466 pos_args[1].done = 0; /* last export? */
2467 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2468 pos_args[1].compr = 0; /* COMPR flag */
2469 pos_args[1].out[0] = base->zero; /* X */
2470 pos_args[1].out[1] = base->zero; /* Y */
2471 pos_args[1].out[2] = base->zero; /* Z */
2472 pos_args[1].out[3] = base->zero; /* W */
2473
2474 if (shader->selector->info.writes_psize)
2475 pos_args[1].out[0] = psize_value;
2476
2477 if (shader->selector->info.writes_edgeflag) {
2478 /* The output is a float, but the hw expects an integer
2479 * with the first bit containing the edge flag. */
2480 edgeflag_value = LLVMBuildFPToUI(ctx->gallivm.builder,
2481 edgeflag_value,
2482 ctx->i32, "");
2483 edgeflag_value = lp_build_min(&bld_base->int_bld,
2484 edgeflag_value,
2485 ctx->i32_1);
2486
2487 /* The LLVM intrinsic expects a float. */
2488 pos_args[1].out[1] = LLVMBuildBitCast(ctx->gallivm.builder,
2489 edgeflag_value,
2490 ctx->f32, "");
2491 }
2492
2493 if (ctx->screen->b.chip_class >= GFX9) {
2494 /* GFX9 has the layer in out.z[10:0] and the viewport
2495 * index in out.z[19:16].
2496 */
2497 if (shader->selector->info.writes_layer)
2498 pos_args[1].out[2] = layer_value;
2499
2500 if (shader->selector->info.writes_viewport_index) {
2501 LLVMValueRef v = viewport_index_value;
2502
2503 v = bitcast(bld_base, TGSI_TYPE_UNSIGNED, v);
2504 v = LLVMBuildShl(ctx->gallivm.builder, v,
2505 LLVMConstInt(ctx->i32, 16, 0), "");
2506 v = LLVMBuildOr(ctx->gallivm.builder, v,
2507 bitcast(bld_base, TGSI_TYPE_UNSIGNED,
2508 pos_args[1].out[2]), "");
2509 pos_args[1].out[2] = bitcast(bld_base, TGSI_TYPE_FLOAT, v);
2510 pos_args[1].enabled_channels |= 1 << 2;
2511 }
2512 } else {
2513 if (shader->selector->info.writes_layer)
2514 pos_args[1].out[2] = layer_value;
2515
2516 if (shader->selector->info.writes_viewport_index) {
2517 pos_args[1].out[3] = viewport_index_value;
2518 pos_args[1].enabled_channels |= 1 << 3;
2519 }
2520 }
2521 }
2522
2523 for (i = 0; i < 4; i++)
2524 if (pos_args[i].out[0])
2525 shader->info.nr_pos_exports++;
2526
2527 pos_idx = 0;
2528 for (i = 0; i < 4; i++) {
2529 if (!pos_args[i].out[0])
2530 continue;
2531
2532 /* Specify the target we are exporting */
2533 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2534
2535 if (pos_idx == shader->info.nr_pos_exports)
2536 /* Specify that this is the last export */
2537 pos_args[i].done = 1;
2538
2539 ac_build_export(&ctx->ac, &pos_args[i]);
2540 }
2541
2542 /* Build parameter exports. */
2543 si_build_param_exports(ctx, outputs, noutput);
2544 }
2545
2546 /**
2547 * Forward all outputs from the vertex shader to the TES. This is only used
2548 * for the fixed function TCS.
2549 */
2550 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2551 {
2552 struct si_shader_context *ctx = si_shader_context(bld_base);
2553 struct gallivm_state *gallivm = &ctx->gallivm;
2554 LLVMValueRef invocation_id, buffer, buffer_offset;
2555 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2556 uint64_t inputs;
2557
2558 invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
2559 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
2560 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2561
2562 lds_vertex_stride = unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
2563 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2564 lds_vertex_stride, "");
2565 lds_base = get_tcs_in_current_patch_offset(ctx);
2566 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2567
2568 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
2569 while (inputs) {
2570 unsigned i = u_bit_scan64(&inputs);
2571
2572 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2573 LLVMConstInt(ctx->i32, 4 * i, 0),
2574 "");
2575
2576 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2577 get_rel_patch_id(ctx),
2578 invocation_id,
2579 LLVMConstInt(ctx->i32, i, 0));
2580
2581 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2582 lds_ptr);
2583
2584 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
2585 buffer_offset, 0, 1, 0, true, false);
2586 }
2587 }
2588
2589 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2590 LLVMValueRef rel_patch_id,
2591 LLVMValueRef invocation_id,
2592 LLVMValueRef tcs_out_current_patch_data_offset)
2593 {
2594 struct si_shader_context *ctx = si_shader_context(bld_base);
2595 struct gallivm_state *gallivm = &ctx->gallivm;
2596 struct si_shader *shader = ctx->shader;
2597 unsigned tess_inner_index, tess_outer_index;
2598 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2599 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2600 unsigned stride, outer_comps, inner_comps, i, offset;
2601 struct lp_build_if_state if_ctx, inner_if_ctx;
2602
2603 si_llvm_emit_barrier(NULL, bld_base, NULL);
2604
2605 /* Do this only for invocation 0, because the tess levels are per-patch,
2606 * not per-vertex.
2607 *
2608 * This can't jump, because invocation 0 executes this. It should
2609 * at least mask out the loads and stores for other invocations.
2610 */
2611 lp_build_if(&if_ctx, gallivm,
2612 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2613 invocation_id, ctx->i32_0, ""));
2614
2615 /* Determine the layout of one tess factor element in the buffer. */
2616 switch (shader->key.part.tcs.epilog.prim_mode) {
2617 case PIPE_PRIM_LINES:
2618 stride = 2; /* 2 dwords, 1 vec2 store */
2619 outer_comps = 2;
2620 inner_comps = 0;
2621 break;
2622 case PIPE_PRIM_TRIANGLES:
2623 stride = 4; /* 4 dwords, 1 vec4 store */
2624 outer_comps = 3;
2625 inner_comps = 1;
2626 break;
2627 case PIPE_PRIM_QUADS:
2628 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2629 outer_comps = 4;
2630 inner_comps = 2;
2631 break;
2632 default:
2633 assert(0);
2634 return;
2635 }
2636
2637 /* Load tess_inner and tess_outer from LDS.
2638 * Any invocation can write them, so we can't get them from a temporary.
2639 */
2640 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
2641 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
2642
2643 lds_base = tcs_out_current_patch_data_offset;
2644 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2645 LLVMConstInt(ctx->i32,
2646 tess_inner_index * 4, 0), "");
2647 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2648 LLVMConstInt(ctx->i32,
2649 tess_outer_index * 4, 0), "");
2650
2651 for (i = 0; i < 4; i++) {
2652 inner[i] = LLVMGetUndef(ctx->i32);
2653 outer[i] = LLVMGetUndef(ctx->i32);
2654 }
2655
2656 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2657 /* For isolines, the hardware expects tess factors in the
2658 * reverse order from what GLSL / TGSI specify.
2659 */
2660 outer[0] = out[1] = lds_load(bld_base, TGSI_TYPE_SIGNED, 0, lds_outer);
2661 outer[1] = out[0] = lds_load(bld_base, TGSI_TYPE_SIGNED, 1, lds_outer);
2662 } else {
2663 for (i = 0; i < outer_comps; i++) {
2664 outer[i] = out[i] =
2665 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2666 }
2667 for (i = 0; i < inner_comps; i++) {
2668 inner[i] = out[outer_comps+i] =
2669 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2670 }
2671 }
2672
2673 /* Convert the outputs to vectors for stores. */
2674 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2675 vec1 = NULL;
2676
2677 if (stride > 4)
2678 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2679
2680 /* Get the buffer. */
2681 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_factor_addr_base64k);
2682
2683 /* Get the offset. */
2684 tf_base = LLVMGetParam(ctx->main_fn,
2685 ctx->param_tcs_factor_offset);
2686 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2687 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
2688
2689 lp_build_if(&inner_if_ctx, gallivm,
2690 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2691 rel_patch_id, ctx->i32_0, ""));
2692
2693 /* Store the dynamic HS control word. */
2694 offset = 0;
2695 if (ctx->screen->b.chip_class <= VI) {
2696 ac_build_buffer_store_dword(&ctx->ac, buffer,
2697 LLVMConstInt(ctx->i32, 0x80000000, 0),
2698 1, ctx->i32_0, tf_base,
2699 offset, 1, 0, true, false);
2700 offset += 4;
2701 }
2702
2703 lp_build_endif(&inner_if_ctx);
2704
2705 /* Store the tessellation factors. */
2706 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2707 MIN2(stride, 4), byteoffset, tf_base,
2708 offset, 1, 0, true, false);
2709 offset += 16;
2710 if (vec1)
2711 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2712 stride - 4, byteoffset, tf_base,
2713 offset, 1, 0, true, false);
2714
2715 /* Store the tess factors into the offchip buffer if TES reads them. */
2716 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
2717 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
2718 LLVMValueRef tf_inner_offset;
2719 unsigned param_outer, param_inner;
2720
2721 buf = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
2722 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2723
2724 param_outer = si_shader_io_get_unique_index_patch(
2725 TGSI_SEMANTIC_TESSOUTER, 0);
2726 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2727 LLVMConstInt(ctx->i32, param_outer, 0));
2728
2729 outer_vec = lp_build_gather_values(gallivm, outer,
2730 util_next_power_of_two(outer_comps));
2731
2732 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
2733 outer_comps, tf_outer_offset,
2734 base, 0, 1, 0, true, false);
2735 if (inner_comps) {
2736 param_inner = si_shader_io_get_unique_index_patch(
2737 TGSI_SEMANTIC_TESSINNER, 0);
2738 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2739 LLVMConstInt(ctx->i32, param_inner, 0));
2740
2741 inner_vec = inner_comps == 1 ? inner[0] :
2742 lp_build_gather_values(gallivm, inner, inner_comps);
2743 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
2744 inner_comps, tf_inner_offset,
2745 base, 0, 1, 0, true, false);
2746 }
2747 }
2748
2749 lp_build_endif(&if_ctx);
2750 }
2751
2752 static LLVMValueRef
2753 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
2754 unsigned param, unsigned return_index)
2755 {
2756 return LLVMBuildInsertValue(ctx->gallivm.builder, ret,
2757 LLVMGetParam(ctx->main_fn, param),
2758 return_index, "");
2759 }
2760
2761 static LLVMValueRef
2762 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
2763 unsigned param, unsigned return_index)
2764 {
2765 LLVMBuilderRef builder = ctx->gallivm.builder;
2766 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
2767
2768 return LLVMBuildInsertValue(builder, ret,
2769 LLVMBuildBitCast(builder, p, ctx->f32, ""),
2770 return_index, "");
2771 }
2772
2773 static LLVMValueRef
2774 si_insert_input_ptr_as_2xi32(struct si_shader_context *ctx, LLVMValueRef ret,
2775 unsigned param, unsigned return_index)
2776 {
2777 LLVMBuilderRef builder = ctx->gallivm.builder;
2778 LLVMValueRef ptr, lo, hi;
2779
2780 ptr = LLVMGetParam(ctx->main_fn, param);
2781 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
2782 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
2783 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
2784 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
2785 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
2786 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
2787 }
2788
2789 /* This only writes the tessellation factor levels. */
2790 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2791 {
2792 struct si_shader_context *ctx = si_shader_context(bld_base);
2793 LLVMBuilderRef builder = ctx->gallivm.builder;
2794 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2795
2796 si_copy_tcs_inputs(bld_base);
2797
2798 rel_patch_id = get_rel_patch_id(ctx);
2799 invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
2800 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2801
2802 if (ctx->screen->b.chip_class >= GFX9) {
2803 LLVMBasicBlockRef blocks[2] = {
2804 LLVMGetInsertBlock(builder),
2805 ctx->merged_wrap_if_state.entry_block
2806 };
2807 LLVMValueRef values[2];
2808
2809 lp_build_endif(&ctx->merged_wrap_if_state);
2810
2811 values[0] = rel_patch_id;
2812 values[1] = LLVMGetUndef(ctx->i32);
2813 rel_patch_id = build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
2814
2815 values[0] = tf_lds_offset;
2816 values[1] = LLVMGetUndef(ctx->i32);
2817 tf_lds_offset = build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
2818
2819 values[0] = invocation_id;
2820 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
2821 invocation_id = build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
2822 }
2823
2824 /* Return epilog parameters from this function. */
2825 LLVMValueRef ret = ctx->return_value;
2826 unsigned vgpr;
2827
2828 if (ctx->screen->b.chip_class >= GFX9) {
2829 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
2830 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
2831 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
2832 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
2833 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
2834 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
2835 /* Tess offchip and tess factor offsets are at the beginning. */
2836 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
2837 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
2838 vgpr = 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K + 1;
2839 } else {
2840 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
2841 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
2842 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
2843 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
2844 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
2845 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K);
2846 /* Tess offchip and tess factor offsets are after user SGPRs. */
2847 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
2848 GFX6_TCS_NUM_USER_SGPR);
2849 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
2850 GFX6_TCS_NUM_USER_SGPR + 1);
2851 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
2852 }
2853
2854 /* VGPRs */
2855 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2856 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2857 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2858
2859 /* Leave a hole corresponding to the two input VGPRs. This ensures that
2860 * the invocation_id output does not alias the param_tcs_rel_ids input,
2861 * which saves a V_MOV on gfx9.
2862 */
2863 vgpr += 2;
2864
2865 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2866 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2867 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2868 ctx->return_value = ret;
2869 }
2870
2871 /* Pass TCS inputs from LS to TCS on GFX9. */
2872 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
2873 {
2874 LLVMValueRef ret = ctx->return_value;
2875
2876 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers, 0);
2877 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
2878 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
2879 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
2880 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
2881
2882 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
2883 8 + SI_SGPR_VS_STATE_BITS);
2884 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
2885 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
2886 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
2887 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
2888 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
2889 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
2890 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
2891 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
2892 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
2893 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
2894
2895 unsigned desc_param = ctx->param_tcs_factor_addr_base64k + 2;
2896 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
2897 8 + GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS);
2898 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
2899 8 + GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES);
2900
2901 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
2902 ret = si_insert_input_ret_float(ctx, ret,
2903 ctx->param_tcs_patch_id, vgpr++);
2904 ret = si_insert_input_ret_float(ctx, ret,
2905 ctx->param_tcs_rel_ids, vgpr++);
2906 ctx->return_value = ret;
2907 }
2908
2909 /* Pass GS inputs from ES to GS on GFX9. */
2910 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
2911 {
2912 LLVMValueRef ret = ctx->return_value;
2913
2914 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers, 0);
2915 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
2916 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
2917
2918 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
2919
2920 unsigned desc_param = ctx->param_vs_state_bits + 1;
2921 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
2922 8 + GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS);
2923 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
2924 8 + GFX9_SGPR_GS_SAMPLERS_AND_IMAGES);
2925
2926 unsigned vgpr = 8 + GFX9_GS_NUM_USER_SGPR;
2927 for (unsigned i = 0; i < 5; i++) {
2928 unsigned param = ctx->param_gs_vtx01_offset + i;
2929 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
2930 }
2931 ctx->return_value = ret;
2932 }
2933
2934 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2935 {
2936 struct si_shader_context *ctx = si_shader_context(bld_base);
2937 struct si_shader *shader = ctx->shader;
2938 struct tgsi_shader_info *info = &shader->selector->info;
2939 struct gallivm_state *gallivm = &ctx->gallivm;
2940 unsigned i, chan;
2941 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
2942 ctx->param_rel_auto_id);
2943 LLVMValueRef vertex_dw_stride =
2944 unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
2945 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2946 vertex_dw_stride, "");
2947
2948 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2949 * its inputs from it. */
2950 for (i = 0; i < info->num_outputs; i++) {
2951 LLVMValueRef *out_ptr = ctx->outputs[i];
2952 unsigned name = info->output_semantic_name[i];
2953 unsigned index = info->output_semantic_index[i];
2954
2955 /* The ARB_shader_viewport_layer_array spec contains the
2956 * following issue:
2957 *
2958 * 2) What happens if gl_ViewportIndex or gl_Layer is
2959 * written in the vertex shader and a geometry shader is
2960 * present?
2961 *
2962 * RESOLVED: The value written by the last vertex processing
2963 * stage is used. If the last vertex processing stage
2964 * (vertex, tessellation evaluation or geometry) does not
2965 * statically assign to gl_ViewportIndex or gl_Layer, index
2966 * or layer zero is assumed.
2967 *
2968 * So writes to those outputs in VS-as-LS are simply ignored.
2969 */
2970 if (name == TGSI_SEMANTIC_LAYER ||
2971 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
2972 continue;
2973
2974 int param = si_shader_io_get_unique_index(name, index);
2975 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2976 LLVMConstInt(ctx->i32, param * 4, 0), "");
2977
2978 for (chan = 0; chan < 4; chan++) {
2979 lds_store(bld_base, chan, dw_addr,
2980 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2981 }
2982 }
2983
2984 if (ctx->screen->b.chip_class >= GFX9)
2985 si_set_ls_return_value_for_tcs(ctx);
2986 }
2987
2988 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2989 {
2990 struct si_shader_context *ctx = si_shader_context(bld_base);
2991 struct gallivm_state *gallivm = &ctx->gallivm;
2992 struct si_shader *es = ctx->shader;
2993 struct tgsi_shader_info *info = &es->selector->info;
2994 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
2995 ctx->param_es2gs_offset);
2996 LLVMValueRef lds_base = NULL;
2997 unsigned chan;
2998 int i;
2999
3000 if (ctx->screen->b.chip_class >= GFX9 && info->num_outputs) {
3001 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3002 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3003 LLVMValueRef wave_idx = unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3004 vertex_idx = LLVMBuildOr(gallivm->builder, vertex_idx,
3005 LLVMBuildMul(gallivm->builder, wave_idx,
3006 LLVMConstInt(ctx->i32, 64, false), ""), "");
3007 lds_base = LLVMBuildMul(gallivm->builder, vertex_idx,
3008 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3009 }
3010
3011 for (i = 0; i < info->num_outputs; i++) {
3012 LLVMValueRef *out_ptr = ctx->outputs[i];
3013 int param;
3014
3015 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3016 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3017 continue;
3018
3019 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3020 info->output_semantic_index[i]);
3021
3022 for (chan = 0; chan < 4; chan++) {
3023 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3024 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
3025
3026 /* GFX9 has the ESGS ring in LDS. */
3027 if (ctx->screen->b.chip_class >= GFX9) {
3028 lds_store(bld_base, param * 4 + chan, lds_base, out_val);
3029 continue;
3030 }
3031
3032 ac_build_buffer_store_dword(&ctx->ac,
3033 ctx->esgs_ring,
3034 out_val, 1, NULL, soffset,
3035 (4 * param + chan) * 4,
3036 1, 1, true, true);
3037 }
3038 }
3039
3040 if (ctx->screen->b.chip_class >= GFX9)
3041 si_set_es_return_value_for_gs(ctx);
3042 }
3043
3044 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3045 {
3046 if (ctx->screen->b.chip_class >= GFX9)
3047 return unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3048 else
3049 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3050 }
3051
3052 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3053 {
3054 struct si_shader_context *ctx = si_shader_context(bld_base);
3055
3056 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3057 si_get_gs_wave_id(ctx));
3058
3059 if (ctx->screen->b.chip_class >= GFX9)
3060 lp_build_endif(&ctx->merged_wrap_if_state);
3061 }
3062
3063 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3064 unsigned max_outputs,
3065 LLVMValueRef *addrs)
3066 {
3067 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3068 struct gallivm_state *gallivm = &ctx->gallivm;
3069 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3070 struct si_shader_output_values *outputs = NULL;
3071 int i,j;
3072
3073 assert(!ctx->shader->is_gs_copy_shader);
3074 assert(info->num_outputs <= max_outputs);
3075
3076 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3077
3078 /* Vertex color clamping.
3079 *
3080 * This uses a state constant loaded in a user data SGPR and
3081 * an IF statement is added that clamps all colors if the constant
3082 * is true.
3083 */
3084 if (ctx->type == PIPE_SHADER_VERTEX) {
3085 struct lp_build_if_state if_ctx;
3086 LLVMValueRef cond = NULL;
3087 LLVMValueRef addr, val;
3088
3089 for (i = 0; i < info->num_outputs; i++) {
3090 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3091 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3092 continue;
3093
3094 /* We've found a color. */
3095 if (!cond) {
3096 /* The state is in the first bit of the user SGPR. */
3097 cond = LLVMGetParam(ctx->main_fn,
3098 ctx->param_vs_state_bits);
3099 cond = LLVMBuildTrunc(gallivm->builder, cond,
3100 ctx->i1, "");
3101 lp_build_if(&if_ctx, gallivm, cond);
3102 }
3103
3104 for (j = 0; j < 4; j++) {
3105 addr = addrs[4 * i + j];
3106 val = LLVMBuildLoad(gallivm->builder, addr, "");
3107 val = ac_build_clamp(&ctx->ac, val);
3108 LLVMBuildStore(gallivm->builder, val, addr);
3109 }
3110 }
3111
3112 if (cond)
3113 lp_build_endif(&if_ctx);
3114 }
3115
3116 for (i = 0; i < info->num_outputs; i++) {
3117 outputs[i].semantic_name = info->output_semantic_name[i];
3118 outputs[i].semantic_index = info->output_semantic_index[i];
3119
3120 for (j = 0; j < 4; j++) {
3121 outputs[i].values[j] =
3122 LLVMBuildLoad(gallivm->builder,
3123 addrs[4 * i + j],
3124 "");
3125 outputs[i].vertex_stream[j] =
3126 (info->output_streams[i] >> (2 * j)) & 3;
3127 }
3128 }
3129
3130 if (ctx->shader->selector->so.num_outputs)
3131 si_llvm_emit_streamout(ctx, outputs, i, 0);
3132
3133 /* Export PrimitiveID. */
3134 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3135 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3136 outputs[i].semantic_index = 0;
3137 outputs[i].values[0] = LLVMBuildBitCast(gallivm->builder,
3138 get_primitive_id(ctx, 0), ctx->f32, "");
3139 for (j = 1; j < 4; j++)
3140 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3141
3142 memset(outputs[i].vertex_stream, 0,
3143 sizeof(outputs[i].vertex_stream));
3144 i++;
3145 }
3146
3147 si_llvm_export_vs(&ctx->bld_base, outputs, i);
3148 FREE(outputs);
3149 }
3150
3151 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3152 {
3153 struct si_shader_context *ctx = si_shader_context(bld_base);
3154
3155 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3156 &ctx->outputs[0][0]);
3157 }
3158
3159 struct si_ps_exports {
3160 unsigned num;
3161 struct ac_export_args args[10];
3162 };
3163
3164 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
3165 bool writes_samplemask)
3166 {
3167 if (writes_z) {
3168 /* Z needs 32 bits. */
3169 if (writes_samplemask)
3170 return V_028710_SPI_SHADER_32_ABGR;
3171 else if (writes_stencil)
3172 return V_028710_SPI_SHADER_32_GR;
3173 else
3174 return V_028710_SPI_SHADER_32_R;
3175 } else if (writes_stencil || writes_samplemask) {
3176 /* Both stencil and sample mask need only 16 bits. */
3177 return V_028710_SPI_SHADER_UINT16_ABGR;
3178 } else {
3179 return V_028710_SPI_SHADER_ZERO;
3180 }
3181 }
3182
3183 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3184 LLVMValueRef depth, LLVMValueRef stencil,
3185 LLVMValueRef samplemask, struct si_ps_exports *exp)
3186 {
3187 struct si_shader_context *ctx = si_shader_context(bld_base);
3188 struct lp_build_context *base = &bld_base->base;
3189 struct ac_export_args args;
3190 unsigned mask = 0;
3191 unsigned format = si_get_spi_shader_z_format(depth != NULL,
3192 stencil != NULL,
3193 samplemask != NULL);
3194
3195 assert(depth || stencil || samplemask);
3196
3197 args.valid_mask = 1; /* whether the EXEC mask is valid */
3198 args.done = 1; /* DONE bit */
3199
3200 /* Specify the target we are exporting */
3201 args.target = V_008DFC_SQ_EXP_MRTZ;
3202
3203 args.compr = 0; /* COMP flag */
3204 args.out[0] = base->undef; /* R, depth */
3205 args.out[1] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
3206 args.out[2] = base->undef; /* B, sample mask */
3207 args.out[3] = base->undef; /* A, alpha to mask */
3208
3209 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
3210 assert(!depth);
3211 args.compr = 1; /* COMPR flag */
3212
3213 if (stencil) {
3214 /* Stencil should be in X[23:16]. */
3215 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
3216 stencil = LLVMBuildShl(ctx->gallivm.builder, stencil,
3217 LLVMConstInt(ctx->i32, 16, 0), "");
3218 args.out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
3219 mask |= 0x3;
3220 }
3221 if (samplemask) {
3222 /* SampleMask should be in Y[15:0]. */
3223 args.out[1] = samplemask;
3224 mask |= 0xc;
3225 }
3226 } else {
3227 if (depth) {
3228 args.out[0] = depth;
3229 mask |= 0x1;
3230 }
3231 if (stencil) {
3232 args.out[1] = stencil;
3233 mask |= 0x2;
3234 }
3235 if (samplemask) {
3236 args.out[2] = samplemask;
3237 mask |= 0x4;
3238 }
3239 }
3240
3241 /* SI (except OLAND and HAINAN) has a bug that it only looks
3242 * at the X writemask component. */
3243 if (ctx->screen->b.chip_class == SI &&
3244 ctx->screen->b.family != CHIP_OLAND &&
3245 ctx->screen->b.family != CHIP_HAINAN)
3246 mask |= 0x1;
3247
3248 /* Specify which components to enable */
3249 args.enabled_channels = mask;
3250
3251 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3252 }
3253
3254 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3255 LLVMValueRef *color, unsigned index,
3256 unsigned samplemask_param,
3257 bool is_last, struct si_ps_exports *exp)
3258 {
3259 struct si_shader_context *ctx = si_shader_context(bld_base);
3260 struct lp_build_context *base = &bld_base->base;
3261 int i;
3262
3263 /* Clamp color */
3264 if (ctx->shader->key.part.ps.epilog.clamp_color)
3265 for (i = 0; i < 4; i++)
3266 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3267
3268 /* Alpha to one */
3269 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3270 color[3] = base->one;
3271
3272 /* Alpha test */
3273 if (index == 0 &&
3274 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3275 si_alpha_test(bld_base, color[3]);
3276
3277 /* Line & polygon smoothing */
3278 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3279 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3280 samplemask_param);
3281
3282 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3283 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3284 struct ac_export_args args[8];
3285 int c, last = -1;
3286
3287 /* Get the export arguments, also find out what the last one is. */
3288 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3289 si_llvm_init_export_args(bld_base, color,
3290 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3291 if (args[c].enabled_channels)
3292 last = c;
3293 }
3294
3295 /* Emit all exports. */
3296 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3297 if (is_last && last == c) {
3298 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3299 args[c].done = 1; /* DONE bit */
3300 } else if (!args[c].enabled_channels)
3301 continue; /* unnecessary NULL export */
3302
3303 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3304 }
3305 } else {
3306 struct ac_export_args args;
3307
3308 /* Export */
3309 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
3310 &args);
3311 if (is_last) {
3312 args.valid_mask = 1; /* whether the EXEC mask is valid */
3313 args.done = 1; /* DONE bit */
3314 } else if (!args.enabled_channels)
3315 return; /* unnecessary NULL export */
3316
3317 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3318 }
3319 }
3320
3321 static void si_emit_ps_exports(struct si_shader_context *ctx,
3322 struct si_ps_exports *exp)
3323 {
3324 for (unsigned i = 0; i < exp->num; i++)
3325 ac_build_export(&ctx->ac, &exp->args[i]);
3326 }
3327
3328 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3329 {
3330 struct si_shader_context *ctx = si_shader_context(bld_base);
3331 struct lp_build_context *base = &bld_base->base;
3332 struct ac_export_args args;
3333
3334 args.enabled_channels = 0x0; /* enabled channels */
3335 args.valid_mask = 1; /* whether the EXEC mask is valid */
3336 args.done = 1; /* DONE bit */
3337 args.target = V_008DFC_SQ_EXP_NULL;
3338 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
3339 args.out[0] = base->undef; /* R */
3340 args.out[1] = base->undef; /* G */
3341 args.out[2] = base->undef; /* B */
3342 args.out[3] = base->undef; /* A */
3343
3344 ac_build_export(&ctx->ac, &args);
3345 }
3346
3347 /**
3348 * Return PS outputs in this order:
3349 *
3350 * v[0:3] = color0.xyzw
3351 * v[4:7] = color1.xyzw
3352 * ...
3353 * vN+0 = Depth
3354 * vN+1 = Stencil
3355 * vN+2 = SampleMask
3356 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3357 *
3358 * The alpha-ref SGPR is returned via its original location.
3359 */
3360 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3361 unsigned max_outputs,
3362 LLVMValueRef *addrs)
3363 {
3364 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3365 struct si_shader *shader = ctx->shader;
3366 struct tgsi_shader_info *info = &shader->selector->info;
3367 LLVMBuilderRef builder = ctx->gallivm.builder;
3368 unsigned i, j, first_vgpr, vgpr;
3369
3370 LLVMValueRef color[8][4] = {};
3371 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3372 LLVMValueRef ret;
3373
3374 if (ctx->postponed_kill)
3375 ac_build_kill(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3376
3377 /* Read the output values. */
3378 for (i = 0; i < info->num_outputs; i++) {
3379 unsigned semantic_name = info->output_semantic_name[i];
3380 unsigned semantic_index = info->output_semantic_index[i];
3381
3382 switch (semantic_name) {
3383 case TGSI_SEMANTIC_COLOR:
3384 assert(semantic_index < 8);
3385 for (j = 0; j < 4; j++) {
3386 LLVMValueRef ptr = addrs[4 * i + j];
3387 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3388 color[semantic_index][j] = result;
3389 }
3390 break;
3391 case TGSI_SEMANTIC_POSITION:
3392 depth = LLVMBuildLoad(builder,
3393 addrs[4 * i + 2], "");
3394 break;
3395 case TGSI_SEMANTIC_STENCIL:
3396 stencil = LLVMBuildLoad(builder,
3397 addrs[4 * i + 1], "");
3398 break;
3399 case TGSI_SEMANTIC_SAMPLEMASK:
3400 samplemask = LLVMBuildLoad(builder,
3401 addrs[4 * i + 0], "");
3402 break;
3403 default:
3404 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3405 semantic_name);
3406 }
3407 }
3408
3409 /* Fill the return structure. */
3410 ret = ctx->return_value;
3411
3412 /* Set SGPRs. */
3413 ret = LLVMBuildInsertValue(builder, ret,
3414 LLVMBuildBitCast(ctx->ac.builder,
3415 LLVMGetParam(ctx->main_fn,
3416 SI_PARAM_ALPHA_REF),
3417 ctx->i32, ""),
3418 SI_SGPR_ALPHA_REF, "");
3419
3420 /* Set VGPRs */
3421 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3422 for (i = 0; i < ARRAY_SIZE(color); i++) {
3423 if (!color[i][0])
3424 continue;
3425
3426 for (j = 0; j < 4; j++)
3427 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3428 }
3429 if (depth)
3430 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3431 if (stencil)
3432 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3433 if (samplemask)
3434 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3435
3436 /* Add the input sample mask for smoothing at the end. */
3437 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3438 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3439 ret = LLVMBuildInsertValue(builder, ret,
3440 LLVMGetParam(ctx->main_fn,
3441 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3442
3443 ctx->return_value = ret;
3444 }
3445
3446 /* Prevent optimizations (at least of memory accesses) across the current
3447 * point in the program by emitting empty inline assembly that is marked as
3448 * having side effects.
3449 *
3450 * Optionally, a value can be passed through the inline assembly to prevent
3451 * LLVM from hoisting calls to ReadNone functions.
3452 */
3453 static void emit_optimization_barrier(struct si_shader_context *ctx,
3454 LLVMValueRef *pvgpr)
3455 {
3456 static int counter = 0;
3457
3458 LLVMBuilderRef builder = ctx->gallivm.builder;
3459 char code[16];
3460
3461 snprintf(code, sizeof(code), "; %d", p_atomic_inc_return(&counter));
3462
3463 if (!pvgpr) {
3464 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3465 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, code, "", true, false);
3466 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3467 } else {
3468 LLVMTypeRef ftype = LLVMFunctionType(ctx->i32, &ctx->i32, 1, false);
3469 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, code, "=v,0", true, false);
3470 LLVMValueRef vgpr = *pvgpr;
3471 LLVMTypeRef vgpr_type = LLVMTypeOf(vgpr);
3472 unsigned vgpr_size = llvm_get_type_size(vgpr_type);
3473 LLVMValueRef vgpr0;
3474
3475 assert(vgpr_size % 4 == 0);
3476
3477 vgpr = LLVMBuildBitCast(builder, vgpr, LLVMVectorType(ctx->i32, vgpr_size / 4), "");
3478 vgpr0 = LLVMBuildExtractElement(builder, vgpr, ctx->i32_0, "");
3479 vgpr0 = LLVMBuildCall(builder, inlineasm, &vgpr0, 1, "");
3480 vgpr = LLVMBuildInsertElement(builder, vgpr, vgpr0, ctx->i32_0, "");
3481 vgpr = LLVMBuildBitCast(builder, vgpr, vgpr_type, "");
3482
3483 *pvgpr = vgpr;
3484 }
3485 }
3486
3487 void si_emit_waitcnt(struct si_shader_context *ctx, unsigned simm16)
3488 {
3489 struct gallivm_state *gallivm = &ctx->gallivm;
3490 LLVMBuilderRef builder = gallivm->builder;
3491 LLVMValueRef args[1] = {
3492 LLVMConstInt(ctx->i32, simm16, 0)
3493 };
3494 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3495 ctx->voidt, args, 1, 0);
3496 }
3497
3498 static void membar_emit(
3499 const struct lp_build_tgsi_action *action,
3500 struct lp_build_tgsi_context *bld_base,
3501 struct lp_build_emit_data *emit_data)
3502 {
3503 struct si_shader_context *ctx = si_shader_context(bld_base);
3504 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3505 unsigned flags = LLVMConstIntGetZExtValue(src0);
3506 unsigned waitcnt = NOOP_WAITCNT;
3507
3508 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3509 waitcnt &= VM_CNT & LGKM_CNT;
3510
3511 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3512 TGSI_MEMBAR_SHADER_BUFFER |
3513 TGSI_MEMBAR_SHADER_IMAGE))
3514 waitcnt &= VM_CNT;
3515
3516 if (flags & TGSI_MEMBAR_SHARED)
3517 waitcnt &= LGKM_CNT;
3518
3519 if (waitcnt != NOOP_WAITCNT)
3520 si_emit_waitcnt(ctx, waitcnt);
3521 }
3522
3523 static void clock_emit(
3524 const struct lp_build_tgsi_action *action,
3525 struct lp_build_tgsi_context *bld_base,
3526 struct lp_build_emit_data *emit_data)
3527 {
3528 struct si_shader_context *ctx = si_shader_context(bld_base);
3529 struct gallivm_state *gallivm = &ctx->gallivm;
3530 LLVMValueRef tmp;
3531
3532 tmp = lp_build_intrinsic(gallivm->builder, "llvm.readcyclecounter",
3533 ctx->i64, NULL, 0, 0);
3534 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->v2i32, "");
3535
3536 emit_data->output[0] =
3537 LLVMBuildExtractElement(gallivm->builder, tmp, ctx->i32_0, "");
3538 emit_data->output[1] =
3539 LLVMBuildExtractElement(gallivm->builder, tmp, ctx->i32_1, "");
3540 }
3541
3542 LLVMTypeRef si_const_array(LLVMTypeRef elem_type, int num_elements)
3543 {
3544 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3545 CONST_ADDR_SPACE);
3546 }
3547
3548 static void si_llvm_emit_ddxy(
3549 const struct lp_build_tgsi_action *action,
3550 struct lp_build_tgsi_context *bld_base,
3551 struct lp_build_emit_data *emit_data)
3552 {
3553 struct si_shader_context *ctx = si_shader_context(bld_base);
3554 struct gallivm_state *gallivm = &ctx->gallivm;
3555 unsigned opcode = emit_data->info->opcode;
3556 LLVMValueRef val;
3557 int idx;
3558 unsigned mask;
3559
3560 if (opcode == TGSI_OPCODE_DDX_FINE)
3561 mask = AC_TID_MASK_LEFT;
3562 else if (opcode == TGSI_OPCODE_DDY_FINE)
3563 mask = AC_TID_MASK_TOP;
3564 else
3565 mask = AC_TID_MASK_TOP_LEFT;
3566
3567 /* for DDX we want to next X pixel, DDY next Y pixel. */
3568 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3569
3570 val = LLVMBuildBitCast(gallivm->builder, emit_data->args[0], ctx->i32, "");
3571 val = ac_build_ddxy(&ctx->ac, ctx->screen->has_ds_bpermute,
3572 mask, idx, ctx->lds, val);
3573 emit_data->output[emit_data->chan] = val;
3574 }
3575
3576 /*
3577 * this takes an I,J coordinate pair,
3578 * and works out the X and Y derivatives.
3579 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3580 */
3581 static LLVMValueRef si_llvm_emit_ddxy_interp(
3582 struct lp_build_tgsi_context *bld_base,
3583 LLVMValueRef interp_ij)
3584 {
3585 struct si_shader_context *ctx = si_shader_context(bld_base);
3586 struct gallivm_state *gallivm = &ctx->gallivm;
3587 LLVMValueRef result[4], a;
3588 unsigned i;
3589
3590 for (i = 0; i < 2; i++) {
3591 a = LLVMBuildExtractElement(gallivm->builder, interp_ij,
3592 LLVMConstInt(ctx->i32, i, 0), "");
3593 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
3594 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
3595 }
3596
3597 return lp_build_gather_values(gallivm, result, 4);
3598 }
3599
3600 static void interp_fetch_args(
3601 struct lp_build_tgsi_context *bld_base,
3602 struct lp_build_emit_data *emit_data)
3603 {
3604 struct si_shader_context *ctx = si_shader_context(bld_base);
3605 struct gallivm_state *gallivm = &ctx->gallivm;
3606 const struct tgsi_full_instruction *inst = emit_data->inst;
3607
3608 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3609 /* offset is in second src, first two channels */
3610 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3611 emit_data->inst, 1,
3612 TGSI_CHAN_X);
3613 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3614 emit_data->inst, 1,
3615 TGSI_CHAN_Y);
3616 emit_data->arg_count = 2;
3617 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3618 LLVMValueRef sample_position;
3619 LLVMValueRef sample_id;
3620 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3621
3622 /* fetch sample ID, then fetch its sample position,
3623 * and place into first two channels.
3624 */
3625 sample_id = lp_build_emit_fetch(bld_base,
3626 emit_data->inst, 1, TGSI_CHAN_X);
3627 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
3628 ctx->i32, "");
3629 sample_position = load_sample_position(ctx, sample_id);
3630
3631 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
3632 sample_position,
3633 ctx->i32_0, "");
3634
3635 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
3636 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
3637 sample_position,
3638 ctx->i32_1, "");
3639 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
3640 emit_data->arg_count = 2;
3641 }
3642 }
3643
3644 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3645 struct lp_build_tgsi_context *bld_base,
3646 struct lp_build_emit_data *emit_data)
3647 {
3648 struct si_shader_context *ctx = si_shader_context(bld_base);
3649 struct si_shader *shader = ctx->shader;
3650 struct gallivm_state *gallivm = &ctx->gallivm;
3651 const struct tgsi_shader_info *info = &shader->selector->info;
3652 LLVMValueRef interp_param;
3653 const struct tgsi_full_instruction *inst = emit_data->inst;
3654 const struct tgsi_full_src_register *input = &inst->Src[0];
3655 int input_base, input_array_size;
3656 int chan;
3657 int i;
3658 LLVMValueRef prim_mask = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
3659 LLVMValueRef array_idx;
3660 int interp_param_idx;
3661 unsigned interp;
3662 unsigned location;
3663
3664 assert(input->Register.File == TGSI_FILE_INPUT);
3665
3666 if (input->Register.Indirect) {
3667 unsigned array_id = input->Indirect.ArrayID;
3668
3669 if (array_id) {
3670 input_base = info->input_array_first[array_id];
3671 input_array_size = info->input_array_last[array_id] - input_base + 1;
3672 } else {
3673 input_base = inst->Src[0].Register.Index;
3674 input_array_size = info->num_inputs - input_base;
3675 }
3676
3677 array_idx = get_indirect_index(ctx, &input->Indirect,
3678 input->Register.Index - input_base);
3679 } else {
3680 input_base = inst->Src[0].Register.Index;
3681 input_array_size = 1;
3682 array_idx = ctx->i32_0;
3683 }
3684
3685 interp = shader->selector->info.input_interpolate[input_base];
3686
3687 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3688 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3689 location = TGSI_INTERPOLATE_LOC_CENTER;
3690 else
3691 location = TGSI_INTERPOLATE_LOC_CENTROID;
3692
3693 interp_param_idx = lookup_interp_param_index(interp, location);
3694 if (interp_param_idx == -1)
3695 return;
3696 else if (interp_param_idx)
3697 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
3698 else
3699 interp_param = NULL;
3700
3701 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3702 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3703 LLVMValueRef ij_out[2];
3704 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3705
3706 /*
3707 * take the I then J parameters, and the DDX/Y for it, and
3708 * calculate the IJ inputs for the interpolator.
3709 * temp1 = ddx * offset/sample.x + I;
3710 * interp_param.I = ddy * offset/sample.y + temp1;
3711 * temp1 = ddx * offset/sample.x + J;
3712 * interp_param.J = ddy * offset/sample.y + temp1;
3713 */
3714 for (i = 0; i < 2; i++) {
3715 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
3716 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
3717 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
3718 ddxy_out, ix_ll, "");
3719 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
3720 ddxy_out, iy_ll, "");
3721 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
3722 interp_param, ix_ll, "");
3723 LLVMValueRef temp1, temp2;
3724
3725 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
3726 ctx->f32, "");
3727
3728 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
3729
3730 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
3731
3732 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
3733
3734 ij_out[i] = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
3735 }
3736 interp_param = lp_build_gather_values(gallivm, ij_out, 2);
3737 }
3738
3739 if (interp_param) {
3740 interp_param = LLVMBuildBitCast(gallivm->builder,
3741 interp_param, LLVMVectorType(ctx->f32, 2), "");
3742 }
3743
3744 for (chan = 0; chan < 4; chan++) {
3745 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
3746 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3747
3748 for (unsigned idx = 0; idx < input_array_size; ++idx) {
3749 LLVMValueRef v, i = NULL, j = NULL;
3750
3751 if (interp_param) {
3752 interp_param = LLVMBuildBitCast(gallivm->builder,
3753 interp_param, LLVMVectorType(ctx->f32, 2), "");
3754 i = LLVMBuildExtractElement(
3755 gallivm->builder, interp_param, ctx->i32_0, "");
3756 j = LLVMBuildExtractElement(
3757 gallivm->builder, interp_param, ctx->i32_1, "");
3758 }
3759 v = si_build_fs_interp(ctx, input_base + idx, schan,
3760 prim_mask, i, j);
3761
3762 gather = LLVMBuildInsertElement(gallivm->builder,
3763 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
3764 }
3765
3766 emit_data->output[chan] = LLVMBuildExtractElement(
3767 gallivm->builder, gather, array_idx, "");
3768 }
3769 }
3770
3771 static LLVMValueRef si_emit_ballot(struct si_shader_context *ctx,
3772 LLVMValueRef value)
3773 {
3774 struct gallivm_state *gallivm = &ctx->gallivm;
3775 LLVMValueRef args[3] = {
3776 value,
3777 ctx->i32_0,
3778 LLVMConstInt(ctx->i32, LLVMIntNE, 0)
3779 };
3780
3781 /* We currently have no other way to prevent LLVM from lifting the icmp
3782 * calls to a dominating basic block.
3783 */
3784 emit_optimization_barrier(ctx, &args[0]);
3785
3786 if (LLVMTypeOf(args[0]) != ctx->i32)
3787 args[0] = LLVMBuildBitCast(gallivm->builder, args[0], ctx->i32, "");
3788
3789 return lp_build_intrinsic(gallivm->builder,
3790 "llvm.amdgcn.icmp.i32",
3791 ctx->i64, args, 3,
3792 LP_FUNC_ATTR_NOUNWIND |
3793 LP_FUNC_ATTR_READNONE |
3794 LP_FUNC_ATTR_CONVERGENT);
3795 }
3796
3797 static void vote_all_emit(
3798 const struct lp_build_tgsi_action *action,
3799 struct lp_build_tgsi_context *bld_base,
3800 struct lp_build_emit_data *emit_data)
3801 {
3802 struct si_shader_context *ctx = si_shader_context(bld_base);
3803 struct gallivm_state *gallivm = &ctx->gallivm;
3804 LLVMValueRef active_set, vote_set;
3805 LLVMValueRef tmp;
3806
3807 active_set = si_emit_ballot(ctx, ctx->i32_1);
3808 vote_set = si_emit_ballot(ctx, emit_data->args[0]);
3809
3810 tmp = LLVMBuildICmp(gallivm->builder, LLVMIntEQ, vote_set, active_set, "");
3811 emit_data->output[emit_data->chan] =
3812 LLVMBuildSExt(gallivm->builder, tmp, ctx->i32, "");
3813 }
3814
3815 static void vote_any_emit(
3816 const struct lp_build_tgsi_action *action,
3817 struct lp_build_tgsi_context *bld_base,
3818 struct lp_build_emit_data *emit_data)
3819 {
3820 struct si_shader_context *ctx = si_shader_context(bld_base);
3821 struct gallivm_state *gallivm = &ctx->gallivm;
3822 LLVMValueRef vote_set;
3823 LLVMValueRef tmp;
3824
3825 vote_set = si_emit_ballot(ctx, emit_data->args[0]);
3826
3827 tmp = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
3828 vote_set, LLVMConstInt(ctx->i64, 0, 0), "");
3829 emit_data->output[emit_data->chan] =
3830 LLVMBuildSExt(gallivm->builder, tmp, ctx->i32, "");
3831 }
3832
3833 static void vote_eq_emit(
3834 const struct lp_build_tgsi_action *action,
3835 struct lp_build_tgsi_context *bld_base,
3836 struct lp_build_emit_data *emit_data)
3837 {
3838 struct si_shader_context *ctx = si_shader_context(bld_base);
3839 struct gallivm_state *gallivm = &ctx->gallivm;
3840 LLVMValueRef active_set, vote_set;
3841 LLVMValueRef all, none, tmp;
3842
3843 active_set = si_emit_ballot(ctx, ctx->i32_1);
3844 vote_set = si_emit_ballot(ctx, emit_data->args[0]);
3845
3846 all = LLVMBuildICmp(gallivm->builder, LLVMIntEQ, vote_set, active_set, "");
3847 none = LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
3848 vote_set, LLVMConstInt(ctx->i64, 0, 0), "");
3849 tmp = LLVMBuildOr(gallivm->builder, all, none, "");
3850 emit_data->output[emit_data->chan] =
3851 LLVMBuildSExt(gallivm->builder, tmp, ctx->i32, "");
3852 }
3853
3854 static void ballot_emit(
3855 const struct lp_build_tgsi_action *action,
3856 struct lp_build_tgsi_context *bld_base,
3857 struct lp_build_emit_data *emit_data)
3858 {
3859 struct si_shader_context *ctx = si_shader_context(bld_base);
3860 LLVMBuilderRef builder = ctx->gallivm.builder;
3861 LLVMValueRef tmp;
3862
3863 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
3864 tmp = si_emit_ballot(ctx, tmp);
3865 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
3866
3867 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
3868 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
3869 }
3870
3871 static void read_invoc_fetch_args(
3872 struct lp_build_tgsi_context *bld_base,
3873 struct lp_build_emit_data *emit_data)
3874 {
3875 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
3876 0, emit_data->src_chan);
3877
3878 /* Always read the source invocation (= lane) from the X channel. */
3879 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
3880 1, TGSI_CHAN_X);
3881 emit_data->arg_count = 2;
3882 }
3883
3884 static void read_lane_emit(
3885 const struct lp_build_tgsi_action *action,
3886 struct lp_build_tgsi_context *bld_base,
3887 struct lp_build_emit_data *emit_data)
3888 {
3889 struct si_shader_context *ctx = si_shader_context(bld_base);
3890 LLVMBuilderRef builder = ctx->gallivm.builder;
3891
3892 /* We currently have no other way to prevent LLVM from lifting the icmp
3893 * calls to a dominating basic block.
3894 */
3895 emit_optimization_barrier(ctx, &emit_data->args[0]);
3896
3897 for (unsigned i = 0; i < emit_data->arg_count; ++i) {
3898 emit_data->args[i] = LLVMBuildBitCast(builder, emit_data->args[i],
3899 ctx->i32, "");
3900 }
3901
3902 emit_data->output[emit_data->chan] =
3903 ac_build_intrinsic(&ctx->ac, action->intr_name,
3904 ctx->i32, emit_data->args, emit_data->arg_count,
3905 AC_FUNC_ATTR_READNONE |
3906 AC_FUNC_ATTR_CONVERGENT);
3907 }
3908
3909 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
3910 struct lp_build_emit_data *emit_data)
3911 {
3912 struct si_shader_context *ctx = si_shader_context(bld_base);
3913 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
3914 LLVMValueRef imm;
3915 unsigned stream;
3916
3917 assert(src0.File == TGSI_FILE_IMMEDIATE);
3918
3919 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
3920 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
3921 return stream;
3922 }
3923
3924 /* Emit one vertex from the geometry shader */
3925 static void si_llvm_emit_vertex(
3926 const struct lp_build_tgsi_action *action,
3927 struct lp_build_tgsi_context *bld_base,
3928 struct lp_build_emit_data *emit_data)
3929 {
3930 struct si_shader_context *ctx = si_shader_context(bld_base);
3931 struct lp_build_context *uint = &bld_base->uint_bld;
3932 struct si_shader *shader = ctx->shader;
3933 struct tgsi_shader_info *info = &shader->selector->info;
3934 struct gallivm_state *gallivm = &ctx->gallivm;
3935 struct lp_build_if_state if_state;
3936 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3937 ctx->param_gs2vs_offset);
3938 LLVMValueRef gs_next_vertex;
3939 LLVMValueRef can_emit, kill;
3940 unsigned chan, offset;
3941 int i;
3942 unsigned stream;
3943
3944 stream = si_llvm_get_stream(bld_base, emit_data);
3945
3946 /* Write vertex attribute values to GSVS ring */
3947 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
3948 ctx->gs_next_vertex[stream],
3949 "");
3950
3951 /* If this thread has already emitted the declared maximum number of
3952 * vertices, skip the write: excessive vertex emissions are not
3953 * supposed to have any effect.
3954 *
3955 * If the shader has no writes to memory, kill it instead. This skips
3956 * further memory loads and may allow LLVM to skip to the end
3957 * altogether.
3958 */
3959 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULT, gs_next_vertex,
3960 LLVMConstInt(ctx->i32,
3961 shader->selector->gs_max_out_vertices, 0), "");
3962
3963 bool use_kill = !info->writes_memory;
3964 if (use_kill) {
3965 kill = lp_build_select(&bld_base->base, can_emit,
3966 LLVMConstReal(ctx->f32, 1.0f),
3967 LLVMConstReal(ctx->f32, -1.0f));
3968
3969 ac_build_kill(&ctx->ac, kill);
3970 } else {
3971 lp_build_if(&if_state, gallivm, can_emit);
3972 }
3973
3974 offset = 0;
3975 for (i = 0; i < info->num_outputs; i++) {
3976 LLVMValueRef *out_ptr = ctx->outputs[i];
3977
3978 for (chan = 0; chan < 4; chan++) {
3979 if (!(info->output_usagemask[i] & (1 << chan)) ||
3980 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
3981 continue;
3982
3983 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3984 LLVMValueRef voffset =
3985 LLVMConstInt(ctx->i32, offset *
3986 shader->selector->gs_max_out_vertices, 0);
3987 offset++;
3988
3989 voffset = lp_build_add(uint, voffset, gs_next_vertex);
3990 voffset = lp_build_mul_imm(uint, voffset, 4);
3991
3992 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
3993
3994 ac_build_buffer_store_dword(&ctx->ac,
3995 ctx->gsvs_ring[stream],
3996 out_val, 1,
3997 voffset, soffset, 0,
3998 1, 1, true, true);
3999 }
4000 }
4001
4002 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4003 ctx->i32_1);
4004
4005 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4006
4007 /* Signal vertex emission */
4008 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4009 si_get_gs_wave_id(ctx));
4010 if (!use_kill)
4011 lp_build_endif(&if_state);
4012 }
4013
4014 /* Cut one primitive from the geometry shader */
4015 static void si_llvm_emit_primitive(
4016 const struct lp_build_tgsi_action *action,
4017 struct lp_build_tgsi_context *bld_base,
4018 struct lp_build_emit_data *emit_data)
4019 {
4020 struct si_shader_context *ctx = si_shader_context(bld_base);
4021 unsigned stream;
4022
4023 /* Signal primitive cut */
4024 stream = si_llvm_get_stream(bld_base, emit_data);
4025 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4026 si_get_gs_wave_id(ctx));
4027 }
4028
4029 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4030 struct lp_build_tgsi_context *bld_base,
4031 struct lp_build_emit_data *emit_data)
4032 {
4033 struct si_shader_context *ctx = si_shader_context(bld_base);
4034 struct gallivm_state *gallivm = &ctx->gallivm;
4035
4036 /* SI only (thanks to a hw bug workaround):
4037 * The real barrier instruction isn’t needed, because an entire patch
4038 * always fits into a single wave.
4039 */
4040 if (ctx->screen->b.chip_class == SI &&
4041 ctx->type == PIPE_SHADER_TESS_CTRL) {
4042 si_emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
4043 return;
4044 }
4045
4046 lp_build_intrinsic(gallivm->builder,
4047 "llvm.amdgcn.s.barrier",
4048 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
4049 }
4050
4051 static const struct lp_build_tgsi_action interp_action = {
4052 .fetch_args = interp_fetch_args,
4053 .emit = build_interp_intrinsic,
4054 };
4055
4056 static void si_create_function(struct si_shader_context *ctx,
4057 const char *name,
4058 LLVMTypeRef *returns, unsigned num_returns,
4059 struct si_function_info *fninfo,
4060 unsigned max_workgroup_size)
4061 {
4062 int i;
4063
4064 si_llvm_create_func(ctx, name, returns, num_returns,
4065 fninfo->types, fninfo->num_params);
4066 ctx->return_value = LLVMGetUndef(ctx->return_type);
4067
4068 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4069 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4070
4071 /* The combination of:
4072 * - ByVal
4073 * - dereferenceable
4074 * - invariant.load
4075 * allows the optimization passes to move loads and reduces
4076 * SGPR spilling significantly.
4077 */
4078 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4079 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
4080 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
4081 ac_add_attr_dereferenceable(P, UINT64_MAX);
4082 } else
4083 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
4084 }
4085
4086 for (i = 0; i < fninfo->num_params; ++i) {
4087 if (fninfo->assign[i])
4088 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4089 }
4090
4091 if (max_workgroup_size) {
4092 si_llvm_add_attribute(ctx->main_fn, "amdgpu-max-work-group-size",
4093 max_workgroup_size);
4094 }
4095 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4096 "no-signed-zeros-fp-math",
4097 "true");
4098
4099 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
4100 /* These were copied from some LLVM test. */
4101 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4102 "less-precise-fpmad",
4103 "true");
4104 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4105 "no-infs-fp-math",
4106 "true");
4107 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4108 "no-nans-fp-math",
4109 "true");
4110 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4111 "unsafe-fp-math",
4112 "true");
4113 }
4114 }
4115
4116 static void declare_streamout_params(struct si_shader_context *ctx,
4117 struct pipe_stream_output_info *so,
4118 struct si_function_info *fninfo)
4119 {
4120 int i;
4121
4122 /* Streamout SGPRs. */
4123 if (so->num_outputs) {
4124 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4125 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4126 else
4127 ctx->param_streamout_config = fninfo->num_params - 1;
4128
4129 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4130 }
4131 /* A streamout buffer offset is loaded if the stride is non-zero. */
4132 for (i = 0; i < 4; i++) {
4133 if (!so->stride[i])
4134 continue;
4135
4136 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4137 }
4138 }
4139
4140 static unsigned llvm_get_type_size(LLVMTypeRef type)
4141 {
4142 LLVMTypeKind kind = LLVMGetTypeKind(type);
4143
4144 switch (kind) {
4145 case LLVMIntegerTypeKind:
4146 return LLVMGetIntTypeWidth(type) / 8;
4147 case LLVMFloatTypeKind:
4148 return 4;
4149 case LLVMPointerTypeKind:
4150 return 8;
4151 case LLVMVectorTypeKind:
4152 return LLVMGetVectorSize(type) *
4153 llvm_get_type_size(LLVMGetElementType(type));
4154 case LLVMArrayTypeKind:
4155 return LLVMGetArrayLength(type) *
4156 llvm_get_type_size(LLVMGetElementType(type));
4157 default:
4158 assert(0);
4159 return 0;
4160 }
4161 }
4162
4163 static void declare_lds_as_pointer(struct si_shader_context *ctx)
4164 {
4165 struct gallivm_state *gallivm = &ctx->gallivm;
4166
4167 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
4168 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, ctx->i32_0,
4169 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
4170 "lds");
4171 }
4172
4173 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4174 {
4175 switch (shader->selector->type) {
4176 case PIPE_SHADER_TESS_CTRL:
4177 /* Return this so that LLVM doesn't remove s_barrier
4178 * instructions on chips where we use s_barrier. */
4179 return shader->selector->screen->b.chip_class >= CIK ? 128 : 64;
4180
4181 case PIPE_SHADER_GEOMETRY:
4182 return shader->selector->screen->b.chip_class >= GFX9 ? 128 : 64;
4183
4184 case PIPE_SHADER_COMPUTE:
4185 break; /* see below */
4186
4187 default:
4188 return 0;
4189 }
4190
4191 const unsigned *properties = shader->selector->info.properties;
4192 unsigned max_work_group_size =
4193 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4194 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4195 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4196
4197 if (!max_work_group_size) {
4198 /* This is a variable group size compute shader,
4199 * compile it for the maximum possible group size.
4200 */
4201 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4202 }
4203 return max_work_group_size;
4204 }
4205
4206 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4207 struct si_function_info *fninfo,
4208 bool assign_params)
4209 {
4210 unsigned const_and_shader_buffers =
4211 add_arg(fninfo, ARG_SGPR,
4212 si_const_array(ctx->v4i32,
4213 SI_NUM_SHADER_BUFFERS + SI_NUM_CONST_BUFFERS));
4214 unsigned samplers_and_images =
4215 add_arg(fninfo, ARG_SGPR,
4216 si_const_array(ctx->v8i32,
4217 SI_NUM_IMAGES + SI_NUM_SAMPLERS * 2));
4218
4219 if (assign_params) {
4220 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4221 ctx->param_samplers_and_images = samplers_and_images;
4222 }
4223 }
4224
4225 static void declare_default_desc_pointers(struct si_shader_context *ctx,
4226 struct si_function_info *fninfo)
4227 {
4228 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4229 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS));
4230 declare_per_stage_desc_pointers(ctx, fninfo, true);
4231 }
4232
4233 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4234 struct si_function_info *fninfo)
4235 {
4236 ctx->param_vertex_buffers = add_arg(fninfo, ARG_SGPR,
4237 si_const_array(ctx->v4i32, SI_NUM_VERTEX_BUFFERS));
4238 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4239 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4240 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4241 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4242 }
4243
4244 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4245 struct si_function_info *fninfo,
4246 unsigned *num_prolog_vgprs)
4247 {
4248 struct si_shader *shader = ctx->shader;
4249
4250 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4251 if (shader->key.as_ls) {
4252 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4253 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4254 } else {
4255 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4256 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4257 }
4258 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4259
4260 if (!shader->is_gs_copy_shader) {
4261 /* Vertex load indices. */
4262 ctx->param_vertex_index0 = fninfo->num_params;
4263 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4264 add_arg(fninfo, ARG_VGPR, ctx->i32);
4265 *num_prolog_vgprs += shader->selector->info.num_inputs;
4266 }
4267 }
4268
4269 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4270 struct si_function_info *fninfo)
4271 {
4272 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4273 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4274 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4275 ctx->param_tes_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4276 }
4277
4278 enum {
4279 /* Convenient merged shader definitions. */
4280 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4281 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4282 };
4283
4284 static void create_function(struct si_shader_context *ctx)
4285 {
4286 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
4287 struct gallivm_state *gallivm = &ctx->gallivm;
4288 struct si_shader *shader = ctx->shader;
4289 struct si_function_info fninfo;
4290 LLVMTypeRef returns[16+32*4];
4291 unsigned i, num_return_sgprs;
4292 unsigned num_returns = 0;
4293 unsigned num_prolog_vgprs = 0;
4294 unsigned type = ctx->type;
4295
4296 si_init_function_info(&fninfo);
4297
4298 /* Set MERGED shaders. */
4299 if (ctx->screen->b.chip_class >= GFX9) {
4300 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4301 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4302 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4303 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4304 }
4305
4306 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4307
4308 switch (type) {
4309 case PIPE_SHADER_VERTEX:
4310 declare_default_desc_pointers(ctx, &fninfo);
4311 declare_vs_specific_input_sgprs(ctx, &fninfo);
4312
4313 if (shader->key.as_es) {
4314 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4315 } else if (shader->key.as_ls) {
4316 /* no extra parameters */
4317 } else {
4318 if (shader->is_gs_copy_shader) {
4319 fninfo.num_params = ctx->param_rw_buffers + 1;
4320 fninfo.num_sgpr_params = fninfo.num_params;
4321 }
4322
4323 /* The locations of the other parameters are assigned dynamically. */
4324 declare_streamout_params(ctx, &shader->selector->so,
4325 &fninfo);
4326 }
4327
4328 /* VGPRs */
4329 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4330 break;
4331
4332 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4333 declare_default_desc_pointers(ctx, &fninfo);
4334 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4335 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4336 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4337 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4338 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4339 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4340 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4341 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4342
4343 /* VGPRs */
4344 ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4345 ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4346
4347 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4348 * placed after the user SGPRs.
4349 */
4350 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4351 returns[num_returns++] = ctx->i32; /* SGPRs */
4352 for (i = 0; i < 5; i++)
4353 returns[num_returns++] = ctx->f32; /* VGPRs */
4354 break;
4355
4356 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4357 /* Merged stages have 8 system SGPRs at the beginning. */
4358 ctx->param_rw_buffers = /* SPI_SHADER_USER_DATA_ADDR_LO_HS */
4359 add_arg(&fninfo, ARG_SGPR, si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS));
4360 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4361 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4362 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4363 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4364 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4365 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4366
4367 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4368 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4369 declare_per_stage_desc_pointers(ctx, &fninfo,
4370 ctx->type == PIPE_SHADER_VERTEX);
4371 declare_vs_specific_input_sgprs(ctx, &fninfo);
4372
4373 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4374 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4375 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4376 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4377 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4378 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4379
4380 declare_per_stage_desc_pointers(ctx, &fninfo,
4381 ctx->type == PIPE_SHADER_TESS_CTRL);
4382
4383 /* VGPRs (first TCS, then VS) */
4384 ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4385 ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4386
4387 if (ctx->type == PIPE_SHADER_VERTEX) {
4388 declare_vs_input_vgprs(ctx, &fninfo,
4389 &num_prolog_vgprs);
4390
4391 /* LS return values are inputs to the TCS main shader part. */
4392 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4393 returns[num_returns++] = ctx->i32; /* SGPRs */
4394 for (i = 0; i < 2; i++)
4395 returns[num_returns++] = ctx->f32; /* VGPRs */
4396 } else {
4397 /* TCS return values are inputs to the TCS epilog.
4398 *
4399 * param_tcs_offchip_offset, param_tcs_factor_offset,
4400 * param_tcs_offchip_layout, and param_rw_buffers
4401 * should be passed to the epilog.
4402 */
4403 for (i = 0; i <= 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K; i++)
4404 returns[num_returns++] = ctx->i32; /* SGPRs */
4405 for (i = 0; i < 5; i++)
4406 returns[num_returns++] = ctx->f32; /* VGPRs */
4407 }
4408 break;
4409
4410 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4411 /* Merged stages have 8 system SGPRs at the beginning. */
4412 ctx->param_rw_buffers = /* SPI_SHADER_USER_DATA_ADDR_LO_GS */
4413 add_arg(&fninfo, ARG_SGPR, si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS));
4414 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4415 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4416 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4417 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4418 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4419 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4420
4421 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4422 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4423 declare_per_stage_desc_pointers(ctx, &fninfo,
4424 (ctx->type == PIPE_SHADER_VERTEX ||
4425 ctx->type == PIPE_SHADER_TESS_EVAL));
4426 if (ctx->type == PIPE_SHADER_VERTEX) {
4427 declare_vs_specific_input_sgprs(ctx, &fninfo);
4428 } else {
4429 /* TESS_EVAL (and also GEOMETRY):
4430 * Declare as many input SGPRs as the VS has. */
4431 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4432 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4433 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4434 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4435 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4436 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4437 }
4438
4439 declare_per_stage_desc_pointers(ctx, &fninfo,
4440 ctx->type == PIPE_SHADER_GEOMETRY);
4441
4442 /* VGPRs (first GS, then VS/TES) */
4443 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4444 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4445 ctx->param_gs_prim_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4446 ctx->param_gs_instance_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4447 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4448
4449 if (ctx->type == PIPE_SHADER_VERTEX) {
4450 declare_vs_input_vgprs(ctx, &fninfo,
4451 &num_prolog_vgprs);
4452 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4453 declare_tes_input_vgprs(ctx, &fninfo);
4454 }
4455
4456 if (ctx->type == PIPE_SHADER_VERTEX ||
4457 ctx->type == PIPE_SHADER_TESS_EVAL) {
4458 /* ES return values are inputs to GS. */
4459 for (i = 0; i < 8 + GFX9_GS_NUM_USER_SGPR; i++)
4460 returns[num_returns++] = ctx->i32; /* SGPRs */
4461 for (i = 0; i < 5; i++)
4462 returns[num_returns++] = ctx->f32; /* VGPRs */
4463 }
4464 break;
4465
4466 case PIPE_SHADER_TESS_EVAL:
4467 declare_default_desc_pointers(ctx, &fninfo);
4468 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4469 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4470
4471 if (shader->key.as_es) {
4472 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4473 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4474 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4475 } else {
4476 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4477 declare_streamout_params(ctx, &shader->selector->so,
4478 &fninfo);
4479 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4480 }
4481
4482 /* VGPRs */
4483 declare_tes_input_vgprs(ctx, &fninfo);
4484 break;
4485
4486 case PIPE_SHADER_GEOMETRY:
4487 declare_default_desc_pointers(ctx, &fninfo);
4488 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4489 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4490
4491 /* VGPRs */
4492 ctx->param_gs_vtx0_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4493 ctx->param_gs_vtx1_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4494 ctx->param_gs_prim_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4495 ctx->param_gs_vtx2_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4496 ctx->param_gs_vtx3_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4497 ctx->param_gs_vtx4_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4498 ctx->param_gs_vtx5_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4499 ctx->param_gs_instance_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4500 break;
4501
4502 case PIPE_SHADER_FRAGMENT:
4503 declare_default_desc_pointers(ctx, &fninfo);
4504 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4505 add_arg_checked(&fninfo, ARG_SGPR, ctx->i32, SI_PARAM_PRIM_MASK);
4506
4507 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4508 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4509 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4510 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4511 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4512 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4513 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4514 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4515 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_POS_X_FLOAT);
4516 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_POS_Y_FLOAT);
4517 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_POS_Z_FLOAT);
4518 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_POS_W_FLOAT);
4519 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_FRONT_FACE);
4520 shader->info.face_vgpr_index = 20;
4521 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_ANCILLARY);
4522 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_SAMPLE_COVERAGE);
4523 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4524
4525 /* Color inputs from the prolog. */
4526 if (shader->selector->info.colors_read) {
4527 unsigned num_color_elements =
4528 util_bitcount(shader->selector->info.colors_read);
4529
4530 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4531 for (i = 0; i < num_color_elements; i++)
4532 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4533
4534 num_prolog_vgprs += num_color_elements;
4535 }
4536
4537 /* Outputs for the epilog. */
4538 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4539 num_returns =
4540 num_return_sgprs +
4541 util_bitcount(shader->selector->info.colors_written) * 4 +
4542 shader->selector->info.writes_z +
4543 shader->selector->info.writes_stencil +
4544 shader->selector->info.writes_samplemask +
4545 1 /* SampleMaskIn */;
4546
4547 num_returns = MAX2(num_returns,
4548 num_return_sgprs +
4549 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4550
4551 for (i = 0; i < num_return_sgprs; i++)
4552 returns[i] = ctx->i32;
4553 for (; i < num_returns; i++)
4554 returns[i] = ctx->f32;
4555 break;
4556
4557 case PIPE_SHADER_COMPUTE:
4558 declare_default_desc_pointers(ctx, &fninfo);
4559 if (shader->selector->info.uses_grid_size)
4560 ctx->param_grid_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4561 if (shader->selector->info.uses_block_size)
4562 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4563
4564 for (i = 0; i < 3; i++) {
4565 ctx->param_block_id[i] = -1;
4566 if (shader->selector->info.uses_block_id[i])
4567 ctx->param_block_id[i] = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4568 }
4569
4570 ctx->param_thread_id = add_arg(&fninfo, ARG_VGPR, v3i32);
4571 break;
4572 default:
4573 assert(0 && "unimplemented shader");
4574 return;
4575 }
4576
4577 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4578 si_get_max_workgroup_size(shader));
4579
4580 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4581 if (ctx->type == PIPE_SHADER_FRAGMENT &&
4582 ctx->separate_prolog) {
4583 si_llvm_add_attribute(ctx->main_fn,
4584 "InitialPSInputAddr",
4585 S_0286D0_PERSP_SAMPLE_ENA(1) |
4586 S_0286D0_PERSP_CENTER_ENA(1) |
4587 S_0286D0_PERSP_CENTROID_ENA(1) |
4588 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4589 S_0286D0_LINEAR_CENTER_ENA(1) |
4590 S_0286D0_LINEAR_CENTROID_ENA(1) |
4591 S_0286D0_FRONT_FACE_ENA(1) |
4592 S_0286D0_POS_FIXED_PT_ENA(1));
4593 }
4594
4595 shader->info.num_input_sgprs = 0;
4596 shader->info.num_input_vgprs = 0;
4597
4598 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4599 shader->info.num_input_sgprs += llvm_get_type_size(fninfo.types[i]) / 4;
4600
4601 for (; i < fninfo.num_params; ++i)
4602 shader->info.num_input_vgprs += llvm_get_type_size(fninfo.types[i]) / 4;
4603
4604 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4605 shader->info.num_input_vgprs -= num_prolog_vgprs;
4606
4607 if (!ctx->screen->has_ds_bpermute &&
4608 bld_base->info &&
4609 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
4610 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
4611 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
4612 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
4613 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
4614 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
4615 ctx->lds =
4616 LLVMAddGlobalInAddressSpace(gallivm->module,
4617 LLVMArrayType(ctx->i32, 64),
4618 "ddxy_lds",
4619 LOCAL_ADDR_SPACE);
4620
4621 if (shader->key.as_ls ||
4622 ctx->type == PIPE_SHADER_TESS_CTRL ||
4623 /* GFX9 has the ESGS ring buffer in LDS. */
4624 (ctx->screen->b.chip_class >= GFX9 &&
4625 (shader->key.as_es ||
4626 ctx->type == PIPE_SHADER_GEOMETRY)))
4627 declare_lds_as_pointer(ctx);
4628 }
4629
4630 /**
4631 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4632 * for later use.
4633 */
4634 static void preload_ring_buffers(struct si_shader_context *ctx)
4635 {
4636 struct gallivm_state *gallivm = &ctx->gallivm;
4637 LLVMBuilderRef builder = gallivm->builder;
4638
4639 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
4640 ctx->param_rw_buffers);
4641
4642 if (ctx->screen->b.chip_class <= VI &&
4643 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
4644 unsigned ring =
4645 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
4646 : SI_ES_RING_ESGS;
4647 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
4648
4649 ctx->esgs_ring =
4650 ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
4651 }
4652
4653 if (ctx->shader->is_gs_copy_shader) {
4654 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4655
4656 ctx->gsvs_ring[0] =
4657 ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
4658 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
4659 const struct si_shader_selector *sel = ctx->shader->selector;
4660 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4661 LLVMValueRef base_ring;
4662
4663 base_ring = ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
4664
4665 /* The conceptual layout of the GSVS ring is
4666 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4667 * but the real memory layout is swizzled across
4668 * threads:
4669 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4670 * t16v0c0 ..
4671 * Override the buffer descriptor accordingly.
4672 */
4673 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
4674 uint64_t stream_offset = 0;
4675
4676 for (unsigned stream = 0; stream < 4; ++stream) {
4677 unsigned num_components;
4678 unsigned stride;
4679 unsigned num_records;
4680 LLVMValueRef ring, tmp;
4681
4682 num_components = sel->info.num_stream_output_components[stream];
4683 if (!num_components)
4684 continue;
4685
4686 stride = 4 * num_components * sel->gs_max_out_vertices;
4687
4688 /* Limit on the stride field for <= CIK. */
4689 assert(stride < (1 << 14));
4690
4691 num_records = 64;
4692
4693 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
4694 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
4695 tmp = LLVMBuildAdd(builder, tmp,
4696 LLVMConstInt(ctx->i64,
4697 stream_offset, 0), "");
4698 stream_offset += stride * 64;
4699
4700 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
4701 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
4702 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
4703 tmp = LLVMBuildOr(builder, tmp,
4704 LLVMConstInt(ctx->i32,
4705 S_008F04_STRIDE(stride) |
4706 S_008F04_SWIZZLE_ENABLE(1), 0), "");
4707 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
4708 ring = LLVMBuildInsertElement(builder, ring,
4709 LLVMConstInt(ctx->i32, num_records, 0),
4710 LLVMConstInt(ctx->i32, 2, 0), "");
4711 ring = LLVMBuildInsertElement(builder, ring,
4712 LLVMConstInt(ctx->i32,
4713 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4714 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4715 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4716 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
4717 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4718 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
4719 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
4720 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
4721 S_008F0C_ADD_TID_ENABLE(1),
4722 0),
4723 LLVMConstInt(ctx->i32, 3, 0), "");
4724
4725 ctx->gsvs_ring[stream] = ring;
4726 }
4727 }
4728 }
4729
4730 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
4731 LLVMValueRef param_rw_buffers,
4732 unsigned param_pos_fixed_pt)
4733 {
4734 struct gallivm_state *gallivm = &ctx->gallivm;
4735 LLVMBuilderRef builder = gallivm->builder;
4736 LLVMValueRef slot, desc, offset, row, bit, address[2];
4737
4738 /* Use the fixed-point gl_FragCoord input.
4739 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
4740 * per coordinate to get the repeating effect.
4741 */
4742 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
4743 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
4744
4745 /* Load the buffer descriptor. */
4746 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
4747 desc = ac_build_indexed_load_const(&ctx->ac, param_rw_buffers, slot);
4748
4749 /* The stipple pattern is 32x32, each row has 32 bits. */
4750 offset = LLVMBuildMul(builder, address[1],
4751 LLVMConstInt(ctx->i32, 4, 0), "");
4752 row = buffer_load_const(ctx, desc, offset);
4753 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
4754 bit = LLVMBuildLShr(builder, row, address[0], "");
4755 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
4756
4757 /* The intrinsic kills the thread if arg < 0. */
4758 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
4759 LLVMConstReal(ctx->f32, -1), "");
4760 ac_build_kill(&ctx->ac, bit);
4761 }
4762
4763 void si_shader_binary_read_config(struct ac_shader_binary *binary,
4764 struct si_shader_config *conf,
4765 unsigned symbol_offset)
4766 {
4767 unsigned i;
4768 const unsigned char *config =
4769 ac_shader_binary_config_start(binary, symbol_offset);
4770 bool really_needs_scratch = false;
4771
4772 /* LLVM adds SGPR spills to the scratch size.
4773 * Find out if we really need the scratch buffer.
4774 */
4775 for (i = 0; i < binary->reloc_count; i++) {
4776 const struct ac_shader_reloc *reloc = &binary->relocs[i];
4777
4778 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
4779 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4780 really_needs_scratch = true;
4781 break;
4782 }
4783 }
4784
4785 /* XXX: We may be able to emit some of these values directly rather than
4786 * extracting fields to be emitted later.
4787 */
4788
4789 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
4790 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
4791 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
4792 switch (reg) {
4793 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
4794 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
4795 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
4796 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
4797 case R_00B848_COMPUTE_PGM_RSRC1:
4798 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
4799 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
4800 conf->float_mode = G_00B028_FLOAT_MODE(value);
4801 conf->rsrc1 = value;
4802 break;
4803 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
4804 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
4805 break;
4806 case R_00B84C_COMPUTE_PGM_RSRC2:
4807 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
4808 conf->rsrc2 = value;
4809 break;
4810 case R_0286CC_SPI_PS_INPUT_ENA:
4811 conf->spi_ps_input_ena = value;
4812 break;
4813 case R_0286D0_SPI_PS_INPUT_ADDR:
4814 conf->spi_ps_input_addr = value;
4815 break;
4816 case R_0286E8_SPI_TMPRING_SIZE:
4817 case R_00B860_COMPUTE_TMPRING_SIZE:
4818 /* WAVESIZE is in units of 256 dwords. */
4819 if (really_needs_scratch)
4820 conf->scratch_bytes_per_wave =
4821 G_00B860_WAVESIZE(value) * 256 * 4;
4822 break;
4823 case 0x4: /* SPILLED_SGPRS */
4824 conf->spilled_sgprs = value;
4825 break;
4826 case 0x8: /* SPILLED_VGPRS */
4827 conf->spilled_vgprs = value;
4828 break;
4829 default:
4830 {
4831 static bool printed;
4832
4833 if (!printed) {
4834 fprintf(stderr, "Warning: LLVM emitted unknown "
4835 "config register: 0x%x\n", reg);
4836 printed = true;
4837 }
4838 }
4839 break;
4840 }
4841 }
4842
4843 if (!conf->spi_ps_input_addr)
4844 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
4845 }
4846
4847 void si_shader_apply_scratch_relocs(struct si_shader *shader,
4848 uint64_t scratch_va)
4849 {
4850 unsigned i;
4851 uint32_t scratch_rsrc_dword0 = scratch_va;
4852 uint32_t scratch_rsrc_dword1 =
4853 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
4854
4855 /* Enable scratch coalescing. */
4856 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
4857
4858 for (i = 0 ; i < shader->binary.reloc_count; i++) {
4859 const struct ac_shader_reloc *reloc =
4860 &shader->binary.relocs[i];
4861 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
4862 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4863 &scratch_rsrc_dword0, 4);
4864 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4865 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4866 &scratch_rsrc_dword1, 4);
4867 }
4868 }
4869 }
4870
4871 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
4872 {
4873 unsigned size = shader->binary.code_size;
4874
4875 if (shader->prolog)
4876 size += shader->prolog->binary.code_size;
4877 if (shader->previous_stage)
4878 size += shader->previous_stage->binary.code_size;
4879 if (shader->prolog2)
4880 size += shader->prolog2->binary.code_size;
4881 if (shader->epilog)
4882 size += shader->epilog->binary.code_size;
4883 return size;
4884 }
4885
4886 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
4887 {
4888 const struct ac_shader_binary *prolog =
4889 shader->prolog ? &shader->prolog->binary : NULL;
4890 const struct ac_shader_binary *previous_stage =
4891 shader->previous_stage ? &shader->previous_stage->binary : NULL;
4892 const struct ac_shader_binary *prolog2 =
4893 shader->prolog2 ? &shader->prolog2->binary : NULL;
4894 const struct ac_shader_binary *epilog =
4895 shader->epilog ? &shader->epilog->binary : NULL;
4896 const struct ac_shader_binary *mainb = &shader->binary;
4897 unsigned bo_size = si_get_shader_binary_size(shader) +
4898 (!epilog ? mainb->rodata_size : 0);
4899 unsigned char *ptr;
4900
4901 assert(!prolog || !prolog->rodata_size);
4902 assert(!previous_stage || !previous_stage->rodata_size);
4903 assert(!prolog2 || !prolog2->rodata_size);
4904 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
4905 !mainb->rodata_size);
4906 assert(!epilog || !epilog->rodata_size);
4907
4908 r600_resource_reference(&shader->bo, NULL);
4909 shader->bo = (struct r600_resource*)
4910 pipe_buffer_create(&sscreen->b.b, 0,
4911 PIPE_USAGE_IMMUTABLE,
4912 align(bo_size, SI_CPDMA_ALIGNMENT));
4913 if (!shader->bo)
4914 return -ENOMEM;
4915
4916 /* Upload. */
4917 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
4918 PIPE_TRANSFER_READ_WRITE |
4919 PIPE_TRANSFER_UNSYNCHRONIZED);
4920
4921 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
4922 * endian-independent. */
4923 if (prolog) {
4924 memcpy(ptr, prolog->code, prolog->code_size);
4925 ptr += prolog->code_size;
4926 }
4927 if (previous_stage) {
4928 memcpy(ptr, previous_stage->code, previous_stage->code_size);
4929 ptr += previous_stage->code_size;
4930 }
4931 if (prolog2) {
4932 memcpy(ptr, prolog2->code, prolog2->code_size);
4933 ptr += prolog2->code_size;
4934 }
4935
4936 memcpy(ptr, mainb->code, mainb->code_size);
4937 ptr += mainb->code_size;
4938
4939 if (epilog)
4940 memcpy(ptr, epilog->code, epilog->code_size);
4941 else if (mainb->rodata_size > 0)
4942 memcpy(ptr, mainb->rodata, mainb->rodata_size);
4943
4944 sscreen->b.ws->buffer_unmap(shader->bo->buf);
4945 return 0;
4946 }
4947
4948 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
4949 struct pipe_debug_callback *debug,
4950 const char *name, FILE *file)
4951 {
4952 char *line, *p;
4953 unsigned i, count;
4954
4955 if (binary->disasm_string) {
4956 fprintf(file, "Shader %s disassembly:\n", name);
4957 fprintf(file, "%s", binary->disasm_string);
4958
4959 if (debug && debug->debug_message) {
4960 /* Very long debug messages are cut off, so send the
4961 * disassembly one line at a time. This causes more
4962 * overhead, but on the plus side it simplifies
4963 * parsing of resulting logs.
4964 */
4965 pipe_debug_message(debug, SHADER_INFO,
4966 "Shader Disassembly Begin");
4967
4968 line = binary->disasm_string;
4969 while (*line) {
4970 p = util_strchrnul(line, '\n');
4971 count = p - line;
4972
4973 if (count) {
4974 pipe_debug_message(debug, SHADER_INFO,
4975 "%.*s", count, line);
4976 }
4977
4978 if (!*p)
4979 break;
4980 line = p + 1;
4981 }
4982
4983 pipe_debug_message(debug, SHADER_INFO,
4984 "Shader Disassembly End");
4985 }
4986 } else {
4987 fprintf(file, "Shader %s binary:\n", name);
4988 for (i = 0; i < binary->code_size; i += 4) {
4989 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
4990 binary->code[i + 3], binary->code[i + 2],
4991 binary->code[i + 1], binary->code[i]);
4992 }
4993 }
4994 }
4995
4996 static void si_shader_dump_stats(struct si_screen *sscreen,
4997 const struct si_shader *shader,
4998 struct pipe_debug_callback *debug,
4999 unsigned processor,
5000 FILE *file,
5001 bool check_debug_option)
5002 {
5003 const struct si_shader_config *conf = &shader->config;
5004 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
5005 unsigned code_size = si_get_shader_binary_size(shader);
5006 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
5007 unsigned lds_per_wave = 0;
5008 unsigned max_simd_waves = 10;
5009
5010 /* Compute LDS usage for PS. */
5011 switch (processor) {
5012 case PIPE_SHADER_FRAGMENT:
5013 /* The minimum usage per wave is (num_inputs * 48). The maximum
5014 * usage is (num_inputs * 48 * 16).
5015 * We can get anything in between and it varies between waves.
5016 *
5017 * The 48 bytes per input for a single primitive is equal to
5018 * 4 bytes/component * 4 components/input * 3 points.
5019 *
5020 * Other stages don't know the size at compile time or don't
5021 * allocate LDS per wave, but instead they do it per thread group.
5022 */
5023 lds_per_wave = conf->lds_size * lds_increment +
5024 align(num_inputs * 48, lds_increment);
5025 break;
5026 case PIPE_SHADER_COMPUTE:
5027 if (shader->selector) {
5028 unsigned max_workgroup_size =
5029 si_get_max_workgroup_size(shader);
5030 lds_per_wave = (conf->lds_size * lds_increment) /
5031 DIV_ROUND_UP(max_workgroup_size, 64);
5032 }
5033 break;
5034 }
5035
5036 /* Compute the per-SIMD wave counts. */
5037 if (conf->num_sgprs) {
5038 if (sscreen->b.chip_class >= VI)
5039 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5040 else
5041 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5042 }
5043
5044 if (conf->num_vgprs)
5045 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5046
5047 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5048 * 16KB makes some SIMDs unoccupied). */
5049 if (lds_per_wave)
5050 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5051
5052 if (!check_debug_option ||
5053 r600_can_dump_shader(&sscreen->b, processor)) {
5054 if (processor == PIPE_SHADER_FRAGMENT) {
5055 fprintf(file, "*** SHADER CONFIG ***\n"
5056 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5057 "SPI_PS_INPUT_ENA = 0x%04x\n",
5058 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5059 }
5060
5061 fprintf(file, "*** SHADER STATS ***\n"
5062 "SGPRS: %d\n"
5063 "VGPRS: %d\n"
5064 "Spilled SGPRs: %d\n"
5065 "Spilled VGPRs: %d\n"
5066 "Private memory VGPRs: %d\n"
5067 "Code Size: %d bytes\n"
5068 "LDS: %d blocks\n"
5069 "Scratch: %d bytes per wave\n"
5070 "Max Waves: %d\n"
5071 "********************\n\n\n",
5072 conf->num_sgprs, conf->num_vgprs,
5073 conf->spilled_sgprs, conf->spilled_vgprs,
5074 conf->private_mem_vgprs, code_size,
5075 conf->lds_size, conf->scratch_bytes_per_wave,
5076 max_simd_waves);
5077 }
5078
5079 pipe_debug_message(debug, SHADER_INFO,
5080 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5081 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5082 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5083 conf->num_sgprs, conf->num_vgprs, code_size,
5084 conf->lds_size, conf->scratch_bytes_per_wave,
5085 max_simd_waves, conf->spilled_sgprs,
5086 conf->spilled_vgprs, conf->private_mem_vgprs);
5087 }
5088
5089 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5090 {
5091 switch (processor) {
5092 case PIPE_SHADER_VERTEX:
5093 if (shader->key.as_es)
5094 return "Vertex Shader as ES";
5095 else if (shader->key.as_ls)
5096 return "Vertex Shader as LS";
5097 else
5098 return "Vertex Shader as VS";
5099 case PIPE_SHADER_TESS_CTRL:
5100 return "Tessellation Control Shader";
5101 case PIPE_SHADER_TESS_EVAL:
5102 if (shader->key.as_es)
5103 return "Tessellation Evaluation Shader as ES";
5104 else
5105 return "Tessellation Evaluation Shader as VS";
5106 case PIPE_SHADER_GEOMETRY:
5107 if (shader->is_gs_copy_shader)
5108 return "GS Copy Shader as VS";
5109 else
5110 return "Geometry Shader";
5111 case PIPE_SHADER_FRAGMENT:
5112 return "Pixel Shader";
5113 case PIPE_SHADER_COMPUTE:
5114 return "Compute Shader";
5115 default:
5116 return "Unknown Shader";
5117 }
5118 }
5119
5120 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5121 struct pipe_debug_callback *debug, unsigned processor,
5122 FILE *file, bool check_debug_option)
5123 {
5124 if (!check_debug_option ||
5125 r600_can_dump_shader(&sscreen->b, processor))
5126 si_dump_shader_key(processor, shader, file);
5127
5128 if (!check_debug_option && shader->binary.llvm_ir_string) {
5129 if (shader->previous_stage &&
5130 shader->previous_stage->binary.llvm_ir_string) {
5131 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5132 si_get_shader_name(shader, processor));
5133 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5134 }
5135
5136 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5137 si_get_shader_name(shader, processor));
5138 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5139 }
5140
5141 if (!check_debug_option ||
5142 (r600_can_dump_shader(&sscreen->b, processor) &&
5143 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
5144 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5145
5146 if (shader->prolog)
5147 si_shader_dump_disassembly(&shader->prolog->binary,
5148 debug, "prolog", file);
5149 if (shader->previous_stage)
5150 si_shader_dump_disassembly(&shader->previous_stage->binary,
5151 debug, "previous stage", file);
5152 if (shader->prolog2)
5153 si_shader_dump_disassembly(&shader->prolog2->binary,
5154 debug, "prolog2", file);
5155
5156 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5157
5158 if (shader->epilog)
5159 si_shader_dump_disassembly(&shader->epilog->binary,
5160 debug, "epilog", file);
5161 fprintf(file, "\n");
5162 }
5163
5164 si_shader_dump_stats(sscreen, shader, debug, processor, file,
5165 check_debug_option);
5166 }
5167
5168 static int si_compile_llvm(struct si_screen *sscreen,
5169 struct ac_shader_binary *binary,
5170 struct si_shader_config *conf,
5171 LLVMTargetMachineRef tm,
5172 LLVMModuleRef mod,
5173 struct pipe_debug_callback *debug,
5174 unsigned processor,
5175 const char *name)
5176 {
5177 int r = 0;
5178 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
5179
5180 if (r600_can_dump_shader(&sscreen->b, processor)) {
5181 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5182
5183 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
5184 fprintf(stderr, "%s LLVM IR:\n\n", name);
5185 ac_dump_module(mod);
5186 fprintf(stderr, "\n");
5187 }
5188 }
5189
5190 if (sscreen->record_llvm_ir) {
5191 char *ir = LLVMPrintModuleToString(mod);
5192 binary->llvm_ir_string = strdup(ir);
5193 LLVMDisposeMessage(ir);
5194 }
5195
5196 if (!si_replace_shader(count, binary)) {
5197 r = si_llvm_compile(mod, binary, tm, debug);
5198 if (r)
5199 return r;
5200 }
5201
5202 si_shader_binary_read_config(binary, conf, 0);
5203
5204 /* Enable 64-bit and 16-bit denormals, because there is no performance
5205 * cost.
5206 *
5207 * If denormals are enabled, all floating-point output modifiers are
5208 * ignored.
5209 *
5210 * Don't enable denormals for 32-bit floats, because:
5211 * - Floating-point output modifiers would be ignored by the hw.
5212 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5213 * have to stop using those.
5214 * - SI & CI would be very slow.
5215 */
5216 conf->float_mode |= V_00B028_FP_64_DENORMS;
5217
5218 FREE(binary->config);
5219 FREE(binary->global_symbol_offsets);
5220 binary->config = NULL;
5221 binary->global_symbol_offsets = NULL;
5222
5223 /* Some shaders can't have rodata because their binaries can be
5224 * concatenated.
5225 */
5226 if (binary->rodata_size &&
5227 (processor == PIPE_SHADER_VERTEX ||
5228 processor == PIPE_SHADER_TESS_CTRL ||
5229 processor == PIPE_SHADER_TESS_EVAL ||
5230 processor == PIPE_SHADER_FRAGMENT)) {
5231 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5232 return -EINVAL;
5233 }
5234
5235 return r;
5236 }
5237
5238 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5239 {
5240 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5241 LLVMBuildRetVoid(ctx->gallivm.builder);
5242 else
5243 LLVMBuildRet(ctx->gallivm.builder, ret);
5244 }
5245
5246 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5247 struct si_shader *
5248 si_generate_gs_copy_shader(struct si_screen *sscreen,
5249 LLVMTargetMachineRef tm,
5250 struct si_shader_selector *gs_selector,
5251 struct pipe_debug_callback *debug)
5252 {
5253 struct si_shader_context ctx;
5254 struct si_shader *shader;
5255 struct gallivm_state *gallivm = &ctx.gallivm;
5256 LLVMBuilderRef builder;
5257 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
5258 struct lp_build_context *uint = &bld_base->uint_bld;
5259 struct si_shader_output_values *outputs;
5260 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5261 int i, r;
5262
5263 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5264
5265 if (!outputs)
5266 return NULL;
5267
5268 shader = CALLOC_STRUCT(si_shader);
5269 if (!shader) {
5270 FREE(outputs);
5271 return NULL;
5272 }
5273
5274
5275 shader->selector = gs_selector;
5276 shader->is_gs_copy_shader = true;
5277
5278 si_init_shader_ctx(&ctx, sscreen, tm);
5279 ctx.shader = shader;
5280 ctx.type = PIPE_SHADER_VERTEX;
5281
5282 builder = gallivm->builder;
5283
5284 create_function(&ctx);
5285 preload_ring_buffers(&ctx);
5286
5287 LLVMValueRef voffset =
5288 lp_build_mul_imm(uint, ctx.abi.vertex_id, 4);
5289
5290 /* Fetch the vertex stream ID.*/
5291 LLVMValueRef stream_id;
5292
5293 if (gs_selector->so.num_outputs)
5294 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5295 else
5296 stream_id = ctx.i32_0;
5297
5298 /* Fill in output information. */
5299 for (i = 0; i < gsinfo->num_outputs; ++i) {
5300 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5301 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5302
5303 for (int chan = 0; chan < 4; chan++) {
5304 outputs[i].vertex_stream[chan] =
5305 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5306 }
5307 }
5308
5309 LLVMBasicBlockRef end_bb;
5310 LLVMValueRef switch_inst;
5311
5312 end_bb = LLVMAppendBasicBlockInContext(gallivm->context, ctx.main_fn, "end");
5313 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5314
5315 for (int stream = 0; stream < 4; stream++) {
5316 LLVMBasicBlockRef bb;
5317 unsigned offset;
5318
5319 if (!gsinfo->num_stream_output_components[stream])
5320 continue;
5321
5322 if (stream > 0 && !gs_selector->so.num_outputs)
5323 continue;
5324
5325 bb = LLVMInsertBasicBlockInContext(gallivm->context, end_bb, "out");
5326 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5327 LLVMPositionBuilderAtEnd(builder, bb);
5328
5329 /* Fetch vertex data from GSVS ring */
5330 offset = 0;
5331 for (i = 0; i < gsinfo->num_outputs; ++i) {
5332 for (unsigned chan = 0; chan < 4; chan++) {
5333 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5334 outputs[i].vertex_stream[chan] != stream) {
5335 outputs[i].values[chan] = ctx.bld_base.base.undef;
5336 continue;
5337 }
5338
5339 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5340 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5341 offset++;
5342
5343 outputs[i].values[chan] =
5344 ac_build_buffer_load(&ctx.ac,
5345 ctx.gsvs_ring[0], 1,
5346 ctx.i32_0, voffset,
5347 soffset, 0, 1, 1,
5348 true, false);
5349 }
5350 }
5351
5352 /* Streamout and exports. */
5353 if (gs_selector->so.num_outputs) {
5354 si_llvm_emit_streamout(&ctx, outputs,
5355 gsinfo->num_outputs,
5356 stream);
5357 }
5358
5359 if (stream == 0)
5360 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
5361
5362 LLVMBuildBr(builder, end_bb);
5363 }
5364
5365 LLVMPositionBuilderAtEnd(builder, end_bb);
5366
5367 LLVMBuildRetVoid(gallivm->builder);
5368
5369 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5370 si_llvm_optimize_module(&ctx);
5371
5372 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5373 &ctx.shader->config, ctx.tm,
5374 ctx.gallivm.module,
5375 debug, PIPE_SHADER_GEOMETRY,
5376 "GS Copy Shader");
5377 if (!r) {
5378 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
5379 fprintf(stderr, "GS Copy Shader:\n");
5380 si_shader_dump(sscreen, ctx.shader, debug,
5381 PIPE_SHADER_GEOMETRY, stderr, true);
5382 r = si_shader_binary_upload(sscreen, ctx.shader);
5383 }
5384
5385 si_llvm_dispose(&ctx);
5386
5387 FREE(outputs);
5388
5389 if (r != 0) {
5390 FREE(shader);
5391 shader = NULL;
5392 }
5393 return shader;
5394 }
5395
5396 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5397 const struct si_vs_prolog_bits *prolog,
5398 const char *prefix, FILE *f)
5399 {
5400 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5401 prefix, prolog->instance_divisor_is_one);
5402 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5403 prefix, prolog->instance_divisor_is_fetched);
5404
5405 fprintf(f, " mono.vs.fix_fetch = {");
5406 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5407 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5408 fprintf(f, "}\n");
5409 }
5410
5411 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5412 FILE *f)
5413 {
5414 const struct si_shader_key *key = &shader->key;
5415
5416 fprintf(f, "SHADER KEY\n");
5417
5418 switch (processor) {
5419 case PIPE_SHADER_VERTEX:
5420 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5421 "part.vs.prolog", f);
5422 fprintf(f, " as_es = %u\n", key->as_es);
5423 fprintf(f, " as_ls = %u\n", key->as_ls);
5424 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5425 key->mono.u.vs_export_prim_id);
5426 break;
5427
5428 case PIPE_SHADER_TESS_CTRL:
5429 if (shader->selector->screen->b.chip_class >= GFX9) {
5430 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5431 "part.tcs.ls_prolog", f);
5432 }
5433 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5434 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5435 break;
5436
5437 case PIPE_SHADER_TESS_EVAL:
5438 fprintf(f, " as_es = %u\n", key->as_es);
5439 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5440 key->mono.u.vs_export_prim_id);
5441 break;
5442
5443 case PIPE_SHADER_GEOMETRY:
5444 if (shader->is_gs_copy_shader)
5445 break;
5446
5447 if (shader->selector->screen->b.chip_class >= GFX9 &&
5448 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5449 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5450 "part.gs.vs_prolog", f);
5451 }
5452 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5453 break;
5454
5455 case PIPE_SHADER_COMPUTE:
5456 break;
5457
5458 case PIPE_SHADER_FRAGMENT:
5459 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5460 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5461 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5462 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5463 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5464 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5465 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5466 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5467 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5468 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5469 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5470 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5471 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5472 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5473 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5474 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5475 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5476 break;
5477
5478 default:
5479 assert(0);
5480 }
5481
5482 if ((processor == PIPE_SHADER_GEOMETRY ||
5483 processor == PIPE_SHADER_TESS_EVAL ||
5484 processor == PIPE_SHADER_VERTEX) &&
5485 !key->as_es && !key->as_ls) {
5486 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5487 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5488 }
5489 }
5490
5491 static void si_init_shader_ctx(struct si_shader_context *ctx,
5492 struct si_screen *sscreen,
5493 LLVMTargetMachineRef tm)
5494 {
5495 struct lp_build_tgsi_context *bld_base;
5496
5497 si_llvm_context_init(ctx, sscreen, tm);
5498
5499 bld_base = &ctx->bld_base;
5500 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5501
5502 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5503 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5504 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5505
5506 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5507
5508 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5509
5510 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5511 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5512 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5513 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5514
5515 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5516 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5517 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5518 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5519 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5520 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5521 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5522 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
5523 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5524
5525 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
5526 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
5527 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5528 }
5529
5530 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5531 {
5532 struct si_shader *shader = ctx->shader;
5533 struct tgsi_shader_info *info = &shader->selector->info;
5534
5535 if ((ctx->type != PIPE_SHADER_VERTEX &&
5536 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5537 shader->key.as_ls ||
5538 shader->key.as_es)
5539 return;
5540
5541 ac_optimize_vs_outputs(&ctx->ac,
5542 ctx->main_fn,
5543 shader->info.vs_output_param_offset,
5544 info->num_outputs,
5545 &shader->info.nr_param_exports);
5546 }
5547
5548 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
5549 {
5550 ctx->shader->config.private_mem_vgprs = 0;
5551
5552 /* Process all LLVM instructions. */
5553 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
5554 while (bb) {
5555 LLVMValueRef next = LLVMGetFirstInstruction(bb);
5556
5557 while (next) {
5558 LLVMValueRef inst = next;
5559 next = LLVMGetNextInstruction(next);
5560
5561 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
5562 continue;
5563
5564 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
5565 /* No idea why LLVM aligns allocas to 4 elements. */
5566 unsigned alignment = LLVMGetAlignment(inst);
5567 unsigned dw_size = align(llvm_get_type_size(type) / 4, alignment);
5568 ctx->shader->config.private_mem_vgprs += dw_size;
5569 }
5570 bb = LLVMGetNextBasicBlock(bb);
5571 }
5572 }
5573
5574 static void si_init_exec_full_mask(struct si_shader_context *ctx)
5575 {
5576 LLVMValueRef full_mask = LLVMConstInt(ctx->i64, ~0ull, 0);
5577 lp_build_intrinsic(ctx->gallivm.builder,
5578 "llvm.amdgcn.init.exec", ctx->voidt,
5579 &full_mask, 1, LP_FUNC_ATTR_CONVERGENT);
5580 }
5581
5582 static void si_init_exec_from_input(struct si_shader_context *ctx,
5583 unsigned param, unsigned bitoffset)
5584 {
5585 LLVMValueRef args[] = {
5586 LLVMGetParam(ctx->main_fn, param),
5587 LLVMConstInt(ctx->i32, bitoffset, 0),
5588 };
5589 lp_build_intrinsic(ctx->gallivm.builder,
5590 "llvm.amdgcn.init.exec.from.input",
5591 ctx->voidt, args, 2, LP_FUNC_ATTR_CONVERGENT);
5592 }
5593
5594 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
5595 bool is_monolithic)
5596 {
5597 struct si_shader *shader = ctx->shader;
5598 struct si_shader_selector *sel = shader->selector;
5599 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5600
5601 // TODO clean all this up!
5602 switch (ctx->type) {
5603 case PIPE_SHADER_VERTEX:
5604 ctx->load_input = declare_input_vs;
5605 if (shader->key.as_ls)
5606 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
5607 else if (shader->key.as_es)
5608 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
5609 else {
5610 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5611 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5612 }
5613 break;
5614 case PIPE_SHADER_TESS_CTRL:
5615 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5616 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5617 bld_base->emit_store = store_output_tcs;
5618 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
5619 break;
5620 case PIPE_SHADER_TESS_EVAL:
5621 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
5622 if (shader->key.as_es)
5623 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
5624 else {
5625 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5626 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5627 }
5628 break;
5629 case PIPE_SHADER_GEOMETRY:
5630 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
5631 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
5632 break;
5633 case PIPE_SHADER_FRAGMENT:
5634 ctx->load_input = declare_input_fs;
5635 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
5636 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5637 break;
5638 case PIPE_SHADER_COMPUTE:
5639 ctx->declare_memory_region = declare_compute_memory;
5640 break;
5641 default:
5642 assert(!"Unsupported shader type");
5643 return false;
5644 }
5645
5646 ctx->abi.load_ubo = load_ubo;
5647
5648 create_function(ctx);
5649 preload_ring_buffers(ctx);
5650
5651 /* For GFX9 merged shaders:
5652 * - Set EXEC for the first shader. If the prolog is present, set
5653 * EXEC there instead.
5654 * - Add a barrier before the second shader.
5655 * - In the second shader, reset EXEC to ~0 and wrap the main part in
5656 * an if-statement. This is required for correctness in geometry
5657 * shaders, to ensure that empty GS waves do not send GS_EMIT and
5658 * GS_CUT messages.
5659 *
5660 * For monolithic merged shaders, the first shader is wrapped in an
5661 * if-block together with its prolog in si_build_wrapper_function.
5662 */
5663 if (ctx->screen->b.chip_class >= GFX9) {
5664 if (!is_monolithic &&
5665 sel->info.num_instructions > 1 && /* not empty shader */
5666 (shader->key.as_es || shader->key.as_ls) &&
5667 (ctx->type == PIPE_SHADER_TESS_EVAL ||
5668 (ctx->type == PIPE_SHADER_VERTEX &&
5669 !sel->vs_needs_prolog))) {
5670 si_init_exec_from_input(ctx,
5671 ctx->param_merged_wave_info, 0);
5672 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
5673 ctx->type == PIPE_SHADER_GEOMETRY) {
5674 if (!is_monolithic)
5675 si_init_exec_full_mask(ctx);
5676
5677 /* The barrier must execute for all shaders in a
5678 * threadgroup.
5679 */
5680 si_llvm_emit_barrier(NULL, bld_base, NULL);
5681
5682 LLVMValueRef num_threads = unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
5683 LLVMValueRef ena =
5684 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
5685 ac_get_thread_id(&ctx->ac), num_threads, "");
5686 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
5687 }
5688 }
5689
5690 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5691 int i;
5692 for (i = 0; i < 4; i++) {
5693 ctx->gs_next_vertex[i] =
5694 lp_build_alloca(&ctx->gallivm,
5695 ctx->i32, "");
5696 }
5697 }
5698
5699 if (ctx->type == PIPE_SHADER_FRAGMENT && sel->info.uses_kill &&
5700 ctx->screen->b.debug_flags & DBG_FS_CORRECT_DERIVS_AFTER_KILL) {
5701 /* This is initialized to 0.0 = not kill. */
5702 ctx->postponed_kill = lp_build_alloca(&ctx->gallivm, ctx->f32, "");
5703 }
5704
5705 if (sel->tokens) {
5706 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
5707 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
5708 return false;
5709 }
5710 } else {
5711 if (!si_nir_build_llvm(ctx, sel->nir)) {
5712 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
5713 return false;
5714 }
5715 }
5716
5717 si_llvm_build_ret(ctx, ctx->return_value);
5718 return true;
5719 }
5720
5721 /**
5722 * Compute the VS prolog key, which contains all the information needed to
5723 * build the VS prolog function, and set shader->info bits where needed.
5724 *
5725 * \param info Shader info of the vertex shader.
5726 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
5727 * \param prolog_key Key of the VS prolog
5728 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
5729 * \param key Output shader part key.
5730 */
5731 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
5732 unsigned num_input_sgprs,
5733 const struct si_vs_prolog_bits *prolog_key,
5734 struct si_shader *shader_out,
5735 union si_shader_part_key *key)
5736 {
5737 memset(key, 0, sizeof(*key));
5738 key->vs_prolog.states = *prolog_key;
5739 key->vs_prolog.num_input_sgprs = num_input_sgprs;
5740 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
5741 key->vs_prolog.as_ls = shader_out->key.as_ls;
5742
5743 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
5744 key->vs_prolog.as_ls = 1;
5745 key->vs_prolog.num_merged_next_stage_vgprs = 2;
5746 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
5747 key->vs_prolog.num_merged_next_stage_vgprs = 5;
5748 }
5749
5750 /* Enable loading the InstanceID VGPR. */
5751 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
5752
5753 if ((key->vs_prolog.states.instance_divisor_is_one |
5754 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
5755 shader_out->info.uses_instanceid = true;
5756 }
5757
5758 /**
5759 * Compute the PS prolog key, which contains all the information needed to
5760 * build the PS prolog function, and set related bits in shader->config.
5761 */
5762 static void si_get_ps_prolog_key(struct si_shader *shader,
5763 union si_shader_part_key *key,
5764 bool separate_prolog)
5765 {
5766 struct tgsi_shader_info *info = &shader->selector->info;
5767
5768 memset(key, 0, sizeof(*key));
5769 key->ps_prolog.states = shader->key.part.ps.prolog;
5770 key->ps_prolog.colors_read = info->colors_read;
5771 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
5772 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
5773 key->ps_prolog.wqm = info->uses_derivatives &&
5774 (key->ps_prolog.colors_read ||
5775 key->ps_prolog.states.force_persp_sample_interp ||
5776 key->ps_prolog.states.force_linear_sample_interp ||
5777 key->ps_prolog.states.force_persp_center_interp ||
5778 key->ps_prolog.states.force_linear_center_interp ||
5779 key->ps_prolog.states.bc_optimize_for_persp ||
5780 key->ps_prolog.states.bc_optimize_for_linear);
5781
5782 if (info->colors_read) {
5783 unsigned *color = shader->selector->color_attr_index;
5784
5785 if (shader->key.part.ps.prolog.color_two_side) {
5786 /* BCOLORs are stored after the last input. */
5787 key->ps_prolog.num_interp_inputs = info->num_inputs;
5788 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
5789 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
5790 }
5791
5792 for (unsigned i = 0; i < 2; i++) {
5793 unsigned interp = info->input_interpolate[color[i]];
5794 unsigned location = info->input_interpolate_loc[color[i]];
5795
5796 if (!(info->colors_read & (0xf << i*4)))
5797 continue;
5798
5799 key->ps_prolog.color_attr_index[i] = color[i];
5800
5801 if (shader->key.part.ps.prolog.flatshade_colors &&
5802 interp == TGSI_INTERPOLATE_COLOR)
5803 interp = TGSI_INTERPOLATE_CONSTANT;
5804
5805 switch (interp) {
5806 case TGSI_INTERPOLATE_CONSTANT:
5807 key->ps_prolog.color_interp_vgpr_index[i] = -1;
5808 break;
5809 case TGSI_INTERPOLATE_PERSPECTIVE:
5810 case TGSI_INTERPOLATE_COLOR:
5811 /* Force the interpolation location for colors here. */
5812 if (shader->key.part.ps.prolog.force_persp_sample_interp)
5813 location = TGSI_INTERPOLATE_LOC_SAMPLE;
5814 if (shader->key.part.ps.prolog.force_persp_center_interp)
5815 location = TGSI_INTERPOLATE_LOC_CENTER;
5816
5817 switch (location) {
5818 case TGSI_INTERPOLATE_LOC_SAMPLE:
5819 key->ps_prolog.color_interp_vgpr_index[i] = 0;
5820 shader->config.spi_ps_input_ena |=
5821 S_0286CC_PERSP_SAMPLE_ENA(1);
5822 break;
5823 case TGSI_INTERPOLATE_LOC_CENTER:
5824 key->ps_prolog.color_interp_vgpr_index[i] = 2;
5825 shader->config.spi_ps_input_ena |=
5826 S_0286CC_PERSP_CENTER_ENA(1);
5827 break;
5828 case TGSI_INTERPOLATE_LOC_CENTROID:
5829 key->ps_prolog.color_interp_vgpr_index[i] = 4;
5830 shader->config.spi_ps_input_ena |=
5831 S_0286CC_PERSP_CENTROID_ENA(1);
5832 break;
5833 default:
5834 assert(0);
5835 }
5836 break;
5837 case TGSI_INTERPOLATE_LINEAR:
5838 /* Force the interpolation location for colors here. */
5839 if (shader->key.part.ps.prolog.force_linear_sample_interp)
5840 location = TGSI_INTERPOLATE_LOC_SAMPLE;
5841 if (shader->key.part.ps.prolog.force_linear_center_interp)
5842 location = TGSI_INTERPOLATE_LOC_CENTER;
5843
5844 /* The VGPR assignment for non-monolithic shaders
5845 * works because InitialPSInputAddr is set on the
5846 * main shader and PERSP_PULL_MODEL is never used.
5847 */
5848 switch (location) {
5849 case TGSI_INTERPOLATE_LOC_SAMPLE:
5850 key->ps_prolog.color_interp_vgpr_index[i] =
5851 separate_prolog ? 6 : 9;
5852 shader->config.spi_ps_input_ena |=
5853 S_0286CC_LINEAR_SAMPLE_ENA(1);
5854 break;
5855 case TGSI_INTERPOLATE_LOC_CENTER:
5856 key->ps_prolog.color_interp_vgpr_index[i] =
5857 separate_prolog ? 8 : 11;
5858 shader->config.spi_ps_input_ena |=
5859 S_0286CC_LINEAR_CENTER_ENA(1);
5860 break;
5861 case TGSI_INTERPOLATE_LOC_CENTROID:
5862 key->ps_prolog.color_interp_vgpr_index[i] =
5863 separate_prolog ? 10 : 13;
5864 shader->config.spi_ps_input_ena |=
5865 S_0286CC_LINEAR_CENTROID_ENA(1);
5866 break;
5867 default:
5868 assert(0);
5869 }
5870 break;
5871 default:
5872 assert(0);
5873 }
5874 }
5875 }
5876 }
5877
5878 /**
5879 * Check whether a PS prolog is required based on the key.
5880 */
5881 static bool si_need_ps_prolog(const union si_shader_part_key *key)
5882 {
5883 return key->ps_prolog.colors_read ||
5884 key->ps_prolog.states.force_persp_sample_interp ||
5885 key->ps_prolog.states.force_linear_sample_interp ||
5886 key->ps_prolog.states.force_persp_center_interp ||
5887 key->ps_prolog.states.force_linear_center_interp ||
5888 key->ps_prolog.states.bc_optimize_for_persp ||
5889 key->ps_prolog.states.bc_optimize_for_linear ||
5890 key->ps_prolog.states.poly_stipple;
5891 }
5892
5893 /**
5894 * Compute the PS epilog key, which contains all the information needed to
5895 * build the PS epilog function.
5896 */
5897 static void si_get_ps_epilog_key(struct si_shader *shader,
5898 union si_shader_part_key *key)
5899 {
5900 struct tgsi_shader_info *info = &shader->selector->info;
5901 memset(key, 0, sizeof(*key));
5902 key->ps_epilog.colors_written = info->colors_written;
5903 key->ps_epilog.writes_z = info->writes_z;
5904 key->ps_epilog.writes_stencil = info->writes_stencil;
5905 key->ps_epilog.writes_samplemask = info->writes_samplemask;
5906 key->ps_epilog.states = shader->key.part.ps.epilog;
5907 }
5908
5909 /**
5910 * Build the GS prolog function. Rotate the input vertices for triangle strips
5911 * with adjacency.
5912 */
5913 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
5914 union si_shader_part_key *key)
5915 {
5916 unsigned num_sgprs, num_vgprs;
5917 struct gallivm_state *gallivm = &ctx->gallivm;
5918 struct si_function_info fninfo;
5919 LLVMBuilderRef builder = gallivm->builder;
5920 LLVMTypeRef returns[48];
5921 LLVMValueRef func, ret;
5922
5923 si_init_function_info(&fninfo);
5924
5925 if (ctx->screen->b.chip_class >= GFX9) {
5926 num_sgprs = 8 + GFX9_GS_NUM_USER_SGPR;
5927 num_vgprs = 5; /* ES inputs are not needed by GS */
5928 } else {
5929 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
5930 num_vgprs = 8;
5931 }
5932
5933 for (unsigned i = 0; i < num_sgprs; ++i) {
5934 add_arg(&fninfo, ARG_SGPR, ctx->i32);
5935 returns[i] = ctx->i32;
5936 }
5937
5938 for (unsigned i = 0; i < num_vgprs; ++i) {
5939 add_arg(&fninfo, ARG_VGPR, ctx->i32);
5940 returns[num_sgprs + i] = ctx->f32;
5941 }
5942
5943 /* Create the function. */
5944 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
5945 &fninfo, 0);
5946 func = ctx->main_fn;
5947
5948 /* Set the full EXEC mask for the prolog, because we are only fiddling
5949 * with registers here. The main shader part will set the correct EXEC
5950 * mask.
5951 */
5952 if (ctx->screen->b.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
5953 si_init_exec_full_mask(ctx);
5954
5955 /* Copy inputs to outputs. This should be no-op, as the registers match,
5956 * but it will prevent the compiler from overwriting them unintentionally.
5957 */
5958 ret = ctx->return_value;
5959 for (unsigned i = 0; i < num_sgprs; i++) {
5960 LLVMValueRef p = LLVMGetParam(func, i);
5961 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
5962 }
5963 for (unsigned i = 0; i < num_vgprs; i++) {
5964 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
5965 p = LLVMBuildBitCast(builder, p, ctx->f32, "");
5966 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
5967 }
5968
5969 if (key->gs_prolog.states.tri_strip_adj_fix) {
5970 /* Remap the input vertices for every other primitive. */
5971 const unsigned gfx6_vtx_params[6] = {
5972 num_sgprs,
5973 num_sgprs + 1,
5974 num_sgprs + 3,
5975 num_sgprs + 4,
5976 num_sgprs + 5,
5977 num_sgprs + 6
5978 };
5979 const unsigned gfx9_vtx_params[3] = {
5980 num_sgprs,
5981 num_sgprs + 1,
5982 num_sgprs + 4,
5983 };
5984 LLVMValueRef vtx_in[6], vtx_out[6];
5985 LLVMValueRef prim_id, rotate;
5986
5987 if (ctx->screen->b.chip_class >= GFX9) {
5988 for (unsigned i = 0; i < 3; i++) {
5989 vtx_in[i*2] = unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
5990 vtx_in[i*2+1] = unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
5991 }
5992 } else {
5993 for (unsigned i = 0; i < 6; i++)
5994 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
5995 }
5996
5997 prim_id = LLVMGetParam(func, num_sgprs + 2);
5998 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
5999
6000 for (unsigned i = 0; i < 6; ++i) {
6001 LLVMValueRef base, rotated;
6002 base = vtx_in[i];
6003 rotated = vtx_in[(i + 4) % 6];
6004 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6005 }
6006
6007 if (ctx->screen->b.chip_class >= GFX9) {
6008 for (unsigned i = 0; i < 3; i++) {
6009 LLVMValueRef hi, out;
6010
6011 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6012 LLVMConstInt(ctx->i32, 16, 0), "");
6013 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6014 out = LLVMBuildBitCast(builder, out, ctx->f32, "");
6015 ret = LLVMBuildInsertValue(builder, ret, out,
6016 gfx9_vtx_params[i], "");
6017 }
6018 } else {
6019 for (unsigned i = 0; i < 6; i++) {
6020 LLVMValueRef out;
6021
6022 out = LLVMBuildBitCast(builder, vtx_out[i], ctx->f32, "");
6023 ret = LLVMBuildInsertValue(builder, ret, out,
6024 gfx6_vtx_params[i], "");
6025 }
6026 }
6027 }
6028
6029 LLVMBuildRet(builder, ret);
6030 }
6031
6032 /**
6033 * Given a list of shader part functions, build a wrapper function that
6034 * runs them in sequence to form a monolithic shader.
6035 */
6036 static void si_build_wrapper_function(struct si_shader_context *ctx,
6037 LLVMValueRef *parts,
6038 unsigned num_parts,
6039 unsigned main_part,
6040 unsigned next_shader_first_part)
6041 {
6042 struct gallivm_state *gallivm = &ctx->gallivm;
6043 LLVMBuilderRef builder = ctx->gallivm.builder;
6044 /* PS epilog has one arg per color component; gfx9 merged shader
6045 * prologs need to forward 32 user SGPRs.
6046 */
6047 struct si_function_info fninfo;
6048 LLVMValueRef initial[64], out[64];
6049 LLVMTypeRef function_type;
6050 unsigned num_first_params;
6051 unsigned num_out, initial_num_out;
6052 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6053 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6054 unsigned num_sgprs, num_vgprs;
6055 unsigned gprs;
6056 struct lp_build_if_state if_state;
6057
6058 si_init_function_info(&fninfo);
6059
6060 for (unsigned i = 0; i < num_parts; ++i) {
6061 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6062 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6063 }
6064
6065 /* The parameters of the wrapper function correspond to those of the
6066 * first part in terms of SGPRs and VGPRs, but we use the types of the
6067 * main part to get the right types. This is relevant for the
6068 * dereferenceable attribute on descriptor table pointers.
6069 */
6070 num_sgprs = 0;
6071 num_vgprs = 0;
6072
6073 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6074 num_first_params = LLVMCountParamTypes(function_type);
6075
6076 for (unsigned i = 0; i < num_first_params; ++i) {
6077 LLVMValueRef param = LLVMGetParam(parts[0], i);
6078
6079 if (ac_is_sgpr_param(param)) {
6080 assert(num_vgprs == 0);
6081 num_sgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
6082 } else {
6083 num_vgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
6084 }
6085 }
6086
6087 gprs = 0;
6088 while (gprs < num_sgprs + num_vgprs) {
6089 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6090 LLVMTypeRef type = LLVMTypeOf(param);
6091 unsigned size = llvm_get_type_size(type) / 4;
6092
6093 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6094
6095 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6096 assert(gprs + size <= num_sgprs + num_vgprs &&
6097 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6098
6099 gprs += size;
6100 }
6101
6102 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6103 si_get_max_workgroup_size(ctx->shader));
6104
6105 if (is_merged_shader(ctx->shader))
6106 si_init_exec_full_mask(ctx);
6107
6108 /* Record the arguments of the function as if they were an output of
6109 * a previous part.
6110 */
6111 num_out = 0;
6112 num_out_sgpr = 0;
6113
6114 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6115 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6116 LLVMTypeRef param_type = LLVMTypeOf(param);
6117 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6118 unsigned size = llvm_get_type_size(param_type) / 4;
6119
6120 if (size == 1) {
6121 if (param_type != out_type)
6122 param = LLVMBuildBitCast(builder, param, out_type, "");
6123 out[num_out++] = param;
6124 } else {
6125 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6126
6127 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6128 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6129 param_type = ctx->i64;
6130 }
6131
6132 if (param_type != vector_type)
6133 param = LLVMBuildBitCast(builder, param, vector_type, "");
6134
6135 for (unsigned j = 0; j < size; ++j)
6136 out[num_out++] = LLVMBuildExtractElement(
6137 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6138 }
6139
6140 if (i < fninfo.num_sgpr_params)
6141 num_out_sgpr = num_out;
6142 }
6143
6144 memcpy(initial, out, sizeof(out));
6145 initial_num_out = num_out;
6146 initial_num_out_sgpr = num_out_sgpr;
6147
6148 /* Now chain the parts. */
6149 for (unsigned part = 0; part < num_parts; ++part) {
6150 LLVMValueRef in[48];
6151 LLVMValueRef ret;
6152 LLVMTypeRef ret_type;
6153 unsigned out_idx = 0;
6154 unsigned num_params = LLVMCountParams(parts[part]);
6155
6156 /* Merged shaders are executed conditionally depending
6157 * on the number of enabled threads passed in the input SGPRs. */
6158 if (is_merged_shader(ctx->shader) && part == 0) {
6159 LLVMValueRef ena, count = initial[3];
6160
6161 count = LLVMBuildAnd(builder, count,
6162 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6163 ena = LLVMBuildICmp(builder, LLVMIntULT,
6164 ac_get_thread_id(&ctx->ac), count, "");
6165 lp_build_if(&if_state, &ctx->gallivm, ena);
6166 }
6167
6168 /* Derive arguments for the next part from outputs of the
6169 * previous one.
6170 */
6171 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6172 LLVMValueRef param;
6173 LLVMTypeRef param_type;
6174 bool is_sgpr;
6175 unsigned param_size;
6176 LLVMValueRef arg = NULL;
6177
6178 param = LLVMGetParam(parts[part], param_idx);
6179 param_type = LLVMTypeOf(param);
6180 param_size = llvm_get_type_size(param_type) / 4;
6181 is_sgpr = ac_is_sgpr_param(param);
6182
6183 if (is_sgpr) {
6184 #if HAVE_LLVM < 0x0400
6185 LLVMRemoveAttribute(param, LLVMByValAttribute);
6186 #else
6187 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
6188 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
6189 #endif
6190 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
6191 }
6192
6193 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6194 assert(is_sgpr || out_idx >= num_out_sgpr);
6195
6196 if (param_size == 1)
6197 arg = out[out_idx];
6198 else
6199 arg = lp_build_gather_values(gallivm, &out[out_idx], param_size);
6200
6201 if (LLVMTypeOf(arg) != param_type) {
6202 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6203 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6204 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6205 } else {
6206 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6207 }
6208 }
6209
6210 in[param_idx] = arg;
6211 out_idx += param_size;
6212 }
6213
6214 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6215
6216 if (is_merged_shader(ctx->shader) &&
6217 part + 1 == next_shader_first_part) {
6218 lp_build_endif(&if_state);
6219
6220 /* The second half of the merged shader should use
6221 * the inputs from the toplevel (wrapper) function,
6222 * not the return value from the last call.
6223 *
6224 * That's because the last call was executed condi-
6225 * tionally, so we can't consume it in the main
6226 * block.
6227 */
6228 memcpy(out, initial, sizeof(initial));
6229 num_out = initial_num_out;
6230 num_out_sgpr = initial_num_out_sgpr;
6231 continue;
6232 }
6233
6234 /* Extract the returned GPRs. */
6235 ret_type = LLVMTypeOf(ret);
6236 num_out = 0;
6237 num_out_sgpr = 0;
6238
6239 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6240 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6241
6242 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6243
6244 for (unsigned i = 0; i < ret_size; ++i) {
6245 LLVMValueRef val =
6246 LLVMBuildExtractValue(builder, ret, i, "");
6247
6248 assert(num_out < ARRAY_SIZE(out));
6249 out[num_out++] = val;
6250
6251 if (LLVMTypeOf(val) == ctx->i32) {
6252 assert(num_out_sgpr + 1 == num_out);
6253 num_out_sgpr = num_out;
6254 }
6255 }
6256 }
6257 }
6258
6259 LLVMBuildRetVoid(builder);
6260 }
6261
6262 int si_compile_tgsi_shader(struct si_screen *sscreen,
6263 LLVMTargetMachineRef tm,
6264 struct si_shader *shader,
6265 bool is_monolithic,
6266 struct pipe_debug_callback *debug)
6267 {
6268 struct si_shader_selector *sel = shader->selector;
6269 struct si_shader_context ctx;
6270 int r = -1;
6271
6272 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6273 * conversion fails. */
6274 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
6275 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
6276 if (sel->tokens)
6277 tgsi_dump(sel->tokens, 0);
6278 else
6279 nir_print_shader(sel->nir, stderr);
6280 si_dump_streamout(&sel->so);
6281 }
6282
6283 si_init_shader_ctx(&ctx, sscreen, tm);
6284 si_llvm_context_set_tgsi(&ctx, shader);
6285 ctx.separate_prolog = !is_monolithic;
6286
6287 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6288 sizeof(shader->info.vs_output_param_offset));
6289
6290 shader->info.uses_instanceid = sel->info.uses_instanceid;
6291
6292 ctx.load_system_value = declare_system_value;
6293
6294 if (!si_compile_tgsi_main(&ctx, is_monolithic)) {
6295 si_llvm_dispose(&ctx);
6296 return -1;
6297 }
6298
6299 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6300 LLVMValueRef parts[2];
6301 bool need_prolog = sel->vs_needs_prolog;
6302
6303 parts[1] = ctx.main_fn;
6304
6305 if (need_prolog) {
6306 union si_shader_part_key prolog_key;
6307 si_get_vs_prolog_key(&sel->info,
6308 shader->info.num_input_sgprs,
6309 &shader->key.part.vs.prolog,
6310 shader, &prolog_key);
6311 si_build_vs_prolog_function(&ctx, &prolog_key);
6312 parts[0] = ctx.main_fn;
6313 }
6314
6315 si_build_wrapper_function(&ctx, parts + !need_prolog,
6316 1 + need_prolog, need_prolog, 0);
6317 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6318 if (sscreen->b.chip_class >= GFX9) {
6319 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6320 LLVMValueRef parts[4];
6321
6322 /* TCS main part */
6323 parts[2] = ctx.main_fn;
6324
6325 /* TCS epilog */
6326 union si_shader_part_key tcs_epilog_key;
6327 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6328 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6329 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6330 parts[3] = ctx.main_fn;
6331
6332 /* VS prolog */
6333 if (ls->vs_needs_prolog) {
6334 union si_shader_part_key vs_prolog_key;
6335 si_get_vs_prolog_key(&ls->info,
6336 shader->info.num_input_sgprs,
6337 &shader->key.part.tcs.ls_prolog,
6338 shader, &vs_prolog_key);
6339 vs_prolog_key.vs_prolog.is_monolithic = true;
6340 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6341 parts[0] = ctx.main_fn;
6342 }
6343
6344 /* VS as LS main part */
6345 struct si_shader shader_ls = {};
6346 shader_ls.selector = ls;
6347 shader_ls.key.as_ls = 1;
6348 shader_ls.key.mono = shader->key.mono;
6349 shader_ls.key.opt = shader->key.opt;
6350 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6351
6352 if (!si_compile_tgsi_main(&ctx, true)) {
6353 si_llvm_dispose(&ctx);
6354 return -1;
6355 }
6356 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6357 parts[1] = ctx.main_fn;
6358
6359 /* Reset the shader context. */
6360 ctx.shader = shader;
6361 ctx.type = PIPE_SHADER_TESS_CTRL;
6362
6363 si_build_wrapper_function(&ctx,
6364 parts + !ls->vs_needs_prolog,
6365 4 - !ls->vs_needs_prolog, 0,
6366 ls->vs_needs_prolog ? 2 : 1);
6367 } else {
6368 LLVMValueRef parts[2];
6369 union si_shader_part_key epilog_key;
6370
6371 parts[0] = ctx.main_fn;
6372
6373 memset(&epilog_key, 0, sizeof(epilog_key));
6374 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6375 si_build_tcs_epilog_function(&ctx, &epilog_key);
6376 parts[1] = ctx.main_fn;
6377
6378 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6379 }
6380 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6381 if (ctx.screen->b.chip_class >= GFX9) {
6382 struct si_shader_selector *es = shader->key.part.gs.es;
6383 LLVMValueRef es_prolog = NULL;
6384 LLVMValueRef es_main = NULL;
6385 LLVMValueRef gs_prolog = NULL;
6386 LLVMValueRef gs_main = ctx.main_fn;
6387
6388 /* GS prolog */
6389 union si_shader_part_key gs_prolog_key;
6390 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6391 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6392 gs_prolog_key.gs_prolog.is_monolithic = true;
6393 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6394 gs_prolog = ctx.main_fn;
6395
6396 /* ES prolog */
6397 if (es->vs_needs_prolog) {
6398 union si_shader_part_key vs_prolog_key;
6399 si_get_vs_prolog_key(&es->info,
6400 shader->info.num_input_sgprs,
6401 &shader->key.part.tcs.ls_prolog,
6402 shader, &vs_prolog_key);
6403 vs_prolog_key.vs_prolog.is_monolithic = true;
6404 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6405 es_prolog = ctx.main_fn;
6406 }
6407
6408 /* ES main part */
6409 struct si_shader shader_es = {};
6410 shader_es.selector = es;
6411 shader_es.key.as_es = 1;
6412 shader_es.key.mono = shader->key.mono;
6413 shader_es.key.opt = shader->key.opt;
6414 si_llvm_context_set_tgsi(&ctx, &shader_es);
6415
6416 if (!si_compile_tgsi_main(&ctx, true)) {
6417 si_llvm_dispose(&ctx);
6418 return -1;
6419 }
6420 shader->info.uses_instanceid |= es->info.uses_instanceid;
6421 es_main = ctx.main_fn;
6422
6423 /* Reset the shader context. */
6424 ctx.shader = shader;
6425 ctx.type = PIPE_SHADER_GEOMETRY;
6426
6427 /* Prepare the array of shader parts. */
6428 LLVMValueRef parts[4];
6429 unsigned num_parts = 0, main_part, next_first_part;
6430
6431 if (es_prolog)
6432 parts[num_parts++] = es_prolog;
6433
6434 parts[main_part = num_parts++] = es_main;
6435 parts[next_first_part = num_parts++] = gs_prolog;
6436 parts[num_parts++] = gs_main;
6437
6438 si_build_wrapper_function(&ctx, parts, num_parts,
6439 main_part, next_first_part);
6440 } else {
6441 LLVMValueRef parts[2];
6442 union si_shader_part_key prolog_key;
6443
6444 parts[1] = ctx.main_fn;
6445
6446 memset(&prolog_key, 0, sizeof(prolog_key));
6447 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6448 si_build_gs_prolog_function(&ctx, &prolog_key);
6449 parts[0] = ctx.main_fn;
6450
6451 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6452 }
6453 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6454 LLVMValueRef parts[3];
6455 union si_shader_part_key prolog_key;
6456 union si_shader_part_key epilog_key;
6457 bool need_prolog;
6458
6459 si_get_ps_prolog_key(shader, &prolog_key, false);
6460 need_prolog = si_need_ps_prolog(&prolog_key);
6461
6462 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6463
6464 if (need_prolog) {
6465 si_build_ps_prolog_function(&ctx, &prolog_key);
6466 parts[0] = ctx.main_fn;
6467 }
6468
6469 si_get_ps_epilog_key(shader, &epilog_key);
6470 si_build_ps_epilog_function(&ctx, &epilog_key);
6471 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6472
6473 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6474 need_prolog ? 1 : 0, 0);
6475 }
6476
6477 si_llvm_optimize_module(&ctx);
6478
6479 /* Post-optimization transformations and analysis. */
6480 si_optimize_vs_outputs(&ctx);
6481
6482 if ((debug && debug->debug_message) ||
6483 r600_can_dump_shader(&sscreen->b, ctx.type))
6484 si_count_scratch_private_memory(&ctx);
6485
6486 /* Compile to bytecode. */
6487 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6488 ctx.gallivm.module, debug, ctx.type, "TGSI shader");
6489 si_llvm_dispose(&ctx);
6490 if (r) {
6491 fprintf(stderr, "LLVM failed to compile shader\n");
6492 return r;
6493 }
6494
6495 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6496 * LLVM 3.9svn has this bug.
6497 */
6498 if (sel->type == PIPE_SHADER_COMPUTE) {
6499 unsigned wave_size = 64;
6500 unsigned max_vgprs = 256;
6501 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
6502 unsigned max_sgprs_per_wave = 128;
6503 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6504 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6505 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6506
6507 max_vgprs = max_vgprs / min_waves_per_simd;
6508 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6509
6510 if (shader->config.num_sgprs > max_sgprs ||
6511 shader->config.num_vgprs > max_vgprs) {
6512 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6513 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6514 shader->config.num_sgprs, shader->config.num_vgprs,
6515 max_sgprs, max_vgprs);
6516
6517 /* Just terminate the process, because dependent
6518 * shaders can hang due to bad input data, but use
6519 * the env var to allow shader-db to work.
6520 */
6521 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6522 abort();
6523 }
6524 }
6525
6526 /* Add the scratch offset to input SGPRs. */
6527 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(shader))
6528 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6529
6530 /* Calculate the number of fragment input VGPRs. */
6531 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6532 shader->info.num_input_vgprs = 0;
6533 shader->info.face_vgpr_index = -1;
6534
6535 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6536 shader->info.num_input_vgprs += 2;
6537 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6538 shader->info.num_input_vgprs += 2;
6539 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6540 shader->info.num_input_vgprs += 2;
6541 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6542 shader->info.num_input_vgprs += 3;
6543 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6544 shader->info.num_input_vgprs += 2;
6545 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6546 shader->info.num_input_vgprs += 2;
6547 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6548 shader->info.num_input_vgprs += 2;
6549 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6550 shader->info.num_input_vgprs += 1;
6551 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6552 shader->info.num_input_vgprs += 1;
6553 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6554 shader->info.num_input_vgprs += 1;
6555 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6556 shader->info.num_input_vgprs += 1;
6557 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6558 shader->info.num_input_vgprs += 1;
6559 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6560 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6561 shader->info.num_input_vgprs += 1;
6562 }
6563 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
6564 shader->info.num_input_vgprs += 1;
6565 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6566 shader->info.num_input_vgprs += 1;
6567 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6568 shader->info.num_input_vgprs += 1;
6569 }
6570
6571 return 0;
6572 }
6573
6574 /**
6575 * Create, compile and return a shader part (prolog or epilog).
6576 *
6577 * \param sscreen screen
6578 * \param list list of shader parts of the same category
6579 * \param type shader type
6580 * \param key shader part key
6581 * \param prolog whether the part being requested is a prolog
6582 * \param tm LLVM target machine
6583 * \param debug debug callback
6584 * \param build the callback responsible for building the main function
6585 * \return non-NULL on success
6586 */
6587 static struct si_shader_part *
6588 si_get_shader_part(struct si_screen *sscreen,
6589 struct si_shader_part **list,
6590 enum pipe_shader_type type,
6591 bool prolog,
6592 union si_shader_part_key *key,
6593 LLVMTargetMachineRef tm,
6594 struct pipe_debug_callback *debug,
6595 void (*build)(struct si_shader_context *,
6596 union si_shader_part_key *),
6597 const char *name)
6598 {
6599 struct si_shader_part *result;
6600
6601 mtx_lock(&sscreen->shader_parts_mutex);
6602
6603 /* Find existing. */
6604 for (result = *list; result; result = result->next) {
6605 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6606 mtx_unlock(&sscreen->shader_parts_mutex);
6607 return result;
6608 }
6609 }
6610
6611 /* Compile a new one. */
6612 result = CALLOC_STRUCT(si_shader_part);
6613 result->key = *key;
6614
6615 struct si_shader shader = {};
6616 struct si_shader_context ctx;
6617 struct gallivm_state *gallivm = &ctx.gallivm;
6618
6619 si_init_shader_ctx(&ctx, sscreen, tm);
6620 ctx.shader = &shader;
6621 ctx.type = type;
6622
6623 switch (type) {
6624 case PIPE_SHADER_VERTEX:
6625 break;
6626 case PIPE_SHADER_TESS_CTRL:
6627 assert(!prolog);
6628 shader.key.part.tcs.epilog = key->tcs_epilog.states;
6629 break;
6630 case PIPE_SHADER_GEOMETRY:
6631 assert(prolog);
6632 break;
6633 case PIPE_SHADER_FRAGMENT:
6634 if (prolog)
6635 shader.key.part.ps.prolog = key->ps_prolog.states;
6636 else
6637 shader.key.part.ps.epilog = key->ps_epilog.states;
6638 break;
6639 default:
6640 unreachable("bad shader part");
6641 }
6642
6643 build(&ctx, key);
6644
6645 /* Compile. */
6646 si_llvm_optimize_module(&ctx);
6647
6648 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
6649 gallivm->module, debug, ctx.type, name)) {
6650 FREE(result);
6651 result = NULL;
6652 goto out;
6653 }
6654
6655 result->next = *list;
6656 *list = result;
6657
6658 out:
6659 si_llvm_dispose(&ctx);
6660 mtx_unlock(&sscreen->shader_parts_mutex);
6661 return result;
6662 }
6663
6664 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
6665 {
6666 struct gallivm_state *gallivm = &ctx->gallivm;
6667 LLVMValueRef ptr[2], list;
6668
6669 /* Get the pointer to rw buffers. */
6670 ptr[0] = LLVMGetParam(ctx->main_fn, SI_SGPR_RW_BUFFERS);
6671 ptr[1] = LLVMGetParam(ctx->main_fn, SI_SGPR_RW_BUFFERS_HI);
6672 list = lp_build_gather_values(gallivm, ptr, 2);
6673 list = LLVMBuildBitCast(gallivm->builder, list, ctx->i64, "");
6674 list = LLVMBuildIntToPtr(gallivm->builder, list,
6675 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS), "");
6676 return list;
6677 }
6678
6679 /**
6680 * Build the vertex shader prolog function.
6681 *
6682 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6683 * All inputs are returned unmodified. The vertex load indices are
6684 * stored after them, which will be used by the API VS for fetching inputs.
6685 *
6686 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6687 * input_v0,
6688 * input_v1,
6689 * input_v2,
6690 * input_v3,
6691 * (VertexID + BaseVertex),
6692 * (InstanceID + StartInstance),
6693 * (InstanceID / 2 + StartInstance)
6694 */
6695 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
6696 union si_shader_part_key *key)
6697 {
6698 struct gallivm_state *gallivm = &ctx->gallivm;
6699 struct si_function_info fninfo;
6700 LLVMTypeRef *returns;
6701 LLVMValueRef ret, func;
6702 int num_returns, i;
6703 unsigned first_vs_vgpr = key->vs_prolog.num_input_sgprs +
6704 key->vs_prolog.num_merged_next_stage_vgprs;
6705 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
6706 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
6707 num_input_vgprs;
6708 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
6709
6710 si_init_function_info(&fninfo);
6711
6712 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6713 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
6714 sizeof(LLVMTypeRef));
6715 num_returns = 0;
6716
6717 /* Declare input and output SGPRs. */
6718 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6719 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6720 returns[num_returns++] = ctx->i32;
6721 }
6722
6723 /* Preloaded VGPRs (outputs must be floats) */
6724 for (i = 0; i < num_input_vgprs; i++) {
6725 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6726 returns[num_returns++] = ctx->f32;
6727 }
6728
6729 fninfo.assign[first_vs_vgpr] = &ctx->abi.vertex_id;
6730 fninfo.assign[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)] = &ctx->abi.instance_id;
6731
6732 /* Vertex load indices. */
6733 for (i = 0; i <= key->vs_prolog.last_input; i++)
6734 returns[num_returns++] = ctx->f32;
6735
6736 /* Create the function. */
6737 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
6738 func = ctx->main_fn;
6739
6740 if (key->vs_prolog.num_merged_next_stage_vgprs &&
6741 !key->vs_prolog.is_monolithic)
6742 si_init_exec_from_input(ctx, 3, 0);
6743
6744 /* Copy inputs to outputs. This should be no-op, as the registers match,
6745 * but it will prevent the compiler from overwriting them unintentionally.
6746 */
6747 ret = ctx->return_value;
6748 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6749 LLVMValueRef p = LLVMGetParam(func, i);
6750 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6751 }
6752 for (; i < fninfo.num_params; i++) {
6753 LLVMValueRef p = LLVMGetParam(func, i);
6754 p = LLVMBuildBitCast(gallivm->builder, p, ctx->f32, "");
6755 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6756 }
6757
6758 /* Compute vertex load indices from instance divisors. */
6759 LLVMValueRef instance_divisor_constbuf = NULL;
6760
6761 if (key->vs_prolog.states.instance_divisor_is_fetched) {
6762 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
6763 LLVMValueRef buf_index =
6764 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
6765 instance_divisor_constbuf =
6766 ac_build_indexed_load_const(&ctx->ac, list, buf_index);
6767 }
6768
6769 for (i = 0; i <= key->vs_prolog.last_input; i++) {
6770 bool divisor_is_one =
6771 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
6772 bool divisor_is_fetched =
6773 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
6774 LLVMValueRef index;
6775
6776 if (divisor_is_one || divisor_is_fetched) {
6777 LLVMValueRef divisor = ctx->i32_1;
6778
6779 if (divisor_is_fetched) {
6780 divisor = buffer_load_const(ctx, instance_divisor_constbuf,
6781 LLVMConstInt(ctx->i32, i * 4, 0));
6782 divisor = LLVMBuildBitCast(gallivm->builder, divisor,
6783 ctx->i32, "");
6784 }
6785
6786 /* InstanceID / Divisor + StartInstance */
6787 index = get_instance_index_for_fetch(ctx,
6788 user_sgpr_base +
6789 SI_SGPR_START_INSTANCE,
6790 divisor);
6791 } else {
6792 /* VertexID + BaseVertex */
6793 index = LLVMBuildAdd(gallivm->builder,
6794 ctx->abi.vertex_id,
6795 LLVMGetParam(func, user_sgpr_base +
6796 SI_SGPR_BASE_VERTEX), "");
6797 }
6798
6799 index = LLVMBuildBitCast(gallivm->builder, index, ctx->f32, "");
6800 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
6801 fninfo.num_params + i, "");
6802 }
6803
6804 si_llvm_build_ret(ctx, ret);
6805 }
6806
6807 static bool si_get_vs_prolog(struct si_screen *sscreen,
6808 LLVMTargetMachineRef tm,
6809 struct si_shader *shader,
6810 struct pipe_debug_callback *debug,
6811 struct si_shader *main_part,
6812 const struct si_vs_prolog_bits *key)
6813 {
6814 struct si_shader_selector *vs = main_part->selector;
6815
6816 /* The prolog is a no-op if there are no inputs. */
6817 if (!vs->vs_needs_prolog)
6818 return true;
6819
6820 /* Get the prolog. */
6821 union si_shader_part_key prolog_key;
6822 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
6823 key, shader, &prolog_key);
6824
6825 shader->prolog =
6826 si_get_shader_part(sscreen, &sscreen->vs_prologs,
6827 PIPE_SHADER_VERTEX, true, &prolog_key, tm,
6828 debug, si_build_vs_prolog_function,
6829 "Vertex Shader Prolog");
6830 return shader->prolog != NULL;
6831 }
6832
6833 /**
6834 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
6835 */
6836 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
6837 LLVMTargetMachineRef tm,
6838 struct si_shader *shader,
6839 struct pipe_debug_callback *debug)
6840 {
6841 return si_get_vs_prolog(sscreen, tm, shader, debug, shader,
6842 &shader->key.part.vs.prolog);
6843 }
6844
6845 /**
6846 * Compile the TCS epilog function. This writes tesselation factors to memory
6847 * based on the output primitive type of the tesselator (determined by TES).
6848 */
6849 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
6850 union si_shader_part_key *key)
6851 {
6852 struct gallivm_state *gallivm = &ctx->gallivm;
6853 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6854 struct si_function_info fninfo;
6855 LLVMValueRef func;
6856
6857 si_init_function_info(&fninfo);
6858
6859 if (ctx->screen->b.chip_class >= GFX9) {
6860 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6861 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6862 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
6863 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6864 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6865 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6866 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6867 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6868 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6869 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6870 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6871 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6872 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6873 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6874 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6875 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6876 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6877 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6878 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6879 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6880 } else {
6881 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6882 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6883 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6884 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6885 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6886 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6887 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6888 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6889 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6890 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6891 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6892 }
6893
6894 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
6895 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
6896 unsigned tess_factors_idx =
6897 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
6898 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
6899 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
6900
6901 /* Create the function. */
6902 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
6903 ctx->screen->b.chip_class >= CIK ? 128 : 64);
6904 declare_lds_as_pointer(ctx);
6905 func = ctx->main_fn;
6906
6907 si_write_tess_factors(bld_base,
6908 LLVMGetParam(func, tess_factors_idx),
6909 LLVMGetParam(func, tess_factors_idx + 1),
6910 LLVMGetParam(func, tess_factors_idx + 2));
6911
6912 LLVMBuildRetVoid(gallivm->builder);
6913 }
6914
6915 /**
6916 * Select and compile (or reuse) TCS parts (epilog).
6917 */
6918 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
6919 LLVMTargetMachineRef tm,
6920 struct si_shader *shader,
6921 struct pipe_debug_callback *debug)
6922 {
6923 if (sscreen->b.chip_class >= GFX9) {
6924 struct si_shader *ls_main_part =
6925 shader->key.part.tcs.ls->main_shader_part_ls;
6926
6927 if (!si_get_vs_prolog(sscreen, tm, shader, debug, ls_main_part,
6928 &shader->key.part.tcs.ls_prolog))
6929 return false;
6930
6931 shader->previous_stage = ls_main_part;
6932 }
6933
6934 /* Get the epilog. */
6935 union si_shader_part_key epilog_key;
6936 memset(&epilog_key, 0, sizeof(epilog_key));
6937 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6938
6939 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
6940 PIPE_SHADER_TESS_CTRL, false,
6941 &epilog_key, tm, debug,
6942 si_build_tcs_epilog_function,
6943 "Tessellation Control Shader Epilog");
6944 return shader->epilog != NULL;
6945 }
6946
6947 /**
6948 * Select and compile (or reuse) GS parts (prolog).
6949 */
6950 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
6951 LLVMTargetMachineRef tm,
6952 struct si_shader *shader,
6953 struct pipe_debug_callback *debug)
6954 {
6955 if (sscreen->b.chip_class >= GFX9) {
6956 struct si_shader *es_main_part =
6957 shader->key.part.gs.es->main_shader_part_es;
6958
6959 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
6960 !si_get_vs_prolog(sscreen, tm, shader, debug, es_main_part,
6961 &shader->key.part.gs.vs_prolog))
6962 return false;
6963
6964 shader->previous_stage = es_main_part;
6965 }
6966
6967 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
6968 return true;
6969
6970 union si_shader_part_key prolog_key;
6971 memset(&prolog_key, 0, sizeof(prolog_key));
6972 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6973
6974 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
6975 PIPE_SHADER_GEOMETRY, true,
6976 &prolog_key, tm, debug,
6977 si_build_gs_prolog_function,
6978 "Geometry Shader Prolog");
6979 return shader->prolog2 != NULL;
6980 }
6981
6982 /**
6983 * Build the pixel shader prolog function. This handles:
6984 * - two-side color selection and interpolation
6985 * - overriding interpolation parameters for the API PS
6986 * - polygon stippling
6987 *
6988 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
6989 * overriden by other states. (e.g. per-sample interpolation)
6990 * Interpolated colors are stored after the preloaded VGPRs.
6991 */
6992 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
6993 union si_shader_part_key *key)
6994 {
6995 struct gallivm_state *gallivm = &ctx->gallivm;
6996 struct si_function_info fninfo;
6997 LLVMValueRef ret, func;
6998 int num_returns, i, num_color_channels;
6999
7000 assert(si_need_ps_prolog(key));
7001
7002 si_init_function_info(&fninfo);
7003
7004 /* Declare inputs. */
7005 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7006 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7007
7008 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7009 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7010
7011 /* Declare outputs (same as inputs + add colors if needed) */
7012 num_returns = fninfo.num_params;
7013 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7014 for (i = 0; i < num_color_channels; i++)
7015 fninfo.types[num_returns++] = ctx->f32;
7016
7017 /* Create the function. */
7018 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7019 &fninfo, 0);
7020 func = ctx->main_fn;
7021
7022 /* Copy inputs to outputs. This should be no-op, as the registers match,
7023 * but it will prevent the compiler from overwriting them unintentionally.
7024 */
7025 ret = ctx->return_value;
7026 for (i = 0; i < fninfo.num_params; i++) {
7027 LLVMValueRef p = LLVMGetParam(func, i);
7028 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7029 }
7030
7031 /* Polygon stippling. */
7032 if (key->ps_prolog.states.poly_stipple) {
7033 /* POS_FIXED_PT is always last. */
7034 unsigned pos = key->ps_prolog.num_input_sgprs +
7035 key->ps_prolog.num_input_vgprs - 1;
7036 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7037
7038 si_llvm_emit_polygon_stipple(ctx, list, pos);
7039 }
7040
7041 if (key->ps_prolog.states.bc_optimize_for_persp ||
7042 key->ps_prolog.states.bc_optimize_for_linear) {
7043 unsigned i, base = key->ps_prolog.num_input_sgprs;
7044 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7045
7046 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7047 * The hw doesn't compute CENTROID if the whole wave only
7048 * contains fully-covered quads.
7049 *
7050 * PRIM_MASK is after user SGPRs.
7051 */
7052 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7053 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
7054 LLVMConstInt(ctx->i32, 31, 0), "");
7055 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
7056 ctx->i1, "");
7057
7058 if (key->ps_prolog.states.bc_optimize_for_persp) {
7059 /* Read PERSP_CENTER. */
7060 for (i = 0; i < 2; i++)
7061 center[i] = LLVMGetParam(func, base + 2 + i);
7062 /* Read PERSP_CENTROID. */
7063 for (i = 0; i < 2; i++)
7064 centroid[i] = LLVMGetParam(func, base + 4 + i);
7065 /* Select PERSP_CENTROID. */
7066 for (i = 0; i < 2; i++) {
7067 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7068 center[i], centroid[i], "");
7069 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7070 tmp, base + 4 + i, "");
7071 }
7072 }
7073 if (key->ps_prolog.states.bc_optimize_for_linear) {
7074 /* Read LINEAR_CENTER. */
7075 for (i = 0; i < 2; i++)
7076 center[i] = LLVMGetParam(func, base + 8 + i);
7077 /* Read LINEAR_CENTROID. */
7078 for (i = 0; i < 2; i++)
7079 centroid[i] = LLVMGetParam(func, base + 10 + i);
7080 /* Select LINEAR_CENTROID. */
7081 for (i = 0; i < 2; i++) {
7082 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7083 center[i], centroid[i], "");
7084 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7085 tmp, base + 10 + i, "");
7086 }
7087 }
7088 }
7089
7090 /* Force per-sample interpolation. */
7091 if (key->ps_prolog.states.force_persp_sample_interp) {
7092 unsigned i, base = key->ps_prolog.num_input_sgprs;
7093 LLVMValueRef persp_sample[2];
7094
7095 /* Read PERSP_SAMPLE. */
7096 for (i = 0; i < 2; i++)
7097 persp_sample[i] = LLVMGetParam(func, base + i);
7098 /* Overwrite PERSP_CENTER. */
7099 for (i = 0; i < 2; i++)
7100 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7101 persp_sample[i], base + 2 + i, "");
7102 /* Overwrite PERSP_CENTROID. */
7103 for (i = 0; i < 2; i++)
7104 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7105 persp_sample[i], base + 4 + i, "");
7106 }
7107 if (key->ps_prolog.states.force_linear_sample_interp) {
7108 unsigned i, base = key->ps_prolog.num_input_sgprs;
7109 LLVMValueRef linear_sample[2];
7110
7111 /* Read LINEAR_SAMPLE. */
7112 for (i = 0; i < 2; i++)
7113 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7114 /* Overwrite LINEAR_CENTER. */
7115 for (i = 0; i < 2; i++)
7116 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7117 linear_sample[i], base + 8 + i, "");
7118 /* Overwrite LINEAR_CENTROID. */
7119 for (i = 0; i < 2; i++)
7120 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7121 linear_sample[i], base + 10 + i, "");
7122 }
7123
7124 /* Force center interpolation. */
7125 if (key->ps_prolog.states.force_persp_center_interp) {
7126 unsigned i, base = key->ps_prolog.num_input_sgprs;
7127 LLVMValueRef persp_center[2];
7128
7129 /* Read PERSP_CENTER. */
7130 for (i = 0; i < 2; i++)
7131 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7132 /* Overwrite PERSP_SAMPLE. */
7133 for (i = 0; i < 2; i++)
7134 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7135 persp_center[i], base + i, "");
7136 /* Overwrite PERSP_CENTROID. */
7137 for (i = 0; i < 2; i++)
7138 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7139 persp_center[i], base + 4 + i, "");
7140 }
7141 if (key->ps_prolog.states.force_linear_center_interp) {
7142 unsigned i, base = key->ps_prolog.num_input_sgprs;
7143 LLVMValueRef linear_center[2];
7144
7145 /* Read LINEAR_CENTER. */
7146 for (i = 0; i < 2; i++)
7147 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7148 /* Overwrite LINEAR_SAMPLE. */
7149 for (i = 0; i < 2; i++)
7150 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7151 linear_center[i], base + 6 + i, "");
7152 /* Overwrite LINEAR_CENTROID. */
7153 for (i = 0; i < 2; i++)
7154 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7155 linear_center[i], base + 10 + i, "");
7156 }
7157
7158 /* Interpolate colors. */
7159 unsigned color_out_idx = 0;
7160 for (i = 0; i < 2; i++) {
7161 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7162 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7163 key->ps_prolog.face_vgpr_index;
7164 LLVMValueRef interp[2], color[4];
7165 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7166
7167 if (!writemask)
7168 continue;
7169
7170 /* If the interpolation qualifier is not CONSTANT (-1). */
7171 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7172 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7173 key->ps_prolog.color_interp_vgpr_index[i];
7174
7175 /* Get the (i,j) updated by bc_optimize handling. */
7176 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
7177 interp_vgpr, "");
7178 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
7179 interp_vgpr + 1, "");
7180 interp_ij = lp_build_gather_values(gallivm, interp, 2);
7181 }
7182
7183 /* Use the absolute location of the input. */
7184 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7185
7186 if (key->ps_prolog.states.color_two_side) {
7187 face = LLVMGetParam(func, face_vgpr);
7188 face = LLVMBuildBitCast(gallivm->builder, face, ctx->i32, "");
7189 }
7190
7191 interp_fs_input(ctx,
7192 key->ps_prolog.color_attr_index[i],
7193 TGSI_SEMANTIC_COLOR, i,
7194 key->ps_prolog.num_interp_inputs,
7195 key->ps_prolog.colors_read, interp_ij,
7196 prim_mask, face, color);
7197
7198 while (writemask) {
7199 unsigned chan = u_bit_scan(&writemask);
7200 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
7201 fninfo.num_params + color_out_idx++, "");
7202 }
7203 }
7204
7205 /* Tell LLVM to insert WQM instruction sequence when needed. */
7206 if (key->ps_prolog.wqm) {
7207 LLVMAddTargetDependentFunctionAttr(func,
7208 "amdgpu-ps-wqm-outputs", "");
7209 }
7210
7211 si_llvm_build_ret(ctx, ret);
7212 }
7213
7214 /**
7215 * Build the pixel shader epilog function. This handles everything that must be
7216 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7217 */
7218 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7219 union si_shader_part_key *key)
7220 {
7221 struct gallivm_state *gallivm = &ctx->gallivm;
7222 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7223 struct si_function_info fninfo;
7224 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7225 int i;
7226 struct si_ps_exports exp = {};
7227
7228 si_init_function_info(&fninfo);
7229
7230 /* Declare input SGPRs. */
7231 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7232 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7233 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7234 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7235
7236 /* Declare input VGPRs. */
7237 unsigned required_num_params =
7238 fninfo.num_sgpr_params +
7239 util_bitcount(key->ps_epilog.colors_written) * 4 +
7240 key->ps_epilog.writes_z +
7241 key->ps_epilog.writes_stencil +
7242 key->ps_epilog.writes_samplemask;
7243
7244 required_num_params = MAX2(required_num_params,
7245 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7246
7247 while (fninfo.num_params < required_num_params)
7248 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7249
7250 /* Create the function. */
7251 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7252 /* Disable elimination of unused inputs. */
7253 si_llvm_add_attribute(ctx->main_fn,
7254 "InitialPSInputAddr", 0xffffff);
7255
7256 /* Process colors. */
7257 unsigned vgpr = fninfo.num_sgpr_params;
7258 unsigned colors_written = key->ps_epilog.colors_written;
7259 int last_color_export = -1;
7260
7261 /* Find the last color export. */
7262 if (!key->ps_epilog.writes_z &&
7263 !key->ps_epilog.writes_stencil &&
7264 !key->ps_epilog.writes_samplemask) {
7265 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7266
7267 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7268 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7269 /* Just set this if any of the colorbuffers are enabled. */
7270 if (spi_format &
7271 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7272 last_color_export = 0;
7273 } else {
7274 for (i = 0; i < 8; i++)
7275 if (colors_written & (1 << i) &&
7276 (spi_format >> (i * 4)) & 0xf)
7277 last_color_export = i;
7278 }
7279 }
7280
7281 while (colors_written) {
7282 LLVMValueRef color[4];
7283 int mrt = u_bit_scan(&colors_written);
7284
7285 for (i = 0; i < 4; i++)
7286 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7287
7288 si_export_mrt_color(bld_base, color, mrt,
7289 fninfo.num_params - 1,
7290 mrt == last_color_export, &exp);
7291 }
7292
7293 /* Process depth, stencil, samplemask. */
7294 if (key->ps_epilog.writes_z)
7295 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7296 if (key->ps_epilog.writes_stencil)
7297 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7298 if (key->ps_epilog.writes_samplemask)
7299 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7300
7301 if (depth || stencil || samplemask)
7302 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7303 else if (last_color_export == -1)
7304 si_export_null(bld_base);
7305
7306 if (exp.num)
7307 si_emit_ps_exports(ctx, &exp);
7308
7309 /* Compile. */
7310 LLVMBuildRetVoid(gallivm->builder);
7311 }
7312
7313 /**
7314 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7315 */
7316 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7317 LLVMTargetMachineRef tm,
7318 struct si_shader *shader,
7319 struct pipe_debug_callback *debug)
7320 {
7321 union si_shader_part_key prolog_key;
7322 union si_shader_part_key epilog_key;
7323
7324 /* Get the prolog. */
7325 si_get_ps_prolog_key(shader, &prolog_key, true);
7326
7327 /* The prolog is a no-op if these aren't set. */
7328 if (si_need_ps_prolog(&prolog_key)) {
7329 shader->prolog =
7330 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7331 PIPE_SHADER_FRAGMENT, true,
7332 &prolog_key, tm, debug,
7333 si_build_ps_prolog_function,
7334 "Fragment Shader Prolog");
7335 if (!shader->prolog)
7336 return false;
7337 }
7338
7339 /* Get the epilog. */
7340 si_get_ps_epilog_key(shader, &epilog_key);
7341
7342 shader->epilog =
7343 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7344 PIPE_SHADER_FRAGMENT, false,
7345 &epilog_key, tm, debug,
7346 si_build_ps_epilog_function,
7347 "Fragment Shader Epilog");
7348 if (!shader->epilog)
7349 return false;
7350
7351 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7352 if (shader->key.part.ps.prolog.poly_stipple) {
7353 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7354 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7355 }
7356
7357 /* Set up the enable bits for per-sample shading if needed. */
7358 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7359 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7360 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7361 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7362 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7363 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7364 }
7365 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7366 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7367 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7368 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7369 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7370 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7371 }
7372 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7373 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7374 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7375 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7376 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7377 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7378 }
7379 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7380 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7381 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7382 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7383 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7384 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7385 }
7386
7387 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7388 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7389 !(shader->config.spi_ps_input_ena & 0xf)) {
7390 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7391 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7392 }
7393
7394 /* At least one pair of interpolation weights must be enabled. */
7395 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7396 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7397 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7398 }
7399
7400 /* The sample mask input is always enabled, because the API shader always
7401 * passes it through to the epilog. Disable it here if it's unused.
7402 */
7403 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7404 !shader->selector->info.reads_samplemask)
7405 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7406
7407 return true;
7408 }
7409
7410 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7411 unsigned *lds_size)
7412 {
7413 /* SPI barrier management bug:
7414 * Make sure we have at least 4k of LDS in use to avoid the bug.
7415 * It applies to workgroup sizes of more than one wavefront.
7416 */
7417 if (sscreen->b.family == CHIP_BONAIRE ||
7418 sscreen->b.family == CHIP_KABINI ||
7419 sscreen->b.family == CHIP_MULLINS)
7420 *lds_size = MAX2(*lds_size, 8);
7421 }
7422
7423 static void si_fix_resource_usage(struct si_screen *sscreen,
7424 struct si_shader *shader)
7425 {
7426 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7427
7428 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7429
7430 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7431 si_get_max_workgroup_size(shader) > 64) {
7432 si_multiwave_lds_size_workaround(sscreen,
7433 &shader->config.lds_size);
7434 }
7435 }
7436
7437 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7438 struct si_shader *shader,
7439 struct pipe_debug_callback *debug)
7440 {
7441 struct si_shader_selector *sel = shader->selector;
7442 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7443 int r;
7444
7445 /* LS, ES, VS are compiled on demand if the main part hasn't been
7446 * compiled for that stage.
7447 *
7448 * Vertex shaders are compiled on demand when a vertex fetch
7449 * workaround must be applied.
7450 */
7451 if (shader->is_monolithic) {
7452 /* Monolithic shader (compiled as a whole, has many variants,
7453 * may take a long time to compile).
7454 */
7455 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7456 if (r)
7457 return r;
7458 } else {
7459 /* The shader consists of several parts:
7460 *
7461 * - the middle part is the user shader, it has 1 variant only
7462 * and it was compiled during the creation of the shader
7463 * selector
7464 * - the prolog part is inserted at the beginning
7465 * - the epilog part is inserted at the end
7466 *
7467 * The prolog and epilog have many (but simple) variants.
7468 *
7469 * Starting with gfx9, geometry and tessellation control
7470 * shaders also contain the prolog and user shader parts of
7471 * the previous shader stage.
7472 */
7473
7474 if (!mainp)
7475 return -1;
7476
7477 /* Copy the compiled TGSI shader data over. */
7478 shader->is_binary_shared = true;
7479 shader->binary = mainp->binary;
7480 shader->config = mainp->config;
7481 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7482 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7483 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7484 memcpy(shader->info.vs_output_param_offset,
7485 mainp->info.vs_output_param_offset,
7486 sizeof(mainp->info.vs_output_param_offset));
7487 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7488 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7489 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7490
7491 /* Select prologs and/or epilogs. */
7492 switch (sel->type) {
7493 case PIPE_SHADER_VERTEX:
7494 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7495 return -1;
7496 break;
7497 case PIPE_SHADER_TESS_CTRL:
7498 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7499 return -1;
7500 break;
7501 case PIPE_SHADER_TESS_EVAL:
7502 break;
7503 case PIPE_SHADER_GEOMETRY:
7504 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
7505 return -1;
7506 break;
7507 case PIPE_SHADER_FRAGMENT:
7508 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7509 return -1;
7510
7511 /* Make sure we have at least as many VGPRs as there
7512 * are allocated inputs.
7513 */
7514 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7515 shader->info.num_input_vgprs);
7516 break;
7517 }
7518
7519 /* Update SGPR and VGPR counts. */
7520 if (shader->prolog) {
7521 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7522 shader->prolog->config.num_sgprs);
7523 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7524 shader->prolog->config.num_vgprs);
7525 }
7526 if (shader->previous_stage) {
7527 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7528 shader->previous_stage->config.num_sgprs);
7529 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7530 shader->previous_stage->config.num_vgprs);
7531 shader->config.spilled_sgprs =
7532 MAX2(shader->config.spilled_sgprs,
7533 shader->previous_stage->config.spilled_sgprs);
7534 shader->config.spilled_vgprs =
7535 MAX2(shader->config.spilled_vgprs,
7536 shader->previous_stage->config.spilled_vgprs);
7537 shader->config.private_mem_vgprs =
7538 MAX2(shader->config.private_mem_vgprs,
7539 shader->previous_stage->config.private_mem_vgprs);
7540 shader->config.scratch_bytes_per_wave =
7541 MAX2(shader->config.scratch_bytes_per_wave,
7542 shader->previous_stage->config.scratch_bytes_per_wave);
7543 shader->info.uses_instanceid |=
7544 shader->previous_stage->info.uses_instanceid;
7545 }
7546 if (shader->prolog2) {
7547 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7548 shader->prolog2->config.num_sgprs);
7549 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7550 shader->prolog2->config.num_vgprs);
7551 }
7552 if (shader->epilog) {
7553 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7554 shader->epilog->config.num_sgprs);
7555 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7556 shader->epilog->config.num_vgprs);
7557 }
7558 }
7559
7560 si_fix_resource_usage(sscreen, shader);
7561 si_shader_dump(sscreen, shader, debug, sel->info.processor,
7562 stderr, true);
7563
7564 /* Upload. */
7565 r = si_shader_binary_upload(sscreen, shader);
7566 if (r) {
7567 fprintf(stderr, "LLVM failed to upload shader\n");
7568 return r;
7569 }
7570
7571 return 0;
7572 }
7573
7574 void si_shader_destroy(struct si_shader *shader)
7575 {
7576 if (shader->scratch_bo)
7577 r600_resource_reference(&shader->scratch_bo, NULL);
7578
7579 r600_resource_reference(&shader->bo, NULL);
7580
7581 if (!shader->is_binary_shared)
7582 radeon_shader_binary_clean(&shader->binary);
7583
7584 free(shader->shader_log);
7585 }