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freedreno/a3xx: only emit dirty consts
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "radeon/radeon_llvm.h"
36 #include "radeon/radeon_llvm_emit.h"
37 #include "util/u_memory.h"
38 #include "tgsi/tgsi_parse.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "si_pipe.h"
43 #include "si_shader.h"
44 #include "sid.h"
45
46 #include <errno.h>
47
48 struct si_shader_output_values
49 {
50 LLVMValueRef values[4];
51 unsigned name;
52 unsigned sid;
53 };
54
55 struct si_shader_context
56 {
57 struct radeon_llvm_context radeon_bld;
58 struct tgsi_parse_context parse;
59 struct tgsi_token * tokens;
60 struct si_shader *shader;
61 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
62 int param_streamout_config;
63 int param_streamout_write_index;
64 int param_streamout_offset[4];
65 int param_vertex_id;
66 int param_instance_id;
67 LLVMValueRef const_md;
68 LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
69 LLVMValueRef ddxy_lds;
70 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
71 LLVMValueRef *resources;
72 LLVMValueRef *samplers;
73 LLVMValueRef so_buffers[4];
74 LLVMValueRef gs_next_vertex;
75 };
76
77 static struct si_shader_context * si_shader_context(
78 struct lp_build_tgsi_context * bld_base)
79 {
80 return (struct si_shader_context *)bld_base;
81 }
82
83
84 #define PERSPECTIVE_BASE 0
85 #define LINEAR_BASE 9
86
87 #define SAMPLE_OFFSET 0
88 #define CENTER_OFFSET 2
89 #define CENTROID_OFSET 4
90
91 #define USE_SGPR_MAX_SUFFIX_LEN 5
92 #define CONST_ADDR_SPACE 2
93 #define LOCAL_ADDR_SPACE 3
94 #define USER_SGPR_ADDR_SPACE 8
95
96
97 #define SENDMSG_GS 2
98 #define SENDMSG_GS_DONE 3
99
100 #define SENDMSG_GS_OP_NOP (0 << 4)
101 #define SENDMSG_GS_OP_CUT (1 << 4)
102 #define SENDMSG_GS_OP_EMIT (2 << 4)
103 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
104
105 /**
106 * Returns a unique index for a semantic name and index. The index must be
107 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
108 * calculated.
109 */
110 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
111 {
112 switch (semantic_name) {
113 case TGSI_SEMANTIC_POSITION:
114 return 0;
115 case TGSI_SEMANTIC_PSIZE:
116 return 1;
117 case TGSI_SEMANTIC_CLIPDIST:
118 assert(index <= 1);
119 return 2 + index;
120 case TGSI_SEMANTIC_CLIPVERTEX:
121 return 4;
122 case TGSI_SEMANTIC_COLOR:
123 assert(index <= 1);
124 return 5 + index;
125 case TGSI_SEMANTIC_BCOLOR:
126 assert(index <= 1);
127 return 7 + index;
128 case TGSI_SEMANTIC_FOG:
129 return 9;
130 case TGSI_SEMANTIC_EDGEFLAG:
131 return 10;
132 case TGSI_SEMANTIC_GENERIC:
133 assert(index <= 63-11);
134 return 11 + index;
135 default:
136 assert(0);
137 return 63;
138 }
139 }
140
141 /**
142 * Given a semantic name and index of a parameter and a mask of used parameters
143 * (inputs or outputs), return the index of the parameter in the list of all
144 * used parameters.
145 *
146 * For example, assume this list of parameters:
147 * POSITION, PSIZE, GENERIC0, GENERIC2
148 * which has the mask:
149 * 11000000000101
150 * Then:
151 * querying POSITION returns 0,
152 * querying PSIZE returns 1,
153 * querying GENERIC0 returns 2,
154 * querying GENERIC2 returns 3.
155 *
156 * Which can be used as an offset to a parameter buffer in units of vec4s.
157 */
158 static int get_param_index(unsigned semantic_name, unsigned index,
159 uint64_t mask)
160 {
161 unsigned unique_index = si_shader_io_get_unique_index(semantic_name, index);
162 int i, param_index = 0;
163
164 /* If not present... */
165 if (!((1llu << unique_index) & mask))
166 return -1;
167
168 for (i = 0; mask; i++) {
169 uint64_t bit = 1llu << i;
170
171 if (bit & mask) {
172 if (i == unique_index)
173 return param_index;
174
175 mask &= ~bit;
176 param_index++;
177 }
178 }
179
180 assert(!"unreachable");
181 return -1;
182 }
183
184 /**
185 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
186 *
187 * @param offset The offset parameter specifies the number of
188 * elements to offset, not the number of bytes or dwords. An element is the
189 * the type pointed to by the base_ptr parameter (e.g. int is the element of
190 * an int* pointer)
191 *
192 * When LLVM lowers the load instruction, it will convert the element offset
193 * into a dword offset automatically.
194 *
195 */
196 static LLVMValueRef build_indexed_load(
197 struct si_shader_context * si_shader_ctx,
198 LLVMValueRef base_ptr,
199 LLVMValueRef offset)
200 {
201 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
202
203 LLVMValueRef indices[2] = {
204 LLVMConstInt(LLVMInt64TypeInContext(base->gallivm->context), 0, false),
205 offset
206 };
207 LLVMValueRef computed_ptr = LLVMBuildGEP(
208 base->gallivm->builder, base_ptr, indices, 2, "");
209
210 LLVMValueRef result = LLVMBuildLoad(base->gallivm->builder, computed_ptr, "");
211 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
212 return result;
213 }
214
215 static LLVMValueRef get_instance_index_for_fetch(
216 struct radeon_llvm_context * radeon_bld,
217 unsigned divisor)
218 {
219 struct si_shader_context *si_shader_ctx =
220 si_shader_context(&radeon_bld->soa.bld_base);
221 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
222
223 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
224 si_shader_ctx->param_instance_id);
225 result = LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
226 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
227
228 if (divisor > 1)
229 result = LLVMBuildUDiv(gallivm->builder, result,
230 lp_build_const_int32(gallivm, divisor), "");
231
232 return result;
233 }
234
235 static void declare_input_vs(
236 struct radeon_llvm_context *radeon_bld,
237 unsigned input_index,
238 const struct tgsi_full_declaration *decl)
239 {
240 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
241 struct gallivm_state *gallivm = base->gallivm;
242 struct si_shader_context *si_shader_ctx =
243 si_shader_context(&radeon_bld->soa.bld_base);
244 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
245
246 unsigned chan;
247
248 LLVMValueRef t_list_ptr;
249 LLVMValueRef t_offset;
250 LLVMValueRef t_list;
251 LLVMValueRef attribute_offset;
252 LLVMValueRef buffer_index;
253 LLVMValueRef args[3];
254 LLVMTypeRef vec4_type;
255 LLVMValueRef input;
256
257 /* Load the T list */
258 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
259
260 t_offset = lp_build_const_int32(gallivm, input_index);
261
262 t_list = build_indexed_load(si_shader_ctx, t_list_ptr, t_offset);
263
264 /* Build the attribute offset */
265 attribute_offset = lp_build_const_int32(gallivm, 0);
266
267 if (divisor) {
268 /* Build index from instance ID, start instance and divisor */
269 si_shader_ctx->shader->uses_instanceid = true;
270 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
271 } else {
272 /* Load the buffer index for vertices. */
273 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
274 si_shader_ctx->param_vertex_id);
275 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
276 SI_PARAM_BASE_VERTEX);
277 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
278 }
279
280 vec4_type = LLVMVectorType(base->elem_type, 4);
281 args[0] = t_list;
282 args[1] = attribute_offset;
283 args[2] = buffer_index;
284 input = build_intrinsic(gallivm->builder,
285 "llvm.SI.vs.load.input", vec4_type, args, 3,
286 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
287
288 /* Break up the vec4 into individual components */
289 for (chan = 0; chan < 4; chan++) {
290 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
291 /* XXX: Use a helper function for this. There is one in
292 * tgsi_llvm.c. */
293 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
294 LLVMBuildExtractElement(gallivm->builder,
295 input, llvm_chan, "");
296 }
297 }
298
299 static LLVMValueRef fetch_input_gs(
300 struct lp_build_tgsi_context *bld_base,
301 const struct tgsi_full_src_register *reg,
302 enum tgsi_opcode_type type,
303 unsigned swizzle)
304 {
305 struct lp_build_context *base = &bld_base->base;
306 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
307 struct si_shader *shader = si_shader_ctx->shader;
308 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
309 struct gallivm_state *gallivm = base->gallivm;
310 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
311 LLVMValueRef vtx_offset;
312 LLVMValueRef t_list_ptr;
313 LLVMValueRef t_list;
314 LLVMValueRef args[9];
315 unsigned vtx_offset_param;
316 struct tgsi_shader_info *info = &shader->selector->info;
317 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
318 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
319
320 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID) {
321 if (swizzle == 0)
322 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
323 SI_PARAM_PRIMITIVE_ID);
324 else
325 return uint->zero;
326 }
327
328 if (!reg->Register.Dimension)
329 return NULL;
330
331 if (swizzle == ~0) {
332 LLVMValueRef values[TGSI_NUM_CHANNELS];
333 unsigned chan;
334 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
335 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
336 }
337 return lp_build_gather_values(bld_base->base.gallivm, values,
338 TGSI_NUM_CHANNELS);
339 }
340
341 /* Get the vertex offset parameter */
342 vtx_offset_param = reg->Dimension.Index;
343 if (vtx_offset_param < 2) {
344 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
345 } else {
346 assert(vtx_offset_param < 6);
347 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
348 }
349 vtx_offset = lp_build_mul_imm(uint,
350 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
351 vtx_offset_param),
352 4);
353
354 /* Load the ESGS ring resource descriptor */
355 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
356 SI_PARAM_RW_BUFFERS);
357 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
358 lp_build_const_int32(gallivm, SI_RING_ESGS));
359
360 args[0] = t_list;
361 args[1] = vtx_offset;
362 args[2] = lp_build_const_int32(gallivm,
363 (get_param_index(semantic_name, semantic_index,
364 shader->selector->gs_used_inputs) * 4 +
365 swizzle) * 256);
366 args[3] = uint->zero;
367 args[4] = uint->one; /* OFFEN */
368 args[5] = uint->zero; /* IDXEN */
369 args[6] = uint->one; /* GLC */
370 args[7] = uint->zero; /* SLC */
371 args[8] = uint->zero; /* TFE */
372
373 return LLVMBuildBitCast(gallivm->builder,
374 build_intrinsic(gallivm->builder,
375 "llvm.SI.buffer.load.dword.i32.i32",
376 i32, args, 9,
377 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
378 tgsi2llvmtype(bld_base, type), "");
379 }
380
381 static void declare_input_fs(
382 struct radeon_llvm_context *radeon_bld,
383 unsigned input_index,
384 const struct tgsi_full_declaration *decl)
385 {
386 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
387 struct si_shader_context *si_shader_ctx =
388 si_shader_context(&radeon_bld->soa.bld_base);
389 struct si_shader *shader = si_shader_ctx->shader;
390 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
391 struct gallivm_state *gallivm = base->gallivm;
392 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
393 LLVMValueRef main_fn = radeon_bld->main_fn;
394
395 LLVMValueRef interp_param;
396 const char * intr_name;
397
398 /* This value is:
399 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
400 * quad begins a new primitive. Bit 0 always needs
401 * to be unset)
402 * [32:16] ParamOffset
403 *
404 */
405 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
406 LLVMValueRef attr_number;
407
408 unsigned chan;
409
410 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
411 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
412 unsigned soa_index =
413 radeon_llvm_reg_index_soa(input_index, chan);
414 radeon_bld->inputs[soa_index] =
415 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
416
417 if (chan == 3)
418 /* RCP for fragcoord.w */
419 radeon_bld->inputs[soa_index] =
420 LLVMBuildFDiv(gallivm->builder,
421 lp_build_const_float(gallivm, 1.0f),
422 radeon_bld->inputs[soa_index],
423 "");
424 }
425 return;
426 }
427
428 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
429 LLVMValueRef face, is_face_positive;
430
431 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
432
433 is_face_positive = LLVMBuildFCmp(gallivm->builder,
434 LLVMRealUGT, face,
435 lp_build_const_float(gallivm, 0.0f),
436 "");
437
438 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
439 LLVMBuildSelect(gallivm->builder,
440 is_face_positive,
441 lp_build_const_float(gallivm, 1.0f),
442 lp_build_const_float(gallivm, 0.0f),
443 "");
444 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
445 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
446 lp_build_const_float(gallivm, 0.0f);
447 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
448 lp_build_const_float(gallivm, 1.0f);
449
450 return;
451 }
452
453 shader->ps_input_param_offset[input_index] = shader->nparam++;
454 attr_number = lp_build_const_int32(gallivm,
455 shader->ps_input_param_offset[input_index]);
456
457 switch (decl->Interp.Interpolate) {
458 case TGSI_INTERPOLATE_CONSTANT:
459 interp_param = 0;
460 break;
461 case TGSI_INTERPOLATE_LINEAR:
462 if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_SAMPLE)
463 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_SAMPLE);
464 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
465 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
466 else
467 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
468 break;
469 case TGSI_INTERPOLATE_COLOR:
470 if (si_shader_ctx->shader->key.ps.flatshade) {
471 interp_param = 0;
472 break;
473 }
474 /* fall through to perspective */
475 case TGSI_INTERPOLATE_PERSPECTIVE:
476 if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_SAMPLE)
477 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_SAMPLE);
478 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
479 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
480 else
481 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
482 break;
483 default:
484 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
485 return;
486 }
487
488 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
489
490 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
491 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
492 si_shader_ctx->shader->key.ps.color_two_side) {
493 LLVMValueRef args[4];
494 LLVMValueRef face, is_face_positive;
495 LLVMValueRef back_attr_number =
496 lp_build_const_int32(gallivm,
497 shader->ps_input_param_offset[input_index] + 1);
498
499 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
500
501 is_face_positive = LLVMBuildFCmp(gallivm->builder,
502 LLVMRealUGT, face,
503 lp_build_const_float(gallivm, 0.0f),
504 "");
505
506 args[2] = params;
507 args[3] = interp_param;
508 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
509 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
510 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
511 LLVMValueRef front, back;
512
513 args[0] = llvm_chan;
514 args[1] = attr_number;
515 front = build_intrinsic(gallivm->builder, intr_name,
516 input_type, args, args[3] ? 4 : 3,
517 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
518
519 args[1] = back_attr_number;
520 back = build_intrinsic(gallivm->builder, intr_name,
521 input_type, args, args[3] ? 4 : 3,
522 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
523
524 radeon_bld->inputs[soa_index] =
525 LLVMBuildSelect(gallivm->builder,
526 is_face_positive,
527 front,
528 back,
529 "");
530 }
531
532 shader->nparam++;
533 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
534 LLVMValueRef args[4];
535
536 args[0] = uint->zero;
537 args[1] = attr_number;
538 args[2] = params;
539 args[3] = interp_param;
540 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
541 build_intrinsic(gallivm->builder, intr_name,
542 input_type, args, args[3] ? 4 : 3,
543 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
544 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
545 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
546 lp_build_const_float(gallivm, 0.0f);
547 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
548 lp_build_const_float(gallivm, 1.0f);
549 } else {
550 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
551 LLVMValueRef args[4];
552 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
553 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
554 args[0] = llvm_chan;
555 args[1] = attr_number;
556 args[2] = params;
557 args[3] = interp_param;
558 radeon_bld->inputs[soa_index] =
559 build_intrinsic(gallivm->builder, intr_name,
560 input_type, args, args[3] ? 4 : 3,
561 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
562 }
563 }
564 }
565
566 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
567 {
568 struct gallivm_state *gallivm = &radeon_bld->gallivm;
569 LLVMValueRef value = LLVMGetParam(radeon_bld->main_fn,
570 SI_PARAM_ANCILLARY);
571 value = LLVMBuildLShr(gallivm->builder, value,
572 lp_build_const_int32(gallivm, 8), "");
573 value = LLVMBuildAnd(gallivm->builder, value,
574 lp_build_const_int32(gallivm, 0xf), "");
575 return value;
576 }
577
578 static LLVMValueRef load_const(LLVMBuilderRef builder, LLVMValueRef resource,
579 LLVMValueRef offset, LLVMTypeRef return_type)
580 {
581 LLVMValueRef args[2] = {resource, offset};
582
583 return build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
584 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
585 }
586
587 static void declare_system_value(
588 struct radeon_llvm_context * radeon_bld,
589 unsigned index,
590 const struct tgsi_full_declaration *decl)
591 {
592 struct si_shader_context *si_shader_ctx =
593 si_shader_context(&radeon_bld->soa.bld_base);
594 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
595 struct gallivm_state *gallivm = &radeon_bld->gallivm;
596 LLVMValueRef value = 0;
597
598 switch (decl->Semantic.Name) {
599 case TGSI_SEMANTIC_INSTANCEID:
600 value = LLVMGetParam(radeon_bld->main_fn,
601 si_shader_ctx->param_instance_id);
602 break;
603
604 case TGSI_SEMANTIC_VERTEXID:
605 value = LLVMGetParam(radeon_bld->main_fn,
606 si_shader_ctx->param_vertex_id);
607 break;
608
609 case TGSI_SEMANTIC_SAMPLEID:
610 value = get_sample_id(radeon_bld);
611 break;
612
613 case TGSI_SEMANTIC_SAMPLEPOS:
614 {
615 LLVMBuilderRef builder = gallivm->builder;
616 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
617 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
618 LLVMValueRef resource = build_indexed_load(si_shader_ctx, desc, buf_index);
619
620 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
621 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, get_sample_id(radeon_bld), 8);
622 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
623
624 LLVMValueRef pos[4] = {
625 load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
626 load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
627 lp_build_const_float(gallivm, 0),
628 lp_build_const_float(gallivm, 0)
629 };
630 value = lp_build_gather_values(gallivm, pos, 4);
631 break;
632 }
633
634 default:
635 assert(!"unknown system value");
636 return;
637 }
638
639 radeon_bld->system_values[index] = value;
640 }
641
642 static LLVMValueRef fetch_constant(
643 struct lp_build_tgsi_context * bld_base,
644 const struct tgsi_full_src_register *reg,
645 enum tgsi_opcode_type type,
646 unsigned swizzle)
647 {
648 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
649 struct lp_build_context * base = &bld_base->base;
650 const struct tgsi_ind_register *ireg = &reg->Indirect;
651 unsigned buf, idx;
652
653 LLVMValueRef addr;
654 LLVMValueRef result;
655
656 if (swizzle == LP_CHAN_ALL) {
657 unsigned chan;
658 LLVMValueRef values[4];
659 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
660 values[chan] = fetch_constant(bld_base, reg, type, chan);
661
662 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
663 }
664
665 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
666 idx = reg->Register.Index * 4 + swizzle;
667
668 if (!reg->Register.Indirect)
669 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
670
671 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
672 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
673 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
674 addr = lp_build_add(&bld_base->uint_bld, addr,
675 lp_build_const_int32(base->gallivm, idx * 4));
676
677 result = load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
678 addr, base->elem_type);
679
680 return bitcast(bld_base, type, result);
681 }
682
683 /* Initialize arguments for the shader export intrinsic */
684 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
685 LLVMValueRef *values,
686 unsigned target,
687 LLVMValueRef *args)
688 {
689 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
690 struct lp_build_context *uint =
691 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
692 struct lp_build_context *base = &bld_base->base;
693 unsigned compressed = 0;
694 unsigned chan;
695
696 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
697 int cbuf = target - V_008DFC_SQ_EXP_MRT;
698
699 if (cbuf >= 0 && cbuf < 8) {
700 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
701
702 if (compressed)
703 si_shader_ctx->shader->spi_shader_col_format |=
704 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
705 else
706 si_shader_ctx->shader->spi_shader_col_format |=
707 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
708
709 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
710 }
711 }
712
713 if (compressed) {
714 /* Pixel shader needs to pack output values before export */
715 for (chan = 0; chan < 2; chan++ ) {
716 args[0] = values[2 * chan];
717 args[1] = values[2 * chan + 1];
718 args[chan + 5] =
719 build_intrinsic(base->gallivm->builder,
720 "llvm.SI.packf16",
721 LLVMInt32TypeInContext(base->gallivm->context),
722 args, 2,
723 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
724 args[chan + 7] = args[chan + 5] =
725 LLVMBuildBitCast(base->gallivm->builder,
726 args[chan + 5],
727 LLVMFloatTypeInContext(base->gallivm->context),
728 "");
729 }
730
731 /* Set COMPR flag */
732 args[4] = uint->one;
733 } else {
734 for (chan = 0; chan < 4; chan++ )
735 /* +5 because the first output value will be
736 * the 6th argument to the intrinsic. */
737 args[chan + 5] = values[chan];
738
739 /* Clear COMPR flag */
740 args[4] = uint->zero;
741 }
742
743 /* XXX: This controls which components of the output
744 * registers actually get exported. (e.g bit 0 means export
745 * X component, bit 1 means export Y component, etc.) I'm
746 * hard coding this to 0xf for now. In the future, we might
747 * want to do something else. */
748 args[0] = lp_build_const_int32(base->gallivm, 0xf);
749
750 /* Specify whether the EXEC mask represents the valid mask */
751 args[1] = uint->zero;
752
753 /* Specify whether this is the last export */
754 args[2] = uint->zero;
755
756 /* Specify the target we are exporting */
757 args[3] = lp_build_const_int32(base->gallivm, target);
758
759 /* XXX: We probably need to keep track of the output
760 * values, so we know what we are passing to the next
761 * stage. */
762 }
763
764 /* Load from output pointers and initialize arguments for the shader export intrinsic */
765 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
766 LLVMValueRef *out_ptr,
767 unsigned target,
768 LLVMValueRef *args)
769 {
770 struct gallivm_state *gallivm = bld_base->base.gallivm;
771 LLVMValueRef values[4];
772 int i;
773
774 for (i = 0; i < 4; i++)
775 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
776
777 si_llvm_init_export_args(bld_base, values, target, args);
778 }
779
780 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
781 LLVMValueRef *out_ptr)
782 {
783 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
784 struct gallivm_state *gallivm = bld_base->base.gallivm;
785
786 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
787 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
788 SI_PARAM_ALPHA_REF);
789
790 LLVMValueRef alpha_pass =
791 lp_build_cmp(&bld_base->base,
792 si_shader_ctx->shader->key.ps.alpha_func,
793 LLVMBuildLoad(gallivm->builder, out_ptr[3], ""),
794 alpha_ref);
795 LLVMValueRef arg =
796 lp_build_select(&bld_base->base,
797 alpha_pass,
798 lp_build_const_float(gallivm, 1.0f),
799 lp_build_const_float(gallivm, -1.0f));
800
801 build_intrinsic(gallivm->builder,
802 "llvm.AMDGPU.kill",
803 LLVMVoidTypeInContext(gallivm->context),
804 &arg, 1, 0);
805 } else {
806 build_intrinsic(gallivm->builder,
807 "llvm.AMDGPU.kilp",
808 LLVMVoidTypeInContext(gallivm->context),
809 NULL, 0, 0);
810 }
811
812 si_shader_ctx->shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
813 }
814
815 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
816 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
817 {
818 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
819 struct si_shader *shader = si_shader_ctx->shader;
820 struct lp_build_context *base = &bld_base->base;
821 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
822 unsigned reg_index;
823 unsigned chan;
824 unsigned const_chan;
825 LLVMValueRef base_elt;
826 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
827 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
828 LLVMValueRef const_resource = build_indexed_load(si_shader_ctx, ptr, constbuf_index);
829
830 for (reg_index = 0; reg_index < 2; reg_index ++) {
831 LLVMValueRef *args = pos[2 + reg_index];
832
833 shader->clip_dist_write |= 0xf << (4 * reg_index);
834
835 args[5] =
836 args[6] =
837 args[7] =
838 args[8] = lp_build_const_float(base->gallivm, 0.0f);
839
840 /* Compute dot products of position and user clip plane vectors */
841 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
842 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
843 args[1] = lp_build_const_int32(base->gallivm,
844 ((reg_index * 4 + chan) * 4 +
845 const_chan) * 4);
846 base_elt = load_const(base->gallivm->builder, const_resource,
847 args[1], base->elem_type);
848 args[5 + chan] =
849 lp_build_add(base, args[5 + chan],
850 lp_build_mul(base, base_elt,
851 out_elts[const_chan]));
852 }
853 }
854
855 args[0] = lp_build_const_int32(base->gallivm, 0xf);
856 args[1] = uint->zero;
857 args[2] = uint->zero;
858 args[3] = lp_build_const_int32(base->gallivm,
859 V_008DFC_SQ_EXP_POS + 2 + reg_index);
860 args[4] = uint->zero;
861 }
862 }
863
864 static void si_dump_streamout(struct pipe_stream_output_info *so)
865 {
866 unsigned i;
867
868 if (so->num_outputs)
869 fprintf(stderr, "STREAMOUT\n");
870
871 for (i = 0; i < so->num_outputs; i++) {
872 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
873 so->output[i].start_component;
874 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
875 i, so->output[i].output_buffer,
876 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
877 so->output[i].register_index,
878 mask & 1 ? "x" : "",
879 mask & 2 ? "y" : "",
880 mask & 4 ? "z" : "",
881 mask & 8 ? "w" : "");
882 }
883 }
884
885 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
886 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
887 * or v4i32 (num_channels=3,4). */
888 static void build_tbuffer_store(struct si_shader_context *shader,
889 LLVMValueRef rsrc,
890 LLVMValueRef vdata,
891 unsigned num_channels,
892 LLVMValueRef vaddr,
893 LLVMValueRef soffset,
894 unsigned inst_offset,
895 unsigned dfmt,
896 unsigned nfmt,
897 unsigned offen,
898 unsigned idxen,
899 unsigned glc,
900 unsigned slc,
901 unsigned tfe)
902 {
903 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
904 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
905 LLVMValueRef args[] = {
906 rsrc,
907 vdata,
908 LLVMConstInt(i32, num_channels, 0),
909 vaddr,
910 soffset,
911 LLVMConstInt(i32, inst_offset, 0),
912 LLVMConstInt(i32, dfmt, 0),
913 LLVMConstInt(i32, nfmt, 0),
914 LLVMConstInt(i32, offen, 0),
915 LLVMConstInt(i32, idxen, 0),
916 LLVMConstInt(i32, glc, 0),
917 LLVMConstInt(i32, slc, 0),
918 LLVMConstInt(i32, tfe, 0)
919 };
920
921 /* The instruction offset field has 12 bits */
922 assert(offen || inst_offset < (1 << 12));
923
924 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
925 unsigned func = CLAMP(num_channels, 1, 3) - 1;
926 const char *types[] = {"i32", "v2i32", "v4i32"};
927 char name[256];
928 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
929
930 lp_build_intrinsic(gallivm->builder, name,
931 LLVMVoidTypeInContext(gallivm->context),
932 args, Elements(args));
933 }
934
935 static void build_streamout_store(struct si_shader_context *shader,
936 LLVMValueRef rsrc,
937 LLVMValueRef vdata,
938 unsigned num_channels,
939 LLVMValueRef vaddr,
940 LLVMValueRef soffset,
941 unsigned inst_offset)
942 {
943 static unsigned dfmt[] = {
944 V_008F0C_BUF_DATA_FORMAT_32,
945 V_008F0C_BUF_DATA_FORMAT_32_32,
946 V_008F0C_BUF_DATA_FORMAT_32_32_32,
947 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
948 };
949 assert(num_channels >= 1 && num_channels <= 4);
950
951 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
952 inst_offset, dfmt[num_channels-1],
953 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
954 }
955
956 /* On SI, the vertex shader is responsible for writing streamout data
957 * to buffers. */
958 static void si_llvm_emit_streamout(struct si_shader_context *shader,
959 struct si_shader_output_values *outputs,
960 unsigned noutput)
961 {
962 struct pipe_stream_output_info *so = &shader->shader->selector->so;
963 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
964 LLVMBuilderRef builder = gallivm->builder;
965 int i, j;
966 struct lp_build_if_state if_ctx;
967
968 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
969
970 LLVMValueRef so_param =
971 LLVMGetParam(shader->radeon_bld.main_fn,
972 shader->param_streamout_config);
973
974 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
975 LLVMValueRef so_vtx_count =
976 LLVMBuildAnd(builder,
977 LLVMBuildLShr(builder, so_param,
978 LLVMConstInt(i32, 16, 0), ""),
979 LLVMConstInt(i32, 127, 0), "");
980
981 LLVMValueRef tid = build_intrinsic(builder, "llvm.SI.tid", i32,
982 NULL, 0, LLVMReadNoneAttribute);
983
984 /* can_emit = tid < so_vtx_count; */
985 LLVMValueRef can_emit =
986 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
987
988 /* Emit the streamout code conditionally. This actually avoids
989 * out-of-bounds buffer access. The hw tells us via the SGPR
990 * (so_vtx_count) which threads are allowed to emit streamout data. */
991 lp_build_if(&if_ctx, gallivm, can_emit);
992 {
993 /* The buffer offset is computed as follows:
994 * ByteOffset = streamout_offset[buffer_id]*4 +
995 * (streamout_write_index + thread_id)*stride[buffer_id] +
996 * attrib_offset
997 */
998
999 LLVMValueRef so_write_index =
1000 LLVMGetParam(shader->radeon_bld.main_fn,
1001 shader->param_streamout_write_index);
1002
1003 /* Compute (streamout_write_index + thread_id). */
1004 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1005
1006 /* Compute the write offset for each enabled buffer. */
1007 LLVMValueRef so_write_offset[4] = {};
1008 for (i = 0; i < 4; i++) {
1009 if (!so->stride[i])
1010 continue;
1011
1012 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1013 shader->param_streamout_offset[i]);
1014 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1015
1016 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1017 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1018 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1019 }
1020
1021 /* Write streamout data. */
1022 for (i = 0; i < so->num_outputs; i++) {
1023 unsigned buf_idx = so->output[i].output_buffer;
1024 unsigned reg = so->output[i].register_index;
1025 unsigned start = so->output[i].start_component;
1026 unsigned num_comps = so->output[i].num_components;
1027 LLVMValueRef out[4];
1028
1029 assert(num_comps && num_comps <= 4);
1030 if (!num_comps || num_comps > 4)
1031 continue;
1032
1033 if (reg >= noutput)
1034 continue;
1035
1036 /* Load the output as int. */
1037 for (j = 0; j < num_comps; j++) {
1038 out[j] = LLVMBuildBitCast(builder,
1039 outputs[reg].values[start+j],
1040 i32, "");
1041 }
1042
1043 /* Pack the output. */
1044 LLVMValueRef vdata = NULL;
1045
1046 switch (num_comps) {
1047 case 1: /* as i32 */
1048 vdata = out[0];
1049 break;
1050 case 2: /* as v2i32 */
1051 case 3: /* as v4i32 (aligned to 4) */
1052 case 4: /* as v4i32 */
1053 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1054 for (j = 0; j < num_comps; j++) {
1055 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1056 LLVMConstInt(i32, j, 0), "");
1057 }
1058 break;
1059 }
1060
1061 build_streamout_store(shader, shader->so_buffers[buf_idx],
1062 vdata, num_comps,
1063 so_write_offset[buf_idx],
1064 LLVMConstInt(i32, 0, 0),
1065 so->output[i].dst_offset*4);
1066 }
1067 }
1068 lp_build_endif(&if_ctx);
1069 }
1070
1071
1072 /* Generate export instructions for hardware VS shader stage */
1073 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1074 struct si_shader_output_values *outputs,
1075 unsigned noutput)
1076 {
1077 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1078 struct si_shader * shader = si_shader_ctx->shader;
1079 struct lp_build_context * base = &bld_base->base;
1080 struct lp_build_context * uint =
1081 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1082 LLVMValueRef args[9];
1083 LLVMValueRef pos_args[4][9] = { { 0 } };
1084 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL;
1085 unsigned semantic_name, semantic_index;
1086 unsigned target;
1087 unsigned param_count = 0;
1088 unsigned pos_idx;
1089 int i;
1090
1091 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1092 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1093 }
1094
1095 for (i = 0; i < noutput; i++) {
1096 semantic_name = outputs[i].name;
1097 semantic_index = outputs[i].sid;
1098
1099 handle_semantic:
1100 /* Select the correct target */
1101 switch(semantic_name) {
1102 case TGSI_SEMANTIC_PSIZE:
1103 shader->vs_out_misc_write = true;
1104 shader->vs_out_point_size = true;
1105 psize_value = outputs[i].values[0];
1106 continue;
1107 case TGSI_SEMANTIC_EDGEFLAG:
1108 shader->vs_out_misc_write = true;
1109 shader->vs_out_edgeflag = true;
1110 edgeflag_value = outputs[i].values[0];
1111 continue;
1112 case TGSI_SEMANTIC_LAYER:
1113 shader->vs_out_misc_write = true;
1114 shader->vs_out_layer = true;
1115 layer_value = outputs[i].values[0];
1116 continue;
1117 case TGSI_SEMANTIC_POSITION:
1118 target = V_008DFC_SQ_EXP_POS;
1119 break;
1120 case TGSI_SEMANTIC_COLOR:
1121 case TGSI_SEMANTIC_BCOLOR:
1122 target = V_008DFC_SQ_EXP_PARAM + param_count;
1123 shader->vs_output_param_offset[i] = param_count;
1124 param_count++;
1125 break;
1126 case TGSI_SEMANTIC_CLIPDIST:
1127 shader->clip_dist_write |=
1128 0xf << (semantic_index * 4);
1129 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1130 break;
1131 case TGSI_SEMANTIC_CLIPVERTEX:
1132 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1133 continue;
1134 case TGSI_SEMANTIC_PRIMID:
1135 case TGSI_SEMANTIC_FOG:
1136 case TGSI_SEMANTIC_GENERIC:
1137 target = V_008DFC_SQ_EXP_PARAM + param_count;
1138 shader->vs_output_param_offset[i] = param_count;
1139 param_count++;
1140 break;
1141 default:
1142 target = 0;
1143 fprintf(stderr,
1144 "Warning: SI unhandled vs output type:%d\n",
1145 semantic_name);
1146 }
1147
1148 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1149
1150 if (target >= V_008DFC_SQ_EXP_POS &&
1151 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1152 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1153 args, sizeof(args));
1154 } else {
1155 lp_build_intrinsic(base->gallivm->builder,
1156 "llvm.SI.export",
1157 LLVMVoidTypeInContext(base->gallivm->context),
1158 args, 9);
1159 }
1160
1161 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1162 semantic_name = TGSI_SEMANTIC_GENERIC;
1163 goto handle_semantic;
1164 }
1165 }
1166
1167 /* We need to add the position output manually if it's missing. */
1168 if (!pos_args[0][0]) {
1169 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1170 pos_args[0][1] = uint->zero; /* EXEC mask */
1171 pos_args[0][2] = uint->zero; /* last export? */
1172 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1173 pos_args[0][4] = uint->zero; /* COMPR flag */
1174 pos_args[0][5] = base->zero; /* X */
1175 pos_args[0][6] = base->zero; /* Y */
1176 pos_args[0][7] = base->zero; /* Z */
1177 pos_args[0][8] = base->one; /* W */
1178 }
1179
1180 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1181 if (shader->vs_out_misc_write) {
1182 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1183 shader->vs_out_point_size |
1184 (shader->vs_out_edgeflag << 1) |
1185 (shader->vs_out_layer << 2));
1186 pos_args[1][1] = uint->zero; /* EXEC mask */
1187 pos_args[1][2] = uint->zero; /* last export? */
1188 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1189 pos_args[1][4] = uint->zero; /* COMPR flag */
1190 pos_args[1][5] = base->zero; /* X */
1191 pos_args[1][6] = base->zero; /* Y */
1192 pos_args[1][7] = base->zero; /* Z */
1193 pos_args[1][8] = base->zero; /* W */
1194
1195 if (shader->vs_out_point_size)
1196 pos_args[1][5] = psize_value;
1197
1198 if (shader->vs_out_edgeflag) {
1199 /* The output is a float, but the hw expects an integer
1200 * with the first bit containing the edge flag. */
1201 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1202 edgeflag_value,
1203 bld_base->uint_bld.elem_type, "");
1204 edgeflag_value = lp_build_min(&bld_base->int_bld,
1205 edgeflag_value,
1206 bld_base->int_bld.one);
1207
1208 /* The LLVM intrinsic expects a float. */
1209 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1210 edgeflag_value,
1211 base->elem_type, "");
1212 }
1213
1214 if (shader->vs_out_layer)
1215 pos_args[1][7] = layer_value;
1216 }
1217
1218 for (i = 0; i < 4; i++)
1219 if (pos_args[i][0])
1220 shader->nr_pos_exports++;
1221
1222 pos_idx = 0;
1223 for (i = 0; i < 4; i++) {
1224 if (!pos_args[i][0])
1225 continue;
1226
1227 /* Specify the target we are exporting */
1228 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1229
1230 if (pos_idx == shader->nr_pos_exports)
1231 /* Specify that this is the last export */
1232 pos_args[i][2] = uint->one;
1233
1234 lp_build_intrinsic(base->gallivm->builder,
1235 "llvm.SI.export",
1236 LLVMVoidTypeInContext(base->gallivm->context),
1237 pos_args[i], 9);
1238 }
1239 }
1240
1241 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1242 {
1243 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1244 struct gallivm_state *gallivm = bld_base->base.gallivm;
1245 struct si_shader *es = si_shader_ctx->shader;
1246 struct tgsi_shader_info *info = &es->selector->info;
1247 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1248 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1249 SI_PARAM_ES2GS_OFFSET);
1250 LLVMValueRef t_list_ptr;
1251 LLVMValueRef t_list;
1252 unsigned chan;
1253 int i;
1254
1255 /* Load the ESGS ring resource descriptor */
1256 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1257 SI_PARAM_RW_BUFFERS);
1258 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
1259 lp_build_const_int32(gallivm, SI_RING_ESGS));
1260
1261 for (i = 0; i < info->num_outputs; i++) {
1262 LLVMValueRef *out_ptr =
1263 si_shader_ctx->radeon_bld.soa.outputs[i];
1264 int param_index = get_param_index(info->output_semantic_name[i],
1265 info->output_semantic_index[i],
1266 es->key.vs.gs_used_inputs);
1267
1268 if (param_index < 0)
1269 continue;
1270
1271 for (chan = 0; chan < 4; chan++) {
1272 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1273 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1274
1275 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
1276 LLVMGetUndef(i32), soffset,
1277 (4 * param_index + chan) * 4,
1278 V_008F0C_BUF_DATA_FORMAT_32,
1279 V_008F0C_BUF_NUM_FORMAT_UINT,
1280 0, 0, 1, 1, 0);
1281 }
1282 }
1283 }
1284
1285 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
1286 {
1287 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1288 struct gallivm_state *gallivm = bld_base->base.gallivm;
1289 LLVMValueRef args[2];
1290
1291 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
1292 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1293 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1294 LLVMVoidTypeInContext(gallivm->context), args, 2,
1295 LLVMNoUnwindAttribute);
1296 }
1297
1298 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
1299 {
1300 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1301 struct gallivm_state *gallivm = bld_base->base.gallivm;
1302 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
1303 struct si_shader_output_values *outputs = NULL;
1304 int i,j;
1305
1306 outputs = MALLOC(info->num_outputs * sizeof(outputs[0]));
1307
1308 for (i = 0; i < info->num_outputs; i++) {
1309 outputs[i].name = info->output_semantic_name[i];
1310 outputs[i].sid = info->output_semantic_index[i];
1311
1312 for (j = 0; j < 4; j++)
1313 outputs[i].values[j] =
1314 LLVMBuildLoad(gallivm->builder,
1315 si_shader_ctx->radeon_bld.soa.outputs[i][j],
1316 "");
1317 }
1318
1319 si_llvm_export_vs(bld_base, outputs, info->num_outputs);
1320 FREE(outputs);
1321 }
1322
1323 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
1324 {
1325 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1326 struct si_shader * shader = si_shader_ctx->shader;
1327 struct lp_build_context * base = &bld_base->base;
1328 struct lp_build_context * uint = &bld_base->uint_bld;
1329 struct tgsi_shader_info *info = &shader->selector->info;
1330 LLVMValueRef args[9];
1331 LLVMValueRef last_args[9] = { 0 };
1332 int depth_index = -1, stencil_index = -1, samplemask_index = -1;
1333 int i;
1334
1335 for (i = 0; i < info->num_outputs; i++) {
1336 unsigned semantic_name = info->output_semantic_name[i];
1337 unsigned semantic_index = info->output_semantic_index[i];
1338 unsigned target;
1339
1340 /* Select the correct target */
1341 switch (semantic_name) {
1342 case TGSI_SEMANTIC_POSITION:
1343 depth_index = i;
1344 continue;
1345 case TGSI_SEMANTIC_STENCIL:
1346 stencil_index = i;
1347 continue;
1348 case TGSI_SEMANTIC_SAMPLEMASK:
1349 samplemask_index = i;
1350 continue;
1351 case TGSI_SEMANTIC_COLOR:
1352 target = V_008DFC_SQ_EXP_MRT + semantic_index;
1353 if (si_shader_ctx->shader->key.ps.alpha_to_one)
1354 LLVMBuildStore(bld_base->base.gallivm->builder,
1355 bld_base->base.one,
1356 si_shader_ctx->radeon_bld.soa.outputs[i][3]);
1357
1358 if (semantic_index == 0 &&
1359 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
1360 si_alpha_test(bld_base,
1361 si_shader_ctx->radeon_bld.soa.outputs[i]);
1362 break;
1363 default:
1364 target = 0;
1365 fprintf(stderr,
1366 "Warning: SI unhandled fs output type:%d\n",
1367 semantic_name);
1368 }
1369
1370 si_llvm_init_export_args_load(bld_base,
1371 si_shader_ctx->radeon_bld.soa.outputs[i],
1372 target, args);
1373
1374 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1375 /* If there is an export instruction waiting to be emitted, do so now. */
1376 if (last_args[0]) {
1377 lp_build_intrinsic(base->gallivm->builder,
1378 "llvm.SI.export",
1379 LLVMVoidTypeInContext(base->gallivm->context),
1380 last_args, 9);
1381 }
1382
1383 /* This instruction will be emitted at the end of the shader. */
1384 memcpy(last_args, args, sizeof(args));
1385
1386 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
1387 if (shader->selector->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1388 semantic_index == 0 &&
1389 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
1390 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
1391 si_llvm_init_export_args_load(bld_base,
1392 si_shader_ctx->radeon_bld.soa.outputs[i],
1393 V_008DFC_SQ_EXP_MRT + c, args);
1394 lp_build_intrinsic(base->gallivm->builder,
1395 "llvm.SI.export",
1396 LLVMVoidTypeInContext(base->gallivm->context),
1397 args, 9);
1398 }
1399 }
1400 } else {
1401 lp_build_intrinsic(base->gallivm->builder,
1402 "llvm.SI.export",
1403 LLVMVoidTypeInContext(base->gallivm->context),
1404 args, 9);
1405 }
1406 }
1407
1408 if (depth_index >= 0 || stencil_index >= 0 || samplemask_index >= 0) {
1409 LLVMValueRef out_ptr;
1410 unsigned mask = 0;
1411
1412 /* Specify the target we are exporting */
1413 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
1414
1415 args[5] = base->zero; /* R, depth */
1416 args[6] = base->zero; /* G, stencil test value[0:7], stencil op value[8:15] */
1417 args[7] = base->zero; /* B, sample mask */
1418 args[8] = base->zero; /* A, alpha to mask */
1419
1420 if (depth_index >= 0) {
1421 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
1422 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1423 mask |= 0x1;
1424 si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1425 }
1426
1427 if (stencil_index >= 0) {
1428 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
1429 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1430 /* Only setting the stencil component bit (0x2) here
1431 * breaks some stencil piglit tests
1432 */
1433 mask |= 0x3;
1434 si_shader_ctx->shader->db_shader_control |=
1435 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
1436 }
1437
1438 if (samplemask_index >= 0) {
1439 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[samplemask_index][0];
1440 args[7] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1441 mask |= 0xf; /* Set all components. */
1442 si_shader_ctx->shader->db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(1);
1443 }
1444
1445 if (samplemask_index >= 0)
1446 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
1447 else if (stencil_index >= 0)
1448 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
1449 else
1450 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
1451
1452 /* Specify which components to enable */
1453 args[0] = lp_build_const_int32(base->gallivm, mask);
1454
1455 args[1] =
1456 args[2] =
1457 args[4] = uint->zero;
1458
1459 if (last_args[0])
1460 lp_build_intrinsic(base->gallivm->builder,
1461 "llvm.SI.export",
1462 LLVMVoidTypeInContext(base->gallivm->context),
1463 args, 9);
1464 else
1465 memcpy(last_args, args, sizeof(args));
1466 }
1467
1468 if (!last_args[0]) {
1469 /* Specify which components to enable */
1470 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
1471
1472 /* Specify the target we are exporting */
1473 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
1474
1475 /* Set COMPR flag to zero to export data as 32-bit */
1476 last_args[4] = uint->zero;
1477
1478 /* dummy bits */
1479 last_args[5]= uint->zero;
1480 last_args[6]= uint->zero;
1481 last_args[7]= uint->zero;
1482 last_args[8]= uint->zero;
1483 }
1484
1485 /* Specify whether the EXEC mask represents the valid mask */
1486 last_args[1] = uint->one;
1487
1488 /* Specify that this is the last export */
1489 last_args[2] = lp_build_const_int32(base->gallivm, 1);
1490
1491 lp_build_intrinsic(base->gallivm->builder,
1492 "llvm.SI.export",
1493 LLVMVoidTypeInContext(base->gallivm->context),
1494 last_args, 9);
1495 }
1496
1497 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1498 struct lp_build_tgsi_context * bld_base,
1499 struct lp_build_emit_data * emit_data);
1500
1501 static bool tgsi_is_shadow_sampler(unsigned target)
1502 {
1503 return target == TGSI_TEXTURE_SHADOW1D ||
1504 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1505 target == TGSI_TEXTURE_SHADOW2D ||
1506 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1507 target == TGSI_TEXTURE_SHADOWCUBE ||
1508 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
1509 target == TGSI_TEXTURE_SHADOWRECT;
1510 }
1511
1512 static const struct lp_build_tgsi_action tex_action;
1513
1514 static void tex_fetch_args(
1515 struct lp_build_tgsi_context * bld_base,
1516 struct lp_build_emit_data * emit_data)
1517 {
1518 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1519 struct gallivm_state *gallivm = bld_base->base.gallivm;
1520 const struct tgsi_full_instruction * inst = emit_data->inst;
1521 unsigned opcode = inst->Instruction.Opcode;
1522 unsigned target = inst->Texture.Texture;
1523 LLVMValueRef coords[4];
1524 LLVMValueRef address[16];
1525 int ref_pos;
1526 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
1527 unsigned count = 0;
1528 unsigned chan;
1529 unsigned sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1530 unsigned sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
1531 bool has_offset = HAVE_LLVM >= 0x0305 ? inst->Texture.NumOffsets > 0 : false;
1532
1533 if (target == TGSI_TEXTURE_BUFFER) {
1534 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
1535 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
1536 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
1537 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
1538
1539 /* Bitcast and truncate v8i32 to v16i8. */
1540 LLVMValueRef res = si_shader_ctx->resources[sampler_index];
1541 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
1542 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.zero, "");
1543 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
1544
1545 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
1546 emit_data->args[0] = res;
1547 emit_data->args[1] = bld_base->uint_bld.zero;
1548 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
1549 emit_data->arg_count = 3;
1550 return;
1551 }
1552
1553 /* Fetch and project texture coordinates */
1554 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1555 for (chan = 0; chan < 3; chan++ ) {
1556 coords[chan] = lp_build_emit_fetch(bld_base,
1557 emit_data->inst, 0,
1558 chan);
1559 if (opcode == TGSI_OPCODE_TXP)
1560 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1561 TGSI_OPCODE_DIV,
1562 coords[chan],
1563 coords[3]);
1564 }
1565
1566 if (opcode == TGSI_OPCODE_TXP)
1567 coords[3] = bld_base->base.one;
1568
1569 /* Pack offsets. */
1570 if (has_offset && opcode != TGSI_OPCODE_TXF) {
1571 /* The offsets are six-bit signed integers packed like this:
1572 * X=[5:0], Y=[13:8], and Z=[21:16].
1573 */
1574 LLVMValueRef offset[3], pack;
1575
1576 assert(inst->Texture.NumOffsets == 1);
1577
1578 for (chan = 0; chan < 3; chan++) {
1579 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
1580 emit_data->inst, 0, chan);
1581 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
1582 lp_build_const_int32(gallivm, 0x3f), "");
1583 if (chan)
1584 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
1585 lp_build_const_int32(gallivm, chan*8), "");
1586 }
1587
1588 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
1589 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
1590 address[count++] = pack;
1591 }
1592
1593 /* Pack LOD bias value */
1594 if (opcode == TGSI_OPCODE_TXB)
1595 address[count++] = coords[3];
1596 if (opcode == TGSI_OPCODE_TXB2)
1597 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1598
1599 /* Pack depth comparison value */
1600 if (tgsi_is_shadow_sampler(target) && opcode != TGSI_OPCODE_LODQ) {
1601 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1602 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1603 } else {
1604 assert(ref_pos >= 0);
1605 address[count++] = coords[ref_pos];
1606 }
1607 }
1608
1609 if (target == TGSI_TEXTURE_CUBE ||
1610 target == TGSI_TEXTURE_CUBE_ARRAY ||
1611 target == TGSI_TEXTURE_SHADOWCUBE ||
1612 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1613 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
1614
1615 /* Pack user derivatives */
1616 if (opcode == TGSI_OPCODE_TXD) {
1617 int num_deriv_channels, param;
1618
1619 switch (target) {
1620 case TGSI_TEXTURE_3D:
1621 num_deriv_channels = 3;
1622 break;
1623 case TGSI_TEXTURE_2D:
1624 case TGSI_TEXTURE_SHADOW2D:
1625 case TGSI_TEXTURE_RECT:
1626 case TGSI_TEXTURE_SHADOWRECT:
1627 case TGSI_TEXTURE_2D_ARRAY:
1628 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1629 case TGSI_TEXTURE_CUBE:
1630 case TGSI_TEXTURE_SHADOWCUBE:
1631 case TGSI_TEXTURE_CUBE_ARRAY:
1632 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1633 num_deriv_channels = 2;
1634 break;
1635 case TGSI_TEXTURE_1D:
1636 case TGSI_TEXTURE_SHADOW1D:
1637 case TGSI_TEXTURE_1D_ARRAY:
1638 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1639 num_deriv_channels = 1;
1640 break;
1641 default:
1642 assert(0); /* no other targets are valid here */
1643 }
1644
1645 for (param = 1; param <= 2; param++)
1646 for (chan = 0; chan < num_deriv_channels; chan++)
1647 address[count++] = lp_build_emit_fetch(bld_base, inst, param, chan);
1648 }
1649
1650 /* Pack texture coordinates */
1651 address[count++] = coords[0];
1652 if (num_coords > 1)
1653 address[count++] = coords[1];
1654 if (num_coords > 2)
1655 address[count++] = coords[2];
1656
1657 /* Pack LOD or sample index */
1658 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1659 address[count++] = coords[3];
1660 else if (opcode == TGSI_OPCODE_TXL2)
1661 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1662
1663 if (count > 16) {
1664 assert(!"Cannot handle more than 16 texture address parameters");
1665 count = 16;
1666 }
1667
1668 for (chan = 0; chan < count; chan++ ) {
1669 address[chan] = LLVMBuildBitCast(gallivm->builder,
1670 address[chan],
1671 LLVMInt32TypeInContext(gallivm->context),
1672 "");
1673 }
1674
1675 /* Adjust the sample index according to FMASK.
1676 *
1677 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1678 * which is the identity mapping. Each nibble says which physical sample
1679 * should be fetched to get that sample.
1680 *
1681 * For example, 0x11111100 means there are only 2 samples stored and
1682 * the second sample covers 3/4 of the pixel. When reading samples 0
1683 * and 1, return physical sample 0 (determined by the first two 0s
1684 * in FMASK), otherwise return physical sample 1.
1685 *
1686 * The sample index should be adjusted as follows:
1687 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1688 */
1689 if (target == TGSI_TEXTURE_2D_MSAA ||
1690 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1691 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1692 struct lp_build_emit_data txf_emit_data = *emit_data;
1693 LLVMValueRef txf_address[4];
1694 unsigned txf_count = count;
1695 struct tgsi_full_instruction inst = {};
1696
1697 memcpy(txf_address, address, sizeof(txf_address));
1698
1699 if (target == TGSI_TEXTURE_2D_MSAA) {
1700 txf_address[2] = bld_base->uint_bld.zero;
1701 }
1702 txf_address[3] = bld_base->uint_bld.zero;
1703
1704 /* Pad to a power-of-two size. */
1705 while (txf_count < util_next_power_of_two(txf_count))
1706 txf_address[txf_count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1707
1708 /* Read FMASK using TXF. */
1709 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
1710 inst.Texture.Texture = target == TGSI_TEXTURE_2D_MSAA ? TGSI_TEXTURE_2D : TGSI_TEXTURE_2D_ARRAY;
1711 txf_emit_data.inst = &inst;
1712 txf_emit_data.chan = 0;
1713 txf_emit_data.dst_type = LLVMVectorType(
1714 LLVMInt32TypeInContext(gallivm->context), 4);
1715 txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
1716 txf_emit_data.args[1] = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
1717 txf_emit_data.args[2] = lp_build_const_int32(gallivm, inst.Texture.Texture);
1718 txf_emit_data.arg_count = 3;
1719
1720 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
1721
1722 /* Initialize some constants. */
1723 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
1724 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
1725
1726 /* Apply the formula. */
1727 LLVMValueRef fmask =
1728 LLVMBuildExtractElement(gallivm->builder,
1729 txf_emit_data.output[0],
1730 uint_bld->zero, "");
1731
1732 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1733
1734 LLVMValueRef sample_index4 =
1735 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1736
1737 LLVMValueRef shifted_fmask =
1738 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1739
1740 LLVMValueRef final_sample =
1741 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1742
1743 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1744 * resource descriptor is 0 (invalid),
1745 */
1746 LLVMValueRef fmask_desc =
1747 LLVMBuildBitCast(gallivm->builder,
1748 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index],
1749 LLVMVectorType(uint_bld->elem_type, 8), "");
1750
1751 LLVMValueRef fmask_word1 =
1752 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1753 uint_bld->one, "");
1754
1755 LLVMValueRef word1_is_nonzero =
1756 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1757 fmask_word1, uint_bld->zero, "");
1758
1759 /* Replace the MSAA sample index. */
1760 address[sample_chan] =
1761 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1762 final_sample, address[sample_chan], "");
1763 }
1764
1765 /* Resource */
1766 emit_data->args[1] = si_shader_ctx->resources[sampler_index];
1767
1768 if (opcode == TGSI_OPCODE_TXF) {
1769 /* add tex offsets */
1770 if (inst->Texture.NumOffsets) {
1771 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1772 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
1773 const struct tgsi_texture_offset * off = inst->TexOffsets;
1774
1775 assert(inst->Texture.NumOffsets == 1);
1776
1777 switch (target) {
1778 case TGSI_TEXTURE_3D:
1779 address[2] = lp_build_add(uint_bld, address[2],
1780 bld->immediates[off->Index][off->SwizzleZ]);
1781 /* fall through */
1782 case TGSI_TEXTURE_2D:
1783 case TGSI_TEXTURE_SHADOW2D:
1784 case TGSI_TEXTURE_RECT:
1785 case TGSI_TEXTURE_SHADOWRECT:
1786 case TGSI_TEXTURE_2D_ARRAY:
1787 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1788 address[1] =
1789 lp_build_add(uint_bld, address[1],
1790 bld->immediates[off->Index][off->SwizzleY]);
1791 /* fall through */
1792 case TGSI_TEXTURE_1D:
1793 case TGSI_TEXTURE_SHADOW1D:
1794 case TGSI_TEXTURE_1D_ARRAY:
1795 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1796 address[0] =
1797 lp_build_add(uint_bld, address[0],
1798 bld->immediates[off->Index][off->SwizzleX]);
1799 break;
1800 /* texture offsets do not apply to other texture targets */
1801 }
1802 }
1803
1804 emit_data->args[2] = lp_build_const_int32(gallivm, target);
1805 emit_data->arg_count = 3;
1806
1807 emit_data->dst_type = LLVMVectorType(
1808 LLVMInt32TypeInContext(gallivm->context),
1809 4);
1810 } else if (opcode == TGSI_OPCODE_TG4 ||
1811 opcode == TGSI_OPCODE_LODQ ||
1812 has_offset) {
1813 unsigned is_array = target == TGSI_TEXTURE_1D_ARRAY ||
1814 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1815 target == TGSI_TEXTURE_2D_ARRAY ||
1816 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1817 target == TGSI_TEXTURE_CUBE_ARRAY ||
1818 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY;
1819 unsigned is_rect = target == TGSI_TEXTURE_RECT;
1820 unsigned dmask = 0xf;
1821
1822 if (opcode == TGSI_OPCODE_TG4) {
1823 unsigned gather_comp = 0;
1824
1825 /* DMASK was repurposed for GATHER4. 4 components are always
1826 * returned and DMASK works like a swizzle - it selects
1827 * the component to fetch. The only valid DMASK values are
1828 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1829 * (red,red,red,red) etc.) The ISA document doesn't mention
1830 * this.
1831 */
1832
1833 /* Get the component index from src1.x for Gather4. */
1834 if (!tgsi_is_shadow_sampler(target)) {
1835 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
1836 LLVMValueRef comp_imm;
1837 struct tgsi_src_register src1 = inst->Src[1].Register;
1838
1839 assert(src1.File == TGSI_FILE_IMMEDIATE);
1840
1841 comp_imm = imms[src1.Index][src1.SwizzleX];
1842 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1843 gather_comp = CLAMP(gather_comp, 0, 3);
1844 }
1845
1846 dmask = 1 << gather_comp;
1847 }
1848
1849 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1850 emit_data->args[3] = lp_build_const_int32(gallivm, dmask);
1851 emit_data->args[4] = lp_build_const_int32(gallivm, is_rect); /* unorm */
1852 emit_data->args[5] = lp_build_const_int32(gallivm, 0); /* r128 */
1853 emit_data->args[6] = lp_build_const_int32(gallivm, is_array); /* da */
1854 emit_data->args[7] = lp_build_const_int32(gallivm, 0); /* glc */
1855 emit_data->args[8] = lp_build_const_int32(gallivm, 0); /* slc */
1856 emit_data->args[9] = lp_build_const_int32(gallivm, 0); /* tfe */
1857 emit_data->args[10] = lp_build_const_int32(gallivm, 0); /* lwe */
1858
1859 emit_data->arg_count = 11;
1860
1861 emit_data->dst_type = LLVMVectorType(
1862 LLVMFloatTypeInContext(gallivm->context),
1863 4);
1864 } else {
1865 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1866 emit_data->args[3] = lp_build_const_int32(gallivm, target);
1867 emit_data->arg_count = 4;
1868
1869 emit_data->dst_type = LLVMVectorType(
1870 LLVMFloatTypeInContext(gallivm->context),
1871 4);
1872 }
1873
1874 /* The fetch opcode has been converted to a 2D array fetch.
1875 * This simplifies the LLVM backend. */
1876 if (target == TGSI_TEXTURE_CUBE_ARRAY)
1877 target = TGSI_TEXTURE_2D_ARRAY;
1878 else if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1879 target = TGSI_TEXTURE_SHADOW2D_ARRAY;
1880
1881 /* Pad to power of two vector */
1882 while (count < util_next_power_of_two(count))
1883 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1884
1885 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
1886 }
1887
1888 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1889 struct lp_build_tgsi_context * bld_base,
1890 struct lp_build_emit_data * emit_data)
1891 {
1892 struct lp_build_context * base = &bld_base->base;
1893 unsigned opcode = emit_data->inst->Instruction.Opcode;
1894 unsigned target = emit_data->inst->Texture.Texture;
1895 char intr_name[127];
1896 bool has_offset = HAVE_LLVM >= 0x0305 ?
1897 emit_data->inst->Texture.NumOffsets > 0 : false;
1898
1899 if (target == TGSI_TEXTURE_BUFFER) {
1900 emit_data->output[emit_data->chan] = build_intrinsic(
1901 base->gallivm->builder,
1902 "llvm.SI.vs.load.input", emit_data->dst_type,
1903 emit_data->args, emit_data->arg_count,
1904 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1905 return;
1906 }
1907
1908 if (opcode == TGSI_OPCODE_TG4 ||
1909 opcode == TGSI_OPCODE_LODQ ||
1910 (opcode != TGSI_OPCODE_TXF && has_offset)) {
1911 bool is_shadow = tgsi_is_shadow_sampler(target);
1912 const char *name = "llvm.SI.image.sample";
1913 const char *infix = "";
1914
1915 switch (opcode) {
1916 case TGSI_OPCODE_TEX:
1917 case TGSI_OPCODE_TEX2:
1918 case TGSI_OPCODE_TXP:
1919 break;
1920 case TGSI_OPCODE_TXB:
1921 case TGSI_OPCODE_TXB2:
1922 infix = ".b";
1923 break;
1924 case TGSI_OPCODE_TXL:
1925 case TGSI_OPCODE_TXL2:
1926 infix = ".l";
1927 break;
1928 case TGSI_OPCODE_TXD:
1929 infix = ".d";
1930 break;
1931 case TGSI_OPCODE_TG4:
1932 name = "llvm.SI.gather4";
1933 break;
1934 case TGSI_OPCODE_LODQ:
1935 name = "llvm.SI.getlod";
1936 is_shadow = false;
1937 has_offset = false;
1938 break;
1939 default:
1940 assert(0);
1941 return;
1942 }
1943
1944 /* Add the type and suffixes .c, .o if needed. */
1945 sprintf(intr_name, "%s%s%s%s.v%ui32", name,
1946 is_shadow ? ".c" : "", infix, has_offset ? ".o" : "",
1947 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
1948
1949 emit_data->output[emit_data->chan] = build_intrinsic(
1950 base->gallivm->builder, intr_name, emit_data->dst_type,
1951 emit_data->args, emit_data->arg_count,
1952 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1953 } else {
1954 LLVMTypeRef i8, v16i8, v32i8;
1955 const char *name;
1956
1957 switch (opcode) {
1958 case TGSI_OPCODE_TEX:
1959 case TGSI_OPCODE_TEX2:
1960 case TGSI_OPCODE_TXP:
1961 name = "llvm.SI.sample";
1962 break;
1963 case TGSI_OPCODE_TXB:
1964 case TGSI_OPCODE_TXB2:
1965 name = "llvm.SI.sampleb";
1966 break;
1967 case TGSI_OPCODE_TXD:
1968 name = "llvm.SI.sampled";
1969 break;
1970 case TGSI_OPCODE_TXF:
1971 name = "llvm.SI.imageload";
1972 break;
1973 case TGSI_OPCODE_TXL:
1974 case TGSI_OPCODE_TXL2:
1975 name = "llvm.SI.samplel";
1976 break;
1977 default:
1978 assert(0);
1979 return;
1980 }
1981
1982 i8 = LLVMInt8TypeInContext(base->gallivm->context);
1983 v16i8 = LLVMVectorType(i8, 16);
1984 v32i8 = LLVMVectorType(i8, 32);
1985
1986 emit_data->args[1] = LLVMBuildBitCast(base->gallivm->builder,
1987 emit_data->args[1], v32i8, "");
1988 if (opcode != TGSI_OPCODE_TXF) {
1989 emit_data->args[2] = LLVMBuildBitCast(base->gallivm->builder,
1990 emit_data->args[2], v16i8, "");
1991 }
1992
1993 sprintf(intr_name, "%s.v%ui32", name,
1994 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
1995
1996 emit_data->output[emit_data->chan] = build_intrinsic(
1997 base->gallivm->builder, intr_name, emit_data->dst_type,
1998 emit_data->args, emit_data->arg_count,
1999 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2000 }
2001 }
2002
2003 static void txq_fetch_args(
2004 struct lp_build_tgsi_context * bld_base,
2005 struct lp_build_emit_data * emit_data)
2006 {
2007 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2008 const struct tgsi_full_instruction *inst = emit_data->inst;
2009 struct gallivm_state *gallivm = bld_base->base.gallivm;
2010 unsigned target = inst->Texture.Texture;
2011
2012 if (target == TGSI_TEXTURE_BUFFER) {
2013 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2014 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2015
2016 /* Read the size from the buffer descriptor directly. */
2017 LLVMValueRef size = si_shader_ctx->resources[inst->Src[1].Register.Index];
2018 size = LLVMBuildBitCast(gallivm->builder, size, v8i32, "");
2019 size = LLVMBuildExtractElement(gallivm->builder, size,
2020 lp_build_const_int32(gallivm, 2), "");
2021 emit_data->args[0] = size;
2022 return;
2023 }
2024
2025 /* Mip level */
2026 emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2027
2028 /* Resource */
2029 emit_data->args[1] = si_shader_ctx->resources[inst->Src[1].Register.Index];
2030
2031 /* Texture target */
2032 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2033 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2034 target = TGSI_TEXTURE_2D_ARRAY;
2035
2036 emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
2037 target);
2038
2039 emit_data->arg_count = 3;
2040
2041 emit_data->dst_type = LLVMVectorType(
2042 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
2043 4);
2044 }
2045
2046 static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
2047 struct lp_build_tgsi_context * bld_base,
2048 struct lp_build_emit_data * emit_data)
2049 {
2050 unsigned target = emit_data->inst->Texture.Texture;
2051
2052 if (target == TGSI_TEXTURE_BUFFER) {
2053 /* Just return the buffer size. */
2054 emit_data->output[emit_data->chan] = emit_data->args[0];
2055 return;
2056 }
2057
2058 build_tgsi_intrinsic_nomem(action, bld_base, emit_data);
2059
2060 /* Divide the number of layers by 6 to get the number of cubes. */
2061 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2062 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2063 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2064 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2065 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2066
2067 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2068 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2069 z = LLVMBuildSDiv(builder, z, six, "");
2070
2071 emit_data->output[emit_data->chan] =
2072 LLVMBuildInsertElement(builder, v4, z, two, "");
2073 }
2074 }
2075
2076 static void si_llvm_emit_ddxy(
2077 const struct lp_build_tgsi_action * action,
2078 struct lp_build_tgsi_context * bld_base,
2079 struct lp_build_emit_data * emit_data)
2080 {
2081 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2082 struct gallivm_state *gallivm = bld_base->base.gallivm;
2083 struct lp_build_context * base = &bld_base->base;
2084 const struct tgsi_full_instruction *inst = emit_data->inst;
2085 unsigned opcode = inst->Instruction.Opcode;
2086 LLVMValueRef indices[2];
2087 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2088 LLVMValueRef tl, trbl, result[4];
2089 LLVMTypeRef i32;
2090 unsigned swizzle[4];
2091 unsigned c;
2092
2093 i32 = LLVMInt32TypeInContext(gallivm->context);
2094
2095 indices[0] = bld_base->uint_bld.zero;
2096 indices[1] = build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2097 NULL, 0, LLVMReadNoneAttribute);
2098 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2099 indices, 2, "");
2100
2101 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2102 lp_build_const_int32(gallivm, 0xfffffffc), "");
2103 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2104 indices, 2, "");
2105
2106 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
2107 lp_build_const_int32(gallivm,
2108 opcode == TGSI_OPCODE_DDX ? 1 : 2),
2109 "");
2110 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2111 indices, 2, "");
2112
2113 for (c = 0; c < 4; ++c) {
2114 unsigned i;
2115
2116 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
2117 for (i = 0; i < c; ++i) {
2118 if (swizzle[i] == swizzle[c]) {
2119 result[c] = result[i];
2120 break;
2121 }
2122 }
2123 if (i != c)
2124 continue;
2125
2126 LLVMBuildStore(gallivm->builder,
2127 LLVMBuildBitCast(gallivm->builder,
2128 lp_build_emit_fetch(bld_base, inst, 0, c),
2129 i32, ""),
2130 store_ptr);
2131
2132 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
2133 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
2134
2135 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
2136 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
2137
2138 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
2139 }
2140
2141 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
2142 }
2143
2144 /* Emit one vertex from the geometry shader */
2145 static void si_llvm_emit_vertex(
2146 const struct lp_build_tgsi_action *action,
2147 struct lp_build_tgsi_context *bld_base,
2148 struct lp_build_emit_data *emit_data)
2149 {
2150 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2151 struct lp_build_context *uint = &bld_base->uint_bld;
2152 struct si_shader *shader = si_shader_ctx->shader;
2153 struct tgsi_shader_info *info = &shader->selector->info;
2154 struct gallivm_state *gallivm = bld_base->base.gallivm;
2155 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2156 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2157 SI_PARAM_GS2VS_OFFSET);
2158 LLVMValueRef gs_next_vertex;
2159 LLVMValueRef can_emit, kill;
2160 LLVMValueRef t_list_ptr;
2161 LLVMValueRef t_list;
2162 LLVMValueRef args[2];
2163 unsigned chan;
2164 int i;
2165
2166 /* Load the GSVS ring resource descriptor */
2167 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2168 SI_PARAM_RW_BUFFERS);
2169 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
2170 lp_build_const_int32(gallivm, SI_RING_GSVS));
2171
2172 /* Write vertex attribute values to GSVS ring */
2173 gs_next_vertex = LLVMBuildLoad(gallivm->builder, si_shader_ctx->gs_next_vertex, "");
2174
2175 /* If this thread has already emitted the declared maximum number of
2176 * vertices, kill it: excessive vertex emissions are not supposed to
2177 * have any effect, and GS threads have no externally observable
2178 * effects other than emitting vertices.
2179 */
2180 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
2181 lp_build_const_int32(gallivm,
2182 shader->selector->gs_max_out_vertices), "");
2183 kill = lp_build_select(&bld_base->base, can_emit,
2184 lp_build_const_float(gallivm, 1.0f),
2185 lp_build_const_float(gallivm, -1.0f));
2186 build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2187 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
2188
2189 for (i = 0; i < info->num_outputs; i++) {
2190 LLVMValueRef *out_ptr =
2191 si_shader_ctx->radeon_bld.soa.outputs[i];
2192
2193 for (chan = 0; chan < 4; chan++) {
2194 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2195 LLVMValueRef voffset =
2196 lp_build_const_int32(gallivm, (i * 4 + chan) *
2197 shader->selector->gs_max_out_vertices);
2198
2199 voffset = lp_build_add(uint, voffset, gs_next_vertex);
2200 voffset = lp_build_mul_imm(uint, voffset, 4);
2201
2202 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2203
2204 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
2205 voffset, soffset, 0,
2206 V_008F0C_BUF_DATA_FORMAT_32,
2207 V_008F0C_BUF_NUM_FORMAT_UINT,
2208 1, 0, 1, 1, 0);
2209 }
2210 }
2211 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
2212 lp_build_const_int32(gallivm, 1));
2213 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex);
2214
2215 /* Signal vertex emission */
2216 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS);
2217 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2218 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2219 LLVMVoidTypeInContext(gallivm->context), args, 2,
2220 LLVMNoUnwindAttribute);
2221 }
2222
2223 /* Cut one primitive from the geometry shader */
2224 static void si_llvm_emit_primitive(
2225 const struct lp_build_tgsi_action *action,
2226 struct lp_build_tgsi_context *bld_base,
2227 struct lp_build_emit_data *emit_data)
2228 {
2229 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2230 struct gallivm_state *gallivm = bld_base->base.gallivm;
2231 LLVMValueRef args[2];
2232
2233 /* Signal primitive cut */
2234 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS);
2235 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2236 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2237 LLVMVoidTypeInContext(gallivm->context), args, 2,
2238 LLVMNoUnwindAttribute);
2239 }
2240
2241 static const struct lp_build_tgsi_action tex_action = {
2242 .fetch_args = tex_fetch_args,
2243 .emit = build_tex_intrinsic,
2244 };
2245
2246 static const struct lp_build_tgsi_action txq_action = {
2247 .fetch_args = txq_fetch_args,
2248 .emit = build_txq_intrinsic,
2249 .intr_name = "llvm.SI.resinfo"
2250 };
2251
2252 static void create_meta_data(struct si_shader_context *si_shader_ctx)
2253 {
2254 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2255 LLVMValueRef args[3];
2256
2257 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
2258 args[1] = 0;
2259 args[2] = lp_build_const_int32(gallivm, 1);
2260
2261 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
2262 }
2263
2264 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
2265 {
2266 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
2267 CONST_ADDR_SPACE);
2268 }
2269
2270 static void create_function(struct si_shader_context *si_shader_ctx)
2271 {
2272 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2273 struct gallivm_state *gallivm = bld_base->base.gallivm;
2274 struct si_shader *shader = si_shader_ctx->shader;
2275 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
2276 unsigned i, last_array_pointer, last_sgpr, num_params;
2277
2278 i8 = LLVMInt8TypeInContext(gallivm->context);
2279 i32 = LLVMInt32TypeInContext(gallivm->context);
2280 f32 = LLVMFloatTypeInContext(gallivm->context);
2281 v2i32 = LLVMVectorType(i32, 2);
2282 v3i32 = LLVMVectorType(i32, 3);
2283 v4i32 = LLVMVectorType(i32, 4);
2284 v8i32 = LLVMVectorType(i32, 8);
2285 v16i8 = LLVMVectorType(i8, 16);
2286
2287 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
2288 params[SI_PARAM_CONST] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
2289 params[SI_PARAM_SAMPLER] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
2290 params[SI_PARAM_RESOURCE] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
2291 last_array_pointer = SI_PARAM_RESOURCE;
2292
2293 switch (si_shader_ctx->type) {
2294 case TGSI_PROCESSOR_VERTEX:
2295 params[SI_PARAM_VERTEX_BUFFER] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
2296 last_array_pointer = SI_PARAM_VERTEX_BUFFER;
2297 params[SI_PARAM_BASE_VERTEX] = i32;
2298 params[SI_PARAM_START_INSTANCE] = i32;
2299 num_params = SI_PARAM_START_INSTANCE+1;
2300
2301 if (shader->key.vs.as_es) {
2302 params[SI_PARAM_ES2GS_OFFSET] = i32;
2303 num_params++;
2304 } else {
2305 if (shader->is_gs_copy_shader) {
2306 last_array_pointer = SI_PARAM_CONST;
2307 num_params = SI_PARAM_CONST+1;
2308 }
2309
2310 /* The locations of the other parameters are assigned dynamically. */
2311
2312 /* Streamout SGPRs. */
2313 if (shader->selector->so.num_outputs) {
2314 params[si_shader_ctx->param_streamout_config = num_params++] = i32;
2315 params[si_shader_ctx->param_streamout_write_index = num_params++] = i32;
2316 }
2317 /* A streamout buffer offset is loaded if the stride is non-zero. */
2318 for (i = 0; i < 4; i++) {
2319 if (!shader->selector->so.stride[i])
2320 continue;
2321
2322 params[si_shader_ctx->param_streamout_offset[i] = num_params++] = i32;
2323 }
2324 }
2325
2326 last_sgpr = num_params-1;
2327
2328 /* VGPRs */
2329 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
2330 params[num_params++] = i32; /* unused*/
2331 params[num_params++] = i32; /* unused */
2332 params[si_shader_ctx->param_instance_id = num_params++] = i32;
2333 break;
2334
2335 case TGSI_PROCESSOR_GEOMETRY:
2336 params[SI_PARAM_GS2VS_OFFSET] = i32;
2337 params[SI_PARAM_GS_WAVE_ID] = i32;
2338 last_sgpr = SI_PARAM_GS_WAVE_ID;
2339
2340 /* VGPRs */
2341 params[SI_PARAM_VTX0_OFFSET] = i32;
2342 params[SI_PARAM_VTX1_OFFSET] = i32;
2343 params[SI_PARAM_PRIMITIVE_ID] = i32;
2344 params[SI_PARAM_VTX2_OFFSET] = i32;
2345 params[SI_PARAM_VTX3_OFFSET] = i32;
2346 params[SI_PARAM_VTX4_OFFSET] = i32;
2347 params[SI_PARAM_VTX5_OFFSET] = i32;
2348 params[SI_PARAM_GS_INSTANCE_ID] = i32;
2349 num_params = SI_PARAM_GS_INSTANCE_ID+1;
2350 break;
2351
2352 case TGSI_PROCESSOR_FRAGMENT:
2353 params[SI_PARAM_ALPHA_REF] = f32;
2354 params[SI_PARAM_PRIM_MASK] = i32;
2355 last_sgpr = SI_PARAM_PRIM_MASK;
2356 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
2357 params[SI_PARAM_PERSP_CENTER] = v2i32;
2358 params[SI_PARAM_PERSP_CENTROID] = v2i32;
2359 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
2360 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
2361 params[SI_PARAM_LINEAR_CENTER] = v2i32;
2362 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
2363 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
2364 params[SI_PARAM_POS_X_FLOAT] = f32;
2365 params[SI_PARAM_POS_Y_FLOAT] = f32;
2366 params[SI_PARAM_POS_Z_FLOAT] = f32;
2367 params[SI_PARAM_POS_W_FLOAT] = f32;
2368 params[SI_PARAM_FRONT_FACE] = f32;
2369 params[SI_PARAM_ANCILLARY] = i32;
2370 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
2371 params[SI_PARAM_POS_FIXED_PT] = f32;
2372 num_params = SI_PARAM_POS_FIXED_PT+1;
2373 break;
2374
2375 default:
2376 assert(0 && "unimplemented shader");
2377 return;
2378 }
2379
2380 assert(num_params <= Elements(params));
2381 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
2382 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
2383
2384 for (i = 0; i <= last_sgpr; ++i) {
2385 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
2386
2387 /* We tell llvm that array inputs are passed by value to allow Sinking pass
2388 * to move load. Inputs are constant so this is fine. */
2389 if (i <= last_array_pointer)
2390 LLVMAddAttribute(P, LLVMByValAttribute);
2391 else
2392 LLVMAddAttribute(P, LLVMInRegAttribute);
2393 }
2394
2395 if (bld_base->info &&
2396 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
2397 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0))
2398 si_shader_ctx->ddxy_lds =
2399 LLVMAddGlobalInAddressSpace(gallivm->module,
2400 LLVMArrayType(i32, 64),
2401 "ddxy_lds",
2402 LOCAL_ADDR_SPACE);
2403 }
2404
2405 static void preload_constants(struct si_shader_context *si_shader_ctx)
2406 {
2407 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2408 struct gallivm_state * gallivm = bld_base->base.gallivm;
2409 const struct tgsi_shader_info * info = bld_base->info;
2410 unsigned buf;
2411 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
2412
2413 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
2414 unsigned i, num_const = info->const_file_max[buf] + 1;
2415
2416 if (num_const == 0)
2417 continue;
2418
2419 /* Allocate space for the constant values */
2420 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
2421
2422 /* Load the resource descriptor */
2423 si_shader_ctx->const_resource[buf] =
2424 build_indexed_load(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
2425
2426 /* Load the constants, we rely on the code sinking to do the rest */
2427 for (i = 0; i < num_const * 4; ++i) {
2428 si_shader_ctx->constants[buf][i] =
2429 load_const(gallivm->builder,
2430 si_shader_ctx->const_resource[buf],
2431 lp_build_const_int32(gallivm, i * 4),
2432 bld_base->base.elem_type);
2433 }
2434 }
2435 }
2436
2437 static void preload_samplers(struct si_shader_context *si_shader_ctx)
2438 {
2439 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2440 struct gallivm_state * gallivm = bld_base->base.gallivm;
2441 const struct tgsi_shader_info * info = bld_base->info;
2442
2443 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
2444
2445 LLVMValueRef res_ptr, samp_ptr;
2446 LLVMValueRef offset;
2447
2448 if (num_samplers == 0)
2449 return;
2450
2451 /* Allocate space for the values */
2452 si_shader_ctx->resources = CALLOC(SI_NUM_SAMPLER_VIEWS, sizeof(LLVMValueRef));
2453 si_shader_ctx->samplers = CALLOC(num_samplers, sizeof(LLVMValueRef));
2454
2455 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2456 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2457
2458 /* Load the resources and samplers, we rely on the code sinking to do the rest */
2459 for (i = 0; i < num_samplers; ++i) {
2460 /* Resource */
2461 offset = lp_build_const_int32(gallivm, i);
2462 si_shader_ctx->resources[i] = build_indexed_load(si_shader_ctx, res_ptr, offset);
2463
2464 /* Sampler */
2465 offset = lp_build_const_int32(gallivm, i);
2466 si_shader_ctx->samplers[i] = build_indexed_load(si_shader_ctx, samp_ptr, offset);
2467
2468 /* FMASK resource */
2469 if (info->is_msaa_sampler[i]) {
2470 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
2471 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + i] =
2472 build_indexed_load(si_shader_ctx, res_ptr, offset);
2473 }
2474 }
2475 }
2476
2477 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
2478 {
2479 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2480 struct gallivm_state * gallivm = bld_base->base.gallivm;
2481 unsigned i;
2482
2483 if (si_shader_ctx->type != TGSI_PROCESSOR_VERTEX ||
2484 si_shader_ctx->shader->key.vs.as_es ||
2485 !si_shader_ctx->shader->selector->so.num_outputs)
2486 return;
2487
2488 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2489 SI_PARAM_RW_BUFFERS);
2490
2491 /* Load the resources, we rely on the code sinking to do the rest */
2492 for (i = 0; i < 4; ++i) {
2493 if (si_shader_ctx->shader->selector->so.stride[i]) {
2494 LLVMValueRef offset = lp_build_const_int32(gallivm,
2495 SI_SO_BUF_OFFSET + i);
2496
2497 si_shader_ctx->so_buffers[i] = build_indexed_load(si_shader_ctx, buf_ptr, offset);
2498 }
2499 }
2500 }
2501
2502 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
2503 LLVMModuleRef mod)
2504 {
2505 unsigned r; /* llvm_compile result */
2506 unsigned i;
2507 unsigned char *ptr;
2508 struct radeon_shader_binary binary;
2509 bool dump = r600_can_dump_shader(&sscreen->b,
2510 shader->selector ? shader->selector->tokens : NULL);
2511 const char * gpu_family = r600_get_llvm_processor_name(sscreen->b.family);
2512 unsigned code_size;
2513
2514 /* Use LLVM to compile shader */
2515 memset(&binary, 0, sizeof(binary));
2516 r = radeon_llvm_compile(mod, &binary, gpu_family, dump);
2517
2518 /* Output binary dump if rscreen->debug_flags are set */
2519 if (dump && ! binary.disassembled) {
2520 fprintf(stderr, "SI CODE:\n");
2521 for (i = 0; i < binary.code_size; i+=4 ) {
2522 fprintf(stderr, "%02x%02x%02x%02x\n", binary.code[i + 3],
2523 binary.code[i + 2], binary.code[i + 1],
2524 binary.code[i]);
2525 }
2526 }
2527
2528 /* XXX: We may be able to emit some of these values directly rather than
2529 * extracting fields to be emitted later.
2530 */
2531 /* Parse config data in compiled binary */
2532 for (i = 0; i < binary.config_size; i+= 8) {
2533 unsigned reg = util_le32_to_cpu(*(uint32_t*)(binary.config + i));
2534 unsigned value = util_le32_to_cpu(*(uint32_t*)(binary.config + i + 4));
2535 switch (reg) {
2536 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
2537 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
2538 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
2539 case R_00B848_COMPUTE_PGM_RSRC1:
2540 shader->num_sgprs = (G_00B028_SGPRS(value) + 1) * 8;
2541 shader->num_vgprs = (G_00B028_VGPRS(value) + 1) * 4;
2542 break;
2543 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
2544 shader->lds_size = G_00B02C_EXTRA_LDS_SIZE(value);
2545 break;
2546 case R_00B84C_COMPUTE_PGM_RSRC2:
2547 shader->lds_size = G_00B84C_LDS_SIZE(value);
2548 break;
2549 case R_0286CC_SPI_PS_INPUT_ENA:
2550 shader->spi_ps_input_ena = value;
2551 break;
2552 case R_00B860_COMPUTE_TMPRING_SIZE:
2553 /* WAVESIZE is in units of 256 dwords. */
2554 shader->scratch_bytes_per_wave =
2555 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
2556 break;
2557 default:
2558 fprintf(stderr, "Warning: Compiler emitted unknown "
2559 "config register: 0x%x\n", reg);
2560 break;
2561 }
2562 }
2563
2564 /* copy new shader */
2565 code_size = binary.code_size + binary.rodata_size;
2566 r600_resource_reference(&shader->bo, NULL);
2567 shader->bo = si_resource_create_custom(&sscreen->b.b, PIPE_USAGE_IMMUTABLE,
2568 code_size);
2569 if (shader->bo == NULL) {
2570 return -ENOMEM;
2571 }
2572
2573 ptr = sscreen->b.ws->buffer_map(shader->bo->cs_buf, NULL, PIPE_TRANSFER_WRITE);
2574 util_memcpy_cpu_to_le32(ptr, binary.code, binary.code_size);
2575 if (binary.rodata_size > 0) {
2576 ptr += binary.code_size;
2577 util_memcpy_cpu_to_le32(ptr, binary.rodata, binary.rodata_size);
2578 }
2579
2580 sscreen->b.ws->buffer_unmap(shader->bo->cs_buf);
2581
2582 free(binary.code);
2583 free(binary.config);
2584 free(binary.rodata);
2585
2586 return r;
2587 }
2588
2589 /* Generate code for the hardware VS shader stage to go with a geometry shader */
2590 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
2591 struct si_shader_context *si_shader_ctx,
2592 struct si_shader *gs, bool dump)
2593 {
2594 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
2595 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2596 struct lp_build_context *base = &bld_base->base;
2597 struct lp_build_context *uint = &bld_base->uint_bld;
2598 struct si_shader *shader = si_shader_ctx->shader;
2599 struct si_shader_output_values *outputs;
2600 struct tgsi_shader_info *gsinfo = &gs->selector->info;
2601 LLVMValueRef t_list_ptr, t_list;
2602 LLVMValueRef args[9];
2603 int i, r;
2604
2605 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
2606
2607 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
2608 shader->is_gs_copy_shader = true;
2609
2610 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
2611
2612 create_meta_data(si_shader_ctx);
2613 create_function(si_shader_ctx);
2614 preload_streamout_buffers(si_shader_ctx);
2615
2616 /* Load the GSVS ring resource descriptor */
2617 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2618 SI_PARAM_RW_BUFFERS);
2619 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
2620 lp_build_const_int32(gallivm, SI_RING_GSVS));
2621
2622 args[0] = t_list;
2623 args[1] = lp_build_mul_imm(uint,
2624 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2625 si_shader_ctx->param_vertex_id),
2626 4);
2627 args[3] = uint->zero;
2628 args[4] = uint->one; /* OFFEN */
2629 args[5] = uint->zero; /* IDXEN */
2630 args[6] = uint->one; /* GLC */
2631 args[7] = uint->one; /* SLC */
2632 args[8] = uint->zero; /* TFE */
2633
2634 /* Fetch vertex data from GSVS ring */
2635 for (i = 0; i < gsinfo->num_outputs; ++i) {
2636 unsigned chan;
2637
2638 outputs[i].name = gsinfo->output_semantic_name[i];
2639 outputs[i].sid = gsinfo->output_semantic_index[i];
2640
2641 for (chan = 0; chan < 4; chan++) {
2642 args[2] = lp_build_const_int32(gallivm,
2643 (i * 4 + chan) *
2644 gs->selector->gs_max_out_vertices * 16 * 4);
2645
2646 outputs[i].values[chan] =
2647 LLVMBuildBitCast(gallivm->builder,
2648 build_intrinsic(gallivm->builder,
2649 "llvm.SI.buffer.load.dword.i32.i32",
2650 LLVMInt32TypeInContext(gallivm->context),
2651 args, 9,
2652 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
2653 base->elem_type, "");
2654 }
2655 }
2656
2657 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
2658
2659 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
2660
2661 if (dump)
2662 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
2663
2664 r = si_compile_llvm(sscreen, si_shader_ctx->shader,
2665 bld_base->base.gallivm->module);
2666
2667 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
2668
2669 FREE(outputs);
2670 return r;
2671 }
2672
2673 int si_shader_create(struct si_screen *sscreen, struct si_shader *shader)
2674 {
2675 struct si_shader_selector *sel = shader->selector;
2676 struct si_shader_context si_shader_ctx;
2677 struct lp_build_tgsi_context * bld_base;
2678 LLVMModuleRef mod;
2679 int r = 0;
2680 bool dump = r600_can_dump_shader(&sscreen->b, sel->tokens);
2681
2682 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2683 * conversion fails. */
2684 if (dump) {
2685 tgsi_dump(sel->tokens, 0);
2686 si_dump_streamout(&sel->so);
2687 }
2688
2689 assert(shader->nparam == 0);
2690
2691 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
2692 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
2693 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
2694
2695 if (sel->info.uses_kill)
2696 shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
2697
2698 shader->uses_instanceid = sel->info.uses_instanceid;
2699 bld_base->info = &sel->info;
2700 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
2701
2702 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
2703 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
2704 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
2705 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
2706 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
2707 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
2708 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
2709 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
2710 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
2711 bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
2712 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
2713 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
2714
2715 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
2716 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
2717
2718 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
2719 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
2720
2721 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
2722 si_shader_ctx.tokens = sel->tokens;
2723 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
2724 si_shader_ctx.shader = shader;
2725 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
2726
2727 switch (si_shader_ctx.type) {
2728 case TGSI_PROCESSOR_VERTEX:
2729 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
2730 if (shader->key.vs.as_es) {
2731 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
2732 } else {
2733 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
2734 }
2735 break;
2736 case TGSI_PROCESSOR_GEOMETRY:
2737 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
2738 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
2739 break;
2740 case TGSI_PROCESSOR_FRAGMENT:
2741 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
2742 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
2743
2744 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2745 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2746 shader->db_shader_control |=
2747 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2748 break;
2749 case TGSI_FS_DEPTH_LAYOUT_LESS:
2750 shader->db_shader_control |=
2751 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2752 break;
2753 }
2754 break;
2755 default:
2756 assert(!"Unsupported shader type");
2757 return -1;
2758 }
2759
2760 create_meta_data(&si_shader_ctx);
2761 create_function(&si_shader_ctx);
2762 preload_constants(&si_shader_ctx);
2763 preload_samplers(&si_shader_ctx);
2764 preload_streamout_buffers(&si_shader_ctx);
2765
2766 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2767 si_shader_ctx.gs_next_vertex =
2768 lp_build_alloca(bld_base->base.gallivm,
2769 bld_base->uint_bld.elem_type, "");
2770 }
2771
2772 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
2773 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
2774 goto out;
2775 }
2776
2777 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
2778
2779 mod = bld_base->base.gallivm->module;
2780 r = si_compile_llvm(sscreen, shader, mod);
2781 if (r) {
2782 fprintf(stderr, "LLVM failed to compile shader\n");
2783 goto out;
2784 }
2785
2786 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
2787
2788 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2789 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
2790 shader->gs_copy_shader->selector = shader->selector;
2791 shader->gs_copy_shader->key = shader->key;
2792 si_shader_ctx.shader = shader->gs_copy_shader;
2793 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
2794 shader, dump))) {
2795 free(shader->gs_copy_shader);
2796 shader->gs_copy_shader = NULL;
2797 goto out;
2798 }
2799 }
2800
2801 tgsi_parse_free(&si_shader_ctx.parse);
2802
2803 out:
2804 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
2805 FREE(si_shader_ctx.constants[i]);
2806 FREE(si_shader_ctx.resources);
2807 FREE(si_shader_ctx.samplers);
2808
2809 return r;
2810 }
2811
2812 void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader)
2813 {
2814 if (shader->gs_copy_shader)
2815 si_shader_destroy(ctx, shader->gs_copy_shader);
2816
2817 r600_resource_reference(&shader->bo, NULL);
2818 r600_resource_reference(&shader->scratch_bo, NULL);
2819 }