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[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "radeon/radeon_elf_util.h"
37 #include "util/u_memory.h"
38 #include "util/u_string.h"
39 #include "tgsi/tgsi_build.h"
40 #include "tgsi/tgsi_util.h"
41 #include "tgsi/tgsi_dump.h"
42
43 #include "ac_llvm_util.h"
44 #include "si_shader_internal.h"
45 #include "si_pipe.h"
46 #include "sid.h"
47
48
49 static const char *scratch_rsrc_dword0_symbol =
50 "SCRATCH_RSRC_DWORD0";
51
52 static const char *scratch_rsrc_dword1_symbol =
53 "SCRATCH_RSRC_DWORD1";
54
55 struct si_shader_output_values
56 {
57 LLVMValueRef values[4];
58 unsigned name;
59 unsigned sid;
60 };
61
62 static void si_init_shader_ctx(struct si_shader_context *ctx,
63 struct si_screen *sscreen,
64 struct si_shader *shader,
65 LLVMTargetMachineRef tm);
66
67 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
68 struct lp_build_tgsi_context *bld_base,
69 struct lp_build_emit_data *emit_data);
70
71 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
72 FILE *f);
73
74 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
75 union si_shader_part_key *key);
76 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
77 union si_shader_part_key *key);
78 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
79 union si_shader_part_key *key);
80 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
81 union si_shader_part_key *key);
82 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
83 union si_shader_part_key *key);
84
85 /* Ideally pass the sample mask input to the PS epilog as v13, which
86 * is its usual location, so that the shader doesn't have to add v_mov.
87 */
88 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
89
90 /* The VS location of the PrimitiveID input is the same in the epilog,
91 * so that the main shader part doesn't have to move it.
92 */
93 #define VS_EPILOG_PRIMID_LOC 2
94
95 enum {
96 CONST_ADDR_SPACE = 2,
97 LOCAL_ADDR_SPACE = 3,
98 };
99
100 #define SENDMSG_GS 2
101 #define SENDMSG_GS_DONE 3
102
103 #define SENDMSG_GS_OP_NOP (0 << 4)
104 #define SENDMSG_GS_OP_CUT (1 << 4)
105 #define SENDMSG_GS_OP_EMIT (2 << 4)
106 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
107
108 /**
109 * Returns a unique index for a semantic name and index. The index must be
110 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
111 * calculated.
112 */
113 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
114 {
115 switch (semantic_name) {
116 case TGSI_SEMANTIC_POSITION:
117 return 0;
118 case TGSI_SEMANTIC_PSIZE:
119 return 1;
120 case TGSI_SEMANTIC_CLIPDIST:
121 assert(index <= 1);
122 return 2 + index;
123 case TGSI_SEMANTIC_GENERIC:
124 if (index <= 63-4)
125 return 4 + index;
126
127 assert(!"invalid generic index");
128 return 0;
129
130 /* patch indices are completely separate and thus start from 0 */
131 case TGSI_SEMANTIC_TESSOUTER:
132 return 0;
133 case TGSI_SEMANTIC_TESSINNER:
134 return 1;
135 case TGSI_SEMANTIC_PATCH:
136 return 2 + index;
137
138 default:
139 assert(!"invalid semantic name");
140 return 0;
141 }
142 }
143
144 /**
145 * Get the value of a shader input parameter and extract a bitfield.
146 */
147 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
148 unsigned param, unsigned rshift,
149 unsigned bitwidth)
150 {
151 struct gallivm_state *gallivm = &ctx->gallivm;
152 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
153 param);
154
155 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
156 value = bitcast(&ctx->soa.bld_base,
157 TGSI_TYPE_UNSIGNED, value);
158
159 if (rshift)
160 value = LLVMBuildLShr(gallivm->builder, value,
161 lp_build_const_int32(gallivm, rshift), "");
162
163 if (rshift + bitwidth < 32) {
164 unsigned mask = (1 << bitwidth) - 1;
165 value = LLVMBuildAnd(gallivm->builder, value,
166 lp_build_const_int32(gallivm, mask), "");
167 }
168
169 return value;
170 }
171
172 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
173 {
174 switch (ctx->type) {
175 case PIPE_SHADER_TESS_CTRL:
176 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
177
178 case PIPE_SHADER_TESS_EVAL:
179 return LLVMGetParam(ctx->main_fn,
180 ctx->param_tes_rel_patch_id);
181
182 default:
183 assert(0);
184 return NULL;
185 }
186 }
187
188 /* Tessellation shaders pass outputs to the next shader using LDS.
189 *
190 * LS outputs = TCS inputs
191 * TCS outputs = TES inputs
192 *
193 * The LDS layout is:
194 * - TCS inputs for patch 0
195 * - TCS inputs for patch 1
196 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
197 * - ...
198 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
199 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
200 * - TCS outputs for patch 1
201 * - Per-patch TCS outputs for patch 1
202 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
203 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
204 * - ...
205 *
206 * All three shaders VS(LS), TCS, TES share the same LDS space.
207 */
208
209 static LLVMValueRef
210 get_tcs_in_patch_stride(struct si_shader_context *ctx)
211 {
212 if (ctx->type == PIPE_SHADER_VERTEX)
213 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
214 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
215 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
216 else {
217 assert(0);
218 return NULL;
219 }
220 }
221
222 static LLVMValueRef
223 get_tcs_out_patch_stride(struct si_shader_context *ctx)
224 {
225 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
226 }
227
228 static LLVMValueRef
229 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
230 {
231 return lp_build_mul_imm(&ctx->soa.bld_base.uint_bld,
232 unpack_param(ctx,
233 SI_PARAM_TCS_OUT_OFFSETS,
234 0, 16),
235 4);
236 }
237
238 static LLVMValueRef
239 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
240 {
241 return lp_build_mul_imm(&ctx->soa.bld_base.uint_bld,
242 unpack_param(ctx,
243 SI_PARAM_TCS_OUT_OFFSETS,
244 16, 16),
245 4);
246 }
247
248 static LLVMValueRef
249 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
250 {
251 struct gallivm_state *gallivm = &ctx->gallivm;
252 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
253 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
254
255 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
256 }
257
258 static LLVMValueRef
259 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
260 {
261 struct gallivm_state *gallivm = &ctx->gallivm;
262 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
263 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
264 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
265
266 return LLVMBuildAdd(gallivm->builder, patch0_offset,
267 LLVMBuildMul(gallivm->builder, patch_stride,
268 rel_patch_id, ""),
269 "");
270 }
271
272 static LLVMValueRef
273 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
274 {
275 struct gallivm_state *gallivm = &ctx->gallivm;
276 LLVMValueRef patch0_patch_data_offset =
277 get_tcs_out_patch0_patch_data_offset(ctx);
278 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
279 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
280
281 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
282 LLVMBuildMul(gallivm->builder, patch_stride,
283 rel_patch_id, ""),
284 "");
285 }
286
287 static LLVMValueRef build_gep0(struct si_shader_context *ctx,
288 LLVMValueRef base_ptr, LLVMValueRef index)
289 {
290 LLVMValueRef indices[2] = {
291 LLVMConstInt(ctx->i32, 0, 0),
292 index,
293 };
294 return LLVMBuildGEP(ctx->gallivm.builder, base_ptr,
295 indices, 2, "");
296 }
297
298 static void build_indexed_store(struct si_shader_context *ctx,
299 LLVMValueRef base_ptr, LLVMValueRef index,
300 LLVMValueRef value)
301 {
302 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
303 struct gallivm_state *gallivm = bld_base->base.gallivm;
304
305 LLVMBuildStore(gallivm->builder, value,
306 build_gep0(ctx, base_ptr, index));
307 }
308
309 /**
310 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
311 * It's equivalent to doing a load from &base_ptr[index].
312 *
313 * \param base_ptr Where the array starts.
314 * \param index The element index into the array.
315 * \param uniform Whether the base_ptr and index can be assumed to be
316 * dynamically uniform
317 */
318 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
319 LLVMValueRef base_ptr, LLVMValueRef index,
320 bool uniform)
321 {
322 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
323 struct gallivm_state *gallivm = bld_base->base.gallivm;
324 LLVMValueRef pointer;
325
326 pointer = build_gep0(ctx, base_ptr, index);
327 if (uniform)
328 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
329 return LLVMBuildLoad(gallivm->builder, pointer, "");
330 }
331
332 /**
333 * Do a load from &base_ptr[index], but also add a flag that it's loading
334 * a constant from a dynamically uniform index.
335 */
336 static LLVMValueRef build_indexed_load_const(
337 struct si_shader_context *ctx,
338 LLVMValueRef base_ptr, LLVMValueRef index)
339 {
340 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
341 LLVMSetMetadata(result, ctx->invariant_load_md_kind, ctx->empty_md);
342 return result;
343 }
344
345 static LLVMValueRef get_instance_index_for_fetch(
346 struct si_shader_context *radeon_bld,
347 unsigned param_start_instance, unsigned divisor)
348 {
349 struct si_shader_context *ctx =
350 si_shader_context(&radeon_bld->soa.bld_base);
351 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
352
353 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
354 ctx->param_instance_id);
355
356 /* The division must be done before START_INSTANCE is added. */
357 if (divisor > 1)
358 result = LLVMBuildUDiv(gallivm->builder, result,
359 lp_build_const_int32(gallivm, divisor), "");
360
361 return LLVMBuildAdd(gallivm->builder, result,
362 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
363 }
364
365 static void declare_input_vs(
366 struct si_shader_context *ctx,
367 unsigned input_index,
368 const struct tgsi_full_declaration *decl,
369 LLVMValueRef out[4])
370 {
371 struct lp_build_context *base = &ctx->soa.bld_base.base;
372 struct gallivm_state *gallivm = base->gallivm;
373
374 unsigned chan;
375 unsigned fix_fetch;
376
377 LLVMValueRef t_list_ptr;
378 LLVMValueRef t_offset;
379 LLVMValueRef t_list;
380 LLVMValueRef attribute_offset;
381 LLVMValueRef buffer_index;
382 LLVMValueRef args[3];
383 LLVMValueRef input;
384
385 /* Load the T list */
386 t_list_ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_VERTEX_BUFFERS);
387
388 t_offset = lp_build_const_int32(gallivm, input_index);
389
390 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
391
392 /* Build the attribute offset */
393 attribute_offset = lp_build_const_int32(gallivm, 0);
394
395 buffer_index = LLVMGetParam(ctx->main_fn,
396 ctx->param_vertex_index0 +
397 input_index);
398
399 args[0] = t_list;
400 args[1] = attribute_offset;
401 args[2] = buffer_index;
402 input = lp_build_intrinsic(gallivm->builder,
403 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
404 LP_FUNC_ATTR_READNONE);
405
406 /* Break up the vec4 into individual components */
407 for (chan = 0; chan < 4; chan++) {
408 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
409 out[chan] = LLVMBuildExtractElement(gallivm->builder,
410 input, llvm_chan, "");
411 }
412
413 fix_fetch = (ctx->shader->key.mono.vs.fix_fetch >> (2 * input_index)) & 3;
414 if (fix_fetch) {
415 /* The hardware returns an unsigned value; convert it to a
416 * signed one.
417 */
418 LLVMValueRef tmp = out[3];
419 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
420
421 /* First, recover the sign-extended signed integer value. */
422 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
423 tmp = LLVMBuildFPToUI(gallivm->builder, tmp, ctx->i32, "");
424 else
425 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->i32, "");
426
427 /* For the integer-like cases, do a natural sign extension.
428 *
429 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
430 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
431 * exponent.
432 */
433 tmp = LLVMBuildShl(gallivm->builder, tmp,
434 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
435 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
436 tmp = LLVMBuildAShr(gallivm->builder, tmp, c30, "");
437
438 /* Convert back to the right type. */
439 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
440 LLVMValueRef clamp;
441 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
442 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
443 clamp = LLVMBuildFCmp(gallivm->builder, LLVMRealULT, tmp, neg_one, "");
444 tmp = LLVMBuildSelect(gallivm->builder, clamp, neg_one, tmp, "");
445 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
446 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
447 }
448
449 out[3] = tmp;
450 }
451 }
452
453 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
454 unsigned swizzle)
455 {
456 struct si_shader_context *ctx = si_shader_context(bld_base);
457
458 if (swizzle > 0)
459 return bld_base->uint_bld.zero;
460
461 switch (ctx->type) {
462 case PIPE_SHADER_VERTEX:
463 return LLVMGetParam(ctx->main_fn,
464 ctx->param_vs_prim_id);
465 case PIPE_SHADER_TESS_CTRL:
466 return LLVMGetParam(ctx->main_fn,
467 SI_PARAM_PATCH_ID);
468 case PIPE_SHADER_TESS_EVAL:
469 return LLVMGetParam(ctx->main_fn,
470 ctx->param_tes_patch_id);
471 case PIPE_SHADER_GEOMETRY:
472 return LLVMGetParam(ctx->main_fn,
473 SI_PARAM_PRIMITIVE_ID);
474 default:
475 assert(0);
476 return bld_base->uint_bld.zero;
477 }
478 }
479
480 /**
481 * Return the value of tgsi_ind_register for indexing.
482 * This is the indirect index with the constant offset added to it.
483 */
484 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
485 const struct tgsi_ind_register *ind,
486 int rel_index)
487 {
488 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
489 LLVMValueRef result;
490
491 result = ctx->soa.addr[ind->Index][ind->Swizzle];
492 result = LLVMBuildLoad(gallivm->builder, result, "");
493 result = LLVMBuildAdd(gallivm->builder, result,
494 lp_build_const_int32(gallivm, rel_index), "");
495 return result;
496 }
497
498 /**
499 * Like get_indirect_index, but restricts the return value to a (possibly
500 * undefined) value inside [0..num).
501 */
502 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
503 const struct tgsi_ind_register *ind,
504 int rel_index, unsigned num)
505 {
506 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
507
508 /* LLVM 3.8: If indirect resource indexing is used:
509 * - SI & CIK hang
510 * - VI crashes
511 */
512 if (HAVE_LLVM <= 0x0308)
513 return LLVMGetUndef(ctx->i32);
514
515 return si_llvm_bound_index(ctx, result, num);
516 }
517
518
519 /**
520 * Calculate a dword address given an input or output register and a stride.
521 */
522 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
523 const struct tgsi_full_dst_register *dst,
524 const struct tgsi_full_src_register *src,
525 LLVMValueRef vertex_dw_stride,
526 LLVMValueRef base_addr)
527 {
528 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
529 struct tgsi_shader_info *info = &ctx->shader->selector->info;
530 ubyte *name, *index, *array_first;
531 int first, param;
532 struct tgsi_full_dst_register reg;
533
534 /* Set the register description. The address computation is the same
535 * for sources and destinations. */
536 if (src) {
537 reg.Register.File = src->Register.File;
538 reg.Register.Index = src->Register.Index;
539 reg.Register.Indirect = src->Register.Indirect;
540 reg.Register.Dimension = src->Register.Dimension;
541 reg.Indirect = src->Indirect;
542 reg.Dimension = src->Dimension;
543 reg.DimIndirect = src->DimIndirect;
544 } else
545 reg = *dst;
546
547 /* If the register is 2-dimensional (e.g. an array of vertices
548 * in a primitive), calculate the base address of the vertex. */
549 if (reg.Register.Dimension) {
550 LLVMValueRef index;
551
552 if (reg.Dimension.Indirect)
553 index = get_indirect_index(ctx, &reg.DimIndirect,
554 reg.Dimension.Index);
555 else
556 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
557
558 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
559 LLVMBuildMul(gallivm->builder, index,
560 vertex_dw_stride, ""), "");
561 }
562
563 /* Get information about the register. */
564 if (reg.Register.File == TGSI_FILE_INPUT) {
565 name = info->input_semantic_name;
566 index = info->input_semantic_index;
567 array_first = info->input_array_first;
568 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
569 name = info->output_semantic_name;
570 index = info->output_semantic_index;
571 array_first = info->output_array_first;
572 } else {
573 assert(0);
574 return NULL;
575 }
576
577 if (reg.Register.Indirect) {
578 /* Add the relative address of the element. */
579 LLVMValueRef ind_index;
580
581 if (reg.Indirect.ArrayID)
582 first = array_first[reg.Indirect.ArrayID];
583 else
584 first = reg.Register.Index;
585
586 ind_index = get_indirect_index(ctx, &reg.Indirect,
587 reg.Register.Index - first);
588
589 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
590 LLVMBuildMul(gallivm->builder, ind_index,
591 lp_build_const_int32(gallivm, 4), ""), "");
592
593 param = si_shader_io_get_unique_index(name[first], index[first]);
594 } else {
595 param = si_shader_io_get_unique_index(name[reg.Register.Index],
596 index[reg.Register.Index]);
597 }
598
599 /* Add the base address of the element. */
600 return LLVMBuildAdd(gallivm->builder, base_addr,
601 lp_build_const_int32(gallivm, param * 4), "");
602 }
603
604 /* The offchip buffer layout for TCS->TES is
605 *
606 * - attribute 0 of patch 0 vertex 0
607 * - attribute 0 of patch 0 vertex 1
608 * - attribute 0 of patch 0 vertex 2
609 * ...
610 * - attribute 0 of patch 1 vertex 0
611 * - attribute 0 of patch 1 vertex 1
612 * ...
613 * - attribute 1 of patch 0 vertex 0
614 * - attribute 1 of patch 0 vertex 1
615 * ...
616 * - per patch attribute 0 of patch 0
617 * - per patch attribute 0 of patch 1
618 * ...
619 *
620 * Note that every attribute has 4 components.
621 */
622 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
623 LLVMValueRef vertex_index,
624 LLVMValueRef param_index)
625 {
626 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
627 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
628 LLVMValueRef param_stride, constant16;
629
630 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
631 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
632 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
633 num_patches, "");
634
635 constant16 = lp_build_const_int32(gallivm, 16);
636 if (vertex_index) {
637 base_addr = LLVMBuildMul(gallivm->builder, get_rel_patch_id(ctx),
638 vertices_per_patch, "");
639
640 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
641 vertex_index, "");
642
643 param_stride = total_vertices;
644 } else {
645 base_addr = get_rel_patch_id(ctx);
646 param_stride = num_patches;
647 }
648
649 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
650 LLVMBuildMul(gallivm->builder, param_index,
651 param_stride, ""), "");
652
653 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
654
655 if (!vertex_index) {
656 LLVMValueRef patch_data_offset =
657 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
658
659 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
660 patch_data_offset, "");
661 }
662 return base_addr;
663 }
664
665 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
666 struct si_shader_context *ctx,
667 const struct tgsi_full_dst_register *dst,
668 const struct tgsi_full_src_register *src)
669 {
670 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
671 struct tgsi_shader_info *info = &ctx->shader->selector->info;
672 ubyte *name, *index, *array_first;
673 struct tgsi_full_src_register reg;
674 LLVMValueRef vertex_index = NULL;
675 LLVMValueRef param_index = NULL;
676 unsigned param_index_base, param_base;
677
678 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
679
680 if (reg.Register.Dimension) {
681
682 if (reg.Dimension.Indirect)
683 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
684 reg.Dimension.Index);
685 else
686 vertex_index = lp_build_const_int32(gallivm,
687 reg.Dimension.Index);
688 }
689
690 /* Get information about the register. */
691 if (reg.Register.File == TGSI_FILE_INPUT) {
692 name = info->input_semantic_name;
693 index = info->input_semantic_index;
694 array_first = info->input_array_first;
695 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
696 name = info->output_semantic_name;
697 index = info->output_semantic_index;
698 array_first = info->output_array_first;
699 } else {
700 assert(0);
701 return NULL;
702 }
703
704 if (reg.Register.Indirect) {
705 if (reg.Indirect.ArrayID)
706 param_base = array_first[reg.Indirect.ArrayID];
707 else
708 param_base = reg.Register.Index;
709
710 param_index = get_indirect_index(ctx, &reg.Indirect,
711 reg.Register.Index - param_base);
712
713 } else {
714 param_base = reg.Register.Index;
715 param_index = lp_build_const_int32(gallivm, 0);
716 }
717
718 param_index_base = si_shader_io_get_unique_index(name[param_base],
719 index[param_base]);
720
721 param_index = LLVMBuildAdd(gallivm->builder, param_index,
722 lp_build_const_int32(gallivm, param_index_base),
723 "");
724
725 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
726 }
727
728 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
729 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
730 * or v4i32 (num_channels=3,4). */
731 static void build_tbuffer_store(struct si_shader_context *ctx,
732 LLVMValueRef rsrc,
733 LLVMValueRef vdata,
734 unsigned num_channels,
735 LLVMValueRef vaddr,
736 LLVMValueRef soffset,
737 unsigned inst_offset,
738 unsigned dfmt,
739 unsigned nfmt,
740 unsigned offen,
741 unsigned idxen,
742 unsigned glc,
743 unsigned slc,
744 unsigned tfe)
745 {
746 struct gallivm_state *gallivm = &ctx->gallivm;
747 LLVMValueRef args[] = {
748 rsrc,
749 vdata,
750 LLVMConstInt(ctx->i32, num_channels, 0),
751 vaddr,
752 soffset,
753 LLVMConstInt(ctx->i32, inst_offset, 0),
754 LLVMConstInt(ctx->i32, dfmt, 0),
755 LLVMConstInt(ctx->i32, nfmt, 0),
756 LLVMConstInt(ctx->i32, offen, 0),
757 LLVMConstInt(ctx->i32, idxen, 0),
758 LLVMConstInt(ctx->i32, glc, 0),
759 LLVMConstInt(ctx->i32, slc, 0),
760 LLVMConstInt(ctx->i32, tfe, 0)
761 };
762
763 /* The instruction offset field has 12 bits */
764 assert(offen || inst_offset < (1 << 12));
765
766 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
767 unsigned func = CLAMP(num_channels, 1, 3) - 1;
768 const char *types[] = {"i32", "v2i32", "v4i32"};
769 char name[256];
770 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
771
772 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
773 args, ARRAY_SIZE(args), 0);
774 }
775
776 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
777 LLVMValueRef rsrc,
778 LLVMValueRef vdata,
779 unsigned num_channels,
780 LLVMValueRef vaddr,
781 LLVMValueRef soffset,
782 unsigned inst_offset)
783 {
784 static unsigned dfmt[] = {
785 V_008F0C_BUF_DATA_FORMAT_32,
786 V_008F0C_BUF_DATA_FORMAT_32_32,
787 V_008F0C_BUF_DATA_FORMAT_32_32_32,
788 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
789 };
790 assert(num_channels >= 1 && num_channels <= 4);
791
792 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
793 inst_offset, dfmt[num_channels-1],
794 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
795 }
796
797 static LLVMValueRef build_buffer_load(struct si_shader_context *ctx,
798 LLVMValueRef rsrc,
799 int num_channels,
800 LLVMValueRef vindex,
801 LLVMValueRef voffset,
802 LLVMValueRef soffset,
803 unsigned inst_offset,
804 unsigned glc,
805 unsigned slc)
806 {
807 struct gallivm_state *gallivm = &ctx->gallivm;
808 unsigned func = CLAMP(num_channels, 1, 3) - 1;
809
810 if (HAVE_LLVM >= 0x309) {
811 LLVMValueRef args[] = {
812 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, ""),
813 vindex ? vindex : LLVMConstInt(ctx->i32, 0, 0),
814 LLVMConstInt(ctx->i32, inst_offset, 0),
815 LLVMConstInt(ctx->i1, glc, 0),
816 LLVMConstInt(ctx->i1, slc, 0)
817 };
818
819 LLVMTypeRef types[] = {ctx->f32, LLVMVectorType(ctx->f32, 2),
820 ctx->v4f32};
821 const char *type_names[] = {"f32", "v2f32", "v4f32"};
822 char name[256];
823
824 if (voffset) {
825 args[2] = LLVMBuildAdd(gallivm->builder, args[2], voffset,
826 "");
827 }
828
829 if (soffset) {
830 args[2] = LLVMBuildAdd(gallivm->builder, args[2], soffset,
831 "");
832 }
833
834 snprintf(name, sizeof(name), "llvm.amdgcn.buffer.load.%s",
835 type_names[func]);
836
837 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
838 ARRAY_SIZE(args), LP_FUNC_ATTR_READONLY);
839 } else {
840 LLVMValueRef args[] = {
841 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v16i8, ""),
842 voffset ? voffset : vindex,
843 soffset,
844 LLVMConstInt(ctx->i32, inst_offset, 0),
845 LLVMConstInt(ctx->i32, voffset ? 1 : 0, 0), // offen
846 LLVMConstInt(ctx->i32, vindex ? 1 : 0, 0), //idxen
847 LLVMConstInt(ctx->i32, glc, 0),
848 LLVMConstInt(ctx->i32, slc, 0),
849 LLVMConstInt(ctx->i32, 0, 0), // TFE
850 };
851
852 LLVMTypeRef types[] = {ctx->i32, LLVMVectorType(ctx->i32, 2),
853 ctx->v4i32};
854 const char *type_names[] = {"i32", "v2i32", "v4i32"};
855 const char *arg_type = "i32";
856 char name[256];
857
858 if (voffset && vindex) {
859 LLVMValueRef vaddr[] = {vindex, voffset};
860
861 arg_type = "v2i32";
862 args[1] = lp_build_gather_values(gallivm, vaddr, 2);
863 }
864
865 snprintf(name, sizeof(name), "llvm.SI.buffer.load.dword.%s.%s",
866 type_names[func], arg_type);
867
868 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
869 ARRAY_SIZE(args), LP_FUNC_ATTR_READONLY);
870 }
871 }
872
873 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
874 enum tgsi_opcode_type type, unsigned swizzle,
875 LLVMValueRef buffer, LLVMValueRef offset,
876 LLVMValueRef base)
877 {
878 struct si_shader_context *ctx = si_shader_context(bld_base);
879 struct gallivm_state *gallivm = bld_base->base.gallivm;
880 LLVMValueRef value, value2;
881 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
882 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
883
884 if (swizzle == ~0) {
885 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
886 0, 1, 0);
887
888 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
889 }
890
891 if (!tgsi_type_is_64bit(type)) {
892 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
893 0, 1, 0);
894
895 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
896 return LLVMBuildExtractElement(gallivm->builder, value,
897 lp_build_const_int32(gallivm, swizzle), "");
898 }
899
900 value = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
901 swizzle * 4, 1, 0);
902
903 value2 = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
904 swizzle * 4 + 4, 1, 0);
905
906 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
907 }
908
909 /**
910 * Load from LDS.
911 *
912 * \param type output value type
913 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
914 * \param dw_addr address in dwords
915 */
916 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
917 enum tgsi_opcode_type type, unsigned swizzle,
918 LLVMValueRef dw_addr)
919 {
920 struct si_shader_context *ctx = si_shader_context(bld_base);
921 struct gallivm_state *gallivm = bld_base->base.gallivm;
922 LLVMValueRef value;
923
924 if (swizzle == ~0) {
925 LLVMValueRef values[TGSI_NUM_CHANNELS];
926
927 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
928 values[chan] = lds_load(bld_base, type, chan, dw_addr);
929
930 return lp_build_gather_values(bld_base->base.gallivm, values,
931 TGSI_NUM_CHANNELS);
932 }
933
934 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
935 lp_build_const_int32(gallivm, swizzle));
936
937 value = build_indexed_load(ctx, ctx->lds, dw_addr, false);
938 if (tgsi_type_is_64bit(type)) {
939 LLVMValueRef value2;
940 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
941 lp_build_const_int32(gallivm, 1));
942 value2 = build_indexed_load(ctx, ctx->lds, dw_addr, false);
943 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
944 }
945
946 return LLVMBuildBitCast(gallivm->builder, value,
947 tgsi2llvmtype(bld_base, type), "");
948 }
949
950 /**
951 * Store to LDS.
952 *
953 * \param swizzle offset (typically 0..3)
954 * \param dw_addr address in dwords
955 * \param value value to store
956 */
957 static void lds_store(struct lp_build_tgsi_context *bld_base,
958 unsigned swizzle, LLVMValueRef dw_addr,
959 LLVMValueRef value)
960 {
961 struct si_shader_context *ctx = si_shader_context(bld_base);
962 struct gallivm_state *gallivm = bld_base->base.gallivm;
963
964 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
965 lp_build_const_int32(gallivm, swizzle));
966
967 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
968 build_indexed_store(ctx, ctx->lds,
969 dw_addr, value);
970 }
971
972 static LLVMValueRef fetch_input_tcs(
973 struct lp_build_tgsi_context *bld_base,
974 const struct tgsi_full_src_register *reg,
975 enum tgsi_opcode_type type, unsigned swizzle)
976 {
977 struct si_shader_context *ctx = si_shader_context(bld_base);
978 LLVMValueRef dw_addr, stride;
979
980 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
981 dw_addr = get_tcs_in_current_patch_offset(ctx);
982 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
983
984 return lds_load(bld_base, type, swizzle, dw_addr);
985 }
986
987 static LLVMValueRef fetch_output_tcs(
988 struct lp_build_tgsi_context *bld_base,
989 const struct tgsi_full_src_register *reg,
990 enum tgsi_opcode_type type, unsigned swizzle)
991 {
992 struct si_shader_context *ctx = si_shader_context(bld_base);
993 LLVMValueRef dw_addr, stride;
994
995 if (reg->Register.Dimension) {
996 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
997 dw_addr = get_tcs_out_current_patch_offset(ctx);
998 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
999 } else {
1000 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1001 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1002 }
1003
1004 return lds_load(bld_base, type, swizzle, dw_addr);
1005 }
1006
1007 static LLVMValueRef fetch_input_tes(
1008 struct lp_build_tgsi_context *bld_base,
1009 const struct tgsi_full_src_register *reg,
1010 enum tgsi_opcode_type type, unsigned swizzle)
1011 {
1012 struct si_shader_context *ctx = si_shader_context(bld_base);
1013 struct gallivm_state *gallivm = bld_base->base.gallivm;
1014 LLVMValueRef rw_buffers, buffer, base, addr;
1015
1016 rw_buffers = LLVMGetParam(ctx->main_fn,
1017 SI_PARAM_RW_BUFFERS);
1018 buffer = build_indexed_load_const(ctx, rw_buffers,
1019 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1020
1021 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1022 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1023
1024 return buffer_load(bld_base, type, swizzle, buffer, base, addr);
1025 }
1026
1027 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1028 const struct tgsi_full_instruction *inst,
1029 const struct tgsi_opcode_info *info,
1030 LLVMValueRef dst[4])
1031 {
1032 struct si_shader_context *ctx = si_shader_context(bld_base);
1033 struct gallivm_state *gallivm = bld_base->base.gallivm;
1034 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
1035 unsigned chan_index;
1036 LLVMValueRef dw_addr, stride;
1037 LLVMValueRef rw_buffers, buffer, base, buf_addr;
1038 LLVMValueRef values[4];
1039
1040 /* Only handle per-patch and per-vertex outputs here.
1041 * Vectors will be lowered to scalars and this function will be called again.
1042 */
1043 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1044 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1045 si_llvm_emit_store(bld_base, inst, info, dst);
1046 return;
1047 }
1048
1049 if (reg->Register.Dimension) {
1050 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1051 dw_addr = get_tcs_out_current_patch_offset(ctx);
1052 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1053 } else {
1054 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1055 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1056 }
1057
1058 rw_buffers = LLVMGetParam(ctx->main_fn,
1059 SI_PARAM_RW_BUFFERS);
1060 buffer = build_indexed_load_const(ctx, rw_buffers,
1061 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1062
1063 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1064 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1065
1066
1067 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1068 LLVMValueRef value = dst[chan_index];
1069
1070 if (inst->Instruction.Saturate)
1071 value = si_llvm_saturate(bld_base, value);
1072
1073 lds_store(bld_base, chan_index, dw_addr, value);
1074
1075 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1076 values[chan_index] = value;
1077
1078 if (inst->Dst[0].Register.WriteMask != 0xF) {
1079 build_tbuffer_store_dwords(ctx, buffer, value, 1,
1080 buf_addr, base,
1081 4 * chan_index);
1082 }
1083 }
1084
1085 if (inst->Dst[0].Register.WriteMask == 0xF) {
1086 LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
1087 values, 4);
1088 build_tbuffer_store_dwords(ctx, buffer, value, 4, buf_addr,
1089 base, 0);
1090 }
1091 }
1092
1093 static LLVMValueRef fetch_input_gs(
1094 struct lp_build_tgsi_context *bld_base,
1095 const struct tgsi_full_src_register *reg,
1096 enum tgsi_opcode_type type,
1097 unsigned swizzle)
1098 {
1099 struct lp_build_context *base = &bld_base->base;
1100 struct si_shader_context *ctx = si_shader_context(bld_base);
1101 struct si_shader *shader = ctx->shader;
1102 struct lp_build_context *uint = &ctx->soa.bld_base.uint_bld;
1103 struct gallivm_state *gallivm = base->gallivm;
1104 LLVMValueRef vtx_offset;
1105 LLVMValueRef args[9];
1106 unsigned vtx_offset_param;
1107 struct tgsi_shader_info *info = &shader->selector->info;
1108 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1109 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1110 unsigned param;
1111 LLVMValueRef value;
1112
1113 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1114 return get_primitive_id(bld_base, swizzle);
1115
1116 if (!reg->Register.Dimension)
1117 return NULL;
1118
1119 if (swizzle == ~0) {
1120 LLVMValueRef values[TGSI_NUM_CHANNELS];
1121 unsigned chan;
1122 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1123 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1124 }
1125 return lp_build_gather_values(bld_base->base.gallivm, values,
1126 TGSI_NUM_CHANNELS);
1127 }
1128
1129 /* Get the vertex offset parameter */
1130 vtx_offset_param = reg->Dimension.Index;
1131 if (vtx_offset_param < 2) {
1132 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1133 } else {
1134 assert(vtx_offset_param < 6);
1135 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1136 }
1137 vtx_offset = lp_build_mul_imm(uint,
1138 LLVMGetParam(ctx->main_fn,
1139 vtx_offset_param),
1140 4);
1141
1142 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1143 args[0] = ctx->esgs_ring;
1144 args[1] = vtx_offset;
1145 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
1146 args[3] = uint->zero;
1147 args[4] = uint->one; /* OFFEN */
1148 args[5] = uint->zero; /* IDXEN */
1149 args[6] = uint->one; /* GLC */
1150 args[7] = uint->zero; /* SLC */
1151 args[8] = uint->zero; /* TFE */
1152
1153 value = lp_build_intrinsic(gallivm->builder,
1154 "llvm.SI.buffer.load.dword.i32.i32",
1155 ctx->i32, args, 9,
1156 LP_FUNC_ATTR_READONLY);
1157 if (tgsi_type_is_64bit(type)) {
1158 LLVMValueRef value2;
1159 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
1160 value2 = lp_build_intrinsic(gallivm->builder,
1161 "llvm.SI.buffer.load.dword.i32.i32",
1162 ctx->i32, args, 9,
1163 LP_FUNC_ATTR_READONLY);
1164 return si_llvm_emit_fetch_64bit(bld_base, type,
1165 value, value2);
1166 }
1167 return LLVMBuildBitCast(gallivm->builder,
1168 value,
1169 tgsi2llvmtype(bld_base, type), "");
1170 }
1171
1172 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1173 {
1174 switch (interpolate) {
1175 case TGSI_INTERPOLATE_CONSTANT:
1176 return 0;
1177
1178 case TGSI_INTERPOLATE_LINEAR:
1179 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1180 return SI_PARAM_LINEAR_SAMPLE;
1181 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1182 return SI_PARAM_LINEAR_CENTROID;
1183 else
1184 return SI_PARAM_LINEAR_CENTER;
1185 break;
1186 case TGSI_INTERPOLATE_COLOR:
1187 case TGSI_INTERPOLATE_PERSPECTIVE:
1188 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1189 return SI_PARAM_PERSP_SAMPLE;
1190 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1191 return SI_PARAM_PERSP_CENTROID;
1192 else
1193 return SI_PARAM_PERSP_CENTER;
1194 break;
1195 default:
1196 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1197 return -1;
1198 }
1199 }
1200
1201 /**
1202 * Interpolate a fragment shader input.
1203 *
1204 * @param ctx context
1205 * @param input_index index of the input in hardware
1206 * @param semantic_name TGSI_SEMANTIC_*
1207 * @param semantic_index semantic index
1208 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1209 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1210 * @param interp_param interpolation weights (i,j)
1211 * @param prim_mask SI_PARAM_PRIM_MASK
1212 * @param face SI_PARAM_FRONT_FACE
1213 * @param result the return value (4 components)
1214 */
1215 static void interp_fs_input(struct si_shader_context *ctx,
1216 unsigned input_index,
1217 unsigned semantic_name,
1218 unsigned semantic_index,
1219 unsigned num_interp_inputs,
1220 unsigned colors_read_mask,
1221 LLVMValueRef interp_param,
1222 LLVMValueRef prim_mask,
1223 LLVMValueRef face,
1224 LLVMValueRef result[4])
1225 {
1226 struct lp_build_context *base = &ctx->soa.bld_base.base;
1227 struct lp_build_context *uint = &ctx->soa.bld_base.uint_bld;
1228 struct gallivm_state *gallivm = base->gallivm;
1229 const char *intr_name;
1230 LLVMValueRef attr_number;
1231
1232 unsigned chan;
1233
1234 attr_number = lp_build_const_int32(gallivm, input_index);
1235
1236 /* fs.constant returns the param from the middle vertex, so it's not
1237 * really useful for flat shading. It's meant to be used for custom
1238 * interpolation (but the intrinsic can't fetch from the other two
1239 * vertices).
1240 *
1241 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1242 * to do the right thing. The only reason we use fs.constant is that
1243 * fs.interp cannot be used on integers, because they can be equal
1244 * to NaN.
1245 */
1246 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
1247
1248 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1249 ctx->shader->key.part.ps.prolog.color_two_side) {
1250 LLVMValueRef args[4];
1251 LLVMValueRef is_face_positive;
1252 LLVMValueRef back_attr_number;
1253
1254 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1255 * otherwise it's at offset "num_inputs".
1256 */
1257 unsigned back_attr_offset = num_interp_inputs;
1258 if (semantic_index == 1 && colors_read_mask & 0xf)
1259 back_attr_offset += 1;
1260
1261 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1262
1263 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1264 face, uint->zero, "");
1265
1266 args[2] = prim_mask;
1267 args[3] = interp_param;
1268 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1269 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1270 LLVMValueRef front, back;
1271
1272 args[0] = llvm_chan;
1273 args[1] = attr_number;
1274 front = lp_build_intrinsic(gallivm->builder, intr_name,
1275 ctx->f32, args, args[3] ? 4 : 3,
1276 LP_FUNC_ATTR_READNONE);
1277
1278 args[1] = back_attr_number;
1279 back = lp_build_intrinsic(gallivm->builder, intr_name,
1280 ctx->f32, args, args[3] ? 4 : 3,
1281 LP_FUNC_ATTR_READNONE);
1282
1283 result[chan] = LLVMBuildSelect(gallivm->builder,
1284 is_face_positive,
1285 front,
1286 back,
1287 "");
1288 }
1289 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1290 LLVMValueRef args[4];
1291
1292 args[0] = uint->zero;
1293 args[1] = attr_number;
1294 args[2] = prim_mask;
1295 args[3] = interp_param;
1296 result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
1297 ctx->f32, args, args[3] ? 4 : 3,
1298 LP_FUNC_ATTR_READNONE);
1299 result[1] =
1300 result[2] = lp_build_const_float(gallivm, 0.0f);
1301 result[3] = lp_build_const_float(gallivm, 1.0f);
1302 } else {
1303 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1304 LLVMValueRef args[4];
1305 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1306
1307 args[0] = llvm_chan;
1308 args[1] = attr_number;
1309 args[2] = prim_mask;
1310 args[3] = interp_param;
1311 result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
1312 ctx->f32, args, args[3] ? 4 : 3,
1313 LP_FUNC_ATTR_READNONE);
1314 }
1315 }
1316 }
1317
1318 static void declare_input_fs(
1319 struct si_shader_context *radeon_bld,
1320 unsigned input_index,
1321 const struct tgsi_full_declaration *decl,
1322 LLVMValueRef out[4])
1323 {
1324 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
1325 struct si_shader_context *ctx =
1326 si_shader_context(&radeon_bld->soa.bld_base);
1327 struct si_shader *shader = ctx->shader;
1328 LLVMValueRef main_fn = radeon_bld->main_fn;
1329 LLVMValueRef interp_param = NULL;
1330 int interp_param_idx;
1331
1332 /* Get colors from input VGPRs (set by the prolog). */
1333 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1334 unsigned i = decl->Semantic.Index;
1335 unsigned colors_read = shader->selector->info.colors_read;
1336 unsigned mask = colors_read >> (i * 4);
1337 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1338 (i ? util_bitcount(colors_read & 0xf) : 0);
1339
1340 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1341 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1342 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1343 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1344 return;
1345 }
1346
1347 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1348 decl->Interp.Location);
1349 if (interp_param_idx == -1)
1350 return;
1351 else if (interp_param_idx) {
1352 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1353 }
1354
1355 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
1356 decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR &&
1357 ctx->shader->key.part.ps.prolog.flatshade_colors)
1358 interp_param = NULL; /* load the constant color */
1359
1360 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1361 decl->Semantic.Index, shader->selector->info.num_inputs,
1362 shader->selector->info.colors_read, interp_param,
1363 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1364 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1365 &out[0]);
1366 }
1367
1368 static LLVMValueRef get_sample_id(struct si_shader_context *radeon_bld)
1369 {
1370 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1371 SI_PARAM_ANCILLARY, 8, 4);
1372 }
1373
1374 /**
1375 * Set range metadata on an instruction. This can only be used on load and
1376 * call instructions. If you know an instruction can only produce the values
1377 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1378 * \p lo is the minimum value inclusive.
1379 * \p hi is the maximum value exclusive.
1380 */
1381 static void set_range_metadata(struct si_shader_context *ctx,
1382 LLVMValueRef value, unsigned lo, unsigned hi)
1383 {
1384 LLVMValueRef range_md, md_args[2];
1385 LLVMTypeRef type = LLVMTypeOf(value);
1386 LLVMContextRef context = LLVMGetTypeContext(type);
1387
1388 md_args[0] = LLVMConstInt(type, lo, false);
1389 md_args[1] = LLVMConstInt(type, hi, false);
1390 range_md = LLVMMDNodeInContext(context, md_args, 2);
1391 LLVMSetMetadata(value, ctx->range_md_kind, range_md);
1392 }
1393
1394 static LLVMValueRef get_thread_id(struct si_shader_context *ctx)
1395 {
1396 struct gallivm_state *gallivm = &ctx->gallivm;
1397 LLVMValueRef tid;
1398
1399 if (HAVE_LLVM < 0x0308) {
1400 tid = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid",
1401 ctx->i32, NULL, 0, LP_FUNC_ATTR_READNONE);
1402 } else {
1403 LLVMValueRef tid_args[2];
1404 tid_args[0] = lp_build_const_int32(gallivm, 0xffffffff);
1405 tid_args[1] = lp_build_const_int32(gallivm, 0);
1406 tid_args[1] = lp_build_intrinsic(gallivm->builder,
1407 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1408 tid_args, 2, LP_FUNC_ATTR_READNONE);
1409
1410 tid = lp_build_intrinsic(gallivm->builder,
1411 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1412 tid_args, 2, LP_FUNC_ATTR_READNONE);
1413 }
1414 set_range_metadata(ctx, tid, 0, 64);
1415 return tid;
1416 }
1417
1418 /**
1419 * Load a dword from a constant buffer.
1420 */
1421 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1422 LLVMValueRef resource,
1423 LLVMValueRef offset)
1424 {
1425 LLVMBuilderRef builder = ctx->gallivm.builder;
1426 LLVMValueRef args[2] = {resource, offset};
1427
1428 return lp_build_intrinsic(builder, "llvm.SI.load.const", ctx->f32, args, 2,
1429 LP_FUNC_ATTR_READNONE);
1430 }
1431
1432 static LLVMValueRef load_sample_position(struct si_shader_context *radeon_bld, LLVMValueRef sample_id)
1433 {
1434 struct si_shader_context *ctx =
1435 si_shader_context(&radeon_bld->soa.bld_base);
1436 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1437 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1438 LLVMBuilderRef builder = gallivm->builder;
1439 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1440 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1441 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1442
1443 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1444 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1445 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1446
1447 LLVMValueRef pos[4] = {
1448 buffer_load_const(ctx, resource, offset0),
1449 buffer_load_const(ctx, resource, offset1),
1450 lp_build_const_float(gallivm, 0),
1451 lp_build_const_float(gallivm, 0)
1452 };
1453
1454 return lp_build_gather_values(gallivm, pos, 4);
1455 }
1456
1457 static void declare_system_value(
1458 struct si_shader_context *radeon_bld,
1459 unsigned index,
1460 const struct tgsi_full_declaration *decl)
1461 {
1462 struct si_shader_context *ctx =
1463 si_shader_context(&radeon_bld->soa.bld_base);
1464 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1465 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1466 LLVMValueRef value = 0;
1467
1468 switch (decl->Semantic.Name) {
1469 case TGSI_SEMANTIC_INSTANCEID:
1470 value = LLVMGetParam(radeon_bld->main_fn,
1471 ctx->param_instance_id);
1472 break;
1473
1474 case TGSI_SEMANTIC_VERTEXID:
1475 value = LLVMBuildAdd(gallivm->builder,
1476 LLVMGetParam(radeon_bld->main_fn,
1477 ctx->param_vertex_id),
1478 LLVMGetParam(radeon_bld->main_fn,
1479 SI_PARAM_BASE_VERTEX), "");
1480 break;
1481
1482 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1483 value = LLVMGetParam(radeon_bld->main_fn,
1484 ctx->param_vertex_id);
1485 break;
1486
1487 case TGSI_SEMANTIC_BASEVERTEX:
1488 value = LLVMGetParam(radeon_bld->main_fn,
1489 SI_PARAM_BASE_VERTEX);
1490 break;
1491
1492 case TGSI_SEMANTIC_BASEINSTANCE:
1493 value = LLVMGetParam(radeon_bld->main_fn,
1494 SI_PARAM_START_INSTANCE);
1495 break;
1496
1497 case TGSI_SEMANTIC_DRAWID:
1498 value = LLVMGetParam(radeon_bld->main_fn,
1499 SI_PARAM_DRAWID);
1500 break;
1501
1502 case TGSI_SEMANTIC_INVOCATIONID:
1503 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1504 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1505 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1506 value = LLVMGetParam(radeon_bld->main_fn,
1507 SI_PARAM_GS_INSTANCE_ID);
1508 else
1509 assert(!"INVOCATIONID not implemented");
1510 break;
1511
1512 case TGSI_SEMANTIC_POSITION:
1513 {
1514 LLVMValueRef pos[4] = {
1515 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1516 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1517 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1518 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1519 LLVMGetParam(radeon_bld->main_fn,
1520 SI_PARAM_POS_W_FLOAT)),
1521 };
1522 value = lp_build_gather_values(gallivm, pos, 4);
1523 break;
1524 }
1525
1526 case TGSI_SEMANTIC_FACE:
1527 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1528 break;
1529
1530 case TGSI_SEMANTIC_SAMPLEID:
1531 value = get_sample_id(radeon_bld);
1532 break;
1533
1534 case TGSI_SEMANTIC_SAMPLEPOS: {
1535 LLVMValueRef pos[4] = {
1536 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1537 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1538 lp_build_const_float(gallivm, 0),
1539 lp_build_const_float(gallivm, 0)
1540 };
1541 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1542 TGSI_OPCODE_FRC, pos[0]);
1543 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1544 TGSI_OPCODE_FRC, pos[1]);
1545 value = lp_build_gather_values(gallivm, pos, 4);
1546 break;
1547 }
1548
1549 case TGSI_SEMANTIC_SAMPLEMASK:
1550 /* This can only occur with the OpenGL Core profile, which
1551 * doesn't support smoothing.
1552 */
1553 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1554 break;
1555
1556 case TGSI_SEMANTIC_TESSCOORD:
1557 {
1558 LLVMValueRef coord[4] = {
1559 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1560 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1561 bld->zero,
1562 bld->zero
1563 };
1564
1565 /* For triangles, the vector should be (u, v, 1-u-v). */
1566 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1567 PIPE_PRIM_TRIANGLES)
1568 coord[2] = lp_build_sub(bld, bld->one,
1569 lp_build_add(bld, coord[0], coord[1]));
1570
1571 value = lp_build_gather_values(gallivm, coord, 4);
1572 break;
1573 }
1574
1575 case TGSI_SEMANTIC_VERTICESIN:
1576 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1577 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1578 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1579 value = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 7);
1580 else
1581 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1582 break;
1583
1584 case TGSI_SEMANTIC_TESSINNER:
1585 case TGSI_SEMANTIC_TESSOUTER:
1586 {
1587 LLVMValueRef rw_buffers, buffer, base, addr;
1588 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1589
1590 rw_buffers = LLVMGetParam(ctx->main_fn,
1591 SI_PARAM_RW_BUFFERS);
1592 buffer = build_indexed_load_const(ctx, rw_buffers,
1593 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1594
1595 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1596 addr = get_tcs_tes_buffer_address(ctx, NULL,
1597 lp_build_const_int32(gallivm, param));
1598
1599 value = buffer_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1600 ~0, buffer, base, addr);
1601
1602 break;
1603 }
1604
1605 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1606 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1607 {
1608 LLVMValueRef buf, slot, val[4];
1609 int i, offset;
1610
1611 slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
1612 buf = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1613 buf = build_indexed_load_const(ctx, buf, slot);
1614 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1615
1616 for (i = 0; i < 4; i++)
1617 val[i] = buffer_load_const(ctx, buf,
1618 lp_build_const_int32(gallivm, (offset + i) * 4));
1619 value = lp_build_gather_values(gallivm, val, 4);
1620 break;
1621 }
1622
1623 case TGSI_SEMANTIC_PRIMID:
1624 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1625 break;
1626
1627 case TGSI_SEMANTIC_GRID_SIZE:
1628 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1629 break;
1630
1631 case TGSI_SEMANTIC_BLOCK_SIZE:
1632 {
1633 LLVMValueRef values[3];
1634 unsigned i;
1635 unsigned *properties = ctx->shader->selector->info.properties;
1636
1637 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1638 unsigned sizes[3] = {
1639 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1640 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1641 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1642 };
1643
1644 for (i = 0; i < 3; ++i)
1645 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1646
1647 value = lp_build_gather_values(gallivm, values, 3);
1648 } else {
1649 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_SIZE);
1650 }
1651 break;
1652 }
1653
1654 case TGSI_SEMANTIC_BLOCK_ID:
1655 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1656 break;
1657
1658 case TGSI_SEMANTIC_THREAD_ID:
1659 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1660 break;
1661
1662 #if HAVE_LLVM >= 0x0309
1663 case TGSI_SEMANTIC_HELPER_INVOCATION:
1664 value = lp_build_intrinsic(gallivm->builder,
1665 "llvm.amdgcn.ps.live",
1666 ctx->i1, NULL, 0,
1667 LP_FUNC_ATTR_READNONE);
1668 value = LLVMBuildNot(gallivm->builder, value, "");
1669 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1670 break;
1671 #endif
1672
1673 default:
1674 assert(!"unknown system value");
1675 return;
1676 }
1677
1678 radeon_bld->system_values[index] = value;
1679 }
1680
1681 static void declare_compute_memory(struct si_shader_context *radeon_bld,
1682 const struct tgsi_full_declaration *decl)
1683 {
1684 struct si_shader_context *ctx =
1685 si_shader_context(&radeon_bld->soa.bld_base);
1686 struct si_shader_selector *sel = ctx->shader->selector;
1687 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1688
1689 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1690 LLVMValueRef var;
1691
1692 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1693 assert(decl->Range.First == decl->Range.Last);
1694 assert(!ctx->shared_memory);
1695
1696 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1697 LLVMArrayType(ctx->i8, sel->local_size),
1698 "compute_lds",
1699 LOCAL_ADDR_SPACE);
1700 LLVMSetAlignment(var, 4);
1701
1702 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1703 }
1704
1705 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1706 {
1707 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1708 SI_PARAM_CONST_BUFFERS);
1709
1710 return build_indexed_load_const(ctx, list_ptr,
1711 LLVMConstInt(ctx->i32, i, 0));
1712 }
1713
1714 static LLVMValueRef fetch_constant(
1715 struct lp_build_tgsi_context *bld_base,
1716 const struct tgsi_full_src_register *reg,
1717 enum tgsi_opcode_type type,
1718 unsigned swizzle)
1719 {
1720 struct si_shader_context *ctx = si_shader_context(bld_base);
1721 struct lp_build_context *base = &bld_base->base;
1722 const struct tgsi_ind_register *ireg = &reg->Indirect;
1723 unsigned buf, idx;
1724
1725 LLVMValueRef addr, bufp;
1726 LLVMValueRef result;
1727
1728 if (swizzle == LP_CHAN_ALL) {
1729 unsigned chan;
1730 LLVMValueRef values[4];
1731 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1732 values[chan] = fetch_constant(bld_base, reg, type, chan);
1733
1734 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1735 }
1736
1737 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1738 idx = reg->Register.Index * 4 + swizzle;
1739
1740 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1741 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_CONST_BUFFERS);
1742 LLVMValueRef index;
1743 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1744 reg->Dimension.Index,
1745 SI_NUM_CONST_BUFFERS);
1746 bufp = build_indexed_load_const(ctx, ptr, index);
1747 } else
1748 bufp = load_const_buffer_desc(ctx, buf);
1749
1750 if (reg->Register.Indirect) {
1751 addr = ctx->soa.addr[ireg->Index][ireg->Swizzle];
1752 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1753 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1754 addr = lp_build_add(&bld_base->uint_bld, addr,
1755 lp_build_const_int32(base->gallivm, idx * 4));
1756 } else {
1757 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
1758 }
1759
1760 result = buffer_load_const(ctx, bufp, addr);
1761
1762 if (!tgsi_type_is_64bit(type))
1763 result = bitcast(bld_base, type, result);
1764 else {
1765 LLVMValueRef addr2, result2;
1766
1767 addr2 = lp_build_add(&bld_base->uint_bld, addr,
1768 LLVMConstInt(ctx->i32, 4, 0));
1769 result2 = buffer_load_const(ctx, bufp, addr2);
1770
1771 result = si_llvm_emit_fetch_64bit(bld_base, type,
1772 result, result2);
1773 }
1774 return result;
1775 }
1776
1777 /* Upper 16 bits must be zero. */
1778 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1779 LLVMValueRef val[2])
1780 {
1781 return LLVMBuildOr(gallivm->builder, val[0],
1782 LLVMBuildShl(gallivm->builder, val[1],
1783 lp_build_const_int32(gallivm, 16),
1784 ""), "");
1785 }
1786
1787 /* Upper 16 bits are ignored and will be dropped. */
1788 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1789 LLVMValueRef val[2])
1790 {
1791 LLVMValueRef v[2] = {
1792 LLVMBuildAnd(gallivm->builder, val[0],
1793 lp_build_const_int32(gallivm, 0xffff), ""),
1794 val[1],
1795 };
1796 return si_llvm_pack_two_int16(gallivm, v);
1797 }
1798
1799 /* Initialize arguments for the shader export intrinsic */
1800 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1801 LLVMValueRef *values,
1802 unsigned target,
1803 LLVMValueRef *args)
1804 {
1805 struct si_shader_context *ctx = si_shader_context(bld_base);
1806 struct lp_build_context *uint =
1807 &ctx->soa.bld_base.uint_bld;
1808 struct lp_build_context *base = &bld_base->base;
1809 struct gallivm_state *gallivm = base->gallivm;
1810 LLVMBuilderRef builder = base->gallivm->builder;
1811 LLVMValueRef val[4];
1812 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1813 unsigned chan;
1814 bool is_int8;
1815
1816 /* Default is 0xf. Adjusted below depending on the format. */
1817 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1818
1819 /* Specify whether the EXEC mask represents the valid mask */
1820 args[1] = uint->zero;
1821
1822 /* Specify whether this is the last export */
1823 args[2] = uint->zero;
1824
1825 /* Specify the target we are exporting */
1826 args[3] = lp_build_const_int32(base->gallivm, target);
1827
1828 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1829 const struct si_shader_key *key = &ctx->shader->key;
1830 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
1831 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1832
1833 assert(cbuf >= 0 && cbuf < 8);
1834 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1835 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
1836 }
1837
1838 args[4] = uint->zero; /* COMPR flag */
1839 args[5] = base->undef;
1840 args[6] = base->undef;
1841 args[7] = base->undef;
1842 args[8] = base->undef;
1843
1844 switch (spi_shader_col_format) {
1845 case V_028714_SPI_SHADER_ZERO:
1846 args[0] = uint->zero; /* writemask */
1847 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
1848 break;
1849
1850 case V_028714_SPI_SHADER_32_R:
1851 args[0] = uint->one; /* writemask */
1852 args[5] = values[0];
1853 break;
1854
1855 case V_028714_SPI_SHADER_32_GR:
1856 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
1857 args[5] = values[0];
1858 args[6] = values[1];
1859 break;
1860
1861 case V_028714_SPI_SHADER_32_AR:
1862 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
1863 args[5] = values[0];
1864 args[8] = values[3];
1865 break;
1866
1867 case V_028714_SPI_SHADER_FP16_ABGR:
1868 args[4] = uint->one; /* COMPR flag */
1869
1870 for (chan = 0; chan < 2; chan++) {
1871 LLVMValueRef pack_args[2] = {
1872 values[2 * chan],
1873 values[2 * chan + 1]
1874 };
1875 LLVMValueRef packed;
1876
1877 packed = lp_build_intrinsic(base->gallivm->builder,
1878 "llvm.SI.packf16",
1879 ctx->i32, pack_args, 2,
1880 LP_FUNC_ATTR_READNONE);
1881 args[chan + 5] =
1882 LLVMBuildBitCast(base->gallivm->builder,
1883 packed, ctx->f32, "");
1884 }
1885 break;
1886
1887 case V_028714_SPI_SHADER_UNORM16_ABGR:
1888 for (chan = 0; chan < 4; chan++) {
1889 val[chan] = si_llvm_saturate(bld_base, values[chan]);
1890 val[chan] = LLVMBuildFMul(builder, val[chan],
1891 lp_build_const_float(gallivm, 65535), "");
1892 val[chan] = LLVMBuildFAdd(builder, val[chan],
1893 lp_build_const_float(gallivm, 0.5), "");
1894 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1895 ctx->i32, "");
1896 }
1897
1898 args[4] = uint->one; /* COMPR flag */
1899 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1900 si_llvm_pack_two_int16(gallivm, val));
1901 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1902 si_llvm_pack_two_int16(gallivm, val+2));
1903 break;
1904
1905 case V_028714_SPI_SHADER_SNORM16_ABGR:
1906 for (chan = 0; chan < 4; chan++) {
1907 /* Clamp between [-1, 1]. */
1908 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1909 values[chan],
1910 lp_build_const_float(gallivm, 1));
1911 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1912 val[chan],
1913 lp_build_const_float(gallivm, -1));
1914 /* Convert to a signed integer in [-32767, 32767]. */
1915 val[chan] = LLVMBuildFMul(builder, val[chan],
1916 lp_build_const_float(gallivm, 32767), "");
1917 /* If positive, add 0.5, else add -0.5. */
1918 val[chan] = LLVMBuildFAdd(builder, val[chan],
1919 LLVMBuildSelect(builder,
1920 LLVMBuildFCmp(builder, LLVMRealOGE,
1921 val[chan], base->zero, ""),
1922 lp_build_const_float(gallivm, 0.5),
1923 lp_build_const_float(gallivm, -0.5), ""), "");
1924 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
1925 }
1926
1927 args[4] = uint->one; /* COMPR flag */
1928 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1929 si_llvm_pack_two_int32_as_int16(gallivm, val));
1930 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1931 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1932 break;
1933
1934 case V_028714_SPI_SHADER_UINT16_ABGR: {
1935 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1936 255 : 65535);
1937 /* Clamp. */
1938 for (chan = 0; chan < 4; chan++) {
1939 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1940 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1941 val[chan], max);
1942 }
1943
1944 args[4] = uint->one; /* COMPR flag */
1945 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1946 si_llvm_pack_two_int16(gallivm, val));
1947 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1948 si_llvm_pack_two_int16(gallivm, val+2));
1949 break;
1950 }
1951
1952 case V_028714_SPI_SHADER_SINT16_ABGR: {
1953 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1954 127 : 32767);
1955 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
1956 -128 : -32768);
1957 /* Clamp. */
1958 for (chan = 0; chan < 4; chan++) {
1959 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1960 val[chan] = lp_build_emit_llvm_binary(bld_base,
1961 TGSI_OPCODE_IMIN,
1962 val[chan], max);
1963 val[chan] = lp_build_emit_llvm_binary(bld_base,
1964 TGSI_OPCODE_IMAX,
1965 val[chan], min);
1966 }
1967
1968 args[4] = uint->one; /* COMPR flag */
1969 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1970 si_llvm_pack_two_int32_as_int16(gallivm, val));
1971 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1972 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1973 break;
1974 }
1975
1976 case V_028714_SPI_SHADER_32_ABGR:
1977 memcpy(&args[5], values, sizeof(values[0]) * 4);
1978 break;
1979 }
1980 }
1981
1982 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1983 LLVMValueRef alpha)
1984 {
1985 struct si_shader_context *ctx = si_shader_context(bld_base);
1986 struct gallivm_state *gallivm = bld_base->base.gallivm;
1987
1988 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
1989 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
1990 SI_PARAM_ALPHA_REF);
1991
1992 LLVMValueRef alpha_pass =
1993 lp_build_cmp(&bld_base->base,
1994 ctx->shader->key.part.ps.epilog.alpha_func,
1995 alpha, alpha_ref);
1996 LLVMValueRef arg =
1997 lp_build_select(&bld_base->base,
1998 alpha_pass,
1999 lp_build_const_float(gallivm, 1.0f),
2000 lp_build_const_float(gallivm, -1.0f));
2001
2002 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2003 ctx->voidt, &arg, 1, 0);
2004 } else {
2005 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
2006 ctx->voidt, NULL, 0, 0);
2007 }
2008 }
2009
2010 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2011 LLVMValueRef alpha,
2012 unsigned samplemask_param)
2013 {
2014 struct si_shader_context *ctx = si_shader_context(bld_base);
2015 struct gallivm_state *gallivm = bld_base->base.gallivm;
2016 LLVMValueRef coverage;
2017
2018 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2019 coverage = LLVMGetParam(ctx->main_fn,
2020 samplemask_param);
2021 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
2022
2023 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
2024 ctx->i32,
2025 &coverage, 1, LP_FUNC_ATTR_READNONE);
2026
2027 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
2028 ctx->f32, "");
2029
2030 coverage = LLVMBuildFMul(gallivm->builder, coverage,
2031 lp_build_const_float(gallivm,
2032 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2033
2034 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
2035 }
2036
2037 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2038 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
2039 {
2040 struct si_shader_context *ctx = si_shader_context(bld_base);
2041 struct lp_build_context *base = &bld_base->base;
2042 struct lp_build_context *uint = &ctx->soa.bld_base.uint_bld;
2043 unsigned reg_index;
2044 unsigned chan;
2045 unsigned const_chan;
2046 LLVMValueRef base_elt;
2047 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2048 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
2049 SI_VS_CONST_CLIP_PLANES);
2050 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
2051
2052 for (reg_index = 0; reg_index < 2; reg_index ++) {
2053 LLVMValueRef *args = pos[2 + reg_index];
2054
2055 args[5] =
2056 args[6] =
2057 args[7] =
2058 args[8] = lp_build_const_float(base->gallivm, 0.0f);
2059
2060 /* Compute dot products of position and user clip plane vectors */
2061 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2062 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2063 args[1] = lp_build_const_int32(base->gallivm,
2064 ((reg_index * 4 + chan) * 4 +
2065 const_chan) * 4);
2066 base_elt = buffer_load_const(ctx, const_resource,
2067 args[1]);
2068 args[5 + chan] =
2069 lp_build_add(base, args[5 + chan],
2070 lp_build_mul(base, base_elt,
2071 out_elts[const_chan]));
2072 }
2073 }
2074
2075 args[0] = lp_build_const_int32(base->gallivm, 0xf);
2076 args[1] = uint->zero;
2077 args[2] = uint->zero;
2078 args[3] = lp_build_const_int32(base->gallivm,
2079 V_008DFC_SQ_EXP_POS + 2 + reg_index);
2080 args[4] = uint->zero;
2081 }
2082 }
2083
2084 static void si_dump_streamout(struct pipe_stream_output_info *so)
2085 {
2086 unsigned i;
2087
2088 if (so->num_outputs)
2089 fprintf(stderr, "STREAMOUT\n");
2090
2091 for (i = 0; i < so->num_outputs; i++) {
2092 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2093 so->output[i].start_component;
2094 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2095 i, so->output[i].output_buffer,
2096 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2097 so->output[i].register_index,
2098 mask & 1 ? "x" : "",
2099 mask & 2 ? "y" : "",
2100 mask & 4 ? "z" : "",
2101 mask & 8 ? "w" : "");
2102 }
2103 }
2104
2105 /* On SI, the vertex shader is responsible for writing streamout data
2106 * to buffers. */
2107 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2108 struct si_shader_output_values *outputs,
2109 unsigned noutput)
2110 {
2111 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
2112 struct gallivm_state *gallivm = &ctx->gallivm;
2113 LLVMBuilderRef builder = gallivm->builder;
2114 int i, j;
2115 struct lp_build_if_state if_ctx;
2116 LLVMValueRef so_buffers[4];
2117 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2118 SI_PARAM_RW_BUFFERS);
2119
2120 /* Load the descriptors. */
2121 for (i = 0; i < 4; ++i) {
2122 if (ctx->shader->selector->so.stride[i]) {
2123 LLVMValueRef offset = lp_build_const_int32(gallivm,
2124 SI_VS_STREAMOUT_BUF0 + i);
2125
2126 so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
2127 }
2128 }
2129
2130 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2131 LLVMValueRef so_vtx_count =
2132 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2133
2134 LLVMValueRef tid = get_thread_id(ctx);
2135
2136 /* can_emit = tid < so_vtx_count; */
2137 LLVMValueRef can_emit =
2138 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2139
2140 LLVMValueRef stream_id =
2141 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
2142
2143 /* Emit the streamout code conditionally. This actually avoids
2144 * out-of-bounds buffer access. The hw tells us via the SGPR
2145 * (so_vtx_count) which threads are allowed to emit streamout data. */
2146 lp_build_if(&if_ctx, gallivm, can_emit);
2147 {
2148 /* The buffer offset is computed as follows:
2149 * ByteOffset = streamout_offset[buffer_id]*4 +
2150 * (streamout_write_index + thread_id)*stride[buffer_id] +
2151 * attrib_offset
2152 */
2153
2154 LLVMValueRef so_write_index =
2155 LLVMGetParam(ctx->main_fn,
2156 ctx->param_streamout_write_index);
2157
2158 /* Compute (streamout_write_index + thread_id). */
2159 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2160
2161 /* Compute the write offset for each enabled buffer. */
2162 LLVMValueRef so_write_offset[4] = {};
2163 for (i = 0; i < 4; i++) {
2164 if (!so->stride[i])
2165 continue;
2166
2167 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2168 ctx->param_streamout_offset[i]);
2169 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2170
2171 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2172 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2173 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2174 }
2175
2176 /* Write streamout data. */
2177 for (i = 0; i < so->num_outputs; i++) {
2178 unsigned buf_idx = so->output[i].output_buffer;
2179 unsigned reg = so->output[i].register_index;
2180 unsigned start = so->output[i].start_component;
2181 unsigned num_comps = so->output[i].num_components;
2182 unsigned stream = so->output[i].stream;
2183 LLVMValueRef out[4];
2184 struct lp_build_if_state if_ctx_stream;
2185
2186 assert(num_comps && num_comps <= 4);
2187 if (!num_comps || num_comps > 4)
2188 continue;
2189
2190 if (reg >= noutput)
2191 continue;
2192
2193 /* Load the output as int. */
2194 for (j = 0; j < num_comps; j++) {
2195 out[j] = LLVMBuildBitCast(builder,
2196 outputs[reg].values[start+j],
2197 ctx->i32, "");
2198 }
2199
2200 /* Pack the output. */
2201 LLVMValueRef vdata = NULL;
2202
2203 switch (num_comps) {
2204 case 1: /* as i32 */
2205 vdata = out[0];
2206 break;
2207 case 2: /* as v2i32 */
2208 case 3: /* as v4i32 (aligned to 4) */
2209 case 4: /* as v4i32 */
2210 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2211 for (j = 0; j < num_comps; j++) {
2212 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2213 LLVMConstInt(ctx->i32, j, 0), "");
2214 }
2215 break;
2216 }
2217
2218 LLVMValueRef can_emit_stream =
2219 LLVMBuildICmp(builder, LLVMIntEQ,
2220 stream_id,
2221 lp_build_const_int32(gallivm, stream), "");
2222
2223 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
2224 build_tbuffer_store_dwords(ctx, so_buffers[buf_idx],
2225 vdata, num_comps,
2226 so_write_offset[buf_idx],
2227 LLVMConstInt(ctx->i32, 0, 0),
2228 so->output[i].dst_offset*4);
2229 lp_build_endif(&if_ctx_stream);
2230 }
2231 }
2232 lp_build_endif(&if_ctx);
2233 }
2234
2235
2236 /* Generate export instructions for hardware VS shader stage */
2237 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2238 struct si_shader_output_values *outputs,
2239 unsigned noutput)
2240 {
2241 struct si_shader_context *ctx = si_shader_context(bld_base);
2242 struct si_shader *shader = ctx->shader;
2243 struct lp_build_context *base = &bld_base->base;
2244 struct lp_build_context *uint =
2245 &ctx->soa.bld_base.uint_bld;
2246 LLVMValueRef args[9];
2247 LLVMValueRef pos_args[4][9] = { { 0 } };
2248 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2249 unsigned semantic_name, semantic_index;
2250 unsigned target;
2251 unsigned param_count = 0;
2252 unsigned pos_idx;
2253 int i;
2254
2255 if (outputs && ctx->shader->selector->so.num_outputs) {
2256 si_llvm_emit_streamout(ctx, outputs, noutput);
2257 }
2258
2259 for (i = 0; i < noutput; i++) {
2260 semantic_name = outputs[i].name;
2261 semantic_index = outputs[i].sid;
2262
2263 handle_semantic:
2264 /* Select the correct target */
2265 switch(semantic_name) {
2266 case TGSI_SEMANTIC_PSIZE:
2267 psize_value = outputs[i].values[0];
2268 continue;
2269 case TGSI_SEMANTIC_EDGEFLAG:
2270 edgeflag_value = outputs[i].values[0];
2271 continue;
2272 case TGSI_SEMANTIC_LAYER:
2273 layer_value = outputs[i].values[0];
2274 semantic_name = TGSI_SEMANTIC_GENERIC;
2275 goto handle_semantic;
2276 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2277 viewport_index_value = outputs[i].values[0];
2278 semantic_name = TGSI_SEMANTIC_GENERIC;
2279 goto handle_semantic;
2280 case TGSI_SEMANTIC_POSITION:
2281 target = V_008DFC_SQ_EXP_POS;
2282 break;
2283 case TGSI_SEMANTIC_COLOR:
2284 case TGSI_SEMANTIC_BCOLOR:
2285 target = V_008DFC_SQ_EXP_PARAM + param_count;
2286 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2287 shader->info.vs_output_param_offset[i] = param_count;
2288 param_count++;
2289 break;
2290 case TGSI_SEMANTIC_CLIPDIST:
2291 if (shader->key.opt.hw_vs.clip_disable) {
2292 semantic_name = TGSI_SEMANTIC_GENERIC;
2293 goto handle_semantic;
2294 }
2295 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2296 break;
2297 case TGSI_SEMANTIC_CLIPVERTEX:
2298 if (shader->key.opt.hw_vs.clip_disable)
2299 continue;
2300 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2301 continue;
2302 case TGSI_SEMANTIC_PRIMID:
2303 case TGSI_SEMANTIC_FOG:
2304 case TGSI_SEMANTIC_TEXCOORD:
2305 case TGSI_SEMANTIC_GENERIC:
2306 target = V_008DFC_SQ_EXP_PARAM + param_count;
2307 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2308 shader->info.vs_output_param_offset[i] = param_count;
2309 param_count++;
2310 break;
2311 default:
2312 target = 0;
2313 fprintf(stderr,
2314 "Warning: SI unhandled vs output type:%d\n",
2315 semantic_name);
2316 }
2317
2318 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
2319
2320 if (target >= V_008DFC_SQ_EXP_POS &&
2321 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2322 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
2323 args, sizeof(args));
2324 } else {
2325 lp_build_intrinsic(base->gallivm->builder,
2326 "llvm.SI.export", ctx->voidt,
2327 args, 9, 0);
2328 }
2329
2330 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2331 semantic_name = TGSI_SEMANTIC_GENERIC;
2332 goto handle_semantic;
2333 }
2334 }
2335
2336 shader->info.nr_param_exports = param_count;
2337
2338 /* We need to add the position output manually if it's missing. */
2339 if (!pos_args[0][0]) {
2340 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
2341 pos_args[0][1] = uint->zero; /* EXEC mask */
2342 pos_args[0][2] = uint->zero; /* last export? */
2343 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
2344 pos_args[0][4] = uint->zero; /* COMPR flag */
2345 pos_args[0][5] = base->zero; /* X */
2346 pos_args[0][6] = base->zero; /* Y */
2347 pos_args[0][7] = base->zero; /* Z */
2348 pos_args[0][8] = base->one; /* W */
2349 }
2350
2351 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2352 if (shader->selector->info.writes_psize ||
2353 shader->selector->info.writes_edgeflag ||
2354 shader->selector->info.writes_viewport_index ||
2355 shader->selector->info.writes_layer) {
2356 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
2357 shader->selector->info.writes_psize |
2358 (shader->selector->info.writes_edgeflag << 1) |
2359 (shader->selector->info.writes_layer << 2) |
2360 (shader->selector->info.writes_viewport_index << 3));
2361 pos_args[1][1] = uint->zero; /* EXEC mask */
2362 pos_args[1][2] = uint->zero; /* last export? */
2363 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
2364 pos_args[1][4] = uint->zero; /* COMPR flag */
2365 pos_args[1][5] = base->zero; /* X */
2366 pos_args[1][6] = base->zero; /* Y */
2367 pos_args[1][7] = base->zero; /* Z */
2368 pos_args[1][8] = base->zero; /* W */
2369
2370 if (shader->selector->info.writes_psize)
2371 pos_args[1][5] = psize_value;
2372
2373 if (shader->selector->info.writes_edgeflag) {
2374 /* The output is a float, but the hw expects an integer
2375 * with the first bit containing the edge flag. */
2376 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2377 edgeflag_value,
2378 ctx->i32, "");
2379 edgeflag_value = lp_build_min(&bld_base->int_bld,
2380 edgeflag_value,
2381 bld_base->int_bld.one);
2382
2383 /* The LLVM intrinsic expects a float. */
2384 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
2385 edgeflag_value,
2386 ctx->f32, "");
2387 }
2388
2389 if (shader->selector->info.writes_layer)
2390 pos_args[1][7] = layer_value;
2391
2392 if (shader->selector->info.writes_viewport_index)
2393 pos_args[1][8] = viewport_index_value;
2394 }
2395
2396 for (i = 0; i < 4; i++)
2397 if (pos_args[i][0])
2398 shader->info.nr_pos_exports++;
2399
2400 pos_idx = 0;
2401 for (i = 0; i < 4; i++) {
2402 if (!pos_args[i][0])
2403 continue;
2404
2405 /* Specify the target we are exporting */
2406 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2407
2408 if (pos_idx == shader->info.nr_pos_exports)
2409 /* Specify that this is the last export */
2410 pos_args[i][2] = uint->one;
2411
2412 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2413 ctx->voidt, pos_args[i], 9, 0);
2414 }
2415 }
2416
2417 /**
2418 * Forward all outputs from the vertex shader to the TES. This is only used
2419 * for the fixed function TCS.
2420 */
2421 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2422 {
2423 struct si_shader_context *ctx = si_shader_context(bld_base);
2424 struct gallivm_state *gallivm = bld_base->base.gallivm;
2425 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2426 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2427 uint64_t inputs;
2428
2429 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2430
2431 rw_buffers = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2432 buffer = build_indexed_load_const(ctx, rw_buffers,
2433 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
2434
2435 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2436
2437 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
2438 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2439 lds_vertex_stride, "");
2440 lds_base = get_tcs_in_current_patch_offset(ctx);
2441 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2442
2443 inputs = ctx->shader->key.mono.tcs.inputs_to_copy;
2444 while (inputs) {
2445 unsigned i = u_bit_scan64(&inputs);
2446
2447 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2448 lp_build_const_int32(gallivm, 4 * i),
2449 "");
2450
2451 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2452 invocation_id,
2453 lp_build_const_int32(gallivm, i));
2454
2455 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2456 lds_ptr);
2457
2458 build_tbuffer_store_dwords(ctx, buffer, value, 4, buffer_addr,
2459 buffer_offset, 0);
2460 }
2461 }
2462
2463 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2464 LLVMValueRef rel_patch_id,
2465 LLVMValueRef invocation_id,
2466 LLVMValueRef tcs_out_current_patch_data_offset)
2467 {
2468 struct si_shader_context *ctx = si_shader_context(bld_base);
2469 struct gallivm_state *gallivm = bld_base->base.gallivm;
2470 struct si_shader *shader = ctx->shader;
2471 unsigned tess_inner_index, tess_outer_index;
2472 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2473 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2474 unsigned stride, outer_comps, inner_comps, i;
2475 struct lp_build_if_state if_ctx, inner_if_ctx;
2476
2477 si_llvm_emit_barrier(NULL, bld_base, NULL);
2478
2479 /* Do this only for invocation 0, because the tess levels are per-patch,
2480 * not per-vertex.
2481 *
2482 * This can't jump, because invocation 0 executes this. It should
2483 * at least mask out the loads and stores for other invocations.
2484 */
2485 lp_build_if(&if_ctx, gallivm,
2486 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2487 invocation_id, bld_base->uint_bld.zero, ""));
2488
2489 /* Determine the layout of one tess factor element in the buffer. */
2490 switch (shader->key.part.tcs.epilog.prim_mode) {
2491 case PIPE_PRIM_LINES:
2492 stride = 2; /* 2 dwords, 1 vec2 store */
2493 outer_comps = 2;
2494 inner_comps = 0;
2495 break;
2496 case PIPE_PRIM_TRIANGLES:
2497 stride = 4; /* 4 dwords, 1 vec4 store */
2498 outer_comps = 3;
2499 inner_comps = 1;
2500 break;
2501 case PIPE_PRIM_QUADS:
2502 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2503 outer_comps = 4;
2504 inner_comps = 2;
2505 break;
2506 default:
2507 assert(0);
2508 return;
2509 }
2510
2511 /* Load tess_inner and tess_outer from LDS.
2512 * Any invocation can write them, so we can't get them from a temporary.
2513 */
2514 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2515 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2516
2517 lds_base = tcs_out_current_patch_data_offset;
2518 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2519 lp_build_const_int32(gallivm,
2520 tess_inner_index * 4), "");
2521 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2522 lp_build_const_int32(gallivm,
2523 tess_outer_index * 4), "");
2524
2525 for (i = 0; i < outer_comps; i++)
2526 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2527 for (i = 0; i < inner_comps; i++)
2528 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2529
2530 /* Convert the outputs to vectors for stores. */
2531 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2532 vec1 = NULL;
2533
2534 if (stride > 4)
2535 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2536
2537 /* Get the buffer. */
2538 rw_buffers = LLVMGetParam(ctx->main_fn,
2539 SI_PARAM_RW_BUFFERS);
2540 buffer = build_indexed_load_const(ctx, rw_buffers,
2541 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2542
2543 /* Get the offset. */
2544 tf_base = LLVMGetParam(ctx->main_fn,
2545 SI_PARAM_TESS_FACTOR_OFFSET);
2546 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2547 lp_build_const_int32(gallivm, 4 * stride), "");
2548
2549 lp_build_if(&inner_if_ctx, gallivm,
2550 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2551 rel_patch_id, bld_base->uint_bld.zero, ""));
2552
2553 /* Store the dynamic HS control word. */
2554 build_tbuffer_store_dwords(ctx, buffer,
2555 lp_build_const_int32(gallivm, 0x80000000),
2556 1, lp_build_const_int32(gallivm, 0), tf_base, 0);
2557
2558 lp_build_endif(&inner_if_ctx);
2559
2560 /* Store the tessellation factors. */
2561 build_tbuffer_store_dwords(ctx, buffer, vec0,
2562 MIN2(stride, 4), byteoffset, tf_base, 4);
2563 if (vec1)
2564 build_tbuffer_store_dwords(ctx, buffer, vec1,
2565 stride - 4, byteoffset, tf_base, 20);
2566 lp_build_endif(&if_ctx);
2567 }
2568
2569 /* This only writes the tessellation factor levels. */
2570 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2571 {
2572 struct si_shader_context *ctx = si_shader_context(bld_base);
2573 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2574
2575 si_copy_tcs_inputs(bld_base);
2576
2577 rel_patch_id = get_rel_patch_id(ctx);
2578 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2579 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2580
2581 /* Return epilog parameters from this function. */
2582 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2583 LLVMValueRef ret = ctx->return_value;
2584 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2585 unsigned vgpr;
2586
2587 /* RW_BUFFERS pointer */
2588 rw_buffers = LLVMGetParam(ctx->main_fn,
2589 SI_PARAM_RW_BUFFERS);
2590 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2591 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2592 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2593 bld_base->uint_bld.zero, "");
2594 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2595 bld_base->uint_bld.one, "");
2596 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2597 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2598
2599 /* Tess factor buffer soffset is after user SGPRs. */
2600 tf_soffset = LLVMGetParam(ctx->main_fn,
2601 SI_PARAM_TESS_FACTOR_OFFSET);
2602 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2603 SI_TCS_NUM_USER_SGPR + 1, "");
2604
2605 /* VGPRs */
2606 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2607 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2608 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2609
2610 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2611 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2612 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2613 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2614 ctx->return_value = ret;
2615 }
2616
2617 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2618 {
2619 struct si_shader_context *ctx = si_shader_context(bld_base);
2620 struct si_shader *shader = ctx->shader;
2621 struct tgsi_shader_info *info = &shader->selector->info;
2622 struct gallivm_state *gallivm = bld_base->base.gallivm;
2623 unsigned i, chan;
2624 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
2625 ctx->param_rel_auto_id);
2626 LLVMValueRef vertex_dw_stride =
2627 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2628 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2629 vertex_dw_stride, "");
2630
2631 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2632 * its inputs from it. */
2633 for (i = 0; i < info->num_outputs; i++) {
2634 LLVMValueRef *out_ptr = ctx->soa.outputs[i];
2635 unsigned name = info->output_semantic_name[i];
2636 unsigned index = info->output_semantic_index[i];
2637 int param = si_shader_io_get_unique_index(name, index);
2638 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2639 lp_build_const_int32(gallivm, param * 4), "");
2640
2641 for (chan = 0; chan < 4; chan++) {
2642 lds_store(bld_base, chan, dw_addr,
2643 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2644 }
2645 }
2646 }
2647
2648 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2649 {
2650 struct si_shader_context *ctx = si_shader_context(bld_base);
2651 struct gallivm_state *gallivm = bld_base->base.gallivm;
2652 struct si_shader *es = ctx->shader;
2653 struct tgsi_shader_info *info = &es->selector->info;
2654 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
2655 ctx->param_es2gs_offset);
2656 unsigned chan;
2657 int i;
2658
2659 for (i = 0; i < info->num_outputs; i++) {
2660 LLVMValueRef *out_ptr =
2661 ctx->soa.outputs[i];
2662 int param_index;
2663
2664 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2665 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2666 continue;
2667
2668 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2669 info->output_semantic_index[i]);
2670
2671 for (chan = 0; chan < 4; chan++) {
2672 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2673 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2674
2675 build_tbuffer_store(ctx,
2676 ctx->esgs_ring,
2677 out_val, 1,
2678 LLVMGetUndef(ctx->i32), soffset,
2679 (4 * param_index + chan) * 4,
2680 V_008F0C_BUF_DATA_FORMAT_32,
2681 V_008F0C_BUF_NUM_FORMAT_UINT,
2682 0, 0, 1, 1, 0);
2683 }
2684 }
2685 }
2686
2687 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2688 {
2689 struct si_shader_context *ctx = si_shader_context(bld_base);
2690 struct gallivm_state *gallivm = bld_base->base.gallivm;
2691 LLVMValueRef args[2];
2692
2693 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2694 args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID);
2695 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2696 ctx->voidt, args, 2, 0);
2697 }
2698
2699 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2700 {
2701 struct si_shader_context *ctx = si_shader_context(bld_base);
2702 struct gallivm_state *gallivm = bld_base->base.gallivm;
2703 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2704 struct si_shader_output_values *outputs = NULL;
2705 int i,j;
2706
2707 assert(!ctx->shader->is_gs_copy_shader);
2708
2709 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2710
2711 /* Vertex color clamping.
2712 *
2713 * This uses a state constant loaded in a user data SGPR and
2714 * an IF statement is added that clamps all colors if the constant
2715 * is true.
2716 */
2717 if (ctx->type == PIPE_SHADER_VERTEX) {
2718 struct lp_build_if_state if_ctx;
2719 LLVMValueRef cond = NULL;
2720 LLVMValueRef addr, val;
2721
2722 for (i = 0; i < info->num_outputs; i++) {
2723 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2724 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2725 continue;
2726
2727 /* We've found a color. */
2728 if (!cond) {
2729 /* The state is in the first bit of the user SGPR. */
2730 cond = LLVMGetParam(ctx->main_fn,
2731 SI_PARAM_VS_STATE_BITS);
2732 cond = LLVMBuildTrunc(gallivm->builder, cond,
2733 ctx->i1, "");
2734 lp_build_if(&if_ctx, gallivm, cond);
2735 }
2736
2737 for (j = 0; j < 4; j++) {
2738 addr = ctx->soa.outputs[i][j];
2739 val = LLVMBuildLoad(gallivm->builder, addr, "");
2740 val = si_llvm_saturate(bld_base, val);
2741 LLVMBuildStore(gallivm->builder, val, addr);
2742 }
2743 }
2744
2745 if (cond)
2746 lp_build_endif(&if_ctx);
2747 }
2748
2749 for (i = 0; i < info->num_outputs; i++) {
2750 outputs[i].name = info->output_semantic_name[i];
2751 outputs[i].sid = info->output_semantic_index[i];
2752
2753 for (j = 0; j < 4; j++)
2754 outputs[i].values[j] =
2755 LLVMBuildLoad(gallivm->builder,
2756 ctx->soa.outputs[i][j],
2757 "");
2758 }
2759
2760 /* Return the primitive ID from the LLVM function. */
2761 ctx->return_value =
2762 LLVMBuildInsertValue(gallivm->builder,
2763 ctx->return_value,
2764 bitcast(bld_base, TGSI_TYPE_FLOAT,
2765 get_primitive_id(bld_base, 0)),
2766 VS_EPILOG_PRIMID_LOC, "");
2767
2768 si_llvm_export_vs(bld_base, outputs, i);
2769 FREE(outputs);
2770 }
2771
2772 struct si_ps_exports {
2773 unsigned num;
2774 LLVMValueRef args[10][9];
2775 };
2776
2777 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
2778 bool writes_samplemask)
2779 {
2780 if (writes_z) {
2781 /* Z needs 32 bits. */
2782 if (writes_samplemask)
2783 return V_028710_SPI_SHADER_32_ABGR;
2784 else if (writes_stencil)
2785 return V_028710_SPI_SHADER_32_GR;
2786 else
2787 return V_028710_SPI_SHADER_32_R;
2788 } else if (writes_stencil || writes_samplemask) {
2789 /* Both stencil and sample mask need only 16 bits. */
2790 return V_028710_SPI_SHADER_UINT16_ABGR;
2791 } else {
2792 return V_028710_SPI_SHADER_ZERO;
2793 }
2794 }
2795
2796 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2797 LLVMValueRef depth, LLVMValueRef stencil,
2798 LLVMValueRef samplemask, struct si_ps_exports *exp)
2799 {
2800 struct si_shader_context *ctx = si_shader_context(bld_base);
2801 struct lp_build_context *base = &bld_base->base;
2802 struct lp_build_context *uint = &bld_base->uint_bld;
2803 LLVMValueRef args[9];
2804 unsigned mask = 0;
2805 unsigned format = si_get_spi_shader_z_format(depth != NULL,
2806 stencil != NULL,
2807 samplemask != NULL);
2808
2809 assert(depth || stencil || samplemask);
2810
2811 args[1] = uint->one; /* whether the EXEC mask is valid */
2812 args[2] = uint->one; /* DONE bit */
2813
2814 /* Specify the target we are exporting */
2815 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2816
2817 args[4] = uint->zero; /* COMP flag */
2818 args[5] = base->undef; /* R, depth */
2819 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2820 args[7] = base->undef; /* B, sample mask */
2821 args[8] = base->undef; /* A, alpha to mask */
2822
2823 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
2824 assert(!depth);
2825 args[4] = uint->one; /* COMPR flag */
2826
2827 if (stencil) {
2828 /* Stencil should be in X[23:16]. */
2829 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
2830 stencil = LLVMBuildShl(base->gallivm->builder, stencil,
2831 LLVMConstInt(ctx->i32, 16, 0), "");
2832 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
2833 mask |= 0x3;
2834 }
2835 if (samplemask) {
2836 /* SampleMask should be in Y[15:0]. */
2837 args[6] = samplemask;
2838 mask |= 0xc;
2839 }
2840 } else {
2841 if (depth) {
2842 args[5] = depth;
2843 mask |= 0x1;
2844 }
2845 if (stencil) {
2846 args[6] = stencil;
2847 mask |= 0x2;
2848 }
2849 if (samplemask) {
2850 args[7] = samplemask;
2851 mask |= 0x4;
2852 }
2853 }
2854
2855 /* SI (except OLAND) has a bug that it only looks
2856 * at the X writemask component. */
2857 if (ctx->screen->b.chip_class == SI &&
2858 ctx->screen->b.family != CHIP_OLAND)
2859 mask |= 0x1;
2860
2861 /* Specify which components to enable */
2862 args[0] = lp_build_const_int32(base->gallivm, mask);
2863
2864 memcpy(exp->args[exp->num++], args, sizeof(args));
2865 }
2866
2867 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2868 LLVMValueRef *color, unsigned index,
2869 unsigned samplemask_param,
2870 bool is_last, struct si_ps_exports *exp)
2871 {
2872 struct si_shader_context *ctx = si_shader_context(bld_base);
2873 struct lp_build_context *base = &bld_base->base;
2874 int i;
2875
2876 /* Clamp color */
2877 if (ctx->shader->key.part.ps.epilog.clamp_color)
2878 for (i = 0; i < 4; i++)
2879 color[i] = si_llvm_saturate(bld_base, color[i]);
2880
2881 /* Alpha to one */
2882 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
2883 color[3] = base->one;
2884
2885 /* Alpha test */
2886 if (index == 0 &&
2887 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2888 si_alpha_test(bld_base, color[3]);
2889
2890 /* Line & polygon smoothing */
2891 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
2892 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
2893 samplemask_param);
2894
2895 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2896 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
2897 LLVMValueRef args[8][9];
2898 int c, last = -1;
2899
2900 /* Get the export arguments, also find out what the last one is. */
2901 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2902 si_llvm_init_export_args(bld_base, color,
2903 V_008DFC_SQ_EXP_MRT + c, args[c]);
2904 if (args[c][0] != bld_base->uint_bld.zero)
2905 last = c;
2906 }
2907
2908 /* Emit all exports. */
2909 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2910 if (is_last && last == c) {
2911 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2912 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
2913 } else if (args[c][0] == bld_base->uint_bld.zero)
2914 continue; /* unnecessary NULL export */
2915
2916 memcpy(exp->args[exp->num++], args[c], sizeof(args[c]));
2917 }
2918 } else {
2919 LLVMValueRef args[9];
2920
2921 /* Export */
2922 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2923 args);
2924 if (is_last) {
2925 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2926 args[2] = bld_base->uint_bld.one; /* DONE bit */
2927 } else if (args[0] == bld_base->uint_bld.zero)
2928 return; /* unnecessary NULL export */
2929
2930 memcpy(exp->args[exp->num++], args, sizeof(args));
2931 }
2932 }
2933
2934 static void si_emit_ps_exports(struct si_shader_context *ctx,
2935 struct si_ps_exports *exp)
2936 {
2937 for (unsigned i = 0; i < exp->num; i++)
2938 lp_build_intrinsic(ctx->gallivm.builder,
2939 "llvm.SI.export", ctx->voidt,
2940 exp->args[i], 9, 0);
2941 }
2942
2943 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2944 {
2945 struct si_shader_context *ctx = si_shader_context(bld_base);
2946 struct lp_build_context *base = &bld_base->base;
2947 struct lp_build_context *uint = &bld_base->uint_bld;
2948 LLVMValueRef args[9];
2949
2950 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
2951 args[1] = uint->one; /* whether the EXEC mask is valid */
2952 args[2] = uint->one; /* DONE bit */
2953 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2954 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
2955 args[5] = base->undef; /* R */
2956 args[6] = base->undef; /* G */
2957 args[7] = base->undef; /* B */
2958 args[8] = base->undef; /* A */
2959
2960 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2961 ctx->voidt, args, 9, 0);
2962 }
2963
2964 /**
2965 * Return PS outputs in this order:
2966 *
2967 * v[0:3] = color0.xyzw
2968 * v[4:7] = color1.xyzw
2969 * ...
2970 * vN+0 = Depth
2971 * vN+1 = Stencil
2972 * vN+2 = SampleMask
2973 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
2974 *
2975 * The alpha-ref SGPR is returned via its original location.
2976 */
2977 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
2978 {
2979 struct si_shader_context *ctx = si_shader_context(bld_base);
2980 struct si_shader *shader = ctx->shader;
2981 struct lp_build_context *base = &bld_base->base;
2982 struct tgsi_shader_info *info = &shader->selector->info;
2983 LLVMBuilderRef builder = base->gallivm->builder;
2984 unsigned i, j, first_vgpr, vgpr;
2985
2986 LLVMValueRef color[8][4] = {};
2987 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2988 LLVMValueRef ret;
2989
2990 /* Read the output values. */
2991 for (i = 0; i < info->num_outputs; i++) {
2992 unsigned semantic_name = info->output_semantic_name[i];
2993 unsigned semantic_index = info->output_semantic_index[i];
2994
2995 switch (semantic_name) {
2996 case TGSI_SEMANTIC_COLOR:
2997 assert(semantic_index < 8);
2998 for (j = 0; j < 4; j++) {
2999 LLVMValueRef ptr = ctx->soa.outputs[i][j];
3000 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3001 color[semantic_index][j] = result;
3002 }
3003 break;
3004 case TGSI_SEMANTIC_POSITION:
3005 depth = LLVMBuildLoad(builder,
3006 ctx->soa.outputs[i][2], "");
3007 break;
3008 case TGSI_SEMANTIC_STENCIL:
3009 stencil = LLVMBuildLoad(builder,
3010 ctx->soa.outputs[i][1], "");
3011 break;
3012 case TGSI_SEMANTIC_SAMPLEMASK:
3013 samplemask = LLVMBuildLoad(builder,
3014 ctx->soa.outputs[i][0], "");
3015 break;
3016 default:
3017 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3018 semantic_name);
3019 }
3020 }
3021
3022 /* Fill the return structure. */
3023 ret = ctx->return_value;
3024
3025 /* Set SGPRs. */
3026 ret = LLVMBuildInsertValue(builder, ret,
3027 bitcast(bld_base, TGSI_TYPE_SIGNED,
3028 LLVMGetParam(ctx->main_fn,
3029 SI_PARAM_ALPHA_REF)),
3030 SI_SGPR_ALPHA_REF, "");
3031
3032 /* Set VGPRs */
3033 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3034 for (i = 0; i < ARRAY_SIZE(color); i++) {
3035 if (!color[i][0])
3036 continue;
3037
3038 for (j = 0; j < 4; j++)
3039 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3040 }
3041 if (depth)
3042 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3043 if (stencil)
3044 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3045 if (samplemask)
3046 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3047
3048 /* Add the input sample mask for smoothing at the end. */
3049 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3050 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3051 ret = LLVMBuildInsertValue(builder, ret,
3052 LLVMGetParam(ctx->main_fn,
3053 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3054
3055 ctx->return_value = ret;
3056 }
3057
3058 /**
3059 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3060 * buffer in number of elements and return it as an i32.
3061 */
3062 static LLVMValueRef get_buffer_size(
3063 struct lp_build_tgsi_context *bld_base,
3064 LLVMValueRef descriptor)
3065 {
3066 struct si_shader_context *ctx = si_shader_context(bld_base);
3067 struct gallivm_state *gallivm = bld_base->base.gallivm;
3068 LLVMBuilderRef builder = gallivm->builder;
3069 LLVMValueRef size =
3070 LLVMBuildExtractElement(builder, descriptor,
3071 lp_build_const_int32(gallivm, 6), "");
3072
3073 if (ctx->screen->b.chip_class >= VI) {
3074 /* On VI, the descriptor contains the size in bytes,
3075 * but TXQ must return the size in elements.
3076 * The stride is always non-zero for resources using TXQ.
3077 */
3078 LLVMValueRef stride =
3079 LLVMBuildExtractElement(builder, descriptor,
3080 lp_build_const_int32(gallivm, 5), "");
3081 stride = LLVMBuildLShr(builder, stride,
3082 lp_build_const_int32(gallivm, 16), "");
3083 stride = LLVMBuildAnd(builder, stride,
3084 lp_build_const_int32(gallivm, 0x3FFF), "");
3085
3086 size = LLVMBuildUDiv(builder, size, stride, "");
3087 }
3088
3089 return size;
3090 }
3091
3092 /**
3093 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
3094 * intrinsic names).
3095 */
3096 static void build_type_name_for_intr(
3097 LLVMTypeRef type,
3098 char *buf, unsigned bufsize)
3099 {
3100 LLVMTypeRef elem_type = type;
3101
3102 assert(bufsize >= 8);
3103
3104 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
3105 int ret = snprintf(buf, bufsize, "v%u",
3106 LLVMGetVectorSize(type));
3107 if (ret < 0) {
3108 char *type_name = LLVMPrintTypeToString(type);
3109 fprintf(stderr, "Error building type name for: %s\n",
3110 type_name);
3111 return;
3112 }
3113 elem_type = LLVMGetElementType(type);
3114 buf += ret;
3115 bufsize -= ret;
3116 }
3117 switch (LLVMGetTypeKind(elem_type)) {
3118 default: break;
3119 case LLVMIntegerTypeKind:
3120 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
3121 break;
3122 case LLVMFloatTypeKind:
3123 snprintf(buf, bufsize, "f32");
3124 break;
3125 case LLVMDoubleTypeKind:
3126 snprintf(buf, bufsize, "f64");
3127 break;
3128 }
3129 }
3130
3131 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3132 struct lp_build_tgsi_context *bld_base,
3133 struct lp_build_emit_data *emit_data);
3134
3135 /* Prevent optimizations (at least of memory accesses) across the current
3136 * point in the program by emitting empty inline assembly that is marked as
3137 * having side effects.
3138 */
3139 static void emit_optimization_barrier(struct si_shader_context *ctx)
3140 {
3141 LLVMBuilderRef builder = ctx->gallivm.builder;
3142 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3143 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
3144 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3145 }
3146
3147 static void emit_waitcnt(struct si_shader_context *ctx)
3148 {
3149 struct gallivm_state *gallivm = &ctx->gallivm;
3150 LLVMBuilderRef builder = gallivm->builder;
3151 LLVMValueRef args[1] = {
3152 lp_build_const_int32(gallivm, 0xf70)
3153 };
3154 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3155 ctx->voidt, args, 1, 0);
3156 }
3157
3158 static void membar_emit(
3159 const struct lp_build_tgsi_action *action,
3160 struct lp_build_tgsi_context *bld_base,
3161 struct lp_build_emit_data *emit_data)
3162 {
3163 struct si_shader_context *ctx = si_shader_context(bld_base);
3164
3165 emit_waitcnt(ctx);
3166 }
3167
3168 static LLVMValueRef
3169 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3170 const struct tgsi_full_src_register *reg)
3171 {
3172 LLVMValueRef index;
3173 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3174 SI_PARAM_SHADER_BUFFERS);
3175
3176 if (!reg->Register.Indirect)
3177 index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
3178 else
3179 index = get_bounded_indirect_index(ctx, &reg->Indirect,
3180 reg->Register.Index,
3181 SI_NUM_SHADER_BUFFERS);
3182
3183 return build_indexed_load_const(ctx, rsrc_ptr, index);
3184 }
3185
3186 static bool tgsi_is_array_sampler(unsigned target)
3187 {
3188 return target == TGSI_TEXTURE_1D_ARRAY ||
3189 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3190 target == TGSI_TEXTURE_2D_ARRAY ||
3191 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3192 target == TGSI_TEXTURE_CUBE_ARRAY ||
3193 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3194 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3195 }
3196
3197 static bool tgsi_is_array_image(unsigned target)
3198 {
3199 return target == TGSI_TEXTURE_3D ||
3200 target == TGSI_TEXTURE_CUBE ||
3201 target == TGSI_TEXTURE_1D_ARRAY ||
3202 target == TGSI_TEXTURE_2D_ARRAY ||
3203 target == TGSI_TEXTURE_CUBE_ARRAY ||
3204 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3205 }
3206
3207 /**
3208 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3209 *
3210 * At least on Tonga, executing image stores on images with DCC enabled and
3211 * non-trivial can eventually lead to lockups. This can occur when an
3212 * application binds an image as read-only but then uses a shader that writes
3213 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3214 * program termination) in this case, but it doesn't cost much to be a bit
3215 * nicer: disabling DCC in the shader still leads to undefined results but
3216 * avoids the lockup.
3217 */
3218 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3219 LLVMValueRef rsrc)
3220 {
3221 if (ctx->screen->b.chip_class <= CIK) {
3222 return rsrc;
3223 } else {
3224 LLVMBuilderRef builder = ctx->gallivm.builder;
3225 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3226 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3227 LLVMValueRef tmp;
3228
3229 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3230 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3231 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3232 }
3233 }
3234
3235 /**
3236 * Load the resource descriptor for \p image.
3237 */
3238 static void
3239 image_fetch_rsrc(
3240 struct lp_build_tgsi_context *bld_base,
3241 const struct tgsi_full_src_register *image,
3242 bool is_store, unsigned target,
3243 LLVMValueRef *rsrc)
3244 {
3245 struct si_shader_context *ctx = si_shader_context(bld_base);
3246 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3247 SI_PARAM_IMAGES);
3248 LLVMValueRef index, tmp;
3249 bool dcc_off = target != TGSI_TEXTURE_BUFFER && is_store;
3250
3251 assert(image->Register.File == TGSI_FILE_IMAGE);
3252
3253 if (!image->Register.Indirect) {
3254 const struct tgsi_shader_info *info = bld_base->info;
3255
3256 index = LLVMConstInt(ctx->i32, image->Register.Index, 0);
3257
3258 if (info->images_writemask & (1 << image->Register.Index) &&
3259 target != TGSI_TEXTURE_BUFFER)
3260 dcc_off = true;
3261 } else {
3262 /* From the GL_ARB_shader_image_load_store extension spec:
3263 *
3264 * If a shader performs an image load, store, or atomic
3265 * operation using an image variable declared as an array,
3266 * and if the index used to select an individual element is
3267 * negative or greater than or equal to the size of the
3268 * array, the results of the operation are undefined but may
3269 * not lead to termination.
3270 */
3271 index = get_bounded_indirect_index(ctx, &image->Indirect,
3272 image->Register.Index,
3273 SI_NUM_IMAGES);
3274 }
3275
3276 tmp = build_indexed_load_const(ctx, rsrc_ptr, index);
3277 if (dcc_off)
3278 tmp = force_dcc_off(ctx, tmp);
3279 *rsrc = tmp;
3280 }
3281
3282 static LLVMValueRef image_fetch_coords(
3283 struct lp_build_tgsi_context *bld_base,
3284 const struct tgsi_full_instruction *inst,
3285 unsigned src)
3286 {
3287 struct gallivm_state *gallivm = bld_base->base.gallivm;
3288 LLVMBuilderRef builder = gallivm->builder;
3289 unsigned target = inst->Memory.Texture;
3290 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3291 LLVMValueRef coords[4];
3292 LLVMValueRef tmp;
3293 int chan;
3294
3295 for (chan = 0; chan < num_coords; ++chan) {
3296 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3297 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3298 coords[chan] = tmp;
3299 }
3300
3301 if (num_coords == 1)
3302 return coords[0];
3303
3304 if (num_coords == 3) {
3305 /* LLVM has difficulties lowering 3-element vectors. */
3306 coords[3] = bld_base->uint_bld.undef;
3307 num_coords = 4;
3308 }
3309
3310 return lp_build_gather_values(gallivm, coords, num_coords);
3311 }
3312
3313 /**
3314 * Append the extra mode bits that are used by image load and store.
3315 */
3316 static void image_append_args(
3317 struct si_shader_context *ctx,
3318 struct lp_build_emit_data * emit_data,
3319 unsigned target,
3320 bool atomic)
3321 {
3322 const struct tgsi_full_instruction *inst = emit_data->inst;
3323 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3324 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3325 LLVMValueRef r128 = i1false;
3326 LLVMValueRef da = tgsi_is_array_image(target) ? i1true : i1false;
3327 LLVMValueRef glc =
3328 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3329 i1true : i1false;
3330 LLVMValueRef slc = i1false;
3331 LLVMValueRef lwe = i1false;
3332
3333 if (atomic || (HAVE_LLVM <= 0x0309)) {
3334 emit_data->args[emit_data->arg_count++] = r128;
3335 emit_data->args[emit_data->arg_count++] = da;
3336 if (!atomic) {
3337 emit_data->args[emit_data->arg_count++] = glc;
3338 }
3339 emit_data->args[emit_data->arg_count++] = slc;
3340 return;
3341 }
3342
3343 /* HAVE_LLVM >= 0x0400 */
3344 emit_data->args[emit_data->arg_count++] = glc;
3345 emit_data->args[emit_data->arg_count++] = slc;
3346 emit_data->args[emit_data->arg_count++] = lwe;
3347 emit_data->args[emit_data->arg_count++] = da;
3348 }
3349
3350 /**
3351 * Given a 256 bit resource, extract the top half (which stores the buffer
3352 * resource in the case of textures and images).
3353 */
3354 static LLVMValueRef extract_rsrc_top_half(
3355 struct si_shader_context *ctx,
3356 LLVMValueRef rsrc)
3357 {
3358 struct gallivm_state *gallivm = &ctx->gallivm;
3359 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
3360 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
3361
3362 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, v2i128, "");
3363 rsrc = LLVMBuildExtractElement(gallivm->builder, rsrc, bld_base->uint_bld.one, "");
3364 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, "");
3365
3366 return rsrc;
3367 }
3368
3369 /**
3370 * Append the resource and indexing arguments for buffer intrinsics.
3371 *
3372 * \param rsrc the v4i32 buffer resource
3373 * \param index index into the buffer (stride-based)
3374 * \param offset byte offset into the buffer
3375 */
3376 static void buffer_append_args(
3377 struct si_shader_context *ctx,
3378 struct lp_build_emit_data *emit_data,
3379 LLVMValueRef rsrc,
3380 LLVMValueRef index,
3381 LLVMValueRef offset,
3382 bool atomic)
3383 {
3384 const struct tgsi_full_instruction *inst = emit_data->inst;
3385 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3386 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3387
3388 emit_data->args[emit_data->arg_count++] = rsrc;
3389 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3390 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3391 if (!atomic) {
3392 emit_data->args[emit_data->arg_count++] =
3393 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3394 i1true : i1false; /* glc */
3395 }
3396 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3397 }
3398
3399 static void load_fetch_args(
3400 struct lp_build_tgsi_context * bld_base,
3401 struct lp_build_emit_data * emit_data)
3402 {
3403 struct si_shader_context *ctx = si_shader_context(bld_base);
3404 struct gallivm_state *gallivm = bld_base->base.gallivm;
3405 const struct tgsi_full_instruction * inst = emit_data->inst;
3406 unsigned target = inst->Memory.Texture;
3407 LLVMValueRef rsrc;
3408
3409 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3410
3411 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3412 LLVMBuilderRef builder = gallivm->builder;
3413 LLVMValueRef offset;
3414 LLVMValueRef tmp;
3415
3416 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3417
3418 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3419 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3420
3421 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3422 offset, false);
3423 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3424 LLVMValueRef coords;
3425
3426 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
3427 coords = image_fetch_coords(bld_base, inst, 1);
3428
3429 if (target == TGSI_TEXTURE_BUFFER) {
3430 rsrc = extract_rsrc_top_half(ctx, rsrc);
3431 buffer_append_args(ctx, emit_data, rsrc, coords,
3432 bld_base->uint_bld.zero, false);
3433 } else {
3434 emit_data->args[0] = coords;
3435 emit_data->args[1] = rsrc;
3436 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3437 emit_data->arg_count = 3;
3438
3439 image_append_args(ctx, emit_data, target, false);
3440 }
3441 }
3442 }
3443
3444 static void load_emit_buffer(struct si_shader_context *ctx,
3445 struct lp_build_emit_data *emit_data)
3446 {
3447 const struct tgsi_full_instruction *inst = emit_data->inst;
3448 struct gallivm_state *gallivm = &ctx->gallivm;
3449 LLVMBuilderRef builder = gallivm->builder;
3450 uint writemask = inst->Dst[0].Register.WriteMask;
3451 uint count = util_last_bit(writemask);
3452 const char *intrinsic_name;
3453 LLVMTypeRef dst_type;
3454
3455 switch (count) {
3456 case 1:
3457 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3458 dst_type = ctx->f32;
3459 break;
3460 case 2:
3461 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3462 dst_type = LLVMVectorType(ctx->f32, 2);
3463 break;
3464 default: // 3 & 4
3465 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3466 dst_type = ctx->v4f32;
3467 count = 4;
3468 }
3469
3470 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3471 builder, intrinsic_name, dst_type,
3472 emit_data->args, emit_data->arg_count,
3473 LP_FUNC_ATTR_READONLY);
3474 }
3475
3476 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3477 const struct tgsi_full_instruction *inst,
3478 LLVMTypeRef type, int arg)
3479 {
3480 struct gallivm_state *gallivm = &ctx->gallivm;
3481 LLVMBuilderRef builder = gallivm->builder;
3482 LLVMValueRef offset, ptr;
3483 int addr_space;
3484
3485 offset = lp_build_emit_fetch(&ctx->soa.bld_base, inst, arg, 0);
3486 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3487
3488 ptr = ctx->shared_memory;
3489 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3490 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3491 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3492
3493 return ptr;
3494 }
3495
3496 static void load_emit_memory(
3497 struct si_shader_context *ctx,
3498 struct lp_build_emit_data *emit_data)
3499 {
3500 const struct tgsi_full_instruction *inst = emit_data->inst;
3501 struct lp_build_context *base = &ctx->soa.bld_base.base;
3502 struct gallivm_state *gallivm = &ctx->gallivm;
3503 LLVMBuilderRef builder = gallivm->builder;
3504 unsigned writemask = inst->Dst[0].Register.WriteMask;
3505 LLVMValueRef channels[4], ptr, derived_ptr, index;
3506 int chan;
3507
3508 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3509
3510 for (chan = 0; chan < 4; ++chan) {
3511 if (!(writemask & (1 << chan))) {
3512 channels[chan] = LLVMGetUndef(base->elem_type);
3513 continue;
3514 }
3515
3516 index = lp_build_const_int32(gallivm, chan);
3517 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3518 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3519 }
3520 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3521 }
3522
3523 static void get_image_intr_name(const char *base_name,
3524 LLVMTypeRef data_type,
3525 LLVMTypeRef coords_type,
3526 LLVMTypeRef rsrc_type,
3527 char *out_name, unsigned out_len)
3528 {
3529 char coords_type_name[8];
3530
3531 build_type_name_for_intr(coords_type, coords_type_name,
3532 sizeof(coords_type_name));
3533
3534 if (HAVE_LLVM <= 0x0309) {
3535 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
3536 } else {
3537 char data_type_name[8];
3538 char rsrc_type_name[8];
3539
3540 build_type_name_for_intr(data_type, data_type_name,
3541 sizeof(data_type_name));
3542 build_type_name_for_intr(rsrc_type, rsrc_type_name,
3543 sizeof(rsrc_type_name));
3544 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
3545 data_type_name, coords_type_name, rsrc_type_name);
3546 }
3547 }
3548
3549 static void load_emit(
3550 const struct lp_build_tgsi_action *action,
3551 struct lp_build_tgsi_context *bld_base,
3552 struct lp_build_emit_data *emit_data)
3553 {
3554 struct si_shader_context *ctx = si_shader_context(bld_base);
3555 struct gallivm_state *gallivm = bld_base->base.gallivm;
3556 LLVMBuilderRef builder = gallivm->builder;
3557 const struct tgsi_full_instruction * inst = emit_data->inst;
3558 char intrinsic_name[64];
3559
3560 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3561 load_emit_memory(ctx, emit_data);
3562 return;
3563 }
3564
3565 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3566 emit_waitcnt(ctx);
3567
3568 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3569 load_emit_buffer(ctx, emit_data);
3570 return;
3571 }
3572
3573 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3574 emit_data->output[emit_data->chan] =
3575 lp_build_intrinsic(
3576 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3577 emit_data->args, emit_data->arg_count,
3578 LP_FUNC_ATTR_READONLY);
3579 } else {
3580 get_image_intr_name("llvm.amdgcn.image.load",
3581 emit_data->dst_type, /* vdata */
3582 LLVMTypeOf(emit_data->args[0]), /* coords */
3583 LLVMTypeOf(emit_data->args[1]), /* rsrc */
3584 intrinsic_name, sizeof(intrinsic_name));
3585
3586 emit_data->output[emit_data->chan] =
3587 lp_build_intrinsic(
3588 builder, intrinsic_name, emit_data->dst_type,
3589 emit_data->args, emit_data->arg_count,
3590 LP_FUNC_ATTR_READONLY);
3591 }
3592 }
3593
3594 static void store_fetch_args(
3595 struct lp_build_tgsi_context * bld_base,
3596 struct lp_build_emit_data * emit_data)
3597 {
3598 struct si_shader_context *ctx = si_shader_context(bld_base);
3599 struct gallivm_state *gallivm = bld_base->base.gallivm;
3600 LLVMBuilderRef builder = gallivm->builder;
3601 const struct tgsi_full_instruction * inst = emit_data->inst;
3602 struct tgsi_full_src_register memory;
3603 LLVMValueRef chans[4];
3604 LLVMValueRef data;
3605 LLVMValueRef rsrc;
3606 unsigned chan;
3607
3608 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3609
3610 for (chan = 0; chan < 4; ++chan) {
3611 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3612 }
3613 data = lp_build_gather_values(gallivm, chans, 4);
3614
3615 emit_data->args[emit_data->arg_count++] = data;
3616
3617 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3618
3619 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3620 LLVMValueRef offset;
3621 LLVMValueRef tmp;
3622
3623 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3624
3625 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3626 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3627
3628 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3629 offset, false);
3630 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3631 unsigned target = inst->Memory.Texture;
3632 LLVMValueRef coords;
3633
3634 coords = image_fetch_coords(bld_base, inst, 0);
3635
3636 if (target == TGSI_TEXTURE_BUFFER) {
3637 image_fetch_rsrc(bld_base, &memory, true, target, &rsrc);
3638
3639 rsrc = extract_rsrc_top_half(ctx, rsrc);
3640 buffer_append_args(ctx, emit_data, rsrc, coords,
3641 bld_base->uint_bld.zero, false);
3642 } else {
3643 emit_data->args[1] = coords;
3644 image_fetch_rsrc(bld_base, &memory, true, target,
3645 &emit_data->args[2]);
3646 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3647 emit_data->arg_count = 4;
3648
3649 image_append_args(ctx, emit_data, target, false);
3650 }
3651 }
3652 }
3653
3654 static void store_emit_buffer(
3655 struct si_shader_context *ctx,
3656 struct lp_build_emit_data *emit_data)
3657 {
3658 const struct tgsi_full_instruction *inst = emit_data->inst;
3659 struct gallivm_state *gallivm = &ctx->gallivm;
3660 LLVMBuilderRef builder = gallivm->builder;
3661 struct lp_build_context *uint_bld = &ctx->soa.bld_base.uint_bld;
3662 LLVMValueRef base_data = emit_data->args[0];
3663 LLVMValueRef base_offset = emit_data->args[3];
3664 unsigned writemask = inst->Dst[0].Register.WriteMask;
3665
3666 while (writemask) {
3667 int start, count;
3668 const char *intrinsic_name;
3669 LLVMValueRef data;
3670 LLVMValueRef offset;
3671 LLVMValueRef tmp;
3672
3673 u_bit_scan_consecutive_range(&writemask, &start, &count);
3674
3675 /* Due to an LLVM limitation, split 3-element writes
3676 * into a 2-element and a 1-element write. */
3677 if (count == 3) {
3678 writemask |= 1 << (start + 2);
3679 count = 2;
3680 }
3681
3682 if (count == 4) {
3683 data = base_data;
3684 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3685 } else if (count == 2) {
3686 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3687
3688 tmp = LLVMBuildExtractElement(
3689 builder, base_data,
3690 lp_build_const_int32(gallivm, start), "");
3691 data = LLVMBuildInsertElement(
3692 builder, LLVMGetUndef(v2f32), tmp,
3693 uint_bld->zero, "");
3694
3695 tmp = LLVMBuildExtractElement(
3696 builder, base_data,
3697 lp_build_const_int32(gallivm, start + 1), "");
3698 data = LLVMBuildInsertElement(
3699 builder, data, tmp, uint_bld->one, "");
3700
3701 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3702 } else {
3703 assert(count == 1);
3704 data = LLVMBuildExtractElement(
3705 builder, base_data,
3706 lp_build_const_int32(gallivm, start), "");
3707 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3708 }
3709
3710 offset = base_offset;
3711 if (start != 0) {
3712 offset = LLVMBuildAdd(
3713 builder, offset,
3714 lp_build_const_int32(gallivm, start * 4), "");
3715 }
3716
3717 emit_data->args[0] = data;
3718 emit_data->args[3] = offset;
3719
3720 lp_build_intrinsic(
3721 builder, intrinsic_name, emit_data->dst_type,
3722 emit_data->args, emit_data->arg_count, 0);
3723 }
3724 }
3725
3726 static void store_emit_memory(
3727 struct si_shader_context *ctx,
3728 struct lp_build_emit_data *emit_data)
3729 {
3730 const struct tgsi_full_instruction *inst = emit_data->inst;
3731 struct gallivm_state *gallivm = &ctx->gallivm;
3732 struct lp_build_context *base = &ctx->soa.bld_base.base;
3733 LLVMBuilderRef builder = gallivm->builder;
3734 unsigned writemask = inst->Dst[0].Register.WriteMask;
3735 LLVMValueRef ptr, derived_ptr, data, index;
3736 int chan;
3737
3738 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3739
3740 for (chan = 0; chan < 4; ++chan) {
3741 if (!(writemask & (1 << chan))) {
3742 continue;
3743 }
3744 data = lp_build_emit_fetch(&ctx->soa.bld_base, inst, 1, chan);
3745 index = lp_build_const_int32(gallivm, chan);
3746 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3747 LLVMBuildStore(builder, data, derived_ptr);
3748 }
3749 }
3750
3751 static void store_emit(
3752 const struct lp_build_tgsi_action *action,
3753 struct lp_build_tgsi_context *bld_base,
3754 struct lp_build_emit_data *emit_data)
3755 {
3756 struct si_shader_context *ctx = si_shader_context(bld_base);
3757 struct gallivm_state *gallivm = bld_base->base.gallivm;
3758 LLVMBuilderRef builder = gallivm->builder;
3759 const struct tgsi_full_instruction * inst = emit_data->inst;
3760 unsigned target = inst->Memory.Texture;
3761 char intrinsic_name[64];
3762
3763 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3764 store_emit_memory(ctx, emit_data);
3765 return;
3766 }
3767
3768 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3769 emit_waitcnt(ctx);
3770
3771 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3772 store_emit_buffer(ctx, emit_data);
3773 return;
3774 }
3775
3776 if (target == TGSI_TEXTURE_BUFFER) {
3777 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3778 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3779 emit_data->dst_type, emit_data->args,
3780 emit_data->arg_count, 0);
3781 } else {
3782 get_image_intr_name("llvm.amdgcn.image.store",
3783 LLVMTypeOf(emit_data->args[0]), /* vdata */
3784 LLVMTypeOf(emit_data->args[1]), /* coords */
3785 LLVMTypeOf(emit_data->args[2]), /* rsrc */
3786 intrinsic_name, sizeof(intrinsic_name));
3787
3788 emit_data->output[emit_data->chan] =
3789 lp_build_intrinsic(
3790 builder, intrinsic_name, emit_data->dst_type,
3791 emit_data->args, emit_data->arg_count, 0);
3792 }
3793 }
3794
3795 static void atomic_fetch_args(
3796 struct lp_build_tgsi_context * bld_base,
3797 struct lp_build_emit_data * emit_data)
3798 {
3799 struct si_shader_context *ctx = si_shader_context(bld_base);
3800 struct gallivm_state *gallivm = bld_base->base.gallivm;
3801 LLVMBuilderRef builder = gallivm->builder;
3802 const struct tgsi_full_instruction * inst = emit_data->inst;
3803 LLVMValueRef data1, data2;
3804 LLVMValueRef rsrc;
3805 LLVMValueRef tmp;
3806
3807 emit_data->dst_type = bld_base->base.elem_type;
3808
3809 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
3810 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3811
3812 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3813 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
3814 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3815 }
3816
3817 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3818 * of arguments, which is reversed relative to TGSI (and GLSL)
3819 */
3820 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3821 emit_data->args[emit_data->arg_count++] = data2;
3822 emit_data->args[emit_data->arg_count++] = data1;
3823
3824 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3825 LLVMValueRef offset;
3826
3827 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3828
3829 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3830 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3831
3832 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3833 offset, true);
3834 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3835 unsigned target = inst->Memory.Texture;
3836 LLVMValueRef coords;
3837
3838 image_fetch_rsrc(bld_base, &inst->Src[0], true, target, &rsrc);
3839 coords = image_fetch_coords(bld_base, inst, 1);
3840
3841 if (target == TGSI_TEXTURE_BUFFER) {
3842 rsrc = extract_rsrc_top_half(ctx, rsrc);
3843 buffer_append_args(ctx, emit_data, rsrc, coords,
3844 bld_base->uint_bld.zero, true);
3845 } else {
3846 emit_data->args[emit_data->arg_count++] = coords;
3847 emit_data->args[emit_data->arg_count++] = rsrc;
3848
3849 image_append_args(ctx, emit_data, target, true);
3850 }
3851 }
3852 }
3853
3854 static void atomic_emit_memory(struct si_shader_context *ctx,
3855 struct lp_build_emit_data *emit_data) {
3856 struct gallivm_state *gallivm = &ctx->gallivm;
3857 LLVMBuilderRef builder = gallivm->builder;
3858 const struct tgsi_full_instruction * inst = emit_data->inst;
3859 LLVMValueRef ptr, result, arg;
3860
3861 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
3862
3863 arg = lp_build_emit_fetch(&ctx->soa.bld_base, inst, 2, 0);
3864 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
3865
3866 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3867 LLVMValueRef new_data;
3868 new_data = lp_build_emit_fetch(&ctx->soa.bld_base,
3869 inst, 3, 0);
3870
3871 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
3872
3873 #if HAVE_LLVM >= 0x309
3874 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
3875 LLVMAtomicOrderingSequentiallyConsistent,
3876 LLVMAtomicOrderingSequentiallyConsistent,
3877 false);
3878 #endif
3879
3880 result = LLVMBuildExtractValue(builder, result, 0, "");
3881 } else {
3882 LLVMAtomicRMWBinOp op;
3883
3884 switch(inst->Instruction.Opcode) {
3885 case TGSI_OPCODE_ATOMUADD:
3886 op = LLVMAtomicRMWBinOpAdd;
3887 break;
3888 case TGSI_OPCODE_ATOMXCHG:
3889 op = LLVMAtomicRMWBinOpXchg;
3890 break;
3891 case TGSI_OPCODE_ATOMAND:
3892 op = LLVMAtomicRMWBinOpAnd;
3893 break;
3894 case TGSI_OPCODE_ATOMOR:
3895 op = LLVMAtomicRMWBinOpOr;
3896 break;
3897 case TGSI_OPCODE_ATOMXOR:
3898 op = LLVMAtomicRMWBinOpXor;
3899 break;
3900 case TGSI_OPCODE_ATOMUMIN:
3901 op = LLVMAtomicRMWBinOpUMin;
3902 break;
3903 case TGSI_OPCODE_ATOMUMAX:
3904 op = LLVMAtomicRMWBinOpUMax;
3905 break;
3906 case TGSI_OPCODE_ATOMIMIN:
3907 op = LLVMAtomicRMWBinOpMin;
3908 break;
3909 case TGSI_OPCODE_ATOMIMAX:
3910 op = LLVMAtomicRMWBinOpMax;
3911 break;
3912 default:
3913 unreachable("unknown atomic opcode");
3914 }
3915
3916 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
3917 LLVMAtomicOrderingSequentiallyConsistent,
3918 false);
3919 }
3920 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
3921 }
3922
3923 static void atomic_emit(
3924 const struct lp_build_tgsi_action *action,
3925 struct lp_build_tgsi_context *bld_base,
3926 struct lp_build_emit_data *emit_data)
3927 {
3928 struct si_shader_context *ctx = si_shader_context(bld_base);
3929 struct gallivm_state *gallivm = bld_base->base.gallivm;
3930 LLVMBuilderRef builder = gallivm->builder;
3931 const struct tgsi_full_instruction * inst = emit_data->inst;
3932 char intrinsic_name[40];
3933 LLVMValueRef tmp;
3934
3935 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3936 atomic_emit_memory(ctx, emit_data);
3937 return;
3938 }
3939
3940 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
3941 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3942 snprintf(intrinsic_name, sizeof(intrinsic_name),
3943 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
3944 } else {
3945 LLVMValueRef coords;
3946 char coords_type[8];
3947
3948 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3949 coords = emit_data->args[2];
3950 else
3951 coords = emit_data->args[1];
3952
3953 build_type_name_for_intr(LLVMTypeOf(coords), coords_type, sizeof(coords_type));
3954 snprintf(intrinsic_name, sizeof(intrinsic_name),
3955 "llvm.amdgcn.image.atomic.%s.%s",
3956 action->intr_name, coords_type);
3957 }
3958
3959 tmp = lp_build_intrinsic(
3960 builder, intrinsic_name, bld_base->uint_bld.elem_type,
3961 emit_data->args, emit_data->arg_count, 0);
3962 emit_data->output[emit_data->chan] =
3963 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
3964 }
3965
3966 static void resq_fetch_args(
3967 struct lp_build_tgsi_context * bld_base,
3968 struct lp_build_emit_data * emit_data)
3969 {
3970 struct si_shader_context *ctx = si_shader_context(bld_base);
3971 struct gallivm_state *gallivm = bld_base->base.gallivm;
3972 const struct tgsi_full_instruction *inst = emit_data->inst;
3973 const struct tgsi_full_src_register *reg = &inst->Src[0];
3974
3975 emit_data->dst_type = ctx->v4i32;
3976
3977 if (reg->Register.File == TGSI_FILE_BUFFER) {
3978 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
3979 emit_data->arg_count = 1;
3980 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3981 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
3982 &emit_data->args[0]);
3983 emit_data->arg_count = 1;
3984 } else {
3985 emit_data->args[0] = bld_base->uint_bld.zero; /* mip level */
3986 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
3987 &emit_data->args[1]);
3988 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3989 emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
3990 emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
3991 emit_data->args[5] = tgsi_is_array_image(inst->Memory.Texture) ?
3992 bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da */
3993 emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
3994 emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
3995 emit_data->args[8] = bld_base->uint_bld.zero; /* tfe */
3996 emit_data->args[9] = bld_base->uint_bld.zero; /* lwe */
3997 emit_data->arg_count = 10;
3998 }
3999 }
4000
4001 static void resq_emit(
4002 const struct lp_build_tgsi_action *action,
4003 struct lp_build_tgsi_context *bld_base,
4004 struct lp_build_emit_data *emit_data)
4005 {
4006 struct gallivm_state *gallivm = bld_base->base.gallivm;
4007 LLVMBuilderRef builder = gallivm->builder;
4008 const struct tgsi_full_instruction *inst = emit_data->inst;
4009 LLVMValueRef out;
4010
4011 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4012 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4013 lp_build_const_int32(gallivm, 2), "");
4014 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4015 out = get_buffer_size(bld_base, emit_data->args[0]);
4016 } else {
4017 out = lp_build_intrinsic(
4018 builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
4019 emit_data->args, emit_data->arg_count,
4020 LP_FUNC_ATTR_READNONE);
4021
4022 /* Divide the number of layers by 6 to get the number of cubes. */
4023 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
4024 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
4025 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
4026
4027 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4028 z = LLVMBuildSDiv(builder, z, imm6, "");
4029 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4030 }
4031 }
4032
4033 emit_data->output[emit_data->chan] = out;
4034 }
4035
4036 static void set_tex_fetch_args(struct si_shader_context *ctx,
4037 struct lp_build_emit_data *emit_data,
4038 unsigned opcode, unsigned target,
4039 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4040 LLVMValueRef *param, unsigned count,
4041 unsigned dmask)
4042 {
4043 struct gallivm_state *gallivm = &ctx->gallivm;
4044 unsigned num_args;
4045 unsigned is_rect = target == TGSI_TEXTURE_RECT;
4046
4047 /* Pad to power of two vector */
4048 while (count < util_next_power_of_two(count))
4049 param[count++] = LLVMGetUndef(ctx->i32);
4050
4051 /* Texture coordinates. */
4052 if (count > 1)
4053 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
4054 else
4055 emit_data->args[0] = param[0];
4056
4057 /* Resource. */
4058 emit_data->args[1] = res_ptr;
4059 num_args = 2;
4060
4061 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
4062 emit_data->dst_type = ctx->v4i32;
4063 else {
4064 emit_data->dst_type = ctx->v4f32;
4065
4066 emit_data->args[num_args++] = samp_ptr;
4067 }
4068
4069 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
4070 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
4071 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
4072 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
4073 tgsi_is_array_sampler(target)); /* da */
4074 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
4075 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
4076 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
4077 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
4078
4079 emit_data->arg_count = num_args;
4080 }
4081
4082 static const struct lp_build_tgsi_action tex_action;
4083
4084 enum desc_type {
4085 DESC_IMAGE,
4086 DESC_FMASK,
4087 DESC_SAMPLER
4088 };
4089
4090 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
4091 {
4092 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
4093 CONST_ADDR_SPACE);
4094 }
4095
4096 /**
4097 * Load an image view, fmask view. or sampler state descriptor.
4098 */
4099 static LLVMValueRef load_sampler_desc_custom(struct si_shader_context *ctx,
4100 LLVMValueRef list, LLVMValueRef index,
4101 enum desc_type type)
4102 {
4103 struct gallivm_state *gallivm = &ctx->gallivm;
4104 LLVMBuilderRef builder = gallivm->builder;
4105
4106 switch (type) {
4107 case DESC_IMAGE:
4108 /* The image is at [0:7]. */
4109 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4110 break;
4111 case DESC_FMASK:
4112 /* The FMASK is at [8:15]. */
4113 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4114 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4115 break;
4116 case DESC_SAMPLER:
4117 /* The sampler state is at [12:15]. */
4118 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4119 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4120 list = LLVMBuildPointerCast(builder, list,
4121 const_array(ctx->v4i32, 0), "");
4122 break;
4123 }
4124
4125 return build_indexed_load_const(ctx, list, index);
4126 }
4127
4128 static LLVMValueRef load_sampler_desc(struct si_shader_context *ctx,
4129 LLVMValueRef index, enum desc_type type)
4130 {
4131 LLVMValueRef list = LLVMGetParam(ctx->main_fn,
4132 SI_PARAM_SAMPLERS);
4133
4134 return load_sampler_desc_custom(ctx, list, index, type);
4135 }
4136
4137 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4138 *
4139 * SI-CI:
4140 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4141 * filtering manually. The driver sets img7 to a mask clearing
4142 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4143 * s_and_b32 samp0, samp0, img7
4144 *
4145 * VI:
4146 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4147 */
4148 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4149 LLVMValueRef res, LLVMValueRef samp)
4150 {
4151 LLVMBuilderRef builder = ctx->gallivm.builder;
4152 LLVMValueRef img7, samp0;
4153
4154 if (ctx->screen->b.chip_class >= VI)
4155 return samp;
4156
4157 img7 = LLVMBuildExtractElement(builder, res,
4158 LLVMConstInt(ctx->i32, 7, 0), "");
4159 samp0 = LLVMBuildExtractElement(builder, samp,
4160 LLVMConstInt(ctx->i32, 0, 0), "");
4161 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4162 return LLVMBuildInsertElement(builder, samp, samp0,
4163 LLVMConstInt(ctx->i32, 0, 0), "");
4164 }
4165
4166 static void tex_fetch_ptrs(
4167 struct lp_build_tgsi_context *bld_base,
4168 struct lp_build_emit_data *emit_data,
4169 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4170 {
4171 struct si_shader_context *ctx = si_shader_context(bld_base);
4172 const struct tgsi_full_instruction *inst = emit_data->inst;
4173 unsigned target = inst->Texture.Texture;
4174 unsigned sampler_src;
4175 unsigned sampler_index;
4176 LLVMValueRef index;
4177
4178 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4179 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
4180
4181 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
4182 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
4183
4184 index = get_bounded_indirect_index(ctx,
4185 &reg->Indirect,
4186 reg->Register.Index,
4187 SI_NUM_SAMPLERS);
4188 } else {
4189 index = LLVMConstInt(ctx->i32, sampler_index, 0);
4190 }
4191
4192 *res_ptr = load_sampler_desc(ctx, index, DESC_IMAGE);
4193
4194 if (target == TGSI_TEXTURE_2D_MSAA ||
4195 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4196 if (samp_ptr)
4197 *samp_ptr = NULL;
4198 if (fmask_ptr)
4199 *fmask_ptr = load_sampler_desc(ctx, index, DESC_FMASK);
4200 } else {
4201 if (samp_ptr) {
4202 *samp_ptr = load_sampler_desc(ctx, index, DESC_SAMPLER);
4203 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4204 }
4205 if (fmask_ptr)
4206 *fmask_ptr = NULL;
4207 }
4208 }
4209
4210 static void txq_fetch_args(
4211 struct lp_build_tgsi_context *bld_base,
4212 struct lp_build_emit_data *emit_data)
4213 {
4214 struct si_shader_context *ctx = si_shader_context(bld_base);
4215 struct gallivm_state *gallivm = bld_base->base.gallivm;
4216 LLVMBuilderRef builder = gallivm->builder;
4217 const struct tgsi_full_instruction *inst = emit_data->inst;
4218 unsigned target = inst->Texture.Texture;
4219 LLVMValueRef res_ptr;
4220 LLVMValueRef address;
4221
4222 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4223
4224 if (target == TGSI_TEXTURE_BUFFER) {
4225 /* Read the size from the buffer descriptor directly. */
4226 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4227 emit_data->args[0] = get_buffer_size(bld_base, res);
4228 return;
4229 }
4230
4231 /* Textures - set the mip level. */
4232 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4233
4234 set_tex_fetch_args(ctx, emit_data, TGSI_OPCODE_TXQ, target, res_ptr,
4235 NULL, &address, 1, 0xf);
4236 }
4237
4238 static void txq_emit(const struct lp_build_tgsi_action *action,
4239 struct lp_build_tgsi_context *bld_base,
4240 struct lp_build_emit_data *emit_data)
4241 {
4242 struct lp_build_context *base = &bld_base->base;
4243 unsigned target = emit_data->inst->Texture.Texture;
4244
4245 if (target == TGSI_TEXTURE_BUFFER) {
4246 /* Just return the buffer size. */
4247 emit_data->output[emit_data->chan] = emit_data->args[0];
4248 return;
4249 }
4250
4251 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4252 base->gallivm->builder, "llvm.SI.getresinfo.i32",
4253 emit_data->dst_type, emit_data->args, emit_data->arg_count,
4254 LP_FUNC_ATTR_READNONE);
4255
4256 /* Divide the number of layers by 6 to get the number of cubes. */
4257 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4258 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4259 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4260 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4261 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4262
4263 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4264 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4265 z = LLVMBuildSDiv(builder, z, six, "");
4266
4267 emit_data->output[emit_data->chan] =
4268 LLVMBuildInsertElement(builder, v4, z, two, "");
4269 }
4270 }
4271
4272 static void tex_fetch_args(
4273 struct lp_build_tgsi_context *bld_base,
4274 struct lp_build_emit_data *emit_data)
4275 {
4276 struct si_shader_context *ctx = si_shader_context(bld_base);
4277 struct gallivm_state *gallivm = bld_base->base.gallivm;
4278 const struct tgsi_full_instruction *inst = emit_data->inst;
4279 unsigned opcode = inst->Instruction.Opcode;
4280 unsigned target = inst->Texture.Texture;
4281 LLVMValueRef coords[5], derivs[6];
4282 LLVMValueRef address[16];
4283 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4284 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4285 unsigned count = 0;
4286 unsigned chan;
4287 unsigned num_deriv_channels = 0;
4288 bool has_offset = inst->Texture.NumOffsets > 0;
4289 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4290 unsigned dmask = 0xf;
4291
4292 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4293
4294 if (target == TGSI_TEXTURE_BUFFER) {
4295 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
4296
4297 /* Bitcast and truncate v8i32 to v16i8. */
4298 LLVMValueRef res = res_ptr;
4299 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
4300 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
4301 res = LLVMBuildBitCast(gallivm->builder, res, ctx->v16i8, "");
4302
4303 emit_data->dst_type = ctx->v4f32;
4304 emit_data->args[0] = res;
4305 emit_data->args[1] = bld_base->uint_bld.zero;
4306 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4307 emit_data->arg_count = 3;
4308 return;
4309 }
4310
4311 /* Fetch and project texture coordinates */
4312 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4313 for (chan = 0; chan < 3; chan++ ) {
4314 coords[chan] = lp_build_emit_fetch(bld_base,
4315 emit_data->inst, 0,
4316 chan);
4317 if (opcode == TGSI_OPCODE_TXP)
4318 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4319 TGSI_OPCODE_DIV,
4320 coords[chan],
4321 coords[3]);
4322 }
4323
4324 if (opcode == TGSI_OPCODE_TXP)
4325 coords[3] = bld_base->base.one;
4326
4327 /* Pack offsets. */
4328 if (has_offset && opcode != TGSI_OPCODE_TXF) {
4329 /* The offsets are six-bit signed integers packed like this:
4330 * X=[5:0], Y=[13:8], and Z=[21:16].
4331 */
4332 LLVMValueRef offset[3], pack;
4333
4334 assert(inst->Texture.NumOffsets == 1);
4335
4336 for (chan = 0; chan < 3; chan++) {
4337 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4338 emit_data->inst, 0, chan);
4339 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4340 lp_build_const_int32(gallivm, 0x3f), "");
4341 if (chan)
4342 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4343 lp_build_const_int32(gallivm, chan*8), "");
4344 }
4345
4346 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4347 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4348 address[count++] = pack;
4349 }
4350
4351 /* Pack LOD bias value */
4352 if (opcode == TGSI_OPCODE_TXB)
4353 address[count++] = coords[3];
4354 if (opcode == TGSI_OPCODE_TXB2)
4355 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4356
4357 /* Pack depth comparison value */
4358 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4359 LLVMValueRef z;
4360
4361 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4362 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4363 } else {
4364 assert(ref_pos >= 0);
4365 z = coords[ref_pos];
4366 }
4367
4368 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4369 * so the depth comparison value isn't clamped for Z16 and
4370 * Z24 anymore. Do it manually here.
4371 *
4372 * It's unnecessary if the original texture format was
4373 * Z32_FLOAT, but we don't know that here.
4374 */
4375 if (ctx->screen->b.chip_class == VI)
4376 z = si_llvm_saturate(bld_base, z);
4377
4378 address[count++] = z;
4379 }
4380
4381 /* Pack user derivatives */
4382 if (opcode == TGSI_OPCODE_TXD) {
4383 int param, num_src_deriv_channels;
4384
4385 switch (target) {
4386 case TGSI_TEXTURE_3D:
4387 num_src_deriv_channels = 3;
4388 num_deriv_channels = 3;
4389 break;
4390 case TGSI_TEXTURE_2D:
4391 case TGSI_TEXTURE_SHADOW2D:
4392 case TGSI_TEXTURE_RECT:
4393 case TGSI_TEXTURE_SHADOWRECT:
4394 case TGSI_TEXTURE_2D_ARRAY:
4395 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4396 num_src_deriv_channels = 2;
4397 num_deriv_channels = 2;
4398 break;
4399 case TGSI_TEXTURE_CUBE:
4400 case TGSI_TEXTURE_SHADOWCUBE:
4401 case TGSI_TEXTURE_CUBE_ARRAY:
4402 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4403 /* Cube derivatives will be converted to 2D. */
4404 num_src_deriv_channels = 3;
4405 num_deriv_channels = 2;
4406 break;
4407 case TGSI_TEXTURE_1D:
4408 case TGSI_TEXTURE_SHADOW1D:
4409 case TGSI_TEXTURE_1D_ARRAY:
4410 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4411 num_src_deriv_channels = 1;
4412 num_deriv_channels = 1;
4413 break;
4414 default:
4415 unreachable("invalid target");
4416 }
4417
4418 for (param = 0; param < 2; param++)
4419 for (chan = 0; chan < num_src_deriv_channels; chan++)
4420 derivs[param * num_src_deriv_channels + chan] =
4421 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4422 }
4423
4424 if (target == TGSI_TEXTURE_CUBE ||
4425 target == TGSI_TEXTURE_CUBE_ARRAY ||
4426 target == TGSI_TEXTURE_SHADOWCUBE ||
4427 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4428 si_prepare_cube_coords(bld_base, emit_data, coords, derivs);
4429
4430 if (opcode == TGSI_OPCODE_TXD)
4431 for (int i = 0; i < num_deriv_channels * 2; i++)
4432 address[count++] = derivs[i];
4433
4434 /* Pack texture coordinates */
4435 address[count++] = coords[0];
4436 if (num_coords > 1)
4437 address[count++] = coords[1];
4438 if (num_coords > 2)
4439 address[count++] = coords[2];
4440
4441 /* Pack LOD or sample index */
4442 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4443 address[count++] = coords[3];
4444 else if (opcode == TGSI_OPCODE_TXL2)
4445 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4446
4447 if (count > 16) {
4448 assert(!"Cannot handle more than 16 texture address parameters");
4449 count = 16;
4450 }
4451
4452 for (chan = 0; chan < count; chan++ ) {
4453 address[chan] = LLVMBuildBitCast(gallivm->builder,
4454 address[chan], ctx->i32, "");
4455 }
4456
4457 /* Adjust the sample index according to FMASK.
4458 *
4459 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4460 * which is the identity mapping. Each nibble says which physical sample
4461 * should be fetched to get that sample.
4462 *
4463 * For example, 0x11111100 means there are only 2 samples stored and
4464 * the second sample covers 3/4 of the pixel. When reading samples 0
4465 * and 1, return physical sample 0 (determined by the first two 0s
4466 * in FMASK), otherwise return physical sample 1.
4467 *
4468 * The sample index should be adjusted as follows:
4469 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4470 */
4471 if (target == TGSI_TEXTURE_2D_MSAA ||
4472 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4473 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4474 struct lp_build_emit_data txf_emit_data = *emit_data;
4475 LLVMValueRef txf_address[4];
4476 unsigned txf_count = count;
4477 struct tgsi_full_instruction inst = {};
4478
4479 memcpy(txf_address, address, sizeof(txf_address));
4480
4481 if (target == TGSI_TEXTURE_2D_MSAA) {
4482 txf_address[2] = bld_base->uint_bld.zero;
4483 }
4484 txf_address[3] = bld_base->uint_bld.zero;
4485
4486 /* Read FMASK using TXF. */
4487 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4488 inst.Texture.Texture = target;
4489 txf_emit_data.inst = &inst;
4490 txf_emit_data.chan = 0;
4491 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
4492 target, fmask_ptr, NULL,
4493 txf_address, txf_count, 0xf);
4494 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4495
4496 /* Initialize some constants. */
4497 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4498 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4499
4500 /* Apply the formula. */
4501 LLVMValueRef fmask =
4502 LLVMBuildExtractElement(gallivm->builder,
4503 txf_emit_data.output[0],
4504 uint_bld->zero, "");
4505
4506 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4507
4508 LLVMValueRef sample_index4 =
4509 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4510
4511 LLVMValueRef shifted_fmask =
4512 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4513
4514 LLVMValueRef final_sample =
4515 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4516
4517 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4518 * resource descriptor is 0 (invalid),
4519 */
4520 LLVMValueRef fmask_desc =
4521 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4522 ctx->v8i32, "");
4523
4524 LLVMValueRef fmask_word1 =
4525 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4526 uint_bld->one, "");
4527
4528 LLVMValueRef word1_is_nonzero =
4529 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4530 fmask_word1, uint_bld->zero, "");
4531
4532 /* Replace the MSAA sample index. */
4533 address[sample_chan] =
4534 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4535 final_sample, address[sample_chan], "");
4536 }
4537
4538 if (opcode == TGSI_OPCODE_TXF) {
4539 /* add tex offsets */
4540 if (inst->Texture.NumOffsets) {
4541 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4542 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
4543 const struct tgsi_texture_offset *off = inst->TexOffsets;
4544
4545 assert(inst->Texture.NumOffsets == 1);
4546
4547 switch (target) {
4548 case TGSI_TEXTURE_3D:
4549 address[2] = lp_build_add(uint_bld, address[2],
4550 bld->immediates[off->Index][off->SwizzleZ]);
4551 /* fall through */
4552 case TGSI_TEXTURE_2D:
4553 case TGSI_TEXTURE_SHADOW2D:
4554 case TGSI_TEXTURE_RECT:
4555 case TGSI_TEXTURE_SHADOWRECT:
4556 case TGSI_TEXTURE_2D_ARRAY:
4557 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4558 address[1] =
4559 lp_build_add(uint_bld, address[1],
4560 bld->immediates[off->Index][off->SwizzleY]);
4561 /* fall through */
4562 case TGSI_TEXTURE_1D:
4563 case TGSI_TEXTURE_SHADOW1D:
4564 case TGSI_TEXTURE_1D_ARRAY:
4565 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4566 address[0] =
4567 lp_build_add(uint_bld, address[0],
4568 bld->immediates[off->Index][off->SwizzleX]);
4569 break;
4570 /* texture offsets do not apply to other texture targets */
4571 }
4572 }
4573 }
4574
4575 if (opcode == TGSI_OPCODE_TG4) {
4576 unsigned gather_comp = 0;
4577
4578 /* DMASK was repurposed for GATHER4. 4 components are always
4579 * returned and DMASK works like a swizzle - it selects
4580 * the component to fetch. The only valid DMASK values are
4581 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4582 * (red,red,red,red) etc.) The ISA document doesn't mention
4583 * this.
4584 */
4585
4586 /* Get the component index from src1.x for Gather4. */
4587 if (!tgsi_is_shadow_target(target)) {
4588 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4589 LLVMValueRef comp_imm;
4590 struct tgsi_src_register src1 = inst->Src[1].Register;
4591
4592 assert(src1.File == TGSI_FILE_IMMEDIATE);
4593
4594 comp_imm = imms[src1.Index][src1.SwizzleX];
4595 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4596 gather_comp = CLAMP(gather_comp, 0, 3);
4597 }
4598
4599 dmask = 1 << gather_comp;
4600 }
4601
4602 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
4603 samp_ptr, address, count, dmask);
4604 }
4605
4606 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
4607 * incorrectly forces nearest filtering if the texture format is integer.
4608 * The only effect it has on Gather4, which always returns 4 texels for
4609 * bilinear filtering, is that the final coordinates are off by 0.5 of
4610 * the texel size.
4611 *
4612 * The workaround is to subtract 0.5 from the unnormalized coordinates,
4613 * or (0.5 / size) from the normalized coordinates.
4614 */
4615 static void si_lower_gather4_integer(struct si_shader_context *ctx,
4616 struct lp_build_emit_data *emit_data,
4617 const char *intr_name,
4618 unsigned coord_vgpr_index)
4619 {
4620 LLVMBuilderRef builder = ctx->gallivm.builder;
4621 LLVMValueRef coord = emit_data->args[0];
4622 LLVMValueRef half_texel[2];
4623 int c;
4624
4625 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_RECT ||
4626 emit_data->inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
4627 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
4628 } else {
4629 struct tgsi_full_instruction txq_inst = {};
4630 struct lp_build_emit_data txq_emit_data = {};
4631
4632 /* Query the texture size. */
4633 txq_inst.Texture.Texture = emit_data->inst->Texture.Texture;
4634 txq_emit_data.inst = &txq_inst;
4635 txq_emit_data.dst_type = ctx->v4i32;
4636 set_tex_fetch_args(ctx, &txq_emit_data, TGSI_OPCODE_TXQ,
4637 txq_inst.Texture.Texture,
4638 emit_data->args[1], NULL,
4639 &ctx->soa.bld_base.uint_bld.zero,
4640 1, 0xf);
4641 txq_emit(NULL, &ctx->soa.bld_base, &txq_emit_data);
4642
4643 /* Compute -0.5 / size. */
4644 for (c = 0; c < 2; c++) {
4645 half_texel[c] =
4646 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
4647 LLVMConstInt(ctx->i32, c, 0), "");
4648 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
4649 half_texel[c] =
4650 lp_build_emit_llvm_unary(&ctx->soa.bld_base,
4651 TGSI_OPCODE_RCP, half_texel[c]);
4652 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
4653 LLVMConstReal(ctx->f32, -0.5), "");
4654 }
4655 }
4656
4657 for (c = 0; c < 2; c++) {
4658 LLVMValueRef tmp;
4659 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
4660
4661 tmp = LLVMBuildExtractElement(builder, coord, index, "");
4662 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4663 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
4664 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4665 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
4666 }
4667
4668 emit_data->args[0] = coord;
4669 emit_data->output[emit_data->chan] =
4670 lp_build_intrinsic(builder, intr_name, emit_data->dst_type,
4671 emit_data->args, emit_data->arg_count,
4672 LP_FUNC_ATTR_READNONE);
4673 }
4674
4675 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4676 struct lp_build_tgsi_context *bld_base,
4677 struct lp_build_emit_data *emit_data)
4678 {
4679 struct si_shader_context *ctx = si_shader_context(bld_base);
4680 struct lp_build_context *base = &bld_base->base;
4681 const struct tgsi_full_instruction *inst = emit_data->inst;
4682 unsigned opcode = inst->Instruction.Opcode;
4683 unsigned target = inst->Texture.Texture;
4684 char intr_name[127];
4685 bool has_offset = inst->Texture.NumOffsets > 0;
4686 bool is_shadow = tgsi_is_shadow_target(target);
4687 char type[64];
4688 const char *name = "llvm.SI.image.sample";
4689 const char *infix = "";
4690
4691 if (target == TGSI_TEXTURE_BUFFER) {
4692 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4693 base->gallivm->builder,
4694 "llvm.SI.vs.load.input", emit_data->dst_type,
4695 emit_data->args, emit_data->arg_count,
4696 LP_FUNC_ATTR_READNONE);
4697 return;
4698 }
4699
4700 switch (opcode) {
4701 case TGSI_OPCODE_TXF:
4702 name = target == TGSI_TEXTURE_2D_MSAA ||
4703 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4704 "llvm.SI.image.load" :
4705 "llvm.SI.image.load.mip";
4706 is_shadow = false;
4707 has_offset = false;
4708 break;
4709 case TGSI_OPCODE_LODQ:
4710 name = "llvm.SI.getlod";
4711 is_shadow = false;
4712 has_offset = false;
4713 break;
4714 case TGSI_OPCODE_TEX:
4715 case TGSI_OPCODE_TEX2:
4716 case TGSI_OPCODE_TXP:
4717 if (ctx->type != PIPE_SHADER_FRAGMENT)
4718 infix = ".lz";
4719 break;
4720 case TGSI_OPCODE_TXB:
4721 case TGSI_OPCODE_TXB2:
4722 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4723 infix = ".b";
4724 break;
4725 case TGSI_OPCODE_TXL:
4726 case TGSI_OPCODE_TXL2:
4727 infix = ".l";
4728 break;
4729 case TGSI_OPCODE_TXD:
4730 infix = ".d";
4731 break;
4732 case TGSI_OPCODE_TG4:
4733 name = "llvm.SI.gather4";
4734 infix = ".lz";
4735 break;
4736 default:
4737 assert(0);
4738 return;
4739 }
4740
4741 /* Add the type and suffixes .c, .o if needed. */
4742 build_type_name_for_intr(LLVMTypeOf(emit_data->args[0]), type, sizeof(type));
4743 sprintf(intr_name, "%s%s%s%s.%s",
4744 name, is_shadow ? ".c" : "", infix,
4745 has_offset ? ".o" : "", type);
4746
4747 /* The hardware needs special lowering for Gather4 with integer formats. */
4748 if (opcode == TGSI_OPCODE_TG4) {
4749 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4750 /* This will also work with non-constant indexing because of how
4751 * glsl_to_tgsi works and we intent to preserve that behavior.
4752 */
4753 const unsigned src_idx = 2;
4754 unsigned sampler = inst->Src[src_idx].Register.Index;
4755
4756 assert(inst->Src[src_idx].Register.File == TGSI_FILE_SAMPLER);
4757
4758 if (info->sampler_type[sampler] == TGSI_RETURN_TYPE_SINT ||
4759 info->sampler_type[sampler] == TGSI_RETURN_TYPE_UINT) {
4760 /* Texture coordinates start after:
4761 * {offset, bias, z-compare, derivatives}
4762 * Only the offset and z-compare can occur here.
4763 */
4764 si_lower_gather4_integer(ctx, emit_data, intr_name,
4765 (int)has_offset + (int)is_shadow);
4766 return;
4767 }
4768 }
4769
4770 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4771 base->gallivm->builder, intr_name, emit_data->dst_type,
4772 emit_data->args, emit_data->arg_count,
4773 LP_FUNC_ATTR_READNONE);
4774 }
4775
4776 static void si_llvm_emit_txqs(
4777 const struct lp_build_tgsi_action *action,
4778 struct lp_build_tgsi_context *bld_base,
4779 struct lp_build_emit_data *emit_data)
4780 {
4781 struct si_shader_context *ctx = si_shader_context(bld_base);
4782 struct gallivm_state *gallivm = bld_base->base.gallivm;
4783 LLVMBuilderRef builder = gallivm->builder;
4784 LLVMValueRef res, samples;
4785 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4786
4787 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4788
4789
4790 /* Read the samples from the descriptor directly. */
4791 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4792 samples = LLVMBuildExtractElement(
4793 builder, res,
4794 lp_build_const_int32(gallivm, 3), "");
4795 samples = LLVMBuildLShr(builder, samples,
4796 lp_build_const_int32(gallivm, 16), "");
4797 samples = LLVMBuildAnd(builder, samples,
4798 lp_build_const_int32(gallivm, 0xf), "");
4799 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
4800 samples, "");
4801
4802 emit_data->output[emit_data->chan] = samples;
4803 }
4804
4805 /*
4806 * SI implements derivatives using the local data store (LDS)
4807 * All writes to the LDS happen in all executing threads at
4808 * the same time. TID is the Thread ID for the current
4809 * thread and is a value between 0 and 63, representing
4810 * the thread's position in the wavefront.
4811 *
4812 * For the pixel shader threads are grouped into quads of four pixels.
4813 * The TIDs of the pixels of a quad are:
4814 *
4815 * +------+------+
4816 * |4n + 0|4n + 1|
4817 * +------+------+
4818 * |4n + 2|4n + 3|
4819 * +------+------+
4820 *
4821 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
4822 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
4823 * the current pixel's column, and masking with 0xfffffffe yields the TID
4824 * of the left pixel of the current pixel's row.
4825 *
4826 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
4827 * adding 2 yields the TID of the pixel below the top pixel.
4828 */
4829 /* masks for thread ID. */
4830 #define TID_MASK_TOP_LEFT 0xfffffffc
4831 #define TID_MASK_TOP 0xfffffffd
4832 #define TID_MASK_LEFT 0xfffffffe
4833
4834 static void si_llvm_emit_ddxy(
4835 const struct lp_build_tgsi_action *action,
4836 struct lp_build_tgsi_context *bld_base,
4837 struct lp_build_emit_data *emit_data)
4838 {
4839 struct si_shader_context *ctx = si_shader_context(bld_base);
4840 struct gallivm_state *gallivm = bld_base->base.gallivm;
4841 unsigned opcode = emit_data->info->opcode;
4842 LLVMValueRef thread_id, tl, trbl, tl_tid, trbl_tid, val, args[2];
4843 int idx;
4844 unsigned mask;
4845
4846 thread_id = get_thread_id(ctx);
4847
4848 if (opcode == TGSI_OPCODE_DDX_FINE)
4849 mask = TID_MASK_LEFT;
4850 else if (opcode == TGSI_OPCODE_DDY_FINE)
4851 mask = TID_MASK_TOP;
4852 else
4853 mask = TID_MASK_TOP_LEFT;
4854
4855 tl_tid = LLVMBuildAnd(gallivm->builder, thread_id,
4856 lp_build_const_int32(gallivm, mask), "");
4857
4858 /* for DDX we want to next X pixel, DDY next Y pixel. */
4859 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
4860 trbl_tid = LLVMBuildAdd(gallivm->builder, tl_tid,
4861 lp_build_const_int32(gallivm, idx), "");
4862
4863 val = LLVMBuildBitCast(gallivm->builder, emit_data->args[0], ctx->i32, "");
4864
4865 if (ctx->screen->has_ds_bpermute) {
4866 args[0] = LLVMBuildMul(gallivm->builder, tl_tid,
4867 lp_build_const_int32(gallivm, 4), "");
4868 args[1] = val;
4869 tl = lp_build_intrinsic(gallivm->builder,
4870 "llvm.amdgcn.ds.bpermute", ctx->i32,
4871 args, 2, LP_FUNC_ATTR_READNONE);
4872
4873 args[0] = LLVMBuildMul(gallivm->builder, trbl_tid,
4874 lp_build_const_int32(gallivm, 4), "");
4875 trbl = lp_build_intrinsic(gallivm->builder,
4876 "llvm.amdgcn.ds.bpermute", ctx->i32,
4877 args, 2, LP_FUNC_ATTR_READNONE);
4878 } else {
4879 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
4880
4881 store_ptr = build_gep0(ctx, ctx->lds, thread_id);
4882 load_ptr0 = build_gep0(ctx, ctx->lds, tl_tid);
4883 load_ptr1 = build_gep0(ctx, ctx->lds, trbl_tid);
4884
4885 LLVMBuildStore(gallivm->builder, val, store_ptr);
4886 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
4887 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
4888 }
4889
4890 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
4891 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
4892
4893 emit_data->output[emit_data->chan] =
4894 LLVMBuildFSub(gallivm->builder, trbl, tl, "");
4895 }
4896
4897 /*
4898 * this takes an I,J coordinate pair,
4899 * and works out the X and Y derivatives.
4900 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
4901 */
4902 static LLVMValueRef si_llvm_emit_ddxy_interp(
4903 struct lp_build_tgsi_context *bld_base,
4904 LLVMValueRef interp_ij)
4905 {
4906 struct si_shader_context *ctx = si_shader_context(bld_base);
4907 struct gallivm_state *gallivm = bld_base->base.gallivm;
4908 LLVMValueRef result[4], a;
4909 unsigned i;
4910
4911 for (i = 0; i < 2; i++) {
4912 a = LLVMBuildExtractElement(gallivm->builder, interp_ij,
4913 LLVMConstInt(ctx->i32, i, 0), "");
4914 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
4915 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
4916 }
4917
4918 return lp_build_gather_values(gallivm, result, 4);
4919 }
4920
4921 static void interp_fetch_args(
4922 struct lp_build_tgsi_context *bld_base,
4923 struct lp_build_emit_data *emit_data)
4924 {
4925 struct si_shader_context *ctx = si_shader_context(bld_base);
4926 struct gallivm_state *gallivm = bld_base->base.gallivm;
4927 const struct tgsi_full_instruction *inst = emit_data->inst;
4928
4929 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
4930 /* offset is in second src, first two channels */
4931 emit_data->args[0] = lp_build_emit_fetch(bld_base,
4932 emit_data->inst, 1,
4933 TGSI_CHAN_X);
4934 emit_data->args[1] = lp_build_emit_fetch(bld_base,
4935 emit_data->inst, 1,
4936 TGSI_CHAN_Y);
4937 emit_data->arg_count = 2;
4938 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4939 LLVMValueRef sample_position;
4940 LLVMValueRef sample_id;
4941 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
4942
4943 /* fetch sample ID, then fetch its sample position,
4944 * and place into first two channels.
4945 */
4946 sample_id = lp_build_emit_fetch(bld_base,
4947 emit_data->inst, 1, TGSI_CHAN_X);
4948 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
4949 ctx->i32, "");
4950 sample_position = load_sample_position(ctx, sample_id);
4951
4952 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
4953 sample_position,
4954 lp_build_const_int32(gallivm, 0), "");
4955
4956 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
4957 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
4958 sample_position,
4959 lp_build_const_int32(gallivm, 1), "");
4960 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
4961 emit_data->arg_count = 2;
4962 }
4963 }
4964
4965 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
4966 struct lp_build_tgsi_context *bld_base,
4967 struct lp_build_emit_data *emit_data)
4968 {
4969 struct si_shader_context *ctx = si_shader_context(bld_base);
4970 struct si_shader *shader = ctx->shader;
4971 struct gallivm_state *gallivm = bld_base->base.gallivm;
4972 LLVMValueRef interp_param;
4973 const struct tgsi_full_instruction *inst = emit_data->inst;
4974 const char *intr_name;
4975 int input_index = inst->Src[0].Register.Index;
4976 int chan;
4977 int i;
4978 LLVMValueRef attr_number;
4979 LLVMValueRef params = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
4980 int interp_param_idx;
4981 unsigned interp = shader->selector->info.input_interpolate[input_index];
4982 unsigned location;
4983
4984 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
4985
4986 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4987 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4988 location = TGSI_INTERPOLATE_LOC_CENTER;
4989 else
4990 location = TGSI_INTERPOLATE_LOC_CENTROID;
4991
4992 interp_param_idx = lookup_interp_param_index(interp, location);
4993 if (interp_param_idx == -1)
4994 return;
4995 else if (interp_param_idx)
4996 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4997 else
4998 interp_param = NULL;
4999
5000 attr_number = lp_build_const_int32(gallivm, input_index);
5001
5002 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5003 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5004 LLVMValueRef ij_out[2];
5005 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
5006
5007 /*
5008 * take the I then J parameters, and the DDX/Y for it, and
5009 * calculate the IJ inputs for the interpolator.
5010 * temp1 = ddx * offset/sample.x + I;
5011 * interp_param.I = ddy * offset/sample.y + temp1;
5012 * temp1 = ddx * offset/sample.x + J;
5013 * interp_param.J = ddy * offset/sample.y + temp1;
5014 */
5015 for (i = 0; i < 2; i++) {
5016 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
5017 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
5018 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
5019 ddxy_out, ix_ll, "");
5020 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
5021 ddxy_out, iy_ll, "");
5022 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5023 interp_param, ix_ll, "");
5024 LLVMValueRef temp1, temp2;
5025
5026 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5027 ctx->f32, "");
5028
5029 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5030
5031 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5032
5033 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5034
5035 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5036
5037 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
5038 temp2, ctx->i32, "");
5039 }
5040 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
5041 }
5042
5043 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
5044 for (chan = 0; chan < 4; chan++) {
5045 LLVMValueRef args[4];
5046 LLVMValueRef llvm_chan;
5047 unsigned schan;
5048
5049 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5050 llvm_chan = lp_build_const_int32(gallivm, schan);
5051
5052 args[0] = llvm_chan;
5053 args[1] = attr_number;
5054 args[2] = params;
5055 args[3] = interp_param;
5056
5057 emit_data->output[chan] =
5058 lp_build_intrinsic(gallivm->builder, intr_name,
5059 ctx->f32, args, args[3] ? 4 : 3,
5060 LP_FUNC_ATTR_READNONE);
5061 }
5062 }
5063
5064 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5065 struct lp_build_emit_data *emit_data)
5066 {
5067 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
5068 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5069 unsigned stream;
5070
5071 assert(src0.File == TGSI_FILE_IMMEDIATE);
5072
5073 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
5074 return stream;
5075 }
5076
5077 /* Emit one vertex from the geometry shader */
5078 static void si_llvm_emit_vertex(
5079 const struct lp_build_tgsi_action *action,
5080 struct lp_build_tgsi_context *bld_base,
5081 struct lp_build_emit_data *emit_data)
5082 {
5083 struct si_shader_context *ctx = si_shader_context(bld_base);
5084 struct lp_build_context *uint = &bld_base->uint_bld;
5085 struct si_shader *shader = ctx->shader;
5086 struct tgsi_shader_info *info = &shader->selector->info;
5087 struct gallivm_state *gallivm = bld_base->base.gallivm;
5088 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
5089 SI_PARAM_GS2VS_OFFSET);
5090 LLVMValueRef gs_next_vertex;
5091 LLVMValueRef can_emit, kill;
5092 LLVMValueRef args[2];
5093 unsigned chan;
5094 int i;
5095 unsigned stream;
5096
5097 stream = si_llvm_get_stream(bld_base, emit_data);
5098
5099 /* Write vertex attribute values to GSVS ring */
5100 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5101 ctx->gs_next_vertex[stream],
5102 "");
5103
5104 /* If this thread has already emitted the declared maximum number of
5105 * vertices, kill it: excessive vertex emissions are not supposed to
5106 * have any effect, and GS threads have no externally observable
5107 * effects other than emitting vertices.
5108 */
5109 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
5110 lp_build_const_int32(gallivm,
5111 shader->selector->gs_max_out_vertices), "");
5112 kill = lp_build_select(&bld_base->base, can_emit,
5113 lp_build_const_float(gallivm, 1.0f),
5114 lp_build_const_float(gallivm, -1.0f));
5115
5116 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
5117 ctx->voidt, &kill, 1, 0);
5118
5119 for (i = 0; i < info->num_outputs; i++) {
5120 LLVMValueRef *out_ptr =
5121 ctx->soa.outputs[i];
5122
5123 for (chan = 0; chan < 4; chan++) {
5124 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5125 LLVMValueRef voffset =
5126 lp_build_const_int32(gallivm, (i * 4 + chan) *
5127 shader->selector->gs_max_out_vertices);
5128
5129 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5130 voffset = lp_build_mul_imm(uint, voffset, 4);
5131
5132 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5133
5134 build_tbuffer_store(ctx,
5135 ctx->gsvs_ring[stream],
5136 out_val, 1,
5137 voffset, soffset, 0,
5138 V_008F0C_BUF_DATA_FORMAT_32,
5139 V_008F0C_BUF_NUM_FORMAT_UINT,
5140 1, 0, 1, 1, 0);
5141 }
5142 }
5143 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5144 lp_build_const_int32(gallivm, 1));
5145
5146 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5147
5148 /* Signal vertex emission */
5149 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
5150 args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID);
5151 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5152 ctx->voidt, args, 2, 0);
5153 }
5154
5155 /* Cut one primitive from the geometry shader */
5156 static void si_llvm_emit_primitive(
5157 const struct lp_build_tgsi_action *action,
5158 struct lp_build_tgsi_context *bld_base,
5159 struct lp_build_emit_data *emit_data)
5160 {
5161 struct si_shader_context *ctx = si_shader_context(bld_base);
5162 struct gallivm_state *gallivm = bld_base->base.gallivm;
5163 LLVMValueRef args[2];
5164 unsigned stream;
5165
5166 /* Signal primitive cut */
5167 stream = si_llvm_get_stream(bld_base, emit_data);
5168 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
5169 args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID);
5170 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5171 ctx->voidt, args, 2, 0);
5172 }
5173
5174 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5175 struct lp_build_tgsi_context *bld_base,
5176 struct lp_build_emit_data *emit_data)
5177 {
5178 struct si_shader_context *ctx = si_shader_context(bld_base);
5179 struct gallivm_state *gallivm = bld_base->base.gallivm;
5180
5181 /* The real barrier instruction isn’t needed, because an entire patch
5182 * always fits into a single wave.
5183 */
5184 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
5185 emit_optimization_barrier(ctx);
5186 return;
5187 }
5188
5189 lp_build_intrinsic(gallivm->builder,
5190 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5191 : "llvm.AMDGPU.barrier.local",
5192 ctx->voidt, NULL, 0, 0);
5193 }
5194
5195 static const struct lp_build_tgsi_action tex_action = {
5196 .fetch_args = tex_fetch_args,
5197 .emit = build_tex_intrinsic,
5198 };
5199
5200 static const struct lp_build_tgsi_action interp_action = {
5201 .fetch_args = interp_fetch_args,
5202 .emit = build_interp_intrinsic,
5203 };
5204
5205 static void si_create_function(struct si_shader_context *ctx,
5206 const char *name,
5207 LLVMTypeRef *returns, unsigned num_returns,
5208 LLVMTypeRef *params, unsigned num_params,
5209 int last_sgpr)
5210 {
5211 int i;
5212
5213 si_llvm_create_func(ctx, name, returns, num_returns,
5214 params, num_params);
5215 si_llvm_shader_type(ctx->main_fn, ctx->type);
5216 ctx->return_value = LLVMGetUndef(ctx->return_type);
5217
5218 for (i = 0; i <= last_sgpr; ++i) {
5219 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
5220
5221 /* The combination of:
5222 * - ByVal
5223 * - dereferenceable
5224 * - invariant.load
5225 * allows the optimization passes to move loads and reduces
5226 * SGPR spilling significantly.
5227 */
5228 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
5229 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
5230 lp_add_attr_dereferenceable(P, UINT64_MAX);
5231 } else
5232 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
5233 }
5234
5235 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5236 /* These were copied from some LLVM test. */
5237 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5238 "less-precise-fpmad",
5239 "true");
5240 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5241 "no-infs-fp-math",
5242 "true");
5243 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5244 "no-nans-fp-math",
5245 "true");
5246 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5247 "unsafe-fp-math",
5248 "true");
5249 }
5250 }
5251
5252 static void create_meta_data(struct si_shader_context *ctx)
5253 {
5254 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
5255
5256 ctx->invariant_load_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5257 "invariant.load", 14);
5258 ctx->range_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5259 "range", 5);
5260 ctx->uniform_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5261 "amdgpu.uniform", 14);
5262
5263 ctx->empty_md = LLVMMDNodeInContext(gallivm->context, NULL, 0);
5264 }
5265
5266 static void declare_streamout_params(struct si_shader_context *ctx,
5267 struct pipe_stream_output_info *so,
5268 LLVMTypeRef *params, LLVMTypeRef i32,
5269 unsigned *num_params)
5270 {
5271 int i;
5272
5273 /* Streamout SGPRs. */
5274 if (so->num_outputs) {
5275 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5276 params[ctx->param_streamout_config = (*num_params)++] = i32;
5277 else
5278 ctx->param_streamout_config = ctx->param_tess_offchip;
5279
5280 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5281 }
5282 /* A streamout buffer offset is loaded if the stride is non-zero. */
5283 for (i = 0; i < 4; i++) {
5284 if (!so->stride[i])
5285 continue;
5286
5287 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5288 }
5289 }
5290
5291 static unsigned llvm_get_type_size(LLVMTypeRef type)
5292 {
5293 LLVMTypeKind kind = LLVMGetTypeKind(type);
5294
5295 switch (kind) {
5296 case LLVMIntegerTypeKind:
5297 return LLVMGetIntTypeWidth(type) / 8;
5298 case LLVMFloatTypeKind:
5299 return 4;
5300 case LLVMPointerTypeKind:
5301 return 8;
5302 case LLVMVectorTypeKind:
5303 return LLVMGetVectorSize(type) *
5304 llvm_get_type_size(LLVMGetElementType(type));
5305 default:
5306 assert(0);
5307 return 0;
5308 }
5309 }
5310
5311 static void declare_tess_lds(struct si_shader_context *ctx)
5312 {
5313 struct gallivm_state *gallivm = &ctx->gallivm;
5314 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
5315 struct lp_build_context *uint = &bld_base->uint_bld;
5316
5317 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5318 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, uint->zero,
5319 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
5320 "tess_lds");
5321 }
5322
5323 static void create_function(struct si_shader_context *ctx)
5324 {
5325 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
5326 struct gallivm_state *gallivm = bld_base->base.gallivm;
5327 struct si_shader *shader = ctx->shader;
5328 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
5329 LLVMTypeRef returns[16+32*4];
5330 unsigned i, last_sgpr, num_params, num_return_sgprs;
5331 unsigned num_returns = 0;
5332 unsigned num_prolog_vgprs = 0;
5333
5334 v3i32 = LLVMVectorType(ctx->i32, 3);
5335
5336 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5337 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5338 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5339 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5340 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5341
5342 switch (ctx->type) {
5343 case PIPE_SHADER_VERTEX:
5344 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
5345 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5346 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5347 params[SI_PARAM_DRAWID] = ctx->i32;
5348 num_params = SI_PARAM_DRAWID+1;
5349
5350 if (shader->key.as_es) {
5351 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5352 } else if (shader->key.as_ls) {
5353 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
5354 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
5355 } else {
5356 if (shader->is_gs_copy_shader) {
5357 num_params = SI_PARAM_RW_BUFFERS+1;
5358 } else {
5359 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5360 num_params = SI_PARAM_VS_STATE_BITS+1;
5361 }
5362
5363 /* The locations of the other parameters are assigned dynamically. */
5364 declare_streamout_params(ctx, &shader->selector->so,
5365 params, ctx->i32, &num_params);
5366 }
5367
5368 last_sgpr = num_params-1;
5369
5370 /* VGPRs */
5371 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5372 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5373 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5374 params[ctx->param_instance_id = num_params++] = ctx->i32;
5375
5376 if (!shader->is_gs_copy_shader) {
5377 /* Vertex load indices. */
5378 ctx->param_vertex_index0 = num_params;
5379
5380 for (i = 0; i < shader->selector->info.num_inputs; i++)
5381 params[num_params++] = ctx->i32;
5382
5383 num_prolog_vgprs += shader->selector->info.num_inputs;
5384
5385 /* PrimitiveID output. */
5386 if (!shader->key.as_es && !shader->key.as_ls)
5387 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5388 returns[num_returns++] = ctx->f32;
5389 }
5390 break;
5391
5392 case PIPE_SHADER_TESS_CTRL:
5393 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5394 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5395 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5396 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5397 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5398 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5399 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5400
5401 /* VGPRs */
5402 params[SI_PARAM_PATCH_ID] = ctx->i32;
5403 params[SI_PARAM_REL_IDS] = ctx->i32;
5404 num_params = SI_PARAM_REL_IDS+1;
5405
5406 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5407 * placed after the user SGPRs.
5408 */
5409 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5410 returns[num_returns++] = ctx->i32; /* SGPRs */
5411
5412 for (i = 0; i < 3; i++)
5413 returns[num_returns++] = ctx->f32; /* VGPRs */
5414 break;
5415
5416 case PIPE_SHADER_TESS_EVAL:
5417 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5418 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5419
5420 if (shader->key.as_es) {
5421 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5422 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5423 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5424 } else {
5425 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5426 declare_streamout_params(ctx, &shader->selector->so,
5427 params, ctx->i32, &num_params);
5428 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5429 }
5430 last_sgpr = num_params - 1;
5431
5432 /* VGPRs */
5433 params[ctx->param_tes_u = num_params++] = ctx->f32;
5434 params[ctx->param_tes_v = num_params++] = ctx->f32;
5435 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5436 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5437
5438 /* PrimitiveID output. */
5439 if (!shader->key.as_es)
5440 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5441 returns[num_returns++] = ctx->f32;
5442 break;
5443
5444 case PIPE_SHADER_GEOMETRY:
5445 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5446 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5447 last_sgpr = SI_PARAM_GS_WAVE_ID;
5448
5449 /* VGPRs */
5450 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5451 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5452 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5453 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5454 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5455 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5456 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5457 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5458 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5459 break;
5460
5461 case PIPE_SHADER_FRAGMENT:
5462 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5463 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5464 last_sgpr = SI_PARAM_PRIM_MASK;
5465 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5466 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5467 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5468 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5469 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5470 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5471 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5472 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5473 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5474 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5475 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5476 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5477 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5478 shader->info.face_vgpr_index = 20;
5479 params[SI_PARAM_ANCILLARY] = ctx->i32;
5480 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5481 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5482 num_params = SI_PARAM_POS_FIXED_PT+1;
5483
5484 /* Color inputs from the prolog. */
5485 if (shader->selector->info.colors_read) {
5486 unsigned num_color_elements =
5487 util_bitcount(shader->selector->info.colors_read);
5488
5489 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5490 for (i = 0; i < num_color_elements; i++)
5491 params[num_params++] = ctx->f32;
5492
5493 num_prolog_vgprs += num_color_elements;
5494 }
5495
5496 /* Outputs for the epilog. */
5497 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5498 num_returns =
5499 num_return_sgprs +
5500 util_bitcount(shader->selector->info.colors_written) * 4 +
5501 shader->selector->info.writes_z +
5502 shader->selector->info.writes_stencil +
5503 shader->selector->info.writes_samplemask +
5504 1 /* SampleMaskIn */;
5505
5506 num_returns = MAX2(num_returns,
5507 num_return_sgprs +
5508 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5509
5510 for (i = 0; i < num_return_sgprs; i++)
5511 returns[i] = ctx->i32;
5512 for (; i < num_returns; i++)
5513 returns[i] = ctx->f32;
5514 break;
5515
5516 case PIPE_SHADER_COMPUTE:
5517 params[SI_PARAM_GRID_SIZE] = v3i32;
5518 params[SI_PARAM_BLOCK_SIZE] = v3i32;
5519 params[SI_PARAM_BLOCK_ID] = v3i32;
5520 last_sgpr = SI_PARAM_BLOCK_ID;
5521
5522 params[SI_PARAM_THREAD_ID] = v3i32;
5523 num_params = SI_PARAM_THREAD_ID + 1;
5524 break;
5525 default:
5526 assert(0 && "unimplemented shader");
5527 return;
5528 }
5529
5530 assert(num_params <= ARRAY_SIZE(params));
5531
5532 si_create_function(ctx, "main", returns, num_returns, params,
5533 num_params, last_sgpr);
5534
5535 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5536 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5537 ctx->separate_prolog) {
5538 si_llvm_add_attribute(ctx->main_fn,
5539 "InitialPSInputAddr",
5540 S_0286D0_PERSP_SAMPLE_ENA(1) |
5541 S_0286D0_PERSP_CENTER_ENA(1) |
5542 S_0286D0_PERSP_CENTROID_ENA(1) |
5543 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5544 S_0286D0_LINEAR_CENTER_ENA(1) |
5545 S_0286D0_LINEAR_CENTROID_ENA(1) |
5546 S_0286D0_FRONT_FACE_ENA(1) |
5547 S_0286D0_POS_FIXED_PT_ENA(1));
5548 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5549 const unsigned *properties = shader->selector->info.properties;
5550 unsigned max_work_group_size =
5551 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5552 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5553 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5554
5555 if (!max_work_group_size) {
5556 /* This is a variable group size compute shader,
5557 * compile it for the maximum possible group size.
5558 */
5559 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
5560 }
5561
5562 si_llvm_add_attribute(ctx->main_fn,
5563 "amdgpu-max-work-group-size",
5564 max_work_group_size);
5565 }
5566
5567 shader->info.num_input_sgprs = 0;
5568 shader->info.num_input_vgprs = 0;
5569
5570 for (i = 0; i <= last_sgpr; ++i)
5571 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5572
5573 for (; i < num_params; ++i)
5574 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5575
5576 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5577 shader->info.num_input_vgprs -= num_prolog_vgprs;
5578
5579 if (!ctx->screen->has_ds_bpermute &&
5580 bld_base->info &&
5581 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5582 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5583 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5584 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5585 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5586 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5587 ctx->lds =
5588 LLVMAddGlobalInAddressSpace(gallivm->module,
5589 LLVMArrayType(ctx->i32, 64),
5590 "ddxy_lds",
5591 LOCAL_ADDR_SPACE);
5592
5593 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.as_ls) ||
5594 ctx->type == PIPE_SHADER_TESS_CTRL ||
5595 ctx->type == PIPE_SHADER_TESS_EVAL)
5596 declare_tess_lds(ctx);
5597 }
5598
5599 /**
5600 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5601 * for later use.
5602 */
5603 static void preload_ring_buffers(struct si_shader_context *ctx)
5604 {
5605 struct gallivm_state *gallivm =
5606 ctx->soa.bld_base.base.gallivm;
5607
5608 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5609 SI_PARAM_RW_BUFFERS);
5610
5611 if ((ctx->type == PIPE_SHADER_VERTEX &&
5612 ctx->shader->key.as_es) ||
5613 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5614 ctx->shader->key.as_es) ||
5615 ctx->type == PIPE_SHADER_GEOMETRY) {
5616 unsigned ring =
5617 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5618 : SI_ES_RING_ESGS;
5619 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5620
5621 ctx->esgs_ring =
5622 build_indexed_load_const(ctx, buf_ptr, offset);
5623 }
5624
5625 if (ctx->shader->is_gs_copy_shader) {
5626 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_VS_RING_GSVS);
5627
5628 ctx->gsvs_ring[0] =
5629 build_indexed_load_const(ctx, buf_ptr, offset);
5630 }
5631 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5632 int i;
5633 for (i = 0; i < 4; i++) {
5634 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_GS_RING_GSVS0 + i);
5635
5636 ctx->gsvs_ring[i] =
5637 build_indexed_load_const(ctx, buf_ptr, offset);
5638 }
5639 }
5640 }
5641
5642 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5643 LLVMValueRef param_rw_buffers,
5644 unsigned param_pos_fixed_pt)
5645 {
5646 struct lp_build_tgsi_context *bld_base =
5647 &ctx->soa.bld_base;
5648 struct gallivm_state *gallivm = bld_base->base.gallivm;
5649 LLVMBuilderRef builder = gallivm->builder;
5650 LLVMValueRef slot, desc, offset, row, bit, address[2];
5651
5652 /* Use the fixed-point gl_FragCoord input.
5653 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5654 * per coordinate to get the repeating effect.
5655 */
5656 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5657 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5658
5659 /* Load the buffer descriptor. */
5660 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
5661 desc = build_indexed_load_const(ctx, param_rw_buffers, slot);
5662
5663 /* The stipple pattern is 32x32, each row has 32 bits. */
5664 offset = LLVMBuildMul(builder, address[1],
5665 LLVMConstInt(ctx->i32, 4, 0), "");
5666 row = buffer_load_const(ctx, desc, offset);
5667 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
5668 bit = LLVMBuildLShr(builder, row, address[0], "");
5669 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5670
5671 /* The intrinsic kills the thread if arg < 0. */
5672 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
5673 LLVMConstReal(ctx->f32, -1), "");
5674 lp_build_intrinsic(builder, "llvm.AMDGPU.kill", ctx->voidt, &bit, 1, 0);
5675 }
5676
5677 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
5678 struct si_shader_config *conf,
5679 unsigned symbol_offset)
5680 {
5681 unsigned i;
5682 const unsigned char *config =
5683 radeon_shader_binary_config_start(binary, symbol_offset);
5684 bool really_needs_scratch = false;
5685
5686 /* LLVM adds SGPR spills to the scratch size.
5687 * Find out if we really need the scratch buffer.
5688 */
5689 for (i = 0; i < binary->reloc_count; i++) {
5690 const struct radeon_shader_reloc *reloc = &binary->relocs[i];
5691
5692 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5693 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5694 really_needs_scratch = true;
5695 break;
5696 }
5697 }
5698
5699 /* XXX: We may be able to emit some of these values directly rather than
5700 * extracting fields to be emitted later.
5701 */
5702
5703 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5704 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5705 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5706 switch (reg) {
5707 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5708 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5709 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5710 case R_00B848_COMPUTE_PGM_RSRC1:
5711 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5712 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5713 conf->float_mode = G_00B028_FLOAT_MODE(value);
5714 conf->rsrc1 = value;
5715 break;
5716 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5717 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5718 break;
5719 case R_00B84C_COMPUTE_PGM_RSRC2:
5720 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5721 conf->rsrc2 = value;
5722 break;
5723 case R_0286CC_SPI_PS_INPUT_ENA:
5724 conf->spi_ps_input_ena = value;
5725 break;
5726 case R_0286D0_SPI_PS_INPUT_ADDR:
5727 conf->spi_ps_input_addr = value;
5728 break;
5729 case R_0286E8_SPI_TMPRING_SIZE:
5730 case R_00B860_COMPUTE_TMPRING_SIZE:
5731 /* WAVESIZE is in units of 256 dwords. */
5732 if (really_needs_scratch)
5733 conf->scratch_bytes_per_wave =
5734 G_00B860_WAVESIZE(value) * 256 * 4;
5735 break;
5736 case 0x4: /* SPILLED_SGPRS */
5737 conf->spilled_sgprs = value;
5738 break;
5739 case 0x8: /* SPILLED_VGPRS */
5740 conf->spilled_vgprs = value;
5741 break;
5742 default:
5743 {
5744 static bool printed;
5745
5746 if (!printed) {
5747 fprintf(stderr, "Warning: LLVM emitted unknown "
5748 "config register: 0x%x\n", reg);
5749 printed = true;
5750 }
5751 }
5752 break;
5753 }
5754 }
5755
5756 if (!conf->spi_ps_input_addr)
5757 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5758 }
5759
5760 void si_shader_apply_scratch_relocs(struct si_context *sctx,
5761 struct si_shader *shader,
5762 struct si_shader_config *config,
5763 uint64_t scratch_va)
5764 {
5765 unsigned i;
5766 uint32_t scratch_rsrc_dword0 = scratch_va;
5767 uint32_t scratch_rsrc_dword1 =
5768 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5769
5770 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
5771 * correctly.
5772 */
5773 if (HAVE_LLVM >= 0x0309)
5774 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5775 else
5776 scratch_rsrc_dword1 |=
5777 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
5778
5779 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5780 const struct radeon_shader_reloc *reloc =
5781 &shader->binary.relocs[i];
5782 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5783 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5784 &scratch_rsrc_dword0, 4);
5785 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5786 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5787 &scratch_rsrc_dword1, 4);
5788 }
5789 }
5790 }
5791
5792 static unsigned si_get_shader_binary_size(struct si_shader *shader)
5793 {
5794 unsigned size = shader->binary.code_size;
5795
5796 if (shader->prolog)
5797 size += shader->prolog->binary.code_size;
5798 if (shader->epilog)
5799 size += shader->epilog->binary.code_size;
5800 return size;
5801 }
5802
5803 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5804 {
5805 const struct radeon_shader_binary *prolog =
5806 shader->prolog ? &shader->prolog->binary : NULL;
5807 const struct radeon_shader_binary *epilog =
5808 shader->epilog ? &shader->epilog->binary : NULL;
5809 const struct radeon_shader_binary *mainb = &shader->binary;
5810 unsigned bo_size = si_get_shader_binary_size(shader) +
5811 (!epilog ? mainb->rodata_size : 0);
5812 unsigned char *ptr;
5813
5814 assert(!prolog || !prolog->rodata_size);
5815 assert((!prolog && !epilog) || !mainb->rodata_size);
5816 assert(!epilog || !epilog->rodata_size);
5817
5818 r600_resource_reference(&shader->bo, NULL);
5819 shader->bo = (struct r600_resource*)
5820 pipe_buffer_create(&sscreen->b.b, 0,
5821 PIPE_USAGE_IMMUTABLE, bo_size);
5822 if (!shader->bo)
5823 return -ENOMEM;
5824
5825 /* Upload. */
5826 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
5827 PIPE_TRANSFER_READ_WRITE);
5828
5829 if (prolog) {
5830 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
5831 ptr += prolog->code_size;
5832 }
5833
5834 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
5835 ptr += mainb->code_size;
5836
5837 if (epilog)
5838 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
5839 else if (mainb->rodata_size > 0)
5840 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
5841
5842 sscreen->b.ws->buffer_unmap(shader->bo->buf);
5843 return 0;
5844 }
5845
5846 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
5847 struct pipe_debug_callback *debug,
5848 const char *name, FILE *file)
5849 {
5850 char *line, *p;
5851 unsigned i, count;
5852
5853 if (binary->disasm_string) {
5854 fprintf(file, "Shader %s disassembly:\n", name);
5855 fprintf(file, "%s", binary->disasm_string);
5856
5857 if (debug && debug->debug_message) {
5858 /* Very long debug messages are cut off, so send the
5859 * disassembly one line at a time. This causes more
5860 * overhead, but on the plus side it simplifies
5861 * parsing of resulting logs.
5862 */
5863 pipe_debug_message(debug, SHADER_INFO,
5864 "Shader Disassembly Begin");
5865
5866 line = binary->disasm_string;
5867 while (*line) {
5868 p = util_strchrnul(line, '\n');
5869 count = p - line;
5870
5871 if (count) {
5872 pipe_debug_message(debug, SHADER_INFO,
5873 "%.*s", count, line);
5874 }
5875
5876 if (!*p)
5877 break;
5878 line = p + 1;
5879 }
5880
5881 pipe_debug_message(debug, SHADER_INFO,
5882 "Shader Disassembly End");
5883 }
5884 } else {
5885 fprintf(file, "Shader %s binary:\n", name);
5886 for (i = 0; i < binary->code_size; i += 4) {
5887 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5888 binary->code[i + 3], binary->code[i + 2],
5889 binary->code[i + 1], binary->code[i]);
5890 }
5891 }
5892 }
5893
5894 static void si_shader_dump_stats(struct si_screen *sscreen,
5895 struct si_shader_config *conf,
5896 unsigned num_inputs,
5897 unsigned code_size,
5898 struct pipe_debug_callback *debug,
5899 unsigned processor,
5900 FILE *file)
5901 {
5902 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
5903 unsigned lds_per_wave = 0;
5904 unsigned max_simd_waves = 10;
5905
5906 /* Compute LDS usage for PS. */
5907 if (processor == PIPE_SHADER_FRAGMENT) {
5908 /* The minimum usage per wave is (num_inputs * 48). The maximum
5909 * usage is (num_inputs * 48 * 16).
5910 * We can get anything in between and it varies between waves.
5911 *
5912 * The 48 bytes per input for a single primitive is equal to
5913 * 4 bytes/component * 4 components/input * 3 points.
5914 *
5915 * Other stages don't know the size at compile time or don't
5916 * allocate LDS per wave, but instead they do it per thread group.
5917 */
5918 lds_per_wave = conf->lds_size * lds_increment +
5919 align(num_inputs * 48, lds_increment);
5920 }
5921
5922 /* Compute the per-SIMD wave counts. */
5923 if (conf->num_sgprs) {
5924 if (sscreen->b.chip_class >= VI)
5925 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5926 else
5927 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5928 }
5929
5930 if (conf->num_vgprs)
5931 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5932
5933 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
5934 * that PS can use.
5935 */
5936 if (lds_per_wave)
5937 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5938
5939 if (file != stderr ||
5940 r600_can_dump_shader(&sscreen->b, processor)) {
5941 if (processor == PIPE_SHADER_FRAGMENT) {
5942 fprintf(file, "*** SHADER CONFIG ***\n"
5943 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5944 "SPI_PS_INPUT_ENA = 0x%04x\n",
5945 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5946 }
5947
5948 fprintf(file, "*** SHADER STATS ***\n"
5949 "SGPRS: %d\n"
5950 "VGPRS: %d\n"
5951 "Spilled SGPRs: %d\n"
5952 "Spilled VGPRs: %d\n"
5953 "Code Size: %d bytes\n"
5954 "LDS: %d blocks\n"
5955 "Scratch: %d bytes per wave\n"
5956 "Max Waves: %d\n"
5957 "********************\n\n\n",
5958 conf->num_sgprs, conf->num_vgprs,
5959 conf->spilled_sgprs, conf->spilled_vgprs, code_size,
5960 conf->lds_size, conf->scratch_bytes_per_wave,
5961 max_simd_waves);
5962 }
5963
5964 pipe_debug_message(debug, SHADER_INFO,
5965 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5966 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5967 "Spilled VGPRs: %d",
5968 conf->num_sgprs, conf->num_vgprs, code_size,
5969 conf->lds_size, conf->scratch_bytes_per_wave,
5970 max_simd_waves, conf->spilled_sgprs,
5971 conf->spilled_vgprs);
5972 }
5973
5974 static const char *si_get_shader_name(struct si_shader *shader,
5975 unsigned processor)
5976 {
5977 switch (processor) {
5978 case PIPE_SHADER_VERTEX:
5979 if (shader->key.as_es)
5980 return "Vertex Shader as ES";
5981 else if (shader->key.as_ls)
5982 return "Vertex Shader as LS";
5983 else
5984 return "Vertex Shader as VS";
5985 case PIPE_SHADER_TESS_CTRL:
5986 return "Tessellation Control Shader";
5987 case PIPE_SHADER_TESS_EVAL:
5988 if (shader->key.as_es)
5989 return "Tessellation Evaluation Shader as ES";
5990 else
5991 return "Tessellation Evaluation Shader as VS";
5992 case PIPE_SHADER_GEOMETRY:
5993 if (shader->is_gs_copy_shader)
5994 return "GS Copy Shader as VS";
5995 else
5996 return "Geometry Shader";
5997 case PIPE_SHADER_FRAGMENT:
5998 return "Pixel Shader";
5999 case PIPE_SHADER_COMPUTE:
6000 return "Compute Shader";
6001 default:
6002 return "Unknown Shader";
6003 }
6004 }
6005
6006 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6007 struct pipe_debug_callback *debug, unsigned processor,
6008 FILE *file)
6009 {
6010 if (file != stderr ||
6011 r600_can_dump_shader(&sscreen->b, processor))
6012 si_dump_shader_key(processor, &shader->key, file);
6013
6014 if (file != stderr && shader->binary.llvm_ir_string) {
6015 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
6016 si_get_shader_name(shader, processor));
6017 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
6018 }
6019
6020 if (file != stderr ||
6021 (r600_can_dump_shader(&sscreen->b, processor) &&
6022 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6023 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6024
6025 if (shader->prolog)
6026 si_shader_dump_disassembly(&shader->prolog->binary,
6027 debug, "prolog", file);
6028
6029 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6030
6031 if (shader->epilog)
6032 si_shader_dump_disassembly(&shader->epilog->binary,
6033 debug, "epilog", file);
6034 fprintf(file, "\n");
6035 }
6036
6037 si_shader_dump_stats(sscreen, &shader->config,
6038 shader->selector ? shader->selector->info.num_inputs : 0,
6039 si_get_shader_binary_size(shader), debug, processor,
6040 file);
6041 }
6042
6043 int si_compile_llvm(struct si_screen *sscreen,
6044 struct radeon_shader_binary *binary,
6045 struct si_shader_config *conf,
6046 LLVMTargetMachineRef tm,
6047 LLVMModuleRef mod,
6048 struct pipe_debug_callback *debug,
6049 unsigned processor,
6050 const char *name)
6051 {
6052 int r = 0;
6053 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6054
6055 if (r600_can_dump_shader(&sscreen->b, processor)) {
6056 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6057
6058 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6059 fprintf(stderr, "%s LLVM IR:\n\n", name);
6060 LLVMDumpModule(mod);
6061 fprintf(stderr, "\n");
6062 }
6063 }
6064
6065 if (sscreen->record_llvm_ir) {
6066 char *ir = LLVMPrintModuleToString(mod);
6067 binary->llvm_ir_string = strdup(ir);
6068 LLVMDisposeMessage(ir);
6069 }
6070
6071 if (!si_replace_shader(count, binary)) {
6072 r = si_llvm_compile(mod, binary, tm, debug);
6073 if (r)
6074 return r;
6075 }
6076
6077 si_shader_binary_read_config(binary, conf, 0);
6078
6079 /* Enable 64-bit and 16-bit denormals, because there is no performance
6080 * cost.
6081 *
6082 * If denormals are enabled, all floating-point output modifiers are
6083 * ignored.
6084 *
6085 * Don't enable denormals for 32-bit floats, because:
6086 * - Floating-point output modifiers would be ignored by the hw.
6087 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6088 * have to stop using those.
6089 * - SI & CI would be very slow.
6090 */
6091 conf->float_mode |= V_00B028_FP_64_DENORMS;
6092
6093 FREE(binary->config);
6094 FREE(binary->global_symbol_offsets);
6095 binary->config = NULL;
6096 binary->global_symbol_offsets = NULL;
6097
6098 /* Some shaders can't have rodata because their binaries can be
6099 * concatenated.
6100 */
6101 if (binary->rodata_size &&
6102 (processor == PIPE_SHADER_VERTEX ||
6103 processor == PIPE_SHADER_TESS_CTRL ||
6104 processor == PIPE_SHADER_TESS_EVAL ||
6105 processor == PIPE_SHADER_FRAGMENT)) {
6106 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6107 return -EINVAL;
6108 }
6109
6110 return r;
6111 }
6112
6113 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6114 {
6115 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6116 LLVMBuildRetVoid(ctx->gallivm.builder);
6117 else
6118 LLVMBuildRet(ctx->gallivm.builder, ret);
6119 }
6120
6121 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6122 struct si_shader *
6123 si_generate_gs_copy_shader(struct si_screen *sscreen,
6124 LLVMTargetMachineRef tm,
6125 struct si_shader_selector *gs_selector,
6126 struct pipe_debug_callback *debug)
6127 {
6128 struct si_shader_context ctx;
6129 struct si_shader *shader;
6130 struct gallivm_state *gallivm = &ctx.gallivm;
6131 struct lp_build_tgsi_context *bld_base = &ctx.soa.bld_base;
6132 struct lp_build_context *uint = &bld_base->uint_bld;
6133 struct si_shader_output_values *outputs;
6134 struct tgsi_shader_info *gsinfo = &gs_selector->info;
6135 LLVMValueRef args[9];
6136 int i, r;
6137
6138 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6139
6140 if (!outputs)
6141 return NULL;
6142
6143 shader = CALLOC_STRUCT(si_shader);
6144 if (!shader) {
6145 FREE(outputs);
6146 return NULL;
6147 }
6148
6149
6150 shader->selector = gs_selector;
6151 shader->is_gs_copy_shader = true;
6152
6153 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6154 ctx.type = PIPE_SHADER_VERTEX;
6155
6156 create_meta_data(&ctx);
6157 create_function(&ctx);
6158 preload_ring_buffers(&ctx);
6159
6160 args[0] = ctx.gsvs_ring[0];
6161 args[1] = lp_build_mul_imm(uint,
6162 LLVMGetParam(ctx.main_fn,
6163 ctx.param_vertex_id),
6164 4);
6165 args[3] = uint->zero;
6166 args[4] = uint->one; /* OFFEN */
6167 args[5] = uint->zero; /* IDXEN */
6168 args[6] = uint->one; /* GLC */
6169 args[7] = uint->one; /* SLC */
6170 args[8] = uint->zero; /* TFE */
6171
6172 /* Fetch vertex data from GSVS ring */
6173 for (i = 0; i < gsinfo->num_outputs; ++i) {
6174 unsigned chan;
6175
6176 outputs[i].name = gsinfo->output_semantic_name[i];
6177 outputs[i].sid = gsinfo->output_semantic_index[i];
6178
6179 for (chan = 0; chan < 4; chan++) {
6180 args[2] = lp_build_const_int32(gallivm,
6181 (i * 4 + chan) *
6182 gs_selector->gs_max_out_vertices * 16 * 4);
6183
6184 outputs[i].values[chan] =
6185 LLVMBuildBitCast(gallivm->builder,
6186 lp_build_intrinsic(gallivm->builder,
6187 "llvm.SI.buffer.load.dword.i32.i32",
6188 ctx.i32, args, 9,
6189 LP_FUNC_ATTR_READONLY),
6190 ctx.f32, "");
6191 }
6192 }
6193
6194 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6195
6196 LLVMBuildRetVoid(gallivm->builder);
6197
6198 /* Dump LLVM IR before any optimization passes */
6199 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6200 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6201 LLVMDumpModule(bld_base->base.gallivm->module);
6202
6203 si_llvm_finalize_module(&ctx,
6204 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_GEOMETRY));
6205
6206 r = si_compile_llvm(sscreen, &ctx.shader->binary,
6207 &ctx.shader->config, ctx.tm,
6208 bld_base->base.gallivm->module,
6209 debug, PIPE_SHADER_GEOMETRY,
6210 "GS Copy Shader");
6211 if (!r) {
6212 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6213 fprintf(stderr, "GS Copy Shader:\n");
6214 si_shader_dump(sscreen, ctx.shader, debug,
6215 PIPE_SHADER_GEOMETRY, stderr);
6216 r = si_shader_binary_upload(sscreen, ctx.shader);
6217 }
6218
6219 si_llvm_dispose(&ctx);
6220
6221 FREE(outputs);
6222
6223 if (r != 0) {
6224 FREE(shader);
6225 shader = NULL;
6226 }
6227 return shader;
6228 }
6229
6230 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
6231 FILE *f)
6232 {
6233 int i;
6234
6235 fprintf(f, "SHADER KEY\n");
6236
6237 switch (shader) {
6238 case PIPE_SHADER_VERTEX:
6239 fprintf(f, " part.vs.prolog.instance_divisors = {");
6240 for (i = 0; i < ARRAY_SIZE(key->part.vs.prolog.instance_divisors); i++)
6241 fprintf(f, !i ? "%u" : ", %u",
6242 key->part.vs.prolog.instance_divisors[i]);
6243 fprintf(f, "}\n");
6244 fprintf(f, " part.vs.epilog.export_prim_id = %u\n", key->part.vs.epilog.export_prim_id);
6245 fprintf(f, " as_es = %u\n", key->as_es);
6246 fprintf(f, " as_ls = %u\n", key->as_ls);
6247 fprintf(f, " mono.vs.fix_fetch = 0x%x\n", key->mono.vs.fix_fetch);
6248 break;
6249
6250 case PIPE_SHADER_TESS_CTRL:
6251 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
6252 fprintf(f, " mono.tcs.inputs_to_copy = 0x%"PRIx64"\n", key->mono.tcs.inputs_to_copy);
6253 break;
6254
6255 case PIPE_SHADER_TESS_EVAL:
6256 fprintf(f, " part.tes.epilog.export_prim_id = %u\n", key->part.tes.epilog.export_prim_id);
6257 fprintf(f, " as_es = %u\n", key->as_es);
6258 break;
6259
6260 case PIPE_SHADER_GEOMETRY:
6261 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
6262 break;
6263
6264 case PIPE_SHADER_COMPUTE:
6265 break;
6266
6267 case PIPE_SHADER_FRAGMENT:
6268 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
6269 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
6270 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
6271 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
6272 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
6273 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
6274 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
6275 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
6276 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
6277 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
6278 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
6279 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
6280 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
6281 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
6282 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
6283 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
6284 break;
6285
6286 default:
6287 assert(0);
6288 }
6289 }
6290
6291 static void si_init_shader_ctx(struct si_shader_context *ctx,
6292 struct si_screen *sscreen,
6293 struct si_shader *shader,
6294 LLVMTargetMachineRef tm)
6295 {
6296 struct lp_build_tgsi_context *bld_base;
6297 struct lp_build_tgsi_action tmpl = {};
6298
6299 si_llvm_context_init(ctx, sscreen, shader, tm,
6300 (shader && shader->selector) ? &shader->selector->info : NULL,
6301 (shader && shader->selector) ? shader->selector->tokens : NULL);
6302
6303 bld_base = &ctx->soa.bld_base;
6304 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6305
6306 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6307 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6308 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6309
6310 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6311 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6312 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6313 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6314 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6315 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6316 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6317 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6318 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6319 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6320 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6321 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6322 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6323 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6324
6325 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6326 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6327 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6328 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6329 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6330 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6331
6332 tmpl.fetch_args = atomic_fetch_args;
6333 tmpl.emit = atomic_emit;
6334 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6335 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6336 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6337 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6338 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6339 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6340 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6341 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6342 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6343 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6344 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6345 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6346 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6347 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6348 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6349 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6350 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6351 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6352 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6353 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6354
6355 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6356
6357 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6358 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6359 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6360 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6361
6362 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6363 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6364 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6365 }
6366
6367 /* Return true if the PARAM export has been eliminated. */
6368 static bool si_eliminate_const_output(struct si_shader_context *ctx,
6369 LLVMValueRef inst, unsigned offset)
6370 {
6371 struct si_shader *shader = ctx->shader;
6372 unsigned num_outputs = shader->selector->info.num_outputs;
6373 unsigned i, default_val; /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL */
6374 bool is_zero[4] = {}, is_one[4] = {};
6375
6376 for (i = 0; i < 4; i++) {
6377 LLVMBool loses_info;
6378 LLVMValueRef p = LLVMGetOperand(inst, 5 + i);
6379
6380 /* It's a constant expression. Undef outputs are eliminated too. */
6381 if (LLVMIsUndef(p)) {
6382 is_zero[i] = true;
6383 is_one[i] = true;
6384 } else if (LLVMIsAConstantFP(p)) {
6385 double a = LLVMConstRealGetDouble(p, &loses_info);
6386
6387 if (a == 0)
6388 is_zero[i] = true;
6389 else if (a == 1)
6390 is_one[i] = true;
6391 else
6392 return false; /* other constant */
6393 } else
6394 return false;
6395 }
6396
6397 /* Only certain combinations of 0 and 1 can be eliminated. */
6398 if (is_zero[0] && is_zero[1] && is_zero[2])
6399 default_val = is_zero[3] ? 0 : 1;
6400 else if (is_one[0] && is_one[1] && is_one[2])
6401 default_val = is_zero[3] ? 2 : 3;
6402 else
6403 return false;
6404
6405 /* The PARAM export can be represented as DEFAULT_VAL. Kill it. */
6406 LLVMInstructionEraseFromParent(inst);
6407
6408 /* Change OFFSET to DEFAULT_VAL. */
6409 for (i = 0; i < num_outputs; i++) {
6410 if (shader->info.vs_output_param_offset[i] == offset) {
6411 shader->info.vs_output_param_offset[i] =
6412 EXP_PARAM_DEFAULT_VAL_0000 + default_val;
6413 break;
6414 }
6415 }
6416 return true;
6417 }
6418
6419 struct si_vs_exports {
6420 unsigned num;
6421 unsigned offset[SI_MAX_VS_OUTPUTS];
6422 LLVMValueRef inst[SI_MAX_VS_OUTPUTS];
6423 };
6424
6425 static void si_eliminate_const_vs_outputs(struct si_shader_context *ctx)
6426 {
6427 struct si_shader *shader = ctx->shader;
6428 struct tgsi_shader_info *info = &shader->selector->info;
6429 LLVMBasicBlockRef bb;
6430 struct si_vs_exports exports;
6431 bool removed_any = false;
6432
6433 exports.num = 0;
6434
6435 if (shader->key.as_es || shader->key.as_ls)
6436 return;
6437
6438 /* Process all LLVM instructions. */
6439 bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6440 while (bb) {
6441 LLVMValueRef inst = LLVMGetFirstInstruction(bb);
6442
6443 while (inst) {
6444 LLVMValueRef cur = inst;
6445 inst = LLVMGetNextInstruction(inst);
6446
6447 if (LLVMGetInstructionOpcode(cur) != LLVMCall)
6448 continue;
6449
6450 LLVMValueRef callee = lp_get_called_value(cur);
6451
6452 if (!lp_is_function(callee))
6453 continue;
6454
6455 const char *name = LLVMGetValueName(callee);
6456 unsigned num_args = LLVMCountParams(callee);
6457
6458 /* Check if this is an export instruction. */
6459 if (num_args != 9 || strcmp(name, "llvm.SI.export"))
6460 continue;
6461
6462 LLVMValueRef arg = LLVMGetOperand(cur, 3);
6463 unsigned target = LLVMConstIntGetZExtValue(arg);
6464
6465 if (target < V_008DFC_SQ_EXP_PARAM)
6466 continue;
6467
6468 target -= V_008DFC_SQ_EXP_PARAM;
6469
6470 /* Eliminate constant value PARAM exports. */
6471 if (si_eliminate_const_output(ctx, cur, target)) {
6472 removed_any = true;
6473 } else {
6474 exports.offset[exports.num] = target;
6475 exports.inst[exports.num] = cur;
6476 exports.num++;
6477 }
6478 }
6479 bb = LLVMGetNextBasicBlock(bb);
6480 }
6481
6482 /* Remove holes in export memory due to removed PARAM exports.
6483 * This is done by renumbering all PARAM exports.
6484 */
6485 if (removed_any) {
6486 ubyte current_offset[SI_MAX_VS_OUTPUTS];
6487 unsigned new_count = 0;
6488 unsigned out, i;
6489
6490 /* Make a copy of the offsets. We need the old version while
6491 * we are modifying some of them. */
6492 assert(sizeof(current_offset) ==
6493 sizeof(shader->info.vs_output_param_offset));
6494 memcpy(current_offset, shader->info.vs_output_param_offset,
6495 sizeof(current_offset));
6496
6497 for (i = 0; i < exports.num; i++) {
6498 unsigned offset = exports.offset[i];
6499
6500 for (out = 0; out < info->num_outputs; out++) {
6501 if (current_offset[out] != offset)
6502 continue;
6503
6504 LLVMSetOperand(exports.inst[i], 3,
6505 LLVMConstInt(ctx->i32,
6506 V_008DFC_SQ_EXP_PARAM + new_count, 0));
6507 shader->info.vs_output_param_offset[out] = new_count;
6508 new_count++;
6509 break;
6510 }
6511 }
6512 shader->info.nr_param_exports = new_count;
6513 }
6514 }
6515
6516 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
6517 struct si_shader *shader)
6518 {
6519 struct si_shader_selector *sel = shader->selector;
6520 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
6521
6522 switch (ctx->type) {
6523 case PIPE_SHADER_VERTEX:
6524 ctx->load_input = declare_input_vs;
6525 if (shader->key.as_ls)
6526 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6527 else if (shader->key.as_es)
6528 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6529 else
6530 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6531 break;
6532 case PIPE_SHADER_TESS_CTRL:
6533 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6534 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6535 bld_base->emit_store = store_output_tcs;
6536 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6537 break;
6538 case PIPE_SHADER_TESS_EVAL:
6539 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6540 if (shader->key.as_es)
6541 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6542 else
6543 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6544 break;
6545 case PIPE_SHADER_GEOMETRY:
6546 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6547 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6548 break;
6549 case PIPE_SHADER_FRAGMENT:
6550 ctx->load_input = declare_input_fs;
6551 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6552 break;
6553 case PIPE_SHADER_COMPUTE:
6554 ctx->declare_memory_region = declare_compute_memory;
6555 break;
6556 default:
6557 assert(!"Unsupported shader type");
6558 return false;
6559 }
6560
6561 create_meta_data(ctx);
6562 create_function(ctx);
6563 preload_ring_buffers(ctx);
6564
6565 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6566 int i;
6567 for (i = 0; i < 4; i++) {
6568 ctx->gs_next_vertex[i] =
6569 lp_build_alloca(bld_base->base.gallivm,
6570 ctx->i32, "");
6571 }
6572 }
6573
6574 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6575 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6576 return false;
6577 }
6578
6579 si_llvm_build_ret(ctx, ctx->return_value);
6580 return true;
6581 }
6582
6583 /**
6584 * Compute the VS prolog key, which contains all the information needed to
6585 * build the VS prolog function, and set shader->info bits where needed.
6586 */
6587 static void si_get_vs_prolog_key(struct si_shader *shader,
6588 union si_shader_part_key *key)
6589 {
6590 struct tgsi_shader_info *info = &shader->selector->info;
6591
6592 memset(key, 0, sizeof(*key));
6593 key->vs_prolog.states = shader->key.part.vs.prolog;
6594 key->vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6595 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6596
6597 /* Set the instanceID flag. */
6598 for (unsigned i = 0; i < info->num_inputs; i++)
6599 if (key->vs_prolog.states.instance_divisors[i])
6600 shader->info.uses_instanceid = true;
6601 }
6602
6603 /**
6604 * Compute the VS epilog key, which contains all the information needed to
6605 * build the VS epilog function, and set the PrimitiveID output offset.
6606 */
6607 static void si_get_vs_epilog_key(struct si_shader *shader,
6608 struct si_vs_epilog_bits *states,
6609 union si_shader_part_key *key)
6610 {
6611 memset(key, 0, sizeof(*key));
6612 key->vs_epilog.states = *states;
6613
6614 /* Set up the PrimitiveID output. */
6615 if (shader->key.part.vs.epilog.export_prim_id) {
6616 unsigned index = shader->selector->info.num_outputs;
6617 unsigned offset = shader->info.nr_param_exports++;
6618
6619 key->vs_epilog.prim_id_param_offset = offset;
6620 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
6621 shader->info.vs_output_param_offset[index] = offset;
6622 }
6623 }
6624
6625 /**
6626 * Compute the PS prolog key, which contains all the information needed to
6627 * build the PS prolog function, and set related bits in shader->config.
6628 */
6629 static void si_get_ps_prolog_key(struct si_shader *shader,
6630 union si_shader_part_key *key,
6631 bool separate_prolog)
6632 {
6633 struct tgsi_shader_info *info = &shader->selector->info;
6634
6635 memset(key, 0, sizeof(*key));
6636 key->ps_prolog.states = shader->key.part.ps.prolog;
6637 key->ps_prolog.colors_read = info->colors_read;
6638 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6639 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6640 key->ps_prolog.wqm = info->uses_derivatives &&
6641 (key->ps_prolog.colors_read ||
6642 key->ps_prolog.states.force_persp_sample_interp ||
6643 key->ps_prolog.states.force_linear_sample_interp ||
6644 key->ps_prolog.states.force_persp_center_interp ||
6645 key->ps_prolog.states.force_linear_center_interp ||
6646 key->ps_prolog.states.bc_optimize_for_persp ||
6647 key->ps_prolog.states.bc_optimize_for_linear);
6648
6649 if (info->colors_read) {
6650 unsigned *color = shader->selector->color_attr_index;
6651
6652 if (shader->key.part.ps.prolog.color_two_side) {
6653 /* BCOLORs are stored after the last input. */
6654 key->ps_prolog.num_interp_inputs = info->num_inputs;
6655 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6656 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6657 }
6658
6659 for (unsigned i = 0; i < 2; i++) {
6660 unsigned interp = info->input_interpolate[color[i]];
6661 unsigned location = info->input_interpolate_loc[color[i]];
6662
6663 if (!(info->colors_read & (0xf << i*4)))
6664 continue;
6665
6666 key->ps_prolog.color_attr_index[i] = color[i];
6667
6668 if (shader->key.part.ps.prolog.flatshade_colors &&
6669 interp == TGSI_INTERPOLATE_COLOR)
6670 interp = TGSI_INTERPOLATE_CONSTANT;
6671
6672 switch (interp) {
6673 case TGSI_INTERPOLATE_CONSTANT:
6674 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6675 break;
6676 case TGSI_INTERPOLATE_PERSPECTIVE:
6677 case TGSI_INTERPOLATE_COLOR:
6678 /* Force the interpolation location for colors here. */
6679 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6680 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6681 if (shader->key.part.ps.prolog.force_persp_center_interp)
6682 location = TGSI_INTERPOLATE_LOC_CENTER;
6683
6684 switch (location) {
6685 case TGSI_INTERPOLATE_LOC_SAMPLE:
6686 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6687 shader->config.spi_ps_input_ena |=
6688 S_0286CC_PERSP_SAMPLE_ENA(1);
6689 break;
6690 case TGSI_INTERPOLATE_LOC_CENTER:
6691 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6692 shader->config.spi_ps_input_ena |=
6693 S_0286CC_PERSP_CENTER_ENA(1);
6694 break;
6695 case TGSI_INTERPOLATE_LOC_CENTROID:
6696 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6697 shader->config.spi_ps_input_ena |=
6698 S_0286CC_PERSP_CENTROID_ENA(1);
6699 break;
6700 default:
6701 assert(0);
6702 }
6703 break;
6704 case TGSI_INTERPOLATE_LINEAR:
6705 /* Force the interpolation location for colors here. */
6706 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6707 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6708 if (shader->key.part.ps.prolog.force_linear_center_interp)
6709 location = TGSI_INTERPOLATE_LOC_CENTER;
6710
6711 /* The VGPR assignment for non-monolithic shaders
6712 * works because InitialPSInputAddr is set on the
6713 * main shader and PERSP_PULL_MODEL is never used.
6714 */
6715 switch (location) {
6716 case TGSI_INTERPOLATE_LOC_SAMPLE:
6717 key->ps_prolog.color_interp_vgpr_index[i] =
6718 separate_prolog ? 6 : 9;
6719 shader->config.spi_ps_input_ena |=
6720 S_0286CC_LINEAR_SAMPLE_ENA(1);
6721 break;
6722 case TGSI_INTERPOLATE_LOC_CENTER:
6723 key->ps_prolog.color_interp_vgpr_index[i] =
6724 separate_prolog ? 8 : 11;
6725 shader->config.spi_ps_input_ena |=
6726 S_0286CC_LINEAR_CENTER_ENA(1);
6727 break;
6728 case TGSI_INTERPOLATE_LOC_CENTROID:
6729 key->ps_prolog.color_interp_vgpr_index[i] =
6730 separate_prolog ? 10 : 13;
6731 shader->config.spi_ps_input_ena |=
6732 S_0286CC_LINEAR_CENTROID_ENA(1);
6733 break;
6734 default:
6735 assert(0);
6736 }
6737 break;
6738 default:
6739 assert(0);
6740 }
6741 }
6742 }
6743 }
6744
6745 /**
6746 * Check whether a PS prolog is required based on the key.
6747 */
6748 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6749 {
6750 return key->ps_prolog.colors_read ||
6751 key->ps_prolog.states.force_persp_sample_interp ||
6752 key->ps_prolog.states.force_linear_sample_interp ||
6753 key->ps_prolog.states.force_persp_center_interp ||
6754 key->ps_prolog.states.force_linear_center_interp ||
6755 key->ps_prolog.states.bc_optimize_for_persp ||
6756 key->ps_prolog.states.bc_optimize_for_linear ||
6757 key->ps_prolog.states.poly_stipple;
6758 }
6759
6760 /**
6761 * Compute the PS epilog key, which contains all the information needed to
6762 * build the PS epilog function.
6763 */
6764 static void si_get_ps_epilog_key(struct si_shader *shader,
6765 union si_shader_part_key *key)
6766 {
6767 struct tgsi_shader_info *info = &shader->selector->info;
6768 memset(key, 0, sizeof(*key));
6769 key->ps_epilog.colors_written = info->colors_written;
6770 key->ps_epilog.writes_z = info->writes_z;
6771 key->ps_epilog.writes_stencil = info->writes_stencil;
6772 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6773 key->ps_epilog.states = shader->key.part.ps.epilog;
6774 }
6775
6776 /**
6777 * Build the GS prolog function. Rotate the input vertices for triangle strips
6778 * with adjacency.
6779 */
6780 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6781 union si_shader_part_key *key)
6782 {
6783 const unsigned num_sgprs = SI_GS_NUM_USER_SGPR + 2;
6784 const unsigned num_vgprs = 8;
6785 struct gallivm_state *gallivm = &ctx->gallivm;
6786 LLVMBuilderRef builder = gallivm->builder;
6787 LLVMTypeRef params[32];
6788 LLVMTypeRef returns[32];
6789 LLVMValueRef func, ret;
6790
6791 for (unsigned i = 0; i < num_sgprs; ++i) {
6792 params[i] = ctx->i32;
6793 returns[i] = ctx->i32;
6794 }
6795
6796 for (unsigned i = 0; i < num_vgprs; ++i) {
6797 params[num_sgprs + i] = ctx->i32;
6798 returns[num_sgprs + i] = ctx->f32;
6799 }
6800
6801 /* Create the function. */
6802 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6803 params, num_sgprs + num_vgprs, num_sgprs - 1);
6804 func = ctx->main_fn;
6805
6806 /* Copy inputs to outputs. This should be no-op, as the registers match,
6807 * but it will prevent the compiler from overwriting them unintentionally.
6808 */
6809 ret = ctx->return_value;
6810 for (unsigned i = 0; i < num_sgprs; i++) {
6811 LLVMValueRef p = LLVMGetParam(func, i);
6812 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6813 }
6814 for (unsigned i = 0; i < num_vgprs; i++) {
6815 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6816 p = LLVMBuildBitCast(builder, p, ctx->f32, "");
6817 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6818 }
6819
6820 if (key->gs_prolog.states.tri_strip_adj_fix) {
6821 /* Remap the input vertices for every other primitive. */
6822 const unsigned vtx_params[6] = {
6823 num_sgprs,
6824 num_sgprs + 1,
6825 num_sgprs + 3,
6826 num_sgprs + 4,
6827 num_sgprs + 5,
6828 num_sgprs + 6
6829 };
6830 LLVMValueRef prim_id, rotate;
6831
6832 prim_id = LLVMGetParam(func, num_sgprs + 2);
6833 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6834
6835 for (unsigned i = 0; i < 6; ++i) {
6836 LLVMValueRef base, rotated, actual;
6837 base = LLVMGetParam(func, vtx_params[i]);
6838 rotated = LLVMGetParam(func, vtx_params[(i + 4) % 6]);
6839 actual = LLVMBuildSelect(builder, rotate, rotated, base, "");
6840 actual = LLVMBuildBitCast(builder, actual, ctx->f32, "");
6841 ret = LLVMBuildInsertValue(builder, ret, actual, vtx_params[i], "");
6842 }
6843 }
6844
6845 LLVMBuildRet(builder, ret);
6846 }
6847
6848 /**
6849 * Given a list of shader part functions, build a wrapper function that
6850 * runs them in sequence to form a monolithic shader.
6851 */
6852 static void si_build_wrapper_function(struct si_shader_context *ctx,
6853 LLVMValueRef *parts,
6854 unsigned num_parts,
6855 unsigned main_part)
6856 {
6857 struct gallivm_state *gallivm = &ctx->gallivm;
6858 LLVMBuilderRef builder = ctx->gallivm.builder;
6859 /* PS epilog has one arg per color component */
6860 LLVMTypeRef param_types[48];
6861 LLVMValueRef out[48];
6862 LLVMTypeRef function_type;
6863 unsigned num_params;
6864 unsigned num_out;
6865 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6866 unsigned num_sgprs, num_vgprs;
6867 unsigned last_sgpr_param;
6868 unsigned gprs;
6869
6870 for (unsigned i = 0; i < num_parts; ++i) {
6871 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6872 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6873 }
6874
6875 /* The parameters of the wrapper function correspond to those of the
6876 * first part in terms of SGPRs and VGPRs, but we use the types of the
6877 * main part to get the right types. This is relevant for the
6878 * dereferenceable attribute on descriptor table pointers.
6879 */
6880 num_sgprs = 0;
6881 num_vgprs = 0;
6882
6883 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6884 num_params = LLVMCountParamTypes(function_type);
6885
6886 for (unsigned i = 0; i < num_params; ++i) {
6887 LLVMValueRef param = LLVMGetParam(parts[0], i);
6888
6889 if (ac_is_sgpr_param(param)) {
6890 assert(num_vgprs == 0);
6891 num_sgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
6892 } else {
6893 num_vgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
6894 }
6895 }
6896 assert(num_vgprs + num_sgprs <= ARRAY_SIZE(param_types));
6897
6898 num_params = 0;
6899 last_sgpr_param = 0;
6900 gprs = 0;
6901 while (gprs < num_sgprs + num_vgprs) {
6902 LLVMValueRef param = LLVMGetParam(parts[main_part], num_params);
6903 unsigned size;
6904
6905 param_types[num_params] = LLVMTypeOf(param);
6906 if (gprs < num_sgprs)
6907 last_sgpr_param = num_params;
6908 size = llvm_get_type_size(param_types[num_params]) / 4;
6909 num_params++;
6910
6911 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6912 assert(gprs + size <= num_sgprs + num_vgprs &&
6913 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6914
6915 gprs += size;
6916 }
6917
6918 si_create_function(ctx, "wrapper", NULL, 0, param_types, num_params, last_sgpr_param);
6919
6920 /* Record the arguments of the function as if they were an output of
6921 * a previous part.
6922 */
6923 num_out = 0;
6924 num_out_sgpr = 0;
6925
6926 for (unsigned i = 0; i < num_params; ++i) {
6927 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6928 LLVMTypeRef param_type = LLVMTypeOf(param);
6929 LLVMTypeRef out_type = i <= last_sgpr_param ? ctx->i32 : ctx->f32;
6930 unsigned size = llvm_get_type_size(param_type) / 4;
6931
6932 if (size == 1) {
6933 if (param_type != out_type)
6934 param = LLVMBuildBitCast(builder, param, out_type, "");
6935 out[num_out++] = param;
6936 } else {
6937 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6938
6939 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6940 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6941 param_type = ctx->i64;
6942 }
6943
6944 if (param_type != vector_type)
6945 param = LLVMBuildBitCast(builder, param, vector_type, "");
6946
6947 for (unsigned j = 0; j < size; ++j)
6948 out[num_out++] = LLVMBuildExtractElement(
6949 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6950 }
6951
6952 if (i <= last_sgpr_param)
6953 num_out_sgpr = num_out;
6954 }
6955
6956 /* Now chain the parts. */
6957 for (unsigned part = 0; part < num_parts; ++part) {
6958 LLVMValueRef in[48];
6959 LLVMValueRef ret;
6960 LLVMTypeRef ret_type;
6961 unsigned out_idx = 0;
6962
6963 num_params = LLVMCountParams(parts[part]);
6964 assert(num_params <= ARRAY_SIZE(param_types));
6965
6966 /* Derive arguments for the next part from outputs of the
6967 * previous one.
6968 */
6969 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6970 LLVMValueRef param;
6971 LLVMTypeRef param_type;
6972 bool is_sgpr;
6973 unsigned param_size;
6974 LLVMValueRef arg = NULL;
6975
6976 param = LLVMGetParam(parts[part], param_idx);
6977 param_type = LLVMTypeOf(param);
6978 param_size = llvm_get_type_size(param_type) / 4;
6979 is_sgpr = ac_is_sgpr_param(param);
6980
6981 if (is_sgpr) {
6982 #if HAVE_LLVM < 0x0400
6983 LLVMRemoveAttribute(param, LLVMByValAttribute);
6984 #else
6985 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
6986 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
6987 #endif
6988 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
6989 }
6990
6991 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6992 assert(is_sgpr || out_idx >= num_out_sgpr);
6993
6994 if (param_size == 1)
6995 arg = out[out_idx];
6996 else
6997 arg = lp_build_gather_values(gallivm, &out[out_idx], param_size);
6998
6999 if (LLVMTypeOf(arg) != param_type) {
7000 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7001 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
7002 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
7003 } else {
7004 arg = LLVMBuildBitCast(builder, arg, param_type, "");
7005 }
7006 }
7007
7008 in[param_idx] = arg;
7009 out_idx += param_size;
7010 }
7011
7012 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
7013 ret_type = LLVMTypeOf(ret);
7014
7015 /* Extract the returned GPRs. */
7016 num_out = 0;
7017 num_out_sgpr = 0;
7018
7019 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
7020 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
7021
7022 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
7023
7024 for (unsigned i = 0; i < ret_size; ++i) {
7025 LLVMValueRef val =
7026 LLVMBuildExtractValue(builder, ret, i, "");
7027
7028 out[num_out++] = val;
7029
7030 if (LLVMTypeOf(val) == ctx->i32) {
7031 assert(num_out_sgpr + 1 == num_out);
7032 num_out_sgpr = num_out;
7033 }
7034 }
7035 }
7036 }
7037
7038 LLVMBuildRetVoid(builder);
7039 }
7040
7041 int si_compile_tgsi_shader(struct si_screen *sscreen,
7042 LLVMTargetMachineRef tm,
7043 struct si_shader *shader,
7044 bool is_monolithic,
7045 struct pipe_debug_callback *debug)
7046 {
7047 struct si_shader_selector *sel = shader->selector;
7048 struct si_shader_context ctx;
7049 struct lp_build_tgsi_context *bld_base;
7050 LLVMModuleRef mod;
7051 int r = -1;
7052
7053 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
7054 * conversion fails. */
7055 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
7056 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
7057 tgsi_dump(sel->tokens, 0);
7058 si_dump_streamout(&sel->so);
7059 }
7060
7061 si_init_shader_ctx(&ctx, sscreen, shader, tm);
7062 ctx.separate_prolog = !is_monolithic;
7063
7064 memset(shader->info.vs_output_param_offset, 0xff,
7065 sizeof(shader->info.vs_output_param_offset));
7066
7067 shader->info.uses_instanceid = sel->info.uses_instanceid;
7068
7069 bld_base = &ctx.soa.bld_base;
7070 ctx.load_system_value = declare_system_value;
7071
7072 if (!si_compile_tgsi_main(&ctx, shader)) {
7073 si_llvm_dispose(&ctx);
7074 return -1;
7075 }
7076
7077 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
7078 LLVMValueRef parts[3];
7079 bool need_prolog;
7080 bool need_epilog;
7081
7082 need_prolog = sel->info.num_inputs;
7083 need_epilog = !shader->key.as_es && !shader->key.as_ls;
7084
7085 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7086
7087 if (need_prolog) {
7088 union si_shader_part_key prolog_key;
7089 si_get_vs_prolog_key(shader, &prolog_key);
7090 si_build_vs_prolog_function(&ctx, &prolog_key);
7091 parts[0] = ctx.main_fn;
7092 }
7093
7094 if (need_epilog) {
7095 union si_shader_part_key epilog_key;
7096 si_get_vs_epilog_key(shader, &shader->key.part.vs.epilog, &epilog_key);
7097 si_build_vs_epilog_function(&ctx, &epilog_key);
7098 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7099 }
7100
7101 si_build_wrapper_function(&ctx, parts, 1 + need_prolog + need_epilog,
7102 need_prolog ? 1 : 0);
7103 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
7104 LLVMValueRef parts[2];
7105 union si_shader_part_key epilog_key;
7106
7107 parts[0] = ctx.main_fn;
7108
7109 memset(&epilog_key, 0, sizeof(epilog_key));
7110 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7111 si_build_tcs_epilog_function(&ctx, &epilog_key);
7112 parts[1] = ctx.main_fn;
7113
7114 si_build_wrapper_function(&ctx, parts, 2, 0);
7115 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_EVAL &&
7116 !shader->key.as_es) {
7117 LLVMValueRef parts[2];
7118 union si_shader_part_key epilog_key;
7119
7120 parts[0] = ctx.main_fn;
7121
7122 si_get_vs_epilog_key(shader, &shader->key.part.tes.epilog, &epilog_key);
7123 si_build_vs_epilog_function(&ctx, &epilog_key);
7124 parts[1] = ctx.main_fn;
7125
7126 si_build_wrapper_function(&ctx, parts, 2, 0);
7127 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
7128 LLVMValueRef parts[2];
7129 union si_shader_part_key prolog_key;
7130
7131 parts[1] = ctx.main_fn;
7132
7133 memset(&prolog_key, 0, sizeof(prolog_key));
7134 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7135 si_build_gs_prolog_function(&ctx, &prolog_key);
7136 parts[0] = ctx.main_fn;
7137
7138 si_build_wrapper_function(&ctx, parts, 2, 1);
7139 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
7140 LLVMValueRef parts[3];
7141 union si_shader_part_key prolog_key;
7142 union si_shader_part_key epilog_key;
7143 bool need_prolog;
7144
7145 si_get_ps_prolog_key(shader, &prolog_key, false);
7146 need_prolog = si_need_ps_prolog(&prolog_key);
7147
7148 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7149
7150 if (need_prolog) {
7151 si_build_ps_prolog_function(&ctx, &prolog_key);
7152 parts[0] = ctx.main_fn;
7153 }
7154
7155 si_get_ps_epilog_key(shader, &epilog_key);
7156 si_build_ps_epilog_function(&ctx, &epilog_key);
7157 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7158
7159 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2, need_prolog ? 1 : 0);
7160 }
7161
7162 mod = bld_base->base.gallivm->module;
7163
7164 /* Dump LLVM IR before any optimization passes */
7165 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
7166 r600_can_dump_shader(&sscreen->b, ctx.type))
7167 LLVMDumpModule(mod);
7168
7169 si_llvm_finalize_module(&ctx,
7170 r600_extra_shader_checks(&sscreen->b, ctx.type));
7171
7172 /* Post-optimization transformations. */
7173 si_eliminate_const_vs_outputs(&ctx);
7174
7175 /* Compile to bytecode. */
7176 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
7177 mod, debug, ctx.type, "TGSI shader");
7178 si_llvm_dispose(&ctx);
7179 if (r) {
7180 fprintf(stderr, "LLVM failed to compile shader\n");
7181 return r;
7182 }
7183
7184 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
7185 * LLVM 3.9svn has this bug.
7186 */
7187 if (sel->type == PIPE_SHADER_COMPUTE) {
7188 unsigned *props = sel->info.properties;
7189 unsigned wave_size = 64;
7190 unsigned max_vgprs = 256;
7191 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
7192 unsigned max_sgprs_per_wave = 128;
7193 unsigned max_block_threads;
7194
7195 if (props[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH])
7196 max_block_threads = props[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
7197 props[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
7198 props[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
7199 else
7200 max_block_threads = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
7201
7202 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
7203 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
7204
7205 max_vgprs = max_vgprs / min_waves_per_simd;
7206 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
7207
7208 if (shader->config.num_sgprs > max_sgprs ||
7209 shader->config.num_vgprs > max_vgprs) {
7210 fprintf(stderr, "LLVM failed to compile a shader correctly: "
7211 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7212 shader->config.num_sgprs, shader->config.num_vgprs,
7213 max_sgprs, max_vgprs);
7214
7215 /* Just terminate the process, because dependent
7216 * shaders can hang due to bad input data, but use
7217 * the env var to allow shader-db to work.
7218 */
7219 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7220 abort();
7221 }
7222 }
7223
7224 /* Add the scratch offset to input SGPRs. */
7225 if (shader->config.scratch_bytes_per_wave)
7226 shader->info.num_input_sgprs += 1; /* scratch byte offset */
7227
7228 /* Calculate the number of fragment input VGPRs. */
7229 if (ctx.type == PIPE_SHADER_FRAGMENT) {
7230 shader->info.num_input_vgprs = 0;
7231 shader->info.face_vgpr_index = -1;
7232
7233 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7234 shader->info.num_input_vgprs += 2;
7235 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
7236 shader->info.num_input_vgprs += 2;
7237 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
7238 shader->info.num_input_vgprs += 2;
7239 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
7240 shader->info.num_input_vgprs += 3;
7241 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7242 shader->info.num_input_vgprs += 2;
7243 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7244 shader->info.num_input_vgprs += 2;
7245 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7246 shader->info.num_input_vgprs += 2;
7247 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7248 shader->info.num_input_vgprs += 1;
7249 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7250 shader->info.num_input_vgprs += 1;
7251 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7252 shader->info.num_input_vgprs += 1;
7253 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7254 shader->info.num_input_vgprs += 1;
7255 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7256 shader->info.num_input_vgprs += 1;
7257 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7258 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7259 shader->info.num_input_vgprs += 1;
7260 }
7261 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
7262 shader->info.num_input_vgprs += 1;
7263 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7264 shader->info.num_input_vgprs += 1;
7265 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7266 shader->info.num_input_vgprs += 1;
7267 }
7268
7269 return 0;
7270 }
7271
7272 /**
7273 * Create, compile and return a shader part (prolog or epilog).
7274 *
7275 * \param sscreen screen
7276 * \param list list of shader parts of the same category
7277 * \param type shader type
7278 * \param key shader part key
7279 * \param prolog whether the part being requested is a prolog
7280 * \param tm LLVM target machine
7281 * \param debug debug callback
7282 * \param build the callback responsible for building the main function
7283 * \return non-NULL on success
7284 */
7285 static struct si_shader_part *
7286 si_get_shader_part(struct si_screen *sscreen,
7287 struct si_shader_part **list,
7288 enum pipe_shader_type type,
7289 bool prolog,
7290 union si_shader_part_key *key,
7291 LLVMTargetMachineRef tm,
7292 struct pipe_debug_callback *debug,
7293 void (*build)(struct si_shader_context *,
7294 union si_shader_part_key *),
7295 const char *name)
7296 {
7297 struct si_shader_part *result;
7298
7299 pipe_mutex_lock(sscreen->shader_parts_mutex);
7300
7301 /* Find existing. */
7302 for (result = *list; result; result = result->next) {
7303 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7304 pipe_mutex_unlock(sscreen->shader_parts_mutex);
7305 return result;
7306 }
7307 }
7308
7309 /* Compile a new one. */
7310 result = CALLOC_STRUCT(si_shader_part);
7311 result->key = *key;
7312
7313 struct si_shader shader = {};
7314 struct si_shader_context ctx;
7315 struct gallivm_state *gallivm = &ctx.gallivm;
7316
7317 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7318 ctx.type = type;
7319
7320 switch (type) {
7321 case PIPE_SHADER_VERTEX:
7322 break;
7323 case PIPE_SHADER_TESS_CTRL:
7324 assert(!prolog);
7325 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7326 break;
7327 case PIPE_SHADER_GEOMETRY:
7328 assert(prolog);
7329 break;
7330 case PIPE_SHADER_FRAGMENT:
7331 if (prolog)
7332 shader.key.part.ps.prolog = key->ps_prolog.states;
7333 else
7334 shader.key.part.ps.epilog = key->ps_epilog.states;
7335 break;
7336 default:
7337 unreachable("bad shader part");
7338 }
7339
7340 build(&ctx, key);
7341
7342 /* Compile. */
7343 si_llvm_finalize_module(&ctx,
7344 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT));
7345
7346 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7347 gallivm->module, debug, ctx.type, name)) {
7348 FREE(result);
7349 result = NULL;
7350 goto out;
7351 }
7352
7353 result->next = *list;
7354 *list = result;
7355
7356 out:
7357 si_llvm_dispose(&ctx);
7358 pipe_mutex_unlock(sscreen->shader_parts_mutex);
7359 return result;
7360 }
7361
7362 /**
7363 * Build the vertex shader prolog function.
7364 *
7365 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7366 * All inputs are returned unmodified. The vertex load indices are
7367 * stored after them, which will be used by the API VS for fetching inputs.
7368 *
7369 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7370 * input_v0,
7371 * input_v1,
7372 * input_v2,
7373 * input_v3,
7374 * (VertexID + BaseVertex),
7375 * (InstanceID + StartInstance),
7376 * (InstanceID / 2 + StartInstance)
7377 */
7378 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7379 union si_shader_part_key *key)
7380 {
7381 struct gallivm_state *gallivm = &ctx->gallivm;
7382 LLVMTypeRef *params, *returns;
7383 LLVMValueRef ret, func;
7384 int last_sgpr, num_params, num_returns, i;
7385
7386 ctx->param_vertex_id = key->vs_prolog.num_input_sgprs;
7387 ctx->param_instance_id = key->vs_prolog.num_input_sgprs + 3;
7388
7389 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7390 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
7391 sizeof(LLVMTypeRef));
7392 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
7393 key->vs_prolog.last_input + 1) *
7394 sizeof(LLVMTypeRef));
7395 num_params = 0;
7396 num_returns = 0;
7397
7398 /* Declare input and output SGPRs. */
7399 num_params = 0;
7400 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7401 params[num_params++] = ctx->i32;
7402 returns[num_returns++] = ctx->i32;
7403 }
7404 last_sgpr = num_params - 1;
7405
7406 /* 4 preloaded VGPRs (outputs must be floats) */
7407 for (i = 0; i < 4; i++) {
7408 params[num_params++] = ctx->i32;
7409 returns[num_returns++] = ctx->f32;
7410 }
7411
7412 /* Vertex load indices. */
7413 for (i = 0; i <= key->vs_prolog.last_input; i++)
7414 returns[num_returns++] = ctx->f32;
7415
7416 /* Create the function. */
7417 si_create_function(ctx, "vs_prolog", returns, num_returns, params,
7418 num_params, last_sgpr);
7419 func = ctx->main_fn;
7420
7421 /* Copy inputs to outputs. This should be no-op, as the registers match,
7422 * but it will prevent the compiler from overwriting them unintentionally.
7423 */
7424 ret = ctx->return_value;
7425 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7426 LLVMValueRef p = LLVMGetParam(func, i);
7427 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7428 }
7429 for (i = num_params - 4; i < num_params; i++) {
7430 LLVMValueRef p = LLVMGetParam(func, i);
7431 p = LLVMBuildBitCast(gallivm->builder, p, ctx->f32, "");
7432 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7433 }
7434
7435 /* Compute vertex load indices from instance divisors. */
7436 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7437 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
7438 LLVMValueRef index;
7439
7440 if (divisor) {
7441 /* InstanceID / Divisor + StartInstance */
7442 index = get_instance_index_for_fetch(ctx,
7443 SI_SGPR_START_INSTANCE,
7444 divisor);
7445 } else {
7446 /* VertexID + BaseVertex */
7447 index = LLVMBuildAdd(gallivm->builder,
7448 LLVMGetParam(func, ctx->param_vertex_id),
7449 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
7450 }
7451
7452 index = LLVMBuildBitCast(gallivm->builder, index, ctx->f32, "");
7453 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
7454 num_params++, "");
7455 }
7456
7457 si_llvm_build_ret(ctx, ret);
7458 }
7459
7460 /**
7461 * Build the vertex shader epilog function. This is also used by the tessellation
7462 * evaluation shader compiled as VS.
7463 *
7464 * The input is PrimitiveID.
7465 *
7466 * If PrimitiveID is required by the pixel shader, export it.
7467 * Otherwise, do nothing.
7468 */
7469 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
7470 union si_shader_part_key *key)
7471 {
7472 struct gallivm_state *gallivm = &ctx->gallivm;
7473 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
7474 LLVMTypeRef params[5];
7475 int num_params, i;
7476
7477 /* Declare input VGPRs. */
7478 num_params = key->vs_epilog.states.export_prim_id ?
7479 (VS_EPILOG_PRIMID_LOC + 1) : 0;
7480 assert(num_params <= ARRAY_SIZE(params));
7481
7482 for (i = 0; i < num_params; i++)
7483 params[i] = ctx->f32;
7484
7485 /* Create the function. */
7486 si_create_function(ctx, "vs_epilog", NULL, 0, params, num_params, -1);
7487
7488 /* Emit exports. */
7489 if (key->vs_epilog.states.export_prim_id) {
7490 struct lp_build_context *base = &bld_base->base;
7491 struct lp_build_context *uint = &bld_base->uint_bld;
7492 LLVMValueRef args[9];
7493
7494 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
7495 args[1] = uint->zero; /* whether the EXEC mask is valid */
7496 args[2] = uint->zero; /* DONE bit */
7497 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
7498 key->vs_epilog.prim_id_param_offset);
7499 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
7500 args[5] = LLVMGetParam(ctx->main_fn,
7501 VS_EPILOG_PRIMID_LOC); /* X */
7502 args[6] = base->undef; /* Y */
7503 args[7] = base->undef; /* Z */
7504 args[8] = base->undef; /* W */
7505
7506 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
7507 LLVMVoidTypeInContext(base->gallivm->context),
7508 args, 9, 0);
7509 }
7510
7511 LLVMBuildRetVoid(gallivm->builder);
7512 }
7513
7514 /**
7515 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7516 */
7517 static bool si_get_vs_epilog(struct si_screen *sscreen,
7518 LLVMTargetMachineRef tm,
7519 struct si_shader *shader,
7520 struct pipe_debug_callback *debug,
7521 struct si_vs_epilog_bits *states)
7522 {
7523 union si_shader_part_key epilog_key;
7524
7525 si_get_vs_epilog_key(shader, states, &epilog_key);
7526
7527 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
7528 PIPE_SHADER_VERTEX, true,
7529 &epilog_key, tm, debug,
7530 si_build_vs_epilog_function,
7531 "Vertex Shader Epilog");
7532 return shader->epilog != NULL;
7533 }
7534
7535 /**
7536 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7537 */
7538 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7539 LLVMTargetMachineRef tm,
7540 struct si_shader *shader,
7541 struct pipe_debug_callback *debug)
7542 {
7543 struct tgsi_shader_info *info = &shader->selector->info;
7544 union si_shader_part_key prolog_key;
7545
7546 /* Get the prolog. */
7547 si_get_vs_prolog_key(shader, &prolog_key);
7548
7549 /* The prolog is a no-op if there are no inputs. */
7550 if (info->num_inputs) {
7551 shader->prolog =
7552 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7553 PIPE_SHADER_VERTEX, true,
7554 &prolog_key, tm, debug,
7555 si_build_vs_prolog_function,
7556 "Vertex Shader Prolog");
7557 if (!shader->prolog)
7558 return false;
7559 }
7560
7561 /* Get the epilog. */
7562 if (!shader->key.as_es && !shader->key.as_ls &&
7563 !si_get_vs_epilog(sscreen, tm, shader, debug,
7564 &shader->key.part.vs.epilog))
7565 return false;
7566
7567 return true;
7568 }
7569
7570 /**
7571 * Select and compile (or reuse) TES parts (epilog).
7572 */
7573 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
7574 LLVMTargetMachineRef tm,
7575 struct si_shader *shader,
7576 struct pipe_debug_callback *debug)
7577 {
7578 if (shader->key.as_es)
7579 return true;
7580
7581 /* TES compiled as VS. */
7582 return si_get_vs_epilog(sscreen, tm, shader, debug,
7583 &shader->key.part.tes.epilog);
7584 }
7585
7586 /**
7587 * Compile the TCS epilog function. This writes tesselation factors to memory
7588 * based on the output primitive type of the tesselator (determined by TES).
7589 */
7590 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7591 union si_shader_part_key *key)
7592 {
7593 struct gallivm_state *gallivm = &ctx->gallivm;
7594 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
7595 LLVMTypeRef params[16];
7596 LLVMValueRef func;
7597 int last_sgpr, num_params;
7598
7599 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
7600 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
7601 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
7602 params[SI_PARAM_SAMPLERS] = ctx->i64;
7603 params[SI_PARAM_IMAGES] = ctx->i64;
7604 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
7605 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
7606 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
7607 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
7608 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
7609 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
7610 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
7611 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
7612 num_params = last_sgpr + 1;
7613
7614 params[num_params++] = ctx->i32; /* patch index within the wave (REL_PATCH_ID) */
7615 params[num_params++] = ctx->i32; /* invocation ID within the patch */
7616 params[num_params++] = ctx->i32; /* LDS offset where tess factors should be loaded from */
7617
7618 /* Create the function. */
7619 si_create_function(ctx, "tcs_epilog", NULL, 0, params, num_params, last_sgpr);
7620 declare_tess_lds(ctx);
7621 func = ctx->main_fn;
7622
7623 si_write_tess_factors(bld_base,
7624 LLVMGetParam(func, last_sgpr + 1),
7625 LLVMGetParam(func, last_sgpr + 2),
7626 LLVMGetParam(func, last_sgpr + 3));
7627
7628 LLVMBuildRetVoid(gallivm->builder);
7629 }
7630
7631 /**
7632 * Select and compile (or reuse) TCS parts (epilog).
7633 */
7634 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7635 LLVMTargetMachineRef tm,
7636 struct si_shader *shader,
7637 struct pipe_debug_callback *debug)
7638 {
7639 union si_shader_part_key epilog_key;
7640
7641 /* Get the epilog. */
7642 memset(&epilog_key, 0, sizeof(epilog_key));
7643 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7644
7645 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7646 PIPE_SHADER_TESS_CTRL, false,
7647 &epilog_key, tm, debug,
7648 si_build_tcs_epilog_function,
7649 "Tessellation Control Shader Epilog");
7650 return shader->epilog != NULL;
7651 }
7652
7653 /**
7654 * Select and compile (or reuse) GS parts (prolog).
7655 */
7656 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7657 LLVMTargetMachineRef tm,
7658 struct si_shader *shader,
7659 struct pipe_debug_callback *debug)
7660 {
7661 union si_shader_part_key prolog_key;
7662
7663 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7664 return true;
7665
7666 memset(&prolog_key, 0, sizeof(prolog_key));
7667 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7668
7669 shader->prolog = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7670 PIPE_SHADER_GEOMETRY, true,
7671 &prolog_key, tm, debug,
7672 si_build_gs_prolog_function,
7673 "Geometry Shader Prolog");
7674 return shader->prolog != NULL;
7675 }
7676
7677 /**
7678 * Build the pixel shader prolog function. This handles:
7679 * - two-side color selection and interpolation
7680 * - overriding interpolation parameters for the API PS
7681 * - polygon stippling
7682 *
7683 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7684 * overriden by other states. (e.g. per-sample interpolation)
7685 * Interpolated colors are stored after the preloaded VGPRs.
7686 */
7687 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7688 union si_shader_part_key *key)
7689 {
7690 struct gallivm_state *gallivm = &ctx->gallivm;
7691 LLVMTypeRef *params;
7692 LLVMValueRef ret, func;
7693 int last_sgpr, num_params, num_returns, i, num_color_channels;
7694
7695 assert(si_need_ps_prolog(key));
7696
7697 /* Number of inputs + 8 color elements. */
7698 params = alloca((key->ps_prolog.num_input_sgprs +
7699 key->ps_prolog.num_input_vgprs + 8) *
7700 sizeof(LLVMTypeRef));
7701
7702 /* Declare inputs. */
7703 num_params = 0;
7704 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7705 params[num_params++] = ctx->i32;
7706 last_sgpr = num_params - 1;
7707
7708 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7709 params[num_params++] = ctx->f32;
7710
7711 /* Declare outputs (same as inputs + add colors if needed) */
7712 num_returns = num_params;
7713 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7714 for (i = 0; i < num_color_channels; i++)
7715 params[num_returns++] = ctx->f32;
7716
7717 /* Create the function. */
7718 si_create_function(ctx, "ps_prolog", params, num_returns, params,
7719 num_params, last_sgpr);
7720 func = ctx->main_fn;
7721
7722 /* Copy inputs to outputs. This should be no-op, as the registers match,
7723 * but it will prevent the compiler from overwriting them unintentionally.
7724 */
7725 ret = ctx->return_value;
7726 for (i = 0; i < num_params; i++) {
7727 LLVMValueRef p = LLVMGetParam(func, i);
7728 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7729 }
7730
7731 /* Polygon stippling. */
7732 if (key->ps_prolog.states.poly_stipple) {
7733 /* POS_FIXED_PT is always last. */
7734 unsigned pos = key->ps_prolog.num_input_sgprs +
7735 key->ps_prolog.num_input_vgprs - 1;
7736 LLVMValueRef ptr[2], list;
7737
7738 /* Get the pointer to rw buffers. */
7739 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
7740 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
7741 list = lp_build_gather_values(gallivm, ptr, 2);
7742 list = LLVMBuildBitCast(gallivm->builder, list, ctx->i64, "");
7743 list = LLVMBuildIntToPtr(gallivm->builder, list,
7744 const_array(ctx->v16i8, SI_NUM_RW_BUFFERS), "");
7745
7746 si_llvm_emit_polygon_stipple(ctx, list, pos);
7747 }
7748
7749 if (key->ps_prolog.states.bc_optimize_for_persp ||
7750 key->ps_prolog.states.bc_optimize_for_linear) {
7751 unsigned i, base = key->ps_prolog.num_input_sgprs;
7752 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7753
7754 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7755 * The hw doesn't compute CENTROID if the whole wave only
7756 * contains fully-covered quads.
7757 *
7758 * PRIM_MASK is after user SGPRs.
7759 */
7760 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7761 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
7762 LLVMConstInt(ctx->i32, 31, 0), "");
7763 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
7764 ctx->i1, "");
7765
7766 if (key->ps_prolog.states.bc_optimize_for_persp) {
7767 /* Read PERSP_CENTER. */
7768 for (i = 0; i < 2; i++)
7769 center[i] = LLVMGetParam(func, base + 2 + i);
7770 /* Read PERSP_CENTROID. */
7771 for (i = 0; i < 2; i++)
7772 centroid[i] = LLVMGetParam(func, base + 4 + i);
7773 /* Select PERSP_CENTROID. */
7774 for (i = 0; i < 2; i++) {
7775 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7776 center[i], centroid[i], "");
7777 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7778 tmp, base + 4 + i, "");
7779 }
7780 }
7781 if (key->ps_prolog.states.bc_optimize_for_linear) {
7782 /* Read LINEAR_CENTER. */
7783 for (i = 0; i < 2; i++)
7784 center[i] = LLVMGetParam(func, base + 8 + i);
7785 /* Read LINEAR_CENTROID. */
7786 for (i = 0; i < 2; i++)
7787 centroid[i] = LLVMGetParam(func, base + 10 + i);
7788 /* Select LINEAR_CENTROID. */
7789 for (i = 0; i < 2; i++) {
7790 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7791 center[i], centroid[i], "");
7792 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7793 tmp, base + 10 + i, "");
7794 }
7795 }
7796 }
7797
7798 /* Force per-sample interpolation. */
7799 if (key->ps_prolog.states.force_persp_sample_interp) {
7800 unsigned i, base = key->ps_prolog.num_input_sgprs;
7801 LLVMValueRef persp_sample[2];
7802
7803 /* Read PERSP_SAMPLE. */
7804 for (i = 0; i < 2; i++)
7805 persp_sample[i] = LLVMGetParam(func, base + i);
7806 /* Overwrite PERSP_CENTER. */
7807 for (i = 0; i < 2; i++)
7808 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7809 persp_sample[i], base + 2 + i, "");
7810 /* Overwrite PERSP_CENTROID. */
7811 for (i = 0; i < 2; i++)
7812 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7813 persp_sample[i], base + 4 + i, "");
7814 }
7815 if (key->ps_prolog.states.force_linear_sample_interp) {
7816 unsigned i, base = key->ps_prolog.num_input_sgprs;
7817 LLVMValueRef linear_sample[2];
7818
7819 /* Read LINEAR_SAMPLE. */
7820 for (i = 0; i < 2; i++)
7821 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7822 /* Overwrite LINEAR_CENTER. */
7823 for (i = 0; i < 2; i++)
7824 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7825 linear_sample[i], base + 8 + i, "");
7826 /* Overwrite LINEAR_CENTROID. */
7827 for (i = 0; i < 2; i++)
7828 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7829 linear_sample[i], base + 10 + i, "");
7830 }
7831
7832 /* Force center interpolation. */
7833 if (key->ps_prolog.states.force_persp_center_interp) {
7834 unsigned i, base = key->ps_prolog.num_input_sgprs;
7835 LLVMValueRef persp_center[2];
7836
7837 /* Read PERSP_CENTER. */
7838 for (i = 0; i < 2; i++)
7839 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7840 /* Overwrite PERSP_SAMPLE. */
7841 for (i = 0; i < 2; i++)
7842 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7843 persp_center[i], base + i, "");
7844 /* Overwrite PERSP_CENTROID. */
7845 for (i = 0; i < 2; i++)
7846 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7847 persp_center[i], base + 4 + i, "");
7848 }
7849 if (key->ps_prolog.states.force_linear_center_interp) {
7850 unsigned i, base = key->ps_prolog.num_input_sgprs;
7851 LLVMValueRef linear_center[2];
7852
7853 /* Read LINEAR_CENTER. */
7854 for (i = 0; i < 2; i++)
7855 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7856 /* Overwrite LINEAR_SAMPLE. */
7857 for (i = 0; i < 2; i++)
7858 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7859 linear_center[i], base + 6 + i, "");
7860 /* Overwrite LINEAR_CENTROID. */
7861 for (i = 0; i < 2; i++)
7862 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7863 linear_center[i], base + 10 + i, "");
7864 }
7865
7866 /* Interpolate colors. */
7867 for (i = 0; i < 2; i++) {
7868 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7869 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7870 key->ps_prolog.face_vgpr_index;
7871 LLVMValueRef interp[2], color[4];
7872 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7873
7874 if (!writemask)
7875 continue;
7876
7877 /* If the interpolation qualifier is not CONSTANT (-1). */
7878 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7879 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7880 key->ps_prolog.color_interp_vgpr_index[i];
7881
7882 /* Get the (i,j) updated by bc_optimize handling. */
7883 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
7884 interp_vgpr, "");
7885 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
7886 interp_vgpr + 1, "");
7887 interp_ij = lp_build_gather_values(gallivm, interp, 2);
7888 interp_ij = LLVMBuildBitCast(gallivm->builder, interp_ij,
7889 ctx->v2i32, "");
7890 }
7891
7892 /* Use the absolute location of the input. */
7893 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7894
7895 if (key->ps_prolog.states.color_two_side) {
7896 face = LLVMGetParam(func, face_vgpr);
7897 face = LLVMBuildBitCast(gallivm->builder, face, ctx->i32, "");
7898 }
7899
7900 interp_fs_input(ctx,
7901 key->ps_prolog.color_attr_index[i],
7902 TGSI_SEMANTIC_COLOR, i,
7903 key->ps_prolog.num_interp_inputs,
7904 key->ps_prolog.colors_read, interp_ij,
7905 prim_mask, face, color);
7906
7907 while (writemask) {
7908 unsigned chan = u_bit_scan(&writemask);
7909 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
7910 num_params++, "");
7911 }
7912 }
7913
7914 /* Tell LLVM to insert WQM instruction sequence when needed. */
7915 if (key->ps_prolog.wqm) {
7916 LLVMAddTargetDependentFunctionAttr(func,
7917 "amdgpu-ps-wqm-outputs", "");
7918 }
7919
7920 si_llvm_build_ret(ctx, ret);
7921 }
7922
7923 /**
7924 * Build the pixel shader epilog function. This handles everything that must be
7925 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7926 */
7927 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7928 union si_shader_part_key *key)
7929 {
7930 struct gallivm_state *gallivm = &ctx->gallivm;
7931 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
7932 LLVMTypeRef params[16+8*4+3];
7933 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7934 int last_sgpr, num_params, i;
7935 struct si_ps_exports exp = {};
7936
7937 /* Declare input SGPRs. */
7938 params[SI_PARAM_RW_BUFFERS] = ctx->i64;
7939 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
7940 params[SI_PARAM_SAMPLERS] = ctx->i64;
7941 params[SI_PARAM_IMAGES] = ctx->i64;
7942 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
7943 params[SI_PARAM_ALPHA_REF] = ctx->f32;
7944 last_sgpr = SI_PARAM_ALPHA_REF;
7945
7946 /* Declare input VGPRs. */
7947 num_params = (last_sgpr + 1) +
7948 util_bitcount(key->ps_epilog.colors_written) * 4 +
7949 key->ps_epilog.writes_z +
7950 key->ps_epilog.writes_stencil +
7951 key->ps_epilog.writes_samplemask;
7952
7953 num_params = MAX2(num_params,
7954 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7955
7956 assert(num_params <= ARRAY_SIZE(params));
7957
7958 for (i = last_sgpr + 1; i < num_params; i++)
7959 params[i] = ctx->f32;
7960
7961 /* Create the function. */
7962 si_create_function(ctx, "ps_epilog", NULL, 0, params, num_params, last_sgpr);
7963 /* Disable elimination of unused inputs. */
7964 si_llvm_add_attribute(ctx->main_fn,
7965 "InitialPSInputAddr", 0xffffff);
7966
7967 /* Process colors. */
7968 unsigned vgpr = last_sgpr + 1;
7969 unsigned colors_written = key->ps_epilog.colors_written;
7970 int last_color_export = -1;
7971
7972 /* Find the last color export. */
7973 if (!key->ps_epilog.writes_z &&
7974 !key->ps_epilog.writes_stencil &&
7975 !key->ps_epilog.writes_samplemask) {
7976 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7977
7978 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7979 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7980 /* Just set this if any of the colorbuffers are enabled. */
7981 if (spi_format &
7982 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7983 last_color_export = 0;
7984 } else {
7985 for (i = 0; i < 8; i++)
7986 if (colors_written & (1 << i) &&
7987 (spi_format >> (i * 4)) & 0xf)
7988 last_color_export = i;
7989 }
7990 }
7991
7992 while (colors_written) {
7993 LLVMValueRef color[4];
7994 int mrt = u_bit_scan(&colors_written);
7995
7996 for (i = 0; i < 4; i++)
7997 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7998
7999 si_export_mrt_color(bld_base, color, mrt,
8000 num_params - 1,
8001 mrt == last_color_export, &exp);
8002 }
8003
8004 /* Process depth, stencil, samplemask. */
8005 if (key->ps_epilog.writes_z)
8006 depth = LLVMGetParam(ctx->main_fn, vgpr++);
8007 if (key->ps_epilog.writes_stencil)
8008 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
8009 if (key->ps_epilog.writes_samplemask)
8010 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
8011
8012 if (depth || stencil || samplemask)
8013 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
8014 else if (last_color_export == -1)
8015 si_export_null(bld_base);
8016
8017 if (exp.num)
8018 si_emit_ps_exports(ctx, &exp);
8019
8020 /* Compile. */
8021 LLVMBuildRetVoid(gallivm->builder);
8022 }
8023
8024 /**
8025 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
8026 */
8027 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
8028 LLVMTargetMachineRef tm,
8029 struct si_shader *shader,
8030 struct pipe_debug_callback *debug)
8031 {
8032 union si_shader_part_key prolog_key;
8033 union si_shader_part_key epilog_key;
8034
8035 /* Get the prolog. */
8036 si_get_ps_prolog_key(shader, &prolog_key, true);
8037
8038 /* The prolog is a no-op if these aren't set. */
8039 if (si_need_ps_prolog(&prolog_key)) {
8040 shader->prolog =
8041 si_get_shader_part(sscreen, &sscreen->ps_prologs,
8042 PIPE_SHADER_FRAGMENT, true,
8043 &prolog_key, tm, debug,
8044 si_build_ps_prolog_function,
8045 "Fragment Shader Prolog");
8046 if (!shader->prolog)
8047 return false;
8048 }
8049
8050 /* Get the epilog. */
8051 si_get_ps_epilog_key(shader, &epilog_key);
8052
8053 shader->epilog =
8054 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
8055 PIPE_SHADER_FRAGMENT, false,
8056 &epilog_key, tm, debug,
8057 si_build_ps_epilog_function,
8058 "Fragment Shader Epilog");
8059 if (!shader->epilog)
8060 return false;
8061
8062 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
8063 if (shader->key.part.ps.prolog.poly_stipple) {
8064 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
8065 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
8066 }
8067
8068 /* Set up the enable bits for per-sample shading if needed. */
8069 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
8070 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8071 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8072 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
8073 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8074 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
8075 }
8076 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
8077 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8078 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8079 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
8080 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8081 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
8082 }
8083 if (shader->key.part.ps.prolog.force_persp_center_interp &&
8084 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8085 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8086 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
8087 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8088 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8089 }
8090 if (shader->key.part.ps.prolog.force_linear_center_interp &&
8091 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8092 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8093 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
8094 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8095 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8096 }
8097
8098 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
8099 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
8100 !(shader->config.spi_ps_input_ena & 0xf)) {
8101 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8102 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
8103 }
8104
8105 /* At least one pair of interpolation weights must be enabled. */
8106 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
8107 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8108 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
8109 }
8110
8111 /* The sample mask input is always enabled, because the API shader always
8112 * passes it through to the epilog. Disable it here if it's unused.
8113 */
8114 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
8115 !shader->selector->info.reads_samplemask)
8116 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
8117
8118 return true;
8119 }
8120
8121 static void si_fix_num_sgprs(struct si_shader *shader)
8122 {
8123 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
8124
8125 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
8126 }
8127
8128 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
8129 struct si_shader *shader,
8130 struct pipe_debug_callback *debug)
8131 {
8132 struct si_shader_selector *sel = shader->selector;
8133 struct si_shader *mainp = sel->main_shader_part;
8134 int r;
8135
8136 /* LS, ES, VS are compiled on demand if the main part hasn't been
8137 * compiled for that stage.
8138 *
8139 * Vertex shaders are compiled on demand when a vertex fetch
8140 * workaround must be applied.
8141 */
8142 if (shader->is_monolithic) {
8143 /* Monolithic shader (compiled as a whole, has many variants,
8144 * may take a long time to compile).
8145 */
8146 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
8147 if (r)
8148 return r;
8149 } else {
8150 /* The shader consists of 2-3 parts:
8151 *
8152 * - the middle part is the user shader, it has 1 variant only
8153 * and it was compiled during the creation of the shader
8154 * selector
8155 * - the prolog part is inserted at the beginning
8156 * - the epilog part is inserted at the end
8157 *
8158 * The prolog and epilog have many (but simple) variants.
8159 */
8160
8161 /* Copy the compiled TGSI shader data over. */
8162 shader->is_binary_shared = true;
8163 shader->binary = mainp->binary;
8164 shader->config = mainp->config;
8165 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8166 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8167 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8168 memcpy(shader->info.vs_output_param_offset,
8169 mainp->info.vs_output_param_offset,
8170 sizeof(mainp->info.vs_output_param_offset));
8171 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8172 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8173 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8174
8175 /* Select prologs and/or epilogs. */
8176 switch (sel->type) {
8177 case PIPE_SHADER_VERTEX:
8178 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
8179 return -1;
8180 break;
8181 case PIPE_SHADER_TESS_CTRL:
8182 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
8183 return -1;
8184 break;
8185 case PIPE_SHADER_TESS_EVAL:
8186 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
8187 return -1;
8188 break;
8189 case PIPE_SHADER_GEOMETRY:
8190 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
8191 return -1;
8192 break;
8193 case PIPE_SHADER_FRAGMENT:
8194 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8195 return -1;
8196
8197 /* Make sure we have at least as many VGPRs as there
8198 * are allocated inputs.
8199 */
8200 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8201 shader->info.num_input_vgprs);
8202 break;
8203 }
8204
8205 /* Update SGPR and VGPR counts. */
8206 if (shader->prolog) {
8207 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8208 shader->prolog->config.num_sgprs);
8209 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8210 shader->prolog->config.num_vgprs);
8211 }
8212 if (shader->epilog) {
8213 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8214 shader->epilog->config.num_sgprs);
8215 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8216 shader->epilog->config.num_vgprs);
8217 }
8218 }
8219
8220 si_fix_num_sgprs(shader);
8221 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8222 stderr);
8223
8224 /* Upload. */
8225 r = si_shader_binary_upload(sscreen, shader);
8226 if (r) {
8227 fprintf(stderr, "LLVM failed to upload shader\n");
8228 return r;
8229 }
8230
8231 return 0;
8232 }
8233
8234 void si_shader_destroy(struct si_shader *shader)
8235 {
8236 if (shader->scratch_bo)
8237 r600_resource_reference(&shader->scratch_bo, NULL);
8238
8239 r600_resource_reference(&shader->bo, NULL);
8240
8241 if (!shader->is_binary_shared)
8242 radeon_shader_binary_clean(&shader->binary);
8243
8244 free(shader->shader_log);
8245 }