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[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_dump.h"
45
46 #include "si_pipe.h"
47 #include "si_shader.h"
48 #include "sid.h"
49
50 #include <errno.h>
51
52 static const char *scratch_rsrc_dword0_symbol =
53 "SCRATCH_RSRC_DWORD0";
54
55 static const char *scratch_rsrc_dword1_symbol =
56 "SCRATCH_RSRC_DWORD1";
57
58 struct si_shader_output_values
59 {
60 LLVMValueRef values[4];
61 unsigned name;
62 unsigned sid;
63 };
64
65 struct si_shader_context
66 {
67 struct radeon_llvm_context radeon_bld;
68 struct si_shader *shader;
69 struct si_screen *screen;
70
71 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
72 bool is_gs_copy_shader;
73
74 /* Whether to generate the optimized shader variant compiled as a whole
75 * (without a prolog and epilog)
76 */
77 bool is_monolithic;
78
79 int param_streamout_config;
80 int param_streamout_write_index;
81 int param_streamout_offset[4];
82 int param_vertex_id;
83 int param_rel_auto_id;
84 int param_vs_prim_id;
85 int param_instance_id;
86 int param_vertex_index0;
87 int param_tes_u;
88 int param_tes_v;
89 int param_tes_rel_patch_id;
90 int param_tes_patch_id;
91 int param_es2gs_offset;
92
93 LLVMTargetMachineRef tm;
94
95 LLVMValueRef const_md;
96 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
97 LLVMValueRef lds;
98 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
99 LLVMValueRef sampler_views[SI_NUM_SAMPLERS];
100 LLVMValueRef sampler_states[SI_NUM_SAMPLERS];
101 LLVMValueRef fmasks[SI_NUM_USER_SAMPLERS];
102 LLVMValueRef so_buffers[4];
103 LLVMValueRef esgs_ring;
104 LLVMValueRef gsvs_ring[4];
105 LLVMValueRef gs_next_vertex[4];
106 LLVMValueRef return_value;
107
108 LLVMTypeRef voidt;
109 LLVMTypeRef i1;
110 LLVMTypeRef i8;
111 LLVMTypeRef i32;
112 LLVMTypeRef i64;
113 LLVMTypeRef i128;
114 LLVMTypeRef f32;
115 LLVMTypeRef v16i8;
116 LLVMTypeRef v2i32;
117 LLVMTypeRef v4i32;
118 LLVMTypeRef v4f32;
119 LLVMTypeRef v8i32;
120 };
121
122 static struct si_shader_context *si_shader_context(
123 struct lp_build_tgsi_context *bld_base)
124 {
125 return (struct si_shader_context *)bld_base;
126 }
127
128 static void si_init_shader_ctx(struct si_shader_context *ctx,
129 struct si_screen *sscreen,
130 struct si_shader *shader,
131 LLVMTargetMachineRef tm,
132 struct tgsi_shader_info *info);
133
134 /* Ideally pass the sample mask input to the PS epilog as v13, which
135 * is its usual location, so that the shader doesn't have to add v_mov.
136 */
137 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
138
139 /* The VS location of the PrimitiveID input is the same in the epilog,
140 * so that the main shader part doesn't have to move it.
141 */
142 #define VS_EPILOG_PRIMID_LOC 2
143
144 #define PERSPECTIVE_BASE 0
145 #define LINEAR_BASE 9
146
147 #define SAMPLE_OFFSET 0
148 #define CENTER_OFFSET 2
149 #define CENTROID_OFSET 4
150
151 #define USE_SGPR_MAX_SUFFIX_LEN 5
152 #define CONST_ADDR_SPACE 2
153 #define LOCAL_ADDR_SPACE 3
154 #define USER_SGPR_ADDR_SPACE 8
155
156
157 #define SENDMSG_GS 2
158 #define SENDMSG_GS_DONE 3
159
160 #define SENDMSG_GS_OP_NOP (0 << 4)
161 #define SENDMSG_GS_OP_CUT (1 << 4)
162 #define SENDMSG_GS_OP_EMIT (2 << 4)
163 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
164
165 /**
166 * Returns a unique index for a semantic name and index. The index must be
167 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
168 * calculated.
169 */
170 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
171 {
172 switch (semantic_name) {
173 case TGSI_SEMANTIC_POSITION:
174 return 0;
175 case TGSI_SEMANTIC_PSIZE:
176 return 1;
177 case TGSI_SEMANTIC_CLIPDIST:
178 assert(index <= 1);
179 return 2 + index;
180 case TGSI_SEMANTIC_GENERIC:
181 if (index <= 63-4)
182 return 4 + index;
183 else
184 /* same explanation as in the default statement,
185 * the only user hitting this is st/nine.
186 */
187 return 0;
188
189 /* patch indices are completely separate and thus start from 0 */
190 case TGSI_SEMANTIC_TESSOUTER:
191 return 0;
192 case TGSI_SEMANTIC_TESSINNER:
193 return 1;
194 case TGSI_SEMANTIC_PATCH:
195 return 2 + index;
196
197 default:
198 /* Don't fail here. The result of this function is only used
199 * for LS, TCS, TES, and GS, where legacy GL semantics can't
200 * occur, but this function is called for all vertex shaders
201 * before it's known whether LS will be compiled or not.
202 */
203 return 0;
204 }
205 }
206
207 /**
208 * Get the value of a shader input parameter and extract a bitfield.
209 */
210 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
211 unsigned param, unsigned rshift,
212 unsigned bitwidth)
213 {
214 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
215 LLVMValueRef value = LLVMGetParam(ctx->radeon_bld.main_fn,
216 param);
217
218 if (rshift)
219 value = LLVMBuildLShr(gallivm->builder, value,
220 lp_build_const_int32(gallivm, rshift), "");
221
222 if (rshift + bitwidth < 32) {
223 unsigned mask = (1 << bitwidth) - 1;
224 value = LLVMBuildAnd(gallivm->builder, value,
225 lp_build_const_int32(gallivm, mask), "");
226 }
227
228 return value;
229 }
230
231 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
232 {
233 switch (ctx->type) {
234 case TGSI_PROCESSOR_TESS_CTRL:
235 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
236
237 case TGSI_PROCESSOR_TESS_EVAL:
238 return LLVMGetParam(ctx->radeon_bld.main_fn,
239 ctx->param_tes_rel_patch_id);
240
241 default:
242 assert(0);
243 return NULL;
244 }
245 }
246
247 /* Tessellation shaders pass outputs to the next shader using LDS.
248 *
249 * LS outputs = TCS inputs
250 * TCS outputs = TES inputs
251 *
252 * The LDS layout is:
253 * - TCS inputs for patch 0
254 * - TCS inputs for patch 1
255 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
256 * - ...
257 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
258 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
259 * - TCS outputs for patch 1
260 * - Per-patch TCS outputs for patch 1
261 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
262 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
263 * - ...
264 *
265 * All three shaders VS(LS), TCS, TES share the same LDS space.
266 */
267
268 static LLVMValueRef
269 get_tcs_in_patch_stride(struct si_shader_context *ctx)
270 {
271 if (ctx->type == TGSI_PROCESSOR_VERTEX)
272 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
273 else if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
274 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
275 else {
276 assert(0);
277 return NULL;
278 }
279 }
280
281 static LLVMValueRef
282 get_tcs_out_patch_stride(struct si_shader_context *ctx)
283 {
284 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
285 }
286
287 static LLVMValueRef
288 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
289 {
290 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
291 unpack_param(ctx,
292 SI_PARAM_TCS_OUT_OFFSETS,
293 0, 16),
294 4);
295 }
296
297 static LLVMValueRef
298 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
299 {
300 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
301 unpack_param(ctx,
302 SI_PARAM_TCS_OUT_OFFSETS,
303 16, 16),
304 4);
305 }
306
307 static LLVMValueRef
308 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
309 {
310 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
311 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
312 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
313
314 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
315 }
316
317 static LLVMValueRef
318 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
319 {
320 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
321 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
322 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
323 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
324
325 return LLVMBuildAdd(gallivm->builder, patch0_offset,
326 LLVMBuildMul(gallivm->builder, patch_stride,
327 rel_patch_id, ""),
328 "");
329 }
330
331 static LLVMValueRef
332 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
333 {
334 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
335 LLVMValueRef patch0_patch_data_offset =
336 get_tcs_out_patch0_patch_data_offset(ctx);
337 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
338 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
339
340 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
341 LLVMBuildMul(gallivm->builder, patch_stride,
342 rel_patch_id, ""),
343 "");
344 }
345
346 static void build_indexed_store(struct si_shader_context *ctx,
347 LLVMValueRef base_ptr, LLVMValueRef index,
348 LLVMValueRef value)
349 {
350 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
351 struct gallivm_state *gallivm = bld_base->base.gallivm;
352 LLVMValueRef indices[2], pointer;
353
354 indices[0] = bld_base->uint_bld.zero;
355 indices[1] = index;
356
357 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
358 LLVMBuildStore(gallivm->builder, value, pointer);
359 }
360
361 /**
362 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
363 * It's equivalent to doing a load from &base_ptr[index].
364 *
365 * \param base_ptr Where the array starts.
366 * \param index The element index into the array.
367 */
368 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
369 LLVMValueRef base_ptr, LLVMValueRef index)
370 {
371 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
372 struct gallivm_state *gallivm = bld_base->base.gallivm;
373 LLVMValueRef indices[2], pointer;
374
375 indices[0] = bld_base->uint_bld.zero;
376 indices[1] = index;
377
378 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
379 return LLVMBuildLoad(gallivm->builder, pointer, "");
380 }
381
382 /**
383 * Do a load from &base_ptr[index], but also add a flag that it's loading
384 * a constant.
385 */
386 static LLVMValueRef build_indexed_load_const(
387 struct si_shader_context *ctx,
388 LLVMValueRef base_ptr, LLVMValueRef index)
389 {
390 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index);
391 LLVMSetMetadata(result, 1, ctx->const_md);
392 return result;
393 }
394
395 static LLVMValueRef get_instance_index_for_fetch(
396 struct radeon_llvm_context *radeon_bld,
397 unsigned param_start_instance, unsigned divisor)
398 {
399 struct si_shader_context *ctx =
400 si_shader_context(&radeon_bld->soa.bld_base);
401 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
402
403 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
404 ctx->param_instance_id);
405
406 /* The division must be done before START_INSTANCE is added. */
407 if (divisor > 1)
408 result = LLVMBuildUDiv(gallivm->builder, result,
409 lp_build_const_int32(gallivm, divisor), "");
410
411 return LLVMBuildAdd(gallivm->builder, result,
412 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
413 }
414
415 static void declare_input_vs(
416 struct radeon_llvm_context *radeon_bld,
417 unsigned input_index,
418 const struct tgsi_full_declaration *decl)
419 {
420 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
421 struct gallivm_state *gallivm = base->gallivm;
422 struct si_shader_context *ctx =
423 si_shader_context(&radeon_bld->soa.bld_base);
424 unsigned divisor =
425 ctx->shader->key.vs.prolog.instance_divisors[input_index];
426
427 unsigned chan;
428
429 LLVMValueRef t_list_ptr;
430 LLVMValueRef t_offset;
431 LLVMValueRef t_list;
432 LLVMValueRef attribute_offset;
433 LLVMValueRef buffer_index;
434 LLVMValueRef args[3];
435 LLVMValueRef input;
436
437 /* Load the T list */
438 t_list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
439
440 t_offset = lp_build_const_int32(gallivm, input_index);
441
442 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
443
444 /* Build the attribute offset */
445 attribute_offset = lp_build_const_int32(gallivm, 0);
446
447 if (!ctx->is_monolithic) {
448 buffer_index = LLVMGetParam(radeon_bld->main_fn,
449 ctx->param_vertex_index0 +
450 input_index);
451 } else if (divisor) {
452 /* Build index from instance ID, start instance and divisor */
453 ctx->shader->uses_instanceid = true;
454 buffer_index = get_instance_index_for_fetch(&ctx->radeon_bld,
455 SI_PARAM_START_INSTANCE,
456 divisor);
457 } else {
458 /* Load the buffer index for vertices. */
459 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
460 ctx->param_vertex_id);
461 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
462 SI_PARAM_BASE_VERTEX);
463 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
464 }
465
466 args[0] = t_list;
467 args[1] = attribute_offset;
468 args[2] = buffer_index;
469 input = lp_build_intrinsic(gallivm->builder,
470 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
471 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
472
473 /* Break up the vec4 into individual components */
474 for (chan = 0; chan < 4; chan++) {
475 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
476 /* XXX: Use a helper function for this. There is one in
477 * tgsi_llvm.c. */
478 ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
479 LLVMBuildExtractElement(gallivm->builder,
480 input, llvm_chan, "");
481 }
482 }
483
484 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
485 unsigned swizzle)
486 {
487 struct si_shader_context *ctx = si_shader_context(bld_base);
488
489 if (swizzle > 0)
490 return bld_base->uint_bld.zero;
491
492 switch (ctx->type) {
493 case TGSI_PROCESSOR_VERTEX:
494 return LLVMGetParam(ctx->radeon_bld.main_fn,
495 ctx->param_vs_prim_id);
496 case TGSI_PROCESSOR_TESS_CTRL:
497 return LLVMGetParam(ctx->radeon_bld.main_fn,
498 SI_PARAM_PATCH_ID);
499 case TGSI_PROCESSOR_TESS_EVAL:
500 return LLVMGetParam(ctx->radeon_bld.main_fn,
501 ctx->param_tes_patch_id);
502 case TGSI_PROCESSOR_GEOMETRY:
503 return LLVMGetParam(ctx->radeon_bld.main_fn,
504 SI_PARAM_PRIMITIVE_ID);
505 default:
506 assert(0);
507 return bld_base->uint_bld.zero;
508 }
509 }
510
511 /**
512 * Return the value of tgsi_ind_register for indexing.
513 * This is the indirect index with the constant offset added to it.
514 */
515 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
516 const struct tgsi_ind_register *ind,
517 int rel_index)
518 {
519 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
520 LLVMValueRef result;
521
522 result = ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
523 result = LLVMBuildLoad(gallivm->builder, result, "");
524 result = LLVMBuildAdd(gallivm->builder, result,
525 lp_build_const_int32(gallivm, rel_index), "");
526 return result;
527 }
528
529 /**
530 * Calculate a dword address given an input or output register and a stride.
531 */
532 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
533 const struct tgsi_full_dst_register *dst,
534 const struct tgsi_full_src_register *src,
535 LLVMValueRef vertex_dw_stride,
536 LLVMValueRef base_addr)
537 {
538 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
539 struct tgsi_shader_info *info = &ctx->shader->selector->info;
540 ubyte *name, *index, *array_first;
541 int first, param;
542 struct tgsi_full_dst_register reg;
543
544 /* Set the register description. The address computation is the same
545 * for sources and destinations. */
546 if (src) {
547 reg.Register.File = src->Register.File;
548 reg.Register.Index = src->Register.Index;
549 reg.Register.Indirect = src->Register.Indirect;
550 reg.Register.Dimension = src->Register.Dimension;
551 reg.Indirect = src->Indirect;
552 reg.Dimension = src->Dimension;
553 reg.DimIndirect = src->DimIndirect;
554 } else
555 reg = *dst;
556
557 /* If the register is 2-dimensional (e.g. an array of vertices
558 * in a primitive), calculate the base address of the vertex. */
559 if (reg.Register.Dimension) {
560 LLVMValueRef index;
561
562 if (reg.Dimension.Indirect)
563 index = get_indirect_index(ctx, &reg.DimIndirect,
564 reg.Dimension.Index);
565 else
566 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
567
568 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
569 LLVMBuildMul(gallivm->builder, index,
570 vertex_dw_stride, ""), "");
571 }
572
573 /* Get information about the register. */
574 if (reg.Register.File == TGSI_FILE_INPUT) {
575 name = info->input_semantic_name;
576 index = info->input_semantic_index;
577 array_first = info->input_array_first;
578 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
579 name = info->output_semantic_name;
580 index = info->output_semantic_index;
581 array_first = info->output_array_first;
582 } else {
583 assert(0);
584 return NULL;
585 }
586
587 if (reg.Register.Indirect) {
588 /* Add the relative address of the element. */
589 LLVMValueRef ind_index;
590
591 if (reg.Indirect.ArrayID)
592 first = array_first[reg.Indirect.ArrayID];
593 else
594 first = reg.Register.Index;
595
596 ind_index = get_indirect_index(ctx, &reg.Indirect,
597 reg.Register.Index - first);
598
599 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
600 LLVMBuildMul(gallivm->builder, ind_index,
601 lp_build_const_int32(gallivm, 4), ""), "");
602
603 param = si_shader_io_get_unique_index(name[first], index[first]);
604 } else {
605 param = si_shader_io_get_unique_index(name[reg.Register.Index],
606 index[reg.Register.Index]);
607 }
608
609 /* Add the base address of the element. */
610 return LLVMBuildAdd(gallivm->builder, base_addr,
611 lp_build_const_int32(gallivm, param * 4), "");
612 }
613
614 /**
615 * Load from LDS.
616 *
617 * \param type output value type
618 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
619 * \param dw_addr address in dwords
620 */
621 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
622 enum tgsi_opcode_type type, unsigned swizzle,
623 LLVMValueRef dw_addr)
624 {
625 struct si_shader_context *ctx = si_shader_context(bld_base);
626 struct gallivm_state *gallivm = bld_base->base.gallivm;
627 LLVMValueRef value;
628
629 if (swizzle == ~0) {
630 LLVMValueRef values[TGSI_NUM_CHANNELS];
631
632 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
633 values[chan] = lds_load(bld_base, type, chan, dw_addr);
634
635 return lp_build_gather_values(bld_base->base.gallivm, values,
636 TGSI_NUM_CHANNELS);
637 }
638
639 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
640 lp_build_const_int32(gallivm, swizzle));
641
642 value = build_indexed_load(ctx, ctx->lds, dw_addr);
643 if (type == TGSI_TYPE_DOUBLE) {
644 LLVMValueRef value2;
645 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
646 lp_build_const_int32(gallivm, swizzle + 1));
647 value2 = build_indexed_load(ctx, ctx->lds, dw_addr);
648 return radeon_llvm_emit_fetch_double(bld_base, value, value2);
649 }
650
651 return LLVMBuildBitCast(gallivm->builder, value,
652 tgsi2llvmtype(bld_base, type), "");
653 }
654
655 /**
656 * Store to LDS.
657 *
658 * \param swizzle offset (typically 0..3)
659 * \param dw_addr address in dwords
660 * \param value value to store
661 */
662 static void lds_store(struct lp_build_tgsi_context *bld_base,
663 unsigned swizzle, LLVMValueRef dw_addr,
664 LLVMValueRef value)
665 {
666 struct si_shader_context *ctx = si_shader_context(bld_base);
667 struct gallivm_state *gallivm = bld_base->base.gallivm;
668
669 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
670 lp_build_const_int32(gallivm, swizzle));
671
672 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
673 build_indexed_store(ctx, ctx->lds,
674 dw_addr, value);
675 }
676
677 static LLVMValueRef fetch_input_tcs(
678 struct lp_build_tgsi_context *bld_base,
679 const struct tgsi_full_src_register *reg,
680 enum tgsi_opcode_type type, unsigned swizzle)
681 {
682 struct si_shader_context *ctx = si_shader_context(bld_base);
683 LLVMValueRef dw_addr, stride;
684
685 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
686 dw_addr = get_tcs_in_current_patch_offset(ctx);
687 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
688
689 return lds_load(bld_base, type, swizzle, dw_addr);
690 }
691
692 static LLVMValueRef fetch_output_tcs(
693 struct lp_build_tgsi_context *bld_base,
694 const struct tgsi_full_src_register *reg,
695 enum tgsi_opcode_type type, unsigned swizzle)
696 {
697 struct si_shader_context *ctx = si_shader_context(bld_base);
698 LLVMValueRef dw_addr, stride;
699
700 if (reg->Register.Dimension) {
701 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
702 dw_addr = get_tcs_out_current_patch_offset(ctx);
703 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
704 } else {
705 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
706 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
707 }
708
709 return lds_load(bld_base, type, swizzle, dw_addr);
710 }
711
712 static LLVMValueRef fetch_input_tes(
713 struct lp_build_tgsi_context *bld_base,
714 const struct tgsi_full_src_register *reg,
715 enum tgsi_opcode_type type, unsigned swizzle)
716 {
717 struct si_shader_context *ctx = si_shader_context(bld_base);
718 LLVMValueRef dw_addr, stride;
719
720 if (reg->Register.Dimension) {
721 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
722 dw_addr = get_tcs_out_current_patch_offset(ctx);
723 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
724 } else {
725 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
726 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
727 }
728
729 return lds_load(bld_base, type, swizzle, dw_addr);
730 }
731
732 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
733 const struct tgsi_full_instruction *inst,
734 const struct tgsi_opcode_info *info,
735 LLVMValueRef dst[4])
736 {
737 struct si_shader_context *ctx = si_shader_context(bld_base);
738 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
739 unsigned chan_index;
740 LLVMValueRef dw_addr, stride;
741
742 /* Only handle per-patch and per-vertex outputs here.
743 * Vectors will be lowered to scalars and this function will be called again.
744 */
745 if (reg->Register.File != TGSI_FILE_OUTPUT ||
746 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
747 radeon_llvm_emit_store(bld_base, inst, info, dst);
748 return;
749 }
750
751 if (reg->Register.Dimension) {
752 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
753 dw_addr = get_tcs_out_current_patch_offset(ctx);
754 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
755 } else {
756 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
757 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
758 }
759
760 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
761 LLVMValueRef value = dst[chan_index];
762
763 if (inst->Instruction.Saturate)
764 value = radeon_llvm_saturate(bld_base, value);
765
766 lds_store(bld_base, chan_index, dw_addr, value);
767 }
768 }
769
770 static LLVMValueRef fetch_input_gs(
771 struct lp_build_tgsi_context *bld_base,
772 const struct tgsi_full_src_register *reg,
773 enum tgsi_opcode_type type,
774 unsigned swizzle)
775 {
776 struct lp_build_context *base = &bld_base->base;
777 struct si_shader_context *ctx = si_shader_context(bld_base);
778 struct si_shader *shader = ctx->shader;
779 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
780 struct gallivm_state *gallivm = base->gallivm;
781 LLVMValueRef vtx_offset;
782 LLVMValueRef args[9];
783 unsigned vtx_offset_param;
784 struct tgsi_shader_info *info = &shader->selector->info;
785 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
786 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
787 unsigned param;
788 LLVMValueRef value;
789
790 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
791 return get_primitive_id(bld_base, swizzle);
792
793 if (!reg->Register.Dimension)
794 return NULL;
795
796 if (swizzle == ~0) {
797 LLVMValueRef values[TGSI_NUM_CHANNELS];
798 unsigned chan;
799 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
800 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
801 }
802 return lp_build_gather_values(bld_base->base.gallivm, values,
803 TGSI_NUM_CHANNELS);
804 }
805
806 /* Get the vertex offset parameter */
807 vtx_offset_param = reg->Dimension.Index;
808 if (vtx_offset_param < 2) {
809 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
810 } else {
811 assert(vtx_offset_param < 6);
812 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
813 }
814 vtx_offset = lp_build_mul_imm(uint,
815 LLVMGetParam(ctx->radeon_bld.main_fn,
816 vtx_offset_param),
817 4);
818
819 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
820 args[0] = ctx->esgs_ring;
821 args[1] = vtx_offset;
822 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
823 args[3] = uint->zero;
824 args[4] = uint->one; /* OFFEN */
825 args[5] = uint->zero; /* IDXEN */
826 args[6] = uint->one; /* GLC */
827 args[7] = uint->zero; /* SLC */
828 args[8] = uint->zero; /* TFE */
829
830 value = lp_build_intrinsic(gallivm->builder,
831 "llvm.SI.buffer.load.dword.i32.i32",
832 ctx->i32, args, 9,
833 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
834 if (type == TGSI_TYPE_DOUBLE) {
835 LLVMValueRef value2;
836 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
837 value2 = lp_build_intrinsic(gallivm->builder,
838 "llvm.SI.buffer.load.dword.i32.i32",
839 ctx->i32, args, 9,
840 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
841 return radeon_llvm_emit_fetch_double(bld_base,
842 value, value2);
843 }
844 return LLVMBuildBitCast(gallivm->builder,
845 value,
846 tgsi2llvmtype(bld_base, type), "");
847 }
848
849 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
850 {
851 switch (interpolate) {
852 case TGSI_INTERPOLATE_CONSTANT:
853 return 0;
854
855 case TGSI_INTERPOLATE_LINEAR:
856 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
857 return SI_PARAM_LINEAR_SAMPLE;
858 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
859 return SI_PARAM_LINEAR_CENTROID;
860 else
861 return SI_PARAM_LINEAR_CENTER;
862 break;
863 case TGSI_INTERPOLATE_COLOR:
864 case TGSI_INTERPOLATE_PERSPECTIVE:
865 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
866 return SI_PARAM_PERSP_SAMPLE;
867 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
868 return SI_PARAM_PERSP_CENTROID;
869 else
870 return SI_PARAM_PERSP_CENTER;
871 break;
872 default:
873 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
874 return -1;
875 }
876 }
877
878 /* This shouldn't be used by explicit INTERP opcodes. */
879 static unsigned select_interp_param(struct si_shader_context *ctx,
880 unsigned param)
881 {
882 if (!ctx->shader->key.ps.prolog.force_persample_interp)
883 return param;
884
885 /* If the shader doesn't use center/centroid, just return the parameter.
886 *
887 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
888 * switch between center/centroid and sample without shader changes.
889 */
890 switch (param) {
891 case SI_PARAM_PERSP_CENTROID:
892 case SI_PARAM_PERSP_CENTER:
893 return SI_PARAM_PERSP_SAMPLE;
894
895 case SI_PARAM_LINEAR_CENTROID:
896 case SI_PARAM_LINEAR_CENTER:
897 return SI_PARAM_LINEAR_SAMPLE;
898
899 default:
900 return param;
901 }
902 }
903
904 /**
905 * Interpolate a fragment shader input.
906 *
907 * @param ctx context
908 * @param input_index index of the input in hardware
909 * @param semantic_name TGSI_SEMANTIC_*
910 * @param semantic_index semantic index
911 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
912 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
913 * @param interp_param interpolation weights (i,j)
914 * @param prim_mask SI_PARAM_PRIM_MASK
915 * @param face SI_PARAM_FRONT_FACE
916 * @param result the return value (4 components)
917 */
918 static void interp_fs_input(struct si_shader_context *ctx,
919 unsigned input_index,
920 unsigned semantic_name,
921 unsigned semantic_index,
922 unsigned num_interp_inputs,
923 unsigned colors_read_mask,
924 LLVMValueRef interp_param,
925 LLVMValueRef prim_mask,
926 LLVMValueRef face,
927 LLVMValueRef result[4])
928 {
929 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
930 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
931 struct gallivm_state *gallivm = base->gallivm;
932 const char *intr_name;
933 LLVMValueRef attr_number;
934
935 unsigned chan;
936
937 attr_number = lp_build_const_int32(gallivm, input_index);
938
939 /* fs.constant returns the param from the middle vertex, so it's not
940 * really useful for flat shading. It's meant to be used for custom
941 * interpolation (but the intrinsic can't fetch from the other two
942 * vertices).
943 *
944 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
945 * to do the right thing. The only reason we use fs.constant is that
946 * fs.interp cannot be used on integers, because they can be equal
947 * to NaN.
948 */
949 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
950
951 if (semantic_name == TGSI_SEMANTIC_COLOR &&
952 ctx->shader->key.ps.prolog.color_two_side) {
953 LLVMValueRef args[4];
954 LLVMValueRef is_face_positive;
955 LLVMValueRef back_attr_number;
956
957 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
958 * otherwise it's at offset "num_inputs".
959 */
960 unsigned back_attr_offset = num_interp_inputs;
961 if (semantic_index == 1 && colors_read_mask & 0xf)
962 back_attr_offset += 1;
963
964 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
965
966 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
967 face, uint->zero, "");
968
969 args[2] = prim_mask;
970 args[3] = interp_param;
971 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
972 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
973 LLVMValueRef front, back;
974
975 args[0] = llvm_chan;
976 args[1] = attr_number;
977 front = lp_build_intrinsic(gallivm->builder, intr_name,
978 ctx->f32, args, args[3] ? 4 : 3,
979 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
980
981 args[1] = back_attr_number;
982 back = lp_build_intrinsic(gallivm->builder, intr_name,
983 ctx->f32, args, args[3] ? 4 : 3,
984 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
985
986 result[chan] = LLVMBuildSelect(gallivm->builder,
987 is_face_positive,
988 front,
989 back,
990 "");
991 }
992 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
993 LLVMValueRef args[4];
994
995 args[0] = uint->zero;
996 args[1] = attr_number;
997 args[2] = prim_mask;
998 args[3] = interp_param;
999 result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
1000 ctx->f32, args, args[3] ? 4 : 3,
1001 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1002 result[1] =
1003 result[2] = lp_build_const_float(gallivm, 0.0f);
1004 result[3] = lp_build_const_float(gallivm, 1.0f);
1005 } else {
1006 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1007 LLVMValueRef args[4];
1008 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1009
1010 args[0] = llvm_chan;
1011 args[1] = attr_number;
1012 args[2] = prim_mask;
1013 args[3] = interp_param;
1014 result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
1015 ctx->f32, args, args[3] ? 4 : 3,
1016 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1017 }
1018 }
1019 }
1020
1021 static void declare_input_fs(
1022 struct radeon_llvm_context *radeon_bld,
1023 unsigned input_index,
1024 const struct tgsi_full_declaration *decl)
1025 {
1026 struct si_shader_context *ctx =
1027 si_shader_context(&radeon_bld->soa.bld_base);
1028 struct si_shader *shader = ctx->shader;
1029 LLVMValueRef main_fn = radeon_bld->main_fn;
1030 LLVMValueRef interp_param = NULL;
1031 int interp_param_idx;
1032
1033 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1034 decl->Interp.Location);
1035 if (interp_param_idx == -1)
1036 return;
1037 else if (interp_param_idx) {
1038 interp_param_idx = select_interp_param(ctx,
1039 interp_param_idx);
1040 interp_param = LLVMGetParam(main_fn, interp_param_idx);
1041 }
1042
1043 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1044 decl->Semantic.Index, shader->selector->info.num_inputs,
1045 shader->selector->info.colors_read, interp_param,
1046 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1047 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1048 &radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)]);
1049 }
1050
1051 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1052 {
1053 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1054 SI_PARAM_ANCILLARY, 8, 4);
1055 }
1056
1057 /**
1058 * Load a dword from a constant buffer.
1059 */
1060 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1061 LLVMValueRef offset, LLVMTypeRef return_type)
1062 {
1063 LLVMValueRef args[2] = {resource, offset};
1064
1065 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1066 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1067 }
1068
1069 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1070 {
1071 struct si_shader_context *ctx =
1072 si_shader_context(&radeon_bld->soa.bld_base);
1073 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1074 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1075 LLVMBuilderRef builder = gallivm->builder;
1076 LLVMValueRef desc = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1077 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
1078 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1079
1080 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1081 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1082 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1083
1084 LLVMValueRef pos[4] = {
1085 buffer_load_const(builder, resource, offset0, ctx->f32),
1086 buffer_load_const(builder, resource, offset1, ctx->f32),
1087 lp_build_const_float(gallivm, 0),
1088 lp_build_const_float(gallivm, 0)
1089 };
1090
1091 return lp_build_gather_values(gallivm, pos, 4);
1092 }
1093
1094 static void declare_system_value(
1095 struct radeon_llvm_context *radeon_bld,
1096 unsigned index,
1097 const struct tgsi_full_declaration *decl)
1098 {
1099 struct si_shader_context *ctx =
1100 si_shader_context(&radeon_bld->soa.bld_base);
1101 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1102 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1103 LLVMValueRef value = 0;
1104
1105 switch (decl->Semantic.Name) {
1106 case TGSI_SEMANTIC_INSTANCEID:
1107 value = LLVMGetParam(radeon_bld->main_fn,
1108 ctx->param_instance_id);
1109 break;
1110
1111 case TGSI_SEMANTIC_VERTEXID:
1112 value = LLVMBuildAdd(gallivm->builder,
1113 LLVMGetParam(radeon_bld->main_fn,
1114 ctx->param_vertex_id),
1115 LLVMGetParam(radeon_bld->main_fn,
1116 SI_PARAM_BASE_VERTEX), "");
1117 break;
1118
1119 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1120 value = LLVMGetParam(radeon_bld->main_fn,
1121 ctx->param_vertex_id);
1122 break;
1123
1124 case TGSI_SEMANTIC_BASEVERTEX:
1125 value = LLVMGetParam(radeon_bld->main_fn,
1126 SI_PARAM_BASE_VERTEX);
1127 break;
1128
1129 case TGSI_SEMANTIC_INVOCATIONID:
1130 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
1131 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1132 else if (ctx->type == TGSI_PROCESSOR_GEOMETRY)
1133 value = LLVMGetParam(radeon_bld->main_fn,
1134 SI_PARAM_GS_INSTANCE_ID);
1135 else
1136 assert(!"INVOCATIONID not implemented");
1137 break;
1138
1139 case TGSI_SEMANTIC_POSITION:
1140 {
1141 LLVMValueRef pos[4] = {
1142 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1143 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1144 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1145 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1146 LLVMGetParam(radeon_bld->main_fn,
1147 SI_PARAM_POS_W_FLOAT)),
1148 };
1149 value = lp_build_gather_values(gallivm, pos, 4);
1150 break;
1151 }
1152
1153 case TGSI_SEMANTIC_FACE:
1154 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1155 break;
1156
1157 case TGSI_SEMANTIC_SAMPLEID:
1158 value = get_sample_id(radeon_bld);
1159 break;
1160
1161 case TGSI_SEMANTIC_SAMPLEPOS: {
1162 LLVMValueRef pos[4] = {
1163 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1164 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1165 lp_build_const_float(gallivm, 0),
1166 lp_build_const_float(gallivm, 0)
1167 };
1168 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1169 TGSI_OPCODE_FRC, pos[0]);
1170 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1171 TGSI_OPCODE_FRC, pos[1]);
1172 value = lp_build_gather_values(gallivm, pos, 4);
1173 break;
1174 }
1175
1176 case TGSI_SEMANTIC_SAMPLEMASK:
1177 /* This can only occur with the OpenGL Core profile, which
1178 * doesn't support smoothing.
1179 */
1180 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1181 break;
1182
1183 case TGSI_SEMANTIC_TESSCOORD:
1184 {
1185 LLVMValueRef coord[4] = {
1186 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1187 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1188 bld->zero,
1189 bld->zero
1190 };
1191
1192 /* For triangles, the vector should be (u, v, 1-u-v). */
1193 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1194 PIPE_PRIM_TRIANGLES)
1195 coord[2] = lp_build_sub(bld, bld->one,
1196 lp_build_add(bld, coord[0], coord[1]));
1197
1198 value = lp_build_gather_values(gallivm, coord, 4);
1199 break;
1200 }
1201
1202 case TGSI_SEMANTIC_VERTICESIN:
1203 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1204 break;
1205
1206 case TGSI_SEMANTIC_TESSINNER:
1207 case TGSI_SEMANTIC_TESSOUTER:
1208 {
1209 LLVMValueRef dw_addr;
1210 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1211
1212 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1213 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1214 lp_build_const_int32(gallivm, param * 4), "");
1215
1216 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1217 ~0, dw_addr);
1218 break;
1219 }
1220
1221 case TGSI_SEMANTIC_PRIMID:
1222 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1223 break;
1224
1225 default:
1226 assert(!"unknown system value");
1227 return;
1228 }
1229
1230 radeon_bld->system_values[index] = value;
1231 }
1232
1233 static LLVMValueRef fetch_constant(
1234 struct lp_build_tgsi_context *bld_base,
1235 const struct tgsi_full_src_register *reg,
1236 enum tgsi_opcode_type type,
1237 unsigned swizzle)
1238 {
1239 struct si_shader_context *ctx = si_shader_context(bld_base);
1240 struct lp_build_context *base = &bld_base->base;
1241 const struct tgsi_ind_register *ireg = &reg->Indirect;
1242 unsigned buf, idx;
1243
1244 LLVMValueRef addr, bufp;
1245 LLVMValueRef result;
1246
1247 if (swizzle == LP_CHAN_ALL) {
1248 unsigned chan;
1249 LLVMValueRef values[4];
1250 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1251 values[chan] = fetch_constant(bld_base, reg, type, chan);
1252
1253 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1254 }
1255
1256 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1257 idx = reg->Register.Index * 4 + swizzle;
1258
1259 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1260 if (type != TGSI_TYPE_DOUBLE)
1261 return bitcast(bld_base, type, ctx->constants[buf][idx]);
1262 else {
1263 return radeon_llvm_emit_fetch_double(bld_base,
1264 ctx->constants[buf][idx],
1265 ctx->constants[buf][idx + 1]);
1266 }
1267 }
1268
1269 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1270 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1271 LLVMValueRef index;
1272 index = get_indirect_index(ctx, &reg->DimIndirect,
1273 reg->Dimension.Index);
1274 bufp = build_indexed_load_const(ctx, ptr, index);
1275 } else
1276 bufp = ctx->const_buffers[buf];
1277
1278 addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1279 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1280 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1281 addr = lp_build_add(&bld_base->uint_bld, addr,
1282 lp_build_const_int32(base->gallivm, idx * 4));
1283
1284 result = buffer_load_const(base->gallivm->builder, bufp,
1285 addr, ctx->f32);
1286
1287 if (type != TGSI_TYPE_DOUBLE)
1288 result = bitcast(bld_base, type, result);
1289 else {
1290 LLVMValueRef addr2, result2;
1291 addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1292 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1293 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1294 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1295 lp_build_const_int32(base->gallivm, idx * 4));
1296
1297 result2 = buffer_load_const(base->gallivm->builder, ctx->const_buffers[buf],
1298 addr2, ctx->f32);
1299
1300 result = radeon_llvm_emit_fetch_double(bld_base,
1301 result, result2);
1302 }
1303 return result;
1304 }
1305
1306 /* Upper 16 bits must be zero. */
1307 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1308 LLVMValueRef val[2])
1309 {
1310 return LLVMBuildOr(gallivm->builder, val[0],
1311 LLVMBuildShl(gallivm->builder, val[1],
1312 lp_build_const_int32(gallivm, 16),
1313 ""), "");
1314 }
1315
1316 /* Upper 16 bits are ignored and will be dropped. */
1317 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1318 LLVMValueRef val[2])
1319 {
1320 LLVMValueRef v[2] = {
1321 LLVMBuildAnd(gallivm->builder, val[0],
1322 lp_build_const_int32(gallivm, 0xffff), ""),
1323 val[1],
1324 };
1325 return si_llvm_pack_two_int16(gallivm, v);
1326 }
1327
1328 /* Initialize arguments for the shader export intrinsic */
1329 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1330 LLVMValueRef *values,
1331 unsigned target,
1332 LLVMValueRef *args)
1333 {
1334 struct si_shader_context *ctx = si_shader_context(bld_base);
1335 struct lp_build_context *uint =
1336 &ctx->radeon_bld.soa.bld_base.uint_bld;
1337 struct lp_build_context *base = &bld_base->base;
1338 struct gallivm_state *gallivm = base->gallivm;
1339 LLVMBuilderRef builder = base->gallivm->builder;
1340 LLVMValueRef val[4];
1341 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1342 unsigned chan;
1343 bool is_int8;
1344
1345 /* Default is 0xf. Adjusted below depending on the format. */
1346 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1347
1348 /* Specify whether the EXEC mask represents the valid mask */
1349 args[1] = uint->zero;
1350
1351 /* Specify whether this is the last export */
1352 args[2] = uint->zero;
1353
1354 /* Specify the target we are exporting */
1355 args[3] = lp_build_const_int32(base->gallivm, target);
1356
1357 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
1358 const union si_shader_key *key = &ctx->shader->key;
1359 unsigned col_formats = key->ps.epilog.spi_shader_col_format;
1360 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1361
1362 assert(cbuf >= 0 && cbuf < 8);
1363 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1364 is_int8 = (key->ps.epilog.color_is_int8 >> cbuf) & 0x1;
1365 }
1366
1367 args[4] = uint->zero; /* COMPR flag */
1368 args[5] = base->undef;
1369 args[6] = base->undef;
1370 args[7] = base->undef;
1371 args[8] = base->undef;
1372
1373 switch (spi_shader_col_format) {
1374 case V_028714_SPI_SHADER_ZERO:
1375 args[0] = uint->zero; /* writemask */
1376 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
1377 break;
1378
1379 case V_028714_SPI_SHADER_32_R:
1380 args[0] = uint->one; /* writemask */
1381 args[5] = values[0];
1382 break;
1383
1384 case V_028714_SPI_SHADER_32_GR:
1385 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
1386 args[5] = values[0];
1387 args[6] = values[1];
1388 break;
1389
1390 case V_028714_SPI_SHADER_32_AR:
1391 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
1392 args[5] = values[0];
1393 args[8] = values[3];
1394 break;
1395
1396 case V_028714_SPI_SHADER_FP16_ABGR:
1397 args[4] = uint->one; /* COMPR flag */
1398
1399 for (chan = 0; chan < 2; chan++) {
1400 LLVMValueRef pack_args[2] = {
1401 values[2 * chan],
1402 values[2 * chan + 1]
1403 };
1404 LLVMValueRef packed;
1405
1406 packed = lp_build_intrinsic(base->gallivm->builder,
1407 "llvm.SI.packf16",
1408 ctx->i32, pack_args, 2,
1409 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1410 args[chan + 5] =
1411 LLVMBuildBitCast(base->gallivm->builder,
1412 packed, ctx->f32, "");
1413 }
1414 break;
1415
1416 case V_028714_SPI_SHADER_UNORM16_ABGR:
1417 for (chan = 0; chan < 4; chan++) {
1418 val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
1419 val[chan] = LLVMBuildFMul(builder, val[chan],
1420 lp_build_const_float(gallivm, 65535), "");
1421 val[chan] = LLVMBuildFAdd(builder, val[chan],
1422 lp_build_const_float(gallivm, 0.5), "");
1423 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1424 ctx->i32, "");
1425 }
1426
1427 args[4] = uint->one; /* COMPR flag */
1428 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1429 si_llvm_pack_two_int16(gallivm, val));
1430 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1431 si_llvm_pack_two_int16(gallivm, val+2));
1432 break;
1433
1434 case V_028714_SPI_SHADER_SNORM16_ABGR:
1435 for (chan = 0; chan < 4; chan++) {
1436 /* Clamp between [-1, 1]. */
1437 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1438 values[chan],
1439 lp_build_const_float(gallivm, 1));
1440 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1441 val[chan],
1442 lp_build_const_float(gallivm, -1));
1443 /* Convert to a signed integer in [-32767, 32767]. */
1444 val[chan] = LLVMBuildFMul(builder, val[chan],
1445 lp_build_const_float(gallivm, 32767), "");
1446 /* If positive, add 0.5, else add -0.5. */
1447 val[chan] = LLVMBuildFAdd(builder, val[chan],
1448 LLVMBuildSelect(builder,
1449 LLVMBuildFCmp(builder, LLVMRealOGE,
1450 val[chan], base->zero, ""),
1451 lp_build_const_float(gallivm, 0.5),
1452 lp_build_const_float(gallivm, -0.5), ""), "");
1453 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
1454 }
1455
1456 args[4] = uint->one; /* COMPR flag */
1457 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1458 si_llvm_pack_two_int32_as_int16(gallivm, val));
1459 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1460 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1461 break;
1462
1463 case V_028714_SPI_SHADER_UINT16_ABGR: {
1464 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1465 255 : 65535);
1466 /* Clamp. */
1467 for (chan = 0; chan < 4; chan++) {
1468 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1469 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1470 val[chan], max);
1471 }
1472
1473 args[4] = uint->one; /* COMPR flag */
1474 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1475 si_llvm_pack_two_int16(gallivm, val));
1476 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1477 si_llvm_pack_two_int16(gallivm, val+2));
1478 break;
1479 }
1480
1481 case V_028714_SPI_SHADER_SINT16_ABGR: {
1482 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1483 127 : 32767);
1484 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
1485 -128 : -32768);
1486 /* Clamp. */
1487 for (chan = 0; chan < 4; chan++) {
1488 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1489 val[chan] = lp_build_emit_llvm_binary(bld_base,
1490 TGSI_OPCODE_IMIN,
1491 val[chan], max);
1492 val[chan] = lp_build_emit_llvm_binary(bld_base,
1493 TGSI_OPCODE_IMAX,
1494 val[chan], min);
1495 }
1496
1497 args[4] = uint->one; /* COMPR flag */
1498 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1499 si_llvm_pack_two_int32_as_int16(gallivm, val));
1500 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1501 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1502 break;
1503 }
1504
1505 case V_028714_SPI_SHADER_32_ABGR:
1506 memcpy(&args[5], values, sizeof(values[0]) * 4);
1507 break;
1508 }
1509 }
1510
1511 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1512 LLVMValueRef alpha)
1513 {
1514 struct si_shader_context *ctx = si_shader_context(bld_base);
1515 struct gallivm_state *gallivm = bld_base->base.gallivm;
1516
1517 if (ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
1518 LLVMValueRef alpha_ref = LLVMGetParam(ctx->radeon_bld.main_fn,
1519 SI_PARAM_ALPHA_REF);
1520
1521 LLVMValueRef alpha_pass =
1522 lp_build_cmp(&bld_base->base,
1523 ctx->shader->key.ps.epilog.alpha_func,
1524 alpha, alpha_ref);
1525 LLVMValueRef arg =
1526 lp_build_select(&bld_base->base,
1527 alpha_pass,
1528 lp_build_const_float(gallivm, 1.0f),
1529 lp_build_const_float(gallivm, -1.0f));
1530
1531 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
1532 ctx->voidt, &arg, 1, 0);
1533 } else {
1534 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
1535 ctx->voidt, NULL, 0, 0);
1536 }
1537 }
1538
1539 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1540 LLVMValueRef alpha,
1541 unsigned samplemask_param)
1542 {
1543 struct si_shader_context *ctx = si_shader_context(bld_base);
1544 struct gallivm_state *gallivm = bld_base->base.gallivm;
1545 LLVMValueRef coverage;
1546
1547 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1548 coverage = LLVMGetParam(ctx->radeon_bld.main_fn,
1549 samplemask_param);
1550 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1551
1552 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1553 ctx->i32,
1554 &coverage, 1, LLVMReadNoneAttribute);
1555
1556 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1557 ctx->f32, "");
1558
1559 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1560 lp_build_const_float(gallivm,
1561 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1562
1563 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1564 }
1565
1566 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
1567 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1568 {
1569 struct si_shader_context *ctx = si_shader_context(bld_base);
1570 struct lp_build_context *base = &bld_base->base;
1571 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1572 unsigned reg_index;
1573 unsigned chan;
1574 unsigned const_chan;
1575 LLVMValueRef base_elt;
1576 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1577 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
1578 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
1579
1580 for (reg_index = 0; reg_index < 2; reg_index ++) {
1581 LLVMValueRef *args = pos[2 + reg_index];
1582
1583 args[5] =
1584 args[6] =
1585 args[7] =
1586 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1587
1588 /* Compute dot products of position and user clip plane vectors */
1589 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1590 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1591 args[1] = lp_build_const_int32(base->gallivm,
1592 ((reg_index * 4 + chan) * 4 +
1593 const_chan) * 4);
1594 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1595 args[1], ctx->f32);
1596 args[5 + chan] =
1597 lp_build_add(base, args[5 + chan],
1598 lp_build_mul(base, base_elt,
1599 out_elts[const_chan]));
1600 }
1601 }
1602
1603 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1604 args[1] = uint->zero;
1605 args[2] = uint->zero;
1606 args[3] = lp_build_const_int32(base->gallivm,
1607 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1608 args[4] = uint->zero;
1609 }
1610 }
1611
1612 static void si_dump_streamout(struct pipe_stream_output_info *so)
1613 {
1614 unsigned i;
1615
1616 if (so->num_outputs)
1617 fprintf(stderr, "STREAMOUT\n");
1618
1619 for (i = 0; i < so->num_outputs; i++) {
1620 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1621 so->output[i].start_component;
1622 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1623 i, so->output[i].output_buffer,
1624 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1625 so->output[i].register_index,
1626 mask & 1 ? "x" : "",
1627 mask & 2 ? "y" : "",
1628 mask & 4 ? "z" : "",
1629 mask & 8 ? "w" : "");
1630 }
1631 }
1632
1633 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1634 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1635 * or v4i32 (num_channels=3,4). */
1636 static void build_tbuffer_store(struct si_shader_context *ctx,
1637 LLVMValueRef rsrc,
1638 LLVMValueRef vdata,
1639 unsigned num_channels,
1640 LLVMValueRef vaddr,
1641 LLVMValueRef soffset,
1642 unsigned inst_offset,
1643 unsigned dfmt,
1644 unsigned nfmt,
1645 unsigned offen,
1646 unsigned idxen,
1647 unsigned glc,
1648 unsigned slc,
1649 unsigned tfe)
1650 {
1651 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1652 LLVMValueRef args[] = {
1653 rsrc,
1654 vdata,
1655 LLVMConstInt(ctx->i32, num_channels, 0),
1656 vaddr,
1657 soffset,
1658 LLVMConstInt(ctx->i32, inst_offset, 0),
1659 LLVMConstInt(ctx->i32, dfmt, 0),
1660 LLVMConstInt(ctx->i32, nfmt, 0),
1661 LLVMConstInt(ctx->i32, offen, 0),
1662 LLVMConstInt(ctx->i32, idxen, 0),
1663 LLVMConstInt(ctx->i32, glc, 0),
1664 LLVMConstInt(ctx->i32, slc, 0),
1665 LLVMConstInt(ctx->i32, tfe, 0)
1666 };
1667
1668 /* The instruction offset field has 12 bits */
1669 assert(offen || inst_offset < (1 << 12));
1670
1671 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1672 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1673 const char *types[] = {"i32", "v2i32", "v4i32"};
1674 char name[256];
1675 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1676
1677 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
1678 args, Elements(args), 0);
1679 }
1680
1681 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
1682 LLVMValueRef rsrc,
1683 LLVMValueRef vdata,
1684 unsigned num_channels,
1685 LLVMValueRef vaddr,
1686 LLVMValueRef soffset,
1687 unsigned inst_offset)
1688 {
1689 static unsigned dfmt[] = {
1690 V_008F0C_BUF_DATA_FORMAT_32,
1691 V_008F0C_BUF_DATA_FORMAT_32_32,
1692 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1693 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1694 };
1695 assert(num_channels >= 1 && num_channels <= 4);
1696
1697 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
1698 inst_offset, dfmt[num_channels-1],
1699 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1700 }
1701
1702 /* On SI, the vertex shader is responsible for writing streamout data
1703 * to buffers. */
1704 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
1705 struct si_shader_output_values *outputs,
1706 unsigned noutput)
1707 {
1708 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
1709 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1710 LLVMBuilderRef builder = gallivm->builder;
1711 int i, j;
1712 struct lp_build_if_state if_ctx;
1713
1714 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1715 LLVMValueRef so_vtx_count =
1716 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
1717
1718 LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", ctx->i32,
1719 NULL, 0, LLVMReadNoneAttribute);
1720
1721 /* can_emit = tid < so_vtx_count; */
1722 LLVMValueRef can_emit =
1723 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1724
1725 LLVMValueRef stream_id =
1726 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
1727
1728 /* Emit the streamout code conditionally. This actually avoids
1729 * out-of-bounds buffer access. The hw tells us via the SGPR
1730 * (so_vtx_count) which threads are allowed to emit streamout data. */
1731 lp_build_if(&if_ctx, gallivm, can_emit);
1732 {
1733 /* The buffer offset is computed as follows:
1734 * ByteOffset = streamout_offset[buffer_id]*4 +
1735 * (streamout_write_index + thread_id)*stride[buffer_id] +
1736 * attrib_offset
1737 */
1738
1739 LLVMValueRef so_write_index =
1740 LLVMGetParam(ctx->radeon_bld.main_fn,
1741 ctx->param_streamout_write_index);
1742
1743 /* Compute (streamout_write_index + thread_id). */
1744 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1745
1746 /* Compute the write offset for each enabled buffer. */
1747 LLVMValueRef so_write_offset[4] = {};
1748 for (i = 0; i < 4; i++) {
1749 if (!so->stride[i])
1750 continue;
1751
1752 LLVMValueRef so_offset = LLVMGetParam(ctx->radeon_bld.main_fn,
1753 ctx->param_streamout_offset[i]);
1754 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
1755
1756 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1757 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
1758 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1759 }
1760
1761 /* Write streamout data. */
1762 for (i = 0; i < so->num_outputs; i++) {
1763 unsigned buf_idx = so->output[i].output_buffer;
1764 unsigned reg = so->output[i].register_index;
1765 unsigned start = so->output[i].start_component;
1766 unsigned num_comps = so->output[i].num_components;
1767 unsigned stream = so->output[i].stream;
1768 LLVMValueRef out[4];
1769 struct lp_build_if_state if_ctx_stream;
1770
1771 assert(num_comps && num_comps <= 4);
1772 if (!num_comps || num_comps > 4)
1773 continue;
1774
1775 if (reg >= noutput)
1776 continue;
1777
1778 /* Load the output as int. */
1779 for (j = 0; j < num_comps; j++) {
1780 out[j] = LLVMBuildBitCast(builder,
1781 outputs[reg].values[start+j],
1782 ctx->i32, "");
1783 }
1784
1785 /* Pack the output. */
1786 LLVMValueRef vdata = NULL;
1787
1788 switch (num_comps) {
1789 case 1: /* as i32 */
1790 vdata = out[0];
1791 break;
1792 case 2: /* as v2i32 */
1793 case 3: /* as v4i32 (aligned to 4) */
1794 case 4: /* as v4i32 */
1795 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
1796 for (j = 0; j < num_comps; j++) {
1797 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1798 LLVMConstInt(ctx->i32, j, 0), "");
1799 }
1800 break;
1801 }
1802
1803 LLVMValueRef can_emit_stream =
1804 LLVMBuildICmp(builder, LLVMIntEQ,
1805 stream_id,
1806 lp_build_const_int32(gallivm, stream), "");
1807
1808 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1809 build_tbuffer_store_dwords(ctx, ctx->so_buffers[buf_idx],
1810 vdata, num_comps,
1811 so_write_offset[buf_idx],
1812 LLVMConstInt(ctx->i32, 0, 0),
1813 so->output[i].dst_offset*4);
1814 lp_build_endif(&if_ctx_stream);
1815 }
1816 }
1817 lp_build_endif(&if_ctx);
1818 }
1819
1820
1821 /* Generate export instructions for hardware VS shader stage */
1822 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1823 struct si_shader_output_values *outputs,
1824 unsigned noutput)
1825 {
1826 struct si_shader_context *ctx = si_shader_context(bld_base);
1827 struct si_shader *shader = ctx->shader;
1828 struct lp_build_context *base = &bld_base->base;
1829 struct lp_build_context *uint =
1830 &ctx->radeon_bld.soa.bld_base.uint_bld;
1831 LLVMValueRef args[9];
1832 LLVMValueRef pos_args[4][9] = { { 0 } };
1833 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1834 unsigned semantic_name, semantic_index;
1835 unsigned target;
1836 unsigned param_count = 0;
1837 unsigned pos_idx;
1838 int i;
1839
1840 if (outputs && ctx->shader->selector->so.num_outputs) {
1841 si_llvm_emit_streamout(ctx, outputs, noutput);
1842 }
1843
1844 for (i = 0; i < noutput; i++) {
1845 semantic_name = outputs[i].name;
1846 semantic_index = outputs[i].sid;
1847
1848 handle_semantic:
1849 /* Select the correct target */
1850 switch(semantic_name) {
1851 case TGSI_SEMANTIC_PSIZE:
1852 psize_value = outputs[i].values[0];
1853 continue;
1854 case TGSI_SEMANTIC_EDGEFLAG:
1855 edgeflag_value = outputs[i].values[0];
1856 continue;
1857 case TGSI_SEMANTIC_LAYER:
1858 layer_value = outputs[i].values[0];
1859 semantic_name = TGSI_SEMANTIC_GENERIC;
1860 goto handle_semantic;
1861 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1862 viewport_index_value = outputs[i].values[0];
1863 semantic_name = TGSI_SEMANTIC_GENERIC;
1864 goto handle_semantic;
1865 case TGSI_SEMANTIC_POSITION:
1866 target = V_008DFC_SQ_EXP_POS;
1867 break;
1868 case TGSI_SEMANTIC_COLOR:
1869 case TGSI_SEMANTIC_BCOLOR:
1870 target = V_008DFC_SQ_EXP_PARAM + param_count;
1871 shader->vs_output_param_offset[i] = param_count;
1872 param_count++;
1873 break;
1874 case TGSI_SEMANTIC_CLIPDIST:
1875 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1876 break;
1877 case TGSI_SEMANTIC_CLIPVERTEX:
1878 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1879 continue;
1880 case TGSI_SEMANTIC_PRIMID:
1881 case TGSI_SEMANTIC_FOG:
1882 case TGSI_SEMANTIC_TEXCOORD:
1883 case TGSI_SEMANTIC_GENERIC:
1884 target = V_008DFC_SQ_EXP_PARAM + param_count;
1885 shader->vs_output_param_offset[i] = param_count;
1886 param_count++;
1887 break;
1888 default:
1889 target = 0;
1890 fprintf(stderr,
1891 "Warning: SI unhandled vs output type:%d\n",
1892 semantic_name);
1893 }
1894
1895 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1896
1897 if (target >= V_008DFC_SQ_EXP_POS &&
1898 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1899 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1900 args, sizeof(args));
1901 } else {
1902 lp_build_intrinsic(base->gallivm->builder,
1903 "llvm.SI.export", ctx->voidt,
1904 args, 9, 0);
1905 }
1906
1907 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1908 semantic_name = TGSI_SEMANTIC_GENERIC;
1909 goto handle_semantic;
1910 }
1911 }
1912
1913 shader->nr_param_exports = param_count;
1914
1915 /* We need to add the position output manually if it's missing. */
1916 if (!pos_args[0][0]) {
1917 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1918 pos_args[0][1] = uint->zero; /* EXEC mask */
1919 pos_args[0][2] = uint->zero; /* last export? */
1920 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1921 pos_args[0][4] = uint->zero; /* COMPR flag */
1922 pos_args[0][5] = base->zero; /* X */
1923 pos_args[0][6] = base->zero; /* Y */
1924 pos_args[0][7] = base->zero; /* Z */
1925 pos_args[0][8] = base->one; /* W */
1926 }
1927
1928 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1929 if (shader->selector->info.writes_psize ||
1930 shader->selector->info.writes_edgeflag ||
1931 shader->selector->info.writes_viewport_index ||
1932 shader->selector->info.writes_layer) {
1933 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1934 shader->selector->info.writes_psize |
1935 (shader->selector->info.writes_edgeflag << 1) |
1936 (shader->selector->info.writes_layer << 2) |
1937 (shader->selector->info.writes_viewport_index << 3));
1938 pos_args[1][1] = uint->zero; /* EXEC mask */
1939 pos_args[1][2] = uint->zero; /* last export? */
1940 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1941 pos_args[1][4] = uint->zero; /* COMPR flag */
1942 pos_args[1][5] = base->zero; /* X */
1943 pos_args[1][6] = base->zero; /* Y */
1944 pos_args[1][7] = base->zero; /* Z */
1945 pos_args[1][8] = base->zero; /* W */
1946
1947 if (shader->selector->info.writes_psize)
1948 pos_args[1][5] = psize_value;
1949
1950 if (shader->selector->info.writes_edgeflag) {
1951 /* The output is a float, but the hw expects an integer
1952 * with the first bit containing the edge flag. */
1953 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1954 edgeflag_value,
1955 ctx->i32, "");
1956 edgeflag_value = lp_build_min(&bld_base->int_bld,
1957 edgeflag_value,
1958 bld_base->int_bld.one);
1959
1960 /* The LLVM intrinsic expects a float. */
1961 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1962 edgeflag_value,
1963 ctx->f32, "");
1964 }
1965
1966 if (shader->selector->info.writes_layer)
1967 pos_args[1][7] = layer_value;
1968
1969 if (shader->selector->info.writes_viewport_index)
1970 pos_args[1][8] = viewport_index_value;
1971 }
1972
1973 for (i = 0; i < 4; i++)
1974 if (pos_args[i][0])
1975 shader->nr_pos_exports++;
1976
1977 pos_idx = 0;
1978 for (i = 0; i < 4; i++) {
1979 if (!pos_args[i][0])
1980 continue;
1981
1982 /* Specify the target we are exporting */
1983 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1984
1985 if (pos_idx == shader->nr_pos_exports)
1986 /* Specify that this is the last export */
1987 pos_args[i][2] = uint->one;
1988
1989 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
1990 ctx->voidt, pos_args[i], 9, 0);
1991 }
1992 }
1993
1994 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
1995 LLVMValueRef rel_patch_id,
1996 LLVMValueRef invocation_id,
1997 LLVMValueRef tcs_out_current_patch_data_offset)
1998 {
1999 struct si_shader_context *ctx = si_shader_context(bld_base);
2000 struct gallivm_state *gallivm = bld_base->base.gallivm;
2001 struct si_shader *shader = ctx->shader;
2002 unsigned tess_inner_index, tess_outer_index;
2003 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2004 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2005 unsigned stride, outer_comps, inner_comps, i;
2006 struct lp_build_if_state if_ctx;
2007
2008 /* Do this only for invocation 0, because the tess levels are per-patch,
2009 * not per-vertex.
2010 *
2011 * This can't jump, because invocation 0 executes this. It should
2012 * at least mask out the loads and stores for other invocations.
2013 */
2014 lp_build_if(&if_ctx, gallivm,
2015 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2016 invocation_id, bld_base->uint_bld.zero, ""));
2017
2018 /* Determine the layout of one tess factor element in the buffer. */
2019 switch (shader->key.tcs.epilog.prim_mode) {
2020 case PIPE_PRIM_LINES:
2021 stride = 2; /* 2 dwords, 1 vec2 store */
2022 outer_comps = 2;
2023 inner_comps = 0;
2024 break;
2025 case PIPE_PRIM_TRIANGLES:
2026 stride = 4; /* 4 dwords, 1 vec4 store */
2027 outer_comps = 3;
2028 inner_comps = 1;
2029 break;
2030 case PIPE_PRIM_QUADS:
2031 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2032 outer_comps = 4;
2033 inner_comps = 2;
2034 break;
2035 default:
2036 assert(0);
2037 return;
2038 }
2039
2040 /* Load tess_inner and tess_outer from LDS.
2041 * Any invocation can write them, so we can't get them from a temporary.
2042 */
2043 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2044 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2045
2046 lds_base = tcs_out_current_patch_data_offset;
2047 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2048 lp_build_const_int32(gallivm,
2049 tess_inner_index * 4), "");
2050 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2051 lp_build_const_int32(gallivm,
2052 tess_outer_index * 4), "");
2053
2054 for (i = 0; i < outer_comps; i++)
2055 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2056 for (i = 0; i < inner_comps; i++)
2057 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2058
2059 /* Convert the outputs to vectors for stores. */
2060 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2061 vec1 = NULL;
2062
2063 if (stride > 4)
2064 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2065
2066 /* Get the buffer. */
2067 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2068 SI_PARAM_RW_BUFFERS);
2069 buffer = build_indexed_load_const(ctx, rw_buffers,
2070 lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR));
2071
2072 /* Get the offset. */
2073 tf_base = LLVMGetParam(ctx->radeon_bld.main_fn,
2074 SI_PARAM_TESS_FACTOR_OFFSET);
2075 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2076 lp_build_const_int32(gallivm, 4 * stride), "");
2077
2078 /* Store the outputs. */
2079 build_tbuffer_store_dwords(ctx, buffer, vec0,
2080 MIN2(stride, 4), byteoffset, tf_base, 0);
2081 if (vec1)
2082 build_tbuffer_store_dwords(ctx, buffer, vec1,
2083 stride - 4, byteoffset, tf_base, 16);
2084 lp_build_endif(&if_ctx);
2085 }
2086
2087 /* This only writes the tessellation factor levels. */
2088 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2089 {
2090 struct si_shader_context *ctx = si_shader_context(bld_base);
2091 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2092
2093 rel_patch_id = get_rel_patch_id(ctx);
2094 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2095 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2096
2097 if (!ctx->is_monolithic) {
2098 /* Return epilog parameters from this function. */
2099 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2100 LLVMValueRef ret = ctx->return_value;
2101 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2102 unsigned vgpr;
2103
2104 /* RW_BUFFERS pointer */
2105 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2106 SI_PARAM_RW_BUFFERS);
2107 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2108 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2109 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2110 bld_base->uint_bld.zero, "");
2111 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2112 bld_base->uint_bld.one, "");
2113 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2114 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2115
2116 /* Tess factor buffer soffset is after user SGPRs. */
2117 tf_soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2118 SI_PARAM_TESS_FACTOR_OFFSET);
2119 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2120 SI_TCS_NUM_USER_SGPR, "");
2121
2122 /* VGPRs */
2123 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2124 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2125 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2126
2127 vgpr = SI_TCS_NUM_USER_SGPR + 1;
2128 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2129 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2130 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2131 ctx->return_value = ret;
2132 return;
2133 }
2134
2135 si_write_tess_factors(bld_base, rel_patch_id, invocation_id, tf_lds_offset);
2136 }
2137
2138 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2139 {
2140 struct si_shader_context *ctx = si_shader_context(bld_base);
2141 struct si_shader *shader = ctx->shader;
2142 struct tgsi_shader_info *info = &shader->selector->info;
2143 struct gallivm_state *gallivm = bld_base->base.gallivm;
2144 unsigned i, chan;
2145 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
2146 ctx->param_rel_auto_id);
2147 LLVMValueRef vertex_dw_stride =
2148 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2149 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2150 vertex_dw_stride, "");
2151
2152 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2153 * its inputs from it. */
2154 for (i = 0; i < info->num_outputs; i++) {
2155 LLVMValueRef *out_ptr = ctx->radeon_bld.soa.outputs[i];
2156 unsigned name = info->output_semantic_name[i];
2157 unsigned index = info->output_semantic_index[i];
2158 int param = si_shader_io_get_unique_index(name, index);
2159 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2160 lp_build_const_int32(gallivm, param * 4), "");
2161
2162 for (chan = 0; chan < 4; chan++) {
2163 lds_store(bld_base, chan, dw_addr,
2164 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2165 }
2166 }
2167 }
2168
2169 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2170 {
2171 struct si_shader_context *ctx = si_shader_context(bld_base);
2172 struct gallivm_state *gallivm = bld_base->base.gallivm;
2173 struct si_shader *es = ctx->shader;
2174 struct tgsi_shader_info *info = &es->selector->info;
2175 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2176 ctx->param_es2gs_offset);
2177 unsigned chan;
2178 int i;
2179
2180 for (i = 0; i < info->num_outputs; i++) {
2181 LLVMValueRef *out_ptr =
2182 ctx->radeon_bld.soa.outputs[i];
2183 int param_index;
2184
2185 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2186 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2187 continue;
2188
2189 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2190 info->output_semantic_index[i]);
2191
2192 for (chan = 0; chan < 4; chan++) {
2193 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2194 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2195
2196 build_tbuffer_store(ctx,
2197 ctx->esgs_ring,
2198 out_val, 1,
2199 LLVMGetUndef(ctx->i32), soffset,
2200 (4 * param_index + chan) * 4,
2201 V_008F0C_BUF_DATA_FORMAT_32,
2202 V_008F0C_BUF_NUM_FORMAT_UINT,
2203 0, 0, 1, 1, 0);
2204 }
2205 }
2206 }
2207
2208 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2209 {
2210 struct si_shader_context *ctx = si_shader_context(bld_base);
2211 struct gallivm_state *gallivm = bld_base->base.gallivm;
2212 LLVMValueRef args[2];
2213
2214 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2215 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2216 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2217 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
2218 }
2219
2220 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2221 {
2222 struct si_shader_context *ctx = si_shader_context(bld_base);
2223 struct gallivm_state *gallivm = bld_base->base.gallivm;
2224 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2225 struct si_shader_output_values *outputs = NULL;
2226 int i,j;
2227
2228 assert(!ctx->is_gs_copy_shader);
2229
2230 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2231
2232 /* Vertex color clamping.
2233 *
2234 * This uses a state constant loaded in a user data SGPR and
2235 * an IF statement is added that clamps all colors if the constant
2236 * is true.
2237 */
2238 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
2239 struct lp_build_if_state if_ctx;
2240 LLVMValueRef cond = NULL;
2241 LLVMValueRef addr, val;
2242
2243 for (i = 0; i < info->num_outputs; i++) {
2244 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2245 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2246 continue;
2247
2248 /* We've found a color. */
2249 if (!cond) {
2250 /* The state is in the first bit of the user SGPR. */
2251 cond = LLVMGetParam(ctx->radeon_bld.main_fn,
2252 SI_PARAM_VS_STATE_BITS);
2253 cond = LLVMBuildTrunc(gallivm->builder, cond,
2254 ctx->i1, "");
2255 lp_build_if(&if_ctx, gallivm, cond);
2256 }
2257
2258 for (j = 0; j < 4; j++) {
2259 addr = ctx->radeon_bld.soa.outputs[i][j];
2260 val = LLVMBuildLoad(gallivm->builder, addr, "");
2261 val = radeon_llvm_saturate(bld_base, val);
2262 LLVMBuildStore(gallivm->builder, val, addr);
2263 }
2264 }
2265
2266 if (cond)
2267 lp_build_endif(&if_ctx);
2268 }
2269
2270 for (i = 0; i < info->num_outputs; i++) {
2271 outputs[i].name = info->output_semantic_name[i];
2272 outputs[i].sid = info->output_semantic_index[i];
2273
2274 for (j = 0; j < 4; j++)
2275 outputs[i].values[j] =
2276 LLVMBuildLoad(gallivm->builder,
2277 ctx->radeon_bld.soa.outputs[i][j],
2278 "");
2279 }
2280
2281 if (ctx->is_monolithic) {
2282 /* Export PrimitiveID when PS needs it. */
2283 if (si_vs_exports_prim_id(ctx->shader)) {
2284 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2285 outputs[i].sid = 0;
2286 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2287 get_primitive_id(bld_base, 0));
2288 outputs[i].values[1] = bld_base->base.undef;
2289 outputs[i].values[2] = bld_base->base.undef;
2290 outputs[i].values[3] = bld_base->base.undef;
2291 i++;
2292 }
2293 } else {
2294 /* Return the primitive ID from the LLVM function. */
2295 ctx->return_value =
2296 LLVMBuildInsertValue(gallivm->builder,
2297 ctx->return_value,
2298 bitcast(bld_base, TGSI_TYPE_FLOAT,
2299 get_primitive_id(bld_base, 0)),
2300 VS_EPILOG_PRIMID_LOC, "");
2301 }
2302
2303 si_llvm_export_vs(bld_base, outputs, i);
2304 FREE(outputs);
2305 }
2306
2307 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2308 LLVMValueRef depth, LLVMValueRef stencil,
2309 LLVMValueRef samplemask)
2310 {
2311 struct si_shader_context *ctx = si_shader_context(bld_base);
2312 struct lp_build_context *base = &bld_base->base;
2313 struct lp_build_context *uint = &bld_base->uint_bld;
2314 LLVMValueRef args[9];
2315 unsigned mask = 0;
2316
2317 assert(depth || stencil || samplemask);
2318
2319 args[1] = uint->one; /* whether the EXEC mask is valid */
2320 args[2] = uint->one; /* DONE bit */
2321
2322 /* Specify the target we are exporting */
2323 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2324
2325 args[4] = uint->zero; /* COMP flag */
2326 args[5] = base->undef; /* R, depth */
2327 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2328 args[7] = base->undef; /* B, sample mask */
2329 args[8] = base->undef; /* A, alpha to mask */
2330
2331 if (depth) {
2332 args[5] = depth;
2333 mask |= 0x1;
2334 }
2335
2336 if (stencil) {
2337 args[6] = stencil;
2338 mask |= 0x2;
2339 }
2340
2341 if (samplemask) {
2342 args[7] = samplemask;
2343 mask |= 0x4;
2344 }
2345
2346 /* SI (except OLAND) has a bug that it only looks
2347 * at the X writemask component. */
2348 if (ctx->screen->b.chip_class == SI &&
2349 ctx->screen->b.family != CHIP_OLAND)
2350 mask |= 0x1;
2351
2352 /* Specify which components to enable */
2353 args[0] = lp_build_const_int32(base->gallivm, mask);
2354
2355 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2356 ctx->voidt, args, 9, 0);
2357 }
2358
2359 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2360 LLVMValueRef *color, unsigned index,
2361 unsigned samplemask_param,
2362 bool is_last)
2363 {
2364 struct si_shader_context *ctx = si_shader_context(bld_base);
2365 struct lp_build_context *base = &bld_base->base;
2366 int i;
2367
2368 /* Clamp color */
2369 if (ctx->shader->key.ps.epilog.clamp_color)
2370 for (i = 0; i < 4; i++)
2371 color[i] = radeon_llvm_saturate(bld_base, color[i]);
2372
2373 /* Alpha to one */
2374 if (ctx->shader->key.ps.epilog.alpha_to_one)
2375 color[3] = base->one;
2376
2377 /* Alpha test */
2378 if (index == 0 &&
2379 ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2380 si_alpha_test(bld_base, color[3]);
2381
2382 /* Line & polygon smoothing */
2383 if (ctx->shader->key.ps.epilog.poly_line_smoothing)
2384 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
2385 samplemask_param);
2386
2387 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2388 if (ctx->shader->key.ps.epilog.last_cbuf > 0) {
2389 LLVMValueRef args[8][9];
2390 int c, last = -1;
2391
2392 /* Get the export arguments, also find out what the last one is. */
2393 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
2394 si_llvm_init_export_args(bld_base, color,
2395 V_008DFC_SQ_EXP_MRT + c, args[c]);
2396 if (args[c][0] != bld_base->uint_bld.zero)
2397 last = c;
2398 }
2399
2400 /* Emit all exports. */
2401 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
2402 if (is_last && last == c) {
2403 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2404 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
2405 } else if (args[c][0] == bld_base->uint_bld.zero)
2406 continue; /* unnecessary NULL export */
2407
2408 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2409 ctx->voidt, args[c], 9, 0);
2410 }
2411 } else {
2412 LLVMValueRef args[9];
2413
2414 /* Export */
2415 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2416 args);
2417 if (is_last) {
2418 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2419 args[2] = bld_base->uint_bld.one; /* DONE bit */
2420 } else if (args[0] == bld_base->uint_bld.zero)
2421 return; /* unnecessary NULL export */
2422
2423 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2424 ctx->voidt, args, 9, 0);
2425 }
2426 }
2427
2428 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2429 {
2430 struct si_shader_context *ctx = si_shader_context(bld_base);
2431 struct lp_build_context *base = &bld_base->base;
2432 struct lp_build_context *uint = &bld_base->uint_bld;
2433 LLVMValueRef args[9];
2434
2435 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
2436 args[1] = uint->one; /* whether the EXEC mask is valid */
2437 args[2] = uint->one; /* DONE bit */
2438 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2439 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
2440 args[5] = uint->undef; /* R */
2441 args[6] = uint->undef; /* G */
2442 args[7] = uint->undef; /* B */
2443 args[8] = uint->undef; /* A */
2444
2445 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2446 ctx->voidt, args, 9, 0);
2447 }
2448
2449 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context *bld_base)
2450 {
2451 struct si_shader_context *ctx = si_shader_context(bld_base);
2452 struct si_shader *shader = ctx->shader;
2453 struct lp_build_context *base = &bld_base->base;
2454 struct tgsi_shader_info *info = &shader->selector->info;
2455 LLVMBuilderRef builder = base->gallivm->builder;
2456 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2457 int last_color_export = -1;
2458 int i;
2459
2460 /* Determine the last export. If MRTZ is present, it's always last.
2461 * Otherwise, find the last color export.
2462 */
2463 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask) {
2464 unsigned spi_format = shader->key.ps.epilog.spi_shader_col_format;
2465
2466 /* Don't export NULL and return if alpha-test is enabled. */
2467 if (shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS &&
2468 shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER &&
2469 (spi_format & 0xf) == 0)
2470 spi_format |= V_028714_SPI_SHADER_32_AR;
2471
2472 for (i = 0; i < info->num_outputs; i++) {
2473 unsigned index = info->output_semantic_index[i];
2474
2475 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR)
2476 continue;
2477
2478 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2479 if (shader->key.ps.epilog.last_cbuf > 0) {
2480 /* Just set this if any of the colorbuffers are enabled. */
2481 if (spi_format &
2482 ((1llu << (4 * (shader->key.ps.epilog.last_cbuf + 1))) - 1))
2483 last_color_export = i;
2484 continue;
2485 }
2486
2487 if ((spi_format >> (index * 4)) & 0xf)
2488 last_color_export = i;
2489 }
2490
2491 /* If there are no outputs, export NULL. */
2492 if (last_color_export == -1) {
2493 si_export_null(bld_base);
2494 return;
2495 }
2496 }
2497
2498 for (i = 0; i < info->num_outputs; i++) {
2499 unsigned semantic_name = info->output_semantic_name[i];
2500 unsigned semantic_index = info->output_semantic_index[i];
2501 unsigned j;
2502 LLVMValueRef color[4] = {};
2503
2504 /* Select the correct target */
2505 switch (semantic_name) {
2506 case TGSI_SEMANTIC_POSITION:
2507 depth = LLVMBuildLoad(builder,
2508 ctx->radeon_bld.soa.outputs[i][2], "");
2509 break;
2510 case TGSI_SEMANTIC_STENCIL:
2511 stencil = LLVMBuildLoad(builder,
2512 ctx->radeon_bld.soa.outputs[i][1], "");
2513 break;
2514 case TGSI_SEMANTIC_SAMPLEMASK:
2515 samplemask = LLVMBuildLoad(builder,
2516 ctx->radeon_bld.soa.outputs[i][0], "");
2517 break;
2518 case TGSI_SEMANTIC_COLOR:
2519 for (j = 0; j < 4; j++)
2520 color[j] = LLVMBuildLoad(builder,
2521 ctx->radeon_bld.soa.outputs[i][j], "");
2522
2523 si_export_mrt_color(bld_base, color, semantic_index,
2524 SI_PARAM_SAMPLE_COVERAGE,
2525 last_color_export == i);
2526 break;
2527 default:
2528 fprintf(stderr,
2529 "Warning: SI unhandled fs output type:%d\n",
2530 semantic_name);
2531 }
2532 }
2533
2534 if (depth || stencil || samplemask)
2535 si_export_mrt_z(bld_base, depth, stencil, samplemask);
2536 }
2537
2538 /**
2539 * Return PS outputs in this order:
2540 *
2541 * v[0:3] = color0.xyzw
2542 * v[4:7] = color1.xyzw
2543 * ...
2544 * vN+0 = Depth
2545 * vN+1 = Stencil
2546 * vN+2 = SampleMask
2547 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
2548 *
2549 * The alpha-ref SGPR is returned via its original location.
2550 */
2551 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
2552 {
2553 struct si_shader_context *ctx = si_shader_context(bld_base);
2554 struct si_shader *shader = ctx->shader;
2555 struct lp_build_context *base = &bld_base->base;
2556 struct tgsi_shader_info *info = &shader->selector->info;
2557 LLVMBuilderRef builder = base->gallivm->builder;
2558 unsigned i, j, first_vgpr, vgpr;
2559
2560 LLVMValueRef color[8][4] = {};
2561 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2562 LLVMValueRef ret;
2563
2564 /* Read the output values. */
2565 for (i = 0; i < info->num_outputs; i++) {
2566 unsigned semantic_name = info->output_semantic_name[i];
2567 unsigned semantic_index = info->output_semantic_index[i];
2568
2569 switch (semantic_name) {
2570 case TGSI_SEMANTIC_COLOR:
2571 assert(semantic_index < 8);
2572 for (j = 0; j < 4; j++) {
2573 LLVMValueRef ptr = ctx->radeon_bld.soa.outputs[i][j];
2574 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
2575 color[semantic_index][j] = result;
2576 }
2577 break;
2578 case TGSI_SEMANTIC_POSITION:
2579 depth = LLVMBuildLoad(builder,
2580 ctx->radeon_bld.soa.outputs[i][2], "");
2581 break;
2582 case TGSI_SEMANTIC_STENCIL:
2583 stencil = LLVMBuildLoad(builder,
2584 ctx->radeon_bld.soa.outputs[i][1], "");
2585 break;
2586 case TGSI_SEMANTIC_SAMPLEMASK:
2587 samplemask = LLVMBuildLoad(builder,
2588 ctx->radeon_bld.soa.outputs[i][0], "");
2589 break;
2590 default:
2591 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
2592 semantic_name);
2593 }
2594 }
2595
2596 /* Fill the return structure. */
2597 ret = ctx->return_value;
2598
2599 /* Set SGPRs. */
2600 ret = LLVMBuildInsertValue(builder, ret,
2601 bitcast(bld_base, TGSI_TYPE_SIGNED,
2602 LLVMGetParam(ctx->radeon_bld.main_fn,
2603 SI_PARAM_ALPHA_REF)),
2604 SI_SGPR_ALPHA_REF, "");
2605
2606 /* Set VGPRs */
2607 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
2608 for (i = 0; i < ARRAY_SIZE(color); i++) {
2609 if (!color[i][0])
2610 continue;
2611
2612 for (j = 0; j < 4; j++)
2613 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
2614 }
2615 if (depth)
2616 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
2617 if (stencil)
2618 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
2619 if (samplemask)
2620 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
2621
2622 /* Add the input sample mask for smoothing at the end. */
2623 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
2624 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
2625 ret = LLVMBuildInsertValue(builder, ret,
2626 LLVMGetParam(ctx->radeon_bld.main_fn,
2627 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
2628
2629 ctx->return_value = ret;
2630 }
2631
2632 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
2633 struct lp_build_tgsi_context *bld_base,
2634 struct lp_build_emit_data *emit_data);
2635
2636 static bool tgsi_is_array_sampler(unsigned target)
2637 {
2638 return target == TGSI_TEXTURE_1D_ARRAY ||
2639 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2640 target == TGSI_TEXTURE_2D_ARRAY ||
2641 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2642 target == TGSI_TEXTURE_CUBE_ARRAY ||
2643 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2644 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2645 }
2646
2647 static void set_tex_fetch_args(struct si_shader_context *ctx,
2648 struct lp_build_emit_data *emit_data,
2649 unsigned opcode, unsigned target,
2650 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
2651 LLVMValueRef *param, unsigned count,
2652 unsigned dmask)
2653 {
2654 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
2655 unsigned num_args;
2656 unsigned is_rect = target == TGSI_TEXTURE_RECT;
2657
2658 /* Pad to power of two vector */
2659 while (count < util_next_power_of_two(count))
2660 param[count++] = LLVMGetUndef(ctx->i32);
2661
2662 /* Texture coordinates. */
2663 if (count > 1)
2664 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
2665 else
2666 emit_data->args[0] = param[0];
2667
2668 /* Resource. */
2669 emit_data->args[1] = res_ptr;
2670 num_args = 2;
2671
2672 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
2673 emit_data->dst_type = ctx->v4i32;
2674 else {
2675 emit_data->dst_type = ctx->v4f32;
2676
2677 emit_data->args[num_args++] = samp_ptr;
2678 }
2679
2680 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
2681 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
2682 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
2683 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
2684 tgsi_is_array_sampler(target)); /* da */
2685 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
2686 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
2687 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
2688 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
2689
2690 emit_data->arg_count = num_args;
2691 }
2692
2693 static const struct lp_build_tgsi_action tex_action;
2694
2695 enum desc_type {
2696 DESC_IMAGE,
2697 DESC_FMASK,
2698 DESC_SAMPLER
2699 };
2700
2701 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
2702 {
2703 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
2704 CONST_ADDR_SPACE);
2705 }
2706
2707 /**
2708 * Load an image view, fmask view. or sampler state descriptor.
2709 */
2710 static LLVMValueRef get_sampler_desc(struct si_shader_context *ctx,
2711 LLVMValueRef index, enum desc_type type)
2712 {
2713 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
2714 LLVMBuilderRef builder = gallivm->builder;
2715 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
2716 SI_PARAM_SAMPLERS);
2717
2718 switch (type) {
2719 case DESC_IMAGE:
2720 /* The image is at [0:7]. */
2721 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
2722 break;
2723 case DESC_FMASK:
2724 /* The FMASK is at [8:15]. */
2725 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
2726 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
2727 break;
2728 case DESC_SAMPLER:
2729 /* The sampler state is at [12:15]. */
2730 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
2731 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
2732 ptr = LLVMBuildPointerCast(builder, ptr,
2733 const_array(ctx->v4i32, 0), "");
2734 break;
2735 }
2736
2737 return build_indexed_load_const(ctx, ptr, index);
2738 }
2739
2740 static void tex_fetch_ptrs(
2741 struct lp_build_tgsi_context *bld_base,
2742 struct lp_build_emit_data *emit_data,
2743 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
2744 {
2745 struct si_shader_context *ctx = si_shader_context(bld_base);
2746 const struct tgsi_full_instruction *inst = emit_data->inst;
2747 unsigned target = inst->Texture.Texture;
2748 unsigned sampler_src;
2749 unsigned sampler_index;
2750
2751 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
2752 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
2753
2754 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
2755 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
2756 LLVMValueRef ind_index;
2757
2758 ind_index = get_indirect_index(ctx, &reg->Indirect, reg->Register.Index);
2759
2760 *res_ptr = get_sampler_desc(ctx, ind_index, DESC_IMAGE);
2761
2762 if (target == TGSI_TEXTURE_2D_MSAA ||
2763 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2764 *samp_ptr = NULL;
2765 *fmask_ptr = get_sampler_desc(ctx, ind_index, DESC_FMASK);
2766 } else {
2767 *samp_ptr = get_sampler_desc(ctx, ind_index, DESC_SAMPLER);
2768 *fmask_ptr = NULL;
2769 }
2770 } else {
2771 *res_ptr = ctx->sampler_views[sampler_index];
2772 *samp_ptr = ctx->sampler_states[sampler_index];
2773 *fmask_ptr = ctx->fmasks[sampler_index];
2774 }
2775 }
2776
2777 static void tex_fetch_args(
2778 struct lp_build_tgsi_context *bld_base,
2779 struct lp_build_emit_data *emit_data)
2780 {
2781 struct si_shader_context *ctx = si_shader_context(bld_base);
2782 struct gallivm_state *gallivm = bld_base->base.gallivm;
2783 LLVMBuilderRef builder = gallivm->builder;
2784 const struct tgsi_full_instruction *inst = emit_data->inst;
2785 unsigned opcode = inst->Instruction.Opcode;
2786 unsigned target = inst->Texture.Texture;
2787 LLVMValueRef coords[5], derivs[6];
2788 LLVMValueRef address[16];
2789 int ref_pos;
2790 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
2791 unsigned count = 0;
2792 unsigned chan;
2793 unsigned num_deriv_channels = 0;
2794 bool has_offset = inst->Texture.NumOffsets > 0;
2795 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2796 unsigned dmask = 0xf;
2797
2798 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2799
2800 if (opcode == TGSI_OPCODE_TXQ) {
2801 if (target == TGSI_TEXTURE_BUFFER) {
2802 /* Read the size from the buffer descriptor directly. */
2803 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
2804 LLVMValueRef size = LLVMBuildExtractElement(builder, res,
2805 lp_build_const_int32(gallivm, 6), "");
2806
2807 if (ctx->screen->b.chip_class >= VI) {
2808 /* On VI, the descriptor contains the size in bytes,
2809 * but TXQ must return the size in elements.
2810 * The stride is always non-zero for resources using TXQ.
2811 */
2812 LLVMValueRef stride =
2813 LLVMBuildExtractElement(builder, res,
2814 lp_build_const_int32(gallivm, 5), "");
2815 stride = LLVMBuildLShr(builder, stride,
2816 lp_build_const_int32(gallivm, 16), "");
2817 stride = LLVMBuildAnd(builder, stride,
2818 lp_build_const_int32(gallivm, 0x3FFF), "");
2819
2820 size = LLVMBuildUDiv(builder, size, stride, "");
2821 }
2822
2823 emit_data->args[0] = size;
2824 return;
2825 }
2826
2827 /* Textures - set the mip level. */
2828 address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2829
2830 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
2831 NULL, address, count, 0xf);
2832 return;
2833 }
2834
2835 if (target == TGSI_TEXTURE_BUFFER) {
2836 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
2837
2838 /* Bitcast and truncate v8i32 to v16i8. */
2839 LLVMValueRef res = res_ptr;
2840 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
2841 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
2842 res = LLVMBuildBitCast(gallivm->builder, res, ctx->v16i8, "");
2843
2844 emit_data->dst_type = ctx->v4f32;
2845 emit_data->args[0] = res;
2846 emit_data->args[1] = bld_base->uint_bld.zero;
2847 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
2848 emit_data->arg_count = 3;
2849 return;
2850 }
2851
2852 /* Fetch and project texture coordinates */
2853 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
2854 for (chan = 0; chan < 3; chan++ ) {
2855 coords[chan] = lp_build_emit_fetch(bld_base,
2856 emit_data->inst, 0,
2857 chan);
2858 if (opcode == TGSI_OPCODE_TXP)
2859 coords[chan] = lp_build_emit_llvm_binary(bld_base,
2860 TGSI_OPCODE_DIV,
2861 coords[chan],
2862 coords[3]);
2863 }
2864
2865 if (opcode == TGSI_OPCODE_TXP)
2866 coords[3] = bld_base->base.one;
2867
2868 /* Pack offsets. */
2869 if (has_offset && opcode != TGSI_OPCODE_TXF) {
2870 /* The offsets are six-bit signed integers packed like this:
2871 * X=[5:0], Y=[13:8], and Z=[21:16].
2872 */
2873 LLVMValueRef offset[3], pack;
2874
2875 assert(inst->Texture.NumOffsets == 1);
2876
2877 for (chan = 0; chan < 3; chan++) {
2878 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
2879 emit_data->inst, 0, chan);
2880 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
2881 lp_build_const_int32(gallivm, 0x3f), "");
2882 if (chan)
2883 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
2884 lp_build_const_int32(gallivm, chan*8), "");
2885 }
2886
2887 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
2888 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
2889 address[count++] = pack;
2890 }
2891
2892 /* Pack LOD bias value */
2893 if (opcode == TGSI_OPCODE_TXB)
2894 address[count++] = coords[3];
2895 if (opcode == TGSI_OPCODE_TXB2)
2896 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2897
2898 /* Pack depth comparison value */
2899 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
2900 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2901 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2902 } else {
2903 assert(ref_pos >= 0);
2904 address[count++] = coords[ref_pos];
2905 }
2906 }
2907
2908 /* Pack user derivatives */
2909 if (opcode == TGSI_OPCODE_TXD) {
2910 int param, num_src_deriv_channels;
2911
2912 switch (target) {
2913 case TGSI_TEXTURE_3D:
2914 num_src_deriv_channels = 3;
2915 num_deriv_channels = 3;
2916 break;
2917 case TGSI_TEXTURE_2D:
2918 case TGSI_TEXTURE_SHADOW2D:
2919 case TGSI_TEXTURE_RECT:
2920 case TGSI_TEXTURE_SHADOWRECT:
2921 case TGSI_TEXTURE_2D_ARRAY:
2922 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2923 num_src_deriv_channels = 2;
2924 num_deriv_channels = 2;
2925 break;
2926 case TGSI_TEXTURE_CUBE:
2927 case TGSI_TEXTURE_SHADOWCUBE:
2928 case TGSI_TEXTURE_CUBE_ARRAY:
2929 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
2930 /* Cube derivatives will be converted to 2D. */
2931 num_src_deriv_channels = 3;
2932 num_deriv_channels = 2;
2933 break;
2934 case TGSI_TEXTURE_1D:
2935 case TGSI_TEXTURE_SHADOW1D:
2936 case TGSI_TEXTURE_1D_ARRAY:
2937 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2938 num_src_deriv_channels = 1;
2939 num_deriv_channels = 1;
2940 break;
2941 default:
2942 unreachable("invalid target");
2943 }
2944
2945 for (param = 0; param < 2; param++)
2946 for (chan = 0; chan < num_src_deriv_channels; chan++)
2947 derivs[param * num_src_deriv_channels + chan] =
2948 lp_build_emit_fetch(bld_base, inst, param+1, chan);
2949 }
2950
2951 if (target == TGSI_TEXTURE_CUBE ||
2952 target == TGSI_TEXTURE_CUBE_ARRAY ||
2953 target == TGSI_TEXTURE_SHADOWCUBE ||
2954 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2955 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
2956
2957 if (opcode == TGSI_OPCODE_TXD)
2958 for (int i = 0; i < num_deriv_channels * 2; i++)
2959 address[count++] = derivs[i];
2960
2961 /* Pack texture coordinates */
2962 address[count++] = coords[0];
2963 if (num_coords > 1)
2964 address[count++] = coords[1];
2965 if (num_coords > 2)
2966 address[count++] = coords[2];
2967
2968 /* Pack LOD or sample index */
2969 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
2970 address[count++] = coords[3];
2971 else if (opcode == TGSI_OPCODE_TXL2)
2972 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2973
2974 if (count > 16) {
2975 assert(!"Cannot handle more than 16 texture address parameters");
2976 count = 16;
2977 }
2978
2979 for (chan = 0; chan < count; chan++ ) {
2980 address[chan] = LLVMBuildBitCast(gallivm->builder,
2981 address[chan], ctx->i32, "");
2982 }
2983
2984 /* Adjust the sample index according to FMASK.
2985 *
2986 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2987 * which is the identity mapping. Each nibble says which physical sample
2988 * should be fetched to get that sample.
2989 *
2990 * For example, 0x11111100 means there are only 2 samples stored and
2991 * the second sample covers 3/4 of the pixel. When reading samples 0
2992 * and 1, return physical sample 0 (determined by the first two 0s
2993 * in FMASK), otherwise return physical sample 1.
2994 *
2995 * The sample index should be adjusted as follows:
2996 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2997 */
2998 if (target == TGSI_TEXTURE_2D_MSAA ||
2999 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
3000 struct lp_build_context *uint_bld = &bld_base->uint_bld;
3001 struct lp_build_emit_data txf_emit_data = *emit_data;
3002 LLVMValueRef txf_address[4];
3003 unsigned txf_count = count;
3004 struct tgsi_full_instruction inst = {};
3005
3006 memcpy(txf_address, address, sizeof(txf_address));
3007
3008 if (target == TGSI_TEXTURE_2D_MSAA) {
3009 txf_address[2] = bld_base->uint_bld.zero;
3010 }
3011 txf_address[3] = bld_base->uint_bld.zero;
3012
3013 /* Read FMASK using TXF. */
3014 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
3015 inst.Texture.Texture = target;
3016 txf_emit_data.inst = &inst;
3017 txf_emit_data.chan = 0;
3018 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
3019 target, fmask_ptr, NULL,
3020 txf_address, txf_count, 0xf);
3021 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
3022
3023 /* Initialize some constants. */
3024 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
3025 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
3026
3027 /* Apply the formula. */
3028 LLVMValueRef fmask =
3029 LLVMBuildExtractElement(gallivm->builder,
3030 txf_emit_data.output[0],
3031 uint_bld->zero, "");
3032
3033 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
3034
3035 LLVMValueRef sample_index4 =
3036 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
3037
3038 LLVMValueRef shifted_fmask =
3039 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
3040
3041 LLVMValueRef final_sample =
3042 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
3043
3044 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3045 * resource descriptor is 0 (invalid),
3046 */
3047 LLVMValueRef fmask_desc =
3048 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
3049 ctx->v8i32, "");
3050
3051 LLVMValueRef fmask_word1 =
3052 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
3053 uint_bld->one, "");
3054
3055 LLVMValueRef word1_is_nonzero =
3056 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
3057 fmask_word1, uint_bld->zero, "");
3058
3059 /* Replace the MSAA sample index. */
3060 address[sample_chan] =
3061 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
3062 final_sample, address[sample_chan], "");
3063 }
3064
3065 if (opcode == TGSI_OPCODE_TXF) {
3066 /* add tex offsets */
3067 if (inst->Texture.NumOffsets) {
3068 struct lp_build_context *uint_bld = &bld_base->uint_bld;
3069 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
3070 const struct tgsi_texture_offset *off = inst->TexOffsets;
3071
3072 assert(inst->Texture.NumOffsets == 1);
3073
3074 switch (target) {
3075 case TGSI_TEXTURE_3D:
3076 address[2] = lp_build_add(uint_bld, address[2],
3077 bld->immediates[off->Index][off->SwizzleZ]);
3078 /* fall through */
3079 case TGSI_TEXTURE_2D:
3080 case TGSI_TEXTURE_SHADOW2D:
3081 case TGSI_TEXTURE_RECT:
3082 case TGSI_TEXTURE_SHADOWRECT:
3083 case TGSI_TEXTURE_2D_ARRAY:
3084 case TGSI_TEXTURE_SHADOW2D_ARRAY:
3085 address[1] =
3086 lp_build_add(uint_bld, address[1],
3087 bld->immediates[off->Index][off->SwizzleY]);
3088 /* fall through */
3089 case TGSI_TEXTURE_1D:
3090 case TGSI_TEXTURE_SHADOW1D:
3091 case TGSI_TEXTURE_1D_ARRAY:
3092 case TGSI_TEXTURE_SHADOW1D_ARRAY:
3093 address[0] =
3094 lp_build_add(uint_bld, address[0],
3095 bld->immediates[off->Index][off->SwizzleX]);
3096 break;
3097 /* texture offsets do not apply to other texture targets */
3098 }
3099 }
3100 }
3101
3102 if (opcode == TGSI_OPCODE_TG4) {
3103 unsigned gather_comp = 0;
3104
3105 /* DMASK was repurposed for GATHER4. 4 components are always
3106 * returned and DMASK works like a swizzle - it selects
3107 * the component to fetch. The only valid DMASK values are
3108 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
3109 * (red,red,red,red) etc.) The ISA document doesn't mention
3110 * this.
3111 */
3112
3113 /* Get the component index from src1.x for Gather4. */
3114 if (!tgsi_is_shadow_target(target)) {
3115 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3116 LLVMValueRef comp_imm;
3117 struct tgsi_src_register src1 = inst->Src[1].Register;
3118
3119 assert(src1.File == TGSI_FILE_IMMEDIATE);
3120
3121 comp_imm = imms[src1.Index][src1.SwizzleX];
3122 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
3123 gather_comp = CLAMP(gather_comp, 0, 3);
3124 }
3125
3126 dmask = 1 << gather_comp;
3127 }
3128
3129 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
3130 samp_ptr, address, count, dmask);
3131 }
3132
3133 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3134 struct lp_build_tgsi_context *bld_base,
3135 struct lp_build_emit_data *emit_data)
3136 {
3137 struct lp_build_context *base = &bld_base->base;
3138 unsigned opcode = emit_data->inst->Instruction.Opcode;
3139 unsigned target = emit_data->inst->Texture.Texture;
3140 char intr_name[127];
3141 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
3142 bool is_shadow = tgsi_is_shadow_target(target);
3143 char type[64];
3144 const char *name = "llvm.SI.image.sample";
3145 const char *infix = "";
3146
3147 if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
3148 /* Just return the buffer size. */
3149 emit_data->output[emit_data->chan] = emit_data->args[0];
3150 return;
3151 }
3152
3153 if (target == TGSI_TEXTURE_BUFFER) {
3154 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3155 base->gallivm->builder,
3156 "llvm.SI.vs.load.input", emit_data->dst_type,
3157 emit_data->args, emit_data->arg_count,
3158 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3159 return;
3160 }
3161
3162 switch (opcode) {
3163 case TGSI_OPCODE_TXF:
3164 name = target == TGSI_TEXTURE_2D_MSAA ||
3165 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
3166 "llvm.SI.image.load" :
3167 "llvm.SI.image.load.mip";
3168 is_shadow = false;
3169 has_offset = false;
3170 break;
3171 case TGSI_OPCODE_TXQ:
3172 name = "llvm.SI.getresinfo";
3173 is_shadow = false;
3174 has_offset = false;
3175 break;
3176 case TGSI_OPCODE_LODQ:
3177 name = "llvm.SI.getlod";
3178 is_shadow = false;
3179 has_offset = false;
3180 break;
3181 case TGSI_OPCODE_TEX:
3182 case TGSI_OPCODE_TEX2:
3183 case TGSI_OPCODE_TXP:
3184 break;
3185 case TGSI_OPCODE_TXB:
3186 case TGSI_OPCODE_TXB2:
3187 infix = ".b";
3188 break;
3189 case TGSI_OPCODE_TXL:
3190 case TGSI_OPCODE_TXL2:
3191 infix = ".l";
3192 break;
3193 case TGSI_OPCODE_TXD:
3194 infix = ".d";
3195 break;
3196 case TGSI_OPCODE_TG4:
3197 name = "llvm.SI.gather4";
3198 break;
3199 default:
3200 assert(0);
3201 return;
3202 }
3203
3204 if (LLVMGetTypeKind(LLVMTypeOf(emit_data->args[0])) == LLVMVectorTypeKind)
3205 sprintf(type, ".v%ui32",
3206 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
3207 else
3208 strcpy(type, ".i32");
3209
3210 /* Add the type and suffixes .c, .o if needed. */
3211 sprintf(intr_name, "%s%s%s%s%s",
3212 name, is_shadow ? ".c" : "", infix,
3213 has_offset ? ".o" : "", type);
3214
3215 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3216 base->gallivm->builder, intr_name, emit_data->dst_type,
3217 emit_data->args, emit_data->arg_count,
3218 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3219
3220 /* Divide the number of layers by 6 to get the number of cubes. */
3221 if (opcode == TGSI_OPCODE_TXQ &&
3222 (target == TGSI_TEXTURE_CUBE_ARRAY ||
3223 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
3224 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
3225 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
3226 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
3227
3228 LLVMValueRef v4 = emit_data->output[emit_data->chan];
3229 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
3230 z = LLVMBuildSDiv(builder, z, six, "");
3231
3232 emit_data->output[emit_data->chan] =
3233 LLVMBuildInsertElement(builder, v4, z, two, "");
3234 }
3235 }
3236
3237 static void si_llvm_emit_txqs(
3238 const struct lp_build_tgsi_action *action,
3239 struct lp_build_tgsi_context *bld_base,
3240 struct lp_build_emit_data *emit_data)
3241 {
3242 struct si_shader_context *ctx = si_shader_context(bld_base);
3243 struct gallivm_state *gallivm = bld_base->base.gallivm;
3244 LLVMBuilderRef builder = gallivm->builder;
3245 LLVMValueRef res, samples;
3246 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
3247
3248 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
3249
3250
3251 /* Read the samples from the descriptor directly. */
3252 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
3253 samples = LLVMBuildExtractElement(
3254 builder, res,
3255 lp_build_const_int32(gallivm, 3), "");
3256 samples = LLVMBuildLShr(builder, samples,
3257 lp_build_const_int32(gallivm, 16), "");
3258 samples = LLVMBuildAnd(builder, samples,
3259 lp_build_const_int32(gallivm, 0xf), "");
3260 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
3261 samples, "");
3262
3263 emit_data->output[emit_data->chan] = samples;
3264 }
3265
3266 /*
3267 * SI implements derivatives using the local data store (LDS)
3268 * All writes to the LDS happen in all executing threads at
3269 * the same time. TID is the Thread ID for the current
3270 * thread and is a value between 0 and 63, representing
3271 * the thread's position in the wavefront.
3272 *
3273 * For the pixel shader threads are grouped into quads of four pixels.
3274 * The TIDs of the pixels of a quad are:
3275 *
3276 * +------+------+
3277 * |4n + 0|4n + 1|
3278 * +------+------+
3279 * |4n + 2|4n + 3|
3280 * +------+------+
3281 *
3282 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
3283 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
3284 * the current pixel's column, and masking with 0xfffffffe yields the TID
3285 * of the left pixel of the current pixel's row.
3286 *
3287 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
3288 * adding 2 yields the TID of the pixel below the top pixel.
3289 */
3290 /* masks for thread ID. */
3291 #define TID_MASK_TOP_LEFT 0xfffffffc
3292 #define TID_MASK_TOP 0xfffffffd
3293 #define TID_MASK_LEFT 0xfffffffe
3294
3295 static void si_llvm_emit_ddxy(
3296 const struct lp_build_tgsi_action *action,
3297 struct lp_build_tgsi_context *bld_base,
3298 struct lp_build_emit_data *emit_data)
3299 {
3300 struct si_shader_context *ctx = si_shader_context(bld_base);
3301 struct gallivm_state *gallivm = bld_base->base.gallivm;
3302 const struct tgsi_full_instruction *inst = emit_data->inst;
3303 unsigned opcode = inst->Instruction.Opcode;
3304 LLVMValueRef indices[2];
3305 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
3306 LLVMValueRef tl, trbl, result[4];
3307 unsigned swizzle[4];
3308 unsigned c;
3309 int idx;
3310 unsigned mask;
3311
3312 indices[0] = bld_base->uint_bld.zero;
3313 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", ctx->i32,
3314 NULL, 0, LLVMReadNoneAttribute);
3315 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
3316 indices, 2, "");
3317
3318 if (opcode == TGSI_OPCODE_DDX_FINE)
3319 mask = TID_MASK_LEFT;
3320 else if (opcode == TGSI_OPCODE_DDY_FINE)
3321 mask = TID_MASK_TOP;
3322 else
3323 mask = TID_MASK_TOP_LEFT;
3324
3325 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
3326 lp_build_const_int32(gallivm, mask), "");
3327 load_ptr0 = LLVMBuildGEP(gallivm->builder, ctx->lds,
3328 indices, 2, "");
3329
3330 /* for DDX we want to next X pixel, DDY next Y pixel. */
3331 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3332 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
3333 lp_build_const_int32(gallivm, idx), "");
3334 load_ptr1 = LLVMBuildGEP(gallivm->builder, ctx->lds,
3335 indices, 2, "");
3336
3337 for (c = 0; c < 4; ++c) {
3338 unsigned i;
3339
3340 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
3341 for (i = 0; i < c; ++i) {
3342 if (swizzle[i] == swizzle[c]) {
3343 result[c] = result[i];
3344 break;
3345 }
3346 }
3347 if (i != c)
3348 continue;
3349
3350 LLVMBuildStore(gallivm->builder,
3351 LLVMBuildBitCast(gallivm->builder,
3352 lp_build_emit_fetch(bld_base, inst, 0, c),
3353 ctx->i32, ""),
3354 store_ptr);
3355
3356 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
3357 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
3358
3359 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
3360 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
3361
3362 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
3363 }
3364
3365 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
3366 }
3367
3368 /*
3369 * this takes an I,J coordinate pair,
3370 * and works out the X and Y derivatives.
3371 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3372 */
3373 static LLVMValueRef si_llvm_emit_ddxy_interp(
3374 struct lp_build_tgsi_context *bld_base,
3375 LLVMValueRef interp_ij)
3376 {
3377 struct si_shader_context *ctx = si_shader_context(bld_base);
3378 struct gallivm_state *gallivm = bld_base->base.gallivm;
3379 LLVMValueRef indices[2];
3380 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
3381 LLVMValueRef tl, tr, bl, result[4];
3382 unsigned c;
3383
3384 indices[0] = bld_base->uint_bld.zero;
3385 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", ctx->i32,
3386 NULL, 0, LLVMReadNoneAttribute);
3387 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
3388 indices, 2, "");
3389
3390 temp = LLVMBuildAnd(gallivm->builder, indices[1],
3391 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
3392
3393 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
3394 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
3395
3396 indices[1] = temp;
3397 load_ptr_x = LLVMBuildGEP(gallivm->builder, ctx->lds,
3398 indices, 2, "");
3399
3400 indices[1] = temp2;
3401 load_ptr_y = LLVMBuildGEP(gallivm->builder, ctx->lds,
3402 indices, 2, "");
3403
3404 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
3405 lp_build_const_int32(gallivm, 1), "");
3406 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, ctx->lds,
3407 indices, 2, "");
3408
3409 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
3410 lp_build_const_int32(gallivm, 2), "");
3411 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, ctx->lds,
3412 indices, 2, "");
3413
3414 for (c = 0; c < 2; ++c) {
3415 LLVMValueRef store_val;
3416 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
3417
3418 store_val = LLVMBuildExtractElement(gallivm->builder,
3419 interp_ij, c_ll, "");
3420 LLVMBuildStore(gallivm->builder,
3421 store_val,
3422 store_ptr);
3423
3424 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
3425 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
3426
3427 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
3428 tr = LLVMBuildBitCast(gallivm->builder, tr, ctx->f32, "");
3429
3430 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
3431
3432 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
3433 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
3434
3435 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
3436 bl = LLVMBuildBitCast(gallivm->builder, bl, ctx->f32, "");
3437
3438 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
3439 }
3440
3441 return lp_build_gather_values(gallivm, result, 4);
3442 }
3443
3444 static void interp_fetch_args(
3445 struct lp_build_tgsi_context *bld_base,
3446 struct lp_build_emit_data *emit_data)
3447 {
3448 struct si_shader_context *ctx = si_shader_context(bld_base);
3449 struct gallivm_state *gallivm = bld_base->base.gallivm;
3450 const struct tgsi_full_instruction *inst = emit_data->inst;
3451
3452 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3453 /* offset is in second src, first two channels */
3454 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3455 emit_data->inst, 1,
3456 TGSI_CHAN_X);
3457 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3458 emit_data->inst, 1,
3459 TGSI_CHAN_Y);
3460 emit_data->arg_count = 2;
3461 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3462 LLVMValueRef sample_position;
3463 LLVMValueRef sample_id;
3464 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
3465
3466 /* fetch sample ID, then fetch its sample position,
3467 * and place into first two channels.
3468 */
3469 sample_id = lp_build_emit_fetch(bld_base,
3470 emit_data->inst, 1, TGSI_CHAN_X);
3471 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
3472 ctx->i32, "");
3473 sample_position = load_sample_position(&ctx->radeon_bld, sample_id);
3474
3475 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
3476 sample_position,
3477 lp_build_const_int32(gallivm, 0), "");
3478
3479 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
3480 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
3481 sample_position,
3482 lp_build_const_int32(gallivm, 1), "");
3483 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
3484 emit_data->arg_count = 2;
3485 }
3486 }
3487
3488 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3489 struct lp_build_tgsi_context *bld_base,
3490 struct lp_build_emit_data *emit_data)
3491 {
3492 struct si_shader_context *ctx = si_shader_context(bld_base);
3493 struct si_shader *shader = ctx->shader;
3494 struct gallivm_state *gallivm = bld_base->base.gallivm;
3495 LLVMValueRef interp_param;
3496 const struct tgsi_full_instruction *inst = emit_data->inst;
3497 const char *intr_name;
3498 int input_index = inst->Src[0].Register.Index;
3499 int chan;
3500 int i;
3501 LLVMValueRef attr_number;
3502 LLVMValueRef params = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
3503 int interp_param_idx;
3504 unsigned interp = shader->selector->info.input_interpolate[input_index];
3505 unsigned location;
3506
3507 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
3508
3509 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3510 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3511 location = TGSI_INTERPOLATE_LOC_CENTER;
3512 else
3513 location = TGSI_INTERPOLATE_LOC_CENTROID;
3514
3515 interp_param_idx = lookup_interp_param_index(interp, location);
3516 if (interp_param_idx == -1)
3517 return;
3518 else if (interp_param_idx)
3519 interp_param = LLVMGetParam(ctx->radeon_bld.main_fn, interp_param_idx);
3520 else
3521 interp_param = NULL;
3522
3523 attr_number = lp_build_const_int32(gallivm, input_index);
3524
3525 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3526 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3527 LLVMValueRef ij_out[2];
3528 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3529
3530 /*
3531 * take the I then J parameters, and the DDX/Y for it, and
3532 * calculate the IJ inputs for the interpolator.
3533 * temp1 = ddx * offset/sample.x + I;
3534 * interp_param.I = ddy * offset/sample.y + temp1;
3535 * temp1 = ddx * offset/sample.x + J;
3536 * interp_param.J = ddy * offset/sample.y + temp1;
3537 */
3538 for (i = 0; i < 2; i++) {
3539 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
3540 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
3541 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
3542 ddxy_out, ix_ll, "");
3543 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
3544 ddxy_out, iy_ll, "");
3545 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
3546 interp_param, ix_ll, "");
3547 LLVMValueRef temp1, temp2;
3548
3549 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
3550 ctx->f32, "");
3551
3552 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
3553
3554 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
3555
3556 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
3557
3558 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
3559
3560 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
3561 temp2, ctx->i32, "");
3562 }
3563 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
3564 }
3565
3566 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3567 for (chan = 0; chan < 2; chan++) {
3568 LLVMValueRef args[4];
3569 LLVMValueRef llvm_chan;
3570 unsigned schan;
3571
3572 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3573 llvm_chan = lp_build_const_int32(gallivm, schan);
3574
3575 args[0] = llvm_chan;
3576 args[1] = attr_number;
3577 args[2] = params;
3578 args[3] = interp_param;
3579
3580 emit_data->output[chan] =
3581 lp_build_intrinsic(gallivm->builder, intr_name,
3582 ctx->f32, args, args[3] ? 4 : 3,
3583 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3584 }
3585 }
3586
3587 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
3588 struct lp_build_emit_data *emit_data)
3589 {
3590 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3591 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
3592 unsigned stream;
3593
3594 assert(src0.File == TGSI_FILE_IMMEDIATE);
3595
3596 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
3597 return stream;
3598 }
3599
3600 /* Emit one vertex from the geometry shader */
3601 static void si_llvm_emit_vertex(
3602 const struct lp_build_tgsi_action *action,
3603 struct lp_build_tgsi_context *bld_base,
3604 struct lp_build_emit_data *emit_data)
3605 {
3606 struct si_shader_context *ctx = si_shader_context(bld_base);
3607 struct lp_build_context *uint = &bld_base->uint_bld;
3608 struct si_shader *shader = ctx->shader;
3609 struct tgsi_shader_info *info = &shader->selector->info;
3610 struct gallivm_state *gallivm = bld_base->base.gallivm;
3611 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
3612 SI_PARAM_GS2VS_OFFSET);
3613 LLVMValueRef gs_next_vertex;
3614 LLVMValueRef can_emit, kill;
3615 LLVMValueRef args[2];
3616 unsigned chan;
3617 int i;
3618 unsigned stream;
3619
3620 stream = si_llvm_get_stream(bld_base, emit_data);
3621
3622 /* Write vertex attribute values to GSVS ring */
3623 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
3624 ctx->gs_next_vertex[stream],
3625 "");
3626
3627 /* If this thread has already emitted the declared maximum number of
3628 * vertices, kill it: excessive vertex emissions are not supposed to
3629 * have any effect, and GS threads have no externally observable
3630 * effects other than emitting vertices.
3631 */
3632 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
3633 lp_build_const_int32(gallivm,
3634 shader->selector->gs_max_out_vertices), "");
3635 kill = lp_build_select(&bld_base->base, can_emit,
3636 lp_build_const_float(gallivm, 1.0f),
3637 lp_build_const_float(gallivm, -1.0f));
3638
3639 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
3640 ctx->voidt, &kill, 1, 0);
3641
3642 for (i = 0; i < info->num_outputs; i++) {
3643 LLVMValueRef *out_ptr =
3644 ctx->radeon_bld.soa.outputs[i];
3645
3646 for (chan = 0; chan < 4; chan++) {
3647 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3648 LLVMValueRef voffset =
3649 lp_build_const_int32(gallivm, (i * 4 + chan) *
3650 shader->selector->gs_max_out_vertices);
3651
3652 voffset = lp_build_add(uint, voffset, gs_next_vertex);
3653 voffset = lp_build_mul_imm(uint, voffset, 4);
3654
3655 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
3656
3657 build_tbuffer_store(ctx,
3658 ctx->gsvs_ring[stream],
3659 out_val, 1,
3660 voffset, soffset, 0,
3661 V_008F0C_BUF_DATA_FORMAT_32,
3662 V_008F0C_BUF_NUM_FORMAT_UINT,
3663 1, 0, 1, 1, 0);
3664 }
3665 }
3666 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
3667 lp_build_const_int32(gallivm, 1));
3668
3669 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
3670
3671 /* Signal vertex emission */
3672 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
3673 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3674 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3675 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
3676 }
3677
3678 /* Cut one primitive from the geometry shader */
3679 static void si_llvm_emit_primitive(
3680 const struct lp_build_tgsi_action *action,
3681 struct lp_build_tgsi_context *bld_base,
3682 struct lp_build_emit_data *emit_data)
3683 {
3684 struct si_shader_context *ctx = si_shader_context(bld_base);
3685 struct gallivm_state *gallivm = bld_base->base.gallivm;
3686 LLVMValueRef args[2];
3687 unsigned stream;
3688
3689 /* Signal primitive cut */
3690 stream = si_llvm_get_stream(bld_base, emit_data);
3691 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
3692 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3693 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3694 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
3695 }
3696
3697 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
3698 struct lp_build_tgsi_context *bld_base,
3699 struct lp_build_emit_data *emit_data)
3700 {
3701 struct si_shader_context *ctx = si_shader_context(bld_base);
3702 struct gallivm_state *gallivm = bld_base->base.gallivm;
3703
3704 lp_build_intrinsic(gallivm->builder,
3705 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
3706 : "llvm.AMDGPU.barrier.local",
3707 ctx->voidt, NULL, 0, LLVMNoUnwindAttribute);
3708 }
3709
3710 static const struct lp_build_tgsi_action tex_action = {
3711 .fetch_args = tex_fetch_args,
3712 .emit = build_tex_intrinsic,
3713 };
3714
3715 static const struct lp_build_tgsi_action interp_action = {
3716 .fetch_args = interp_fetch_args,
3717 .emit = build_interp_intrinsic,
3718 };
3719
3720 static void si_create_function(struct si_shader_context *ctx,
3721 LLVMTypeRef *returns, unsigned num_returns,
3722 LLVMTypeRef *params, unsigned num_params,
3723 int last_array_pointer, int last_sgpr)
3724 {
3725 int i;
3726
3727 radeon_llvm_create_func(&ctx->radeon_bld, returns, num_returns,
3728 params, num_params);
3729 radeon_llvm_shader_type(ctx->radeon_bld.main_fn, ctx->type);
3730 ctx->return_value = LLVMGetUndef(ctx->radeon_bld.return_type);
3731
3732 for (i = 0; i <= last_sgpr; ++i) {
3733 LLVMValueRef P = LLVMGetParam(ctx->radeon_bld.main_fn, i);
3734
3735 /* We tell llvm that array inputs are passed by value to allow Sinking pass
3736 * to move load. Inputs are constant so this is fine. */
3737 if (i <= last_array_pointer)
3738 LLVMAddAttribute(P, LLVMByValAttribute);
3739 else
3740 LLVMAddAttribute(P, LLVMInRegAttribute);
3741 }
3742 }
3743
3744 static void create_meta_data(struct si_shader_context *ctx)
3745 {
3746 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
3747 LLVMValueRef args[3];
3748
3749 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
3750 args[1] = 0;
3751 args[2] = lp_build_const_int32(gallivm, 1);
3752
3753 ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
3754 }
3755
3756 static void declare_streamout_params(struct si_shader_context *ctx,
3757 struct pipe_stream_output_info *so,
3758 LLVMTypeRef *params, LLVMTypeRef i32,
3759 unsigned *num_params)
3760 {
3761 int i;
3762
3763 /* Streamout SGPRs. */
3764 if (so->num_outputs) {
3765 params[ctx->param_streamout_config = (*num_params)++] = i32;
3766 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
3767 }
3768 /* A streamout buffer offset is loaded if the stride is non-zero. */
3769 for (i = 0; i < 4; i++) {
3770 if (!so->stride[i])
3771 continue;
3772
3773 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
3774 }
3775 }
3776
3777 static unsigned llvm_get_type_size(LLVMTypeRef type)
3778 {
3779 LLVMTypeKind kind = LLVMGetTypeKind(type);
3780
3781 switch (kind) {
3782 case LLVMIntegerTypeKind:
3783 return LLVMGetIntTypeWidth(type) / 8;
3784 case LLVMFloatTypeKind:
3785 return 4;
3786 case LLVMPointerTypeKind:
3787 return 8;
3788 case LLVMVectorTypeKind:
3789 return LLVMGetVectorSize(type) *
3790 llvm_get_type_size(LLVMGetElementType(type));
3791 default:
3792 assert(0);
3793 return 0;
3794 }
3795 }
3796
3797 static void declare_tess_lds(struct si_shader_context *ctx)
3798 {
3799 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3800 LLVMTypeRef i32 = ctx->radeon_bld.soa.bld_base.uint_bld.elem_type;
3801
3802 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
3803 unsigned vertex_data_dw_size = 32*32*4;
3804 unsigned patch_data_dw_size = 32*4;
3805 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
3806 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
3807 unsigned lds_dwords = patch_dw_size;
3808
3809 /* The actual size is computed outside of the shader to reduce
3810 * the number of shader variants. */
3811 ctx->lds =
3812 LLVMAddGlobalInAddressSpace(gallivm->module,
3813 LLVMArrayType(i32, lds_dwords),
3814 "tess_lds",
3815 LOCAL_ADDR_SPACE);
3816 }
3817
3818 static void create_function(struct si_shader_context *ctx)
3819 {
3820 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
3821 struct gallivm_state *gallivm = bld_base->base.gallivm;
3822 struct si_shader *shader = ctx->shader;
3823 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
3824 LLVMTypeRef returns[16+32*4];
3825 unsigned i, last_array_pointer, last_sgpr, num_params, num_return_sgprs;
3826 unsigned num_returns = 0;
3827
3828 v3i32 = LLVMVectorType(ctx->i32, 3);
3829
3830 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
3831 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
3832 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
3833 params[SI_PARAM_UNUSED] = LLVMPointerType(ctx->i32, CONST_ADDR_SPACE);
3834 last_array_pointer = SI_PARAM_UNUSED;
3835
3836 switch (ctx->type) {
3837 case TGSI_PROCESSOR_VERTEX:
3838 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
3839 last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
3840 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
3841 params[SI_PARAM_START_INSTANCE] = ctx->i32;
3842 num_params = SI_PARAM_START_INSTANCE+1;
3843
3844 if (shader->key.vs.as_es) {
3845 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
3846 } else if (shader->key.vs.as_ls) {
3847 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
3848 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
3849 } else {
3850 if (ctx->is_gs_copy_shader) {
3851 last_array_pointer = SI_PARAM_CONST_BUFFERS;
3852 num_params = SI_PARAM_CONST_BUFFERS+1;
3853 } else {
3854 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
3855 num_params = SI_PARAM_VS_STATE_BITS+1;
3856 }
3857
3858 /* The locations of the other parameters are assigned dynamically. */
3859 declare_streamout_params(ctx, &shader->selector->so,
3860 params, ctx->i32, &num_params);
3861 }
3862
3863 last_sgpr = num_params-1;
3864
3865 /* VGPRs */
3866 params[ctx->param_vertex_id = num_params++] = ctx->i32;
3867 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
3868 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
3869 params[ctx->param_instance_id = num_params++] = ctx->i32;
3870
3871 if (!ctx->is_monolithic &&
3872 !ctx->is_gs_copy_shader) {
3873 /* Vertex load indices. */
3874 ctx->param_vertex_index0 = num_params;
3875
3876 for (i = 0; i < shader->selector->info.num_inputs; i++)
3877 params[num_params++] = ctx->i32;
3878
3879 /* PrimitiveID output. */
3880 if (!shader->key.vs.as_es && !shader->key.vs.as_ls)
3881 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
3882 returns[num_returns++] = ctx->f32;
3883 }
3884 break;
3885
3886 case TGSI_PROCESSOR_TESS_CTRL:
3887 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
3888 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
3889 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
3890 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
3891 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
3892
3893 /* VGPRs */
3894 params[SI_PARAM_PATCH_ID] = ctx->i32;
3895 params[SI_PARAM_REL_IDS] = ctx->i32;
3896 num_params = SI_PARAM_REL_IDS+1;
3897
3898 if (!ctx->is_monolithic) {
3899 /* PARAM_TESS_FACTOR_OFFSET is after user SGPRs. */
3900 for (i = 0; i <= SI_TCS_NUM_USER_SGPR; i++)
3901 returns[num_returns++] = ctx->i32; /* SGPRs */
3902
3903 for (i = 0; i < 3; i++)
3904 returns[num_returns++] = ctx->f32; /* VGPRs */
3905 }
3906 break;
3907
3908 case TGSI_PROCESSOR_TESS_EVAL:
3909 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
3910 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
3911 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
3912
3913 if (shader->key.tes.as_es) {
3914 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
3915 } else {
3916 declare_streamout_params(ctx, &shader->selector->so,
3917 params, ctx->i32, &num_params);
3918 }
3919 last_sgpr = num_params - 1;
3920
3921 /* VGPRs */
3922 params[ctx->param_tes_u = num_params++] = ctx->f32;
3923 params[ctx->param_tes_v = num_params++] = ctx->f32;
3924 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
3925 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
3926
3927 /* PrimitiveID output. */
3928 if (!ctx->is_monolithic && !shader->key.tes.as_es)
3929 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
3930 returns[num_returns++] = ctx->f32;
3931 break;
3932
3933 case TGSI_PROCESSOR_GEOMETRY:
3934 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
3935 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
3936 last_sgpr = SI_PARAM_GS_WAVE_ID;
3937
3938 /* VGPRs */
3939 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
3940 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
3941 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
3942 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
3943 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
3944 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
3945 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
3946 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
3947 num_params = SI_PARAM_GS_INSTANCE_ID+1;
3948 break;
3949
3950 case TGSI_PROCESSOR_FRAGMENT:
3951 params[SI_PARAM_ALPHA_REF] = ctx->f32;
3952 params[SI_PARAM_PRIM_MASK] = ctx->i32;
3953 last_sgpr = SI_PARAM_PRIM_MASK;
3954 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
3955 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
3956 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
3957 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
3958 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
3959 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
3960 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
3961 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
3962 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
3963 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
3964 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
3965 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
3966 params[SI_PARAM_FRONT_FACE] = ctx->i32;
3967 params[SI_PARAM_ANCILLARY] = ctx->i32;
3968 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
3969 params[SI_PARAM_POS_FIXED_PT] = ctx->f32;
3970 num_params = SI_PARAM_POS_FIXED_PT+1;
3971
3972 if (!ctx->is_monolithic) {
3973 /* Outputs for the epilog. */
3974 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
3975 num_returns =
3976 num_return_sgprs +
3977 util_bitcount(shader->selector->info.colors_written) * 4 +
3978 shader->selector->info.writes_z +
3979 shader->selector->info.writes_stencil +
3980 shader->selector->info.writes_samplemask +
3981 1 /* SampleMaskIn */;
3982
3983 num_returns = MAX2(num_returns,
3984 num_return_sgprs +
3985 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
3986
3987 for (i = 0; i < num_return_sgprs; i++)
3988 returns[i] = ctx->i32;
3989 for (; i < num_returns; i++)
3990 returns[i] = ctx->f32;
3991 }
3992 break;
3993
3994 default:
3995 assert(0 && "unimplemented shader");
3996 return;
3997 }
3998
3999 assert(num_params <= Elements(params));
4000
4001 si_create_function(ctx, returns, num_returns, params,
4002 num_params, last_array_pointer, last_sgpr);
4003
4004 shader->num_input_sgprs = 0;
4005 shader->num_input_vgprs = 0;
4006
4007 for (i = 0; i <= last_sgpr; ++i)
4008 shader->num_input_sgprs += llvm_get_type_size(params[i]) / 4;
4009
4010 /* Unused fragment shader inputs are eliminated by the compiler,
4011 * so we don't know yet how many there will be.
4012 */
4013 if (ctx->type != TGSI_PROCESSOR_FRAGMENT)
4014 for (; i < num_params; ++i)
4015 shader->num_input_vgprs += llvm_get_type_size(params[i]) / 4;
4016
4017 if (bld_base->info &&
4018 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
4019 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
4020 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
4021 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
4022 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
4023 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
4024 ctx->lds =
4025 LLVMAddGlobalInAddressSpace(gallivm->module,
4026 LLVMArrayType(ctx->i32, 64),
4027 "ddxy_lds",
4028 LOCAL_ADDR_SPACE);
4029
4030 if ((ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
4031 ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
4032 ctx->type == TGSI_PROCESSOR_TESS_EVAL)
4033 declare_tess_lds(ctx);
4034 }
4035
4036 static void preload_constants(struct si_shader_context *ctx)
4037 {
4038 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4039 struct gallivm_state *gallivm = bld_base->base.gallivm;
4040 const struct tgsi_shader_info *info = bld_base->info;
4041 unsigned buf;
4042 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
4043
4044 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
4045 unsigned i, num_const = info->const_file_max[buf] + 1;
4046
4047 if (num_const == 0)
4048 continue;
4049
4050 /* Allocate space for the constant values */
4051 ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
4052
4053 /* Load the resource descriptor */
4054 ctx->const_buffers[buf] =
4055 build_indexed_load_const(ctx, ptr, lp_build_const_int32(gallivm, buf));
4056
4057 /* Load the constants, we rely on the code sinking to do the rest */
4058 for (i = 0; i < num_const * 4; ++i) {
4059 ctx->constants[buf][i] =
4060 buffer_load_const(gallivm->builder,
4061 ctx->const_buffers[buf],
4062 lp_build_const_int32(gallivm, i * 4),
4063 ctx->f32);
4064 }
4065 }
4066 }
4067
4068 static void preload_samplers(struct si_shader_context *ctx)
4069 {
4070 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4071 struct gallivm_state *gallivm = bld_base->base.gallivm;
4072 const struct tgsi_shader_info *info = bld_base->info;
4073 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
4074 LLVMValueRef offset;
4075
4076 if (num_samplers == 0)
4077 return;
4078
4079 /* Load the resources and samplers, we rely on the code sinking to do the rest */
4080 for (i = 0; i < num_samplers; ++i) {
4081 /* Resource */
4082 offset = lp_build_const_int32(gallivm, i);
4083 ctx->sampler_views[i] =
4084 get_sampler_desc(ctx, offset, DESC_IMAGE);
4085
4086 /* FMASK resource */
4087 if (info->is_msaa_sampler[i])
4088 ctx->fmasks[i] =
4089 get_sampler_desc(ctx, offset, DESC_FMASK);
4090 else
4091 ctx->sampler_states[i] =
4092 get_sampler_desc(ctx, offset, DESC_SAMPLER);
4093 }
4094 }
4095
4096 static void preload_streamout_buffers(struct si_shader_context *ctx)
4097 {
4098 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4099 struct gallivm_state *gallivm = bld_base->base.gallivm;
4100 unsigned i;
4101
4102 /* Streamout can only be used if the shader is compiled as VS. */
4103 if (!ctx->shader->selector->so.num_outputs ||
4104 (ctx->type == TGSI_PROCESSOR_VERTEX &&
4105 (ctx->shader->key.vs.as_es ||
4106 ctx->shader->key.vs.as_ls)) ||
4107 (ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
4108 ctx->shader->key.tes.as_es))
4109 return;
4110
4111 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
4112 SI_PARAM_RW_BUFFERS);
4113
4114 /* Load the resources, we rely on the code sinking to do the rest */
4115 for (i = 0; i < 4; ++i) {
4116 if (ctx->shader->selector->so.stride[i]) {
4117 LLVMValueRef offset = lp_build_const_int32(gallivm,
4118 SI_SO_BUF_OFFSET + i);
4119
4120 ctx->so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
4121 }
4122 }
4123 }
4124
4125 /**
4126 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4127 * for later use.
4128 */
4129 static void preload_ring_buffers(struct si_shader_context *ctx)
4130 {
4131 struct gallivm_state *gallivm =
4132 ctx->radeon_bld.soa.bld_base.base.gallivm;
4133
4134 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
4135 SI_PARAM_RW_BUFFERS);
4136
4137 if ((ctx->type == TGSI_PROCESSOR_VERTEX &&
4138 ctx->shader->key.vs.as_es) ||
4139 (ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
4140 ctx->shader->key.tes.as_es) ||
4141 ctx->type == TGSI_PROCESSOR_GEOMETRY) {
4142 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
4143
4144 ctx->esgs_ring =
4145 build_indexed_load_const(ctx, buf_ptr, offset);
4146 }
4147
4148 if (ctx->is_gs_copy_shader) {
4149 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
4150
4151 ctx->gsvs_ring[0] =
4152 build_indexed_load_const(ctx, buf_ptr, offset);
4153 }
4154 if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
4155 int i;
4156 for (i = 0; i < 4; i++) {
4157 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i);
4158
4159 ctx->gsvs_ring[i] =
4160 build_indexed_load_const(ctx, buf_ptr, offset);
4161 }
4162 }
4163 }
4164
4165 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
4166 struct si_shader_config *conf,
4167 unsigned symbol_offset)
4168 {
4169 unsigned i;
4170 const unsigned char *config =
4171 radeon_shader_binary_config_start(binary, symbol_offset);
4172
4173 /* XXX: We may be able to emit some of these values directly rather than
4174 * extracting fields to be emitted later.
4175 */
4176
4177 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
4178 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
4179 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
4180 switch (reg) {
4181 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
4182 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
4183 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
4184 case R_00B848_COMPUTE_PGM_RSRC1:
4185 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
4186 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
4187 conf->float_mode = G_00B028_FLOAT_MODE(value);
4188 conf->rsrc1 = value;
4189 break;
4190 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
4191 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
4192 break;
4193 case R_00B84C_COMPUTE_PGM_RSRC2:
4194 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
4195 conf->rsrc2 = value;
4196 break;
4197 case R_0286CC_SPI_PS_INPUT_ENA:
4198 conf->spi_ps_input_ena = value;
4199 break;
4200 case R_0286D0_SPI_PS_INPUT_ADDR:
4201 conf->spi_ps_input_addr = value;
4202 break;
4203 case R_0286E8_SPI_TMPRING_SIZE:
4204 case R_00B860_COMPUTE_TMPRING_SIZE:
4205 /* WAVESIZE is in units of 256 dwords. */
4206 conf->scratch_bytes_per_wave =
4207 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
4208 break;
4209 default:
4210 {
4211 static bool printed;
4212
4213 if (!printed) {
4214 fprintf(stderr, "Warning: LLVM emitted unknown "
4215 "config register: 0x%x\n", reg);
4216 printed = true;
4217 }
4218 }
4219 break;
4220 }
4221
4222 if (!conf->spi_ps_input_addr)
4223 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
4224 }
4225 }
4226
4227 void si_shader_apply_scratch_relocs(struct si_context *sctx,
4228 struct si_shader *shader,
4229 uint64_t scratch_va)
4230 {
4231 unsigned i;
4232 uint32_t scratch_rsrc_dword0 = scratch_va;
4233 uint32_t scratch_rsrc_dword1 =
4234 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
4235 | S_008F04_STRIDE(shader->config.scratch_bytes_per_wave / 64);
4236
4237 for (i = 0 ; i < shader->binary.reloc_count; i++) {
4238 const struct radeon_shader_reloc *reloc =
4239 &shader->binary.relocs[i];
4240 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
4241 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4242 &scratch_rsrc_dword0, 4);
4243 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4244 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4245 &scratch_rsrc_dword1, 4);
4246 }
4247 }
4248 }
4249
4250 static unsigned si_get_shader_binary_size(struct si_shader *shader)
4251 {
4252 unsigned size = shader->binary.code_size;
4253
4254 if (shader->prolog)
4255 size += shader->prolog->binary.code_size;
4256 if (shader->epilog)
4257 size += shader->epilog->binary.code_size;
4258 return size;
4259 }
4260
4261 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
4262 {
4263 const struct radeon_shader_binary *prolog =
4264 shader->prolog ? &shader->prolog->binary : NULL;
4265 const struct radeon_shader_binary *epilog =
4266 shader->epilog ? &shader->epilog->binary : NULL;
4267 const struct radeon_shader_binary *mainb = &shader->binary;
4268 unsigned bo_size = si_get_shader_binary_size(shader) +
4269 (!epilog ? mainb->rodata_size : 0);
4270 unsigned char *ptr;
4271
4272 assert(!prolog || !prolog->rodata_size);
4273 assert((!prolog && !epilog) || !mainb->rodata_size);
4274 assert(!epilog || !epilog->rodata_size);
4275
4276 r600_resource_reference(&shader->bo, NULL);
4277 shader->bo = si_resource_create_custom(&sscreen->b.b,
4278 PIPE_USAGE_IMMUTABLE,
4279 bo_size);
4280 if (!shader->bo)
4281 return -ENOMEM;
4282
4283 /* Upload. */
4284 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
4285 PIPE_TRANSFER_READ_WRITE);
4286
4287 if (prolog) {
4288 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
4289 ptr += prolog->code_size;
4290 }
4291
4292 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
4293 ptr += mainb->code_size;
4294
4295 if (epilog)
4296 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
4297 else if (mainb->rodata_size > 0)
4298 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
4299
4300 sscreen->b.ws->buffer_unmap(shader->bo->buf);
4301 return 0;
4302 }
4303
4304 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
4305 struct pipe_debug_callback *debug,
4306 const char *name)
4307 {
4308 char *line, *p;
4309 unsigned i, count;
4310
4311 if (binary->disasm_string) {
4312 fprintf(stderr, "Shader %s disassembly:\n", name);
4313 fprintf(stderr, "%s", binary->disasm_string);
4314
4315 if (debug && debug->debug_message) {
4316 /* Very long debug messages are cut off, so send the
4317 * disassembly one line at a time. This causes more
4318 * overhead, but on the plus side it simplifies
4319 * parsing of resulting logs.
4320 */
4321 pipe_debug_message(debug, SHADER_INFO,
4322 "Shader Disassembly Begin");
4323
4324 line = binary->disasm_string;
4325 while (*line) {
4326 p = strchrnul(line, '\n');
4327 count = p - line;
4328
4329 if (count) {
4330 pipe_debug_message(debug, SHADER_INFO,
4331 "%.*s", count, line);
4332 }
4333
4334 if (!*p)
4335 break;
4336 line = p + 1;
4337 }
4338
4339 pipe_debug_message(debug, SHADER_INFO,
4340 "Shader Disassembly End");
4341 }
4342 } else {
4343 fprintf(stderr, "Shader %s binary:\n", name);
4344 for (i = 0; i < binary->code_size; i += 4) {
4345 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i,
4346 binary->code[i + 3], binary->code[i + 2],
4347 binary->code[i + 1], binary->code[i]);
4348 }
4349 }
4350 }
4351
4352 static void si_shader_dump_stats(struct si_screen *sscreen,
4353 struct si_shader_config *conf,
4354 unsigned num_inputs,
4355 unsigned code_size,
4356 struct pipe_debug_callback *debug,
4357 unsigned processor)
4358 {
4359 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
4360 unsigned lds_per_wave = 0;
4361 unsigned max_simd_waves = 10;
4362
4363 /* Compute LDS usage for PS. */
4364 if (processor == TGSI_PROCESSOR_FRAGMENT) {
4365 /* The minimum usage per wave is (num_inputs * 36). The maximum
4366 * usage is (num_inputs * 36 * 16).
4367 * We can get anything in between and it varies between waves.
4368 *
4369 * Other stages don't know the size at compile time or don't
4370 * allocate LDS per wave, but instead they do it per thread group.
4371 */
4372 lds_per_wave = conf->lds_size * lds_increment +
4373 align(num_inputs * 36, lds_increment);
4374 }
4375
4376 /* Compute the per-SIMD wave counts. */
4377 if (conf->num_sgprs) {
4378 if (sscreen->b.chip_class >= VI)
4379 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
4380 else
4381 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
4382 }
4383
4384 if (conf->num_vgprs)
4385 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
4386
4387 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
4388 * that PS can use.
4389 */
4390 if (lds_per_wave)
4391 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
4392
4393 if (r600_can_dump_shader(&sscreen->b, processor)) {
4394 if (processor == TGSI_PROCESSOR_FRAGMENT) {
4395 fprintf(stderr, "*** SHADER CONFIG ***\n"
4396 "SPI_PS_INPUT_ADDR = 0x%04x\n"
4397 "SPI_PS_INPUT_ENA = 0x%04x\n",
4398 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
4399 }
4400
4401 fprintf(stderr, "*** SHADER STATS ***\n"
4402 "SGPRS: %d\n"
4403 "VGPRS: %d\n"
4404 "Code Size: %d bytes\n"
4405 "LDS: %d blocks\n"
4406 "Scratch: %d bytes per wave\n"
4407 "Max Waves: %d\n"
4408 "********************\n",
4409 conf->num_sgprs, conf->num_vgprs, code_size,
4410 conf->lds_size, conf->scratch_bytes_per_wave,
4411 max_simd_waves);
4412 }
4413
4414 pipe_debug_message(debug, SHADER_INFO,
4415 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
4416 "LDS: %d Scratch: %d Max Waves: %d",
4417 conf->num_sgprs, conf->num_vgprs, code_size,
4418 conf->lds_size, conf->scratch_bytes_per_wave,
4419 max_simd_waves);
4420 }
4421
4422 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
4423 struct pipe_debug_callback *debug, unsigned processor)
4424 {
4425 if (r600_can_dump_shader(&sscreen->b, processor) &&
4426 !(sscreen->b.debug_flags & DBG_NO_ASM)) {
4427 fprintf(stderr, "\n");
4428
4429 if (shader->prolog)
4430 si_shader_dump_disassembly(&shader->prolog->binary,
4431 debug, "prolog");
4432
4433 si_shader_dump_disassembly(&shader->binary, debug, "main");
4434
4435 if (shader->epilog)
4436 si_shader_dump_disassembly(&shader->epilog->binary,
4437 debug, "epilog");
4438 fprintf(stderr, "\n");
4439 }
4440
4441 si_shader_dump_stats(sscreen, &shader->config,
4442 shader->selector ? shader->selector->info.num_inputs : 0,
4443 si_get_shader_binary_size(shader), debug, processor);
4444 }
4445
4446 int si_compile_llvm(struct si_screen *sscreen,
4447 struct radeon_shader_binary *binary,
4448 struct si_shader_config *conf,
4449 LLVMTargetMachineRef tm,
4450 LLVMModuleRef mod,
4451 struct pipe_debug_callback *debug,
4452 unsigned processor,
4453 const char *name)
4454 {
4455 int r = 0;
4456 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
4457
4458 if (r600_can_dump_shader(&sscreen->b, processor)) {
4459 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
4460
4461 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
4462 fprintf(stderr, "%s LLVM IR:\n\n", name);
4463 LLVMDumpModule(mod);
4464 fprintf(stderr, "\n");
4465 }
4466 }
4467
4468 if (!si_replace_shader(count, binary)) {
4469 r = radeon_llvm_compile(mod, binary,
4470 r600_get_llvm_processor_name(sscreen->b.family), tm,
4471 debug);
4472 if (r)
4473 return r;
4474 }
4475
4476 si_shader_binary_read_config(binary, conf, 0);
4477
4478 /* Enable 64-bit and 16-bit denormals, because there is no performance
4479 * cost.
4480 *
4481 * If denormals are enabled, all floating-point output modifiers are
4482 * ignored.
4483 *
4484 * Don't enable denormals for 32-bit floats, because:
4485 * - Floating-point output modifiers would be ignored by the hw.
4486 * - Some opcodes don't support denormals, such as v_mad_f32. We would
4487 * have to stop using those.
4488 * - SI & CI would be very slow.
4489 */
4490 conf->float_mode |= V_00B028_FP_64_DENORMS;
4491
4492 FREE(binary->config);
4493 FREE(binary->global_symbol_offsets);
4494 binary->config = NULL;
4495 binary->global_symbol_offsets = NULL;
4496
4497 /* Some shaders can't have rodata because their binaries can be
4498 * concatenated.
4499 */
4500 if (binary->rodata_size &&
4501 (processor == TGSI_PROCESSOR_VERTEX ||
4502 processor == TGSI_PROCESSOR_TESS_CTRL ||
4503 processor == TGSI_PROCESSOR_TESS_EVAL ||
4504 processor == TGSI_PROCESSOR_FRAGMENT)) {
4505 fprintf(stderr, "radeonsi: The shader can't have rodata.");
4506 return -EINVAL;
4507 }
4508
4509 return r;
4510 }
4511
4512 /* Generate code for the hardware VS shader stage to go with a geometry shader */
4513 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
4514 struct si_shader_context *ctx,
4515 struct si_shader *gs,
4516 struct pipe_debug_callback *debug)
4517 {
4518 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4519 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4520 struct lp_build_context *uint = &bld_base->uint_bld;
4521 struct si_shader_output_values *outputs;
4522 struct tgsi_shader_info *gsinfo = &gs->selector->info;
4523 LLVMValueRef args[9];
4524 int i, r;
4525
4526 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
4527
4528 si_init_shader_ctx(ctx, sscreen, ctx->shader, ctx->tm, gsinfo);
4529 ctx->type = TGSI_PROCESSOR_VERTEX;
4530 ctx->is_gs_copy_shader = true;
4531
4532 create_meta_data(ctx);
4533 create_function(ctx);
4534 preload_streamout_buffers(ctx);
4535 preload_ring_buffers(ctx);
4536
4537 args[0] = ctx->gsvs_ring[0];
4538 args[1] = lp_build_mul_imm(uint,
4539 LLVMGetParam(ctx->radeon_bld.main_fn,
4540 ctx->param_vertex_id),
4541 4);
4542 args[3] = uint->zero;
4543 args[4] = uint->one; /* OFFEN */
4544 args[5] = uint->zero; /* IDXEN */
4545 args[6] = uint->one; /* GLC */
4546 args[7] = uint->one; /* SLC */
4547 args[8] = uint->zero; /* TFE */
4548
4549 /* Fetch vertex data from GSVS ring */
4550 for (i = 0; i < gsinfo->num_outputs; ++i) {
4551 unsigned chan;
4552
4553 outputs[i].name = gsinfo->output_semantic_name[i];
4554 outputs[i].sid = gsinfo->output_semantic_index[i];
4555
4556 for (chan = 0; chan < 4; chan++) {
4557 args[2] = lp_build_const_int32(gallivm,
4558 (i * 4 + chan) *
4559 gs->selector->gs_max_out_vertices * 16 * 4);
4560
4561 outputs[i].values[chan] =
4562 LLVMBuildBitCast(gallivm->builder,
4563 lp_build_intrinsic(gallivm->builder,
4564 "llvm.SI.buffer.load.dword.i32.i32",
4565 ctx->i32, args, 9,
4566 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
4567 ctx->f32, "");
4568 }
4569 }
4570
4571 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
4572
4573 LLVMBuildRet(gallivm->builder, ctx->return_value);
4574
4575 /* Dump LLVM IR before any optimization passes */
4576 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
4577 r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
4578 LLVMDumpModule(bld_base->base.gallivm->module);
4579
4580 radeon_llvm_finalize_module(&ctx->radeon_bld);
4581
4582 r = si_compile_llvm(sscreen, &ctx->shader->binary,
4583 &ctx->shader->config, ctx->tm,
4584 bld_base->base.gallivm->module,
4585 debug, TGSI_PROCESSOR_GEOMETRY,
4586 "GS Copy Shader");
4587 if (!r) {
4588 if (r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
4589 fprintf(stderr, "GS Copy Shader:\n");
4590 si_shader_dump(sscreen, ctx->shader, debug,
4591 TGSI_PROCESSOR_GEOMETRY);
4592 r = si_shader_binary_upload(sscreen, ctx->shader);
4593 }
4594
4595 radeon_llvm_dispose(&ctx->radeon_bld);
4596
4597 FREE(outputs);
4598 return r;
4599 }
4600
4601 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
4602 {
4603 int i;
4604
4605 fprintf(f, "SHADER KEY\n");
4606
4607 switch (shader) {
4608 case PIPE_SHADER_VERTEX:
4609 fprintf(f, " instance_divisors = {");
4610 for (i = 0; i < Elements(key->vs.prolog.instance_divisors); i++)
4611 fprintf(f, !i ? "%u" : ", %u",
4612 key->vs.prolog.instance_divisors[i]);
4613 fprintf(f, "}\n");
4614 fprintf(f, " as_es = %u\n", key->vs.as_es);
4615 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
4616 fprintf(f, " export_prim_id = %u\n", key->vs.epilog.export_prim_id);
4617 break;
4618
4619 case PIPE_SHADER_TESS_CTRL:
4620 fprintf(f, " prim_mode = %u\n", key->tcs.epilog.prim_mode);
4621 break;
4622
4623 case PIPE_SHADER_TESS_EVAL:
4624 fprintf(f, " as_es = %u\n", key->tes.as_es);
4625 fprintf(f, " export_prim_id = %u\n", key->tes.epilog.export_prim_id);
4626 break;
4627
4628 case PIPE_SHADER_GEOMETRY:
4629 break;
4630
4631 case PIPE_SHADER_FRAGMENT:
4632 fprintf(f, " prolog.color_two_side = %u\n", key->ps.prolog.color_two_side);
4633 fprintf(f, " prolog.poly_stipple = %u\n", key->ps.prolog.poly_stipple);
4634 fprintf(f, " prolog.force_persample_interp = %u\n", key->ps.prolog.force_persample_interp);
4635 fprintf(f, " epilog.spi_shader_col_format = 0x%x\n", key->ps.epilog.spi_shader_col_format);
4636 fprintf(f, " epilog.color_is_int8 = 0x%X\n", key->ps.epilog.color_is_int8);
4637 fprintf(f, " epilog.last_cbuf = %u\n", key->ps.epilog.last_cbuf);
4638 fprintf(f, " epilog.alpha_func = %u\n", key->ps.epilog.alpha_func);
4639 fprintf(f, " epilog.alpha_to_one = %u\n", key->ps.epilog.alpha_to_one);
4640 fprintf(f, " epilog.poly_line_smoothing = %u\n", key->ps.epilog.poly_line_smoothing);
4641 fprintf(f, " epilog.clamp_color = %u\n", key->ps.epilog.clamp_color);
4642 break;
4643
4644 default:
4645 assert(0);
4646 }
4647 }
4648
4649 static void si_init_shader_ctx(struct si_shader_context *ctx,
4650 struct si_screen *sscreen,
4651 struct si_shader *shader,
4652 LLVMTargetMachineRef tm,
4653 struct tgsi_shader_info *info)
4654 {
4655 struct lp_build_tgsi_context *bld_base;
4656
4657 memset(ctx, 0, sizeof(*ctx));
4658 radeon_llvm_context_init(&ctx->radeon_bld, "amdgcn--");
4659 ctx->tm = tm;
4660 ctx->screen = sscreen;
4661 if (shader && shader->selector)
4662 ctx->type = shader->selector->info.processor;
4663 else
4664 ctx->type = -1;
4665 ctx->shader = shader;
4666
4667 ctx->voidt = LLVMVoidTypeInContext(ctx->radeon_bld.gallivm.context);
4668 ctx->i1 = LLVMInt1TypeInContext(ctx->radeon_bld.gallivm.context);
4669 ctx->i8 = LLVMInt8TypeInContext(ctx->radeon_bld.gallivm.context);
4670 ctx->i32 = LLVMInt32TypeInContext(ctx->radeon_bld.gallivm.context);
4671 ctx->i64 = LLVMInt64TypeInContext(ctx->radeon_bld.gallivm.context);
4672 ctx->i128 = LLVMIntTypeInContext(ctx->radeon_bld.gallivm.context, 128);
4673 ctx->f32 = LLVMFloatTypeInContext(ctx->radeon_bld.gallivm.context);
4674 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
4675 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
4676 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
4677 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
4678 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
4679
4680 bld_base = &ctx->radeon_bld.soa.bld_base;
4681 bld_base->info = info;
4682 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
4683
4684 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
4685 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
4686 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
4687
4688 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
4689 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
4690 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
4691 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
4692 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
4693 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
4694 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
4695 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
4696 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
4697 bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
4698 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
4699 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
4700 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
4701
4702 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
4703 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
4704 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
4705 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
4706
4707 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
4708 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
4709 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
4710
4711 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
4712 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
4713 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
4714 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
4715 }
4716
4717 static int si_compile_tgsi_shader(struct si_screen *sscreen,
4718 LLVMTargetMachineRef tm,
4719 struct si_shader *shader,
4720 bool is_monolithic,
4721 struct pipe_debug_callback *debug)
4722 {
4723 struct si_shader_selector *sel = shader->selector;
4724 struct tgsi_token *tokens = sel->tokens;
4725 struct si_shader_context ctx;
4726 struct lp_build_tgsi_context *bld_base;
4727 struct tgsi_shader_info stipple_shader_info;
4728 LLVMModuleRef mod;
4729 int r = 0;
4730 bool poly_stipple = sel->type == PIPE_SHADER_FRAGMENT &&
4731 shader->key.ps.prolog.poly_stipple;
4732
4733 if (poly_stipple) {
4734 tokens = util_pstipple_create_fragment_shader(tokens, NULL,
4735 SI_POLY_STIPPLE_SAMPLER,
4736 TGSI_FILE_SYSTEM_VALUE);
4737 tgsi_scan_shader(tokens, &stipple_shader_info);
4738 }
4739
4740 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
4741 * conversion fails. */
4742 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
4743 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
4744 si_dump_shader_key(sel->type, &shader->key, stderr);
4745 tgsi_dump(tokens, 0);
4746 si_dump_streamout(&sel->so);
4747 }
4748
4749 si_init_shader_ctx(&ctx, sscreen, shader, tm,
4750 poly_stipple ? &stipple_shader_info : &sel->info);
4751 ctx.is_monolithic = is_monolithic;
4752
4753 shader->uses_instanceid = sel->info.uses_instanceid;
4754
4755 bld_base = &ctx.radeon_bld.soa.bld_base;
4756 ctx.radeon_bld.load_system_value = declare_system_value;
4757
4758 switch (ctx.type) {
4759 case TGSI_PROCESSOR_VERTEX:
4760 ctx.radeon_bld.load_input = declare_input_vs;
4761 if (shader->key.vs.as_ls)
4762 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
4763 else if (shader->key.vs.as_es)
4764 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4765 else
4766 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4767 break;
4768 case TGSI_PROCESSOR_TESS_CTRL:
4769 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
4770 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
4771 bld_base->emit_store = store_output_tcs;
4772 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
4773 break;
4774 case TGSI_PROCESSOR_TESS_EVAL:
4775 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
4776 if (shader->key.tes.as_es)
4777 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4778 else
4779 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4780 break;
4781 case TGSI_PROCESSOR_GEOMETRY:
4782 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
4783 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
4784 break;
4785 case TGSI_PROCESSOR_FRAGMENT:
4786 ctx.radeon_bld.load_input = declare_input_fs;
4787 if (is_monolithic)
4788 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
4789 else
4790 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
4791 break;
4792 default:
4793 assert(!"Unsupported shader type");
4794 return -1;
4795 }
4796
4797 create_meta_data(&ctx);
4798 create_function(&ctx);
4799 preload_constants(&ctx);
4800 preload_samplers(&ctx);
4801 preload_streamout_buffers(&ctx);
4802 preload_ring_buffers(&ctx);
4803
4804 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4805 int i;
4806 for (i = 0; i < 4; i++) {
4807 ctx.gs_next_vertex[i] =
4808 lp_build_alloca(bld_base->base.gallivm,
4809 ctx.i32, "");
4810 }
4811 }
4812
4813 if (!lp_build_tgsi_llvm(bld_base, tokens)) {
4814 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
4815 goto out;
4816 }
4817
4818 LLVMBuildRet(bld_base->base.gallivm->builder, ctx.return_value);
4819 mod = bld_base->base.gallivm->module;
4820
4821 /* Dump LLVM IR before any optimization passes */
4822 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
4823 r600_can_dump_shader(&sscreen->b, ctx.type))
4824 LLVMDumpModule(mod);
4825
4826 radeon_llvm_finalize_module(&ctx.radeon_bld);
4827
4828 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
4829 mod, debug, ctx.type, "TGSI shader");
4830 if (r) {
4831 fprintf(stderr, "LLVM failed to compile shader\n");
4832 goto out;
4833 }
4834
4835 radeon_llvm_dispose(&ctx.radeon_bld);
4836
4837 /* Calculate the number of fragment input VGPRs. */
4838 if (ctx.type == TGSI_PROCESSOR_FRAGMENT) {
4839 shader->num_input_vgprs = 0;
4840 shader->face_vgpr_index = -1;
4841
4842 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
4843 shader->num_input_vgprs += 2;
4844 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
4845 shader->num_input_vgprs += 2;
4846 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
4847 shader->num_input_vgprs += 2;
4848 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
4849 shader->num_input_vgprs += 3;
4850 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
4851 shader->num_input_vgprs += 2;
4852 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
4853 shader->num_input_vgprs += 2;
4854 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
4855 shader->num_input_vgprs += 2;
4856 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
4857 shader->num_input_vgprs += 1;
4858 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
4859 shader->num_input_vgprs += 1;
4860 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
4861 shader->num_input_vgprs += 1;
4862 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
4863 shader->num_input_vgprs += 1;
4864 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
4865 shader->num_input_vgprs += 1;
4866 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
4867 shader->face_vgpr_index = shader->num_input_vgprs;
4868 shader->num_input_vgprs += 1;
4869 }
4870 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
4871 shader->num_input_vgprs += 1;
4872 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
4873 shader->num_input_vgprs += 1;
4874 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
4875 shader->num_input_vgprs += 1;
4876 }
4877
4878 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4879 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
4880 shader->gs_copy_shader->selector = shader->selector;
4881 ctx.shader = shader->gs_copy_shader;
4882 if ((r = si_generate_gs_copy_shader(sscreen, &ctx,
4883 shader, debug))) {
4884 free(shader->gs_copy_shader);
4885 shader->gs_copy_shader = NULL;
4886 goto out;
4887 }
4888 }
4889
4890 out:
4891 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
4892 FREE(ctx.constants[i]);
4893 if (poly_stipple)
4894 tgsi_free_tokens(tokens);
4895 return r;
4896 }
4897
4898 /**
4899 * Create, compile and return a shader part (prolog or epilog).
4900 *
4901 * \param sscreen screen
4902 * \param list list of shader parts of the same category
4903 * \param key shader part key
4904 * \param tm LLVM target machine
4905 * \param debug debug callback
4906 * \param compile the callback responsible for compilation
4907 * \return non-NULL on success
4908 */
4909 static struct si_shader_part *
4910 si_get_shader_part(struct si_screen *sscreen,
4911 struct si_shader_part **list,
4912 union si_shader_part_key *key,
4913 LLVMTargetMachineRef tm,
4914 struct pipe_debug_callback *debug,
4915 bool (*compile)(struct si_screen *,
4916 LLVMTargetMachineRef,
4917 struct pipe_debug_callback *,
4918 struct si_shader_part *))
4919 {
4920 struct si_shader_part *result;
4921
4922 pipe_mutex_lock(sscreen->shader_parts_mutex);
4923
4924 /* Find existing. */
4925 for (result = *list; result; result = result->next) {
4926 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
4927 pipe_mutex_unlock(sscreen->shader_parts_mutex);
4928 return result;
4929 }
4930 }
4931
4932 /* Compile a new one. */
4933 result = CALLOC_STRUCT(si_shader_part);
4934 result->key = *key;
4935 if (!compile(sscreen, tm, debug, result)) {
4936 FREE(result);
4937 pipe_mutex_unlock(sscreen->shader_parts_mutex);
4938 return NULL;
4939 }
4940
4941 result->next = *list;
4942 *list = result;
4943 pipe_mutex_unlock(sscreen->shader_parts_mutex);
4944 return result;
4945 }
4946
4947 /**
4948 * Create a vertex shader prolog.
4949 *
4950 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
4951 * All inputs are returned unmodified. The vertex load indices are
4952 * stored after them, which will used by the API VS for fetching inputs.
4953 *
4954 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
4955 * input_v0,
4956 * input_v1,
4957 * input_v2,
4958 * input_v3,
4959 * (VertexID + BaseVertex),
4960 * (InstanceID + StartInstance),
4961 * (InstanceID / 2 + StartInstance)
4962 */
4963 static bool si_compile_vs_prolog(struct si_screen *sscreen,
4964 LLVMTargetMachineRef tm,
4965 struct pipe_debug_callback *debug,
4966 struct si_shader_part *out)
4967 {
4968 union si_shader_part_key *key = &out->key;
4969 struct si_shader shader = {};
4970 struct si_shader_context ctx;
4971 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
4972 LLVMTypeRef *params, *returns;
4973 LLVMValueRef ret, func;
4974 int last_sgpr, num_params, num_returns, i;
4975 bool status = true;
4976
4977 si_init_shader_ctx(&ctx, sscreen, &shader, tm, NULL);
4978 ctx.type = TGSI_PROCESSOR_VERTEX;
4979 ctx.param_vertex_id = key->vs_prolog.num_input_sgprs;
4980 ctx.param_instance_id = key->vs_prolog.num_input_sgprs + 3;
4981
4982 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
4983 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
4984 sizeof(LLVMTypeRef));
4985 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
4986 key->vs_prolog.last_input + 1) *
4987 sizeof(LLVMTypeRef));
4988 num_params = 0;
4989 num_returns = 0;
4990
4991 /* Declare input and output SGPRs. */
4992 num_params = 0;
4993 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
4994 params[num_params++] = ctx.i32;
4995 returns[num_returns++] = ctx.i32;
4996 }
4997 last_sgpr = num_params - 1;
4998
4999 /* 4 preloaded VGPRs (outputs must be floats) */
5000 for (i = 0; i < 4; i++) {
5001 params[num_params++] = ctx.i32;
5002 returns[num_returns++] = ctx.f32;
5003 }
5004
5005 /* Vertex load indices. */
5006 for (i = 0; i <= key->vs_prolog.last_input; i++)
5007 returns[num_returns++] = ctx.f32;
5008
5009 /* Create the function. */
5010 si_create_function(&ctx, returns, num_returns, params,
5011 num_params, -1, last_sgpr);
5012 func = ctx.radeon_bld.main_fn;
5013
5014 /* Copy inputs to outputs. This should be no-op, as the registers match,
5015 * but it will prevent the compiler from overwriting them unintentionally.
5016 */
5017 ret = ctx.return_value;
5018 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
5019 LLVMValueRef p = LLVMGetParam(func, i);
5020 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
5021 }
5022 for (i = num_params - 4; i < num_params; i++) {
5023 LLVMValueRef p = LLVMGetParam(func, i);
5024 p = LLVMBuildBitCast(gallivm->builder, p, ctx.f32, "");
5025 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
5026 }
5027
5028 /* Compute vertex load indices from instance divisors. */
5029 for (i = 0; i <= key->vs_prolog.last_input; i++) {
5030 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
5031 LLVMValueRef index;
5032
5033 if (divisor) {
5034 /* InstanceID / Divisor + StartInstance */
5035 index = get_instance_index_for_fetch(&ctx.radeon_bld,
5036 SI_SGPR_START_INSTANCE,
5037 divisor);
5038 } else {
5039 /* VertexID + BaseVertex */
5040 index = LLVMBuildAdd(gallivm->builder,
5041 LLVMGetParam(func, ctx.param_vertex_id),
5042 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
5043 }
5044
5045 index = LLVMBuildBitCast(gallivm->builder, index, ctx.f32, "");
5046 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
5047 num_params++, "");
5048 }
5049
5050 /* Compile. */
5051 LLVMBuildRet(gallivm->builder, ret);
5052 radeon_llvm_finalize_module(&ctx.radeon_bld);
5053
5054 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
5055 gallivm->module, debug, ctx.type,
5056 "Vertex Shader Prolog"))
5057 status = false;
5058
5059 radeon_llvm_dispose(&ctx.radeon_bld);
5060 return status;
5061 }
5062
5063 /**
5064 * Compile the vertex shader epilog. This is also used by the tessellation
5065 * evaluation shader compiled as VS.
5066 *
5067 * The input is PrimitiveID.
5068 *
5069 * If PrimitiveID is required by the pixel shader, export it.
5070 * Otherwise, do nothing.
5071 */
5072 static bool si_compile_vs_epilog(struct si_screen *sscreen,
5073 LLVMTargetMachineRef tm,
5074 struct pipe_debug_callback *debug,
5075 struct si_shader_part *out)
5076 {
5077 union si_shader_part_key *key = &out->key;
5078 struct si_shader_context ctx;
5079 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
5080 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
5081 LLVMTypeRef params[5];
5082 int num_params, i;
5083 bool status = true;
5084
5085 si_init_shader_ctx(&ctx, sscreen, NULL, tm, NULL);
5086 ctx.type = TGSI_PROCESSOR_VERTEX;
5087
5088 /* Declare input VGPRs. */
5089 num_params = key->vs_epilog.states.export_prim_id ?
5090 (VS_EPILOG_PRIMID_LOC + 1) : 0;
5091 assert(num_params <= ARRAY_SIZE(params));
5092
5093 for (i = 0; i < num_params; i++)
5094 params[i] = ctx.f32;
5095
5096 /* Create the function. */
5097 si_create_function(&ctx, NULL, 0, params, num_params,
5098 -1, -1);
5099
5100 /* Emit exports. */
5101 if (key->vs_epilog.states.export_prim_id) {
5102 struct lp_build_context *base = &bld_base->base;
5103 struct lp_build_context *uint = &bld_base->uint_bld;
5104 LLVMValueRef args[9];
5105
5106 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
5107 args[1] = uint->zero; /* whether the EXEC mask is valid */
5108 args[2] = uint->zero; /* DONE bit */
5109 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
5110 key->vs_epilog.prim_id_param_offset);
5111 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
5112 args[5] = LLVMGetParam(ctx.radeon_bld.main_fn,
5113 VS_EPILOG_PRIMID_LOC); /* X */
5114 args[6] = uint->undef; /* Y */
5115 args[7] = uint->undef; /* Z */
5116 args[8] = uint->undef; /* W */
5117
5118 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
5119 LLVMVoidTypeInContext(base->gallivm->context),
5120 args, 9, 0);
5121 }
5122
5123 /* Compile. */
5124 LLVMBuildRet(gallivm->builder, ctx.return_value);
5125 radeon_llvm_finalize_module(&ctx.radeon_bld);
5126
5127 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
5128 gallivm->module, debug, ctx.type,
5129 "Vertex Shader Epilog"))
5130 status = false;
5131
5132 radeon_llvm_dispose(&ctx.radeon_bld);
5133 return status;
5134 }
5135
5136 /**
5137 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
5138 */
5139 static bool si_get_vs_epilog(struct si_screen *sscreen,
5140 LLVMTargetMachineRef tm,
5141 struct si_shader *shader,
5142 struct pipe_debug_callback *debug,
5143 struct si_vs_epilog_bits *states)
5144 {
5145 union si_shader_part_key epilog_key;
5146
5147 memset(&epilog_key, 0, sizeof(epilog_key));
5148 epilog_key.vs_epilog.states = *states;
5149
5150 /* Set up the PrimitiveID output. */
5151 if (shader->key.vs.epilog.export_prim_id) {
5152 unsigned index = shader->selector->info.num_outputs;
5153 unsigned offset = shader->nr_param_exports++;
5154
5155 epilog_key.vs_epilog.prim_id_param_offset = offset;
5156 shader->vs_output_param_offset[index] = offset;
5157 }
5158
5159 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
5160 &epilog_key, tm, debug,
5161 si_compile_vs_epilog);
5162 return shader->epilog != NULL;
5163 }
5164
5165 /**
5166 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
5167 */
5168 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
5169 LLVMTargetMachineRef tm,
5170 struct si_shader *shader,
5171 struct pipe_debug_callback *debug)
5172 {
5173 struct tgsi_shader_info *info = &shader->selector->info;
5174 union si_shader_part_key prolog_key;
5175 unsigned i;
5176
5177 /* Get the prolog. */
5178 memset(&prolog_key, 0, sizeof(prolog_key));
5179 prolog_key.vs_prolog.states = shader->key.vs.prolog;
5180 prolog_key.vs_prolog.num_input_sgprs = shader->num_input_sgprs;
5181 prolog_key.vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
5182
5183 /* The prolog is a no-op if there are no inputs. */
5184 if (info->num_inputs) {
5185 shader->prolog =
5186 si_get_shader_part(sscreen, &sscreen->vs_prologs,
5187 &prolog_key, tm, debug,
5188 si_compile_vs_prolog);
5189 if (!shader->prolog)
5190 return false;
5191 }
5192
5193 /* Get the epilog. */
5194 if (!shader->key.vs.as_es && !shader->key.vs.as_ls &&
5195 !si_get_vs_epilog(sscreen, tm, shader, debug,
5196 &shader->key.vs.epilog))
5197 return false;
5198
5199 /* Set the instanceID flag. */
5200 for (i = 0; i < info->num_inputs; i++)
5201 if (prolog_key.vs_prolog.states.instance_divisors[i])
5202 shader->uses_instanceid = true;
5203
5204 return true;
5205 }
5206
5207 /**
5208 * Select and compile (or reuse) TES parts (epilog).
5209 */
5210 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
5211 LLVMTargetMachineRef tm,
5212 struct si_shader *shader,
5213 struct pipe_debug_callback *debug)
5214 {
5215 if (shader->key.tes.as_es)
5216 return true;
5217
5218 /* TES compiled as VS. */
5219 return si_get_vs_epilog(sscreen, tm, shader, debug,
5220 &shader->key.tes.epilog);
5221 }
5222
5223 /**
5224 * Compile the TCS epilog. This writes tesselation factors to memory based on
5225 * the output primitive type of the tesselator (determined by TES).
5226 */
5227 static bool si_compile_tcs_epilog(struct si_screen *sscreen,
5228 LLVMTargetMachineRef tm,
5229 struct pipe_debug_callback *debug,
5230 struct si_shader_part *out)
5231 {
5232 union si_shader_part_key *key = &out->key;
5233 struct si_shader shader = {};
5234 struct si_shader_context ctx;
5235 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
5236 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
5237 LLVMTypeRef params[16];
5238 LLVMValueRef func;
5239 int last_array_pointer, last_sgpr, num_params;
5240 bool status = true;
5241
5242 si_init_shader_ctx(&ctx, sscreen, &shader, tm, NULL);
5243 ctx.type = TGSI_PROCESSOR_TESS_CTRL;
5244 shader.key.tcs.epilog = key->tcs_epilog.states;
5245
5246 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
5247 params[SI_PARAM_RW_BUFFERS] = const_array(ctx.v16i8, SI_NUM_RW_BUFFERS);
5248 last_array_pointer = SI_PARAM_RW_BUFFERS;
5249 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
5250 params[SI_PARAM_SAMPLERS] = ctx.i64;
5251 params[SI_PARAM_UNUSED] = ctx.i64;
5252 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx.i32;
5253 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx.i32;
5254 params[SI_PARAM_TCS_IN_LAYOUT] = ctx.i32;
5255 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx.i32;
5256 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5257 num_params = last_sgpr + 1;
5258
5259 params[num_params++] = ctx.i32; /* patch index within the wave (REL_PATCH_ID) */
5260 params[num_params++] = ctx.i32; /* invocation ID within the patch */
5261 params[num_params++] = ctx.i32; /* LDS offset where tess factors should be loaded from */
5262
5263 /* Create the function. */
5264 si_create_function(&ctx, NULL, 0, params, num_params,
5265 last_array_pointer, last_sgpr);
5266 declare_tess_lds(&ctx);
5267 func = ctx.radeon_bld.main_fn;
5268
5269 si_write_tess_factors(bld_base,
5270 LLVMGetParam(func, last_sgpr + 1),
5271 LLVMGetParam(func, last_sgpr + 2),
5272 LLVMGetParam(func, last_sgpr + 3));
5273
5274 /* Compile. */
5275 LLVMBuildRet(gallivm->builder, ctx.return_value);
5276 radeon_llvm_finalize_module(&ctx.radeon_bld);
5277
5278 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
5279 gallivm->module, debug, ctx.type,
5280 "Tessellation Control Shader Epilog"))
5281 status = false;
5282
5283 radeon_llvm_dispose(&ctx.radeon_bld);
5284 return status;
5285 }
5286
5287 /**
5288 * Select and compile (or reuse) TCS parts (epilog).
5289 */
5290 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
5291 LLVMTargetMachineRef tm,
5292 struct si_shader *shader,
5293 struct pipe_debug_callback *debug)
5294 {
5295 union si_shader_part_key epilog_key;
5296
5297 /* Get the epilog. */
5298 memset(&epilog_key, 0, sizeof(epilog_key));
5299 epilog_key.tcs_epilog.states = shader->key.tcs.epilog;
5300
5301 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
5302 &epilog_key, tm, debug,
5303 si_compile_tcs_epilog);
5304 return shader->epilog != NULL;
5305 }
5306
5307 /**
5308 * Compile the pixel shader epilog. This handles everything that must be
5309 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
5310 */
5311 static bool si_compile_ps_epilog(struct si_screen *sscreen,
5312 LLVMTargetMachineRef tm,
5313 struct pipe_debug_callback *debug,
5314 struct si_shader_part *out)
5315 {
5316 union si_shader_part_key *key = &out->key;
5317 struct si_shader shader = {};
5318 struct si_shader_context ctx;
5319 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
5320 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
5321 LLVMTypeRef params[16+8*4+3];
5322 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5323 int last_array_pointer, last_sgpr, num_params, i;
5324 bool status = true;
5325
5326 si_init_shader_ctx(&ctx, sscreen, &shader, tm, NULL);
5327 ctx.type = TGSI_PROCESSOR_FRAGMENT;
5328 shader.key.ps.epilog = key->ps_epilog.states;
5329
5330 /* Declare input SGPRs. */
5331 params[SI_PARAM_RW_BUFFERS] = ctx.i64;
5332 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
5333 params[SI_PARAM_SAMPLERS] = ctx.i64;
5334 params[SI_PARAM_UNUSED] = ctx.i64;
5335 params[SI_PARAM_ALPHA_REF] = ctx.f32;
5336 last_array_pointer = -1;
5337 last_sgpr = SI_PARAM_ALPHA_REF;
5338
5339 /* Declare input VGPRs. */
5340 num_params = (last_sgpr + 1) +
5341 util_bitcount(key->ps_epilog.colors_written) * 4 +
5342 key->ps_epilog.writes_z +
5343 key->ps_epilog.writes_stencil +
5344 key->ps_epilog.writes_samplemask;
5345
5346 num_params = MAX2(num_params,
5347 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5348
5349 assert(num_params <= ARRAY_SIZE(params));
5350
5351 for (i = last_sgpr + 1; i < num_params; i++)
5352 params[i] = ctx.f32;
5353
5354 /* Create the function. */
5355 si_create_function(&ctx, NULL, 0, params, num_params,
5356 last_array_pointer, last_sgpr);
5357 /* Disable elimination of unused inputs. */
5358 radeon_llvm_add_attribute(ctx.radeon_bld.main_fn,
5359 "InitialPSInputAddr", 0xffffff);
5360
5361 /* Process colors. */
5362 unsigned vgpr = last_sgpr + 1;
5363 unsigned colors_written = key->ps_epilog.colors_written;
5364 int last_color_export = -1;
5365
5366 /* Find the last color export. */
5367 if (!key->ps_epilog.writes_z &&
5368 !key->ps_epilog.writes_stencil &&
5369 !key->ps_epilog.writes_samplemask) {
5370 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
5371
5372 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
5373 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
5374 /* Just set this if any of the colorbuffers are enabled. */
5375 if (spi_format &
5376 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
5377 last_color_export = 0;
5378 } else {
5379 for (i = 0; i < 8; i++)
5380 if (colors_written & (1 << i) &&
5381 (spi_format >> (i * 4)) & 0xf)
5382 last_color_export = i;
5383 }
5384 }
5385
5386 while (colors_written) {
5387 LLVMValueRef color[4];
5388 int mrt = u_bit_scan(&colors_written);
5389
5390 for (i = 0; i < 4; i++)
5391 color[i] = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
5392
5393 si_export_mrt_color(bld_base, color, mrt,
5394 num_params - 1,
5395 mrt == last_color_export);
5396 }
5397
5398 /* Process depth, stencil, samplemask. */
5399 if (key->ps_epilog.writes_z)
5400 depth = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
5401 if (key->ps_epilog.writes_stencil)
5402 stencil = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
5403 if (key->ps_epilog.writes_samplemask)
5404 samplemask = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
5405
5406 if (depth || stencil || samplemask)
5407 si_export_mrt_z(bld_base, depth, stencil, samplemask);
5408 else if (last_color_export == -1)
5409 si_export_null(bld_base);
5410
5411 /* Compile. */
5412 LLVMBuildRetVoid(gallivm->builder);
5413 radeon_llvm_finalize_module(&ctx.radeon_bld);
5414
5415 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
5416 gallivm->module, debug, ctx.type,
5417 "Fragment Shader Epilog"))
5418 status = false;
5419
5420 radeon_llvm_dispose(&ctx.radeon_bld);
5421 return status;
5422 }
5423
5424 /**
5425 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
5426 */
5427 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
5428 LLVMTargetMachineRef tm,
5429 struct si_shader *shader,
5430 struct pipe_debug_callback *debug)
5431 {
5432 struct tgsi_shader_info *info = &shader->selector->info;
5433 union si_shader_part_key epilog_key;
5434
5435 /* Get the epilog. */
5436 memset(&epilog_key, 0, sizeof(epilog_key));
5437 epilog_key.ps_epilog.colors_written = info->colors_written;
5438 epilog_key.ps_epilog.writes_z = info->writes_z;
5439 epilog_key.ps_epilog.writes_stencil = info->writes_stencil;
5440 epilog_key.ps_epilog.writes_samplemask = info->writes_samplemask;
5441 epilog_key.ps_epilog.states = shader->key.ps.epilog;
5442
5443 shader->epilog =
5444 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
5445 &epilog_key, tm, debug,
5446 si_compile_ps_epilog);
5447 if (!shader->epilog)
5448 return false;
5449
5450 /* The sample mask input is always enabled, because the API shader always
5451 * passes it through to the epilog. Disable it here if it's unused.
5452 */
5453 if (!shader->key.ps.epilog.poly_line_smoothing &&
5454 !shader->selector->info.reads_samplemask)
5455 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
5456
5457 return true;
5458 }
5459
5460 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
5461 struct si_shader *shader,
5462 struct pipe_debug_callback *debug)
5463 {
5464 int r;
5465
5466 /* Compile TGSI. */
5467 r = si_compile_tgsi_shader(sscreen, tm, shader,
5468 sscreen->use_monolithic_shaders, debug);
5469 if (r)
5470 return r;
5471
5472 if (!sscreen->use_monolithic_shaders) {
5473 switch (shader->selector->type) {
5474 case PIPE_SHADER_VERTEX:
5475 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
5476 return -1;
5477 break;
5478 case PIPE_SHADER_TESS_CTRL:
5479 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
5480 return -1;
5481 break;
5482 case PIPE_SHADER_TESS_EVAL:
5483 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
5484 return -1;
5485 break;
5486 case PIPE_SHADER_FRAGMENT:
5487 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
5488 return -1;
5489
5490 /* Make sure we have at least as many VGPRs as there
5491 * are allocated inputs.
5492 */
5493 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
5494 shader->num_input_vgprs);
5495 break;
5496 }
5497
5498 /* Update SGPR and VGPR counts. */
5499 if (shader->prolog) {
5500 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
5501 shader->prolog->config.num_sgprs);
5502 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
5503 shader->prolog->config.num_vgprs);
5504 }
5505 if (shader->epilog) {
5506 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
5507 shader->epilog->config.num_sgprs);
5508 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
5509 shader->epilog->config.num_vgprs);
5510 }
5511 }
5512
5513 si_shader_dump(sscreen, shader, debug, shader->selector->info.processor);
5514
5515 /* Upload. */
5516 r = si_shader_binary_upload(sscreen, shader);
5517 if (r) {
5518 fprintf(stderr, "LLVM failed to upload shader\n");
5519 return r;
5520 }
5521
5522 return 0;
5523 }
5524
5525 void si_shader_destroy(struct si_shader *shader)
5526 {
5527 if (shader->gs_copy_shader) {
5528 si_shader_destroy(shader->gs_copy_shader);
5529 FREE(shader->gs_copy_shader);
5530 }
5531
5532 if (shader->scratch_bo)
5533 r600_resource_reference(&shader->scratch_bo, NULL);
5534
5535 r600_resource_reference(&shader->bo, NULL);
5536
5537 radeon_shader_binary_clean(&shader->binary);
5538 }