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radeonsi: Set PIPE_SHADER_CAP_MAX_SHADER_IMAGES
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_build.h"
44 #include "tgsi/tgsi_util.h"
45 #include "tgsi/tgsi_dump.h"
46
47 #include "si_pipe.h"
48 #include "si_shader.h"
49 #include "sid.h"
50
51 #include <errno.h>
52
53 static const char *scratch_rsrc_dword0_symbol =
54 "SCRATCH_RSRC_DWORD0";
55
56 static const char *scratch_rsrc_dword1_symbol =
57 "SCRATCH_RSRC_DWORD1";
58
59 struct si_shader_output_values
60 {
61 LLVMValueRef values[4];
62 unsigned name;
63 unsigned sid;
64 };
65
66 struct si_shader_context
67 {
68 struct radeon_llvm_context radeon_bld;
69 struct si_shader *shader;
70 struct si_screen *screen;
71
72 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
73 bool is_gs_copy_shader;
74
75 /* Whether to generate the optimized shader variant compiled as a whole
76 * (without a prolog and epilog)
77 */
78 bool is_monolithic;
79
80 int param_streamout_config;
81 int param_streamout_write_index;
82 int param_streamout_offset[4];
83 int param_vertex_id;
84 int param_rel_auto_id;
85 int param_vs_prim_id;
86 int param_instance_id;
87 int param_vertex_index0;
88 int param_tes_u;
89 int param_tes_v;
90 int param_tes_rel_patch_id;
91 int param_tes_patch_id;
92 int param_es2gs_offset;
93
94 LLVMTargetMachineRef tm;
95
96 LLVMValueRef const_md;
97 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
98 LLVMValueRef lds;
99 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
100 LLVMValueRef sampler_views[SI_NUM_SAMPLERS];
101 LLVMValueRef sampler_states[SI_NUM_SAMPLERS];
102 LLVMValueRef fmasks[SI_NUM_USER_SAMPLERS];
103 LLVMValueRef images[SI_NUM_IMAGES];
104 LLVMValueRef so_buffers[4];
105 LLVMValueRef esgs_ring;
106 LLVMValueRef gsvs_ring[4];
107 LLVMValueRef gs_next_vertex[4];
108 LLVMValueRef return_value;
109
110 LLVMTypeRef voidt;
111 LLVMTypeRef i1;
112 LLVMTypeRef i8;
113 LLVMTypeRef i32;
114 LLVMTypeRef i64;
115 LLVMTypeRef i128;
116 LLVMTypeRef f32;
117 LLVMTypeRef v16i8;
118 LLVMTypeRef v2i32;
119 LLVMTypeRef v4i32;
120 LLVMTypeRef v4f32;
121 LLVMTypeRef v8i32;
122 };
123
124 static struct si_shader_context *si_shader_context(
125 struct lp_build_tgsi_context *bld_base)
126 {
127 return (struct si_shader_context *)bld_base;
128 }
129
130 static void si_init_shader_ctx(struct si_shader_context *ctx,
131 struct si_screen *sscreen,
132 struct si_shader *shader,
133 LLVMTargetMachineRef tm);
134
135 /* Ideally pass the sample mask input to the PS epilog as v13, which
136 * is its usual location, so that the shader doesn't have to add v_mov.
137 */
138 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
139
140 /* The VS location of the PrimitiveID input is the same in the epilog,
141 * so that the main shader part doesn't have to move it.
142 */
143 #define VS_EPILOG_PRIMID_LOC 2
144
145 #define PERSPECTIVE_BASE 0
146 #define LINEAR_BASE 9
147
148 #define SAMPLE_OFFSET 0
149 #define CENTER_OFFSET 2
150 #define CENTROID_OFSET 4
151
152 #define USE_SGPR_MAX_SUFFIX_LEN 5
153 #define CONST_ADDR_SPACE 2
154 #define LOCAL_ADDR_SPACE 3
155 #define USER_SGPR_ADDR_SPACE 8
156
157
158 #define SENDMSG_GS 2
159 #define SENDMSG_GS_DONE 3
160
161 #define SENDMSG_GS_OP_NOP (0 << 4)
162 #define SENDMSG_GS_OP_CUT (1 << 4)
163 #define SENDMSG_GS_OP_EMIT (2 << 4)
164 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
165
166 /**
167 * Returns a unique index for a semantic name and index. The index must be
168 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
169 * calculated.
170 */
171 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
172 {
173 switch (semantic_name) {
174 case TGSI_SEMANTIC_POSITION:
175 return 0;
176 case TGSI_SEMANTIC_PSIZE:
177 return 1;
178 case TGSI_SEMANTIC_CLIPDIST:
179 assert(index <= 1);
180 return 2 + index;
181 case TGSI_SEMANTIC_GENERIC:
182 if (index <= 63-4)
183 return 4 + index;
184 else
185 /* same explanation as in the default statement,
186 * the only user hitting this is st/nine.
187 */
188 return 0;
189
190 /* patch indices are completely separate and thus start from 0 */
191 case TGSI_SEMANTIC_TESSOUTER:
192 return 0;
193 case TGSI_SEMANTIC_TESSINNER:
194 return 1;
195 case TGSI_SEMANTIC_PATCH:
196 return 2 + index;
197
198 default:
199 /* Don't fail here. The result of this function is only used
200 * for LS, TCS, TES, and GS, where legacy GL semantics can't
201 * occur, but this function is called for all vertex shaders
202 * before it's known whether LS will be compiled or not.
203 */
204 return 0;
205 }
206 }
207
208 /**
209 * Get the value of a shader input parameter and extract a bitfield.
210 */
211 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
212 unsigned param, unsigned rshift,
213 unsigned bitwidth)
214 {
215 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
216 LLVMValueRef value = LLVMGetParam(ctx->radeon_bld.main_fn,
217 param);
218
219 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
220 value = bitcast(&ctx->radeon_bld.soa.bld_base,
221 TGSI_TYPE_UNSIGNED, value);
222
223 if (rshift)
224 value = LLVMBuildLShr(gallivm->builder, value,
225 lp_build_const_int32(gallivm, rshift), "");
226
227 if (rshift + bitwidth < 32) {
228 unsigned mask = (1 << bitwidth) - 1;
229 value = LLVMBuildAnd(gallivm->builder, value,
230 lp_build_const_int32(gallivm, mask), "");
231 }
232
233 return value;
234 }
235
236 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
237 {
238 switch (ctx->type) {
239 case TGSI_PROCESSOR_TESS_CTRL:
240 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
241
242 case TGSI_PROCESSOR_TESS_EVAL:
243 return LLVMGetParam(ctx->radeon_bld.main_fn,
244 ctx->param_tes_rel_patch_id);
245
246 default:
247 assert(0);
248 return NULL;
249 }
250 }
251
252 /* Tessellation shaders pass outputs to the next shader using LDS.
253 *
254 * LS outputs = TCS inputs
255 * TCS outputs = TES inputs
256 *
257 * The LDS layout is:
258 * - TCS inputs for patch 0
259 * - TCS inputs for patch 1
260 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
261 * - ...
262 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
263 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
264 * - TCS outputs for patch 1
265 * - Per-patch TCS outputs for patch 1
266 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
267 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
268 * - ...
269 *
270 * All three shaders VS(LS), TCS, TES share the same LDS space.
271 */
272
273 static LLVMValueRef
274 get_tcs_in_patch_stride(struct si_shader_context *ctx)
275 {
276 if (ctx->type == TGSI_PROCESSOR_VERTEX)
277 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
278 else if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
279 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
280 else {
281 assert(0);
282 return NULL;
283 }
284 }
285
286 static LLVMValueRef
287 get_tcs_out_patch_stride(struct si_shader_context *ctx)
288 {
289 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
290 }
291
292 static LLVMValueRef
293 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
294 {
295 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
296 unpack_param(ctx,
297 SI_PARAM_TCS_OUT_OFFSETS,
298 0, 16),
299 4);
300 }
301
302 static LLVMValueRef
303 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
304 {
305 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
306 unpack_param(ctx,
307 SI_PARAM_TCS_OUT_OFFSETS,
308 16, 16),
309 4);
310 }
311
312 static LLVMValueRef
313 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
314 {
315 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
316 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
317 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
318
319 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
320 }
321
322 static LLVMValueRef
323 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
324 {
325 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
326 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
327 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
328 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
329
330 return LLVMBuildAdd(gallivm->builder, patch0_offset,
331 LLVMBuildMul(gallivm->builder, patch_stride,
332 rel_patch_id, ""),
333 "");
334 }
335
336 static LLVMValueRef
337 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
338 {
339 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
340 LLVMValueRef patch0_patch_data_offset =
341 get_tcs_out_patch0_patch_data_offset(ctx);
342 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
343 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
344
345 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
346 LLVMBuildMul(gallivm->builder, patch_stride,
347 rel_patch_id, ""),
348 "");
349 }
350
351 static void build_indexed_store(struct si_shader_context *ctx,
352 LLVMValueRef base_ptr, LLVMValueRef index,
353 LLVMValueRef value)
354 {
355 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
356 struct gallivm_state *gallivm = bld_base->base.gallivm;
357 LLVMValueRef indices[2], pointer;
358
359 indices[0] = bld_base->uint_bld.zero;
360 indices[1] = index;
361
362 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
363 LLVMBuildStore(gallivm->builder, value, pointer);
364 }
365
366 /**
367 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
368 * It's equivalent to doing a load from &base_ptr[index].
369 *
370 * \param base_ptr Where the array starts.
371 * \param index The element index into the array.
372 */
373 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
374 LLVMValueRef base_ptr, LLVMValueRef index)
375 {
376 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
377 struct gallivm_state *gallivm = bld_base->base.gallivm;
378 LLVMValueRef indices[2], pointer;
379
380 indices[0] = bld_base->uint_bld.zero;
381 indices[1] = index;
382
383 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
384 return LLVMBuildLoad(gallivm->builder, pointer, "");
385 }
386
387 /**
388 * Do a load from &base_ptr[index], but also add a flag that it's loading
389 * a constant.
390 */
391 static LLVMValueRef build_indexed_load_const(
392 struct si_shader_context *ctx,
393 LLVMValueRef base_ptr, LLVMValueRef index)
394 {
395 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index);
396 LLVMSetMetadata(result, 1, ctx->const_md);
397 return result;
398 }
399
400 static LLVMValueRef get_instance_index_for_fetch(
401 struct radeon_llvm_context *radeon_bld,
402 unsigned param_start_instance, unsigned divisor)
403 {
404 struct si_shader_context *ctx =
405 si_shader_context(&radeon_bld->soa.bld_base);
406 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
407
408 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
409 ctx->param_instance_id);
410
411 /* The division must be done before START_INSTANCE is added. */
412 if (divisor > 1)
413 result = LLVMBuildUDiv(gallivm->builder, result,
414 lp_build_const_int32(gallivm, divisor), "");
415
416 return LLVMBuildAdd(gallivm->builder, result,
417 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
418 }
419
420 static void declare_input_vs(
421 struct radeon_llvm_context *radeon_bld,
422 unsigned input_index,
423 const struct tgsi_full_declaration *decl)
424 {
425 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
426 struct gallivm_state *gallivm = base->gallivm;
427 struct si_shader_context *ctx =
428 si_shader_context(&radeon_bld->soa.bld_base);
429 unsigned divisor =
430 ctx->shader->key.vs.prolog.instance_divisors[input_index];
431
432 unsigned chan;
433
434 LLVMValueRef t_list_ptr;
435 LLVMValueRef t_offset;
436 LLVMValueRef t_list;
437 LLVMValueRef attribute_offset;
438 LLVMValueRef buffer_index;
439 LLVMValueRef args[3];
440 LLVMValueRef input;
441
442 /* Load the T list */
443 t_list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
444
445 t_offset = lp_build_const_int32(gallivm, input_index);
446
447 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
448
449 /* Build the attribute offset */
450 attribute_offset = lp_build_const_int32(gallivm, 0);
451
452 if (!ctx->is_monolithic) {
453 buffer_index = LLVMGetParam(radeon_bld->main_fn,
454 ctx->param_vertex_index0 +
455 input_index);
456 } else if (divisor) {
457 /* Build index from instance ID, start instance and divisor */
458 ctx->shader->info.uses_instanceid = true;
459 buffer_index = get_instance_index_for_fetch(&ctx->radeon_bld,
460 SI_PARAM_START_INSTANCE,
461 divisor);
462 } else {
463 /* Load the buffer index for vertices. */
464 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
465 ctx->param_vertex_id);
466 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
467 SI_PARAM_BASE_VERTEX);
468 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
469 }
470
471 args[0] = t_list;
472 args[1] = attribute_offset;
473 args[2] = buffer_index;
474 input = lp_build_intrinsic(gallivm->builder,
475 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
476 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
477
478 /* Break up the vec4 into individual components */
479 for (chan = 0; chan < 4; chan++) {
480 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
481 /* XXX: Use a helper function for this. There is one in
482 * tgsi_llvm.c. */
483 ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
484 LLVMBuildExtractElement(gallivm->builder,
485 input, llvm_chan, "");
486 }
487 }
488
489 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
490 unsigned swizzle)
491 {
492 struct si_shader_context *ctx = si_shader_context(bld_base);
493
494 if (swizzle > 0)
495 return bld_base->uint_bld.zero;
496
497 switch (ctx->type) {
498 case TGSI_PROCESSOR_VERTEX:
499 return LLVMGetParam(ctx->radeon_bld.main_fn,
500 ctx->param_vs_prim_id);
501 case TGSI_PROCESSOR_TESS_CTRL:
502 return LLVMGetParam(ctx->radeon_bld.main_fn,
503 SI_PARAM_PATCH_ID);
504 case TGSI_PROCESSOR_TESS_EVAL:
505 return LLVMGetParam(ctx->radeon_bld.main_fn,
506 ctx->param_tes_patch_id);
507 case TGSI_PROCESSOR_GEOMETRY:
508 return LLVMGetParam(ctx->radeon_bld.main_fn,
509 SI_PARAM_PRIMITIVE_ID);
510 default:
511 assert(0);
512 return bld_base->uint_bld.zero;
513 }
514 }
515
516 /**
517 * Return the value of tgsi_ind_register for indexing.
518 * This is the indirect index with the constant offset added to it.
519 */
520 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
521 const struct tgsi_ind_register *ind,
522 int rel_index)
523 {
524 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
525 LLVMValueRef result;
526
527 result = ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
528 result = LLVMBuildLoad(gallivm->builder, result, "");
529 result = LLVMBuildAdd(gallivm->builder, result,
530 lp_build_const_int32(gallivm, rel_index), "");
531 return result;
532 }
533
534 /**
535 * Calculate a dword address given an input or output register and a stride.
536 */
537 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
538 const struct tgsi_full_dst_register *dst,
539 const struct tgsi_full_src_register *src,
540 LLVMValueRef vertex_dw_stride,
541 LLVMValueRef base_addr)
542 {
543 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
544 struct tgsi_shader_info *info = &ctx->shader->selector->info;
545 ubyte *name, *index, *array_first;
546 int first, param;
547 struct tgsi_full_dst_register reg;
548
549 /* Set the register description. The address computation is the same
550 * for sources and destinations. */
551 if (src) {
552 reg.Register.File = src->Register.File;
553 reg.Register.Index = src->Register.Index;
554 reg.Register.Indirect = src->Register.Indirect;
555 reg.Register.Dimension = src->Register.Dimension;
556 reg.Indirect = src->Indirect;
557 reg.Dimension = src->Dimension;
558 reg.DimIndirect = src->DimIndirect;
559 } else
560 reg = *dst;
561
562 /* If the register is 2-dimensional (e.g. an array of vertices
563 * in a primitive), calculate the base address of the vertex. */
564 if (reg.Register.Dimension) {
565 LLVMValueRef index;
566
567 if (reg.Dimension.Indirect)
568 index = get_indirect_index(ctx, &reg.DimIndirect,
569 reg.Dimension.Index);
570 else
571 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
572
573 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
574 LLVMBuildMul(gallivm->builder, index,
575 vertex_dw_stride, ""), "");
576 }
577
578 /* Get information about the register. */
579 if (reg.Register.File == TGSI_FILE_INPUT) {
580 name = info->input_semantic_name;
581 index = info->input_semantic_index;
582 array_first = info->input_array_first;
583 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
584 name = info->output_semantic_name;
585 index = info->output_semantic_index;
586 array_first = info->output_array_first;
587 } else {
588 assert(0);
589 return NULL;
590 }
591
592 if (reg.Register.Indirect) {
593 /* Add the relative address of the element. */
594 LLVMValueRef ind_index;
595
596 if (reg.Indirect.ArrayID)
597 first = array_first[reg.Indirect.ArrayID];
598 else
599 first = reg.Register.Index;
600
601 ind_index = get_indirect_index(ctx, &reg.Indirect,
602 reg.Register.Index - first);
603
604 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
605 LLVMBuildMul(gallivm->builder, ind_index,
606 lp_build_const_int32(gallivm, 4), ""), "");
607
608 param = si_shader_io_get_unique_index(name[first], index[first]);
609 } else {
610 param = si_shader_io_get_unique_index(name[reg.Register.Index],
611 index[reg.Register.Index]);
612 }
613
614 /* Add the base address of the element. */
615 return LLVMBuildAdd(gallivm->builder, base_addr,
616 lp_build_const_int32(gallivm, param * 4), "");
617 }
618
619 /**
620 * Load from LDS.
621 *
622 * \param type output value type
623 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
624 * \param dw_addr address in dwords
625 */
626 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
627 enum tgsi_opcode_type type, unsigned swizzle,
628 LLVMValueRef dw_addr)
629 {
630 struct si_shader_context *ctx = si_shader_context(bld_base);
631 struct gallivm_state *gallivm = bld_base->base.gallivm;
632 LLVMValueRef value;
633
634 if (swizzle == ~0) {
635 LLVMValueRef values[TGSI_NUM_CHANNELS];
636
637 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
638 values[chan] = lds_load(bld_base, type, chan, dw_addr);
639
640 return lp_build_gather_values(bld_base->base.gallivm, values,
641 TGSI_NUM_CHANNELS);
642 }
643
644 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
645 lp_build_const_int32(gallivm, swizzle));
646
647 value = build_indexed_load(ctx, ctx->lds, dw_addr);
648 if (type == TGSI_TYPE_DOUBLE) {
649 LLVMValueRef value2;
650 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
651 lp_build_const_int32(gallivm, swizzle + 1));
652 value2 = build_indexed_load(ctx, ctx->lds, dw_addr);
653 return radeon_llvm_emit_fetch_double(bld_base, value, value2);
654 }
655
656 return LLVMBuildBitCast(gallivm->builder, value,
657 tgsi2llvmtype(bld_base, type), "");
658 }
659
660 /**
661 * Store to LDS.
662 *
663 * \param swizzle offset (typically 0..3)
664 * \param dw_addr address in dwords
665 * \param value value to store
666 */
667 static void lds_store(struct lp_build_tgsi_context *bld_base,
668 unsigned swizzle, LLVMValueRef dw_addr,
669 LLVMValueRef value)
670 {
671 struct si_shader_context *ctx = si_shader_context(bld_base);
672 struct gallivm_state *gallivm = bld_base->base.gallivm;
673
674 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
675 lp_build_const_int32(gallivm, swizzle));
676
677 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
678 build_indexed_store(ctx, ctx->lds,
679 dw_addr, value);
680 }
681
682 static LLVMValueRef fetch_input_tcs(
683 struct lp_build_tgsi_context *bld_base,
684 const struct tgsi_full_src_register *reg,
685 enum tgsi_opcode_type type, unsigned swizzle)
686 {
687 struct si_shader_context *ctx = si_shader_context(bld_base);
688 LLVMValueRef dw_addr, stride;
689
690 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
691 dw_addr = get_tcs_in_current_patch_offset(ctx);
692 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
693
694 return lds_load(bld_base, type, swizzle, dw_addr);
695 }
696
697 static LLVMValueRef fetch_output_tcs(
698 struct lp_build_tgsi_context *bld_base,
699 const struct tgsi_full_src_register *reg,
700 enum tgsi_opcode_type type, unsigned swizzle)
701 {
702 struct si_shader_context *ctx = si_shader_context(bld_base);
703 LLVMValueRef dw_addr, stride;
704
705 if (reg->Register.Dimension) {
706 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
707 dw_addr = get_tcs_out_current_patch_offset(ctx);
708 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
709 } else {
710 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
711 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
712 }
713
714 return lds_load(bld_base, type, swizzle, dw_addr);
715 }
716
717 static LLVMValueRef fetch_input_tes(
718 struct lp_build_tgsi_context *bld_base,
719 const struct tgsi_full_src_register *reg,
720 enum tgsi_opcode_type type, unsigned swizzle)
721 {
722 struct si_shader_context *ctx = si_shader_context(bld_base);
723 LLVMValueRef dw_addr, stride;
724
725 if (reg->Register.Dimension) {
726 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
727 dw_addr = get_tcs_out_current_patch_offset(ctx);
728 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
729 } else {
730 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
731 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
732 }
733
734 return lds_load(bld_base, type, swizzle, dw_addr);
735 }
736
737 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
738 const struct tgsi_full_instruction *inst,
739 const struct tgsi_opcode_info *info,
740 LLVMValueRef dst[4])
741 {
742 struct si_shader_context *ctx = si_shader_context(bld_base);
743 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
744 unsigned chan_index;
745 LLVMValueRef dw_addr, stride;
746
747 /* Only handle per-patch and per-vertex outputs here.
748 * Vectors will be lowered to scalars and this function will be called again.
749 */
750 if (reg->Register.File != TGSI_FILE_OUTPUT ||
751 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
752 radeon_llvm_emit_store(bld_base, inst, info, dst);
753 return;
754 }
755
756 if (reg->Register.Dimension) {
757 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
758 dw_addr = get_tcs_out_current_patch_offset(ctx);
759 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
760 } else {
761 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
762 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
763 }
764
765 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
766 LLVMValueRef value = dst[chan_index];
767
768 if (inst->Instruction.Saturate)
769 value = radeon_llvm_saturate(bld_base, value);
770
771 lds_store(bld_base, chan_index, dw_addr, value);
772 }
773 }
774
775 static LLVMValueRef fetch_input_gs(
776 struct lp_build_tgsi_context *bld_base,
777 const struct tgsi_full_src_register *reg,
778 enum tgsi_opcode_type type,
779 unsigned swizzle)
780 {
781 struct lp_build_context *base = &bld_base->base;
782 struct si_shader_context *ctx = si_shader_context(bld_base);
783 struct si_shader *shader = ctx->shader;
784 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
785 struct gallivm_state *gallivm = base->gallivm;
786 LLVMValueRef vtx_offset;
787 LLVMValueRef args[9];
788 unsigned vtx_offset_param;
789 struct tgsi_shader_info *info = &shader->selector->info;
790 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
791 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
792 unsigned param;
793 LLVMValueRef value;
794
795 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
796 return get_primitive_id(bld_base, swizzle);
797
798 if (!reg->Register.Dimension)
799 return NULL;
800
801 if (swizzle == ~0) {
802 LLVMValueRef values[TGSI_NUM_CHANNELS];
803 unsigned chan;
804 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
805 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
806 }
807 return lp_build_gather_values(bld_base->base.gallivm, values,
808 TGSI_NUM_CHANNELS);
809 }
810
811 /* Get the vertex offset parameter */
812 vtx_offset_param = reg->Dimension.Index;
813 if (vtx_offset_param < 2) {
814 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
815 } else {
816 assert(vtx_offset_param < 6);
817 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
818 }
819 vtx_offset = lp_build_mul_imm(uint,
820 LLVMGetParam(ctx->radeon_bld.main_fn,
821 vtx_offset_param),
822 4);
823
824 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
825 args[0] = ctx->esgs_ring;
826 args[1] = vtx_offset;
827 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
828 args[3] = uint->zero;
829 args[4] = uint->one; /* OFFEN */
830 args[5] = uint->zero; /* IDXEN */
831 args[6] = uint->one; /* GLC */
832 args[7] = uint->zero; /* SLC */
833 args[8] = uint->zero; /* TFE */
834
835 value = lp_build_intrinsic(gallivm->builder,
836 "llvm.SI.buffer.load.dword.i32.i32",
837 ctx->i32, args, 9,
838 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
839 if (type == TGSI_TYPE_DOUBLE) {
840 LLVMValueRef value2;
841 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
842 value2 = lp_build_intrinsic(gallivm->builder,
843 "llvm.SI.buffer.load.dword.i32.i32",
844 ctx->i32, args, 9,
845 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
846 return radeon_llvm_emit_fetch_double(bld_base,
847 value, value2);
848 }
849 return LLVMBuildBitCast(gallivm->builder,
850 value,
851 tgsi2llvmtype(bld_base, type), "");
852 }
853
854 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
855 {
856 switch (interpolate) {
857 case TGSI_INTERPOLATE_CONSTANT:
858 return 0;
859
860 case TGSI_INTERPOLATE_LINEAR:
861 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
862 return SI_PARAM_LINEAR_SAMPLE;
863 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
864 return SI_PARAM_LINEAR_CENTROID;
865 else
866 return SI_PARAM_LINEAR_CENTER;
867 break;
868 case TGSI_INTERPOLATE_COLOR:
869 case TGSI_INTERPOLATE_PERSPECTIVE:
870 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
871 return SI_PARAM_PERSP_SAMPLE;
872 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
873 return SI_PARAM_PERSP_CENTROID;
874 else
875 return SI_PARAM_PERSP_CENTER;
876 break;
877 default:
878 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
879 return -1;
880 }
881 }
882
883 /* This shouldn't be used by explicit INTERP opcodes. */
884 static unsigned select_interp_param(struct si_shader_context *ctx,
885 unsigned param)
886 {
887 if (!ctx->shader->key.ps.prolog.force_persample_interp ||
888 !ctx->is_monolithic)
889 return param;
890
891 /* If the shader doesn't use center/centroid, just return the parameter.
892 *
893 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
894 * switch between center/centroid and sample without shader changes.
895 */
896 switch (param) {
897 case SI_PARAM_PERSP_CENTROID:
898 case SI_PARAM_PERSP_CENTER:
899 return SI_PARAM_PERSP_SAMPLE;
900
901 case SI_PARAM_LINEAR_CENTROID:
902 case SI_PARAM_LINEAR_CENTER:
903 return SI_PARAM_LINEAR_SAMPLE;
904
905 default:
906 return param;
907 }
908 }
909
910 /**
911 * Interpolate a fragment shader input.
912 *
913 * @param ctx context
914 * @param input_index index of the input in hardware
915 * @param semantic_name TGSI_SEMANTIC_*
916 * @param semantic_index semantic index
917 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
918 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
919 * @param interp_param interpolation weights (i,j)
920 * @param prim_mask SI_PARAM_PRIM_MASK
921 * @param face SI_PARAM_FRONT_FACE
922 * @param result the return value (4 components)
923 */
924 static void interp_fs_input(struct si_shader_context *ctx,
925 unsigned input_index,
926 unsigned semantic_name,
927 unsigned semantic_index,
928 unsigned num_interp_inputs,
929 unsigned colors_read_mask,
930 LLVMValueRef interp_param,
931 LLVMValueRef prim_mask,
932 LLVMValueRef face,
933 LLVMValueRef result[4])
934 {
935 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
936 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
937 struct gallivm_state *gallivm = base->gallivm;
938 const char *intr_name;
939 LLVMValueRef attr_number;
940
941 unsigned chan;
942
943 attr_number = lp_build_const_int32(gallivm, input_index);
944
945 /* fs.constant returns the param from the middle vertex, so it's not
946 * really useful for flat shading. It's meant to be used for custom
947 * interpolation (but the intrinsic can't fetch from the other two
948 * vertices).
949 *
950 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
951 * to do the right thing. The only reason we use fs.constant is that
952 * fs.interp cannot be used on integers, because they can be equal
953 * to NaN.
954 */
955 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
956
957 if (semantic_name == TGSI_SEMANTIC_COLOR &&
958 ctx->shader->key.ps.prolog.color_two_side) {
959 LLVMValueRef args[4];
960 LLVMValueRef is_face_positive;
961 LLVMValueRef back_attr_number;
962
963 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
964 * otherwise it's at offset "num_inputs".
965 */
966 unsigned back_attr_offset = num_interp_inputs;
967 if (semantic_index == 1 && colors_read_mask & 0xf)
968 back_attr_offset += 1;
969
970 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
971
972 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
973 face, uint->zero, "");
974
975 args[2] = prim_mask;
976 args[3] = interp_param;
977 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
978 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
979 LLVMValueRef front, back;
980
981 args[0] = llvm_chan;
982 args[1] = attr_number;
983 front = lp_build_intrinsic(gallivm->builder, intr_name,
984 ctx->f32, args, args[3] ? 4 : 3,
985 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
986
987 args[1] = back_attr_number;
988 back = lp_build_intrinsic(gallivm->builder, intr_name,
989 ctx->f32, args, args[3] ? 4 : 3,
990 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
991
992 result[chan] = LLVMBuildSelect(gallivm->builder,
993 is_face_positive,
994 front,
995 back,
996 "");
997 }
998 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
999 LLVMValueRef args[4];
1000
1001 args[0] = uint->zero;
1002 args[1] = attr_number;
1003 args[2] = prim_mask;
1004 args[3] = interp_param;
1005 result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
1006 ctx->f32, args, args[3] ? 4 : 3,
1007 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1008 result[1] =
1009 result[2] = lp_build_const_float(gallivm, 0.0f);
1010 result[3] = lp_build_const_float(gallivm, 1.0f);
1011 } else {
1012 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1013 LLVMValueRef args[4];
1014 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1015
1016 args[0] = llvm_chan;
1017 args[1] = attr_number;
1018 args[2] = prim_mask;
1019 args[3] = interp_param;
1020 result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
1021 ctx->f32, args, args[3] ? 4 : 3,
1022 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1023 }
1024 }
1025 }
1026
1027 static void declare_input_fs(
1028 struct radeon_llvm_context *radeon_bld,
1029 unsigned input_index,
1030 const struct tgsi_full_declaration *decl)
1031 {
1032 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
1033 struct si_shader_context *ctx =
1034 si_shader_context(&radeon_bld->soa.bld_base);
1035 struct si_shader *shader = ctx->shader;
1036 LLVMValueRef main_fn = radeon_bld->main_fn;
1037 LLVMValueRef interp_param = NULL;
1038 int interp_param_idx;
1039
1040 /* Get colors from input VGPRs (set by the prolog). */
1041 if (!ctx->is_monolithic &&
1042 decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1043 unsigned i = decl->Semantic.Index;
1044 unsigned colors_read = shader->selector->info.colors_read;
1045 unsigned mask = colors_read >> (i * 4);
1046 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1047 (i ? util_bitcount(colors_read & 0xf) : 0);
1048
1049 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
1050 mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1051 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
1052 mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1053 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
1054 mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1055 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
1056 mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1057 return;
1058 }
1059
1060 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1061 decl->Interp.Location);
1062 if (interp_param_idx == -1)
1063 return;
1064 else if (interp_param_idx) {
1065 interp_param_idx = select_interp_param(ctx,
1066 interp_param_idx);
1067 interp_param = LLVMGetParam(main_fn, interp_param_idx);
1068 }
1069
1070 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1071 decl->Semantic.Index, shader->selector->info.num_inputs,
1072 shader->selector->info.colors_read, interp_param,
1073 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1074 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1075 &radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)]);
1076 }
1077
1078 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1079 {
1080 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1081 SI_PARAM_ANCILLARY, 8, 4);
1082 }
1083
1084 /**
1085 * Load a dword from a constant buffer.
1086 */
1087 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1088 LLVMValueRef offset, LLVMTypeRef return_type)
1089 {
1090 LLVMValueRef args[2] = {resource, offset};
1091
1092 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1093 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1094 }
1095
1096 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1097 {
1098 struct si_shader_context *ctx =
1099 si_shader_context(&radeon_bld->soa.bld_base);
1100 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1101 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1102 LLVMBuilderRef builder = gallivm->builder;
1103 LLVMValueRef desc = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1104 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
1105 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1106
1107 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1108 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1109 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1110
1111 LLVMValueRef pos[4] = {
1112 buffer_load_const(builder, resource, offset0, ctx->f32),
1113 buffer_load_const(builder, resource, offset1, ctx->f32),
1114 lp_build_const_float(gallivm, 0),
1115 lp_build_const_float(gallivm, 0)
1116 };
1117
1118 return lp_build_gather_values(gallivm, pos, 4);
1119 }
1120
1121 static void declare_system_value(
1122 struct radeon_llvm_context *radeon_bld,
1123 unsigned index,
1124 const struct tgsi_full_declaration *decl)
1125 {
1126 struct si_shader_context *ctx =
1127 si_shader_context(&radeon_bld->soa.bld_base);
1128 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1129 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1130 LLVMValueRef value = 0;
1131
1132 switch (decl->Semantic.Name) {
1133 case TGSI_SEMANTIC_INSTANCEID:
1134 value = LLVMGetParam(radeon_bld->main_fn,
1135 ctx->param_instance_id);
1136 break;
1137
1138 case TGSI_SEMANTIC_VERTEXID:
1139 value = LLVMBuildAdd(gallivm->builder,
1140 LLVMGetParam(radeon_bld->main_fn,
1141 ctx->param_vertex_id),
1142 LLVMGetParam(radeon_bld->main_fn,
1143 SI_PARAM_BASE_VERTEX), "");
1144 break;
1145
1146 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1147 value = LLVMGetParam(radeon_bld->main_fn,
1148 ctx->param_vertex_id);
1149 break;
1150
1151 case TGSI_SEMANTIC_BASEVERTEX:
1152 value = LLVMGetParam(radeon_bld->main_fn,
1153 SI_PARAM_BASE_VERTEX);
1154 break;
1155
1156 case TGSI_SEMANTIC_INVOCATIONID:
1157 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
1158 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1159 else if (ctx->type == TGSI_PROCESSOR_GEOMETRY)
1160 value = LLVMGetParam(radeon_bld->main_fn,
1161 SI_PARAM_GS_INSTANCE_ID);
1162 else
1163 assert(!"INVOCATIONID not implemented");
1164 break;
1165
1166 case TGSI_SEMANTIC_POSITION:
1167 {
1168 LLVMValueRef pos[4] = {
1169 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1170 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1171 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1172 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1173 LLVMGetParam(radeon_bld->main_fn,
1174 SI_PARAM_POS_W_FLOAT)),
1175 };
1176 value = lp_build_gather_values(gallivm, pos, 4);
1177 break;
1178 }
1179
1180 case TGSI_SEMANTIC_FACE:
1181 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1182 break;
1183
1184 case TGSI_SEMANTIC_SAMPLEID:
1185 value = get_sample_id(radeon_bld);
1186 break;
1187
1188 case TGSI_SEMANTIC_SAMPLEPOS: {
1189 LLVMValueRef pos[4] = {
1190 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1191 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1192 lp_build_const_float(gallivm, 0),
1193 lp_build_const_float(gallivm, 0)
1194 };
1195 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1196 TGSI_OPCODE_FRC, pos[0]);
1197 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1198 TGSI_OPCODE_FRC, pos[1]);
1199 value = lp_build_gather_values(gallivm, pos, 4);
1200 break;
1201 }
1202
1203 case TGSI_SEMANTIC_SAMPLEMASK:
1204 /* This can only occur with the OpenGL Core profile, which
1205 * doesn't support smoothing.
1206 */
1207 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1208 break;
1209
1210 case TGSI_SEMANTIC_TESSCOORD:
1211 {
1212 LLVMValueRef coord[4] = {
1213 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1214 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1215 bld->zero,
1216 bld->zero
1217 };
1218
1219 /* For triangles, the vector should be (u, v, 1-u-v). */
1220 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1221 PIPE_PRIM_TRIANGLES)
1222 coord[2] = lp_build_sub(bld, bld->one,
1223 lp_build_add(bld, coord[0], coord[1]));
1224
1225 value = lp_build_gather_values(gallivm, coord, 4);
1226 break;
1227 }
1228
1229 case TGSI_SEMANTIC_VERTICESIN:
1230 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1231 break;
1232
1233 case TGSI_SEMANTIC_TESSINNER:
1234 case TGSI_SEMANTIC_TESSOUTER:
1235 {
1236 LLVMValueRef dw_addr;
1237 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1238
1239 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1240 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1241 lp_build_const_int32(gallivm, param * 4), "");
1242
1243 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1244 ~0, dw_addr);
1245 break;
1246 }
1247
1248 case TGSI_SEMANTIC_PRIMID:
1249 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1250 break;
1251
1252 default:
1253 assert(!"unknown system value");
1254 return;
1255 }
1256
1257 radeon_bld->system_values[index] = value;
1258 }
1259
1260 static LLVMValueRef fetch_constant(
1261 struct lp_build_tgsi_context *bld_base,
1262 const struct tgsi_full_src_register *reg,
1263 enum tgsi_opcode_type type,
1264 unsigned swizzle)
1265 {
1266 struct si_shader_context *ctx = si_shader_context(bld_base);
1267 struct lp_build_context *base = &bld_base->base;
1268 const struct tgsi_ind_register *ireg = &reg->Indirect;
1269 unsigned buf, idx;
1270
1271 LLVMValueRef addr, bufp;
1272 LLVMValueRef result;
1273
1274 if (swizzle == LP_CHAN_ALL) {
1275 unsigned chan;
1276 LLVMValueRef values[4];
1277 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1278 values[chan] = fetch_constant(bld_base, reg, type, chan);
1279
1280 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1281 }
1282
1283 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1284 idx = reg->Register.Index * 4 + swizzle;
1285
1286 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1287 if (type != TGSI_TYPE_DOUBLE)
1288 return bitcast(bld_base, type, ctx->constants[buf][idx]);
1289 else {
1290 return radeon_llvm_emit_fetch_double(bld_base,
1291 ctx->constants[buf][idx],
1292 ctx->constants[buf][idx + 1]);
1293 }
1294 }
1295
1296 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1297 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1298 LLVMValueRef index;
1299 index = get_indirect_index(ctx, &reg->DimIndirect,
1300 reg->Dimension.Index);
1301 bufp = build_indexed_load_const(ctx, ptr, index);
1302 } else
1303 bufp = ctx->const_buffers[buf];
1304
1305 addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1306 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1307 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1308 addr = lp_build_add(&bld_base->uint_bld, addr,
1309 lp_build_const_int32(base->gallivm, idx * 4));
1310
1311 result = buffer_load_const(base->gallivm->builder, bufp,
1312 addr, ctx->f32);
1313
1314 if (type != TGSI_TYPE_DOUBLE)
1315 result = bitcast(bld_base, type, result);
1316 else {
1317 LLVMValueRef addr2, result2;
1318 addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1319 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1320 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1321 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1322 lp_build_const_int32(base->gallivm, idx * 4));
1323
1324 result2 = buffer_load_const(base->gallivm->builder, ctx->const_buffers[buf],
1325 addr2, ctx->f32);
1326
1327 result = radeon_llvm_emit_fetch_double(bld_base,
1328 result, result2);
1329 }
1330 return result;
1331 }
1332
1333 /* Upper 16 bits must be zero. */
1334 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1335 LLVMValueRef val[2])
1336 {
1337 return LLVMBuildOr(gallivm->builder, val[0],
1338 LLVMBuildShl(gallivm->builder, val[1],
1339 lp_build_const_int32(gallivm, 16),
1340 ""), "");
1341 }
1342
1343 /* Upper 16 bits are ignored and will be dropped. */
1344 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1345 LLVMValueRef val[2])
1346 {
1347 LLVMValueRef v[2] = {
1348 LLVMBuildAnd(gallivm->builder, val[0],
1349 lp_build_const_int32(gallivm, 0xffff), ""),
1350 val[1],
1351 };
1352 return si_llvm_pack_two_int16(gallivm, v);
1353 }
1354
1355 /* Initialize arguments for the shader export intrinsic */
1356 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1357 LLVMValueRef *values,
1358 unsigned target,
1359 LLVMValueRef *args)
1360 {
1361 struct si_shader_context *ctx = si_shader_context(bld_base);
1362 struct lp_build_context *uint =
1363 &ctx->radeon_bld.soa.bld_base.uint_bld;
1364 struct lp_build_context *base = &bld_base->base;
1365 struct gallivm_state *gallivm = base->gallivm;
1366 LLVMBuilderRef builder = base->gallivm->builder;
1367 LLVMValueRef val[4];
1368 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1369 unsigned chan;
1370 bool is_int8;
1371
1372 /* Default is 0xf. Adjusted below depending on the format. */
1373 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1374
1375 /* Specify whether the EXEC mask represents the valid mask */
1376 args[1] = uint->zero;
1377
1378 /* Specify whether this is the last export */
1379 args[2] = uint->zero;
1380
1381 /* Specify the target we are exporting */
1382 args[3] = lp_build_const_int32(base->gallivm, target);
1383
1384 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
1385 const union si_shader_key *key = &ctx->shader->key;
1386 unsigned col_formats = key->ps.epilog.spi_shader_col_format;
1387 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1388
1389 assert(cbuf >= 0 && cbuf < 8);
1390 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1391 is_int8 = (key->ps.epilog.color_is_int8 >> cbuf) & 0x1;
1392 }
1393
1394 args[4] = uint->zero; /* COMPR flag */
1395 args[5] = base->undef;
1396 args[6] = base->undef;
1397 args[7] = base->undef;
1398 args[8] = base->undef;
1399
1400 switch (spi_shader_col_format) {
1401 case V_028714_SPI_SHADER_ZERO:
1402 args[0] = uint->zero; /* writemask */
1403 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
1404 break;
1405
1406 case V_028714_SPI_SHADER_32_R:
1407 args[0] = uint->one; /* writemask */
1408 args[5] = values[0];
1409 break;
1410
1411 case V_028714_SPI_SHADER_32_GR:
1412 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
1413 args[5] = values[0];
1414 args[6] = values[1];
1415 break;
1416
1417 case V_028714_SPI_SHADER_32_AR:
1418 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
1419 args[5] = values[0];
1420 args[8] = values[3];
1421 break;
1422
1423 case V_028714_SPI_SHADER_FP16_ABGR:
1424 args[4] = uint->one; /* COMPR flag */
1425
1426 for (chan = 0; chan < 2; chan++) {
1427 LLVMValueRef pack_args[2] = {
1428 values[2 * chan],
1429 values[2 * chan + 1]
1430 };
1431 LLVMValueRef packed;
1432
1433 packed = lp_build_intrinsic(base->gallivm->builder,
1434 "llvm.SI.packf16",
1435 ctx->i32, pack_args, 2,
1436 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1437 args[chan + 5] =
1438 LLVMBuildBitCast(base->gallivm->builder,
1439 packed, ctx->f32, "");
1440 }
1441 break;
1442
1443 case V_028714_SPI_SHADER_UNORM16_ABGR:
1444 for (chan = 0; chan < 4; chan++) {
1445 val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
1446 val[chan] = LLVMBuildFMul(builder, val[chan],
1447 lp_build_const_float(gallivm, 65535), "");
1448 val[chan] = LLVMBuildFAdd(builder, val[chan],
1449 lp_build_const_float(gallivm, 0.5), "");
1450 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1451 ctx->i32, "");
1452 }
1453
1454 args[4] = uint->one; /* COMPR flag */
1455 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1456 si_llvm_pack_two_int16(gallivm, val));
1457 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1458 si_llvm_pack_two_int16(gallivm, val+2));
1459 break;
1460
1461 case V_028714_SPI_SHADER_SNORM16_ABGR:
1462 for (chan = 0; chan < 4; chan++) {
1463 /* Clamp between [-1, 1]. */
1464 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1465 values[chan],
1466 lp_build_const_float(gallivm, 1));
1467 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1468 val[chan],
1469 lp_build_const_float(gallivm, -1));
1470 /* Convert to a signed integer in [-32767, 32767]. */
1471 val[chan] = LLVMBuildFMul(builder, val[chan],
1472 lp_build_const_float(gallivm, 32767), "");
1473 /* If positive, add 0.5, else add -0.5. */
1474 val[chan] = LLVMBuildFAdd(builder, val[chan],
1475 LLVMBuildSelect(builder,
1476 LLVMBuildFCmp(builder, LLVMRealOGE,
1477 val[chan], base->zero, ""),
1478 lp_build_const_float(gallivm, 0.5),
1479 lp_build_const_float(gallivm, -0.5), ""), "");
1480 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
1481 }
1482
1483 args[4] = uint->one; /* COMPR flag */
1484 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1485 si_llvm_pack_two_int32_as_int16(gallivm, val));
1486 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1487 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1488 break;
1489
1490 case V_028714_SPI_SHADER_UINT16_ABGR: {
1491 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1492 255 : 65535);
1493 /* Clamp. */
1494 for (chan = 0; chan < 4; chan++) {
1495 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1496 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1497 val[chan], max);
1498 }
1499
1500 args[4] = uint->one; /* COMPR flag */
1501 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1502 si_llvm_pack_two_int16(gallivm, val));
1503 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1504 si_llvm_pack_two_int16(gallivm, val+2));
1505 break;
1506 }
1507
1508 case V_028714_SPI_SHADER_SINT16_ABGR: {
1509 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1510 127 : 32767);
1511 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
1512 -128 : -32768);
1513 /* Clamp. */
1514 for (chan = 0; chan < 4; chan++) {
1515 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1516 val[chan] = lp_build_emit_llvm_binary(bld_base,
1517 TGSI_OPCODE_IMIN,
1518 val[chan], max);
1519 val[chan] = lp_build_emit_llvm_binary(bld_base,
1520 TGSI_OPCODE_IMAX,
1521 val[chan], min);
1522 }
1523
1524 args[4] = uint->one; /* COMPR flag */
1525 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1526 si_llvm_pack_two_int32_as_int16(gallivm, val));
1527 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1528 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1529 break;
1530 }
1531
1532 case V_028714_SPI_SHADER_32_ABGR:
1533 memcpy(&args[5], values, sizeof(values[0]) * 4);
1534 break;
1535 }
1536 }
1537
1538 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1539 LLVMValueRef alpha)
1540 {
1541 struct si_shader_context *ctx = si_shader_context(bld_base);
1542 struct gallivm_state *gallivm = bld_base->base.gallivm;
1543
1544 if (ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
1545 LLVMValueRef alpha_ref = LLVMGetParam(ctx->radeon_bld.main_fn,
1546 SI_PARAM_ALPHA_REF);
1547
1548 LLVMValueRef alpha_pass =
1549 lp_build_cmp(&bld_base->base,
1550 ctx->shader->key.ps.epilog.alpha_func,
1551 alpha, alpha_ref);
1552 LLVMValueRef arg =
1553 lp_build_select(&bld_base->base,
1554 alpha_pass,
1555 lp_build_const_float(gallivm, 1.0f),
1556 lp_build_const_float(gallivm, -1.0f));
1557
1558 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
1559 ctx->voidt, &arg, 1, 0);
1560 } else {
1561 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
1562 ctx->voidt, NULL, 0, 0);
1563 }
1564 }
1565
1566 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1567 LLVMValueRef alpha,
1568 unsigned samplemask_param)
1569 {
1570 struct si_shader_context *ctx = si_shader_context(bld_base);
1571 struct gallivm_state *gallivm = bld_base->base.gallivm;
1572 LLVMValueRef coverage;
1573
1574 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1575 coverage = LLVMGetParam(ctx->radeon_bld.main_fn,
1576 samplemask_param);
1577 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1578
1579 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1580 ctx->i32,
1581 &coverage, 1, LLVMReadNoneAttribute);
1582
1583 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1584 ctx->f32, "");
1585
1586 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1587 lp_build_const_float(gallivm,
1588 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1589
1590 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1591 }
1592
1593 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
1594 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1595 {
1596 struct si_shader_context *ctx = si_shader_context(bld_base);
1597 struct lp_build_context *base = &bld_base->base;
1598 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1599 unsigned reg_index;
1600 unsigned chan;
1601 unsigned const_chan;
1602 LLVMValueRef base_elt;
1603 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1604 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
1605 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
1606
1607 for (reg_index = 0; reg_index < 2; reg_index ++) {
1608 LLVMValueRef *args = pos[2 + reg_index];
1609
1610 args[5] =
1611 args[6] =
1612 args[7] =
1613 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1614
1615 /* Compute dot products of position and user clip plane vectors */
1616 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1617 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1618 args[1] = lp_build_const_int32(base->gallivm,
1619 ((reg_index * 4 + chan) * 4 +
1620 const_chan) * 4);
1621 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1622 args[1], ctx->f32);
1623 args[5 + chan] =
1624 lp_build_add(base, args[5 + chan],
1625 lp_build_mul(base, base_elt,
1626 out_elts[const_chan]));
1627 }
1628 }
1629
1630 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1631 args[1] = uint->zero;
1632 args[2] = uint->zero;
1633 args[3] = lp_build_const_int32(base->gallivm,
1634 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1635 args[4] = uint->zero;
1636 }
1637 }
1638
1639 static void si_dump_streamout(struct pipe_stream_output_info *so)
1640 {
1641 unsigned i;
1642
1643 if (so->num_outputs)
1644 fprintf(stderr, "STREAMOUT\n");
1645
1646 for (i = 0; i < so->num_outputs; i++) {
1647 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1648 so->output[i].start_component;
1649 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1650 i, so->output[i].output_buffer,
1651 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1652 so->output[i].register_index,
1653 mask & 1 ? "x" : "",
1654 mask & 2 ? "y" : "",
1655 mask & 4 ? "z" : "",
1656 mask & 8 ? "w" : "");
1657 }
1658 }
1659
1660 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1661 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1662 * or v4i32 (num_channels=3,4). */
1663 static void build_tbuffer_store(struct si_shader_context *ctx,
1664 LLVMValueRef rsrc,
1665 LLVMValueRef vdata,
1666 unsigned num_channels,
1667 LLVMValueRef vaddr,
1668 LLVMValueRef soffset,
1669 unsigned inst_offset,
1670 unsigned dfmt,
1671 unsigned nfmt,
1672 unsigned offen,
1673 unsigned idxen,
1674 unsigned glc,
1675 unsigned slc,
1676 unsigned tfe)
1677 {
1678 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1679 LLVMValueRef args[] = {
1680 rsrc,
1681 vdata,
1682 LLVMConstInt(ctx->i32, num_channels, 0),
1683 vaddr,
1684 soffset,
1685 LLVMConstInt(ctx->i32, inst_offset, 0),
1686 LLVMConstInt(ctx->i32, dfmt, 0),
1687 LLVMConstInt(ctx->i32, nfmt, 0),
1688 LLVMConstInt(ctx->i32, offen, 0),
1689 LLVMConstInt(ctx->i32, idxen, 0),
1690 LLVMConstInt(ctx->i32, glc, 0),
1691 LLVMConstInt(ctx->i32, slc, 0),
1692 LLVMConstInt(ctx->i32, tfe, 0)
1693 };
1694
1695 /* The instruction offset field has 12 bits */
1696 assert(offen || inst_offset < (1 << 12));
1697
1698 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1699 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1700 const char *types[] = {"i32", "v2i32", "v4i32"};
1701 char name[256];
1702 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1703
1704 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
1705 args, Elements(args), 0);
1706 }
1707
1708 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
1709 LLVMValueRef rsrc,
1710 LLVMValueRef vdata,
1711 unsigned num_channels,
1712 LLVMValueRef vaddr,
1713 LLVMValueRef soffset,
1714 unsigned inst_offset)
1715 {
1716 static unsigned dfmt[] = {
1717 V_008F0C_BUF_DATA_FORMAT_32,
1718 V_008F0C_BUF_DATA_FORMAT_32_32,
1719 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1720 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1721 };
1722 assert(num_channels >= 1 && num_channels <= 4);
1723
1724 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
1725 inst_offset, dfmt[num_channels-1],
1726 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1727 }
1728
1729 /* On SI, the vertex shader is responsible for writing streamout data
1730 * to buffers. */
1731 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
1732 struct si_shader_output_values *outputs,
1733 unsigned noutput)
1734 {
1735 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
1736 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1737 LLVMBuilderRef builder = gallivm->builder;
1738 int i, j;
1739 struct lp_build_if_state if_ctx;
1740
1741 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1742 LLVMValueRef so_vtx_count =
1743 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
1744
1745 LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", ctx->i32,
1746 NULL, 0, LLVMReadNoneAttribute);
1747
1748 /* can_emit = tid < so_vtx_count; */
1749 LLVMValueRef can_emit =
1750 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1751
1752 LLVMValueRef stream_id =
1753 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
1754
1755 /* Emit the streamout code conditionally. This actually avoids
1756 * out-of-bounds buffer access. The hw tells us via the SGPR
1757 * (so_vtx_count) which threads are allowed to emit streamout data. */
1758 lp_build_if(&if_ctx, gallivm, can_emit);
1759 {
1760 /* The buffer offset is computed as follows:
1761 * ByteOffset = streamout_offset[buffer_id]*4 +
1762 * (streamout_write_index + thread_id)*stride[buffer_id] +
1763 * attrib_offset
1764 */
1765
1766 LLVMValueRef so_write_index =
1767 LLVMGetParam(ctx->radeon_bld.main_fn,
1768 ctx->param_streamout_write_index);
1769
1770 /* Compute (streamout_write_index + thread_id). */
1771 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1772
1773 /* Compute the write offset for each enabled buffer. */
1774 LLVMValueRef so_write_offset[4] = {};
1775 for (i = 0; i < 4; i++) {
1776 if (!so->stride[i])
1777 continue;
1778
1779 LLVMValueRef so_offset = LLVMGetParam(ctx->radeon_bld.main_fn,
1780 ctx->param_streamout_offset[i]);
1781 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
1782
1783 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1784 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
1785 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1786 }
1787
1788 /* Write streamout data. */
1789 for (i = 0; i < so->num_outputs; i++) {
1790 unsigned buf_idx = so->output[i].output_buffer;
1791 unsigned reg = so->output[i].register_index;
1792 unsigned start = so->output[i].start_component;
1793 unsigned num_comps = so->output[i].num_components;
1794 unsigned stream = so->output[i].stream;
1795 LLVMValueRef out[4];
1796 struct lp_build_if_state if_ctx_stream;
1797
1798 assert(num_comps && num_comps <= 4);
1799 if (!num_comps || num_comps > 4)
1800 continue;
1801
1802 if (reg >= noutput)
1803 continue;
1804
1805 /* Load the output as int. */
1806 for (j = 0; j < num_comps; j++) {
1807 out[j] = LLVMBuildBitCast(builder,
1808 outputs[reg].values[start+j],
1809 ctx->i32, "");
1810 }
1811
1812 /* Pack the output. */
1813 LLVMValueRef vdata = NULL;
1814
1815 switch (num_comps) {
1816 case 1: /* as i32 */
1817 vdata = out[0];
1818 break;
1819 case 2: /* as v2i32 */
1820 case 3: /* as v4i32 (aligned to 4) */
1821 case 4: /* as v4i32 */
1822 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
1823 for (j = 0; j < num_comps; j++) {
1824 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1825 LLVMConstInt(ctx->i32, j, 0), "");
1826 }
1827 break;
1828 }
1829
1830 LLVMValueRef can_emit_stream =
1831 LLVMBuildICmp(builder, LLVMIntEQ,
1832 stream_id,
1833 lp_build_const_int32(gallivm, stream), "");
1834
1835 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1836 build_tbuffer_store_dwords(ctx, ctx->so_buffers[buf_idx],
1837 vdata, num_comps,
1838 so_write_offset[buf_idx],
1839 LLVMConstInt(ctx->i32, 0, 0),
1840 so->output[i].dst_offset*4);
1841 lp_build_endif(&if_ctx_stream);
1842 }
1843 }
1844 lp_build_endif(&if_ctx);
1845 }
1846
1847
1848 /* Generate export instructions for hardware VS shader stage */
1849 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1850 struct si_shader_output_values *outputs,
1851 unsigned noutput)
1852 {
1853 struct si_shader_context *ctx = si_shader_context(bld_base);
1854 struct si_shader *shader = ctx->shader;
1855 struct lp_build_context *base = &bld_base->base;
1856 struct lp_build_context *uint =
1857 &ctx->radeon_bld.soa.bld_base.uint_bld;
1858 LLVMValueRef args[9];
1859 LLVMValueRef pos_args[4][9] = { { 0 } };
1860 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1861 unsigned semantic_name, semantic_index;
1862 unsigned target;
1863 unsigned param_count = 0;
1864 unsigned pos_idx;
1865 int i;
1866
1867 if (outputs && ctx->shader->selector->so.num_outputs) {
1868 si_llvm_emit_streamout(ctx, outputs, noutput);
1869 }
1870
1871 for (i = 0; i < noutput; i++) {
1872 semantic_name = outputs[i].name;
1873 semantic_index = outputs[i].sid;
1874
1875 handle_semantic:
1876 /* Select the correct target */
1877 switch(semantic_name) {
1878 case TGSI_SEMANTIC_PSIZE:
1879 psize_value = outputs[i].values[0];
1880 continue;
1881 case TGSI_SEMANTIC_EDGEFLAG:
1882 edgeflag_value = outputs[i].values[0];
1883 continue;
1884 case TGSI_SEMANTIC_LAYER:
1885 layer_value = outputs[i].values[0];
1886 semantic_name = TGSI_SEMANTIC_GENERIC;
1887 goto handle_semantic;
1888 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1889 viewport_index_value = outputs[i].values[0];
1890 semantic_name = TGSI_SEMANTIC_GENERIC;
1891 goto handle_semantic;
1892 case TGSI_SEMANTIC_POSITION:
1893 target = V_008DFC_SQ_EXP_POS;
1894 break;
1895 case TGSI_SEMANTIC_COLOR:
1896 case TGSI_SEMANTIC_BCOLOR:
1897 target = V_008DFC_SQ_EXP_PARAM + param_count;
1898 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
1899 shader->info.vs_output_param_offset[i] = param_count;
1900 param_count++;
1901 break;
1902 case TGSI_SEMANTIC_CLIPDIST:
1903 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1904 break;
1905 case TGSI_SEMANTIC_CLIPVERTEX:
1906 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1907 continue;
1908 case TGSI_SEMANTIC_PRIMID:
1909 case TGSI_SEMANTIC_FOG:
1910 case TGSI_SEMANTIC_TEXCOORD:
1911 case TGSI_SEMANTIC_GENERIC:
1912 target = V_008DFC_SQ_EXP_PARAM + param_count;
1913 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
1914 shader->info.vs_output_param_offset[i] = param_count;
1915 param_count++;
1916 break;
1917 default:
1918 target = 0;
1919 fprintf(stderr,
1920 "Warning: SI unhandled vs output type:%d\n",
1921 semantic_name);
1922 }
1923
1924 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1925
1926 if (target >= V_008DFC_SQ_EXP_POS &&
1927 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1928 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1929 args, sizeof(args));
1930 } else {
1931 lp_build_intrinsic(base->gallivm->builder,
1932 "llvm.SI.export", ctx->voidt,
1933 args, 9, 0);
1934 }
1935
1936 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1937 semantic_name = TGSI_SEMANTIC_GENERIC;
1938 goto handle_semantic;
1939 }
1940 }
1941
1942 shader->info.nr_param_exports = param_count;
1943
1944 /* We need to add the position output manually if it's missing. */
1945 if (!pos_args[0][0]) {
1946 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1947 pos_args[0][1] = uint->zero; /* EXEC mask */
1948 pos_args[0][2] = uint->zero; /* last export? */
1949 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1950 pos_args[0][4] = uint->zero; /* COMPR flag */
1951 pos_args[0][5] = base->zero; /* X */
1952 pos_args[0][6] = base->zero; /* Y */
1953 pos_args[0][7] = base->zero; /* Z */
1954 pos_args[0][8] = base->one; /* W */
1955 }
1956
1957 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1958 if (shader->selector->info.writes_psize ||
1959 shader->selector->info.writes_edgeflag ||
1960 shader->selector->info.writes_viewport_index ||
1961 shader->selector->info.writes_layer) {
1962 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1963 shader->selector->info.writes_psize |
1964 (shader->selector->info.writes_edgeflag << 1) |
1965 (shader->selector->info.writes_layer << 2) |
1966 (shader->selector->info.writes_viewport_index << 3));
1967 pos_args[1][1] = uint->zero; /* EXEC mask */
1968 pos_args[1][2] = uint->zero; /* last export? */
1969 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1970 pos_args[1][4] = uint->zero; /* COMPR flag */
1971 pos_args[1][5] = base->zero; /* X */
1972 pos_args[1][6] = base->zero; /* Y */
1973 pos_args[1][7] = base->zero; /* Z */
1974 pos_args[1][8] = base->zero; /* W */
1975
1976 if (shader->selector->info.writes_psize)
1977 pos_args[1][5] = psize_value;
1978
1979 if (shader->selector->info.writes_edgeflag) {
1980 /* The output is a float, but the hw expects an integer
1981 * with the first bit containing the edge flag. */
1982 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1983 edgeflag_value,
1984 ctx->i32, "");
1985 edgeflag_value = lp_build_min(&bld_base->int_bld,
1986 edgeflag_value,
1987 bld_base->int_bld.one);
1988
1989 /* The LLVM intrinsic expects a float. */
1990 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1991 edgeflag_value,
1992 ctx->f32, "");
1993 }
1994
1995 if (shader->selector->info.writes_layer)
1996 pos_args[1][7] = layer_value;
1997
1998 if (shader->selector->info.writes_viewport_index)
1999 pos_args[1][8] = viewport_index_value;
2000 }
2001
2002 for (i = 0; i < 4; i++)
2003 if (pos_args[i][0])
2004 shader->info.nr_pos_exports++;
2005
2006 pos_idx = 0;
2007 for (i = 0; i < 4; i++) {
2008 if (!pos_args[i][0])
2009 continue;
2010
2011 /* Specify the target we are exporting */
2012 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2013
2014 if (pos_idx == shader->info.nr_pos_exports)
2015 /* Specify that this is the last export */
2016 pos_args[i][2] = uint->one;
2017
2018 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2019 ctx->voidt, pos_args[i], 9, 0);
2020 }
2021 }
2022
2023 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2024 LLVMValueRef rel_patch_id,
2025 LLVMValueRef invocation_id,
2026 LLVMValueRef tcs_out_current_patch_data_offset)
2027 {
2028 struct si_shader_context *ctx = si_shader_context(bld_base);
2029 struct gallivm_state *gallivm = bld_base->base.gallivm;
2030 struct si_shader *shader = ctx->shader;
2031 unsigned tess_inner_index, tess_outer_index;
2032 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2033 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2034 unsigned stride, outer_comps, inner_comps, i;
2035 struct lp_build_if_state if_ctx;
2036
2037 /* Do this only for invocation 0, because the tess levels are per-patch,
2038 * not per-vertex.
2039 *
2040 * This can't jump, because invocation 0 executes this. It should
2041 * at least mask out the loads and stores for other invocations.
2042 */
2043 lp_build_if(&if_ctx, gallivm,
2044 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2045 invocation_id, bld_base->uint_bld.zero, ""));
2046
2047 /* Determine the layout of one tess factor element in the buffer. */
2048 switch (shader->key.tcs.epilog.prim_mode) {
2049 case PIPE_PRIM_LINES:
2050 stride = 2; /* 2 dwords, 1 vec2 store */
2051 outer_comps = 2;
2052 inner_comps = 0;
2053 break;
2054 case PIPE_PRIM_TRIANGLES:
2055 stride = 4; /* 4 dwords, 1 vec4 store */
2056 outer_comps = 3;
2057 inner_comps = 1;
2058 break;
2059 case PIPE_PRIM_QUADS:
2060 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2061 outer_comps = 4;
2062 inner_comps = 2;
2063 break;
2064 default:
2065 assert(0);
2066 return;
2067 }
2068
2069 /* Load tess_inner and tess_outer from LDS.
2070 * Any invocation can write them, so we can't get them from a temporary.
2071 */
2072 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2073 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2074
2075 lds_base = tcs_out_current_patch_data_offset;
2076 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2077 lp_build_const_int32(gallivm,
2078 tess_inner_index * 4), "");
2079 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2080 lp_build_const_int32(gallivm,
2081 tess_outer_index * 4), "");
2082
2083 for (i = 0; i < outer_comps; i++)
2084 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2085 for (i = 0; i < inner_comps; i++)
2086 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2087
2088 /* Convert the outputs to vectors for stores. */
2089 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2090 vec1 = NULL;
2091
2092 if (stride > 4)
2093 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2094
2095 /* Get the buffer. */
2096 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2097 SI_PARAM_RW_BUFFERS);
2098 buffer = build_indexed_load_const(ctx, rw_buffers,
2099 lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR));
2100
2101 /* Get the offset. */
2102 tf_base = LLVMGetParam(ctx->radeon_bld.main_fn,
2103 SI_PARAM_TESS_FACTOR_OFFSET);
2104 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2105 lp_build_const_int32(gallivm, 4 * stride), "");
2106
2107 /* Store the outputs. */
2108 build_tbuffer_store_dwords(ctx, buffer, vec0,
2109 MIN2(stride, 4), byteoffset, tf_base, 0);
2110 if (vec1)
2111 build_tbuffer_store_dwords(ctx, buffer, vec1,
2112 stride - 4, byteoffset, tf_base, 16);
2113 lp_build_endif(&if_ctx);
2114 }
2115
2116 /* This only writes the tessellation factor levels. */
2117 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2118 {
2119 struct si_shader_context *ctx = si_shader_context(bld_base);
2120 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2121
2122 rel_patch_id = get_rel_patch_id(ctx);
2123 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2124 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2125
2126 if (!ctx->is_monolithic) {
2127 /* Return epilog parameters from this function. */
2128 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2129 LLVMValueRef ret = ctx->return_value;
2130 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2131 unsigned vgpr;
2132
2133 /* RW_BUFFERS pointer */
2134 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2135 SI_PARAM_RW_BUFFERS);
2136 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2137 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2138 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2139 bld_base->uint_bld.zero, "");
2140 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2141 bld_base->uint_bld.one, "");
2142 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2143 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2144
2145 /* Tess factor buffer soffset is after user SGPRs. */
2146 tf_soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2147 SI_PARAM_TESS_FACTOR_OFFSET);
2148 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2149 SI_TCS_NUM_USER_SGPR, "");
2150
2151 /* VGPRs */
2152 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2153 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2154 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2155
2156 vgpr = SI_TCS_NUM_USER_SGPR + 1;
2157 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2158 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2159 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2160 ctx->return_value = ret;
2161 return;
2162 }
2163
2164 si_write_tess_factors(bld_base, rel_patch_id, invocation_id, tf_lds_offset);
2165 }
2166
2167 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2168 {
2169 struct si_shader_context *ctx = si_shader_context(bld_base);
2170 struct si_shader *shader = ctx->shader;
2171 struct tgsi_shader_info *info = &shader->selector->info;
2172 struct gallivm_state *gallivm = bld_base->base.gallivm;
2173 unsigned i, chan;
2174 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
2175 ctx->param_rel_auto_id);
2176 LLVMValueRef vertex_dw_stride =
2177 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2178 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2179 vertex_dw_stride, "");
2180
2181 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2182 * its inputs from it. */
2183 for (i = 0; i < info->num_outputs; i++) {
2184 LLVMValueRef *out_ptr = ctx->radeon_bld.soa.outputs[i];
2185 unsigned name = info->output_semantic_name[i];
2186 unsigned index = info->output_semantic_index[i];
2187 int param = si_shader_io_get_unique_index(name, index);
2188 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2189 lp_build_const_int32(gallivm, param * 4), "");
2190
2191 for (chan = 0; chan < 4; chan++) {
2192 lds_store(bld_base, chan, dw_addr,
2193 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2194 }
2195 }
2196 }
2197
2198 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2199 {
2200 struct si_shader_context *ctx = si_shader_context(bld_base);
2201 struct gallivm_state *gallivm = bld_base->base.gallivm;
2202 struct si_shader *es = ctx->shader;
2203 struct tgsi_shader_info *info = &es->selector->info;
2204 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2205 ctx->param_es2gs_offset);
2206 unsigned chan;
2207 int i;
2208
2209 for (i = 0; i < info->num_outputs; i++) {
2210 LLVMValueRef *out_ptr =
2211 ctx->radeon_bld.soa.outputs[i];
2212 int param_index;
2213
2214 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2215 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2216 continue;
2217
2218 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2219 info->output_semantic_index[i]);
2220
2221 for (chan = 0; chan < 4; chan++) {
2222 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2223 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2224
2225 build_tbuffer_store(ctx,
2226 ctx->esgs_ring,
2227 out_val, 1,
2228 LLVMGetUndef(ctx->i32), soffset,
2229 (4 * param_index + chan) * 4,
2230 V_008F0C_BUF_DATA_FORMAT_32,
2231 V_008F0C_BUF_NUM_FORMAT_UINT,
2232 0, 0, 1, 1, 0);
2233 }
2234 }
2235 }
2236
2237 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2238 {
2239 struct si_shader_context *ctx = si_shader_context(bld_base);
2240 struct gallivm_state *gallivm = bld_base->base.gallivm;
2241 LLVMValueRef args[2];
2242
2243 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2244 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2245 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2246 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
2247 }
2248
2249 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2250 {
2251 struct si_shader_context *ctx = si_shader_context(bld_base);
2252 struct gallivm_state *gallivm = bld_base->base.gallivm;
2253 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2254 struct si_shader_output_values *outputs = NULL;
2255 int i,j;
2256
2257 assert(!ctx->is_gs_copy_shader);
2258
2259 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2260
2261 /* Vertex color clamping.
2262 *
2263 * This uses a state constant loaded in a user data SGPR and
2264 * an IF statement is added that clamps all colors if the constant
2265 * is true.
2266 */
2267 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
2268 struct lp_build_if_state if_ctx;
2269 LLVMValueRef cond = NULL;
2270 LLVMValueRef addr, val;
2271
2272 for (i = 0; i < info->num_outputs; i++) {
2273 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2274 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2275 continue;
2276
2277 /* We've found a color. */
2278 if (!cond) {
2279 /* The state is in the first bit of the user SGPR. */
2280 cond = LLVMGetParam(ctx->radeon_bld.main_fn,
2281 SI_PARAM_VS_STATE_BITS);
2282 cond = LLVMBuildTrunc(gallivm->builder, cond,
2283 ctx->i1, "");
2284 lp_build_if(&if_ctx, gallivm, cond);
2285 }
2286
2287 for (j = 0; j < 4; j++) {
2288 addr = ctx->radeon_bld.soa.outputs[i][j];
2289 val = LLVMBuildLoad(gallivm->builder, addr, "");
2290 val = radeon_llvm_saturate(bld_base, val);
2291 LLVMBuildStore(gallivm->builder, val, addr);
2292 }
2293 }
2294
2295 if (cond)
2296 lp_build_endif(&if_ctx);
2297 }
2298
2299 for (i = 0; i < info->num_outputs; i++) {
2300 outputs[i].name = info->output_semantic_name[i];
2301 outputs[i].sid = info->output_semantic_index[i];
2302
2303 for (j = 0; j < 4; j++)
2304 outputs[i].values[j] =
2305 LLVMBuildLoad(gallivm->builder,
2306 ctx->radeon_bld.soa.outputs[i][j],
2307 "");
2308 }
2309
2310 if (ctx->is_monolithic) {
2311 /* Export PrimitiveID when PS needs it. */
2312 if (si_vs_exports_prim_id(ctx->shader)) {
2313 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2314 outputs[i].sid = 0;
2315 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2316 get_primitive_id(bld_base, 0));
2317 outputs[i].values[1] = bld_base->base.undef;
2318 outputs[i].values[2] = bld_base->base.undef;
2319 outputs[i].values[3] = bld_base->base.undef;
2320 i++;
2321 }
2322 } else {
2323 /* Return the primitive ID from the LLVM function. */
2324 ctx->return_value =
2325 LLVMBuildInsertValue(gallivm->builder,
2326 ctx->return_value,
2327 bitcast(bld_base, TGSI_TYPE_FLOAT,
2328 get_primitive_id(bld_base, 0)),
2329 VS_EPILOG_PRIMID_LOC, "");
2330 }
2331
2332 si_llvm_export_vs(bld_base, outputs, i);
2333 FREE(outputs);
2334 }
2335
2336 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2337 LLVMValueRef depth, LLVMValueRef stencil,
2338 LLVMValueRef samplemask)
2339 {
2340 struct si_shader_context *ctx = si_shader_context(bld_base);
2341 struct lp_build_context *base = &bld_base->base;
2342 struct lp_build_context *uint = &bld_base->uint_bld;
2343 LLVMValueRef args[9];
2344 unsigned mask = 0;
2345
2346 assert(depth || stencil || samplemask);
2347
2348 args[1] = uint->one; /* whether the EXEC mask is valid */
2349 args[2] = uint->one; /* DONE bit */
2350
2351 /* Specify the target we are exporting */
2352 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2353
2354 args[4] = uint->zero; /* COMP flag */
2355 args[5] = base->undef; /* R, depth */
2356 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2357 args[7] = base->undef; /* B, sample mask */
2358 args[8] = base->undef; /* A, alpha to mask */
2359
2360 if (depth) {
2361 args[5] = depth;
2362 mask |= 0x1;
2363 }
2364
2365 if (stencil) {
2366 args[6] = stencil;
2367 mask |= 0x2;
2368 }
2369
2370 if (samplemask) {
2371 args[7] = samplemask;
2372 mask |= 0x4;
2373 }
2374
2375 /* SI (except OLAND) has a bug that it only looks
2376 * at the X writemask component. */
2377 if (ctx->screen->b.chip_class == SI &&
2378 ctx->screen->b.family != CHIP_OLAND)
2379 mask |= 0x1;
2380
2381 /* Specify which components to enable */
2382 args[0] = lp_build_const_int32(base->gallivm, mask);
2383
2384 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2385 ctx->voidt, args, 9, 0);
2386 }
2387
2388 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2389 LLVMValueRef *color, unsigned index,
2390 unsigned samplemask_param,
2391 bool is_last)
2392 {
2393 struct si_shader_context *ctx = si_shader_context(bld_base);
2394 struct lp_build_context *base = &bld_base->base;
2395 int i;
2396
2397 /* Clamp color */
2398 if (ctx->shader->key.ps.epilog.clamp_color)
2399 for (i = 0; i < 4; i++)
2400 color[i] = radeon_llvm_saturate(bld_base, color[i]);
2401
2402 /* Alpha to one */
2403 if (ctx->shader->key.ps.epilog.alpha_to_one)
2404 color[3] = base->one;
2405
2406 /* Alpha test */
2407 if (index == 0 &&
2408 ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2409 si_alpha_test(bld_base, color[3]);
2410
2411 /* Line & polygon smoothing */
2412 if (ctx->shader->key.ps.epilog.poly_line_smoothing)
2413 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
2414 samplemask_param);
2415
2416 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2417 if (ctx->shader->key.ps.epilog.last_cbuf > 0) {
2418 LLVMValueRef args[8][9];
2419 int c, last = -1;
2420
2421 /* Get the export arguments, also find out what the last one is. */
2422 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
2423 si_llvm_init_export_args(bld_base, color,
2424 V_008DFC_SQ_EXP_MRT + c, args[c]);
2425 if (args[c][0] != bld_base->uint_bld.zero)
2426 last = c;
2427 }
2428
2429 /* Emit all exports. */
2430 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
2431 if (is_last && last == c) {
2432 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2433 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
2434 } else if (args[c][0] == bld_base->uint_bld.zero)
2435 continue; /* unnecessary NULL export */
2436
2437 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2438 ctx->voidt, args[c], 9, 0);
2439 }
2440 } else {
2441 LLVMValueRef args[9];
2442
2443 /* Export */
2444 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2445 args);
2446 if (is_last) {
2447 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2448 args[2] = bld_base->uint_bld.one; /* DONE bit */
2449 } else if (args[0] == bld_base->uint_bld.zero)
2450 return; /* unnecessary NULL export */
2451
2452 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2453 ctx->voidt, args, 9, 0);
2454 }
2455 }
2456
2457 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2458 {
2459 struct si_shader_context *ctx = si_shader_context(bld_base);
2460 struct lp_build_context *base = &bld_base->base;
2461 struct lp_build_context *uint = &bld_base->uint_bld;
2462 LLVMValueRef args[9];
2463
2464 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
2465 args[1] = uint->one; /* whether the EXEC mask is valid */
2466 args[2] = uint->one; /* DONE bit */
2467 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2468 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
2469 args[5] = uint->undef; /* R */
2470 args[6] = uint->undef; /* G */
2471 args[7] = uint->undef; /* B */
2472 args[8] = uint->undef; /* A */
2473
2474 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2475 ctx->voidt, args, 9, 0);
2476 }
2477
2478 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context *bld_base)
2479 {
2480 struct si_shader_context *ctx = si_shader_context(bld_base);
2481 struct si_shader *shader = ctx->shader;
2482 struct lp_build_context *base = &bld_base->base;
2483 struct tgsi_shader_info *info = &shader->selector->info;
2484 LLVMBuilderRef builder = base->gallivm->builder;
2485 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2486 int last_color_export = -1;
2487 int i;
2488
2489 /* Determine the last export. If MRTZ is present, it's always last.
2490 * Otherwise, find the last color export.
2491 */
2492 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask) {
2493 unsigned spi_format = shader->key.ps.epilog.spi_shader_col_format;
2494
2495 /* Don't export NULL and return if alpha-test is enabled. */
2496 if (shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS &&
2497 shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER &&
2498 (spi_format & 0xf) == 0)
2499 spi_format |= V_028714_SPI_SHADER_32_AR;
2500
2501 for (i = 0; i < info->num_outputs; i++) {
2502 unsigned index = info->output_semantic_index[i];
2503
2504 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR)
2505 continue;
2506
2507 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2508 if (shader->key.ps.epilog.last_cbuf > 0) {
2509 /* Just set this if any of the colorbuffers are enabled. */
2510 if (spi_format &
2511 ((1llu << (4 * (shader->key.ps.epilog.last_cbuf + 1))) - 1))
2512 last_color_export = i;
2513 continue;
2514 }
2515
2516 if ((spi_format >> (index * 4)) & 0xf)
2517 last_color_export = i;
2518 }
2519
2520 /* If there are no outputs, export NULL. */
2521 if (last_color_export == -1) {
2522 si_export_null(bld_base);
2523 return;
2524 }
2525 }
2526
2527 for (i = 0; i < info->num_outputs; i++) {
2528 unsigned semantic_name = info->output_semantic_name[i];
2529 unsigned semantic_index = info->output_semantic_index[i];
2530 unsigned j;
2531 LLVMValueRef color[4] = {};
2532
2533 /* Select the correct target */
2534 switch (semantic_name) {
2535 case TGSI_SEMANTIC_POSITION:
2536 depth = LLVMBuildLoad(builder,
2537 ctx->radeon_bld.soa.outputs[i][2], "");
2538 break;
2539 case TGSI_SEMANTIC_STENCIL:
2540 stencil = LLVMBuildLoad(builder,
2541 ctx->radeon_bld.soa.outputs[i][1], "");
2542 break;
2543 case TGSI_SEMANTIC_SAMPLEMASK:
2544 samplemask = LLVMBuildLoad(builder,
2545 ctx->radeon_bld.soa.outputs[i][0], "");
2546 break;
2547 case TGSI_SEMANTIC_COLOR:
2548 for (j = 0; j < 4; j++)
2549 color[j] = LLVMBuildLoad(builder,
2550 ctx->radeon_bld.soa.outputs[i][j], "");
2551
2552 si_export_mrt_color(bld_base, color, semantic_index,
2553 SI_PARAM_SAMPLE_COVERAGE,
2554 last_color_export == i);
2555 break;
2556 default:
2557 fprintf(stderr,
2558 "Warning: SI unhandled fs output type:%d\n",
2559 semantic_name);
2560 }
2561 }
2562
2563 if (depth || stencil || samplemask)
2564 si_export_mrt_z(bld_base, depth, stencil, samplemask);
2565 }
2566
2567 /**
2568 * Return PS outputs in this order:
2569 *
2570 * v[0:3] = color0.xyzw
2571 * v[4:7] = color1.xyzw
2572 * ...
2573 * vN+0 = Depth
2574 * vN+1 = Stencil
2575 * vN+2 = SampleMask
2576 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
2577 *
2578 * The alpha-ref SGPR is returned via its original location.
2579 */
2580 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
2581 {
2582 struct si_shader_context *ctx = si_shader_context(bld_base);
2583 struct si_shader *shader = ctx->shader;
2584 struct lp_build_context *base = &bld_base->base;
2585 struct tgsi_shader_info *info = &shader->selector->info;
2586 LLVMBuilderRef builder = base->gallivm->builder;
2587 unsigned i, j, first_vgpr, vgpr;
2588
2589 LLVMValueRef color[8][4] = {};
2590 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2591 LLVMValueRef ret;
2592
2593 /* Read the output values. */
2594 for (i = 0; i < info->num_outputs; i++) {
2595 unsigned semantic_name = info->output_semantic_name[i];
2596 unsigned semantic_index = info->output_semantic_index[i];
2597
2598 switch (semantic_name) {
2599 case TGSI_SEMANTIC_COLOR:
2600 assert(semantic_index < 8);
2601 for (j = 0; j < 4; j++) {
2602 LLVMValueRef ptr = ctx->radeon_bld.soa.outputs[i][j];
2603 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
2604 color[semantic_index][j] = result;
2605 }
2606 break;
2607 case TGSI_SEMANTIC_POSITION:
2608 depth = LLVMBuildLoad(builder,
2609 ctx->radeon_bld.soa.outputs[i][2], "");
2610 break;
2611 case TGSI_SEMANTIC_STENCIL:
2612 stencil = LLVMBuildLoad(builder,
2613 ctx->radeon_bld.soa.outputs[i][1], "");
2614 break;
2615 case TGSI_SEMANTIC_SAMPLEMASK:
2616 samplemask = LLVMBuildLoad(builder,
2617 ctx->radeon_bld.soa.outputs[i][0], "");
2618 break;
2619 default:
2620 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
2621 semantic_name);
2622 }
2623 }
2624
2625 /* Fill the return structure. */
2626 ret = ctx->return_value;
2627
2628 /* Set SGPRs. */
2629 ret = LLVMBuildInsertValue(builder, ret,
2630 bitcast(bld_base, TGSI_TYPE_SIGNED,
2631 LLVMGetParam(ctx->radeon_bld.main_fn,
2632 SI_PARAM_ALPHA_REF)),
2633 SI_SGPR_ALPHA_REF, "");
2634
2635 /* Set VGPRs */
2636 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
2637 for (i = 0; i < ARRAY_SIZE(color); i++) {
2638 if (!color[i][0])
2639 continue;
2640
2641 for (j = 0; j < 4; j++)
2642 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
2643 }
2644 if (depth)
2645 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
2646 if (stencil)
2647 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
2648 if (samplemask)
2649 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
2650
2651 /* Add the input sample mask for smoothing at the end. */
2652 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
2653 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
2654 ret = LLVMBuildInsertValue(builder, ret,
2655 LLVMGetParam(ctx->radeon_bld.main_fn,
2656 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
2657
2658 ctx->return_value = ret;
2659 }
2660
2661 /**
2662 * Given a v8i32 resource descriptor for a buffer, extract the size of the
2663 * buffer in number of elements and return it as an i32.
2664 */
2665 static LLVMValueRef get_buffer_size(
2666 struct lp_build_tgsi_context *bld_base,
2667 LLVMValueRef descriptor)
2668 {
2669 struct si_shader_context *ctx = si_shader_context(bld_base);
2670 struct gallivm_state *gallivm = bld_base->base.gallivm;
2671 LLVMBuilderRef builder = gallivm->builder;
2672 LLVMValueRef size =
2673 LLVMBuildExtractElement(builder, descriptor,
2674 lp_build_const_int32(gallivm, 6), "");
2675
2676 if (ctx->screen->b.chip_class >= VI) {
2677 /* On VI, the descriptor contains the size in bytes,
2678 * but TXQ must return the size in elements.
2679 * The stride is always non-zero for resources using TXQ.
2680 */
2681 LLVMValueRef stride =
2682 LLVMBuildExtractElement(builder, descriptor,
2683 lp_build_const_int32(gallivm, 5), "");
2684 stride = LLVMBuildLShr(builder, stride,
2685 lp_build_const_int32(gallivm, 16), "");
2686 stride = LLVMBuildAnd(builder, stride,
2687 lp_build_const_int32(gallivm, 0x3FFF), "");
2688
2689 size = LLVMBuildUDiv(builder, size, stride, "");
2690 }
2691
2692 return size;
2693 }
2694
2695 /**
2696 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2697 * intrinsic names).
2698 */
2699 static void build_int_type_name(
2700 LLVMTypeRef type,
2701 char *buf, unsigned bufsize)
2702 {
2703 assert(bufsize >= 6);
2704
2705 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2706 snprintf(buf, bufsize, "v%ui32",
2707 LLVMGetVectorSize(type));
2708 else
2709 strcpy(buf, "i32");
2710 }
2711
2712 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
2713 struct lp_build_tgsi_context *bld_base,
2714 struct lp_build_emit_data *emit_data);
2715
2716 /* Prevent optimizations (at least of memory accesses) across the current
2717 * point in the program by emitting empty inline assembly that is marked as
2718 * having side effects.
2719 */
2720 static void emit_optimization_barrier(struct si_shader_context *ctx)
2721 {
2722 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
2723 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
2724 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
2725 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
2726 }
2727
2728 static void membar_emit(
2729 const struct lp_build_tgsi_action *action,
2730 struct lp_build_tgsi_context *bld_base,
2731 struct lp_build_emit_data *emit_data)
2732 {
2733 struct si_shader_context *ctx = si_shader_context(bld_base);
2734
2735 /* Since memoryBarrier only makes guarantees about atomics and
2736 * coherent image accesses (which bypass TC L1), we do not need to emit
2737 * any special cache handling here.
2738 *
2739 * We do have to prevent LLVM from re-ordering loads across
2740 * the barrier though.
2741 */
2742 emit_optimization_barrier(ctx);
2743 }
2744
2745 static bool tgsi_is_array_sampler(unsigned target)
2746 {
2747 return target == TGSI_TEXTURE_1D_ARRAY ||
2748 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2749 target == TGSI_TEXTURE_2D_ARRAY ||
2750 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2751 target == TGSI_TEXTURE_CUBE_ARRAY ||
2752 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2753 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2754 }
2755
2756 static bool tgsi_is_array_image(unsigned target)
2757 {
2758 return target == TGSI_TEXTURE_3D ||
2759 target == TGSI_TEXTURE_CUBE ||
2760 target == TGSI_TEXTURE_1D_ARRAY ||
2761 target == TGSI_TEXTURE_2D_ARRAY ||
2762 target == TGSI_TEXTURE_CUBE_ARRAY ||
2763 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2764 }
2765
2766 /**
2767 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
2768 *
2769 * At least on Tonga, executing image stores on images with DCC enabled and
2770 * non-trivial can eventually lead to lockups. This can occur when an
2771 * application binds an image as read-only but then uses a shader that writes
2772 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
2773 * program termination) in this case, but it doesn't cost much to be a bit
2774 * nicer: disabling DCC in the shader still leads to undefined results but
2775 * avoids the lockup.
2776 */
2777 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
2778 LLVMValueRef rsrc)
2779 {
2780 if (ctx->screen->b.chip_class <= CIK) {
2781 return rsrc;
2782 } else {
2783 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
2784 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
2785 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
2786 LLVMValueRef tmp;
2787
2788 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
2789 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
2790 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
2791 }
2792 }
2793
2794 /**
2795 * Load the resource descriptor for \p image.
2796 */
2797 static void
2798 image_fetch_rsrc(
2799 struct lp_build_tgsi_context *bld_base,
2800 const struct tgsi_full_src_register *image,
2801 bool dcc_off,
2802 LLVMValueRef *rsrc)
2803 {
2804 struct si_shader_context *ctx = si_shader_context(bld_base);
2805
2806 assert(image->Register.File == TGSI_FILE_IMAGE);
2807
2808 if (!image->Register.Indirect) {
2809 /* Fast path: use preloaded resources */
2810 *rsrc = ctx->images[image->Register.Index];
2811 } else {
2812 /* Indexing and manual load */
2813 LLVMValueRef ind_index;
2814 LLVMValueRef rsrc_ptr;
2815 LLVMValueRef tmp;
2816
2817 ind_index = get_indirect_index(ctx, &image->Indirect, image->Register.Index);
2818
2819 rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
2820 tmp = build_indexed_load_const(ctx, rsrc_ptr, ind_index);
2821 if (dcc_off)
2822 tmp = force_dcc_off(ctx, tmp);
2823 *rsrc = tmp;
2824 }
2825 }
2826
2827 static LLVMValueRef image_fetch_coords(
2828 struct lp_build_tgsi_context *bld_base,
2829 const struct tgsi_full_instruction *inst,
2830 unsigned src)
2831 {
2832 struct gallivm_state *gallivm = bld_base->base.gallivm;
2833 LLVMBuilderRef builder = gallivm->builder;
2834 unsigned target = inst->Memory.Texture;
2835 int sample;
2836 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &sample);
2837 LLVMValueRef coords[4];
2838 LLVMValueRef tmp;
2839 int chan;
2840
2841 for (chan = 0; chan < num_coords; ++chan) {
2842 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
2843 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
2844 coords[chan] = tmp;
2845 }
2846
2847 if (num_coords == 1)
2848 return coords[0];
2849
2850 if (num_coords == 3) {
2851 /* LLVM has difficulties lowering 3-element vectors. */
2852 coords[3] = bld_base->uint_bld.undef;
2853 num_coords = 4;
2854 }
2855
2856 return lp_build_gather_values(gallivm, coords, num_coords);
2857 }
2858
2859 /**
2860 * Append the extra mode bits that are used by image load and store.
2861 */
2862 static void image_append_args(
2863 struct si_shader_context *ctx,
2864 struct lp_build_emit_data * emit_data,
2865 unsigned target,
2866 bool atomic)
2867 {
2868 const struct tgsi_full_instruction *inst = emit_data->inst;
2869 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2870 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2871
2872 emit_data->args[emit_data->arg_count++] = i1false; /* r128 */
2873 emit_data->args[emit_data->arg_count++] =
2874 tgsi_is_array_image(target) ? i1true : i1false; /* da */
2875 if (!atomic) {
2876 emit_data->args[emit_data->arg_count++] =
2877 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
2878 i1true : i1false; /* glc */
2879 }
2880 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
2881 }
2882
2883 /**
2884 * Append the resource and indexing arguments for buffer intrinsics.
2885 *
2886 * \param rsrc the 256 bit resource
2887 * \param index index into the buffer
2888 */
2889 static void buffer_append_args(
2890 struct si_shader_context *ctx,
2891 struct lp_build_emit_data *emit_data,
2892 LLVMValueRef rsrc,
2893 LLVMValueRef index,
2894 bool atomic)
2895 {
2896 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
2897 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
2898 const struct tgsi_full_instruction *inst = emit_data->inst;
2899 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
2900 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2901 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2902
2903 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, v2i128, "");
2904 rsrc = LLVMBuildExtractElement(gallivm->builder, rsrc, bld_base->uint_bld.one, "");
2905 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, "");
2906
2907 emit_data->args[emit_data->arg_count++] = rsrc;
2908 emit_data->args[emit_data->arg_count++] = index; /* vindex */
2909 emit_data->args[emit_data->arg_count++] = bld_base->uint_bld.zero; /* voffset */
2910 if (!atomic) {
2911 emit_data->args[emit_data->arg_count++] =
2912 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
2913 i1true : i1false; /* glc */
2914 }
2915 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
2916 }
2917
2918 static void load_fetch_args(
2919 struct lp_build_tgsi_context * bld_base,
2920 struct lp_build_emit_data * emit_data)
2921 {
2922 struct si_shader_context *ctx = si_shader_context(bld_base);
2923 struct gallivm_state *gallivm = bld_base->base.gallivm;
2924 const struct tgsi_full_instruction * inst = emit_data->inst;
2925 unsigned target = inst->Memory.Texture;
2926 LLVMValueRef coords;
2927 LLVMValueRef rsrc;
2928
2929 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
2930
2931 image_fetch_rsrc(bld_base, &inst->Src[0], false, &rsrc);
2932 coords = image_fetch_coords(bld_base, inst, 1);
2933
2934 if (target == TGSI_TEXTURE_BUFFER) {
2935 buffer_append_args(ctx, emit_data, rsrc, coords, false);
2936 } else {
2937 emit_data->args[0] = coords;
2938 emit_data->args[1] = rsrc;
2939 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
2940 emit_data->arg_count = 3;
2941
2942 image_append_args(ctx, emit_data, target, false);
2943 }
2944 }
2945
2946 static void load_emit(
2947 const struct lp_build_tgsi_action *action,
2948 struct lp_build_tgsi_context *bld_base,
2949 struct lp_build_emit_data *emit_data)
2950 {
2951 struct si_shader_context *ctx = si_shader_context(bld_base);
2952 struct gallivm_state *gallivm = bld_base->base.gallivm;
2953 LLVMBuilderRef builder = gallivm->builder;
2954 const struct tgsi_full_instruction * inst = emit_data->inst;
2955 unsigned target = inst->Memory.Texture;
2956 char intrinsic_name[32];
2957 char coords_type[8];
2958
2959 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
2960 emit_optimization_barrier(ctx);
2961
2962 if (target == TGSI_TEXTURE_BUFFER) {
2963 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2964 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
2965 emit_data->args, emit_data->arg_count,
2966 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
2967 } else {
2968 build_int_type_name(LLVMTypeOf(emit_data->args[0]),
2969 coords_type, sizeof(coords_type));
2970
2971 snprintf(intrinsic_name, sizeof(intrinsic_name),
2972 "llvm.amdgcn.image.load.%s", coords_type);
2973
2974 emit_data->output[emit_data->chan] =
2975 lp_build_intrinsic(
2976 builder, intrinsic_name, emit_data->dst_type,
2977 emit_data->args, emit_data->arg_count,
2978 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
2979 }
2980 }
2981
2982 static void store_fetch_args(
2983 struct lp_build_tgsi_context * bld_base,
2984 struct lp_build_emit_data * emit_data)
2985 {
2986 struct si_shader_context *ctx = si_shader_context(bld_base);
2987 struct gallivm_state *gallivm = bld_base->base.gallivm;
2988 const struct tgsi_full_instruction * inst = emit_data->inst;
2989 struct tgsi_full_src_register image;
2990 unsigned target = inst->Memory.Texture;
2991 LLVMValueRef chans[4];
2992 LLVMValueRef data;
2993 LLVMValueRef coords;
2994 LLVMValueRef rsrc;
2995 unsigned chan;
2996
2997 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
2998
2999 image = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3000 coords = image_fetch_coords(bld_base, inst, 0);
3001
3002 for (chan = 0; chan < 4; ++chan) {
3003 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3004 }
3005 data = lp_build_gather_values(gallivm, chans, 4);
3006
3007 if (target == TGSI_TEXTURE_BUFFER) {
3008 image_fetch_rsrc(bld_base, &image, false, &rsrc);
3009 emit_data->args[0] = data;
3010 emit_data->arg_count = 1;
3011
3012 buffer_append_args(ctx, emit_data, rsrc, coords, false);
3013 } else {
3014 emit_data->args[0] = data;
3015 emit_data->args[1] = coords;
3016 image_fetch_rsrc(bld_base, &image, true, &emit_data->args[2]);
3017 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3018 emit_data->arg_count = 4;
3019
3020 image_append_args(ctx, emit_data, target, false);
3021 }
3022 }
3023
3024 static void store_emit(
3025 const struct lp_build_tgsi_action *action,
3026 struct lp_build_tgsi_context *bld_base,
3027 struct lp_build_emit_data *emit_data)
3028 {
3029 struct gallivm_state *gallivm = bld_base->base.gallivm;
3030 LLVMBuilderRef builder = gallivm->builder;
3031 const struct tgsi_full_instruction * inst = emit_data->inst;
3032 unsigned target = inst->Memory.Texture;
3033 char intrinsic_name[32];
3034 char coords_type[8];
3035
3036 if (target == TGSI_TEXTURE_BUFFER) {
3037 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3038 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3039 emit_data->dst_type, emit_data->args, emit_data->arg_count,
3040 LLVMNoUnwindAttribute);
3041 } else {
3042 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
3043 coords_type, sizeof(coords_type));
3044 snprintf(intrinsic_name, sizeof(intrinsic_name),
3045 "llvm.amdgcn.image.store.%s", coords_type);
3046
3047 emit_data->output[emit_data->chan] =
3048 lp_build_intrinsic(
3049 builder, intrinsic_name, emit_data->dst_type,
3050 emit_data->args, emit_data->arg_count,
3051 LLVMNoUnwindAttribute);
3052 }
3053 }
3054
3055 static void atomic_fetch_args(
3056 struct lp_build_tgsi_context * bld_base,
3057 struct lp_build_emit_data * emit_data)
3058 {
3059 struct si_shader_context *ctx = si_shader_context(bld_base);
3060 struct gallivm_state *gallivm = bld_base->base.gallivm;
3061 LLVMBuilderRef builder = gallivm->builder;
3062 const struct tgsi_full_instruction * inst = emit_data->inst;
3063 unsigned target = inst->Memory.Texture;
3064 LLVMValueRef data1, data2;
3065 LLVMValueRef coords;
3066 LLVMValueRef rsrc;
3067 LLVMValueRef tmp;
3068
3069 emit_data->dst_type = bld_base->base.elem_type;
3070
3071 image_fetch_rsrc(bld_base, &inst->Src[0], target != TGSI_TEXTURE_BUFFER,
3072 &rsrc);
3073 coords = image_fetch_coords(bld_base, inst, 1);
3074
3075 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
3076 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3077
3078 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3079 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
3080 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3081 }
3082
3083 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3084 * of arguments, which is reversed relative to TGSI (and GLSL)
3085 */
3086 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3087 emit_data->args[emit_data->arg_count++] = data2;
3088 emit_data->args[emit_data->arg_count++] = data1;
3089
3090 if (target == TGSI_TEXTURE_BUFFER) {
3091 buffer_append_args(ctx, emit_data, rsrc, coords, true);
3092 } else {
3093 emit_data->args[emit_data->arg_count++] = coords;
3094 emit_data->args[emit_data->arg_count++] = rsrc;
3095
3096 image_append_args(ctx, emit_data, target, true);
3097 }
3098 }
3099
3100 static void atomic_emit(
3101 const struct lp_build_tgsi_action *action,
3102 struct lp_build_tgsi_context *bld_base,
3103 struct lp_build_emit_data *emit_data)
3104 {
3105 struct gallivm_state *gallivm = bld_base->base.gallivm;
3106 LLVMBuilderRef builder = gallivm->builder;
3107 const struct tgsi_full_instruction * inst = emit_data->inst;
3108 unsigned target = inst->Memory.Texture;
3109 char intrinsic_name[40];
3110 LLVMValueRef tmp;
3111
3112 if (target == TGSI_TEXTURE_BUFFER) {
3113 snprintf(intrinsic_name, sizeof(intrinsic_name),
3114 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
3115 } else {
3116 char coords_type[8];
3117
3118 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
3119 coords_type, sizeof(coords_type));
3120 snprintf(intrinsic_name, sizeof(intrinsic_name),
3121 "llvm.amdgcn.image.atomic.%s.%s",
3122 action->intr_name, coords_type);
3123 }
3124
3125 tmp = lp_build_intrinsic(
3126 builder, intrinsic_name, bld_base->uint_bld.elem_type,
3127 emit_data->args, emit_data->arg_count,
3128 LLVMNoUnwindAttribute);
3129 emit_data->output[emit_data->chan] =
3130 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
3131 }
3132
3133 static void resq_fetch_args(
3134 struct lp_build_tgsi_context * bld_base,
3135 struct lp_build_emit_data * emit_data)
3136 {
3137 struct gallivm_state *gallivm = bld_base->base.gallivm;
3138 const struct tgsi_full_instruction *inst = emit_data->inst;
3139 const struct tgsi_full_src_register *reg = &inst->Src[0];
3140 unsigned tex_target = inst->Memory.Texture;
3141
3142 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3143
3144 if (tex_target == TGSI_TEXTURE_BUFFER) {
3145 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[0]);
3146 emit_data->arg_count = 1;
3147 } else {
3148 emit_data->args[0] = bld_base->uint_bld.zero; /* mip level */
3149 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[1]);
3150 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3151 emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
3152 emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
3153 emit_data->args[5] = tgsi_is_array_image(tex_target) ?
3154 bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da */
3155 emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
3156 emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
3157 emit_data->args[8] = bld_base->uint_bld.zero; /* tfe */
3158 emit_data->args[9] = bld_base->uint_bld.zero; /* lwe */
3159 emit_data->arg_count = 10;
3160 }
3161 }
3162
3163 static void resq_emit(
3164 const struct lp_build_tgsi_action *action,
3165 struct lp_build_tgsi_context *bld_base,
3166 struct lp_build_emit_data *emit_data)
3167 {
3168 struct gallivm_state *gallivm = bld_base->base.gallivm;
3169 LLVMBuilderRef builder = gallivm->builder;
3170 const struct tgsi_full_instruction *inst = emit_data->inst;
3171 unsigned target = inst->Memory.Texture;
3172 LLVMValueRef out;
3173
3174 if (target == TGSI_TEXTURE_BUFFER) {
3175 out = get_buffer_size(bld_base, emit_data->args[0]);
3176 } else {
3177 out = lp_build_intrinsic(
3178 builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
3179 emit_data->args, emit_data->arg_count,
3180 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3181
3182 /* Divide the number of layers by 6 to get the number of cubes. */
3183 if (target == TGSI_TEXTURE_CUBE_ARRAY) {
3184 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
3185 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
3186
3187 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
3188 z = LLVMBuildBitCast(builder, z, bld_base->uint_bld.elem_type, "");
3189 z = LLVMBuildSDiv(builder, z, imm6, "");
3190 z = LLVMBuildBitCast(builder, z, bld_base->base.elem_type, "");
3191 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
3192 }
3193 }
3194
3195 emit_data->output[emit_data->chan] = out;
3196 }
3197
3198 static void set_tex_fetch_args(struct si_shader_context *ctx,
3199 struct lp_build_emit_data *emit_data,
3200 unsigned opcode, unsigned target,
3201 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3202 LLVMValueRef *param, unsigned count,
3203 unsigned dmask)
3204 {
3205 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3206 unsigned num_args;
3207 unsigned is_rect = target == TGSI_TEXTURE_RECT;
3208
3209 /* Pad to power of two vector */
3210 while (count < util_next_power_of_two(count))
3211 param[count++] = LLVMGetUndef(ctx->i32);
3212
3213 /* Texture coordinates. */
3214 if (count > 1)
3215 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
3216 else
3217 emit_data->args[0] = param[0];
3218
3219 /* Resource. */
3220 emit_data->args[1] = res_ptr;
3221 num_args = 2;
3222
3223 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
3224 emit_data->dst_type = ctx->v4i32;
3225 else {
3226 emit_data->dst_type = ctx->v4f32;
3227
3228 emit_data->args[num_args++] = samp_ptr;
3229 }
3230
3231 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
3232 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
3233 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
3234 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
3235 tgsi_is_array_sampler(target)); /* da */
3236 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
3237 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
3238 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
3239 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
3240
3241 emit_data->arg_count = num_args;
3242 }
3243
3244 static const struct lp_build_tgsi_action tex_action;
3245
3246 enum desc_type {
3247 DESC_IMAGE,
3248 DESC_FMASK,
3249 DESC_SAMPLER
3250 };
3251
3252 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3253 {
3254 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3255 CONST_ADDR_SPACE);
3256 }
3257
3258 /**
3259 * Load an image view, fmask view. or sampler state descriptor.
3260 */
3261 static LLVMValueRef get_sampler_desc_custom(struct si_shader_context *ctx,
3262 LLVMValueRef list, LLVMValueRef index,
3263 enum desc_type type)
3264 {
3265 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3266 LLVMBuilderRef builder = gallivm->builder;
3267
3268 switch (type) {
3269 case DESC_IMAGE:
3270 /* The image is at [0:7]. */
3271 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
3272 break;
3273 case DESC_FMASK:
3274 /* The FMASK is at [8:15]. */
3275 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
3276 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
3277 break;
3278 case DESC_SAMPLER:
3279 /* The sampler state is at [12:15]. */
3280 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
3281 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
3282 list = LLVMBuildPointerCast(builder, list,
3283 const_array(ctx->v4i32, 0), "");
3284 break;
3285 }
3286
3287 return build_indexed_load_const(ctx, list, index);
3288 }
3289
3290 static LLVMValueRef get_sampler_desc(struct si_shader_context *ctx,
3291 LLVMValueRef index, enum desc_type type)
3292 {
3293 LLVMValueRef list = LLVMGetParam(ctx->radeon_bld.main_fn,
3294 SI_PARAM_SAMPLERS);
3295
3296 return get_sampler_desc_custom(ctx, list, index, type);
3297 }
3298
3299 static void tex_fetch_ptrs(
3300 struct lp_build_tgsi_context *bld_base,
3301 struct lp_build_emit_data *emit_data,
3302 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
3303 {
3304 struct si_shader_context *ctx = si_shader_context(bld_base);
3305 const struct tgsi_full_instruction *inst = emit_data->inst;
3306 unsigned target = inst->Texture.Texture;
3307 unsigned sampler_src;
3308 unsigned sampler_index;
3309
3310 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
3311 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
3312
3313 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
3314 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
3315 LLVMValueRef ind_index;
3316
3317 ind_index = get_indirect_index(ctx, &reg->Indirect, reg->Register.Index);
3318
3319 *res_ptr = get_sampler_desc(ctx, ind_index, DESC_IMAGE);
3320
3321 if (target == TGSI_TEXTURE_2D_MSAA ||
3322 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
3323 *samp_ptr = NULL;
3324 *fmask_ptr = get_sampler_desc(ctx, ind_index, DESC_FMASK);
3325 } else {
3326 *samp_ptr = get_sampler_desc(ctx, ind_index, DESC_SAMPLER);
3327 *fmask_ptr = NULL;
3328 }
3329 } else {
3330 *res_ptr = ctx->sampler_views[sampler_index];
3331 *samp_ptr = ctx->sampler_states[sampler_index];
3332 *fmask_ptr = ctx->fmasks[sampler_index];
3333 }
3334 }
3335
3336 static void tex_fetch_args(
3337 struct lp_build_tgsi_context *bld_base,
3338 struct lp_build_emit_data *emit_data)
3339 {
3340 struct si_shader_context *ctx = si_shader_context(bld_base);
3341 struct gallivm_state *gallivm = bld_base->base.gallivm;
3342 LLVMBuilderRef builder = gallivm->builder;
3343 const struct tgsi_full_instruction *inst = emit_data->inst;
3344 unsigned opcode = inst->Instruction.Opcode;
3345 unsigned target = inst->Texture.Texture;
3346 LLVMValueRef coords[5], derivs[6];
3347 LLVMValueRef address[16];
3348 int ref_pos;
3349 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
3350 unsigned count = 0;
3351 unsigned chan;
3352 unsigned num_deriv_channels = 0;
3353 bool has_offset = inst->Texture.NumOffsets > 0;
3354 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
3355 unsigned dmask = 0xf;
3356
3357 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
3358
3359 if (opcode == TGSI_OPCODE_TXQ) {
3360 if (target == TGSI_TEXTURE_BUFFER) {
3361 /* Read the size from the buffer descriptor directly. */
3362 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
3363 emit_data->args[0] = get_buffer_size(bld_base, res);
3364 return;
3365 }
3366
3367 /* Textures - set the mip level. */
3368 address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
3369
3370 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
3371 NULL, address, count, 0xf);
3372 return;
3373 }
3374
3375 if (target == TGSI_TEXTURE_BUFFER) {
3376 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
3377
3378 /* Bitcast and truncate v8i32 to v16i8. */
3379 LLVMValueRef res = res_ptr;
3380 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
3381 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
3382 res = LLVMBuildBitCast(gallivm->builder, res, ctx->v16i8, "");
3383
3384 emit_data->dst_type = ctx->v4f32;
3385 emit_data->args[0] = res;
3386 emit_data->args[1] = bld_base->uint_bld.zero;
3387 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
3388 emit_data->arg_count = 3;
3389 return;
3390 }
3391
3392 /* Fetch and project texture coordinates */
3393 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
3394 for (chan = 0; chan < 3; chan++ ) {
3395 coords[chan] = lp_build_emit_fetch(bld_base,
3396 emit_data->inst, 0,
3397 chan);
3398 if (opcode == TGSI_OPCODE_TXP)
3399 coords[chan] = lp_build_emit_llvm_binary(bld_base,
3400 TGSI_OPCODE_DIV,
3401 coords[chan],
3402 coords[3]);
3403 }
3404
3405 if (opcode == TGSI_OPCODE_TXP)
3406 coords[3] = bld_base->base.one;
3407
3408 /* Pack offsets. */
3409 if (has_offset && opcode != TGSI_OPCODE_TXF) {
3410 /* The offsets are six-bit signed integers packed like this:
3411 * X=[5:0], Y=[13:8], and Z=[21:16].
3412 */
3413 LLVMValueRef offset[3], pack;
3414
3415 assert(inst->Texture.NumOffsets == 1);
3416
3417 for (chan = 0; chan < 3; chan++) {
3418 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
3419 emit_data->inst, 0, chan);
3420 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
3421 lp_build_const_int32(gallivm, 0x3f), "");
3422 if (chan)
3423 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
3424 lp_build_const_int32(gallivm, chan*8), "");
3425 }
3426
3427 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
3428 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
3429 address[count++] = pack;
3430 }
3431
3432 /* Pack LOD bias value */
3433 if (opcode == TGSI_OPCODE_TXB)
3434 address[count++] = coords[3];
3435 if (opcode == TGSI_OPCODE_TXB2)
3436 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
3437
3438 /* Pack depth comparison value */
3439 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
3440 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
3441 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
3442 } else {
3443 assert(ref_pos >= 0);
3444 address[count++] = coords[ref_pos];
3445 }
3446 }
3447
3448 /* Pack user derivatives */
3449 if (opcode == TGSI_OPCODE_TXD) {
3450 int param, num_src_deriv_channels;
3451
3452 switch (target) {
3453 case TGSI_TEXTURE_3D:
3454 num_src_deriv_channels = 3;
3455 num_deriv_channels = 3;
3456 break;
3457 case TGSI_TEXTURE_2D:
3458 case TGSI_TEXTURE_SHADOW2D:
3459 case TGSI_TEXTURE_RECT:
3460 case TGSI_TEXTURE_SHADOWRECT:
3461 case TGSI_TEXTURE_2D_ARRAY:
3462 case TGSI_TEXTURE_SHADOW2D_ARRAY:
3463 num_src_deriv_channels = 2;
3464 num_deriv_channels = 2;
3465 break;
3466 case TGSI_TEXTURE_CUBE:
3467 case TGSI_TEXTURE_SHADOWCUBE:
3468 case TGSI_TEXTURE_CUBE_ARRAY:
3469 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
3470 /* Cube derivatives will be converted to 2D. */
3471 num_src_deriv_channels = 3;
3472 num_deriv_channels = 2;
3473 break;
3474 case TGSI_TEXTURE_1D:
3475 case TGSI_TEXTURE_SHADOW1D:
3476 case TGSI_TEXTURE_1D_ARRAY:
3477 case TGSI_TEXTURE_SHADOW1D_ARRAY:
3478 num_src_deriv_channels = 1;
3479 num_deriv_channels = 1;
3480 break;
3481 default:
3482 unreachable("invalid target");
3483 }
3484
3485 for (param = 0; param < 2; param++)
3486 for (chan = 0; chan < num_src_deriv_channels; chan++)
3487 derivs[param * num_src_deriv_channels + chan] =
3488 lp_build_emit_fetch(bld_base, inst, param+1, chan);
3489 }
3490
3491 if (target == TGSI_TEXTURE_CUBE ||
3492 target == TGSI_TEXTURE_CUBE_ARRAY ||
3493 target == TGSI_TEXTURE_SHADOWCUBE ||
3494 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
3495 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
3496
3497 if (opcode == TGSI_OPCODE_TXD)
3498 for (int i = 0; i < num_deriv_channels * 2; i++)
3499 address[count++] = derivs[i];
3500
3501 /* Pack texture coordinates */
3502 address[count++] = coords[0];
3503 if (num_coords > 1)
3504 address[count++] = coords[1];
3505 if (num_coords > 2)
3506 address[count++] = coords[2];
3507
3508 /* Pack LOD or sample index */
3509 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
3510 address[count++] = coords[3];
3511 else if (opcode == TGSI_OPCODE_TXL2)
3512 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
3513
3514 if (count > 16) {
3515 assert(!"Cannot handle more than 16 texture address parameters");
3516 count = 16;
3517 }
3518
3519 for (chan = 0; chan < count; chan++ ) {
3520 address[chan] = LLVMBuildBitCast(gallivm->builder,
3521 address[chan], ctx->i32, "");
3522 }
3523
3524 /* Adjust the sample index according to FMASK.
3525 *
3526 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3527 * which is the identity mapping. Each nibble says which physical sample
3528 * should be fetched to get that sample.
3529 *
3530 * For example, 0x11111100 means there are only 2 samples stored and
3531 * the second sample covers 3/4 of the pixel. When reading samples 0
3532 * and 1, return physical sample 0 (determined by the first two 0s
3533 * in FMASK), otherwise return physical sample 1.
3534 *
3535 * The sample index should be adjusted as follows:
3536 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3537 */
3538 if (target == TGSI_TEXTURE_2D_MSAA ||
3539 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
3540 struct lp_build_context *uint_bld = &bld_base->uint_bld;
3541 struct lp_build_emit_data txf_emit_data = *emit_data;
3542 LLVMValueRef txf_address[4];
3543 unsigned txf_count = count;
3544 struct tgsi_full_instruction inst = {};
3545
3546 memcpy(txf_address, address, sizeof(txf_address));
3547
3548 if (target == TGSI_TEXTURE_2D_MSAA) {
3549 txf_address[2] = bld_base->uint_bld.zero;
3550 }
3551 txf_address[3] = bld_base->uint_bld.zero;
3552
3553 /* Read FMASK using TXF. */
3554 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
3555 inst.Texture.Texture = target;
3556 txf_emit_data.inst = &inst;
3557 txf_emit_data.chan = 0;
3558 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
3559 target, fmask_ptr, NULL,
3560 txf_address, txf_count, 0xf);
3561 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
3562
3563 /* Initialize some constants. */
3564 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
3565 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
3566
3567 /* Apply the formula. */
3568 LLVMValueRef fmask =
3569 LLVMBuildExtractElement(gallivm->builder,
3570 txf_emit_data.output[0],
3571 uint_bld->zero, "");
3572
3573 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
3574
3575 LLVMValueRef sample_index4 =
3576 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
3577
3578 LLVMValueRef shifted_fmask =
3579 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
3580
3581 LLVMValueRef final_sample =
3582 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
3583
3584 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3585 * resource descriptor is 0 (invalid),
3586 */
3587 LLVMValueRef fmask_desc =
3588 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
3589 ctx->v8i32, "");
3590
3591 LLVMValueRef fmask_word1 =
3592 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
3593 uint_bld->one, "");
3594
3595 LLVMValueRef word1_is_nonzero =
3596 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
3597 fmask_word1, uint_bld->zero, "");
3598
3599 /* Replace the MSAA sample index. */
3600 address[sample_chan] =
3601 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
3602 final_sample, address[sample_chan], "");
3603 }
3604
3605 if (opcode == TGSI_OPCODE_TXF) {
3606 /* add tex offsets */
3607 if (inst->Texture.NumOffsets) {
3608 struct lp_build_context *uint_bld = &bld_base->uint_bld;
3609 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
3610 const struct tgsi_texture_offset *off = inst->TexOffsets;
3611
3612 assert(inst->Texture.NumOffsets == 1);
3613
3614 switch (target) {
3615 case TGSI_TEXTURE_3D:
3616 address[2] = lp_build_add(uint_bld, address[2],
3617 bld->immediates[off->Index][off->SwizzleZ]);
3618 /* fall through */
3619 case TGSI_TEXTURE_2D:
3620 case TGSI_TEXTURE_SHADOW2D:
3621 case TGSI_TEXTURE_RECT:
3622 case TGSI_TEXTURE_SHADOWRECT:
3623 case TGSI_TEXTURE_2D_ARRAY:
3624 case TGSI_TEXTURE_SHADOW2D_ARRAY:
3625 address[1] =
3626 lp_build_add(uint_bld, address[1],
3627 bld->immediates[off->Index][off->SwizzleY]);
3628 /* fall through */
3629 case TGSI_TEXTURE_1D:
3630 case TGSI_TEXTURE_SHADOW1D:
3631 case TGSI_TEXTURE_1D_ARRAY:
3632 case TGSI_TEXTURE_SHADOW1D_ARRAY:
3633 address[0] =
3634 lp_build_add(uint_bld, address[0],
3635 bld->immediates[off->Index][off->SwizzleX]);
3636 break;
3637 /* texture offsets do not apply to other texture targets */
3638 }
3639 }
3640 }
3641
3642 if (opcode == TGSI_OPCODE_TG4) {
3643 unsigned gather_comp = 0;
3644
3645 /* DMASK was repurposed for GATHER4. 4 components are always
3646 * returned and DMASK works like a swizzle - it selects
3647 * the component to fetch. The only valid DMASK values are
3648 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
3649 * (red,red,red,red) etc.) The ISA document doesn't mention
3650 * this.
3651 */
3652
3653 /* Get the component index from src1.x for Gather4. */
3654 if (!tgsi_is_shadow_target(target)) {
3655 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3656 LLVMValueRef comp_imm;
3657 struct tgsi_src_register src1 = inst->Src[1].Register;
3658
3659 assert(src1.File == TGSI_FILE_IMMEDIATE);
3660
3661 comp_imm = imms[src1.Index][src1.SwizzleX];
3662 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
3663 gather_comp = CLAMP(gather_comp, 0, 3);
3664 }
3665
3666 dmask = 1 << gather_comp;
3667 }
3668
3669 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
3670 samp_ptr, address, count, dmask);
3671 }
3672
3673 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3674 struct lp_build_tgsi_context *bld_base,
3675 struct lp_build_emit_data *emit_data)
3676 {
3677 struct lp_build_context *base = &bld_base->base;
3678 unsigned opcode = emit_data->inst->Instruction.Opcode;
3679 unsigned target = emit_data->inst->Texture.Texture;
3680 char intr_name[127];
3681 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
3682 bool is_shadow = tgsi_is_shadow_target(target);
3683 char type[64];
3684 const char *name = "llvm.SI.image.sample";
3685 const char *infix = "";
3686
3687 if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
3688 /* Just return the buffer size. */
3689 emit_data->output[emit_data->chan] = emit_data->args[0];
3690 return;
3691 }
3692
3693 if (target == TGSI_TEXTURE_BUFFER) {
3694 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3695 base->gallivm->builder,
3696 "llvm.SI.vs.load.input", emit_data->dst_type,
3697 emit_data->args, emit_data->arg_count,
3698 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3699 return;
3700 }
3701
3702 switch (opcode) {
3703 case TGSI_OPCODE_TXF:
3704 name = target == TGSI_TEXTURE_2D_MSAA ||
3705 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
3706 "llvm.SI.image.load" :
3707 "llvm.SI.image.load.mip";
3708 is_shadow = false;
3709 has_offset = false;
3710 break;
3711 case TGSI_OPCODE_TXQ:
3712 name = "llvm.SI.getresinfo";
3713 is_shadow = false;
3714 has_offset = false;
3715 break;
3716 case TGSI_OPCODE_LODQ:
3717 name = "llvm.SI.getlod";
3718 is_shadow = false;
3719 has_offset = false;
3720 break;
3721 case TGSI_OPCODE_TEX:
3722 case TGSI_OPCODE_TEX2:
3723 case TGSI_OPCODE_TXP:
3724 break;
3725 case TGSI_OPCODE_TXB:
3726 case TGSI_OPCODE_TXB2:
3727 infix = ".b";
3728 break;
3729 case TGSI_OPCODE_TXL:
3730 case TGSI_OPCODE_TXL2:
3731 infix = ".l";
3732 break;
3733 case TGSI_OPCODE_TXD:
3734 infix = ".d";
3735 break;
3736 case TGSI_OPCODE_TG4:
3737 name = "llvm.SI.gather4";
3738 break;
3739 default:
3740 assert(0);
3741 return;
3742 }
3743
3744 /* Add the type and suffixes .c, .o if needed. */
3745 build_int_type_name(LLVMTypeOf(emit_data->args[0]), type, sizeof(type));
3746 sprintf(intr_name, "%s%s%s%s.%s",
3747 name, is_shadow ? ".c" : "", infix,
3748 has_offset ? ".o" : "", type);
3749
3750 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3751 base->gallivm->builder, intr_name, emit_data->dst_type,
3752 emit_data->args, emit_data->arg_count,
3753 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3754
3755 /* Divide the number of layers by 6 to get the number of cubes. */
3756 if (opcode == TGSI_OPCODE_TXQ &&
3757 (target == TGSI_TEXTURE_CUBE_ARRAY ||
3758 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
3759 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
3760 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
3761 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
3762
3763 LLVMValueRef v4 = emit_data->output[emit_data->chan];
3764 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
3765 z = LLVMBuildSDiv(builder, z, six, "");
3766
3767 emit_data->output[emit_data->chan] =
3768 LLVMBuildInsertElement(builder, v4, z, two, "");
3769 }
3770 }
3771
3772 static void si_llvm_emit_txqs(
3773 const struct lp_build_tgsi_action *action,
3774 struct lp_build_tgsi_context *bld_base,
3775 struct lp_build_emit_data *emit_data)
3776 {
3777 struct si_shader_context *ctx = si_shader_context(bld_base);
3778 struct gallivm_state *gallivm = bld_base->base.gallivm;
3779 LLVMBuilderRef builder = gallivm->builder;
3780 LLVMValueRef res, samples;
3781 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
3782
3783 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
3784
3785
3786 /* Read the samples from the descriptor directly. */
3787 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
3788 samples = LLVMBuildExtractElement(
3789 builder, res,
3790 lp_build_const_int32(gallivm, 3), "");
3791 samples = LLVMBuildLShr(builder, samples,
3792 lp_build_const_int32(gallivm, 16), "");
3793 samples = LLVMBuildAnd(builder, samples,
3794 lp_build_const_int32(gallivm, 0xf), "");
3795 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
3796 samples, "");
3797
3798 emit_data->output[emit_data->chan] = samples;
3799 }
3800
3801 /*
3802 * SI implements derivatives using the local data store (LDS)
3803 * All writes to the LDS happen in all executing threads at
3804 * the same time. TID is the Thread ID for the current
3805 * thread and is a value between 0 and 63, representing
3806 * the thread's position in the wavefront.
3807 *
3808 * For the pixel shader threads are grouped into quads of four pixels.
3809 * The TIDs of the pixels of a quad are:
3810 *
3811 * +------+------+
3812 * |4n + 0|4n + 1|
3813 * +------+------+
3814 * |4n + 2|4n + 3|
3815 * +------+------+
3816 *
3817 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
3818 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
3819 * the current pixel's column, and masking with 0xfffffffe yields the TID
3820 * of the left pixel of the current pixel's row.
3821 *
3822 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
3823 * adding 2 yields the TID of the pixel below the top pixel.
3824 */
3825 /* masks for thread ID. */
3826 #define TID_MASK_TOP_LEFT 0xfffffffc
3827 #define TID_MASK_TOP 0xfffffffd
3828 #define TID_MASK_LEFT 0xfffffffe
3829
3830 static void si_llvm_emit_ddxy(
3831 const struct lp_build_tgsi_action *action,
3832 struct lp_build_tgsi_context *bld_base,
3833 struct lp_build_emit_data *emit_data)
3834 {
3835 struct si_shader_context *ctx = si_shader_context(bld_base);
3836 struct gallivm_state *gallivm = bld_base->base.gallivm;
3837 const struct tgsi_full_instruction *inst = emit_data->inst;
3838 unsigned opcode = inst->Instruction.Opcode;
3839 LLVMValueRef indices[2];
3840 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
3841 LLVMValueRef tl, trbl, result[4];
3842 unsigned swizzle[4];
3843 unsigned c;
3844 int idx;
3845 unsigned mask;
3846
3847 indices[0] = bld_base->uint_bld.zero;
3848 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", ctx->i32,
3849 NULL, 0, LLVMReadNoneAttribute);
3850 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
3851 indices, 2, "");
3852
3853 if (opcode == TGSI_OPCODE_DDX_FINE)
3854 mask = TID_MASK_LEFT;
3855 else if (opcode == TGSI_OPCODE_DDY_FINE)
3856 mask = TID_MASK_TOP;
3857 else
3858 mask = TID_MASK_TOP_LEFT;
3859
3860 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
3861 lp_build_const_int32(gallivm, mask), "");
3862 load_ptr0 = LLVMBuildGEP(gallivm->builder, ctx->lds,
3863 indices, 2, "");
3864
3865 /* for DDX we want to next X pixel, DDY next Y pixel. */
3866 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3867 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
3868 lp_build_const_int32(gallivm, idx), "");
3869 load_ptr1 = LLVMBuildGEP(gallivm->builder, ctx->lds,
3870 indices, 2, "");
3871
3872 for (c = 0; c < 4; ++c) {
3873 unsigned i;
3874
3875 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
3876 for (i = 0; i < c; ++i) {
3877 if (swizzle[i] == swizzle[c]) {
3878 result[c] = result[i];
3879 break;
3880 }
3881 }
3882 if (i != c)
3883 continue;
3884
3885 LLVMBuildStore(gallivm->builder,
3886 LLVMBuildBitCast(gallivm->builder,
3887 lp_build_emit_fetch(bld_base, inst, 0, c),
3888 ctx->i32, ""),
3889 store_ptr);
3890
3891 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
3892 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
3893
3894 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
3895 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
3896
3897 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
3898 }
3899
3900 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
3901 }
3902
3903 /*
3904 * this takes an I,J coordinate pair,
3905 * and works out the X and Y derivatives.
3906 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3907 */
3908 static LLVMValueRef si_llvm_emit_ddxy_interp(
3909 struct lp_build_tgsi_context *bld_base,
3910 LLVMValueRef interp_ij)
3911 {
3912 struct si_shader_context *ctx = si_shader_context(bld_base);
3913 struct gallivm_state *gallivm = bld_base->base.gallivm;
3914 LLVMValueRef indices[2];
3915 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
3916 LLVMValueRef tl, tr, bl, result[4];
3917 unsigned c;
3918
3919 indices[0] = bld_base->uint_bld.zero;
3920 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", ctx->i32,
3921 NULL, 0, LLVMReadNoneAttribute);
3922 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
3923 indices, 2, "");
3924
3925 temp = LLVMBuildAnd(gallivm->builder, indices[1],
3926 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
3927
3928 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
3929 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
3930
3931 indices[1] = temp;
3932 load_ptr_x = LLVMBuildGEP(gallivm->builder, ctx->lds,
3933 indices, 2, "");
3934
3935 indices[1] = temp2;
3936 load_ptr_y = LLVMBuildGEP(gallivm->builder, ctx->lds,
3937 indices, 2, "");
3938
3939 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
3940 lp_build_const_int32(gallivm, 1), "");
3941 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, ctx->lds,
3942 indices, 2, "");
3943
3944 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
3945 lp_build_const_int32(gallivm, 2), "");
3946 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, ctx->lds,
3947 indices, 2, "");
3948
3949 for (c = 0; c < 2; ++c) {
3950 LLVMValueRef store_val;
3951 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
3952
3953 store_val = LLVMBuildExtractElement(gallivm->builder,
3954 interp_ij, c_ll, "");
3955 LLVMBuildStore(gallivm->builder,
3956 store_val,
3957 store_ptr);
3958
3959 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
3960 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
3961
3962 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
3963 tr = LLVMBuildBitCast(gallivm->builder, tr, ctx->f32, "");
3964
3965 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
3966
3967 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
3968 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
3969
3970 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
3971 bl = LLVMBuildBitCast(gallivm->builder, bl, ctx->f32, "");
3972
3973 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
3974 }
3975
3976 return lp_build_gather_values(gallivm, result, 4);
3977 }
3978
3979 static void interp_fetch_args(
3980 struct lp_build_tgsi_context *bld_base,
3981 struct lp_build_emit_data *emit_data)
3982 {
3983 struct si_shader_context *ctx = si_shader_context(bld_base);
3984 struct gallivm_state *gallivm = bld_base->base.gallivm;
3985 const struct tgsi_full_instruction *inst = emit_data->inst;
3986
3987 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3988 /* offset is in second src, first two channels */
3989 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3990 emit_data->inst, 1,
3991 TGSI_CHAN_X);
3992 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3993 emit_data->inst, 1,
3994 TGSI_CHAN_Y);
3995 emit_data->arg_count = 2;
3996 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3997 LLVMValueRef sample_position;
3998 LLVMValueRef sample_id;
3999 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
4000
4001 /* fetch sample ID, then fetch its sample position,
4002 * and place into first two channels.
4003 */
4004 sample_id = lp_build_emit_fetch(bld_base,
4005 emit_data->inst, 1, TGSI_CHAN_X);
4006 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
4007 ctx->i32, "");
4008 sample_position = load_sample_position(&ctx->radeon_bld, sample_id);
4009
4010 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
4011 sample_position,
4012 lp_build_const_int32(gallivm, 0), "");
4013
4014 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
4015 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
4016 sample_position,
4017 lp_build_const_int32(gallivm, 1), "");
4018 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
4019 emit_data->arg_count = 2;
4020 }
4021 }
4022
4023 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
4024 struct lp_build_tgsi_context *bld_base,
4025 struct lp_build_emit_data *emit_data)
4026 {
4027 struct si_shader_context *ctx = si_shader_context(bld_base);
4028 struct si_shader *shader = ctx->shader;
4029 struct gallivm_state *gallivm = bld_base->base.gallivm;
4030 LLVMValueRef interp_param;
4031 const struct tgsi_full_instruction *inst = emit_data->inst;
4032 const char *intr_name;
4033 int input_index = inst->Src[0].Register.Index;
4034 int chan;
4035 int i;
4036 LLVMValueRef attr_number;
4037 LLVMValueRef params = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
4038 int interp_param_idx;
4039 unsigned interp = shader->selector->info.input_interpolate[input_index];
4040 unsigned location;
4041
4042 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
4043
4044 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4045 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4046 location = TGSI_INTERPOLATE_LOC_CENTER;
4047 else
4048 location = TGSI_INTERPOLATE_LOC_CENTROID;
4049
4050 interp_param_idx = lookup_interp_param_index(interp, location);
4051 if (interp_param_idx == -1)
4052 return;
4053 else if (interp_param_idx)
4054 interp_param = LLVMGetParam(ctx->radeon_bld.main_fn, interp_param_idx);
4055 else
4056 interp_param = NULL;
4057
4058 attr_number = lp_build_const_int32(gallivm, input_index);
4059
4060 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4061 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4062 LLVMValueRef ij_out[2];
4063 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
4064
4065 /*
4066 * take the I then J parameters, and the DDX/Y for it, and
4067 * calculate the IJ inputs for the interpolator.
4068 * temp1 = ddx * offset/sample.x + I;
4069 * interp_param.I = ddy * offset/sample.y + temp1;
4070 * temp1 = ddx * offset/sample.x + J;
4071 * interp_param.J = ddy * offset/sample.y + temp1;
4072 */
4073 for (i = 0; i < 2; i++) {
4074 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
4075 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
4076 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
4077 ddxy_out, ix_ll, "");
4078 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
4079 ddxy_out, iy_ll, "");
4080 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
4081 interp_param, ix_ll, "");
4082 LLVMValueRef temp1, temp2;
4083
4084 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
4085 ctx->f32, "");
4086
4087 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
4088
4089 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
4090
4091 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
4092
4093 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
4094
4095 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
4096 temp2, ctx->i32, "");
4097 }
4098 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
4099 }
4100
4101 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
4102 for (chan = 0; chan < 2; chan++) {
4103 LLVMValueRef args[4];
4104 LLVMValueRef llvm_chan;
4105 unsigned schan;
4106
4107 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4108 llvm_chan = lp_build_const_int32(gallivm, schan);
4109
4110 args[0] = llvm_chan;
4111 args[1] = attr_number;
4112 args[2] = params;
4113 args[3] = interp_param;
4114
4115 emit_data->output[chan] =
4116 lp_build_intrinsic(gallivm->builder, intr_name,
4117 ctx->f32, args, args[3] ? 4 : 3,
4118 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4119 }
4120 }
4121
4122 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4123 struct lp_build_emit_data *emit_data)
4124 {
4125 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4126 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4127 unsigned stream;
4128
4129 assert(src0.File == TGSI_FILE_IMMEDIATE);
4130
4131 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
4132 return stream;
4133 }
4134
4135 /* Emit one vertex from the geometry shader */
4136 static void si_llvm_emit_vertex(
4137 const struct lp_build_tgsi_action *action,
4138 struct lp_build_tgsi_context *bld_base,
4139 struct lp_build_emit_data *emit_data)
4140 {
4141 struct si_shader_context *ctx = si_shader_context(bld_base);
4142 struct lp_build_context *uint = &bld_base->uint_bld;
4143 struct si_shader *shader = ctx->shader;
4144 struct tgsi_shader_info *info = &shader->selector->info;
4145 struct gallivm_state *gallivm = bld_base->base.gallivm;
4146 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
4147 SI_PARAM_GS2VS_OFFSET);
4148 LLVMValueRef gs_next_vertex;
4149 LLVMValueRef can_emit, kill;
4150 LLVMValueRef args[2];
4151 unsigned chan;
4152 int i;
4153 unsigned stream;
4154
4155 stream = si_llvm_get_stream(bld_base, emit_data);
4156
4157 /* Write vertex attribute values to GSVS ring */
4158 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
4159 ctx->gs_next_vertex[stream],
4160 "");
4161
4162 /* If this thread has already emitted the declared maximum number of
4163 * vertices, kill it: excessive vertex emissions are not supposed to
4164 * have any effect, and GS threads have no externally observable
4165 * effects other than emitting vertices.
4166 */
4167 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
4168 lp_build_const_int32(gallivm,
4169 shader->selector->gs_max_out_vertices), "");
4170 kill = lp_build_select(&bld_base->base, can_emit,
4171 lp_build_const_float(gallivm, 1.0f),
4172 lp_build_const_float(gallivm, -1.0f));
4173
4174 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
4175 ctx->voidt, &kill, 1, 0);
4176
4177 for (i = 0; i < info->num_outputs; i++) {
4178 LLVMValueRef *out_ptr =
4179 ctx->radeon_bld.soa.outputs[i];
4180
4181 for (chan = 0; chan < 4; chan++) {
4182 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
4183 LLVMValueRef voffset =
4184 lp_build_const_int32(gallivm, (i * 4 + chan) *
4185 shader->selector->gs_max_out_vertices);
4186
4187 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4188 voffset = lp_build_mul_imm(uint, voffset, 4);
4189
4190 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
4191
4192 build_tbuffer_store(ctx,
4193 ctx->gsvs_ring[stream],
4194 out_val, 1,
4195 voffset, soffset, 0,
4196 V_008F0C_BUF_DATA_FORMAT_32,
4197 V_008F0C_BUF_NUM_FORMAT_UINT,
4198 1, 0, 1, 1, 0);
4199 }
4200 }
4201 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4202 lp_build_const_int32(gallivm, 1));
4203
4204 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4205
4206 /* Signal vertex emission */
4207 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
4208 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
4209 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
4210 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
4211 }
4212
4213 /* Cut one primitive from the geometry shader */
4214 static void si_llvm_emit_primitive(
4215 const struct lp_build_tgsi_action *action,
4216 struct lp_build_tgsi_context *bld_base,
4217 struct lp_build_emit_data *emit_data)
4218 {
4219 struct si_shader_context *ctx = si_shader_context(bld_base);
4220 struct gallivm_state *gallivm = bld_base->base.gallivm;
4221 LLVMValueRef args[2];
4222 unsigned stream;
4223
4224 /* Signal primitive cut */
4225 stream = si_llvm_get_stream(bld_base, emit_data);
4226 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
4227 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
4228 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
4229 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
4230 }
4231
4232 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4233 struct lp_build_tgsi_context *bld_base,
4234 struct lp_build_emit_data *emit_data)
4235 {
4236 struct si_shader_context *ctx = si_shader_context(bld_base);
4237 struct gallivm_state *gallivm = bld_base->base.gallivm;
4238
4239 lp_build_intrinsic(gallivm->builder,
4240 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
4241 : "llvm.AMDGPU.barrier.local",
4242 ctx->voidt, NULL, 0, LLVMNoUnwindAttribute);
4243 }
4244
4245 static const struct lp_build_tgsi_action tex_action = {
4246 .fetch_args = tex_fetch_args,
4247 .emit = build_tex_intrinsic,
4248 };
4249
4250 static const struct lp_build_tgsi_action interp_action = {
4251 .fetch_args = interp_fetch_args,
4252 .emit = build_interp_intrinsic,
4253 };
4254
4255 static void si_create_function(struct si_shader_context *ctx,
4256 LLVMTypeRef *returns, unsigned num_returns,
4257 LLVMTypeRef *params, unsigned num_params,
4258 int last_array_pointer, int last_sgpr)
4259 {
4260 int i;
4261
4262 radeon_llvm_create_func(&ctx->radeon_bld, returns, num_returns,
4263 params, num_params);
4264 radeon_llvm_shader_type(ctx->radeon_bld.main_fn, ctx->type);
4265 ctx->return_value = LLVMGetUndef(ctx->radeon_bld.return_type);
4266
4267 for (i = 0; i <= last_sgpr; ++i) {
4268 LLVMValueRef P = LLVMGetParam(ctx->radeon_bld.main_fn, i);
4269
4270 /* We tell llvm that array inputs are passed by value to allow Sinking pass
4271 * to move load. Inputs are constant so this is fine. */
4272 if (i <= last_array_pointer)
4273 LLVMAddAttribute(P, LLVMByValAttribute);
4274 else
4275 LLVMAddAttribute(P, LLVMInRegAttribute);
4276 }
4277 }
4278
4279 static void create_meta_data(struct si_shader_context *ctx)
4280 {
4281 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
4282 LLVMValueRef args[3];
4283
4284 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
4285 args[1] = 0;
4286 args[2] = lp_build_const_int32(gallivm, 1);
4287
4288 ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
4289 }
4290
4291 static void declare_streamout_params(struct si_shader_context *ctx,
4292 struct pipe_stream_output_info *so,
4293 LLVMTypeRef *params, LLVMTypeRef i32,
4294 unsigned *num_params)
4295 {
4296 int i;
4297
4298 /* Streamout SGPRs. */
4299 if (so->num_outputs) {
4300 params[ctx->param_streamout_config = (*num_params)++] = i32;
4301 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
4302 }
4303 /* A streamout buffer offset is loaded if the stride is non-zero. */
4304 for (i = 0; i < 4; i++) {
4305 if (!so->stride[i])
4306 continue;
4307
4308 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
4309 }
4310 }
4311
4312 static unsigned llvm_get_type_size(LLVMTypeRef type)
4313 {
4314 LLVMTypeKind kind = LLVMGetTypeKind(type);
4315
4316 switch (kind) {
4317 case LLVMIntegerTypeKind:
4318 return LLVMGetIntTypeWidth(type) / 8;
4319 case LLVMFloatTypeKind:
4320 return 4;
4321 case LLVMPointerTypeKind:
4322 return 8;
4323 case LLVMVectorTypeKind:
4324 return LLVMGetVectorSize(type) *
4325 llvm_get_type_size(LLVMGetElementType(type));
4326 default:
4327 assert(0);
4328 return 0;
4329 }
4330 }
4331
4332 static void declare_tess_lds(struct si_shader_context *ctx)
4333 {
4334 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4335 LLVMTypeRef i32 = ctx->radeon_bld.soa.bld_base.uint_bld.elem_type;
4336
4337 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
4338 unsigned vertex_data_dw_size = 32*32*4;
4339 unsigned patch_data_dw_size = 32*4;
4340 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
4341 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
4342 unsigned lds_dwords = patch_dw_size;
4343
4344 /* The actual size is computed outside of the shader to reduce
4345 * the number of shader variants. */
4346 ctx->lds =
4347 LLVMAddGlobalInAddressSpace(gallivm->module,
4348 LLVMArrayType(i32, lds_dwords),
4349 "tess_lds",
4350 LOCAL_ADDR_SPACE);
4351 }
4352
4353 static void create_function(struct si_shader_context *ctx)
4354 {
4355 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4356 struct gallivm_state *gallivm = bld_base->base.gallivm;
4357 struct si_shader *shader = ctx->shader;
4358 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
4359 LLVMTypeRef returns[16+32*4];
4360 unsigned i, last_array_pointer, last_sgpr, num_params, num_return_sgprs;
4361 unsigned num_returns = 0;
4362
4363 v3i32 = LLVMVectorType(ctx->i32, 3);
4364
4365 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
4366 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
4367 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
4368 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
4369 last_array_pointer = SI_PARAM_IMAGES;
4370
4371 switch (ctx->type) {
4372 case TGSI_PROCESSOR_VERTEX:
4373 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
4374 last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
4375 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
4376 params[SI_PARAM_START_INSTANCE] = ctx->i32;
4377 num_params = SI_PARAM_START_INSTANCE+1;
4378
4379 if (shader->key.vs.as_es) {
4380 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
4381 } else if (shader->key.vs.as_ls) {
4382 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
4383 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
4384 } else {
4385 if (ctx->is_gs_copy_shader) {
4386 last_array_pointer = SI_PARAM_CONST_BUFFERS;
4387 num_params = SI_PARAM_CONST_BUFFERS+1;
4388 } else {
4389 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
4390 num_params = SI_PARAM_VS_STATE_BITS+1;
4391 }
4392
4393 /* The locations of the other parameters are assigned dynamically. */
4394 declare_streamout_params(ctx, &shader->selector->so,
4395 params, ctx->i32, &num_params);
4396 }
4397
4398 last_sgpr = num_params-1;
4399
4400 /* VGPRs */
4401 params[ctx->param_vertex_id = num_params++] = ctx->i32;
4402 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
4403 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
4404 params[ctx->param_instance_id = num_params++] = ctx->i32;
4405
4406 if (!ctx->is_monolithic &&
4407 !ctx->is_gs_copy_shader) {
4408 /* Vertex load indices. */
4409 ctx->param_vertex_index0 = num_params;
4410
4411 for (i = 0; i < shader->selector->info.num_inputs; i++)
4412 params[num_params++] = ctx->i32;
4413
4414 /* PrimitiveID output. */
4415 if (!shader->key.vs.as_es && !shader->key.vs.as_ls)
4416 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
4417 returns[num_returns++] = ctx->f32;
4418 }
4419 break;
4420
4421 case TGSI_PROCESSOR_TESS_CTRL:
4422 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
4423 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
4424 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
4425 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
4426 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
4427
4428 /* VGPRs */
4429 params[SI_PARAM_PATCH_ID] = ctx->i32;
4430 params[SI_PARAM_REL_IDS] = ctx->i32;
4431 num_params = SI_PARAM_REL_IDS+1;
4432
4433 if (!ctx->is_monolithic) {
4434 /* PARAM_TESS_FACTOR_OFFSET is after user SGPRs. */
4435 for (i = 0; i <= SI_TCS_NUM_USER_SGPR; i++)
4436 returns[num_returns++] = ctx->i32; /* SGPRs */
4437
4438 for (i = 0; i < 3; i++)
4439 returns[num_returns++] = ctx->f32; /* VGPRs */
4440 }
4441 break;
4442
4443 case TGSI_PROCESSOR_TESS_EVAL:
4444 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
4445 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
4446 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
4447
4448 if (shader->key.tes.as_es) {
4449 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
4450 } else {
4451 declare_streamout_params(ctx, &shader->selector->so,
4452 params, ctx->i32, &num_params);
4453 }
4454 last_sgpr = num_params - 1;
4455
4456 /* VGPRs */
4457 params[ctx->param_tes_u = num_params++] = ctx->f32;
4458 params[ctx->param_tes_v = num_params++] = ctx->f32;
4459 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
4460 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
4461
4462 /* PrimitiveID output. */
4463 if (!ctx->is_monolithic && !shader->key.tes.as_es)
4464 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
4465 returns[num_returns++] = ctx->f32;
4466 break;
4467
4468 case TGSI_PROCESSOR_GEOMETRY:
4469 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
4470 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
4471 last_sgpr = SI_PARAM_GS_WAVE_ID;
4472
4473 /* VGPRs */
4474 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
4475 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
4476 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
4477 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
4478 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
4479 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
4480 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
4481 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
4482 num_params = SI_PARAM_GS_INSTANCE_ID+1;
4483 break;
4484
4485 case TGSI_PROCESSOR_FRAGMENT:
4486 params[SI_PARAM_ALPHA_REF] = ctx->f32;
4487 params[SI_PARAM_PRIM_MASK] = ctx->i32;
4488 last_sgpr = SI_PARAM_PRIM_MASK;
4489 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
4490 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
4491 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
4492 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
4493 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
4494 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
4495 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
4496 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
4497 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
4498 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
4499 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
4500 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
4501 params[SI_PARAM_FRONT_FACE] = ctx->i32;
4502 params[SI_PARAM_ANCILLARY] = ctx->i32;
4503 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
4504 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
4505 num_params = SI_PARAM_POS_FIXED_PT+1;
4506
4507 if (!ctx->is_monolithic) {
4508 /* Color inputs from the prolog. */
4509 if (shader->selector->info.colors_read) {
4510 unsigned num_color_elements =
4511 util_bitcount(shader->selector->info.colors_read);
4512
4513 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
4514 for (i = 0; i < num_color_elements; i++)
4515 params[num_params++] = ctx->f32;
4516 }
4517
4518 /* Outputs for the epilog. */
4519 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4520 num_returns =
4521 num_return_sgprs +
4522 util_bitcount(shader->selector->info.colors_written) * 4 +
4523 shader->selector->info.writes_z +
4524 shader->selector->info.writes_stencil +
4525 shader->selector->info.writes_samplemask +
4526 1 /* SampleMaskIn */;
4527
4528 num_returns = MAX2(num_returns,
4529 num_return_sgprs +
4530 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4531
4532 for (i = 0; i < num_return_sgprs; i++)
4533 returns[i] = ctx->i32;
4534 for (; i < num_returns; i++)
4535 returns[i] = ctx->f32;
4536 }
4537 break;
4538
4539 default:
4540 assert(0 && "unimplemented shader");
4541 return;
4542 }
4543
4544 assert(num_params <= Elements(params));
4545
4546 si_create_function(ctx, returns, num_returns, params,
4547 num_params, last_array_pointer, last_sgpr);
4548
4549 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4550 if (ctx->type == TGSI_PROCESSOR_FRAGMENT &&
4551 !ctx->is_monolithic) {
4552 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
4553 "InitialPSInputAddr",
4554 S_0286D0_PERSP_SAMPLE_ENA(1) |
4555 S_0286D0_PERSP_CENTER_ENA(1) |
4556 S_0286D0_PERSP_CENTROID_ENA(1) |
4557 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4558 S_0286D0_LINEAR_CENTER_ENA(1) |
4559 S_0286D0_LINEAR_CENTROID_ENA(1) |
4560 S_0286D0_FRONT_FACE_ENA(1) |
4561 S_0286D0_POS_FIXED_PT_ENA(1));
4562 }
4563
4564 shader->info.num_input_sgprs = 0;
4565 shader->info.num_input_vgprs = 0;
4566
4567 for (i = 0; i <= last_sgpr; ++i)
4568 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
4569
4570 /* Unused fragment shader inputs are eliminated by the compiler,
4571 * so we don't know yet how many there will be.
4572 */
4573 if (ctx->type != TGSI_PROCESSOR_FRAGMENT)
4574 for (; i < num_params; ++i)
4575 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
4576
4577 if (bld_base->info &&
4578 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
4579 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
4580 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
4581 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
4582 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
4583 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
4584 ctx->lds =
4585 LLVMAddGlobalInAddressSpace(gallivm->module,
4586 LLVMArrayType(ctx->i32, 64),
4587 "ddxy_lds",
4588 LOCAL_ADDR_SPACE);
4589
4590 if ((ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
4591 ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
4592 ctx->type == TGSI_PROCESSOR_TESS_EVAL)
4593 declare_tess_lds(ctx);
4594 }
4595
4596 static void preload_constants(struct si_shader_context *ctx)
4597 {
4598 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4599 struct gallivm_state *gallivm = bld_base->base.gallivm;
4600 const struct tgsi_shader_info *info = bld_base->info;
4601 unsigned buf;
4602 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
4603
4604 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
4605 unsigned i, num_const = info->const_file_max[buf] + 1;
4606
4607 if (num_const == 0)
4608 continue;
4609
4610 /* Allocate space for the constant values */
4611 ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
4612
4613 /* Load the resource descriptor */
4614 ctx->const_buffers[buf] =
4615 build_indexed_load_const(ctx, ptr, lp_build_const_int32(gallivm, buf));
4616
4617 /* Load the constants, we rely on the code sinking to do the rest */
4618 for (i = 0; i < num_const * 4; ++i) {
4619 ctx->constants[buf][i] =
4620 buffer_load_const(gallivm->builder,
4621 ctx->const_buffers[buf],
4622 lp_build_const_int32(gallivm, i * 4),
4623 ctx->f32);
4624 }
4625 }
4626 }
4627
4628 static void preload_samplers(struct si_shader_context *ctx)
4629 {
4630 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4631 struct gallivm_state *gallivm = bld_base->base.gallivm;
4632 const struct tgsi_shader_info *info = bld_base->info;
4633 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
4634 LLVMValueRef offset;
4635
4636 if (num_samplers == 0)
4637 return;
4638
4639 /* Load the resources and samplers, we rely on the code sinking to do the rest */
4640 for (i = 0; i < num_samplers; ++i) {
4641 /* Resource */
4642 offset = lp_build_const_int32(gallivm, i);
4643 ctx->sampler_views[i] =
4644 get_sampler_desc(ctx, offset, DESC_IMAGE);
4645
4646 /* FMASK resource */
4647 if (info->is_msaa_sampler[i])
4648 ctx->fmasks[i] =
4649 get_sampler_desc(ctx, offset, DESC_FMASK);
4650 else
4651 ctx->sampler_states[i] =
4652 get_sampler_desc(ctx, offset, DESC_SAMPLER);
4653 }
4654 }
4655
4656 static void preload_images(struct si_shader_context *ctx)
4657 {
4658 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4659 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4660 struct gallivm_state *gallivm = bld_base->base.gallivm;
4661 unsigned num_images = bld_base->info->file_max[TGSI_FILE_IMAGE] + 1;
4662 LLVMValueRef res_ptr;
4663 unsigned i;
4664
4665 if (num_images == 0)
4666 return;
4667
4668 res_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
4669
4670 for (i = 0; i < num_images; ++i) {
4671 /* Rely on LLVM to shrink the load for buffer resources. */
4672 LLVMValueRef rsrc =
4673 build_indexed_load_const(ctx, res_ptr,
4674 lp_build_const_int32(gallivm, i));
4675
4676 if (info->images_writemask & (1 << i) &&
4677 !(info->images_buffers & (1 << i)))
4678 rsrc = force_dcc_off(ctx, rsrc);
4679
4680 ctx->images[i] = rsrc;
4681 }
4682 }
4683
4684 static void preload_streamout_buffers(struct si_shader_context *ctx)
4685 {
4686 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4687 struct gallivm_state *gallivm = bld_base->base.gallivm;
4688 unsigned i;
4689
4690 /* Streamout can only be used if the shader is compiled as VS. */
4691 if (!ctx->shader->selector->so.num_outputs ||
4692 (ctx->type == TGSI_PROCESSOR_VERTEX &&
4693 (ctx->shader->key.vs.as_es ||
4694 ctx->shader->key.vs.as_ls)) ||
4695 (ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
4696 ctx->shader->key.tes.as_es))
4697 return;
4698
4699 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
4700 SI_PARAM_RW_BUFFERS);
4701
4702 /* Load the resources, we rely on the code sinking to do the rest */
4703 for (i = 0; i < 4; ++i) {
4704 if (ctx->shader->selector->so.stride[i]) {
4705 LLVMValueRef offset = lp_build_const_int32(gallivm,
4706 SI_SO_BUF_OFFSET + i);
4707
4708 ctx->so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
4709 }
4710 }
4711 }
4712
4713 /**
4714 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4715 * for later use.
4716 */
4717 static void preload_ring_buffers(struct si_shader_context *ctx)
4718 {
4719 struct gallivm_state *gallivm =
4720 ctx->radeon_bld.soa.bld_base.base.gallivm;
4721
4722 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
4723 SI_PARAM_RW_BUFFERS);
4724
4725 if ((ctx->type == TGSI_PROCESSOR_VERTEX &&
4726 ctx->shader->key.vs.as_es) ||
4727 (ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
4728 ctx->shader->key.tes.as_es) ||
4729 ctx->type == TGSI_PROCESSOR_GEOMETRY) {
4730 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
4731
4732 ctx->esgs_ring =
4733 build_indexed_load_const(ctx, buf_ptr, offset);
4734 }
4735
4736 if (ctx->is_gs_copy_shader) {
4737 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
4738
4739 ctx->gsvs_ring[0] =
4740 build_indexed_load_const(ctx, buf_ptr, offset);
4741 }
4742 if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
4743 int i;
4744 for (i = 0; i < 4; i++) {
4745 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i);
4746
4747 ctx->gsvs_ring[i] =
4748 build_indexed_load_const(ctx, buf_ptr, offset);
4749 }
4750 }
4751 }
4752
4753 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
4754 LLVMValueRef param_sampler_views,
4755 unsigned param_pos_fixed_pt)
4756 {
4757 struct lp_build_tgsi_context *bld_base =
4758 &ctx->radeon_bld.soa.bld_base;
4759 struct gallivm_state *gallivm = bld_base->base.gallivm;
4760 struct lp_build_emit_data result = {};
4761 struct tgsi_full_instruction inst = {};
4762 LLVMValueRef desc, sampler_index, address[2], pix;
4763
4764 /* Use the fixed-point gl_FragCoord input.
4765 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
4766 * per coordinate to get the repeating effect.
4767 */
4768 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
4769 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
4770
4771 /* Load the sampler view descriptor. */
4772 sampler_index = lp_build_const_int32(gallivm, SI_POLY_STIPPLE_SAMPLER);
4773 desc = get_sampler_desc_custom(ctx, param_sampler_views,
4774 sampler_index, DESC_IMAGE);
4775
4776 /* Load the texel. */
4777 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4778 inst.Texture.Texture = TGSI_TEXTURE_2D_MSAA; /* = use load, not load_mip */
4779 result.inst = &inst;
4780 set_tex_fetch_args(ctx, &result, TGSI_OPCODE_TXF,
4781 inst.Texture.Texture,
4782 desc, NULL, address, ARRAY_SIZE(address), 0xf);
4783 build_tex_intrinsic(&tex_action, bld_base, &result);
4784
4785 /* Kill the thread accordingly. */
4786 pix = LLVMBuildExtractElement(gallivm->builder, result.output[0],
4787 lp_build_const_int32(gallivm, 3), "");
4788 pix = bitcast(bld_base, TGSI_TYPE_FLOAT, pix);
4789 pix = LLVMBuildFNeg(gallivm->builder, pix, "");
4790
4791 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
4792 LLVMVoidTypeInContext(gallivm->context),
4793 &pix, 1, 0);
4794 }
4795
4796 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
4797 struct si_shader_config *conf,
4798 unsigned symbol_offset)
4799 {
4800 unsigned i;
4801 const unsigned char *config =
4802 radeon_shader_binary_config_start(binary, symbol_offset);
4803
4804 /* XXX: We may be able to emit some of these values directly rather than
4805 * extracting fields to be emitted later.
4806 */
4807
4808 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
4809 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
4810 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
4811 switch (reg) {
4812 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
4813 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
4814 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
4815 case R_00B848_COMPUTE_PGM_RSRC1:
4816 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
4817 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
4818 conf->float_mode = G_00B028_FLOAT_MODE(value);
4819 conf->rsrc1 = value;
4820 break;
4821 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
4822 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
4823 break;
4824 case R_00B84C_COMPUTE_PGM_RSRC2:
4825 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
4826 conf->rsrc2 = value;
4827 break;
4828 case R_0286CC_SPI_PS_INPUT_ENA:
4829 conf->spi_ps_input_ena = value;
4830 break;
4831 case R_0286D0_SPI_PS_INPUT_ADDR:
4832 conf->spi_ps_input_addr = value;
4833 break;
4834 case R_0286E8_SPI_TMPRING_SIZE:
4835 case R_00B860_COMPUTE_TMPRING_SIZE:
4836 /* WAVESIZE is in units of 256 dwords. */
4837 conf->scratch_bytes_per_wave =
4838 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
4839 break;
4840 default:
4841 {
4842 static bool printed;
4843
4844 if (!printed) {
4845 fprintf(stderr, "Warning: LLVM emitted unknown "
4846 "config register: 0x%x\n", reg);
4847 printed = true;
4848 }
4849 }
4850 break;
4851 }
4852
4853 if (!conf->spi_ps_input_addr)
4854 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
4855 }
4856 }
4857
4858 void si_shader_apply_scratch_relocs(struct si_context *sctx,
4859 struct si_shader *shader,
4860 uint64_t scratch_va)
4861 {
4862 unsigned i;
4863 uint32_t scratch_rsrc_dword0 = scratch_va;
4864 uint32_t scratch_rsrc_dword1 =
4865 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
4866 | S_008F04_STRIDE(shader->config.scratch_bytes_per_wave / 64);
4867
4868 for (i = 0 ; i < shader->binary.reloc_count; i++) {
4869 const struct radeon_shader_reloc *reloc =
4870 &shader->binary.relocs[i];
4871 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
4872 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4873 &scratch_rsrc_dword0, 4);
4874 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4875 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4876 &scratch_rsrc_dword1, 4);
4877 }
4878 }
4879 }
4880
4881 static unsigned si_get_shader_binary_size(struct si_shader *shader)
4882 {
4883 unsigned size = shader->binary.code_size;
4884
4885 if (shader->prolog)
4886 size += shader->prolog->binary.code_size;
4887 if (shader->epilog)
4888 size += shader->epilog->binary.code_size;
4889 return size;
4890 }
4891
4892 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
4893 {
4894 const struct radeon_shader_binary *prolog =
4895 shader->prolog ? &shader->prolog->binary : NULL;
4896 const struct radeon_shader_binary *epilog =
4897 shader->epilog ? &shader->epilog->binary : NULL;
4898 const struct radeon_shader_binary *mainb = &shader->binary;
4899 unsigned bo_size = si_get_shader_binary_size(shader) +
4900 (!epilog ? mainb->rodata_size : 0);
4901 unsigned char *ptr;
4902
4903 assert(!prolog || !prolog->rodata_size);
4904 assert((!prolog && !epilog) || !mainb->rodata_size);
4905 assert(!epilog || !epilog->rodata_size);
4906
4907 r600_resource_reference(&shader->bo, NULL);
4908 shader->bo = si_resource_create_custom(&sscreen->b.b,
4909 PIPE_USAGE_IMMUTABLE,
4910 bo_size);
4911 if (!shader->bo)
4912 return -ENOMEM;
4913
4914 /* Upload. */
4915 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
4916 PIPE_TRANSFER_READ_WRITE);
4917
4918 if (prolog) {
4919 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
4920 ptr += prolog->code_size;
4921 }
4922
4923 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
4924 ptr += mainb->code_size;
4925
4926 if (epilog)
4927 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
4928 else if (mainb->rodata_size > 0)
4929 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
4930
4931 sscreen->b.ws->buffer_unmap(shader->bo->buf);
4932 return 0;
4933 }
4934
4935 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
4936 struct pipe_debug_callback *debug,
4937 const char *name, FILE *file)
4938 {
4939 char *line, *p;
4940 unsigned i, count;
4941
4942 if (binary->disasm_string) {
4943 fprintf(file, "Shader %s disassembly:\n", name);
4944 fprintf(file, "%s", binary->disasm_string);
4945
4946 if (debug && debug->debug_message) {
4947 /* Very long debug messages are cut off, so send the
4948 * disassembly one line at a time. This causes more
4949 * overhead, but on the plus side it simplifies
4950 * parsing of resulting logs.
4951 */
4952 pipe_debug_message(debug, SHADER_INFO,
4953 "Shader Disassembly Begin");
4954
4955 line = binary->disasm_string;
4956 while (*line) {
4957 p = strchrnul(line, '\n');
4958 count = p - line;
4959
4960 if (count) {
4961 pipe_debug_message(debug, SHADER_INFO,
4962 "%.*s", count, line);
4963 }
4964
4965 if (!*p)
4966 break;
4967 line = p + 1;
4968 }
4969
4970 pipe_debug_message(debug, SHADER_INFO,
4971 "Shader Disassembly End");
4972 }
4973 } else {
4974 fprintf(file, "Shader %s binary:\n", name);
4975 for (i = 0; i < binary->code_size; i += 4) {
4976 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
4977 binary->code[i + 3], binary->code[i + 2],
4978 binary->code[i + 1], binary->code[i]);
4979 }
4980 }
4981 }
4982
4983 static void si_shader_dump_stats(struct si_screen *sscreen,
4984 struct si_shader_config *conf,
4985 unsigned num_inputs,
4986 unsigned code_size,
4987 struct pipe_debug_callback *debug,
4988 unsigned processor,
4989 FILE *file)
4990 {
4991 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
4992 unsigned lds_per_wave = 0;
4993 unsigned max_simd_waves = 10;
4994
4995 /* Compute LDS usage for PS. */
4996 if (processor == TGSI_PROCESSOR_FRAGMENT) {
4997 /* The minimum usage per wave is (num_inputs * 36). The maximum
4998 * usage is (num_inputs * 36 * 16).
4999 * We can get anything in between and it varies between waves.
5000 *
5001 * Other stages don't know the size at compile time or don't
5002 * allocate LDS per wave, but instead they do it per thread group.
5003 */
5004 lds_per_wave = conf->lds_size * lds_increment +
5005 align(num_inputs * 36, lds_increment);
5006 }
5007
5008 /* Compute the per-SIMD wave counts. */
5009 if (conf->num_sgprs) {
5010 if (sscreen->b.chip_class >= VI)
5011 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5012 else
5013 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5014 }
5015
5016 if (conf->num_vgprs)
5017 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5018
5019 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
5020 * that PS can use.
5021 */
5022 if (lds_per_wave)
5023 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5024
5025 if (file != stderr ||
5026 r600_can_dump_shader(&sscreen->b, processor)) {
5027 if (processor == TGSI_PROCESSOR_FRAGMENT) {
5028 fprintf(file, "*** SHADER CONFIG ***\n"
5029 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5030 "SPI_PS_INPUT_ENA = 0x%04x\n",
5031 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5032 }
5033
5034 fprintf(file, "*** SHADER STATS ***\n"
5035 "SGPRS: %d\n"
5036 "VGPRS: %d\n"
5037 "Code Size: %d bytes\n"
5038 "LDS: %d blocks\n"
5039 "Scratch: %d bytes per wave\n"
5040 "Max Waves: %d\n"
5041 "********************\n",
5042 conf->num_sgprs, conf->num_vgprs, code_size,
5043 conf->lds_size, conf->scratch_bytes_per_wave,
5044 max_simd_waves);
5045 }
5046
5047 pipe_debug_message(debug, SHADER_INFO,
5048 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5049 "LDS: %d Scratch: %d Max Waves: %d",
5050 conf->num_sgprs, conf->num_vgprs, code_size,
5051 conf->lds_size, conf->scratch_bytes_per_wave,
5052 max_simd_waves);
5053 }
5054
5055 static const char *si_get_shader_name(struct si_shader *shader,
5056 unsigned processor)
5057 {
5058 switch (processor) {
5059 case TGSI_PROCESSOR_VERTEX:
5060 if (shader->key.vs.as_es)
5061 return "Vertex Shader as ES";
5062 else if (shader->key.vs.as_ls)
5063 return "Vertex Shader as LS";
5064 else
5065 return "Vertex Shader as VS";
5066 case TGSI_PROCESSOR_TESS_CTRL:
5067 return "Tessellation Control Shader";
5068 case TGSI_PROCESSOR_TESS_EVAL:
5069 if (shader->key.tes.as_es)
5070 return "Tessellation Evaluation Shader as ES";
5071 else
5072 return "Tessellation Evaluation Shader as VS";
5073 case TGSI_PROCESSOR_GEOMETRY:
5074 if (shader->gs_copy_shader == NULL)
5075 return "GS Copy Shader as VS";
5076 else
5077 return "Geometry Shader";
5078 case TGSI_PROCESSOR_FRAGMENT:
5079 return "Pixel Shader";
5080 case TGSI_PROCESSOR_COMPUTE:
5081 return "Compute Shader";
5082 default:
5083 return "Unknown Shader";
5084 }
5085 }
5086
5087 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
5088 struct pipe_debug_callback *debug, unsigned processor,
5089 FILE *file)
5090 {
5091 if (file != stderr ||
5092 (r600_can_dump_shader(&sscreen->b, processor) &&
5093 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
5094 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5095
5096 if (shader->prolog)
5097 si_shader_dump_disassembly(&shader->prolog->binary,
5098 debug, "prolog", file);
5099
5100 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5101
5102 if (shader->epilog)
5103 si_shader_dump_disassembly(&shader->epilog->binary,
5104 debug, "epilog", file);
5105 fprintf(file, "\n");
5106 }
5107
5108 si_shader_dump_stats(sscreen, &shader->config,
5109 shader->selector ? shader->selector->info.num_inputs : 0,
5110 si_get_shader_binary_size(shader), debug, processor,
5111 file);
5112 }
5113
5114 int si_compile_llvm(struct si_screen *sscreen,
5115 struct radeon_shader_binary *binary,
5116 struct si_shader_config *conf,
5117 LLVMTargetMachineRef tm,
5118 LLVMModuleRef mod,
5119 struct pipe_debug_callback *debug,
5120 unsigned processor,
5121 const char *name)
5122 {
5123 int r = 0;
5124 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
5125
5126 if (r600_can_dump_shader(&sscreen->b, processor)) {
5127 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5128
5129 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
5130 fprintf(stderr, "%s LLVM IR:\n\n", name);
5131 LLVMDumpModule(mod);
5132 fprintf(stderr, "\n");
5133 }
5134 }
5135
5136 if (!si_replace_shader(count, binary)) {
5137 r = radeon_llvm_compile(mod, binary,
5138 r600_get_llvm_processor_name(sscreen->b.family), tm,
5139 debug);
5140 if (r)
5141 return r;
5142 }
5143
5144 si_shader_binary_read_config(binary, conf, 0);
5145
5146 /* Enable 64-bit and 16-bit denormals, because there is no performance
5147 * cost.
5148 *
5149 * If denormals are enabled, all floating-point output modifiers are
5150 * ignored.
5151 *
5152 * Don't enable denormals for 32-bit floats, because:
5153 * - Floating-point output modifiers would be ignored by the hw.
5154 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5155 * have to stop using those.
5156 * - SI & CI would be very slow.
5157 */
5158 conf->float_mode |= V_00B028_FP_64_DENORMS;
5159
5160 FREE(binary->config);
5161 FREE(binary->global_symbol_offsets);
5162 binary->config = NULL;
5163 binary->global_symbol_offsets = NULL;
5164
5165 /* Some shaders can't have rodata because their binaries can be
5166 * concatenated.
5167 */
5168 if (binary->rodata_size &&
5169 (processor == TGSI_PROCESSOR_VERTEX ||
5170 processor == TGSI_PROCESSOR_TESS_CTRL ||
5171 processor == TGSI_PROCESSOR_TESS_EVAL ||
5172 processor == TGSI_PROCESSOR_FRAGMENT)) {
5173 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5174 return -EINVAL;
5175 }
5176
5177 return r;
5178 }
5179
5180 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5181 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
5182 struct si_shader_context *ctx,
5183 struct si_shader *gs,
5184 struct pipe_debug_callback *debug)
5185 {
5186 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5187 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5188 struct lp_build_context *uint = &bld_base->uint_bld;
5189 struct si_shader_output_values *outputs;
5190 struct tgsi_shader_info *gsinfo = &gs->selector->info;
5191 LLVMValueRef args[9];
5192 int i, r;
5193
5194 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5195
5196 si_init_shader_ctx(ctx, sscreen, ctx->shader, ctx->tm);
5197 ctx->type = TGSI_PROCESSOR_VERTEX;
5198 ctx->is_gs_copy_shader = true;
5199
5200 create_meta_data(ctx);
5201 create_function(ctx);
5202 preload_streamout_buffers(ctx);
5203 preload_ring_buffers(ctx);
5204
5205 args[0] = ctx->gsvs_ring[0];
5206 args[1] = lp_build_mul_imm(uint,
5207 LLVMGetParam(ctx->radeon_bld.main_fn,
5208 ctx->param_vertex_id),
5209 4);
5210 args[3] = uint->zero;
5211 args[4] = uint->one; /* OFFEN */
5212 args[5] = uint->zero; /* IDXEN */
5213 args[6] = uint->one; /* GLC */
5214 args[7] = uint->one; /* SLC */
5215 args[8] = uint->zero; /* TFE */
5216
5217 /* Fetch vertex data from GSVS ring */
5218 for (i = 0; i < gsinfo->num_outputs; ++i) {
5219 unsigned chan;
5220
5221 outputs[i].name = gsinfo->output_semantic_name[i];
5222 outputs[i].sid = gsinfo->output_semantic_index[i];
5223
5224 for (chan = 0; chan < 4; chan++) {
5225 args[2] = lp_build_const_int32(gallivm,
5226 (i * 4 + chan) *
5227 gs->selector->gs_max_out_vertices * 16 * 4);
5228
5229 outputs[i].values[chan] =
5230 LLVMBuildBitCast(gallivm->builder,
5231 lp_build_intrinsic(gallivm->builder,
5232 "llvm.SI.buffer.load.dword.i32.i32",
5233 ctx->i32, args, 9,
5234 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
5235 ctx->f32, "");
5236 }
5237 }
5238
5239 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
5240
5241 LLVMBuildRet(gallivm->builder, ctx->return_value);
5242
5243 /* Dump LLVM IR before any optimization passes */
5244 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
5245 r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
5246 LLVMDumpModule(bld_base->base.gallivm->module);
5247
5248 radeon_llvm_finalize_module(&ctx->radeon_bld);
5249
5250 r = si_compile_llvm(sscreen, &ctx->shader->binary,
5251 &ctx->shader->config, ctx->tm,
5252 bld_base->base.gallivm->module,
5253 debug, TGSI_PROCESSOR_GEOMETRY,
5254 "GS Copy Shader");
5255 if (!r) {
5256 if (r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
5257 fprintf(stderr, "GS Copy Shader:\n");
5258 si_shader_dump(sscreen, ctx->shader, debug,
5259 TGSI_PROCESSOR_GEOMETRY, stderr);
5260 r = si_shader_binary_upload(sscreen, ctx->shader);
5261 }
5262
5263 radeon_llvm_dispose(&ctx->radeon_bld);
5264
5265 FREE(outputs);
5266 return r;
5267 }
5268
5269 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
5270 {
5271 int i;
5272
5273 fprintf(f, "SHADER KEY\n");
5274
5275 switch (shader) {
5276 case PIPE_SHADER_VERTEX:
5277 fprintf(f, " instance_divisors = {");
5278 for (i = 0; i < Elements(key->vs.prolog.instance_divisors); i++)
5279 fprintf(f, !i ? "%u" : ", %u",
5280 key->vs.prolog.instance_divisors[i]);
5281 fprintf(f, "}\n");
5282 fprintf(f, " as_es = %u\n", key->vs.as_es);
5283 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
5284 fprintf(f, " export_prim_id = %u\n", key->vs.epilog.export_prim_id);
5285 break;
5286
5287 case PIPE_SHADER_TESS_CTRL:
5288 fprintf(f, " prim_mode = %u\n", key->tcs.epilog.prim_mode);
5289 break;
5290
5291 case PIPE_SHADER_TESS_EVAL:
5292 fprintf(f, " as_es = %u\n", key->tes.as_es);
5293 fprintf(f, " export_prim_id = %u\n", key->tes.epilog.export_prim_id);
5294 break;
5295
5296 case PIPE_SHADER_GEOMETRY:
5297 break;
5298
5299 case PIPE_SHADER_FRAGMENT:
5300 fprintf(f, " prolog.color_two_side = %u\n", key->ps.prolog.color_two_side);
5301 fprintf(f, " prolog.poly_stipple = %u\n", key->ps.prolog.poly_stipple);
5302 fprintf(f, " prolog.force_persample_interp = %u\n", key->ps.prolog.force_persample_interp);
5303 fprintf(f, " epilog.spi_shader_col_format = 0x%x\n", key->ps.epilog.spi_shader_col_format);
5304 fprintf(f, " epilog.color_is_int8 = 0x%X\n", key->ps.epilog.color_is_int8);
5305 fprintf(f, " epilog.last_cbuf = %u\n", key->ps.epilog.last_cbuf);
5306 fprintf(f, " epilog.alpha_func = %u\n", key->ps.epilog.alpha_func);
5307 fprintf(f, " epilog.alpha_to_one = %u\n", key->ps.epilog.alpha_to_one);
5308 fprintf(f, " epilog.poly_line_smoothing = %u\n", key->ps.epilog.poly_line_smoothing);
5309 fprintf(f, " epilog.clamp_color = %u\n", key->ps.epilog.clamp_color);
5310 break;
5311
5312 default:
5313 assert(0);
5314 }
5315 }
5316
5317 static void si_init_shader_ctx(struct si_shader_context *ctx,
5318 struct si_screen *sscreen,
5319 struct si_shader *shader,
5320 LLVMTargetMachineRef tm)
5321 {
5322 struct lp_build_tgsi_context *bld_base;
5323 struct lp_build_tgsi_action tmpl;
5324
5325 memset(ctx, 0, sizeof(*ctx));
5326 radeon_llvm_context_init(&ctx->radeon_bld, "amdgcn--");
5327 ctx->tm = tm;
5328 ctx->screen = sscreen;
5329 if (shader && shader->selector)
5330 ctx->type = shader->selector->info.processor;
5331 else
5332 ctx->type = -1;
5333 ctx->shader = shader;
5334
5335 ctx->voidt = LLVMVoidTypeInContext(ctx->radeon_bld.gallivm.context);
5336 ctx->i1 = LLVMInt1TypeInContext(ctx->radeon_bld.gallivm.context);
5337 ctx->i8 = LLVMInt8TypeInContext(ctx->radeon_bld.gallivm.context);
5338 ctx->i32 = LLVMInt32TypeInContext(ctx->radeon_bld.gallivm.context);
5339 ctx->i64 = LLVMInt64TypeInContext(ctx->radeon_bld.gallivm.context);
5340 ctx->i128 = LLVMIntTypeInContext(ctx->radeon_bld.gallivm.context, 128);
5341 ctx->f32 = LLVMFloatTypeInContext(ctx->radeon_bld.gallivm.context);
5342 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
5343 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
5344 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
5345 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
5346 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
5347
5348 bld_base = &ctx->radeon_bld.soa.bld_base;
5349 if (shader && shader->selector)
5350 bld_base->info = &shader->selector->info;
5351 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5352
5353 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5354 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5355 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5356
5357 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
5358 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
5359 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
5360 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
5361 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
5362 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
5363 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
5364 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
5365 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
5366 bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
5367 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
5368 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
5369 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
5370
5371 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
5372 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
5373 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
5374 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
5375 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
5376 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
5377
5378 tmpl.fetch_args = atomic_fetch_args;
5379 tmpl.emit = atomic_emit;
5380 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
5381 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
5382 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
5383 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
5384 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
5385 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
5386 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
5387 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
5388 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
5389 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
5390 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
5391 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
5392 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
5393 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
5394 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
5395 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
5396 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
5397 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
5398 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
5399 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
5400
5401 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5402
5403 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5404 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5405 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5406 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5407
5408 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
5409 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
5410 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5411
5412 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
5413 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
5414 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
5415 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
5416 }
5417
5418 int si_compile_tgsi_shader(struct si_screen *sscreen,
5419 LLVMTargetMachineRef tm,
5420 struct si_shader *shader,
5421 bool is_monolithic,
5422 struct pipe_debug_callback *debug)
5423 {
5424 struct si_shader_selector *sel = shader->selector;
5425 struct si_shader_context ctx;
5426 struct lp_build_tgsi_context *bld_base;
5427 LLVMModuleRef mod;
5428 int r = 0;
5429
5430 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
5431 * conversion fails. */
5432 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
5433 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
5434 si_dump_shader_key(sel->type, &shader->key, stderr);
5435 tgsi_dump(sel->tokens, 0);
5436 si_dump_streamout(&sel->so);
5437 }
5438
5439 si_init_shader_ctx(&ctx, sscreen, shader, tm);
5440 ctx.is_monolithic = is_monolithic;
5441
5442 shader->info.uses_instanceid = sel->info.uses_instanceid;
5443
5444 bld_base = &ctx.radeon_bld.soa.bld_base;
5445 ctx.radeon_bld.load_system_value = declare_system_value;
5446
5447 switch (ctx.type) {
5448 case TGSI_PROCESSOR_VERTEX:
5449 ctx.radeon_bld.load_input = declare_input_vs;
5450 if (shader->key.vs.as_ls)
5451 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
5452 else if (shader->key.vs.as_es)
5453 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
5454 else
5455 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
5456 break;
5457 case TGSI_PROCESSOR_TESS_CTRL:
5458 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5459 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5460 bld_base->emit_store = store_output_tcs;
5461 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
5462 break;
5463 case TGSI_PROCESSOR_TESS_EVAL:
5464 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
5465 if (shader->key.tes.as_es)
5466 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
5467 else
5468 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
5469 break;
5470 case TGSI_PROCESSOR_GEOMETRY:
5471 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
5472 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
5473 break;
5474 case TGSI_PROCESSOR_FRAGMENT:
5475 ctx.radeon_bld.load_input = declare_input_fs;
5476 if (is_monolithic)
5477 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
5478 else
5479 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
5480 break;
5481 default:
5482 assert(!"Unsupported shader type");
5483 return -1;
5484 }
5485
5486 create_meta_data(&ctx);
5487 create_function(&ctx);
5488 preload_constants(&ctx);
5489 preload_samplers(&ctx);
5490 preload_images(&ctx);
5491 preload_streamout_buffers(&ctx);
5492 preload_ring_buffers(&ctx);
5493
5494 if (ctx.is_monolithic && sel->type == PIPE_SHADER_FRAGMENT &&
5495 shader->key.ps.prolog.poly_stipple) {
5496 LLVMValueRef views = LLVMGetParam(ctx.radeon_bld.main_fn,
5497 SI_PARAM_SAMPLERS);
5498 si_llvm_emit_polygon_stipple(&ctx, views,
5499 SI_PARAM_POS_FIXED_PT);
5500 }
5501
5502 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
5503 int i;
5504 for (i = 0; i < 4; i++) {
5505 ctx.gs_next_vertex[i] =
5506 lp_build_alloca(bld_base->base.gallivm,
5507 ctx.i32, "");
5508 }
5509 }
5510
5511 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
5512 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
5513 goto out;
5514 }
5515
5516 LLVMBuildRet(bld_base->base.gallivm->builder, ctx.return_value);
5517 mod = bld_base->base.gallivm->module;
5518
5519 /* Dump LLVM IR before any optimization passes */
5520 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
5521 r600_can_dump_shader(&sscreen->b, ctx.type))
5522 LLVMDumpModule(mod);
5523
5524 radeon_llvm_finalize_module(&ctx.radeon_bld);
5525
5526 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
5527 mod, debug, ctx.type, "TGSI shader");
5528 if (r) {
5529 fprintf(stderr, "LLVM failed to compile shader\n");
5530 goto out;
5531 }
5532
5533 radeon_llvm_dispose(&ctx.radeon_bld);
5534
5535 /* Calculate the number of fragment input VGPRs. */
5536 if (ctx.type == TGSI_PROCESSOR_FRAGMENT) {
5537 shader->info.num_input_vgprs = 0;
5538 shader->info.face_vgpr_index = -1;
5539
5540 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
5541 shader->info.num_input_vgprs += 2;
5542 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
5543 shader->info.num_input_vgprs += 2;
5544 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
5545 shader->info.num_input_vgprs += 2;
5546 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
5547 shader->info.num_input_vgprs += 3;
5548 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
5549 shader->info.num_input_vgprs += 2;
5550 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
5551 shader->info.num_input_vgprs += 2;
5552 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
5553 shader->info.num_input_vgprs += 2;
5554 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
5555 shader->info.num_input_vgprs += 1;
5556 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
5557 shader->info.num_input_vgprs += 1;
5558 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
5559 shader->info.num_input_vgprs += 1;
5560 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
5561 shader->info.num_input_vgprs += 1;
5562 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
5563 shader->info.num_input_vgprs += 1;
5564 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
5565 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
5566 shader->info.num_input_vgprs += 1;
5567 }
5568 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
5569 shader->info.num_input_vgprs += 1;
5570 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
5571 shader->info.num_input_vgprs += 1;
5572 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
5573 shader->info.num_input_vgprs += 1;
5574 }
5575
5576 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
5577 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
5578 shader->gs_copy_shader->selector = shader->selector;
5579 ctx.shader = shader->gs_copy_shader;
5580 if ((r = si_generate_gs_copy_shader(sscreen, &ctx,
5581 shader, debug))) {
5582 free(shader->gs_copy_shader);
5583 shader->gs_copy_shader = NULL;
5584 goto out;
5585 }
5586 }
5587
5588 out:
5589 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
5590 FREE(ctx.constants[i]);
5591 return r;
5592 }
5593
5594 /**
5595 * Create, compile and return a shader part (prolog or epilog).
5596 *
5597 * \param sscreen screen
5598 * \param list list of shader parts of the same category
5599 * \param key shader part key
5600 * \param tm LLVM target machine
5601 * \param debug debug callback
5602 * \param compile the callback responsible for compilation
5603 * \return non-NULL on success
5604 */
5605 static struct si_shader_part *
5606 si_get_shader_part(struct si_screen *sscreen,
5607 struct si_shader_part **list,
5608 union si_shader_part_key *key,
5609 LLVMTargetMachineRef tm,
5610 struct pipe_debug_callback *debug,
5611 bool (*compile)(struct si_screen *,
5612 LLVMTargetMachineRef,
5613 struct pipe_debug_callback *,
5614 struct si_shader_part *))
5615 {
5616 struct si_shader_part *result;
5617
5618 pipe_mutex_lock(sscreen->shader_parts_mutex);
5619
5620 /* Find existing. */
5621 for (result = *list; result; result = result->next) {
5622 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
5623 pipe_mutex_unlock(sscreen->shader_parts_mutex);
5624 return result;
5625 }
5626 }
5627
5628 /* Compile a new one. */
5629 result = CALLOC_STRUCT(si_shader_part);
5630 result->key = *key;
5631 if (!compile(sscreen, tm, debug, result)) {
5632 FREE(result);
5633 pipe_mutex_unlock(sscreen->shader_parts_mutex);
5634 return NULL;
5635 }
5636
5637 result->next = *list;
5638 *list = result;
5639 pipe_mutex_unlock(sscreen->shader_parts_mutex);
5640 return result;
5641 }
5642
5643 /**
5644 * Create a vertex shader prolog.
5645 *
5646 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
5647 * All inputs are returned unmodified. The vertex load indices are
5648 * stored after them, which will used by the API VS for fetching inputs.
5649 *
5650 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
5651 * input_v0,
5652 * input_v1,
5653 * input_v2,
5654 * input_v3,
5655 * (VertexID + BaseVertex),
5656 * (InstanceID + StartInstance),
5657 * (InstanceID / 2 + StartInstance)
5658 */
5659 static bool si_compile_vs_prolog(struct si_screen *sscreen,
5660 LLVMTargetMachineRef tm,
5661 struct pipe_debug_callback *debug,
5662 struct si_shader_part *out)
5663 {
5664 union si_shader_part_key *key = &out->key;
5665 struct si_shader shader = {};
5666 struct si_shader_context ctx;
5667 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
5668 LLVMTypeRef *params, *returns;
5669 LLVMValueRef ret, func;
5670 int last_sgpr, num_params, num_returns, i;
5671 bool status = true;
5672
5673 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
5674 ctx.type = TGSI_PROCESSOR_VERTEX;
5675 ctx.param_vertex_id = key->vs_prolog.num_input_sgprs;
5676 ctx.param_instance_id = key->vs_prolog.num_input_sgprs + 3;
5677
5678 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
5679 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
5680 sizeof(LLVMTypeRef));
5681 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
5682 key->vs_prolog.last_input + 1) *
5683 sizeof(LLVMTypeRef));
5684 num_params = 0;
5685 num_returns = 0;
5686
5687 /* Declare input and output SGPRs. */
5688 num_params = 0;
5689 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
5690 params[num_params++] = ctx.i32;
5691 returns[num_returns++] = ctx.i32;
5692 }
5693 last_sgpr = num_params - 1;
5694
5695 /* 4 preloaded VGPRs (outputs must be floats) */
5696 for (i = 0; i < 4; i++) {
5697 params[num_params++] = ctx.i32;
5698 returns[num_returns++] = ctx.f32;
5699 }
5700
5701 /* Vertex load indices. */
5702 for (i = 0; i <= key->vs_prolog.last_input; i++)
5703 returns[num_returns++] = ctx.f32;
5704
5705 /* Create the function. */
5706 si_create_function(&ctx, returns, num_returns, params,
5707 num_params, -1, last_sgpr);
5708 func = ctx.radeon_bld.main_fn;
5709
5710 /* Copy inputs to outputs. This should be no-op, as the registers match,
5711 * but it will prevent the compiler from overwriting them unintentionally.
5712 */
5713 ret = ctx.return_value;
5714 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
5715 LLVMValueRef p = LLVMGetParam(func, i);
5716 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
5717 }
5718 for (i = num_params - 4; i < num_params; i++) {
5719 LLVMValueRef p = LLVMGetParam(func, i);
5720 p = LLVMBuildBitCast(gallivm->builder, p, ctx.f32, "");
5721 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
5722 }
5723
5724 /* Compute vertex load indices from instance divisors. */
5725 for (i = 0; i <= key->vs_prolog.last_input; i++) {
5726 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
5727 LLVMValueRef index;
5728
5729 if (divisor) {
5730 /* InstanceID / Divisor + StartInstance */
5731 index = get_instance_index_for_fetch(&ctx.radeon_bld,
5732 SI_SGPR_START_INSTANCE,
5733 divisor);
5734 } else {
5735 /* VertexID + BaseVertex */
5736 index = LLVMBuildAdd(gallivm->builder,
5737 LLVMGetParam(func, ctx.param_vertex_id),
5738 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
5739 }
5740
5741 index = LLVMBuildBitCast(gallivm->builder, index, ctx.f32, "");
5742 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
5743 num_params++, "");
5744 }
5745
5746 /* Compile. */
5747 LLVMBuildRet(gallivm->builder, ret);
5748 radeon_llvm_finalize_module(&ctx.radeon_bld);
5749
5750 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
5751 gallivm->module, debug, ctx.type,
5752 "Vertex Shader Prolog"))
5753 status = false;
5754
5755 radeon_llvm_dispose(&ctx.radeon_bld);
5756 return status;
5757 }
5758
5759 /**
5760 * Compile the vertex shader epilog. This is also used by the tessellation
5761 * evaluation shader compiled as VS.
5762 *
5763 * The input is PrimitiveID.
5764 *
5765 * If PrimitiveID is required by the pixel shader, export it.
5766 * Otherwise, do nothing.
5767 */
5768 static bool si_compile_vs_epilog(struct si_screen *sscreen,
5769 LLVMTargetMachineRef tm,
5770 struct pipe_debug_callback *debug,
5771 struct si_shader_part *out)
5772 {
5773 union si_shader_part_key *key = &out->key;
5774 struct si_shader_context ctx;
5775 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
5776 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
5777 LLVMTypeRef params[5];
5778 int num_params, i;
5779 bool status = true;
5780
5781 si_init_shader_ctx(&ctx, sscreen, NULL, tm);
5782 ctx.type = TGSI_PROCESSOR_VERTEX;
5783
5784 /* Declare input VGPRs. */
5785 num_params = key->vs_epilog.states.export_prim_id ?
5786 (VS_EPILOG_PRIMID_LOC + 1) : 0;
5787 assert(num_params <= ARRAY_SIZE(params));
5788
5789 for (i = 0; i < num_params; i++)
5790 params[i] = ctx.f32;
5791
5792 /* Create the function. */
5793 si_create_function(&ctx, NULL, 0, params, num_params,
5794 -1, -1);
5795
5796 /* Emit exports. */
5797 if (key->vs_epilog.states.export_prim_id) {
5798 struct lp_build_context *base = &bld_base->base;
5799 struct lp_build_context *uint = &bld_base->uint_bld;
5800 LLVMValueRef args[9];
5801
5802 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
5803 args[1] = uint->zero; /* whether the EXEC mask is valid */
5804 args[2] = uint->zero; /* DONE bit */
5805 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
5806 key->vs_epilog.prim_id_param_offset);
5807 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
5808 args[5] = LLVMGetParam(ctx.radeon_bld.main_fn,
5809 VS_EPILOG_PRIMID_LOC); /* X */
5810 args[6] = uint->undef; /* Y */
5811 args[7] = uint->undef; /* Z */
5812 args[8] = uint->undef; /* W */
5813
5814 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
5815 LLVMVoidTypeInContext(base->gallivm->context),
5816 args, 9, 0);
5817 }
5818
5819 /* Compile. */
5820 LLVMBuildRet(gallivm->builder, ctx.return_value);
5821 radeon_llvm_finalize_module(&ctx.radeon_bld);
5822
5823 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
5824 gallivm->module, debug, ctx.type,
5825 "Vertex Shader Epilog"))
5826 status = false;
5827
5828 radeon_llvm_dispose(&ctx.radeon_bld);
5829 return status;
5830 }
5831
5832 /**
5833 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
5834 */
5835 static bool si_get_vs_epilog(struct si_screen *sscreen,
5836 LLVMTargetMachineRef tm,
5837 struct si_shader *shader,
5838 struct pipe_debug_callback *debug,
5839 struct si_vs_epilog_bits *states)
5840 {
5841 union si_shader_part_key epilog_key;
5842
5843 memset(&epilog_key, 0, sizeof(epilog_key));
5844 epilog_key.vs_epilog.states = *states;
5845
5846 /* Set up the PrimitiveID output. */
5847 if (shader->key.vs.epilog.export_prim_id) {
5848 unsigned index = shader->selector->info.num_outputs;
5849 unsigned offset = shader->info.nr_param_exports++;
5850
5851 epilog_key.vs_epilog.prim_id_param_offset = offset;
5852 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
5853 shader->info.vs_output_param_offset[index] = offset;
5854 }
5855
5856 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
5857 &epilog_key, tm, debug,
5858 si_compile_vs_epilog);
5859 return shader->epilog != NULL;
5860 }
5861
5862 /**
5863 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
5864 */
5865 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
5866 LLVMTargetMachineRef tm,
5867 struct si_shader *shader,
5868 struct pipe_debug_callback *debug)
5869 {
5870 struct tgsi_shader_info *info = &shader->selector->info;
5871 union si_shader_part_key prolog_key;
5872 unsigned i;
5873
5874 /* Get the prolog. */
5875 memset(&prolog_key, 0, sizeof(prolog_key));
5876 prolog_key.vs_prolog.states = shader->key.vs.prolog;
5877 prolog_key.vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
5878 prolog_key.vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
5879
5880 /* The prolog is a no-op if there are no inputs. */
5881 if (info->num_inputs) {
5882 shader->prolog =
5883 si_get_shader_part(sscreen, &sscreen->vs_prologs,
5884 &prolog_key, tm, debug,
5885 si_compile_vs_prolog);
5886 if (!shader->prolog)
5887 return false;
5888 }
5889
5890 /* Get the epilog. */
5891 if (!shader->key.vs.as_es && !shader->key.vs.as_ls &&
5892 !si_get_vs_epilog(sscreen, tm, shader, debug,
5893 &shader->key.vs.epilog))
5894 return false;
5895
5896 /* Set the instanceID flag. */
5897 for (i = 0; i < info->num_inputs; i++)
5898 if (prolog_key.vs_prolog.states.instance_divisors[i])
5899 shader->info.uses_instanceid = true;
5900
5901 return true;
5902 }
5903
5904 /**
5905 * Select and compile (or reuse) TES parts (epilog).
5906 */
5907 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
5908 LLVMTargetMachineRef tm,
5909 struct si_shader *shader,
5910 struct pipe_debug_callback *debug)
5911 {
5912 if (shader->key.tes.as_es)
5913 return true;
5914
5915 /* TES compiled as VS. */
5916 return si_get_vs_epilog(sscreen, tm, shader, debug,
5917 &shader->key.tes.epilog);
5918 }
5919
5920 /**
5921 * Compile the TCS epilog. This writes tesselation factors to memory based on
5922 * the output primitive type of the tesselator (determined by TES).
5923 */
5924 static bool si_compile_tcs_epilog(struct si_screen *sscreen,
5925 LLVMTargetMachineRef tm,
5926 struct pipe_debug_callback *debug,
5927 struct si_shader_part *out)
5928 {
5929 union si_shader_part_key *key = &out->key;
5930 struct si_shader shader = {};
5931 struct si_shader_context ctx;
5932 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
5933 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
5934 LLVMTypeRef params[16];
5935 LLVMValueRef func;
5936 int last_array_pointer, last_sgpr, num_params;
5937 bool status = true;
5938
5939 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
5940 ctx.type = TGSI_PROCESSOR_TESS_CTRL;
5941 shader.key.tcs.epilog = key->tcs_epilog.states;
5942
5943 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
5944 params[SI_PARAM_RW_BUFFERS] = const_array(ctx.v16i8, SI_NUM_RW_BUFFERS);
5945 last_array_pointer = SI_PARAM_RW_BUFFERS;
5946 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
5947 params[SI_PARAM_SAMPLERS] = ctx.i64;
5948 params[SI_PARAM_IMAGES] = ctx.i64;
5949 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx.i32;
5950 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx.i32;
5951 params[SI_PARAM_TCS_IN_LAYOUT] = ctx.i32;
5952 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx.i32;
5953 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5954 num_params = last_sgpr + 1;
5955
5956 params[num_params++] = ctx.i32; /* patch index within the wave (REL_PATCH_ID) */
5957 params[num_params++] = ctx.i32; /* invocation ID within the patch */
5958 params[num_params++] = ctx.i32; /* LDS offset where tess factors should be loaded from */
5959
5960 /* Create the function. */
5961 si_create_function(&ctx, NULL, 0, params, num_params,
5962 last_array_pointer, last_sgpr);
5963 declare_tess_lds(&ctx);
5964 func = ctx.radeon_bld.main_fn;
5965
5966 si_write_tess_factors(bld_base,
5967 LLVMGetParam(func, last_sgpr + 1),
5968 LLVMGetParam(func, last_sgpr + 2),
5969 LLVMGetParam(func, last_sgpr + 3));
5970
5971 /* Compile. */
5972 LLVMBuildRet(gallivm->builder, ctx.return_value);
5973 radeon_llvm_finalize_module(&ctx.radeon_bld);
5974
5975 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
5976 gallivm->module, debug, ctx.type,
5977 "Tessellation Control Shader Epilog"))
5978 status = false;
5979
5980 radeon_llvm_dispose(&ctx.radeon_bld);
5981 return status;
5982 }
5983
5984 /**
5985 * Select and compile (or reuse) TCS parts (epilog).
5986 */
5987 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
5988 LLVMTargetMachineRef tm,
5989 struct si_shader *shader,
5990 struct pipe_debug_callback *debug)
5991 {
5992 union si_shader_part_key epilog_key;
5993
5994 /* Get the epilog. */
5995 memset(&epilog_key, 0, sizeof(epilog_key));
5996 epilog_key.tcs_epilog.states = shader->key.tcs.epilog;
5997
5998 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
5999 &epilog_key, tm, debug,
6000 si_compile_tcs_epilog);
6001 return shader->epilog != NULL;
6002 }
6003
6004 /**
6005 * Compile the pixel shader prolog. This handles:
6006 * - two-side color selection and interpolation
6007 * - overriding interpolation parameters for the API PS
6008 * - polygon stippling
6009 *
6010 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
6011 * overriden by other states. (e.g. per-sample interpolation)
6012 * Interpolated colors are stored after the preloaded VGPRs.
6013 */
6014 static bool si_compile_ps_prolog(struct si_screen *sscreen,
6015 LLVMTargetMachineRef tm,
6016 struct pipe_debug_callback *debug,
6017 struct si_shader_part *out)
6018 {
6019 union si_shader_part_key *key = &out->key;
6020 struct si_shader shader = {};
6021 struct si_shader_context ctx;
6022 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6023 LLVMTypeRef *params;
6024 LLVMValueRef ret, func;
6025 int last_sgpr, num_params, num_returns, i, num_color_channels;
6026 bool status = true;
6027
6028 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6029 ctx.type = TGSI_PROCESSOR_FRAGMENT;
6030 shader.key.ps.prolog = key->ps_prolog.states;
6031
6032 /* Number of inputs + 8 color elements. */
6033 params = alloca((key->ps_prolog.num_input_sgprs +
6034 key->ps_prolog.num_input_vgprs + 8) *
6035 sizeof(LLVMTypeRef));
6036
6037 /* Declare inputs. */
6038 num_params = 0;
6039 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
6040 params[num_params++] = ctx.i32;
6041 last_sgpr = num_params - 1;
6042
6043 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
6044 params[num_params++] = ctx.f32;
6045
6046 /* Declare outputs (same as inputs + add colors if needed) */
6047 num_returns = num_params;
6048 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
6049 for (i = 0; i < num_color_channels; i++)
6050 params[num_returns++] = ctx.f32;
6051
6052 /* Create the function. */
6053 si_create_function(&ctx, params, num_returns, params,
6054 num_params, -1, last_sgpr);
6055 func = ctx.radeon_bld.main_fn;
6056
6057 /* Copy inputs to outputs. This should be no-op, as the registers match,
6058 * but it will prevent the compiler from overwriting them unintentionally.
6059 */
6060 ret = ctx.return_value;
6061 for (i = 0; i < num_params; i++) {
6062 LLVMValueRef p = LLVMGetParam(func, i);
6063 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6064 }
6065
6066 /* Polygon stippling. */
6067 if (key->ps_prolog.states.poly_stipple) {
6068 /* POS_FIXED_PT is always last. */
6069 unsigned pos = key->ps_prolog.num_input_sgprs +
6070 key->ps_prolog.num_input_vgprs - 1;
6071 LLVMValueRef ptr[2], views;
6072
6073 /* Get the pointer to sampler views. */
6074 ptr[0] = LLVMGetParam(func, SI_SGPR_SAMPLERS);
6075 ptr[1] = LLVMGetParam(func, SI_SGPR_SAMPLERS+1);
6076 views = lp_build_gather_values(gallivm, ptr, 2);
6077 views = LLVMBuildBitCast(gallivm->builder, views, ctx.i64, "");
6078 views = LLVMBuildIntToPtr(gallivm->builder, views,
6079 const_array(ctx.v8i32, SI_NUM_SAMPLERS), "");
6080
6081 si_llvm_emit_polygon_stipple(&ctx, views, pos);
6082 }
6083
6084 /* Interpolate colors. */
6085 for (i = 0; i < 2; i++) {
6086 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
6087 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
6088 key->ps_prolog.face_vgpr_index;
6089 LLVMValueRef interp[2], color[4];
6090 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
6091
6092 if (!writemask)
6093 continue;
6094
6095 /* If the interpolation qualifier is not CONSTANT (-1). */
6096 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
6097 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
6098 key->ps_prolog.color_interp_vgpr_index[i];
6099
6100 interp[0] = LLVMGetParam(func, interp_vgpr);
6101 interp[1] = LLVMGetParam(func, interp_vgpr + 1);
6102 interp_ij = lp_build_gather_values(gallivm, interp, 2);
6103 interp_ij = LLVMBuildBitCast(gallivm->builder, interp_ij,
6104 ctx.v2i32, "");
6105 }
6106
6107 /* Use the absolute location of the input. */
6108 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
6109
6110 if (key->ps_prolog.states.color_two_side) {
6111 face = LLVMGetParam(func, face_vgpr);
6112 face = LLVMBuildBitCast(gallivm->builder, face, ctx.i32, "");
6113 }
6114
6115 interp_fs_input(&ctx,
6116 key->ps_prolog.color_attr_index[i],
6117 TGSI_SEMANTIC_COLOR, i,
6118 key->ps_prolog.num_interp_inputs,
6119 key->ps_prolog.colors_read, interp_ij,
6120 prim_mask, face, color);
6121
6122 while (writemask) {
6123 unsigned chan = u_bit_scan(&writemask);
6124 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
6125 num_params++, "");
6126 }
6127 }
6128
6129 /* Force per-sample interpolation. */
6130 if (key->ps_prolog.states.force_persample_interp) {
6131 unsigned i, base = key->ps_prolog.num_input_sgprs;
6132 LLVMValueRef persp_sample[2], linear_sample[2];
6133
6134 /* Read PERSP_SAMPLE. */
6135 for (i = 0; i < 2; i++)
6136 persp_sample[i] = LLVMGetParam(func, base + i);
6137 /* Overwrite PERSP_CENTER. */
6138 for (i = 0; i < 2; i++)
6139 ret = LLVMBuildInsertValue(gallivm->builder, ret,
6140 persp_sample[i], base + 2 + i, "");
6141 /* Overwrite PERSP_CENTROID. */
6142 for (i = 0; i < 2; i++)
6143 ret = LLVMBuildInsertValue(gallivm->builder, ret,
6144 persp_sample[i], base + 4 + i, "");
6145 /* Read LINEAR_SAMPLE. */
6146 for (i = 0; i < 2; i++)
6147 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
6148 /* Overwrite LINEAR_CENTER. */
6149 for (i = 0; i < 2; i++)
6150 ret = LLVMBuildInsertValue(gallivm->builder, ret,
6151 linear_sample[i], base + 8 + i, "");
6152 /* Overwrite LINEAR_CENTROID. */
6153 for (i = 0; i < 2; i++)
6154 ret = LLVMBuildInsertValue(gallivm->builder, ret,
6155 linear_sample[i], base + 10 + i, "");
6156 }
6157
6158 /* Compile. */
6159 LLVMBuildRet(gallivm->builder, ret);
6160 radeon_llvm_finalize_module(&ctx.radeon_bld);
6161
6162 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6163 gallivm->module, debug, ctx.type,
6164 "Fragment Shader Prolog"))
6165 status = false;
6166
6167 radeon_llvm_dispose(&ctx.radeon_bld);
6168 return status;
6169 }
6170
6171 /**
6172 * Compile the pixel shader epilog. This handles everything that must be
6173 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
6174 */
6175 static bool si_compile_ps_epilog(struct si_screen *sscreen,
6176 LLVMTargetMachineRef tm,
6177 struct pipe_debug_callback *debug,
6178 struct si_shader_part *out)
6179 {
6180 union si_shader_part_key *key = &out->key;
6181 struct si_shader shader = {};
6182 struct si_shader_context ctx;
6183 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6184 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
6185 LLVMTypeRef params[16+8*4+3];
6186 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6187 int last_array_pointer, last_sgpr, num_params, i;
6188 bool status = true;
6189
6190 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6191 ctx.type = TGSI_PROCESSOR_FRAGMENT;
6192 shader.key.ps.epilog = key->ps_epilog.states;
6193
6194 /* Declare input SGPRs. */
6195 params[SI_PARAM_RW_BUFFERS] = ctx.i64;
6196 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
6197 params[SI_PARAM_SAMPLERS] = ctx.i64;
6198 params[SI_PARAM_IMAGES] = ctx.i64;
6199 params[SI_PARAM_ALPHA_REF] = ctx.f32;
6200 last_array_pointer = -1;
6201 last_sgpr = SI_PARAM_ALPHA_REF;
6202
6203 /* Declare input VGPRs. */
6204 num_params = (last_sgpr + 1) +
6205 util_bitcount(key->ps_epilog.colors_written) * 4 +
6206 key->ps_epilog.writes_z +
6207 key->ps_epilog.writes_stencil +
6208 key->ps_epilog.writes_samplemask;
6209
6210 num_params = MAX2(num_params,
6211 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
6212
6213 assert(num_params <= ARRAY_SIZE(params));
6214
6215 for (i = last_sgpr + 1; i < num_params; i++)
6216 params[i] = ctx.f32;
6217
6218 /* Create the function. */
6219 si_create_function(&ctx, NULL, 0, params, num_params,
6220 last_array_pointer, last_sgpr);
6221 /* Disable elimination of unused inputs. */
6222 radeon_llvm_add_attribute(ctx.radeon_bld.main_fn,
6223 "InitialPSInputAddr", 0xffffff);
6224
6225 /* Process colors. */
6226 unsigned vgpr = last_sgpr + 1;
6227 unsigned colors_written = key->ps_epilog.colors_written;
6228 int last_color_export = -1;
6229
6230 /* Find the last color export. */
6231 if (!key->ps_epilog.writes_z &&
6232 !key->ps_epilog.writes_stencil &&
6233 !key->ps_epilog.writes_samplemask) {
6234 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
6235
6236 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
6237 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
6238 /* Just set this if any of the colorbuffers are enabled. */
6239 if (spi_format &
6240 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
6241 last_color_export = 0;
6242 } else {
6243 for (i = 0; i < 8; i++)
6244 if (colors_written & (1 << i) &&
6245 (spi_format >> (i * 4)) & 0xf)
6246 last_color_export = i;
6247 }
6248 }
6249
6250 while (colors_written) {
6251 LLVMValueRef color[4];
6252 int mrt = u_bit_scan(&colors_written);
6253
6254 for (i = 0; i < 4; i++)
6255 color[i] = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
6256
6257 si_export_mrt_color(bld_base, color, mrt,
6258 num_params - 1,
6259 mrt == last_color_export);
6260 }
6261
6262 /* Process depth, stencil, samplemask. */
6263 if (key->ps_epilog.writes_z)
6264 depth = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
6265 if (key->ps_epilog.writes_stencil)
6266 stencil = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
6267 if (key->ps_epilog.writes_samplemask)
6268 samplemask = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
6269
6270 if (depth || stencil || samplemask)
6271 si_export_mrt_z(bld_base, depth, stencil, samplemask);
6272 else if (last_color_export == -1)
6273 si_export_null(bld_base);
6274
6275 /* Compile. */
6276 LLVMBuildRetVoid(gallivm->builder);
6277 radeon_llvm_finalize_module(&ctx.radeon_bld);
6278
6279 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6280 gallivm->module, debug, ctx.type,
6281 "Fragment Shader Epilog"))
6282 status = false;
6283
6284 radeon_llvm_dispose(&ctx.radeon_bld);
6285 return status;
6286 }
6287
6288 /**
6289 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
6290 */
6291 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
6292 LLVMTargetMachineRef tm,
6293 struct si_shader *shader,
6294 struct pipe_debug_callback *debug)
6295 {
6296 struct tgsi_shader_info *info = &shader->selector->info;
6297 union si_shader_part_key prolog_key;
6298 union si_shader_part_key epilog_key;
6299 unsigned i;
6300
6301 /* Get the prolog. */
6302 memset(&prolog_key, 0, sizeof(prolog_key));
6303 prolog_key.ps_prolog.states = shader->key.ps.prolog;
6304 prolog_key.ps_prolog.colors_read = info->colors_read;
6305 prolog_key.ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6306 prolog_key.ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6307
6308 if (info->colors_read) {
6309 unsigned *color = shader->selector->color_attr_index;
6310
6311 if (shader->key.ps.prolog.color_two_side) {
6312 /* BCOLORs are stored after the last input. */
6313 prolog_key.ps_prolog.num_interp_inputs = info->num_inputs;
6314 prolog_key.ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6315 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6316 }
6317
6318 for (i = 0; i < 2; i++) {
6319 unsigned location = info->input_interpolate_loc[color[i]];
6320
6321 if (!(info->colors_read & (0xf << i*4)))
6322 continue;
6323
6324 prolog_key.ps_prolog.color_attr_index[i] = color[i];
6325
6326 /* Force per-sample interpolation for the colors here. */
6327 if (shader->key.ps.prolog.force_persample_interp)
6328 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6329
6330 switch (info->input_interpolate[color[i]]) {
6331 case TGSI_INTERPOLATE_CONSTANT:
6332 prolog_key.ps_prolog.color_interp_vgpr_index[i] = -1;
6333 break;
6334 case TGSI_INTERPOLATE_PERSPECTIVE:
6335 case TGSI_INTERPOLATE_COLOR:
6336 switch (location) {
6337 case TGSI_INTERPOLATE_LOC_SAMPLE:
6338 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 0;
6339 shader->config.spi_ps_input_ena |=
6340 S_0286CC_PERSP_SAMPLE_ENA(1);
6341 break;
6342 case TGSI_INTERPOLATE_LOC_CENTER:
6343 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 2;
6344 shader->config.spi_ps_input_ena |=
6345 S_0286CC_PERSP_CENTER_ENA(1);
6346 break;
6347 case TGSI_INTERPOLATE_LOC_CENTROID:
6348 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 4;
6349 shader->config.spi_ps_input_ena |=
6350 S_0286CC_PERSP_CENTROID_ENA(1);
6351 break;
6352 default:
6353 assert(0);
6354 }
6355 break;
6356 case TGSI_INTERPOLATE_LINEAR:
6357 switch (location) {
6358 case TGSI_INTERPOLATE_LOC_SAMPLE:
6359 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 6;
6360 shader->config.spi_ps_input_ena |=
6361 S_0286CC_LINEAR_SAMPLE_ENA(1);
6362 break;
6363 case TGSI_INTERPOLATE_LOC_CENTER:
6364 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 8;
6365 shader->config.spi_ps_input_ena |=
6366 S_0286CC_LINEAR_CENTER_ENA(1);
6367 break;
6368 case TGSI_INTERPOLATE_LOC_CENTROID:
6369 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 10;
6370 shader->config.spi_ps_input_ena |=
6371 S_0286CC_LINEAR_CENTROID_ENA(1);
6372 break;
6373 default:
6374 assert(0);
6375 }
6376 break;
6377 default:
6378 assert(0);
6379 }
6380 }
6381 }
6382
6383 /* The prolog is a no-op if these aren't set. */
6384 if (prolog_key.ps_prolog.colors_read ||
6385 prolog_key.ps_prolog.states.force_persample_interp ||
6386 prolog_key.ps_prolog.states.poly_stipple) {
6387 shader->prolog =
6388 si_get_shader_part(sscreen, &sscreen->ps_prologs,
6389 &prolog_key, tm, debug,
6390 si_compile_ps_prolog);
6391 if (!shader->prolog)
6392 return false;
6393 }
6394
6395 /* Get the epilog. */
6396 memset(&epilog_key, 0, sizeof(epilog_key));
6397 epilog_key.ps_epilog.colors_written = info->colors_written;
6398 epilog_key.ps_epilog.writes_z = info->writes_z;
6399 epilog_key.ps_epilog.writes_stencil = info->writes_stencil;
6400 epilog_key.ps_epilog.writes_samplemask = info->writes_samplemask;
6401 epilog_key.ps_epilog.states = shader->key.ps.epilog;
6402
6403 shader->epilog =
6404 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
6405 &epilog_key, tm, debug,
6406 si_compile_ps_epilog);
6407 if (!shader->epilog)
6408 return false;
6409
6410 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
6411 if (shader->key.ps.prolog.poly_stipple) {
6412 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
6413 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
6414 }
6415
6416 /* Set up the enable bits for per-sample shading if needed. */
6417 if (shader->key.ps.prolog.force_persample_interp) {
6418 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
6419 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena)) {
6420 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
6421 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
6422 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
6423 }
6424 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
6425 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena)) {
6426 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
6427 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
6428 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
6429 }
6430 }
6431
6432 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
6433 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
6434 !(shader->config.spi_ps_input_ena & 0xf)) {
6435 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
6436 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
6437 }
6438
6439 /* At least one pair of interpolation weights must be enabled. */
6440 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
6441 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
6442 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
6443 }
6444
6445 /* The sample mask input is always enabled, because the API shader always
6446 * passes it through to the epilog. Disable it here if it's unused.
6447 */
6448 if (!shader->key.ps.epilog.poly_line_smoothing &&
6449 !shader->selector->info.reads_samplemask)
6450 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
6451
6452 return true;
6453 }
6454
6455 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
6456 struct si_shader *shader,
6457 struct pipe_debug_callback *debug)
6458 {
6459 struct si_shader *mainp = shader->selector->main_shader_part;
6460 int r;
6461
6462 /* LS, ES, VS are compiled on demand if the main part hasn't been
6463 * compiled for that stage.
6464 */
6465 if (!mainp ||
6466 (shader->selector->type == PIPE_SHADER_VERTEX &&
6467 (shader->key.vs.as_es != mainp->key.vs.as_es ||
6468 shader->key.vs.as_ls != mainp->key.vs.as_ls)) ||
6469 (shader->selector->type == PIPE_SHADER_TESS_EVAL &&
6470 shader->key.tes.as_es != mainp->key.tes.as_es)) {
6471 /* Monolithic shader (compiled as a whole, has many variants,
6472 * may take a long time to compile).
6473 */
6474 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
6475 if (r)
6476 return r;
6477 } else {
6478 /* The shader consists of 2-3 parts:
6479 *
6480 * - the middle part is the user shader, it has 1 variant only
6481 * and it was compiled during the creation of the shader
6482 * selector
6483 * - the prolog part is inserted at the beginning
6484 * - the epilog part is inserted at the end
6485 *
6486 * The prolog and epilog have many (but simple) variants.
6487 */
6488
6489 /* Copy the compiled TGSI shader data over. */
6490 shader->is_binary_shared = true;
6491 shader->binary = mainp->binary;
6492 shader->config = mainp->config;
6493 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
6494 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
6495 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
6496 memcpy(shader->info.vs_output_param_offset,
6497 mainp->info.vs_output_param_offset,
6498 sizeof(mainp->info.vs_output_param_offset));
6499 shader->info.uses_instanceid = mainp->info.uses_instanceid;
6500 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
6501 shader->info.nr_param_exports = mainp->info.nr_param_exports;
6502
6503 /* Select prologs and/or epilogs. */
6504 switch (shader->selector->type) {
6505 case PIPE_SHADER_VERTEX:
6506 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
6507 return -1;
6508 break;
6509 case PIPE_SHADER_TESS_CTRL:
6510 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
6511 return -1;
6512 break;
6513 case PIPE_SHADER_TESS_EVAL:
6514 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
6515 return -1;
6516 break;
6517 case PIPE_SHADER_FRAGMENT:
6518 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
6519 return -1;
6520
6521 /* Make sure we have at least as many VGPRs as there
6522 * are allocated inputs.
6523 */
6524 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
6525 shader->info.num_input_vgprs);
6526 break;
6527 }
6528
6529 /* Update SGPR and VGPR counts. */
6530 if (shader->prolog) {
6531 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
6532 shader->prolog->config.num_sgprs);
6533 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
6534 shader->prolog->config.num_vgprs);
6535 }
6536 if (shader->epilog) {
6537 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
6538 shader->epilog->config.num_sgprs);
6539 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
6540 shader->epilog->config.num_vgprs);
6541 }
6542 }
6543
6544 si_shader_dump(sscreen, shader, debug, shader->selector->info.processor,
6545 stderr);
6546
6547 /* Upload. */
6548 r = si_shader_binary_upload(sscreen, shader);
6549 if (r) {
6550 fprintf(stderr, "LLVM failed to upload shader\n");
6551 return r;
6552 }
6553
6554 return 0;
6555 }
6556
6557 void si_shader_destroy(struct si_shader *shader)
6558 {
6559 if (shader->gs_copy_shader) {
6560 si_shader_destroy(shader->gs_copy_shader);
6561 FREE(shader->gs_copy_shader);
6562 }
6563
6564 if (shader->scratch_bo)
6565 r600_resource_reference(&shader->scratch_bo, NULL);
6566
6567 r600_resource_reference(&shader->bo, NULL);
6568
6569 if (!shader->is_binary_shared)
6570 radeon_shader_binary_clean(&shader->binary);
6571 }