2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "gallivm/lp_bld_const.h"
25 #include "gallivm/lp_bld_gather.h"
26 #include "gallivm/lp_bld_intr.h"
27 #include "gallivm/lp_bld_logic.h"
28 #include "gallivm/lp_bld_arit.h"
29 #include "gallivm/lp_bld_flow.h"
30 #include "gallivm/lp_bld_misc.h"
31 #include "util/u_memory.h"
32 #include "util/u_string.h"
33 #include "tgsi/tgsi_build.h"
34 #include "tgsi/tgsi_util.h"
35 #include "tgsi/tgsi_dump.h"
37 #include "ac_binary.h"
38 #include "ac_llvm_util.h"
39 #include "ac_exp_param.h"
40 #include "si_shader_internal.h"
44 #include "compiler/nir/nir.h"
46 static const char *scratch_rsrc_dword0_symbol
=
47 "SCRATCH_RSRC_DWORD0";
49 static const char *scratch_rsrc_dword1_symbol
=
50 "SCRATCH_RSRC_DWORD1";
52 struct si_shader_output_values
54 LLVMValueRef values
[4];
55 unsigned semantic_name
;
56 unsigned semantic_index
;
57 ubyte vertex_stream
[4];
61 * Used to collect types and other info about arguments of the LLVM function
62 * before the function is created.
64 struct si_function_info
{
65 LLVMTypeRef types
[100];
66 LLVMValueRef
*assign
[100];
67 unsigned num_sgpr_params
;
76 static void si_init_shader_ctx(struct si_shader_context
*ctx
,
77 struct si_screen
*sscreen
,
78 LLVMTargetMachineRef tm
);
80 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action
*action
,
81 struct lp_build_tgsi_context
*bld_base
,
82 struct lp_build_emit_data
*emit_data
);
84 static void si_dump_shader_key(unsigned processor
, const struct si_shader
*shader
,
87 static void si_build_vs_prolog_function(struct si_shader_context
*ctx
,
88 union si_shader_part_key
*key
);
89 static void si_build_tcs_epilog_function(struct si_shader_context
*ctx
,
90 union si_shader_part_key
*key
);
91 static void si_build_ps_prolog_function(struct si_shader_context
*ctx
,
92 union si_shader_part_key
*key
);
93 static void si_build_ps_epilog_function(struct si_shader_context
*ctx
,
94 union si_shader_part_key
*key
);
96 /* Ideally pass the sample mask input to the PS epilog as v14, which
97 * is its usual location, so that the shader doesn't have to add v_mov.
99 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
102 CONST_ADDR_SPACE
= 2,
103 LOCAL_ADDR_SPACE
= 3,
106 static bool llvm_type_is_64bit(struct si_shader_context
*ctx
,
109 if (type
== ctx
->ac
.i64
|| type
== ctx
->ac
.f64
)
115 static bool is_merged_shader(struct si_shader
*shader
)
117 if (shader
->selector
->screen
->info
.chip_class
<= VI
)
120 return shader
->key
.as_ls
||
122 shader
->selector
->type
== PIPE_SHADER_TESS_CTRL
||
123 shader
->selector
->type
== PIPE_SHADER_GEOMETRY
;
126 static void si_init_function_info(struct si_function_info
*fninfo
)
128 fninfo
->num_params
= 0;
129 fninfo
->num_sgpr_params
= 0;
132 static unsigned add_arg_assign(struct si_function_info
*fninfo
,
133 enum si_arg_regfile regfile
, LLVMTypeRef type
,
134 LLVMValueRef
*assign
)
136 assert(regfile
!= ARG_SGPR
|| fninfo
->num_sgpr_params
== fninfo
->num_params
);
138 unsigned idx
= fninfo
->num_params
++;
139 assert(idx
< ARRAY_SIZE(fninfo
->types
));
141 if (regfile
== ARG_SGPR
)
142 fninfo
->num_sgpr_params
= fninfo
->num_params
;
144 fninfo
->types
[idx
] = type
;
145 fninfo
->assign
[idx
] = assign
;
149 static unsigned add_arg(struct si_function_info
*fninfo
,
150 enum si_arg_regfile regfile
, LLVMTypeRef type
)
152 return add_arg_assign(fninfo
, regfile
, type
, NULL
);
155 static void add_arg_assign_checked(struct si_function_info
*fninfo
,
156 enum si_arg_regfile regfile
, LLVMTypeRef type
,
157 LLVMValueRef
*assign
, unsigned idx
)
159 MAYBE_UNUSED
unsigned actual
= add_arg_assign(fninfo
, regfile
, type
, assign
);
160 assert(actual
== idx
);
163 static void add_arg_checked(struct si_function_info
*fninfo
,
164 enum si_arg_regfile regfile
, LLVMTypeRef type
,
167 add_arg_assign_checked(fninfo
, regfile
, type
, NULL
, idx
);
171 * Returns a unique index for a per-patch semantic name and index. The index
172 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
175 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name
, unsigned index
)
177 switch (semantic_name
) {
178 case TGSI_SEMANTIC_TESSOUTER
:
180 case TGSI_SEMANTIC_TESSINNER
:
182 case TGSI_SEMANTIC_PATCH
:
187 assert(!"invalid semantic name");
193 * Returns a unique index for a semantic name and index. The index must be
194 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
197 unsigned si_shader_io_get_unique_index(unsigned semantic_name
, unsigned index
)
199 switch (semantic_name
) {
200 case TGSI_SEMANTIC_POSITION
:
202 case TGSI_SEMANTIC_GENERIC
:
203 /* Since some shader stages use the the highest used IO index
204 * to determine the size to allocate for inputs/outputs
205 * (in LDS, tess and GS rings). GENERIC should be placed right
206 * after POSITION to make that size as small as possible.
208 if (index
< SI_MAX_IO_GENERIC
)
211 assert(!"invalid generic index");
213 case TGSI_SEMANTIC_PSIZE
:
214 return SI_MAX_IO_GENERIC
+ 1;
215 case TGSI_SEMANTIC_CLIPDIST
:
217 return SI_MAX_IO_GENERIC
+ 2 + index
;
218 case TGSI_SEMANTIC_FOG
:
219 return SI_MAX_IO_GENERIC
+ 4;
220 case TGSI_SEMANTIC_LAYER
:
221 return SI_MAX_IO_GENERIC
+ 5;
222 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
223 return SI_MAX_IO_GENERIC
+ 6;
224 case TGSI_SEMANTIC_PRIMID
:
225 return SI_MAX_IO_GENERIC
+ 7;
226 case TGSI_SEMANTIC_COLOR
: /* these alias */
227 case TGSI_SEMANTIC_BCOLOR
:
229 return SI_MAX_IO_GENERIC
+ 8 + index
;
230 case TGSI_SEMANTIC_TEXCOORD
:
232 assert(SI_MAX_IO_GENERIC
+ 10 + index
< 64);
233 return SI_MAX_IO_GENERIC
+ 10 + index
;
235 assert(!"invalid semantic name");
241 * Get the value of a shader input parameter and extract a bitfield.
243 static LLVMValueRef
unpack_param(struct si_shader_context
*ctx
,
244 unsigned param
, unsigned rshift
,
247 LLVMValueRef value
= LLVMGetParam(ctx
->main_fn
,
250 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMFloatTypeKind
)
251 value
= ac_to_integer(&ctx
->ac
, value
);
254 value
= LLVMBuildLShr(ctx
->ac
.builder
, value
,
255 LLVMConstInt(ctx
->i32
, rshift
, 0), "");
257 if (rshift
+ bitwidth
< 32) {
258 unsigned mask
= (1 << bitwidth
) - 1;
259 value
= LLVMBuildAnd(ctx
->ac
.builder
, value
,
260 LLVMConstInt(ctx
->i32
, mask
, 0), "");
266 static LLVMValueRef
get_rel_patch_id(struct si_shader_context
*ctx
)
269 case PIPE_SHADER_TESS_CTRL
:
270 return unpack_param(ctx
, ctx
->param_tcs_rel_ids
, 0, 8);
272 case PIPE_SHADER_TESS_EVAL
:
273 return LLVMGetParam(ctx
->main_fn
,
274 ctx
->param_tes_rel_patch_id
);
282 /* Tessellation shaders pass outputs to the next shader using LDS.
284 * LS outputs = TCS inputs
285 * TCS outputs = TES inputs
288 * - TCS inputs for patch 0
289 * - TCS inputs for patch 1
290 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
292 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
293 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
294 * - TCS outputs for patch 1
295 * - Per-patch TCS outputs for patch 1
296 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
297 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
300 * All three shaders VS(LS), TCS, TES share the same LDS space.
304 get_tcs_in_patch_stride(struct si_shader_context
*ctx
)
306 return unpack_param(ctx
, ctx
->param_vs_state_bits
, 8, 13);
309 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context
*ctx
)
311 assert(ctx
->type
== PIPE_SHADER_TESS_CTRL
);
313 if (ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
)
314 return util_last_bit64(ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
) * 4;
316 return util_last_bit64(ctx
->shader
->selector
->outputs_written
) * 4;
319 static LLVMValueRef
get_tcs_out_vertex_dw_stride(struct si_shader_context
*ctx
)
321 unsigned stride
= get_tcs_out_vertex_dw_stride_constant(ctx
);
323 return LLVMConstInt(ctx
->i32
, stride
, 0);
326 static LLVMValueRef
get_tcs_out_patch_stride(struct si_shader_context
*ctx
)
328 if (ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
)
329 return unpack_param(ctx
, ctx
->param_tcs_out_lds_layout
, 0, 13);
331 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
332 unsigned tcs_out_vertices
= info
->properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
333 unsigned vertex_dw_stride
= get_tcs_out_vertex_dw_stride_constant(ctx
);
334 unsigned num_patch_outputs
= util_last_bit64(ctx
->shader
->selector
->patch_outputs_written
);
335 unsigned patch_dw_stride
= tcs_out_vertices
* vertex_dw_stride
+
336 num_patch_outputs
* 4;
337 return LLVMConstInt(ctx
->i32
, patch_dw_stride
, 0);
341 get_tcs_out_patch0_offset(struct si_shader_context
*ctx
)
343 return lp_build_mul_imm(&ctx
->bld_base
.uint_bld
,
345 ctx
->param_tcs_out_lds_offsets
,
351 get_tcs_out_patch0_patch_data_offset(struct si_shader_context
*ctx
)
353 return lp_build_mul_imm(&ctx
->bld_base
.uint_bld
,
355 ctx
->param_tcs_out_lds_offsets
,
361 get_tcs_in_current_patch_offset(struct si_shader_context
*ctx
)
363 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
364 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
366 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
370 get_tcs_out_current_patch_offset(struct si_shader_context
*ctx
)
372 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
373 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
374 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
376 return LLVMBuildAdd(ctx
->ac
.builder
, patch0_offset
,
377 LLVMBuildMul(ctx
->ac
.builder
, patch_stride
,
383 get_tcs_out_current_patch_data_offset(struct si_shader_context
*ctx
)
385 LLVMValueRef patch0_patch_data_offset
=
386 get_tcs_out_patch0_patch_data_offset(ctx
);
387 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
388 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
390 return LLVMBuildAdd(ctx
->ac
.builder
, patch0_patch_data_offset
,
391 LLVMBuildMul(ctx
->ac
.builder
, patch_stride
,
396 static LLVMValueRef
get_num_tcs_out_vertices(struct si_shader_context
*ctx
)
398 unsigned tcs_out_vertices
=
399 ctx
->shader
->selector
?
400 ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
] : 0;
402 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
403 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&& tcs_out_vertices
)
404 return LLVMConstInt(ctx
->i32
, tcs_out_vertices
, 0);
406 return unpack_param(ctx
, ctx
->param_tcs_offchip_layout
, 6, 6);
409 static LLVMValueRef
get_tcs_in_vertex_dw_stride(struct si_shader_context
*ctx
)
414 case PIPE_SHADER_VERTEX
:
415 stride
= util_last_bit64(ctx
->shader
->selector
->outputs_written
);
416 return LLVMConstInt(ctx
->i32
, stride
* 4, 0);
418 case PIPE_SHADER_TESS_CTRL
:
419 if (ctx
->screen
->info
.chip_class
>= GFX9
&&
420 ctx
->shader
->is_monolithic
) {
421 stride
= util_last_bit64(ctx
->shader
->key
.part
.tcs
.ls
->outputs_written
);
422 return LLVMConstInt(ctx
->i32
, stride
* 4, 0);
424 return unpack_param(ctx
, ctx
->param_vs_state_bits
, 24, 8);
432 static LLVMValueRef
get_instance_index_for_fetch(
433 struct si_shader_context
*ctx
,
434 unsigned param_start_instance
, LLVMValueRef divisor
)
436 LLVMValueRef result
= ctx
->abi
.instance_id
;
438 /* The division must be done before START_INSTANCE is added. */
439 if (divisor
!= ctx
->i32_1
)
440 result
= LLVMBuildUDiv(ctx
->ac
.builder
, result
, divisor
, "");
442 return LLVMBuildAdd(ctx
->ac
.builder
, result
,
443 LLVMGetParam(ctx
->main_fn
, param_start_instance
), "");
446 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
448 static LLVMValueRef
extract_double_to_float(struct si_shader_context
*ctx
,
450 unsigned double_index
)
452 LLVMBuilderRef builder
= ctx
->ac
.builder
;
453 LLVMTypeRef f64
= LLVMDoubleTypeInContext(ctx
->ac
.context
);
454 LLVMValueRef dvec2
= LLVMBuildBitCast(builder
, vec4
,
455 LLVMVectorType(f64
, 2), "");
456 LLVMValueRef index
= LLVMConstInt(ctx
->i32
, double_index
, 0);
457 LLVMValueRef value
= LLVMBuildExtractElement(builder
, dvec2
, index
, "");
458 return LLVMBuildFPTrunc(builder
, value
, ctx
->f32
, "");
461 static LLVMValueRef
unpack_sint16(struct si_shader_context
*ctx
,
462 LLVMValueRef i32
, unsigned index
)
467 return LLVMBuildAShr(ctx
->ac
.builder
, i32
,
468 LLVMConstInt(ctx
->i32
, 16, 0), "");
470 return LLVMBuildSExt(ctx
->ac
.builder
,
471 LLVMBuildTrunc(ctx
->ac
.builder
, i32
,
476 void si_llvm_load_input_vs(
477 struct si_shader_context
*ctx
,
478 unsigned input_index
,
481 unsigned vs_blit_property
=
482 ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
484 if (vs_blit_property
) {
485 LLVMValueRef vertex_id
= ctx
->abi
.vertex_id
;
486 LLVMValueRef sel_x1
= LLVMBuildICmp(ctx
->ac
.builder
,
487 LLVMIntULE
, vertex_id
,
489 /* Use LLVMIntNE, because we have 3 vertices and only
490 * the middle one should use y2.
492 LLVMValueRef sel_y1
= LLVMBuildICmp(ctx
->ac
.builder
,
493 LLVMIntNE
, vertex_id
,
496 if (input_index
== 0) {
498 LLVMValueRef x1y1
= LLVMGetParam(ctx
->main_fn
,
499 ctx
->param_vs_blit_inputs
);
500 LLVMValueRef x2y2
= LLVMGetParam(ctx
->main_fn
,
501 ctx
->param_vs_blit_inputs
+ 1);
503 LLVMValueRef x1
= unpack_sint16(ctx
, x1y1
, 0);
504 LLVMValueRef y1
= unpack_sint16(ctx
, x1y1
, 1);
505 LLVMValueRef x2
= unpack_sint16(ctx
, x2y2
, 0);
506 LLVMValueRef y2
= unpack_sint16(ctx
, x2y2
, 1);
508 LLVMValueRef x
= LLVMBuildSelect(ctx
->ac
.builder
, sel_x1
,
510 LLVMValueRef y
= LLVMBuildSelect(ctx
->ac
.builder
, sel_y1
,
513 out
[0] = LLVMBuildSIToFP(ctx
->ac
.builder
, x
, ctx
->f32
, "");
514 out
[1] = LLVMBuildSIToFP(ctx
->ac
.builder
, y
, ctx
->f32
, "");
515 out
[2] = LLVMGetParam(ctx
->main_fn
,
516 ctx
->param_vs_blit_inputs
+ 2);
517 out
[3] = ctx
->ac
.f32_1
;
521 /* Color or texture coordinates: */
522 assert(input_index
== 1);
524 if (vs_blit_property
== SI_VS_BLIT_SGPRS_POS_COLOR
) {
525 for (int i
= 0; i
< 4; i
++) {
526 out
[i
] = LLVMGetParam(ctx
->main_fn
,
527 ctx
->param_vs_blit_inputs
+ 3 + i
);
530 assert(vs_blit_property
== SI_VS_BLIT_SGPRS_POS_TEXCOORD
);
531 LLVMValueRef x1
= LLVMGetParam(ctx
->main_fn
,
532 ctx
->param_vs_blit_inputs
+ 3);
533 LLVMValueRef y1
= LLVMGetParam(ctx
->main_fn
,
534 ctx
->param_vs_blit_inputs
+ 4);
535 LLVMValueRef x2
= LLVMGetParam(ctx
->main_fn
,
536 ctx
->param_vs_blit_inputs
+ 5);
537 LLVMValueRef y2
= LLVMGetParam(ctx
->main_fn
,
538 ctx
->param_vs_blit_inputs
+ 6);
540 out
[0] = LLVMBuildSelect(ctx
->ac
.builder
, sel_x1
,
542 out
[1] = LLVMBuildSelect(ctx
->ac
.builder
, sel_y1
,
544 out
[2] = LLVMGetParam(ctx
->main_fn
,
545 ctx
->param_vs_blit_inputs
+ 7);
546 out
[3] = LLVMGetParam(ctx
->main_fn
,
547 ctx
->param_vs_blit_inputs
+ 8);
554 unsigned num_fetches
;
555 unsigned fetch_stride
;
557 LLVMValueRef t_list_ptr
;
558 LLVMValueRef t_offset
;
560 LLVMValueRef vertex_index
;
561 LLVMValueRef input
[3];
563 /* Load the T list */
564 t_list_ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_vertex_buffers
);
566 t_offset
= LLVMConstInt(ctx
->i32
, input_index
, 0);
568 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
570 vertex_index
= LLVMGetParam(ctx
->main_fn
,
571 ctx
->param_vertex_index0
+
574 fix_fetch
= ctx
->shader
->key
.mono
.vs_fix_fetch
[input_index
];
576 /* Do multiple loads for special formats. */
578 case SI_FIX_FETCH_RGB_64_FLOAT
:
579 num_fetches
= 3; /* 3 2-dword loads */
582 case SI_FIX_FETCH_RGBA_64_FLOAT
:
583 num_fetches
= 2; /* 2 4-dword loads */
586 case SI_FIX_FETCH_RGB_8
:
587 case SI_FIX_FETCH_RGB_8_INT
:
591 case SI_FIX_FETCH_RGB_16
:
592 case SI_FIX_FETCH_RGB_16_INT
:
601 for (unsigned i
= 0; i
< num_fetches
; i
++) {
602 LLVMValueRef voffset
= LLVMConstInt(ctx
->i32
, fetch_stride
* i
, 0);
604 input
[i
] = ac_build_buffer_load_format(&ctx
->ac
, t_list
,
605 vertex_index
, voffset
,
609 /* Break up the vec4 into individual components */
610 for (chan
= 0; chan
< 4; chan
++) {
611 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->i32
, chan
, 0);
612 out
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
613 input
[0], llvm_chan
, "");
617 case SI_FIX_FETCH_A2_SNORM
:
618 case SI_FIX_FETCH_A2_SSCALED
:
619 case SI_FIX_FETCH_A2_SINT
: {
620 /* The hardware returns an unsigned value; convert it to a
623 LLVMValueRef tmp
= out
[3];
624 LLVMValueRef c30
= LLVMConstInt(ctx
->i32
, 30, 0);
626 /* First, recover the sign-extended signed integer value. */
627 if (fix_fetch
== SI_FIX_FETCH_A2_SSCALED
)
628 tmp
= LLVMBuildFPToUI(ctx
->ac
.builder
, tmp
, ctx
->i32
, "");
630 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
632 /* For the integer-like cases, do a natural sign extension.
634 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
635 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
638 tmp
= LLVMBuildShl(ctx
->ac
.builder
, tmp
,
639 fix_fetch
== SI_FIX_FETCH_A2_SNORM
?
640 LLVMConstInt(ctx
->i32
, 7, 0) : c30
, "");
641 tmp
= LLVMBuildAShr(ctx
->ac
.builder
, tmp
, c30
, "");
643 /* Convert back to the right type. */
644 if (fix_fetch
== SI_FIX_FETCH_A2_SNORM
) {
646 LLVMValueRef neg_one
= LLVMConstReal(ctx
->f32
, -1.0);
647 tmp
= LLVMBuildSIToFP(ctx
->ac
.builder
, tmp
, ctx
->f32
, "");
648 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, tmp
, neg_one
, "");
649 tmp
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, tmp
, "");
650 } else if (fix_fetch
== SI_FIX_FETCH_A2_SSCALED
) {
651 tmp
= LLVMBuildSIToFP(ctx
->ac
.builder
, tmp
, ctx
->f32
, "");
657 case SI_FIX_FETCH_RGBA_32_UNORM
:
658 case SI_FIX_FETCH_RGBX_32_UNORM
:
659 for (chan
= 0; chan
< 4; chan
++) {
660 out
[chan
] = ac_to_integer(&ctx
->ac
, out
[chan
]);
661 out
[chan
] = LLVMBuildUIToFP(ctx
->ac
.builder
,
662 out
[chan
], ctx
->f32
, "");
663 out
[chan
] = LLVMBuildFMul(ctx
->ac
.builder
, out
[chan
],
664 LLVMConstReal(ctx
->f32
, 1.0 / UINT_MAX
), "");
666 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
667 if (fix_fetch
== SI_FIX_FETCH_RGBX_32_UNORM
)
668 out
[3] = LLVMConstReal(ctx
->f32
, 1);
670 case SI_FIX_FETCH_RGBA_32_SNORM
:
671 case SI_FIX_FETCH_RGBX_32_SNORM
:
672 case SI_FIX_FETCH_RGBA_32_FIXED
:
673 case SI_FIX_FETCH_RGBX_32_FIXED
: {
675 if (fix_fetch
>= SI_FIX_FETCH_RGBA_32_FIXED
)
676 scale
= 1.0 / 0x10000;
678 scale
= 1.0 / INT_MAX
;
680 for (chan
= 0; chan
< 4; chan
++) {
681 out
[chan
] = ac_to_integer(&ctx
->ac
, out
[chan
]);
682 out
[chan
] = LLVMBuildSIToFP(ctx
->ac
.builder
,
683 out
[chan
], ctx
->f32
, "");
684 out
[chan
] = LLVMBuildFMul(ctx
->ac
.builder
, out
[chan
],
685 LLVMConstReal(ctx
->f32
, scale
), "");
687 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
688 if (fix_fetch
== SI_FIX_FETCH_RGBX_32_SNORM
||
689 fix_fetch
== SI_FIX_FETCH_RGBX_32_FIXED
)
690 out
[3] = LLVMConstReal(ctx
->f32
, 1);
693 case SI_FIX_FETCH_RGBA_32_USCALED
:
694 for (chan
= 0; chan
< 4; chan
++) {
695 out
[chan
] = ac_to_integer(&ctx
->ac
, out
[chan
]);
696 out
[chan
] = LLVMBuildUIToFP(ctx
->ac
.builder
,
697 out
[chan
], ctx
->f32
, "");
700 case SI_FIX_FETCH_RGBA_32_SSCALED
:
701 for (chan
= 0; chan
< 4; chan
++) {
702 out
[chan
] = ac_to_integer(&ctx
->ac
, out
[chan
]);
703 out
[chan
] = LLVMBuildSIToFP(ctx
->ac
.builder
,
704 out
[chan
], ctx
->f32
, "");
707 case SI_FIX_FETCH_RG_64_FLOAT
:
708 for (chan
= 0; chan
< 2; chan
++)
709 out
[chan
] = extract_double_to_float(ctx
, input
[0], chan
);
711 out
[2] = LLVMConstReal(ctx
->f32
, 0);
712 out
[3] = LLVMConstReal(ctx
->f32
, 1);
714 case SI_FIX_FETCH_RGB_64_FLOAT
:
715 for (chan
= 0; chan
< 3; chan
++)
716 out
[chan
] = extract_double_to_float(ctx
, input
[chan
], 0);
718 out
[3] = LLVMConstReal(ctx
->f32
, 1);
720 case SI_FIX_FETCH_RGBA_64_FLOAT
:
721 for (chan
= 0; chan
< 4; chan
++) {
722 out
[chan
] = extract_double_to_float(ctx
, input
[chan
/ 2],
726 case SI_FIX_FETCH_RGB_8
:
727 case SI_FIX_FETCH_RGB_8_INT
:
728 case SI_FIX_FETCH_RGB_16
:
729 case SI_FIX_FETCH_RGB_16_INT
:
730 for (chan
= 0; chan
< 3; chan
++) {
731 out
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
735 if (fix_fetch
== SI_FIX_FETCH_RGB_8
||
736 fix_fetch
== SI_FIX_FETCH_RGB_16
) {
737 out
[3] = LLVMConstReal(ctx
->f32
, 1);
739 out
[3] = ac_to_float(&ctx
->ac
, ctx
->i32_1
);
745 static void declare_input_vs(
746 struct si_shader_context
*ctx
,
747 unsigned input_index
,
748 const struct tgsi_full_declaration
*decl
,
751 si_llvm_load_input_vs(ctx
, input_index
, out
);
754 static LLVMValueRef
get_primitive_id(struct si_shader_context
*ctx
,
761 case PIPE_SHADER_VERTEX
:
762 return LLVMGetParam(ctx
->main_fn
,
763 ctx
->param_vs_prim_id
);
764 case PIPE_SHADER_TESS_CTRL
:
765 return LLVMGetParam(ctx
->main_fn
,
766 ctx
->param_tcs_patch_id
);
767 case PIPE_SHADER_TESS_EVAL
:
768 return LLVMGetParam(ctx
->main_fn
,
769 ctx
->param_tes_patch_id
);
770 case PIPE_SHADER_GEOMETRY
:
771 return ctx
->abi
.gs_prim_id
;
779 * Return the value of tgsi_ind_register for indexing.
780 * This is the indirect index with the constant offset added to it.
782 LLVMValueRef
si_get_indirect_index(struct si_shader_context
*ctx
,
783 const struct tgsi_ind_register
*ind
,
789 if (ind
->File
== TGSI_FILE_ADDRESS
) {
790 result
= ctx
->addrs
[ind
->Index
][ind
->Swizzle
];
791 result
= LLVMBuildLoad(ctx
->ac
.builder
, result
, "");
793 struct tgsi_full_src_register src
= {};
795 src
.Register
.File
= ind
->File
;
796 src
.Register
.Index
= ind
->Index
;
798 /* Set the second index to 0 for constants. */
799 if (ind
->File
== TGSI_FILE_CONSTANT
)
800 src
.Register
.Dimension
= 1;
802 result
= ctx
->bld_base
.emit_fetch_funcs
[ind
->File
](&ctx
->bld_base
, &src
,
805 result
= ac_to_integer(&ctx
->ac
, result
);
809 result
= LLVMBuildMul(ctx
->ac
.builder
, result
,
810 LLVMConstInt(ctx
->i32
, addr_mul
, 0), "");
811 result
= LLVMBuildAdd(ctx
->ac
.builder
, result
,
812 LLVMConstInt(ctx
->i32
, rel_index
, 0), "");
817 * Like si_get_indirect_index, but restricts the return value to a (possibly
818 * undefined) value inside [0..num).
820 LLVMValueRef
si_get_bounded_indirect_index(struct si_shader_context
*ctx
,
821 const struct tgsi_ind_register
*ind
,
822 int rel_index
, unsigned num
)
824 LLVMValueRef result
= si_get_indirect_index(ctx
, ind
, 1, rel_index
);
826 return si_llvm_bound_index(ctx
, result
, num
);
831 * Calculate a dword address given an input or output register and a stride.
833 static LLVMValueRef
get_dw_address(struct si_shader_context
*ctx
,
834 const struct tgsi_full_dst_register
*dst
,
835 const struct tgsi_full_src_register
*src
,
836 LLVMValueRef vertex_dw_stride
,
837 LLVMValueRef base_addr
)
839 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
840 ubyte
*name
, *index
, *array_first
;
842 struct tgsi_full_dst_register reg
;
844 /* Set the register description. The address computation is the same
845 * for sources and destinations. */
847 reg
.Register
.File
= src
->Register
.File
;
848 reg
.Register
.Index
= src
->Register
.Index
;
849 reg
.Register
.Indirect
= src
->Register
.Indirect
;
850 reg
.Register
.Dimension
= src
->Register
.Dimension
;
851 reg
.Indirect
= src
->Indirect
;
852 reg
.Dimension
= src
->Dimension
;
853 reg
.DimIndirect
= src
->DimIndirect
;
857 /* If the register is 2-dimensional (e.g. an array of vertices
858 * in a primitive), calculate the base address of the vertex. */
859 if (reg
.Register
.Dimension
) {
862 if (reg
.Dimension
.Indirect
)
863 index
= si_get_indirect_index(ctx
, ®
.DimIndirect
,
864 1, reg
.Dimension
.Index
);
866 index
= LLVMConstInt(ctx
->i32
, reg
.Dimension
.Index
, 0);
868 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
869 LLVMBuildMul(ctx
->ac
.builder
, index
,
870 vertex_dw_stride
, ""), "");
873 /* Get information about the register. */
874 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
875 name
= info
->input_semantic_name
;
876 index
= info
->input_semantic_index
;
877 array_first
= info
->input_array_first
;
878 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
879 name
= info
->output_semantic_name
;
880 index
= info
->output_semantic_index
;
881 array_first
= info
->output_array_first
;
887 if (reg
.Register
.Indirect
) {
888 /* Add the relative address of the element. */
889 LLVMValueRef ind_index
;
891 if (reg
.Indirect
.ArrayID
)
892 first
= array_first
[reg
.Indirect
.ArrayID
];
894 first
= reg
.Register
.Index
;
896 ind_index
= si_get_indirect_index(ctx
, ®
.Indirect
,
897 1, reg
.Register
.Index
- first
);
899 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
900 LLVMBuildMul(ctx
->ac
.builder
, ind_index
,
901 LLVMConstInt(ctx
->i32
, 4, 0), ""), "");
903 param
= reg
.Register
.Dimension
?
904 si_shader_io_get_unique_index(name
[first
], index
[first
]) :
905 si_shader_io_get_unique_index_patch(name
[first
], index
[first
]);
907 param
= reg
.Register
.Dimension
?
908 si_shader_io_get_unique_index(name
[reg
.Register
.Index
],
909 index
[reg
.Register
.Index
]) :
910 si_shader_io_get_unique_index_patch(name
[reg
.Register
.Index
],
911 index
[reg
.Register
.Index
]);
914 /* Add the base address of the element. */
915 return LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
916 LLVMConstInt(ctx
->i32
, param
* 4, 0), "");
919 /* The offchip buffer layout for TCS->TES is
921 * - attribute 0 of patch 0 vertex 0
922 * - attribute 0 of patch 0 vertex 1
923 * - attribute 0 of patch 0 vertex 2
925 * - attribute 0 of patch 1 vertex 0
926 * - attribute 0 of patch 1 vertex 1
928 * - attribute 1 of patch 0 vertex 0
929 * - attribute 1 of patch 0 vertex 1
931 * - per patch attribute 0 of patch 0
932 * - per patch attribute 0 of patch 1
935 * Note that every attribute has 4 components.
937 static LLVMValueRef
get_tcs_tes_buffer_address(struct si_shader_context
*ctx
,
938 LLVMValueRef rel_patch_id
,
939 LLVMValueRef vertex_index
,
940 LLVMValueRef param_index
)
942 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
, total_vertices
;
943 LLVMValueRef param_stride
, constant16
;
945 vertices_per_patch
= get_num_tcs_out_vertices(ctx
);
946 num_patches
= unpack_param(ctx
, ctx
->param_tcs_offchip_layout
, 0, 6);
947 total_vertices
= LLVMBuildMul(ctx
->ac
.builder
, vertices_per_patch
,
950 constant16
= LLVMConstInt(ctx
->i32
, 16, 0);
952 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
953 vertices_per_patch
, "");
955 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
958 param_stride
= total_vertices
;
960 base_addr
= rel_patch_id
;
961 param_stride
= num_patches
;
964 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
965 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
966 param_stride
, ""), "");
968 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
971 LLVMValueRef patch_data_offset
=
972 unpack_param(ctx
, ctx
->param_tcs_offchip_layout
, 12, 20);
974 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
975 patch_data_offset
, "");
980 static LLVMValueRef
get_tcs_tes_buffer_address_from_reg(
981 struct si_shader_context
*ctx
,
982 const struct tgsi_full_dst_register
*dst
,
983 const struct tgsi_full_src_register
*src
)
985 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
986 ubyte
*name
, *index
, *array_first
;
987 struct tgsi_full_src_register reg
;
988 LLVMValueRef vertex_index
= NULL
;
989 LLVMValueRef param_index
= NULL
;
990 unsigned param_index_base
, param_base
;
992 reg
= src
? *src
: tgsi_full_src_register_from_dst(dst
);
994 if (reg
.Register
.Dimension
) {
996 if (reg
.Dimension
.Indirect
)
997 vertex_index
= si_get_indirect_index(ctx
, ®
.DimIndirect
,
998 1, reg
.Dimension
.Index
);
1000 vertex_index
= LLVMConstInt(ctx
->i32
, reg
.Dimension
.Index
, 0);
1003 /* Get information about the register. */
1004 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
1005 name
= info
->input_semantic_name
;
1006 index
= info
->input_semantic_index
;
1007 array_first
= info
->input_array_first
;
1008 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
1009 name
= info
->output_semantic_name
;
1010 index
= info
->output_semantic_index
;
1011 array_first
= info
->output_array_first
;
1017 if (reg
.Register
.Indirect
) {
1018 if (reg
.Indirect
.ArrayID
)
1019 param_base
= array_first
[reg
.Indirect
.ArrayID
];
1021 param_base
= reg
.Register
.Index
;
1023 param_index
= si_get_indirect_index(ctx
, ®
.Indirect
,
1024 1, reg
.Register
.Index
- param_base
);
1027 param_base
= reg
.Register
.Index
;
1028 param_index
= ctx
->i32_0
;
1031 param_index_base
= reg
.Register
.Dimension
?
1032 si_shader_io_get_unique_index(name
[param_base
], index
[param_base
]) :
1033 si_shader_io_get_unique_index_patch(name
[param_base
], index
[param_base
]);
1035 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, param_index
,
1036 LLVMConstInt(ctx
->i32
, param_index_base
, 0),
1039 return get_tcs_tes_buffer_address(ctx
, get_rel_patch_id(ctx
),
1040 vertex_index
, param_index
);
1043 static LLVMValueRef
buffer_load(struct lp_build_tgsi_context
*bld_base
,
1044 enum tgsi_opcode_type type
, unsigned swizzle
,
1045 LLVMValueRef buffer
, LLVMValueRef offset
,
1046 LLVMValueRef base
, bool can_speculate
)
1048 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1049 LLVMValueRef value
, value2
;
1050 LLVMTypeRef llvm_type
= tgsi2llvmtype(bld_base
, type
);
1051 LLVMTypeRef vec_type
= LLVMVectorType(llvm_type
, 4);
1053 if (swizzle
== ~0) {
1054 value
= ac_build_buffer_load(&ctx
->ac
, buffer
, 4, NULL
, base
, offset
,
1055 0, 1, 0, can_speculate
, false);
1057 return LLVMBuildBitCast(ctx
->ac
.builder
, value
, vec_type
, "");
1060 if (!tgsi_type_is_64bit(type
)) {
1061 value
= ac_build_buffer_load(&ctx
->ac
, buffer
, 4, NULL
, base
, offset
,
1062 0, 1, 0, can_speculate
, false);
1064 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, vec_type
, "");
1065 return LLVMBuildExtractElement(ctx
->ac
.builder
, value
,
1066 LLVMConstInt(ctx
->i32
, swizzle
, 0), "");
1069 value
= ac_build_buffer_load(&ctx
->ac
, buffer
, 1, NULL
, base
, offset
,
1070 swizzle
* 4, 1, 0, can_speculate
, false);
1072 value2
= ac_build_buffer_load(&ctx
->ac
, buffer
, 1, NULL
, base
, offset
,
1073 swizzle
* 4 + 4, 1, 0, can_speculate
, false);
1075 return si_llvm_emit_fetch_64bit(bld_base
, tgsi2llvmtype(bld_base
, type
),
1082 * \param type output value type
1083 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1084 * \param dw_addr address in dwords
1086 static LLVMValueRef
lds_load(struct lp_build_tgsi_context
*bld_base
,
1087 LLVMTypeRef type
, unsigned swizzle
,
1088 LLVMValueRef dw_addr
)
1090 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1093 if (swizzle
== ~0) {
1094 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
1096 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++)
1097 values
[chan
] = lds_load(bld_base
, type
, chan
, dw_addr
);
1099 return lp_build_gather_values(&ctx
->gallivm
, values
,
1103 /* Split 64-bit loads. */
1104 if (llvm_type_is_64bit(ctx
, type
)) {
1105 LLVMValueRef lo
, hi
;
1107 lo
= lds_load(bld_base
, ctx
->i32
, swizzle
, dw_addr
);
1108 hi
= lds_load(bld_base
, ctx
->i32
, swizzle
+ 1, dw_addr
);
1109 return si_llvm_emit_fetch_64bit(bld_base
, type
, lo
, hi
);
1112 dw_addr
= lp_build_add(&bld_base
->uint_bld
, dw_addr
,
1113 LLVMConstInt(ctx
->i32
, swizzle
, 0));
1115 value
= ac_lds_load(&ctx
->ac
, dw_addr
);
1117 return LLVMBuildBitCast(ctx
->ac
.builder
, value
, type
, "");
1123 * \param swizzle offset (typically 0..3)
1124 * \param dw_addr address in dwords
1125 * \param value value to store
1127 static void lds_store(struct si_shader_context
*ctx
,
1128 unsigned dw_offset_imm
, LLVMValueRef dw_addr
,
1131 dw_addr
= lp_build_add(&ctx
->bld_base
.uint_bld
, dw_addr
,
1132 LLVMConstInt(ctx
->i32
, dw_offset_imm
, 0));
1134 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
1137 static LLVMValueRef
desc_from_addr_base64k(struct si_shader_context
*ctx
,
1140 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1142 LLVMValueRef addr
= LLVMGetParam(ctx
->main_fn
, param
);
1143 addr
= LLVMBuildZExt(builder
, addr
, ctx
->i64
, "");
1144 addr
= LLVMBuildShl(builder
, addr
, LLVMConstInt(ctx
->i64
, 16, 0), "");
1146 uint64_t desc2
= 0xffffffff;
1147 uint64_t desc3
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1148 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1149 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1150 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1151 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1152 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1153 LLVMValueRef hi
= LLVMConstInt(ctx
->i64
, desc2
| (desc3
<< 32), 0);
1155 LLVMValueRef desc
= LLVMGetUndef(LLVMVectorType(ctx
->i64
, 2));
1156 desc
= LLVMBuildInsertElement(builder
, desc
, addr
, ctx
->i32_0
, "");
1157 desc
= LLVMBuildInsertElement(builder
, desc
, hi
, ctx
->i32_1
, "");
1158 return LLVMBuildBitCast(builder
, desc
, ctx
->v4i32
, "");
1161 static LLVMValueRef
fetch_input_tcs(
1162 struct lp_build_tgsi_context
*bld_base
,
1163 const struct tgsi_full_src_register
*reg
,
1164 enum tgsi_opcode_type type
, unsigned swizzle
)
1166 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1167 LLVMValueRef dw_addr
, stride
;
1169 stride
= get_tcs_in_vertex_dw_stride(ctx
);
1170 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1171 dw_addr
= get_dw_address(ctx
, NULL
, reg
, stride
, dw_addr
);
1173 return lds_load(bld_base
, tgsi2llvmtype(bld_base
, type
), swizzle
, dw_addr
);
1176 static LLVMValueRef
fetch_output_tcs(
1177 struct lp_build_tgsi_context
*bld_base
,
1178 const struct tgsi_full_src_register
*reg
,
1179 enum tgsi_opcode_type type
, unsigned swizzle
)
1181 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1182 LLVMValueRef dw_addr
, stride
;
1184 if (reg
->Register
.Dimension
) {
1185 stride
= get_tcs_out_vertex_dw_stride(ctx
);
1186 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1187 dw_addr
= get_dw_address(ctx
, NULL
, reg
, stride
, dw_addr
);
1189 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1190 dw_addr
= get_dw_address(ctx
, NULL
, reg
, NULL
, dw_addr
);
1193 return lds_load(bld_base
, tgsi2llvmtype(bld_base
, type
), swizzle
, dw_addr
);
1196 static LLVMValueRef
fetch_input_tes(
1197 struct lp_build_tgsi_context
*bld_base
,
1198 const struct tgsi_full_src_register
*reg
,
1199 enum tgsi_opcode_type type
, unsigned swizzle
)
1201 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1202 LLVMValueRef buffer
, base
, addr
;
1204 buffer
= desc_from_addr_base64k(ctx
, ctx
->param_tcs_offchip_addr_base64k
);
1206 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1207 addr
= get_tcs_tes_buffer_address_from_reg(ctx
, NULL
, reg
);
1209 return buffer_load(bld_base
, type
, swizzle
, buffer
, base
, addr
, true);
1212 static void store_output_tcs(struct lp_build_tgsi_context
*bld_base
,
1213 const struct tgsi_full_instruction
*inst
,
1214 const struct tgsi_opcode_info
*info
,
1216 LLVMValueRef dst
[4])
1218 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1219 const struct tgsi_full_dst_register
*reg
= &inst
->Dst
[index
];
1220 const struct tgsi_shader_info
*sh_info
= &ctx
->shader
->selector
->info
;
1221 unsigned chan_index
;
1222 LLVMValueRef dw_addr
, stride
;
1223 LLVMValueRef buffer
, base
, buf_addr
;
1224 LLVMValueRef values
[4];
1225 bool skip_lds_store
;
1226 bool is_tess_factor
= false, is_tess_inner
= false;
1228 /* Only handle per-patch and per-vertex outputs here.
1229 * Vectors will be lowered to scalars and this function will be called again.
1231 if (reg
->Register
.File
!= TGSI_FILE_OUTPUT
||
1232 (dst
[0] && LLVMGetTypeKind(LLVMTypeOf(dst
[0])) == LLVMVectorTypeKind
)) {
1233 si_llvm_emit_store(bld_base
, inst
, info
, index
, dst
);
1237 if (reg
->Register
.Dimension
) {
1238 stride
= get_tcs_out_vertex_dw_stride(ctx
);
1239 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1240 dw_addr
= get_dw_address(ctx
, reg
, NULL
, stride
, dw_addr
);
1241 skip_lds_store
= !sh_info
->reads_pervertex_outputs
;
1243 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1244 dw_addr
= get_dw_address(ctx
, reg
, NULL
, NULL
, dw_addr
);
1245 skip_lds_store
= !sh_info
->reads_perpatch_outputs
;
1247 if (!reg
->Register
.Indirect
) {
1248 int name
= sh_info
->output_semantic_name
[reg
->Register
.Index
];
1250 /* Always write tess factors into LDS for the TCS epilog. */
1251 if (name
== TGSI_SEMANTIC_TESSINNER
||
1252 name
== TGSI_SEMANTIC_TESSOUTER
) {
1253 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1254 skip_lds_store
= !sh_info
->reads_tessfactor_outputs
&&
1255 ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1256 is_tess_factor
= true;
1257 is_tess_inner
= name
== TGSI_SEMANTIC_TESSINNER
;
1262 buffer
= desc_from_addr_base64k(ctx
, ctx
->param_tcs_offchip_addr_base64k
);
1264 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1265 buf_addr
= get_tcs_tes_buffer_address_from_reg(ctx
, reg
, NULL
);
1267 uint32_t writemask
= reg
->Register
.WriteMask
;
1269 chan_index
= u_bit_scan(&writemask
);
1270 LLVMValueRef value
= dst
[chan_index
];
1272 if (inst
->Instruction
.Saturate
)
1273 value
= ac_build_clamp(&ctx
->ac
, value
);
1275 /* Skip LDS stores if there is no LDS read of this output. */
1276 if (!skip_lds_store
)
1277 lds_store(ctx
, chan_index
, dw_addr
, value
);
1279 value
= ac_to_integer(&ctx
->ac
, value
);
1280 values
[chan_index
] = value
;
1282 if (reg
->Register
.WriteMask
!= 0xF && !is_tess_factor
) {
1283 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 1,
1285 4 * chan_index
, 1, 0, true, false);
1288 /* Write tess factors into VGPRs for the epilog. */
1289 if (is_tess_factor
&&
1290 ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
) {
1291 if (!is_tess_inner
) {
1292 LLVMBuildStore(ctx
->ac
.builder
, value
, /* outer */
1293 ctx
->invoc0_tess_factors
[chan_index
]);
1294 } else if (chan_index
< 2) {
1295 LLVMBuildStore(ctx
->ac
.builder
, value
, /* inner */
1296 ctx
->invoc0_tess_factors
[4 + chan_index
]);
1301 if (reg
->Register
.WriteMask
== 0xF && !is_tess_factor
) {
1302 LLVMValueRef value
= lp_build_gather_values(&ctx
->gallivm
,
1304 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 4, buf_addr
,
1305 base
, 0, 1, 0, true, false);
1309 LLVMValueRef
si_llvm_load_input_gs(struct ac_shader_abi
*abi
,
1310 unsigned input_index
,
1311 unsigned vtx_offset_param
,
1315 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1316 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
1317 struct si_shader
*shader
= ctx
->shader
;
1318 struct lp_build_context
*uint
= &ctx
->bld_base
.uint_bld
;
1319 LLVMValueRef vtx_offset
, soffset
;
1320 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1321 unsigned semantic_name
= info
->input_semantic_name
[input_index
];
1322 unsigned semantic_index
= info
->input_semantic_index
[input_index
];
1326 param
= si_shader_io_get_unique_index(semantic_name
, semantic_index
);
1328 /* GFX9 has the ESGS ring in LDS. */
1329 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
1330 unsigned index
= vtx_offset_param
;
1332 switch (index
/ 2) {
1334 vtx_offset
= unpack_param(ctx
, ctx
->param_gs_vtx01_offset
,
1335 index
% 2 ? 16 : 0, 16);
1338 vtx_offset
= unpack_param(ctx
, ctx
->param_gs_vtx23_offset
,
1339 index
% 2 ? 16 : 0, 16);
1342 vtx_offset
= unpack_param(ctx
, ctx
->param_gs_vtx45_offset
,
1343 index
% 2 ? 16 : 0, 16);
1350 vtx_offset
= LLVMBuildAdd(ctx
->ac
.builder
, vtx_offset
,
1351 LLVMConstInt(ctx
->i32
, param
* 4, 0), "");
1352 return lds_load(bld_base
, type
, swizzle
, vtx_offset
);
1355 /* GFX6: input load from the ESGS ring in memory. */
1356 if (swizzle
== ~0) {
1357 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
1359 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1360 values
[chan
] = si_llvm_load_input_gs(abi
, input_index
, vtx_offset_param
,
1363 return lp_build_gather_values(&ctx
->gallivm
, values
,
1367 /* Get the vertex offset parameter on GFX6. */
1368 LLVMValueRef gs_vtx_offset
= ctx
->gs_vtx_offset
[vtx_offset_param
];
1370 vtx_offset
= lp_build_mul_imm(uint
, gs_vtx_offset
, 4);
1372 soffset
= LLVMConstInt(ctx
->i32
, (param
* 4 + swizzle
) * 256, 0);
1374 value
= ac_build_buffer_load(&ctx
->ac
, ctx
->esgs_ring
, 1, ctx
->i32_0
,
1375 vtx_offset
, soffset
, 0, 1, 0, true, false);
1376 if (llvm_type_is_64bit(ctx
, type
)) {
1377 LLVMValueRef value2
;
1378 soffset
= LLVMConstInt(ctx
->i32
, (param
* 4 + swizzle
+ 1) * 256, 0);
1380 value2
= ac_build_buffer_load(&ctx
->ac
, ctx
->esgs_ring
, 1,
1381 ctx
->i32_0
, vtx_offset
, soffset
,
1382 0, 1, 0, true, false);
1383 return si_llvm_emit_fetch_64bit(bld_base
, type
, value
, value2
);
1385 return LLVMBuildBitCast(ctx
->ac
.builder
, value
, type
, "");
1388 static LLVMValueRef
fetch_input_gs(
1389 struct lp_build_tgsi_context
*bld_base
,
1390 const struct tgsi_full_src_register
*reg
,
1391 enum tgsi_opcode_type type
,
1394 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1395 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1397 unsigned semantic_name
= info
->input_semantic_name
[reg
->Register
.Index
];
1398 if (swizzle
!= ~0 && semantic_name
== TGSI_SEMANTIC_PRIMID
)
1399 return get_primitive_id(ctx
, swizzle
);
1401 if (!reg
->Register
.Dimension
)
1404 return si_llvm_load_input_gs(&ctx
->abi
, reg
->Register
.Index
,
1405 reg
->Dimension
.Index
,
1406 tgsi2llvmtype(bld_base
, type
),
1410 static int lookup_interp_param_index(unsigned interpolate
, unsigned location
)
1412 switch (interpolate
) {
1413 case TGSI_INTERPOLATE_CONSTANT
:
1416 case TGSI_INTERPOLATE_LINEAR
:
1417 if (location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
1418 return SI_PARAM_LINEAR_SAMPLE
;
1419 else if (location
== TGSI_INTERPOLATE_LOC_CENTROID
)
1420 return SI_PARAM_LINEAR_CENTROID
;
1422 return SI_PARAM_LINEAR_CENTER
;
1424 case TGSI_INTERPOLATE_COLOR
:
1425 case TGSI_INTERPOLATE_PERSPECTIVE
:
1426 if (location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
1427 return SI_PARAM_PERSP_SAMPLE
;
1428 else if (location
== TGSI_INTERPOLATE_LOC_CENTROID
)
1429 return SI_PARAM_PERSP_CENTROID
;
1431 return SI_PARAM_PERSP_CENTER
;
1434 fprintf(stderr
, "Warning: Unhandled interpolation mode.\n");
1439 static LLVMValueRef
si_build_fs_interp(struct si_shader_context
*ctx
,
1440 unsigned attr_index
, unsigned chan
,
1441 LLVMValueRef prim_mask
,
1442 LLVMValueRef i
, LLVMValueRef j
)
1445 return ac_build_fs_interp(&ctx
->ac
,
1446 LLVMConstInt(ctx
->i32
, chan
, 0),
1447 LLVMConstInt(ctx
->i32
, attr_index
, 0),
1450 return ac_build_fs_interp_mov(&ctx
->ac
,
1451 LLVMConstInt(ctx
->i32
, 2, 0), /* P0 */
1452 LLVMConstInt(ctx
->i32
, chan
, 0),
1453 LLVMConstInt(ctx
->i32
, attr_index
, 0),
1458 * Interpolate a fragment shader input.
1460 * @param ctx context
1461 * @param input_index index of the input in hardware
1462 * @param semantic_name TGSI_SEMANTIC_*
1463 * @param semantic_index semantic index
1464 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1465 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1466 * @param interp_param interpolation weights (i,j)
1467 * @param prim_mask SI_PARAM_PRIM_MASK
1468 * @param face SI_PARAM_FRONT_FACE
1469 * @param result the return value (4 components)
1471 static void interp_fs_input(struct si_shader_context
*ctx
,
1472 unsigned input_index
,
1473 unsigned semantic_name
,
1474 unsigned semantic_index
,
1475 unsigned num_interp_inputs
,
1476 unsigned colors_read_mask
,
1477 LLVMValueRef interp_param
,
1478 LLVMValueRef prim_mask
,
1480 LLVMValueRef result
[4])
1482 LLVMValueRef i
= NULL
, j
= NULL
;
1485 /* fs.constant returns the param from the middle vertex, so it's not
1486 * really useful for flat shading. It's meant to be used for custom
1487 * interpolation (but the intrinsic can't fetch from the other two
1490 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1491 * to do the right thing. The only reason we use fs.constant is that
1492 * fs.interp cannot be used on integers, because they can be equal
1495 * When interp is false we will use fs.constant or for newer llvm,
1496 * amdgcn.interp.mov.
1498 bool interp
= interp_param
!= NULL
;
1501 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_param
,
1502 LLVMVectorType(ctx
->f32
, 2), "");
1504 i
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
1506 j
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
1510 if (semantic_name
== TGSI_SEMANTIC_COLOR
&&
1511 ctx
->shader
->key
.part
.ps
.prolog
.color_two_side
) {
1512 LLVMValueRef is_face_positive
;
1514 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1515 * otherwise it's at offset "num_inputs".
1517 unsigned back_attr_offset
= num_interp_inputs
;
1518 if (semantic_index
== 1 && colors_read_mask
& 0xf)
1519 back_attr_offset
+= 1;
1521 is_face_positive
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
,
1522 face
, ctx
->i32_0
, "");
1524 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1525 LLVMValueRef front
, back
;
1527 front
= si_build_fs_interp(ctx
,
1530 back
= si_build_fs_interp(ctx
,
1531 back_attr_offset
, chan
,
1534 result
[chan
] = LLVMBuildSelect(ctx
->ac
.builder
,
1540 } else if (semantic_name
== TGSI_SEMANTIC_FOG
) {
1541 result
[0] = si_build_fs_interp(ctx
, input_index
,
1542 0, prim_mask
, i
, j
);
1544 result
[2] = LLVMConstReal(ctx
->f32
, 0.0f
);
1545 result
[3] = LLVMConstReal(ctx
->f32
, 1.0f
);
1547 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1548 result
[chan
] = si_build_fs_interp(ctx
,
1555 void si_llvm_load_input_fs(
1556 struct si_shader_context
*ctx
,
1557 unsigned input_index
,
1558 LLVMValueRef out
[4])
1560 struct lp_build_context
*base
= &ctx
->bld_base
.base
;
1561 struct si_shader
*shader
= ctx
->shader
;
1562 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1563 LLVMValueRef main_fn
= ctx
->main_fn
;
1564 LLVMValueRef interp_param
= NULL
;
1565 int interp_param_idx
;
1566 enum tgsi_semantic semantic_name
= info
->input_semantic_name
[input_index
];
1567 unsigned semantic_index
= info
->input_semantic_index
[input_index
];
1568 enum tgsi_interpolate_mode interp_mode
= info
->input_interpolate
[input_index
];
1569 enum tgsi_interpolate_loc interp_loc
= info
->input_interpolate_loc
[input_index
];
1571 /* Get colors from input VGPRs (set by the prolog). */
1572 if (semantic_name
== TGSI_SEMANTIC_COLOR
) {
1573 unsigned colors_read
= shader
->selector
->info
.colors_read
;
1574 unsigned mask
= colors_read
>> (semantic_index
* 4);
1575 unsigned offset
= SI_PARAM_POS_FIXED_PT
+ 1 +
1576 (semantic_index
? util_bitcount(colors_read
& 0xf) : 0);
1578 out
[0] = mask
& 0x1 ? LLVMGetParam(main_fn
, offset
++) : base
->undef
;
1579 out
[1] = mask
& 0x2 ? LLVMGetParam(main_fn
, offset
++) : base
->undef
;
1580 out
[2] = mask
& 0x4 ? LLVMGetParam(main_fn
, offset
++) : base
->undef
;
1581 out
[3] = mask
& 0x8 ? LLVMGetParam(main_fn
, offset
++) : base
->undef
;
1585 interp_param_idx
= lookup_interp_param_index(interp_mode
, interp_loc
);
1586 if (interp_param_idx
== -1)
1588 else if (interp_param_idx
) {
1589 interp_param
= LLVMGetParam(ctx
->main_fn
, interp_param_idx
);
1592 interp_fs_input(ctx
, input_index
, semantic_name
,
1593 semantic_index
, 0, /* this param is unused */
1594 shader
->selector
->info
.colors_read
, interp_param
,
1595 LLVMGetParam(main_fn
, SI_PARAM_PRIM_MASK
),
1596 LLVMGetParam(main_fn
, SI_PARAM_FRONT_FACE
),
1600 static void declare_input_fs(
1601 struct si_shader_context
*ctx
,
1602 unsigned input_index
,
1603 const struct tgsi_full_declaration
*decl
,
1604 LLVMValueRef out
[4])
1606 si_llvm_load_input_fs(ctx
, input_index
, out
);
1609 static LLVMValueRef
get_sample_id(struct si_shader_context
*ctx
)
1611 return unpack_param(ctx
, SI_PARAM_ANCILLARY
, 8, 4);
1616 * Load a dword from a constant buffer.
1618 static LLVMValueRef
buffer_load_const(struct si_shader_context
*ctx
,
1619 LLVMValueRef resource
,
1620 LLVMValueRef offset
)
1622 return ac_build_buffer_load(&ctx
->ac
, resource
, 1, NULL
, offset
, NULL
,
1623 0, 0, 0, true, true);
1626 static LLVMValueRef
load_sample_position(struct si_shader_context
*ctx
, LLVMValueRef sample_id
)
1628 struct lp_build_context
*uint_bld
= &ctx
->bld_base
.uint_bld
;
1629 LLVMValueRef desc
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
1630 LLVMValueRef buf_index
= LLVMConstInt(ctx
->i32
, SI_PS_CONST_SAMPLE_POSITIONS
, 0);
1631 LLVMValueRef resource
= ac_build_load_to_sgpr(&ctx
->ac
, desc
, buf_index
);
1633 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1634 LLVMValueRef offset0
= lp_build_mul_imm(uint_bld
, sample_id
, 8);
1635 LLVMValueRef offset1
= LLVMBuildAdd(ctx
->ac
.builder
, offset0
, LLVMConstInt(ctx
->i32
, 4, 0), "");
1637 LLVMValueRef pos
[4] = {
1638 buffer_load_const(ctx
, resource
, offset0
),
1639 buffer_load_const(ctx
, resource
, offset1
),
1640 LLVMConstReal(ctx
->f32
, 0),
1641 LLVMConstReal(ctx
->f32
, 0)
1644 return lp_build_gather_values(&ctx
->gallivm
, pos
, 4);
1647 void si_load_system_value(struct si_shader_context
*ctx
,
1649 const struct tgsi_full_declaration
*decl
)
1651 struct lp_build_context
*bld
= &ctx
->bld_base
.base
;
1652 LLVMValueRef value
= 0;
1654 assert(index
< RADEON_LLVM_MAX_SYSTEM_VALUES
);
1656 switch (decl
->Semantic
.Name
) {
1657 case TGSI_SEMANTIC_INSTANCEID
:
1658 value
= ctx
->abi
.instance_id
;
1661 case TGSI_SEMANTIC_VERTEXID
:
1662 value
= LLVMBuildAdd(ctx
->ac
.builder
,
1664 ctx
->abi
.base_vertex
, "");
1667 case TGSI_SEMANTIC_VERTEXID_NOBASE
:
1668 /* Unused. Clarify the meaning in indexed vs. non-indexed
1669 * draws if this is ever used again. */
1673 case TGSI_SEMANTIC_BASEVERTEX
:
1675 /* For non-indexed draws, the base vertex set by the driver
1676 * (for direct draws) or the CP (for indirect draws) is the
1677 * first vertex ID, but GLSL expects 0 to be returned.
1679 LLVMValueRef vs_state
= LLVMGetParam(ctx
->main_fn
, ctx
->param_vs_state_bits
);
1680 LLVMValueRef indexed
;
1682 indexed
= LLVMBuildLShr(ctx
->ac
.builder
, vs_state
, ctx
->i32_1
, "");
1683 indexed
= LLVMBuildTrunc(ctx
->ac
.builder
, indexed
, ctx
->i1
, "");
1685 value
= LLVMBuildSelect(ctx
->ac
.builder
, indexed
,
1686 ctx
->abi
.base_vertex
, ctx
->i32_0
, "");
1690 case TGSI_SEMANTIC_BASEINSTANCE
:
1691 value
= ctx
->abi
.start_instance
;
1694 case TGSI_SEMANTIC_DRAWID
:
1695 value
= ctx
->abi
.draw_id
;
1698 case TGSI_SEMANTIC_INVOCATIONID
:
1699 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
1700 value
= unpack_param(ctx
, ctx
->param_tcs_rel_ids
, 8, 5);
1701 else if (ctx
->type
== PIPE_SHADER_GEOMETRY
)
1702 value
= ctx
->abi
.gs_invocation_id
;
1704 assert(!"INVOCATIONID not implemented");
1707 case TGSI_SEMANTIC_POSITION
:
1709 LLVMValueRef pos
[4] = {
1710 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_X_FLOAT
),
1711 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Y_FLOAT
),
1712 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Z_FLOAT
),
1713 lp_build_emit_llvm_unary(&ctx
->bld_base
, TGSI_OPCODE_RCP
,
1714 LLVMGetParam(ctx
->main_fn
,
1715 SI_PARAM_POS_W_FLOAT
)),
1717 value
= lp_build_gather_values(&ctx
->gallivm
, pos
, 4);
1721 case TGSI_SEMANTIC_FACE
:
1722 value
= ctx
->abi
.front_face
;
1725 case TGSI_SEMANTIC_SAMPLEID
:
1726 value
= get_sample_id(ctx
);
1729 case TGSI_SEMANTIC_SAMPLEPOS
: {
1730 LLVMValueRef pos
[4] = {
1731 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_X_FLOAT
),
1732 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Y_FLOAT
),
1733 LLVMConstReal(ctx
->f32
, 0),
1734 LLVMConstReal(ctx
->f32
, 0)
1736 pos
[0] = lp_build_emit_llvm_unary(&ctx
->bld_base
,
1737 TGSI_OPCODE_FRC
, pos
[0]);
1738 pos
[1] = lp_build_emit_llvm_unary(&ctx
->bld_base
,
1739 TGSI_OPCODE_FRC
, pos
[1]);
1740 value
= lp_build_gather_values(&ctx
->gallivm
, pos
, 4);
1744 case TGSI_SEMANTIC_SAMPLEMASK
:
1745 /* This can only occur with the OpenGL Core profile, which
1746 * doesn't support smoothing.
1748 value
= LLVMGetParam(ctx
->main_fn
, SI_PARAM_SAMPLE_COVERAGE
);
1751 case TGSI_SEMANTIC_TESSCOORD
:
1753 LLVMValueRef coord
[4] = {
1754 LLVMGetParam(ctx
->main_fn
, ctx
->param_tes_u
),
1755 LLVMGetParam(ctx
->main_fn
, ctx
->param_tes_v
),
1760 /* For triangles, the vector should be (u, v, 1-u-v). */
1761 if (ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] ==
1762 PIPE_PRIM_TRIANGLES
)
1763 coord
[2] = lp_build_sub(bld
, ctx
->ac
.f32_1
,
1764 lp_build_add(bld
, coord
[0], coord
[1]));
1766 value
= lp_build_gather_values(&ctx
->gallivm
, coord
, 4);
1770 case TGSI_SEMANTIC_VERTICESIN
:
1771 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
1772 value
= unpack_param(ctx
, ctx
->param_tcs_out_lds_layout
, 26, 6);
1773 else if (ctx
->type
== PIPE_SHADER_TESS_EVAL
)
1774 value
= get_num_tcs_out_vertices(ctx
);
1776 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1779 case TGSI_SEMANTIC_TESSINNER
:
1780 case TGSI_SEMANTIC_TESSOUTER
:
1782 LLVMValueRef buffer
, base
, addr
;
1783 int param
= si_shader_io_get_unique_index_patch(decl
->Semantic
.Name
, 0);
1785 buffer
= desc_from_addr_base64k(ctx
, ctx
->param_tcs_offchip_addr_base64k
);
1787 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1788 addr
= get_tcs_tes_buffer_address(ctx
, get_rel_patch_id(ctx
), NULL
,
1789 LLVMConstInt(ctx
->i32
, param
, 0));
1791 value
= buffer_load(&ctx
->bld_base
, TGSI_TYPE_FLOAT
,
1792 ~0, buffer
, base
, addr
, true);
1797 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
:
1798 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
:
1800 LLVMValueRef buf
, slot
, val
[4];
1803 slot
= LLVMConstInt(ctx
->i32
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, 0);
1804 buf
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
1805 buf
= ac_build_load_to_sgpr(&ctx
->ac
, buf
, slot
);
1806 offset
= decl
->Semantic
.Name
== TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
? 4 : 0;
1808 for (i
= 0; i
< 4; i
++)
1809 val
[i
] = buffer_load_const(ctx
, buf
,
1810 LLVMConstInt(ctx
->i32
, (offset
+ i
) * 4, 0));
1811 value
= lp_build_gather_values(&ctx
->gallivm
, val
, 4);
1815 case TGSI_SEMANTIC_PRIMID
:
1816 value
= get_primitive_id(ctx
, 0);
1819 case TGSI_SEMANTIC_GRID_SIZE
:
1820 value
= LLVMGetParam(ctx
->main_fn
, ctx
->param_grid_size
);
1823 case TGSI_SEMANTIC_BLOCK_SIZE
:
1825 LLVMValueRef values
[3];
1827 unsigned *properties
= ctx
->shader
->selector
->info
.properties
;
1829 if (properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] != 0) {
1830 unsigned sizes
[3] = {
1831 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
],
1832 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
],
1833 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
]
1836 for (i
= 0; i
< 3; ++i
)
1837 values
[i
] = LLVMConstInt(ctx
->i32
, sizes
[i
], 0);
1839 value
= lp_build_gather_values(&ctx
->gallivm
, values
, 3);
1841 value
= LLVMGetParam(ctx
->main_fn
, ctx
->param_block_size
);
1846 case TGSI_SEMANTIC_BLOCK_ID
:
1848 LLVMValueRef values
[3];
1850 for (int i
= 0; i
< 3; i
++) {
1851 values
[i
] = ctx
->i32_0
;
1852 if (ctx
->param_block_id
[i
] >= 0) {
1853 values
[i
] = LLVMGetParam(ctx
->main_fn
,
1854 ctx
->param_block_id
[i
]);
1857 value
= lp_build_gather_values(&ctx
->gallivm
, values
, 3);
1861 case TGSI_SEMANTIC_THREAD_ID
:
1862 value
= LLVMGetParam(ctx
->main_fn
, ctx
->param_thread_id
);
1865 case TGSI_SEMANTIC_HELPER_INVOCATION
:
1866 value
= lp_build_intrinsic(ctx
->ac
.builder
,
1867 "llvm.amdgcn.ps.live",
1869 LP_FUNC_ATTR_READNONE
);
1870 value
= LLVMBuildNot(ctx
->ac
.builder
, value
, "");
1871 value
= LLVMBuildSExt(ctx
->ac
.builder
, value
, ctx
->i32
, "");
1874 case TGSI_SEMANTIC_SUBGROUP_SIZE
:
1875 value
= LLVMConstInt(ctx
->i32
, 64, 0);
1878 case TGSI_SEMANTIC_SUBGROUP_INVOCATION
:
1879 value
= ac_get_thread_id(&ctx
->ac
);
1882 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK
:
1884 LLVMValueRef id
= ac_get_thread_id(&ctx
->ac
);
1885 id
= LLVMBuildZExt(ctx
->ac
.builder
, id
, ctx
->i64
, "");
1886 value
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->i64
, 1, 0), id
, "");
1887 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->v2i32
, "");
1891 case TGSI_SEMANTIC_SUBGROUP_GE_MASK
:
1892 case TGSI_SEMANTIC_SUBGROUP_GT_MASK
:
1893 case TGSI_SEMANTIC_SUBGROUP_LE_MASK
:
1894 case TGSI_SEMANTIC_SUBGROUP_LT_MASK
:
1896 LLVMValueRef id
= ac_get_thread_id(&ctx
->ac
);
1897 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_GT_MASK
||
1898 decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_LE_MASK
) {
1899 /* All bits set except LSB */
1900 value
= LLVMConstInt(ctx
->i64
, -2, 0);
1903 value
= LLVMConstInt(ctx
->i64
, -1, 0);
1905 id
= LLVMBuildZExt(ctx
->ac
.builder
, id
, ctx
->i64
, "");
1906 value
= LLVMBuildShl(ctx
->ac
.builder
, value
, id
, "");
1907 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_LE_MASK
||
1908 decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_LT_MASK
)
1909 value
= LLVMBuildNot(ctx
->ac
.builder
, value
, "");
1910 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->v2i32
, "");
1915 assert(!"unknown system value");
1919 ctx
->system_values
[index
] = value
;
1922 void si_declare_compute_memory(struct si_shader_context
*ctx
,
1923 const struct tgsi_full_declaration
*decl
)
1925 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
1927 LLVMTypeRef i8p
= LLVMPointerType(ctx
->i8
, LOCAL_ADDR_SPACE
);
1930 assert(decl
->Declaration
.MemType
== TGSI_MEMORY_TYPE_SHARED
);
1931 assert(decl
->Range
.First
== decl
->Range
.Last
);
1932 assert(!ctx
->ac
.lds
);
1934 var
= LLVMAddGlobalInAddressSpace(ctx
->ac
.module
,
1935 LLVMArrayType(ctx
->i8
, sel
->local_size
),
1938 LLVMSetAlignment(var
, 4);
1940 ctx
->ac
.lds
= LLVMBuildBitCast(ctx
->ac
.builder
, var
, i8p
, "");
1943 static LLVMValueRef
load_const_buffer_desc(struct si_shader_context
*ctx
, int i
)
1945 LLVMValueRef list_ptr
= LLVMGetParam(ctx
->main_fn
,
1946 ctx
->param_const_and_shader_buffers
);
1948 return ac_build_load_to_sgpr(&ctx
->ac
, list_ptr
,
1949 LLVMConstInt(ctx
->i32
, si_get_constbuf_slot(i
), 0));
1952 static LLVMValueRef
load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef index
)
1954 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1955 LLVMValueRef ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_const_and_shader_buffers
);
1957 index
= si_llvm_bound_index(ctx
, index
, ctx
->num_const_buffers
);
1958 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
1959 LLVMConstInt(ctx
->i32
, SI_NUM_SHADER_BUFFERS
, 0), "");
1961 return ac_build_load_to_sgpr(&ctx
->ac
, ptr
, index
);
1965 load_ssbo(struct ac_shader_abi
*abi
, LLVMValueRef index
, bool write
)
1967 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1968 LLVMValueRef rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
1969 ctx
->param_const_and_shader_buffers
);
1971 index
= si_llvm_bound_index(ctx
, index
, ctx
->num_shader_buffers
);
1972 index
= LLVMBuildSub(ctx
->ac
.builder
,
1973 LLVMConstInt(ctx
->i32
, SI_NUM_SHADER_BUFFERS
- 1, 0),
1976 return ac_build_load_to_sgpr(&ctx
->ac
, rsrc_ptr
, index
);
1979 static LLVMValueRef
fetch_constant(
1980 struct lp_build_tgsi_context
*bld_base
,
1981 const struct tgsi_full_src_register
*reg
,
1982 enum tgsi_opcode_type type
,
1985 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1986 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
1987 const struct tgsi_ind_register
*ireg
= ®
->Indirect
;
1990 LLVMValueRef addr
, bufp
;
1992 if (swizzle
== LP_CHAN_ALL
) {
1994 LLVMValueRef values
[4];
1995 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; ++chan
)
1996 values
[chan
] = fetch_constant(bld_base
, reg
, type
, chan
);
1998 return lp_build_gather_values(&ctx
->gallivm
, values
, 4);
2001 /* Split 64-bit loads. */
2002 if (tgsi_type_is_64bit(type
)) {
2003 LLVMValueRef lo
, hi
;
2005 lo
= fetch_constant(bld_base
, reg
, TGSI_TYPE_UNSIGNED
, swizzle
);
2006 hi
= fetch_constant(bld_base
, reg
, TGSI_TYPE_UNSIGNED
, swizzle
+ 1);
2007 return si_llvm_emit_fetch_64bit(bld_base
, tgsi2llvmtype(bld_base
, type
),
2011 idx
= reg
->Register
.Index
* 4 + swizzle
;
2012 if (reg
->Register
.Indirect
) {
2013 addr
= si_get_indirect_index(ctx
, ireg
, 16, idx
* 4);
2015 addr
= LLVMConstInt(ctx
->i32
, idx
* 4, 0);
2018 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2019 if (sel
->info
.const_buffers_declared
== 1 &&
2020 sel
->info
.shader_buffers_declared
== 0) {
2022 LLVMGetParam(ctx
->main_fn
, ctx
->param_const_and_shader_buffers
);
2024 /* This enables use of s_load_dword and flat_load_dword for const buffer 0
2025 * loads, and up to x4 load opcode merging. However, it leads to horrible
2026 * code reducing SIMD wave occupancy from 8 to 2 in many cases.
2028 * Using s_buffer_load_dword (x1) seems to be the best option right now.
2030 * LLVM 5.0 on SI doesn't insert a required s_nop between SALU setting
2031 * a descriptor and s_buffer_load_dword using it, so we can't expand
2032 * the pointer into a full descriptor like below. We have to use
2033 * s_load_dword instead. The only case when LLVM 5.0 would select
2034 * s_buffer_load_dword (that we have to prevent) is when we use use
2035 * a literal offset where we don't need bounds checking.
2037 if (ctx
->screen
->info
.chip_class
== SI
&&
2038 HAVE_LLVM
< 0x0600 &&
2039 !reg
->Register
.Indirect
) {
2040 addr
= LLVMBuildLShr(ctx
->ac
.builder
, addr
, LLVMConstInt(ctx
->i32
, 2, 0), "");
2041 LLVMValueRef result
= ac_build_load_invariant(&ctx
->ac
, ptr
, addr
);
2042 return bitcast(bld_base
, type
, result
);
2045 /* Do the bounds checking with a descriptor, because
2046 * doing computation and manual bounds checking of 64-bit
2047 * addresses generates horrible VALU code with very high
2048 * VGPR usage and very low SIMD occupancy.
2050 ptr
= LLVMBuildPtrToInt(ctx
->ac
.builder
, ptr
, ctx
->i64
, "");
2051 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
, ctx
->v2i32
, "");
2053 LLVMValueRef desc_elems
[] = {
2054 LLVMBuildExtractElement(ctx
->ac
.builder
, ptr
, ctx
->i32_0
, ""),
2055 LLVMBuildExtractElement(ctx
->ac
.builder
, ptr
, ctx
->i32_1
, ""),
2056 LLVMConstInt(ctx
->i32
, (sel
->info
.const_file_max
[0] + 1) * 16, 0),
2057 LLVMConstInt(ctx
->i32
,
2058 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2059 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2060 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2061 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2062 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2063 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
), 0)
2065 LLVMValueRef desc
= ac_build_gather_values(&ctx
->ac
, desc_elems
, 4);
2066 LLVMValueRef result
= buffer_load_const(ctx
, desc
, addr
);
2067 return bitcast(bld_base
, type
, result
);
2070 assert(reg
->Register
.Dimension
);
2071 buf
= reg
->Dimension
.Index
;
2073 if (reg
->Dimension
.Indirect
) {
2074 LLVMValueRef ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_const_and_shader_buffers
);
2076 index
= si_get_bounded_indirect_index(ctx
, ®
->DimIndirect
,
2077 reg
->Dimension
.Index
,
2078 ctx
->num_const_buffers
);
2079 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
2080 LLVMConstInt(ctx
->i32
, SI_NUM_SHADER_BUFFERS
, 0), "");
2081 bufp
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
, index
);
2083 bufp
= load_const_buffer_desc(ctx
, buf
);
2085 return bitcast(bld_base
, type
, buffer_load_const(ctx
, bufp
, addr
));
2088 /* Upper 16 bits must be zero. */
2089 static LLVMValueRef
si_llvm_pack_two_int16(struct si_shader_context
*ctx
,
2090 LLVMValueRef val
[2])
2092 return LLVMBuildOr(ctx
->ac
.builder
, val
[0],
2093 LLVMBuildShl(ctx
->ac
.builder
, val
[1],
2094 LLVMConstInt(ctx
->i32
, 16, 0),
2098 /* Upper 16 bits are ignored and will be dropped. */
2099 static LLVMValueRef
si_llvm_pack_two_int32_as_int16(struct si_shader_context
*ctx
,
2100 LLVMValueRef val
[2])
2102 LLVMValueRef v
[2] = {
2103 LLVMBuildAnd(ctx
->ac
.builder
, val
[0],
2104 LLVMConstInt(ctx
->i32
, 0xffff, 0), ""),
2107 return si_llvm_pack_two_int16(ctx
, v
);
2110 /* Initialize arguments for the shader export intrinsic */
2111 static void si_llvm_init_export_args(struct si_shader_context
*ctx
,
2112 LLVMValueRef
*values
,
2114 struct ac_export_args
*args
)
2116 LLVMValueRef f32undef
= LLVMGetUndef(ctx
->ac
.f32
);
2117 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2118 LLVMValueRef val
[4];
2119 unsigned spi_shader_col_format
= V_028714_SPI_SHADER_32_ABGR
;
2121 bool is_int8
, is_int10
;
2123 /* Default is 0xf. Adjusted below depending on the format. */
2124 args
->enabled_channels
= 0xf; /* writemask */
2126 /* Specify whether the EXEC mask represents the valid mask */
2127 args
->valid_mask
= 0;
2129 /* Specify whether this is the last export */
2132 /* Specify the target we are exporting */
2133 args
->target
= target
;
2135 if (ctx
->type
== PIPE_SHADER_FRAGMENT
) {
2136 const struct si_shader_key
*key
= &ctx
->shader
->key
;
2137 unsigned col_formats
= key
->part
.ps
.epilog
.spi_shader_col_format
;
2138 int cbuf
= target
- V_008DFC_SQ_EXP_MRT
;
2140 assert(cbuf
>= 0 && cbuf
< 8);
2141 spi_shader_col_format
= (col_formats
>> (cbuf
* 4)) & 0xf;
2142 is_int8
= (key
->part
.ps
.epilog
.color_is_int8
>> cbuf
) & 0x1;
2143 is_int10
= (key
->part
.ps
.epilog
.color_is_int10
>> cbuf
) & 0x1;
2146 args
->compr
= false;
2147 args
->out
[0] = f32undef
;
2148 args
->out
[1] = f32undef
;
2149 args
->out
[2] = f32undef
;
2150 args
->out
[3] = f32undef
;
2152 switch (spi_shader_col_format
) {
2153 case V_028714_SPI_SHADER_ZERO
:
2154 args
->enabled_channels
= 0; /* writemask */
2155 args
->target
= V_008DFC_SQ_EXP_NULL
;
2158 case V_028714_SPI_SHADER_32_R
:
2159 args
->enabled_channels
= 1; /* writemask */
2160 args
->out
[0] = values
[0];
2163 case V_028714_SPI_SHADER_32_GR
:
2164 args
->enabled_channels
= 0x3; /* writemask */
2165 args
->out
[0] = values
[0];
2166 args
->out
[1] = values
[1];
2169 case V_028714_SPI_SHADER_32_AR
:
2170 args
->enabled_channels
= 0x9; /* writemask */
2171 args
->out
[0] = values
[0];
2172 args
->out
[3] = values
[3];
2175 case V_028714_SPI_SHADER_FP16_ABGR
:
2176 args
->compr
= 1; /* COMPR flag */
2178 for (chan
= 0; chan
< 2; chan
++) {
2179 LLVMValueRef pack_args
[2] = {
2181 values
[2 * chan
+ 1]
2183 LLVMValueRef packed
;
2185 packed
= ac_build_cvt_pkrtz_f16(&ctx
->ac
, pack_args
);
2186 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2190 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2191 for (chan
= 0; chan
< 4; chan
++) {
2192 val
[chan
] = ac_build_clamp(&ctx
->ac
, values
[chan
]);
2193 val
[chan
] = LLVMBuildFMul(builder
, val
[chan
],
2194 LLVMConstReal(ctx
->f32
, 65535), "");
2195 val
[chan
] = LLVMBuildFAdd(builder
, val
[chan
],
2196 LLVMConstReal(ctx
->f32
, 0.5), "");
2197 val
[chan
] = LLVMBuildFPToUI(builder
, val
[chan
],
2201 args
->compr
= 1; /* COMPR flag */
2202 args
->out
[0] = ac_to_float(&ctx
->ac
, si_llvm_pack_two_int16(ctx
, val
));
2203 args
->out
[1] = ac_to_float(&ctx
->ac
, si_llvm_pack_two_int16(ctx
, val
+2));
2206 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2207 for (chan
= 0; chan
< 4; chan
++) {
2208 /* Clamp between [-1, 1]. */
2209 val
[chan
] = lp_build_emit_llvm_binary(&ctx
->bld_base
, TGSI_OPCODE_MIN
,
2211 LLVMConstReal(ctx
->f32
, 1));
2212 val
[chan
] = lp_build_emit_llvm_binary(&ctx
->bld_base
, TGSI_OPCODE_MAX
,
2214 LLVMConstReal(ctx
->f32
, -1));
2215 /* Convert to a signed integer in [-32767, 32767]. */
2216 val
[chan
] = LLVMBuildFMul(builder
, val
[chan
],
2217 LLVMConstReal(ctx
->f32
, 32767), "");
2218 /* If positive, add 0.5, else add -0.5. */
2219 val
[chan
] = LLVMBuildFAdd(builder
, val
[chan
],
2220 LLVMBuildSelect(builder
,
2221 LLVMBuildFCmp(builder
, LLVMRealOGE
,
2222 val
[chan
], ctx
->ac
.f32_0
, ""),
2223 LLVMConstReal(ctx
->f32
, 0.5),
2224 LLVMConstReal(ctx
->f32
, -0.5), ""), "");
2225 val
[chan
] = LLVMBuildFPToSI(builder
, val
[chan
], ctx
->i32
, "");
2228 args
->compr
= 1; /* COMPR flag */
2229 args
->out
[0] = ac_to_float(&ctx
->ac
, si_llvm_pack_two_int32_as_int16(ctx
, val
));
2230 args
->out
[1] = ac_to_float(&ctx
->ac
, si_llvm_pack_two_int32_as_int16(ctx
, val
+2));
2233 case V_028714_SPI_SHADER_UINT16_ABGR
: {
2234 LLVMValueRef max_rgb
= LLVMConstInt(ctx
->i32
,
2235 is_int8
? 255 : is_int10
? 1023 : 65535, 0);
2236 LLVMValueRef max_alpha
=
2237 !is_int10
? max_rgb
: LLVMConstInt(ctx
->i32
, 3, 0);
2240 for (chan
= 0; chan
< 4; chan
++) {
2241 val
[chan
] = ac_to_integer(&ctx
->ac
, values
[chan
]);
2242 val
[chan
] = lp_build_emit_llvm_binary(&ctx
->bld_base
, TGSI_OPCODE_UMIN
,
2244 chan
== 3 ? max_alpha
: max_rgb
);
2247 args
->compr
= 1; /* COMPR flag */
2248 args
->out
[0] = ac_to_float(&ctx
->ac
, si_llvm_pack_two_int16(ctx
, val
));
2249 args
->out
[1] = ac_to_float(&ctx
->ac
, si_llvm_pack_two_int16(ctx
, val
+2));
2253 case V_028714_SPI_SHADER_SINT16_ABGR
: {
2254 LLVMValueRef max_rgb
= LLVMConstInt(ctx
->i32
,
2255 is_int8
? 127 : is_int10
? 511 : 32767, 0);
2256 LLVMValueRef min_rgb
= LLVMConstInt(ctx
->i32
,
2257 is_int8
? -128 : is_int10
? -512 : -32768, 0);
2258 LLVMValueRef max_alpha
=
2259 !is_int10
? max_rgb
: ctx
->i32_1
;
2260 LLVMValueRef min_alpha
=
2261 !is_int10
? min_rgb
: LLVMConstInt(ctx
->i32
, -2, 0);
2264 for (chan
= 0; chan
< 4; chan
++) {
2265 val
[chan
] = ac_to_integer(&ctx
->ac
, values
[chan
]);
2266 val
[chan
] = lp_build_emit_llvm_binary(&ctx
->bld_base
,
2268 val
[chan
], chan
== 3 ? max_alpha
: max_rgb
);
2269 val
[chan
] = lp_build_emit_llvm_binary(&ctx
->bld_base
,
2271 val
[chan
], chan
== 3 ? min_alpha
: min_rgb
);
2274 args
->compr
= 1; /* COMPR flag */
2275 args
->out
[0] = ac_to_float(&ctx
->ac
, si_llvm_pack_two_int32_as_int16(ctx
, val
));
2276 args
->out
[1] = ac_to_float(&ctx
->ac
, si_llvm_pack_two_int32_as_int16(ctx
, val
+2));
2280 case V_028714_SPI_SHADER_32_ABGR
:
2281 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2286 static void si_alpha_test(struct lp_build_tgsi_context
*bld_base
,
2289 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2291 if (ctx
->shader
->key
.part
.ps
.epilog
.alpha_func
!= PIPE_FUNC_NEVER
) {
2292 static LLVMRealPredicate cond_map
[PIPE_FUNC_ALWAYS
+ 1] = {
2293 [PIPE_FUNC_LESS
] = LLVMRealOLT
,
2294 [PIPE_FUNC_EQUAL
] = LLVMRealOEQ
,
2295 [PIPE_FUNC_LEQUAL
] = LLVMRealOLE
,
2296 [PIPE_FUNC_GREATER
] = LLVMRealOGT
,
2297 [PIPE_FUNC_NOTEQUAL
] = LLVMRealONE
,
2298 [PIPE_FUNC_GEQUAL
] = LLVMRealOGE
,
2300 LLVMRealPredicate cond
= cond_map
[ctx
->shader
->key
.part
.ps
.epilog
.alpha_func
];
2303 LLVMValueRef alpha_ref
= LLVMGetParam(ctx
->main_fn
,
2304 SI_PARAM_ALPHA_REF
);
2305 LLVMValueRef alpha_pass
=
2306 LLVMBuildFCmp(ctx
->ac
.builder
, cond
, alpha
, alpha_ref
, "");
2307 ac_build_kill_if_false(&ctx
->ac
, alpha_pass
);
2309 ac_build_kill_if_false(&ctx
->ac
, LLVMConstInt(ctx
->i1
, 0, 0));
2313 static LLVMValueRef
si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context
*bld_base
,
2315 unsigned samplemask_param
)
2317 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2318 LLVMValueRef coverage
;
2320 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2321 coverage
= LLVMGetParam(ctx
->main_fn
,
2323 coverage
= ac_to_integer(&ctx
->ac
, coverage
);
2325 coverage
= lp_build_intrinsic(ctx
->ac
.builder
, "llvm.ctpop.i32",
2327 &coverage
, 1, LP_FUNC_ATTR_READNONE
);
2329 coverage
= LLVMBuildUIToFP(ctx
->ac
.builder
, coverage
,
2332 coverage
= LLVMBuildFMul(ctx
->ac
.builder
, coverage
,
2333 LLVMConstReal(ctx
->f32
,
2334 1.0 / SI_NUM_SMOOTH_AA_SAMPLES
), "");
2336 return LLVMBuildFMul(ctx
->ac
.builder
, alpha
, coverage
, "");
2339 static void si_llvm_emit_clipvertex(struct si_shader_context
*ctx
,
2340 struct ac_export_args
*pos
, LLVMValueRef
*out_elts
)
2344 unsigned const_chan
;
2345 LLVMValueRef base_elt
;
2346 LLVMValueRef ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
2347 LLVMValueRef constbuf_index
= LLVMConstInt(ctx
->i32
,
2348 SI_VS_CONST_CLIP_PLANES
, 0);
2349 LLVMValueRef const_resource
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
, constbuf_index
);
2351 for (reg_index
= 0; reg_index
< 2; reg_index
++) {
2352 struct ac_export_args
*args
= &pos
[2 + reg_index
];
2357 args
->out
[3] = LLVMConstReal(ctx
->f32
, 0.0f
);
2359 /* Compute dot products of position and user clip plane vectors */
2360 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2361 for (const_chan
= 0; const_chan
< TGSI_NUM_CHANNELS
; const_chan
++) {
2363 LLVMConstInt(ctx
->i32
, ((reg_index
* 4 + chan
) * 4 +
2364 const_chan
) * 4, 0);
2365 base_elt
= buffer_load_const(ctx
, const_resource
,
2368 lp_build_add(&ctx
->bld_base
.base
, args
->out
[chan
],
2369 lp_build_mul(&ctx
->bld_base
.base
, base_elt
,
2370 out_elts
[const_chan
]));
2374 args
->enabled_channels
= 0xf;
2375 args
->valid_mask
= 0;
2377 args
->target
= V_008DFC_SQ_EXP_POS
+ 2 + reg_index
;
2382 static void si_dump_streamout(struct pipe_stream_output_info
*so
)
2386 if (so
->num_outputs
)
2387 fprintf(stderr
, "STREAMOUT\n");
2389 for (i
= 0; i
< so
->num_outputs
; i
++) {
2390 unsigned mask
= ((1 << so
->output
[i
].num_components
) - 1) <<
2391 so
->output
[i
].start_component
;
2392 fprintf(stderr
, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2393 i
, so
->output
[i
].output_buffer
,
2394 so
->output
[i
].dst_offset
, so
->output
[i
].dst_offset
+ so
->output
[i
].num_components
- 1,
2395 so
->output
[i
].register_index
,
2396 mask
& 1 ? "x" : "",
2397 mask
& 2 ? "y" : "",
2398 mask
& 4 ? "z" : "",
2399 mask
& 8 ? "w" : "");
2403 static void emit_streamout_output(struct si_shader_context
*ctx
,
2404 LLVMValueRef
const *so_buffers
,
2405 LLVMValueRef
const *so_write_offsets
,
2406 struct pipe_stream_output
*stream_out
,
2407 struct si_shader_output_values
*shader_out
)
2409 unsigned buf_idx
= stream_out
->output_buffer
;
2410 unsigned start
= stream_out
->start_component
;
2411 unsigned num_comps
= stream_out
->num_components
;
2412 LLVMValueRef out
[4];
2414 assert(num_comps
&& num_comps
<= 4);
2415 if (!num_comps
|| num_comps
> 4)
2418 /* Load the output as int. */
2419 for (int j
= 0; j
< num_comps
; j
++) {
2420 assert(stream_out
->stream
== shader_out
->vertex_stream
[start
+ j
]);
2422 out
[j
] = ac_to_integer(&ctx
->ac
, shader_out
->values
[start
+ j
]);
2425 /* Pack the output. */
2426 LLVMValueRef vdata
= NULL
;
2428 switch (num_comps
) {
2429 case 1: /* as i32 */
2432 case 2: /* as v2i32 */
2433 case 3: /* as v4i32 (aligned to 4) */
2434 case 4: /* as v4i32 */
2435 vdata
= LLVMGetUndef(LLVMVectorType(ctx
->i32
, util_next_power_of_two(num_comps
)));
2436 for (int j
= 0; j
< num_comps
; j
++) {
2437 vdata
= LLVMBuildInsertElement(ctx
->ac
.builder
, vdata
, out
[j
],
2438 LLVMConstInt(ctx
->i32
, j
, 0), "");
2443 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf_idx
],
2445 so_write_offsets
[buf_idx
],
2447 stream_out
->dst_offset
* 4, 1, 1, true, false);
2451 * Write streamout data to buffers for vertex stream @p stream (different
2452 * vertex streams can occur for GS copy shaders).
2454 static void si_llvm_emit_streamout(struct si_shader_context
*ctx
,
2455 struct si_shader_output_values
*outputs
,
2456 unsigned noutput
, unsigned stream
)
2458 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2459 struct pipe_stream_output_info
*so
= &sel
->so
;
2460 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2462 struct lp_build_if_state if_ctx
;
2464 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2465 LLVMValueRef so_vtx_count
=
2466 unpack_param(ctx
, ctx
->param_streamout_config
, 16, 7);
2468 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
2470 /* can_emit = tid < so_vtx_count; */
2471 LLVMValueRef can_emit
=
2472 LLVMBuildICmp(builder
, LLVMIntULT
, tid
, so_vtx_count
, "");
2474 /* Emit the streamout code conditionally. This actually avoids
2475 * out-of-bounds buffer access. The hw tells us via the SGPR
2476 * (so_vtx_count) which threads are allowed to emit streamout data. */
2477 lp_build_if(&if_ctx
, &ctx
->gallivm
, can_emit
);
2479 /* The buffer offset is computed as follows:
2480 * ByteOffset = streamout_offset[buffer_id]*4 +
2481 * (streamout_write_index + thread_id)*stride[buffer_id] +
2485 LLVMValueRef so_write_index
=
2486 LLVMGetParam(ctx
->main_fn
,
2487 ctx
->param_streamout_write_index
);
2489 /* Compute (streamout_write_index + thread_id). */
2490 so_write_index
= LLVMBuildAdd(builder
, so_write_index
, tid
, "");
2492 /* Load the descriptor and compute the write offset for each
2493 * enabled buffer. */
2494 LLVMValueRef so_write_offset
[4] = {};
2495 LLVMValueRef so_buffers
[4];
2496 LLVMValueRef buf_ptr
= LLVMGetParam(ctx
->main_fn
,
2497 ctx
->param_rw_buffers
);
2499 for (i
= 0; i
< 4; i
++) {
2503 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
,
2504 SI_VS_STREAMOUT_BUF0
+ i
, 0);
2506 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
, offset
);
2508 LLVMValueRef so_offset
= LLVMGetParam(ctx
->main_fn
,
2509 ctx
->param_streamout_offset
[i
]);
2510 so_offset
= LLVMBuildMul(builder
, so_offset
, LLVMConstInt(ctx
->i32
, 4, 0), "");
2512 so_write_offset
[i
] = LLVMBuildMul(builder
, so_write_index
,
2513 LLVMConstInt(ctx
->i32
, so
->stride
[i
]*4, 0), "");
2514 so_write_offset
[i
] = LLVMBuildAdd(builder
, so_write_offset
[i
], so_offset
, "");
2517 /* Write streamout data. */
2518 for (i
= 0; i
< so
->num_outputs
; i
++) {
2519 unsigned reg
= so
->output
[i
].register_index
;
2524 if (stream
!= so
->output
[i
].stream
)
2527 emit_streamout_output(ctx
, so_buffers
, so_write_offset
,
2528 &so
->output
[i
], &outputs
[reg
]);
2531 lp_build_endif(&if_ctx
);
2534 static void si_export_param(struct si_shader_context
*ctx
, unsigned index
,
2535 LLVMValueRef
*values
)
2537 struct ac_export_args args
;
2539 si_llvm_init_export_args(ctx
, values
,
2540 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
2541 ac_build_export(&ctx
->ac
, &args
);
2544 static void si_build_param_exports(struct si_shader_context
*ctx
,
2545 struct si_shader_output_values
*outputs
,
2548 struct si_shader
*shader
= ctx
->shader
;
2549 unsigned param_count
= 0;
2551 for (unsigned i
= 0; i
< noutput
; i
++) {
2552 unsigned semantic_name
= outputs
[i
].semantic_name
;
2553 unsigned semantic_index
= outputs
[i
].semantic_index
;
2555 if (outputs
[i
].vertex_stream
[0] != 0 &&
2556 outputs
[i
].vertex_stream
[1] != 0 &&
2557 outputs
[i
].vertex_stream
[2] != 0 &&
2558 outputs
[i
].vertex_stream
[3] != 0)
2561 switch (semantic_name
) {
2562 case TGSI_SEMANTIC_LAYER
:
2563 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
2564 case TGSI_SEMANTIC_CLIPDIST
:
2565 case TGSI_SEMANTIC_COLOR
:
2566 case TGSI_SEMANTIC_BCOLOR
:
2567 case TGSI_SEMANTIC_PRIMID
:
2568 case TGSI_SEMANTIC_FOG
:
2569 case TGSI_SEMANTIC_TEXCOORD
:
2570 case TGSI_SEMANTIC_GENERIC
:
2576 if ((semantic_name
!= TGSI_SEMANTIC_GENERIC
||
2577 semantic_index
< SI_MAX_IO_GENERIC
) &&
2578 shader
->key
.opt
.kill_outputs
&
2579 (1ull << si_shader_io_get_unique_index(semantic_name
, semantic_index
)))
2582 si_export_param(ctx
, param_count
, outputs
[i
].values
);
2584 assert(i
< ARRAY_SIZE(shader
->info
.vs_output_param_offset
));
2585 shader
->info
.vs_output_param_offset
[i
] = param_count
++;
2588 shader
->info
.nr_param_exports
= param_count
;
2591 /* Generate export instructions for hardware VS shader stage */
2592 static void si_llvm_export_vs(struct si_shader_context
*ctx
,
2593 struct si_shader_output_values
*outputs
,
2596 struct si_shader
*shader
= ctx
->shader
;
2597 struct ac_export_args pos_args
[4] = {};
2598 LLVMValueRef psize_value
= NULL
, edgeflag_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
2602 /* Build position exports. */
2603 for (i
= 0; i
< noutput
; i
++) {
2604 switch (outputs
[i
].semantic_name
) {
2605 case TGSI_SEMANTIC_POSITION
:
2606 si_llvm_init_export_args(ctx
, outputs
[i
].values
,
2607 V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
2609 case TGSI_SEMANTIC_PSIZE
:
2610 psize_value
= outputs
[i
].values
[0];
2612 case TGSI_SEMANTIC_LAYER
:
2613 layer_value
= outputs
[i
].values
[0];
2615 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
2616 viewport_index_value
= outputs
[i
].values
[0];
2618 case TGSI_SEMANTIC_EDGEFLAG
:
2619 edgeflag_value
= outputs
[i
].values
[0];
2621 case TGSI_SEMANTIC_CLIPDIST
:
2622 if (!shader
->key
.opt
.clip_disable
) {
2623 unsigned index
= 2 + outputs
[i
].semantic_index
;
2624 si_llvm_init_export_args(ctx
, outputs
[i
].values
,
2625 V_008DFC_SQ_EXP_POS
+ index
,
2629 case TGSI_SEMANTIC_CLIPVERTEX
:
2630 if (!shader
->key
.opt
.clip_disable
) {
2631 si_llvm_emit_clipvertex(ctx
, pos_args
,
2638 /* We need to add the position output manually if it's missing. */
2639 if (!pos_args
[0].out
[0]) {
2640 pos_args
[0].enabled_channels
= 0xf; /* writemask */
2641 pos_args
[0].valid_mask
= 0; /* EXEC mask */
2642 pos_args
[0].done
= 0; /* last export? */
2643 pos_args
[0].target
= V_008DFC_SQ_EXP_POS
;
2644 pos_args
[0].compr
= 0; /* COMPR flag */
2645 pos_args
[0].out
[0] = ctx
->ac
.f32_0
; /* X */
2646 pos_args
[0].out
[1] = ctx
->ac
.f32_0
; /* Y */
2647 pos_args
[0].out
[2] = ctx
->ac
.f32_0
; /* Z */
2648 pos_args
[0].out
[3] = ctx
->ac
.f32_1
; /* W */
2651 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2652 if (shader
->selector
->info
.writes_psize
||
2653 shader
->selector
->info
.writes_edgeflag
||
2654 shader
->selector
->info
.writes_viewport_index
||
2655 shader
->selector
->info
.writes_layer
) {
2656 pos_args
[1].enabled_channels
= shader
->selector
->info
.writes_psize
|
2657 (shader
->selector
->info
.writes_edgeflag
<< 1) |
2658 (shader
->selector
->info
.writes_layer
<< 2);
2660 pos_args
[1].valid_mask
= 0; /* EXEC mask */
2661 pos_args
[1].done
= 0; /* last export? */
2662 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
2663 pos_args
[1].compr
= 0; /* COMPR flag */
2664 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
2665 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
2666 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
2667 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
2669 if (shader
->selector
->info
.writes_psize
)
2670 pos_args
[1].out
[0] = psize_value
;
2672 if (shader
->selector
->info
.writes_edgeflag
) {
2673 /* The output is a float, but the hw expects an integer
2674 * with the first bit containing the edge flag. */
2675 edgeflag_value
= LLVMBuildFPToUI(ctx
->ac
.builder
,
2678 edgeflag_value
= ac_build_umin(&ctx
->ac
,
2682 /* The LLVM intrinsic expects a float. */
2683 pos_args
[1].out
[1] = ac_to_float(&ctx
->ac
, edgeflag_value
);
2686 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
2687 /* GFX9 has the layer in out.z[10:0] and the viewport
2688 * index in out.z[19:16].
2690 if (shader
->selector
->info
.writes_layer
)
2691 pos_args
[1].out
[2] = layer_value
;
2693 if (shader
->selector
->info
.writes_viewport_index
) {
2694 LLVMValueRef v
= viewport_index_value
;
2696 v
= ac_to_integer(&ctx
->ac
, v
);
2697 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
2698 LLVMConstInt(ctx
->i32
, 16, 0), "");
2699 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
2700 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
2701 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
2702 pos_args
[1].enabled_channels
|= 1 << 2;
2705 if (shader
->selector
->info
.writes_layer
)
2706 pos_args
[1].out
[2] = layer_value
;
2708 if (shader
->selector
->info
.writes_viewport_index
) {
2709 pos_args
[1].out
[3] = viewport_index_value
;
2710 pos_args
[1].enabled_channels
|= 1 << 3;
2715 for (i
= 0; i
< 4; i
++)
2716 if (pos_args
[i
].out
[0])
2717 shader
->info
.nr_pos_exports
++;
2720 for (i
= 0; i
< 4; i
++) {
2721 if (!pos_args
[i
].out
[0])
2724 /* Specify the target we are exporting */
2725 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
2727 if (pos_idx
== shader
->info
.nr_pos_exports
)
2728 /* Specify that this is the last export */
2729 pos_args
[i
].done
= 1;
2731 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
2734 /* Build parameter exports. */
2735 si_build_param_exports(ctx
, outputs
, noutput
);
2739 * Forward all outputs from the vertex shader to the TES. This is only used
2740 * for the fixed function TCS.
2742 static void si_copy_tcs_inputs(struct lp_build_tgsi_context
*bld_base
)
2744 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2745 LLVMValueRef invocation_id
, buffer
, buffer_offset
;
2746 LLVMValueRef lds_vertex_stride
, lds_vertex_offset
, lds_base
;
2749 invocation_id
= unpack_param(ctx
, ctx
->param_tcs_rel_ids
, 8, 5);
2750 buffer
= desc_from_addr_base64k(ctx
, ctx
->param_tcs_offchip_addr_base64k
);
2751 buffer_offset
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
2753 lds_vertex_stride
= get_tcs_in_vertex_dw_stride(ctx
);
2754 lds_vertex_offset
= LLVMBuildMul(ctx
->ac
.builder
, invocation_id
,
2755 lds_vertex_stride
, "");
2756 lds_base
= get_tcs_in_current_patch_offset(ctx
);
2757 lds_base
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
, lds_vertex_offset
, "");
2759 inputs
= ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
;
2761 unsigned i
= u_bit_scan64(&inputs
);
2763 LLVMValueRef lds_ptr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2764 LLVMConstInt(ctx
->i32
, 4 * i
, 0),
2767 LLVMValueRef buffer_addr
= get_tcs_tes_buffer_address(ctx
,
2768 get_rel_patch_id(ctx
),
2770 LLVMConstInt(ctx
->i32
, i
, 0));
2772 LLVMValueRef value
= lds_load(bld_base
, ctx
->ac
.i32
, ~0,
2775 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 4, buffer_addr
,
2776 buffer_offset
, 0, 1, 0, true, false);
2780 static void si_write_tess_factors(struct lp_build_tgsi_context
*bld_base
,
2781 LLVMValueRef rel_patch_id
,
2782 LLVMValueRef invocation_id
,
2783 LLVMValueRef tcs_out_current_patch_data_offset
,
2784 LLVMValueRef invoc0_tf_outer
[4],
2785 LLVMValueRef invoc0_tf_inner
[2])
2787 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2788 struct si_shader
*shader
= ctx
->shader
;
2789 unsigned tess_inner_index
, tess_outer_index
;
2790 LLVMValueRef lds_base
, lds_inner
, lds_outer
, byteoffset
, buffer
;
2791 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
2792 unsigned stride
, outer_comps
, inner_comps
, i
, offset
;
2793 struct lp_build_if_state if_ctx
, inner_if_ctx
;
2795 /* Add a barrier before loading tess factors from LDS. */
2796 if (!shader
->key
.part
.tcs
.epilog
.invoc0_tess_factors_are_def
)
2797 si_llvm_emit_barrier(NULL
, bld_base
, NULL
);
2799 /* Do this only for invocation 0, because the tess levels are per-patch,
2802 * This can't jump, because invocation 0 executes this. It should
2803 * at least mask out the loads and stores for other invocations.
2805 lp_build_if(&if_ctx
, &ctx
->gallivm
,
2806 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
2807 invocation_id
, ctx
->i32_0
, ""));
2809 /* Determine the layout of one tess factor element in the buffer. */
2810 switch (shader
->key
.part
.tcs
.epilog
.prim_mode
) {
2811 case PIPE_PRIM_LINES
:
2812 stride
= 2; /* 2 dwords, 1 vec2 store */
2816 case PIPE_PRIM_TRIANGLES
:
2817 stride
= 4; /* 4 dwords, 1 vec4 store */
2821 case PIPE_PRIM_QUADS
:
2822 stride
= 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2831 for (i
= 0; i
< 4; i
++) {
2832 inner
[i
] = LLVMGetUndef(ctx
->i32
);
2833 outer
[i
] = LLVMGetUndef(ctx
->i32
);
2836 if (shader
->key
.part
.tcs
.epilog
.invoc0_tess_factors_are_def
) {
2837 /* Tess factors are in VGPRs. */
2838 for (i
= 0; i
< outer_comps
; i
++)
2839 outer
[i
] = out
[i
] = invoc0_tf_outer
[i
];
2840 for (i
= 0; i
< inner_comps
; i
++)
2841 inner
[i
] = out
[outer_comps
+i
] = invoc0_tf_inner
[i
];
2843 /* Load tess_inner and tess_outer from LDS.
2844 * Any invocation can write them, so we can't get them from a temporary.
2846 tess_inner_index
= si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0);
2847 tess_outer_index
= si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0);
2849 lds_base
= tcs_out_current_patch_data_offset
;
2850 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2851 LLVMConstInt(ctx
->i32
,
2852 tess_inner_index
* 4, 0), "");
2853 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2854 LLVMConstInt(ctx
->i32
,
2855 tess_outer_index
* 4, 0), "");
2857 for (i
= 0; i
< outer_comps
; i
++) {
2859 lds_load(bld_base
, ctx
->ac
.i32
, i
, lds_outer
);
2861 for (i
= 0; i
< inner_comps
; i
++) {
2862 inner
[i
] = out
[outer_comps
+i
] =
2863 lds_load(bld_base
, ctx
->ac
.i32
, i
, lds_inner
);
2867 if (shader
->key
.part
.tcs
.epilog
.prim_mode
== PIPE_PRIM_LINES
) {
2868 /* For isolines, the hardware expects tess factors in the
2869 * reverse order from what GLSL / TGSI specify.
2871 LLVMValueRef tmp
= out
[0];
2876 /* Convert the outputs to vectors for stores. */
2877 vec0
= lp_build_gather_values(&ctx
->gallivm
, out
, MIN2(stride
, 4));
2881 vec1
= lp_build_gather_values(&ctx
->gallivm
, out
+4, stride
- 4);
2883 /* Get the buffer. */
2884 buffer
= desc_from_addr_base64k(ctx
, ctx
->param_tcs_factor_addr_base64k
);
2886 /* Get the offset. */
2887 tf_base
= LLVMGetParam(ctx
->main_fn
,
2888 ctx
->param_tcs_factor_offset
);
2889 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
2890 LLVMConstInt(ctx
->i32
, 4 * stride
, 0), "");
2892 lp_build_if(&inner_if_ctx
, &ctx
->gallivm
,
2893 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
2894 rel_patch_id
, ctx
->i32_0
, ""));
2896 /* Store the dynamic HS control word. */
2898 if (ctx
->screen
->info
.chip_class
<= VI
) {
2899 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
2900 LLVMConstInt(ctx
->i32
, 0x80000000, 0),
2901 1, ctx
->i32_0
, tf_base
,
2902 offset
, 1, 0, true, false);
2906 lp_build_endif(&inner_if_ctx
);
2908 /* Store the tessellation factors. */
2909 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
2910 MIN2(stride
, 4), byteoffset
, tf_base
,
2911 offset
, 1, 0, true, false);
2914 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
2915 stride
- 4, byteoffset
, tf_base
,
2916 offset
, 1, 0, true, false);
2918 /* Store the tess factors into the offchip buffer if TES reads them. */
2919 if (shader
->key
.part
.tcs
.epilog
.tes_reads_tess_factors
) {
2920 LLVMValueRef buf
, base
, inner_vec
, outer_vec
, tf_outer_offset
;
2921 LLVMValueRef tf_inner_offset
;
2922 unsigned param_outer
, param_inner
;
2924 buf
= desc_from_addr_base64k(ctx
, ctx
->param_tcs_offchip_addr_base64k
);
2925 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
2927 param_outer
= si_shader_io_get_unique_index_patch(
2928 TGSI_SEMANTIC_TESSOUTER
, 0);
2929 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, rel_patch_id
, NULL
,
2930 LLVMConstInt(ctx
->i32
, param_outer
, 0));
2932 outer_vec
= lp_build_gather_values(&ctx
->gallivm
, outer
,
2933 util_next_power_of_two(outer_comps
));
2935 ac_build_buffer_store_dword(&ctx
->ac
, buf
, outer_vec
,
2936 outer_comps
, tf_outer_offset
,
2937 base
, 0, 1, 0, true, false);
2939 param_inner
= si_shader_io_get_unique_index_patch(
2940 TGSI_SEMANTIC_TESSINNER
, 0);
2941 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, rel_patch_id
, NULL
,
2942 LLVMConstInt(ctx
->i32
, param_inner
, 0));
2944 inner_vec
= inner_comps
== 1 ? inner
[0] :
2945 lp_build_gather_values(&ctx
->gallivm
, inner
, inner_comps
);
2946 ac_build_buffer_store_dword(&ctx
->ac
, buf
, inner_vec
,
2947 inner_comps
, tf_inner_offset
,
2948 base
, 0, 1, 0, true, false);
2952 lp_build_endif(&if_ctx
);
2956 si_insert_input_ret(struct si_shader_context
*ctx
, LLVMValueRef ret
,
2957 unsigned param
, unsigned return_index
)
2959 return LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
2960 LLVMGetParam(ctx
->main_fn
, param
),
2965 si_insert_input_ret_float(struct si_shader_context
*ctx
, LLVMValueRef ret
,
2966 unsigned param
, unsigned return_index
)
2968 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2969 LLVMValueRef p
= LLVMGetParam(ctx
->main_fn
, param
);
2971 return LLVMBuildInsertValue(builder
, ret
,
2972 ac_to_float(&ctx
->ac
, p
),
2977 si_insert_input_ptr_as_2xi32(struct si_shader_context
*ctx
, LLVMValueRef ret
,
2978 unsigned param
, unsigned return_index
)
2980 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2981 LLVMValueRef ptr
, lo
, hi
;
2983 ptr
= LLVMGetParam(ctx
->main_fn
, param
);
2984 ptr
= LLVMBuildPtrToInt(builder
, ptr
, ctx
->i64
, "");
2985 ptr
= LLVMBuildBitCast(builder
, ptr
, ctx
->v2i32
, "");
2986 lo
= LLVMBuildExtractElement(builder
, ptr
, ctx
->i32_0
, "");
2987 hi
= LLVMBuildExtractElement(builder
, ptr
, ctx
->i32_1
, "");
2988 ret
= LLVMBuildInsertValue(builder
, ret
, lo
, return_index
, "");
2989 return LLVMBuildInsertValue(builder
, ret
, hi
, return_index
+ 1, "");
2992 /* This only writes the tessellation factor levels. */
2993 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context
*bld_base
)
2995 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2996 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2997 LLVMValueRef rel_patch_id
, invocation_id
, tf_lds_offset
;
2999 si_copy_tcs_inputs(bld_base
);
3001 rel_patch_id
= get_rel_patch_id(ctx
);
3002 invocation_id
= unpack_param(ctx
, ctx
->param_tcs_rel_ids
, 8, 5);
3003 tf_lds_offset
= get_tcs_out_current_patch_data_offset(ctx
);
3005 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
3006 LLVMBasicBlockRef blocks
[2] = {
3007 LLVMGetInsertBlock(builder
),
3008 ctx
->merged_wrap_if_state
.entry_block
3010 LLVMValueRef values
[2];
3012 lp_build_endif(&ctx
->merged_wrap_if_state
);
3014 values
[0] = rel_patch_id
;
3015 values
[1] = LLVMGetUndef(ctx
->i32
);
3016 rel_patch_id
= ac_build_phi(&ctx
->ac
, ctx
->i32
, 2, values
, blocks
);
3018 values
[0] = tf_lds_offset
;
3019 values
[1] = LLVMGetUndef(ctx
->i32
);
3020 tf_lds_offset
= ac_build_phi(&ctx
->ac
, ctx
->i32
, 2, values
, blocks
);
3022 values
[0] = invocation_id
;
3023 values
[1] = ctx
->i32_1
; /* cause the epilog to skip threads */
3024 invocation_id
= ac_build_phi(&ctx
->ac
, ctx
->i32
, 2, values
, blocks
);
3027 /* Return epilog parameters from this function. */
3028 LLVMValueRef ret
= ctx
->return_value
;
3031 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
3032 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_layout
,
3033 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT
);
3034 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_addr_base64k
,
3035 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K
);
3036 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_factor_addr_base64k
,
3037 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K
);
3038 /* Tess offchip and tess factor offsets are at the beginning. */
3039 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_offset
, 2);
3040 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_factor_offset
, 4);
3041 vgpr
= 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K
+ 1;
3043 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_layout
,
3044 GFX6_SGPR_TCS_OFFCHIP_LAYOUT
);
3045 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_addr_base64k
,
3046 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K
);
3047 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_factor_addr_base64k
,
3048 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K
);
3049 /* Tess offchip and tess factor offsets are after user SGPRs. */
3050 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_offset
,
3051 GFX6_TCS_NUM_USER_SGPR
);
3052 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_factor_offset
,
3053 GFX6_TCS_NUM_USER_SGPR
+ 1);
3054 vgpr
= GFX6_TCS_NUM_USER_SGPR
+ 2;
3058 rel_patch_id
= ac_to_float(&ctx
->ac
, rel_patch_id
);
3059 invocation_id
= ac_to_float(&ctx
->ac
, invocation_id
);
3060 tf_lds_offset
= ac_to_float(&ctx
->ac
, tf_lds_offset
);
3062 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3063 * the invocation_id output does not alias the param_tcs_rel_ids input,
3064 * which saves a V_MOV on gfx9.
3068 ret
= LLVMBuildInsertValue(builder
, ret
, rel_patch_id
, vgpr
++, "");
3069 ret
= LLVMBuildInsertValue(builder
, ret
, invocation_id
, vgpr
++, "");
3071 if (ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
) {
3072 vgpr
++; /* skip the tess factor LDS offset */
3073 for (unsigned i
= 0; i
< 6; i
++) {
3074 LLVMValueRef value
=
3075 LLVMBuildLoad(builder
, ctx
->invoc0_tess_factors
[i
], "");
3076 value
= ac_to_float(&ctx
->ac
, value
);
3077 ret
= LLVMBuildInsertValue(builder
, ret
, value
, vgpr
++, "");
3080 ret
= LLVMBuildInsertValue(builder
, ret
, tf_lds_offset
, vgpr
++, "");
3082 ctx
->return_value
= ret
;
3085 /* Pass TCS inputs from LS to TCS on GFX9. */
3086 static void si_set_ls_return_value_for_tcs(struct si_shader_context
*ctx
)
3088 LLVMValueRef ret
= ctx
->return_value
;
3090 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_offset
, 2);
3091 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_merged_wave_info
, 3);
3092 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_factor_offset
, 4);
3093 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_merged_scratch_offset
, 5);
3095 ret
= si_insert_input_ptr_as_2xi32(ctx
, ret
, ctx
->param_rw_buffers
,
3096 8 + SI_SGPR_RW_BUFFERS
);
3097 ret
= si_insert_input_ptr_as_2xi32(ctx
, ret
,
3098 ctx
->param_bindless_samplers_and_images
,
3099 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
);
3101 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_vs_state_bits
,
3102 8 + SI_SGPR_VS_STATE_BITS
);
3103 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_layout
,
3104 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT
);
3105 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_out_lds_offsets
,
3106 8 + GFX9_SGPR_TCS_OUT_OFFSETS
);
3107 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_out_lds_layout
,
3108 8 + GFX9_SGPR_TCS_OUT_LAYOUT
);
3109 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_addr_base64k
,
3110 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K
);
3111 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_factor_addr_base64k
,
3112 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K
);
3114 unsigned desc_param
= ctx
->param_tcs_factor_addr_base64k
+ 2;
3115 ret
= si_insert_input_ptr_as_2xi32(ctx
, ret
, desc_param
,
3116 8 + GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS
);
3117 ret
= si_insert_input_ptr_as_2xi32(ctx
, ret
, desc_param
+ 1,
3118 8 + GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES
);
3120 unsigned vgpr
= 8 + GFX9_TCS_NUM_USER_SGPR
;
3121 ret
= si_insert_input_ret_float(ctx
, ret
,
3122 ctx
->param_tcs_patch_id
, vgpr
++);
3123 ret
= si_insert_input_ret_float(ctx
, ret
,
3124 ctx
->param_tcs_rel_ids
, vgpr
++);
3125 ctx
->return_value
= ret
;
3128 /* Pass GS inputs from ES to GS on GFX9. */
3129 static void si_set_es_return_value_for_gs(struct si_shader_context
*ctx
)
3131 LLVMValueRef ret
= ctx
->return_value
;
3133 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_gs2vs_offset
, 2);
3134 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_merged_wave_info
, 3);
3135 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_merged_scratch_offset
, 5);
3137 ret
= si_insert_input_ptr_as_2xi32(ctx
, ret
, ctx
->param_rw_buffers
,
3138 8 + SI_SGPR_RW_BUFFERS
);
3139 ret
= si_insert_input_ptr_as_2xi32(ctx
, ret
,
3140 ctx
->param_bindless_samplers_and_images
,
3141 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
);
3143 unsigned desc_param
= ctx
->param_vs_state_bits
+ 1;
3144 ret
= si_insert_input_ptr_as_2xi32(ctx
, ret
, desc_param
,
3145 8 + GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS
);
3146 ret
= si_insert_input_ptr_as_2xi32(ctx
, ret
, desc_param
+ 1,
3147 8 + GFX9_SGPR_GS_SAMPLERS_AND_IMAGES
);
3149 unsigned vgpr
= 8 + GFX9_GS_NUM_USER_SGPR
;
3150 for (unsigned i
= 0; i
< 5; i
++) {
3151 unsigned param
= ctx
->param_gs_vtx01_offset
+ i
;
3152 ret
= si_insert_input_ret_float(ctx
, ret
, param
, vgpr
++);
3154 ctx
->return_value
= ret
;
3157 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi
*abi
,
3158 unsigned max_outputs
,
3159 LLVMValueRef
*addrs
)
3161 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3162 struct si_shader
*shader
= ctx
->shader
;
3163 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
3165 LLVMValueRef vertex_id
= LLVMGetParam(ctx
->main_fn
,
3166 ctx
->param_rel_auto_id
);
3167 LLVMValueRef vertex_dw_stride
= get_tcs_in_vertex_dw_stride(ctx
);
3168 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
3169 vertex_dw_stride
, "");
3171 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3172 * its inputs from it. */
3173 for (i
= 0; i
< info
->num_outputs
; i
++) {
3174 unsigned name
= info
->output_semantic_name
[i
];
3175 unsigned index
= info
->output_semantic_index
[i
];
3177 /* The ARB_shader_viewport_layer_array spec contains the
3180 * 2) What happens if gl_ViewportIndex or gl_Layer is
3181 * written in the vertex shader and a geometry shader is
3184 * RESOLVED: The value written by the last vertex processing
3185 * stage is used. If the last vertex processing stage
3186 * (vertex, tessellation evaluation or geometry) does not
3187 * statically assign to gl_ViewportIndex or gl_Layer, index
3188 * or layer zero is assumed.
3190 * So writes to those outputs in VS-as-LS are simply ignored.
3192 if (name
== TGSI_SEMANTIC_LAYER
||
3193 name
== TGSI_SEMANTIC_VIEWPORT_INDEX
)
3196 int param
= si_shader_io_get_unique_index(name
, index
);
3197 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
3198 LLVMConstInt(ctx
->i32
, param
* 4, 0), "");
3200 for (chan
= 0; chan
< 4; chan
++) {
3201 if (!(info
->output_usagemask
[i
] & (1 << chan
)))
3204 lds_store(ctx
, chan
, dw_addr
,
3205 LLVMBuildLoad(ctx
->ac
.builder
, addrs
[4 * i
+ chan
], ""));
3209 if (ctx
->screen
->info
.chip_class
>= GFX9
)
3210 si_set_ls_return_value_for_tcs(ctx
);
3213 static void si_llvm_emit_es_epilogue(struct ac_shader_abi
*abi
,
3214 unsigned max_outputs
,
3215 LLVMValueRef
*addrs
)
3217 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3218 struct si_shader
*es
= ctx
->shader
;
3219 struct tgsi_shader_info
*info
= &es
->selector
->info
;
3220 LLVMValueRef soffset
= LLVMGetParam(ctx
->main_fn
,
3221 ctx
->param_es2gs_offset
);
3222 LLVMValueRef lds_base
= NULL
;
3226 if (ctx
->screen
->info
.chip_class
>= GFX9
&& info
->num_outputs
) {
3227 unsigned itemsize_dw
= es
->selector
->esgs_itemsize
/ 4;
3228 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
3229 LLVMValueRef wave_idx
= unpack_param(ctx
, ctx
->param_merged_wave_info
, 24, 4);
3230 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
3231 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
3232 LLVMConstInt(ctx
->i32
, 64, false), ""), "");
3233 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
3234 LLVMConstInt(ctx
->i32
, itemsize_dw
, 0), "");
3237 for (i
= 0; i
< info
->num_outputs
; i
++) {
3240 if (info
->output_semantic_name
[i
] == TGSI_SEMANTIC_VIEWPORT_INDEX
||
3241 info
->output_semantic_name
[i
] == TGSI_SEMANTIC_LAYER
)
3244 param
= si_shader_io_get_unique_index(info
->output_semantic_name
[i
],
3245 info
->output_semantic_index
[i
]);
3247 for (chan
= 0; chan
< 4; chan
++) {
3248 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, addrs
[4 * i
+ chan
], "");
3249 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
3251 /* GFX9 has the ESGS ring in LDS. */
3252 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
3253 lds_store(ctx
, param
* 4 + chan
, lds_base
, out_val
);
3257 ac_build_buffer_store_dword(&ctx
->ac
,
3259 out_val
, 1, NULL
, soffset
,
3260 (4 * param
+ chan
) * 4,
3265 if (ctx
->screen
->info
.chip_class
>= GFX9
)
3266 si_set_es_return_value_for_gs(ctx
);
3269 static LLVMValueRef
si_get_gs_wave_id(struct si_shader_context
*ctx
)
3271 if (ctx
->screen
->info
.chip_class
>= GFX9
)
3272 return unpack_param(ctx
, ctx
->param_merged_wave_info
, 16, 8);
3274 return LLVMGetParam(ctx
->main_fn
, ctx
->param_gs_wave_id
);
3277 static void emit_gs_epilogue(struct si_shader_context
*ctx
)
3279 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
,
3280 si_get_gs_wave_id(ctx
));
3282 if (ctx
->screen
->info
.chip_class
>= GFX9
)
3283 lp_build_endif(&ctx
->merged_wrap_if_state
);
3286 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi
*abi
,
3287 unsigned max_outputs
,
3288 LLVMValueRef
*addrs
)
3290 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3291 struct tgsi_shader_info UNUSED
*info
= &ctx
->shader
->selector
->info
;
3293 assert(info
->num_outputs
<= max_outputs
);
3295 emit_gs_epilogue(ctx
);
3298 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context
*bld_base
)
3300 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3301 emit_gs_epilogue(ctx
);
3304 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi
*abi
,
3305 unsigned max_outputs
,
3306 LLVMValueRef
*addrs
)
3308 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3309 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
3310 struct si_shader_output_values
*outputs
= NULL
;
3313 assert(!ctx
->shader
->is_gs_copy_shader
);
3314 assert(info
->num_outputs
<= max_outputs
);
3316 outputs
= MALLOC((info
->num_outputs
+ 1) * sizeof(outputs
[0]));
3318 /* Vertex color clamping.
3320 * This uses a state constant loaded in a user data SGPR and
3321 * an IF statement is added that clamps all colors if the constant
3324 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
3325 struct lp_build_if_state if_ctx
;
3326 LLVMValueRef cond
= NULL
;
3327 LLVMValueRef addr
, val
;
3329 for (i
= 0; i
< info
->num_outputs
; i
++) {
3330 if (info
->output_semantic_name
[i
] != TGSI_SEMANTIC_COLOR
&&
3331 info
->output_semantic_name
[i
] != TGSI_SEMANTIC_BCOLOR
)
3334 /* We've found a color. */
3336 /* The state is in the first bit of the user SGPR. */
3337 cond
= LLVMGetParam(ctx
->main_fn
,
3338 ctx
->param_vs_state_bits
);
3339 cond
= LLVMBuildTrunc(ctx
->ac
.builder
, cond
,
3341 lp_build_if(&if_ctx
, &ctx
->gallivm
, cond
);
3344 for (j
= 0; j
< 4; j
++) {
3345 addr
= addrs
[4 * i
+ j
];
3346 val
= LLVMBuildLoad(ctx
->ac
.builder
, addr
, "");
3347 val
= ac_build_clamp(&ctx
->ac
, val
);
3348 LLVMBuildStore(ctx
->ac
.builder
, val
, addr
);
3353 lp_build_endif(&if_ctx
);
3356 for (i
= 0; i
< info
->num_outputs
; i
++) {
3357 outputs
[i
].semantic_name
= info
->output_semantic_name
[i
];
3358 outputs
[i
].semantic_index
= info
->output_semantic_index
[i
];
3360 for (j
= 0; j
< 4; j
++) {
3361 outputs
[i
].values
[j
] =
3362 LLVMBuildLoad(ctx
->ac
.builder
,
3365 outputs
[i
].vertex_stream
[j
] =
3366 (info
->output_streams
[i
] >> (2 * j
)) & 3;
3370 if (ctx
->shader
->selector
->so
.num_outputs
)
3371 si_llvm_emit_streamout(ctx
, outputs
, i
, 0);
3373 /* Export PrimitiveID. */
3374 if (ctx
->shader
->key
.mono
.u
.vs_export_prim_id
) {
3375 outputs
[i
].semantic_name
= TGSI_SEMANTIC_PRIMID
;
3376 outputs
[i
].semantic_index
= 0;
3377 outputs
[i
].values
[0] = ac_to_float(&ctx
->ac
, get_primitive_id(ctx
, 0));
3378 for (j
= 1; j
< 4; j
++)
3379 outputs
[i
].values
[j
] = LLVMConstReal(ctx
->f32
, 0);
3381 memset(outputs
[i
].vertex_stream
, 0,
3382 sizeof(outputs
[i
].vertex_stream
));
3386 si_llvm_export_vs(ctx
, outputs
, i
);
3390 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context
*bld_base
)
3392 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3394 ctx
->abi
.emit_outputs(&ctx
->abi
, RADEON_LLVM_MAX_OUTPUTS
,
3395 &ctx
->outputs
[0][0]);
3398 struct si_ps_exports
{
3400 struct ac_export_args args
[10];
3403 unsigned si_get_spi_shader_z_format(bool writes_z
, bool writes_stencil
,
3404 bool writes_samplemask
)
3407 /* Z needs 32 bits. */
3408 if (writes_samplemask
)
3409 return V_028710_SPI_SHADER_32_ABGR
;
3410 else if (writes_stencil
)
3411 return V_028710_SPI_SHADER_32_GR
;
3413 return V_028710_SPI_SHADER_32_R
;
3414 } else if (writes_stencil
|| writes_samplemask
) {
3415 /* Both stencil and sample mask need only 16 bits. */
3416 return V_028710_SPI_SHADER_UINT16_ABGR
;
3418 return V_028710_SPI_SHADER_ZERO
;
3422 static void si_export_mrt_z(struct lp_build_tgsi_context
*bld_base
,
3423 LLVMValueRef depth
, LLVMValueRef stencil
,
3424 LLVMValueRef samplemask
, struct si_ps_exports
*exp
)
3426 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3427 struct lp_build_context
*base
= &bld_base
->base
;
3428 struct ac_export_args args
;
3430 unsigned format
= si_get_spi_shader_z_format(depth
!= NULL
,
3432 samplemask
!= NULL
);
3434 assert(depth
|| stencil
|| samplemask
);
3436 args
.valid_mask
= 1; /* whether the EXEC mask is valid */
3437 args
.done
= 1; /* DONE bit */
3439 /* Specify the target we are exporting */
3440 args
.target
= V_008DFC_SQ_EXP_MRTZ
;
3442 args
.compr
= 0; /* COMP flag */
3443 args
.out
[0] = base
->undef
; /* R, depth */
3444 args
.out
[1] = base
->undef
; /* G, stencil test value[0:7], stencil op value[8:15] */
3445 args
.out
[2] = base
->undef
; /* B, sample mask */
3446 args
.out
[3] = base
->undef
; /* A, alpha to mask */
3448 if (format
== V_028710_SPI_SHADER_UINT16_ABGR
) {
3450 args
.compr
= 1; /* COMPR flag */
3453 /* Stencil should be in X[23:16]. */
3454 stencil
= ac_to_integer(&ctx
->ac
, stencil
);
3455 stencil
= LLVMBuildShl(ctx
->ac
.builder
, stencil
,
3456 LLVMConstInt(ctx
->i32
, 16, 0), "");
3457 args
.out
[0] = ac_to_float(&ctx
->ac
, stencil
);
3461 /* SampleMask should be in Y[15:0]. */
3462 args
.out
[1] = samplemask
;
3467 args
.out
[0] = depth
;
3471 args
.out
[1] = stencil
;
3475 args
.out
[2] = samplemask
;
3480 /* SI (except OLAND and HAINAN) has a bug that it only looks
3481 * at the X writemask component. */
3482 if (ctx
->screen
->info
.chip_class
== SI
&&
3483 ctx
->screen
->info
.family
!= CHIP_OLAND
&&
3484 ctx
->screen
->info
.family
!= CHIP_HAINAN
)
3487 /* Specify which components to enable */
3488 args
.enabled_channels
= mask
;
3490 memcpy(&exp
->args
[exp
->num
++], &args
, sizeof(args
));
3493 static void si_export_mrt_color(struct lp_build_tgsi_context
*bld_base
,
3494 LLVMValueRef
*color
, unsigned index
,
3495 unsigned samplemask_param
,
3496 bool is_last
, struct si_ps_exports
*exp
)
3498 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3502 if (ctx
->shader
->key
.part
.ps
.epilog
.clamp_color
)
3503 for (i
= 0; i
< 4; i
++)
3504 color
[i
] = ac_build_clamp(&ctx
->ac
, color
[i
]);
3507 if (ctx
->shader
->key
.part
.ps
.epilog
.alpha_to_one
)
3508 color
[3] = ctx
->ac
.f32_1
;
3512 ctx
->shader
->key
.part
.ps
.epilog
.alpha_func
!= PIPE_FUNC_ALWAYS
)
3513 si_alpha_test(bld_base
, color
[3]);
3515 /* Line & polygon smoothing */
3516 if (ctx
->shader
->key
.part
.ps
.epilog
.poly_line_smoothing
)
3517 color
[3] = si_scale_alpha_by_sample_mask(bld_base
, color
[3],
3520 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3521 if (ctx
->shader
->key
.part
.ps
.epilog
.last_cbuf
> 0) {
3522 struct ac_export_args args
[8];
3525 /* Get the export arguments, also find out what the last one is. */
3526 for (c
= 0; c
<= ctx
->shader
->key
.part
.ps
.epilog
.last_cbuf
; c
++) {
3527 si_llvm_init_export_args(ctx
, color
,
3528 V_008DFC_SQ_EXP_MRT
+ c
, &args
[c
]);
3529 if (args
[c
].enabled_channels
)
3533 /* Emit all exports. */
3534 for (c
= 0; c
<= ctx
->shader
->key
.part
.ps
.epilog
.last_cbuf
; c
++) {
3535 if (is_last
&& last
== c
) {
3536 args
[c
].valid_mask
= 1; /* whether the EXEC mask is valid */
3537 args
[c
].done
= 1; /* DONE bit */
3538 } else if (!args
[c
].enabled_channels
)
3539 continue; /* unnecessary NULL export */
3541 memcpy(&exp
->args
[exp
->num
++], &args
[c
], sizeof(args
[c
]));
3544 struct ac_export_args args
;
3547 si_llvm_init_export_args(ctx
, color
, V_008DFC_SQ_EXP_MRT
+ index
,
3550 args
.valid_mask
= 1; /* whether the EXEC mask is valid */
3551 args
.done
= 1; /* DONE bit */
3552 } else if (!args
.enabled_channels
)
3553 return; /* unnecessary NULL export */
3555 memcpy(&exp
->args
[exp
->num
++], &args
, sizeof(args
));
3559 static void si_emit_ps_exports(struct si_shader_context
*ctx
,
3560 struct si_ps_exports
*exp
)
3562 for (unsigned i
= 0; i
< exp
->num
; i
++)
3563 ac_build_export(&ctx
->ac
, &exp
->args
[i
]);
3566 static void si_export_null(struct lp_build_tgsi_context
*bld_base
)
3568 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3569 struct lp_build_context
*base
= &bld_base
->base
;
3570 struct ac_export_args args
;
3572 args
.enabled_channels
= 0x0; /* enabled channels */
3573 args
.valid_mask
= 1; /* whether the EXEC mask is valid */
3574 args
.done
= 1; /* DONE bit */
3575 args
.target
= V_008DFC_SQ_EXP_NULL
;
3576 args
.compr
= 0; /* COMPR flag (0 = 32-bit export) */
3577 args
.out
[0] = base
->undef
; /* R */
3578 args
.out
[1] = base
->undef
; /* G */
3579 args
.out
[2] = base
->undef
; /* B */
3580 args
.out
[3] = base
->undef
; /* A */
3582 ac_build_export(&ctx
->ac
, &args
);
3586 * Return PS outputs in this order:
3588 * v[0:3] = color0.xyzw
3589 * v[4:7] = color1.xyzw
3594 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3596 * The alpha-ref SGPR is returned via its original location.
3598 static void si_llvm_return_fs_outputs(struct ac_shader_abi
*abi
,
3599 unsigned max_outputs
,
3600 LLVMValueRef
*addrs
)
3602 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3603 struct si_shader
*shader
= ctx
->shader
;
3604 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
3605 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3606 unsigned i
, j
, first_vgpr
, vgpr
;
3608 LLVMValueRef color
[8][4] = {};
3609 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3612 if (ctx
->postponed_kill
)
3613 ac_build_kill_if_false(&ctx
->ac
, LLVMBuildLoad(builder
, ctx
->postponed_kill
, ""));
3615 /* Read the output values. */
3616 for (i
= 0; i
< info
->num_outputs
; i
++) {
3617 unsigned semantic_name
= info
->output_semantic_name
[i
];
3618 unsigned semantic_index
= info
->output_semantic_index
[i
];
3620 switch (semantic_name
) {
3621 case TGSI_SEMANTIC_COLOR
:
3622 assert(semantic_index
< 8);
3623 for (j
= 0; j
< 4; j
++) {
3624 LLVMValueRef ptr
= addrs
[4 * i
+ j
];
3625 LLVMValueRef result
= LLVMBuildLoad(builder
, ptr
, "");
3626 color
[semantic_index
][j
] = result
;
3629 case TGSI_SEMANTIC_POSITION
:
3630 depth
= LLVMBuildLoad(builder
,
3631 addrs
[4 * i
+ 2], "");
3633 case TGSI_SEMANTIC_STENCIL
:
3634 stencil
= LLVMBuildLoad(builder
,
3635 addrs
[4 * i
+ 1], "");
3637 case TGSI_SEMANTIC_SAMPLEMASK
:
3638 samplemask
= LLVMBuildLoad(builder
,
3639 addrs
[4 * i
+ 0], "");
3642 fprintf(stderr
, "Warning: SI unhandled fs output type:%d\n",
3647 /* Fill the return structure. */
3648 ret
= ctx
->return_value
;
3651 ret
= LLVMBuildInsertValue(builder
, ret
,
3652 ac_to_integer(&ctx
->ac
,
3653 LLVMGetParam(ctx
->main_fn
,
3654 SI_PARAM_ALPHA_REF
)),
3655 SI_SGPR_ALPHA_REF
, "");
3658 first_vgpr
= vgpr
= SI_SGPR_ALPHA_REF
+ 1;
3659 for (i
= 0; i
< ARRAY_SIZE(color
); i
++) {
3663 for (j
= 0; j
< 4; j
++)
3664 ret
= LLVMBuildInsertValue(builder
, ret
, color
[i
][j
], vgpr
++, "");
3667 ret
= LLVMBuildInsertValue(builder
, ret
, depth
, vgpr
++, "");
3669 ret
= LLVMBuildInsertValue(builder
, ret
, stencil
, vgpr
++, "");
3671 ret
= LLVMBuildInsertValue(builder
, ret
, samplemask
, vgpr
++, "");
3673 /* Add the input sample mask for smoothing at the end. */
3674 if (vgpr
< first_vgpr
+ PS_EPILOG_SAMPLEMASK_MIN_LOC
)
3675 vgpr
= first_vgpr
+ PS_EPILOG_SAMPLEMASK_MIN_LOC
;
3676 ret
= LLVMBuildInsertValue(builder
, ret
,
3677 LLVMGetParam(ctx
->main_fn
,
3678 SI_PARAM_SAMPLE_COVERAGE
), vgpr
++, "");
3680 ctx
->return_value
= ret
;
3683 void si_emit_waitcnt(struct si_shader_context
*ctx
, unsigned simm16
)
3685 LLVMValueRef args
[1] = {
3686 LLVMConstInt(ctx
->i32
, simm16
, 0)
3688 lp_build_intrinsic(ctx
->ac
.builder
, "llvm.amdgcn.s.waitcnt",
3689 ctx
->voidt
, args
, 1, 0);
3692 static void membar_emit(
3693 const struct lp_build_tgsi_action
*action
,
3694 struct lp_build_tgsi_context
*bld_base
,
3695 struct lp_build_emit_data
*emit_data
)
3697 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3698 LLVMValueRef src0
= lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, 0);
3699 unsigned flags
= LLVMConstIntGetZExtValue(src0
);
3700 unsigned waitcnt
= NOOP_WAITCNT
;
3702 if (flags
& TGSI_MEMBAR_THREAD_GROUP
)
3703 waitcnt
&= VM_CNT
& LGKM_CNT
;
3705 if (flags
& (TGSI_MEMBAR_ATOMIC_BUFFER
|
3706 TGSI_MEMBAR_SHADER_BUFFER
|
3707 TGSI_MEMBAR_SHADER_IMAGE
))
3710 if (flags
& TGSI_MEMBAR_SHARED
)
3711 waitcnt
&= LGKM_CNT
;
3713 if (waitcnt
!= NOOP_WAITCNT
)
3714 si_emit_waitcnt(ctx
, waitcnt
);
3717 static void clock_emit(
3718 const struct lp_build_tgsi_action
*action
,
3719 struct lp_build_tgsi_context
*bld_base
,
3720 struct lp_build_emit_data
*emit_data
)
3722 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3725 tmp
= lp_build_intrinsic(ctx
->ac
.builder
, "llvm.readcyclecounter",
3726 ctx
->i64
, NULL
, 0, 0);
3727 tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, tmp
, ctx
->v2i32
, "");
3729 emit_data
->output
[0] =
3730 LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
, ctx
->i32_0
, "");
3731 emit_data
->output
[1] =
3732 LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
, ctx
->i32_1
, "");
3735 LLVMTypeRef
si_const_array(LLVMTypeRef elem_type
, int num_elements
)
3737 return LLVMPointerType(LLVMArrayType(elem_type
, num_elements
),
3741 static void si_llvm_emit_ddxy(
3742 const struct lp_build_tgsi_action
*action
,
3743 struct lp_build_tgsi_context
*bld_base
,
3744 struct lp_build_emit_data
*emit_data
)
3746 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3747 unsigned opcode
= emit_data
->info
->opcode
;
3752 if (opcode
== TGSI_OPCODE_DDX_FINE
)
3753 mask
= AC_TID_MASK_LEFT
;
3754 else if (opcode
== TGSI_OPCODE_DDY_FINE
)
3755 mask
= AC_TID_MASK_TOP
;
3757 mask
= AC_TID_MASK_TOP_LEFT
;
3759 /* for DDX we want to next X pixel, DDY next Y pixel. */
3760 idx
= (opcode
== TGSI_OPCODE_DDX
|| opcode
== TGSI_OPCODE_DDX_FINE
) ? 1 : 2;
3762 val
= ac_to_integer(&ctx
->ac
, emit_data
->args
[0]);
3763 val
= ac_build_ddxy(&ctx
->ac
, mask
, idx
, val
);
3764 emit_data
->output
[emit_data
->chan
] = val
;
3768 * this takes an I,J coordinate pair,
3769 * and works out the X and Y derivatives.
3770 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3772 static LLVMValueRef
si_llvm_emit_ddxy_interp(
3773 struct lp_build_tgsi_context
*bld_base
,
3774 LLVMValueRef interp_ij
)
3776 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3777 LLVMValueRef result
[4], a
;
3780 for (i
= 0; i
< 2; i
++) {
3781 a
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_ij
,
3782 LLVMConstInt(ctx
->i32
, i
, 0), "");
3783 result
[i
] = lp_build_emit_llvm_unary(bld_base
, TGSI_OPCODE_DDX
, a
);
3784 result
[2+i
] = lp_build_emit_llvm_unary(bld_base
, TGSI_OPCODE_DDY
, a
);
3787 return lp_build_gather_values(&ctx
->gallivm
, result
, 4);
3790 static void interp_fetch_args(
3791 struct lp_build_tgsi_context
*bld_base
,
3792 struct lp_build_emit_data
*emit_data
)
3794 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3795 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3797 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
3798 /* offset is in second src, first two channels */
3799 emit_data
->args
[0] = lp_build_emit_fetch(bld_base
,
3802 emit_data
->args
[1] = lp_build_emit_fetch(bld_base
,
3805 emit_data
->arg_count
= 2;
3806 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
3807 LLVMValueRef sample_position
;
3808 LLVMValueRef sample_id
;
3809 LLVMValueRef halfval
= LLVMConstReal(ctx
->f32
, 0.5f
);
3811 /* fetch sample ID, then fetch its sample position,
3812 * and place into first two channels.
3814 sample_id
= lp_build_emit_fetch(bld_base
,
3815 emit_data
->inst
, 1, TGSI_CHAN_X
);
3816 sample_id
= ac_to_integer(&ctx
->ac
, sample_id
);
3818 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
3819 * Language 4.50 spec says about interpolateAtSample:
3821 * "Returns the value of the input interpolant variable at
3822 * the location of sample number sample. If multisample
3823 * buffers are not available, the input variable will be
3824 * evaluated at the center of the pixel. If sample sample
3825 * does not exist, the position used to interpolate the
3826 * input variable is undefined."
3828 * This means that sample_id values outside of the valid are
3829 * in fact valid input, and the usual mechanism for loading the
3830 * sample position doesn't work.
3832 if (ctx
->shader
->key
.mono
.u
.ps
.interpolate_at_sample_force_center
) {
3833 LLVMValueRef center
[4] = {
3834 LLVMConstReal(ctx
->f32
, 0.5),
3835 LLVMConstReal(ctx
->f32
, 0.5),
3840 sample_position
= lp_build_gather_values(&ctx
->gallivm
, center
, 4);
3842 sample_position
= load_sample_position(ctx
, sample_id
);
3845 emit_data
->args
[0] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3849 emit_data
->args
[0] = LLVMBuildFSub(ctx
->ac
.builder
, emit_data
->args
[0], halfval
, "");
3850 emit_data
->args
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3853 emit_data
->args
[1] = LLVMBuildFSub(ctx
->ac
.builder
, emit_data
->args
[1], halfval
, "");
3854 emit_data
->arg_count
= 2;
3858 static void build_interp_intrinsic(const struct lp_build_tgsi_action
*action
,
3859 struct lp_build_tgsi_context
*bld_base
,
3860 struct lp_build_emit_data
*emit_data
)
3862 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3863 struct si_shader
*shader
= ctx
->shader
;
3864 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
3865 LLVMValueRef interp_param
;
3866 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3867 const struct tgsi_full_src_register
*input
= &inst
->Src
[0];
3868 int input_base
, input_array_size
;
3871 LLVMValueRef prim_mask
= LLVMGetParam(ctx
->main_fn
, SI_PARAM_PRIM_MASK
);
3872 LLVMValueRef array_idx
;
3873 int interp_param_idx
;
3877 assert(input
->Register
.File
== TGSI_FILE_INPUT
);
3879 if (input
->Register
.Indirect
) {
3880 unsigned array_id
= input
->Indirect
.ArrayID
;
3883 input_base
= info
->input_array_first
[array_id
];
3884 input_array_size
= info
->input_array_last
[array_id
] - input_base
+ 1;
3886 input_base
= inst
->Src
[0].Register
.Index
;
3887 input_array_size
= info
->num_inputs
- input_base
;
3890 array_idx
= si_get_indirect_index(ctx
, &input
->Indirect
,
3891 1, input
->Register
.Index
- input_base
);
3893 input_base
= inst
->Src
[0].Register
.Index
;
3894 input_array_size
= 1;
3895 array_idx
= ctx
->i32_0
;
3898 interp
= shader
->selector
->info
.input_interpolate
[input_base
];
3900 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
3901 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
)
3902 location
= TGSI_INTERPOLATE_LOC_CENTER
;
3904 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
3906 interp_param_idx
= lookup_interp_param_index(interp
, location
);
3907 if (interp_param_idx
== -1)
3909 else if (interp_param_idx
)
3910 interp_param
= LLVMGetParam(ctx
->main_fn
, interp_param_idx
);
3912 interp_param
= NULL
;
3914 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
3915 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
3916 LLVMValueRef ij_out
[2];
3917 LLVMValueRef ddxy_out
= si_llvm_emit_ddxy_interp(bld_base
, interp_param
);
3920 * take the I then J parameters, and the DDX/Y for it, and
3921 * calculate the IJ inputs for the interpolator.
3922 * temp1 = ddx * offset/sample.x + I;
3923 * interp_param.I = ddy * offset/sample.y + temp1;
3924 * temp1 = ddx * offset/sample.x + J;
3925 * interp_param.J = ddy * offset/sample.y + temp1;
3927 for (i
= 0; i
< 2; i
++) {
3928 LLVMValueRef ix_ll
= LLVMConstInt(ctx
->i32
, i
, 0);
3929 LLVMValueRef iy_ll
= LLVMConstInt(ctx
->i32
, i
+ 2, 0);
3930 LLVMValueRef ddx_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
3931 ddxy_out
, ix_ll
, "");
3932 LLVMValueRef ddy_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
3933 ddxy_out
, iy_ll
, "");
3934 LLVMValueRef interp_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
3935 interp_param
, ix_ll
, "");
3936 LLVMValueRef temp1
, temp2
;
3938 interp_el
= ac_to_float(&ctx
->ac
, interp_el
);
3940 temp1
= LLVMBuildFMul(ctx
->ac
.builder
, ddx_el
, emit_data
->args
[0], "");
3942 temp1
= LLVMBuildFAdd(ctx
->ac
.builder
, temp1
, interp_el
, "");
3944 temp2
= LLVMBuildFMul(ctx
->ac
.builder
, ddy_el
, emit_data
->args
[1], "");
3946 ij_out
[i
] = LLVMBuildFAdd(ctx
->ac
.builder
, temp2
, temp1
, "");
3948 interp_param
= lp_build_gather_values(&ctx
->gallivm
, ij_out
, 2);
3952 interp_param
= ac_to_float(&ctx
->ac
, interp_param
);
3954 for (chan
= 0; chan
< 4; chan
++) {
3955 LLVMValueRef gather
= LLVMGetUndef(LLVMVectorType(ctx
->f32
, input_array_size
));
3956 unsigned schan
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[0], chan
);
3958 for (unsigned idx
= 0; idx
< input_array_size
; ++idx
) {
3959 LLVMValueRef v
, i
= NULL
, j
= NULL
;
3962 i
= LLVMBuildExtractElement(
3963 ctx
->ac
.builder
, interp_param
, ctx
->i32_0
, "");
3964 j
= LLVMBuildExtractElement(
3965 ctx
->ac
.builder
, interp_param
, ctx
->i32_1
, "");
3967 v
= si_build_fs_interp(ctx
, input_base
+ idx
, schan
,
3970 gather
= LLVMBuildInsertElement(ctx
->ac
.builder
,
3971 gather
, v
, LLVMConstInt(ctx
->i32
, idx
, false), "");
3974 emit_data
->output
[chan
] = LLVMBuildExtractElement(
3975 ctx
->ac
.builder
, gather
, array_idx
, "");
3979 static void vote_all_emit(
3980 const struct lp_build_tgsi_action
*action
,
3981 struct lp_build_tgsi_context
*bld_base
,
3982 struct lp_build_emit_data
*emit_data
)
3984 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3986 LLVMValueRef tmp
= ac_build_vote_all(&ctx
->ac
, emit_data
->args
[0]);
3987 emit_data
->output
[emit_data
->chan
] =
3988 LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->i32
, "");
3991 static void vote_any_emit(
3992 const struct lp_build_tgsi_action
*action
,
3993 struct lp_build_tgsi_context
*bld_base
,
3994 struct lp_build_emit_data
*emit_data
)
3996 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3998 LLVMValueRef tmp
= ac_build_vote_any(&ctx
->ac
, emit_data
->args
[0]);
3999 emit_data
->output
[emit_data
->chan
] =
4000 LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->i32
, "");
4003 static void vote_eq_emit(
4004 const struct lp_build_tgsi_action
*action
,
4005 struct lp_build_tgsi_context
*bld_base
,
4006 struct lp_build_emit_data
*emit_data
)
4008 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4010 LLVMValueRef tmp
= ac_build_vote_eq(&ctx
->ac
, emit_data
->args
[0]);
4011 emit_data
->output
[emit_data
->chan
] =
4012 LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->i32
, "");
4015 static void ballot_emit(
4016 const struct lp_build_tgsi_action
*action
,
4017 struct lp_build_tgsi_context
*bld_base
,
4018 struct lp_build_emit_data
*emit_data
)
4020 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4021 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4024 tmp
= lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_X
);
4025 tmp
= ac_build_ballot(&ctx
->ac
, tmp
);
4026 tmp
= LLVMBuildBitCast(builder
, tmp
, ctx
->v2i32
, "");
4028 emit_data
->output
[0] = LLVMBuildExtractElement(builder
, tmp
, ctx
->i32_0
, "");
4029 emit_data
->output
[1] = LLVMBuildExtractElement(builder
, tmp
, ctx
->i32_1
, "");
4032 static void read_invoc_fetch_args(
4033 struct lp_build_tgsi_context
*bld_base
,
4034 struct lp_build_emit_data
*emit_data
)
4036 emit_data
->args
[0] = lp_build_emit_fetch(bld_base
, emit_data
->inst
,
4037 0, emit_data
->src_chan
);
4039 /* Always read the source invocation (= lane) from the X channel. */
4040 emit_data
->args
[1] = lp_build_emit_fetch(bld_base
, emit_data
->inst
,
4042 emit_data
->arg_count
= 2;
4045 static void read_lane_emit(
4046 const struct lp_build_tgsi_action
*action
,
4047 struct lp_build_tgsi_context
*bld_base
,
4048 struct lp_build_emit_data
*emit_data
)
4050 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4052 /* We currently have no other way to prevent LLVM from lifting the icmp
4053 * calls to a dominating basic block.
4055 ac_build_optimization_barrier(&ctx
->ac
, &emit_data
->args
[0]);
4057 for (unsigned i
= 0; i
< emit_data
->arg_count
; ++i
)
4058 emit_data
->args
[i
] = ac_to_integer(&ctx
->ac
, emit_data
->args
[i
]);
4060 emit_data
->output
[emit_data
->chan
] =
4061 ac_build_intrinsic(&ctx
->ac
, action
->intr_name
,
4062 ctx
->i32
, emit_data
->args
, emit_data
->arg_count
,
4063 AC_FUNC_ATTR_READNONE
|
4064 AC_FUNC_ATTR_CONVERGENT
);
4067 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context
*bld_base
,
4068 struct lp_build_emit_data
*emit_data
)
4070 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4071 struct tgsi_src_register src0
= emit_data
->inst
->Src
[0].Register
;
4075 assert(src0
.File
== TGSI_FILE_IMMEDIATE
);
4077 imm
= ctx
->imms
[src0
.Index
* TGSI_NUM_CHANNELS
+ src0
.SwizzleX
];
4078 stream
= LLVMConstIntGetZExtValue(imm
) & 0x3;
4082 /* Emit one vertex from the geometry shader */
4083 static void si_llvm_emit_vertex(struct ac_shader_abi
*abi
,
4085 LLVMValueRef
*addrs
)
4087 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
4088 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
4089 struct lp_build_context
*uint
= &ctx
->bld_base
.uint_bld
;
4090 struct si_shader
*shader
= ctx
->shader
;
4091 struct lp_build_if_state if_state
;
4092 LLVMValueRef soffset
= LLVMGetParam(ctx
->main_fn
,
4093 ctx
->param_gs2vs_offset
);
4094 LLVMValueRef gs_next_vertex
;
4095 LLVMValueRef can_emit
;
4096 unsigned chan
, offset
;
4099 /* Write vertex attribute values to GSVS ring */
4100 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
4101 ctx
->gs_next_vertex
[stream
],
4104 /* If this thread has already emitted the declared maximum number of
4105 * vertices, skip the write: excessive vertex emissions are not
4106 * supposed to have any effect.
4108 * If the shader has no writes to memory, kill it instead. This skips
4109 * further memory loads and may allow LLVM to skip to the end
4112 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
4113 LLVMConstInt(ctx
->i32
,
4114 shader
->selector
->gs_max_out_vertices
, 0), "");
4116 bool use_kill
= !info
->writes_memory
;
4118 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
4120 lp_build_if(&if_state
, &ctx
->gallivm
, can_emit
);
4124 for (i
= 0; i
< info
->num_outputs
; i
++) {
4125 for (chan
= 0; chan
< 4; chan
++) {
4126 if (!(info
->output_usagemask
[i
] & (1 << chan
)) ||
4127 ((info
->output_streams
[i
] >> (2 * chan
)) & 3) != stream
)
4130 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, addrs
[4 * i
+ chan
], "");
4131 LLVMValueRef voffset
=
4132 LLVMConstInt(ctx
->i32
, offset
*
4133 shader
->selector
->gs_max_out_vertices
, 0);
4136 voffset
= lp_build_add(uint
, voffset
, gs_next_vertex
);
4137 voffset
= lp_build_mul_imm(uint
, voffset
, 4);
4139 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
4141 ac_build_buffer_store_dword(&ctx
->ac
,
4142 ctx
->gsvs_ring
[stream
],
4144 voffset
, soffset
, 0,
4149 gs_next_vertex
= lp_build_add(uint
, gs_next_vertex
,
4152 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
4154 /* Signal vertex emission */
4155 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
4156 si_get_gs_wave_id(ctx
));
4158 lp_build_endif(&if_state
);
4161 /* Emit one vertex from the geometry shader */
4162 static void si_tgsi_emit_vertex(
4163 const struct lp_build_tgsi_action
*action
,
4164 struct lp_build_tgsi_context
*bld_base
,
4165 struct lp_build_emit_data
*emit_data
)
4167 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4168 unsigned stream
= si_llvm_get_stream(bld_base
, emit_data
);
4170 si_llvm_emit_vertex(&ctx
->abi
, stream
, ctx
->outputs
[0]);
4173 /* Cut one primitive from the geometry shader */
4174 static void si_llvm_emit_primitive(
4175 const struct lp_build_tgsi_action
*action
,
4176 struct lp_build_tgsi_context
*bld_base
,
4177 struct lp_build_emit_data
*emit_data
)
4179 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4182 /* Signal primitive cut */
4183 stream
= si_llvm_get_stream(bld_base
, emit_data
);
4184 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8),
4185 si_get_gs_wave_id(ctx
));
4188 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action
*action
,
4189 struct lp_build_tgsi_context
*bld_base
,
4190 struct lp_build_emit_data
*emit_data
)
4192 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4194 /* SI only (thanks to a hw bug workaround):
4195 * The real barrier instruction isn’t needed, because an entire patch
4196 * always fits into a single wave.
4198 if (ctx
->screen
->info
.chip_class
== SI
&&
4199 ctx
->type
== PIPE_SHADER_TESS_CTRL
) {
4200 si_emit_waitcnt(ctx
, LGKM_CNT
& VM_CNT
);
4204 lp_build_intrinsic(ctx
->ac
.builder
,
4205 "llvm.amdgcn.s.barrier",
4206 ctx
->voidt
, NULL
, 0, LP_FUNC_ATTR_CONVERGENT
);
4209 static const struct lp_build_tgsi_action interp_action
= {
4210 .fetch_args
= interp_fetch_args
,
4211 .emit
= build_interp_intrinsic
,
4214 static void si_create_function(struct si_shader_context
*ctx
,
4216 LLVMTypeRef
*returns
, unsigned num_returns
,
4217 struct si_function_info
*fninfo
,
4218 unsigned max_workgroup_size
)
4222 si_llvm_create_func(ctx
, name
, returns
, num_returns
,
4223 fninfo
->types
, fninfo
->num_params
);
4224 ctx
->return_value
= LLVMGetUndef(ctx
->return_type
);
4226 for (i
= 0; i
< fninfo
->num_sgpr_params
; ++i
) {
4227 LLVMValueRef P
= LLVMGetParam(ctx
->main_fn
, i
);
4229 /* The combination of:
4233 * allows the optimization passes to move loads and reduces
4234 * SGPR spilling significantly.
4236 if (LLVMGetTypeKind(LLVMTypeOf(P
)) == LLVMPointerTypeKind
) {
4237 lp_add_function_attr(ctx
->main_fn
, i
+ 1, LP_FUNC_ATTR_BYVAL
);
4238 lp_add_function_attr(ctx
->main_fn
, i
+ 1, LP_FUNC_ATTR_NOALIAS
);
4239 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
4241 lp_add_function_attr(ctx
->main_fn
, i
+ 1, LP_FUNC_ATTR_INREG
);
4244 for (i
= 0; i
< fninfo
->num_params
; ++i
) {
4245 if (fninfo
->assign
[i
])
4246 *fninfo
->assign
[i
] = LLVMGetParam(ctx
->main_fn
, i
);
4249 if (max_workgroup_size
) {
4250 si_llvm_add_attribute(ctx
->main_fn
, "amdgpu-max-work-group-size",
4251 max_workgroup_size
);
4253 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4254 "no-signed-zeros-fp-math",
4257 if (ctx
->screen
->debug_flags
& DBG(UNSAFE_MATH
)) {
4258 /* These were copied from some LLVM test. */
4259 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4260 "less-precise-fpmad",
4262 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4265 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4268 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4274 static void declare_streamout_params(struct si_shader_context
*ctx
,
4275 struct pipe_stream_output_info
*so
,
4276 struct si_function_info
*fninfo
)
4280 /* Streamout SGPRs. */
4281 if (so
->num_outputs
) {
4282 if (ctx
->type
!= PIPE_SHADER_TESS_EVAL
)
4283 ctx
->param_streamout_config
= add_arg(fninfo
, ARG_SGPR
, ctx
->ac
.i32
);
4285 ctx
->param_streamout_config
= fninfo
->num_params
- 1;
4287 ctx
->param_streamout_write_index
= add_arg(fninfo
, ARG_SGPR
, ctx
->ac
.i32
);
4289 /* A streamout buffer offset is loaded if the stride is non-zero. */
4290 for (i
= 0; i
< 4; i
++) {
4294 ctx
->param_streamout_offset
[i
] = add_arg(fninfo
, ARG_SGPR
, ctx
->ac
.i32
);
4298 static unsigned si_get_max_workgroup_size(const struct si_shader
*shader
)
4300 switch (shader
->selector
->type
) {
4301 case PIPE_SHADER_TESS_CTRL
:
4302 /* Return this so that LLVM doesn't remove s_barrier
4303 * instructions on chips where we use s_barrier. */
4304 return shader
->selector
->screen
->info
.chip_class
>= CIK
? 128 : 64;
4306 case PIPE_SHADER_GEOMETRY
:
4307 return shader
->selector
->screen
->info
.chip_class
>= GFX9
? 128 : 64;
4309 case PIPE_SHADER_COMPUTE
:
4310 break; /* see below */
4316 const unsigned *properties
= shader
->selector
->info
.properties
;
4317 unsigned max_work_group_size
=
4318 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] *
4319 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
] *
4320 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
];
4322 if (!max_work_group_size
) {
4323 /* This is a variable group size compute shader,
4324 * compile it for the maximum possible group size.
4326 max_work_group_size
= SI_MAX_VARIABLE_THREADS_PER_BLOCK
;
4328 return max_work_group_size
;
4331 static void declare_per_stage_desc_pointers(struct si_shader_context
*ctx
,
4332 struct si_function_info
*fninfo
,
4335 LLVMTypeRef const_shader_buf_type
;
4337 if (ctx
->shader
->selector
->info
.const_buffers_declared
== 1 &&
4338 ctx
->shader
->selector
->info
.shader_buffers_declared
== 0)
4339 const_shader_buf_type
= ctx
->f32
;
4341 const_shader_buf_type
= ctx
->v4i32
;
4343 unsigned const_and_shader_buffers
=
4344 add_arg(fninfo
, ARG_SGPR
,
4345 si_const_array(const_shader_buf_type
, 0));
4347 unsigned samplers_and_images
=
4348 add_arg(fninfo
, ARG_SGPR
,
4349 si_const_array(ctx
->v8i32
,
4350 SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2));
4352 if (assign_params
) {
4353 ctx
->param_const_and_shader_buffers
= const_and_shader_buffers
;
4354 ctx
->param_samplers_and_images
= samplers_and_images
;
4358 static void declare_global_desc_pointers(struct si_shader_context
*ctx
,
4359 struct si_function_info
*fninfo
)
4361 ctx
->param_rw_buffers
= add_arg(fninfo
, ARG_SGPR
,
4362 si_const_array(ctx
->v4i32
, SI_NUM_RW_BUFFERS
));
4363 ctx
->param_bindless_samplers_and_images
= add_arg(fninfo
, ARG_SGPR
,
4364 si_const_array(ctx
->v8i32
, 0));
4367 static void declare_vs_specific_input_sgprs(struct si_shader_context
*ctx
,
4368 struct si_function_info
*fninfo
)
4370 ctx
->param_vertex_buffers
= add_arg(fninfo
, ARG_SGPR
,
4371 si_const_array(ctx
->v4i32
, SI_NUM_VERTEX_BUFFERS
));
4372 add_arg_assign(fninfo
, ARG_SGPR
, ctx
->i32
, &ctx
->abi
.base_vertex
);
4373 add_arg_assign(fninfo
, ARG_SGPR
, ctx
->i32
, &ctx
->abi
.start_instance
);
4374 add_arg_assign(fninfo
, ARG_SGPR
, ctx
->i32
, &ctx
->abi
.draw_id
);
4375 ctx
->param_vs_state_bits
= add_arg(fninfo
, ARG_SGPR
, ctx
->i32
);
4378 static void declare_vs_input_vgprs(struct si_shader_context
*ctx
,
4379 struct si_function_info
*fninfo
,
4380 unsigned *num_prolog_vgprs
)
4382 struct si_shader
*shader
= ctx
->shader
;
4384 add_arg_assign(fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.vertex_id
);
4385 if (shader
->key
.as_ls
) {
4386 ctx
->param_rel_auto_id
= add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4387 add_arg_assign(fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.instance_id
);
4389 add_arg_assign(fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.instance_id
);
4390 ctx
->param_vs_prim_id
= add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4392 add_arg(fninfo
, ARG_VGPR
, ctx
->i32
); /* unused */
4394 if (!shader
->is_gs_copy_shader
) {
4395 /* Vertex load indices. */
4396 ctx
->param_vertex_index0
= fninfo
->num_params
;
4397 for (unsigned i
= 0; i
< shader
->selector
->info
.num_inputs
; i
++)
4398 add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4399 *num_prolog_vgprs
+= shader
->selector
->info
.num_inputs
;
4403 static void declare_tes_input_vgprs(struct si_shader_context
*ctx
,
4404 struct si_function_info
*fninfo
)
4406 ctx
->param_tes_u
= add_arg(fninfo
, ARG_VGPR
, ctx
->f32
);
4407 ctx
->param_tes_v
= add_arg(fninfo
, ARG_VGPR
, ctx
->f32
);
4408 ctx
->param_tes_rel_patch_id
= add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4409 ctx
->param_tes_patch_id
= add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4413 /* Convenient merged shader definitions. */
4414 SI_SHADER_MERGED_VERTEX_TESSCTRL
= PIPE_SHADER_TYPES
,
4415 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY
,
4418 static void create_function(struct si_shader_context
*ctx
)
4420 struct si_shader
*shader
= ctx
->shader
;
4421 struct si_function_info fninfo
;
4422 LLVMTypeRef returns
[16+32*4];
4423 unsigned i
, num_return_sgprs
;
4424 unsigned num_returns
= 0;
4425 unsigned num_prolog_vgprs
= 0;
4426 unsigned type
= ctx
->type
;
4427 unsigned vs_blit_property
=
4428 shader
->selector
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
4430 si_init_function_info(&fninfo
);
4432 /* Set MERGED shaders. */
4433 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
4434 if (shader
->key
.as_ls
|| type
== PIPE_SHADER_TESS_CTRL
)
4435 type
= SI_SHADER_MERGED_VERTEX_TESSCTRL
; /* LS or HS */
4436 else if (shader
->key
.as_es
|| type
== PIPE_SHADER_GEOMETRY
)
4437 type
= SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY
;
4440 LLVMTypeRef v3i32
= LLVMVectorType(ctx
->i32
, 3);
4443 case PIPE_SHADER_VERTEX
:
4444 declare_global_desc_pointers(ctx
, &fninfo
);
4446 if (vs_blit_property
) {
4447 ctx
->param_vs_blit_inputs
= fninfo
.num_params
;
4448 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* i16 x1, y1 */
4449 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* i16 x2, y2 */
4450 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* depth */
4452 if (vs_blit_property
== SI_VS_BLIT_SGPRS_POS_COLOR
) {
4453 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* color0 */
4454 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* color1 */
4455 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* color2 */
4456 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* color3 */
4457 } else if (vs_blit_property
== SI_VS_BLIT_SGPRS_POS_TEXCOORD
) {
4458 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.x1 */
4459 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.y1 */
4460 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.x2 */
4461 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.y2 */
4462 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.z */
4463 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.w */
4467 declare_vs_input_vgprs(ctx
, &fninfo
, &num_prolog_vgprs
);
4471 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4472 declare_vs_specific_input_sgprs(ctx
, &fninfo
);
4474 if (shader
->key
.as_es
) {
4475 ctx
->param_es2gs_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4476 } else if (shader
->key
.as_ls
) {
4477 /* no extra parameters */
4479 if (shader
->is_gs_copy_shader
) {
4480 fninfo
.num_params
= ctx
->param_rw_buffers
+ 1;
4481 fninfo
.num_sgpr_params
= fninfo
.num_params
;
4484 /* The locations of the other parameters are assigned dynamically. */
4485 declare_streamout_params(ctx
, &shader
->selector
->so
,
4490 declare_vs_input_vgprs(ctx
, &fninfo
, &num_prolog_vgprs
);
4493 case PIPE_SHADER_TESS_CTRL
: /* SI-CI-VI */
4494 declare_global_desc_pointers(ctx
, &fninfo
);
4495 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4496 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4497 ctx
->param_tcs_out_lds_offsets
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4498 ctx
->param_tcs_out_lds_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4499 ctx
->param_vs_state_bits
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4500 ctx
->param_tcs_offchip_addr_base64k
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4501 ctx
->param_tcs_factor_addr_base64k
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4502 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4503 ctx
->param_tcs_factor_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4506 ctx
->param_tcs_patch_id
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4507 ctx
->param_tcs_rel_ids
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4509 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4510 * placed after the user SGPRs.
4512 for (i
= 0; i
< GFX6_TCS_NUM_USER_SGPR
+ 2; i
++)
4513 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
4514 for (i
= 0; i
< 11; i
++)
4515 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
4518 case SI_SHADER_MERGED_VERTEX_TESSCTRL
:
4519 /* Merged stages have 8 system SGPRs at the beginning. */
4520 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* SPI_SHADER_USER_DATA_ADDR_LO_HS */
4521 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* SPI_SHADER_USER_DATA_ADDR_HI_HS */
4522 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4523 ctx
->param_merged_wave_info
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4524 ctx
->param_tcs_factor_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4525 ctx
->param_merged_scratch_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4526 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4527 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4529 declare_global_desc_pointers(ctx
, &fninfo
);
4530 declare_per_stage_desc_pointers(ctx
, &fninfo
,
4531 ctx
->type
== PIPE_SHADER_VERTEX
);
4532 declare_vs_specific_input_sgprs(ctx
, &fninfo
);
4534 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4535 ctx
->param_tcs_out_lds_offsets
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4536 ctx
->param_tcs_out_lds_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4537 ctx
->param_tcs_offchip_addr_base64k
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4538 ctx
->param_tcs_factor_addr_base64k
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4539 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4541 declare_per_stage_desc_pointers(ctx
, &fninfo
,
4542 ctx
->type
== PIPE_SHADER_TESS_CTRL
);
4544 /* VGPRs (first TCS, then VS) */
4545 ctx
->param_tcs_patch_id
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4546 ctx
->param_tcs_rel_ids
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4548 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
4549 declare_vs_input_vgprs(ctx
, &fninfo
,
4552 /* LS return values are inputs to the TCS main shader part. */
4553 for (i
= 0; i
< 8 + GFX9_TCS_NUM_USER_SGPR
; i
++)
4554 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
4555 for (i
= 0; i
< 2; i
++)
4556 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
4558 /* TCS return values are inputs to the TCS epilog.
4560 * param_tcs_offchip_offset, param_tcs_factor_offset,
4561 * param_tcs_offchip_layout, and param_rw_buffers
4562 * should be passed to the epilog.
4564 for (i
= 0; i
<= 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K
; i
++)
4565 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
4566 for (i
= 0; i
< 11; i
++)
4567 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
4571 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY
:
4572 /* Merged stages have 8 system SGPRs at the beginning. */
4573 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused (SPI_SHADER_USER_DATA_ADDR_LO_GS) */
4574 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused (SPI_SHADER_USER_DATA_ADDR_HI_GS) */
4575 ctx
->param_gs2vs_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4576 ctx
->param_merged_wave_info
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4577 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4578 ctx
->param_merged_scratch_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4579 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4580 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4582 declare_global_desc_pointers(ctx
, &fninfo
);
4583 declare_per_stage_desc_pointers(ctx
, &fninfo
,
4584 (ctx
->type
== PIPE_SHADER_VERTEX
||
4585 ctx
->type
== PIPE_SHADER_TESS_EVAL
));
4586 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
4587 declare_vs_specific_input_sgprs(ctx
, &fninfo
);
4589 /* TESS_EVAL (and also GEOMETRY):
4590 * Declare as many input SGPRs as the VS has. */
4591 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4592 ctx
->param_tcs_offchip_addr_base64k
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4593 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4594 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4595 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4596 ctx
->param_vs_state_bits
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4599 declare_per_stage_desc_pointers(ctx
, &fninfo
,
4600 ctx
->type
== PIPE_SHADER_GEOMETRY
);
4602 /* VGPRs (first GS, then VS/TES) */
4603 ctx
->param_gs_vtx01_offset
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4604 ctx
->param_gs_vtx23_offset
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4605 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.gs_prim_id
);
4606 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.gs_invocation_id
);
4607 ctx
->param_gs_vtx45_offset
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4609 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
4610 declare_vs_input_vgprs(ctx
, &fninfo
,
4612 } else if (ctx
->type
== PIPE_SHADER_TESS_EVAL
) {
4613 declare_tes_input_vgprs(ctx
, &fninfo
);
4616 if (ctx
->type
== PIPE_SHADER_VERTEX
||
4617 ctx
->type
== PIPE_SHADER_TESS_EVAL
) {
4618 /* ES return values are inputs to GS. */
4619 for (i
= 0; i
< 8 + GFX9_GS_NUM_USER_SGPR
; i
++)
4620 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
4621 for (i
= 0; i
< 5; i
++)
4622 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
4626 case PIPE_SHADER_TESS_EVAL
:
4627 declare_global_desc_pointers(ctx
, &fninfo
);
4628 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4629 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4630 ctx
->param_tcs_offchip_addr_base64k
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4632 if (shader
->key
.as_es
) {
4633 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4634 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4635 ctx
->param_es2gs_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4637 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4638 declare_streamout_params(ctx
, &shader
->selector
->so
,
4640 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4644 declare_tes_input_vgprs(ctx
, &fninfo
);
4647 case PIPE_SHADER_GEOMETRY
:
4648 declare_global_desc_pointers(ctx
, &fninfo
);
4649 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4650 ctx
->param_gs2vs_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4651 ctx
->param_gs_wave_id
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4654 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[0]);
4655 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[1]);
4656 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.gs_prim_id
);
4657 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[2]);
4658 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[3]);
4659 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[4]);
4660 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[5]);
4661 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.gs_invocation_id
);
4664 case PIPE_SHADER_FRAGMENT
:
4665 declare_global_desc_pointers(ctx
, &fninfo
);
4666 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4667 add_arg_checked(&fninfo
, ARG_SGPR
, ctx
->f32
, SI_PARAM_ALPHA_REF
);
4668 add_arg_checked(&fninfo
, ARG_SGPR
, ctx
->i32
, SI_PARAM_PRIM_MASK
);
4670 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_PERSP_SAMPLE
);
4671 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_PERSP_CENTER
);
4672 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_PERSP_CENTROID
);
4673 add_arg_checked(&fninfo
, ARG_VGPR
, v3i32
, SI_PARAM_PERSP_PULL_MODEL
);
4674 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_LINEAR_SAMPLE
);
4675 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_LINEAR_CENTER
);
4676 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_LINEAR_CENTROID
);
4677 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->f32
, SI_PARAM_LINE_STIPPLE_TEX
);
4678 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4679 &ctx
->abi
.frag_pos
[0], SI_PARAM_POS_X_FLOAT
);
4680 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4681 &ctx
->abi
.frag_pos
[1], SI_PARAM_POS_Y_FLOAT
);
4682 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4683 &ctx
->abi
.frag_pos
[2], SI_PARAM_POS_Z_FLOAT
);
4684 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4685 &ctx
->abi
.frag_pos
[3], SI_PARAM_POS_W_FLOAT
);
4686 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->i32
,
4687 &ctx
->abi
.front_face
, SI_PARAM_FRONT_FACE
);
4688 shader
->info
.face_vgpr_index
= 20;
4689 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->i32
,
4690 &ctx
->abi
.ancillary
, SI_PARAM_ANCILLARY
);
4691 shader
->info
.ancillary_vgpr_index
= 21;
4692 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4693 &ctx
->abi
.sample_coverage
, SI_PARAM_SAMPLE_COVERAGE
);
4694 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->i32
, SI_PARAM_POS_FIXED_PT
);
4696 /* Color inputs from the prolog. */
4697 if (shader
->selector
->info
.colors_read
) {
4698 unsigned num_color_elements
=
4699 util_bitcount(shader
->selector
->info
.colors_read
);
4701 assert(fninfo
.num_params
+ num_color_elements
<= ARRAY_SIZE(fninfo
.types
));
4702 for (i
= 0; i
< num_color_elements
; i
++)
4703 add_arg(&fninfo
, ARG_VGPR
, ctx
->f32
);
4705 num_prolog_vgprs
+= num_color_elements
;
4708 /* Outputs for the epilog. */
4709 num_return_sgprs
= SI_SGPR_ALPHA_REF
+ 1;
4712 util_bitcount(shader
->selector
->info
.colors_written
) * 4 +
4713 shader
->selector
->info
.writes_z
+
4714 shader
->selector
->info
.writes_stencil
+
4715 shader
->selector
->info
.writes_samplemask
+
4716 1 /* SampleMaskIn */;
4718 num_returns
= MAX2(num_returns
,
4720 PS_EPILOG_SAMPLEMASK_MIN_LOC
+ 1);
4722 for (i
= 0; i
< num_return_sgprs
; i
++)
4723 returns
[i
] = ctx
->i32
;
4724 for (; i
< num_returns
; i
++)
4725 returns
[i
] = ctx
->f32
;
4728 case PIPE_SHADER_COMPUTE
:
4729 declare_global_desc_pointers(ctx
, &fninfo
);
4730 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4731 if (shader
->selector
->info
.uses_grid_size
)
4732 ctx
->param_grid_size
= add_arg(&fninfo
, ARG_SGPR
, v3i32
);
4733 if (shader
->selector
->info
.uses_block_size
)
4734 ctx
->param_block_size
= add_arg(&fninfo
, ARG_SGPR
, v3i32
);
4736 for (i
= 0; i
< 3; i
++) {
4737 ctx
->param_block_id
[i
] = -1;
4738 if (shader
->selector
->info
.uses_block_id
[i
])
4739 ctx
->param_block_id
[i
] = add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4742 ctx
->param_thread_id
= add_arg(&fninfo
, ARG_VGPR
, v3i32
);
4745 assert(0 && "unimplemented shader");
4749 si_create_function(ctx
, "main", returns
, num_returns
, &fninfo
,
4750 si_get_max_workgroup_size(shader
));
4752 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4753 if (ctx
->type
== PIPE_SHADER_FRAGMENT
&&
4754 ctx
->separate_prolog
) {
4755 si_llvm_add_attribute(ctx
->main_fn
,
4756 "InitialPSInputAddr",
4757 S_0286D0_PERSP_SAMPLE_ENA(1) |
4758 S_0286D0_PERSP_CENTER_ENA(1) |
4759 S_0286D0_PERSP_CENTROID_ENA(1) |
4760 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4761 S_0286D0_LINEAR_CENTER_ENA(1) |
4762 S_0286D0_LINEAR_CENTROID_ENA(1) |
4763 S_0286D0_FRONT_FACE_ENA(1) |
4764 S_0286D0_ANCILLARY_ENA(1) |
4765 S_0286D0_POS_FIXED_PT_ENA(1));
4768 shader
->info
.num_input_sgprs
= 0;
4769 shader
->info
.num_input_vgprs
= 0;
4771 for (i
= 0; i
< fninfo
.num_sgpr_params
; ++i
)
4772 shader
->info
.num_input_sgprs
+= ac_get_type_size(fninfo
.types
[i
]) / 4;
4774 for (; i
< fninfo
.num_params
; ++i
)
4775 shader
->info
.num_input_vgprs
+= ac_get_type_size(fninfo
.types
[i
]) / 4;
4777 assert(shader
->info
.num_input_vgprs
>= num_prolog_vgprs
);
4778 shader
->info
.num_input_vgprs
-= num_prolog_vgprs
;
4780 if (shader
->key
.as_ls
||
4781 ctx
->type
== PIPE_SHADER_TESS_CTRL
||
4782 /* GFX9 has the ESGS ring buffer in LDS. */
4783 type
== SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY
)
4784 ac_declare_lds_as_pointer(&ctx
->ac
);
4788 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4791 static void preload_ring_buffers(struct si_shader_context
*ctx
)
4793 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4795 LLVMValueRef buf_ptr
= LLVMGetParam(ctx
->main_fn
,
4796 ctx
->param_rw_buffers
);
4798 if (ctx
->screen
->info
.chip_class
<= VI
&&
4799 (ctx
->shader
->key
.as_es
|| ctx
->type
== PIPE_SHADER_GEOMETRY
)) {
4801 ctx
->type
== PIPE_SHADER_GEOMETRY
? SI_GS_RING_ESGS
4803 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
, ring
, 0);
4806 ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
, offset
);
4809 if (ctx
->shader
->is_gs_copy_shader
) {
4810 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
, SI_RING_GSVS
, 0);
4813 ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
, offset
);
4814 } else if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
4815 const struct si_shader_selector
*sel
= ctx
->shader
->selector
;
4816 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
, SI_RING_GSVS
, 0);
4817 LLVMValueRef base_ring
;
4819 base_ring
= ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
, offset
);
4821 /* The conceptual layout of the GSVS ring is
4822 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4823 * but the real memory layout is swizzled across
4825 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4827 * Override the buffer descriptor accordingly.
4829 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->i64
, 2);
4830 uint64_t stream_offset
= 0;
4832 for (unsigned stream
= 0; stream
< 4; ++stream
) {
4833 unsigned num_components
;
4835 unsigned num_records
;
4836 LLVMValueRef ring
, tmp
;
4838 num_components
= sel
->info
.num_stream_output_components
[stream
];
4839 if (!num_components
)
4842 stride
= 4 * num_components
* sel
->gs_max_out_vertices
;
4844 /* Limit on the stride field for <= CIK. */
4845 assert(stride
< (1 << 14));
4849 ring
= LLVMBuildBitCast(builder
, base_ring
, v2i64
, "");
4850 tmp
= LLVMBuildExtractElement(builder
, ring
, ctx
->i32_0
, "");
4851 tmp
= LLVMBuildAdd(builder
, tmp
,
4852 LLVMConstInt(ctx
->i64
,
4853 stream_offset
, 0), "");
4854 stream_offset
+= stride
* 64;
4856 ring
= LLVMBuildInsertElement(builder
, ring
, tmp
, ctx
->i32_0
, "");
4857 ring
= LLVMBuildBitCast(builder
, ring
, ctx
->v4i32
, "");
4858 tmp
= LLVMBuildExtractElement(builder
, ring
, ctx
->i32_1
, "");
4859 tmp
= LLVMBuildOr(builder
, tmp
,
4860 LLVMConstInt(ctx
->i32
,
4861 S_008F04_STRIDE(stride
) |
4862 S_008F04_SWIZZLE_ENABLE(1), 0), "");
4863 ring
= LLVMBuildInsertElement(builder
, ring
, tmp
, ctx
->i32_1
, "");
4864 ring
= LLVMBuildInsertElement(builder
, ring
,
4865 LLVMConstInt(ctx
->i32
, num_records
, 0),
4866 LLVMConstInt(ctx
->i32
, 2, 0), "");
4867 ring
= LLVMBuildInsertElement(builder
, ring
,
4868 LLVMConstInt(ctx
->i32
,
4869 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4870 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4871 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4872 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
4873 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4874 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
4875 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
4876 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
4877 S_008F0C_ADD_TID_ENABLE(1),
4879 LLVMConstInt(ctx
->i32
, 3, 0), "");
4881 ctx
->gsvs_ring
[stream
] = ring
;
4886 static void si_llvm_emit_polygon_stipple(struct si_shader_context
*ctx
,
4887 LLVMValueRef param_rw_buffers
,
4888 unsigned param_pos_fixed_pt
)
4890 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4891 LLVMValueRef slot
, desc
, offset
, row
, bit
, address
[2];
4893 /* Use the fixed-point gl_FragCoord input.
4894 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
4895 * per coordinate to get the repeating effect.
4897 address
[0] = unpack_param(ctx
, param_pos_fixed_pt
, 0, 5);
4898 address
[1] = unpack_param(ctx
, param_pos_fixed_pt
, 16, 5);
4900 /* Load the buffer descriptor. */
4901 slot
= LLVMConstInt(ctx
->i32
, SI_PS_CONST_POLY_STIPPLE
, 0);
4902 desc
= ac_build_load_to_sgpr(&ctx
->ac
, param_rw_buffers
, slot
);
4904 /* The stipple pattern is 32x32, each row has 32 bits. */
4905 offset
= LLVMBuildMul(builder
, address
[1],
4906 LLVMConstInt(ctx
->i32
, 4, 0), "");
4907 row
= buffer_load_const(ctx
, desc
, offset
);
4908 row
= ac_to_integer(&ctx
->ac
, row
);
4909 bit
= LLVMBuildLShr(builder
, row
, address
[0], "");
4910 bit
= LLVMBuildTrunc(builder
, bit
, ctx
->i1
, "");
4911 ac_build_kill_if_false(&ctx
->ac
, bit
);
4914 void si_shader_binary_read_config(struct ac_shader_binary
*binary
,
4915 struct si_shader_config
*conf
,
4916 unsigned symbol_offset
)
4919 const unsigned char *config
=
4920 ac_shader_binary_config_start(binary
, symbol_offset
);
4921 bool really_needs_scratch
= false;
4923 /* LLVM adds SGPR spills to the scratch size.
4924 * Find out if we really need the scratch buffer.
4926 for (i
= 0; i
< binary
->reloc_count
; i
++) {
4927 const struct ac_shader_reloc
*reloc
= &binary
->relocs
[i
];
4929 if (!strcmp(scratch_rsrc_dword0_symbol
, reloc
->name
) ||
4930 !strcmp(scratch_rsrc_dword1_symbol
, reloc
->name
)) {
4931 really_needs_scratch
= true;
4936 /* XXX: We may be able to emit some of these values directly rather than
4937 * extracting fields to be emitted later.
4940 for (i
= 0; i
< binary
->config_size_per_symbol
; i
+= 8) {
4941 unsigned reg
= util_le32_to_cpu(*(uint32_t*)(config
+ i
));
4942 unsigned value
= util_le32_to_cpu(*(uint32_t*)(config
+ i
+ 4));
4944 case R_00B028_SPI_SHADER_PGM_RSRC1_PS
:
4945 case R_00B128_SPI_SHADER_PGM_RSRC1_VS
:
4946 case R_00B228_SPI_SHADER_PGM_RSRC1_GS
:
4947 case R_00B428_SPI_SHADER_PGM_RSRC1_HS
:
4948 case R_00B848_COMPUTE_PGM_RSRC1
:
4949 conf
->num_sgprs
= MAX2(conf
->num_sgprs
, (G_00B028_SGPRS(value
) + 1) * 8);
4950 conf
->num_vgprs
= MAX2(conf
->num_vgprs
, (G_00B028_VGPRS(value
) + 1) * 4);
4951 conf
->float_mode
= G_00B028_FLOAT_MODE(value
);
4952 conf
->rsrc1
= value
;
4954 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS
:
4955 conf
->lds_size
= MAX2(conf
->lds_size
, G_00B02C_EXTRA_LDS_SIZE(value
));
4957 case R_00B84C_COMPUTE_PGM_RSRC2
:
4958 conf
->lds_size
= MAX2(conf
->lds_size
, G_00B84C_LDS_SIZE(value
));
4959 conf
->rsrc2
= value
;
4961 case R_0286CC_SPI_PS_INPUT_ENA
:
4962 conf
->spi_ps_input_ena
= value
;
4964 case R_0286D0_SPI_PS_INPUT_ADDR
:
4965 conf
->spi_ps_input_addr
= value
;
4967 case R_0286E8_SPI_TMPRING_SIZE
:
4968 case R_00B860_COMPUTE_TMPRING_SIZE
:
4969 /* WAVESIZE is in units of 256 dwords. */
4970 if (really_needs_scratch
)
4971 conf
->scratch_bytes_per_wave
=
4972 G_00B860_WAVESIZE(value
) * 256 * 4;
4974 case 0x4: /* SPILLED_SGPRS */
4975 conf
->spilled_sgprs
= value
;
4977 case 0x8: /* SPILLED_VGPRS */
4978 conf
->spilled_vgprs
= value
;
4982 static bool printed
;
4985 fprintf(stderr
, "Warning: LLVM emitted unknown "
4986 "config register: 0x%x\n", reg
);
4994 if (!conf
->spi_ps_input_addr
)
4995 conf
->spi_ps_input_addr
= conf
->spi_ps_input_ena
;
4998 void si_shader_apply_scratch_relocs(struct si_shader
*shader
,
4999 uint64_t scratch_va
)
5002 uint32_t scratch_rsrc_dword0
= scratch_va
;
5003 uint32_t scratch_rsrc_dword1
=
5004 S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32);
5006 /* Enable scratch coalescing. */
5007 scratch_rsrc_dword1
|= S_008F04_SWIZZLE_ENABLE(1);
5009 for (i
= 0 ; i
< shader
->binary
.reloc_count
; i
++) {
5010 const struct ac_shader_reloc
*reloc
=
5011 &shader
->binary
.relocs
[i
];
5012 if (!strcmp(scratch_rsrc_dword0_symbol
, reloc
->name
)) {
5013 util_memcpy_cpu_to_le32(shader
->binary
.code
+ reloc
->offset
,
5014 &scratch_rsrc_dword0
, 4);
5015 } else if (!strcmp(scratch_rsrc_dword1_symbol
, reloc
->name
)) {
5016 util_memcpy_cpu_to_le32(shader
->binary
.code
+ reloc
->offset
,
5017 &scratch_rsrc_dword1
, 4);
5022 static unsigned si_get_shader_binary_size(const struct si_shader
*shader
)
5024 unsigned size
= shader
->binary
.code_size
;
5027 size
+= shader
->prolog
->binary
.code_size
;
5028 if (shader
->previous_stage
)
5029 size
+= shader
->previous_stage
->binary
.code_size
;
5030 if (shader
->prolog2
)
5031 size
+= shader
->prolog2
->binary
.code_size
;
5033 size
+= shader
->epilog
->binary
.code_size
;
5037 int si_shader_binary_upload(struct si_screen
*sscreen
, struct si_shader
*shader
)
5039 const struct ac_shader_binary
*prolog
=
5040 shader
->prolog
? &shader
->prolog
->binary
: NULL
;
5041 const struct ac_shader_binary
*previous_stage
=
5042 shader
->previous_stage
? &shader
->previous_stage
->binary
: NULL
;
5043 const struct ac_shader_binary
*prolog2
=
5044 shader
->prolog2
? &shader
->prolog2
->binary
: NULL
;
5045 const struct ac_shader_binary
*epilog
=
5046 shader
->epilog
? &shader
->epilog
->binary
: NULL
;
5047 const struct ac_shader_binary
*mainb
= &shader
->binary
;
5048 unsigned bo_size
= si_get_shader_binary_size(shader
) +
5049 (!epilog
? mainb
->rodata_size
: 0);
5052 assert(!prolog
|| !prolog
->rodata_size
);
5053 assert(!previous_stage
|| !previous_stage
->rodata_size
);
5054 assert(!prolog2
|| !prolog2
->rodata_size
);
5055 assert((!prolog
&& !previous_stage
&& !prolog2
&& !epilog
) ||
5056 !mainb
->rodata_size
);
5057 assert(!epilog
|| !epilog
->rodata_size
);
5059 r600_resource_reference(&shader
->bo
, NULL
);
5060 shader
->bo
= (struct r600_resource
*)
5061 pipe_buffer_create(&sscreen
->b
, 0,
5062 PIPE_USAGE_IMMUTABLE
,
5063 align(bo_size
, SI_CPDMA_ALIGNMENT
));
5068 ptr
= sscreen
->ws
->buffer_map(shader
->bo
->buf
, NULL
,
5069 PIPE_TRANSFER_READ_WRITE
|
5070 PIPE_TRANSFER_UNSYNCHRONIZED
);
5072 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5073 * endian-independent. */
5075 memcpy(ptr
, prolog
->code
, prolog
->code_size
);
5076 ptr
+= prolog
->code_size
;
5078 if (previous_stage
) {
5079 memcpy(ptr
, previous_stage
->code
, previous_stage
->code_size
);
5080 ptr
+= previous_stage
->code_size
;
5083 memcpy(ptr
, prolog2
->code
, prolog2
->code_size
);
5084 ptr
+= prolog2
->code_size
;
5087 memcpy(ptr
, mainb
->code
, mainb
->code_size
);
5088 ptr
+= mainb
->code_size
;
5091 memcpy(ptr
, epilog
->code
, epilog
->code_size
);
5092 else if (mainb
->rodata_size
> 0)
5093 memcpy(ptr
, mainb
->rodata
, mainb
->rodata_size
);
5095 sscreen
->ws
->buffer_unmap(shader
->bo
->buf
);
5099 static void si_shader_dump_disassembly(const struct ac_shader_binary
*binary
,
5100 struct pipe_debug_callback
*debug
,
5101 const char *name
, FILE *file
)
5106 if (binary
->disasm_string
) {
5107 fprintf(file
, "Shader %s disassembly:\n", name
);
5108 fprintf(file
, "%s", binary
->disasm_string
);
5110 if (debug
&& debug
->debug_message
) {
5111 /* Very long debug messages are cut off, so send the
5112 * disassembly one line at a time. This causes more
5113 * overhead, but on the plus side it simplifies
5114 * parsing of resulting logs.
5116 pipe_debug_message(debug
, SHADER_INFO
,
5117 "Shader Disassembly Begin");
5119 line
= binary
->disasm_string
;
5121 p
= util_strchrnul(line
, '\n');
5125 pipe_debug_message(debug
, SHADER_INFO
,
5126 "%.*s", count
, line
);
5134 pipe_debug_message(debug
, SHADER_INFO
,
5135 "Shader Disassembly End");
5138 fprintf(file
, "Shader %s binary:\n", name
);
5139 for (i
= 0; i
< binary
->code_size
; i
+= 4) {
5140 fprintf(file
, "@0x%x: %02x%02x%02x%02x\n", i
,
5141 binary
->code
[i
+ 3], binary
->code
[i
+ 2],
5142 binary
->code
[i
+ 1], binary
->code
[i
]);
5147 static void si_shader_dump_stats(struct si_screen
*sscreen
,
5148 const struct si_shader
*shader
,
5149 struct pipe_debug_callback
*debug
,
5152 bool check_debug_option
)
5154 const struct si_shader_config
*conf
= &shader
->config
;
5155 unsigned num_inputs
= shader
->selector
? shader
->selector
->info
.num_inputs
: 0;
5156 unsigned code_size
= si_get_shader_binary_size(shader
);
5157 unsigned lds_increment
= sscreen
->info
.chip_class
>= CIK
? 512 : 256;
5158 unsigned lds_per_wave
= 0;
5159 unsigned max_simd_waves
;
5161 switch (sscreen
->info
.family
) {
5162 /* These always have 8 waves: */
5163 case CHIP_POLARIS10
:
5164 case CHIP_POLARIS11
:
5165 case CHIP_POLARIS12
:
5169 max_simd_waves
= 10;
5172 /* Compute LDS usage for PS. */
5173 switch (processor
) {
5174 case PIPE_SHADER_FRAGMENT
:
5175 /* The minimum usage per wave is (num_inputs * 48). The maximum
5176 * usage is (num_inputs * 48 * 16).
5177 * We can get anything in between and it varies between waves.
5179 * The 48 bytes per input for a single primitive is equal to
5180 * 4 bytes/component * 4 components/input * 3 points.
5182 * Other stages don't know the size at compile time or don't
5183 * allocate LDS per wave, but instead they do it per thread group.
5185 lds_per_wave
= conf
->lds_size
* lds_increment
+
5186 align(num_inputs
* 48, lds_increment
);
5188 case PIPE_SHADER_COMPUTE
:
5189 if (shader
->selector
) {
5190 unsigned max_workgroup_size
=
5191 si_get_max_workgroup_size(shader
);
5192 lds_per_wave
= (conf
->lds_size
* lds_increment
) /
5193 DIV_ROUND_UP(max_workgroup_size
, 64);
5198 /* Compute the per-SIMD wave counts. */
5199 if (conf
->num_sgprs
) {
5200 if (sscreen
->info
.chip_class
>= VI
)
5201 max_simd_waves
= MIN2(max_simd_waves
, 800 / conf
->num_sgprs
);
5203 max_simd_waves
= MIN2(max_simd_waves
, 512 / conf
->num_sgprs
);
5206 if (conf
->num_vgprs
)
5207 max_simd_waves
= MIN2(max_simd_waves
, 256 / conf
->num_vgprs
);
5209 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5210 * 16KB makes some SIMDs unoccupied). */
5212 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
5214 if (!check_debug_option
||
5215 si_can_dump_shader(sscreen
, processor
)) {
5216 if (processor
== PIPE_SHADER_FRAGMENT
) {
5217 fprintf(file
, "*** SHADER CONFIG ***\n"
5218 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5219 "SPI_PS_INPUT_ENA = 0x%04x\n",
5220 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
5223 fprintf(file
, "*** SHADER STATS ***\n"
5226 "Spilled SGPRs: %d\n"
5227 "Spilled VGPRs: %d\n"
5228 "Private memory VGPRs: %d\n"
5229 "Code Size: %d bytes\n"
5231 "Scratch: %d bytes per wave\n"
5233 "********************\n\n\n",
5234 conf
->num_sgprs
, conf
->num_vgprs
,
5235 conf
->spilled_sgprs
, conf
->spilled_vgprs
,
5236 conf
->private_mem_vgprs
, code_size
,
5237 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
5241 pipe_debug_message(debug
, SHADER_INFO
,
5242 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5243 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5244 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5245 conf
->num_sgprs
, conf
->num_vgprs
, code_size
,
5246 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
5247 max_simd_waves
, conf
->spilled_sgprs
,
5248 conf
->spilled_vgprs
, conf
->private_mem_vgprs
);
5251 const char *si_get_shader_name(const struct si_shader
*shader
, unsigned processor
)
5253 switch (processor
) {
5254 case PIPE_SHADER_VERTEX
:
5255 if (shader
->key
.as_es
)
5256 return "Vertex Shader as ES";
5257 else if (shader
->key
.as_ls
)
5258 return "Vertex Shader as LS";
5260 return "Vertex Shader as VS";
5261 case PIPE_SHADER_TESS_CTRL
:
5262 return "Tessellation Control Shader";
5263 case PIPE_SHADER_TESS_EVAL
:
5264 if (shader
->key
.as_es
)
5265 return "Tessellation Evaluation Shader as ES";
5267 return "Tessellation Evaluation Shader as VS";
5268 case PIPE_SHADER_GEOMETRY
:
5269 if (shader
->is_gs_copy_shader
)
5270 return "GS Copy Shader as VS";
5272 return "Geometry Shader";
5273 case PIPE_SHADER_FRAGMENT
:
5274 return "Pixel Shader";
5275 case PIPE_SHADER_COMPUTE
:
5276 return "Compute Shader";
5278 return "Unknown Shader";
5282 void si_shader_dump(struct si_screen
*sscreen
, const struct si_shader
*shader
,
5283 struct pipe_debug_callback
*debug
, unsigned processor
,
5284 FILE *file
, bool check_debug_option
)
5286 if (!check_debug_option
||
5287 si_can_dump_shader(sscreen
, processor
))
5288 si_dump_shader_key(processor
, shader
, file
);
5290 if (!check_debug_option
&& shader
->binary
.llvm_ir_string
) {
5291 if (shader
->previous_stage
&&
5292 shader
->previous_stage
->binary
.llvm_ir_string
) {
5293 fprintf(file
, "\n%s - previous stage - LLVM IR:\n\n",
5294 si_get_shader_name(shader
, processor
));
5295 fprintf(file
, "%s\n", shader
->previous_stage
->binary
.llvm_ir_string
);
5298 fprintf(file
, "\n%s - main shader part - LLVM IR:\n\n",
5299 si_get_shader_name(shader
, processor
));
5300 fprintf(file
, "%s\n", shader
->binary
.llvm_ir_string
);
5303 if (!check_debug_option
||
5304 (si_can_dump_shader(sscreen
, processor
) &&
5305 !(sscreen
->debug_flags
& DBG(NO_ASM
)))) {
5306 fprintf(file
, "\n%s:\n", si_get_shader_name(shader
, processor
));
5309 si_shader_dump_disassembly(&shader
->prolog
->binary
,
5310 debug
, "prolog", file
);
5311 if (shader
->previous_stage
)
5312 si_shader_dump_disassembly(&shader
->previous_stage
->binary
,
5313 debug
, "previous stage", file
);
5314 if (shader
->prolog2
)
5315 si_shader_dump_disassembly(&shader
->prolog2
->binary
,
5316 debug
, "prolog2", file
);
5318 si_shader_dump_disassembly(&shader
->binary
, debug
, "main", file
);
5321 si_shader_dump_disassembly(&shader
->epilog
->binary
,
5322 debug
, "epilog", file
);
5323 fprintf(file
, "\n");
5326 si_shader_dump_stats(sscreen
, shader
, debug
, processor
, file
,
5327 check_debug_option
);
5330 static int si_compile_llvm(struct si_screen
*sscreen
,
5331 struct ac_shader_binary
*binary
,
5332 struct si_shader_config
*conf
,
5333 LLVMTargetMachineRef tm
,
5335 struct pipe_debug_callback
*debug
,
5340 unsigned count
= p_atomic_inc_return(&sscreen
->num_compilations
);
5342 if (si_can_dump_shader(sscreen
, processor
)) {
5343 fprintf(stderr
, "radeonsi: Compiling shader %d\n", count
);
5345 if (!(sscreen
->debug_flags
& (DBG(NO_IR
) | DBG(PREOPT_IR
)))) {
5346 fprintf(stderr
, "%s LLVM IR:\n\n", name
);
5347 ac_dump_module(mod
);
5348 fprintf(stderr
, "\n");
5352 if (sscreen
->record_llvm_ir
) {
5353 char *ir
= LLVMPrintModuleToString(mod
);
5354 binary
->llvm_ir_string
= strdup(ir
);
5355 LLVMDisposeMessage(ir
);
5358 if (!si_replace_shader(count
, binary
)) {
5359 r
= si_llvm_compile(mod
, binary
, tm
, debug
);
5364 si_shader_binary_read_config(binary
, conf
, 0);
5366 /* Enable 64-bit and 16-bit denormals, because there is no performance
5369 * If denormals are enabled, all floating-point output modifiers are
5372 * Don't enable denormals for 32-bit floats, because:
5373 * - Floating-point output modifiers would be ignored by the hw.
5374 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5375 * have to stop using those.
5376 * - SI & CI would be very slow.
5378 conf
->float_mode
|= V_00B028_FP_64_DENORMS
;
5380 FREE(binary
->config
);
5381 FREE(binary
->global_symbol_offsets
);
5382 binary
->config
= NULL
;
5383 binary
->global_symbol_offsets
= NULL
;
5385 /* Some shaders can't have rodata because their binaries can be
5388 if (binary
->rodata_size
&&
5389 (processor
== PIPE_SHADER_VERTEX
||
5390 processor
== PIPE_SHADER_TESS_CTRL
||
5391 processor
== PIPE_SHADER_TESS_EVAL
||
5392 processor
== PIPE_SHADER_FRAGMENT
)) {
5393 fprintf(stderr
, "radeonsi: The shader can't have rodata.");
5400 static void si_llvm_build_ret(struct si_shader_context
*ctx
, LLVMValueRef ret
)
5402 if (LLVMGetTypeKind(LLVMTypeOf(ret
)) == LLVMVoidTypeKind
)
5403 LLVMBuildRetVoid(ctx
->ac
.builder
);
5405 LLVMBuildRet(ctx
->ac
.builder
, ret
);
5408 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5410 si_generate_gs_copy_shader(struct si_screen
*sscreen
,
5411 LLVMTargetMachineRef tm
,
5412 struct si_shader_selector
*gs_selector
,
5413 struct pipe_debug_callback
*debug
)
5415 struct si_shader_context ctx
;
5416 struct si_shader
*shader
;
5417 LLVMBuilderRef builder
;
5418 struct lp_build_tgsi_context
*bld_base
= &ctx
.bld_base
;
5419 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
5420 struct si_shader_output_values
*outputs
;
5421 struct tgsi_shader_info
*gsinfo
= &gs_selector
->info
;
5424 outputs
= MALLOC(gsinfo
->num_outputs
* sizeof(outputs
[0]));
5429 shader
= CALLOC_STRUCT(si_shader
);
5435 /* We can leave the fence as permanently signaled because the GS copy
5436 * shader only becomes visible globally after it has been compiled. */
5437 util_queue_fence_init(&shader
->ready
);
5439 shader
->selector
= gs_selector
;
5440 shader
->is_gs_copy_shader
= true;
5442 si_init_shader_ctx(&ctx
, sscreen
, tm
);
5443 ctx
.shader
= shader
;
5444 ctx
.type
= PIPE_SHADER_VERTEX
;
5446 builder
= ctx
.ac
.builder
;
5448 create_function(&ctx
);
5449 preload_ring_buffers(&ctx
);
5451 LLVMValueRef voffset
=
5452 lp_build_mul_imm(uint
, ctx
.abi
.vertex_id
, 4);
5454 /* Fetch the vertex stream ID.*/
5455 LLVMValueRef stream_id
;
5457 if (gs_selector
->so
.num_outputs
)
5458 stream_id
= unpack_param(&ctx
, ctx
.param_streamout_config
, 24, 2);
5460 stream_id
= ctx
.i32_0
;
5462 /* Fill in output information. */
5463 for (i
= 0; i
< gsinfo
->num_outputs
; ++i
) {
5464 outputs
[i
].semantic_name
= gsinfo
->output_semantic_name
[i
];
5465 outputs
[i
].semantic_index
= gsinfo
->output_semantic_index
[i
];
5467 for (int chan
= 0; chan
< 4; chan
++) {
5468 outputs
[i
].vertex_stream
[chan
] =
5469 (gsinfo
->output_streams
[i
] >> (2 * chan
)) & 3;
5473 LLVMBasicBlockRef end_bb
;
5474 LLVMValueRef switch_inst
;
5476 end_bb
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, ctx
.main_fn
, "end");
5477 switch_inst
= LLVMBuildSwitch(builder
, stream_id
, end_bb
, 4);
5479 for (int stream
= 0; stream
< 4; stream
++) {
5480 LLVMBasicBlockRef bb
;
5483 if (!gsinfo
->num_stream_output_components
[stream
])
5486 if (stream
> 0 && !gs_selector
->so
.num_outputs
)
5489 bb
= LLVMInsertBasicBlockInContext(ctx
.ac
.context
, end_bb
, "out");
5490 LLVMAddCase(switch_inst
, LLVMConstInt(ctx
.i32
, stream
, 0), bb
);
5491 LLVMPositionBuilderAtEnd(builder
, bb
);
5493 /* Fetch vertex data from GSVS ring */
5495 for (i
= 0; i
< gsinfo
->num_outputs
; ++i
) {
5496 for (unsigned chan
= 0; chan
< 4; chan
++) {
5497 if (!(gsinfo
->output_usagemask
[i
] & (1 << chan
)) ||
5498 outputs
[i
].vertex_stream
[chan
] != stream
) {
5499 outputs
[i
].values
[chan
] = ctx
.bld_base
.base
.undef
;
5503 LLVMValueRef soffset
= LLVMConstInt(ctx
.i32
,
5504 offset
* gs_selector
->gs_max_out_vertices
* 16 * 4, 0);
5507 outputs
[i
].values
[chan
] =
5508 ac_build_buffer_load(&ctx
.ac
,
5509 ctx
.gsvs_ring
[0], 1,
5516 /* Streamout and exports. */
5517 if (gs_selector
->so
.num_outputs
) {
5518 si_llvm_emit_streamout(&ctx
, outputs
,
5519 gsinfo
->num_outputs
,
5524 si_llvm_export_vs(&ctx
, outputs
, gsinfo
->num_outputs
);
5526 LLVMBuildBr(builder
, end_bb
);
5529 LLVMPositionBuilderAtEnd(builder
, end_bb
);
5531 LLVMBuildRetVoid(ctx
.ac
.builder
);
5533 ctx
.type
= PIPE_SHADER_GEOMETRY
; /* override for shader dumping */
5534 si_llvm_optimize_module(&ctx
);
5536 r
= si_compile_llvm(sscreen
, &ctx
.shader
->binary
,
5537 &ctx
.shader
->config
, ctx
.tm
,
5539 debug
, PIPE_SHADER_GEOMETRY
,
5542 if (si_can_dump_shader(sscreen
, PIPE_SHADER_GEOMETRY
))
5543 fprintf(stderr
, "GS Copy Shader:\n");
5544 si_shader_dump(sscreen
, ctx
.shader
, debug
,
5545 PIPE_SHADER_GEOMETRY
, stderr
, true);
5546 r
= si_shader_binary_upload(sscreen
, ctx
.shader
);
5549 si_llvm_dispose(&ctx
);
5560 static void si_dump_shader_key_vs(const struct si_shader_key
*key
,
5561 const struct si_vs_prolog_bits
*prolog
,
5562 const char *prefix
, FILE *f
)
5564 fprintf(f
, " %s.instance_divisor_is_one = %u\n",
5565 prefix
, prolog
->instance_divisor_is_one
);
5566 fprintf(f
, " %s.instance_divisor_is_fetched = %u\n",
5567 prefix
, prolog
->instance_divisor_is_fetched
);
5568 fprintf(f
, " %s.ls_vgpr_fix = %u\n",
5569 prefix
, prolog
->ls_vgpr_fix
);
5571 fprintf(f
, " mono.vs.fix_fetch = {");
5572 for (int i
= 0; i
< SI_MAX_ATTRIBS
; i
++)
5573 fprintf(f
, !i
? "%u" : ", %u", key
->mono
.vs_fix_fetch
[i
]);
5577 static void si_dump_shader_key(unsigned processor
, const struct si_shader
*shader
,
5580 const struct si_shader_key
*key
= &shader
->key
;
5582 fprintf(f
, "SHADER KEY\n");
5584 switch (processor
) {
5585 case PIPE_SHADER_VERTEX
:
5586 si_dump_shader_key_vs(key
, &key
->part
.vs
.prolog
,
5587 "part.vs.prolog", f
);
5588 fprintf(f
, " as_es = %u\n", key
->as_es
);
5589 fprintf(f
, " as_ls = %u\n", key
->as_ls
);
5590 fprintf(f
, " mono.u.vs_export_prim_id = %u\n",
5591 key
->mono
.u
.vs_export_prim_id
);
5594 case PIPE_SHADER_TESS_CTRL
:
5595 if (shader
->selector
->screen
->info
.chip_class
>= GFX9
) {
5596 si_dump_shader_key_vs(key
, &key
->part
.tcs
.ls_prolog
,
5597 "part.tcs.ls_prolog", f
);
5599 fprintf(f
, " part.tcs.epilog.prim_mode = %u\n", key
->part
.tcs
.epilog
.prim_mode
);
5600 fprintf(f
, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64
"\n", key
->mono
.u
.ff_tcs_inputs_to_copy
);
5603 case PIPE_SHADER_TESS_EVAL
:
5604 fprintf(f
, " as_es = %u\n", key
->as_es
);
5605 fprintf(f
, " mono.u.vs_export_prim_id = %u\n",
5606 key
->mono
.u
.vs_export_prim_id
);
5609 case PIPE_SHADER_GEOMETRY
:
5610 if (shader
->is_gs_copy_shader
)
5613 if (shader
->selector
->screen
->info
.chip_class
>= GFX9
&&
5614 key
->part
.gs
.es
->type
== PIPE_SHADER_VERTEX
) {
5615 si_dump_shader_key_vs(key
, &key
->part
.gs
.vs_prolog
,
5616 "part.gs.vs_prolog", f
);
5618 fprintf(f
, " part.gs.prolog.tri_strip_adj_fix = %u\n", key
->part
.gs
.prolog
.tri_strip_adj_fix
);
5621 case PIPE_SHADER_COMPUTE
:
5624 case PIPE_SHADER_FRAGMENT
:
5625 fprintf(f
, " part.ps.prolog.color_two_side = %u\n", key
->part
.ps
.prolog
.color_two_side
);
5626 fprintf(f
, " part.ps.prolog.flatshade_colors = %u\n", key
->part
.ps
.prolog
.flatshade_colors
);
5627 fprintf(f
, " part.ps.prolog.poly_stipple = %u\n", key
->part
.ps
.prolog
.poly_stipple
);
5628 fprintf(f
, " part.ps.prolog.force_persp_sample_interp = %u\n", key
->part
.ps
.prolog
.force_persp_sample_interp
);
5629 fprintf(f
, " part.ps.prolog.force_linear_sample_interp = %u\n", key
->part
.ps
.prolog
.force_linear_sample_interp
);
5630 fprintf(f
, " part.ps.prolog.force_persp_center_interp = %u\n", key
->part
.ps
.prolog
.force_persp_center_interp
);
5631 fprintf(f
, " part.ps.prolog.force_linear_center_interp = %u\n", key
->part
.ps
.prolog
.force_linear_center_interp
);
5632 fprintf(f
, " part.ps.prolog.bc_optimize_for_persp = %u\n", key
->part
.ps
.prolog
.bc_optimize_for_persp
);
5633 fprintf(f
, " part.ps.prolog.bc_optimize_for_linear = %u\n", key
->part
.ps
.prolog
.bc_optimize_for_linear
);
5634 fprintf(f
, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key
->part
.ps
.epilog
.spi_shader_col_format
);
5635 fprintf(f
, " part.ps.epilog.color_is_int8 = 0x%X\n", key
->part
.ps
.epilog
.color_is_int8
);
5636 fprintf(f
, " part.ps.epilog.color_is_int10 = 0x%X\n", key
->part
.ps
.epilog
.color_is_int10
);
5637 fprintf(f
, " part.ps.epilog.last_cbuf = %u\n", key
->part
.ps
.epilog
.last_cbuf
);
5638 fprintf(f
, " part.ps.epilog.alpha_func = %u\n", key
->part
.ps
.epilog
.alpha_func
);
5639 fprintf(f
, " part.ps.epilog.alpha_to_one = %u\n", key
->part
.ps
.epilog
.alpha_to_one
);
5640 fprintf(f
, " part.ps.epilog.poly_line_smoothing = %u\n", key
->part
.ps
.epilog
.poly_line_smoothing
);
5641 fprintf(f
, " part.ps.epilog.clamp_color = %u\n", key
->part
.ps
.epilog
.clamp_color
);
5648 if ((processor
== PIPE_SHADER_GEOMETRY
||
5649 processor
== PIPE_SHADER_TESS_EVAL
||
5650 processor
== PIPE_SHADER_VERTEX
) &&
5651 !key
->as_es
&& !key
->as_ls
) {
5652 fprintf(f
, " opt.kill_outputs = 0x%"PRIx64
"\n", key
->opt
.kill_outputs
);
5653 fprintf(f
, " opt.clip_disable = %u\n", key
->opt
.clip_disable
);
5657 static void si_init_shader_ctx(struct si_shader_context
*ctx
,
5658 struct si_screen
*sscreen
,
5659 LLVMTargetMachineRef tm
)
5661 struct lp_build_tgsi_context
*bld_base
;
5663 si_llvm_context_init(ctx
, sscreen
, tm
);
5665 bld_base
= &ctx
->bld_base
;
5666 bld_base
->emit_fetch_funcs
[TGSI_FILE_CONSTANT
] = fetch_constant
;
5668 bld_base
->op_actions
[TGSI_OPCODE_INTERP_CENTROID
] = interp_action
;
5669 bld_base
->op_actions
[TGSI_OPCODE_INTERP_SAMPLE
] = interp_action
;
5670 bld_base
->op_actions
[TGSI_OPCODE_INTERP_OFFSET
] = interp_action
;
5672 bld_base
->op_actions
[TGSI_OPCODE_MEMBAR
].emit
= membar_emit
;
5674 bld_base
->op_actions
[TGSI_OPCODE_CLOCK
].emit
= clock_emit
;
5676 bld_base
->op_actions
[TGSI_OPCODE_DDX
].emit
= si_llvm_emit_ddxy
;
5677 bld_base
->op_actions
[TGSI_OPCODE_DDY
].emit
= si_llvm_emit_ddxy
;
5678 bld_base
->op_actions
[TGSI_OPCODE_DDX_FINE
].emit
= si_llvm_emit_ddxy
;
5679 bld_base
->op_actions
[TGSI_OPCODE_DDY_FINE
].emit
= si_llvm_emit_ddxy
;
5681 bld_base
->op_actions
[TGSI_OPCODE_VOTE_ALL
].emit
= vote_all_emit
;
5682 bld_base
->op_actions
[TGSI_OPCODE_VOTE_ANY
].emit
= vote_any_emit
;
5683 bld_base
->op_actions
[TGSI_OPCODE_VOTE_EQ
].emit
= vote_eq_emit
;
5684 bld_base
->op_actions
[TGSI_OPCODE_BALLOT
].emit
= ballot_emit
;
5685 bld_base
->op_actions
[TGSI_OPCODE_READ_FIRST
].intr_name
= "llvm.amdgcn.readfirstlane";
5686 bld_base
->op_actions
[TGSI_OPCODE_READ_FIRST
].emit
= read_lane_emit
;
5687 bld_base
->op_actions
[TGSI_OPCODE_READ_INVOC
].intr_name
= "llvm.amdgcn.readlane";
5688 bld_base
->op_actions
[TGSI_OPCODE_READ_INVOC
].fetch_args
= read_invoc_fetch_args
;
5689 bld_base
->op_actions
[TGSI_OPCODE_READ_INVOC
].emit
= read_lane_emit
;
5691 bld_base
->op_actions
[TGSI_OPCODE_EMIT
].emit
= si_tgsi_emit_vertex
;
5692 bld_base
->op_actions
[TGSI_OPCODE_ENDPRIM
].emit
= si_llvm_emit_primitive
;
5693 bld_base
->op_actions
[TGSI_OPCODE_BARRIER
].emit
= si_llvm_emit_barrier
;
5696 static void si_optimize_vs_outputs(struct si_shader_context
*ctx
)
5698 struct si_shader
*shader
= ctx
->shader
;
5699 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
5701 if ((ctx
->type
!= PIPE_SHADER_VERTEX
&&
5702 ctx
->type
!= PIPE_SHADER_TESS_EVAL
) ||
5703 shader
->key
.as_ls
||
5707 ac_optimize_vs_outputs(&ctx
->ac
,
5709 shader
->info
.vs_output_param_offset
,
5711 &shader
->info
.nr_param_exports
);
5714 static void si_count_scratch_private_memory(struct si_shader_context
*ctx
)
5716 ctx
->shader
->config
.private_mem_vgprs
= 0;
5718 /* Process all LLVM instructions. */
5719 LLVMBasicBlockRef bb
= LLVMGetFirstBasicBlock(ctx
->main_fn
);
5721 LLVMValueRef next
= LLVMGetFirstInstruction(bb
);
5724 LLVMValueRef inst
= next
;
5725 next
= LLVMGetNextInstruction(next
);
5727 if (LLVMGetInstructionOpcode(inst
) != LLVMAlloca
)
5730 LLVMTypeRef type
= LLVMGetElementType(LLVMTypeOf(inst
));
5731 /* No idea why LLVM aligns allocas to 4 elements. */
5732 unsigned alignment
= LLVMGetAlignment(inst
);
5733 unsigned dw_size
= align(ac_get_type_size(type
) / 4, alignment
);
5734 ctx
->shader
->config
.private_mem_vgprs
+= dw_size
;
5736 bb
= LLVMGetNextBasicBlock(bb
);
5740 static void si_init_exec_full_mask(struct si_shader_context
*ctx
)
5742 LLVMValueRef full_mask
= LLVMConstInt(ctx
->i64
, ~0ull, 0);
5743 lp_build_intrinsic(ctx
->ac
.builder
,
5744 "llvm.amdgcn.init.exec", ctx
->voidt
,
5745 &full_mask
, 1, LP_FUNC_ATTR_CONVERGENT
);
5748 static void si_init_exec_from_input(struct si_shader_context
*ctx
,
5749 unsigned param
, unsigned bitoffset
)
5751 LLVMValueRef args
[] = {
5752 LLVMGetParam(ctx
->main_fn
, param
),
5753 LLVMConstInt(ctx
->i32
, bitoffset
, 0),
5755 lp_build_intrinsic(ctx
->ac
.builder
,
5756 "llvm.amdgcn.init.exec.from.input",
5757 ctx
->voidt
, args
, 2, LP_FUNC_ATTR_CONVERGENT
);
5760 static bool si_vs_needs_prolog(const struct si_shader_selector
*sel
,
5761 const struct si_vs_prolog_bits
*key
)
5763 /* VGPR initialization fixup for Vega10 and Raven is always done in the
5765 return sel
->vs_needs_prolog
|| key
->ls_vgpr_fix
;
5768 static bool si_compile_tgsi_main(struct si_shader_context
*ctx
,
5771 struct si_shader
*shader
= ctx
->shader
;
5772 struct si_shader_selector
*sel
= shader
->selector
;
5773 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
5775 // TODO clean all this up!
5776 switch (ctx
->type
) {
5777 case PIPE_SHADER_VERTEX
:
5778 ctx
->load_input
= declare_input_vs
;
5779 if (shader
->key
.as_ls
)
5780 ctx
->abi
.emit_outputs
= si_llvm_emit_ls_epilogue
;
5781 else if (shader
->key
.as_es
)
5782 ctx
->abi
.emit_outputs
= si_llvm_emit_es_epilogue
;
5784 ctx
->abi
.emit_outputs
= si_llvm_emit_vs_epilogue
;
5785 bld_base
->emit_epilogue
= si_tgsi_emit_epilogue
;
5787 case PIPE_SHADER_TESS_CTRL
:
5788 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_tcs
;
5789 bld_base
->emit_fetch_funcs
[TGSI_FILE_OUTPUT
] = fetch_output_tcs
;
5790 bld_base
->emit_store
= store_output_tcs
;
5791 bld_base
->emit_epilogue
= si_llvm_emit_tcs_epilogue
;
5793 case PIPE_SHADER_TESS_EVAL
:
5794 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_tes
;
5795 if (shader
->key
.as_es
)
5796 ctx
->abi
.emit_outputs
= si_llvm_emit_es_epilogue
;
5798 ctx
->abi
.emit_outputs
= si_llvm_emit_vs_epilogue
;
5799 bld_base
->emit_epilogue
= si_tgsi_emit_epilogue
;
5801 case PIPE_SHADER_GEOMETRY
:
5802 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_gs
;
5803 ctx
->abi
.load_inputs
= si_nir_load_input_gs
;
5804 ctx
->abi
.emit_vertex
= si_llvm_emit_vertex
;
5805 ctx
->abi
.emit_outputs
= si_llvm_emit_gs_epilogue
;
5806 bld_base
->emit_epilogue
= si_tgsi_emit_gs_epilogue
;
5808 case PIPE_SHADER_FRAGMENT
:
5809 ctx
->load_input
= declare_input_fs
;
5810 ctx
->abi
.emit_outputs
= si_llvm_return_fs_outputs
;
5811 bld_base
->emit_epilogue
= si_tgsi_emit_epilogue
;
5813 case PIPE_SHADER_COMPUTE
:
5816 assert(!"Unsupported shader type");
5820 ctx
->abi
.load_ubo
= load_ubo
;
5821 ctx
->abi
.load_ssbo
= load_ssbo
;
5823 create_function(ctx
);
5824 preload_ring_buffers(ctx
);
5826 /* For GFX9 merged shaders:
5827 * - Set EXEC for the first shader. If the prolog is present, set
5828 * EXEC there instead.
5829 * - Add a barrier before the second shader.
5830 * - In the second shader, reset EXEC to ~0 and wrap the main part in
5831 * an if-statement. This is required for correctness in geometry
5832 * shaders, to ensure that empty GS waves do not send GS_EMIT and
5835 * For monolithic merged shaders, the first shader is wrapped in an
5836 * if-block together with its prolog in si_build_wrapper_function.
5838 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
5839 if (!is_monolithic
&&
5840 sel
->info
.num_instructions
> 1 && /* not empty shader */
5841 (shader
->key
.as_es
|| shader
->key
.as_ls
) &&
5842 (ctx
->type
== PIPE_SHADER_TESS_EVAL
||
5843 (ctx
->type
== PIPE_SHADER_VERTEX
&&
5844 !si_vs_needs_prolog(sel
, &shader
->key
.part
.vs
.prolog
)))) {
5845 si_init_exec_from_input(ctx
,
5846 ctx
->param_merged_wave_info
, 0);
5847 } else if (ctx
->type
== PIPE_SHADER_TESS_CTRL
||
5848 ctx
->type
== PIPE_SHADER_GEOMETRY
) {
5850 si_init_exec_full_mask(ctx
);
5852 /* The barrier must execute for all shaders in a
5855 si_llvm_emit_barrier(NULL
, bld_base
, NULL
);
5857 LLVMValueRef num_threads
= unpack_param(ctx
, ctx
->param_merged_wave_info
, 8, 8);
5859 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
5860 ac_get_thread_id(&ctx
->ac
), num_threads
, "");
5861 lp_build_if(&ctx
->merged_wrap_if_state
, &ctx
->gallivm
, ena
);
5865 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&&
5866 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
) {
5867 for (unsigned i
= 0; i
< 6; i
++) {
5868 ctx
->invoc0_tess_factors
[i
] =
5869 lp_build_alloca_undef(&ctx
->gallivm
, ctx
->i32
, "");
5873 if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
5875 for (i
= 0; i
< 4; i
++) {
5876 ctx
->gs_next_vertex
[i
] =
5877 lp_build_alloca(&ctx
->gallivm
,
5882 if (sel
->force_correct_derivs_after_kill
) {
5883 ctx
->postponed_kill
= lp_build_alloca_undef(&ctx
->gallivm
, ctx
->i1
, "");
5884 /* true = don't kill. */
5885 LLVMBuildStore(ctx
->ac
.builder
, LLVMConstInt(ctx
->i1
, 1, 0),
5886 ctx
->postponed_kill
);
5890 if (!lp_build_tgsi_llvm(bld_base
, sel
->tokens
)) {
5891 fprintf(stderr
, "Failed to translate shader from TGSI to LLVM\n");
5895 if (!si_nir_build_llvm(ctx
, sel
->nir
)) {
5896 fprintf(stderr
, "Failed to translate shader from NIR to LLVM\n");
5901 si_llvm_build_ret(ctx
, ctx
->return_value
);
5906 * Compute the VS prolog key, which contains all the information needed to
5907 * build the VS prolog function, and set shader->info bits where needed.
5909 * \param info Shader info of the vertex shader.
5910 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
5911 * \param prolog_key Key of the VS prolog
5912 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
5913 * \param key Output shader part key.
5915 static void si_get_vs_prolog_key(const struct tgsi_shader_info
*info
,
5916 unsigned num_input_sgprs
,
5917 const struct si_vs_prolog_bits
*prolog_key
,
5918 struct si_shader
*shader_out
,
5919 union si_shader_part_key
*key
)
5921 memset(key
, 0, sizeof(*key
));
5922 key
->vs_prolog
.states
= *prolog_key
;
5923 key
->vs_prolog
.num_input_sgprs
= num_input_sgprs
;
5924 key
->vs_prolog
.last_input
= MAX2(1, info
->num_inputs
) - 1;
5925 key
->vs_prolog
.as_ls
= shader_out
->key
.as_ls
;
5926 key
->vs_prolog
.as_es
= shader_out
->key
.as_es
;
5928 if (shader_out
->selector
->type
== PIPE_SHADER_TESS_CTRL
) {
5929 key
->vs_prolog
.as_ls
= 1;
5930 key
->vs_prolog
.num_merged_next_stage_vgprs
= 2;
5931 } else if (shader_out
->selector
->type
== PIPE_SHADER_GEOMETRY
) {
5932 key
->vs_prolog
.as_es
= 1;
5933 key
->vs_prolog
.num_merged_next_stage_vgprs
= 5;
5936 /* Enable loading the InstanceID VGPR. */
5937 uint16_t input_mask
= u_bit_consecutive(0, info
->num_inputs
);
5939 if ((key
->vs_prolog
.states
.instance_divisor_is_one
|
5940 key
->vs_prolog
.states
.instance_divisor_is_fetched
) & input_mask
)
5941 shader_out
->info
.uses_instanceid
= true;
5945 * Compute the PS prolog key, which contains all the information needed to
5946 * build the PS prolog function, and set related bits in shader->config.
5948 static void si_get_ps_prolog_key(struct si_shader
*shader
,
5949 union si_shader_part_key
*key
,
5950 bool separate_prolog
)
5952 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
5954 memset(key
, 0, sizeof(*key
));
5955 key
->ps_prolog
.states
= shader
->key
.part
.ps
.prolog
;
5956 key
->ps_prolog
.colors_read
= info
->colors_read
;
5957 key
->ps_prolog
.num_input_sgprs
= shader
->info
.num_input_sgprs
;
5958 key
->ps_prolog
.num_input_vgprs
= shader
->info
.num_input_vgprs
;
5959 key
->ps_prolog
.wqm
= info
->uses_derivatives
&&
5960 (key
->ps_prolog
.colors_read
||
5961 key
->ps_prolog
.states
.force_persp_sample_interp
||
5962 key
->ps_prolog
.states
.force_linear_sample_interp
||
5963 key
->ps_prolog
.states
.force_persp_center_interp
||
5964 key
->ps_prolog
.states
.force_linear_center_interp
||
5965 key
->ps_prolog
.states
.bc_optimize_for_persp
||
5966 key
->ps_prolog
.states
.bc_optimize_for_linear
);
5967 key
->ps_prolog
.ancillary_vgpr_index
= shader
->info
.ancillary_vgpr_index
;
5969 if (info
->colors_read
) {
5970 unsigned *color
= shader
->selector
->color_attr_index
;
5972 if (shader
->key
.part
.ps
.prolog
.color_two_side
) {
5973 /* BCOLORs are stored after the last input. */
5974 key
->ps_prolog
.num_interp_inputs
= info
->num_inputs
;
5975 key
->ps_prolog
.face_vgpr_index
= shader
->info
.face_vgpr_index
;
5976 shader
->config
.spi_ps_input_ena
|= S_0286CC_FRONT_FACE_ENA(1);
5979 for (unsigned i
= 0; i
< 2; i
++) {
5980 unsigned interp
= info
->input_interpolate
[color
[i
]];
5981 unsigned location
= info
->input_interpolate_loc
[color
[i
]];
5983 if (!(info
->colors_read
& (0xf << i
*4)))
5986 key
->ps_prolog
.color_attr_index
[i
] = color
[i
];
5988 if (shader
->key
.part
.ps
.prolog
.flatshade_colors
&&
5989 interp
== TGSI_INTERPOLATE_COLOR
)
5990 interp
= TGSI_INTERPOLATE_CONSTANT
;
5993 case TGSI_INTERPOLATE_CONSTANT
:
5994 key
->ps_prolog
.color_interp_vgpr_index
[i
] = -1;
5996 case TGSI_INTERPOLATE_PERSPECTIVE
:
5997 case TGSI_INTERPOLATE_COLOR
:
5998 /* Force the interpolation location for colors here. */
5999 if (shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
)
6000 location
= TGSI_INTERPOLATE_LOC_SAMPLE
;
6001 if (shader
->key
.part
.ps
.prolog
.force_persp_center_interp
)
6002 location
= TGSI_INTERPOLATE_LOC_CENTER
;
6005 case TGSI_INTERPOLATE_LOC_SAMPLE
:
6006 key
->ps_prolog
.color_interp_vgpr_index
[i
] = 0;
6007 shader
->config
.spi_ps_input_ena
|=
6008 S_0286CC_PERSP_SAMPLE_ENA(1);
6010 case TGSI_INTERPOLATE_LOC_CENTER
:
6011 key
->ps_prolog
.color_interp_vgpr_index
[i
] = 2;
6012 shader
->config
.spi_ps_input_ena
|=
6013 S_0286CC_PERSP_CENTER_ENA(1);
6015 case TGSI_INTERPOLATE_LOC_CENTROID
:
6016 key
->ps_prolog
.color_interp_vgpr_index
[i
] = 4;
6017 shader
->config
.spi_ps_input_ena
|=
6018 S_0286CC_PERSP_CENTROID_ENA(1);
6024 case TGSI_INTERPOLATE_LINEAR
:
6025 /* Force the interpolation location for colors here. */
6026 if (shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
)
6027 location
= TGSI_INTERPOLATE_LOC_SAMPLE
;
6028 if (shader
->key
.part
.ps
.prolog
.force_linear_center_interp
)
6029 location
= TGSI_INTERPOLATE_LOC_CENTER
;
6031 /* The VGPR assignment for non-monolithic shaders
6032 * works because InitialPSInputAddr is set on the
6033 * main shader and PERSP_PULL_MODEL is never used.
6036 case TGSI_INTERPOLATE_LOC_SAMPLE
:
6037 key
->ps_prolog
.color_interp_vgpr_index
[i
] =
6038 separate_prolog
? 6 : 9;
6039 shader
->config
.spi_ps_input_ena
|=
6040 S_0286CC_LINEAR_SAMPLE_ENA(1);
6042 case TGSI_INTERPOLATE_LOC_CENTER
:
6043 key
->ps_prolog
.color_interp_vgpr_index
[i
] =
6044 separate_prolog
? 8 : 11;
6045 shader
->config
.spi_ps_input_ena
|=
6046 S_0286CC_LINEAR_CENTER_ENA(1);
6048 case TGSI_INTERPOLATE_LOC_CENTROID
:
6049 key
->ps_prolog
.color_interp_vgpr_index
[i
] =
6050 separate_prolog
? 10 : 13;
6051 shader
->config
.spi_ps_input_ena
|=
6052 S_0286CC_LINEAR_CENTROID_ENA(1);
6066 * Check whether a PS prolog is required based on the key.
6068 static bool si_need_ps_prolog(const union si_shader_part_key
*key
)
6070 return key
->ps_prolog
.colors_read
||
6071 key
->ps_prolog
.states
.force_persp_sample_interp
||
6072 key
->ps_prolog
.states
.force_linear_sample_interp
||
6073 key
->ps_prolog
.states
.force_persp_center_interp
||
6074 key
->ps_prolog
.states
.force_linear_center_interp
||
6075 key
->ps_prolog
.states
.bc_optimize_for_persp
||
6076 key
->ps_prolog
.states
.bc_optimize_for_linear
||
6077 key
->ps_prolog
.states
.poly_stipple
||
6078 key
->ps_prolog
.states
.samplemask_log_ps_iter
;
6082 * Compute the PS epilog key, which contains all the information needed to
6083 * build the PS epilog function.
6085 static void si_get_ps_epilog_key(struct si_shader
*shader
,
6086 union si_shader_part_key
*key
)
6088 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
6089 memset(key
, 0, sizeof(*key
));
6090 key
->ps_epilog
.colors_written
= info
->colors_written
;
6091 key
->ps_epilog
.writes_z
= info
->writes_z
;
6092 key
->ps_epilog
.writes_stencil
= info
->writes_stencil
;
6093 key
->ps_epilog
.writes_samplemask
= info
->writes_samplemask
;
6094 key
->ps_epilog
.states
= shader
->key
.part
.ps
.epilog
;
6098 * Build the GS prolog function. Rotate the input vertices for triangle strips
6101 static void si_build_gs_prolog_function(struct si_shader_context
*ctx
,
6102 union si_shader_part_key
*key
)
6104 unsigned num_sgprs
, num_vgprs
;
6105 struct si_function_info fninfo
;
6106 LLVMBuilderRef builder
= ctx
->ac
.builder
;
6107 LLVMTypeRef returns
[48];
6108 LLVMValueRef func
, ret
;
6110 si_init_function_info(&fninfo
);
6112 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
6113 num_sgprs
= 8 + GFX9_GS_NUM_USER_SGPR
;
6114 num_vgprs
= 5; /* ES inputs are not needed by GS */
6116 num_sgprs
= GFX6_GS_NUM_USER_SGPR
+ 2;
6120 for (unsigned i
= 0; i
< num_sgprs
; ++i
) {
6121 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
6122 returns
[i
] = ctx
->i32
;
6125 for (unsigned i
= 0; i
< num_vgprs
; ++i
) {
6126 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
6127 returns
[num_sgprs
+ i
] = ctx
->f32
;
6130 /* Create the function. */
6131 si_create_function(ctx
, "gs_prolog", returns
, num_sgprs
+ num_vgprs
,
6133 func
= ctx
->main_fn
;
6135 /* Set the full EXEC mask for the prolog, because we are only fiddling
6136 * with registers here. The main shader part will set the correct EXEC
6139 if (ctx
->screen
->info
.chip_class
>= GFX9
&& !key
->gs_prolog
.is_monolithic
)
6140 si_init_exec_full_mask(ctx
);
6142 /* Copy inputs to outputs. This should be no-op, as the registers match,
6143 * but it will prevent the compiler from overwriting them unintentionally.
6145 ret
= ctx
->return_value
;
6146 for (unsigned i
= 0; i
< num_sgprs
; i
++) {
6147 LLVMValueRef p
= LLVMGetParam(func
, i
);
6148 ret
= LLVMBuildInsertValue(builder
, ret
, p
, i
, "");
6150 for (unsigned i
= 0; i
< num_vgprs
; i
++) {
6151 LLVMValueRef p
= LLVMGetParam(func
, num_sgprs
+ i
);
6152 p
= ac_to_float(&ctx
->ac
, p
);
6153 ret
= LLVMBuildInsertValue(builder
, ret
, p
, num_sgprs
+ i
, "");
6156 if (key
->gs_prolog
.states
.tri_strip_adj_fix
) {
6157 /* Remap the input vertices for every other primitive. */
6158 const unsigned gfx6_vtx_params
[6] = {
6166 const unsigned gfx9_vtx_params
[3] = {
6171 LLVMValueRef vtx_in
[6], vtx_out
[6];
6172 LLVMValueRef prim_id
, rotate
;
6174 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
6175 for (unsigned i
= 0; i
< 3; i
++) {
6176 vtx_in
[i
*2] = unpack_param(ctx
, gfx9_vtx_params
[i
], 0, 16);
6177 vtx_in
[i
*2+1] = unpack_param(ctx
, gfx9_vtx_params
[i
], 16, 16);
6180 for (unsigned i
= 0; i
< 6; i
++)
6181 vtx_in
[i
] = LLVMGetParam(func
, gfx6_vtx_params
[i
]);
6184 prim_id
= LLVMGetParam(func
, num_sgprs
+ 2);
6185 rotate
= LLVMBuildTrunc(builder
, prim_id
, ctx
->i1
, "");
6187 for (unsigned i
= 0; i
< 6; ++i
) {
6188 LLVMValueRef base
, rotated
;
6190 rotated
= vtx_in
[(i
+ 4) % 6];
6191 vtx_out
[i
] = LLVMBuildSelect(builder
, rotate
, rotated
, base
, "");
6194 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
6195 for (unsigned i
= 0; i
< 3; i
++) {
6196 LLVMValueRef hi
, out
;
6198 hi
= LLVMBuildShl(builder
, vtx_out
[i
*2+1],
6199 LLVMConstInt(ctx
->i32
, 16, 0), "");
6200 out
= LLVMBuildOr(builder
, vtx_out
[i
*2], hi
, "");
6201 out
= ac_to_float(&ctx
->ac
, out
);
6202 ret
= LLVMBuildInsertValue(builder
, ret
, out
,
6203 gfx9_vtx_params
[i
], "");
6206 for (unsigned i
= 0; i
< 6; i
++) {
6209 out
= ac_to_float(&ctx
->ac
, vtx_out
[i
]);
6210 ret
= LLVMBuildInsertValue(builder
, ret
, out
,
6211 gfx6_vtx_params
[i
], "");
6216 LLVMBuildRet(builder
, ret
);
6220 * Given a list of shader part functions, build a wrapper function that
6221 * runs them in sequence to form a monolithic shader.
6223 static void si_build_wrapper_function(struct si_shader_context
*ctx
,
6224 LLVMValueRef
*parts
,
6227 unsigned next_shader_first_part
)
6229 LLVMBuilderRef builder
= ctx
->ac
.builder
;
6230 /* PS epilog has one arg per color component; gfx9 merged shader
6231 * prologs need to forward 32 user SGPRs.
6233 struct si_function_info fninfo
;
6234 LLVMValueRef initial
[64], out
[64];
6235 LLVMTypeRef function_type
;
6236 unsigned num_first_params
;
6237 unsigned num_out
, initial_num_out
;
6238 MAYBE_UNUSED
unsigned num_out_sgpr
; /* used in debug checks */
6239 MAYBE_UNUSED
unsigned initial_num_out_sgpr
; /* used in debug checks */
6240 unsigned num_sgprs
, num_vgprs
;
6242 struct lp_build_if_state if_state
;
6244 si_init_function_info(&fninfo
);
6246 for (unsigned i
= 0; i
< num_parts
; ++i
) {
6247 lp_add_function_attr(parts
[i
], -1, LP_FUNC_ATTR_ALWAYSINLINE
);
6248 LLVMSetLinkage(parts
[i
], LLVMPrivateLinkage
);
6251 /* The parameters of the wrapper function correspond to those of the
6252 * first part in terms of SGPRs and VGPRs, but we use the types of the
6253 * main part to get the right types. This is relevant for the
6254 * dereferenceable attribute on descriptor table pointers.
6259 function_type
= LLVMGetElementType(LLVMTypeOf(parts
[0]));
6260 num_first_params
= LLVMCountParamTypes(function_type
);
6262 for (unsigned i
= 0; i
< num_first_params
; ++i
) {
6263 LLVMValueRef param
= LLVMGetParam(parts
[0], i
);
6265 if (ac_is_sgpr_param(param
)) {
6266 assert(num_vgprs
== 0);
6267 num_sgprs
+= ac_get_type_size(LLVMTypeOf(param
)) / 4;
6269 num_vgprs
+= ac_get_type_size(LLVMTypeOf(param
)) / 4;
6274 while (gprs
< num_sgprs
+ num_vgprs
) {
6275 LLVMValueRef param
= LLVMGetParam(parts
[main_part
], fninfo
.num_params
);
6276 LLVMTypeRef type
= LLVMTypeOf(param
);
6277 unsigned size
= ac_get_type_size(type
) / 4;
6279 add_arg(&fninfo
, gprs
< num_sgprs
? ARG_SGPR
: ARG_VGPR
, type
);
6281 assert(ac_is_sgpr_param(param
) == (gprs
< num_sgprs
));
6282 assert(gprs
+ size
<= num_sgprs
+ num_vgprs
&&
6283 (gprs
>= num_sgprs
|| gprs
+ size
<= num_sgprs
));
6288 si_create_function(ctx
, "wrapper", NULL
, 0, &fninfo
,
6289 si_get_max_workgroup_size(ctx
->shader
));
6291 if (is_merged_shader(ctx
->shader
))
6292 si_init_exec_full_mask(ctx
);
6294 /* Record the arguments of the function as if they were an output of
6300 for (unsigned i
= 0; i
< fninfo
.num_params
; ++i
) {
6301 LLVMValueRef param
= LLVMGetParam(ctx
->main_fn
, i
);
6302 LLVMTypeRef param_type
= LLVMTypeOf(param
);
6303 LLVMTypeRef out_type
= i
< fninfo
.num_sgpr_params
? ctx
->i32
: ctx
->f32
;
6304 unsigned size
= ac_get_type_size(param_type
) / 4;
6307 if (param_type
!= out_type
)
6308 param
= LLVMBuildBitCast(builder
, param
, out_type
, "");
6309 out
[num_out
++] = param
;
6311 LLVMTypeRef vector_type
= LLVMVectorType(out_type
, size
);
6313 if (LLVMGetTypeKind(param_type
) == LLVMPointerTypeKind
) {
6314 param
= LLVMBuildPtrToInt(builder
, param
, ctx
->i64
, "");
6315 param_type
= ctx
->i64
;
6318 if (param_type
!= vector_type
)
6319 param
= LLVMBuildBitCast(builder
, param
, vector_type
, "");
6321 for (unsigned j
= 0; j
< size
; ++j
)
6322 out
[num_out
++] = LLVMBuildExtractElement(
6323 builder
, param
, LLVMConstInt(ctx
->i32
, j
, 0), "");
6326 if (i
< fninfo
.num_sgpr_params
)
6327 num_out_sgpr
= num_out
;
6330 memcpy(initial
, out
, sizeof(out
));
6331 initial_num_out
= num_out
;
6332 initial_num_out_sgpr
= num_out_sgpr
;
6334 /* Now chain the parts. */
6335 for (unsigned part
= 0; part
< num_parts
; ++part
) {
6336 LLVMValueRef in
[48];
6338 LLVMTypeRef ret_type
;
6339 unsigned out_idx
= 0;
6340 unsigned num_params
= LLVMCountParams(parts
[part
]);
6342 /* Merged shaders are executed conditionally depending
6343 * on the number of enabled threads passed in the input SGPRs. */
6344 if (is_merged_shader(ctx
->shader
) && part
== 0) {
6345 LLVMValueRef ena
, count
= initial
[3];
6347 count
= LLVMBuildAnd(builder
, count
,
6348 LLVMConstInt(ctx
->i32
, 0x7f, 0), "");
6349 ena
= LLVMBuildICmp(builder
, LLVMIntULT
,
6350 ac_get_thread_id(&ctx
->ac
), count
, "");
6351 lp_build_if(&if_state
, &ctx
->gallivm
, ena
);
6354 /* Derive arguments for the next part from outputs of the
6357 for (unsigned param_idx
= 0; param_idx
< num_params
; ++param_idx
) {
6359 LLVMTypeRef param_type
;
6361 unsigned param_size
;
6362 LLVMValueRef arg
= NULL
;
6364 param
= LLVMGetParam(parts
[part
], param_idx
);
6365 param_type
= LLVMTypeOf(param
);
6366 param_size
= ac_get_type_size(param_type
) / 4;
6367 is_sgpr
= ac_is_sgpr_param(param
);
6370 #if HAVE_LLVM < 0x0400
6371 LLVMRemoveAttribute(param
, LLVMByValAttribute
);
6373 unsigned kind_id
= LLVMGetEnumAttributeKindForName("byval", 5);
6374 LLVMRemoveEnumAttributeAtIndex(parts
[part
], param_idx
+ 1, kind_id
);
6376 lp_add_function_attr(parts
[part
], param_idx
+ 1, LP_FUNC_ATTR_INREG
);
6379 assert(out_idx
+ param_size
<= (is_sgpr
? num_out_sgpr
: num_out
));
6380 assert(is_sgpr
|| out_idx
>= num_out_sgpr
);
6382 if (param_size
== 1)
6385 arg
= lp_build_gather_values(&ctx
->gallivm
, &out
[out_idx
], param_size
);
6387 if (LLVMTypeOf(arg
) != param_type
) {
6388 if (LLVMGetTypeKind(param_type
) == LLVMPointerTypeKind
) {
6389 arg
= LLVMBuildBitCast(builder
, arg
, ctx
->i64
, "");
6390 arg
= LLVMBuildIntToPtr(builder
, arg
, param_type
, "");
6392 arg
= LLVMBuildBitCast(builder
, arg
, param_type
, "");
6396 in
[param_idx
] = arg
;
6397 out_idx
+= param_size
;
6400 ret
= LLVMBuildCall(builder
, parts
[part
], in
, num_params
, "");
6402 if (is_merged_shader(ctx
->shader
) &&
6403 part
+ 1 == next_shader_first_part
) {
6404 lp_build_endif(&if_state
);
6406 /* The second half of the merged shader should use
6407 * the inputs from the toplevel (wrapper) function,
6408 * not the return value from the last call.
6410 * That's because the last call was executed condi-
6411 * tionally, so we can't consume it in the main
6414 memcpy(out
, initial
, sizeof(initial
));
6415 num_out
= initial_num_out
;
6416 num_out_sgpr
= initial_num_out_sgpr
;
6420 /* Extract the returned GPRs. */
6421 ret_type
= LLVMTypeOf(ret
);
6425 if (LLVMGetTypeKind(ret_type
) != LLVMVoidTypeKind
) {
6426 assert(LLVMGetTypeKind(ret_type
) == LLVMStructTypeKind
);
6428 unsigned ret_size
= LLVMCountStructElementTypes(ret_type
);
6430 for (unsigned i
= 0; i
< ret_size
; ++i
) {
6432 LLVMBuildExtractValue(builder
, ret
, i
, "");
6434 assert(num_out
< ARRAY_SIZE(out
));
6435 out
[num_out
++] = val
;
6437 if (LLVMTypeOf(val
) == ctx
->i32
) {
6438 assert(num_out_sgpr
+ 1 == num_out
);
6439 num_out_sgpr
= num_out
;
6445 LLVMBuildRetVoid(builder
);
6448 int si_compile_tgsi_shader(struct si_screen
*sscreen
,
6449 LLVMTargetMachineRef tm
,
6450 struct si_shader
*shader
,
6452 struct pipe_debug_callback
*debug
)
6454 struct si_shader_selector
*sel
= shader
->selector
;
6455 struct si_shader_context ctx
;
6458 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6459 * conversion fails. */
6460 if (si_can_dump_shader(sscreen
, sel
->info
.processor
) &&
6461 !(sscreen
->debug_flags
& DBG(NO_TGSI
))) {
6463 tgsi_dump(sel
->tokens
, 0);
6465 nir_print_shader(sel
->nir
, stderr
);
6466 si_dump_streamout(&sel
->so
);
6469 si_init_shader_ctx(&ctx
, sscreen
, tm
);
6470 si_llvm_context_set_tgsi(&ctx
, shader
);
6471 ctx
.separate_prolog
= !is_monolithic
;
6473 memset(shader
->info
.vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
6474 sizeof(shader
->info
.vs_output_param_offset
));
6476 shader
->info
.uses_instanceid
= sel
->info
.uses_instanceid
;
6478 if (!si_compile_tgsi_main(&ctx
, is_monolithic
)) {
6479 si_llvm_dispose(&ctx
);
6483 if (is_monolithic
&& ctx
.type
== PIPE_SHADER_VERTEX
) {
6484 LLVMValueRef parts
[2];
6485 bool need_prolog
= sel
->vs_needs_prolog
;
6487 parts
[1] = ctx
.main_fn
;
6490 union si_shader_part_key prolog_key
;
6491 si_get_vs_prolog_key(&sel
->info
,
6492 shader
->info
.num_input_sgprs
,
6493 &shader
->key
.part
.vs
.prolog
,
6494 shader
, &prolog_key
);
6495 si_build_vs_prolog_function(&ctx
, &prolog_key
);
6496 parts
[0] = ctx
.main_fn
;
6499 si_build_wrapper_function(&ctx
, parts
+ !need_prolog
,
6500 1 + need_prolog
, need_prolog
, 0);
6501 } else if (is_monolithic
&& ctx
.type
== PIPE_SHADER_TESS_CTRL
) {
6502 if (sscreen
->info
.chip_class
>= GFX9
) {
6503 struct si_shader_selector
*ls
= shader
->key
.part
.tcs
.ls
;
6504 LLVMValueRef parts
[4];
6505 bool vs_needs_prolog
=
6506 si_vs_needs_prolog(ls
, &shader
->key
.part
.tcs
.ls_prolog
);
6509 parts
[2] = ctx
.main_fn
;
6512 union si_shader_part_key tcs_epilog_key
;
6513 memset(&tcs_epilog_key
, 0, sizeof(tcs_epilog_key
));
6514 tcs_epilog_key
.tcs_epilog
.states
= shader
->key
.part
.tcs
.epilog
;
6515 si_build_tcs_epilog_function(&ctx
, &tcs_epilog_key
);
6516 parts
[3] = ctx
.main_fn
;
6519 if (vs_needs_prolog
) {
6520 union si_shader_part_key vs_prolog_key
;
6521 si_get_vs_prolog_key(&ls
->info
,
6522 shader
->info
.num_input_sgprs
,
6523 &shader
->key
.part
.tcs
.ls_prolog
,
6524 shader
, &vs_prolog_key
);
6525 vs_prolog_key
.vs_prolog
.is_monolithic
= true;
6526 si_build_vs_prolog_function(&ctx
, &vs_prolog_key
);
6527 parts
[0] = ctx
.main_fn
;
6530 /* VS as LS main part */
6531 struct si_shader shader_ls
= {};
6532 shader_ls
.selector
= ls
;
6533 shader_ls
.key
.as_ls
= 1;
6534 shader_ls
.key
.mono
= shader
->key
.mono
;
6535 shader_ls
.key
.opt
= shader
->key
.opt
;
6536 si_llvm_context_set_tgsi(&ctx
, &shader_ls
);
6538 if (!si_compile_tgsi_main(&ctx
, true)) {
6539 si_llvm_dispose(&ctx
);
6542 shader
->info
.uses_instanceid
|= ls
->info
.uses_instanceid
;
6543 parts
[1] = ctx
.main_fn
;
6545 /* Reset the shader context. */
6546 ctx
.shader
= shader
;
6547 ctx
.type
= PIPE_SHADER_TESS_CTRL
;
6549 si_build_wrapper_function(&ctx
,
6550 parts
+ !vs_needs_prolog
,
6551 4 - !vs_needs_prolog
, 0,
6552 vs_needs_prolog
? 2 : 1);
6554 LLVMValueRef parts
[2];
6555 union si_shader_part_key epilog_key
;
6557 parts
[0] = ctx
.main_fn
;
6559 memset(&epilog_key
, 0, sizeof(epilog_key
));
6560 epilog_key
.tcs_epilog
.states
= shader
->key
.part
.tcs
.epilog
;
6561 si_build_tcs_epilog_function(&ctx
, &epilog_key
);
6562 parts
[1] = ctx
.main_fn
;
6564 si_build_wrapper_function(&ctx
, parts
, 2, 0, 0);
6566 } else if (is_monolithic
&& ctx
.type
== PIPE_SHADER_GEOMETRY
) {
6567 if (ctx
.screen
->info
.chip_class
>= GFX9
) {
6568 struct si_shader_selector
*es
= shader
->key
.part
.gs
.es
;
6569 LLVMValueRef es_prolog
= NULL
;
6570 LLVMValueRef es_main
= NULL
;
6571 LLVMValueRef gs_prolog
= NULL
;
6572 LLVMValueRef gs_main
= ctx
.main_fn
;
6575 union si_shader_part_key gs_prolog_key
;
6576 memset(&gs_prolog_key
, 0, sizeof(gs_prolog_key
));
6577 gs_prolog_key
.gs_prolog
.states
= shader
->key
.part
.gs
.prolog
;
6578 gs_prolog_key
.gs_prolog
.is_monolithic
= true;
6579 si_build_gs_prolog_function(&ctx
, &gs_prolog_key
);
6580 gs_prolog
= ctx
.main_fn
;
6583 if (es
->vs_needs_prolog
) {
6584 union si_shader_part_key vs_prolog_key
;
6585 si_get_vs_prolog_key(&es
->info
,
6586 shader
->info
.num_input_sgprs
,
6587 &shader
->key
.part
.gs
.vs_prolog
,
6588 shader
, &vs_prolog_key
);
6589 vs_prolog_key
.vs_prolog
.is_monolithic
= true;
6590 si_build_vs_prolog_function(&ctx
, &vs_prolog_key
);
6591 es_prolog
= ctx
.main_fn
;
6595 struct si_shader shader_es
= {};
6596 shader_es
.selector
= es
;
6597 shader_es
.key
.as_es
= 1;
6598 shader_es
.key
.mono
= shader
->key
.mono
;
6599 shader_es
.key
.opt
= shader
->key
.opt
;
6600 si_llvm_context_set_tgsi(&ctx
, &shader_es
);
6602 if (!si_compile_tgsi_main(&ctx
, true)) {
6603 si_llvm_dispose(&ctx
);
6606 shader
->info
.uses_instanceid
|= es
->info
.uses_instanceid
;
6607 es_main
= ctx
.main_fn
;
6609 /* Reset the shader context. */
6610 ctx
.shader
= shader
;
6611 ctx
.type
= PIPE_SHADER_GEOMETRY
;
6613 /* Prepare the array of shader parts. */
6614 LLVMValueRef parts
[4];
6615 unsigned num_parts
= 0, main_part
, next_first_part
;
6618 parts
[num_parts
++] = es_prolog
;
6620 parts
[main_part
= num_parts
++] = es_main
;
6621 parts
[next_first_part
= num_parts
++] = gs_prolog
;
6622 parts
[num_parts
++] = gs_main
;
6624 si_build_wrapper_function(&ctx
, parts
, num_parts
,
6625 main_part
, next_first_part
);
6627 LLVMValueRef parts
[2];
6628 union si_shader_part_key prolog_key
;
6630 parts
[1] = ctx
.main_fn
;
6632 memset(&prolog_key
, 0, sizeof(prolog_key
));
6633 prolog_key
.gs_prolog
.states
= shader
->key
.part
.gs
.prolog
;
6634 si_build_gs_prolog_function(&ctx
, &prolog_key
);
6635 parts
[0] = ctx
.main_fn
;
6637 si_build_wrapper_function(&ctx
, parts
, 2, 1, 0);
6639 } else if (is_monolithic
&& ctx
.type
== PIPE_SHADER_FRAGMENT
) {
6640 LLVMValueRef parts
[3];
6641 union si_shader_part_key prolog_key
;
6642 union si_shader_part_key epilog_key
;
6645 si_get_ps_prolog_key(shader
, &prolog_key
, false);
6646 need_prolog
= si_need_ps_prolog(&prolog_key
);
6648 parts
[need_prolog
? 1 : 0] = ctx
.main_fn
;
6651 si_build_ps_prolog_function(&ctx
, &prolog_key
);
6652 parts
[0] = ctx
.main_fn
;
6655 si_get_ps_epilog_key(shader
, &epilog_key
);
6656 si_build_ps_epilog_function(&ctx
, &epilog_key
);
6657 parts
[need_prolog
? 2 : 1] = ctx
.main_fn
;
6659 si_build_wrapper_function(&ctx
, parts
, need_prolog
? 3 : 2,
6660 need_prolog
? 1 : 0, 0);
6663 si_llvm_optimize_module(&ctx
);
6665 /* Post-optimization transformations and analysis. */
6666 si_optimize_vs_outputs(&ctx
);
6668 if ((debug
&& debug
->debug_message
) ||
6669 si_can_dump_shader(sscreen
, ctx
.type
))
6670 si_count_scratch_private_memory(&ctx
);
6672 /* Compile to bytecode. */
6673 r
= si_compile_llvm(sscreen
, &shader
->binary
, &shader
->config
, tm
,
6674 ctx
.gallivm
.module
, debug
, ctx
.type
, "TGSI shader");
6675 si_llvm_dispose(&ctx
);
6677 fprintf(stderr
, "LLVM failed to compile shader\n");
6681 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6682 * LLVM 3.9svn has this bug.
6684 if (sel
->type
== PIPE_SHADER_COMPUTE
) {
6685 unsigned wave_size
= 64;
6686 unsigned max_vgprs
= 256;
6687 unsigned max_sgprs
= sscreen
->info
.chip_class
>= VI
? 800 : 512;
6688 unsigned max_sgprs_per_wave
= 128;
6689 unsigned max_block_threads
= si_get_max_workgroup_size(shader
);
6690 unsigned min_waves_per_cu
= DIV_ROUND_UP(max_block_threads
, wave_size
);
6691 unsigned min_waves_per_simd
= DIV_ROUND_UP(min_waves_per_cu
, 4);
6693 max_vgprs
= max_vgprs
/ min_waves_per_simd
;
6694 max_sgprs
= MIN2(max_sgprs
/ min_waves_per_simd
, max_sgprs_per_wave
);
6696 if (shader
->config
.num_sgprs
> max_sgprs
||
6697 shader
->config
.num_vgprs
> max_vgprs
) {
6698 fprintf(stderr
, "LLVM failed to compile a shader correctly: "
6699 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6700 shader
->config
.num_sgprs
, shader
->config
.num_vgprs
,
6701 max_sgprs
, max_vgprs
);
6703 /* Just terminate the process, because dependent
6704 * shaders can hang due to bad input data, but use
6705 * the env var to allow shader-db to work.
6707 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6712 /* Add the scratch offset to input SGPRs. */
6713 if (shader
->config
.scratch_bytes_per_wave
&& !is_merged_shader(shader
))
6714 shader
->info
.num_input_sgprs
+= 1; /* scratch byte offset */
6716 /* Calculate the number of fragment input VGPRs. */
6717 if (ctx
.type
== PIPE_SHADER_FRAGMENT
) {
6718 shader
->info
.num_input_vgprs
= 0;
6719 shader
->info
.face_vgpr_index
= -1;
6720 shader
->info
.ancillary_vgpr_index
= -1;
6722 if (G_0286CC_PERSP_SAMPLE_ENA(shader
->config
.spi_ps_input_addr
))
6723 shader
->info
.num_input_vgprs
+= 2;
6724 if (G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_addr
))
6725 shader
->info
.num_input_vgprs
+= 2;
6726 if (G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_addr
))
6727 shader
->info
.num_input_vgprs
+= 2;
6728 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader
->config
.spi_ps_input_addr
))
6729 shader
->info
.num_input_vgprs
+= 3;
6730 if (G_0286CC_LINEAR_SAMPLE_ENA(shader
->config
.spi_ps_input_addr
))
6731 shader
->info
.num_input_vgprs
+= 2;
6732 if (G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_addr
))
6733 shader
->info
.num_input_vgprs
+= 2;
6734 if (G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_addr
))
6735 shader
->info
.num_input_vgprs
+= 2;
6736 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader
->config
.spi_ps_input_addr
))
6737 shader
->info
.num_input_vgprs
+= 1;
6738 if (G_0286CC_POS_X_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
6739 shader
->info
.num_input_vgprs
+= 1;
6740 if (G_0286CC_POS_Y_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
6741 shader
->info
.num_input_vgprs
+= 1;
6742 if (G_0286CC_POS_Z_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
6743 shader
->info
.num_input_vgprs
+= 1;
6744 if (G_0286CC_POS_W_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
6745 shader
->info
.num_input_vgprs
+= 1;
6746 if (G_0286CC_FRONT_FACE_ENA(shader
->config
.spi_ps_input_addr
)) {
6747 shader
->info
.face_vgpr_index
= shader
->info
.num_input_vgprs
;
6748 shader
->info
.num_input_vgprs
+= 1;
6750 if (G_0286CC_ANCILLARY_ENA(shader
->config
.spi_ps_input_addr
)) {
6751 shader
->info
.ancillary_vgpr_index
= shader
->info
.num_input_vgprs
;
6752 shader
->info
.num_input_vgprs
+= 1;
6754 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader
->config
.spi_ps_input_addr
))
6755 shader
->info
.num_input_vgprs
+= 1;
6756 if (G_0286CC_POS_FIXED_PT_ENA(shader
->config
.spi_ps_input_addr
))
6757 shader
->info
.num_input_vgprs
+= 1;
6764 * Create, compile and return a shader part (prolog or epilog).
6766 * \param sscreen screen
6767 * \param list list of shader parts of the same category
6768 * \param type shader type
6769 * \param key shader part key
6770 * \param prolog whether the part being requested is a prolog
6771 * \param tm LLVM target machine
6772 * \param debug debug callback
6773 * \param build the callback responsible for building the main function
6774 * \return non-NULL on success
6776 static struct si_shader_part
*
6777 si_get_shader_part(struct si_screen
*sscreen
,
6778 struct si_shader_part
**list
,
6779 enum pipe_shader_type type
,
6781 union si_shader_part_key
*key
,
6782 LLVMTargetMachineRef tm
,
6783 struct pipe_debug_callback
*debug
,
6784 void (*build
)(struct si_shader_context
*,
6785 union si_shader_part_key
*),
6788 struct si_shader_part
*result
;
6790 mtx_lock(&sscreen
->shader_parts_mutex
);
6792 /* Find existing. */
6793 for (result
= *list
; result
; result
= result
->next
) {
6794 if (memcmp(&result
->key
, key
, sizeof(*key
)) == 0) {
6795 mtx_unlock(&sscreen
->shader_parts_mutex
);
6800 /* Compile a new one. */
6801 result
= CALLOC_STRUCT(si_shader_part
);
6804 struct si_shader shader
= {};
6805 struct si_shader_context ctx
;
6807 si_init_shader_ctx(&ctx
, sscreen
, tm
);
6808 ctx
.shader
= &shader
;
6812 case PIPE_SHADER_VERTEX
:
6813 shader
.key
.as_ls
= key
->vs_prolog
.as_ls
;
6814 shader
.key
.as_es
= key
->vs_prolog
.as_es
;
6816 case PIPE_SHADER_TESS_CTRL
:
6818 shader
.key
.part
.tcs
.epilog
= key
->tcs_epilog
.states
;
6820 case PIPE_SHADER_GEOMETRY
:
6823 case PIPE_SHADER_FRAGMENT
:
6825 shader
.key
.part
.ps
.prolog
= key
->ps_prolog
.states
;
6827 shader
.key
.part
.ps
.epilog
= key
->ps_epilog
.states
;
6830 unreachable("bad shader part");
6836 si_llvm_optimize_module(&ctx
);
6838 if (si_compile_llvm(sscreen
, &result
->binary
, &result
->config
, tm
,
6839 ctx
.ac
.module
, debug
, ctx
.type
, name
)) {
6845 result
->next
= *list
;
6849 si_llvm_dispose(&ctx
);
6850 mtx_unlock(&sscreen
->shader_parts_mutex
);
6854 static LLVMValueRef
si_prolog_get_rw_buffers(struct si_shader_context
*ctx
)
6856 LLVMValueRef ptr
[2], list
;
6857 bool is_merged_shader
=
6858 ctx
->screen
->info
.chip_class
>= GFX9
&&
6859 (ctx
->type
== PIPE_SHADER_TESS_CTRL
||
6860 ctx
->type
== PIPE_SHADER_GEOMETRY
||
6861 ctx
->shader
->key
.as_ls
|| ctx
->shader
->key
.as_es
);
6863 /* Get the pointer to rw buffers. */
6864 ptr
[0] = LLVMGetParam(ctx
->main_fn
, (is_merged_shader
? 8 : 0) + SI_SGPR_RW_BUFFERS
);
6865 ptr
[1] = LLVMGetParam(ctx
->main_fn
, (is_merged_shader
? 8 : 0) + SI_SGPR_RW_BUFFERS_HI
);
6866 list
= lp_build_gather_values(&ctx
->gallivm
, ptr
, 2);
6867 list
= LLVMBuildBitCast(ctx
->ac
.builder
, list
, ctx
->i64
, "");
6868 list
= LLVMBuildIntToPtr(ctx
->ac
.builder
, list
,
6869 si_const_array(ctx
->v4i32
, SI_NUM_RW_BUFFERS
), "");
6874 * Build the vertex shader prolog function.
6876 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6877 * All inputs are returned unmodified. The vertex load indices are
6878 * stored after them, which will be used by the API VS for fetching inputs.
6880 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6885 * (VertexID + BaseVertex),
6886 * (InstanceID + StartInstance),
6887 * (InstanceID / 2 + StartInstance)
6889 static void si_build_vs_prolog_function(struct si_shader_context
*ctx
,
6890 union si_shader_part_key
*key
)
6892 struct si_function_info fninfo
;
6893 LLVMTypeRef
*returns
;
6894 LLVMValueRef ret
, func
;
6896 unsigned first_vs_vgpr
= key
->vs_prolog
.num_merged_next_stage_vgprs
;
6897 unsigned num_input_vgprs
= key
->vs_prolog
.num_merged_next_stage_vgprs
+ 4;
6898 LLVMValueRef input_vgprs
[9];
6899 unsigned num_all_input_regs
= key
->vs_prolog
.num_input_sgprs
+
6901 unsigned user_sgpr_base
= key
->vs_prolog
.num_merged_next_stage_vgprs
? 8 : 0;
6903 si_init_function_info(&fninfo
);
6905 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6906 returns
= alloca((num_all_input_regs
+ key
->vs_prolog
.last_input
+ 1) *
6907 sizeof(LLVMTypeRef
));
6910 /* Declare input and output SGPRs. */
6911 for (i
= 0; i
< key
->vs_prolog
.num_input_sgprs
; i
++) {
6912 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
6913 returns
[num_returns
++] = ctx
->i32
;
6916 /* Preloaded VGPRs (outputs must be floats) */
6917 for (i
= 0; i
< num_input_vgprs
; i
++) {
6918 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &input_vgprs
[i
]);
6919 returns
[num_returns
++] = ctx
->f32
;
6922 /* Vertex load indices. */
6923 for (i
= 0; i
<= key
->vs_prolog
.last_input
; i
++)
6924 returns
[num_returns
++] = ctx
->f32
;
6926 /* Create the function. */
6927 si_create_function(ctx
, "vs_prolog", returns
, num_returns
, &fninfo
, 0);
6928 func
= ctx
->main_fn
;
6930 if (key
->vs_prolog
.num_merged_next_stage_vgprs
) {
6931 if (!key
->vs_prolog
.is_monolithic
)
6932 si_init_exec_from_input(ctx
, 3, 0);
6934 if (key
->vs_prolog
.as_ls
&&
6935 ctx
->screen
->has_ls_vgpr_init_bug
) {
6936 /* If there are no HS threads, SPI loads the LS VGPRs
6937 * starting at VGPR 0. Shift them back to where they
6940 LLVMValueRef has_hs_threads
=
6941 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
,
6942 unpack_param(ctx
, 3, 8, 8),
6945 for (i
= 4; i
> 0; --i
) {
6946 input_vgprs
[i
+ 1] =
6947 LLVMBuildSelect(ctx
->ac
.builder
, has_hs_threads
,
6949 input_vgprs
[i
- 1], "");
6954 ctx
->abi
.vertex_id
= input_vgprs
[first_vs_vgpr
];
6955 ctx
->abi
.instance_id
= input_vgprs
[first_vs_vgpr
+ (key
->vs_prolog
.as_ls
? 2 : 1)];
6957 /* Copy inputs to outputs. This should be no-op, as the registers match,
6958 * but it will prevent the compiler from overwriting them unintentionally.
6960 ret
= ctx
->return_value
;
6961 for (i
= 0; i
< key
->vs_prolog
.num_input_sgprs
; i
++) {
6962 LLVMValueRef p
= LLVMGetParam(func
, i
);
6963 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, p
, i
, "");
6965 for (i
= 0; i
< num_input_vgprs
; i
++) {
6966 LLVMValueRef p
= input_vgprs
[i
];
6967 p
= ac_to_float(&ctx
->ac
, p
);
6968 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, p
,
6969 key
->vs_prolog
.num_input_sgprs
+ i
, "");
6972 /* Compute vertex load indices from instance divisors. */
6973 LLVMValueRef instance_divisor_constbuf
= NULL
;
6975 if (key
->vs_prolog
.states
.instance_divisor_is_fetched
) {
6976 LLVMValueRef list
= si_prolog_get_rw_buffers(ctx
);
6977 LLVMValueRef buf_index
=
6978 LLVMConstInt(ctx
->i32
, SI_VS_CONST_INSTANCE_DIVISORS
, 0);
6979 instance_divisor_constbuf
=
6980 ac_build_load_to_sgpr(&ctx
->ac
, list
, buf_index
);
6983 for (i
= 0; i
<= key
->vs_prolog
.last_input
; i
++) {
6984 bool divisor_is_one
=
6985 key
->vs_prolog
.states
.instance_divisor_is_one
& (1u << i
);
6986 bool divisor_is_fetched
=
6987 key
->vs_prolog
.states
.instance_divisor_is_fetched
& (1u << i
);
6990 if (divisor_is_one
|| divisor_is_fetched
) {
6991 LLVMValueRef divisor
= ctx
->i32_1
;
6993 if (divisor_is_fetched
) {
6994 divisor
= buffer_load_const(ctx
, instance_divisor_constbuf
,
6995 LLVMConstInt(ctx
->i32
, i
* 4, 0));
6996 divisor
= ac_to_integer(&ctx
->ac
, divisor
);
6999 /* InstanceID / Divisor + StartInstance */
7000 index
= get_instance_index_for_fetch(ctx
,
7002 SI_SGPR_START_INSTANCE
,
7005 /* VertexID + BaseVertex */
7006 index
= LLVMBuildAdd(ctx
->ac
.builder
,
7008 LLVMGetParam(func
, user_sgpr_base
+
7009 SI_SGPR_BASE_VERTEX
), "");
7012 index
= ac_to_float(&ctx
->ac
, index
);
7013 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, index
,
7014 fninfo
.num_params
+ i
, "");
7017 si_llvm_build_ret(ctx
, ret
);
7020 static bool si_get_vs_prolog(struct si_screen
*sscreen
,
7021 LLVMTargetMachineRef tm
,
7022 struct si_shader
*shader
,
7023 struct pipe_debug_callback
*debug
,
7024 struct si_shader
*main_part
,
7025 const struct si_vs_prolog_bits
*key
)
7027 struct si_shader_selector
*vs
= main_part
->selector
;
7029 if (!si_vs_needs_prolog(vs
, key
))
7032 /* Get the prolog. */
7033 union si_shader_part_key prolog_key
;
7034 si_get_vs_prolog_key(&vs
->info
, main_part
->info
.num_input_sgprs
,
7035 key
, shader
, &prolog_key
);
7038 si_get_shader_part(sscreen
, &sscreen
->vs_prologs
,
7039 PIPE_SHADER_VERTEX
, true, &prolog_key
, tm
,
7040 debug
, si_build_vs_prolog_function
,
7041 "Vertex Shader Prolog");
7042 return shader
->prolog
!= NULL
;
7046 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7048 static bool si_shader_select_vs_parts(struct si_screen
*sscreen
,
7049 LLVMTargetMachineRef tm
,
7050 struct si_shader
*shader
,
7051 struct pipe_debug_callback
*debug
)
7053 return si_get_vs_prolog(sscreen
, tm
, shader
, debug
, shader
,
7054 &shader
->key
.part
.vs
.prolog
);
7058 * Compile the TCS epilog function. This writes tesselation factors to memory
7059 * based on the output primitive type of the tesselator (determined by TES).
7061 static void si_build_tcs_epilog_function(struct si_shader_context
*ctx
,
7062 union si_shader_part_key
*key
)
7064 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
7065 struct si_function_info fninfo
;
7068 si_init_function_info(&fninfo
);
7070 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
7071 add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7072 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7073 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* wave info */
7074 ctx
->param_tcs_factor_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7075 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7076 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7077 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7078 add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7079 add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7080 add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7081 add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7082 add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7083 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7084 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7085 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7086 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7087 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7088 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7089 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7090 ctx
->param_tcs_offchip_addr_base64k
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7091 ctx
->param_tcs_factor_addr_base64k
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7093 add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7094 add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7095 add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7096 add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7097 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7098 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7099 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7100 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7101 ctx
->param_tcs_offchip_addr_base64k
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7102 ctx
->param_tcs_factor_addr_base64k
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7103 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7104 ctx
->param_tcs_factor_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7107 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* VGPR gap */
7108 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* VGPR gap */
7109 unsigned tess_factors_idx
=
7110 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* patch index within the wave (REL_PATCH_ID) */
7111 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* invocation ID within the patch */
7112 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* LDS offset where tess factors should be loaded from */
7114 for (unsigned i
= 0; i
< 6; i
++)
7115 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* tess factors */
7117 /* Create the function. */
7118 si_create_function(ctx
, "tcs_epilog", NULL
, 0, &fninfo
,
7119 ctx
->screen
->info
.chip_class
>= CIK
? 128 : 64);
7120 ac_declare_lds_as_pointer(&ctx
->ac
);
7121 func
= ctx
->main_fn
;
7123 LLVMValueRef invoc0_tess_factors
[6];
7124 for (unsigned i
= 0; i
< 6; i
++)
7125 invoc0_tess_factors
[i
] = LLVMGetParam(func
, tess_factors_idx
+ 3 + i
);
7127 si_write_tess_factors(bld_base
,
7128 LLVMGetParam(func
, tess_factors_idx
),
7129 LLVMGetParam(func
, tess_factors_idx
+ 1),
7130 LLVMGetParam(func
, tess_factors_idx
+ 2),
7131 invoc0_tess_factors
, invoc0_tess_factors
+ 4);
7133 LLVMBuildRetVoid(ctx
->ac
.builder
);
7137 * Select and compile (or reuse) TCS parts (epilog).
7139 static bool si_shader_select_tcs_parts(struct si_screen
*sscreen
,
7140 LLVMTargetMachineRef tm
,
7141 struct si_shader
*shader
,
7142 struct pipe_debug_callback
*debug
)
7144 if (sscreen
->info
.chip_class
>= GFX9
) {
7145 struct si_shader
*ls_main_part
=
7146 shader
->key
.part
.tcs
.ls
->main_shader_part_ls
;
7148 if (!si_get_vs_prolog(sscreen
, tm
, shader
, debug
, ls_main_part
,
7149 &shader
->key
.part
.tcs
.ls_prolog
))
7152 shader
->previous_stage
= ls_main_part
;
7155 /* Get the epilog. */
7156 union si_shader_part_key epilog_key
;
7157 memset(&epilog_key
, 0, sizeof(epilog_key
));
7158 epilog_key
.tcs_epilog
.states
= shader
->key
.part
.tcs
.epilog
;
7160 shader
->epilog
= si_get_shader_part(sscreen
, &sscreen
->tcs_epilogs
,
7161 PIPE_SHADER_TESS_CTRL
, false,
7162 &epilog_key
, tm
, debug
,
7163 si_build_tcs_epilog_function
,
7164 "Tessellation Control Shader Epilog");
7165 return shader
->epilog
!= NULL
;
7169 * Select and compile (or reuse) GS parts (prolog).
7171 static bool si_shader_select_gs_parts(struct si_screen
*sscreen
,
7172 LLVMTargetMachineRef tm
,
7173 struct si_shader
*shader
,
7174 struct pipe_debug_callback
*debug
)
7176 if (sscreen
->info
.chip_class
>= GFX9
) {
7177 struct si_shader
*es_main_part
=
7178 shader
->key
.part
.gs
.es
->main_shader_part_es
;
7180 if (shader
->key
.part
.gs
.es
->type
== PIPE_SHADER_VERTEX
&&
7181 !si_get_vs_prolog(sscreen
, tm
, shader
, debug
, es_main_part
,
7182 &shader
->key
.part
.gs
.vs_prolog
))
7185 shader
->previous_stage
= es_main_part
;
7188 if (!shader
->key
.part
.gs
.prolog
.tri_strip_adj_fix
)
7191 union si_shader_part_key prolog_key
;
7192 memset(&prolog_key
, 0, sizeof(prolog_key
));
7193 prolog_key
.gs_prolog
.states
= shader
->key
.part
.gs
.prolog
;
7195 shader
->prolog2
= si_get_shader_part(sscreen
, &sscreen
->gs_prologs
,
7196 PIPE_SHADER_GEOMETRY
, true,
7197 &prolog_key
, tm
, debug
,
7198 si_build_gs_prolog_function
,
7199 "Geometry Shader Prolog");
7200 return shader
->prolog2
!= NULL
;
7204 * Build the pixel shader prolog function. This handles:
7205 * - two-side color selection and interpolation
7206 * - overriding interpolation parameters for the API PS
7207 * - polygon stippling
7209 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7210 * overriden by other states. (e.g. per-sample interpolation)
7211 * Interpolated colors are stored after the preloaded VGPRs.
7213 static void si_build_ps_prolog_function(struct si_shader_context
*ctx
,
7214 union si_shader_part_key
*key
)
7216 struct si_function_info fninfo
;
7217 LLVMValueRef ret
, func
;
7218 int num_returns
, i
, num_color_channels
;
7220 assert(si_need_ps_prolog(key
));
7222 si_init_function_info(&fninfo
);
7224 /* Declare inputs. */
7225 for (i
= 0; i
< key
->ps_prolog
.num_input_sgprs
; i
++)
7226 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7228 for (i
= 0; i
< key
->ps_prolog
.num_input_vgprs
; i
++)
7229 add_arg(&fninfo
, ARG_VGPR
, ctx
->f32
);
7231 /* Declare outputs (same as inputs + add colors if needed) */
7232 num_returns
= fninfo
.num_params
;
7233 num_color_channels
= util_bitcount(key
->ps_prolog
.colors_read
);
7234 for (i
= 0; i
< num_color_channels
; i
++)
7235 fninfo
.types
[num_returns
++] = ctx
->f32
;
7237 /* Create the function. */
7238 si_create_function(ctx
, "ps_prolog", fninfo
.types
, num_returns
,
7240 func
= ctx
->main_fn
;
7242 /* Copy inputs to outputs. This should be no-op, as the registers match,
7243 * but it will prevent the compiler from overwriting them unintentionally.
7245 ret
= ctx
->return_value
;
7246 for (i
= 0; i
< fninfo
.num_params
; i
++) {
7247 LLVMValueRef p
= LLVMGetParam(func
, i
);
7248 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, p
, i
, "");
7251 /* Polygon stippling. */
7252 if (key
->ps_prolog
.states
.poly_stipple
) {
7253 /* POS_FIXED_PT is always last. */
7254 unsigned pos
= key
->ps_prolog
.num_input_sgprs
+
7255 key
->ps_prolog
.num_input_vgprs
- 1;
7256 LLVMValueRef list
= si_prolog_get_rw_buffers(ctx
);
7258 si_llvm_emit_polygon_stipple(ctx
, list
, pos
);
7261 if (key
->ps_prolog
.states
.bc_optimize_for_persp
||
7262 key
->ps_prolog
.states
.bc_optimize_for_linear
) {
7263 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7264 LLVMValueRef center
[2], centroid
[2], tmp
, bc_optimize
;
7266 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7267 * The hw doesn't compute CENTROID if the whole wave only
7268 * contains fully-covered quads.
7270 * PRIM_MASK is after user SGPRs.
7272 bc_optimize
= LLVMGetParam(func
, SI_PS_NUM_USER_SGPR
);
7273 bc_optimize
= LLVMBuildLShr(ctx
->ac
.builder
, bc_optimize
,
7274 LLVMConstInt(ctx
->i32
, 31, 0), "");
7275 bc_optimize
= LLVMBuildTrunc(ctx
->ac
.builder
, bc_optimize
,
7278 if (key
->ps_prolog
.states
.bc_optimize_for_persp
) {
7279 /* Read PERSP_CENTER. */
7280 for (i
= 0; i
< 2; i
++)
7281 center
[i
] = LLVMGetParam(func
, base
+ 2 + i
);
7282 /* Read PERSP_CENTROID. */
7283 for (i
= 0; i
< 2; i
++)
7284 centroid
[i
] = LLVMGetParam(func
, base
+ 4 + i
);
7285 /* Select PERSP_CENTROID. */
7286 for (i
= 0; i
< 2; i
++) {
7287 tmp
= LLVMBuildSelect(ctx
->ac
.builder
, bc_optimize
,
7288 center
[i
], centroid
[i
], "");
7289 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7290 tmp
, base
+ 4 + i
, "");
7293 if (key
->ps_prolog
.states
.bc_optimize_for_linear
) {
7294 /* Read LINEAR_CENTER. */
7295 for (i
= 0; i
< 2; i
++)
7296 center
[i
] = LLVMGetParam(func
, base
+ 8 + i
);
7297 /* Read LINEAR_CENTROID. */
7298 for (i
= 0; i
< 2; i
++)
7299 centroid
[i
] = LLVMGetParam(func
, base
+ 10 + i
);
7300 /* Select LINEAR_CENTROID. */
7301 for (i
= 0; i
< 2; i
++) {
7302 tmp
= LLVMBuildSelect(ctx
->ac
.builder
, bc_optimize
,
7303 center
[i
], centroid
[i
], "");
7304 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7305 tmp
, base
+ 10 + i
, "");
7310 /* Force per-sample interpolation. */
7311 if (key
->ps_prolog
.states
.force_persp_sample_interp
) {
7312 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7313 LLVMValueRef persp_sample
[2];
7315 /* Read PERSP_SAMPLE. */
7316 for (i
= 0; i
< 2; i
++)
7317 persp_sample
[i
] = LLVMGetParam(func
, base
+ i
);
7318 /* Overwrite PERSP_CENTER. */
7319 for (i
= 0; i
< 2; i
++)
7320 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7321 persp_sample
[i
], base
+ 2 + i
, "");
7322 /* Overwrite PERSP_CENTROID. */
7323 for (i
= 0; i
< 2; i
++)
7324 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7325 persp_sample
[i
], base
+ 4 + i
, "");
7327 if (key
->ps_prolog
.states
.force_linear_sample_interp
) {
7328 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7329 LLVMValueRef linear_sample
[2];
7331 /* Read LINEAR_SAMPLE. */
7332 for (i
= 0; i
< 2; i
++)
7333 linear_sample
[i
] = LLVMGetParam(func
, base
+ 6 + i
);
7334 /* Overwrite LINEAR_CENTER. */
7335 for (i
= 0; i
< 2; i
++)
7336 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7337 linear_sample
[i
], base
+ 8 + i
, "");
7338 /* Overwrite LINEAR_CENTROID. */
7339 for (i
= 0; i
< 2; i
++)
7340 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7341 linear_sample
[i
], base
+ 10 + i
, "");
7344 /* Force center interpolation. */
7345 if (key
->ps_prolog
.states
.force_persp_center_interp
) {
7346 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7347 LLVMValueRef persp_center
[2];
7349 /* Read PERSP_CENTER. */
7350 for (i
= 0; i
< 2; i
++)
7351 persp_center
[i
] = LLVMGetParam(func
, base
+ 2 + i
);
7352 /* Overwrite PERSP_SAMPLE. */
7353 for (i
= 0; i
< 2; i
++)
7354 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7355 persp_center
[i
], base
+ i
, "");
7356 /* Overwrite PERSP_CENTROID. */
7357 for (i
= 0; i
< 2; i
++)
7358 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7359 persp_center
[i
], base
+ 4 + i
, "");
7361 if (key
->ps_prolog
.states
.force_linear_center_interp
) {
7362 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7363 LLVMValueRef linear_center
[2];
7365 /* Read LINEAR_CENTER. */
7366 for (i
= 0; i
< 2; i
++)
7367 linear_center
[i
] = LLVMGetParam(func
, base
+ 8 + i
);
7368 /* Overwrite LINEAR_SAMPLE. */
7369 for (i
= 0; i
< 2; i
++)
7370 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7371 linear_center
[i
], base
+ 6 + i
, "");
7372 /* Overwrite LINEAR_CENTROID. */
7373 for (i
= 0; i
< 2; i
++)
7374 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7375 linear_center
[i
], base
+ 10 + i
, "");
7378 /* Interpolate colors. */
7379 unsigned color_out_idx
= 0;
7380 for (i
= 0; i
< 2; i
++) {
7381 unsigned writemask
= (key
->ps_prolog
.colors_read
>> (i
* 4)) & 0xf;
7382 unsigned face_vgpr
= key
->ps_prolog
.num_input_sgprs
+
7383 key
->ps_prolog
.face_vgpr_index
;
7384 LLVMValueRef interp
[2], color
[4];
7385 LLVMValueRef interp_ij
= NULL
, prim_mask
= NULL
, face
= NULL
;
7390 /* If the interpolation qualifier is not CONSTANT (-1). */
7391 if (key
->ps_prolog
.color_interp_vgpr_index
[i
] != -1) {
7392 unsigned interp_vgpr
= key
->ps_prolog
.num_input_sgprs
+
7393 key
->ps_prolog
.color_interp_vgpr_index
[i
];
7395 /* Get the (i,j) updated by bc_optimize handling. */
7396 interp
[0] = LLVMBuildExtractValue(ctx
->ac
.builder
, ret
,
7398 interp
[1] = LLVMBuildExtractValue(ctx
->ac
.builder
, ret
,
7399 interp_vgpr
+ 1, "");
7400 interp_ij
= lp_build_gather_values(&ctx
->gallivm
, interp
, 2);
7403 /* Use the absolute location of the input. */
7404 prim_mask
= LLVMGetParam(func
, SI_PS_NUM_USER_SGPR
);
7406 if (key
->ps_prolog
.states
.color_two_side
) {
7407 face
= LLVMGetParam(func
, face_vgpr
);
7408 face
= ac_to_integer(&ctx
->ac
, face
);
7411 interp_fs_input(ctx
,
7412 key
->ps_prolog
.color_attr_index
[i
],
7413 TGSI_SEMANTIC_COLOR
, i
,
7414 key
->ps_prolog
.num_interp_inputs
,
7415 key
->ps_prolog
.colors_read
, interp_ij
,
7416 prim_mask
, face
, color
);
7419 unsigned chan
= u_bit_scan(&writemask
);
7420 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, color
[chan
],
7421 fninfo
.num_params
+ color_out_idx
++, "");
7425 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7428 * "When per-sample shading is active due to the use of a fragment
7429 * input qualified by sample or due to the use of the gl_SampleID
7430 * or gl_SamplePosition variables, only the bit for the current
7431 * sample is set in gl_SampleMaskIn. When state specifies multiple
7432 * fragment shader invocations for a given fragment, the sample
7433 * mask for any single fragment shader invocation may specify a
7434 * subset of the covered samples for the fragment. In this case,
7435 * the bit corresponding to each covered sample will be set in
7436 * exactly one fragment shader invocation."
7438 * The samplemask loaded by hardware is always the coverage of the
7439 * entire pixel/fragment, so mask bits out based on the sample ID.
7441 if (key
->ps_prolog
.states
.samplemask_log_ps_iter
) {
7442 /* The bit pattern matches that used by fixed function fragment
7444 static const uint16_t ps_iter_masks
[] = {
7445 0xffff, /* not used */
7451 assert(key
->ps_prolog
.states
.samplemask_log_ps_iter
< ARRAY_SIZE(ps_iter_masks
));
7453 uint32_t ps_iter_mask
= ps_iter_masks
[key
->ps_prolog
.states
.samplemask_log_ps_iter
];
7454 unsigned ancillary_vgpr
= key
->ps_prolog
.num_input_sgprs
+
7455 key
->ps_prolog
.ancillary_vgpr_index
;
7456 LLVMValueRef sampleid
= unpack_param(ctx
, ancillary_vgpr
, 8, 4);
7457 LLVMValueRef samplemask
= LLVMGetParam(func
, ancillary_vgpr
+ 1);
7459 samplemask
= ac_to_integer(&ctx
->ac
, samplemask
);
7460 samplemask
= LLVMBuildAnd(
7463 LLVMBuildShl(ctx
->ac
.builder
,
7464 LLVMConstInt(ctx
->i32
, ps_iter_mask
, false),
7467 samplemask
= ac_to_float(&ctx
->ac
, samplemask
);
7469 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, samplemask
,
7470 ancillary_vgpr
+ 1, "");
7473 /* Tell LLVM to insert WQM instruction sequence when needed. */
7474 if (key
->ps_prolog
.wqm
) {
7475 LLVMAddTargetDependentFunctionAttr(func
,
7476 "amdgpu-ps-wqm-outputs", "");
7479 si_llvm_build_ret(ctx
, ret
);
7483 * Build the pixel shader epilog function. This handles everything that must be
7484 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7486 static void si_build_ps_epilog_function(struct si_shader_context
*ctx
,
7487 union si_shader_part_key
*key
)
7489 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
7490 struct si_function_info fninfo
;
7491 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
7493 struct si_ps_exports exp
= {};
7495 si_init_function_info(&fninfo
);
7497 /* Declare input SGPRs. */
7498 ctx
->param_rw_buffers
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7499 ctx
->param_bindless_samplers_and_images
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7500 ctx
->param_const_and_shader_buffers
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7501 ctx
->param_samplers_and_images
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i64
);
7502 add_arg_checked(&fninfo
, ARG_SGPR
, ctx
->f32
, SI_PARAM_ALPHA_REF
);
7504 /* Declare input VGPRs. */
7505 unsigned required_num_params
=
7506 fninfo
.num_sgpr_params
+
7507 util_bitcount(key
->ps_epilog
.colors_written
) * 4 +
7508 key
->ps_epilog
.writes_z
+
7509 key
->ps_epilog
.writes_stencil
+
7510 key
->ps_epilog
.writes_samplemask
;
7512 required_num_params
= MAX2(required_num_params
,
7513 fninfo
.num_sgpr_params
+ PS_EPILOG_SAMPLEMASK_MIN_LOC
+ 1);
7515 while (fninfo
.num_params
< required_num_params
)
7516 add_arg(&fninfo
, ARG_VGPR
, ctx
->f32
);
7518 /* Create the function. */
7519 si_create_function(ctx
, "ps_epilog", NULL
, 0, &fninfo
, 0);
7520 /* Disable elimination of unused inputs. */
7521 si_llvm_add_attribute(ctx
->main_fn
,
7522 "InitialPSInputAddr", 0xffffff);
7524 /* Process colors. */
7525 unsigned vgpr
= fninfo
.num_sgpr_params
;
7526 unsigned colors_written
= key
->ps_epilog
.colors_written
;
7527 int last_color_export
= -1;
7529 /* Find the last color export. */
7530 if (!key
->ps_epilog
.writes_z
&&
7531 !key
->ps_epilog
.writes_stencil
&&
7532 !key
->ps_epilog
.writes_samplemask
) {
7533 unsigned spi_format
= key
->ps_epilog
.states
.spi_shader_col_format
;
7535 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7536 if (colors_written
== 0x1 && key
->ps_epilog
.states
.last_cbuf
> 0) {
7537 /* Just set this if any of the colorbuffers are enabled. */
7539 ((1ull << (4 * (key
->ps_epilog
.states
.last_cbuf
+ 1))) - 1))
7540 last_color_export
= 0;
7542 for (i
= 0; i
< 8; i
++)
7543 if (colors_written
& (1 << i
) &&
7544 (spi_format
>> (i
* 4)) & 0xf)
7545 last_color_export
= i
;
7549 while (colors_written
) {
7550 LLVMValueRef color
[4];
7551 int mrt
= u_bit_scan(&colors_written
);
7553 for (i
= 0; i
< 4; i
++)
7554 color
[i
] = LLVMGetParam(ctx
->main_fn
, vgpr
++);
7556 si_export_mrt_color(bld_base
, color
, mrt
,
7557 fninfo
.num_params
- 1,
7558 mrt
== last_color_export
, &exp
);
7561 /* Process depth, stencil, samplemask. */
7562 if (key
->ps_epilog
.writes_z
)
7563 depth
= LLVMGetParam(ctx
->main_fn
, vgpr
++);
7564 if (key
->ps_epilog
.writes_stencil
)
7565 stencil
= LLVMGetParam(ctx
->main_fn
, vgpr
++);
7566 if (key
->ps_epilog
.writes_samplemask
)
7567 samplemask
= LLVMGetParam(ctx
->main_fn
, vgpr
++);
7569 if (depth
|| stencil
|| samplemask
)
7570 si_export_mrt_z(bld_base
, depth
, stencil
, samplemask
, &exp
);
7571 else if (last_color_export
== -1)
7572 si_export_null(bld_base
);
7575 si_emit_ps_exports(ctx
, &exp
);
7578 LLVMBuildRetVoid(ctx
->ac
.builder
);
7582 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7584 static bool si_shader_select_ps_parts(struct si_screen
*sscreen
,
7585 LLVMTargetMachineRef tm
,
7586 struct si_shader
*shader
,
7587 struct pipe_debug_callback
*debug
)
7589 union si_shader_part_key prolog_key
;
7590 union si_shader_part_key epilog_key
;
7592 /* Get the prolog. */
7593 si_get_ps_prolog_key(shader
, &prolog_key
, true);
7595 /* The prolog is a no-op if these aren't set. */
7596 if (si_need_ps_prolog(&prolog_key
)) {
7598 si_get_shader_part(sscreen
, &sscreen
->ps_prologs
,
7599 PIPE_SHADER_FRAGMENT
, true,
7600 &prolog_key
, tm
, debug
,
7601 si_build_ps_prolog_function
,
7602 "Fragment Shader Prolog");
7603 if (!shader
->prolog
)
7607 /* Get the epilog. */
7608 si_get_ps_epilog_key(shader
, &epilog_key
);
7611 si_get_shader_part(sscreen
, &sscreen
->ps_epilogs
,
7612 PIPE_SHADER_FRAGMENT
, false,
7613 &epilog_key
, tm
, debug
,
7614 si_build_ps_epilog_function
,
7615 "Fragment Shader Epilog");
7616 if (!shader
->epilog
)
7619 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7620 if (shader
->key
.part
.ps
.prolog
.poly_stipple
) {
7621 shader
->config
.spi_ps_input_ena
|= S_0286CC_POS_FIXED_PT_ENA(1);
7622 assert(G_0286CC_POS_FIXED_PT_ENA(shader
->config
.spi_ps_input_addr
));
7625 /* Set up the enable bits for per-sample shading if needed. */
7626 if (shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
&&
7627 (G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_ena
) ||
7628 G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7629 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTER_ENA
;
7630 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTROID_ENA
;
7631 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_SAMPLE_ENA(1);
7633 if (shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
&&
7634 (G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_ena
) ||
7635 G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7636 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTER_ENA
;
7637 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTROID_ENA
;
7638 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_SAMPLE_ENA(1);
7640 if (shader
->key
.part
.ps
.prolog
.force_persp_center_interp
&&
7641 (G_0286CC_PERSP_SAMPLE_ENA(shader
->config
.spi_ps_input_ena
) ||
7642 G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7643 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_SAMPLE_ENA
;
7644 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTROID_ENA
;
7645 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_CENTER_ENA(1);
7647 if (shader
->key
.part
.ps
.prolog
.force_linear_center_interp
&&
7648 (G_0286CC_LINEAR_SAMPLE_ENA(shader
->config
.spi_ps_input_ena
) ||
7649 G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7650 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_SAMPLE_ENA
;
7651 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTROID_ENA
;
7652 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_CENTER_ENA(1);
7655 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7656 if (G_0286CC_POS_W_FLOAT_ENA(shader
->config
.spi_ps_input_ena
) &&
7657 !(shader
->config
.spi_ps_input_ena
& 0xf)) {
7658 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_CENTER_ENA(1);
7659 assert(G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_addr
));
7662 /* At least one pair of interpolation weights must be enabled. */
7663 if (!(shader
->config
.spi_ps_input_ena
& 0x7f)) {
7664 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_CENTER_ENA(1);
7665 assert(G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_addr
));
7668 /* Samplemask fixup requires the sample ID. */
7669 if (shader
->key
.part
.ps
.prolog
.samplemask_log_ps_iter
) {
7670 shader
->config
.spi_ps_input_ena
|= S_0286CC_ANCILLARY_ENA(1);
7671 assert(G_0286CC_ANCILLARY_ENA(shader
->config
.spi_ps_input_addr
));
7674 /* The sample mask input is always enabled, because the API shader always
7675 * passes it through to the epilog. Disable it here if it's unused.
7677 if (!shader
->key
.part
.ps
.epilog
.poly_line_smoothing
&&
7678 !shader
->selector
->info
.reads_samplemask
)
7679 shader
->config
.spi_ps_input_ena
&= C_0286CC_SAMPLE_COVERAGE_ENA
;
7684 void si_multiwave_lds_size_workaround(struct si_screen
*sscreen
,
7687 /* SPI barrier management bug:
7688 * Make sure we have at least 4k of LDS in use to avoid the bug.
7689 * It applies to workgroup sizes of more than one wavefront.
7691 if (sscreen
->info
.family
== CHIP_BONAIRE
||
7692 sscreen
->info
.family
== CHIP_KABINI
||
7693 sscreen
->info
.family
== CHIP_MULLINS
)
7694 *lds_size
= MAX2(*lds_size
, 8);
7697 static void si_fix_resource_usage(struct si_screen
*sscreen
,
7698 struct si_shader
*shader
)
7700 unsigned min_sgprs
= shader
->info
.num_input_sgprs
+ 2; /* VCC */
7702 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
, min_sgprs
);
7704 if (shader
->selector
->type
== PIPE_SHADER_COMPUTE
&&
7705 si_get_max_workgroup_size(shader
) > 64) {
7706 si_multiwave_lds_size_workaround(sscreen
,
7707 &shader
->config
.lds_size
);
7711 int si_shader_create(struct si_screen
*sscreen
, LLVMTargetMachineRef tm
,
7712 struct si_shader
*shader
,
7713 struct pipe_debug_callback
*debug
)
7715 struct si_shader_selector
*sel
= shader
->selector
;
7716 struct si_shader
*mainp
= *si_get_main_shader_part(sel
, &shader
->key
);
7719 /* LS, ES, VS are compiled on demand if the main part hasn't been
7720 * compiled for that stage.
7722 * Vertex shaders are compiled on demand when a vertex fetch
7723 * workaround must be applied.
7725 if (shader
->is_monolithic
) {
7726 /* Monolithic shader (compiled as a whole, has many variants,
7727 * may take a long time to compile).
7729 r
= si_compile_tgsi_shader(sscreen
, tm
, shader
, true, debug
);
7733 /* The shader consists of several parts:
7735 * - the middle part is the user shader, it has 1 variant only
7736 * and it was compiled during the creation of the shader
7738 * - the prolog part is inserted at the beginning
7739 * - the epilog part is inserted at the end
7741 * The prolog and epilog have many (but simple) variants.
7743 * Starting with gfx9, geometry and tessellation control
7744 * shaders also contain the prolog and user shader parts of
7745 * the previous shader stage.
7751 /* Copy the compiled TGSI shader data over. */
7752 shader
->is_binary_shared
= true;
7753 shader
->binary
= mainp
->binary
;
7754 shader
->config
= mainp
->config
;
7755 shader
->info
.num_input_sgprs
= mainp
->info
.num_input_sgprs
;
7756 shader
->info
.num_input_vgprs
= mainp
->info
.num_input_vgprs
;
7757 shader
->info
.face_vgpr_index
= mainp
->info
.face_vgpr_index
;
7758 shader
->info
.ancillary_vgpr_index
= mainp
->info
.ancillary_vgpr_index
;
7759 memcpy(shader
->info
.vs_output_param_offset
,
7760 mainp
->info
.vs_output_param_offset
,
7761 sizeof(mainp
->info
.vs_output_param_offset
));
7762 shader
->info
.uses_instanceid
= mainp
->info
.uses_instanceid
;
7763 shader
->info
.nr_pos_exports
= mainp
->info
.nr_pos_exports
;
7764 shader
->info
.nr_param_exports
= mainp
->info
.nr_param_exports
;
7766 /* Select prologs and/or epilogs. */
7767 switch (sel
->type
) {
7768 case PIPE_SHADER_VERTEX
:
7769 if (!si_shader_select_vs_parts(sscreen
, tm
, shader
, debug
))
7772 case PIPE_SHADER_TESS_CTRL
:
7773 if (!si_shader_select_tcs_parts(sscreen
, tm
, shader
, debug
))
7776 case PIPE_SHADER_TESS_EVAL
:
7778 case PIPE_SHADER_GEOMETRY
:
7779 if (!si_shader_select_gs_parts(sscreen
, tm
, shader
, debug
))
7782 case PIPE_SHADER_FRAGMENT
:
7783 if (!si_shader_select_ps_parts(sscreen
, tm
, shader
, debug
))
7786 /* Make sure we have at least as many VGPRs as there
7787 * are allocated inputs.
7789 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
7790 shader
->info
.num_input_vgprs
);
7794 /* Update SGPR and VGPR counts. */
7795 if (shader
->prolog
) {
7796 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
7797 shader
->prolog
->config
.num_sgprs
);
7798 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
7799 shader
->prolog
->config
.num_vgprs
);
7801 if (shader
->previous_stage
) {
7802 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
7803 shader
->previous_stage
->config
.num_sgprs
);
7804 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
7805 shader
->previous_stage
->config
.num_vgprs
);
7806 shader
->config
.spilled_sgprs
=
7807 MAX2(shader
->config
.spilled_sgprs
,
7808 shader
->previous_stage
->config
.spilled_sgprs
);
7809 shader
->config
.spilled_vgprs
=
7810 MAX2(shader
->config
.spilled_vgprs
,
7811 shader
->previous_stage
->config
.spilled_vgprs
);
7812 shader
->config
.private_mem_vgprs
=
7813 MAX2(shader
->config
.private_mem_vgprs
,
7814 shader
->previous_stage
->config
.private_mem_vgprs
);
7815 shader
->config
.scratch_bytes_per_wave
=
7816 MAX2(shader
->config
.scratch_bytes_per_wave
,
7817 shader
->previous_stage
->config
.scratch_bytes_per_wave
);
7818 shader
->info
.uses_instanceid
|=
7819 shader
->previous_stage
->info
.uses_instanceid
;
7821 if (shader
->prolog2
) {
7822 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
7823 shader
->prolog2
->config
.num_sgprs
);
7824 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
7825 shader
->prolog2
->config
.num_vgprs
);
7827 if (shader
->epilog
) {
7828 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
7829 shader
->epilog
->config
.num_sgprs
);
7830 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
7831 shader
->epilog
->config
.num_vgprs
);
7835 si_fix_resource_usage(sscreen
, shader
);
7836 si_shader_dump(sscreen
, shader
, debug
, sel
->info
.processor
,
7840 r
= si_shader_binary_upload(sscreen
, shader
);
7842 fprintf(stderr
, "LLVM failed to upload shader\n");
7849 void si_shader_destroy(struct si_shader
*shader
)
7851 if (shader
->scratch_bo
)
7852 r600_resource_reference(&shader
->scratch_bo
, NULL
);
7854 r600_resource_reference(&shader
->bo
, NULL
);
7856 if (!shader
->is_binary_shared
)
7857 ac_shader_binary_clean(&shader
->binary
);
7859 free(shader
->shader_log
);