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radeonsi: remove 2 unused user SGPRs from merged TES-GS with 32-bit pointers
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "gallivm/lp_bld_const.h"
25 #include "gallivm/lp_bld_gather.h"
26 #include "gallivm/lp_bld_intr.h"
27 #include "gallivm/lp_bld_logic.h"
28 #include "gallivm/lp_bld_arit.h"
29 #include "gallivm/lp_bld_flow.h"
30 #include "gallivm/lp_bld_misc.h"
31 #include "util/u_memory.h"
32 #include "util/u_string.h"
33 #include "tgsi/tgsi_build.h"
34 #include "tgsi/tgsi_util.h"
35 #include "tgsi/tgsi_dump.h"
36
37 #include "ac_binary.h"
38 #include "ac_llvm_util.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41 #include "si_shader_internal.h"
42 #include "si_pipe.h"
43 #include "sid.h"
44
45 #include "compiler/nir/nir.h"
46
47 static const char *scratch_rsrc_dword0_symbol =
48 "SCRATCH_RSRC_DWORD0";
49
50 static const char *scratch_rsrc_dword1_symbol =
51 "SCRATCH_RSRC_DWORD1";
52
53 struct si_shader_output_values
54 {
55 LLVMValueRef values[4];
56 unsigned semantic_name;
57 unsigned semantic_index;
58 ubyte vertex_stream[4];
59 };
60
61 /**
62 * Used to collect types and other info about arguments of the LLVM function
63 * before the function is created.
64 */
65 struct si_function_info {
66 LLVMTypeRef types[100];
67 LLVMValueRef *assign[100];
68 unsigned num_sgpr_params;
69 unsigned num_params;
70 };
71
72 enum si_arg_regfile {
73 ARG_SGPR,
74 ARG_VGPR
75 };
76
77 static void si_init_shader_ctx(struct si_shader_context *ctx,
78 struct si_screen *sscreen,
79 LLVMTargetMachineRef tm);
80
81 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
82 struct lp_build_tgsi_context *bld_base,
83 struct lp_build_emit_data *emit_data);
84
85 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
86 FILE *f);
87
88 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
89 union si_shader_part_key *key);
90 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
91 union si_shader_part_key *key);
92 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
93 union si_shader_part_key *key);
94 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
95 union si_shader_part_key *key);
96
97 /* Ideally pass the sample mask input to the PS epilog as v14, which
98 * is its usual location, so that the shader doesn't have to add v_mov.
99 */
100 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
101
102 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
103 LLVMTypeRef type)
104 {
105 if (type == ctx->ac.i64 || type == ctx->ac.f64)
106 return true;
107
108 return false;
109 }
110
111 static bool is_merged_shader(struct si_shader *shader)
112 {
113 if (shader->selector->screen->info.chip_class <= VI)
114 return false;
115
116 return shader->key.as_ls ||
117 shader->key.as_es ||
118 shader->selector->type == PIPE_SHADER_TESS_CTRL ||
119 shader->selector->type == PIPE_SHADER_GEOMETRY;
120 }
121
122 static void si_init_function_info(struct si_function_info *fninfo)
123 {
124 fninfo->num_params = 0;
125 fninfo->num_sgpr_params = 0;
126 }
127
128 static unsigned add_arg_assign(struct si_function_info *fninfo,
129 enum si_arg_regfile regfile, LLVMTypeRef type,
130 LLVMValueRef *assign)
131 {
132 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
133
134 unsigned idx = fninfo->num_params++;
135 assert(idx < ARRAY_SIZE(fninfo->types));
136
137 if (regfile == ARG_SGPR)
138 fninfo->num_sgpr_params = fninfo->num_params;
139
140 fninfo->types[idx] = type;
141 fninfo->assign[idx] = assign;
142 return idx;
143 }
144
145 static unsigned add_arg(struct si_function_info *fninfo,
146 enum si_arg_regfile regfile, LLVMTypeRef type)
147 {
148 return add_arg_assign(fninfo, regfile, type, NULL);
149 }
150
151 static void add_arg_assign_checked(struct si_function_info *fninfo,
152 enum si_arg_regfile regfile, LLVMTypeRef type,
153 LLVMValueRef *assign, unsigned idx)
154 {
155 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
156 assert(actual == idx);
157 }
158
159 static void add_arg_checked(struct si_function_info *fninfo,
160 enum si_arg_regfile regfile, LLVMTypeRef type,
161 unsigned idx)
162 {
163 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
164 }
165
166 /**
167 * Returns a unique index for a per-patch semantic name and index. The index
168 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
169 * can be calculated.
170 */
171 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
172 {
173 switch (semantic_name) {
174 case TGSI_SEMANTIC_TESSOUTER:
175 return 0;
176 case TGSI_SEMANTIC_TESSINNER:
177 return 1;
178 case TGSI_SEMANTIC_PATCH:
179 assert(index < 30);
180 return 2 + index;
181
182 default:
183 assert(!"invalid semantic name");
184 return 0;
185 }
186 }
187
188 /**
189 * Returns a unique index for a semantic name and index. The index must be
190 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
191 * calculated.
192 */
193 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
194 {
195 switch (semantic_name) {
196 case TGSI_SEMANTIC_POSITION:
197 return 0;
198 case TGSI_SEMANTIC_GENERIC:
199 /* Since some shader stages use the the highest used IO index
200 * to determine the size to allocate for inputs/outputs
201 * (in LDS, tess and GS rings). GENERIC should be placed right
202 * after POSITION to make that size as small as possible.
203 */
204 if (index < SI_MAX_IO_GENERIC)
205 return 1 + index;
206
207 assert(!"invalid generic index");
208 return 0;
209 case TGSI_SEMANTIC_PSIZE:
210 return SI_MAX_IO_GENERIC + 1;
211 case TGSI_SEMANTIC_CLIPDIST:
212 assert(index <= 1);
213 return SI_MAX_IO_GENERIC + 2 + index;
214 case TGSI_SEMANTIC_FOG:
215 return SI_MAX_IO_GENERIC + 4;
216 case TGSI_SEMANTIC_LAYER:
217 return SI_MAX_IO_GENERIC + 5;
218 case TGSI_SEMANTIC_VIEWPORT_INDEX:
219 return SI_MAX_IO_GENERIC + 6;
220 case TGSI_SEMANTIC_PRIMID:
221 return SI_MAX_IO_GENERIC + 7;
222 case TGSI_SEMANTIC_COLOR: /* these alias */
223 case TGSI_SEMANTIC_BCOLOR:
224 assert(index < 2);
225 return SI_MAX_IO_GENERIC + 8 + index;
226 case TGSI_SEMANTIC_TEXCOORD:
227 assert(index < 8);
228 assert(SI_MAX_IO_GENERIC + 10 + index < 64);
229 return SI_MAX_IO_GENERIC + 10 + index;
230 default:
231 assert(!"invalid semantic name");
232 return 0;
233 }
234 }
235
236 /**
237 * Get the value of a shader input parameter and extract a bitfield.
238 */
239 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
240 LLVMValueRef value, unsigned rshift,
241 unsigned bitwidth)
242 {
243 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
244 value = ac_to_integer(&ctx->ac, value);
245
246 if (rshift)
247 value = LLVMBuildLShr(ctx->ac.builder, value,
248 LLVMConstInt(ctx->i32, rshift, 0), "");
249
250 if (rshift + bitwidth < 32) {
251 unsigned mask = (1 << bitwidth) - 1;
252 value = LLVMBuildAnd(ctx->ac.builder, value,
253 LLVMConstInt(ctx->i32, mask, 0), "");
254 }
255
256 return value;
257 }
258
259 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
260 unsigned param, unsigned rshift,
261 unsigned bitwidth)
262 {
263 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
264
265 return unpack_llvm_param(ctx, value, rshift, bitwidth);
266 }
267
268 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
269 {
270 switch (ctx->type) {
271 case PIPE_SHADER_TESS_CTRL:
272 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
273
274 case PIPE_SHADER_TESS_EVAL:
275 return LLVMGetParam(ctx->main_fn,
276 ctx->param_tes_rel_patch_id);
277
278 default:
279 assert(0);
280 return NULL;
281 }
282 }
283
284 /* Tessellation shaders pass outputs to the next shader using LDS.
285 *
286 * LS outputs = TCS inputs
287 * TCS outputs = TES inputs
288 *
289 * The LDS layout is:
290 * - TCS inputs for patch 0
291 * - TCS inputs for patch 1
292 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
293 * - ...
294 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
295 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
296 * - TCS outputs for patch 1
297 * - Per-patch TCS outputs for patch 1
298 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
299 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
300 * - ...
301 *
302 * All three shaders VS(LS), TCS, TES share the same LDS space.
303 */
304
305 static LLVMValueRef
306 get_tcs_in_patch_stride(struct si_shader_context *ctx)
307 {
308 return unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
309 }
310
311 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
312 {
313 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
314
315 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
316 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
317
318 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
319 }
320
321 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
322 {
323 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
324
325 return LLVMConstInt(ctx->i32, stride, 0);
326 }
327
328 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
329 {
330 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
331 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
332
333 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
334 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
335 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
336 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
337 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
338 num_patch_outputs * 4;
339 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
340 }
341
342 static LLVMValueRef
343 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
344 {
345 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
346 unpack_param(ctx,
347 ctx->param_tcs_out_lds_offsets,
348 0, 16),
349 4);
350 }
351
352 static LLVMValueRef
353 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
354 {
355 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
356 unpack_param(ctx,
357 ctx->param_tcs_out_lds_offsets,
358 16, 16),
359 4);
360 }
361
362 static LLVMValueRef
363 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
364 {
365 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
366 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
367
368 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
369 }
370
371 static LLVMValueRef
372 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
373 {
374 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
375 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
376 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
377
378 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
379 LLVMBuildMul(ctx->ac.builder, patch_stride,
380 rel_patch_id, ""),
381 "");
382 }
383
384 static LLVMValueRef
385 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
386 {
387 LLVMValueRef patch0_patch_data_offset =
388 get_tcs_out_patch0_patch_data_offset(ctx);
389 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
390 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
391
392 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
393 LLVMBuildMul(ctx->ac.builder, patch_stride,
394 rel_patch_id, ""),
395 "");
396 }
397
398 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
399 {
400 unsigned tcs_out_vertices =
401 ctx->shader->selector ?
402 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
403
404 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
405 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
406 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
407
408 return unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
409 }
410
411 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
412 {
413 unsigned stride;
414
415 switch (ctx->type) {
416 case PIPE_SHADER_VERTEX:
417 stride = util_last_bit64(ctx->shader->selector->outputs_written);
418 return LLVMConstInt(ctx->i32, stride * 4, 0);
419
420 case PIPE_SHADER_TESS_CTRL:
421 if (ctx->screen->info.chip_class >= GFX9 &&
422 ctx->shader->is_monolithic) {
423 stride = util_last_bit64(ctx->shader->key.part.tcs.ls->outputs_written);
424 return LLVMConstInt(ctx->i32, stride * 4, 0);
425 }
426 return unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
427
428 default:
429 assert(0);
430 return NULL;
431 }
432 }
433
434 static LLVMValueRef get_instance_index_for_fetch(
435 struct si_shader_context *ctx,
436 unsigned param_start_instance, LLVMValueRef divisor)
437 {
438 LLVMValueRef result = ctx->abi.instance_id;
439
440 /* The division must be done before START_INSTANCE is added. */
441 if (divisor != ctx->i32_1)
442 result = LLVMBuildUDiv(ctx->ac.builder, result, divisor, "");
443
444 return LLVMBuildAdd(ctx->ac.builder, result,
445 LLVMGetParam(ctx->main_fn, param_start_instance), "");
446 }
447
448 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
449 * to float. */
450 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
451 LLVMValueRef vec4,
452 unsigned double_index)
453 {
454 LLVMBuilderRef builder = ctx->ac.builder;
455 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->ac.context);
456 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
457 LLVMVectorType(f64, 2), "");
458 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
459 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
460 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
461 }
462
463 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
464 LLVMValueRef i32, unsigned index)
465 {
466 assert(index <= 1);
467
468 if (index == 1)
469 return LLVMBuildAShr(ctx->ac.builder, i32,
470 LLVMConstInt(ctx->i32, 16, 0), "");
471
472 return LLVMBuildSExt(ctx->ac.builder,
473 LLVMBuildTrunc(ctx->ac.builder, i32,
474 ctx->ac.i16, ""),
475 ctx->i32, "");
476 }
477
478 void si_llvm_load_input_vs(
479 struct si_shader_context *ctx,
480 unsigned input_index,
481 LLVMValueRef out[4])
482 {
483 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
484 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
485
486 if (vs_blit_property) {
487 LLVMValueRef vertex_id = ctx->abi.vertex_id;
488 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
489 LLVMIntULE, vertex_id,
490 ctx->i32_1, "");
491 /* Use LLVMIntNE, because we have 3 vertices and only
492 * the middle one should use y2.
493 */
494 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
495 LLVMIntNE, vertex_id,
496 ctx->i32_1, "");
497
498 if (input_index == 0) {
499 /* Position: */
500 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
501 ctx->param_vs_blit_inputs);
502 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
503 ctx->param_vs_blit_inputs + 1);
504
505 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
506 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
507 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
508 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
509
510 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
511 x1, x2, "");
512 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
513 y1, y2, "");
514
515 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
516 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
517 out[2] = LLVMGetParam(ctx->main_fn,
518 ctx->param_vs_blit_inputs + 2);
519 out[3] = ctx->ac.f32_1;
520 return;
521 }
522
523 /* Color or texture coordinates: */
524 assert(input_index == 1);
525
526 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
527 for (int i = 0; i < 4; i++) {
528 out[i] = LLVMGetParam(ctx->main_fn,
529 ctx->param_vs_blit_inputs + 3 + i);
530 }
531 } else {
532 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
533 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
534 ctx->param_vs_blit_inputs + 3);
535 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
536 ctx->param_vs_blit_inputs + 4);
537 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
538 ctx->param_vs_blit_inputs + 5);
539 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
540 ctx->param_vs_blit_inputs + 6);
541
542 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
543 x1, x2, "");
544 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
545 y1, y2, "");
546 out[2] = LLVMGetParam(ctx->main_fn,
547 ctx->param_vs_blit_inputs + 7);
548 out[3] = LLVMGetParam(ctx->main_fn,
549 ctx->param_vs_blit_inputs + 8);
550 }
551 return;
552 }
553
554 unsigned chan;
555 unsigned fix_fetch;
556 unsigned num_fetches;
557 unsigned fetch_stride;
558 unsigned num_channels;
559
560 LLVMValueRef t_list_ptr;
561 LLVMValueRef t_offset;
562 LLVMValueRef t_list;
563 LLVMValueRef vertex_index;
564 LLVMValueRef input[3];
565
566 /* Load the T list */
567 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
568
569 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
570
571 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
572
573 vertex_index = LLVMGetParam(ctx->main_fn,
574 ctx->param_vertex_index0 +
575 input_index);
576
577 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
578
579 /* Do multiple loads for special formats. */
580 switch (fix_fetch) {
581 case SI_FIX_FETCH_RGB_64_FLOAT:
582 num_fetches = 3; /* 3 2-dword loads */
583 fetch_stride = 8;
584 num_channels = 2;
585 break;
586 case SI_FIX_FETCH_RGBA_64_FLOAT:
587 num_fetches = 2; /* 2 4-dword loads */
588 fetch_stride = 16;
589 num_channels = 4;
590 break;
591 case SI_FIX_FETCH_RGB_8:
592 case SI_FIX_FETCH_RGB_8_INT:
593 num_fetches = 3;
594 fetch_stride = 1;
595 num_channels = 1;
596 break;
597 case SI_FIX_FETCH_RGB_16:
598 case SI_FIX_FETCH_RGB_16_INT:
599 num_fetches = 3;
600 fetch_stride = 2;
601 num_channels = 1;
602 break;
603 default:
604 num_fetches = 1;
605 fetch_stride = 0;
606 num_channels = util_last_bit(info->input_usage_mask[input_index]);
607 }
608
609 for (unsigned i = 0; i < num_fetches; i++) {
610 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
611
612 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
613 vertex_index, voffset,
614 num_channels, false, true);
615 input[i] = ac_build_expand_to_vec4(&ctx->ac, input[i], num_channels);
616 }
617
618 /* Break up the vec4 into individual components */
619 for (chan = 0; chan < 4; chan++) {
620 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
621 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
622 input[0], llvm_chan, "");
623 }
624
625 switch (fix_fetch) {
626 case SI_FIX_FETCH_A2_SNORM:
627 case SI_FIX_FETCH_A2_SSCALED:
628 case SI_FIX_FETCH_A2_SINT: {
629 /* The hardware returns an unsigned value; convert it to a
630 * signed one.
631 */
632 LLVMValueRef tmp = out[3];
633 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
634
635 /* First, recover the sign-extended signed integer value. */
636 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
637 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
638 else
639 tmp = ac_to_integer(&ctx->ac, tmp);
640
641 /* For the integer-like cases, do a natural sign extension.
642 *
643 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
644 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
645 * exponent.
646 */
647 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
648 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
649 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
650 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
651
652 /* Convert back to the right type. */
653 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
654 LLVMValueRef clamp;
655 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
656 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
657 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
658 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
659 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
660 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
661 }
662
663 out[3] = tmp;
664 break;
665 }
666 case SI_FIX_FETCH_RGBA_32_UNORM:
667 case SI_FIX_FETCH_RGBX_32_UNORM:
668 for (chan = 0; chan < 4; chan++) {
669 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
670 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
671 out[chan], ctx->f32, "");
672 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
673 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
674 }
675 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
676 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
677 out[3] = LLVMConstReal(ctx->f32, 1);
678 break;
679 case SI_FIX_FETCH_RGBA_32_SNORM:
680 case SI_FIX_FETCH_RGBX_32_SNORM:
681 case SI_FIX_FETCH_RGBA_32_FIXED:
682 case SI_FIX_FETCH_RGBX_32_FIXED: {
683 double scale;
684 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
685 scale = 1.0 / 0x10000;
686 else
687 scale = 1.0 / INT_MAX;
688
689 for (chan = 0; chan < 4; chan++) {
690 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
691 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
692 out[chan], ctx->f32, "");
693 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
694 LLVMConstReal(ctx->f32, scale), "");
695 }
696 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
697 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
698 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
699 out[3] = LLVMConstReal(ctx->f32, 1);
700 break;
701 }
702 case SI_FIX_FETCH_RGBA_32_USCALED:
703 for (chan = 0; chan < 4; chan++) {
704 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
705 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
706 out[chan], ctx->f32, "");
707 }
708 break;
709 case SI_FIX_FETCH_RGBA_32_SSCALED:
710 for (chan = 0; chan < 4; chan++) {
711 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
712 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
713 out[chan], ctx->f32, "");
714 }
715 break;
716 case SI_FIX_FETCH_RG_64_FLOAT:
717 for (chan = 0; chan < 2; chan++)
718 out[chan] = extract_double_to_float(ctx, input[0], chan);
719
720 out[2] = LLVMConstReal(ctx->f32, 0);
721 out[3] = LLVMConstReal(ctx->f32, 1);
722 break;
723 case SI_FIX_FETCH_RGB_64_FLOAT:
724 for (chan = 0; chan < 3; chan++)
725 out[chan] = extract_double_to_float(ctx, input[chan], 0);
726
727 out[3] = LLVMConstReal(ctx->f32, 1);
728 break;
729 case SI_FIX_FETCH_RGBA_64_FLOAT:
730 for (chan = 0; chan < 4; chan++) {
731 out[chan] = extract_double_to_float(ctx, input[chan / 2],
732 chan % 2);
733 }
734 break;
735 case SI_FIX_FETCH_RGB_8:
736 case SI_FIX_FETCH_RGB_8_INT:
737 case SI_FIX_FETCH_RGB_16:
738 case SI_FIX_FETCH_RGB_16_INT:
739 for (chan = 0; chan < 3; chan++) {
740 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
741 input[chan],
742 ctx->i32_0, "");
743 }
744 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
745 fix_fetch == SI_FIX_FETCH_RGB_16) {
746 out[3] = LLVMConstReal(ctx->f32, 1);
747 } else {
748 out[3] = ac_to_float(&ctx->ac, ctx->i32_1);
749 }
750 break;
751 }
752 }
753
754 static void declare_input_vs(
755 struct si_shader_context *ctx,
756 unsigned input_index,
757 const struct tgsi_full_declaration *decl,
758 LLVMValueRef out[4])
759 {
760 si_llvm_load_input_vs(ctx, input_index, out);
761 }
762
763 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
764 unsigned swizzle)
765 {
766 if (swizzle > 0)
767 return ctx->i32_0;
768
769 switch (ctx->type) {
770 case PIPE_SHADER_VERTEX:
771 return LLVMGetParam(ctx->main_fn,
772 ctx->param_vs_prim_id);
773 case PIPE_SHADER_TESS_CTRL:
774 return ctx->abi.tcs_patch_id;
775 case PIPE_SHADER_TESS_EVAL:
776 return ctx->abi.tes_patch_id;
777 case PIPE_SHADER_GEOMETRY:
778 return ctx->abi.gs_prim_id;
779 default:
780 assert(0);
781 return ctx->i32_0;
782 }
783 }
784
785 /**
786 * Return the value of tgsi_ind_register for indexing.
787 * This is the indirect index with the constant offset added to it.
788 */
789 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
790 const struct tgsi_ind_register *ind,
791 unsigned addr_mul,
792 int rel_index)
793 {
794 LLVMValueRef result;
795
796 if (ind->File == TGSI_FILE_ADDRESS) {
797 result = ctx->addrs[ind->Index][ind->Swizzle];
798 result = LLVMBuildLoad(ctx->ac.builder, result, "");
799 } else {
800 struct tgsi_full_src_register src = {};
801
802 src.Register.File = ind->File;
803 src.Register.Index = ind->Index;
804
805 /* Set the second index to 0 for constants. */
806 if (ind->File == TGSI_FILE_CONSTANT)
807 src.Register.Dimension = 1;
808
809 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
810 TGSI_TYPE_SIGNED,
811 ind->Swizzle);
812 result = ac_to_integer(&ctx->ac, result);
813 }
814
815 if (addr_mul != 1)
816 result = LLVMBuildMul(ctx->ac.builder, result,
817 LLVMConstInt(ctx->i32, addr_mul, 0), "");
818 result = LLVMBuildAdd(ctx->ac.builder, result,
819 LLVMConstInt(ctx->i32, rel_index, 0), "");
820 return result;
821 }
822
823 /**
824 * Like si_get_indirect_index, but restricts the return value to a (possibly
825 * undefined) value inside [0..num).
826 */
827 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
828 const struct tgsi_ind_register *ind,
829 int rel_index, unsigned num)
830 {
831 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
832
833 return si_llvm_bound_index(ctx, result, num);
834 }
835
836 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
837 LLVMValueRef vertex_dw_stride,
838 LLVMValueRef base_addr,
839 LLVMValueRef vertex_index,
840 LLVMValueRef param_index,
841 unsigned input_index,
842 ubyte *name,
843 ubyte *index,
844 bool is_patch)
845 {
846 if (vertex_dw_stride) {
847 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
848 LLVMBuildMul(ctx->ac.builder, vertex_index,
849 vertex_dw_stride, ""), "");
850 }
851
852 if (param_index) {
853 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
854 LLVMBuildMul(ctx->ac.builder, param_index,
855 LLVMConstInt(ctx->i32, 4, 0), ""), "");
856 }
857
858 int param = is_patch ?
859 si_shader_io_get_unique_index_patch(name[input_index],
860 index[input_index]) :
861 si_shader_io_get_unique_index(name[input_index],
862 index[input_index]);
863
864 /* Add the base address of the element. */
865 return LLVMBuildAdd(ctx->ac.builder, base_addr,
866 LLVMConstInt(ctx->i32, param * 4, 0), "");
867 }
868
869 /**
870 * Calculate a dword address given an input or output register and a stride.
871 */
872 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
873 const struct tgsi_full_dst_register *dst,
874 const struct tgsi_full_src_register *src,
875 LLVMValueRef vertex_dw_stride,
876 LLVMValueRef base_addr)
877 {
878 struct tgsi_shader_info *info = &ctx->shader->selector->info;
879 ubyte *name, *index, *array_first;
880 int input_index;
881 struct tgsi_full_dst_register reg;
882 LLVMValueRef vertex_index = NULL;
883 LLVMValueRef ind_index = NULL;
884
885 /* Set the register description. The address computation is the same
886 * for sources and destinations. */
887 if (src) {
888 reg.Register.File = src->Register.File;
889 reg.Register.Index = src->Register.Index;
890 reg.Register.Indirect = src->Register.Indirect;
891 reg.Register.Dimension = src->Register.Dimension;
892 reg.Indirect = src->Indirect;
893 reg.Dimension = src->Dimension;
894 reg.DimIndirect = src->DimIndirect;
895 } else
896 reg = *dst;
897
898 /* If the register is 2-dimensional (e.g. an array of vertices
899 * in a primitive), calculate the base address of the vertex. */
900 if (reg.Register.Dimension) {
901 if (reg.Dimension.Indirect)
902 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
903 1, reg.Dimension.Index);
904 else
905 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
906 }
907
908 /* Get information about the register. */
909 if (reg.Register.File == TGSI_FILE_INPUT) {
910 name = info->input_semantic_name;
911 index = info->input_semantic_index;
912 array_first = info->input_array_first;
913 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
914 name = info->output_semantic_name;
915 index = info->output_semantic_index;
916 array_first = info->output_array_first;
917 } else {
918 assert(0);
919 return NULL;
920 }
921
922 if (reg.Register.Indirect) {
923 /* Add the relative address of the element. */
924 if (reg.Indirect.ArrayID)
925 input_index = array_first[reg.Indirect.ArrayID];
926 else
927 input_index = reg.Register.Index;
928
929 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
930 1, reg.Register.Index - input_index);
931 } else {
932 input_index = reg.Register.Index;
933 }
934
935 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
936 base_addr, vertex_index,
937 ind_index, input_index,
938 name, index,
939 !reg.Register.Dimension);
940 }
941
942 /* The offchip buffer layout for TCS->TES is
943 *
944 * - attribute 0 of patch 0 vertex 0
945 * - attribute 0 of patch 0 vertex 1
946 * - attribute 0 of patch 0 vertex 2
947 * ...
948 * - attribute 0 of patch 1 vertex 0
949 * - attribute 0 of patch 1 vertex 1
950 * ...
951 * - attribute 1 of patch 0 vertex 0
952 * - attribute 1 of patch 0 vertex 1
953 * ...
954 * - per patch attribute 0 of patch 0
955 * - per patch attribute 0 of patch 1
956 * ...
957 *
958 * Note that every attribute has 4 components.
959 */
960 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
961 LLVMValueRef rel_patch_id,
962 LLVMValueRef vertex_index,
963 LLVMValueRef param_index)
964 {
965 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
966 LLVMValueRef param_stride, constant16;
967
968 vertices_per_patch = get_num_tcs_out_vertices(ctx);
969 num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
970 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
971 num_patches, "");
972
973 constant16 = LLVMConstInt(ctx->i32, 16, 0);
974 if (vertex_index) {
975 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
976 vertices_per_patch, "");
977
978 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
979 vertex_index, "");
980
981 param_stride = total_vertices;
982 } else {
983 base_addr = rel_patch_id;
984 param_stride = num_patches;
985 }
986
987 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
988 LLVMBuildMul(ctx->ac.builder, param_index,
989 param_stride, ""), "");
990
991 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
992
993 if (!vertex_index) {
994 LLVMValueRef patch_data_offset =
995 unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
996
997 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
998 patch_data_offset, "");
999 }
1000 return base_addr;
1001 }
1002
1003 /* This is a generic helper that can be shared by the NIR and TGSI backends */
1004 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
1005 struct si_shader_context *ctx,
1006 LLVMValueRef vertex_index,
1007 LLVMValueRef param_index,
1008 unsigned param_base,
1009 ubyte *name,
1010 ubyte *index,
1011 bool is_patch)
1012 {
1013 unsigned param_index_base;
1014
1015 param_index_base = is_patch ?
1016 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
1017 si_shader_io_get_unique_index(name[param_base], index[param_base]);
1018
1019 if (param_index) {
1020 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1021 LLVMConstInt(ctx->i32, param_index_base, 0),
1022 "");
1023 } else {
1024 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
1025 }
1026
1027 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
1028 vertex_index, param_index);
1029 }
1030
1031 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
1032 struct si_shader_context *ctx,
1033 const struct tgsi_full_dst_register *dst,
1034 const struct tgsi_full_src_register *src)
1035 {
1036 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1037 ubyte *name, *index, *array_first;
1038 struct tgsi_full_src_register reg;
1039 LLVMValueRef vertex_index = NULL;
1040 LLVMValueRef param_index = NULL;
1041 unsigned param_base;
1042
1043 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
1044
1045 if (reg.Register.Dimension) {
1046
1047 if (reg.Dimension.Indirect)
1048 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
1049 1, reg.Dimension.Index);
1050 else
1051 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
1052 }
1053
1054 /* Get information about the register. */
1055 if (reg.Register.File == TGSI_FILE_INPUT) {
1056 name = info->input_semantic_name;
1057 index = info->input_semantic_index;
1058 array_first = info->input_array_first;
1059 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1060 name = info->output_semantic_name;
1061 index = info->output_semantic_index;
1062 array_first = info->output_array_first;
1063 } else {
1064 assert(0);
1065 return NULL;
1066 }
1067
1068 if (reg.Register.Indirect) {
1069 if (reg.Indirect.ArrayID)
1070 param_base = array_first[reg.Indirect.ArrayID];
1071 else
1072 param_base = reg.Register.Index;
1073
1074 param_index = si_get_indirect_index(ctx, &reg.Indirect,
1075 1, reg.Register.Index - param_base);
1076
1077 } else {
1078 param_base = reg.Register.Index;
1079 }
1080
1081 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1082 param_index, param_base,
1083 name, index, !reg.Register.Dimension);
1084 }
1085
1086 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
1087 LLVMTypeRef type, unsigned swizzle,
1088 LLVMValueRef buffer, LLVMValueRef offset,
1089 LLVMValueRef base, bool can_speculate)
1090 {
1091 struct si_shader_context *ctx = si_shader_context(bld_base);
1092 LLVMValueRef value, value2;
1093 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
1094
1095 if (swizzle == ~0) {
1096 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1097 0, 1, 0, can_speculate, false);
1098
1099 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1100 }
1101
1102 if (!llvm_type_is_64bit(ctx, type)) {
1103 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1104 0, 1, 0, can_speculate, false);
1105
1106 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1107 return LLVMBuildExtractElement(ctx->ac.builder, value,
1108 LLVMConstInt(ctx->i32, swizzle, 0), "");
1109 }
1110
1111 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1112 swizzle * 4, 1, 0, can_speculate, false);
1113
1114 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1115 swizzle * 4 + 4, 1, 0, can_speculate, false);
1116
1117 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1118 }
1119
1120 /**
1121 * Load from LDS.
1122 *
1123 * \param type output value type
1124 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1125 * \param dw_addr address in dwords
1126 */
1127 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1128 LLVMTypeRef type, unsigned swizzle,
1129 LLVMValueRef dw_addr)
1130 {
1131 struct si_shader_context *ctx = si_shader_context(bld_base);
1132 LLVMValueRef value;
1133
1134 if (swizzle == ~0) {
1135 LLVMValueRef values[TGSI_NUM_CHANNELS];
1136
1137 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1138 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1139
1140 return lp_build_gather_values(&ctx->gallivm, values,
1141 TGSI_NUM_CHANNELS);
1142 }
1143
1144 /* Split 64-bit loads. */
1145 if (llvm_type_is_64bit(ctx, type)) {
1146 LLVMValueRef lo, hi;
1147
1148 lo = lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1149 hi = lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1150 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1151 }
1152
1153 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1154 LLVMConstInt(ctx->i32, swizzle, 0));
1155
1156 value = ac_lds_load(&ctx->ac, dw_addr);
1157
1158 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1159 }
1160
1161 /**
1162 * Store to LDS.
1163 *
1164 * \param swizzle offset (typically 0..3)
1165 * \param dw_addr address in dwords
1166 * \param value value to store
1167 */
1168 static void lds_store(struct si_shader_context *ctx,
1169 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1170 LLVMValueRef value)
1171 {
1172 dw_addr = lp_build_add(&ctx->bld_base.uint_bld, dw_addr,
1173 LLVMConstInt(ctx->i32, dw_offset_imm, 0));
1174
1175 ac_lds_store(&ctx->ac, dw_addr, value);
1176 }
1177
1178 enum si_tess_ring {
1179 TCS_FACTOR_RING,
1180 TESS_OFFCHIP_RING_TCS,
1181 TESS_OFFCHIP_RING_TES,
1182 };
1183
1184 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
1185 enum si_tess_ring ring)
1186 {
1187 LLVMBuilderRef builder = ctx->ac.builder;
1188 unsigned param = ring == TESS_OFFCHIP_RING_TES ? ctx->param_tes_offchip_addr :
1189 ctx->param_tcs_out_lds_layout;
1190 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1191
1192 /* TCS only receives high 13 bits of the address. */
1193 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
1194 addr = LLVMBuildAnd(builder, addr,
1195 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
1196 }
1197
1198 if (ring == TCS_FACTOR_RING) {
1199 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
1200 addr = LLVMBuildAdd(builder, addr,
1201 LLVMConstInt(ctx->i32, tf_offset, 0), "");
1202 }
1203
1204 LLVMValueRef desc[4];
1205 desc[0] = addr;
1206 desc[1] = LLVMConstInt(ctx->i32,
1207 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1208 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
1209 desc[3] = LLVMConstInt(ctx->i32,
1210 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1211 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1212 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1213 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1214 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1215 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0);
1216
1217 return ac_build_gather_values(&ctx->ac, desc, 4);
1218 }
1219
1220 static LLVMValueRef fetch_input_tcs(
1221 struct lp_build_tgsi_context *bld_base,
1222 const struct tgsi_full_src_register *reg,
1223 enum tgsi_opcode_type type, unsigned swizzle)
1224 {
1225 struct si_shader_context *ctx = si_shader_context(bld_base);
1226 LLVMValueRef dw_addr, stride;
1227
1228 stride = get_tcs_in_vertex_dw_stride(ctx);
1229 dw_addr = get_tcs_in_current_patch_offset(ctx);
1230 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1231
1232 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1233 }
1234
1235 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1236 LLVMTypeRef type,
1237 LLVMValueRef vertex_index,
1238 LLVMValueRef param_index,
1239 unsigned const_index,
1240 unsigned location,
1241 unsigned driver_location,
1242 unsigned component,
1243 unsigned num_components,
1244 bool is_patch,
1245 bool is_compact,
1246 bool load_input)
1247 {
1248 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1249 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1250 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1251 LLVMValueRef dw_addr, stride;
1252
1253 driver_location = driver_location / 4;
1254
1255 if (load_input) {
1256 stride = get_tcs_in_vertex_dw_stride(ctx);
1257 dw_addr = get_tcs_in_current_patch_offset(ctx);
1258 } else {
1259 if (is_patch) {
1260 stride = NULL;
1261 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1262 } else {
1263 stride = get_tcs_out_vertex_dw_stride(ctx);
1264 dw_addr = get_tcs_out_current_patch_offset(ctx);
1265 }
1266 }
1267
1268 if (param_index) {
1269 /* Add the constant index to the indirect index */
1270 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1271 LLVMConstInt(ctx->i32, const_index, 0), "");
1272 } else {
1273 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1274 }
1275
1276 ubyte *names;
1277 ubyte *indices;
1278 if (load_input) {
1279 names = info->input_semantic_name;
1280 indices = info->input_semantic_index;
1281 } else {
1282 names = info->output_semantic_name;
1283 indices = info->output_semantic_index;
1284 }
1285
1286 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1287 vertex_index, param_index,
1288 driver_location,
1289 names, indices,
1290 is_patch);
1291
1292 LLVMValueRef value[4];
1293 for (unsigned i = 0; i < num_components + component; i++) {
1294 unsigned offset = i;
1295 if (llvm_type_is_64bit(ctx, type))
1296 offset *= 2;
1297
1298 value[i] = lds_load(bld_base, type, offset, dw_addr);
1299 }
1300
1301 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1302 }
1303
1304 static LLVMValueRef fetch_output_tcs(
1305 struct lp_build_tgsi_context *bld_base,
1306 const struct tgsi_full_src_register *reg,
1307 enum tgsi_opcode_type type, unsigned swizzle)
1308 {
1309 struct si_shader_context *ctx = si_shader_context(bld_base);
1310 LLVMValueRef dw_addr, stride;
1311
1312 if (reg->Register.Dimension) {
1313 stride = get_tcs_out_vertex_dw_stride(ctx);
1314 dw_addr = get_tcs_out_current_patch_offset(ctx);
1315 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1316 } else {
1317 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1318 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1319 }
1320
1321 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1322 }
1323
1324 static LLVMValueRef fetch_input_tes(
1325 struct lp_build_tgsi_context *bld_base,
1326 const struct tgsi_full_src_register *reg,
1327 enum tgsi_opcode_type type, unsigned swizzle)
1328 {
1329 struct si_shader_context *ctx = si_shader_context(bld_base);
1330 LLVMValueRef base, addr;
1331
1332 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1333 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1334
1335 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1336 ctx->tess_offchip_ring, base, addr, true);
1337 }
1338
1339 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1340 LLVMTypeRef type,
1341 LLVMValueRef vertex_index,
1342 LLVMValueRef param_index,
1343 unsigned const_index,
1344 unsigned location,
1345 unsigned driver_location,
1346 unsigned component,
1347 unsigned num_components,
1348 bool is_patch,
1349 bool is_compact,
1350 bool load_input)
1351 {
1352 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1353 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1354 LLVMValueRef base, addr;
1355
1356 driver_location = driver_location / 4;
1357
1358 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1359
1360 if (param_index) {
1361 /* Add the constant index to the indirect index */
1362 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1363 LLVMConstInt(ctx->i32, const_index, 0), "");
1364 } else {
1365 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1366 }
1367
1368 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1369 param_index, driver_location,
1370 info->input_semantic_name,
1371 info->input_semantic_index,
1372 is_patch);
1373
1374 /* TODO: This will generate rather ordinary llvm code, although it
1375 * should be easy for the optimiser to fix up. In future we might want
1376 * to refactor buffer_load(), but for now this maximises code sharing
1377 * between the NIR and TGSI backends.
1378 */
1379 LLVMValueRef value[4];
1380 for (unsigned i = component; i < num_components + component; i++) {
1381 unsigned offset = i;
1382 if (llvm_type_is_64bit(ctx, type))
1383 offset *= 2;
1384
1385 value[i] = buffer_load(&ctx->bld_base, type, offset,
1386 ctx->tess_offchip_ring, base, addr, true);
1387 }
1388
1389 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1390 }
1391
1392 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1393 const struct tgsi_full_instruction *inst,
1394 const struct tgsi_opcode_info *info,
1395 unsigned index,
1396 LLVMValueRef dst[4])
1397 {
1398 struct si_shader_context *ctx = si_shader_context(bld_base);
1399 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1400 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1401 unsigned chan_index;
1402 LLVMValueRef dw_addr, stride;
1403 LLVMValueRef buffer, base, buf_addr;
1404 LLVMValueRef values[4];
1405 bool skip_lds_store;
1406 bool is_tess_factor = false, is_tess_inner = false;
1407
1408 /* Only handle per-patch and per-vertex outputs here.
1409 * Vectors will be lowered to scalars and this function will be called again.
1410 */
1411 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1412 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1413 si_llvm_emit_store(bld_base, inst, info, index, dst);
1414 return;
1415 }
1416
1417 if (reg->Register.Dimension) {
1418 stride = get_tcs_out_vertex_dw_stride(ctx);
1419 dw_addr = get_tcs_out_current_patch_offset(ctx);
1420 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1421 skip_lds_store = !sh_info->reads_pervertex_outputs;
1422 } else {
1423 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1424 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1425 skip_lds_store = !sh_info->reads_perpatch_outputs;
1426
1427 if (!reg->Register.Indirect) {
1428 int name = sh_info->output_semantic_name[reg->Register.Index];
1429
1430 /* Always write tess factors into LDS for the TCS epilog. */
1431 if (name == TGSI_SEMANTIC_TESSINNER ||
1432 name == TGSI_SEMANTIC_TESSOUTER) {
1433 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1434 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1435 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1436 is_tess_factor = true;
1437 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1438 }
1439 }
1440 }
1441
1442 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1443
1444 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1445 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1446
1447 uint32_t writemask = reg->Register.WriteMask;
1448 while (writemask) {
1449 chan_index = u_bit_scan(&writemask);
1450 LLVMValueRef value = dst[chan_index];
1451
1452 if (inst->Instruction.Saturate)
1453 value = ac_build_clamp(&ctx->ac, value);
1454
1455 /* Skip LDS stores if there is no LDS read of this output. */
1456 if (!skip_lds_store)
1457 lds_store(ctx, chan_index, dw_addr, value);
1458
1459 value = ac_to_integer(&ctx->ac, value);
1460 values[chan_index] = value;
1461
1462 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1463 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1464 buf_addr, base,
1465 4 * chan_index, 1, 0, true, false);
1466 }
1467
1468 /* Write tess factors into VGPRs for the epilog. */
1469 if (is_tess_factor &&
1470 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1471 if (!is_tess_inner) {
1472 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1473 ctx->invoc0_tess_factors[chan_index]);
1474 } else if (chan_index < 2) {
1475 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1476 ctx->invoc0_tess_factors[4 + chan_index]);
1477 }
1478 }
1479 }
1480
1481 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1482 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1483 values, 4);
1484 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1485 base, 0, 1, 0, true, false);
1486 }
1487 }
1488
1489 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1490 LLVMValueRef vertex_index,
1491 LLVMValueRef param_index,
1492 unsigned const_index,
1493 unsigned location,
1494 unsigned driver_location,
1495 LLVMValueRef src,
1496 unsigned component,
1497 bool is_patch,
1498 bool is_compact,
1499 unsigned writemask)
1500 {
1501 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1502 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1503 LLVMValueRef dw_addr, stride;
1504 LLVMValueRef buffer, base, addr;
1505 LLVMValueRef values[4];
1506 bool skip_lds_store;
1507 bool is_tess_factor = false, is_tess_inner = false;
1508
1509 driver_location = driver_location / 4;
1510
1511 if (param_index) {
1512 /* Add the constant index to the indirect index */
1513 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1514 LLVMConstInt(ctx->i32, const_index, 0), "");
1515 } else {
1516 if (const_index != 0)
1517 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1518 }
1519
1520 if (!is_patch) {
1521 stride = get_tcs_out_vertex_dw_stride(ctx);
1522 dw_addr = get_tcs_out_current_patch_offset(ctx);
1523 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1524 vertex_index, param_index,
1525 driver_location,
1526 info->output_semantic_name,
1527 info->output_semantic_index,
1528 is_patch);
1529
1530 skip_lds_store = !info->reads_pervertex_outputs;
1531 } else {
1532 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1533 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1534 vertex_index, param_index,
1535 driver_location,
1536 info->output_semantic_name,
1537 info->output_semantic_index,
1538 is_patch);
1539
1540 skip_lds_store = !info->reads_perpatch_outputs;
1541
1542 if (!param_index) {
1543 int name = info->output_semantic_name[driver_location];
1544
1545 /* Always write tess factors into LDS for the TCS epilog. */
1546 if (name == TGSI_SEMANTIC_TESSINNER ||
1547 name == TGSI_SEMANTIC_TESSOUTER) {
1548 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1549 skip_lds_store = !info->reads_tessfactor_outputs &&
1550 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1551 is_tess_factor = true;
1552 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1553 }
1554 }
1555 }
1556
1557 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1558
1559 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1560
1561 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1562 param_index, driver_location,
1563 info->output_semantic_name,
1564 info->output_semantic_index,
1565 is_patch);
1566
1567 for (unsigned chan = 0; chan < 4; chan++) {
1568 if (!(writemask & (1 << chan)))
1569 continue;
1570 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1571
1572 /* Skip LDS stores if there is no LDS read of this output. */
1573 if (!skip_lds_store)
1574 lds_store(ctx, chan, dw_addr, value);
1575
1576 value = ac_to_integer(&ctx->ac, value);
1577 values[chan] = value;
1578
1579 if (writemask != 0xF && !is_tess_factor) {
1580 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1581 addr, base,
1582 4 * chan, 1, 0, true, false);
1583 }
1584
1585 /* Write tess factors into VGPRs for the epilog. */
1586 if (is_tess_factor &&
1587 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1588 if (!is_tess_inner) {
1589 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1590 ctx->invoc0_tess_factors[chan]);
1591 } else if (chan < 2) {
1592 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1593 ctx->invoc0_tess_factors[4 + chan]);
1594 }
1595 }
1596 }
1597
1598 if (writemask == 0xF && !is_tess_factor) {
1599 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1600 values, 4);
1601 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1602 base, 0, 1, 0, true, false);
1603 }
1604 }
1605
1606 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1607 unsigned input_index,
1608 unsigned vtx_offset_param,
1609 LLVMTypeRef type,
1610 unsigned swizzle)
1611 {
1612 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1613 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1614 struct si_shader *shader = ctx->shader;
1615 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1616 LLVMValueRef vtx_offset, soffset;
1617 struct tgsi_shader_info *info = &shader->selector->info;
1618 unsigned semantic_name = info->input_semantic_name[input_index];
1619 unsigned semantic_index = info->input_semantic_index[input_index];
1620 unsigned param;
1621 LLVMValueRef value;
1622
1623 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1624
1625 /* GFX9 has the ESGS ring in LDS. */
1626 if (ctx->screen->info.chip_class >= GFX9) {
1627 unsigned index = vtx_offset_param;
1628
1629 switch (index / 2) {
1630 case 0:
1631 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx01_offset,
1632 index % 2 ? 16 : 0, 16);
1633 break;
1634 case 1:
1635 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx23_offset,
1636 index % 2 ? 16 : 0, 16);
1637 break;
1638 case 2:
1639 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx45_offset,
1640 index % 2 ? 16 : 0, 16);
1641 break;
1642 default:
1643 assert(0);
1644 return NULL;
1645 }
1646
1647 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1648 LLVMConstInt(ctx->i32, param * 4, 0), "");
1649 return lds_load(bld_base, type, swizzle, vtx_offset);
1650 }
1651
1652 /* GFX6: input load from the ESGS ring in memory. */
1653 if (swizzle == ~0) {
1654 LLVMValueRef values[TGSI_NUM_CHANNELS];
1655 unsigned chan;
1656 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1657 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1658 type, chan);
1659 }
1660 return lp_build_gather_values(&ctx->gallivm, values,
1661 TGSI_NUM_CHANNELS);
1662 }
1663
1664 /* Get the vertex offset parameter on GFX6. */
1665 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1666
1667 vtx_offset = lp_build_mul_imm(uint, gs_vtx_offset, 4);
1668
1669 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1670
1671 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1672 vtx_offset, soffset, 0, 1, 0, true, false);
1673 if (llvm_type_is_64bit(ctx, type)) {
1674 LLVMValueRef value2;
1675 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1676
1677 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1678 ctx->i32_0, vtx_offset, soffset,
1679 0, 1, 0, true, false);
1680 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1681 }
1682 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1683 }
1684
1685 static LLVMValueRef fetch_input_gs(
1686 struct lp_build_tgsi_context *bld_base,
1687 const struct tgsi_full_src_register *reg,
1688 enum tgsi_opcode_type type,
1689 unsigned swizzle)
1690 {
1691 struct si_shader_context *ctx = si_shader_context(bld_base);
1692 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1693
1694 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1695 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1696 return get_primitive_id(ctx, swizzle);
1697
1698 if (!reg->Register.Dimension)
1699 return NULL;
1700
1701 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1702 reg->Dimension.Index,
1703 tgsi2llvmtype(bld_base, type),
1704 swizzle);
1705 }
1706
1707 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1708 {
1709 switch (interpolate) {
1710 case TGSI_INTERPOLATE_CONSTANT:
1711 return 0;
1712
1713 case TGSI_INTERPOLATE_LINEAR:
1714 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1715 return SI_PARAM_LINEAR_SAMPLE;
1716 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1717 return SI_PARAM_LINEAR_CENTROID;
1718 else
1719 return SI_PARAM_LINEAR_CENTER;
1720 break;
1721 case TGSI_INTERPOLATE_COLOR:
1722 case TGSI_INTERPOLATE_PERSPECTIVE:
1723 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1724 return SI_PARAM_PERSP_SAMPLE;
1725 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1726 return SI_PARAM_PERSP_CENTROID;
1727 else
1728 return SI_PARAM_PERSP_CENTER;
1729 break;
1730 default:
1731 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1732 return -1;
1733 }
1734 }
1735
1736 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1737 unsigned attr_index, unsigned chan,
1738 LLVMValueRef prim_mask,
1739 LLVMValueRef i, LLVMValueRef j)
1740 {
1741 if (i || j) {
1742 return ac_build_fs_interp(&ctx->ac,
1743 LLVMConstInt(ctx->i32, chan, 0),
1744 LLVMConstInt(ctx->i32, attr_index, 0),
1745 prim_mask, i, j);
1746 }
1747 return ac_build_fs_interp_mov(&ctx->ac,
1748 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1749 LLVMConstInt(ctx->i32, chan, 0),
1750 LLVMConstInt(ctx->i32, attr_index, 0),
1751 prim_mask);
1752 }
1753
1754 /**
1755 * Interpolate a fragment shader input.
1756 *
1757 * @param ctx context
1758 * @param input_index index of the input in hardware
1759 * @param semantic_name TGSI_SEMANTIC_*
1760 * @param semantic_index semantic index
1761 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1762 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1763 * @param interp_param interpolation weights (i,j)
1764 * @param prim_mask SI_PARAM_PRIM_MASK
1765 * @param face SI_PARAM_FRONT_FACE
1766 * @param result the return value (4 components)
1767 */
1768 static void interp_fs_input(struct si_shader_context *ctx,
1769 unsigned input_index,
1770 unsigned semantic_name,
1771 unsigned semantic_index,
1772 unsigned num_interp_inputs,
1773 unsigned colors_read_mask,
1774 LLVMValueRef interp_param,
1775 LLVMValueRef prim_mask,
1776 LLVMValueRef face,
1777 LLVMValueRef result[4])
1778 {
1779 LLVMValueRef i = NULL, j = NULL;
1780 unsigned chan;
1781
1782 /* fs.constant returns the param from the middle vertex, so it's not
1783 * really useful for flat shading. It's meant to be used for custom
1784 * interpolation (but the intrinsic can't fetch from the other two
1785 * vertices).
1786 *
1787 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1788 * to do the right thing. The only reason we use fs.constant is that
1789 * fs.interp cannot be used on integers, because they can be equal
1790 * to NaN.
1791 *
1792 * When interp is false we will use fs.constant or for newer llvm,
1793 * amdgcn.interp.mov.
1794 */
1795 bool interp = interp_param != NULL;
1796
1797 if (interp) {
1798 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1799 LLVMVectorType(ctx->f32, 2), "");
1800
1801 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1802 ctx->i32_0, "");
1803 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1804 ctx->i32_1, "");
1805 }
1806
1807 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1808 ctx->shader->key.part.ps.prolog.color_two_side) {
1809 LLVMValueRef is_face_positive;
1810
1811 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1812 * otherwise it's at offset "num_inputs".
1813 */
1814 unsigned back_attr_offset = num_interp_inputs;
1815 if (semantic_index == 1 && colors_read_mask & 0xf)
1816 back_attr_offset += 1;
1817
1818 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1819 face, ctx->i32_0, "");
1820
1821 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1822 LLVMValueRef front, back;
1823
1824 front = si_build_fs_interp(ctx,
1825 input_index, chan,
1826 prim_mask, i, j);
1827 back = si_build_fs_interp(ctx,
1828 back_attr_offset, chan,
1829 prim_mask, i, j);
1830
1831 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1832 is_face_positive,
1833 front,
1834 back,
1835 "");
1836 }
1837 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1838 result[0] = si_build_fs_interp(ctx, input_index,
1839 0, prim_mask, i, j);
1840 result[1] =
1841 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1842 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1843 } else {
1844 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1845 result[chan] = si_build_fs_interp(ctx,
1846 input_index, chan,
1847 prim_mask, i, j);
1848 }
1849 }
1850 }
1851
1852 void si_llvm_load_input_fs(
1853 struct si_shader_context *ctx,
1854 unsigned input_index,
1855 LLVMValueRef out[4])
1856 {
1857 struct lp_build_context *base = &ctx->bld_base.base;
1858 struct si_shader *shader = ctx->shader;
1859 struct tgsi_shader_info *info = &shader->selector->info;
1860 LLVMValueRef main_fn = ctx->main_fn;
1861 LLVMValueRef interp_param = NULL;
1862 int interp_param_idx;
1863 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1864 unsigned semantic_index = info->input_semantic_index[input_index];
1865 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1866 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1867
1868 /* Get colors from input VGPRs (set by the prolog). */
1869 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1870 unsigned colors_read = shader->selector->info.colors_read;
1871 unsigned mask = colors_read >> (semantic_index * 4);
1872 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1873 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1874
1875 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1876 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1877 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1878 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1879 return;
1880 }
1881
1882 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1883 if (interp_param_idx == -1)
1884 return;
1885 else if (interp_param_idx) {
1886 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1887 }
1888
1889 interp_fs_input(ctx, input_index, semantic_name,
1890 semantic_index, 0, /* this param is unused */
1891 shader->selector->info.colors_read, interp_param,
1892 ctx->abi.prim_mask,
1893 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1894 &out[0]);
1895 }
1896
1897 static void declare_input_fs(
1898 struct si_shader_context *ctx,
1899 unsigned input_index,
1900 const struct tgsi_full_declaration *decl,
1901 LLVMValueRef out[4])
1902 {
1903 si_llvm_load_input_fs(ctx, input_index, out);
1904 }
1905
1906 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1907 {
1908 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1909 }
1910
1911 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1912 {
1913 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1914
1915 LLVMValueRef values[3];
1916 LLVMValueRef result;
1917 unsigned i;
1918 unsigned *properties = ctx->shader->selector->info.properties;
1919
1920 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1921 unsigned sizes[3] = {
1922 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1923 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1924 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1925 };
1926
1927 for (i = 0; i < 3; ++i)
1928 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1929
1930 result = lp_build_gather_values(&ctx->gallivm, values, 3);
1931 } else {
1932 result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1933 }
1934
1935 return result;
1936 }
1937
1938 /**
1939 * Load a dword from a constant buffer.
1940 */
1941 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1942 LLVMValueRef resource,
1943 LLVMValueRef offset)
1944 {
1945 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1946 0, 0, 0, true, true);
1947 }
1948
1949 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1950 {
1951 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1952 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1953 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1954 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1955 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1956
1957 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1958 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1959 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1960
1961 LLVMValueRef pos[4] = {
1962 buffer_load_const(ctx, resource, offset0),
1963 buffer_load_const(ctx, resource, offset1),
1964 LLVMConstReal(ctx->f32, 0),
1965 LLVMConstReal(ctx->f32, 0)
1966 };
1967
1968 return lp_build_gather_values(&ctx->gallivm, pos, 4);
1969 }
1970
1971 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1972 {
1973 return abi->sample_coverage;
1974 }
1975
1976 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
1977 {
1978 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1979 struct lp_build_context *bld = &ctx->bld_base.base;
1980
1981 LLVMValueRef coord[4] = {
1982 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1983 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1984 ctx->ac.f32_0,
1985 ctx->ac.f32_0
1986 };
1987
1988 /* For triangles, the vector should be (u, v, 1-u-v). */
1989 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1990 PIPE_PRIM_TRIANGLES)
1991 coord[2] = lp_build_sub(bld, ctx->ac.f32_1,
1992 lp_build_add(bld, coord[0], coord[1]));
1993
1994 return lp_build_gather_values(&ctx->gallivm, coord, 4);
1995 }
1996
1997 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
1998 unsigned semantic_name)
1999 {
2000 LLVMValueRef base, addr;
2001
2002 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
2003
2004 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2005 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
2006 LLVMConstInt(ctx->i32, param, 0));
2007
2008 return buffer_load(&ctx->bld_base, ctx->f32,
2009 ~0, ctx->tess_offchip_ring, base, addr, true);
2010
2011 }
2012
2013 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
2014 unsigned varying_id)
2015 {
2016 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2017 unsigned semantic_name;
2018
2019 switch (varying_id) {
2020 case VARYING_SLOT_TESS_LEVEL_INNER:
2021 semantic_name = TGSI_SEMANTIC_TESSINNER;
2022 break;
2023 case VARYING_SLOT_TESS_LEVEL_OUTER:
2024 semantic_name = TGSI_SEMANTIC_TESSOUTER;
2025 break;
2026 default:
2027 unreachable("unknown tess level");
2028 }
2029
2030 return load_tess_level(ctx, semantic_name);
2031
2032 }
2033
2034 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
2035 {
2036 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2037 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2038 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
2039 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
2040 return get_num_tcs_out_vertices(ctx);
2041 else
2042 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2043 }
2044
2045 void si_load_system_value(struct si_shader_context *ctx,
2046 unsigned index,
2047 const struct tgsi_full_declaration *decl)
2048 {
2049 LLVMValueRef value = 0;
2050
2051 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
2052
2053 switch (decl->Semantic.Name) {
2054 case TGSI_SEMANTIC_INSTANCEID:
2055 value = ctx->abi.instance_id;
2056 break;
2057
2058 case TGSI_SEMANTIC_VERTEXID:
2059 value = LLVMBuildAdd(ctx->ac.builder,
2060 ctx->abi.vertex_id,
2061 ctx->abi.base_vertex, "");
2062 break;
2063
2064 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2065 /* Unused. Clarify the meaning in indexed vs. non-indexed
2066 * draws if this is ever used again. */
2067 assert(false);
2068 break;
2069
2070 case TGSI_SEMANTIC_BASEVERTEX:
2071 {
2072 /* For non-indexed draws, the base vertex set by the driver
2073 * (for direct draws) or the CP (for indirect draws) is the
2074 * first vertex ID, but GLSL expects 0 to be returned.
2075 */
2076 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
2077 LLVMValueRef indexed;
2078
2079 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
2080 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
2081
2082 value = LLVMBuildSelect(ctx->ac.builder, indexed,
2083 ctx->abi.base_vertex, ctx->i32_0, "");
2084 break;
2085 }
2086
2087 case TGSI_SEMANTIC_BASEINSTANCE:
2088 value = ctx->abi.start_instance;
2089 break;
2090
2091 case TGSI_SEMANTIC_DRAWID:
2092 value = ctx->abi.draw_id;
2093 break;
2094
2095 case TGSI_SEMANTIC_INVOCATIONID:
2096 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2097 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2098 else if (ctx->type == PIPE_SHADER_GEOMETRY)
2099 value = ctx->abi.gs_invocation_id;
2100 else
2101 assert(!"INVOCATIONID not implemented");
2102 break;
2103
2104 case TGSI_SEMANTIC_POSITION:
2105 {
2106 LLVMValueRef pos[4] = {
2107 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2108 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2109 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2110 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
2111 LLVMGetParam(ctx->main_fn,
2112 SI_PARAM_POS_W_FLOAT)),
2113 };
2114 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
2115 break;
2116 }
2117
2118 case TGSI_SEMANTIC_FACE:
2119 value = ctx->abi.front_face;
2120 break;
2121
2122 case TGSI_SEMANTIC_SAMPLEID:
2123 value = get_sample_id(ctx);
2124 break;
2125
2126 case TGSI_SEMANTIC_SAMPLEPOS: {
2127 LLVMValueRef pos[4] = {
2128 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2129 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2130 LLVMConstReal(ctx->f32, 0),
2131 LLVMConstReal(ctx->f32, 0)
2132 };
2133 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
2134 TGSI_OPCODE_FRC, pos[0]);
2135 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
2136 TGSI_OPCODE_FRC, pos[1]);
2137 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
2138 break;
2139 }
2140
2141 case TGSI_SEMANTIC_SAMPLEMASK:
2142 /* This can only occur with the OpenGL Core profile, which
2143 * doesn't support smoothing.
2144 */
2145 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2146 break;
2147
2148 case TGSI_SEMANTIC_TESSCOORD:
2149 value = si_load_tess_coord(&ctx->abi);
2150 break;
2151
2152 case TGSI_SEMANTIC_VERTICESIN:
2153 value = si_load_patch_vertices_in(&ctx->abi);
2154 break;
2155
2156 case TGSI_SEMANTIC_TESSINNER:
2157 case TGSI_SEMANTIC_TESSOUTER:
2158 value = load_tess_level(ctx, decl->Semantic.Name);
2159 break;
2160
2161 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
2162 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
2163 {
2164 LLVMValueRef buf, slot, val[4];
2165 int i, offset;
2166
2167 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
2168 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2169 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
2170 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
2171
2172 for (i = 0; i < 4; i++)
2173 val[i] = buffer_load_const(ctx, buf,
2174 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
2175 value = lp_build_gather_values(&ctx->gallivm, val, 4);
2176 break;
2177 }
2178
2179 case TGSI_SEMANTIC_PRIMID:
2180 value = get_primitive_id(ctx, 0);
2181 break;
2182
2183 case TGSI_SEMANTIC_GRID_SIZE:
2184 value = ctx->abi.num_work_groups;
2185 break;
2186
2187 case TGSI_SEMANTIC_BLOCK_SIZE:
2188 value = get_block_size(&ctx->abi);
2189 break;
2190
2191 case TGSI_SEMANTIC_BLOCK_ID:
2192 {
2193 LLVMValueRef values[3];
2194
2195 for (int i = 0; i < 3; i++) {
2196 values[i] = ctx->i32_0;
2197 if (ctx->abi.workgroup_ids[i]) {
2198 values[i] = ctx->abi.workgroup_ids[i];
2199 }
2200 }
2201 value = lp_build_gather_values(&ctx->gallivm, values, 3);
2202 break;
2203 }
2204
2205 case TGSI_SEMANTIC_THREAD_ID:
2206 value = ctx->abi.local_invocation_ids;
2207 break;
2208
2209 case TGSI_SEMANTIC_HELPER_INVOCATION:
2210 value = lp_build_intrinsic(ctx->ac.builder,
2211 "llvm.amdgcn.ps.live",
2212 ctx->i1, NULL, 0,
2213 LP_FUNC_ATTR_READNONE);
2214 value = LLVMBuildNot(ctx->ac.builder, value, "");
2215 value = LLVMBuildSExt(ctx->ac.builder, value, ctx->i32, "");
2216 break;
2217
2218 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2219 value = LLVMConstInt(ctx->i32, 64, 0);
2220 break;
2221
2222 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2223 value = ac_get_thread_id(&ctx->ac);
2224 break;
2225
2226 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2227 {
2228 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2229 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2230 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
2231 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2232 break;
2233 }
2234
2235 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2236 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2237 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2238 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2239 {
2240 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2241 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2242 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2243 /* All bits set except LSB */
2244 value = LLVMConstInt(ctx->i64, -2, 0);
2245 } else {
2246 /* All bits set */
2247 value = LLVMConstInt(ctx->i64, -1, 0);
2248 }
2249 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2250 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2251 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2252 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2253 value = LLVMBuildNot(ctx->ac.builder, value, "");
2254 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2255 break;
2256 }
2257
2258 default:
2259 assert(!"unknown system value");
2260 return;
2261 }
2262
2263 ctx->system_values[index] = value;
2264 }
2265
2266 void si_declare_compute_memory(struct si_shader_context *ctx)
2267 {
2268 struct si_shader_selector *sel = ctx->shader->selector;
2269
2270 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_LOCAL_ADDR_SPACE);
2271 LLVMValueRef var;
2272
2273 assert(!ctx->ac.lds);
2274
2275 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2276 LLVMArrayType(ctx->i8, sel->local_size),
2277 "compute_lds",
2278 AC_LOCAL_ADDR_SPACE);
2279 LLVMSetAlignment(var, 4);
2280
2281 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2282 }
2283
2284 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
2285 const struct tgsi_full_declaration *decl)
2286 {
2287 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2288 assert(decl->Range.First == decl->Range.Last);
2289
2290 si_declare_compute_memory(ctx);
2291 }
2292
2293 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2294 {
2295 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2296 ctx->param_const_and_shader_buffers);
2297
2298 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2299 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2300 }
2301
2302 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2303 {
2304 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2305 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2306
2307 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2308 index = LLVMBuildAdd(ctx->ac.builder, index,
2309 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2310
2311 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2312 }
2313
2314 static LLVMValueRef
2315 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2316 {
2317 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2318 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2319 ctx->param_const_and_shader_buffers);
2320
2321 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2322 index = LLVMBuildSub(ctx->ac.builder,
2323 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2324 index, "");
2325
2326 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2327 }
2328
2329 static LLVMValueRef fetch_constant(
2330 struct lp_build_tgsi_context *bld_base,
2331 const struct tgsi_full_src_register *reg,
2332 enum tgsi_opcode_type type,
2333 unsigned swizzle)
2334 {
2335 struct si_shader_context *ctx = si_shader_context(bld_base);
2336 struct si_shader_selector *sel = ctx->shader->selector;
2337 const struct tgsi_ind_register *ireg = &reg->Indirect;
2338 unsigned buf, idx;
2339
2340 LLVMValueRef addr, bufp;
2341
2342 if (swizzle == LP_CHAN_ALL) {
2343 unsigned chan;
2344 LLVMValueRef values[4];
2345 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2346 values[chan] = fetch_constant(bld_base, reg, type, chan);
2347
2348 return lp_build_gather_values(&ctx->gallivm, values, 4);
2349 }
2350
2351 /* Split 64-bit loads. */
2352 if (tgsi_type_is_64bit(type)) {
2353 LLVMValueRef lo, hi;
2354
2355 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2356 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle + 1);
2357 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2358 lo, hi);
2359 }
2360
2361 idx = reg->Register.Index * 4 + swizzle;
2362 if (reg->Register.Indirect) {
2363 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2364 } else {
2365 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2366 }
2367
2368 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2369 if (sel->info.const_buffers_declared == 1 &&
2370 sel->info.shader_buffers_declared == 0) {
2371 LLVMValueRef ptr =
2372 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2373
2374 /* This enables use of s_load_dword and flat_load_dword for const buffer 0
2375 * loads, and up to x4 load opcode merging. However, it leads to horrible
2376 * code reducing SIMD wave occupancy from 8 to 2 in many cases.
2377 *
2378 * Using s_buffer_load_dword (x1) seems to be the best option right now.
2379 *
2380 * LLVM 5.0 on SI doesn't insert a required s_nop between SALU setting
2381 * a descriptor and s_buffer_load_dword using it, so we can't expand
2382 * the pointer into a full descriptor like below. We have to use
2383 * s_load_dword instead. The only case when LLVM 5.0 would select
2384 * s_buffer_load_dword (that we have to prevent) is when we use use
2385 * a literal offset where we don't need bounds checking.
2386 */
2387 if (ctx->screen->info.chip_class == SI &&
2388 HAVE_LLVM < 0x0600 &&
2389 !reg->Register.Indirect) {
2390 addr = LLVMBuildLShr(ctx->ac.builder, addr, LLVMConstInt(ctx->i32, 2, 0), "");
2391 LLVMValueRef result = ac_build_load_invariant(&ctx->ac, ptr, addr);
2392 return bitcast(bld_base, type, result);
2393 }
2394
2395 /* Do the bounds checking with a descriptor, because
2396 * doing computation and manual bounds checking of 64-bit
2397 * addresses generates horrible VALU code with very high
2398 * VGPR usage and very low SIMD occupancy.
2399 */
2400 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->i64, "");
2401 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ctx->v2i32, "");
2402
2403 LLVMValueRef desc_elems[] = {
2404 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_0, ""),
2405 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_1, ""),
2406 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2407 LLVMConstInt(ctx->i32,
2408 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2409 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2410 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2411 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2412 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2413 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2414 };
2415 LLVMValueRef desc = ac_build_gather_values(&ctx->ac, desc_elems, 4);
2416 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2417 return bitcast(bld_base, type, result);
2418 }
2419
2420 assert(reg->Register.Dimension);
2421 buf = reg->Dimension.Index;
2422
2423 if (reg->Dimension.Indirect) {
2424 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2425 LLVMValueRef index;
2426 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2427 reg->Dimension.Index,
2428 ctx->num_const_buffers);
2429 index = LLVMBuildAdd(ctx->ac.builder, index,
2430 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2431 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2432 } else
2433 bufp = load_const_buffer_desc(ctx, buf);
2434
2435 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2436 }
2437
2438 /* Initialize arguments for the shader export intrinsic */
2439 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2440 LLVMValueRef *values,
2441 unsigned target,
2442 struct ac_export_args *args)
2443 {
2444 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2445 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2446 unsigned chan;
2447 bool is_int8, is_int10;
2448
2449 /* Default is 0xf. Adjusted below depending on the format. */
2450 args->enabled_channels = 0xf; /* writemask */
2451
2452 /* Specify whether the EXEC mask represents the valid mask */
2453 args->valid_mask = 0;
2454
2455 /* Specify whether this is the last export */
2456 args->done = 0;
2457
2458 /* Specify the target we are exporting */
2459 args->target = target;
2460
2461 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2462 const struct si_shader_key *key = &ctx->shader->key;
2463 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2464 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2465
2466 assert(cbuf >= 0 && cbuf < 8);
2467 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2468 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2469 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2470 }
2471
2472 args->compr = false;
2473 args->out[0] = f32undef;
2474 args->out[1] = f32undef;
2475 args->out[2] = f32undef;
2476 args->out[3] = f32undef;
2477
2478 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2479 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2480 unsigned bits, bool hi) = NULL;
2481
2482 switch (spi_shader_col_format) {
2483 case V_028714_SPI_SHADER_ZERO:
2484 args->enabled_channels = 0; /* writemask */
2485 args->target = V_008DFC_SQ_EXP_NULL;
2486 break;
2487
2488 case V_028714_SPI_SHADER_32_R:
2489 args->enabled_channels = 1; /* writemask */
2490 args->out[0] = values[0];
2491 break;
2492
2493 case V_028714_SPI_SHADER_32_GR:
2494 args->enabled_channels = 0x3; /* writemask */
2495 args->out[0] = values[0];
2496 args->out[1] = values[1];
2497 break;
2498
2499 case V_028714_SPI_SHADER_32_AR:
2500 args->enabled_channels = 0x9; /* writemask */
2501 args->out[0] = values[0];
2502 args->out[3] = values[3];
2503 break;
2504
2505 case V_028714_SPI_SHADER_FP16_ABGR:
2506 packf = ac_build_cvt_pkrtz_f16;
2507 break;
2508
2509 case V_028714_SPI_SHADER_UNORM16_ABGR:
2510 packf = ac_build_cvt_pknorm_u16;
2511 break;
2512
2513 case V_028714_SPI_SHADER_SNORM16_ABGR:
2514 packf = ac_build_cvt_pknorm_i16;
2515 break;
2516
2517 case V_028714_SPI_SHADER_UINT16_ABGR:
2518 packi = ac_build_cvt_pk_u16;
2519 break;
2520
2521 case V_028714_SPI_SHADER_SINT16_ABGR:
2522 packi = ac_build_cvt_pk_i16;
2523 break;
2524
2525 case V_028714_SPI_SHADER_32_ABGR:
2526 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2527 break;
2528 }
2529
2530 /* Pack f16 or norm_i16/u16. */
2531 if (packf) {
2532 for (chan = 0; chan < 2; chan++) {
2533 LLVMValueRef pack_args[2] = {
2534 values[2 * chan],
2535 values[2 * chan + 1]
2536 };
2537 LLVMValueRef packed;
2538
2539 packed = packf(&ctx->ac, pack_args);
2540 args->out[chan] = ac_to_float(&ctx->ac, packed);
2541 }
2542 args->compr = 1; /* COMPR flag */
2543 }
2544 /* Pack i16/u16. */
2545 if (packi) {
2546 for (chan = 0; chan < 2; chan++) {
2547 LLVMValueRef pack_args[2] = {
2548 ac_to_integer(&ctx->ac, values[2 * chan]),
2549 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2550 };
2551 LLVMValueRef packed;
2552
2553 packed = packi(&ctx->ac, pack_args,
2554 is_int8 ? 8 : is_int10 ? 10 : 16,
2555 chan == 1);
2556 args->out[chan] = ac_to_float(&ctx->ac, packed);
2557 }
2558 args->compr = 1; /* COMPR flag */
2559 }
2560 }
2561
2562 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2563 LLVMValueRef alpha)
2564 {
2565 struct si_shader_context *ctx = si_shader_context(bld_base);
2566
2567 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2568 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2569 [PIPE_FUNC_LESS] = LLVMRealOLT,
2570 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2571 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2572 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2573 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2574 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2575 };
2576 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2577 assert(cond);
2578
2579 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2580 SI_PARAM_ALPHA_REF);
2581 LLVMValueRef alpha_pass =
2582 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2583 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2584 } else {
2585 ac_build_kill_if_false(&ctx->ac, LLVMConstInt(ctx->i1, 0, 0));
2586 }
2587 }
2588
2589 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2590 LLVMValueRef alpha,
2591 unsigned samplemask_param)
2592 {
2593 struct si_shader_context *ctx = si_shader_context(bld_base);
2594 LLVMValueRef coverage;
2595
2596 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2597 coverage = LLVMGetParam(ctx->main_fn,
2598 samplemask_param);
2599 coverage = ac_to_integer(&ctx->ac, coverage);
2600
2601 coverage = lp_build_intrinsic(ctx->ac.builder, "llvm.ctpop.i32",
2602 ctx->i32,
2603 &coverage, 1, LP_FUNC_ATTR_READNONE);
2604
2605 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2606 ctx->f32, "");
2607
2608 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2609 LLVMConstReal(ctx->f32,
2610 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2611
2612 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2613 }
2614
2615 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2616 struct ac_export_args *pos, LLVMValueRef *out_elts)
2617 {
2618 unsigned reg_index;
2619 unsigned chan;
2620 unsigned const_chan;
2621 LLVMValueRef base_elt;
2622 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2623 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2624 SI_VS_CONST_CLIP_PLANES, 0);
2625 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2626
2627 for (reg_index = 0; reg_index < 2; reg_index ++) {
2628 struct ac_export_args *args = &pos[2 + reg_index];
2629
2630 args->out[0] =
2631 args->out[1] =
2632 args->out[2] =
2633 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2634
2635 /* Compute dot products of position and user clip plane vectors */
2636 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2637 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2638 LLVMValueRef addr =
2639 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2640 const_chan) * 4, 0);
2641 base_elt = buffer_load_const(ctx, const_resource,
2642 addr);
2643 args->out[chan] =
2644 lp_build_add(&ctx->bld_base.base, args->out[chan],
2645 lp_build_mul(&ctx->bld_base.base, base_elt,
2646 out_elts[const_chan]));
2647 }
2648 }
2649
2650 args->enabled_channels = 0xf;
2651 args->valid_mask = 0;
2652 args->done = 0;
2653 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2654 args->compr = 0;
2655 }
2656 }
2657
2658 static void si_dump_streamout(struct pipe_stream_output_info *so)
2659 {
2660 unsigned i;
2661
2662 if (so->num_outputs)
2663 fprintf(stderr, "STREAMOUT\n");
2664
2665 for (i = 0; i < so->num_outputs; i++) {
2666 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2667 so->output[i].start_component;
2668 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2669 i, so->output[i].output_buffer,
2670 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2671 so->output[i].register_index,
2672 mask & 1 ? "x" : "",
2673 mask & 2 ? "y" : "",
2674 mask & 4 ? "z" : "",
2675 mask & 8 ? "w" : "");
2676 }
2677 }
2678
2679 static void emit_streamout_output(struct si_shader_context *ctx,
2680 LLVMValueRef const *so_buffers,
2681 LLVMValueRef const *so_write_offsets,
2682 struct pipe_stream_output *stream_out,
2683 struct si_shader_output_values *shader_out)
2684 {
2685 unsigned buf_idx = stream_out->output_buffer;
2686 unsigned start = stream_out->start_component;
2687 unsigned num_comps = stream_out->num_components;
2688 LLVMValueRef out[4];
2689
2690 assert(num_comps && num_comps <= 4);
2691 if (!num_comps || num_comps > 4)
2692 return;
2693
2694 /* Load the output as int. */
2695 for (int j = 0; j < num_comps; j++) {
2696 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2697
2698 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2699 }
2700
2701 /* Pack the output. */
2702 LLVMValueRef vdata = NULL;
2703
2704 switch (num_comps) {
2705 case 1: /* as i32 */
2706 vdata = out[0];
2707 break;
2708 case 2: /* as v2i32 */
2709 case 3: /* as v4i32 (aligned to 4) */
2710 case 4: /* as v4i32 */
2711 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2712 for (int j = 0; j < num_comps; j++) {
2713 vdata = LLVMBuildInsertElement(ctx->ac.builder, vdata, out[j],
2714 LLVMConstInt(ctx->i32, j, 0), "");
2715 }
2716 break;
2717 }
2718
2719 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2720 vdata, num_comps,
2721 so_write_offsets[buf_idx],
2722 ctx->i32_0,
2723 stream_out->dst_offset * 4, 1, 1, true, false);
2724 }
2725
2726 /**
2727 * Write streamout data to buffers for vertex stream @p stream (different
2728 * vertex streams can occur for GS copy shaders).
2729 */
2730 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2731 struct si_shader_output_values *outputs,
2732 unsigned noutput, unsigned stream)
2733 {
2734 struct si_shader_selector *sel = ctx->shader->selector;
2735 struct pipe_stream_output_info *so = &sel->so;
2736 LLVMBuilderRef builder = ctx->ac.builder;
2737 int i;
2738 struct lp_build_if_state if_ctx;
2739
2740 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2741 LLVMValueRef so_vtx_count =
2742 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2743
2744 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2745
2746 /* can_emit = tid < so_vtx_count; */
2747 LLVMValueRef can_emit =
2748 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2749
2750 /* Emit the streamout code conditionally. This actually avoids
2751 * out-of-bounds buffer access. The hw tells us via the SGPR
2752 * (so_vtx_count) which threads are allowed to emit streamout data. */
2753 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2754 {
2755 /* The buffer offset is computed as follows:
2756 * ByteOffset = streamout_offset[buffer_id]*4 +
2757 * (streamout_write_index + thread_id)*stride[buffer_id] +
2758 * attrib_offset
2759 */
2760
2761 LLVMValueRef so_write_index =
2762 LLVMGetParam(ctx->main_fn,
2763 ctx->param_streamout_write_index);
2764
2765 /* Compute (streamout_write_index + thread_id). */
2766 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2767
2768 /* Load the descriptor and compute the write offset for each
2769 * enabled buffer. */
2770 LLVMValueRef so_write_offset[4] = {};
2771 LLVMValueRef so_buffers[4];
2772 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2773 ctx->param_rw_buffers);
2774
2775 for (i = 0; i < 4; i++) {
2776 if (!so->stride[i])
2777 continue;
2778
2779 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2780 SI_VS_STREAMOUT_BUF0 + i, 0);
2781
2782 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2783
2784 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2785 ctx->param_streamout_offset[i]);
2786 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2787
2788 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2789 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2790 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2791 }
2792
2793 /* Write streamout data. */
2794 for (i = 0; i < so->num_outputs; i++) {
2795 unsigned reg = so->output[i].register_index;
2796
2797 if (reg >= noutput)
2798 continue;
2799
2800 if (stream != so->output[i].stream)
2801 continue;
2802
2803 emit_streamout_output(ctx, so_buffers, so_write_offset,
2804 &so->output[i], &outputs[reg]);
2805 }
2806 }
2807 lp_build_endif(&if_ctx);
2808 }
2809
2810 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2811 LLVMValueRef *values)
2812 {
2813 struct ac_export_args args;
2814
2815 si_llvm_init_export_args(ctx, values,
2816 V_008DFC_SQ_EXP_PARAM + index, &args);
2817 ac_build_export(&ctx->ac, &args);
2818 }
2819
2820 static void si_build_param_exports(struct si_shader_context *ctx,
2821 struct si_shader_output_values *outputs,
2822 unsigned noutput)
2823 {
2824 struct si_shader *shader = ctx->shader;
2825 unsigned param_count = 0;
2826
2827 for (unsigned i = 0; i < noutput; i++) {
2828 unsigned semantic_name = outputs[i].semantic_name;
2829 unsigned semantic_index = outputs[i].semantic_index;
2830
2831 if (outputs[i].vertex_stream[0] != 0 &&
2832 outputs[i].vertex_stream[1] != 0 &&
2833 outputs[i].vertex_stream[2] != 0 &&
2834 outputs[i].vertex_stream[3] != 0)
2835 continue;
2836
2837 switch (semantic_name) {
2838 case TGSI_SEMANTIC_LAYER:
2839 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2840 case TGSI_SEMANTIC_CLIPDIST:
2841 case TGSI_SEMANTIC_COLOR:
2842 case TGSI_SEMANTIC_BCOLOR:
2843 case TGSI_SEMANTIC_PRIMID:
2844 case TGSI_SEMANTIC_FOG:
2845 case TGSI_SEMANTIC_TEXCOORD:
2846 case TGSI_SEMANTIC_GENERIC:
2847 break;
2848 default:
2849 continue;
2850 }
2851
2852 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2853 semantic_index < SI_MAX_IO_GENERIC) &&
2854 shader->key.opt.kill_outputs &
2855 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2856 continue;
2857
2858 si_export_param(ctx, param_count, outputs[i].values);
2859
2860 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2861 shader->info.vs_output_param_offset[i] = param_count++;
2862 }
2863
2864 shader->info.nr_param_exports = param_count;
2865 }
2866
2867 /* Generate export instructions for hardware VS shader stage */
2868 static void si_llvm_export_vs(struct si_shader_context *ctx,
2869 struct si_shader_output_values *outputs,
2870 unsigned noutput)
2871 {
2872 struct si_shader *shader = ctx->shader;
2873 struct ac_export_args pos_args[4] = {};
2874 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2875 unsigned pos_idx;
2876 int i;
2877
2878 /* Build position exports. */
2879 for (i = 0; i < noutput; i++) {
2880 switch (outputs[i].semantic_name) {
2881 case TGSI_SEMANTIC_POSITION:
2882 si_llvm_init_export_args(ctx, outputs[i].values,
2883 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2884 break;
2885 case TGSI_SEMANTIC_PSIZE:
2886 psize_value = outputs[i].values[0];
2887 break;
2888 case TGSI_SEMANTIC_LAYER:
2889 layer_value = outputs[i].values[0];
2890 break;
2891 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2892 viewport_index_value = outputs[i].values[0];
2893 break;
2894 case TGSI_SEMANTIC_EDGEFLAG:
2895 edgeflag_value = outputs[i].values[0];
2896 break;
2897 case TGSI_SEMANTIC_CLIPDIST:
2898 if (!shader->key.opt.clip_disable) {
2899 unsigned index = 2 + outputs[i].semantic_index;
2900 si_llvm_init_export_args(ctx, outputs[i].values,
2901 V_008DFC_SQ_EXP_POS + index,
2902 &pos_args[index]);
2903 }
2904 break;
2905 case TGSI_SEMANTIC_CLIPVERTEX:
2906 if (!shader->key.opt.clip_disable) {
2907 si_llvm_emit_clipvertex(ctx, pos_args,
2908 outputs[i].values);
2909 }
2910 break;
2911 }
2912 }
2913
2914 /* We need to add the position output manually if it's missing. */
2915 if (!pos_args[0].out[0]) {
2916 pos_args[0].enabled_channels = 0xf; /* writemask */
2917 pos_args[0].valid_mask = 0; /* EXEC mask */
2918 pos_args[0].done = 0; /* last export? */
2919 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2920 pos_args[0].compr = 0; /* COMPR flag */
2921 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2922 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2923 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2924 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2925 }
2926
2927 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2928 if (shader->selector->info.writes_psize ||
2929 shader->selector->info.writes_edgeflag ||
2930 shader->selector->info.writes_viewport_index ||
2931 shader->selector->info.writes_layer) {
2932 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2933 (shader->selector->info.writes_edgeflag << 1) |
2934 (shader->selector->info.writes_layer << 2);
2935
2936 pos_args[1].valid_mask = 0; /* EXEC mask */
2937 pos_args[1].done = 0; /* last export? */
2938 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2939 pos_args[1].compr = 0; /* COMPR flag */
2940 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2941 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2942 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2943 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2944
2945 if (shader->selector->info.writes_psize)
2946 pos_args[1].out[0] = psize_value;
2947
2948 if (shader->selector->info.writes_edgeflag) {
2949 /* The output is a float, but the hw expects an integer
2950 * with the first bit containing the edge flag. */
2951 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2952 edgeflag_value,
2953 ctx->i32, "");
2954 edgeflag_value = ac_build_umin(&ctx->ac,
2955 edgeflag_value,
2956 ctx->i32_1);
2957
2958 /* The LLVM intrinsic expects a float. */
2959 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2960 }
2961
2962 if (ctx->screen->info.chip_class >= GFX9) {
2963 /* GFX9 has the layer in out.z[10:0] and the viewport
2964 * index in out.z[19:16].
2965 */
2966 if (shader->selector->info.writes_layer)
2967 pos_args[1].out[2] = layer_value;
2968
2969 if (shader->selector->info.writes_viewport_index) {
2970 LLVMValueRef v = viewport_index_value;
2971
2972 v = ac_to_integer(&ctx->ac, v);
2973 v = LLVMBuildShl(ctx->ac.builder, v,
2974 LLVMConstInt(ctx->i32, 16, 0), "");
2975 v = LLVMBuildOr(ctx->ac.builder, v,
2976 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2977 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2978 pos_args[1].enabled_channels |= 1 << 2;
2979 }
2980 } else {
2981 if (shader->selector->info.writes_layer)
2982 pos_args[1].out[2] = layer_value;
2983
2984 if (shader->selector->info.writes_viewport_index) {
2985 pos_args[1].out[3] = viewport_index_value;
2986 pos_args[1].enabled_channels |= 1 << 3;
2987 }
2988 }
2989 }
2990
2991 for (i = 0; i < 4; i++)
2992 if (pos_args[i].out[0])
2993 shader->info.nr_pos_exports++;
2994
2995 pos_idx = 0;
2996 for (i = 0; i < 4; i++) {
2997 if (!pos_args[i].out[0])
2998 continue;
2999
3000 /* Specify the target we are exporting */
3001 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
3002
3003 if (pos_idx == shader->info.nr_pos_exports)
3004 /* Specify that this is the last export */
3005 pos_args[i].done = 1;
3006
3007 ac_build_export(&ctx->ac, &pos_args[i]);
3008 }
3009
3010 /* Build parameter exports. */
3011 si_build_param_exports(ctx, outputs, noutput);
3012 }
3013
3014 /**
3015 * Forward all outputs from the vertex shader to the TES. This is only used
3016 * for the fixed function TCS.
3017 */
3018 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
3019 {
3020 struct si_shader_context *ctx = si_shader_context(bld_base);
3021 LLVMValueRef invocation_id, buffer, buffer_offset;
3022 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
3023 uint64_t inputs;
3024
3025 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3026 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3027 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3028
3029 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
3030 lds_vertex_offset = LLVMBuildMul(ctx->ac.builder, invocation_id,
3031 lds_vertex_stride, "");
3032 lds_base = get_tcs_in_current_patch_offset(ctx);
3033 lds_base = LLVMBuildAdd(ctx->ac.builder, lds_base, lds_vertex_offset, "");
3034
3035 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
3036 while (inputs) {
3037 unsigned i = u_bit_scan64(&inputs);
3038
3039 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
3040 LLVMConstInt(ctx->i32, 4 * i, 0),
3041 "");
3042
3043 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
3044 get_rel_patch_id(ctx),
3045 invocation_id,
3046 LLVMConstInt(ctx->i32, i, 0));
3047
3048 LLVMValueRef value = lds_load(bld_base, ctx->ac.i32, ~0,
3049 lds_ptr);
3050
3051 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
3052 buffer_offset, 0, 1, 0, true, false);
3053 }
3054 }
3055
3056 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
3057 LLVMValueRef rel_patch_id,
3058 LLVMValueRef invocation_id,
3059 LLVMValueRef tcs_out_current_patch_data_offset,
3060 LLVMValueRef invoc0_tf_outer[4],
3061 LLVMValueRef invoc0_tf_inner[2])
3062 {
3063 struct si_shader_context *ctx = si_shader_context(bld_base);
3064 struct si_shader *shader = ctx->shader;
3065 unsigned tess_inner_index, tess_outer_index;
3066 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
3067 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3068 unsigned stride, outer_comps, inner_comps, i, offset;
3069 struct lp_build_if_state if_ctx, inner_if_ctx;
3070
3071 /* Add a barrier before loading tess factors from LDS. */
3072 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
3073 si_llvm_emit_barrier(NULL, bld_base, NULL);
3074
3075 /* Do this only for invocation 0, because the tess levels are per-patch,
3076 * not per-vertex.
3077 *
3078 * This can't jump, because invocation 0 executes this. It should
3079 * at least mask out the loads and stores for other invocations.
3080 */
3081 lp_build_if(&if_ctx, &ctx->gallivm,
3082 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3083 invocation_id, ctx->i32_0, ""));
3084
3085 /* Determine the layout of one tess factor element in the buffer. */
3086 switch (shader->key.part.tcs.epilog.prim_mode) {
3087 case PIPE_PRIM_LINES:
3088 stride = 2; /* 2 dwords, 1 vec2 store */
3089 outer_comps = 2;
3090 inner_comps = 0;
3091 break;
3092 case PIPE_PRIM_TRIANGLES:
3093 stride = 4; /* 4 dwords, 1 vec4 store */
3094 outer_comps = 3;
3095 inner_comps = 1;
3096 break;
3097 case PIPE_PRIM_QUADS:
3098 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3099 outer_comps = 4;
3100 inner_comps = 2;
3101 break;
3102 default:
3103 assert(0);
3104 return;
3105 }
3106
3107 for (i = 0; i < 4; i++) {
3108 inner[i] = LLVMGetUndef(ctx->i32);
3109 outer[i] = LLVMGetUndef(ctx->i32);
3110 }
3111
3112 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3113 /* Tess factors are in VGPRs. */
3114 for (i = 0; i < outer_comps; i++)
3115 outer[i] = out[i] = invoc0_tf_outer[i];
3116 for (i = 0; i < inner_comps; i++)
3117 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3118 } else {
3119 /* Load tess_inner and tess_outer from LDS.
3120 * Any invocation can write them, so we can't get them from a temporary.
3121 */
3122 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3123 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3124
3125 lds_base = tcs_out_current_patch_data_offset;
3126 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3127 LLVMConstInt(ctx->i32,
3128 tess_inner_index * 4, 0), "");
3129 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3130 LLVMConstInt(ctx->i32,
3131 tess_outer_index * 4, 0), "");
3132
3133 for (i = 0; i < outer_comps; i++) {
3134 outer[i] = out[i] =
3135 lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3136 }
3137 for (i = 0; i < inner_comps; i++) {
3138 inner[i] = out[outer_comps+i] =
3139 lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3140 }
3141 }
3142
3143 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3144 /* For isolines, the hardware expects tess factors in the
3145 * reverse order from what GLSL / TGSI specify.
3146 */
3147 LLVMValueRef tmp = out[0];
3148 out[0] = out[1];
3149 out[1] = tmp;
3150 }
3151
3152 /* Convert the outputs to vectors for stores. */
3153 vec0 = lp_build_gather_values(&ctx->gallivm, out, MIN2(stride, 4));
3154 vec1 = NULL;
3155
3156 if (stride > 4)
3157 vec1 = lp_build_gather_values(&ctx->gallivm, out+4, stride - 4);
3158
3159 /* Get the buffer. */
3160 buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
3161
3162 /* Get the offset. */
3163 tf_base = LLVMGetParam(ctx->main_fn,
3164 ctx->param_tcs_factor_offset);
3165 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3166 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3167
3168 lp_build_if(&inner_if_ctx, &ctx->gallivm,
3169 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3170 rel_patch_id, ctx->i32_0, ""));
3171
3172 /* Store the dynamic HS control word. */
3173 offset = 0;
3174 if (ctx->screen->info.chip_class <= VI) {
3175 ac_build_buffer_store_dword(&ctx->ac, buffer,
3176 LLVMConstInt(ctx->i32, 0x80000000, 0),
3177 1, ctx->i32_0, tf_base,
3178 offset, 1, 0, true, false);
3179 offset += 4;
3180 }
3181
3182 lp_build_endif(&inner_if_ctx);
3183
3184 /* Store the tessellation factors. */
3185 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3186 MIN2(stride, 4), byteoffset, tf_base,
3187 offset, 1, 0, true, false);
3188 offset += 16;
3189 if (vec1)
3190 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3191 stride - 4, byteoffset, tf_base,
3192 offset, 1, 0, true, false);
3193
3194 /* Store the tess factors into the offchip buffer if TES reads them. */
3195 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3196 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3197 LLVMValueRef tf_inner_offset;
3198 unsigned param_outer, param_inner;
3199
3200 buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3201 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3202
3203 param_outer = si_shader_io_get_unique_index_patch(
3204 TGSI_SEMANTIC_TESSOUTER, 0);
3205 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3206 LLVMConstInt(ctx->i32, param_outer, 0));
3207
3208 outer_vec = lp_build_gather_values(&ctx->gallivm, outer,
3209 util_next_power_of_two(outer_comps));
3210
3211 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3212 outer_comps, tf_outer_offset,
3213 base, 0, 1, 0, true, false);
3214 if (inner_comps) {
3215 param_inner = si_shader_io_get_unique_index_patch(
3216 TGSI_SEMANTIC_TESSINNER, 0);
3217 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3218 LLVMConstInt(ctx->i32, param_inner, 0));
3219
3220 inner_vec = inner_comps == 1 ? inner[0] :
3221 lp_build_gather_values(&ctx->gallivm, inner, inner_comps);
3222 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3223 inner_comps, tf_inner_offset,
3224 base, 0, 1, 0, true, false);
3225 }
3226 }
3227
3228 lp_build_endif(&if_ctx);
3229 }
3230
3231 static LLVMValueRef
3232 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3233 unsigned param, unsigned return_index)
3234 {
3235 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3236 LLVMGetParam(ctx->main_fn, param),
3237 return_index, "");
3238 }
3239
3240 static LLVMValueRef
3241 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3242 unsigned param, unsigned return_index)
3243 {
3244 LLVMBuilderRef builder = ctx->ac.builder;
3245 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3246
3247 return LLVMBuildInsertValue(builder, ret,
3248 ac_to_float(&ctx->ac, p),
3249 return_index, "");
3250 }
3251
3252 static LLVMValueRef
3253 si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret,
3254 unsigned param, unsigned return_index)
3255 {
3256 LLVMBuilderRef builder = ctx->ac.builder;
3257 LLVMValueRef ptr, lo, hi;
3258
3259 if (HAVE_32BIT_POINTERS) {
3260 ptr = LLVMGetParam(ctx->main_fn, param);
3261 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i32, "");
3262 return LLVMBuildInsertValue(builder, ret, ptr, return_index, "");
3263 }
3264
3265 ptr = LLVMGetParam(ctx->main_fn, param);
3266 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
3267 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
3268 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
3269 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
3270 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
3271 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
3272 }
3273
3274 /* This only writes the tessellation factor levels. */
3275 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
3276 unsigned max_outputs,
3277 LLVMValueRef *addrs)
3278 {
3279 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3280 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
3281 LLVMBuilderRef builder = ctx->ac.builder;
3282 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3283
3284 si_copy_tcs_inputs(bld_base);
3285
3286 rel_patch_id = get_rel_patch_id(ctx);
3287 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3288 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3289
3290 if (ctx->screen->info.chip_class >= GFX9) {
3291 LLVMBasicBlockRef blocks[2] = {
3292 LLVMGetInsertBlock(builder),
3293 ctx->merged_wrap_if_state.entry_block
3294 };
3295 LLVMValueRef values[2];
3296
3297 lp_build_endif(&ctx->merged_wrap_if_state);
3298
3299 values[0] = rel_patch_id;
3300 values[1] = LLVMGetUndef(ctx->i32);
3301 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3302
3303 values[0] = tf_lds_offset;
3304 values[1] = LLVMGetUndef(ctx->i32);
3305 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3306
3307 values[0] = invocation_id;
3308 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3309 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3310 }
3311
3312 /* Return epilog parameters from this function. */
3313 LLVMValueRef ret = ctx->return_value;
3314 unsigned vgpr;
3315
3316 if (ctx->screen->info.chip_class >= GFX9) {
3317 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3318 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3319 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3320 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3321 /* Tess offchip and tess factor offsets are at the beginning. */
3322 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3323 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3324 vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
3325 } else {
3326 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3327 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3328 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3329 GFX6_SGPR_TCS_OUT_LAYOUT);
3330 /* Tess offchip and tess factor offsets are after user SGPRs. */
3331 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3332 GFX6_TCS_NUM_USER_SGPR);
3333 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3334 GFX6_TCS_NUM_USER_SGPR + 1);
3335 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3336 }
3337
3338 /* VGPRs */
3339 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3340 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3341 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3342
3343 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3344 * the invocation_id output does not alias the tcs_rel_ids input,
3345 * which saves a V_MOV on gfx9.
3346 */
3347 vgpr += 2;
3348
3349 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3350 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3351
3352 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3353 vgpr++; /* skip the tess factor LDS offset */
3354 for (unsigned i = 0; i < 6; i++) {
3355 LLVMValueRef value =
3356 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3357 value = ac_to_float(&ctx->ac, value);
3358 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3359 }
3360 } else {
3361 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3362 }
3363 ctx->return_value = ret;
3364 }
3365
3366 /* Pass TCS inputs from LS to TCS on GFX9. */
3367 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3368 {
3369 LLVMValueRef ret = ctx->return_value;
3370
3371 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3372 if (HAVE_32BIT_POINTERS)
3373 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3374 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3375 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3376 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3377 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3378
3379 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3380 8 + SI_SGPR_RW_BUFFERS);
3381 ret = si_insert_input_ptr(ctx, ret,
3382 ctx->param_bindless_samplers_and_images,
3383 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3384
3385 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3386 8 + SI_SGPR_VS_STATE_BITS);
3387
3388 #if !HAVE_32BIT_POINTERS
3389 ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 1,
3390 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
3391 #endif
3392
3393 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3394 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3395 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3396 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3397 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3398 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3399
3400 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3401 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3402 ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
3403 vgpr++, "");
3404 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3405 ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
3406 vgpr++, "");
3407 ctx->return_value = ret;
3408 }
3409
3410 /* Pass GS inputs from ES to GS on GFX9. */
3411 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3412 {
3413 LLVMValueRef ret = ctx->return_value;
3414
3415 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3416 if (HAVE_32BIT_POINTERS)
3417 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3418 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3419 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3420 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3421
3422 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3423 8 + SI_SGPR_RW_BUFFERS);
3424 ret = si_insert_input_ptr(ctx, ret,
3425 ctx->param_bindless_samplers_and_images,
3426 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3427
3428 #if !HAVE_32BIT_POINTERS
3429 ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 1,
3430 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
3431 #endif
3432
3433 unsigned vgpr;
3434 if (ctx->type == PIPE_SHADER_VERTEX)
3435 vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
3436 else
3437 vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
3438
3439 for (unsigned i = 0; i < 5; i++) {
3440 unsigned param = ctx->param_gs_vtx01_offset + i;
3441 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3442 }
3443 ctx->return_value = ret;
3444 }
3445
3446 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3447 unsigned max_outputs,
3448 LLVMValueRef *addrs)
3449 {
3450 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3451 struct si_shader *shader = ctx->shader;
3452 struct tgsi_shader_info *info = &shader->selector->info;
3453 unsigned i, chan;
3454 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3455 ctx->param_rel_auto_id);
3456 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3457 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3458 vertex_dw_stride, "");
3459
3460 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3461 * its inputs from it. */
3462 for (i = 0; i < info->num_outputs; i++) {
3463 unsigned name = info->output_semantic_name[i];
3464 unsigned index = info->output_semantic_index[i];
3465
3466 /* The ARB_shader_viewport_layer_array spec contains the
3467 * following issue:
3468 *
3469 * 2) What happens if gl_ViewportIndex or gl_Layer is
3470 * written in the vertex shader and a geometry shader is
3471 * present?
3472 *
3473 * RESOLVED: The value written by the last vertex processing
3474 * stage is used. If the last vertex processing stage
3475 * (vertex, tessellation evaluation or geometry) does not
3476 * statically assign to gl_ViewportIndex or gl_Layer, index
3477 * or layer zero is assumed.
3478 *
3479 * So writes to those outputs in VS-as-LS are simply ignored.
3480 */
3481 if (name == TGSI_SEMANTIC_LAYER ||
3482 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3483 continue;
3484
3485 int param = si_shader_io_get_unique_index(name, index);
3486 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3487 LLVMConstInt(ctx->i32, param * 4, 0), "");
3488
3489 for (chan = 0; chan < 4; chan++) {
3490 if (!(info->output_usagemask[i] & (1 << chan)))
3491 continue;
3492
3493 lds_store(ctx, chan, dw_addr,
3494 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3495 }
3496 }
3497
3498 if (ctx->screen->info.chip_class >= GFX9)
3499 si_set_ls_return_value_for_tcs(ctx);
3500 }
3501
3502 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3503 unsigned max_outputs,
3504 LLVMValueRef *addrs)
3505 {
3506 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3507 struct si_shader *es = ctx->shader;
3508 struct tgsi_shader_info *info = &es->selector->info;
3509 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3510 ctx->param_es2gs_offset);
3511 LLVMValueRef lds_base = NULL;
3512 unsigned chan;
3513 int i;
3514
3515 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3516 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3517 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3518 LLVMValueRef wave_idx = unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3519 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3520 LLVMBuildMul(ctx->ac.builder, wave_idx,
3521 LLVMConstInt(ctx->i32, 64, false), ""), "");
3522 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3523 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3524 }
3525
3526 for (i = 0; i < info->num_outputs; i++) {
3527 int param;
3528
3529 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3530 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3531 continue;
3532
3533 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3534 info->output_semantic_index[i]);
3535
3536 for (chan = 0; chan < 4; chan++) {
3537 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3538 out_val = ac_to_integer(&ctx->ac, out_val);
3539
3540 /* GFX9 has the ESGS ring in LDS. */
3541 if (ctx->screen->info.chip_class >= GFX9) {
3542 lds_store(ctx, param * 4 + chan, lds_base, out_val);
3543 continue;
3544 }
3545
3546 ac_build_buffer_store_dword(&ctx->ac,
3547 ctx->esgs_ring,
3548 out_val, 1, NULL, soffset,
3549 (4 * param + chan) * 4,
3550 1, 1, true, true);
3551 }
3552 }
3553
3554 if (ctx->screen->info.chip_class >= GFX9)
3555 si_set_es_return_value_for_gs(ctx);
3556 }
3557
3558 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3559 {
3560 if (ctx->screen->info.chip_class >= GFX9)
3561 return unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3562 else
3563 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3564 }
3565
3566 static void emit_gs_epilogue(struct si_shader_context *ctx)
3567 {
3568 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3569 si_get_gs_wave_id(ctx));
3570
3571 if (ctx->screen->info.chip_class >= GFX9)
3572 lp_build_endif(&ctx->merged_wrap_if_state);
3573 }
3574
3575 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3576 unsigned max_outputs,
3577 LLVMValueRef *addrs)
3578 {
3579 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3580 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3581
3582 assert(info->num_outputs <= max_outputs);
3583
3584 emit_gs_epilogue(ctx);
3585 }
3586
3587 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3588 {
3589 struct si_shader_context *ctx = si_shader_context(bld_base);
3590 emit_gs_epilogue(ctx);
3591 }
3592
3593 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3594 unsigned max_outputs,
3595 LLVMValueRef *addrs)
3596 {
3597 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3598 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3599 struct si_shader_output_values *outputs = NULL;
3600 int i,j;
3601
3602 assert(!ctx->shader->is_gs_copy_shader);
3603 assert(info->num_outputs <= max_outputs);
3604
3605 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3606
3607 /* Vertex color clamping.
3608 *
3609 * This uses a state constant loaded in a user data SGPR and
3610 * an IF statement is added that clamps all colors if the constant
3611 * is true.
3612 */
3613 if (ctx->type == PIPE_SHADER_VERTEX) {
3614 struct lp_build_if_state if_ctx;
3615 LLVMValueRef cond = NULL;
3616 LLVMValueRef addr, val;
3617
3618 for (i = 0; i < info->num_outputs; i++) {
3619 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3620 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3621 continue;
3622
3623 /* We've found a color. */
3624 if (!cond) {
3625 /* The state is in the first bit of the user SGPR. */
3626 cond = LLVMGetParam(ctx->main_fn,
3627 ctx->param_vs_state_bits);
3628 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3629 ctx->i1, "");
3630 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3631 }
3632
3633 for (j = 0; j < 4; j++) {
3634 addr = addrs[4 * i + j];
3635 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3636 val = ac_build_clamp(&ctx->ac, val);
3637 LLVMBuildStore(ctx->ac.builder, val, addr);
3638 }
3639 }
3640
3641 if (cond)
3642 lp_build_endif(&if_ctx);
3643 }
3644
3645 for (i = 0; i < info->num_outputs; i++) {
3646 outputs[i].semantic_name = info->output_semantic_name[i];
3647 outputs[i].semantic_index = info->output_semantic_index[i];
3648
3649 for (j = 0; j < 4; j++) {
3650 outputs[i].values[j] =
3651 LLVMBuildLoad(ctx->ac.builder,
3652 addrs[4 * i + j],
3653 "");
3654 outputs[i].vertex_stream[j] =
3655 (info->output_streams[i] >> (2 * j)) & 3;
3656 }
3657 }
3658
3659 if (ctx->shader->selector->so.num_outputs)
3660 si_llvm_emit_streamout(ctx, outputs, i, 0);
3661
3662 /* Export PrimitiveID. */
3663 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3664 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3665 outputs[i].semantic_index = 0;
3666 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3667 for (j = 1; j < 4; j++)
3668 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3669
3670 memset(outputs[i].vertex_stream, 0,
3671 sizeof(outputs[i].vertex_stream));
3672 i++;
3673 }
3674
3675 si_llvm_export_vs(ctx, outputs, i);
3676 FREE(outputs);
3677 }
3678
3679 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3680 {
3681 struct si_shader_context *ctx = si_shader_context(bld_base);
3682
3683 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3684 &ctx->outputs[0][0]);
3685 }
3686
3687 struct si_ps_exports {
3688 unsigned num;
3689 struct ac_export_args args[10];
3690 };
3691
3692 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3693 LLVMValueRef depth, LLVMValueRef stencil,
3694 LLVMValueRef samplemask, struct si_ps_exports *exp)
3695 {
3696 struct si_shader_context *ctx = si_shader_context(bld_base);
3697 struct ac_export_args args;
3698
3699 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3700
3701 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3702 }
3703
3704 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3705 LLVMValueRef *color, unsigned index,
3706 unsigned samplemask_param,
3707 bool is_last, struct si_ps_exports *exp)
3708 {
3709 struct si_shader_context *ctx = si_shader_context(bld_base);
3710 int i;
3711
3712 /* Clamp color */
3713 if (ctx->shader->key.part.ps.epilog.clamp_color)
3714 for (i = 0; i < 4; i++)
3715 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3716
3717 /* Alpha to one */
3718 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3719 color[3] = ctx->ac.f32_1;
3720
3721 /* Alpha test */
3722 if (index == 0 &&
3723 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3724 si_alpha_test(bld_base, color[3]);
3725
3726 /* Line & polygon smoothing */
3727 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3728 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3729 samplemask_param);
3730
3731 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3732 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3733 struct ac_export_args args[8];
3734 int c, last = -1;
3735
3736 /* Get the export arguments, also find out what the last one is. */
3737 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3738 si_llvm_init_export_args(ctx, color,
3739 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3740 if (args[c].enabled_channels)
3741 last = c;
3742 }
3743
3744 /* Emit all exports. */
3745 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3746 if (is_last && last == c) {
3747 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3748 args[c].done = 1; /* DONE bit */
3749 } else if (!args[c].enabled_channels)
3750 continue; /* unnecessary NULL export */
3751
3752 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3753 }
3754 } else {
3755 struct ac_export_args args;
3756
3757 /* Export */
3758 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3759 &args);
3760 if (is_last) {
3761 args.valid_mask = 1; /* whether the EXEC mask is valid */
3762 args.done = 1; /* DONE bit */
3763 } else if (!args.enabled_channels)
3764 return; /* unnecessary NULL export */
3765
3766 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3767 }
3768 }
3769
3770 static void si_emit_ps_exports(struct si_shader_context *ctx,
3771 struct si_ps_exports *exp)
3772 {
3773 for (unsigned i = 0; i < exp->num; i++)
3774 ac_build_export(&ctx->ac, &exp->args[i]);
3775 }
3776
3777 /**
3778 * Return PS outputs in this order:
3779 *
3780 * v[0:3] = color0.xyzw
3781 * v[4:7] = color1.xyzw
3782 * ...
3783 * vN+0 = Depth
3784 * vN+1 = Stencil
3785 * vN+2 = SampleMask
3786 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3787 *
3788 * The alpha-ref SGPR is returned via its original location.
3789 */
3790 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3791 unsigned max_outputs,
3792 LLVMValueRef *addrs)
3793 {
3794 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3795 struct si_shader *shader = ctx->shader;
3796 struct tgsi_shader_info *info = &shader->selector->info;
3797 LLVMBuilderRef builder = ctx->ac.builder;
3798 unsigned i, j, first_vgpr, vgpr;
3799
3800 LLVMValueRef color[8][4] = {};
3801 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3802 LLVMValueRef ret;
3803
3804 if (ctx->postponed_kill)
3805 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3806
3807 /* Read the output values. */
3808 for (i = 0; i < info->num_outputs; i++) {
3809 unsigned semantic_name = info->output_semantic_name[i];
3810 unsigned semantic_index = info->output_semantic_index[i];
3811
3812 switch (semantic_name) {
3813 case TGSI_SEMANTIC_COLOR:
3814 assert(semantic_index < 8);
3815 for (j = 0; j < 4; j++) {
3816 LLVMValueRef ptr = addrs[4 * i + j];
3817 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3818 color[semantic_index][j] = result;
3819 }
3820 break;
3821 case TGSI_SEMANTIC_POSITION:
3822 depth = LLVMBuildLoad(builder,
3823 addrs[4 * i + 2], "");
3824 break;
3825 case TGSI_SEMANTIC_STENCIL:
3826 stencil = LLVMBuildLoad(builder,
3827 addrs[4 * i + 1], "");
3828 break;
3829 case TGSI_SEMANTIC_SAMPLEMASK:
3830 samplemask = LLVMBuildLoad(builder,
3831 addrs[4 * i + 0], "");
3832 break;
3833 default:
3834 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3835 semantic_name);
3836 }
3837 }
3838
3839 /* Fill the return structure. */
3840 ret = ctx->return_value;
3841
3842 /* Set SGPRs. */
3843 ret = LLVMBuildInsertValue(builder, ret,
3844 ac_to_integer(&ctx->ac,
3845 LLVMGetParam(ctx->main_fn,
3846 SI_PARAM_ALPHA_REF)),
3847 SI_SGPR_ALPHA_REF, "");
3848
3849 /* Set VGPRs */
3850 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3851 for (i = 0; i < ARRAY_SIZE(color); i++) {
3852 if (!color[i][0])
3853 continue;
3854
3855 for (j = 0; j < 4; j++)
3856 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3857 }
3858 if (depth)
3859 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3860 if (stencil)
3861 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3862 if (samplemask)
3863 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3864
3865 /* Add the input sample mask for smoothing at the end. */
3866 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3867 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3868 ret = LLVMBuildInsertValue(builder, ret,
3869 LLVMGetParam(ctx->main_fn,
3870 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3871
3872 ctx->return_value = ret;
3873 }
3874
3875 static void membar_emit(
3876 const struct lp_build_tgsi_action *action,
3877 struct lp_build_tgsi_context *bld_base,
3878 struct lp_build_emit_data *emit_data)
3879 {
3880 struct si_shader_context *ctx = si_shader_context(bld_base);
3881 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3882 unsigned flags = LLVMConstIntGetZExtValue(src0);
3883 unsigned waitcnt = NOOP_WAITCNT;
3884
3885 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3886 waitcnt &= VM_CNT & LGKM_CNT;
3887
3888 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3889 TGSI_MEMBAR_SHADER_BUFFER |
3890 TGSI_MEMBAR_SHADER_IMAGE))
3891 waitcnt &= VM_CNT;
3892
3893 if (flags & TGSI_MEMBAR_SHARED)
3894 waitcnt &= LGKM_CNT;
3895
3896 if (waitcnt != NOOP_WAITCNT)
3897 ac_build_waitcnt(&ctx->ac, waitcnt);
3898 }
3899
3900 static void clock_emit(
3901 const struct lp_build_tgsi_action *action,
3902 struct lp_build_tgsi_context *bld_base,
3903 struct lp_build_emit_data *emit_data)
3904 {
3905 struct si_shader_context *ctx = si_shader_context(bld_base);
3906 LLVMValueRef tmp = ac_build_shader_clock(&ctx->ac);
3907
3908 emit_data->output[0] =
3909 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3910 emit_data->output[1] =
3911 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3912 }
3913
3914 static void si_llvm_emit_ddxy(
3915 const struct lp_build_tgsi_action *action,
3916 struct lp_build_tgsi_context *bld_base,
3917 struct lp_build_emit_data *emit_data)
3918 {
3919 struct si_shader_context *ctx = si_shader_context(bld_base);
3920 unsigned opcode = emit_data->info->opcode;
3921 LLVMValueRef val;
3922 int idx;
3923 unsigned mask;
3924
3925 if (opcode == TGSI_OPCODE_DDX_FINE)
3926 mask = AC_TID_MASK_LEFT;
3927 else if (opcode == TGSI_OPCODE_DDY_FINE)
3928 mask = AC_TID_MASK_TOP;
3929 else
3930 mask = AC_TID_MASK_TOP_LEFT;
3931
3932 /* for DDX we want to next X pixel, DDY next Y pixel. */
3933 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3934
3935 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3936 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3937 emit_data->output[emit_data->chan] = val;
3938 }
3939
3940 /*
3941 * this takes an I,J coordinate pair,
3942 * and works out the X and Y derivatives.
3943 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3944 */
3945 static LLVMValueRef si_llvm_emit_ddxy_interp(
3946 struct lp_build_tgsi_context *bld_base,
3947 LLVMValueRef interp_ij)
3948 {
3949 struct si_shader_context *ctx = si_shader_context(bld_base);
3950 LLVMValueRef result[4], a;
3951 unsigned i;
3952
3953 for (i = 0; i < 2; i++) {
3954 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
3955 LLVMConstInt(ctx->i32, i, 0), "");
3956 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
3957 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
3958 }
3959
3960 return lp_build_gather_values(&ctx->gallivm, result, 4);
3961 }
3962
3963 static void interp_fetch_args(
3964 struct lp_build_tgsi_context *bld_base,
3965 struct lp_build_emit_data *emit_data)
3966 {
3967 struct si_shader_context *ctx = si_shader_context(bld_base);
3968 const struct tgsi_full_instruction *inst = emit_data->inst;
3969
3970 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3971 /* offset is in second src, first two channels */
3972 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3973 emit_data->inst, 1,
3974 TGSI_CHAN_X);
3975 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3976 emit_data->inst, 1,
3977 TGSI_CHAN_Y);
3978 emit_data->arg_count = 2;
3979 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3980 LLVMValueRef sample_position;
3981 LLVMValueRef sample_id;
3982 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3983
3984 /* fetch sample ID, then fetch its sample position,
3985 * and place into first two channels.
3986 */
3987 sample_id = lp_build_emit_fetch(bld_base,
3988 emit_data->inst, 1, TGSI_CHAN_X);
3989 sample_id = ac_to_integer(&ctx->ac, sample_id);
3990
3991 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
3992 * Language 4.50 spec says about interpolateAtSample:
3993 *
3994 * "Returns the value of the input interpolant variable at
3995 * the location of sample number sample. If multisample
3996 * buffers are not available, the input variable will be
3997 * evaluated at the center of the pixel. If sample sample
3998 * does not exist, the position used to interpolate the
3999 * input variable is undefined."
4000 *
4001 * This means that sample_id values outside of the valid are
4002 * in fact valid input, and the usual mechanism for loading the
4003 * sample position doesn't work.
4004 */
4005 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
4006 LLVMValueRef center[4] = {
4007 LLVMConstReal(ctx->f32, 0.5),
4008 LLVMConstReal(ctx->f32, 0.5),
4009 ctx->ac.f32_0,
4010 ctx->ac.f32_0,
4011 };
4012
4013 sample_position = lp_build_gather_values(&ctx->gallivm, center, 4);
4014 } else {
4015 sample_position = load_sample_position(&ctx->abi, sample_id);
4016 }
4017
4018 emit_data->args[0] = LLVMBuildExtractElement(ctx->ac.builder,
4019 sample_position,
4020 ctx->i32_0, "");
4021
4022 emit_data->args[0] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[0], halfval, "");
4023 emit_data->args[1] = LLVMBuildExtractElement(ctx->ac.builder,
4024 sample_position,
4025 ctx->i32_1, "");
4026 emit_data->args[1] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[1], halfval, "");
4027 emit_data->arg_count = 2;
4028 }
4029 }
4030
4031 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
4032 struct lp_build_tgsi_context *bld_base,
4033 struct lp_build_emit_data *emit_data)
4034 {
4035 struct si_shader_context *ctx = si_shader_context(bld_base);
4036 struct si_shader *shader = ctx->shader;
4037 const struct tgsi_shader_info *info = &shader->selector->info;
4038 LLVMValueRef interp_param;
4039 const struct tgsi_full_instruction *inst = emit_data->inst;
4040 const struct tgsi_full_src_register *input = &inst->Src[0];
4041 int input_base, input_array_size;
4042 int chan;
4043 int i;
4044 LLVMValueRef prim_mask = ctx->abi.prim_mask;
4045 LLVMValueRef array_idx;
4046 int interp_param_idx;
4047 unsigned interp;
4048 unsigned location;
4049
4050 assert(input->Register.File == TGSI_FILE_INPUT);
4051
4052 if (input->Register.Indirect) {
4053 unsigned array_id = input->Indirect.ArrayID;
4054
4055 if (array_id) {
4056 input_base = info->input_array_first[array_id];
4057 input_array_size = info->input_array_last[array_id] - input_base + 1;
4058 } else {
4059 input_base = inst->Src[0].Register.Index;
4060 input_array_size = info->num_inputs - input_base;
4061 }
4062
4063 array_idx = si_get_indirect_index(ctx, &input->Indirect,
4064 1, input->Register.Index - input_base);
4065 } else {
4066 input_base = inst->Src[0].Register.Index;
4067 input_array_size = 1;
4068 array_idx = ctx->i32_0;
4069 }
4070
4071 interp = shader->selector->info.input_interpolate[input_base];
4072
4073 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4074 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4075 location = TGSI_INTERPOLATE_LOC_CENTER;
4076 else
4077 location = TGSI_INTERPOLATE_LOC_CENTROID;
4078
4079 interp_param_idx = lookup_interp_param_index(interp, location);
4080 if (interp_param_idx == -1)
4081 return;
4082 else if (interp_param_idx)
4083 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4084 else
4085 interp_param = NULL;
4086
4087 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4088 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4089 LLVMValueRef ij_out[2];
4090 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
4091
4092 /*
4093 * take the I then J parameters, and the DDX/Y for it, and
4094 * calculate the IJ inputs for the interpolator.
4095 * temp1 = ddx * offset/sample.x + I;
4096 * interp_param.I = ddy * offset/sample.y + temp1;
4097 * temp1 = ddx * offset/sample.x + J;
4098 * interp_param.J = ddy * offset/sample.y + temp1;
4099 */
4100 for (i = 0; i < 2; i++) {
4101 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
4102 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
4103 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4104 ddxy_out, ix_ll, "");
4105 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4106 ddxy_out, iy_ll, "");
4107 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4108 interp_param, ix_ll, "");
4109 LLVMValueRef temp1, temp2;
4110
4111 interp_el = ac_to_float(&ctx->ac, interp_el);
4112
4113 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, emit_data->args[0], "");
4114
4115 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4116
4117 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, emit_data->args[1], "");
4118
4119 ij_out[i] = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4120 }
4121 interp_param = lp_build_gather_values(&ctx->gallivm, ij_out, 2);
4122 }
4123
4124 if (interp_param)
4125 interp_param = ac_to_float(&ctx->ac, interp_param);
4126
4127 for (chan = 0; chan < 4; chan++) {
4128 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
4129 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4130
4131 for (unsigned idx = 0; idx < input_array_size; ++idx) {
4132 LLVMValueRef v, i = NULL, j = NULL;
4133
4134 if (interp_param) {
4135 i = LLVMBuildExtractElement(
4136 ctx->ac.builder, interp_param, ctx->i32_0, "");
4137 j = LLVMBuildExtractElement(
4138 ctx->ac.builder, interp_param, ctx->i32_1, "");
4139 }
4140 v = si_build_fs_interp(ctx, input_base + idx, schan,
4141 prim_mask, i, j);
4142
4143 gather = LLVMBuildInsertElement(ctx->ac.builder,
4144 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
4145 }
4146
4147 emit_data->output[chan] = LLVMBuildExtractElement(
4148 ctx->ac.builder, gather, array_idx, "");
4149 }
4150 }
4151
4152 static void vote_all_emit(
4153 const struct lp_build_tgsi_action *action,
4154 struct lp_build_tgsi_context *bld_base,
4155 struct lp_build_emit_data *emit_data)
4156 {
4157 struct si_shader_context *ctx = si_shader_context(bld_base);
4158
4159 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
4160 emit_data->output[emit_data->chan] =
4161 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4162 }
4163
4164 static void vote_any_emit(
4165 const struct lp_build_tgsi_action *action,
4166 struct lp_build_tgsi_context *bld_base,
4167 struct lp_build_emit_data *emit_data)
4168 {
4169 struct si_shader_context *ctx = si_shader_context(bld_base);
4170
4171 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
4172 emit_data->output[emit_data->chan] =
4173 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4174 }
4175
4176 static void vote_eq_emit(
4177 const struct lp_build_tgsi_action *action,
4178 struct lp_build_tgsi_context *bld_base,
4179 struct lp_build_emit_data *emit_data)
4180 {
4181 struct si_shader_context *ctx = si_shader_context(bld_base);
4182
4183 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4184 emit_data->output[emit_data->chan] =
4185 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4186 }
4187
4188 static void ballot_emit(
4189 const struct lp_build_tgsi_action *action,
4190 struct lp_build_tgsi_context *bld_base,
4191 struct lp_build_emit_data *emit_data)
4192 {
4193 struct si_shader_context *ctx = si_shader_context(bld_base);
4194 LLVMBuilderRef builder = ctx->ac.builder;
4195 LLVMValueRef tmp;
4196
4197 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4198 tmp = ac_build_ballot(&ctx->ac, tmp);
4199 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4200
4201 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4202 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4203 }
4204
4205 static void read_invoc_fetch_args(
4206 struct lp_build_tgsi_context *bld_base,
4207 struct lp_build_emit_data *emit_data)
4208 {
4209 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4210 0, emit_data->src_chan);
4211
4212 /* Always read the source invocation (= lane) from the X channel. */
4213 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4214 1, TGSI_CHAN_X);
4215 emit_data->arg_count = 2;
4216 }
4217
4218 static void read_lane_emit(
4219 const struct lp_build_tgsi_action *action,
4220 struct lp_build_tgsi_context *bld_base,
4221 struct lp_build_emit_data *emit_data)
4222 {
4223 struct si_shader_context *ctx = si_shader_context(bld_base);
4224
4225 /* We currently have no other way to prevent LLVM from lifting the icmp
4226 * calls to a dominating basic block.
4227 */
4228 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4229
4230 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4231 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4232
4233 emit_data->output[emit_data->chan] =
4234 ac_build_intrinsic(&ctx->ac, action->intr_name,
4235 ctx->i32, emit_data->args, emit_data->arg_count,
4236 AC_FUNC_ATTR_READNONE |
4237 AC_FUNC_ATTR_CONVERGENT);
4238 }
4239
4240 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4241 struct lp_build_emit_data *emit_data)
4242 {
4243 struct si_shader_context *ctx = si_shader_context(bld_base);
4244 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4245 LLVMValueRef imm;
4246 unsigned stream;
4247
4248 assert(src0.File == TGSI_FILE_IMMEDIATE);
4249
4250 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4251 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4252 return stream;
4253 }
4254
4255 /* Emit one vertex from the geometry shader */
4256 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4257 unsigned stream,
4258 LLVMValueRef *addrs)
4259 {
4260 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4261 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4262 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
4263 struct si_shader *shader = ctx->shader;
4264 struct lp_build_if_state if_state;
4265 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4266 ctx->param_gs2vs_offset);
4267 LLVMValueRef gs_next_vertex;
4268 LLVMValueRef can_emit;
4269 unsigned chan, offset;
4270 int i;
4271
4272 /* Write vertex attribute values to GSVS ring */
4273 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4274 ctx->gs_next_vertex[stream],
4275 "");
4276
4277 /* If this thread has already emitted the declared maximum number of
4278 * vertices, skip the write: excessive vertex emissions are not
4279 * supposed to have any effect.
4280 *
4281 * If the shader has no writes to memory, kill it instead. This skips
4282 * further memory loads and may allow LLVM to skip to the end
4283 * altogether.
4284 */
4285 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4286 LLVMConstInt(ctx->i32,
4287 shader->selector->gs_max_out_vertices, 0), "");
4288
4289 bool use_kill = !info->writes_memory;
4290 if (use_kill) {
4291 ac_build_kill_if_false(&ctx->ac, can_emit);
4292 } else {
4293 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4294 }
4295
4296 offset = 0;
4297 for (i = 0; i < info->num_outputs; i++) {
4298 for (chan = 0; chan < 4; chan++) {
4299 if (!(info->output_usagemask[i] & (1 << chan)) ||
4300 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4301 continue;
4302
4303 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4304 LLVMValueRef voffset =
4305 LLVMConstInt(ctx->i32, offset *
4306 shader->selector->gs_max_out_vertices, 0);
4307 offset++;
4308
4309 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4310 voffset = lp_build_mul_imm(uint, voffset, 4);
4311
4312 out_val = ac_to_integer(&ctx->ac, out_val);
4313
4314 ac_build_buffer_store_dword(&ctx->ac,
4315 ctx->gsvs_ring[stream],
4316 out_val, 1,
4317 voffset, soffset, 0,
4318 1, 1, true, true);
4319 }
4320 }
4321
4322 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4323 ctx->i32_1);
4324
4325 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4326
4327 /* Signal vertex emission */
4328 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4329 si_get_gs_wave_id(ctx));
4330 if (!use_kill)
4331 lp_build_endif(&if_state);
4332 }
4333
4334 /* Emit one vertex from the geometry shader */
4335 static void si_tgsi_emit_vertex(
4336 const struct lp_build_tgsi_action *action,
4337 struct lp_build_tgsi_context *bld_base,
4338 struct lp_build_emit_data *emit_data)
4339 {
4340 struct si_shader_context *ctx = si_shader_context(bld_base);
4341 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4342
4343 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4344 }
4345
4346 /* Cut one primitive from the geometry shader */
4347 static void si_llvm_emit_primitive(struct ac_shader_abi *abi,
4348 unsigned stream)
4349 {
4350 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4351
4352 /* Signal primitive cut */
4353 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4354 si_get_gs_wave_id(ctx));
4355 }
4356
4357 /* Cut one primitive from the geometry shader */
4358 static void si_tgsi_emit_primitive(
4359 const struct lp_build_tgsi_action *action,
4360 struct lp_build_tgsi_context *bld_base,
4361 struct lp_build_emit_data *emit_data)
4362 {
4363 struct si_shader_context *ctx = si_shader_context(bld_base);
4364
4365 si_llvm_emit_primitive(&ctx->abi, si_llvm_get_stream(bld_base, emit_data));
4366 }
4367
4368 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4369 struct lp_build_tgsi_context *bld_base,
4370 struct lp_build_emit_data *emit_data)
4371 {
4372 struct si_shader_context *ctx = si_shader_context(bld_base);
4373
4374 /* SI only (thanks to a hw bug workaround):
4375 * The real barrier instruction isn’t needed, because an entire patch
4376 * always fits into a single wave.
4377 */
4378 if (ctx->screen->info.chip_class == SI &&
4379 ctx->type == PIPE_SHADER_TESS_CTRL) {
4380 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
4381 return;
4382 }
4383
4384 lp_build_intrinsic(ctx->ac.builder,
4385 "llvm.amdgcn.s.barrier",
4386 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
4387 }
4388
4389 static const struct lp_build_tgsi_action interp_action = {
4390 .fetch_args = interp_fetch_args,
4391 .emit = build_interp_intrinsic,
4392 };
4393
4394 static void si_create_function(struct si_shader_context *ctx,
4395 const char *name,
4396 LLVMTypeRef *returns, unsigned num_returns,
4397 struct si_function_info *fninfo,
4398 unsigned max_workgroup_size)
4399 {
4400 int i;
4401
4402 si_llvm_create_func(ctx, name, returns, num_returns,
4403 fninfo->types, fninfo->num_params);
4404 ctx->return_value = LLVMGetUndef(ctx->return_type);
4405
4406 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4407 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4408
4409 /* The combination of:
4410 * - noalias
4411 * - dereferenceable
4412 * - invariant.load
4413 * allows the optimization passes to move loads and reduces
4414 * SGPR spilling significantly.
4415 */
4416 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
4417
4418 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4419 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
4420 ac_add_attr_dereferenceable(P, UINT64_MAX);
4421 }
4422 }
4423
4424 for (i = 0; i < fninfo->num_params; ++i) {
4425 if (fninfo->assign[i])
4426 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4427 }
4428
4429 si_llvm_add_attribute(ctx->main_fn, "amdgpu-32bit-address-high-bits",
4430 ctx->screen->info.address32_hi);
4431
4432 if (max_workgroup_size) {
4433 si_llvm_add_attribute(ctx->main_fn, "amdgpu-max-work-group-size",
4434 max_workgroup_size);
4435 }
4436 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4437 "no-signed-zeros-fp-math",
4438 "true");
4439
4440 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4441 /* These were copied from some LLVM test. */
4442 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4443 "less-precise-fpmad",
4444 "true");
4445 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4446 "no-infs-fp-math",
4447 "true");
4448 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4449 "no-nans-fp-math",
4450 "true");
4451 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4452 "unsafe-fp-math",
4453 "true");
4454 }
4455 }
4456
4457 static void declare_streamout_params(struct si_shader_context *ctx,
4458 struct pipe_stream_output_info *so,
4459 struct si_function_info *fninfo)
4460 {
4461 int i;
4462
4463 /* Streamout SGPRs. */
4464 if (so->num_outputs) {
4465 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4466 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4467 else
4468 ctx->param_streamout_config = fninfo->num_params - 1;
4469
4470 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4471 }
4472 /* A streamout buffer offset is loaded if the stride is non-zero. */
4473 for (i = 0; i < 4; i++) {
4474 if (!so->stride[i])
4475 continue;
4476
4477 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4478 }
4479 }
4480
4481 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4482 {
4483 switch (shader->selector->type) {
4484 case PIPE_SHADER_TESS_CTRL:
4485 /* Return this so that LLVM doesn't remove s_barrier
4486 * instructions on chips where we use s_barrier. */
4487 return shader->selector->screen->info.chip_class >= CIK ? 128 : 64;
4488
4489 case PIPE_SHADER_GEOMETRY:
4490 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4491
4492 case PIPE_SHADER_COMPUTE:
4493 break; /* see below */
4494
4495 default:
4496 return 0;
4497 }
4498
4499 const unsigned *properties = shader->selector->info.properties;
4500 unsigned max_work_group_size =
4501 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4502 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4503 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4504
4505 if (!max_work_group_size) {
4506 /* This is a variable group size compute shader,
4507 * compile it for the maximum possible group size.
4508 */
4509 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4510 }
4511 return max_work_group_size;
4512 }
4513
4514 static void declare_const_and_shader_buffers(struct si_shader_context *ctx,
4515 struct si_function_info *fninfo,
4516 bool assign_params)
4517 {
4518 LLVMTypeRef const_shader_buf_type;
4519
4520 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4521 ctx->shader->selector->info.shader_buffers_declared == 0)
4522 const_shader_buf_type = ctx->f32;
4523 else
4524 const_shader_buf_type = ctx->v4i32;
4525
4526 unsigned const_and_shader_buffers =
4527 add_arg(fninfo, ARG_SGPR,
4528 ac_array_in_const32_addr_space(const_shader_buf_type));
4529
4530 if (assign_params)
4531 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4532 }
4533
4534 static void declare_samplers_and_images(struct si_shader_context *ctx,
4535 struct si_function_info *fninfo,
4536 bool assign_params)
4537 {
4538 unsigned samplers_and_images =
4539 add_arg(fninfo, ARG_SGPR,
4540 ac_array_in_const32_addr_space(ctx->v8i32));
4541
4542 if (assign_params)
4543 ctx->param_samplers_and_images = samplers_and_images;
4544 }
4545
4546 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4547 struct si_function_info *fninfo,
4548 bool assign_params)
4549 {
4550 declare_const_and_shader_buffers(ctx, fninfo, assign_params);
4551 declare_samplers_and_images(ctx, fninfo, assign_params);
4552 }
4553
4554 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4555 struct si_function_info *fninfo)
4556 {
4557 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4558 ac_array_in_const32_addr_space(ctx->v4i32));
4559 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4560 ac_array_in_const32_addr_space(ctx->v8i32));
4561 }
4562
4563 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4564 struct si_function_info *fninfo)
4565 {
4566 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4567 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4568 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4569 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4570 }
4571
4572 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4573 struct si_function_info *fninfo,
4574 unsigned *num_prolog_vgprs)
4575 {
4576 struct si_shader *shader = ctx->shader;
4577
4578 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4579 if (shader->key.as_ls) {
4580 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4581 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4582 } else {
4583 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4584 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4585 }
4586 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4587
4588 if (!shader->is_gs_copy_shader) {
4589 /* Vertex load indices. */
4590 ctx->param_vertex_index0 = fninfo->num_params;
4591 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4592 add_arg(fninfo, ARG_VGPR, ctx->i32);
4593 *num_prolog_vgprs += shader->selector->info.num_inputs;
4594 }
4595 }
4596
4597 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4598 struct si_function_info *fninfo)
4599 {
4600 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4601 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4602 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4603 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
4604 }
4605
4606 enum {
4607 /* Convenient merged shader definitions. */
4608 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4609 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4610 };
4611
4612 static void create_function(struct si_shader_context *ctx)
4613 {
4614 struct si_shader *shader = ctx->shader;
4615 struct si_function_info fninfo;
4616 LLVMTypeRef returns[16+32*4];
4617 unsigned i, num_return_sgprs;
4618 unsigned num_returns = 0;
4619 unsigned num_prolog_vgprs = 0;
4620 unsigned type = ctx->type;
4621 unsigned vs_blit_property =
4622 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4623
4624 si_init_function_info(&fninfo);
4625
4626 /* Set MERGED shaders. */
4627 if (ctx->screen->info.chip_class >= GFX9) {
4628 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4629 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4630 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4631 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4632 }
4633
4634 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4635
4636 switch (type) {
4637 case PIPE_SHADER_VERTEX:
4638 declare_global_desc_pointers(ctx, &fninfo);
4639
4640 if (vs_blit_property) {
4641 ctx->param_vs_blit_inputs = fninfo.num_params;
4642 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4643 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4644 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* depth */
4645
4646 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4647 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color0 */
4648 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color1 */
4649 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color2 */
4650 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color3 */
4651 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4652 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4653 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4654 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4655 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4656 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4657 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4658 }
4659
4660 /* VGPRs */
4661 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4662 break;
4663 }
4664
4665 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4666 declare_vs_specific_input_sgprs(ctx, &fninfo);
4667 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4668 ac_array_in_const32_addr_space(ctx->v4i32));
4669
4670 if (shader->key.as_es) {
4671 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4672 } else if (shader->key.as_ls) {
4673 /* no extra parameters */
4674 } else {
4675 if (shader->is_gs_copy_shader) {
4676 fninfo.num_params = ctx->param_rw_buffers + 1;
4677 fninfo.num_sgpr_params = fninfo.num_params;
4678 }
4679
4680 /* The locations of the other parameters are assigned dynamically. */
4681 declare_streamout_params(ctx, &shader->selector->so,
4682 &fninfo);
4683 }
4684
4685 /* VGPRs */
4686 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4687 break;
4688
4689 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4690 declare_global_desc_pointers(ctx, &fninfo);
4691 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4692 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4693 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4694 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4695 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4696 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4697 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4698
4699 /* VGPRs */
4700 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4701 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4702
4703 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4704 * placed after the user SGPRs.
4705 */
4706 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4707 returns[num_returns++] = ctx->i32; /* SGPRs */
4708 for (i = 0; i < 11; i++)
4709 returns[num_returns++] = ctx->f32; /* VGPRs */
4710 break;
4711
4712 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4713 /* Merged stages have 8 system SGPRs at the beginning. */
4714 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
4715 if (HAVE_32BIT_POINTERS) {
4716 declare_per_stage_desc_pointers(ctx, &fninfo,
4717 ctx->type == PIPE_SHADER_TESS_CTRL);
4718 } else {
4719 declare_const_and_shader_buffers(ctx, &fninfo,
4720 ctx->type == PIPE_SHADER_TESS_CTRL);
4721 }
4722 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4723 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4724 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4725 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4726 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4727 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4728
4729 declare_global_desc_pointers(ctx, &fninfo);
4730 declare_per_stage_desc_pointers(ctx, &fninfo,
4731 ctx->type == PIPE_SHADER_VERTEX);
4732 declare_vs_specific_input_sgprs(ctx, &fninfo);
4733
4734 if (!HAVE_32BIT_POINTERS) {
4735 declare_samplers_and_images(ctx, &fninfo,
4736 ctx->type == PIPE_SHADER_TESS_CTRL);
4737 }
4738 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4739 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4740 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4741 if (!HAVE_32BIT_POINTERS) /* Align to 2 dwords. */
4742 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4743 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4744 ac_array_in_const32_addr_space(ctx->v4i32));
4745
4746 /* VGPRs (first TCS, then VS) */
4747 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4748 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4749
4750 if (ctx->type == PIPE_SHADER_VERTEX) {
4751 declare_vs_input_vgprs(ctx, &fninfo,
4752 &num_prolog_vgprs);
4753
4754 /* LS return values are inputs to the TCS main shader part. */
4755 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4756 returns[num_returns++] = ctx->i32; /* SGPRs */
4757 for (i = 0; i < 2; i++)
4758 returns[num_returns++] = ctx->f32; /* VGPRs */
4759 } else {
4760 /* TCS return values are inputs to the TCS epilog.
4761 *
4762 * param_tcs_offchip_offset, param_tcs_factor_offset,
4763 * param_tcs_offchip_layout, and param_rw_buffers
4764 * should be passed to the epilog.
4765 */
4766 for (i = 0; i <= 8 + GFX9_SGPR_TCS_OUT_LAYOUT; i++)
4767 returns[num_returns++] = ctx->i32; /* SGPRs */
4768 for (i = 0; i < 11; i++)
4769 returns[num_returns++] = ctx->f32; /* VGPRs */
4770 }
4771 break;
4772
4773 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4774 /* Merged stages have 8 system SGPRs at the beginning. */
4775 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
4776 if (HAVE_32BIT_POINTERS) {
4777 declare_per_stage_desc_pointers(ctx, &fninfo,
4778 ctx->type == PIPE_SHADER_GEOMETRY);
4779 } else {
4780 declare_const_and_shader_buffers(ctx, &fninfo,
4781 ctx->type == PIPE_SHADER_GEOMETRY);
4782 }
4783 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4784 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4785 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4786 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4787 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4788 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4789
4790 declare_global_desc_pointers(ctx, &fninfo);
4791 declare_per_stage_desc_pointers(ctx, &fninfo,
4792 (ctx->type == PIPE_SHADER_VERTEX ||
4793 ctx->type == PIPE_SHADER_TESS_EVAL));
4794 if (ctx->type == PIPE_SHADER_VERTEX) {
4795 declare_vs_specific_input_sgprs(ctx, &fninfo);
4796 } else {
4797 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4798 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4799 if (!HAVE_32BIT_POINTERS) {
4800 /* Declare as many input SGPRs as the VS has. */
4801 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4802 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4803 }
4804 }
4805
4806 if (!HAVE_32BIT_POINTERS) {
4807 declare_samplers_and_images(ctx, &fninfo,
4808 ctx->type == PIPE_SHADER_GEOMETRY);
4809 }
4810 if (ctx->type == PIPE_SHADER_VERTEX) {
4811 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4812 ac_array_in_const32_addr_space(ctx->v4i32));
4813 }
4814
4815 /* VGPRs (first GS, then VS/TES) */
4816 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4817 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4818 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4819 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4820 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4821
4822 if (ctx->type == PIPE_SHADER_VERTEX) {
4823 declare_vs_input_vgprs(ctx, &fninfo,
4824 &num_prolog_vgprs);
4825 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4826 declare_tes_input_vgprs(ctx, &fninfo);
4827 }
4828
4829 if (ctx->type == PIPE_SHADER_VERTEX ||
4830 ctx->type == PIPE_SHADER_TESS_EVAL) {
4831 unsigned num_user_sgprs;
4832
4833 if (ctx->type == PIPE_SHADER_VERTEX)
4834 num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR;
4835 else
4836 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
4837
4838 /* ES return values are inputs to GS. */
4839 for (i = 0; i < 8 + num_user_sgprs; i++)
4840 returns[num_returns++] = ctx->i32; /* SGPRs */
4841 for (i = 0; i < 5; i++)
4842 returns[num_returns++] = ctx->f32; /* VGPRs */
4843 }
4844 break;
4845
4846 case PIPE_SHADER_TESS_EVAL:
4847 declare_global_desc_pointers(ctx, &fninfo);
4848 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4849 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4850 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4851
4852 if (shader->key.as_es) {
4853 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4854 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4855 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4856 } else {
4857 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4858 declare_streamout_params(ctx, &shader->selector->so,
4859 &fninfo);
4860 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4861 }
4862
4863 /* VGPRs */
4864 declare_tes_input_vgprs(ctx, &fninfo);
4865 break;
4866
4867 case PIPE_SHADER_GEOMETRY:
4868 declare_global_desc_pointers(ctx, &fninfo);
4869 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4870 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4871 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4872
4873 /* VGPRs */
4874 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4875 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4876 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4877 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4878 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4879 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4880 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4881 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4882 break;
4883
4884 case PIPE_SHADER_FRAGMENT:
4885 declare_global_desc_pointers(ctx, &fninfo);
4886 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4887 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4888 add_arg_assign_checked(&fninfo, ARG_SGPR, ctx->i32,
4889 &ctx->abi.prim_mask, SI_PARAM_PRIM_MASK);
4890
4891 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4892 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4893 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4894 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4895 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4896 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4897 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4898 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4899 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4900 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4901 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4902 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4903 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4904 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4905 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4906 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4907 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4908 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4909 shader->info.face_vgpr_index = 20;
4910 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4911 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4912 shader->info.ancillary_vgpr_index = 21;
4913 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4914 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4915 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4916
4917 /* Color inputs from the prolog. */
4918 if (shader->selector->info.colors_read) {
4919 unsigned num_color_elements =
4920 util_bitcount(shader->selector->info.colors_read);
4921
4922 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4923 for (i = 0; i < num_color_elements; i++)
4924 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4925
4926 num_prolog_vgprs += num_color_elements;
4927 }
4928
4929 /* Outputs for the epilog. */
4930 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4931 num_returns =
4932 num_return_sgprs +
4933 util_bitcount(shader->selector->info.colors_written) * 4 +
4934 shader->selector->info.writes_z +
4935 shader->selector->info.writes_stencil +
4936 shader->selector->info.writes_samplemask +
4937 1 /* SampleMaskIn */;
4938
4939 num_returns = MAX2(num_returns,
4940 num_return_sgprs +
4941 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4942
4943 for (i = 0; i < num_return_sgprs; i++)
4944 returns[i] = ctx->i32;
4945 for (; i < num_returns; i++)
4946 returns[i] = ctx->f32;
4947 break;
4948
4949 case PIPE_SHADER_COMPUTE:
4950 declare_global_desc_pointers(ctx, &fninfo);
4951 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4952 if (shader->selector->info.uses_grid_size)
4953 add_arg_assign(&fninfo, ARG_SGPR, v3i32, &ctx->abi.num_work_groups);
4954 if (shader->selector->info.uses_block_size)
4955 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4956
4957 for (i = 0; i < 3; i++) {
4958 ctx->abi.workgroup_ids[i] = NULL;
4959 if (shader->selector->info.uses_block_id[i])
4960 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->abi.workgroup_ids[i]);
4961 }
4962
4963 add_arg_assign(&fninfo, ARG_VGPR, v3i32, &ctx->abi.local_invocation_ids);
4964 break;
4965 default:
4966 assert(0 && "unimplemented shader");
4967 return;
4968 }
4969
4970 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4971 si_get_max_workgroup_size(shader));
4972
4973 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4974 if (ctx->type == PIPE_SHADER_FRAGMENT &&
4975 ctx->separate_prolog) {
4976 si_llvm_add_attribute(ctx->main_fn,
4977 "InitialPSInputAddr",
4978 S_0286D0_PERSP_SAMPLE_ENA(1) |
4979 S_0286D0_PERSP_CENTER_ENA(1) |
4980 S_0286D0_PERSP_CENTROID_ENA(1) |
4981 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4982 S_0286D0_LINEAR_CENTER_ENA(1) |
4983 S_0286D0_LINEAR_CENTROID_ENA(1) |
4984 S_0286D0_FRONT_FACE_ENA(1) |
4985 S_0286D0_ANCILLARY_ENA(1) |
4986 S_0286D0_POS_FIXED_PT_ENA(1));
4987 }
4988
4989 shader->info.num_input_sgprs = 0;
4990 shader->info.num_input_vgprs = 0;
4991
4992 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4993 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
4994
4995 for (; i < fninfo.num_params; ++i)
4996 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
4997
4998 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4999 shader->info.num_input_vgprs -= num_prolog_vgprs;
5000
5001 if (shader->key.as_ls ||
5002 ctx->type == PIPE_SHADER_TESS_CTRL ||
5003 /* GFX9 has the ESGS ring buffer in LDS. */
5004 type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY)
5005 ac_declare_lds_as_pointer(&ctx->ac);
5006 }
5007
5008 /**
5009 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5010 * for later use.
5011 */
5012 static void preload_ring_buffers(struct si_shader_context *ctx)
5013 {
5014 LLVMBuilderRef builder = ctx->ac.builder;
5015
5016 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5017 ctx->param_rw_buffers);
5018
5019 if (ctx->screen->info.chip_class <= VI &&
5020 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
5021 unsigned ring =
5022 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5023 : SI_ES_RING_ESGS;
5024 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
5025
5026 ctx->esgs_ring =
5027 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5028 }
5029
5030 if (ctx->shader->is_gs_copy_shader) {
5031 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5032
5033 ctx->gsvs_ring[0] =
5034 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5035 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5036 const struct si_shader_selector *sel = ctx->shader->selector;
5037 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5038 LLVMValueRef base_ring;
5039
5040 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5041
5042 /* The conceptual layout of the GSVS ring is
5043 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5044 * but the real memory layout is swizzled across
5045 * threads:
5046 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5047 * t16v0c0 ..
5048 * Override the buffer descriptor accordingly.
5049 */
5050 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5051 uint64_t stream_offset = 0;
5052
5053 for (unsigned stream = 0; stream < 4; ++stream) {
5054 unsigned num_components;
5055 unsigned stride;
5056 unsigned num_records;
5057 LLVMValueRef ring, tmp;
5058
5059 num_components = sel->info.num_stream_output_components[stream];
5060 if (!num_components)
5061 continue;
5062
5063 stride = 4 * num_components * sel->gs_max_out_vertices;
5064
5065 /* Limit on the stride field for <= CIK. */
5066 assert(stride < (1 << 14));
5067
5068 num_records = 64;
5069
5070 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5071 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
5072 tmp = LLVMBuildAdd(builder, tmp,
5073 LLVMConstInt(ctx->i64,
5074 stream_offset, 0), "");
5075 stream_offset += stride * 64;
5076
5077 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5078 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5079 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5080 tmp = LLVMBuildOr(builder, tmp,
5081 LLVMConstInt(ctx->i32,
5082 S_008F04_STRIDE(stride) |
5083 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5084 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5085 ring = LLVMBuildInsertElement(builder, ring,
5086 LLVMConstInt(ctx->i32, num_records, 0),
5087 LLVMConstInt(ctx->i32, 2, 0), "");
5088 ring = LLVMBuildInsertElement(builder, ring,
5089 LLVMConstInt(ctx->i32,
5090 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5091 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5092 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5093 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5094 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5095 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5096 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5097 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5098 S_008F0C_ADD_TID_ENABLE(1),
5099 0),
5100 LLVMConstInt(ctx->i32, 3, 0), "");
5101
5102 ctx->gsvs_ring[stream] = ring;
5103 }
5104 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
5105 ctx->tess_offchip_ring = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TES);
5106 }
5107 }
5108
5109 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5110 LLVMValueRef param_rw_buffers,
5111 unsigned param_pos_fixed_pt)
5112 {
5113 LLVMBuilderRef builder = ctx->ac.builder;
5114 LLVMValueRef slot, desc, offset, row, bit, address[2];
5115
5116 /* Use the fixed-point gl_FragCoord input.
5117 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5118 * per coordinate to get the repeating effect.
5119 */
5120 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5121 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5122
5123 /* Load the buffer descriptor. */
5124 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5125 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
5126
5127 /* The stipple pattern is 32x32, each row has 32 bits. */
5128 offset = LLVMBuildMul(builder, address[1],
5129 LLVMConstInt(ctx->i32, 4, 0), "");
5130 row = buffer_load_const(ctx, desc, offset);
5131 row = ac_to_integer(&ctx->ac, row);
5132 bit = LLVMBuildLShr(builder, row, address[0], "");
5133 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5134 ac_build_kill_if_false(&ctx->ac, bit);
5135 }
5136
5137 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5138 struct si_shader_config *conf,
5139 unsigned symbol_offset)
5140 {
5141 unsigned i;
5142 const unsigned char *config =
5143 ac_shader_binary_config_start(binary, symbol_offset);
5144 bool really_needs_scratch = false;
5145
5146 /* LLVM adds SGPR spills to the scratch size.
5147 * Find out if we really need the scratch buffer.
5148 */
5149 for (i = 0; i < binary->reloc_count; i++) {
5150 const struct ac_shader_reloc *reloc = &binary->relocs[i];
5151
5152 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5153 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5154 really_needs_scratch = true;
5155 break;
5156 }
5157 }
5158
5159 /* XXX: We may be able to emit some of these values directly rather than
5160 * extracting fields to be emitted later.
5161 */
5162
5163 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5164 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5165 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5166 switch (reg) {
5167 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5168 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5169 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5170 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
5171 case R_00B848_COMPUTE_PGM_RSRC1:
5172 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5173 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5174 conf->float_mode = G_00B028_FLOAT_MODE(value);
5175 conf->rsrc1 = value;
5176 break;
5177 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5178 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5179 break;
5180 case R_00B84C_COMPUTE_PGM_RSRC2:
5181 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5182 conf->rsrc2 = value;
5183 break;
5184 case R_0286CC_SPI_PS_INPUT_ENA:
5185 conf->spi_ps_input_ena = value;
5186 break;
5187 case R_0286D0_SPI_PS_INPUT_ADDR:
5188 conf->spi_ps_input_addr = value;
5189 break;
5190 case R_0286E8_SPI_TMPRING_SIZE:
5191 case R_00B860_COMPUTE_TMPRING_SIZE:
5192 /* WAVESIZE is in units of 256 dwords. */
5193 if (really_needs_scratch)
5194 conf->scratch_bytes_per_wave =
5195 G_00B860_WAVESIZE(value) * 256 * 4;
5196 break;
5197 case 0x4: /* SPILLED_SGPRS */
5198 conf->spilled_sgprs = value;
5199 break;
5200 case 0x8: /* SPILLED_VGPRS */
5201 conf->spilled_vgprs = value;
5202 break;
5203 default:
5204 {
5205 static bool printed;
5206
5207 if (!printed) {
5208 fprintf(stderr, "Warning: LLVM emitted unknown "
5209 "config register: 0x%x\n", reg);
5210 printed = true;
5211 }
5212 }
5213 break;
5214 }
5215 }
5216
5217 if (!conf->spi_ps_input_addr)
5218 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5219 }
5220
5221 void si_shader_apply_scratch_relocs(struct si_shader *shader,
5222 uint64_t scratch_va)
5223 {
5224 unsigned i;
5225 uint32_t scratch_rsrc_dword0 = scratch_va;
5226 uint32_t scratch_rsrc_dword1 =
5227 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5228
5229 /* Enable scratch coalescing. */
5230 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5231
5232 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5233 const struct ac_shader_reloc *reloc =
5234 &shader->binary.relocs[i];
5235 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5236 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5237 &scratch_rsrc_dword0, 4);
5238 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5239 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5240 &scratch_rsrc_dword1, 4);
5241 }
5242 }
5243 }
5244
5245 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
5246 {
5247 unsigned size = shader->binary.code_size;
5248
5249 if (shader->prolog)
5250 size += shader->prolog->binary.code_size;
5251 if (shader->previous_stage)
5252 size += shader->previous_stage->binary.code_size;
5253 if (shader->prolog2)
5254 size += shader->prolog2->binary.code_size;
5255 if (shader->epilog)
5256 size += shader->epilog->binary.code_size;
5257 return size;
5258 }
5259
5260 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5261 {
5262 const struct ac_shader_binary *prolog =
5263 shader->prolog ? &shader->prolog->binary : NULL;
5264 const struct ac_shader_binary *previous_stage =
5265 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5266 const struct ac_shader_binary *prolog2 =
5267 shader->prolog2 ? &shader->prolog2->binary : NULL;
5268 const struct ac_shader_binary *epilog =
5269 shader->epilog ? &shader->epilog->binary : NULL;
5270 const struct ac_shader_binary *mainb = &shader->binary;
5271 unsigned bo_size = si_get_shader_binary_size(shader) +
5272 (!epilog ? mainb->rodata_size : 0);
5273 unsigned char *ptr;
5274
5275 assert(!prolog || !prolog->rodata_size);
5276 assert(!previous_stage || !previous_stage->rodata_size);
5277 assert(!prolog2 || !prolog2->rodata_size);
5278 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5279 !mainb->rodata_size);
5280 assert(!epilog || !epilog->rodata_size);
5281
5282 r600_resource_reference(&shader->bo, NULL);
5283 shader->bo = (struct r600_resource*)
5284 si_aligned_buffer_create(&sscreen->b,
5285 sscreen->cpdma_prefetch_writes_memory ?
5286 0 : R600_RESOURCE_FLAG_READ_ONLY,
5287 PIPE_USAGE_IMMUTABLE,
5288 align(bo_size, SI_CPDMA_ALIGNMENT),
5289 256);
5290 if (!shader->bo)
5291 return -ENOMEM;
5292
5293 /* Upload. */
5294 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5295 PIPE_TRANSFER_READ_WRITE |
5296 PIPE_TRANSFER_UNSYNCHRONIZED);
5297
5298 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5299 * endian-independent. */
5300 if (prolog) {
5301 memcpy(ptr, prolog->code, prolog->code_size);
5302 ptr += prolog->code_size;
5303 }
5304 if (previous_stage) {
5305 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5306 ptr += previous_stage->code_size;
5307 }
5308 if (prolog2) {
5309 memcpy(ptr, prolog2->code, prolog2->code_size);
5310 ptr += prolog2->code_size;
5311 }
5312
5313 memcpy(ptr, mainb->code, mainb->code_size);
5314 ptr += mainb->code_size;
5315
5316 if (epilog)
5317 memcpy(ptr, epilog->code, epilog->code_size);
5318 else if (mainb->rodata_size > 0)
5319 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5320
5321 sscreen->ws->buffer_unmap(shader->bo->buf);
5322 return 0;
5323 }
5324
5325 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5326 struct pipe_debug_callback *debug,
5327 const char *name, FILE *file)
5328 {
5329 char *line, *p;
5330 unsigned i, count;
5331
5332 if (binary->disasm_string) {
5333 fprintf(file, "Shader %s disassembly:\n", name);
5334 fprintf(file, "%s", binary->disasm_string);
5335
5336 if (debug && debug->debug_message) {
5337 /* Very long debug messages are cut off, so send the
5338 * disassembly one line at a time. This causes more
5339 * overhead, but on the plus side it simplifies
5340 * parsing of resulting logs.
5341 */
5342 pipe_debug_message(debug, SHADER_INFO,
5343 "Shader Disassembly Begin");
5344
5345 line = binary->disasm_string;
5346 while (*line) {
5347 p = util_strchrnul(line, '\n');
5348 count = p - line;
5349
5350 if (count) {
5351 pipe_debug_message(debug, SHADER_INFO,
5352 "%.*s", count, line);
5353 }
5354
5355 if (!*p)
5356 break;
5357 line = p + 1;
5358 }
5359
5360 pipe_debug_message(debug, SHADER_INFO,
5361 "Shader Disassembly End");
5362 }
5363 } else {
5364 fprintf(file, "Shader %s binary:\n", name);
5365 for (i = 0; i < binary->code_size; i += 4) {
5366 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5367 binary->code[i + 3], binary->code[i + 2],
5368 binary->code[i + 1], binary->code[i]);
5369 }
5370 }
5371 }
5372
5373 static void si_calculate_max_simd_waves(struct si_shader *shader)
5374 {
5375 struct si_screen *sscreen = shader->selector->screen;
5376 struct si_shader_config *conf = &shader->config;
5377 unsigned num_inputs = shader->selector->info.num_inputs;
5378 unsigned lds_increment = sscreen->info.chip_class >= CIK ? 512 : 256;
5379 unsigned lds_per_wave = 0;
5380 unsigned max_simd_waves;
5381
5382 switch (sscreen->info.family) {
5383 /* These always have 8 waves: */
5384 case CHIP_POLARIS10:
5385 case CHIP_POLARIS11:
5386 case CHIP_POLARIS12:
5387 max_simd_waves = 8;
5388 break;
5389 default:
5390 max_simd_waves = 10;
5391 }
5392
5393 /* Compute LDS usage for PS. */
5394 switch (shader->selector->type) {
5395 case PIPE_SHADER_FRAGMENT:
5396 /* The minimum usage per wave is (num_inputs * 48). The maximum
5397 * usage is (num_inputs * 48 * 16).
5398 * We can get anything in between and it varies between waves.
5399 *
5400 * The 48 bytes per input for a single primitive is equal to
5401 * 4 bytes/component * 4 components/input * 3 points.
5402 *
5403 * Other stages don't know the size at compile time or don't
5404 * allocate LDS per wave, but instead they do it per thread group.
5405 */
5406 lds_per_wave = conf->lds_size * lds_increment +
5407 align(num_inputs * 48, lds_increment);
5408 break;
5409 case PIPE_SHADER_COMPUTE:
5410 if (shader->selector) {
5411 unsigned max_workgroup_size =
5412 si_get_max_workgroup_size(shader);
5413 lds_per_wave = (conf->lds_size * lds_increment) /
5414 DIV_ROUND_UP(max_workgroup_size, 64);
5415 }
5416 break;
5417 }
5418
5419 /* Compute the per-SIMD wave counts. */
5420 if (conf->num_sgprs) {
5421 if (sscreen->info.chip_class >= VI)
5422 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5423 else
5424 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5425 }
5426
5427 if (conf->num_vgprs)
5428 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5429
5430 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5431 * 16KB makes some SIMDs unoccupied). */
5432 if (lds_per_wave)
5433 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5434
5435 conf->max_simd_waves = max_simd_waves;
5436 }
5437
5438 void si_shader_dump_stats_for_shader_db(const struct si_shader *shader,
5439 struct pipe_debug_callback *debug)
5440 {
5441 const struct si_shader_config *conf = &shader->config;
5442
5443 pipe_debug_message(debug, SHADER_INFO,
5444 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5445 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5446 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5447 conf->num_sgprs, conf->num_vgprs,
5448 si_get_shader_binary_size(shader),
5449 conf->lds_size, conf->scratch_bytes_per_wave,
5450 conf->max_simd_waves, conf->spilled_sgprs,
5451 conf->spilled_vgprs, conf->private_mem_vgprs);
5452 }
5453
5454 static void si_shader_dump_stats(struct si_screen *sscreen,
5455 const struct si_shader *shader,
5456 unsigned processor,
5457 FILE *file,
5458 bool check_debug_option)
5459 {
5460 const struct si_shader_config *conf = &shader->config;
5461
5462 if (!check_debug_option ||
5463 si_can_dump_shader(sscreen, processor)) {
5464 if (processor == PIPE_SHADER_FRAGMENT) {
5465 fprintf(file, "*** SHADER CONFIG ***\n"
5466 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5467 "SPI_PS_INPUT_ENA = 0x%04x\n",
5468 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5469 }
5470
5471 fprintf(file, "*** SHADER STATS ***\n"
5472 "SGPRS: %d\n"
5473 "VGPRS: %d\n"
5474 "Spilled SGPRs: %d\n"
5475 "Spilled VGPRs: %d\n"
5476 "Private memory VGPRs: %d\n"
5477 "Code Size: %d bytes\n"
5478 "LDS: %d blocks\n"
5479 "Scratch: %d bytes per wave\n"
5480 "Max Waves: %d\n"
5481 "********************\n\n\n",
5482 conf->num_sgprs, conf->num_vgprs,
5483 conf->spilled_sgprs, conf->spilled_vgprs,
5484 conf->private_mem_vgprs,
5485 si_get_shader_binary_size(shader),
5486 conf->lds_size, conf->scratch_bytes_per_wave,
5487 conf->max_simd_waves);
5488 }
5489 }
5490
5491 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5492 {
5493 switch (processor) {
5494 case PIPE_SHADER_VERTEX:
5495 if (shader->key.as_es)
5496 return "Vertex Shader as ES";
5497 else if (shader->key.as_ls)
5498 return "Vertex Shader as LS";
5499 else
5500 return "Vertex Shader as VS";
5501 case PIPE_SHADER_TESS_CTRL:
5502 return "Tessellation Control Shader";
5503 case PIPE_SHADER_TESS_EVAL:
5504 if (shader->key.as_es)
5505 return "Tessellation Evaluation Shader as ES";
5506 else
5507 return "Tessellation Evaluation Shader as VS";
5508 case PIPE_SHADER_GEOMETRY:
5509 if (shader->is_gs_copy_shader)
5510 return "GS Copy Shader as VS";
5511 else
5512 return "Geometry Shader";
5513 case PIPE_SHADER_FRAGMENT:
5514 return "Pixel Shader";
5515 case PIPE_SHADER_COMPUTE:
5516 return "Compute Shader";
5517 default:
5518 return "Unknown Shader";
5519 }
5520 }
5521
5522 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5523 struct pipe_debug_callback *debug, unsigned processor,
5524 FILE *file, bool check_debug_option)
5525 {
5526 if (!check_debug_option ||
5527 si_can_dump_shader(sscreen, processor))
5528 si_dump_shader_key(processor, shader, file);
5529
5530 if (!check_debug_option && shader->binary.llvm_ir_string) {
5531 if (shader->previous_stage &&
5532 shader->previous_stage->binary.llvm_ir_string) {
5533 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5534 si_get_shader_name(shader, processor));
5535 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5536 }
5537
5538 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5539 si_get_shader_name(shader, processor));
5540 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5541 }
5542
5543 if (!check_debug_option ||
5544 (si_can_dump_shader(sscreen, processor) &&
5545 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5546 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5547
5548 if (shader->prolog)
5549 si_shader_dump_disassembly(&shader->prolog->binary,
5550 debug, "prolog", file);
5551 if (shader->previous_stage)
5552 si_shader_dump_disassembly(&shader->previous_stage->binary,
5553 debug, "previous stage", file);
5554 if (shader->prolog2)
5555 si_shader_dump_disassembly(&shader->prolog2->binary,
5556 debug, "prolog2", file);
5557
5558 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5559
5560 if (shader->epilog)
5561 si_shader_dump_disassembly(&shader->epilog->binary,
5562 debug, "epilog", file);
5563 fprintf(file, "\n");
5564 }
5565
5566 si_shader_dump_stats(sscreen, shader, processor, file,
5567 check_debug_option);
5568 }
5569
5570 static int si_compile_llvm(struct si_screen *sscreen,
5571 struct ac_shader_binary *binary,
5572 struct si_shader_config *conf,
5573 LLVMTargetMachineRef tm,
5574 LLVMModuleRef mod,
5575 struct pipe_debug_callback *debug,
5576 unsigned processor,
5577 const char *name)
5578 {
5579 int r = 0;
5580 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5581
5582 if (si_can_dump_shader(sscreen, processor)) {
5583 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5584
5585 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5586 fprintf(stderr, "%s LLVM IR:\n\n", name);
5587 ac_dump_module(mod);
5588 fprintf(stderr, "\n");
5589 }
5590 }
5591
5592 if (sscreen->record_llvm_ir) {
5593 char *ir = LLVMPrintModuleToString(mod);
5594 binary->llvm_ir_string = strdup(ir);
5595 LLVMDisposeMessage(ir);
5596 }
5597
5598 if (!si_replace_shader(count, binary)) {
5599 r = si_llvm_compile(mod, binary, tm, debug);
5600 if (r)
5601 return r;
5602 }
5603
5604 si_shader_binary_read_config(binary, conf, 0);
5605
5606 /* Enable 64-bit and 16-bit denormals, because there is no performance
5607 * cost.
5608 *
5609 * If denormals are enabled, all floating-point output modifiers are
5610 * ignored.
5611 *
5612 * Don't enable denormals for 32-bit floats, because:
5613 * - Floating-point output modifiers would be ignored by the hw.
5614 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5615 * have to stop using those.
5616 * - SI & CI would be very slow.
5617 */
5618 conf->float_mode |= V_00B028_FP_64_DENORMS;
5619
5620 FREE(binary->config);
5621 FREE(binary->global_symbol_offsets);
5622 binary->config = NULL;
5623 binary->global_symbol_offsets = NULL;
5624
5625 /* Some shaders can't have rodata because their binaries can be
5626 * concatenated.
5627 */
5628 if (binary->rodata_size &&
5629 (processor == PIPE_SHADER_VERTEX ||
5630 processor == PIPE_SHADER_TESS_CTRL ||
5631 processor == PIPE_SHADER_TESS_EVAL ||
5632 processor == PIPE_SHADER_FRAGMENT)) {
5633 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5634 return -EINVAL;
5635 }
5636
5637 return r;
5638 }
5639
5640 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5641 {
5642 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5643 LLVMBuildRetVoid(ctx->ac.builder);
5644 else
5645 LLVMBuildRet(ctx->ac.builder, ret);
5646 }
5647
5648 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5649 struct si_shader *
5650 si_generate_gs_copy_shader(struct si_screen *sscreen,
5651 LLVMTargetMachineRef tm,
5652 struct si_shader_selector *gs_selector,
5653 struct pipe_debug_callback *debug)
5654 {
5655 struct si_shader_context ctx;
5656 struct si_shader *shader;
5657 LLVMBuilderRef builder;
5658 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
5659 struct lp_build_context *uint = &bld_base->uint_bld;
5660 struct si_shader_output_values *outputs;
5661 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5662 int i, r;
5663
5664 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5665
5666 if (!outputs)
5667 return NULL;
5668
5669 shader = CALLOC_STRUCT(si_shader);
5670 if (!shader) {
5671 FREE(outputs);
5672 return NULL;
5673 }
5674
5675 /* We can leave the fence as permanently signaled because the GS copy
5676 * shader only becomes visible globally after it has been compiled. */
5677 util_queue_fence_init(&shader->ready);
5678
5679 shader->selector = gs_selector;
5680 shader->is_gs_copy_shader = true;
5681
5682 si_init_shader_ctx(&ctx, sscreen, tm);
5683 ctx.shader = shader;
5684 ctx.type = PIPE_SHADER_VERTEX;
5685
5686 builder = ctx.ac.builder;
5687
5688 create_function(&ctx);
5689 preload_ring_buffers(&ctx);
5690
5691 LLVMValueRef voffset =
5692 lp_build_mul_imm(uint, ctx.abi.vertex_id, 4);
5693
5694 /* Fetch the vertex stream ID.*/
5695 LLVMValueRef stream_id;
5696
5697 if (gs_selector->so.num_outputs)
5698 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5699 else
5700 stream_id = ctx.i32_0;
5701
5702 /* Fill in output information. */
5703 for (i = 0; i < gsinfo->num_outputs; ++i) {
5704 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5705 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5706
5707 for (int chan = 0; chan < 4; chan++) {
5708 outputs[i].vertex_stream[chan] =
5709 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5710 }
5711 }
5712
5713 LLVMBasicBlockRef end_bb;
5714 LLVMValueRef switch_inst;
5715
5716 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5717 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5718
5719 for (int stream = 0; stream < 4; stream++) {
5720 LLVMBasicBlockRef bb;
5721 unsigned offset;
5722
5723 if (!gsinfo->num_stream_output_components[stream])
5724 continue;
5725
5726 if (stream > 0 && !gs_selector->so.num_outputs)
5727 continue;
5728
5729 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5730 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5731 LLVMPositionBuilderAtEnd(builder, bb);
5732
5733 /* Fetch vertex data from GSVS ring */
5734 offset = 0;
5735 for (i = 0; i < gsinfo->num_outputs; ++i) {
5736 for (unsigned chan = 0; chan < 4; chan++) {
5737 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5738 outputs[i].vertex_stream[chan] != stream) {
5739 outputs[i].values[chan] = ctx.bld_base.base.undef;
5740 continue;
5741 }
5742
5743 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5744 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5745 offset++;
5746
5747 outputs[i].values[chan] =
5748 ac_build_buffer_load(&ctx.ac,
5749 ctx.gsvs_ring[0], 1,
5750 ctx.i32_0, voffset,
5751 soffset, 0, 1, 1,
5752 true, false);
5753 }
5754 }
5755
5756 /* Streamout and exports. */
5757 if (gs_selector->so.num_outputs) {
5758 si_llvm_emit_streamout(&ctx, outputs,
5759 gsinfo->num_outputs,
5760 stream);
5761 }
5762
5763 if (stream == 0)
5764 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5765
5766 LLVMBuildBr(builder, end_bb);
5767 }
5768
5769 LLVMPositionBuilderAtEnd(builder, end_bb);
5770
5771 LLVMBuildRetVoid(ctx.ac.builder);
5772
5773 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5774 si_llvm_optimize_module(&ctx);
5775
5776 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5777 &ctx.shader->config, ctx.tm,
5778 ctx.gallivm.module,
5779 debug, PIPE_SHADER_GEOMETRY,
5780 "GS Copy Shader");
5781 if (!r) {
5782 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5783 fprintf(stderr, "GS Copy Shader:\n");
5784 si_shader_dump(sscreen, ctx.shader, debug,
5785 PIPE_SHADER_GEOMETRY, stderr, true);
5786 r = si_shader_binary_upload(sscreen, ctx.shader);
5787 }
5788
5789 si_llvm_dispose(&ctx);
5790
5791 FREE(outputs);
5792
5793 if (r != 0) {
5794 FREE(shader);
5795 shader = NULL;
5796 }
5797 return shader;
5798 }
5799
5800 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5801 const struct si_vs_prolog_bits *prolog,
5802 const char *prefix, FILE *f)
5803 {
5804 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5805 prefix, prolog->instance_divisor_is_one);
5806 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5807 prefix, prolog->instance_divisor_is_fetched);
5808 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5809 prefix, prolog->ls_vgpr_fix);
5810
5811 fprintf(f, " mono.vs.fix_fetch = {");
5812 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5813 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5814 fprintf(f, "}\n");
5815 }
5816
5817 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5818 FILE *f)
5819 {
5820 const struct si_shader_key *key = &shader->key;
5821
5822 fprintf(f, "SHADER KEY\n");
5823
5824 switch (processor) {
5825 case PIPE_SHADER_VERTEX:
5826 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5827 "part.vs.prolog", f);
5828 fprintf(f, " as_es = %u\n", key->as_es);
5829 fprintf(f, " as_ls = %u\n", key->as_ls);
5830 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5831 key->mono.u.vs_export_prim_id);
5832 break;
5833
5834 case PIPE_SHADER_TESS_CTRL:
5835 if (shader->selector->screen->info.chip_class >= GFX9) {
5836 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5837 "part.tcs.ls_prolog", f);
5838 }
5839 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5840 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5841 break;
5842
5843 case PIPE_SHADER_TESS_EVAL:
5844 fprintf(f, " as_es = %u\n", key->as_es);
5845 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5846 key->mono.u.vs_export_prim_id);
5847 break;
5848
5849 case PIPE_SHADER_GEOMETRY:
5850 if (shader->is_gs_copy_shader)
5851 break;
5852
5853 if (shader->selector->screen->info.chip_class >= GFX9 &&
5854 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5855 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5856 "part.gs.vs_prolog", f);
5857 }
5858 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5859 break;
5860
5861 case PIPE_SHADER_COMPUTE:
5862 break;
5863
5864 case PIPE_SHADER_FRAGMENT:
5865 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5866 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5867 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5868 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5869 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5870 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5871 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5872 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5873 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5874 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5875 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5876 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5877 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5878 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5879 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5880 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5881 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5882 break;
5883
5884 default:
5885 assert(0);
5886 }
5887
5888 if ((processor == PIPE_SHADER_GEOMETRY ||
5889 processor == PIPE_SHADER_TESS_EVAL ||
5890 processor == PIPE_SHADER_VERTEX) &&
5891 !key->as_es && !key->as_ls) {
5892 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5893 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5894 }
5895 }
5896
5897 static void si_init_shader_ctx(struct si_shader_context *ctx,
5898 struct si_screen *sscreen,
5899 LLVMTargetMachineRef tm)
5900 {
5901 struct lp_build_tgsi_context *bld_base;
5902
5903 si_llvm_context_init(ctx, sscreen, tm);
5904
5905 bld_base = &ctx->bld_base;
5906 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5907
5908 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5909 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5910 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5911
5912 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5913
5914 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5915
5916 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5917 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5918 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5919 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5920
5921 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5922 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5923 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5924 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5925 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5926 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5927 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5928 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
5929 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5930
5931 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5932 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_tgsi_emit_primitive;
5933 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5934 }
5935
5936 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5937 {
5938 struct si_shader *shader = ctx->shader;
5939 struct tgsi_shader_info *info = &shader->selector->info;
5940
5941 if ((ctx->type != PIPE_SHADER_VERTEX &&
5942 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5943 shader->key.as_ls ||
5944 shader->key.as_es)
5945 return;
5946
5947 ac_optimize_vs_outputs(&ctx->ac,
5948 ctx->main_fn,
5949 shader->info.vs_output_param_offset,
5950 info->num_outputs,
5951 &shader->info.nr_param_exports);
5952 }
5953
5954 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
5955 {
5956 ctx->shader->config.private_mem_vgprs = 0;
5957
5958 /* Process all LLVM instructions. */
5959 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
5960 while (bb) {
5961 LLVMValueRef next = LLVMGetFirstInstruction(bb);
5962
5963 while (next) {
5964 LLVMValueRef inst = next;
5965 next = LLVMGetNextInstruction(next);
5966
5967 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
5968 continue;
5969
5970 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
5971 /* No idea why LLVM aligns allocas to 4 elements. */
5972 unsigned alignment = LLVMGetAlignment(inst);
5973 unsigned dw_size = align(ac_get_type_size(type) / 4, alignment);
5974 ctx->shader->config.private_mem_vgprs += dw_size;
5975 }
5976 bb = LLVMGetNextBasicBlock(bb);
5977 }
5978 }
5979
5980 static void si_init_exec_from_input(struct si_shader_context *ctx,
5981 unsigned param, unsigned bitoffset)
5982 {
5983 LLVMValueRef args[] = {
5984 LLVMGetParam(ctx->main_fn, param),
5985 LLVMConstInt(ctx->i32, bitoffset, 0),
5986 };
5987 lp_build_intrinsic(ctx->ac.builder,
5988 "llvm.amdgcn.init.exec.from.input",
5989 ctx->voidt, args, 2, LP_FUNC_ATTR_CONVERGENT);
5990 }
5991
5992 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
5993 const struct si_vs_prolog_bits *key)
5994 {
5995 /* VGPR initialization fixup for Vega10 and Raven is always done in the
5996 * VS prolog. */
5997 return sel->vs_needs_prolog || key->ls_vgpr_fix;
5998 }
5999
6000 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
6001 bool is_monolithic)
6002 {
6003 struct si_shader *shader = ctx->shader;
6004 struct si_shader_selector *sel = shader->selector;
6005 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6006
6007 // TODO clean all this up!
6008 switch (ctx->type) {
6009 case PIPE_SHADER_VERTEX:
6010 ctx->load_input = declare_input_vs;
6011 if (shader->key.as_ls)
6012 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
6013 else if (shader->key.as_es)
6014 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6015 else
6016 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6017 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6018 break;
6019 case PIPE_SHADER_TESS_CTRL:
6020 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6021 ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
6022 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6023 bld_base->emit_store = store_output_tcs;
6024 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
6025 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
6026 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6027 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6028 break;
6029 case PIPE_SHADER_TESS_EVAL:
6030 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6031 ctx->abi.load_tess_varyings = si_nir_load_input_tes;
6032 ctx->abi.load_tess_coord = si_load_tess_coord;
6033 ctx->abi.load_tess_level = si_load_tess_level;
6034 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6035 if (shader->key.as_es)
6036 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6037 else
6038 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6039 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6040 break;
6041 case PIPE_SHADER_GEOMETRY:
6042 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6043 ctx->abi.load_inputs = si_nir_load_input_gs;
6044 ctx->abi.emit_vertex = si_llvm_emit_vertex;
6045 ctx->abi.emit_primitive = si_llvm_emit_primitive;
6046 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
6047 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
6048 break;
6049 case PIPE_SHADER_FRAGMENT:
6050 ctx->load_input = declare_input_fs;
6051 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
6052 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6053 ctx->abi.lookup_interp_param = si_nir_lookup_interp_param;
6054 ctx->abi.load_sample_position = load_sample_position;
6055 ctx->abi.load_sample_mask_in = load_sample_mask_in;
6056 break;
6057 case PIPE_SHADER_COMPUTE:
6058 ctx->abi.load_local_group_size = get_block_size;
6059 break;
6060 default:
6061 assert(!"Unsupported shader type");
6062 return false;
6063 }
6064
6065 ctx->abi.load_ubo = load_ubo;
6066 ctx->abi.load_ssbo = load_ssbo;
6067
6068 create_function(ctx);
6069 preload_ring_buffers(ctx);
6070
6071 /* For GFX9 merged shaders:
6072 * - Set EXEC for the first shader. If the prolog is present, set
6073 * EXEC there instead.
6074 * - Add a barrier before the second shader.
6075 * - In the second shader, reset EXEC to ~0 and wrap the main part in
6076 * an if-statement. This is required for correctness in geometry
6077 * shaders, to ensure that empty GS waves do not send GS_EMIT and
6078 * GS_CUT messages.
6079 *
6080 * For monolithic merged shaders, the first shader is wrapped in an
6081 * if-block together with its prolog in si_build_wrapper_function.
6082 */
6083 if (ctx->screen->info.chip_class >= GFX9) {
6084 if (!is_monolithic &&
6085 sel->info.num_instructions > 1 && /* not empty shader */
6086 (shader->key.as_es || shader->key.as_ls) &&
6087 (ctx->type == PIPE_SHADER_TESS_EVAL ||
6088 (ctx->type == PIPE_SHADER_VERTEX &&
6089 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
6090 si_init_exec_from_input(ctx,
6091 ctx->param_merged_wave_info, 0);
6092 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6093 ctx->type == PIPE_SHADER_GEOMETRY) {
6094 if (!is_monolithic)
6095 ac_init_exec_full_mask(&ctx->ac);
6096
6097 /* The barrier must execute for all shaders in a
6098 * threadgroup.
6099 */
6100 si_llvm_emit_barrier(NULL, bld_base, NULL);
6101
6102 LLVMValueRef num_threads = unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
6103 LLVMValueRef ena =
6104 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
6105 ac_get_thread_id(&ctx->ac), num_threads, "");
6106 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
6107 }
6108 }
6109
6110 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
6111 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
6112 for (unsigned i = 0; i < 6; i++) {
6113 ctx->invoc0_tess_factors[i] =
6114 lp_build_alloca_undef(&ctx->gallivm, ctx->i32, "");
6115 }
6116 }
6117
6118 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6119 int i;
6120 for (i = 0; i < 4; i++) {
6121 ctx->gs_next_vertex[i] =
6122 lp_build_alloca(&ctx->gallivm,
6123 ctx->i32, "");
6124 }
6125 }
6126
6127 if (sel->force_correct_derivs_after_kill) {
6128 ctx->postponed_kill = lp_build_alloca_undef(&ctx->gallivm, ctx->i1, "");
6129 /* true = don't kill. */
6130 LLVMBuildStore(ctx->ac.builder, LLVMConstInt(ctx->i1, 1, 0),
6131 ctx->postponed_kill);
6132 }
6133
6134 if (sel->tokens) {
6135 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6136 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6137 return false;
6138 }
6139 } else {
6140 if (!si_nir_build_llvm(ctx, sel->nir)) {
6141 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
6142 return false;
6143 }
6144 }
6145
6146 si_llvm_build_ret(ctx, ctx->return_value);
6147 return true;
6148 }
6149
6150 /**
6151 * Compute the VS prolog key, which contains all the information needed to
6152 * build the VS prolog function, and set shader->info bits where needed.
6153 *
6154 * \param info Shader info of the vertex shader.
6155 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6156 * \param prolog_key Key of the VS prolog
6157 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6158 * \param key Output shader part key.
6159 */
6160 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
6161 unsigned num_input_sgprs,
6162 const struct si_vs_prolog_bits *prolog_key,
6163 struct si_shader *shader_out,
6164 union si_shader_part_key *key)
6165 {
6166 memset(key, 0, sizeof(*key));
6167 key->vs_prolog.states = *prolog_key;
6168 key->vs_prolog.num_input_sgprs = num_input_sgprs;
6169 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6170 key->vs_prolog.as_ls = shader_out->key.as_ls;
6171 key->vs_prolog.as_es = shader_out->key.as_es;
6172
6173 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
6174 key->vs_prolog.as_ls = 1;
6175 key->vs_prolog.num_merged_next_stage_vgprs = 2;
6176 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
6177 key->vs_prolog.as_es = 1;
6178 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6179 }
6180
6181 /* Enable loading the InstanceID VGPR. */
6182 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
6183
6184 if ((key->vs_prolog.states.instance_divisor_is_one |
6185 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
6186 shader_out->info.uses_instanceid = true;
6187 }
6188
6189 /**
6190 * Compute the PS prolog key, which contains all the information needed to
6191 * build the PS prolog function, and set related bits in shader->config.
6192 */
6193 static void si_get_ps_prolog_key(struct si_shader *shader,
6194 union si_shader_part_key *key,
6195 bool separate_prolog)
6196 {
6197 struct tgsi_shader_info *info = &shader->selector->info;
6198
6199 memset(key, 0, sizeof(*key));
6200 key->ps_prolog.states = shader->key.part.ps.prolog;
6201 key->ps_prolog.colors_read = info->colors_read;
6202 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6203 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6204 key->ps_prolog.wqm = info->uses_derivatives &&
6205 (key->ps_prolog.colors_read ||
6206 key->ps_prolog.states.force_persp_sample_interp ||
6207 key->ps_prolog.states.force_linear_sample_interp ||
6208 key->ps_prolog.states.force_persp_center_interp ||
6209 key->ps_prolog.states.force_linear_center_interp ||
6210 key->ps_prolog.states.bc_optimize_for_persp ||
6211 key->ps_prolog.states.bc_optimize_for_linear);
6212 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
6213
6214 if (info->colors_read) {
6215 unsigned *color = shader->selector->color_attr_index;
6216
6217 if (shader->key.part.ps.prolog.color_two_side) {
6218 /* BCOLORs are stored after the last input. */
6219 key->ps_prolog.num_interp_inputs = info->num_inputs;
6220 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6221 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6222 }
6223
6224 for (unsigned i = 0; i < 2; i++) {
6225 unsigned interp = info->input_interpolate[color[i]];
6226 unsigned location = info->input_interpolate_loc[color[i]];
6227
6228 if (!(info->colors_read & (0xf << i*4)))
6229 continue;
6230
6231 key->ps_prolog.color_attr_index[i] = color[i];
6232
6233 if (shader->key.part.ps.prolog.flatshade_colors &&
6234 interp == TGSI_INTERPOLATE_COLOR)
6235 interp = TGSI_INTERPOLATE_CONSTANT;
6236
6237 switch (interp) {
6238 case TGSI_INTERPOLATE_CONSTANT:
6239 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6240 break;
6241 case TGSI_INTERPOLATE_PERSPECTIVE:
6242 case TGSI_INTERPOLATE_COLOR:
6243 /* Force the interpolation location for colors here. */
6244 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6245 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6246 if (shader->key.part.ps.prolog.force_persp_center_interp)
6247 location = TGSI_INTERPOLATE_LOC_CENTER;
6248
6249 switch (location) {
6250 case TGSI_INTERPOLATE_LOC_SAMPLE:
6251 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6252 shader->config.spi_ps_input_ena |=
6253 S_0286CC_PERSP_SAMPLE_ENA(1);
6254 break;
6255 case TGSI_INTERPOLATE_LOC_CENTER:
6256 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6257 shader->config.spi_ps_input_ena |=
6258 S_0286CC_PERSP_CENTER_ENA(1);
6259 break;
6260 case TGSI_INTERPOLATE_LOC_CENTROID:
6261 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6262 shader->config.spi_ps_input_ena |=
6263 S_0286CC_PERSP_CENTROID_ENA(1);
6264 break;
6265 default:
6266 assert(0);
6267 }
6268 break;
6269 case TGSI_INTERPOLATE_LINEAR:
6270 /* Force the interpolation location for colors here. */
6271 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6272 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6273 if (shader->key.part.ps.prolog.force_linear_center_interp)
6274 location = TGSI_INTERPOLATE_LOC_CENTER;
6275
6276 /* The VGPR assignment for non-monolithic shaders
6277 * works because InitialPSInputAddr is set on the
6278 * main shader and PERSP_PULL_MODEL is never used.
6279 */
6280 switch (location) {
6281 case TGSI_INTERPOLATE_LOC_SAMPLE:
6282 key->ps_prolog.color_interp_vgpr_index[i] =
6283 separate_prolog ? 6 : 9;
6284 shader->config.spi_ps_input_ena |=
6285 S_0286CC_LINEAR_SAMPLE_ENA(1);
6286 break;
6287 case TGSI_INTERPOLATE_LOC_CENTER:
6288 key->ps_prolog.color_interp_vgpr_index[i] =
6289 separate_prolog ? 8 : 11;
6290 shader->config.spi_ps_input_ena |=
6291 S_0286CC_LINEAR_CENTER_ENA(1);
6292 break;
6293 case TGSI_INTERPOLATE_LOC_CENTROID:
6294 key->ps_prolog.color_interp_vgpr_index[i] =
6295 separate_prolog ? 10 : 13;
6296 shader->config.spi_ps_input_ena |=
6297 S_0286CC_LINEAR_CENTROID_ENA(1);
6298 break;
6299 default:
6300 assert(0);
6301 }
6302 break;
6303 default:
6304 assert(0);
6305 }
6306 }
6307 }
6308 }
6309
6310 /**
6311 * Check whether a PS prolog is required based on the key.
6312 */
6313 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6314 {
6315 return key->ps_prolog.colors_read ||
6316 key->ps_prolog.states.force_persp_sample_interp ||
6317 key->ps_prolog.states.force_linear_sample_interp ||
6318 key->ps_prolog.states.force_persp_center_interp ||
6319 key->ps_prolog.states.force_linear_center_interp ||
6320 key->ps_prolog.states.bc_optimize_for_persp ||
6321 key->ps_prolog.states.bc_optimize_for_linear ||
6322 key->ps_prolog.states.poly_stipple ||
6323 key->ps_prolog.states.samplemask_log_ps_iter;
6324 }
6325
6326 /**
6327 * Compute the PS epilog key, which contains all the information needed to
6328 * build the PS epilog function.
6329 */
6330 static void si_get_ps_epilog_key(struct si_shader *shader,
6331 union si_shader_part_key *key)
6332 {
6333 struct tgsi_shader_info *info = &shader->selector->info;
6334 memset(key, 0, sizeof(*key));
6335 key->ps_epilog.colors_written = info->colors_written;
6336 key->ps_epilog.writes_z = info->writes_z;
6337 key->ps_epilog.writes_stencil = info->writes_stencil;
6338 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6339 key->ps_epilog.states = shader->key.part.ps.epilog;
6340 }
6341
6342 /**
6343 * Build the GS prolog function. Rotate the input vertices for triangle strips
6344 * with adjacency.
6345 */
6346 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6347 union si_shader_part_key *key)
6348 {
6349 unsigned num_sgprs, num_vgprs;
6350 struct si_function_info fninfo;
6351 LLVMBuilderRef builder = ctx->ac.builder;
6352 LLVMTypeRef returns[48];
6353 LLVMValueRef func, ret;
6354
6355 si_init_function_info(&fninfo);
6356
6357 if (ctx->screen->info.chip_class >= GFX9) {
6358 if (key->gs_prolog.states.gfx9_prev_is_vs)
6359 num_sgprs = 8 + GFX9_VSGS_NUM_USER_SGPR;
6360 else
6361 num_sgprs = 8 + GFX9_TESGS_NUM_USER_SGPR;
6362 num_vgprs = 5; /* ES inputs are not needed by GS */
6363 } else {
6364 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6365 num_vgprs = 8;
6366 }
6367
6368 for (unsigned i = 0; i < num_sgprs; ++i) {
6369 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6370 returns[i] = ctx->i32;
6371 }
6372
6373 for (unsigned i = 0; i < num_vgprs; ++i) {
6374 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6375 returns[num_sgprs + i] = ctx->f32;
6376 }
6377
6378 /* Create the function. */
6379 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6380 &fninfo, 0);
6381 func = ctx->main_fn;
6382
6383 /* Set the full EXEC mask for the prolog, because we are only fiddling
6384 * with registers here. The main shader part will set the correct EXEC
6385 * mask.
6386 */
6387 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6388 ac_init_exec_full_mask(&ctx->ac);
6389
6390 /* Copy inputs to outputs. This should be no-op, as the registers match,
6391 * but it will prevent the compiler from overwriting them unintentionally.
6392 */
6393 ret = ctx->return_value;
6394 for (unsigned i = 0; i < num_sgprs; i++) {
6395 LLVMValueRef p = LLVMGetParam(func, i);
6396 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6397 }
6398 for (unsigned i = 0; i < num_vgprs; i++) {
6399 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6400 p = ac_to_float(&ctx->ac, p);
6401 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6402 }
6403
6404 if (key->gs_prolog.states.tri_strip_adj_fix) {
6405 /* Remap the input vertices for every other primitive. */
6406 const unsigned gfx6_vtx_params[6] = {
6407 num_sgprs,
6408 num_sgprs + 1,
6409 num_sgprs + 3,
6410 num_sgprs + 4,
6411 num_sgprs + 5,
6412 num_sgprs + 6
6413 };
6414 const unsigned gfx9_vtx_params[3] = {
6415 num_sgprs,
6416 num_sgprs + 1,
6417 num_sgprs + 4,
6418 };
6419 LLVMValueRef vtx_in[6], vtx_out[6];
6420 LLVMValueRef prim_id, rotate;
6421
6422 if (ctx->screen->info.chip_class >= GFX9) {
6423 for (unsigned i = 0; i < 3; i++) {
6424 vtx_in[i*2] = unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6425 vtx_in[i*2+1] = unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6426 }
6427 } else {
6428 for (unsigned i = 0; i < 6; i++)
6429 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6430 }
6431
6432 prim_id = LLVMGetParam(func, num_sgprs + 2);
6433 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6434
6435 for (unsigned i = 0; i < 6; ++i) {
6436 LLVMValueRef base, rotated;
6437 base = vtx_in[i];
6438 rotated = vtx_in[(i + 4) % 6];
6439 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6440 }
6441
6442 if (ctx->screen->info.chip_class >= GFX9) {
6443 for (unsigned i = 0; i < 3; i++) {
6444 LLVMValueRef hi, out;
6445
6446 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6447 LLVMConstInt(ctx->i32, 16, 0), "");
6448 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6449 out = ac_to_float(&ctx->ac, out);
6450 ret = LLVMBuildInsertValue(builder, ret, out,
6451 gfx9_vtx_params[i], "");
6452 }
6453 } else {
6454 for (unsigned i = 0; i < 6; i++) {
6455 LLVMValueRef out;
6456
6457 out = ac_to_float(&ctx->ac, vtx_out[i]);
6458 ret = LLVMBuildInsertValue(builder, ret, out,
6459 gfx6_vtx_params[i], "");
6460 }
6461 }
6462 }
6463
6464 LLVMBuildRet(builder, ret);
6465 }
6466
6467 /**
6468 * Given a list of shader part functions, build a wrapper function that
6469 * runs them in sequence to form a monolithic shader.
6470 */
6471 static void si_build_wrapper_function(struct si_shader_context *ctx,
6472 LLVMValueRef *parts,
6473 unsigned num_parts,
6474 unsigned main_part,
6475 unsigned next_shader_first_part)
6476 {
6477 LLVMBuilderRef builder = ctx->ac.builder;
6478 /* PS epilog has one arg per color component; gfx9 merged shader
6479 * prologs need to forward 32 user SGPRs.
6480 */
6481 struct si_function_info fninfo;
6482 LLVMValueRef initial[64], out[64];
6483 LLVMTypeRef function_type;
6484 unsigned num_first_params;
6485 unsigned num_out, initial_num_out;
6486 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6487 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6488 unsigned num_sgprs, num_vgprs;
6489 unsigned gprs;
6490 struct lp_build_if_state if_state;
6491
6492 si_init_function_info(&fninfo);
6493
6494 for (unsigned i = 0; i < num_parts; ++i) {
6495 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6496 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6497 }
6498
6499 /* The parameters of the wrapper function correspond to those of the
6500 * first part in terms of SGPRs and VGPRs, but we use the types of the
6501 * main part to get the right types. This is relevant for the
6502 * dereferenceable attribute on descriptor table pointers.
6503 */
6504 num_sgprs = 0;
6505 num_vgprs = 0;
6506
6507 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6508 num_first_params = LLVMCountParamTypes(function_type);
6509
6510 for (unsigned i = 0; i < num_first_params; ++i) {
6511 LLVMValueRef param = LLVMGetParam(parts[0], i);
6512
6513 if (ac_is_sgpr_param(param)) {
6514 assert(num_vgprs == 0);
6515 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6516 } else {
6517 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6518 }
6519 }
6520
6521 gprs = 0;
6522 while (gprs < num_sgprs + num_vgprs) {
6523 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6524 LLVMTypeRef type = LLVMTypeOf(param);
6525 unsigned size = ac_get_type_size(type) / 4;
6526
6527 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6528
6529 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6530 assert(gprs + size <= num_sgprs + num_vgprs &&
6531 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6532
6533 gprs += size;
6534 }
6535
6536 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6537 si_get_max_workgroup_size(ctx->shader));
6538
6539 if (is_merged_shader(ctx->shader))
6540 ac_init_exec_full_mask(&ctx->ac);
6541
6542 /* Record the arguments of the function as if they were an output of
6543 * a previous part.
6544 */
6545 num_out = 0;
6546 num_out_sgpr = 0;
6547
6548 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6549 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6550 LLVMTypeRef param_type = LLVMTypeOf(param);
6551 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6552 unsigned size = ac_get_type_size(param_type) / 4;
6553
6554 if (size == 1) {
6555 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6556 param = LLVMBuildPtrToInt(builder, param, ctx->i32, "");
6557 param_type = ctx->i32;
6558 }
6559
6560 if (param_type != out_type)
6561 param = LLVMBuildBitCast(builder, param, out_type, "");
6562 out[num_out++] = param;
6563 } else {
6564 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6565
6566 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6567 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6568 param_type = ctx->i64;
6569 }
6570
6571 if (param_type != vector_type)
6572 param = LLVMBuildBitCast(builder, param, vector_type, "");
6573
6574 for (unsigned j = 0; j < size; ++j)
6575 out[num_out++] = LLVMBuildExtractElement(
6576 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6577 }
6578
6579 if (i < fninfo.num_sgpr_params)
6580 num_out_sgpr = num_out;
6581 }
6582
6583 memcpy(initial, out, sizeof(out));
6584 initial_num_out = num_out;
6585 initial_num_out_sgpr = num_out_sgpr;
6586
6587 /* Now chain the parts. */
6588 for (unsigned part = 0; part < num_parts; ++part) {
6589 LLVMValueRef in[48];
6590 LLVMValueRef ret;
6591 LLVMTypeRef ret_type;
6592 unsigned out_idx = 0;
6593 unsigned num_params = LLVMCountParams(parts[part]);
6594
6595 /* Merged shaders are executed conditionally depending
6596 * on the number of enabled threads passed in the input SGPRs. */
6597 if (is_merged_shader(ctx->shader) && part == 0) {
6598 LLVMValueRef ena, count = initial[3];
6599
6600 count = LLVMBuildAnd(builder, count,
6601 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6602 ena = LLVMBuildICmp(builder, LLVMIntULT,
6603 ac_get_thread_id(&ctx->ac), count, "");
6604 lp_build_if(&if_state, &ctx->gallivm, ena);
6605 }
6606
6607 /* Derive arguments for the next part from outputs of the
6608 * previous one.
6609 */
6610 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6611 LLVMValueRef param;
6612 LLVMTypeRef param_type;
6613 bool is_sgpr;
6614 unsigned param_size;
6615 LLVMValueRef arg = NULL;
6616
6617 param = LLVMGetParam(parts[part], param_idx);
6618 param_type = LLVMTypeOf(param);
6619 param_size = ac_get_type_size(param_type) / 4;
6620 is_sgpr = ac_is_sgpr_param(param);
6621
6622 if (is_sgpr)
6623 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
6624 else if (out_idx < num_out_sgpr) {
6625 /* Skip returned SGPRs the current part doesn't
6626 * declare on the input. */
6627 out_idx = num_out_sgpr;
6628 }
6629
6630 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6631
6632 if (param_size == 1)
6633 arg = out[out_idx];
6634 else
6635 arg = lp_build_gather_values(&ctx->gallivm, &out[out_idx], param_size);
6636
6637 if (LLVMTypeOf(arg) != param_type) {
6638 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6639 if (LLVMGetPointerAddressSpace(param_type) ==
6640 AC_CONST_32BIT_ADDR_SPACE) {
6641 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
6642 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6643 } else {
6644 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6645 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6646 }
6647 } else {
6648 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6649 }
6650 }
6651
6652 in[param_idx] = arg;
6653 out_idx += param_size;
6654 }
6655
6656 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6657
6658 if (is_merged_shader(ctx->shader) &&
6659 part + 1 == next_shader_first_part) {
6660 lp_build_endif(&if_state);
6661
6662 /* The second half of the merged shader should use
6663 * the inputs from the toplevel (wrapper) function,
6664 * not the return value from the last call.
6665 *
6666 * That's because the last call was executed condi-
6667 * tionally, so we can't consume it in the main
6668 * block.
6669 */
6670 memcpy(out, initial, sizeof(initial));
6671 num_out = initial_num_out;
6672 num_out_sgpr = initial_num_out_sgpr;
6673 continue;
6674 }
6675
6676 /* Extract the returned GPRs. */
6677 ret_type = LLVMTypeOf(ret);
6678 num_out = 0;
6679 num_out_sgpr = 0;
6680
6681 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6682 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6683
6684 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6685
6686 for (unsigned i = 0; i < ret_size; ++i) {
6687 LLVMValueRef val =
6688 LLVMBuildExtractValue(builder, ret, i, "");
6689
6690 assert(num_out < ARRAY_SIZE(out));
6691 out[num_out++] = val;
6692
6693 if (LLVMTypeOf(val) == ctx->i32) {
6694 assert(num_out_sgpr + 1 == num_out);
6695 num_out_sgpr = num_out;
6696 }
6697 }
6698 }
6699 }
6700
6701 LLVMBuildRetVoid(builder);
6702 }
6703
6704 int si_compile_tgsi_shader(struct si_screen *sscreen,
6705 LLVMTargetMachineRef tm,
6706 struct si_shader *shader,
6707 bool is_monolithic,
6708 struct pipe_debug_callback *debug)
6709 {
6710 struct si_shader_selector *sel = shader->selector;
6711 struct si_shader_context ctx;
6712 int r = -1;
6713
6714 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6715 * conversion fails. */
6716 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6717 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6718 if (sel->tokens)
6719 tgsi_dump(sel->tokens, 0);
6720 else
6721 nir_print_shader(sel->nir, stderr);
6722 si_dump_streamout(&sel->so);
6723 }
6724
6725 si_init_shader_ctx(&ctx, sscreen, tm);
6726 si_llvm_context_set_tgsi(&ctx, shader);
6727 ctx.separate_prolog = !is_monolithic;
6728
6729 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6730 sizeof(shader->info.vs_output_param_offset));
6731
6732 shader->info.uses_instanceid = sel->info.uses_instanceid;
6733
6734 if (!si_compile_tgsi_main(&ctx, is_monolithic)) {
6735 si_llvm_dispose(&ctx);
6736 return -1;
6737 }
6738
6739 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6740 LLVMValueRef parts[2];
6741 bool need_prolog = sel->vs_needs_prolog;
6742
6743 parts[1] = ctx.main_fn;
6744
6745 if (need_prolog) {
6746 union si_shader_part_key prolog_key;
6747 si_get_vs_prolog_key(&sel->info,
6748 shader->info.num_input_sgprs,
6749 &shader->key.part.vs.prolog,
6750 shader, &prolog_key);
6751 si_build_vs_prolog_function(&ctx, &prolog_key);
6752 parts[0] = ctx.main_fn;
6753 }
6754
6755 si_build_wrapper_function(&ctx, parts + !need_prolog,
6756 1 + need_prolog, need_prolog, 0);
6757 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6758 if (sscreen->info.chip_class >= GFX9) {
6759 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6760 LLVMValueRef parts[4];
6761 bool vs_needs_prolog =
6762 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6763
6764 /* TCS main part */
6765 parts[2] = ctx.main_fn;
6766
6767 /* TCS epilog */
6768 union si_shader_part_key tcs_epilog_key;
6769 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6770 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6771 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6772 parts[3] = ctx.main_fn;
6773
6774 /* VS as LS main part */
6775 struct si_shader shader_ls = {};
6776 shader_ls.selector = ls;
6777 shader_ls.key.as_ls = 1;
6778 shader_ls.key.mono = shader->key.mono;
6779 shader_ls.key.opt = shader->key.opt;
6780 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6781
6782 if (!si_compile_tgsi_main(&ctx, true)) {
6783 si_llvm_dispose(&ctx);
6784 return -1;
6785 }
6786 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6787 parts[1] = ctx.main_fn;
6788
6789 /* LS prolog */
6790 if (vs_needs_prolog) {
6791 union si_shader_part_key vs_prolog_key;
6792 si_get_vs_prolog_key(&ls->info,
6793 shader_ls.info.num_input_sgprs,
6794 &shader->key.part.tcs.ls_prolog,
6795 shader, &vs_prolog_key);
6796 vs_prolog_key.vs_prolog.is_monolithic = true;
6797 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6798 parts[0] = ctx.main_fn;
6799 }
6800
6801 /* Reset the shader context. */
6802 ctx.shader = shader;
6803 ctx.type = PIPE_SHADER_TESS_CTRL;
6804
6805 si_build_wrapper_function(&ctx,
6806 parts + !vs_needs_prolog,
6807 4 - !vs_needs_prolog, 0,
6808 vs_needs_prolog ? 2 : 1);
6809 } else {
6810 LLVMValueRef parts[2];
6811 union si_shader_part_key epilog_key;
6812
6813 parts[0] = ctx.main_fn;
6814
6815 memset(&epilog_key, 0, sizeof(epilog_key));
6816 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6817 si_build_tcs_epilog_function(&ctx, &epilog_key);
6818 parts[1] = ctx.main_fn;
6819
6820 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6821 }
6822 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6823 if (ctx.screen->info.chip_class >= GFX9) {
6824 struct si_shader_selector *es = shader->key.part.gs.es;
6825 LLVMValueRef es_prolog = NULL;
6826 LLVMValueRef es_main = NULL;
6827 LLVMValueRef gs_prolog = NULL;
6828 LLVMValueRef gs_main = ctx.main_fn;
6829
6830 /* GS prolog */
6831 union si_shader_part_key gs_prolog_key;
6832 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6833 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6834 gs_prolog_key.gs_prolog.is_monolithic = true;
6835 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6836 gs_prolog = ctx.main_fn;
6837
6838 /* ES main part */
6839 struct si_shader shader_es = {};
6840 shader_es.selector = es;
6841 shader_es.key.as_es = 1;
6842 shader_es.key.mono = shader->key.mono;
6843 shader_es.key.opt = shader->key.opt;
6844 si_llvm_context_set_tgsi(&ctx, &shader_es);
6845
6846 if (!si_compile_tgsi_main(&ctx, true)) {
6847 si_llvm_dispose(&ctx);
6848 return -1;
6849 }
6850 shader->info.uses_instanceid |= es->info.uses_instanceid;
6851 es_main = ctx.main_fn;
6852
6853 /* ES prolog */
6854 if (es->vs_needs_prolog) {
6855 union si_shader_part_key vs_prolog_key;
6856 si_get_vs_prolog_key(&es->info,
6857 shader_es.info.num_input_sgprs,
6858 &shader->key.part.gs.vs_prolog,
6859 shader, &vs_prolog_key);
6860 vs_prolog_key.vs_prolog.is_monolithic = true;
6861 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6862 es_prolog = ctx.main_fn;
6863 }
6864
6865 /* Reset the shader context. */
6866 ctx.shader = shader;
6867 ctx.type = PIPE_SHADER_GEOMETRY;
6868
6869 /* Prepare the array of shader parts. */
6870 LLVMValueRef parts[4];
6871 unsigned num_parts = 0, main_part, next_first_part;
6872
6873 if (es_prolog)
6874 parts[num_parts++] = es_prolog;
6875
6876 parts[main_part = num_parts++] = es_main;
6877 parts[next_first_part = num_parts++] = gs_prolog;
6878 parts[num_parts++] = gs_main;
6879
6880 si_build_wrapper_function(&ctx, parts, num_parts,
6881 main_part, next_first_part);
6882 } else {
6883 LLVMValueRef parts[2];
6884 union si_shader_part_key prolog_key;
6885
6886 parts[1] = ctx.main_fn;
6887
6888 memset(&prolog_key, 0, sizeof(prolog_key));
6889 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6890 si_build_gs_prolog_function(&ctx, &prolog_key);
6891 parts[0] = ctx.main_fn;
6892
6893 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6894 }
6895 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6896 LLVMValueRef parts[3];
6897 union si_shader_part_key prolog_key;
6898 union si_shader_part_key epilog_key;
6899 bool need_prolog;
6900
6901 si_get_ps_prolog_key(shader, &prolog_key, false);
6902 need_prolog = si_need_ps_prolog(&prolog_key);
6903
6904 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6905
6906 if (need_prolog) {
6907 si_build_ps_prolog_function(&ctx, &prolog_key);
6908 parts[0] = ctx.main_fn;
6909 }
6910
6911 si_get_ps_epilog_key(shader, &epilog_key);
6912 si_build_ps_epilog_function(&ctx, &epilog_key);
6913 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6914
6915 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6916 need_prolog ? 1 : 0, 0);
6917 }
6918
6919 si_llvm_optimize_module(&ctx);
6920
6921 /* Post-optimization transformations and analysis. */
6922 si_optimize_vs_outputs(&ctx);
6923
6924 if ((debug && debug->debug_message) ||
6925 si_can_dump_shader(sscreen, ctx.type))
6926 si_count_scratch_private_memory(&ctx);
6927
6928 /* Compile to bytecode. */
6929 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6930 ctx.gallivm.module, debug, ctx.type, "TGSI shader");
6931 si_llvm_dispose(&ctx);
6932 if (r) {
6933 fprintf(stderr, "LLVM failed to compile shader\n");
6934 return r;
6935 }
6936
6937 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6938 * LLVM 3.9svn has this bug.
6939 */
6940 if (sel->type == PIPE_SHADER_COMPUTE) {
6941 unsigned wave_size = 64;
6942 unsigned max_vgprs = 256;
6943 unsigned max_sgprs = sscreen->info.chip_class >= VI ? 800 : 512;
6944 unsigned max_sgprs_per_wave = 128;
6945 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6946 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6947 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6948
6949 max_vgprs = max_vgprs / min_waves_per_simd;
6950 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6951
6952 if (shader->config.num_sgprs > max_sgprs ||
6953 shader->config.num_vgprs > max_vgprs) {
6954 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6955 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6956 shader->config.num_sgprs, shader->config.num_vgprs,
6957 max_sgprs, max_vgprs);
6958
6959 /* Just terminate the process, because dependent
6960 * shaders can hang due to bad input data, but use
6961 * the env var to allow shader-db to work.
6962 */
6963 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6964 abort();
6965 }
6966 }
6967
6968 /* Add the scratch offset to input SGPRs. */
6969 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(shader))
6970 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6971
6972 /* Calculate the number of fragment input VGPRs. */
6973 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6974 shader->info.num_input_vgprs = 0;
6975 shader->info.face_vgpr_index = -1;
6976 shader->info.ancillary_vgpr_index = -1;
6977
6978 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6979 shader->info.num_input_vgprs += 2;
6980 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6981 shader->info.num_input_vgprs += 2;
6982 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6983 shader->info.num_input_vgprs += 2;
6984 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6985 shader->info.num_input_vgprs += 3;
6986 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6987 shader->info.num_input_vgprs += 2;
6988 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6989 shader->info.num_input_vgprs += 2;
6990 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6991 shader->info.num_input_vgprs += 2;
6992 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6993 shader->info.num_input_vgprs += 1;
6994 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6995 shader->info.num_input_vgprs += 1;
6996 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6997 shader->info.num_input_vgprs += 1;
6998 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6999 shader->info.num_input_vgprs += 1;
7000 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7001 shader->info.num_input_vgprs += 1;
7002 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7003 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7004 shader->info.num_input_vgprs += 1;
7005 }
7006 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
7007 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
7008 shader->info.num_input_vgprs += 1;
7009 }
7010 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7011 shader->info.num_input_vgprs += 1;
7012 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7013 shader->info.num_input_vgprs += 1;
7014 }
7015
7016 si_calculate_max_simd_waves(shader);
7017 si_shader_dump_stats_for_shader_db(shader, debug);
7018 return 0;
7019 }
7020
7021 /**
7022 * Create, compile and return a shader part (prolog or epilog).
7023 *
7024 * \param sscreen screen
7025 * \param list list of shader parts of the same category
7026 * \param type shader type
7027 * \param key shader part key
7028 * \param prolog whether the part being requested is a prolog
7029 * \param tm LLVM target machine
7030 * \param debug debug callback
7031 * \param build the callback responsible for building the main function
7032 * \return non-NULL on success
7033 */
7034 static struct si_shader_part *
7035 si_get_shader_part(struct si_screen *sscreen,
7036 struct si_shader_part **list,
7037 enum pipe_shader_type type,
7038 bool prolog,
7039 union si_shader_part_key *key,
7040 LLVMTargetMachineRef tm,
7041 struct pipe_debug_callback *debug,
7042 void (*build)(struct si_shader_context *,
7043 union si_shader_part_key *),
7044 const char *name)
7045 {
7046 struct si_shader_part *result;
7047
7048 mtx_lock(&sscreen->shader_parts_mutex);
7049
7050 /* Find existing. */
7051 for (result = *list; result; result = result->next) {
7052 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7053 mtx_unlock(&sscreen->shader_parts_mutex);
7054 return result;
7055 }
7056 }
7057
7058 /* Compile a new one. */
7059 result = CALLOC_STRUCT(si_shader_part);
7060 result->key = *key;
7061
7062 struct si_shader shader = {};
7063 struct si_shader_context ctx;
7064
7065 si_init_shader_ctx(&ctx, sscreen, tm);
7066 ctx.shader = &shader;
7067 ctx.type = type;
7068
7069 switch (type) {
7070 case PIPE_SHADER_VERTEX:
7071 shader.key.as_ls = key->vs_prolog.as_ls;
7072 shader.key.as_es = key->vs_prolog.as_es;
7073 break;
7074 case PIPE_SHADER_TESS_CTRL:
7075 assert(!prolog);
7076 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7077 break;
7078 case PIPE_SHADER_GEOMETRY:
7079 assert(prolog);
7080 break;
7081 case PIPE_SHADER_FRAGMENT:
7082 if (prolog)
7083 shader.key.part.ps.prolog = key->ps_prolog.states;
7084 else
7085 shader.key.part.ps.epilog = key->ps_epilog.states;
7086 break;
7087 default:
7088 unreachable("bad shader part");
7089 }
7090
7091 build(&ctx, key);
7092
7093 /* Compile. */
7094 si_llvm_optimize_module(&ctx);
7095
7096 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7097 ctx.ac.module, debug, ctx.type, name)) {
7098 FREE(result);
7099 result = NULL;
7100 goto out;
7101 }
7102
7103 result->next = *list;
7104 *list = result;
7105
7106 out:
7107 si_llvm_dispose(&ctx);
7108 mtx_unlock(&sscreen->shader_parts_mutex);
7109 return result;
7110 }
7111
7112 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
7113 {
7114 LLVMValueRef ptr[2], list;
7115 bool is_merged_shader =
7116 ctx->screen->info.chip_class >= GFX9 &&
7117 (ctx->type == PIPE_SHADER_TESS_CTRL ||
7118 ctx->type == PIPE_SHADER_GEOMETRY ||
7119 ctx->shader->key.as_ls || ctx->shader->key.as_es);
7120
7121 if (HAVE_32BIT_POINTERS) {
7122 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7123 list = LLVMBuildIntToPtr(ctx->ac.builder, ptr[0],
7124 ac_array_in_const32_addr_space(ctx->v4i32), "");
7125 return list;
7126 }
7127
7128 /* Get the pointer to rw buffers. */
7129 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7130 ptr[1] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS + 1);
7131 list = lp_build_gather_values(&ctx->gallivm, ptr, 2);
7132 list = LLVMBuildBitCast(ctx->ac.builder, list, ctx->i64, "");
7133 list = LLVMBuildIntToPtr(ctx->ac.builder, list,
7134 ac_array_in_const_addr_space(ctx->v4i32), "");
7135 return list;
7136 }
7137
7138 /**
7139 * Build the vertex shader prolog function.
7140 *
7141 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7142 * All inputs are returned unmodified. The vertex load indices are
7143 * stored after them, which will be used by the API VS for fetching inputs.
7144 *
7145 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7146 * input_v0,
7147 * input_v1,
7148 * input_v2,
7149 * input_v3,
7150 * (VertexID + BaseVertex),
7151 * (InstanceID + StartInstance),
7152 * (InstanceID / 2 + StartInstance)
7153 */
7154 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7155 union si_shader_part_key *key)
7156 {
7157 struct si_function_info fninfo;
7158 LLVMTypeRef *returns;
7159 LLVMValueRef ret, func;
7160 int num_returns, i;
7161 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
7162 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
7163 LLVMValueRef input_vgprs[9];
7164 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
7165 num_input_vgprs;
7166 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
7167
7168 si_init_function_info(&fninfo);
7169
7170 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7171 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
7172 sizeof(LLVMTypeRef));
7173 num_returns = 0;
7174
7175 /* Declare input and output SGPRs. */
7176 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7177 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7178 returns[num_returns++] = ctx->i32;
7179 }
7180
7181 /* Preloaded VGPRs (outputs must be floats) */
7182 for (i = 0; i < num_input_vgprs; i++) {
7183 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
7184 returns[num_returns++] = ctx->f32;
7185 }
7186
7187 /* Vertex load indices. */
7188 for (i = 0; i <= key->vs_prolog.last_input; i++)
7189 returns[num_returns++] = ctx->f32;
7190
7191 /* Create the function. */
7192 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
7193 func = ctx->main_fn;
7194
7195 if (key->vs_prolog.num_merged_next_stage_vgprs) {
7196 if (!key->vs_prolog.is_monolithic)
7197 si_init_exec_from_input(ctx, 3, 0);
7198
7199 if (key->vs_prolog.as_ls &&
7200 ctx->screen->has_ls_vgpr_init_bug) {
7201 /* If there are no HS threads, SPI loads the LS VGPRs
7202 * starting at VGPR 0. Shift them back to where they
7203 * belong.
7204 */
7205 LLVMValueRef has_hs_threads =
7206 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
7207 unpack_param(ctx, 3, 8, 8),
7208 ctx->i32_0, "");
7209
7210 for (i = 4; i > 0; --i) {
7211 input_vgprs[i + 1] =
7212 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
7213 input_vgprs[i + 1],
7214 input_vgprs[i - 1], "");
7215 }
7216 }
7217 }
7218
7219 ctx->abi.vertex_id = input_vgprs[first_vs_vgpr];
7220 ctx->abi.instance_id = input_vgprs[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)];
7221
7222 /* Copy inputs to outputs. This should be no-op, as the registers match,
7223 * but it will prevent the compiler from overwriting them unintentionally.
7224 */
7225 ret = ctx->return_value;
7226 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7227 LLVMValueRef p = LLVMGetParam(func, i);
7228 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7229 }
7230 for (i = 0; i < num_input_vgprs; i++) {
7231 LLVMValueRef p = input_vgprs[i];
7232 p = ac_to_float(&ctx->ac, p);
7233 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
7234 key->vs_prolog.num_input_sgprs + i, "");
7235 }
7236
7237 /* Compute vertex load indices from instance divisors. */
7238 LLVMValueRef instance_divisor_constbuf = NULL;
7239
7240 if (key->vs_prolog.states.instance_divisor_is_fetched) {
7241 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7242 LLVMValueRef buf_index =
7243 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
7244 instance_divisor_constbuf =
7245 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
7246 }
7247
7248 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7249 bool divisor_is_one =
7250 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
7251 bool divisor_is_fetched =
7252 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
7253 LLVMValueRef index;
7254
7255 if (divisor_is_one || divisor_is_fetched) {
7256 LLVMValueRef divisor = ctx->i32_1;
7257
7258 if (divisor_is_fetched) {
7259 divisor = buffer_load_const(ctx, instance_divisor_constbuf,
7260 LLVMConstInt(ctx->i32, i * 4, 0));
7261 divisor = ac_to_integer(&ctx->ac, divisor);
7262 }
7263
7264 /* InstanceID / Divisor + StartInstance */
7265 index = get_instance_index_for_fetch(ctx,
7266 user_sgpr_base +
7267 SI_SGPR_START_INSTANCE,
7268 divisor);
7269 } else {
7270 /* VertexID + BaseVertex */
7271 index = LLVMBuildAdd(ctx->ac.builder,
7272 ctx->abi.vertex_id,
7273 LLVMGetParam(func, user_sgpr_base +
7274 SI_SGPR_BASE_VERTEX), "");
7275 }
7276
7277 index = ac_to_float(&ctx->ac, index);
7278 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7279 fninfo.num_params + i, "");
7280 }
7281
7282 si_llvm_build_ret(ctx, ret);
7283 }
7284
7285 static bool si_get_vs_prolog(struct si_screen *sscreen,
7286 LLVMTargetMachineRef tm,
7287 struct si_shader *shader,
7288 struct pipe_debug_callback *debug,
7289 struct si_shader *main_part,
7290 const struct si_vs_prolog_bits *key)
7291 {
7292 struct si_shader_selector *vs = main_part->selector;
7293
7294 if (!si_vs_needs_prolog(vs, key))
7295 return true;
7296
7297 /* Get the prolog. */
7298 union si_shader_part_key prolog_key;
7299 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7300 key, shader, &prolog_key);
7301
7302 shader->prolog =
7303 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7304 PIPE_SHADER_VERTEX, true, &prolog_key, tm,
7305 debug, si_build_vs_prolog_function,
7306 "Vertex Shader Prolog");
7307 return shader->prolog != NULL;
7308 }
7309
7310 /**
7311 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7312 */
7313 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7314 LLVMTargetMachineRef tm,
7315 struct si_shader *shader,
7316 struct pipe_debug_callback *debug)
7317 {
7318 return si_get_vs_prolog(sscreen, tm, shader, debug, shader,
7319 &shader->key.part.vs.prolog);
7320 }
7321
7322 /**
7323 * Compile the TCS epilog function. This writes tesselation factors to memory
7324 * based on the output primitive type of the tesselator (determined by TES).
7325 */
7326 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7327 union si_shader_part_key *key)
7328 {
7329 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7330 struct si_function_info fninfo;
7331 LLVMValueRef func;
7332
7333 si_init_function_info(&fninfo);
7334
7335 if (ctx->screen->info.chip_class >= GFX9) {
7336 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7337 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7338 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7339 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7340 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7341 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7342 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7343 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7344 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7345 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7346 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7347 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7348 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7349 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7350 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7351 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7352 if (!HAVE_32BIT_POINTERS)
7353 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7354 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7355 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7356 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7357 } else {
7358 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7359 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7360 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7361 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7362 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7363 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7364 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7365 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7366 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7367 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7368 }
7369
7370 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7371 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7372 unsigned tess_factors_idx =
7373 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7374 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7375 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7376
7377 for (unsigned i = 0; i < 6; i++)
7378 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7379
7380 /* Create the function. */
7381 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7382 ctx->screen->info.chip_class >= CIK ? 128 : 64);
7383 ac_declare_lds_as_pointer(&ctx->ac);
7384 func = ctx->main_fn;
7385
7386 LLVMValueRef invoc0_tess_factors[6];
7387 for (unsigned i = 0; i < 6; i++)
7388 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7389
7390 si_write_tess_factors(bld_base,
7391 LLVMGetParam(func, tess_factors_idx),
7392 LLVMGetParam(func, tess_factors_idx + 1),
7393 LLVMGetParam(func, tess_factors_idx + 2),
7394 invoc0_tess_factors, invoc0_tess_factors + 4);
7395
7396 LLVMBuildRetVoid(ctx->ac.builder);
7397 }
7398
7399 /**
7400 * Select and compile (or reuse) TCS parts (epilog).
7401 */
7402 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7403 LLVMTargetMachineRef tm,
7404 struct si_shader *shader,
7405 struct pipe_debug_callback *debug)
7406 {
7407 if (sscreen->info.chip_class >= GFX9) {
7408 struct si_shader *ls_main_part =
7409 shader->key.part.tcs.ls->main_shader_part_ls;
7410
7411 if (!si_get_vs_prolog(sscreen, tm, shader, debug, ls_main_part,
7412 &shader->key.part.tcs.ls_prolog))
7413 return false;
7414
7415 shader->previous_stage = ls_main_part;
7416 }
7417
7418 /* Get the epilog. */
7419 union si_shader_part_key epilog_key;
7420 memset(&epilog_key, 0, sizeof(epilog_key));
7421 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7422
7423 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7424 PIPE_SHADER_TESS_CTRL, false,
7425 &epilog_key, tm, debug,
7426 si_build_tcs_epilog_function,
7427 "Tessellation Control Shader Epilog");
7428 return shader->epilog != NULL;
7429 }
7430
7431 /**
7432 * Select and compile (or reuse) GS parts (prolog).
7433 */
7434 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7435 LLVMTargetMachineRef tm,
7436 struct si_shader *shader,
7437 struct pipe_debug_callback *debug)
7438 {
7439 if (sscreen->info.chip_class >= GFX9) {
7440 struct si_shader *es_main_part =
7441 shader->key.part.gs.es->main_shader_part_es;
7442
7443 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7444 !si_get_vs_prolog(sscreen, tm, shader, debug, es_main_part,
7445 &shader->key.part.gs.vs_prolog))
7446 return false;
7447
7448 shader->previous_stage = es_main_part;
7449 }
7450
7451 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7452 return true;
7453
7454 union si_shader_part_key prolog_key;
7455 memset(&prolog_key, 0, sizeof(prolog_key));
7456 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7457
7458 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7459 PIPE_SHADER_GEOMETRY, true,
7460 &prolog_key, tm, debug,
7461 si_build_gs_prolog_function,
7462 "Geometry Shader Prolog");
7463 return shader->prolog2 != NULL;
7464 }
7465
7466 /**
7467 * Build the pixel shader prolog function. This handles:
7468 * - two-side color selection and interpolation
7469 * - overriding interpolation parameters for the API PS
7470 * - polygon stippling
7471 *
7472 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7473 * overriden by other states. (e.g. per-sample interpolation)
7474 * Interpolated colors are stored after the preloaded VGPRs.
7475 */
7476 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7477 union si_shader_part_key *key)
7478 {
7479 struct si_function_info fninfo;
7480 LLVMValueRef ret, func;
7481 int num_returns, i, num_color_channels;
7482
7483 assert(si_need_ps_prolog(key));
7484
7485 si_init_function_info(&fninfo);
7486
7487 /* Declare inputs. */
7488 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7489 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7490
7491 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7492 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7493
7494 /* Declare outputs (same as inputs + add colors if needed) */
7495 num_returns = fninfo.num_params;
7496 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7497 for (i = 0; i < num_color_channels; i++)
7498 fninfo.types[num_returns++] = ctx->f32;
7499
7500 /* Create the function. */
7501 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7502 &fninfo, 0);
7503 func = ctx->main_fn;
7504
7505 /* Copy inputs to outputs. This should be no-op, as the registers match,
7506 * but it will prevent the compiler from overwriting them unintentionally.
7507 */
7508 ret = ctx->return_value;
7509 for (i = 0; i < fninfo.num_params; i++) {
7510 LLVMValueRef p = LLVMGetParam(func, i);
7511 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7512 }
7513
7514 /* Polygon stippling. */
7515 if (key->ps_prolog.states.poly_stipple) {
7516 /* POS_FIXED_PT is always last. */
7517 unsigned pos = key->ps_prolog.num_input_sgprs +
7518 key->ps_prolog.num_input_vgprs - 1;
7519 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7520
7521 si_llvm_emit_polygon_stipple(ctx, list, pos);
7522 }
7523
7524 if (key->ps_prolog.states.bc_optimize_for_persp ||
7525 key->ps_prolog.states.bc_optimize_for_linear) {
7526 unsigned i, base = key->ps_prolog.num_input_sgprs;
7527 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7528
7529 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7530 * The hw doesn't compute CENTROID if the whole wave only
7531 * contains fully-covered quads.
7532 *
7533 * PRIM_MASK is after user SGPRs.
7534 */
7535 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7536 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7537 LLVMConstInt(ctx->i32, 31, 0), "");
7538 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7539 ctx->i1, "");
7540
7541 if (key->ps_prolog.states.bc_optimize_for_persp) {
7542 /* Read PERSP_CENTER. */
7543 for (i = 0; i < 2; i++)
7544 center[i] = LLVMGetParam(func, base + 2 + i);
7545 /* Read PERSP_CENTROID. */
7546 for (i = 0; i < 2; i++)
7547 centroid[i] = LLVMGetParam(func, base + 4 + i);
7548 /* Select PERSP_CENTROID. */
7549 for (i = 0; i < 2; i++) {
7550 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7551 center[i], centroid[i], "");
7552 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7553 tmp, base + 4 + i, "");
7554 }
7555 }
7556 if (key->ps_prolog.states.bc_optimize_for_linear) {
7557 /* Read LINEAR_CENTER. */
7558 for (i = 0; i < 2; i++)
7559 center[i] = LLVMGetParam(func, base + 8 + i);
7560 /* Read LINEAR_CENTROID. */
7561 for (i = 0; i < 2; i++)
7562 centroid[i] = LLVMGetParam(func, base + 10 + i);
7563 /* Select LINEAR_CENTROID. */
7564 for (i = 0; i < 2; i++) {
7565 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7566 center[i], centroid[i], "");
7567 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7568 tmp, base + 10 + i, "");
7569 }
7570 }
7571 }
7572
7573 /* Force per-sample interpolation. */
7574 if (key->ps_prolog.states.force_persp_sample_interp) {
7575 unsigned i, base = key->ps_prolog.num_input_sgprs;
7576 LLVMValueRef persp_sample[2];
7577
7578 /* Read PERSP_SAMPLE. */
7579 for (i = 0; i < 2; i++)
7580 persp_sample[i] = LLVMGetParam(func, base + i);
7581 /* Overwrite PERSP_CENTER. */
7582 for (i = 0; i < 2; i++)
7583 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7584 persp_sample[i], base + 2 + i, "");
7585 /* Overwrite PERSP_CENTROID. */
7586 for (i = 0; i < 2; i++)
7587 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7588 persp_sample[i], base + 4 + i, "");
7589 }
7590 if (key->ps_prolog.states.force_linear_sample_interp) {
7591 unsigned i, base = key->ps_prolog.num_input_sgprs;
7592 LLVMValueRef linear_sample[2];
7593
7594 /* Read LINEAR_SAMPLE. */
7595 for (i = 0; i < 2; i++)
7596 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7597 /* Overwrite LINEAR_CENTER. */
7598 for (i = 0; i < 2; i++)
7599 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7600 linear_sample[i], base + 8 + i, "");
7601 /* Overwrite LINEAR_CENTROID. */
7602 for (i = 0; i < 2; i++)
7603 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7604 linear_sample[i], base + 10 + i, "");
7605 }
7606
7607 /* Force center interpolation. */
7608 if (key->ps_prolog.states.force_persp_center_interp) {
7609 unsigned i, base = key->ps_prolog.num_input_sgprs;
7610 LLVMValueRef persp_center[2];
7611
7612 /* Read PERSP_CENTER. */
7613 for (i = 0; i < 2; i++)
7614 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7615 /* Overwrite PERSP_SAMPLE. */
7616 for (i = 0; i < 2; i++)
7617 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7618 persp_center[i], base + i, "");
7619 /* Overwrite PERSP_CENTROID. */
7620 for (i = 0; i < 2; i++)
7621 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7622 persp_center[i], base + 4 + i, "");
7623 }
7624 if (key->ps_prolog.states.force_linear_center_interp) {
7625 unsigned i, base = key->ps_prolog.num_input_sgprs;
7626 LLVMValueRef linear_center[2];
7627
7628 /* Read LINEAR_CENTER. */
7629 for (i = 0; i < 2; i++)
7630 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7631 /* Overwrite LINEAR_SAMPLE. */
7632 for (i = 0; i < 2; i++)
7633 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7634 linear_center[i], base + 6 + i, "");
7635 /* Overwrite LINEAR_CENTROID. */
7636 for (i = 0; i < 2; i++)
7637 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7638 linear_center[i], base + 10 + i, "");
7639 }
7640
7641 /* Interpolate colors. */
7642 unsigned color_out_idx = 0;
7643 for (i = 0; i < 2; i++) {
7644 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7645 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7646 key->ps_prolog.face_vgpr_index;
7647 LLVMValueRef interp[2], color[4];
7648 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7649
7650 if (!writemask)
7651 continue;
7652
7653 /* If the interpolation qualifier is not CONSTANT (-1). */
7654 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7655 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7656 key->ps_prolog.color_interp_vgpr_index[i];
7657
7658 /* Get the (i,j) updated by bc_optimize handling. */
7659 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7660 interp_vgpr, "");
7661 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7662 interp_vgpr + 1, "");
7663 interp_ij = lp_build_gather_values(&ctx->gallivm, interp, 2);
7664 }
7665
7666 /* Use the absolute location of the input. */
7667 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7668
7669 if (key->ps_prolog.states.color_two_side) {
7670 face = LLVMGetParam(func, face_vgpr);
7671 face = ac_to_integer(&ctx->ac, face);
7672 }
7673
7674 interp_fs_input(ctx,
7675 key->ps_prolog.color_attr_index[i],
7676 TGSI_SEMANTIC_COLOR, i,
7677 key->ps_prolog.num_interp_inputs,
7678 key->ps_prolog.colors_read, interp_ij,
7679 prim_mask, face, color);
7680
7681 while (writemask) {
7682 unsigned chan = u_bit_scan(&writemask);
7683 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7684 fninfo.num_params + color_out_idx++, "");
7685 }
7686 }
7687
7688 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7689 * says:
7690 *
7691 * "When per-sample shading is active due to the use of a fragment
7692 * input qualified by sample or due to the use of the gl_SampleID
7693 * or gl_SamplePosition variables, only the bit for the current
7694 * sample is set in gl_SampleMaskIn. When state specifies multiple
7695 * fragment shader invocations for a given fragment, the sample
7696 * mask for any single fragment shader invocation may specify a
7697 * subset of the covered samples for the fragment. In this case,
7698 * the bit corresponding to each covered sample will be set in
7699 * exactly one fragment shader invocation."
7700 *
7701 * The samplemask loaded by hardware is always the coverage of the
7702 * entire pixel/fragment, so mask bits out based on the sample ID.
7703 */
7704 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7705 /* The bit pattern matches that used by fixed function fragment
7706 * processing. */
7707 static const uint16_t ps_iter_masks[] = {
7708 0xffff, /* not used */
7709 0x5555,
7710 0x1111,
7711 0x0101,
7712 0x0001,
7713 };
7714 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7715
7716 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7717 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7718 key->ps_prolog.ancillary_vgpr_index;
7719 LLVMValueRef sampleid = unpack_param(ctx, ancillary_vgpr, 8, 4);
7720 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7721
7722 samplemask = ac_to_integer(&ctx->ac, samplemask);
7723 samplemask = LLVMBuildAnd(
7724 ctx->ac.builder,
7725 samplemask,
7726 LLVMBuildShl(ctx->ac.builder,
7727 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7728 sampleid, ""),
7729 "");
7730 samplemask = ac_to_float(&ctx->ac, samplemask);
7731
7732 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7733 ancillary_vgpr + 1, "");
7734 }
7735
7736 /* Tell LLVM to insert WQM instruction sequence when needed. */
7737 if (key->ps_prolog.wqm) {
7738 LLVMAddTargetDependentFunctionAttr(func,
7739 "amdgpu-ps-wqm-outputs", "");
7740 }
7741
7742 si_llvm_build_ret(ctx, ret);
7743 }
7744
7745 /**
7746 * Build the pixel shader epilog function. This handles everything that must be
7747 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7748 */
7749 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7750 union si_shader_part_key *key)
7751 {
7752 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7753 struct si_function_info fninfo;
7754 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7755 int i;
7756 struct si_ps_exports exp = {};
7757
7758 si_init_function_info(&fninfo);
7759
7760 /* Declare input SGPRs. */
7761 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7762 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7763 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7764 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7765 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7766
7767 /* Declare input VGPRs. */
7768 unsigned required_num_params =
7769 fninfo.num_sgpr_params +
7770 util_bitcount(key->ps_epilog.colors_written) * 4 +
7771 key->ps_epilog.writes_z +
7772 key->ps_epilog.writes_stencil +
7773 key->ps_epilog.writes_samplemask;
7774
7775 required_num_params = MAX2(required_num_params,
7776 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7777
7778 while (fninfo.num_params < required_num_params)
7779 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7780
7781 /* Create the function. */
7782 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7783 /* Disable elimination of unused inputs. */
7784 si_llvm_add_attribute(ctx->main_fn,
7785 "InitialPSInputAddr", 0xffffff);
7786
7787 /* Process colors. */
7788 unsigned vgpr = fninfo.num_sgpr_params;
7789 unsigned colors_written = key->ps_epilog.colors_written;
7790 int last_color_export = -1;
7791
7792 /* Find the last color export. */
7793 if (!key->ps_epilog.writes_z &&
7794 !key->ps_epilog.writes_stencil &&
7795 !key->ps_epilog.writes_samplemask) {
7796 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7797
7798 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7799 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7800 /* Just set this if any of the colorbuffers are enabled. */
7801 if (spi_format &
7802 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7803 last_color_export = 0;
7804 } else {
7805 for (i = 0; i < 8; i++)
7806 if (colors_written & (1 << i) &&
7807 (spi_format >> (i * 4)) & 0xf)
7808 last_color_export = i;
7809 }
7810 }
7811
7812 while (colors_written) {
7813 LLVMValueRef color[4];
7814 int mrt = u_bit_scan(&colors_written);
7815
7816 for (i = 0; i < 4; i++)
7817 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7818
7819 si_export_mrt_color(bld_base, color, mrt,
7820 fninfo.num_params - 1,
7821 mrt == last_color_export, &exp);
7822 }
7823
7824 /* Process depth, stencil, samplemask. */
7825 if (key->ps_epilog.writes_z)
7826 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7827 if (key->ps_epilog.writes_stencil)
7828 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7829 if (key->ps_epilog.writes_samplemask)
7830 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7831
7832 if (depth || stencil || samplemask)
7833 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7834 else if (last_color_export == -1)
7835 ac_build_export_null(&ctx->ac);
7836
7837 if (exp.num)
7838 si_emit_ps_exports(ctx, &exp);
7839
7840 /* Compile. */
7841 LLVMBuildRetVoid(ctx->ac.builder);
7842 }
7843
7844 /**
7845 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7846 */
7847 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7848 LLVMTargetMachineRef tm,
7849 struct si_shader *shader,
7850 struct pipe_debug_callback *debug)
7851 {
7852 union si_shader_part_key prolog_key;
7853 union si_shader_part_key epilog_key;
7854
7855 /* Get the prolog. */
7856 si_get_ps_prolog_key(shader, &prolog_key, true);
7857
7858 /* The prolog is a no-op if these aren't set. */
7859 if (si_need_ps_prolog(&prolog_key)) {
7860 shader->prolog =
7861 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7862 PIPE_SHADER_FRAGMENT, true,
7863 &prolog_key, tm, debug,
7864 si_build_ps_prolog_function,
7865 "Fragment Shader Prolog");
7866 if (!shader->prolog)
7867 return false;
7868 }
7869
7870 /* Get the epilog. */
7871 si_get_ps_epilog_key(shader, &epilog_key);
7872
7873 shader->epilog =
7874 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7875 PIPE_SHADER_FRAGMENT, false,
7876 &epilog_key, tm, debug,
7877 si_build_ps_epilog_function,
7878 "Fragment Shader Epilog");
7879 if (!shader->epilog)
7880 return false;
7881
7882 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7883 if (shader->key.part.ps.prolog.poly_stipple) {
7884 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7885 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7886 }
7887
7888 /* Set up the enable bits for per-sample shading if needed. */
7889 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7890 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7891 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7892 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7893 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7894 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7895 }
7896 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7897 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7898 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7899 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7900 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7901 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7902 }
7903 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7904 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7905 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7906 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7907 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7908 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7909 }
7910 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7911 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7912 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7913 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7914 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7915 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7916 }
7917
7918 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7919 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7920 !(shader->config.spi_ps_input_ena & 0xf)) {
7921 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7922 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7923 }
7924
7925 /* At least one pair of interpolation weights must be enabled. */
7926 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7927 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7928 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7929 }
7930
7931 /* Samplemask fixup requires the sample ID. */
7932 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7933 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7934 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7935 }
7936
7937 /* The sample mask input is always enabled, because the API shader always
7938 * passes it through to the epilog. Disable it here if it's unused.
7939 */
7940 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7941 !shader->selector->info.reads_samplemask)
7942 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7943
7944 return true;
7945 }
7946
7947 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7948 unsigned *lds_size)
7949 {
7950 /* SPI barrier management bug:
7951 * Make sure we have at least 4k of LDS in use to avoid the bug.
7952 * It applies to workgroup sizes of more than one wavefront.
7953 */
7954 if (sscreen->info.family == CHIP_BONAIRE ||
7955 sscreen->info.family == CHIP_KABINI ||
7956 sscreen->info.family == CHIP_MULLINS)
7957 *lds_size = MAX2(*lds_size, 8);
7958 }
7959
7960 static void si_fix_resource_usage(struct si_screen *sscreen,
7961 struct si_shader *shader)
7962 {
7963 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7964
7965 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7966
7967 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7968 si_get_max_workgroup_size(shader) > 64) {
7969 si_multiwave_lds_size_workaround(sscreen,
7970 &shader->config.lds_size);
7971 }
7972 }
7973
7974 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7975 struct si_shader *shader,
7976 struct pipe_debug_callback *debug)
7977 {
7978 struct si_shader_selector *sel = shader->selector;
7979 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7980 int r;
7981
7982 /* LS, ES, VS are compiled on demand if the main part hasn't been
7983 * compiled for that stage.
7984 *
7985 * Vertex shaders are compiled on demand when a vertex fetch
7986 * workaround must be applied.
7987 */
7988 if (shader->is_monolithic) {
7989 /* Monolithic shader (compiled as a whole, has many variants,
7990 * may take a long time to compile).
7991 */
7992 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7993 if (r)
7994 return r;
7995 } else {
7996 /* The shader consists of several parts:
7997 *
7998 * - the middle part is the user shader, it has 1 variant only
7999 * and it was compiled during the creation of the shader
8000 * selector
8001 * - the prolog part is inserted at the beginning
8002 * - the epilog part is inserted at the end
8003 *
8004 * The prolog and epilog have many (but simple) variants.
8005 *
8006 * Starting with gfx9, geometry and tessellation control
8007 * shaders also contain the prolog and user shader parts of
8008 * the previous shader stage.
8009 */
8010
8011 if (!mainp)
8012 return -1;
8013
8014 /* Copy the compiled TGSI shader data over. */
8015 shader->is_binary_shared = true;
8016 shader->binary = mainp->binary;
8017 shader->config = mainp->config;
8018 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8019 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8020 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8021 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
8022 memcpy(shader->info.vs_output_param_offset,
8023 mainp->info.vs_output_param_offset,
8024 sizeof(mainp->info.vs_output_param_offset));
8025 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8026 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8027 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8028
8029 /* Select prologs and/or epilogs. */
8030 switch (sel->type) {
8031 case PIPE_SHADER_VERTEX:
8032 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
8033 return -1;
8034 break;
8035 case PIPE_SHADER_TESS_CTRL:
8036 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
8037 return -1;
8038 break;
8039 case PIPE_SHADER_TESS_EVAL:
8040 break;
8041 case PIPE_SHADER_GEOMETRY:
8042 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
8043 return -1;
8044 break;
8045 case PIPE_SHADER_FRAGMENT:
8046 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8047 return -1;
8048
8049 /* Make sure we have at least as many VGPRs as there
8050 * are allocated inputs.
8051 */
8052 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8053 shader->info.num_input_vgprs);
8054 break;
8055 }
8056
8057 /* Update SGPR and VGPR counts. */
8058 if (shader->prolog) {
8059 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8060 shader->prolog->config.num_sgprs);
8061 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8062 shader->prolog->config.num_vgprs);
8063 }
8064 if (shader->previous_stage) {
8065 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8066 shader->previous_stage->config.num_sgprs);
8067 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8068 shader->previous_stage->config.num_vgprs);
8069 shader->config.spilled_sgprs =
8070 MAX2(shader->config.spilled_sgprs,
8071 shader->previous_stage->config.spilled_sgprs);
8072 shader->config.spilled_vgprs =
8073 MAX2(shader->config.spilled_vgprs,
8074 shader->previous_stage->config.spilled_vgprs);
8075 shader->config.private_mem_vgprs =
8076 MAX2(shader->config.private_mem_vgprs,
8077 shader->previous_stage->config.private_mem_vgprs);
8078 shader->config.scratch_bytes_per_wave =
8079 MAX2(shader->config.scratch_bytes_per_wave,
8080 shader->previous_stage->config.scratch_bytes_per_wave);
8081 shader->info.uses_instanceid |=
8082 shader->previous_stage->info.uses_instanceid;
8083 }
8084 if (shader->prolog2) {
8085 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8086 shader->prolog2->config.num_sgprs);
8087 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8088 shader->prolog2->config.num_vgprs);
8089 }
8090 if (shader->epilog) {
8091 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8092 shader->epilog->config.num_sgprs);
8093 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8094 shader->epilog->config.num_vgprs);
8095 }
8096 si_calculate_max_simd_waves(shader);
8097 }
8098
8099 si_fix_resource_usage(sscreen, shader);
8100 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8101 stderr, true);
8102
8103 /* Upload. */
8104 r = si_shader_binary_upload(sscreen, shader);
8105 if (r) {
8106 fprintf(stderr, "LLVM failed to upload shader\n");
8107 return r;
8108 }
8109
8110 return 0;
8111 }
8112
8113 void si_shader_destroy(struct si_shader *shader)
8114 {
8115 if (shader->scratch_bo)
8116 r600_resource_reference(&shader->scratch_bo, NULL);
8117
8118 r600_resource_reference(&shader->bo, NULL);
8119
8120 if (!shader->is_binary_shared)
8121 ac_shader_binary_clean(&shader->binary);
8122
8123 free(shader->shader_log);
8124 }