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radeonsi: add si_nir_load_input_tes()
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "gallivm/lp_bld_const.h"
25 #include "gallivm/lp_bld_gather.h"
26 #include "gallivm/lp_bld_intr.h"
27 #include "gallivm/lp_bld_logic.h"
28 #include "gallivm/lp_bld_arit.h"
29 #include "gallivm/lp_bld_flow.h"
30 #include "gallivm/lp_bld_misc.h"
31 #include "util/u_memory.h"
32 #include "util/u_string.h"
33 #include "tgsi/tgsi_build.h"
34 #include "tgsi/tgsi_util.h"
35 #include "tgsi/tgsi_dump.h"
36
37 #include "ac_binary.h"
38 #include "ac_llvm_util.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41 #include "si_shader_internal.h"
42 #include "si_pipe.h"
43 #include "sid.h"
44
45 #include "compiler/nir/nir.h"
46
47 static const char *scratch_rsrc_dword0_symbol =
48 "SCRATCH_RSRC_DWORD0";
49
50 static const char *scratch_rsrc_dword1_symbol =
51 "SCRATCH_RSRC_DWORD1";
52
53 struct si_shader_output_values
54 {
55 LLVMValueRef values[4];
56 unsigned semantic_name;
57 unsigned semantic_index;
58 ubyte vertex_stream[4];
59 };
60
61 /**
62 * Used to collect types and other info about arguments of the LLVM function
63 * before the function is created.
64 */
65 struct si_function_info {
66 LLVMTypeRef types[100];
67 LLVMValueRef *assign[100];
68 unsigned num_sgpr_params;
69 unsigned num_params;
70 };
71
72 enum si_arg_regfile {
73 ARG_SGPR,
74 ARG_VGPR
75 };
76
77 static void si_init_shader_ctx(struct si_shader_context *ctx,
78 struct si_screen *sscreen,
79 LLVMTargetMachineRef tm);
80
81 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
82 struct lp_build_tgsi_context *bld_base,
83 struct lp_build_emit_data *emit_data);
84
85 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
86 FILE *f);
87
88 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
89 union si_shader_part_key *key);
90 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
91 union si_shader_part_key *key);
92 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
93 union si_shader_part_key *key);
94 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
95 union si_shader_part_key *key);
96
97 /* Ideally pass the sample mask input to the PS epilog as v14, which
98 * is its usual location, so that the shader doesn't have to add v_mov.
99 */
100 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
101
102 enum {
103 CONST_ADDR_SPACE = 2,
104 LOCAL_ADDR_SPACE = 3,
105 };
106
107 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
108 LLVMTypeRef type)
109 {
110 if (type == ctx->ac.i64 || type == ctx->ac.f64)
111 return true;
112
113 return false;
114 }
115
116 static bool is_merged_shader(struct si_shader *shader)
117 {
118 if (shader->selector->screen->info.chip_class <= VI)
119 return false;
120
121 return shader->key.as_ls ||
122 shader->key.as_es ||
123 shader->selector->type == PIPE_SHADER_TESS_CTRL ||
124 shader->selector->type == PIPE_SHADER_GEOMETRY;
125 }
126
127 static void si_init_function_info(struct si_function_info *fninfo)
128 {
129 fninfo->num_params = 0;
130 fninfo->num_sgpr_params = 0;
131 }
132
133 static unsigned add_arg_assign(struct si_function_info *fninfo,
134 enum si_arg_regfile regfile, LLVMTypeRef type,
135 LLVMValueRef *assign)
136 {
137 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
138
139 unsigned idx = fninfo->num_params++;
140 assert(idx < ARRAY_SIZE(fninfo->types));
141
142 if (regfile == ARG_SGPR)
143 fninfo->num_sgpr_params = fninfo->num_params;
144
145 fninfo->types[idx] = type;
146 fninfo->assign[idx] = assign;
147 return idx;
148 }
149
150 static unsigned add_arg(struct si_function_info *fninfo,
151 enum si_arg_regfile regfile, LLVMTypeRef type)
152 {
153 return add_arg_assign(fninfo, regfile, type, NULL);
154 }
155
156 static void add_arg_assign_checked(struct si_function_info *fninfo,
157 enum si_arg_regfile regfile, LLVMTypeRef type,
158 LLVMValueRef *assign, unsigned idx)
159 {
160 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
161 assert(actual == idx);
162 }
163
164 static void add_arg_checked(struct si_function_info *fninfo,
165 enum si_arg_regfile regfile, LLVMTypeRef type,
166 unsigned idx)
167 {
168 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
169 }
170
171 /**
172 * Returns a unique index for a per-patch semantic name and index. The index
173 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
174 * can be calculated.
175 */
176 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
177 {
178 switch (semantic_name) {
179 case TGSI_SEMANTIC_TESSOUTER:
180 return 0;
181 case TGSI_SEMANTIC_TESSINNER:
182 return 1;
183 case TGSI_SEMANTIC_PATCH:
184 assert(index < 30);
185 return 2 + index;
186
187 default:
188 assert(!"invalid semantic name");
189 return 0;
190 }
191 }
192
193 /**
194 * Returns a unique index for a semantic name and index. The index must be
195 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
196 * calculated.
197 */
198 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
199 {
200 switch (semantic_name) {
201 case TGSI_SEMANTIC_POSITION:
202 return 0;
203 case TGSI_SEMANTIC_GENERIC:
204 /* Since some shader stages use the the highest used IO index
205 * to determine the size to allocate for inputs/outputs
206 * (in LDS, tess and GS rings). GENERIC should be placed right
207 * after POSITION to make that size as small as possible.
208 */
209 if (index < SI_MAX_IO_GENERIC)
210 return 1 + index;
211
212 assert(!"invalid generic index");
213 return 0;
214 case TGSI_SEMANTIC_PSIZE:
215 return SI_MAX_IO_GENERIC + 1;
216 case TGSI_SEMANTIC_CLIPDIST:
217 assert(index <= 1);
218 return SI_MAX_IO_GENERIC + 2 + index;
219 case TGSI_SEMANTIC_FOG:
220 return SI_MAX_IO_GENERIC + 4;
221 case TGSI_SEMANTIC_LAYER:
222 return SI_MAX_IO_GENERIC + 5;
223 case TGSI_SEMANTIC_VIEWPORT_INDEX:
224 return SI_MAX_IO_GENERIC + 6;
225 case TGSI_SEMANTIC_PRIMID:
226 return SI_MAX_IO_GENERIC + 7;
227 case TGSI_SEMANTIC_COLOR: /* these alias */
228 case TGSI_SEMANTIC_BCOLOR:
229 assert(index < 2);
230 return SI_MAX_IO_GENERIC + 8 + index;
231 case TGSI_SEMANTIC_TEXCOORD:
232 assert(index < 8);
233 assert(SI_MAX_IO_GENERIC + 10 + index < 64);
234 return SI_MAX_IO_GENERIC + 10 + index;
235 default:
236 assert(!"invalid semantic name");
237 return 0;
238 }
239 }
240
241 /**
242 * Get the value of a shader input parameter and extract a bitfield.
243 */
244 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
245 unsigned param, unsigned rshift,
246 unsigned bitwidth)
247 {
248 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
249 param);
250
251 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
252 value = ac_to_integer(&ctx->ac, value);
253
254 if (rshift)
255 value = LLVMBuildLShr(ctx->ac.builder, value,
256 LLVMConstInt(ctx->i32, rshift, 0), "");
257
258 if (rshift + bitwidth < 32) {
259 unsigned mask = (1 << bitwidth) - 1;
260 value = LLVMBuildAnd(ctx->ac.builder, value,
261 LLVMConstInt(ctx->i32, mask, 0), "");
262 }
263
264 return value;
265 }
266
267 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
268 {
269 switch (ctx->type) {
270 case PIPE_SHADER_TESS_CTRL:
271 return unpack_param(ctx, ctx->param_tcs_rel_ids, 0, 8);
272
273 case PIPE_SHADER_TESS_EVAL:
274 return LLVMGetParam(ctx->main_fn,
275 ctx->param_tes_rel_patch_id);
276
277 default:
278 assert(0);
279 return NULL;
280 }
281 }
282
283 /* Tessellation shaders pass outputs to the next shader using LDS.
284 *
285 * LS outputs = TCS inputs
286 * TCS outputs = TES inputs
287 *
288 * The LDS layout is:
289 * - TCS inputs for patch 0
290 * - TCS inputs for patch 1
291 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
292 * - ...
293 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
294 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
295 * - TCS outputs for patch 1
296 * - Per-patch TCS outputs for patch 1
297 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
298 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
299 * - ...
300 *
301 * All three shaders VS(LS), TCS, TES share the same LDS space.
302 */
303
304 static LLVMValueRef
305 get_tcs_in_patch_stride(struct si_shader_context *ctx)
306 {
307 return unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
308 }
309
310 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
311 {
312 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
313
314 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
315 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
316
317 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
318 }
319
320 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
321 {
322 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
323
324 return LLVMConstInt(ctx->i32, stride, 0);
325 }
326
327 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
328 {
329 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
330 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
331
332 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
333 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
334 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
335 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
336 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
337 num_patch_outputs * 4;
338 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
339 }
340
341 static LLVMValueRef
342 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
343 {
344 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
345 unpack_param(ctx,
346 ctx->param_tcs_out_lds_offsets,
347 0, 16),
348 4);
349 }
350
351 static LLVMValueRef
352 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
353 {
354 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
355 unpack_param(ctx,
356 ctx->param_tcs_out_lds_offsets,
357 16, 16),
358 4);
359 }
360
361 static LLVMValueRef
362 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
363 {
364 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
365 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
366
367 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
368 }
369
370 static LLVMValueRef
371 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
372 {
373 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
374 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
375 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
376
377 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
378 LLVMBuildMul(ctx->ac.builder, patch_stride,
379 rel_patch_id, ""),
380 "");
381 }
382
383 static LLVMValueRef
384 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
385 {
386 LLVMValueRef patch0_patch_data_offset =
387 get_tcs_out_patch0_patch_data_offset(ctx);
388 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
389 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
390
391 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
392 LLVMBuildMul(ctx->ac.builder, patch_stride,
393 rel_patch_id, ""),
394 "");
395 }
396
397 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
398 {
399 unsigned tcs_out_vertices =
400 ctx->shader->selector ?
401 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
402
403 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
404 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
405 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
406
407 return unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
408 }
409
410 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
411 {
412 unsigned stride;
413
414 switch (ctx->type) {
415 case PIPE_SHADER_VERTEX:
416 stride = util_last_bit64(ctx->shader->selector->outputs_written);
417 return LLVMConstInt(ctx->i32, stride * 4, 0);
418
419 case PIPE_SHADER_TESS_CTRL:
420 if (ctx->screen->info.chip_class >= GFX9 &&
421 ctx->shader->is_monolithic) {
422 stride = util_last_bit64(ctx->shader->key.part.tcs.ls->outputs_written);
423 return LLVMConstInt(ctx->i32, stride * 4, 0);
424 }
425 return unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
426
427 default:
428 assert(0);
429 return NULL;
430 }
431 }
432
433 static LLVMValueRef get_instance_index_for_fetch(
434 struct si_shader_context *ctx,
435 unsigned param_start_instance, LLVMValueRef divisor)
436 {
437 LLVMValueRef result = ctx->abi.instance_id;
438
439 /* The division must be done before START_INSTANCE is added. */
440 if (divisor != ctx->i32_1)
441 result = LLVMBuildUDiv(ctx->ac.builder, result, divisor, "");
442
443 return LLVMBuildAdd(ctx->ac.builder, result,
444 LLVMGetParam(ctx->main_fn, param_start_instance), "");
445 }
446
447 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
448 * to float. */
449 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
450 LLVMValueRef vec4,
451 unsigned double_index)
452 {
453 LLVMBuilderRef builder = ctx->ac.builder;
454 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->ac.context);
455 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
456 LLVMVectorType(f64, 2), "");
457 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
458 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
459 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
460 }
461
462 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
463 LLVMValueRef i32, unsigned index)
464 {
465 assert(index <= 1);
466
467 if (index == 1)
468 return LLVMBuildAShr(ctx->ac.builder, i32,
469 LLVMConstInt(ctx->i32, 16, 0), "");
470
471 return LLVMBuildSExt(ctx->ac.builder,
472 LLVMBuildTrunc(ctx->ac.builder, i32,
473 ctx->ac.i16, ""),
474 ctx->i32, "");
475 }
476
477 void si_llvm_load_input_vs(
478 struct si_shader_context *ctx,
479 unsigned input_index,
480 LLVMValueRef out[4])
481 {
482 unsigned vs_blit_property =
483 ctx->shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
484
485 if (vs_blit_property) {
486 LLVMValueRef vertex_id = ctx->abi.vertex_id;
487 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
488 LLVMIntULE, vertex_id,
489 ctx->i32_1, "");
490 /* Use LLVMIntNE, because we have 3 vertices and only
491 * the middle one should use y2.
492 */
493 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
494 LLVMIntNE, vertex_id,
495 ctx->i32_1, "");
496
497 if (input_index == 0) {
498 /* Position: */
499 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
500 ctx->param_vs_blit_inputs);
501 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
502 ctx->param_vs_blit_inputs + 1);
503
504 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
505 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
506 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
507 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
508
509 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
510 x1, x2, "");
511 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
512 y1, y2, "");
513
514 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
515 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
516 out[2] = LLVMGetParam(ctx->main_fn,
517 ctx->param_vs_blit_inputs + 2);
518 out[3] = ctx->ac.f32_1;
519 return;
520 }
521
522 /* Color or texture coordinates: */
523 assert(input_index == 1);
524
525 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
526 for (int i = 0; i < 4; i++) {
527 out[i] = LLVMGetParam(ctx->main_fn,
528 ctx->param_vs_blit_inputs + 3 + i);
529 }
530 } else {
531 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
532 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
533 ctx->param_vs_blit_inputs + 3);
534 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
535 ctx->param_vs_blit_inputs + 4);
536 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
537 ctx->param_vs_blit_inputs + 5);
538 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
539 ctx->param_vs_blit_inputs + 6);
540
541 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
542 x1, x2, "");
543 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
544 y1, y2, "");
545 out[2] = LLVMGetParam(ctx->main_fn,
546 ctx->param_vs_blit_inputs + 7);
547 out[3] = LLVMGetParam(ctx->main_fn,
548 ctx->param_vs_blit_inputs + 8);
549 }
550 return;
551 }
552
553 unsigned chan;
554 unsigned fix_fetch;
555 unsigned num_fetches;
556 unsigned fetch_stride;
557
558 LLVMValueRef t_list_ptr;
559 LLVMValueRef t_offset;
560 LLVMValueRef t_list;
561 LLVMValueRef vertex_index;
562 LLVMValueRef input[3];
563
564 /* Load the T list */
565 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
566
567 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
568
569 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
570
571 vertex_index = LLVMGetParam(ctx->main_fn,
572 ctx->param_vertex_index0 +
573 input_index);
574
575 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
576
577 /* Do multiple loads for special formats. */
578 switch (fix_fetch) {
579 case SI_FIX_FETCH_RGB_64_FLOAT:
580 num_fetches = 3; /* 3 2-dword loads */
581 fetch_stride = 8;
582 break;
583 case SI_FIX_FETCH_RGBA_64_FLOAT:
584 num_fetches = 2; /* 2 4-dword loads */
585 fetch_stride = 16;
586 break;
587 case SI_FIX_FETCH_RGB_8:
588 case SI_FIX_FETCH_RGB_8_INT:
589 num_fetches = 3;
590 fetch_stride = 1;
591 break;
592 case SI_FIX_FETCH_RGB_16:
593 case SI_FIX_FETCH_RGB_16_INT:
594 num_fetches = 3;
595 fetch_stride = 2;
596 break;
597 default:
598 num_fetches = 1;
599 fetch_stride = 0;
600 }
601
602 for (unsigned i = 0; i < num_fetches; i++) {
603 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
604
605 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
606 vertex_index, voffset,
607 true);
608 }
609
610 /* Break up the vec4 into individual components */
611 for (chan = 0; chan < 4; chan++) {
612 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
613 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
614 input[0], llvm_chan, "");
615 }
616
617 switch (fix_fetch) {
618 case SI_FIX_FETCH_A2_SNORM:
619 case SI_FIX_FETCH_A2_SSCALED:
620 case SI_FIX_FETCH_A2_SINT: {
621 /* The hardware returns an unsigned value; convert it to a
622 * signed one.
623 */
624 LLVMValueRef tmp = out[3];
625 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
626
627 /* First, recover the sign-extended signed integer value. */
628 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
629 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
630 else
631 tmp = ac_to_integer(&ctx->ac, tmp);
632
633 /* For the integer-like cases, do a natural sign extension.
634 *
635 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
636 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
637 * exponent.
638 */
639 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
640 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
641 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
642 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
643
644 /* Convert back to the right type. */
645 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
646 LLVMValueRef clamp;
647 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
648 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
649 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
650 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
651 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
652 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
653 }
654
655 out[3] = tmp;
656 break;
657 }
658 case SI_FIX_FETCH_RGBA_32_UNORM:
659 case SI_FIX_FETCH_RGBX_32_UNORM:
660 for (chan = 0; chan < 4; chan++) {
661 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
662 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
663 out[chan], ctx->f32, "");
664 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
665 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
666 }
667 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
668 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
669 out[3] = LLVMConstReal(ctx->f32, 1);
670 break;
671 case SI_FIX_FETCH_RGBA_32_SNORM:
672 case SI_FIX_FETCH_RGBX_32_SNORM:
673 case SI_FIX_FETCH_RGBA_32_FIXED:
674 case SI_FIX_FETCH_RGBX_32_FIXED: {
675 double scale;
676 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
677 scale = 1.0 / 0x10000;
678 else
679 scale = 1.0 / INT_MAX;
680
681 for (chan = 0; chan < 4; chan++) {
682 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
683 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
684 out[chan], ctx->f32, "");
685 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
686 LLVMConstReal(ctx->f32, scale), "");
687 }
688 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
689 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
690 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
691 out[3] = LLVMConstReal(ctx->f32, 1);
692 break;
693 }
694 case SI_FIX_FETCH_RGBA_32_USCALED:
695 for (chan = 0; chan < 4; chan++) {
696 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
697 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
698 out[chan], ctx->f32, "");
699 }
700 break;
701 case SI_FIX_FETCH_RGBA_32_SSCALED:
702 for (chan = 0; chan < 4; chan++) {
703 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
704 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
705 out[chan], ctx->f32, "");
706 }
707 break;
708 case SI_FIX_FETCH_RG_64_FLOAT:
709 for (chan = 0; chan < 2; chan++)
710 out[chan] = extract_double_to_float(ctx, input[0], chan);
711
712 out[2] = LLVMConstReal(ctx->f32, 0);
713 out[3] = LLVMConstReal(ctx->f32, 1);
714 break;
715 case SI_FIX_FETCH_RGB_64_FLOAT:
716 for (chan = 0; chan < 3; chan++)
717 out[chan] = extract_double_to_float(ctx, input[chan], 0);
718
719 out[3] = LLVMConstReal(ctx->f32, 1);
720 break;
721 case SI_FIX_FETCH_RGBA_64_FLOAT:
722 for (chan = 0; chan < 4; chan++) {
723 out[chan] = extract_double_to_float(ctx, input[chan / 2],
724 chan % 2);
725 }
726 break;
727 case SI_FIX_FETCH_RGB_8:
728 case SI_FIX_FETCH_RGB_8_INT:
729 case SI_FIX_FETCH_RGB_16:
730 case SI_FIX_FETCH_RGB_16_INT:
731 for (chan = 0; chan < 3; chan++) {
732 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
733 input[chan],
734 ctx->i32_0, "");
735 }
736 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
737 fix_fetch == SI_FIX_FETCH_RGB_16) {
738 out[3] = LLVMConstReal(ctx->f32, 1);
739 } else {
740 out[3] = ac_to_float(&ctx->ac, ctx->i32_1);
741 }
742 break;
743 }
744 }
745
746 static void declare_input_vs(
747 struct si_shader_context *ctx,
748 unsigned input_index,
749 const struct tgsi_full_declaration *decl,
750 LLVMValueRef out[4])
751 {
752 si_llvm_load_input_vs(ctx, input_index, out);
753 }
754
755 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
756 unsigned swizzle)
757 {
758 if (swizzle > 0)
759 return ctx->i32_0;
760
761 switch (ctx->type) {
762 case PIPE_SHADER_VERTEX:
763 return LLVMGetParam(ctx->main_fn,
764 ctx->param_vs_prim_id);
765 case PIPE_SHADER_TESS_CTRL:
766 return LLVMGetParam(ctx->main_fn,
767 ctx->param_tcs_patch_id);
768 case PIPE_SHADER_TESS_EVAL:
769 return LLVMGetParam(ctx->main_fn,
770 ctx->param_tes_patch_id);
771 case PIPE_SHADER_GEOMETRY:
772 return ctx->abi.gs_prim_id;
773 default:
774 assert(0);
775 return ctx->i32_0;
776 }
777 }
778
779 /**
780 * Return the value of tgsi_ind_register for indexing.
781 * This is the indirect index with the constant offset added to it.
782 */
783 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
784 const struct tgsi_ind_register *ind,
785 unsigned addr_mul,
786 int rel_index)
787 {
788 LLVMValueRef result;
789
790 if (ind->File == TGSI_FILE_ADDRESS) {
791 result = ctx->addrs[ind->Index][ind->Swizzle];
792 result = LLVMBuildLoad(ctx->ac.builder, result, "");
793 } else {
794 struct tgsi_full_src_register src = {};
795
796 src.Register.File = ind->File;
797 src.Register.Index = ind->Index;
798
799 /* Set the second index to 0 for constants. */
800 if (ind->File == TGSI_FILE_CONSTANT)
801 src.Register.Dimension = 1;
802
803 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
804 TGSI_TYPE_SIGNED,
805 ind->Swizzle);
806 result = ac_to_integer(&ctx->ac, result);
807 }
808
809 if (addr_mul != 1)
810 result = LLVMBuildMul(ctx->ac.builder, result,
811 LLVMConstInt(ctx->i32, addr_mul, 0), "");
812 result = LLVMBuildAdd(ctx->ac.builder, result,
813 LLVMConstInt(ctx->i32, rel_index, 0), "");
814 return result;
815 }
816
817 /**
818 * Like si_get_indirect_index, but restricts the return value to a (possibly
819 * undefined) value inside [0..num).
820 */
821 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
822 const struct tgsi_ind_register *ind,
823 int rel_index, unsigned num)
824 {
825 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
826
827 return si_llvm_bound_index(ctx, result, num);
828 }
829
830
831 /**
832 * Calculate a dword address given an input or output register and a stride.
833 */
834 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
835 const struct tgsi_full_dst_register *dst,
836 const struct tgsi_full_src_register *src,
837 LLVMValueRef vertex_dw_stride,
838 LLVMValueRef base_addr)
839 {
840 struct tgsi_shader_info *info = &ctx->shader->selector->info;
841 ubyte *name, *index, *array_first;
842 int first, param;
843 struct tgsi_full_dst_register reg;
844
845 /* Set the register description. The address computation is the same
846 * for sources and destinations. */
847 if (src) {
848 reg.Register.File = src->Register.File;
849 reg.Register.Index = src->Register.Index;
850 reg.Register.Indirect = src->Register.Indirect;
851 reg.Register.Dimension = src->Register.Dimension;
852 reg.Indirect = src->Indirect;
853 reg.Dimension = src->Dimension;
854 reg.DimIndirect = src->DimIndirect;
855 } else
856 reg = *dst;
857
858 /* If the register is 2-dimensional (e.g. an array of vertices
859 * in a primitive), calculate the base address of the vertex. */
860 if (reg.Register.Dimension) {
861 LLVMValueRef index;
862
863 if (reg.Dimension.Indirect)
864 index = si_get_indirect_index(ctx, &reg.DimIndirect,
865 1, reg.Dimension.Index);
866 else
867 index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
868
869 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
870 LLVMBuildMul(ctx->ac.builder, index,
871 vertex_dw_stride, ""), "");
872 }
873
874 /* Get information about the register. */
875 if (reg.Register.File == TGSI_FILE_INPUT) {
876 name = info->input_semantic_name;
877 index = info->input_semantic_index;
878 array_first = info->input_array_first;
879 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
880 name = info->output_semantic_name;
881 index = info->output_semantic_index;
882 array_first = info->output_array_first;
883 } else {
884 assert(0);
885 return NULL;
886 }
887
888 if (reg.Register.Indirect) {
889 /* Add the relative address of the element. */
890 LLVMValueRef ind_index;
891
892 if (reg.Indirect.ArrayID)
893 first = array_first[reg.Indirect.ArrayID];
894 else
895 first = reg.Register.Index;
896
897 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
898 1, reg.Register.Index - first);
899
900 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
901 LLVMBuildMul(ctx->ac.builder, ind_index,
902 LLVMConstInt(ctx->i32, 4, 0), ""), "");
903
904 param = reg.Register.Dimension ?
905 si_shader_io_get_unique_index(name[first], index[first]) :
906 si_shader_io_get_unique_index_patch(name[first], index[first]);
907 } else {
908 param = reg.Register.Dimension ?
909 si_shader_io_get_unique_index(name[reg.Register.Index],
910 index[reg.Register.Index]) :
911 si_shader_io_get_unique_index_patch(name[reg.Register.Index],
912 index[reg.Register.Index]);
913 }
914
915 /* Add the base address of the element. */
916 return LLVMBuildAdd(ctx->ac.builder, base_addr,
917 LLVMConstInt(ctx->i32, param * 4, 0), "");
918 }
919
920 /* The offchip buffer layout for TCS->TES is
921 *
922 * - attribute 0 of patch 0 vertex 0
923 * - attribute 0 of patch 0 vertex 1
924 * - attribute 0 of patch 0 vertex 2
925 * ...
926 * - attribute 0 of patch 1 vertex 0
927 * - attribute 0 of patch 1 vertex 1
928 * ...
929 * - attribute 1 of patch 0 vertex 0
930 * - attribute 1 of patch 0 vertex 1
931 * ...
932 * - per patch attribute 0 of patch 0
933 * - per patch attribute 0 of patch 1
934 * ...
935 *
936 * Note that every attribute has 4 components.
937 */
938 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
939 LLVMValueRef rel_patch_id,
940 LLVMValueRef vertex_index,
941 LLVMValueRef param_index)
942 {
943 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
944 LLVMValueRef param_stride, constant16;
945
946 vertices_per_patch = get_num_tcs_out_vertices(ctx);
947 num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
948 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
949 num_patches, "");
950
951 constant16 = LLVMConstInt(ctx->i32, 16, 0);
952 if (vertex_index) {
953 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
954 vertices_per_patch, "");
955
956 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
957 vertex_index, "");
958
959 param_stride = total_vertices;
960 } else {
961 base_addr = rel_patch_id;
962 param_stride = num_patches;
963 }
964
965 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
966 LLVMBuildMul(ctx->ac.builder, param_index,
967 param_stride, ""), "");
968
969 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
970
971 if (!vertex_index) {
972 LLVMValueRef patch_data_offset =
973 unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
974
975 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
976 patch_data_offset, "");
977 }
978 return base_addr;
979 }
980
981 /* This is a generic helper that can be shared by the NIR and TGSI backends */
982 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
983 struct si_shader_context *ctx,
984 LLVMValueRef vertex_index,
985 LLVMValueRef param_index,
986 unsigned param_base,
987 ubyte *name,
988 ubyte *index,
989 bool is_patch)
990 {
991 unsigned param_index_base;
992
993 param_index_base = is_patch ?
994 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
995 si_shader_io_get_unique_index(name[param_base], index[param_base]);
996
997 if (param_index) {
998 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
999 LLVMConstInt(ctx->i32, param_index_base, 0),
1000 "");
1001 } else {
1002 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
1003 }
1004
1005 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
1006 vertex_index, param_index);
1007 }
1008
1009 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
1010 struct si_shader_context *ctx,
1011 const struct tgsi_full_dst_register *dst,
1012 const struct tgsi_full_src_register *src)
1013 {
1014 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1015 ubyte *name, *index, *array_first;
1016 struct tgsi_full_src_register reg;
1017 LLVMValueRef vertex_index = NULL;
1018 LLVMValueRef param_index = NULL;
1019 unsigned param_base;
1020
1021 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
1022
1023 if (reg.Register.Dimension) {
1024
1025 if (reg.Dimension.Indirect)
1026 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
1027 1, reg.Dimension.Index);
1028 else
1029 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
1030 }
1031
1032 /* Get information about the register. */
1033 if (reg.Register.File == TGSI_FILE_INPUT) {
1034 name = info->input_semantic_name;
1035 index = info->input_semantic_index;
1036 array_first = info->input_array_first;
1037 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1038 name = info->output_semantic_name;
1039 index = info->output_semantic_index;
1040 array_first = info->output_array_first;
1041 } else {
1042 assert(0);
1043 return NULL;
1044 }
1045
1046 if (reg.Register.Indirect) {
1047 if (reg.Indirect.ArrayID)
1048 param_base = array_first[reg.Indirect.ArrayID];
1049 else
1050 param_base = reg.Register.Index;
1051
1052 param_index = si_get_indirect_index(ctx, &reg.Indirect,
1053 1, reg.Register.Index - param_base);
1054
1055 } else {
1056 param_base = reg.Register.Index;
1057 }
1058
1059 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1060 param_index, param_base,
1061 name, index, !reg.Register.Dimension);
1062 }
1063
1064 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
1065 LLVMTypeRef type, unsigned swizzle,
1066 LLVMValueRef buffer, LLVMValueRef offset,
1067 LLVMValueRef base, bool can_speculate)
1068 {
1069 struct si_shader_context *ctx = si_shader_context(bld_base);
1070 LLVMValueRef value, value2;
1071 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
1072
1073 if (swizzle == ~0) {
1074 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1075 0, 1, 0, can_speculate, false);
1076
1077 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1078 }
1079
1080 if (!llvm_type_is_64bit(ctx, type)) {
1081 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1082 0, 1, 0, can_speculate, false);
1083
1084 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1085 return LLVMBuildExtractElement(ctx->ac.builder, value,
1086 LLVMConstInt(ctx->i32, swizzle, 0), "");
1087 }
1088
1089 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1090 swizzle * 4, 1, 0, can_speculate, false);
1091
1092 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1093 swizzle * 4 + 4, 1, 0, can_speculate, false);
1094
1095 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1096 }
1097
1098 /**
1099 * Load from LDS.
1100 *
1101 * \param type output value type
1102 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1103 * \param dw_addr address in dwords
1104 */
1105 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1106 LLVMTypeRef type, unsigned swizzle,
1107 LLVMValueRef dw_addr)
1108 {
1109 struct si_shader_context *ctx = si_shader_context(bld_base);
1110 LLVMValueRef value;
1111
1112 if (swizzle == ~0) {
1113 LLVMValueRef values[TGSI_NUM_CHANNELS];
1114
1115 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1116 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1117
1118 return lp_build_gather_values(&ctx->gallivm, values,
1119 TGSI_NUM_CHANNELS);
1120 }
1121
1122 /* Split 64-bit loads. */
1123 if (llvm_type_is_64bit(ctx, type)) {
1124 LLVMValueRef lo, hi;
1125
1126 lo = lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1127 hi = lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1128 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1129 }
1130
1131 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1132 LLVMConstInt(ctx->i32, swizzle, 0));
1133
1134 value = ac_lds_load(&ctx->ac, dw_addr);
1135
1136 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1137 }
1138
1139 /**
1140 * Store to LDS.
1141 *
1142 * \param swizzle offset (typically 0..3)
1143 * \param dw_addr address in dwords
1144 * \param value value to store
1145 */
1146 static void lds_store(struct si_shader_context *ctx,
1147 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1148 LLVMValueRef value)
1149 {
1150 dw_addr = lp_build_add(&ctx->bld_base.uint_bld, dw_addr,
1151 LLVMConstInt(ctx->i32, dw_offset_imm, 0));
1152
1153 ac_lds_store(&ctx->ac, dw_addr, value);
1154 }
1155
1156 static LLVMValueRef desc_from_addr_base64k(struct si_shader_context *ctx,
1157 unsigned param)
1158 {
1159 LLVMBuilderRef builder = ctx->ac.builder;
1160
1161 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1162 addr = LLVMBuildZExt(builder, addr, ctx->i64, "");
1163 addr = LLVMBuildShl(builder, addr, LLVMConstInt(ctx->i64, 16, 0), "");
1164
1165 uint64_t desc2 = 0xffffffff;
1166 uint64_t desc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1167 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1168 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1169 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1170 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1171 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1172 LLVMValueRef hi = LLVMConstInt(ctx->i64, desc2 | (desc3 << 32), 0);
1173
1174 LLVMValueRef desc = LLVMGetUndef(LLVMVectorType(ctx->i64, 2));
1175 desc = LLVMBuildInsertElement(builder, desc, addr, ctx->i32_0, "");
1176 desc = LLVMBuildInsertElement(builder, desc, hi, ctx->i32_1, "");
1177 return LLVMBuildBitCast(builder, desc, ctx->v4i32, "");
1178 }
1179
1180 static LLVMValueRef fetch_input_tcs(
1181 struct lp_build_tgsi_context *bld_base,
1182 const struct tgsi_full_src_register *reg,
1183 enum tgsi_opcode_type type, unsigned swizzle)
1184 {
1185 struct si_shader_context *ctx = si_shader_context(bld_base);
1186 LLVMValueRef dw_addr, stride;
1187
1188 stride = get_tcs_in_vertex_dw_stride(ctx);
1189 dw_addr = get_tcs_in_current_patch_offset(ctx);
1190 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1191
1192 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1193 }
1194
1195 static LLVMValueRef fetch_output_tcs(
1196 struct lp_build_tgsi_context *bld_base,
1197 const struct tgsi_full_src_register *reg,
1198 enum tgsi_opcode_type type, unsigned swizzle)
1199 {
1200 struct si_shader_context *ctx = si_shader_context(bld_base);
1201 LLVMValueRef dw_addr, stride;
1202
1203 if (reg->Register.Dimension) {
1204 stride = get_tcs_out_vertex_dw_stride(ctx);
1205 dw_addr = get_tcs_out_current_patch_offset(ctx);
1206 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1207 } else {
1208 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1209 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1210 }
1211
1212 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1213 }
1214
1215 static LLVMValueRef fetch_input_tes(
1216 struct lp_build_tgsi_context *bld_base,
1217 const struct tgsi_full_src_register *reg,
1218 enum tgsi_opcode_type type, unsigned swizzle)
1219 {
1220 struct si_shader_context *ctx = si_shader_context(bld_base);
1221 LLVMValueRef buffer, base, addr;
1222
1223 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1224
1225 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1226 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1227
1228 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1229 buffer, base, addr, true);
1230 }
1231
1232 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1233 LLVMValueRef vertex_index,
1234 LLVMValueRef param_index,
1235 unsigned const_index,
1236 unsigned location,
1237 unsigned driver_location,
1238 unsigned component,
1239 unsigned num_components,
1240 bool is_patch,
1241 bool is_compact)
1242 {
1243 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1244 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1245 LLVMValueRef buffer, base, addr;
1246
1247 driver_location = driver_location / 4;
1248
1249 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1250
1251 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1252
1253 if (param_index) {
1254 /* Add the constant index to the indirect index */
1255 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1256 LLVMConstInt(ctx->i32, const_index, 0), "");
1257 } else {
1258 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1259 }
1260
1261 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1262 param_index, driver_location,
1263 info->input_semantic_name,
1264 info->input_semantic_index,
1265 is_patch);
1266
1267 /* TODO: This will generate rather ordinary llvm code, although it
1268 * should be easy for the optimiser to fix up. In future we might want
1269 * to refactor buffer_load(), but for now this maximises code sharing
1270 * between the NIR and TGSI backends.
1271 */
1272 LLVMValueRef value[4];
1273 for (unsigned i = component; i < num_components + component; i++) {
1274 value[i] = buffer_load(&ctx->bld_base, ctx->i32, i, buffer, base, addr, true);
1275 }
1276
1277 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1278 }
1279
1280 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1281 const struct tgsi_full_instruction *inst,
1282 const struct tgsi_opcode_info *info,
1283 unsigned index,
1284 LLVMValueRef dst[4])
1285 {
1286 struct si_shader_context *ctx = si_shader_context(bld_base);
1287 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1288 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1289 unsigned chan_index;
1290 LLVMValueRef dw_addr, stride;
1291 LLVMValueRef buffer, base, buf_addr;
1292 LLVMValueRef values[4];
1293 bool skip_lds_store;
1294 bool is_tess_factor = false, is_tess_inner = false;
1295
1296 /* Only handle per-patch and per-vertex outputs here.
1297 * Vectors will be lowered to scalars and this function will be called again.
1298 */
1299 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1300 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1301 si_llvm_emit_store(bld_base, inst, info, index, dst);
1302 return;
1303 }
1304
1305 if (reg->Register.Dimension) {
1306 stride = get_tcs_out_vertex_dw_stride(ctx);
1307 dw_addr = get_tcs_out_current_patch_offset(ctx);
1308 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1309 skip_lds_store = !sh_info->reads_pervertex_outputs;
1310 } else {
1311 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1312 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1313 skip_lds_store = !sh_info->reads_perpatch_outputs;
1314
1315 if (!reg->Register.Indirect) {
1316 int name = sh_info->output_semantic_name[reg->Register.Index];
1317
1318 /* Always write tess factors into LDS for the TCS epilog. */
1319 if (name == TGSI_SEMANTIC_TESSINNER ||
1320 name == TGSI_SEMANTIC_TESSOUTER) {
1321 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1322 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1323 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1324 is_tess_factor = true;
1325 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1326 }
1327 }
1328 }
1329
1330 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1331
1332 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1333 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1334
1335 uint32_t writemask = reg->Register.WriteMask;
1336 while (writemask) {
1337 chan_index = u_bit_scan(&writemask);
1338 LLVMValueRef value = dst[chan_index];
1339
1340 if (inst->Instruction.Saturate)
1341 value = ac_build_clamp(&ctx->ac, value);
1342
1343 /* Skip LDS stores if there is no LDS read of this output. */
1344 if (!skip_lds_store)
1345 lds_store(ctx, chan_index, dw_addr, value);
1346
1347 value = ac_to_integer(&ctx->ac, value);
1348 values[chan_index] = value;
1349
1350 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1351 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1352 buf_addr, base,
1353 4 * chan_index, 1, 0, true, false);
1354 }
1355
1356 /* Write tess factors into VGPRs for the epilog. */
1357 if (is_tess_factor &&
1358 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1359 if (!is_tess_inner) {
1360 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1361 ctx->invoc0_tess_factors[chan_index]);
1362 } else if (chan_index < 2) {
1363 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1364 ctx->invoc0_tess_factors[4 + chan_index]);
1365 }
1366 }
1367 }
1368
1369 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1370 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1371 values, 4);
1372 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1373 base, 0, 1, 0, true, false);
1374 }
1375 }
1376
1377 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1378 unsigned input_index,
1379 unsigned vtx_offset_param,
1380 LLVMTypeRef type,
1381 unsigned swizzle)
1382 {
1383 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1384 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1385 struct si_shader *shader = ctx->shader;
1386 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1387 LLVMValueRef vtx_offset, soffset;
1388 struct tgsi_shader_info *info = &shader->selector->info;
1389 unsigned semantic_name = info->input_semantic_name[input_index];
1390 unsigned semantic_index = info->input_semantic_index[input_index];
1391 unsigned param;
1392 LLVMValueRef value;
1393
1394 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1395
1396 /* GFX9 has the ESGS ring in LDS. */
1397 if (ctx->screen->info.chip_class >= GFX9) {
1398 unsigned index = vtx_offset_param;
1399
1400 switch (index / 2) {
1401 case 0:
1402 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx01_offset,
1403 index % 2 ? 16 : 0, 16);
1404 break;
1405 case 1:
1406 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx23_offset,
1407 index % 2 ? 16 : 0, 16);
1408 break;
1409 case 2:
1410 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx45_offset,
1411 index % 2 ? 16 : 0, 16);
1412 break;
1413 default:
1414 assert(0);
1415 return NULL;
1416 }
1417
1418 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1419 LLVMConstInt(ctx->i32, param * 4, 0), "");
1420 return lds_load(bld_base, type, swizzle, vtx_offset);
1421 }
1422
1423 /* GFX6: input load from the ESGS ring in memory. */
1424 if (swizzle == ~0) {
1425 LLVMValueRef values[TGSI_NUM_CHANNELS];
1426 unsigned chan;
1427 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1428 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1429 type, chan);
1430 }
1431 return lp_build_gather_values(&ctx->gallivm, values,
1432 TGSI_NUM_CHANNELS);
1433 }
1434
1435 /* Get the vertex offset parameter on GFX6. */
1436 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1437
1438 vtx_offset = lp_build_mul_imm(uint, gs_vtx_offset, 4);
1439
1440 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1441
1442 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1443 vtx_offset, soffset, 0, 1, 0, true, false);
1444 if (llvm_type_is_64bit(ctx, type)) {
1445 LLVMValueRef value2;
1446 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1447
1448 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1449 ctx->i32_0, vtx_offset, soffset,
1450 0, 1, 0, true, false);
1451 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1452 }
1453 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1454 }
1455
1456 static LLVMValueRef fetch_input_gs(
1457 struct lp_build_tgsi_context *bld_base,
1458 const struct tgsi_full_src_register *reg,
1459 enum tgsi_opcode_type type,
1460 unsigned swizzle)
1461 {
1462 struct si_shader_context *ctx = si_shader_context(bld_base);
1463 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1464
1465 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1466 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1467 return get_primitive_id(ctx, swizzle);
1468
1469 if (!reg->Register.Dimension)
1470 return NULL;
1471
1472 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1473 reg->Dimension.Index,
1474 tgsi2llvmtype(bld_base, type),
1475 swizzle);
1476 }
1477
1478 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1479 {
1480 switch (interpolate) {
1481 case TGSI_INTERPOLATE_CONSTANT:
1482 return 0;
1483
1484 case TGSI_INTERPOLATE_LINEAR:
1485 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1486 return SI_PARAM_LINEAR_SAMPLE;
1487 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1488 return SI_PARAM_LINEAR_CENTROID;
1489 else
1490 return SI_PARAM_LINEAR_CENTER;
1491 break;
1492 case TGSI_INTERPOLATE_COLOR:
1493 case TGSI_INTERPOLATE_PERSPECTIVE:
1494 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1495 return SI_PARAM_PERSP_SAMPLE;
1496 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1497 return SI_PARAM_PERSP_CENTROID;
1498 else
1499 return SI_PARAM_PERSP_CENTER;
1500 break;
1501 default:
1502 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1503 return -1;
1504 }
1505 }
1506
1507 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1508 unsigned attr_index, unsigned chan,
1509 LLVMValueRef prim_mask,
1510 LLVMValueRef i, LLVMValueRef j)
1511 {
1512 if (i || j) {
1513 return ac_build_fs_interp(&ctx->ac,
1514 LLVMConstInt(ctx->i32, chan, 0),
1515 LLVMConstInt(ctx->i32, attr_index, 0),
1516 prim_mask, i, j);
1517 }
1518 return ac_build_fs_interp_mov(&ctx->ac,
1519 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1520 LLVMConstInt(ctx->i32, chan, 0),
1521 LLVMConstInt(ctx->i32, attr_index, 0),
1522 prim_mask);
1523 }
1524
1525 /**
1526 * Interpolate a fragment shader input.
1527 *
1528 * @param ctx context
1529 * @param input_index index of the input in hardware
1530 * @param semantic_name TGSI_SEMANTIC_*
1531 * @param semantic_index semantic index
1532 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1533 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1534 * @param interp_param interpolation weights (i,j)
1535 * @param prim_mask SI_PARAM_PRIM_MASK
1536 * @param face SI_PARAM_FRONT_FACE
1537 * @param result the return value (4 components)
1538 */
1539 static void interp_fs_input(struct si_shader_context *ctx,
1540 unsigned input_index,
1541 unsigned semantic_name,
1542 unsigned semantic_index,
1543 unsigned num_interp_inputs,
1544 unsigned colors_read_mask,
1545 LLVMValueRef interp_param,
1546 LLVMValueRef prim_mask,
1547 LLVMValueRef face,
1548 LLVMValueRef result[4])
1549 {
1550 LLVMValueRef i = NULL, j = NULL;
1551 unsigned chan;
1552
1553 /* fs.constant returns the param from the middle vertex, so it's not
1554 * really useful for flat shading. It's meant to be used for custom
1555 * interpolation (but the intrinsic can't fetch from the other two
1556 * vertices).
1557 *
1558 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1559 * to do the right thing. The only reason we use fs.constant is that
1560 * fs.interp cannot be used on integers, because they can be equal
1561 * to NaN.
1562 *
1563 * When interp is false we will use fs.constant or for newer llvm,
1564 * amdgcn.interp.mov.
1565 */
1566 bool interp = interp_param != NULL;
1567
1568 if (interp) {
1569 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1570 LLVMVectorType(ctx->f32, 2), "");
1571
1572 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1573 ctx->i32_0, "");
1574 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1575 ctx->i32_1, "");
1576 }
1577
1578 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1579 ctx->shader->key.part.ps.prolog.color_two_side) {
1580 LLVMValueRef is_face_positive;
1581
1582 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1583 * otherwise it's at offset "num_inputs".
1584 */
1585 unsigned back_attr_offset = num_interp_inputs;
1586 if (semantic_index == 1 && colors_read_mask & 0xf)
1587 back_attr_offset += 1;
1588
1589 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1590 face, ctx->i32_0, "");
1591
1592 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1593 LLVMValueRef front, back;
1594
1595 front = si_build_fs_interp(ctx,
1596 input_index, chan,
1597 prim_mask, i, j);
1598 back = si_build_fs_interp(ctx,
1599 back_attr_offset, chan,
1600 prim_mask, i, j);
1601
1602 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1603 is_face_positive,
1604 front,
1605 back,
1606 "");
1607 }
1608 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1609 result[0] = si_build_fs_interp(ctx, input_index,
1610 0, prim_mask, i, j);
1611 result[1] =
1612 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1613 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1614 } else {
1615 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1616 result[chan] = si_build_fs_interp(ctx,
1617 input_index, chan,
1618 prim_mask, i, j);
1619 }
1620 }
1621 }
1622
1623 void si_llvm_load_input_fs(
1624 struct si_shader_context *ctx,
1625 unsigned input_index,
1626 LLVMValueRef out[4])
1627 {
1628 struct lp_build_context *base = &ctx->bld_base.base;
1629 struct si_shader *shader = ctx->shader;
1630 struct tgsi_shader_info *info = &shader->selector->info;
1631 LLVMValueRef main_fn = ctx->main_fn;
1632 LLVMValueRef interp_param = NULL;
1633 int interp_param_idx;
1634 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1635 unsigned semantic_index = info->input_semantic_index[input_index];
1636 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1637 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1638
1639 /* Get colors from input VGPRs (set by the prolog). */
1640 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1641 unsigned colors_read = shader->selector->info.colors_read;
1642 unsigned mask = colors_read >> (semantic_index * 4);
1643 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1644 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1645
1646 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1647 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1648 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1649 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1650 return;
1651 }
1652
1653 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1654 if (interp_param_idx == -1)
1655 return;
1656 else if (interp_param_idx) {
1657 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1658 }
1659
1660 interp_fs_input(ctx, input_index, semantic_name,
1661 semantic_index, 0, /* this param is unused */
1662 shader->selector->info.colors_read, interp_param,
1663 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1664 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1665 &out[0]);
1666 }
1667
1668 static void declare_input_fs(
1669 struct si_shader_context *ctx,
1670 unsigned input_index,
1671 const struct tgsi_full_declaration *decl,
1672 LLVMValueRef out[4])
1673 {
1674 si_llvm_load_input_fs(ctx, input_index, out);
1675 }
1676
1677 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1678 {
1679 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1680 }
1681
1682
1683 /**
1684 * Load a dword from a constant buffer.
1685 */
1686 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1687 LLVMValueRef resource,
1688 LLVMValueRef offset)
1689 {
1690 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1691 0, 0, 0, true, true);
1692 }
1693
1694 static LLVMValueRef load_sample_position(struct si_shader_context *ctx, LLVMValueRef sample_id)
1695 {
1696 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1697 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1698 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1699 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1700
1701 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1702 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1703 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1704
1705 LLVMValueRef pos[4] = {
1706 buffer_load_const(ctx, resource, offset0),
1707 buffer_load_const(ctx, resource, offset1),
1708 LLVMConstReal(ctx->f32, 0),
1709 LLVMConstReal(ctx->f32, 0)
1710 };
1711
1712 return lp_build_gather_values(&ctx->gallivm, pos, 4);
1713 }
1714
1715 void si_load_system_value(struct si_shader_context *ctx,
1716 unsigned index,
1717 const struct tgsi_full_declaration *decl)
1718 {
1719 struct lp_build_context *bld = &ctx->bld_base.base;
1720 LLVMValueRef value = 0;
1721
1722 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
1723
1724 switch (decl->Semantic.Name) {
1725 case TGSI_SEMANTIC_INSTANCEID:
1726 value = ctx->abi.instance_id;
1727 break;
1728
1729 case TGSI_SEMANTIC_VERTEXID:
1730 value = LLVMBuildAdd(ctx->ac.builder,
1731 ctx->abi.vertex_id,
1732 ctx->abi.base_vertex, "");
1733 break;
1734
1735 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1736 /* Unused. Clarify the meaning in indexed vs. non-indexed
1737 * draws if this is ever used again. */
1738 assert(false);
1739 break;
1740
1741 case TGSI_SEMANTIC_BASEVERTEX:
1742 {
1743 /* For non-indexed draws, the base vertex set by the driver
1744 * (for direct draws) or the CP (for indirect draws) is the
1745 * first vertex ID, but GLSL expects 0 to be returned.
1746 */
1747 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
1748 LLVMValueRef indexed;
1749
1750 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1751 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1752
1753 value = LLVMBuildSelect(ctx->ac.builder, indexed,
1754 ctx->abi.base_vertex, ctx->i32_0, "");
1755 break;
1756 }
1757
1758 case TGSI_SEMANTIC_BASEINSTANCE:
1759 value = ctx->abi.start_instance;
1760 break;
1761
1762 case TGSI_SEMANTIC_DRAWID:
1763 value = ctx->abi.draw_id;
1764 break;
1765
1766 case TGSI_SEMANTIC_INVOCATIONID:
1767 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1768 value = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
1769 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1770 value = ctx->abi.gs_invocation_id;
1771 else
1772 assert(!"INVOCATIONID not implemented");
1773 break;
1774
1775 case TGSI_SEMANTIC_POSITION:
1776 {
1777 LLVMValueRef pos[4] = {
1778 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1779 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1780 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
1781 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
1782 LLVMGetParam(ctx->main_fn,
1783 SI_PARAM_POS_W_FLOAT)),
1784 };
1785 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
1786 break;
1787 }
1788
1789 case TGSI_SEMANTIC_FACE:
1790 value = ctx->abi.front_face;
1791 break;
1792
1793 case TGSI_SEMANTIC_SAMPLEID:
1794 value = get_sample_id(ctx);
1795 break;
1796
1797 case TGSI_SEMANTIC_SAMPLEPOS: {
1798 LLVMValueRef pos[4] = {
1799 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1800 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1801 LLVMConstReal(ctx->f32, 0),
1802 LLVMConstReal(ctx->f32, 0)
1803 };
1804 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
1805 TGSI_OPCODE_FRC, pos[0]);
1806 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
1807 TGSI_OPCODE_FRC, pos[1]);
1808 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
1809 break;
1810 }
1811
1812 case TGSI_SEMANTIC_SAMPLEMASK:
1813 /* This can only occur with the OpenGL Core profile, which
1814 * doesn't support smoothing.
1815 */
1816 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1817 break;
1818
1819 case TGSI_SEMANTIC_TESSCOORD:
1820 {
1821 LLVMValueRef coord[4] = {
1822 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1823 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1824 ctx->ac.f32_0,
1825 ctx->ac.f32_0
1826 };
1827
1828 /* For triangles, the vector should be (u, v, 1-u-v). */
1829 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1830 PIPE_PRIM_TRIANGLES)
1831 coord[2] = lp_build_sub(bld, ctx->ac.f32_1,
1832 lp_build_add(bld, coord[0], coord[1]));
1833
1834 value = lp_build_gather_values(&ctx->gallivm, coord, 4);
1835 break;
1836 }
1837
1838 case TGSI_SEMANTIC_VERTICESIN:
1839 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1840 value = unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6);
1841 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1842 value = get_num_tcs_out_vertices(ctx);
1843 else
1844 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1845 break;
1846
1847 case TGSI_SEMANTIC_TESSINNER:
1848 case TGSI_SEMANTIC_TESSOUTER:
1849 {
1850 LLVMValueRef buffer, base, addr;
1851 int param = si_shader_io_get_unique_index_patch(decl->Semantic.Name, 0);
1852
1853 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1854
1855 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1856 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1857 LLVMConstInt(ctx->i32, param, 0));
1858
1859 value = buffer_load(&ctx->bld_base, ctx->f32,
1860 ~0, buffer, base, addr, true);
1861
1862 break;
1863 }
1864
1865 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1866 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1867 {
1868 LLVMValueRef buf, slot, val[4];
1869 int i, offset;
1870
1871 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
1872 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1873 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
1874 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1875
1876 for (i = 0; i < 4; i++)
1877 val[i] = buffer_load_const(ctx, buf,
1878 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
1879 value = lp_build_gather_values(&ctx->gallivm, val, 4);
1880 break;
1881 }
1882
1883 case TGSI_SEMANTIC_PRIMID:
1884 value = get_primitive_id(ctx, 0);
1885 break;
1886
1887 case TGSI_SEMANTIC_GRID_SIZE:
1888 value = LLVMGetParam(ctx->main_fn, ctx->param_grid_size);
1889 break;
1890
1891 case TGSI_SEMANTIC_BLOCK_SIZE:
1892 {
1893 LLVMValueRef values[3];
1894 unsigned i;
1895 unsigned *properties = ctx->shader->selector->info.properties;
1896
1897 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1898 unsigned sizes[3] = {
1899 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1900 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1901 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1902 };
1903
1904 for (i = 0; i < 3; ++i)
1905 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1906
1907 value = lp_build_gather_values(&ctx->gallivm, values, 3);
1908 } else {
1909 value = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1910 }
1911 break;
1912 }
1913
1914 case TGSI_SEMANTIC_BLOCK_ID:
1915 {
1916 LLVMValueRef values[3];
1917
1918 for (int i = 0; i < 3; i++) {
1919 values[i] = ctx->i32_0;
1920 if (ctx->param_block_id[i] >= 0) {
1921 values[i] = LLVMGetParam(ctx->main_fn,
1922 ctx->param_block_id[i]);
1923 }
1924 }
1925 value = lp_build_gather_values(&ctx->gallivm, values, 3);
1926 break;
1927 }
1928
1929 case TGSI_SEMANTIC_THREAD_ID:
1930 value = LLVMGetParam(ctx->main_fn, ctx->param_thread_id);
1931 break;
1932
1933 case TGSI_SEMANTIC_HELPER_INVOCATION:
1934 value = lp_build_intrinsic(ctx->ac.builder,
1935 "llvm.amdgcn.ps.live",
1936 ctx->i1, NULL, 0,
1937 LP_FUNC_ATTR_READNONE);
1938 value = LLVMBuildNot(ctx->ac.builder, value, "");
1939 value = LLVMBuildSExt(ctx->ac.builder, value, ctx->i32, "");
1940 break;
1941
1942 case TGSI_SEMANTIC_SUBGROUP_SIZE:
1943 value = LLVMConstInt(ctx->i32, 64, 0);
1944 break;
1945
1946 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
1947 value = ac_get_thread_id(&ctx->ac);
1948 break;
1949
1950 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
1951 {
1952 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1953 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
1954 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
1955 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
1956 break;
1957 }
1958
1959 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
1960 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
1961 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
1962 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
1963 {
1964 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1965 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
1966 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
1967 /* All bits set except LSB */
1968 value = LLVMConstInt(ctx->i64, -2, 0);
1969 } else {
1970 /* All bits set */
1971 value = LLVMConstInt(ctx->i64, -1, 0);
1972 }
1973 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
1974 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
1975 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
1976 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
1977 value = LLVMBuildNot(ctx->ac.builder, value, "");
1978 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
1979 break;
1980 }
1981
1982 default:
1983 assert(!"unknown system value");
1984 return;
1985 }
1986
1987 ctx->system_values[index] = value;
1988 }
1989
1990 void si_declare_compute_memory(struct si_shader_context *ctx,
1991 const struct tgsi_full_declaration *decl)
1992 {
1993 struct si_shader_selector *sel = ctx->shader->selector;
1994
1995 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1996 LLVMValueRef var;
1997
1998 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1999 assert(decl->Range.First == decl->Range.Last);
2000 assert(!ctx->ac.lds);
2001
2002 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2003 LLVMArrayType(ctx->i8, sel->local_size),
2004 "compute_lds",
2005 LOCAL_ADDR_SPACE);
2006 LLVMSetAlignment(var, 4);
2007
2008 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2009 }
2010
2011 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2012 {
2013 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2014 ctx->param_const_and_shader_buffers);
2015
2016 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2017 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2018 }
2019
2020 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2021 {
2022 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2023 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2024
2025 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2026 index = LLVMBuildAdd(ctx->ac.builder, index,
2027 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2028
2029 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2030 }
2031
2032 static LLVMValueRef
2033 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2034 {
2035 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2036 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2037 ctx->param_const_and_shader_buffers);
2038
2039 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2040 index = LLVMBuildSub(ctx->ac.builder,
2041 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2042 index, "");
2043
2044 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2045 }
2046
2047 static LLVMValueRef fetch_constant(
2048 struct lp_build_tgsi_context *bld_base,
2049 const struct tgsi_full_src_register *reg,
2050 enum tgsi_opcode_type type,
2051 unsigned swizzle)
2052 {
2053 struct si_shader_context *ctx = si_shader_context(bld_base);
2054 struct si_shader_selector *sel = ctx->shader->selector;
2055 const struct tgsi_ind_register *ireg = &reg->Indirect;
2056 unsigned buf, idx;
2057
2058 LLVMValueRef addr, bufp;
2059
2060 if (swizzle == LP_CHAN_ALL) {
2061 unsigned chan;
2062 LLVMValueRef values[4];
2063 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2064 values[chan] = fetch_constant(bld_base, reg, type, chan);
2065
2066 return lp_build_gather_values(&ctx->gallivm, values, 4);
2067 }
2068
2069 /* Split 64-bit loads. */
2070 if (tgsi_type_is_64bit(type)) {
2071 LLVMValueRef lo, hi;
2072
2073 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2074 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle + 1);
2075 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2076 lo, hi);
2077 }
2078
2079 idx = reg->Register.Index * 4 + swizzle;
2080 if (reg->Register.Indirect) {
2081 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2082 } else {
2083 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2084 }
2085
2086 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2087 if (sel->info.const_buffers_declared == 1 &&
2088 sel->info.shader_buffers_declared == 0) {
2089 LLVMValueRef ptr =
2090 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2091
2092 /* This enables use of s_load_dword and flat_load_dword for const buffer 0
2093 * loads, and up to x4 load opcode merging. However, it leads to horrible
2094 * code reducing SIMD wave occupancy from 8 to 2 in many cases.
2095 *
2096 * Using s_buffer_load_dword (x1) seems to be the best option right now.
2097 *
2098 * LLVM 5.0 on SI doesn't insert a required s_nop between SALU setting
2099 * a descriptor and s_buffer_load_dword using it, so we can't expand
2100 * the pointer into a full descriptor like below. We have to use
2101 * s_load_dword instead. The only case when LLVM 5.0 would select
2102 * s_buffer_load_dword (that we have to prevent) is when we use use
2103 * a literal offset where we don't need bounds checking.
2104 */
2105 if (ctx->screen->info.chip_class == SI &&
2106 HAVE_LLVM < 0x0600 &&
2107 !reg->Register.Indirect) {
2108 addr = LLVMBuildLShr(ctx->ac.builder, addr, LLVMConstInt(ctx->i32, 2, 0), "");
2109 LLVMValueRef result = ac_build_load_invariant(&ctx->ac, ptr, addr);
2110 return bitcast(bld_base, type, result);
2111 }
2112
2113 /* Do the bounds checking with a descriptor, because
2114 * doing computation and manual bounds checking of 64-bit
2115 * addresses generates horrible VALU code with very high
2116 * VGPR usage and very low SIMD occupancy.
2117 */
2118 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->i64, "");
2119 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ctx->v2i32, "");
2120
2121 LLVMValueRef desc_elems[] = {
2122 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_0, ""),
2123 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_1, ""),
2124 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2125 LLVMConstInt(ctx->i32,
2126 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2127 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2128 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2129 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2130 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2131 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2132 };
2133 LLVMValueRef desc = ac_build_gather_values(&ctx->ac, desc_elems, 4);
2134 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2135 return bitcast(bld_base, type, result);
2136 }
2137
2138 assert(reg->Register.Dimension);
2139 buf = reg->Dimension.Index;
2140
2141 if (reg->Dimension.Indirect) {
2142 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2143 LLVMValueRef index;
2144 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2145 reg->Dimension.Index,
2146 ctx->num_const_buffers);
2147 index = LLVMBuildAdd(ctx->ac.builder, index,
2148 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2149 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2150 } else
2151 bufp = load_const_buffer_desc(ctx, buf);
2152
2153 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2154 }
2155
2156 /* Upper 16 bits must be zero. */
2157 static LLVMValueRef si_llvm_pack_two_int16(struct si_shader_context *ctx,
2158 LLVMValueRef val[2])
2159 {
2160 return LLVMBuildOr(ctx->ac.builder, val[0],
2161 LLVMBuildShl(ctx->ac.builder, val[1],
2162 LLVMConstInt(ctx->i32, 16, 0),
2163 ""), "");
2164 }
2165
2166 /* Upper 16 bits are ignored and will be dropped. */
2167 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct si_shader_context *ctx,
2168 LLVMValueRef val[2])
2169 {
2170 LLVMValueRef v[2] = {
2171 LLVMBuildAnd(ctx->ac.builder, val[0],
2172 LLVMConstInt(ctx->i32, 0xffff, 0), ""),
2173 val[1],
2174 };
2175 return si_llvm_pack_two_int16(ctx, v);
2176 }
2177
2178 /* Initialize arguments for the shader export intrinsic */
2179 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2180 LLVMValueRef *values,
2181 unsigned target,
2182 struct ac_export_args *args)
2183 {
2184 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2185 LLVMBuilderRef builder = ctx->ac.builder;
2186 LLVMValueRef val[4];
2187 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2188 unsigned chan;
2189 bool is_int8, is_int10;
2190
2191 /* Default is 0xf. Adjusted below depending on the format. */
2192 args->enabled_channels = 0xf; /* writemask */
2193
2194 /* Specify whether the EXEC mask represents the valid mask */
2195 args->valid_mask = 0;
2196
2197 /* Specify whether this is the last export */
2198 args->done = 0;
2199
2200 /* Specify the target we are exporting */
2201 args->target = target;
2202
2203 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2204 const struct si_shader_key *key = &ctx->shader->key;
2205 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2206 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2207
2208 assert(cbuf >= 0 && cbuf < 8);
2209 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2210 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2211 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2212 }
2213
2214 args->compr = false;
2215 args->out[0] = f32undef;
2216 args->out[1] = f32undef;
2217 args->out[2] = f32undef;
2218 args->out[3] = f32undef;
2219
2220 switch (spi_shader_col_format) {
2221 case V_028714_SPI_SHADER_ZERO:
2222 args->enabled_channels = 0; /* writemask */
2223 args->target = V_008DFC_SQ_EXP_NULL;
2224 break;
2225
2226 case V_028714_SPI_SHADER_32_R:
2227 args->enabled_channels = 1; /* writemask */
2228 args->out[0] = values[0];
2229 break;
2230
2231 case V_028714_SPI_SHADER_32_GR:
2232 args->enabled_channels = 0x3; /* writemask */
2233 args->out[0] = values[0];
2234 args->out[1] = values[1];
2235 break;
2236
2237 case V_028714_SPI_SHADER_32_AR:
2238 args->enabled_channels = 0x9; /* writemask */
2239 args->out[0] = values[0];
2240 args->out[3] = values[3];
2241 break;
2242
2243 case V_028714_SPI_SHADER_FP16_ABGR:
2244 args->compr = 1; /* COMPR flag */
2245
2246 for (chan = 0; chan < 2; chan++) {
2247 LLVMValueRef pack_args[2] = {
2248 values[2 * chan],
2249 values[2 * chan + 1]
2250 };
2251 LLVMValueRef packed;
2252
2253 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
2254 args->out[chan] = ac_to_float(&ctx->ac, packed);
2255 }
2256 break;
2257
2258 case V_028714_SPI_SHADER_UNORM16_ABGR:
2259 for (chan = 0; chan < 4; chan++) {
2260 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
2261 val[chan] = LLVMBuildFMul(builder, val[chan],
2262 LLVMConstReal(ctx->f32, 65535), "");
2263 val[chan] = LLVMBuildFAdd(builder, val[chan],
2264 LLVMConstReal(ctx->f32, 0.5), "");
2265 val[chan] = LLVMBuildFPToUI(builder, val[chan],
2266 ctx->i32, "");
2267 }
2268
2269 args->compr = 1; /* COMPR flag */
2270 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val));
2271 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val+2));
2272 break;
2273
2274 case V_028714_SPI_SHADER_SNORM16_ABGR:
2275 for (chan = 0; chan < 4; chan++) {
2276 /* Clamp between [-1, 1]. */
2277 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base, TGSI_OPCODE_MIN,
2278 values[chan],
2279 LLVMConstReal(ctx->f32, 1));
2280 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base, TGSI_OPCODE_MAX,
2281 val[chan],
2282 LLVMConstReal(ctx->f32, -1));
2283 /* Convert to a signed integer in [-32767, 32767]. */
2284 val[chan] = LLVMBuildFMul(builder, val[chan],
2285 LLVMConstReal(ctx->f32, 32767), "");
2286 /* If positive, add 0.5, else add -0.5. */
2287 val[chan] = LLVMBuildFAdd(builder, val[chan],
2288 LLVMBuildSelect(builder,
2289 LLVMBuildFCmp(builder, LLVMRealOGE,
2290 val[chan], ctx->ac.f32_0, ""),
2291 LLVMConstReal(ctx->f32, 0.5),
2292 LLVMConstReal(ctx->f32, -0.5), ""), "");
2293 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2294 }
2295
2296 args->compr = 1; /* COMPR flag */
2297 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val));
2298 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val+2));
2299 break;
2300
2301 case V_028714_SPI_SHADER_UINT16_ABGR: {
2302 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2303 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
2304 LLVMValueRef max_alpha =
2305 !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
2306
2307 /* Clamp. */
2308 for (chan = 0; chan < 4; chan++) {
2309 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
2310 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base, TGSI_OPCODE_UMIN,
2311 val[chan],
2312 chan == 3 ? max_alpha : max_rgb);
2313 }
2314
2315 args->compr = 1; /* COMPR flag */
2316 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val));
2317 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val+2));
2318 break;
2319 }
2320
2321 case V_028714_SPI_SHADER_SINT16_ABGR: {
2322 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2323 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
2324 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
2325 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
2326 LLVMValueRef max_alpha =
2327 !is_int10 ? max_rgb : ctx->i32_1;
2328 LLVMValueRef min_alpha =
2329 !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
2330
2331 /* Clamp. */
2332 for (chan = 0; chan < 4; chan++) {
2333 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
2334 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base,
2335 TGSI_OPCODE_IMIN,
2336 val[chan], chan == 3 ? max_alpha : max_rgb);
2337 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base,
2338 TGSI_OPCODE_IMAX,
2339 val[chan], chan == 3 ? min_alpha : min_rgb);
2340 }
2341
2342 args->compr = 1; /* COMPR flag */
2343 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val));
2344 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val+2));
2345 break;
2346 }
2347
2348 case V_028714_SPI_SHADER_32_ABGR:
2349 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2350 break;
2351 }
2352 }
2353
2354 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2355 LLVMValueRef alpha)
2356 {
2357 struct si_shader_context *ctx = si_shader_context(bld_base);
2358
2359 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2360 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2361 [PIPE_FUNC_LESS] = LLVMRealOLT,
2362 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2363 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2364 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2365 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2366 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2367 };
2368 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2369 assert(cond);
2370
2371 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2372 SI_PARAM_ALPHA_REF);
2373 LLVMValueRef alpha_pass =
2374 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2375 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2376 } else {
2377 ac_build_kill_if_false(&ctx->ac, LLVMConstInt(ctx->i1, 0, 0));
2378 }
2379 }
2380
2381 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2382 LLVMValueRef alpha,
2383 unsigned samplemask_param)
2384 {
2385 struct si_shader_context *ctx = si_shader_context(bld_base);
2386 LLVMValueRef coverage;
2387
2388 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2389 coverage = LLVMGetParam(ctx->main_fn,
2390 samplemask_param);
2391 coverage = ac_to_integer(&ctx->ac, coverage);
2392
2393 coverage = lp_build_intrinsic(ctx->ac.builder, "llvm.ctpop.i32",
2394 ctx->i32,
2395 &coverage, 1, LP_FUNC_ATTR_READNONE);
2396
2397 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2398 ctx->f32, "");
2399
2400 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2401 LLVMConstReal(ctx->f32,
2402 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2403
2404 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2405 }
2406
2407 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2408 struct ac_export_args *pos, LLVMValueRef *out_elts)
2409 {
2410 unsigned reg_index;
2411 unsigned chan;
2412 unsigned const_chan;
2413 LLVMValueRef base_elt;
2414 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2415 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2416 SI_VS_CONST_CLIP_PLANES, 0);
2417 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2418
2419 for (reg_index = 0; reg_index < 2; reg_index ++) {
2420 struct ac_export_args *args = &pos[2 + reg_index];
2421
2422 args->out[0] =
2423 args->out[1] =
2424 args->out[2] =
2425 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2426
2427 /* Compute dot products of position and user clip plane vectors */
2428 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2429 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2430 LLVMValueRef addr =
2431 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2432 const_chan) * 4, 0);
2433 base_elt = buffer_load_const(ctx, const_resource,
2434 addr);
2435 args->out[chan] =
2436 lp_build_add(&ctx->bld_base.base, args->out[chan],
2437 lp_build_mul(&ctx->bld_base.base, base_elt,
2438 out_elts[const_chan]));
2439 }
2440 }
2441
2442 args->enabled_channels = 0xf;
2443 args->valid_mask = 0;
2444 args->done = 0;
2445 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2446 args->compr = 0;
2447 }
2448 }
2449
2450 static void si_dump_streamout(struct pipe_stream_output_info *so)
2451 {
2452 unsigned i;
2453
2454 if (so->num_outputs)
2455 fprintf(stderr, "STREAMOUT\n");
2456
2457 for (i = 0; i < so->num_outputs; i++) {
2458 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2459 so->output[i].start_component;
2460 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2461 i, so->output[i].output_buffer,
2462 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2463 so->output[i].register_index,
2464 mask & 1 ? "x" : "",
2465 mask & 2 ? "y" : "",
2466 mask & 4 ? "z" : "",
2467 mask & 8 ? "w" : "");
2468 }
2469 }
2470
2471 static void emit_streamout_output(struct si_shader_context *ctx,
2472 LLVMValueRef const *so_buffers,
2473 LLVMValueRef const *so_write_offsets,
2474 struct pipe_stream_output *stream_out,
2475 struct si_shader_output_values *shader_out)
2476 {
2477 unsigned buf_idx = stream_out->output_buffer;
2478 unsigned start = stream_out->start_component;
2479 unsigned num_comps = stream_out->num_components;
2480 LLVMValueRef out[4];
2481
2482 assert(num_comps && num_comps <= 4);
2483 if (!num_comps || num_comps > 4)
2484 return;
2485
2486 /* Load the output as int. */
2487 for (int j = 0; j < num_comps; j++) {
2488 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2489
2490 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2491 }
2492
2493 /* Pack the output. */
2494 LLVMValueRef vdata = NULL;
2495
2496 switch (num_comps) {
2497 case 1: /* as i32 */
2498 vdata = out[0];
2499 break;
2500 case 2: /* as v2i32 */
2501 case 3: /* as v4i32 (aligned to 4) */
2502 case 4: /* as v4i32 */
2503 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2504 for (int j = 0; j < num_comps; j++) {
2505 vdata = LLVMBuildInsertElement(ctx->ac.builder, vdata, out[j],
2506 LLVMConstInt(ctx->i32, j, 0), "");
2507 }
2508 break;
2509 }
2510
2511 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2512 vdata, num_comps,
2513 so_write_offsets[buf_idx],
2514 ctx->i32_0,
2515 stream_out->dst_offset * 4, 1, 1, true, false);
2516 }
2517
2518 /**
2519 * Write streamout data to buffers for vertex stream @p stream (different
2520 * vertex streams can occur for GS copy shaders).
2521 */
2522 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2523 struct si_shader_output_values *outputs,
2524 unsigned noutput, unsigned stream)
2525 {
2526 struct si_shader_selector *sel = ctx->shader->selector;
2527 struct pipe_stream_output_info *so = &sel->so;
2528 LLVMBuilderRef builder = ctx->ac.builder;
2529 int i;
2530 struct lp_build_if_state if_ctx;
2531
2532 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2533 LLVMValueRef so_vtx_count =
2534 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2535
2536 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2537
2538 /* can_emit = tid < so_vtx_count; */
2539 LLVMValueRef can_emit =
2540 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2541
2542 /* Emit the streamout code conditionally. This actually avoids
2543 * out-of-bounds buffer access. The hw tells us via the SGPR
2544 * (so_vtx_count) which threads are allowed to emit streamout data. */
2545 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2546 {
2547 /* The buffer offset is computed as follows:
2548 * ByteOffset = streamout_offset[buffer_id]*4 +
2549 * (streamout_write_index + thread_id)*stride[buffer_id] +
2550 * attrib_offset
2551 */
2552
2553 LLVMValueRef so_write_index =
2554 LLVMGetParam(ctx->main_fn,
2555 ctx->param_streamout_write_index);
2556
2557 /* Compute (streamout_write_index + thread_id). */
2558 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2559
2560 /* Load the descriptor and compute the write offset for each
2561 * enabled buffer. */
2562 LLVMValueRef so_write_offset[4] = {};
2563 LLVMValueRef so_buffers[4];
2564 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2565 ctx->param_rw_buffers);
2566
2567 for (i = 0; i < 4; i++) {
2568 if (!so->stride[i])
2569 continue;
2570
2571 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2572 SI_VS_STREAMOUT_BUF0 + i, 0);
2573
2574 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2575
2576 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2577 ctx->param_streamout_offset[i]);
2578 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2579
2580 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2581 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2582 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2583 }
2584
2585 /* Write streamout data. */
2586 for (i = 0; i < so->num_outputs; i++) {
2587 unsigned reg = so->output[i].register_index;
2588
2589 if (reg >= noutput)
2590 continue;
2591
2592 if (stream != so->output[i].stream)
2593 continue;
2594
2595 emit_streamout_output(ctx, so_buffers, so_write_offset,
2596 &so->output[i], &outputs[reg]);
2597 }
2598 }
2599 lp_build_endif(&if_ctx);
2600 }
2601
2602 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2603 LLVMValueRef *values)
2604 {
2605 struct ac_export_args args;
2606
2607 si_llvm_init_export_args(ctx, values,
2608 V_008DFC_SQ_EXP_PARAM + index, &args);
2609 ac_build_export(&ctx->ac, &args);
2610 }
2611
2612 static void si_build_param_exports(struct si_shader_context *ctx,
2613 struct si_shader_output_values *outputs,
2614 unsigned noutput)
2615 {
2616 struct si_shader *shader = ctx->shader;
2617 unsigned param_count = 0;
2618
2619 for (unsigned i = 0; i < noutput; i++) {
2620 unsigned semantic_name = outputs[i].semantic_name;
2621 unsigned semantic_index = outputs[i].semantic_index;
2622
2623 if (outputs[i].vertex_stream[0] != 0 &&
2624 outputs[i].vertex_stream[1] != 0 &&
2625 outputs[i].vertex_stream[2] != 0 &&
2626 outputs[i].vertex_stream[3] != 0)
2627 continue;
2628
2629 switch (semantic_name) {
2630 case TGSI_SEMANTIC_LAYER:
2631 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2632 case TGSI_SEMANTIC_CLIPDIST:
2633 case TGSI_SEMANTIC_COLOR:
2634 case TGSI_SEMANTIC_BCOLOR:
2635 case TGSI_SEMANTIC_PRIMID:
2636 case TGSI_SEMANTIC_FOG:
2637 case TGSI_SEMANTIC_TEXCOORD:
2638 case TGSI_SEMANTIC_GENERIC:
2639 break;
2640 default:
2641 continue;
2642 }
2643
2644 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2645 semantic_index < SI_MAX_IO_GENERIC) &&
2646 shader->key.opt.kill_outputs &
2647 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2648 continue;
2649
2650 si_export_param(ctx, param_count, outputs[i].values);
2651
2652 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2653 shader->info.vs_output_param_offset[i] = param_count++;
2654 }
2655
2656 shader->info.nr_param_exports = param_count;
2657 }
2658
2659 /* Generate export instructions for hardware VS shader stage */
2660 static void si_llvm_export_vs(struct si_shader_context *ctx,
2661 struct si_shader_output_values *outputs,
2662 unsigned noutput)
2663 {
2664 struct si_shader *shader = ctx->shader;
2665 struct ac_export_args pos_args[4] = {};
2666 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2667 unsigned pos_idx;
2668 int i;
2669
2670 /* Build position exports. */
2671 for (i = 0; i < noutput; i++) {
2672 switch (outputs[i].semantic_name) {
2673 case TGSI_SEMANTIC_POSITION:
2674 si_llvm_init_export_args(ctx, outputs[i].values,
2675 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2676 break;
2677 case TGSI_SEMANTIC_PSIZE:
2678 psize_value = outputs[i].values[0];
2679 break;
2680 case TGSI_SEMANTIC_LAYER:
2681 layer_value = outputs[i].values[0];
2682 break;
2683 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2684 viewport_index_value = outputs[i].values[0];
2685 break;
2686 case TGSI_SEMANTIC_EDGEFLAG:
2687 edgeflag_value = outputs[i].values[0];
2688 break;
2689 case TGSI_SEMANTIC_CLIPDIST:
2690 if (!shader->key.opt.clip_disable) {
2691 unsigned index = 2 + outputs[i].semantic_index;
2692 si_llvm_init_export_args(ctx, outputs[i].values,
2693 V_008DFC_SQ_EXP_POS + index,
2694 &pos_args[index]);
2695 }
2696 break;
2697 case TGSI_SEMANTIC_CLIPVERTEX:
2698 if (!shader->key.opt.clip_disable) {
2699 si_llvm_emit_clipvertex(ctx, pos_args,
2700 outputs[i].values);
2701 }
2702 break;
2703 }
2704 }
2705
2706 /* We need to add the position output manually if it's missing. */
2707 if (!pos_args[0].out[0]) {
2708 pos_args[0].enabled_channels = 0xf; /* writemask */
2709 pos_args[0].valid_mask = 0; /* EXEC mask */
2710 pos_args[0].done = 0; /* last export? */
2711 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2712 pos_args[0].compr = 0; /* COMPR flag */
2713 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2714 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2715 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2716 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2717 }
2718
2719 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2720 if (shader->selector->info.writes_psize ||
2721 shader->selector->info.writes_edgeflag ||
2722 shader->selector->info.writes_viewport_index ||
2723 shader->selector->info.writes_layer) {
2724 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2725 (shader->selector->info.writes_edgeflag << 1) |
2726 (shader->selector->info.writes_layer << 2);
2727
2728 pos_args[1].valid_mask = 0; /* EXEC mask */
2729 pos_args[1].done = 0; /* last export? */
2730 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2731 pos_args[1].compr = 0; /* COMPR flag */
2732 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2733 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2734 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2735 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2736
2737 if (shader->selector->info.writes_psize)
2738 pos_args[1].out[0] = psize_value;
2739
2740 if (shader->selector->info.writes_edgeflag) {
2741 /* The output is a float, but the hw expects an integer
2742 * with the first bit containing the edge flag. */
2743 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2744 edgeflag_value,
2745 ctx->i32, "");
2746 edgeflag_value = ac_build_umin(&ctx->ac,
2747 edgeflag_value,
2748 ctx->i32_1);
2749
2750 /* The LLVM intrinsic expects a float. */
2751 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2752 }
2753
2754 if (ctx->screen->info.chip_class >= GFX9) {
2755 /* GFX9 has the layer in out.z[10:0] and the viewport
2756 * index in out.z[19:16].
2757 */
2758 if (shader->selector->info.writes_layer)
2759 pos_args[1].out[2] = layer_value;
2760
2761 if (shader->selector->info.writes_viewport_index) {
2762 LLVMValueRef v = viewport_index_value;
2763
2764 v = ac_to_integer(&ctx->ac, v);
2765 v = LLVMBuildShl(ctx->ac.builder, v,
2766 LLVMConstInt(ctx->i32, 16, 0), "");
2767 v = LLVMBuildOr(ctx->ac.builder, v,
2768 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2769 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2770 pos_args[1].enabled_channels |= 1 << 2;
2771 }
2772 } else {
2773 if (shader->selector->info.writes_layer)
2774 pos_args[1].out[2] = layer_value;
2775
2776 if (shader->selector->info.writes_viewport_index) {
2777 pos_args[1].out[3] = viewport_index_value;
2778 pos_args[1].enabled_channels |= 1 << 3;
2779 }
2780 }
2781 }
2782
2783 for (i = 0; i < 4; i++)
2784 if (pos_args[i].out[0])
2785 shader->info.nr_pos_exports++;
2786
2787 pos_idx = 0;
2788 for (i = 0; i < 4; i++) {
2789 if (!pos_args[i].out[0])
2790 continue;
2791
2792 /* Specify the target we are exporting */
2793 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2794
2795 if (pos_idx == shader->info.nr_pos_exports)
2796 /* Specify that this is the last export */
2797 pos_args[i].done = 1;
2798
2799 ac_build_export(&ctx->ac, &pos_args[i]);
2800 }
2801
2802 /* Build parameter exports. */
2803 si_build_param_exports(ctx, outputs, noutput);
2804 }
2805
2806 /**
2807 * Forward all outputs from the vertex shader to the TES. This is only used
2808 * for the fixed function TCS.
2809 */
2810 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2811 {
2812 struct si_shader_context *ctx = si_shader_context(bld_base);
2813 LLVMValueRef invocation_id, buffer, buffer_offset;
2814 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2815 uint64_t inputs;
2816
2817 invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
2818 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
2819 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2820
2821 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
2822 lds_vertex_offset = LLVMBuildMul(ctx->ac.builder, invocation_id,
2823 lds_vertex_stride, "");
2824 lds_base = get_tcs_in_current_patch_offset(ctx);
2825 lds_base = LLVMBuildAdd(ctx->ac.builder, lds_base, lds_vertex_offset, "");
2826
2827 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
2828 while (inputs) {
2829 unsigned i = u_bit_scan64(&inputs);
2830
2831 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2832 LLVMConstInt(ctx->i32, 4 * i, 0),
2833 "");
2834
2835 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2836 get_rel_patch_id(ctx),
2837 invocation_id,
2838 LLVMConstInt(ctx->i32, i, 0));
2839
2840 LLVMValueRef value = lds_load(bld_base, ctx->ac.i32, ~0,
2841 lds_ptr);
2842
2843 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
2844 buffer_offset, 0, 1, 0, true, false);
2845 }
2846 }
2847
2848 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2849 LLVMValueRef rel_patch_id,
2850 LLVMValueRef invocation_id,
2851 LLVMValueRef tcs_out_current_patch_data_offset,
2852 LLVMValueRef invoc0_tf_outer[4],
2853 LLVMValueRef invoc0_tf_inner[2])
2854 {
2855 struct si_shader_context *ctx = si_shader_context(bld_base);
2856 struct si_shader *shader = ctx->shader;
2857 unsigned tess_inner_index, tess_outer_index;
2858 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2859 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2860 unsigned stride, outer_comps, inner_comps, i, offset;
2861 struct lp_build_if_state if_ctx, inner_if_ctx;
2862
2863 /* Add a barrier before loading tess factors from LDS. */
2864 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
2865 si_llvm_emit_barrier(NULL, bld_base, NULL);
2866
2867 /* Do this only for invocation 0, because the tess levels are per-patch,
2868 * not per-vertex.
2869 *
2870 * This can't jump, because invocation 0 executes this. It should
2871 * at least mask out the loads and stores for other invocations.
2872 */
2873 lp_build_if(&if_ctx, &ctx->gallivm,
2874 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2875 invocation_id, ctx->i32_0, ""));
2876
2877 /* Determine the layout of one tess factor element in the buffer. */
2878 switch (shader->key.part.tcs.epilog.prim_mode) {
2879 case PIPE_PRIM_LINES:
2880 stride = 2; /* 2 dwords, 1 vec2 store */
2881 outer_comps = 2;
2882 inner_comps = 0;
2883 break;
2884 case PIPE_PRIM_TRIANGLES:
2885 stride = 4; /* 4 dwords, 1 vec4 store */
2886 outer_comps = 3;
2887 inner_comps = 1;
2888 break;
2889 case PIPE_PRIM_QUADS:
2890 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2891 outer_comps = 4;
2892 inner_comps = 2;
2893 break;
2894 default:
2895 assert(0);
2896 return;
2897 }
2898
2899 for (i = 0; i < 4; i++) {
2900 inner[i] = LLVMGetUndef(ctx->i32);
2901 outer[i] = LLVMGetUndef(ctx->i32);
2902 }
2903
2904 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
2905 /* Tess factors are in VGPRs. */
2906 for (i = 0; i < outer_comps; i++)
2907 outer[i] = out[i] = invoc0_tf_outer[i];
2908 for (i = 0; i < inner_comps; i++)
2909 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
2910 } else {
2911 /* Load tess_inner and tess_outer from LDS.
2912 * Any invocation can write them, so we can't get them from a temporary.
2913 */
2914 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
2915 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
2916
2917 lds_base = tcs_out_current_patch_data_offset;
2918 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2919 LLVMConstInt(ctx->i32,
2920 tess_inner_index * 4, 0), "");
2921 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2922 LLVMConstInt(ctx->i32,
2923 tess_outer_index * 4, 0), "");
2924
2925 for (i = 0; i < outer_comps; i++) {
2926 outer[i] = out[i] =
2927 lds_load(bld_base, ctx->ac.i32, i, lds_outer);
2928 }
2929 for (i = 0; i < inner_comps; i++) {
2930 inner[i] = out[outer_comps+i] =
2931 lds_load(bld_base, ctx->ac.i32, i, lds_inner);
2932 }
2933 }
2934
2935 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2936 /* For isolines, the hardware expects tess factors in the
2937 * reverse order from what GLSL / TGSI specify.
2938 */
2939 LLVMValueRef tmp = out[0];
2940 out[0] = out[1];
2941 out[1] = tmp;
2942 }
2943
2944 /* Convert the outputs to vectors for stores. */
2945 vec0 = lp_build_gather_values(&ctx->gallivm, out, MIN2(stride, 4));
2946 vec1 = NULL;
2947
2948 if (stride > 4)
2949 vec1 = lp_build_gather_values(&ctx->gallivm, out+4, stride - 4);
2950
2951 /* Get the buffer. */
2952 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_factor_addr_base64k);
2953
2954 /* Get the offset. */
2955 tf_base = LLVMGetParam(ctx->main_fn,
2956 ctx->param_tcs_factor_offset);
2957 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2958 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
2959
2960 lp_build_if(&inner_if_ctx, &ctx->gallivm,
2961 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2962 rel_patch_id, ctx->i32_0, ""));
2963
2964 /* Store the dynamic HS control word. */
2965 offset = 0;
2966 if (ctx->screen->info.chip_class <= VI) {
2967 ac_build_buffer_store_dword(&ctx->ac, buffer,
2968 LLVMConstInt(ctx->i32, 0x80000000, 0),
2969 1, ctx->i32_0, tf_base,
2970 offset, 1, 0, true, false);
2971 offset += 4;
2972 }
2973
2974 lp_build_endif(&inner_if_ctx);
2975
2976 /* Store the tessellation factors. */
2977 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2978 MIN2(stride, 4), byteoffset, tf_base,
2979 offset, 1, 0, true, false);
2980 offset += 16;
2981 if (vec1)
2982 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2983 stride - 4, byteoffset, tf_base,
2984 offset, 1, 0, true, false);
2985
2986 /* Store the tess factors into the offchip buffer if TES reads them. */
2987 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
2988 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
2989 LLVMValueRef tf_inner_offset;
2990 unsigned param_outer, param_inner;
2991
2992 buf = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
2993 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2994
2995 param_outer = si_shader_io_get_unique_index_patch(
2996 TGSI_SEMANTIC_TESSOUTER, 0);
2997 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2998 LLVMConstInt(ctx->i32, param_outer, 0));
2999
3000 outer_vec = lp_build_gather_values(&ctx->gallivm, outer,
3001 util_next_power_of_two(outer_comps));
3002
3003 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3004 outer_comps, tf_outer_offset,
3005 base, 0, 1, 0, true, false);
3006 if (inner_comps) {
3007 param_inner = si_shader_io_get_unique_index_patch(
3008 TGSI_SEMANTIC_TESSINNER, 0);
3009 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3010 LLVMConstInt(ctx->i32, param_inner, 0));
3011
3012 inner_vec = inner_comps == 1 ? inner[0] :
3013 lp_build_gather_values(&ctx->gallivm, inner, inner_comps);
3014 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3015 inner_comps, tf_inner_offset,
3016 base, 0, 1, 0, true, false);
3017 }
3018 }
3019
3020 lp_build_endif(&if_ctx);
3021 }
3022
3023 static LLVMValueRef
3024 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3025 unsigned param, unsigned return_index)
3026 {
3027 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3028 LLVMGetParam(ctx->main_fn, param),
3029 return_index, "");
3030 }
3031
3032 static LLVMValueRef
3033 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3034 unsigned param, unsigned return_index)
3035 {
3036 LLVMBuilderRef builder = ctx->ac.builder;
3037 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3038
3039 return LLVMBuildInsertValue(builder, ret,
3040 ac_to_float(&ctx->ac, p),
3041 return_index, "");
3042 }
3043
3044 static LLVMValueRef
3045 si_insert_input_ptr_as_2xi32(struct si_shader_context *ctx, LLVMValueRef ret,
3046 unsigned param, unsigned return_index)
3047 {
3048 LLVMBuilderRef builder = ctx->ac.builder;
3049 LLVMValueRef ptr, lo, hi;
3050
3051 ptr = LLVMGetParam(ctx->main_fn, param);
3052 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
3053 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
3054 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
3055 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
3056 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
3057 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
3058 }
3059
3060 /* This only writes the tessellation factor levels. */
3061 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
3062 {
3063 struct si_shader_context *ctx = si_shader_context(bld_base);
3064 LLVMBuilderRef builder = ctx->ac.builder;
3065 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3066
3067 si_copy_tcs_inputs(bld_base);
3068
3069 rel_patch_id = get_rel_patch_id(ctx);
3070 invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
3071 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3072
3073 if (ctx->screen->info.chip_class >= GFX9) {
3074 LLVMBasicBlockRef blocks[2] = {
3075 LLVMGetInsertBlock(builder),
3076 ctx->merged_wrap_if_state.entry_block
3077 };
3078 LLVMValueRef values[2];
3079
3080 lp_build_endif(&ctx->merged_wrap_if_state);
3081
3082 values[0] = rel_patch_id;
3083 values[1] = LLVMGetUndef(ctx->i32);
3084 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3085
3086 values[0] = tf_lds_offset;
3087 values[1] = LLVMGetUndef(ctx->i32);
3088 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3089
3090 values[0] = invocation_id;
3091 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3092 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3093 }
3094
3095 /* Return epilog parameters from this function. */
3096 LLVMValueRef ret = ctx->return_value;
3097 unsigned vgpr;
3098
3099 if (ctx->screen->info.chip_class >= GFX9) {
3100 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3101 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3102 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3103 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3104 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3105 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
3106 /* Tess offchip and tess factor offsets are at the beginning. */
3107 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3108 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3109 vgpr = 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K + 1;
3110 } else {
3111 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3112 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3113 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3114 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3115 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3116 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K);
3117 /* Tess offchip and tess factor offsets are after user SGPRs. */
3118 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3119 GFX6_TCS_NUM_USER_SGPR);
3120 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3121 GFX6_TCS_NUM_USER_SGPR + 1);
3122 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3123 }
3124
3125 /* VGPRs */
3126 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3127 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3128 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3129
3130 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3131 * the invocation_id output does not alias the param_tcs_rel_ids input,
3132 * which saves a V_MOV on gfx9.
3133 */
3134 vgpr += 2;
3135
3136 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3137 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3138
3139 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3140 vgpr++; /* skip the tess factor LDS offset */
3141 for (unsigned i = 0; i < 6; i++) {
3142 LLVMValueRef value =
3143 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3144 value = ac_to_float(&ctx->ac, value);
3145 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3146 }
3147 } else {
3148 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3149 }
3150 ctx->return_value = ret;
3151 }
3152
3153 /* Pass TCS inputs from LS to TCS on GFX9. */
3154 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3155 {
3156 LLVMValueRef ret = ctx->return_value;
3157
3158 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3159 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3160 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3161 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3162
3163 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
3164 8 + SI_SGPR_RW_BUFFERS);
3165 ret = si_insert_input_ptr_as_2xi32(ctx, ret,
3166 ctx->param_bindless_samplers_and_images,
3167 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3168
3169 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3170 8 + SI_SGPR_VS_STATE_BITS);
3171 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3172 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3173 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3174 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3175 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3176 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3177 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3178 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3179 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3180 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
3181
3182 unsigned desc_param = ctx->param_tcs_factor_addr_base64k + 2;
3183 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
3184 8 + GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS);
3185 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
3186 8 + GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES);
3187
3188 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3189 ret = si_insert_input_ret_float(ctx, ret,
3190 ctx->param_tcs_patch_id, vgpr++);
3191 ret = si_insert_input_ret_float(ctx, ret,
3192 ctx->param_tcs_rel_ids, vgpr++);
3193 ctx->return_value = ret;
3194 }
3195
3196 /* Pass GS inputs from ES to GS on GFX9. */
3197 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3198 {
3199 LLVMValueRef ret = ctx->return_value;
3200
3201 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3202 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3203 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3204
3205 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
3206 8 + SI_SGPR_RW_BUFFERS);
3207 ret = si_insert_input_ptr_as_2xi32(ctx, ret,
3208 ctx->param_bindless_samplers_and_images,
3209 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3210
3211 unsigned desc_param = ctx->param_vs_state_bits + 1;
3212 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
3213 8 + GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS);
3214 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
3215 8 + GFX9_SGPR_GS_SAMPLERS_AND_IMAGES);
3216
3217 unsigned vgpr = 8 + GFX9_GS_NUM_USER_SGPR;
3218 for (unsigned i = 0; i < 5; i++) {
3219 unsigned param = ctx->param_gs_vtx01_offset + i;
3220 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3221 }
3222 ctx->return_value = ret;
3223 }
3224
3225 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3226 unsigned max_outputs,
3227 LLVMValueRef *addrs)
3228 {
3229 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3230 struct si_shader *shader = ctx->shader;
3231 struct tgsi_shader_info *info = &shader->selector->info;
3232 unsigned i, chan;
3233 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3234 ctx->param_rel_auto_id);
3235 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3236 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3237 vertex_dw_stride, "");
3238
3239 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3240 * its inputs from it. */
3241 for (i = 0; i < info->num_outputs; i++) {
3242 unsigned name = info->output_semantic_name[i];
3243 unsigned index = info->output_semantic_index[i];
3244
3245 /* The ARB_shader_viewport_layer_array spec contains the
3246 * following issue:
3247 *
3248 * 2) What happens if gl_ViewportIndex or gl_Layer is
3249 * written in the vertex shader and a geometry shader is
3250 * present?
3251 *
3252 * RESOLVED: The value written by the last vertex processing
3253 * stage is used. If the last vertex processing stage
3254 * (vertex, tessellation evaluation or geometry) does not
3255 * statically assign to gl_ViewportIndex or gl_Layer, index
3256 * or layer zero is assumed.
3257 *
3258 * So writes to those outputs in VS-as-LS are simply ignored.
3259 */
3260 if (name == TGSI_SEMANTIC_LAYER ||
3261 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3262 continue;
3263
3264 int param = si_shader_io_get_unique_index(name, index);
3265 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3266 LLVMConstInt(ctx->i32, param * 4, 0), "");
3267
3268 for (chan = 0; chan < 4; chan++) {
3269 if (!(info->output_usagemask[i] & (1 << chan)))
3270 continue;
3271
3272 lds_store(ctx, chan, dw_addr,
3273 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3274 }
3275 }
3276
3277 if (ctx->screen->info.chip_class >= GFX9)
3278 si_set_ls_return_value_for_tcs(ctx);
3279 }
3280
3281 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3282 unsigned max_outputs,
3283 LLVMValueRef *addrs)
3284 {
3285 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3286 struct si_shader *es = ctx->shader;
3287 struct tgsi_shader_info *info = &es->selector->info;
3288 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3289 ctx->param_es2gs_offset);
3290 LLVMValueRef lds_base = NULL;
3291 unsigned chan;
3292 int i;
3293
3294 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3295 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3296 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3297 LLVMValueRef wave_idx = unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3298 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3299 LLVMBuildMul(ctx->ac.builder, wave_idx,
3300 LLVMConstInt(ctx->i32, 64, false), ""), "");
3301 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3302 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3303 }
3304
3305 for (i = 0; i < info->num_outputs; i++) {
3306 int param;
3307
3308 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3309 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3310 continue;
3311
3312 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3313 info->output_semantic_index[i]);
3314
3315 for (chan = 0; chan < 4; chan++) {
3316 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3317 out_val = ac_to_integer(&ctx->ac, out_val);
3318
3319 /* GFX9 has the ESGS ring in LDS. */
3320 if (ctx->screen->info.chip_class >= GFX9) {
3321 lds_store(ctx, param * 4 + chan, lds_base, out_val);
3322 continue;
3323 }
3324
3325 ac_build_buffer_store_dword(&ctx->ac,
3326 ctx->esgs_ring,
3327 out_val, 1, NULL, soffset,
3328 (4 * param + chan) * 4,
3329 1, 1, true, true);
3330 }
3331 }
3332
3333 if (ctx->screen->info.chip_class >= GFX9)
3334 si_set_es_return_value_for_gs(ctx);
3335 }
3336
3337 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3338 {
3339 if (ctx->screen->info.chip_class >= GFX9)
3340 return unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3341 else
3342 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3343 }
3344
3345 static void emit_gs_epilogue(struct si_shader_context *ctx)
3346 {
3347 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3348 si_get_gs_wave_id(ctx));
3349
3350 if (ctx->screen->info.chip_class >= GFX9)
3351 lp_build_endif(&ctx->merged_wrap_if_state);
3352 }
3353
3354 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3355 unsigned max_outputs,
3356 LLVMValueRef *addrs)
3357 {
3358 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3359 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3360
3361 assert(info->num_outputs <= max_outputs);
3362
3363 emit_gs_epilogue(ctx);
3364 }
3365
3366 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3367 {
3368 struct si_shader_context *ctx = si_shader_context(bld_base);
3369 emit_gs_epilogue(ctx);
3370 }
3371
3372 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3373 unsigned max_outputs,
3374 LLVMValueRef *addrs)
3375 {
3376 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3377 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3378 struct si_shader_output_values *outputs = NULL;
3379 int i,j;
3380
3381 assert(!ctx->shader->is_gs_copy_shader);
3382 assert(info->num_outputs <= max_outputs);
3383
3384 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3385
3386 /* Vertex color clamping.
3387 *
3388 * This uses a state constant loaded in a user data SGPR and
3389 * an IF statement is added that clamps all colors if the constant
3390 * is true.
3391 */
3392 if (ctx->type == PIPE_SHADER_VERTEX) {
3393 struct lp_build_if_state if_ctx;
3394 LLVMValueRef cond = NULL;
3395 LLVMValueRef addr, val;
3396
3397 for (i = 0; i < info->num_outputs; i++) {
3398 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3399 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3400 continue;
3401
3402 /* We've found a color. */
3403 if (!cond) {
3404 /* The state is in the first bit of the user SGPR. */
3405 cond = LLVMGetParam(ctx->main_fn,
3406 ctx->param_vs_state_bits);
3407 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3408 ctx->i1, "");
3409 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3410 }
3411
3412 for (j = 0; j < 4; j++) {
3413 addr = addrs[4 * i + j];
3414 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3415 val = ac_build_clamp(&ctx->ac, val);
3416 LLVMBuildStore(ctx->ac.builder, val, addr);
3417 }
3418 }
3419
3420 if (cond)
3421 lp_build_endif(&if_ctx);
3422 }
3423
3424 for (i = 0; i < info->num_outputs; i++) {
3425 outputs[i].semantic_name = info->output_semantic_name[i];
3426 outputs[i].semantic_index = info->output_semantic_index[i];
3427
3428 for (j = 0; j < 4; j++) {
3429 outputs[i].values[j] =
3430 LLVMBuildLoad(ctx->ac.builder,
3431 addrs[4 * i + j],
3432 "");
3433 outputs[i].vertex_stream[j] =
3434 (info->output_streams[i] >> (2 * j)) & 3;
3435 }
3436 }
3437
3438 if (ctx->shader->selector->so.num_outputs)
3439 si_llvm_emit_streamout(ctx, outputs, i, 0);
3440
3441 /* Export PrimitiveID. */
3442 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3443 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3444 outputs[i].semantic_index = 0;
3445 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3446 for (j = 1; j < 4; j++)
3447 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3448
3449 memset(outputs[i].vertex_stream, 0,
3450 sizeof(outputs[i].vertex_stream));
3451 i++;
3452 }
3453
3454 si_llvm_export_vs(ctx, outputs, i);
3455 FREE(outputs);
3456 }
3457
3458 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3459 {
3460 struct si_shader_context *ctx = si_shader_context(bld_base);
3461
3462 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3463 &ctx->outputs[0][0]);
3464 }
3465
3466 struct si_ps_exports {
3467 unsigned num;
3468 struct ac_export_args args[10];
3469 };
3470
3471 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3472 LLVMValueRef depth, LLVMValueRef stencil,
3473 LLVMValueRef samplemask, struct si_ps_exports *exp)
3474 {
3475 struct si_shader_context *ctx = si_shader_context(bld_base);
3476 struct ac_export_args args;
3477
3478 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3479
3480 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3481 }
3482
3483 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3484 LLVMValueRef *color, unsigned index,
3485 unsigned samplemask_param,
3486 bool is_last, struct si_ps_exports *exp)
3487 {
3488 struct si_shader_context *ctx = si_shader_context(bld_base);
3489 int i;
3490
3491 /* Clamp color */
3492 if (ctx->shader->key.part.ps.epilog.clamp_color)
3493 for (i = 0; i < 4; i++)
3494 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3495
3496 /* Alpha to one */
3497 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3498 color[3] = ctx->ac.f32_1;
3499
3500 /* Alpha test */
3501 if (index == 0 &&
3502 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3503 si_alpha_test(bld_base, color[3]);
3504
3505 /* Line & polygon smoothing */
3506 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3507 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3508 samplemask_param);
3509
3510 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3511 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3512 struct ac_export_args args[8];
3513 int c, last = -1;
3514
3515 /* Get the export arguments, also find out what the last one is. */
3516 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3517 si_llvm_init_export_args(ctx, color,
3518 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3519 if (args[c].enabled_channels)
3520 last = c;
3521 }
3522
3523 /* Emit all exports. */
3524 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3525 if (is_last && last == c) {
3526 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3527 args[c].done = 1; /* DONE bit */
3528 } else if (!args[c].enabled_channels)
3529 continue; /* unnecessary NULL export */
3530
3531 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3532 }
3533 } else {
3534 struct ac_export_args args;
3535
3536 /* Export */
3537 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3538 &args);
3539 if (is_last) {
3540 args.valid_mask = 1; /* whether the EXEC mask is valid */
3541 args.done = 1; /* DONE bit */
3542 } else if (!args.enabled_channels)
3543 return; /* unnecessary NULL export */
3544
3545 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3546 }
3547 }
3548
3549 static void si_emit_ps_exports(struct si_shader_context *ctx,
3550 struct si_ps_exports *exp)
3551 {
3552 for (unsigned i = 0; i < exp->num; i++)
3553 ac_build_export(&ctx->ac, &exp->args[i]);
3554 }
3555
3556 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3557 {
3558 struct si_shader_context *ctx = si_shader_context(bld_base);
3559 struct lp_build_context *base = &bld_base->base;
3560 struct ac_export_args args;
3561
3562 args.enabled_channels = 0x0; /* enabled channels */
3563 args.valid_mask = 1; /* whether the EXEC mask is valid */
3564 args.done = 1; /* DONE bit */
3565 args.target = V_008DFC_SQ_EXP_NULL;
3566 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
3567 args.out[0] = base->undef; /* R */
3568 args.out[1] = base->undef; /* G */
3569 args.out[2] = base->undef; /* B */
3570 args.out[3] = base->undef; /* A */
3571
3572 ac_build_export(&ctx->ac, &args);
3573 }
3574
3575 /**
3576 * Return PS outputs in this order:
3577 *
3578 * v[0:3] = color0.xyzw
3579 * v[4:7] = color1.xyzw
3580 * ...
3581 * vN+0 = Depth
3582 * vN+1 = Stencil
3583 * vN+2 = SampleMask
3584 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3585 *
3586 * The alpha-ref SGPR is returned via its original location.
3587 */
3588 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3589 unsigned max_outputs,
3590 LLVMValueRef *addrs)
3591 {
3592 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3593 struct si_shader *shader = ctx->shader;
3594 struct tgsi_shader_info *info = &shader->selector->info;
3595 LLVMBuilderRef builder = ctx->ac.builder;
3596 unsigned i, j, first_vgpr, vgpr;
3597
3598 LLVMValueRef color[8][4] = {};
3599 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3600 LLVMValueRef ret;
3601
3602 if (ctx->postponed_kill)
3603 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3604
3605 /* Read the output values. */
3606 for (i = 0; i < info->num_outputs; i++) {
3607 unsigned semantic_name = info->output_semantic_name[i];
3608 unsigned semantic_index = info->output_semantic_index[i];
3609
3610 switch (semantic_name) {
3611 case TGSI_SEMANTIC_COLOR:
3612 assert(semantic_index < 8);
3613 for (j = 0; j < 4; j++) {
3614 LLVMValueRef ptr = addrs[4 * i + j];
3615 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3616 color[semantic_index][j] = result;
3617 }
3618 break;
3619 case TGSI_SEMANTIC_POSITION:
3620 depth = LLVMBuildLoad(builder,
3621 addrs[4 * i + 2], "");
3622 break;
3623 case TGSI_SEMANTIC_STENCIL:
3624 stencil = LLVMBuildLoad(builder,
3625 addrs[4 * i + 1], "");
3626 break;
3627 case TGSI_SEMANTIC_SAMPLEMASK:
3628 samplemask = LLVMBuildLoad(builder,
3629 addrs[4 * i + 0], "");
3630 break;
3631 default:
3632 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3633 semantic_name);
3634 }
3635 }
3636
3637 /* Fill the return structure. */
3638 ret = ctx->return_value;
3639
3640 /* Set SGPRs. */
3641 ret = LLVMBuildInsertValue(builder, ret,
3642 ac_to_integer(&ctx->ac,
3643 LLVMGetParam(ctx->main_fn,
3644 SI_PARAM_ALPHA_REF)),
3645 SI_SGPR_ALPHA_REF, "");
3646
3647 /* Set VGPRs */
3648 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3649 for (i = 0; i < ARRAY_SIZE(color); i++) {
3650 if (!color[i][0])
3651 continue;
3652
3653 for (j = 0; j < 4; j++)
3654 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3655 }
3656 if (depth)
3657 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3658 if (stencil)
3659 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3660 if (samplemask)
3661 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3662
3663 /* Add the input sample mask for smoothing at the end. */
3664 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3665 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3666 ret = LLVMBuildInsertValue(builder, ret,
3667 LLVMGetParam(ctx->main_fn,
3668 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3669
3670 ctx->return_value = ret;
3671 }
3672
3673 static void membar_emit(
3674 const struct lp_build_tgsi_action *action,
3675 struct lp_build_tgsi_context *bld_base,
3676 struct lp_build_emit_data *emit_data)
3677 {
3678 struct si_shader_context *ctx = si_shader_context(bld_base);
3679 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3680 unsigned flags = LLVMConstIntGetZExtValue(src0);
3681 unsigned waitcnt = NOOP_WAITCNT;
3682
3683 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3684 waitcnt &= VM_CNT & LGKM_CNT;
3685
3686 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3687 TGSI_MEMBAR_SHADER_BUFFER |
3688 TGSI_MEMBAR_SHADER_IMAGE))
3689 waitcnt &= VM_CNT;
3690
3691 if (flags & TGSI_MEMBAR_SHARED)
3692 waitcnt &= LGKM_CNT;
3693
3694 if (waitcnt != NOOP_WAITCNT)
3695 ac_build_waitcnt(&ctx->ac, waitcnt);
3696 }
3697
3698 static void clock_emit(
3699 const struct lp_build_tgsi_action *action,
3700 struct lp_build_tgsi_context *bld_base,
3701 struct lp_build_emit_data *emit_data)
3702 {
3703 struct si_shader_context *ctx = si_shader_context(bld_base);
3704 LLVMValueRef tmp;
3705
3706 tmp = lp_build_intrinsic(ctx->ac.builder, "llvm.readcyclecounter",
3707 ctx->i64, NULL, 0, 0);
3708 tmp = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->v2i32, "");
3709
3710 emit_data->output[0] =
3711 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3712 emit_data->output[1] =
3713 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3714 }
3715
3716 LLVMTypeRef si_const_array(LLVMTypeRef elem_type, int num_elements)
3717 {
3718 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3719 CONST_ADDR_SPACE);
3720 }
3721
3722 static void si_llvm_emit_ddxy(
3723 const struct lp_build_tgsi_action *action,
3724 struct lp_build_tgsi_context *bld_base,
3725 struct lp_build_emit_data *emit_data)
3726 {
3727 struct si_shader_context *ctx = si_shader_context(bld_base);
3728 unsigned opcode = emit_data->info->opcode;
3729 LLVMValueRef val;
3730 int idx;
3731 unsigned mask;
3732
3733 if (opcode == TGSI_OPCODE_DDX_FINE)
3734 mask = AC_TID_MASK_LEFT;
3735 else if (opcode == TGSI_OPCODE_DDY_FINE)
3736 mask = AC_TID_MASK_TOP;
3737 else
3738 mask = AC_TID_MASK_TOP_LEFT;
3739
3740 /* for DDX we want to next X pixel, DDY next Y pixel. */
3741 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3742
3743 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3744 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3745 emit_data->output[emit_data->chan] = val;
3746 }
3747
3748 /*
3749 * this takes an I,J coordinate pair,
3750 * and works out the X and Y derivatives.
3751 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3752 */
3753 static LLVMValueRef si_llvm_emit_ddxy_interp(
3754 struct lp_build_tgsi_context *bld_base,
3755 LLVMValueRef interp_ij)
3756 {
3757 struct si_shader_context *ctx = si_shader_context(bld_base);
3758 LLVMValueRef result[4], a;
3759 unsigned i;
3760
3761 for (i = 0; i < 2; i++) {
3762 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
3763 LLVMConstInt(ctx->i32, i, 0), "");
3764 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
3765 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
3766 }
3767
3768 return lp_build_gather_values(&ctx->gallivm, result, 4);
3769 }
3770
3771 static void interp_fetch_args(
3772 struct lp_build_tgsi_context *bld_base,
3773 struct lp_build_emit_data *emit_data)
3774 {
3775 struct si_shader_context *ctx = si_shader_context(bld_base);
3776 const struct tgsi_full_instruction *inst = emit_data->inst;
3777
3778 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3779 /* offset is in second src, first two channels */
3780 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3781 emit_data->inst, 1,
3782 TGSI_CHAN_X);
3783 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3784 emit_data->inst, 1,
3785 TGSI_CHAN_Y);
3786 emit_data->arg_count = 2;
3787 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3788 LLVMValueRef sample_position;
3789 LLVMValueRef sample_id;
3790 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3791
3792 /* fetch sample ID, then fetch its sample position,
3793 * and place into first two channels.
3794 */
3795 sample_id = lp_build_emit_fetch(bld_base,
3796 emit_data->inst, 1, TGSI_CHAN_X);
3797 sample_id = ac_to_integer(&ctx->ac, sample_id);
3798
3799 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
3800 * Language 4.50 spec says about interpolateAtSample:
3801 *
3802 * "Returns the value of the input interpolant variable at
3803 * the location of sample number sample. If multisample
3804 * buffers are not available, the input variable will be
3805 * evaluated at the center of the pixel. If sample sample
3806 * does not exist, the position used to interpolate the
3807 * input variable is undefined."
3808 *
3809 * This means that sample_id values outside of the valid are
3810 * in fact valid input, and the usual mechanism for loading the
3811 * sample position doesn't work.
3812 */
3813 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
3814 LLVMValueRef center[4] = {
3815 LLVMConstReal(ctx->f32, 0.5),
3816 LLVMConstReal(ctx->f32, 0.5),
3817 ctx->ac.f32_0,
3818 ctx->ac.f32_0,
3819 };
3820
3821 sample_position = lp_build_gather_values(&ctx->gallivm, center, 4);
3822 } else {
3823 sample_position = load_sample_position(ctx, sample_id);
3824 }
3825
3826 emit_data->args[0] = LLVMBuildExtractElement(ctx->ac.builder,
3827 sample_position,
3828 ctx->i32_0, "");
3829
3830 emit_data->args[0] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[0], halfval, "");
3831 emit_data->args[1] = LLVMBuildExtractElement(ctx->ac.builder,
3832 sample_position,
3833 ctx->i32_1, "");
3834 emit_data->args[1] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[1], halfval, "");
3835 emit_data->arg_count = 2;
3836 }
3837 }
3838
3839 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3840 struct lp_build_tgsi_context *bld_base,
3841 struct lp_build_emit_data *emit_data)
3842 {
3843 struct si_shader_context *ctx = si_shader_context(bld_base);
3844 struct si_shader *shader = ctx->shader;
3845 const struct tgsi_shader_info *info = &shader->selector->info;
3846 LLVMValueRef interp_param;
3847 const struct tgsi_full_instruction *inst = emit_data->inst;
3848 const struct tgsi_full_src_register *input = &inst->Src[0];
3849 int input_base, input_array_size;
3850 int chan;
3851 int i;
3852 LLVMValueRef prim_mask = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
3853 LLVMValueRef array_idx;
3854 int interp_param_idx;
3855 unsigned interp;
3856 unsigned location;
3857
3858 assert(input->Register.File == TGSI_FILE_INPUT);
3859
3860 if (input->Register.Indirect) {
3861 unsigned array_id = input->Indirect.ArrayID;
3862
3863 if (array_id) {
3864 input_base = info->input_array_first[array_id];
3865 input_array_size = info->input_array_last[array_id] - input_base + 1;
3866 } else {
3867 input_base = inst->Src[0].Register.Index;
3868 input_array_size = info->num_inputs - input_base;
3869 }
3870
3871 array_idx = si_get_indirect_index(ctx, &input->Indirect,
3872 1, input->Register.Index - input_base);
3873 } else {
3874 input_base = inst->Src[0].Register.Index;
3875 input_array_size = 1;
3876 array_idx = ctx->i32_0;
3877 }
3878
3879 interp = shader->selector->info.input_interpolate[input_base];
3880
3881 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3882 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3883 location = TGSI_INTERPOLATE_LOC_CENTER;
3884 else
3885 location = TGSI_INTERPOLATE_LOC_CENTROID;
3886
3887 interp_param_idx = lookup_interp_param_index(interp, location);
3888 if (interp_param_idx == -1)
3889 return;
3890 else if (interp_param_idx)
3891 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
3892 else
3893 interp_param = NULL;
3894
3895 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3896 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3897 LLVMValueRef ij_out[2];
3898 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3899
3900 /*
3901 * take the I then J parameters, and the DDX/Y for it, and
3902 * calculate the IJ inputs for the interpolator.
3903 * temp1 = ddx * offset/sample.x + I;
3904 * interp_param.I = ddy * offset/sample.y + temp1;
3905 * temp1 = ddx * offset/sample.x + J;
3906 * interp_param.J = ddy * offset/sample.y + temp1;
3907 */
3908 for (i = 0; i < 2; i++) {
3909 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
3910 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
3911 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
3912 ddxy_out, ix_ll, "");
3913 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
3914 ddxy_out, iy_ll, "");
3915 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
3916 interp_param, ix_ll, "");
3917 LLVMValueRef temp1, temp2;
3918
3919 interp_el = ac_to_float(&ctx->ac, interp_el);
3920
3921 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, emit_data->args[0], "");
3922
3923 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
3924
3925 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, emit_data->args[1], "");
3926
3927 ij_out[i] = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
3928 }
3929 interp_param = lp_build_gather_values(&ctx->gallivm, ij_out, 2);
3930 }
3931
3932 if (interp_param)
3933 interp_param = ac_to_float(&ctx->ac, interp_param);
3934
3935 for (chan = 0; chan < 4; chan++) {
3936 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
3937 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3938
3939 for (unsigned idx = 0; idx < input_array_size; ++idx) {
3940 LLVMValueRef v, i = NULL, j = NULL;
3941
3942 if (interp_param) {
3943 i = LLVMBuildExtractElement(
3944 ctx->ac.builder, interp_param, ctx->i32_0, "");
3945 j = LLVMBuildExtractElement(
3946 ctx->ac.builder, interp_param, ctx->i32_1, "");
3947 }
3948 v = si_build_fs_interp(ctx, input_base + idx, schan,
3949 prim_mask, i, j);
3950
3951 gather = LLVMBuildInsertElement(ctx->ac.builder,
3952 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
3953 }
3954
3955 emit_data->output[chan] = LLVMBuildExtractElement(
3956 ctx->ac.builder, gather, array_idx, "");
3957 }
3958 }
3959
3960 static void vote_all_emit(
3961 const struct lp_build_tgsi_action *action,
3962 struct lp_build_tgsi_context *bld_base,
3963 struct lp_build_emit_data *emit_data)
3964 {
3965 struct si_shader_context *ctx = si_shader_context(bld_base);
3966
3967 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
3968 emit_data->output[emit_data->chan] =
3969 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
3970 }
3971
3972 static void vote_any_emit(
3973 const struct lp_build_tgsi_action *action,
3974 struct lp_build_tgsi_context *bld_base,
3975 struct lp_build_emit_data *emit_data)
3976 {
3977 struct si_shader_context *ctx = si_shader_context(bld_base);
3978
3979 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
3980 emit_data->output[emit_data->chan] =
3981 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
3982 }
3983
3984 static void vote_eq_emit(
3985 const struct lp_build_tgsi_action *action,
3986 struct lp_build_tgsi_context *bld_base,
3987 struct lp_build_emit_data *emit_data)
3988 {
3989 struct si_shader_context *ctx = si_shader_context(bld_base);
3990
3991 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
3992 emit_data->output[emit_data->chan] =
3993 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
3994 }
3995
3996 static void ballot_emit(
3997 const struct lp_build_tgsi_action *action,
3998 struct lp_build_tgsi_context *bld_base,
3999 struct lp_build_emit_data *emit_data)
4000 {
4001 struct si_shader_context *ctx = si_shader_context(bld_base);
4002 LLVMBuilderRef builder = ctx->ac.builder;
4003 LLVMValueRef tmp;
4004
4005 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4006 tmp = ac_build_ballot(&ctx->ac, tmp);
4007 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4008
4009 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4010 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4011 }
4012
4013 static void read_invoc_fetch_args(
4014 struct lp_build_tgsi_context *bld_base,
4015 struct lp_build_emit_data *emit_data)
4016 {
4017 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4018 0, emit_data->src_chan);
4019
4020 /* Always read the source invocation (= lane) from the X channel. */
4021 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4022 1, TGSI_CHAN_X);
4023 emit_data->arg_count = 2;
4024 }
4025
4026 static void read_lane_emit(
4027 const struct lp_build_tgsi_action *action,
4028 struct lp_build_tgsi_context *bld_base,
4029 struct lp_build_emit_data *emit_data)
4030 {
4031 struct si_shader_context *ctx = si_shader_context(bld_base);
4032
4033 /* We currently have no other way to prevent LLVM from lifting the icmp
4034 * calls to a dominating basic block.
4035 */
4036 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4037
4038 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4039 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4040
4041 emit_data->output[emit_data->chan] =
4042 ac_build_intrinsic(&ctx->ac, action->intr_name,
4043 ctx->i32, emit_data->args, emit_data->arg_count,
4044 AC_FUNC_ATTR_READNONE |
4045 AC_FUNC_ATTR_CONVERGENT);
4046 }
4047
4048 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4049 struct lp_build_emit_data *emit_data)
4050 {
4051 struct si_shader_context *ctx = si_shader_context(bld_base);
4052 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4053 LLVMValueRef imm;
4054 unsigned stream;
4055
4056 assert(src0.File == TGSI_FILE_IMMEDIATE);
4057
4058 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4059 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4060 return stream;
4061 }
4062
4063 /* Emit one vertex from the geometry shader */
4064 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4065 unsigned stream,
4066 LLVMValueRef *addrs)
4067 {
4068 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4069 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4070 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
4071 struct si_shader *shader = ctx->shader;
4072 struct lp_build_if_state if_state;
4073 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4074 ctx->param_gs2vs_offset);
4075 LLVMValueRef gs_next_vertex;
4076 LLVMValueRef can_emit;
4077 unsigned chan, offset;
4078 int i;
4079
4080 /* Write vertex attribute values to GSVS ring */
4081 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4082 ctx->gs_next_vertex[stream],
4083 "");
4084
4085 /* If this thread has already emitted the declared maximum number of
4086 * vertices, skip the write: excessive vertex emissions are not
4087 * supposed to have any effect.
4088 *
4089 * If the shader has no writes to memory, kill it instead. This skips
4090 * further memory loads and may allow LLVM to skip to the end
4091 * altogether.
4092 */
4093 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4094 LLVMConstInt(ctx->i32,
4095 shader->selector->gs_max_out_vertices, 0), "");
4096
4097 bool use_kill = !info->writes_memory;
4098 if (use_kill) {
4099 ac_build_kill_if_false(&ctx->ac, can_emit);
4100 } else {
4101 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4102 }
4103
4104 offset = 0;
4105 for (i = 0; i < info->num_outputs; i++) {
4106 for (chan = 0; chan < 4; chan++) {
4107 if (!(info->output_usagemask[i] & (1 << chan)) ||
4108 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4109 continue;
4110
4111 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4112 LLVMValueRef voffset =
4113 LLVMConstInt(ctx->i32, offset *
4114 shader->selector->gs_max_out_vertices, 0);
4115 offset++;
4116
4117 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4118 voffset = lp_build_mul_imm(uint, voffset, 4);
4119
4120 out_val = ac_to_integer(&ctx->ac, out_val);
4121
4122 ac_build_buffer_store_dword(&ctx->ac,
4123 ctx->gsvs_ring[stream],
4124 out_val, 1,
4125 voffset, soffset, 0,
4126 1, 1, true, true);
4127 }
4128 }
4129
4130 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4131 ctx->i32_1);
4132
4133 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4134
4135 /* Signal vertex emission */
4136 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4137 si_get_gs_wave_id(ctx));
4138 if (!use_kill)
4139 lp_build_endif(&if_state);
4140 }
4141
4142 /* Emit one vertex from the geometry shader */
4143 static void si_tgsi_emit_vertex(
4144 const struct lp_build_tgsi_action *action,
4145 struct lp_build_tgsi_context *bld_base,
4146 struct lp_build_emit_data *emit_data)
4147 {
4148 struct si_shader_context *ctx = si_shader_context(bld_base);
4149 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4150
4151 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4152 }
4153
4154 /* Cut one primitive from the geometry shader */
4155 static void si_llvm_emit_primitive(
4156 const struct lp_build_tgsi_action *action,
4157 struct lp_build_tgsi_context *bld_base,
4158 struct lp_build_emit_data *emit_data)
4159 {
4160 struct si_shader_context *ctx = si_shader_context(bld_base);
4161 unsigned stream;
4162
4163 /* Signal primitive cut */
4164 stream = si_llvm_get_stream(bld_base, emit_data);
4165 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4166 si_get_gs_wave_id(ctx));
4167 }
4168
4169 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4170 struct lp_build_tgsi_context *bld_base,
4171 struct lp_build_emit_data *emit_data)
4172 {
4173 struct si_shader_context *ctx = si_shader_context(bld_base);
4174
4175 /* SI only (thanks to a hw bug workaround):
4176 * The real barrier instruction isn’t needed, because an entire patch
4177 * always fits into a single wave.
4178 */
4179 if (ctx->screen->info.chip_class == SI &&
4180 ctx->type == PIPE_SHADER_TESS_CTRL) {
4181 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
4182 return;
4183 }
4184
4185 lp_build_intrinsic(ctx->ac.builder,
4186 "llvm.amdgcn.s.barrier",
4187 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
4188 }
4189
4190 static const struct lp_build_tgsi_action interp_action = {
4191 .fetch_args = interp_fetch_args,
4192 .emit = build_interp_intrinsic,
4193 };
4194
4195 static void si_create_function(struct si_shader_context *ctx,
4196 const char *name,
4197 LLVMTypeRef *returns, unsigned num_returns,
4198 struct si_function_info *fninfo,
4199 unsigned max_workgroup_size)
4200 {
4201 int i;
4202
4203 si_llvm_create_func(ctx, name, returns, num_returns,
4204 fninfo->types, fninfo->num_params);
4205 ctx->return_value = LLVMGetUndef(ctx->return_type);
4206
4207 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4208 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4209
4210 /* The combination of:
4211 * - ByVal
4212 * - dereferenceable
4213 * - invariant.load
4214 * allows the optimization passes to move loads and reduces
4215 * SGPR spilling significantly.
4216 */
4217 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4218 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
4219 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
4220 ac_add_attr_dereferenceable(P, UINT64_MAX);
4221 } else
4222 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
4223 }
4224
4225 for (i = 0; i < fninfo->num_params; ++i) {
4226 if (fninfo->assign[i])
4227 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4228 }
4229
4230 if (max_workgroup_size) {
4231 si_llvm_add_attribute(ctx->main_fn, "amdgpu-max-work-group-size",
4232 max_workgroup_size);
4233 }
4234 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4235 "no-signed-zeros-fp-math",
4236 "true");
4237
4238 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4239 /* These were copied from some LLVM test. */
4240 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4241 "less-precise-fpmad",
4242 "true");
4243 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4244 "no-infs-fp-math",
4245 "true");
4246 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4247 "no-nans-fp-math",
4248 "true");
4249 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4250 "unsafe-fp-math",
4251 "true");
4252 }
4253 }
4254
4255 static void declare_streamout_params(struct si_shader_context *ctx,
4256 struct pipe_stream_output_info *so,
4257 struct si_function_info *fninfo)
4258 {
4259 int i;
4260
4261 /* Streamout SGPRs. */
4262 if (so->num_outputs) {
4263 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4264 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4265 else
4266 ctx->param_streamout_config = fninfo->num_params - 1;
4267
4268 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4269 }
4270 /* A streamout buffer offset is loaded if the stride is non-zero. */
4271 for (i = 0; i < 4; i++) {
4272 if (!so->stride[i])
4273 continue;
4274
4275 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4276 }
4277 }
4278
4279 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4280 {
4281 switch (shader->selector->type) {
4282 case PIPE_SHADER_TESS_CTRL:
4283 /* Return this so that LLVM doesn't remove s_barrier
4284 * instructions on chips where we use s_barrier. */
4285 return shader->selector->screen->info.chip_class >= CIK ? 128 : 64;
4286
4287 case PIPE_SHADER_GEOMETRY:
4288 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4289
4290 case PIPE_SHADER_COMPUTE:
4291 break; /* see below */
4292
4293 default:
4294 return 0;
4295 }
4296
4297 const unsigned *properties = shader->selector->info.properties;
4298 unsigned max_work_group_size =
4299 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4300 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4301 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4302
4303 if (!max_work_group_size) {
4304 /* This is a variable group size compute shader,
4305 * compile it for the maximum possible group size.
4306 */
4307 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4308 }
4309 return max_work_group_size;
4310 }
4311
4312 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4313 struct si_function_info *fninfo,
4314 bool assign_params)
4315 {
4316 LLVMTypeRef const_shader_buf_type;
4317
4318 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4319 ctx->shader->selector->info.shader_buffers_declared == 0)
4320 const_shader_buf_type = ctx->f32;
4321 else
4322 const_shader_buf_type = ctx->v4i32;
4323
4324 unsigned const_and_shader_buffers =
4325 add_arg(fninfo, ARG_SGPR,
4326 si_const_array(const_shader_buf_type, 0));
4327
4328 unsigned samplers_and_images =
4329 add_arg(fninfo, ARG_SGPR,
4330 si_const_array(ctx->v8i32,
4331 SI_NUM_IMAGES + SI_NUM_SAMPLERS * 2));
4332
4333 if (assign_params) {
4334 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4335 ctx->param_samplers_and_images = samplers_and_images;
4336 }
4337 }
4338
4339 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4340 struct si_function_info *fninfo)
4341 {
4342 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4343 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS));
4344 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4345 si_const_array(ctx->v8i32, 0));
4346 }
4347
4348 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4349 struct si_function_info *fninfo)
4350 {
4351 ctx->param_vertex_buffers = add_arg(fninfo, ARG_SGPR,
4352 si_const_array(ctx->v4i32, SI_NUM_VERTEX_BUFFERS));
4353 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4354 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4355 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4356 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4357 }
4358
4359 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4360 struct si_function_info *fninfo,
4361 unsigned *num_prolog_vgprs)
4362 {
4363 struct si_shader *shader = ctx->shader;
4364
4365 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4366 if (shader->key.as_ls) {
4367 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4368 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4369 } else {
4370 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4371 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4372 }
4373 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4374
4375 if (!shader->is_gs_copy_shader) {
4376 /* Vertex load indices. */
4377 ctx->param_vertex_index0 = fninfo->num_params;
4378 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4379 add_arg(fninfo, ARG_VGPR, ctx->i32);
4380 *num_prolog_vgprs += shader->selector->info.num_inputs;
4381 }
4382 }
4383
4384 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4385 struct si_function_info *fninfo)
4386 {
4387 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4388 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4389 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4390 ctx->param_tes_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4391 }
4392
4393 enum {
4394 /* Convenient merged shader definitions. */
4395 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4396 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4397 };
4398
4399 static void create_function(struct si_shader_context *ctx)
4400 {
4401 struct si_shader *shader = ctx->shader;
4402 struct si_function_info fninfo;
4403 LLVMTypeRef returns[16+32*4];
4404 unsigned i, num_return_sgprs;
4405 unsigned num_returns = 0;
4406 unsigned num_prolog_vgprs = 0;
4407 unsigned type = ctx->type;
4408 unsigned vs_blit_property =
4409 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4410
4411 si_init_function_info(&fninfo);
4412
4413 /* Set MERGED shaders. */
4414 if (ctx->screen->info.chip_class >= GFX9) {
4415 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4416 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4417 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4418 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4419 }
4420
4421 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4422
4423 switch (type) {
4424 case PIPE_SHADER_VERTEX:
4425 declare_global_desc_pointers(ctx, &fninfo);
4426
4427 if (vs_blit_property) {
4428 ctx->param_vs_blit_inputs = fninfo.num_params;
4429 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4430 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4431 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* depth */
4432
4433 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4434 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color0 */
4435 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color1 */
4436 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color2 */
4437 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color3 */
4438 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4439 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4440 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4441 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4442 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4443 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4444 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4445 }
4446
4447 /* VGPRs */
4448 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4449 break;
4450 }
4451
4452 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4453 declare_vs_specific_input_sgprs(ctx, &fninfo);
4454
4455 if (shader->key.as_es) {
4456 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4457 } else if (shader->key.as_ls) {
4458 /* no extra parameters */
4459 } else {
4460 if (shader->is_gs_copy_shader) {
4461 fninfo.num_params = ctx->param_rw_buffers + 1;
4462 fninfo.num_sgpr_params = fninfo.num_params;
4463 }
4464
4465 /* The locations of the other parameters are assigned dynamically. */
4466 declare_streamout_params(ctx, &shader->selector->so,
4467 &fninfo);
4468 }
4469
4470 /* VGPRs */
4471 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4472 break;
4473
4474 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4475 declare_global_desc_pointers(ctx, &fninfo);
4476 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4477 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4478 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4479 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4480 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4481 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4482 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4483 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4484 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4485
4486 /* VGPRs */
4487 ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4488 ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4489
4490 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4491 * placed after the user SGPRs.
4492 */
4493 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4494 returns[num_returns++] = ctx->i32; /* SGPRs */
4495 for (i = 0; i < 11; i++)
4496 returns[num_returns++] = ctx->f32; /* VGPRs */
4497 break;
4498
4499 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4500 /* Merged stages have 8 system SGPRs at the beginning. */
4501 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_LO_HS */
4502 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_HI_HS */
4503 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4504 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4505 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4506 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4507 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4508 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4509
4510 declare_global_desc_pointers(ctx, &fninfo);
4511 declare_per_stage_desc_pointers(ctx, &fninfo,
4512 ctx->type == PIPE_SHADER_VERTEX);
4513 declare_vs_specific_input_sgprs(ctx, &fninfo);
4514
4515 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4516 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4517 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4518 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4519 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4520 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4521
4522 declare_per_stage_desc_pointers(ctx, &fninfo,
4523 ctx->type == PIPE_SHADER_TESS_CTRL);
4524
4525 /* VGPRs (first TCS, then VS) */
4526 ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4527 ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4528
4529 if (ctx->type == PIPE_SHADER_VERTEX) {
4530 declare_vs_input_vgprs(ctx, &fninfo,
4531 &num_prolog_vgprs);
4532
4533 /* LS return values are inputs to the TCS main shader part. */
4534 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4535 returns[num_returns++] = ctx->i32; /* SGPRs */
4536 for (i = 0; i < 2; i++)
4537 returns[num_returns++] = ctx->f32; /* VGPRs */
4538 } else {
4539 /* TCS return values are inputs to the TCS epilog.
4540 *
4541 * param_tcs_offchip_offset, param_tcs_factor_offset,
4542 * param_tcs_offchip_layout, and param_rw_buffers
4543 * should be passed to the epilog.
4544 */
4545 for (i = 0; i <= 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K; i++)
4546 returns[num_returns++] = ctx->i32; /* SGPRs */
4547 for (i = 0; i < 11; i++)
4548 returns[num_returns++] = ctx->f32; /* VGPRs */
4549 }
4550 break;
4551
4552 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4553 /* Merged stages have 8 system SGPRs at the beginning. */
4554 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_LO_GS) */
4555 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_HI_GS) */
4556 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4557 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4558 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4559 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4560 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4561 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4562
4563 declare_global_desc_pointers(ctx, &fninfo);
4564 declare_per_stage_desc_pointers(ctx, &fninfo,
4565 (ctx->type == PIPE_SHADER_VERTEX ||
4566 ctx->type == PIPE_SHADER_TESS_EVAL));
4567 if (ctx->type == PIPE_SHADER_VERTEX) {
4568 declare_vs_specific_input_sgprs(ctx, &fninfo);
4569 } else {
4570 /* TESS_EVAL (and also GEOMETRY):
4571 * Declare as many input SGPRs as the VS has. */
4572 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4573 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4574 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4575 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4576 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4577 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4578 }
4579
4580 declare_per_stage_desc_pointers(ctx, &fninfo,
4581 ctx->type == PIPE_SHADER_GEOMETRY);
4582
4583 /* VGPRs (first GS, then VS/TES) */
4584 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4585 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4586 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4587 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4588 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4589
4590 if (ctx->type == PIPE_SHADER_VERTEX) {
4591 declare_vs_input_vgprs(ctx, &fninfo,
4592 &num_prolog_vgprs);
4593 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4594 declare_tes_input_vgprs(ctx, &fninfo);
4595 }
4596
4597 if (ctx->type == PIPE_SHADER_VERTEX ||
4598 ctx->type == PIPE_SHADER_TESS_EVAL) {
4599 /* ES return values are inputs to GS. */
4600 for (i = 0; i < 8 + GFX9_GS_NUM_USER_SGPR; i++)
4601 returns[num_returns++] = ctx->i32; /* SGPRs */
4602 for (i = 0; i < 5; i++)
4603 returns[num_returns++] = ctx->f32; /* VGPRs */
4604 }
4605 break;
4606
4607 case PIPE_SHADER_TESS_EVAL:
4608 declare_global_desc_pointers(ctx, &fninfo);
4609 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4610 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4611 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4612
4613 if (shader->key.as_es) {
4614 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4615 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4616 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4617 } else {
4618 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4619 declare_streamout_params(ctx, &shader->selector->so,
4620 &fninfo);
4621 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4622 }
4623
4624 /* VGPRs */
4625 declare_tes_input_vgprs(ctx, &fninfo);
4626 break;
4627
4628 case PIPE_SHADER_GEOMETRY:
4629 declare_global_desc_pointers(ctx, &fninfo);
4630 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4631 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4632 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4633
4634 /* VGPRs */
4635 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4636 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4637 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4638 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4639 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4640 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4641 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4642 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4643 break;
4644
4645 case PIPE_SHADER_FRAGMENT:
4646 declare_global_desc_pointers(ctx, &fninfo);
4647 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4648 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4649 add_arg_checked(&fninfo, ARG_SGPR, ctx->i32, SI_PARAM_PRIM_MASK);
4650
4651 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4652 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4653 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4654 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4655 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4656 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4657 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4658 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4659 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4660 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4661 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4662 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4663 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4664 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4665 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4666 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4667 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4668 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4669 shader->info.face_vgpr_index = 20;
4670 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4671 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4672 shader->info.ancillary_vgpr_index = 21;
4673 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4674 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4675 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4676
4677 /* Color inputs from the prolog. */
4678 if (shader->selector->info.colors_read) {
4679 unsigned num_color_elements =
4680 util_bitcount(shader->selector->info.colors_read);
4681
4682 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4683 for (i = 0; i < num_color_elements; i++)
4684 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4685
4686 num_prolog_vgprs += num_color_elements;
4687 }
4688
4689 /* Outputs for the epilog. */
4690 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4691 num_returns =
4692 num_return_sgprs +
4693 util_bitcount(shader->selector->info.colors_written) * 4 +
4694 shader->selector->info.writes_z +
4695 shader->selector->info.writes_stencil +
4696 shader->selector->info.writes_samplemask +
4697 1 /* SampleMaskIn */;
4698
4699 num_returns = MAX2(num_returns,
4700 num_return_sgprs +
4701 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4702
4703 for (i = 0; i < num_return_sgprs; i++)
4704 returns[i] = ctx->i32;
4705 for (; i < num_returns; i++)
4706 returns[i] = ctx->f32;
4707 break;
4708
4709 case PIPE_SHADER_COMPUTE:
4710 declare_global_desc_pointers(ctx, &fninfo);
4711 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4712 if (shader->selector->info.uses_grid_size)
4713 ctx->param_grid_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4714 if (shader->selector->info.uses_block_size)
4715 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4716
4717 for (i = 0; i < 3; i++) {
4718 ctx->param_block_id[i] = -1;
4719 if (shader->selector->info.uses_block_id[i])
4720 ctx->param_block_id[i] = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4721 }
4722
4723 ctx->param_thread_id = add_arg(&fninfo, ARG_VGPR, v3i32);
4724 break;
4725 default:
4726 assert(0 && "unimplemented shader");
4727 return;
4728 }
4729
4730 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4731 si_get_max_workgroup_size(shader));
4732
4733 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4734 if (ctx->type == PIPE_SHADER_FRAGMENT &&
4735 ctx->separate_prolog) {
4736 si_llvm_add_attribute(ctx->main_fn,
4737 "InitialPSInputAddr",
4738 S_0286D0_PERSP_SAMPLE_ENA(1) |
4739 S_0286D0_PERSP_CENTER_ENA(1) |
4740 S_0286D0_PERSP_CENTROID_ENA(1) |
4741 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4742 S_0286D0_LINEAR_CENTER_ENA(1) |
4743 S_0286D0_LINEAR_CENTROID_ENA(1) |
4744 S_0286D0_FRONT_FACE_ENA(1) |
4745 S_0286D0_ANCILLARY_ENA(1) |
4746 S_0286D0_POS_FIXED_PT_ENA(1));
4747 }
4748
4749 shader->info.num_input_sgprs = 0;
4750 shader->info.num_input_vgprs = 0;
4751
4752 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4753 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
4754
4755 for (; i < fninfo.num_params; ++i)
4756 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
4757
4758 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4759 shader->info.num_input_vgprs -= num_prolog_vgprs;
4760
4761 if (shader->key.as_ls ||
4762 ctx->type == PIPE_SHADER_TESS_CTRL ||
4763 /* GFX9 has the ESGS ring buffer in LDS. */
4764 type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY)
4765 ac_declare_lds_as_pointer(&ctx->ac);
4766 }
4767
4768 /**
4769 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4770 * for later use.
4771 */
4772 static void preload_ring_buffers(struct si_shader_context *ctx)
4773 {
4774 LLVMBuilderRef builder = ctx->ac.builder;
4775
4776 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
4777 ctx->param_rw_buffers);
4778
4779 if (ctx->screen->info.chip_class <= VI &&
4780 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
4781 unsigned ring =
4782 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
4783 : SI_ES_RING_ESGS;
4784 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
4785
4786 ctx->esgs_ring =
4787 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4788 }
4789
4790 if (ctx->shader->is_gs_copy_shader) {
4791 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4792
4793 ctx->gsvs_ring[0] =
4794 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4795 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
4796 const struct si_shader_selector *sel = ctx->shader->selector;
4797 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4798 LLVMValueRef base_ring;
4799
4800 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4801
4802 /* The conceptual layout of the GSVS ring is
4803 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4804 * but the real memory layout is swizzled across
4805 * threads:
4806 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4807 * t16v0c0 ..
4808 * Override the buffer descriptor accordingly.
4809 */
4810 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
4811 uint64_t stream_offset = 0;
4812
4813 for (unsigned stream = 0; stream < 4; ++stream) {
4814 unsigned num_components;
4815 unsigned stride;
4816 unsigned num_records;
4817 LLVMValueRef ring, tmp;
4818
4819 num_components = sel->info.num_stream_output_components[stream];
4820 if (!num_components)
4821 continue;
4822
4823 stride = 4 * num_components * sel->gs_max_out_vertices;
4824
4825 /* Limit on the stride field for <= CIK. */
4826 assert(stride < (1 << 14));
4827
4828 num_records = 64;
4829
4830 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
4831 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
4832 tmp = LLVMBuildAdd(builder, tmp,
4833 LLVMConstInt(ctx->i64,
4834 stream_offset, 0), "");
4835 stream_offset += stride * 64;
4836
4837 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
4838 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
4839 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
4840 tmp = LLVMBuildOr(builder, tmp,
4841 LLVMConstInt(ctx->i32,
4842 S_008F04_STRIDE(stride) |
4843 S_008F04_SWIZZLE_ENABLE(1), 0), "");
4844 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
4845 ring = LLVMBuildInsertElement(builder, ring,
4846 LLVMConstInt(ctx->i32, num_records, 0),
4847 LLVMConstInt(ctx->i32, 2, 0), "");
4848 ring = LLVMBuildInsertElement(builder, ring,
4849 LLVMConstInt(ctx->i32,
4850 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4851 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4852 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4853 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
4854 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4855 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
4856 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
4857 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
4858 S_008F0C_ADD_TID_ENABLE(1),
4859 0),
4860 LLVMConstInt(ctx->i32, 3, 0), "");
4861
4862 ctx->gsvs_ring[stream] = ring;
4863 }
4864 }
4865 }
4866
4867 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
4868 LLVMValueRef param_rw_buffers,
4869 unsigned param_pos_fixed_pt)
4870 {
4871 LLVMBuilderRef builder = ctx->ac.builder;
4872 LLVMValueRef slot, desc, offset, row, bit, address[2];
4873
4874 /* Use the fixed-point gl_FragCoord input.
4875 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
4876 * per coordinate to get the repeating effect.
4877 */
4878 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
4879 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
4880
4881 /* Load the buffer descriptor. */
4882 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
4883 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
4884
4885 /* The stipple pattern is 32x32, each row has 32 bits. */
4886 offset = LLVMBuildMul(builder, address[1],
4887 LLVMConstInt(ctx->i32, 4, 0), "");
4888 row = buffer_load_const(ctx, desc, offset);
4889 row = ac_to_integer(&ctx->ac, row);
4890 bit = LLVMBuildLShr(builder, row, address[0], "");
4891 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
4892 ac_build_kill_if_false(&ctx->ac, bit);
4893 }
4894
4895 void si_shader_binary_read_config(struct ac_shader_binary *binary,
4896 struct si_shader_config *conf,
4897 unsigned symbol_offset)
4898 {
4899 unsigned i;
4900 const unsigned char *config =
4901 ac_shader_binary_config_start(binary, symbol_offset);
4902 bool really_needs_scratch = false;
4903
4904 /* LLVM adds SGPR spills to the scratch size.
4905 * Find out if we really need the scratch buffer.
4906 */
4907 for (i = 0; i < binary->reloc_count; i++) {
4908 const struct ac_shader_reloc *reloc = &binary->relocs[i];
4909
4910 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
4911 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4912 really_needs_scratch = true;
4913 break;
4914 }
4915 }
4916
4917 /* XXX: We may be able to emit some of these values directly rather than
4918 * extracting fields to be emitted later.
4919 */
4920
4921 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
4922 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
4923 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
4924 switch (reg) {
4925 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
4926 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
4927 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
4928 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
4929 case R_00B848_COMPUTE_PGM_RSRC1:
4930 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
4931 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
4932 conf->float_mode = G_00B028_FLOAT_MODE(value);
4933 conf->rsrc1 = value;
4934 break;
4935 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
4936 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
4937 break;
4938 case R_00B84C_COMPUTE_PGM_RSRC2:
4939 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
4940 conf->rsrc2 = value;
4941 break;
4942 case R_0286CC_SPI_PS_INPUT_ENA:
4943 conf->spi_ps_input_ena = value;
4944 break;
4945 case R_0286D0_SPI_PS_INPUT_ADDR:
4946 conf->spi_ps_input_addr = value;
4947 break;
4948 case R_0286E8_SPI_TMPRING_SIZE:
4949 case R_00B860_COMPUTE_TMPRING_SIZE:
4950 /* WAVESIZE is in units of 256 dwords. */
4951 if (really_needs_scratch)
4952 conf->scratch_bytes_per_wave =
4953 G_00B860_WAVESIZE(value) * 256 * 4;
4954 break;
4955 case 0x4: /* SPILLED_SGPRS */
4956 conf->spilled_sgprs = value;
4957 break;
4958 case 0x8: /* SPILLED_VGPRS */
4959 conf->spilled_vgprs = value;
4960 break;
4961 default:
4962 {
4963 static bool printed;
4964
4965 if (!printed) {
4966 fprintf(stderr, "Warning: LLVM emitted unknown "
4967 "config register: 0x%x\n", reg);
4968 printed = true;
4969 }
4970 }
4971 break;
4972 }
4973 }
4974
4975 if (!conf->spi_ps_input_addr)
4976 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
4977 }
4978
4979 void si_shader_apply_scratch_relocs(struct si_shader *shader,
4980 uint64_t scratch_va)
4981 {
4982 unsigned i;
4983 uint32_t scratch_rsrc_dword0 = scratch_va;
4984 uint32_t scratch_rsrc_dword1 =
4985 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
4986
4987 /* Enable scratch coalescing. */
4988 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
4989
4990 for (i = 0 ; i < shader->binary.reloc_count; i++) {
4991 const struct ac_shader_reloc *reloc =
4992 &shader->binary.relocs[i];
4993 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
4994 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4995 &scratch_rsrc_dword0, 4);
4996 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4997 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4998 &scratch_rsrc_dword1, 4);
4999 }
5000 }
5001 }
5002
5003 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
5004 {
5005 unsigned size = shader->binary.code_size;
5006
5007 if (shader->prolog)
5008 size += shader->prolog->binary.code_size;
5009 if (shader->previous_stage)
5010 size += shader->previous_stage->binary.code_size;
5011 if (shader->prolog2)
5012 size += shader->prolog2->binary.code_size;
5013 if (shader->epilog)
5014 size += shader->epilog->binary.code_size;
5015 return size;
5016 }
5017
5018 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5019 {
5020 const struct ac_shader_binary *prolog =
5021 shader->prolog ? &shader->prolog->binary : NULL;
5022 const struct ac_shader_binary *previous_stage =
5023 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5024 const struct ac_shader_binary *prolog2 =
5025 shader->prolog2 ? &shader->prolog2->binary : NULL;
5026 const struct ac_shader_binary *epilog =
5027 shader->epilog ? &shader->epilog->binary : NULL;
5028 const struct ac_shader_binary *mainb = &shader->binary;
5029 unsigned bo_size = si_get_shader_binary_size(shader) +
5030 (!epilog ? mainb->rodata_size : 0);
5031 unsigned char *ptr;
5032
5033 assert(!prolog || !prolog->rodata_size);
5034 assert(!previous_stage || !previous_stage->rodata_size);
5035 assert(!prolog2 || !prolog2->rodata_size);
5036 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5037 !mainb->rodata_size);
5038 assert(!epilog || !epilog->rodata_size);
5039
5040 r600_resource_reference(&shader->bo, NULL);
5041 shader->bo = (struct r600_resource*)
5042 si_aligned_buffer_create(&sscreen->b,
5043 sscreen->cpdma_prefetch_writes_memory ?
5044 0 : R600_RESOURCE_FLAG_READ_ONLY,
5045 PIPE_USAGE_IMMUTABLE,
5046 align(bo_size, SI_CPDMA_ALIGNMENT),
5047 256);
5048 if (!shader->bo)
5049 return -ENOMEM;
5050
5051 /* Upload. */
5052 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5053 PIPE_TRANSFER_READ_WRITE |
5054 PIPE_TRANSFER_UNSYNCHRONIZED);
5055
5056 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5057 * endian-independent. */
5058 if (prolog) {
5059 memcpy(ptr, prolog->code, prolog->code_size);
5060 ptr += prolog->code_size;
5061 }
5062 if (previous_stage) {
5063 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5064 ptr += previous_stage->code_size;
5065 }
5066 if (prolog2) {
5067 memcpy(ptr, prolog2->code, prolog2->code_size);
5068 ptr += prolog2->code_size;
5069 }
5070
5071 memcpy(ptr, mainb->code, mainb->code_size);
5072 ptr += mainb->code_size;
5073
5074 if (epilog)
5075 memcpy(ptr, epilog->code, epilog->code_size);
5076 else if (mainb->rodata_size > 0)
5077 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5078
5079 sscreen->ws->buffer_unmap(shader->bo->buf);
5080 return 0;
5081 }
5082
5083 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5084 struct pipe_debug_callback *debug,
5085 const char *name, FILE *file)
5086 {
5087 char *line, *p;
5088 unsigned i, count;
5089
5090 if (binary->disasm_string) {
5091 fprintf(file, "Shader %s disassembly:\n", name);
5092 fprintf(file, "%s", binary->disasm_string);
5093
5094 if (debug && debug->debug_message) {
5095 /* Very long debug messages are cut off, so send the
5096 * disassembly one line at a time. This causes more
5097 * overhead, but on the plus side it simplifies
5098 * parsing of resulting logs.
5099 */
5100 pipe_debug_message(debug, SHADER_INFO,
5101 "Shader Disassembly Begin");
5102
5103 line = binary->disasm_string;
5104 while (*line) {
5105 p = util_strchrnul(line, '\n');
5106 count = p - line;
5107
5108 if (count) {
5109 pipe_debug_message(debug, SHADER_INFO,
5110 "%.*s", count, line);
5111 }
5112
5113 if (!*p)
5114 break;
5115 line = p + 1;
5116 }
5117
5118 pipe_debug_message(debug, SHADER_INFO,
5119 "Shader Disassembly End");
5120 }
5121 } else {
5122 fprintf(file, "Shader %s binary:\n", name);
5123 for (i = 0; i < binary->code_size; i += 4) {
5124 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5125 binary->code[i + 3], binary->code[i + 2],
5126 binary->code[i + 1], binary->code[i]);
5127 }
5128 }
5129 }
5130
5131 static void si_shader_dump_stats(struct si_screen *sscreen,
5132 const struct si_shader *shader,
5133 struct pipe_debug_callback *debug,
5134 unsigned processor,
5135 FILE *file,
5136 bool check_debug_option)
5137 {
5138 const struct si_shader_config *conf = &shader->config;
5139 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
5140 unsigned code_size = si_get_shader_binary_size(shader);
5141 unsigned lds_increment = sscreen->info.chip_class >= CIK ? 512 : 256;
5142 unsigned lds_per_wave = 0;
5143 unsigned max_simd_waves;
5144
5145 switch (sscreen->info.family) {
5146 /* These always have 8 waves: */
5147 case CHIP_POLARIS10:
5148 case CHIP_POLARIS11:
5149 case CHIP_POLARIS12:
5150 max_simd_waves = 8;
5151 break;
5152 default:
5153 max_simd_waves = 10;
5154 }
5155
5156 /* Compute LDS usage for PS. */
5157 switch (processor) {
5158 case PIPE_SHADER_FRAGMENT:
5159 /* The minimum usage per wave is (num_inputs * 48). The maximum
5160 * usage is (num_inputs * 48 * 16).
5161 * We can get anything in between and it varies between waves.
5162 *
5163 * The 48 bytes per input for a single primitive is equal to
5164 * 4 bytes/component * 4 components/input * 3 points.
5165 *
5166 * Other stages don't know the size at compile time or don't
5167 * allocate LDS per wave, but instead they do it per thread group.
5168 */
5169 lds_per_wave = conf->lds_size * lds_increment +
5170 align(num_inputs * 48, lds_increment);
5171 break;
5172 case PIPE_SHADER_COMPUTE:
5173 if (shader->selector) {
5174 unsigned max_workgroup_size =
5175 si_get_max_workgroup_size(shader);
5176 lds_per_wave = (conf->lds_size * lds_increment) /
5177 DIV_ROUND_UP(max_workgroup_size, 64);
5178 }
5179 break;
5180 }
5181
5182 /* Compute the per-SIMD wave counts. */
5183 if (conf->num_sgprs) {
5184 if (sscreen->info.chip_class >= VI)
5185 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5186 else
5187 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5188 }
5189
5190 if (conf->num_vgprs)
5191 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5192
5193 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5194 * 16KB makes some SIMDs unoccupied). */
5195 if (lds_per_wave)
5196 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5197
5198 if (!check_debug_option ||
5199 si_can_dump_shader(sscreen, processor)) {
5200 if (processor == PIPE_SHADER_FRAGMENT) {
5201 fprintf(file, "*** SHADER CONFIG ***\n"
5202 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5203 "SPI_PS_INPUT_ENA = 0x%04x\n",
5204 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5205 }
5206
5207 fprintf(file, "*** SHADER STATS ***\n"
5208 "SGPRS: %d\n"
5209 "VGPRS: %d\n"
5210 "Spilled SGPRs: %d\n"
5211 "Spilled VGPRs: %d\n"
5212 "Private memory VGPRs: %d\n"
5213 "Code Size: %d bytes\n"
5214 "LDS: %d blocks\n"
5215 "Scratch: %d bytes per wave\n"
5216 "Max Waves: %d\n"
5217 "********************\n\n\n",
5218 conf->num_sgprs, conf->num_vgprs,
5219 conf->spilled_sgprs, conf->spilled_vgprs,
5220 conf->private_mem_vgprs, code_size,
5221 conf->lds_size, conf->scratch_bytes_per_wave,
5222 max_simd_waves);
5223 }
5224
5225 pipe_debug_message(debug, SHADER_INFO,
5226 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5227 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5228 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5229 conf->num_sgprs, conf->num_vgprs, code_size,
5230 conf->lds_size, conf->scratch_bytes_per_wave,
5231 max_simd_waves, conf->spilled_sgprs,
5232 conf->spilled_vgprs, conf->private_mem_vgprs);
5233 }
5234
5235 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5236 {
5237 switch (processor) {
5238 case PIPE_SHADER_VERTEX:
5239 if (shader->key.as_es)
5240 return "Vertex Shader as ES";
5241 else if (shader->key.as_ls)
5242 return "Vertex Shader as LS";
5243 else
5244 return "Vertex Shader as VS";
5245 case PIPE_SHADER_TESS_CTRL:
5246 return "Tessellation Control Shader";
5247 case PIPE_SHADER_TESS_EVAL:
5248 if (shader->key.as_es)
5249 return "Tessellation Evaluation Shader as ES";
5250 else
5251 return "Tessellation Evaluation Shader as VS";
5252 case PIPE_SHADER_GEOMETRY:
5253 if (shader->is_gs_copy_shader)
5254 return "GS Copy Shader as VS";
5255 else
5256 return "Geometry Shader";
5257 case PIPE_SHADER_FRAGMENT:
5258 return "Pixel Shader";
5259 case PIPE_SHADER_COMPUTE:
5260 return "Compute Shader";
5261 default:
5262 return "Unknown Shader";
5263 }
5264 }
5265
5266 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5267 struct pipe_debug_callback *debug, unsigned processor,
5268 FILE *file, bool check_debug_option)
5269 {
5270 if (!check_debug_option ||
5271 si_can_dump_shader(sscreen, processor))
5272 si_dump_shader_key(processor, shader, file);
5273
5274 if (!check_debug_option && shader->binary.llvm_ir_string) {
5275 if (shader->previous_stage &&
5276 shader->previous_stage->binary.llvm_ir_string) {
5277 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5278 si_get_shader_name(shader, processor));
5279 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5280 }
5281
5282 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5283 si_get_shader_name(shader, processor));
5284 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5285 }
5286
5287 if (!check_debug_option ||
5288 (si_can_dump_shader(sscreen, processor) &&
5289 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5290 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5291
5292 if (shader->prolog)
5293 si_shader_dump_disassembly(&shader->prolog->binary,
5294 debug, "prolog", file);
5295 if (shader->previous_stage)
5296 si_shader_dump_disassembly(&shader->previous_stage->binary,
5297 debug, "previous stage", file);
5298 if (shader->prolog2)
5299 si_shader_dump_disassembly(&shader->prolog2->binary,
5300 debug, "prolog2", file);
5301
5302 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5303
5304 if (shader->epilog)
5305 si_shader_dump_disassembly(&shader->epilog->binary,
5306 debug, "epilog", file);
5307 fprintf(file, "\n");
5308 }
5309
5310 si_shader_dump_stats(sscreen, shader, debug, processor, file,
5311 check_debug_option);
5312 }
5313
5314 static int si_compile_llvm(struct si_screen *sscreen,
5315 struct ac_shader_binary *binary,
5316 struct si_shader_config *conf,
5317 LLVMTargetMachineRef tm,
5318 LLVMModuleRef mod,
5319 struct pipe_debug_callback *debug,
5320 unsigned processor,
5321 const char *name)
5322 {
5323 int r = 0;
5324 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5325
5326 if (si_can_dump_shader(sscreen, processor)) {
5327 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5328
5329 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5330 fprintf(stderr, "%s LLVM IR:\n\n", name);
5331 ac_dump_module(mod);
5332 fprintf(stderr, "\n");
5333 }
5334 }
5335
5336 if (sscreen->record_llvm_ir) {
5337 char *ir = LLVMPrintModuleToString(mod);
5338 binary->llvm_ir_string = strdup(ir);
5339 LLVMDisposeMessage(ir);
5340 }
5341
5342 if (!si_replace_shader(count, binary)) {
5343 r = si_llvm_compile(mod, binary, tm, debug);
5344 if (r)
5345 return r;
5346 }
5347
5348 si_shader_binary_read_config(binary, conf, 0);
5349
5350 /* Enable 64-bit and 16-bit denormals, because there is no performance
5351 * cost.
5352 *
5353 * If denormals are enabled, all floating-point output modifiers are
5354 * ignored.
5355 *
5356 * Don't enable denormals for 32-bit floats, because:
5357 * - Floating-point output modifiers would be ignored by the hw.
5358 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5359 * have to stop using those.
5360 * - SI & CI would be very slow.
5361 */
5362 conf->float_mode |= V_00B028_FP_64_DENORMS;
5363
5364 FREE(binary->config);
5365 FREE(binary->global_symbol_offsets);
5366 binary->config = NULL;
5367 binary->global_symbol_offsets = NULL;
5368
5369 /* Some shaders can't have rodata because their binaries can be
5370 * concatenated.
5371 */
5372 if (binary->rodata_size &&
5373 (processor == PIPE_SHADER_VERTEX ||
5374 processor == PIPE_SHADER_TESS_CTRL ||
5375 processor == PIPE_SHADER_TESS_EVAL ||
5376 processor == PIPE_SHADER_FRAGMENT)) {
5377 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5378 return -EINVAL;
5379 }
5380
5381 return r;
5382 }
5383
5384 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5385 {
5386 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5387 LLVMBuildRetVoid(ctx->ac.builder);
5388 else
5389 LLVMBuildRet(ctx->ac.builder, ret);
5390 }
5391
5392 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5393 struct si_shader *
5394 si_generate_gs_copy_shader(struct si_screen *sscreen,
5395 LLVMTargetMachineRef tm,
5396 struct si_shader_selector *gs_selector,
5397 struct pipe_debug_callback *debug)
5398 {
5399 struct si_shader_context ctx;
5400 struct si_shader *shader;
5401 LLVMBuilderRef builder;
5402 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
5403 struct lp_build_context *uint = &bld_base->uint_bld;
5404 struct si_shader_output_values *outputs;
5405 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5406 int i, r;
5407
5408 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5409
5410 if (!outputs)
5411 return NULL;
5412
5413 shader = CALLOC_STRUCT(si_shader);
5414 if (!shader) {
5415 FREE(outputs);
5416 return NULL;
5417 }
5418
5419 /* We can leave the fence as permanently signaled because the GS copy
5420 * shader only becomes visible globally after it has been compiled. */
5421 util_queue_fence_init(&shader->ready);
5422
5423 shader->selector = gs_selector;
5424 shader->is_gs_copy_shader = true;
5425
5426 si_init_shader_ctx(&ctx, sscreen, tm);
5427 ctx.shader = shader;
5428 ctx.type = PIPE_SHADER_VERTEX;
5429
5430 builder = ctx.ac.builder;
5431
5432 create_function(&ctx);
5433 preload_ring_buffers(&ctx);
5434
5435 LLVMValueRef voffset =
5436 lp_build_mul_imm(uint, ctx.abi.vertex_id, 4);
5437
5438 /* Fetch the vertex stream ID.*/
5439 LLVMValueRef stream_id;
5440
5441 if (gs_selector->so.num_outputs)
5442 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5443 else
5444 stream_id = ctx.i32_0;
5445
5446 /* Fill in output information. */
5447 for (i = 0; i < gsinfo->num_outputs; ++i) {
5448 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5449 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5450
5451 for (int chan = 0; chan < 4; chan++) {
5452 outputs[i].vertex_stream[chan] =
5453 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5454 }
5455 }
5456
5457 LLVMBasicBlockRef end_bb;
5458 LLVMValueRef switch_inst;
5459
5460 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5461 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5462
5463 for (int stream = 0; stream < 4; stream++) {
5464 LLVMBasicBlockRef bb;
5465 unsigned offset;
5466
5467 if (!gsinfo->num_stream_output_components[stream])
5468 continue;
5469
5470 if (stream > 0 && !gs_selector->so.num_outputs)
5471 continue;
5472
5473 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5474 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5475 LLVMPositionBuilderAtEnd(builder, bb);
5476
5477 /* Fetch vertex data from GSVS ring */
5478 offset = 0;
5479 for (i = 0; i < gsinfo->num_outputs; ++i) {
5480 for (unsigned chan = 0; chan < 4; chan++) {
5481 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5482 outputs[i].vertex_stream[chan] != stream) {
5483 outputs[i].values[chan] = ctx.bld_base.base.undef;
5484 continue;
5485 }
5486
5487 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5488 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5489 offset++;
5490
5491 outputs[i].values[chan] =
5492 ac_build_buffer_load(&ctx.ac,
5493 ctx.gsvs_ring[0], 1,
5494 ctx.i32_0, voffset,
5495 soffset, 0, 1, 1,
5496 true, false);
5497 }
5498 }
5499
5500 /* Streamout and exports. */
5501 if (gs_selector->so.num_outputs) {
5502 si_llvm_emit_streamout(&ctx, outputs,
5503 gsinfo->num_outputs,
5504 stream);
5505 }
5506
5507 if (stream == 0)
5508 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5509
5510 LLVMBuildBr(builder, end_bb);
5511 }
5512
5513 LLVMPositionBuilderAtEnd(builder, end_bb);
5514
5515 LLVMBuildRetVoid(ctx.ac.builder);
5516
5517 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5518 si_llvm_optimize_module(&ctx);
5519
5520 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5521 &ctx.shader->config, ctx.tm,
5522 ctx.gallivm.module,
5523 debug, PIPE_SHADER_GEOMETRY,
5524 "GS Copy Shader");
5525 if (!r) {
5526 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5527 fprintf(stderr, "GS Copy Shader:\n");
5528 si_shader_dump(sscreen, ctx.shader, debug,
5529 PIPE_SHADER_GEOMETRY, stderr, true);
5530 r = si_shader_binary_upload(sscreen, ctx.shader);
5531 }
5532
5533 si_llvm_dispose(&ctx);
5534
5535 FREE(outputs);
5536
5537 if (r != 0) {
5538 FREE(shader);
5539 shader = NULL;
5540 }
5541 return shader;
5542 }
5543
5544 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5545 const struct si_vs_prolog_bits *prolog,
5546 const char *prefix, FILE *f)
5547 {
5548 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5549 prefix, prolog->instance_divisor_is_one);
5550 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5551 prefix, prolog->instance_divisor_is_fetched);
5552 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5553 prefix, prolog->ls_vgpr_fix);
5554
5555 fprintf(f, " mono.vs.fix_fetch = {");
5556 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5557 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5558 fprintf(f, "}\n");
5559 }
5560
5561 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5562 FILE *f)
5563 {
5564 const struct si_shader_key *key = &shader->key;
5565
5566 fprintf(f, "SHADER KEY\n");
5567
5568 switch (processor) {
5569 case PIPE_SHADER_VERTEX:
5570 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5571 "part.vs.prolog", f);
5572 fprintf(f, " as_es = %u\n", key->as_es);
5573 fprintf(f, " as_ls = %u\n", key->as_ls);
5574 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5575 key->mono.u.vs_export_prim_id);
5576 break;
5577
5578 case PIPE_SHADER_TESS_CTRL:
5579 if (shader->selector->screen->info.chip_class >= GFX9) {
5580 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5581 "part.tcs.ls_prolog", f);
5582 }
5583 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5584 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5585 break;
5586
5587 case PIPE_SHADER_TESS_EVAL:
5588 fprintf(f, " as_es = %u\n", key->as_es);
5589 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5590 key->mono.u.vs_export_prim_id);
5591 break;
5592
5593 case PIPE_SHADER_GEOMETRY:
5594 if (shader->is_gs_copy_shader)
5595 break;
5596
5597 if (shader->selector->screen->info.chip_class >= GFX9 &&
5598 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5599 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5600 "part.gs.vs_prolog", f);
5601 }
5602 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5603 break;
5604
5605 case PIPE_SHADER_COMPUTE:
5606 break;
5607
5608 case PIPE_SHADER_FRAGMENT:
5609 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5610 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5611 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5612 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5613 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5614 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5615 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5616 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5617 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5618 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5619 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5620 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5621 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5622 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5623 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5624 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5625 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5626 break;
5627
5628 default:
5629 assert(0);
5630 }
5631
5632 if ((processor == PIPE_SHADER_GEOMETRY ||
5633 processor == PIPE_SHADER_TESS_EVAL ||
5634 processor == PIPE_SHADER_VERTEX) &&
5635 !key->as_es && !key->as_ls) {
5636 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5637 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5638 }
5639 }
5640
5641 static void si_init_shader_ctx(struct si_shader_context *ctx,
5642 struct si_screen *sscreen,
5643 LLVMTargetMachineRef tm)
5644 {
5645 struct lp_build_tgsi_context *bld_base;
5646
5647 si_llvm_context_init(ctx, sscreen, tm);
5648
5649 bld_base = &ctx->bld_base;
5650 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5651
5652 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5653 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5654 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5655
5656 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5657
5658 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5659
5660 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5661 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5662 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5663 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5664
5665 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5666 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5667 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5668 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5669 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5670 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5671 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5672 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
5673 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5674
5675 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5676 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
5677 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5678 }
5679
5680 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5681 {
5682 struct si_shader *shader = ctx->shader;
5683 struct tgsi_shader_info *info = &shader->selector->info;
5684
5685 if ((ctx->type != PIPE_SHADER_VERTEX &&
5686 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5687 shader->key.as_ls ||
5688 shader->key.as_es)
5689 return;
5690
5691 ac_optimize_vs_outputs(&ctx->ac,
5692 ctx->main_fn,
5693 shader->info.vs_output_param_offset,
5694 info->num_outputs,
5695 &shader->info.nr_param_exports);
5696 }
5697
5698 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
5699 {
5700 ctx->shader->config.private_mem_vgprs = 0;
5701
5702 /* Process all LLVM instructions. */
5703 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
5704 while (bb) {
5705 LLVMValueRef next = LLVMGetFirstInstruction(bb);
5706
5707 while (next) {
5708 LLVMValueRef inst = next;
5709 next = LLVMGetNextInstruction(next);
5710
5711 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
5712 continue;
5713
5714 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
5715 /* No idea why LLVM aligns allocas to 4 elements. */
5716 unsigned alignment = LLVMGetAlignment(inst);
5717 unsigned dw_size = align(ac_get_type_size(type) / 4, alignment);
5718 ctx->shader->config.private_mem_vgprs += dw_size;
5719 }
5720 bb = LLVMGetNextBasicBlock(bb);
5721 }
5722 }
5723
5724 static void si_init_exec_from_input(struct si_shader_context *ctx,
5725 unsigned param, unsigned bitoffset)
5726 {
5727 LLVMValueRef args[] = {
5728 LLVMGetParam(ctx->main_fn, param),
5729 LLVMConstInt(ctx->i32, bitoffset, 0),
5730 };
5731 lp_build_intrinsic(ctx->ac.builder,
5732 "llvm.amdgcn.init.exec.from.input",
5733 ctx->voidt, args, 2, LP_FUNC_ATTR_CONVERGENT);
5734 }
5735
5736 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
5737 const struct si_vs_prolog_bits *key)
5738 {
5739 /* VGPR initialization fixup for Vega10 and Raven is always done in the
5740 * VS prolog. */
5741 return sel->vs_needs_prolog || key->ls_vgpr_fix;
5742 }
5743
5744 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
5745 bool is_monolithic)
5746 {
5747 struct si_shader *shader = ctx->shader;
5748 struct si_shader_selector *sel = shader->selector;
5749 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5750
5751 // TODO clean all this up!
5752 switch (ctx->type) {
5753 case PIPE_SHADER_VERTEX:
5754 ctx->load_input = declare_input_vs;
5755 if (shader->key.as_ls)
5756 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
5757 else if (shader->key.as_es)
5758 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5759 else
5760 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5761 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5762 break;
5763 case PIPE_SHADER_TESS_CTRL:
5764 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5765 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5766 bld_base->emit_store = store_output_tcs;
5767 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
5768 break;
5769 case PIPE_SHADER_TESS_EVAL:
5770 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
5771 if (shader->key.as_es)
5772 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5773 else
5774 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5775 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5776 break;
5777 case PIPE_SHADER_GEOMETRY:
5778 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
5779 ctx->abi.load_inputs = si_nir_load_input_gs;
5780 ctx->abi.emit_vertex = si_llvm_emit_vertex;
5781 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
5782 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
5783 break;
5784 case PIPE_SHADER_FRAGMENT:
5785 ctx->load_input = declare_input_fs;
5786 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
5787 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5788 break;
5789 case PIPE_SHADER_COMPUTE:
5790 break;
5791 default:
5792 assert(!"Unsupported shader type");
5793 return false;
5794 }
5795
5796 ctx->abi.load_ubo = load_ubo;
5797 ctx->abi.load_ssbo = load_ssbo;
5798
5799 create_function(ctx);
5800 preload_ring_buffers(ctx);
5801
5802 /* For GFX9 merged shaders:
5803 * - Set EXEC for the first shader. If the prolog is present, set
5804 * EXEC there instead.
5805 * - Add a barrier before the second shader.
5806 * - In the second shader, reset EXEC to ~0 and wrap the main part in
5807 * an if-statement. This is required for correctness in geometry
5808 * shaders, to ensure that empty GS waves do not send GS_EMIT and
5809 * GS_CUT messages.
5810 *
5811 * For monolithic merged shaders, the first shader is wrapped in an
5812 * if-block together with its prolog in si_build_wrapper_function.
5813 */
5814 if (ctx->screen->info.chip_class >= GFX9) {
5815 if (!is_monolithic &&
5816 sel->info.num_instructions > 1 && /* not empty shader */
5817 (shader->key.as_es || shader->key.as_ls) &&
5818 (ctx->type == PIPE_SHADER_TESS_EVAL ||
5819 (ctx->type == PIPE_SHADER_VERTEX &&
5820 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
5821 si_init_exec_from_input(ctx,
5822 ctx->param_merged_wave_info, 0);
5823 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
5824 ctx->type == PIPE_SHADER_GEOMETRY) {
5825 if (!is_monolithic)
5826 ac_init_exec_full_mask(&ctx->ac);
5827
5828 /* The barrier must execute for all shaders in a
5829 * threadgroup.
5830 */
5831 si_llvm_emit_barrier(NULL, bld_base, NULL);
5832
5833 LLVMValueRef num_threads = unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
5834 LLVMValueRef ena =
5835 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
5836 ac_get_thread_id(&ctx->ac), num_threads, "");
5837 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
5838 }
5839 }
5840
5841 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
5842 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
5843 for (unsigned i = 0; i < 6; i++) {
5844 ctx->invoc0_tess_factors[i] =
5845 lp_build_alloca_undef(&ctx->gallivm, ctx->i32, "");
5846 }
5847 }
5848
5849 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5850 int i;
5851 for (i = 0; i < 4; i++) {
5852 ctx->gs_next_vertex[i] =
5853 lp_build_alloca(&ctx->gallivm,
5854 ctx->i32, "");
5855 }
5856 }
5857
5858 if (sel->force_correct_derivs_after_kill) {
5859 ctx->postponed_kill = lp_build_alloca_undef(&ctx->gallivm, ctx->i1, "");
5860 /* true = don't kill. */
5861 LLVMBuildStore(ctx->ac.builder, LLVMConstInt(ctx->i1, 1, 0),
5862 ctx->postponed_kill);
5863 }
5864
5865 if (sel->tokens) {
5866 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
5867 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
5868 return false;
5869 }
5870 } else {
5871 if (!si_nir_build_llvm(ctx, sel->nir)) {
5872 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
5873 return false;
5874 }
5875 }
5876
5877 si_llvm_build_ret(ctx, ctx->return_value);
5878 return true;
5879 }
5880
5881 /**
5882 * Compute the VS prolog key, which contains all the information needed to
5883 * build the VS prolog function, and set shader->info bits where needed.
5884 *
5885 * \param info Shader info of the vertex shader.
5886 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
5887 * \param prolog_key Key of the VS prolog
5888 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
5889 * \param key Output shader part key.
5890 */
5891 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
5892 unsigned num_input_sgprs,
5893 const struct si_vs_prolog_bits *prolog_key,
5894 struct si_shader *shader_out,
5895 union si_shader_part_key *key)
5896 {
5897 memset(key, 0, sizeof(*key));
5898 key->vs_prolog.states = *prolog_key;
5899 key->vs_prolog.num_input_sgprs = num_input_sgprs;
5900 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
5901 key->vs_prolog.as_ls = shader_out->key.as_ls;
5902 key->vs_prolog.as_es = shader_out->key.as_es;
5903
5904 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
5905 key->vs_prolog.as_ls = 1;
5906 key->vs_prolog.num_merged_next_stage_vgprs = 2;
5907 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
5908 key->vs_prolog.as_es = 1;
5909 key->vs_prolog.num_merged_next_stage_vgprs = 5;
5910 }
5911
5912 /* Enable loading the InstanceID VGPR. */
5913 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
5914
5915 if ((key->vs_prolog.states.instance_divisor_is_one |
5916 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
5917 shader_out->info.uses_instanceid = true;
5918 }
5919
5920 /**
5921 * Compute the PS prolog key, which contains all the information needed to
5922 * build the PS prolog function, and set related bits in shader->config.
5923 */
5924 static void si_get_ps_prolog_key(struct si_shader *shader,
5925 union si_shader_part_key *key,
5926 bool separate_prolog)
5927 {
5928 struct tgsi_shader_info *info = &shader->selector->info;
5929
5930 memset(key, 0, sizeof(*key));
5931 key->ps_prolog.states = shader->key.part.ps.prolog;
5932 key->ps_prolog.colors_read = info->colors_read;
5933 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
5934 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
5935 key->ps_prolog.wqm = info->uses_derivatives &&
5936 (key->ps_prolog.colors_read ||
5937 key->ps_prolog.states.force_persp_sample_interp ||
5938 key->ps_prolog.states.force_linear_sample_interp ||
5939 key->ps_prolog.states.force_persp_center_interp ||
5940 key->ps_prolog.states.force_linear_center_interp ||
5941 key->ps_prolog.states.bc_optimize_for_persp ||
5942 key->ps_prolog.states.bc_optimize_for_linear);
5943 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
5944
5945 if (info->colors_read) {
5946 unsigned *color = shader->selector->color_attr_index;
5947
5948 if (shader->key.part.ps.prolog.color_two_side) {
5949 /* BCOLORs are stored after the last input. */
5950 key->ps_prolog.num_interp_inputs = info->num_inputs;
5951 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
5952 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
5953 }
5954
5955 for (unsigned i = 0; i < 2; i++) {
5956 unsigned interp = info->input_interpolate[color[i]];
5957 unsigned location = info->input_interpolate_loc[color[i]];
5958
5959 if (!(info->colors_read & (0xf << i*4)))
5960 continue;
5961
5962 key->ps_prolog.color_attr_index[i] = color[i];
5963
5964 if (shader->key.part.ps.prolog.flatshade_colors &&
5965 interp == TGSI_INTERPOLATE_COLOR)
5966 interp = TGSI_INTERPOLATE_CONSTANT;
5967
5968 switch (interp) {
5969 case TGSI_INTERPOLATE_CONSTANT:
5970 key->ps_prolog.color_interp_vgpr_index[i] = -1;
5971 break;
5972 case TGSI_INTERPOLATE_PERSPECTIVE:
5973 case TGSI_INTERPOLATE_COLOR:
5974 /* Force the interpolation location for colors here. */
5975 if (shader->key.part.ps.prolog.force_persp_sample_interp)
5976 location = TGSI_INTERPOLATE_LOC_SAMPLE;
5977 if (shader->key.part.ps.prolog.force_persp_center_interp)
5978 location = TGSI_INTERPOLATE_LOC_CENTER;
5979
5980 switch (location) {
5981 case TGSI_INTERPOLATE_LOC_SAMPLE:
5982 key->ps_prolog.color_interp_vgpr_index[i] = 0;
5983 shader->config.spi_ps_input_ena |=
5984 S_0286CC_PERSP_SAMPLE_ENA(1);
5985 break;
5986 case TGSI_INTERPOLATE_LOC_CENTER:
5987 key->ps_prolog.color_interp_vgpr_index[i] = 2;
5988 shader->config.spi_ps_input_ena |=
5989 S_0286CC_PERSP_CENTER_ENA(1);
5990 break;
5991 case TGSI_INTERPOLATE_LOC_CENTROID:
5992 key->ps_prolog.color_interp_vgpr_index[i] = 4;
5993 shader->config.spi_ps_input_ena |=
5994 S_0286CC_PERSP_CENTROID_ENA(1);
5995 break;
5996 default:
5997 assert(0);
5998 }
5999 break;
6000 case TGSI_INTERPOLATE_LINEAR:
6001 /* Force the interpolation location for colors here. */
6002 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6003 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6004 if (shader->key.part.ps.prolog.force_linear_center_interp)
6005 location = TGSI_INTERPOLATE_LOC_CENTER;
6006
6007 /* The VGPR assignment for non-monolithic shaders
6008 * works because InitialPSInputAddr is set on the
6009 * main shader and PERSP_PULL_MODEL is never used.
6010 */
6011 switch (location) {
6012 case TGSI_INTERPOLATE_LOC_SAMPLE:
6013 key->ps_prolog.color_interp_vgpr_index[i] =
6014 separate_prolog ? 6 : 9;
6015 shader->config.spi_ps_input_ena |=
6016 S_0286CC_LINEAR_SAMPLE_ENA(1);
6017 break;
6018 case TGSI_INTERPOLATE_LOC_CENTER:
6019 key->ps_prolog.color_interp_vgpr_index[i] =
6020 separate_prolog ? 8 : 11;
6021 shader->config.spi_ps_input_ena |=
6022 S_0286CC_LINEAR_CENTER_ENA(1);
6023 break;
6024 case TGSI_INTERPOLATE_LOC_CENTROID:
6025 key->ps_prolog.color_interp_vgpr_index[i] =
6026 separate_prolog ? 10 : 13;
6027 shader->config.spi_ps_input_ena |=
6028 S_0286CC_LINEAR_CENTROID_ENA(1);
6029 break;
6030 default:
6031 assert(0);
6032 }
6033 break;
6034 default:
6035 assert(0);
6036 }
6037 }
6038 }
6039 }
6040
6041 /**
6042 * Check whether a PS prolog is required based on the key.
6043 */
6044 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6045 {
6046 return key->ps_prolog.colors_read ||
6047 key->ps_prolog.states.force_persp_sample_interp ||
6048 key->ps_prolog.states.force_linear_sample_interp ||
6049 key->ps_prolog.states.force_persp_center_interp ||
6050 key->ps_prolog.states.force_linear_center_interp ||
6051 key->ps_prolog.states.bc_optimize_for_persp ||
6052 key->ps_prolog.states.bc_optimize_for_linear ||
6053 key->ps_prolog.states.poly_stipple ||
6054 key->ps_prolog.states.samplemask_log_ps_iter;
6055 }
6056
6057 /**
6058 * Compute the PS epilog key, which contains all the information needed to
6059 * build the PS epilog function.
6060 */
6061 static void si_get_ps_epilog_key(struct si_shader *shader,
6062 union si_shader_part_key *key)
6063 {
6064 struct tgsi_shader_info *info = &shader->selector->info;
6065 memset(key, 0, sizeof(*key));
6066 key->ps_epilog.colors_written = info->colors_written;
6067 key->ps_epilog.writes_z = info->writes_z;
6068 key->ps_epilog.writes_stencil = info->writes_stencil;
6069 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6070 key->ps_epilog.states = shader->key.part.ps.epilog;
6071 }
6072
6073 /**
6074 * Build the GS prolog function. Rotate the input vertices for triangle strips
6075 * with adjacency.
6076 */
6077 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6078 union si_shader_part_key *key)
6079 {
6080 unsigned num_sgprs, num_vgprs;
6081 struct si_function_info fninfo;
6082 LLVMBuilderRef builder = ctx->ac.builder;
6083 LLVMTypeRef returns[48];
6084 LLVMValueRef func, ret;
6085
6086 si_init_function_info(&fninfo);
6087
6088 if (ctx->screen->info.chip_class >= GFX9) {
6089 num_sgprs = 8 + GFX9_GS_NUM_USER_SGPR;
6090 num_vgprs = 5; /* ES inputs are not needed by GS */
6091 } else {
6092 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6093 num_vgprs = 8;
6094 }
6095
6096 for (unsigned i = 0; i < num_sgprs; ++i) {
6097 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6098 returns[i] = ctx->i32;
6099 }
6100
6101 for (unsigned i = 0; i < num_vgprs; ++i) {
6102 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6103 returns[num_sgprs + i] = ctx->f32;
6104 }
6105
6106 /* Create the function. */
6107 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6108 &fninfo, 0);
6109 func = ctx->main_fn;
6110
6111 /* Set the full EXEC mask for the prolog, because we are only fiddling
6112 * with registers here. The main shader part will set the correct EXEC
6113 * mask.
6114 */
6115 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6116 ac_init_exec_full_mask(&ctx->ac);
6117
6118 /* Copy inputs to outputs. This should be no-op, as the registers match,
6119 * but it will prevent the compiler from overwriting them unintentionally.
6120 */
6121 ret = ctx->return_value;
6122 for (unsigned i = 0; i < num_sgprs; i++) {
6123 LLVMValueRef p = LLVMGetParam(func, i);
6124 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6125 }
6126 for (unsigned i = 0; i < num_vgprs; i++) {
6127 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6128 p = ac_to_float(&ctx->ac, p);
6129 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6130 }
6131
6132 if (key->gs_prolog.states.tri_strip_adj_fix) {
6133 /* Remap the input vertices for every other primitive. */
6134 const unsigned gfx6_vtx_params[6] = {
6135 num_sgprs,
6136 num_sgprs + 1,
6137 num_sgprs + 3,
6138 num_sgprs + 4,
6139 num_sgprs + 5,
6140 num_sgprs + 6
6141 };
6142 const unsigned gfx9_vtx_params[3] = {
6143 num_sgprs,
6144 num_sgprs + 1,
6145 num_sgprs + 4,
6146 };
6147 LLVMValueRef vtx_in[6], vtx_out[6];
6148 LLVMValueRef prim_id, rotate;
6149
6150 if (ctx->screen->info.chip_class >= GFX9) {
6151 for (unsigned i = 0; i < 3; i++) {
6152 vtx_in[i*2] = unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6153 vtx_in[i*2+1] = unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6154 }
6155 } else {
6156 for (unsigned i = 0; i < 6; i++)
6157 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6158 }
6159
6160 prim_id = LLVMGetParam(func, num_sgprs + 2);
6161 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6162
6163 for (unsigned i = 0; i < 6; ++i) {
6164 LLVMValueRef base, rotated;
6165 base = vtx_in[i];
6166 rotated = vtx_in[(i + 4) % 6];
6167 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6168 }
6169
6170 if (ctx->screen->info.chip_class >= GFX9) {
6171 for (unsigned i = 0; i < 3; i++) {
6172 LLVMValueRef hi, out;
6173
6174 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6175 LLVMConstInt(ctx->i32, 16, 0), "");
6176 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6177 out = ac_to_float(&ctx->ac, out);
6178 ret = LLVMBuildInsertValue(builder, ret, out,
6179 gfx9_vtx_params[i], "");
6180 }
6181 } else {
6182 for (unsigned i = 0; i < 6; i++) {
6183 LLVMValueRef out;
6184
6185 out = ac_to_float(&ctx->ac, vtx_out[i]);
6186 ret = LLVMBuildInsertValue(builder, ret, out,
6187 gfx6_vtx_params[i], "");
6188 }
6189 }
6190 }
6191
6192 LLVMBuildRet(builder, ret);
6193 }
6194
6195 /**
6196 * Given a list of shader part functions, build a wrapper function that
6197 * runs them in sequence to form a monolithic shader.
6198 */
6199 static void si_build_wrapper_function(struct si_shader_context *ctx,
6200 LLVMValueRef *parts,
6201 unsigned num_parts,
6202 unsigned main_part,
6203 unsigned next_shader_first_part)
6204 {
6205 LLVMBuilderRef builder = ctx->ac.builder;
6206 /* PS epilog has one arg per color component; gfx9 merged shader
6207 * prologs need to forward 32 user SGPRs.
6208 */
6209 struct si_function_info fninfo;
6210 LLVMValueRef initial[64], out[64];
6211 LLVMTypeRef function_type;
6212 unsigned num_first_params;
6213 unsigned num_out, initial_num_out;
6214 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6215 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6216 unsigned num_sgprs, num_vgprs;
6217 unsigned gprs;
6218 struct lp_build_if_state if_state;
6219
6220 si_init_function_info(&fninfo);
6221
6222 for (unsigned i = 0; i < num_parts; ++i) {
6223 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6224 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6225 }
6226
6227 /* The parameters of the wrapper function correspond to those of the
6228 * first part in terms of SGPRs and VGPRs, but we use the types of the
6229 * main part to get the right types. This is relevant for the
6230 * dereferenceable attribute on descriptor table pointers.
6231 */
6232 num_sgprs = 0;
6233 num_vgprs = 0;
6234
6235 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6236 num_first_params = LLVMCountParamTypes(function_type);
6237
6238 for (unsigned i = 0; i < num_first_params; ++i) {
6239 LLVMValueRef param = LLVMGetParam(parts[0], i);
6240
6241 if (ac_is_sgpr_param(param)) {
6242 assert(num_vgprs == 0);
6243 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6244 } else {
6245 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6246 }
6247 }
6248
6249 gprs = 0;
6250 while (gprs < num_sgprs + num_vgprs) {
6251 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6252 LLVMTypeRef type = LLVMTypeOf(param);
6253 unsigned size = ac_get_type_size(type) / 4;
6254
6255 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6256
6257 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6258 assert(gprs + size <= num_sgprs + num_vgprs &&
6259 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6260
6261 gprs += size;
6262 }
6263
6264 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6265 si_get_max_workgroup_size(ctx->shader));
6266
6267 if (is_merged_shader(ctx->shader))
6268 ac_init_exec_full_mask(&ctx->ac);
6269
6270 /* Record the arguments of the function as if they were an output of
6271 * a previous part.
6272 */
6273 num_out = 0;
6274 num_out_sgpr = 0;
6275
6276 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6277 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6278 LLVMTypeRef param_type = LLVMTypeOf(param);
6279 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6280 unsigned size = ac_get_type_size(param_type) / 4;
6281
6282 if (size == 1) {
6283 if (param_type != out_type)
6284 param = LLVMBuildBitCast(builder, param, out_type, "");
6285 out[num_out++] = param;
6286 } else {
6287 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6288
6289 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6290 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6291 param_type = ctx->i64;
6292 }
6293
6294 if (param_type != vector_type)
6295 param = LLVMBuildBitCast(builder, param, vector_type, "");
6296
6297 for (unsigned j = 0; j < size; ++j)
6298 out[num_out++] = LLVMBuildExtractElement(
6299 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6300 }
6301
6302 if (i < fninfo.num_sgpr_params)
6303 num_out_sgpr = num_out;
6304 }
6305
6306 memcpy(initial, out, sizeof(out));
6307 initial_num_out = num_out;
6308 initial_num_out_sgpr = num_out_sgpr;
6309
6310 /* Now chain the parts. */
6311 for (unsigned part = 0; part < num_parts; ++part) {
6312 LLVMValueRef in[48];
6313 LLVMValueRef ret;
6314 LLVMTypeRef ret_type;
6315 unsigned out_idx = 0;
6316 unsigned num_params = LLVMCountParams(parts[part]);
6317
6318 /* Merged shaders are executed conditionally depending
6319 * on the number of enabled threads passed in the input SGPRs. */
6320 if (is_merged_shader(ctx->shader) && part == 0) {
6321 LLVMValueRef ena, count = initial[3];
6322
6323 count = LLVMBuildAnd(builder, count,
6324 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6325 ena = LLVMBuildICmp(builder, LLVMIntULT,
6326 ac_get_thread_id(&ctx->ac), count, "");
6327 lp_build_if(&if_state, &ctx->gallivm, ena);
6328 }
6329
6330 /* Derive arguments for the next part from outputs of the
6331 * previous one.
6332 */
6333 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6334 LLVMValueRef param;
6335 LLVMTypeRef param_type;
6336 bool is_sgpr;
6337 unsigned param_size;
6338 LLVMValueRef arg = NULL;
6339
6340 param = LLVMGetParam(parts[part], param_idx);
6341 param_type = LLVMTypeOf(param);
6342 param_size = ac_get_type_size(param_type) / 4;
6343 is_sgpr = ac_is_sgpr_param(param);
6344
6345 if (is_sgpr) {
6346 #if HAVE_LLVM < 0x0400
6347 LLVMRemoveAttribute(param, LLVMByValAttribute);
6348 #else
6349 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
6350 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
6351 #endif
6352 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
6353 }
6354
6355 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6356 assert(is_sgpr || out_idx >= num_out_sgpr);
6357
6358 if (param_size == 1)
6359 arg = out[out_idx];
6360 else
6361 arg = lp_build_gather_values(&ctx->gallivm, &out[out_idx], param_size);
6362
6363 if (LLVMTypeOf(arg) != param_type) {
6364 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6365 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6366 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6367 } else {
6368 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6369 }
6370 }
6371
6372 in[param_idx] = arg;
6373 out_idx += param_size;
6374 }
6375
6376 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6377
6378 if (is_merged_shader(ctx->shader) &&
6379 part + 1 == next_shader_first_part) {
6380 lp_build_endif(&if_state);
6381
6382 /* The second half of the merged shader should use
6383 * the inputs from the toplevel (wrapper) function,
6384 * not the return value from the last call.
6385 *
6386 * That's because the last call was executed condi-
6387 * tionally, so we can't consume it in the main
6388 * block.
6389 */
6390 memcpy(out, initial, sizeof(initial));
6391 num_out = initial_num_out;
6392 num_out_sgpr = initial_num_out_sgpr;
6393 continue;
6394 }
6395
6396 /* Extract the returned GPRs. */
6397 ret_type = LLVMTypeOf(ret);
6398 num_out = 0;
6399 num_out_sgpr = 0;
6400
6401 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6402 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6403
6404 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6405
6406 for (unsigned i = 0; i < ret_size; ++i) {
6407 LLVMValueRef val =
6408 LLVMBuildExtractValue(builder, ret, i, "");
6409
6410 assert(num_out < ARRAY_SIZE(out));
6411 out[num_out++] = val;
6412
6413 if (LLVMTypeOf(val) == ctx->i32) {
6414 assert(num_out_sgpr + 1 == num_out);
6415 num_out_sgpr = num_out;
6416 }
6417 }
6418 }
6419 }
6420
6421 LLVMBuildRetVoid(builder);
6422 }
6423
6424 int si_compile_tgsi_shader(struct si_screen *sscreen,
6425 LLVMTargetMachineRef tm,
6426 struct si_shader *shader,
6427 bool is_monolithic,
6428 struct pipe_debug_callback *debug)
6429 {
6430 struct si_shader_selector *sel = shader->selector;
6431 struct si_shader_context ctx;
6432 int r = -1;
6433
6434 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6435 * conversion fails. */
6436 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6437 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6438 if (sel->tokens)
6439 tgsi_dump(sel->tokens, 0);
6440 else
6441 nir_print_shader(sel->nir, stderr);
6442 si_dump_streamout(&sel->so);
6443 }
6444
6445 si_init_shader_ctx(&ctx, sscreen, tm);
6446 si_llvm_context_set_tgsi(&ctx, shader);
6447 ctx.separate_prolog = !is_monolithic;
6448
6449 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6450 sizeof(shader->info.vs_output_param_offset));
6451
6452 shader->info.uses_instanceid = sel->info.uses_instanceid;
6453
6454 if (!si_compile_tgsi_main(&ctx, is_monolithic)) {
6455 si_llvm_dispose(&ctx);
6456 return -1;
6457 }
6458
6459 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6460 LLVMValueRef parts[2];
6461 bool need_prolog = sel->vs_needs_prolog;
6462
6463 parts[1] = ctx.main_fn;
6464
6465 if (need_prolog) {
6466 union si_shader_part_key prolog_key;
6467 si_get_vs_prolog_key(&sel->info,
6468 shader->info.num_input_sgprs,
6469 &shader->key.part.vs.prolog,
6470 shader, &prolog_key);
6471 si_build_vs_prolog_function(&ctx, &prolog_key);
6472 parts[0] = ctx.main_fn;
6473 }
6474
6475 si_build_wrapper_function(&ctx, parts + !need_prolog,
6476 1 + need_prolog, need_prolog, 0);
6477 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6478 if (sscreen->info.chip_class >= GFX9) {
6479 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6480 LLVMValueRef parts[4];
6481 bool vs_needs_prolog =
6482 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6483
6484 /* TCS main part */
6485 parts[2] = ctx.main_fn;
6486
6487 /* TCS epilog */
6488 union si_shader_part_key tcs_epilog_key;
6489 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6490 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6491 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6492 parts[3] = ctx.main_fn;
6493
6494 /* VS prolog */
6495 if (vs_needs_prolog) {
6496 union si_shader_part_key vs_prolog_key;
6497 si_get_vs_prolog_key(&ls->info,
6498 shader->info.num_input_sgprs,
6499 &shader->key.part.tcs.ls_prolog,
6500 shader, &vs_prolog_key);
6501 vs_prolog_key.vs_prolog.is_monolithic = true;
6502 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6503 parts[0] = ctx.main_fn;
6504 }
6505
6506 /* VS as LS main part */
6507 struct si_shader shader_ls = {};
6508 shader_ls.selector = ls;
6509 shader_ls.key.as_ls = 1;
6510 shader_ls.key.mono = shader->key.mono;
6511 shader_ls.key.opt = shader->key.opt;
6512 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6513
6514 if (!si_compile_tgsi_main(&ctx, true)) {
6515 si_llvm_dispose(&ctx);
6516 return -1;
6517 }
6518 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6519 parts[1] = ctx.main_fn;
6520
6521 /* Reset the shader context. */
6522 ctx.shader = shader;
6523 ctx.type = PIPE_SHADER_TESS_CTRL;
6524
6525 si_build_wrapper_function(&ctx,
6526 parts + !vs_needs_prolog,
6527 4 - !vs_needs_prolog, 0,
6528 vs_needs_prolog ? 2 : 1);
6529 } else {
6530 LLVMValueRef parts[2];
6531 union si_shader_part_key epilog_key;
6532
6533 parts[0] = ctx.main_fn;
6534
6535 memset(&epilog_key, 0, sizeof(epilog_key));
6536 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6537 si_build_tcs_epilog_function(&ctx, &epilog_key);
6538 parts[1] = ctx.main_fn;
6539
6540 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6541 }
6542 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6543 if (ctx.screen->info.chip_class >= GFX9) {
6544 struct si_shader_selector *es = shader->key.part.gs.es;
6545 LLVMValueRef es_prolog = NULL;
6546 LLVMValueRef es_main = NULL;
6547 LLVMValueRef gs_prolog = NULL;
6548 LLVMValueRef gs_main = ctx.main_fn;
6549
6550 /* GS prolog */
6551 union si_shader_part_key gs_prolog_key;
6552 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6553 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6554 gs_prolog_key.gs_prolog.is_monolithic = true;
6555 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6556 gs_prolog = ctx.main_fn;
6557
6558 /* ES prolog */
6559 if (es->vs_needs_prolog) {
6560 union si_shader_part_key vs_prolog_key;
6561 si_get_vs_prolog_key(&es->info,
6562 shader->info.num_input_sgprs,
6563 &shader->key.part.gs.vs_prolog,
6564 shader, &vs_prolog_key);
6565 vs_prolog_key.vs_prolog.is_monolithic = true;
6566 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6567 es_prolog = ctx.main_fn;
6568 }
6569
6570 /* ES main part */
6571 struct si_shader shader_es = {};
6572 shader_es.selector = es;
6573 shader_es.key.as_es = 1;
6574 shader_es.key.mono = shader->key.mono;
6575 shader_es.key.opt = shader->key.opt;
6576 si_llvm_context_set_tgsi(&ctx, &shader_es);
6577
6578 if (!si_compile_tgsi_main(&ctx, true)) {
6579 si_llvm_dispose(&ctx);
6580 return -1;
6581 }
6582 shader->info.uses_instanceid |= es->info.uses_instanceid;
6583 es_main = ctx.main_fn;
6584
6585 /* Reset the shader context. */
6586 ctx.shader = shader;
6587 ctx.type = PIPE_SHADER_GEOMETRY;
6588
6589 /* Prepare the array of shader parts. */
6590 LLVMValueRef parts[4];
6591 unsigned num_parts = 0, main_part, next_first_part;
6592
6593 if (es_prolog)
6594 parts[num_parts++] = es_prolog;
6595
6596 parts[main_part = num_parts++] = es_main;
6597 parts[next_first_part = num_parts++] = gs_prolog;
6598 parts[num_parts++] = gs_main;
6599
6600 si_build_wrapper_function(&ctx, parts, num_parts,
6601 main_part, next_first_part);
6602 } else {
6603 LLVMValueRef parts[2];
6604 union si_shader_part_key prolog_key;
6605
6606 parts[1] = ctx.main_fn;
6607
6608 memset(&prolog_key, 0, sizeof(prolog_key));
6609 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6610 si_build_gs_prolog_function(&ctx, &prolog_key);
6611 parts[0] = ctx.main_fn;
6612
6613 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6614 }
6615 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6616 LLVMValueRef parts[3];
6617 union si_shader_part_key prolog_key;
6618 union si_shader_part_key epilog_key;
6619 bool need_prolog;
6620
6621 si_get_ps_prolog_key(shader, &prolog_key, false);
6622 need_prolog = si_need_ps_prolog(&prolog_key);
6623
6624 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6625
6626 if (need_prolog) {
6627 si_build_ps_prolog_function(&ctx, &prolog_key);
6628 parts[0] = ctx.main_fn;
6629 }
6630
6631 si_get_ps_epilog_key(shader, &epilog_key);
6632 si_build_ps_epilog_function(&ctx, &epilog_key);
6633 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6634
6635 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6636 need_prolog ? 1 : 0, 0);
6637 }
6638
6639 si_llvm_optimize_module(&ctx);
6640
6641 /* Post-optimization transformations and analysis. */
6642 si_optimize_vs_outputs(&ctx);
6643
6644 if ((debug && debug->debug_message) ||
6645 si_can_dump_shader(sscreen, ctx.type))
6646 si_count_scratch_private_memory(&ctx);
6647
6648 /* Compile to bytecode. */
6649 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6650 ctx.gallivm.module, debug, ctx.type, "TGSI shader");
6651 si_llvm_dispose(&ctx);
6652 if (r) {
6653 fprintf(stderr, "LLVM failed to compile shader\n");
6654 return r;
6655 }
6656
6657 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6658 * LLVM 3.9svn has this bug.
6659 */
6660 if (sel->type == PIPE_SHADER_COMPUTE) {
6661 unsigned wave_size = 64;
6662 unsigned max_vgprs = 256;
6663 unsigned max_sgprs = sscreen->info.chip_class >= VI ? 800 : 512;
6664 unsigned max_sgprs_per_wave = 128;
6665 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6666 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6667 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6668
6669 max_vgprs = max_vgprs / min_waves_per_simd;
6670 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6671
6672 if (shader->config.num_sgprs > max_sgprs ||
6673 shader->config.num_vgprs > max_vgprs) {
6674 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6675 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6676 shader->config.num_sgprs, shader->config.num_vgprs,
6677 max_sgprs, max_vgprs);
6678
6679 /* Just terminate the process, because dependent
6680 * shaders can hang due to bad input data, but use
6681 * the env var to allow shader-db to work.
6682 */
6683 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6684 abort();
6685 }
6686 }
6687
6688 /* Add the scratch offset to input SGPRs. */
6689 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(shader))
6690 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6691
6692 /* Calculate the number of fragment input VGPRs. */
6693 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6694 shader->info.num_input_vgprs = 0;
6695 shader->info.face_vgpr_index = -1;
6696 shader->info.ancillary_vgpr_index = -1;
6697
6698 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6699 shader->info.num_input_vgprs += 2;
6700 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6701 shader->info.num_input_vgprs += 2;
6702 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6703 shader->info.num_input_vgprs += 2;
6704 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6705 shader->info.num_input_vgprs += 3;
6706 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6707 shader->info.num_input_vgprs += 2;
6708 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6709 shader->info.num_input_vgprs += 2;
6710 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6711 shader->info.num_input_vgprs += 2;
6712 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6713 shader->info.num_input_vgprs += 1;
6714 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6715 shader->info.num_input_vgprs += 1;
6716 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6717 shader->info.num_input_vgprs += 1;
6718 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6719 shader->info.num_input_vgprs += 1;
6720 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6721 shader->info.num_input_vgprs += 1;
6722 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6723 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6724 shader->info.num_input_vgprs += 1;
6725 }
6726 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
6727 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
6728 shader->info.num_input_vgprs += 1;
6729 }
6730 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6731 shader->info.num_input_vgprs += 1;
6732 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6733 shader->info.num_input_vgprs += 1;
6734 }
6735
6736 return 0;
6737 }
6738
6739 /**
6740 * Create, compile and return a shader part (prolog or epilog).
6741 *
6742 * \param sscreen screen
6743 * \param list list of shader parts of the same category
6744 * \param type shader type
6745 * \param key shader part key
6746 * \param prolog whether the part being requested is a prolog
6747 * \param tm LLVM target machine
6748 * \param debug debug callback
6749 * \param build the callback responsible for building the main function
6750 * \return non-NULL on success
6751 */
6752 static struct si_shader_part *
6753 si_get_shader_part(struct si_screen *sscreen,
6754 struct si_shader_part **list,
6755 enum pipe_shader_type type,
6756 bool prolog,
6757 union si_shader_part_key *key,
6758 LLVMTargetMachineRef tm,
6759 struct pipe_debug_callback *debug,
6760 void (*build)(struct si_shader_context *,
6761 union si_shader_part_key *),
6762 const char *name)
6763 {
6764 struct si_shader_part *result;
6765
6766 mtx_lock(&sscreen->shader_parts_mutex);
6767
6768 /* Find existing. */
6769 for (result = *list; result; result = result->next) {
6770 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6771 mtx_unlock(&sscreen->shader_parts_mutex);
6772 return result;
6773 }
6774 }
6775
6776 /* Compile a new one. */
6777 result = CALLOC_STRUCT(si_shader_part);
6778 result->key = *key;
6779
6780 struct si_shader shader = {};
6781 struct si_shader_context ctx;
6782
6783 si_init_shader_ctx(&ctx, sscreen, tm);
6784 ctx.shader = &shader;
6785 ctx.type = type;
6786
6787 switch (type) {
6788 case PIPE_SHADER_VERTEX:
6789 shader.key.as_ls = key->vs_prolog.as_ls;
6790 shader.key.as_es = key->vs_prolog.as_es;
6791 break;
6792 case PIPE_SHADER_TESS_CTRL:
6793 assert(!prolog);
6794 shader.key.part.tcs.epilog = key->tcs_epilog.states;
6795 break;
6796 case PIPE_SHADER_GEOMETRY:
6797 assert(prolog);
6798 break;
6799 case PIPE_SHADER_FRAGMENT:
6800 if (prolog)
6801 shader.key.part.ps.prolog = key->ps_prolog.states;
6802 else
6803 shader.key.part.ps.epilog = key->ps_epilog.states;
6804 break;
6805 default:
6806 unreachable("bad shader part");
6807 }
6808
6809 build(&ctx, key);
6810
6811 /* Compile. */
6812 si_llvm_optimize_module(&ctx);
6813
6814 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
6815 ctx.ac.module, debug, ctx.type, name)) {
6816 FREE(result);
6817 result = NULL;
6818 goto out;
6819 }
6820
6821 result->next = *list;
6822 *list = result;
6823
6824 out:
6825 si_llvm_dispose(&ctx);
6826 mtx_unlock(&sscreen->shader_parts_mutex);
6827 return result;
6828 }
6829
6830 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
6831 {
6832 LLVMValueRef ptr[2], list;
6833 bool is_merged_shader =
6834 ctx->screen->info.chip_class >= GFX9 &&
6835 (ctx->type == PIPE_SHADER_TESS_CTRL ||
6836 ctx->type == PIPE_SHADER_GEOMETRY ||
6837 ctx->shader->key.as_ls || ctx->shader->key.as_es);
6838
6839 /* Get the pointer to rw buffers. */
6840 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
6841 ptr[1] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS_HI);
6842 list = lp_build_gather_values(&ctx->gallivm, ptr, 2);
6843 list = LLVMBuildBitCast(ctx->ac.builder, list, ctx->i64, "");
6844 list = LLVMBuildIntToPtr(ctx->ac.builder, list,
6845 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS), "");
6846 return list;
6847 }
6848
6849 /**
6850 * Build the vertex shader prolog function.
6851 *
6852 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6853 * All inputs are returned unmodified. The vertex load indices are
6854 * stored after them, which will be used by the API VS for fetching inputs.
6855 *
6856 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6857 * input_v0,
6858 * input_v1,
6859 * input_v2,
6860 * input_v3,
6861 * (VertexID + BaseVertex),
6862 * (InstanceID + StartInstance),
6863 * (InstanceID / 2 + StartInstance)
6864 */
6865 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
6866 union si_shader_part_key *key)
6867 {
6868 struct si_function_info fninfo;
6869 LLVMTypeRef *returns;
6870 LLVMValueRef ret, func;
6871 int num_returns, i;
6872 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
6873 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
6874 LLVMValueRef input_vgprs[9];
6875 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
6876 num_input_vgprs;
6877 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
6878
6879 si_init_function_info(&fninfo);
6880
6881 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6882 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
6883 sizeof(LLVMTypeRef));
6884 num_returns = 0;
6885
6886 /* Declare input and output SGPRs. */
6887 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6888 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6889 returns[num_returns++] = ctx->i32;
6890 }
6891
6892 /* Preloaded VGPRs (outputs must be floats) */
6893 for (i = 0; i < num_input_vgprs; i++) {
6894 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
6895 returns[num_returns++] = ctx->f32;
6896 }
6897
6898 /* Vertex load indices. */
6899 for (i = 0; i <= key->vs_prolog.last_input; i++)
6900 returns[num_returns++] = ctx->f32;
6901
6902 /* Create the function. */
6903 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
6904 func = ctx->main_fn;
6905
6906 if (key->vs_prolog.num_merged_next_stage_vgprs) {
6907 if (!key->vs_prolog.is_monolithic)
6908 si_init_exec_from_input(ctx, 3, 0);
6909
6910 if (key->vs_prolog.as_ls &&
6911 ctx->screen->has_ls_vgpr_init_bug) {
6912 /* If there are no HS threads, SPI loads the LS VGPRs
6913 * starting at VGPR 0. Shift them back to where they
6914 * belong.
6915 */
6916 LLVMValueRef has_hs_threads =
6917 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
6918 unpack_param(ctx, 3, 8, 8),
6919 ctx->i32_0, "");
6920
6921 for (i = 4; i > 0; --i) {
6922 input_vgprs[i + 1] =
6923 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
6924 input_vgprs[i + 1],
6925 input_vgprs[i - 1], "");
6926 }
6927 }
6928 }
6929
6930 ctx->abi.vertex_id = input_vgprs[first_vs_vgpr];
6931 ctx->abi.instance_id = input_vgprs[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)];
6932
6933 /* Copy inputs to outputs. This should be no-op, as the registers match,
6934 * but it will prevent the compiler from overwriting them unintentionally.
6935 */
6936 ret = ctx->return_value;
6937 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6938 LLVMValueRef p = LLVMGetParam(func, i);
6939 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
6940 }
6941 for (i = 0; i < num_input_vgprs; i++) {
6942 LLVMValueRef p = input_vgprs[i];
6943 p = ac_to_float(&ctx->ac, p);
6944 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
6945 key->vs_prolog.num_input_sgprs + i, "");
6946 }
6947
6948 /* Compute vertex load indices from instance divisors. */
6949 LLVMValueRef instance_divisor_constbuf = NULL;
6950
6951 if (key->vs_prolog.states.instance_divisor_is_fetched) {
6952 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
6953 LLVMValueRef buf_index =
6954 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
6955 instance_divisor_constbuf =
6956 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
6957 }
6958
6959 for (i = 0; i <= key->vs_prolog.last_input; i++) {
6960 bool divisor_is_one =
6961 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
6962 bool divisor_is_fetched =
6963 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
6964 LLVMValueRef index;
6965
6966 if (divisor_is_one || divisor_is_fetched) {
6967 LLVMValueRef divisor = ctx->i32_1;
6968
6969 if (divisor_is_fetched) {
6970 divisor = buffer_load_const(ctx, instance_divisor_constbuf,
6971 LLVMConstInt(ctx->i32, i * 4, 0));
6972 divisor = ac_to_integer(&ctx->ac, divisor);
6973 }
6974
6975 /* InstanceID / Divisor + StartInstance */
6976 index = get_instance_index_for_fetch(ctx,
6977 user_sgpr_base +
6978 SI_SGPR_START_INSTANCE,
6979 divisor);
6980 } else {
6981 /* VertexID + BaseVertex */
6982 index = LLVMBuildAdd(ctx->ac.builder,
6983 ctx->abi.vertex_id,
6984 LLVMGetParam(func, user_sgpr_base +
6985 SI_SGPR_BASE_VERTEX), "");
6986 }
6987
6988 index = ac_to_float(&ctx->ac, index);
6989 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
6990 fninfo.num_params + i, "");
6991 }
6992
6993 si_llvm_build_ret(ctx, ret);
6994 }
6995
6996 static bool si_get_vs_prolog(struct si_screen *sscreen,
6997 LLVMTargetMachineRef tm,
6998 struct si_shader *shader,
6999 struct pipe_debug_callback *debug,
7000 struct si_shader *main_part,
7001 const struct si_vs_prolog_bits *key)
7002 {
7003 struct si_shader_selector *vs = main_part->selector;
7004
7005 if (!si_vs_needs_prolog(vs, key))
7006 return true;
7007
7008 /* Get the prolog. */
7009 union si_shader_part_key prolog_key;
7010 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7011 key, shader, &prolog_key);
7012
7013 shader->prolog =
7014 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7015 PIPE_SHADER_VERTEX, true, &prolog_key, tm,
7016 debug, si_build_vs_prolog_function,
7017 "Vertex Shader Prolog");
7018 return shader->prolog != NULL;
7019 }
7020
7021 /**
7022 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7023 */
7024 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7025 LLVMTargetMachineRef tm,
7026 struct si_shader *shader,
7027 struct pipe_debug_callback *debug)
7028 {
7029 return si_get_vs_prolog(sscreen, tm, shader, debug, shader,
7030 &shader->key.part.vs.prolog);
7031 }
7032
7033 /**
7034 * Compile the TCS epilog function. This writes tesselation factors to memory
7035 * based on the output primitive type of the tesselator (determined by TES).
7036 */
7037 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7038 union si_shader_part_key *key)
7039 {
7040 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7041 struct si_function_info fninfo;
7042 LLVMValueRef func;
7043
7044 si_init_function_info(&fninfo);
7045
7046 if (ctx->screen->info.chip_class >= GFX9) {
7047 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7048 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7049 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7050 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7051 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7052 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7053 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7054 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7055 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7056 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7057 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7058 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7059 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7060 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7061 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7062 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7063 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7064 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7065 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7066 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7067 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7068 } else {
7069 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7070 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7071 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7072 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7073 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7074 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7075 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7076 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7077 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7078 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7079 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7080 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7081 }
7082
7083 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7084 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7085 unsigned tess_factors_idx =
7086 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7087 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7088 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7089
7090 for (unsigned i = 0; i < 6; i++)
7091 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7092
7093 /* Create the function. */
7094 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7095 ctx->screen->info.chip_class >= CIK ? 128 : 64);
7096 ac_declare_lds_as_pointer(&ctx->ac);
7097 func = ctx->main_fn;
7098
7099 LLVMValueRef invoc0_tess_factors[6];
7100 for (unsigned i = 0; i < 6; i++)
7101 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7102
7103 si_write_tess_factors(bld_base,
7104 LLVMGetParam(func, tess_factors_idx),
7105 LLVMGetParam(func, tess_factors_idx + 1),
7106 LLVMGetParam(func, tess_factors_idx + 2),
7107 invoc0_tess_factors, invoc0_tess_factors + 4);
7108
7109 LLVMBuildRetVoid(ctx->ac.builder);
7110 }
7111
7112 /**
7113 * Select and compile (or reuse) TCS parts (epilog).
7114 */
7115 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7116 LLVMTargetMachineRef tm,
7117 struct si_shader *shader,
7118 struct pipe_debug_callback *debug)
7119 {
7120 if (sscreen->info.chip_class >= GFX9) {
7121 struct si_shader *ls_main_part =
7122 shader->key.part.tcs.ls->main_shader_part_ls;
7123
7124 if (!si_get_vs_prolog(sscreen, tm, shader, debug, ls_main_part,
7125 &shader->key.part.tcs.ls_prolog))
7126 return false;
7127
7128 shader->previous_stage = ls_main_part;
7129 }
7130
7131 /* Get the epilog. */
7132 union si_shader_part_key epilog_key;
7133 memset(&epilog_key, 0, sizeof(epilog_key));
7134 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7135
7136 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7137 PIPE_SHADER_TESS_CTRL, false,
7138 &epilog_key, tm, debug,
7139 si_build_tcs_epilog_function,
7140 "Tessellation Control Shader Epilog");
7141 return shader->epilog != NULL;
7142 }
7143
7144 /**
7145 * Select and compile (or reuse) GS parts (prolog).
7146 */
7147 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7148 LLVMTargetMachineRef tm,
7149 struct si_shader *shader,
7150 struct pipe_debug_callback *debug)
7151 {
7152 if (sscreen->info.chip_class >= GFX9) {
7153 struct si_shader *es_main_part =
7154 shader->key.part.gs.es->main_shader_part_es;
7155
7156 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7157 !si_get_vs_prolog(sscreen, tm, shader, debug, es_main_part,
7158 &shader->key.part.gs.vs_prolog))
7159 return false;
7160
7161 shader->previous_stage = es_main_part;
7162 }
7163
7164 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7165 return true;
7166
7167 union si_shader_part_key prolog_key;
7168 memset(&prolog_key, 0, sizeof(prolog_key));
7169 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7170
7171 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7172 PIPE_SHADER_GEOMETRY, true,
7173 &prolog_key, tm, debug,
7174 si_build_gs_prolog_function,
7175 "Geometry Shader Prolog");
7176 return shader->prolog2 != NULL;
7177 }
7178
7179 /**
7180 * Build the pixel shader prolog function. This handles:
7181 * - two-side color selection and interpolation
7182 * - overriding interpolation parameters for the API PS
7183 * - polygon stippling
7184 *
7185 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7186 * overriden by other states. (e.g. per-sample interpolation)
7187 * Interpolated colors are stored after the preloaded VGPRs.
7188 */
7189 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7190 union si_shader_part_key *key)
7191 {
7192 struct si_function_info fninfo;
7193 LLVMValueRef ret, func;
7194 int num_returns, i, num_color_channels;
7195
7196 assert(si_need_ps_prolog(key));
7197
7198 si_init_function_info(&fninfo);
7199
7200 /* Declare inputs. */
7201 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7202 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7203
7204 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7205 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7206
7207 /* Declare outputs (same as inputs + add colors if needed) */
7208 num_returns = fninfo.num_params;
7209 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7210 for (i = 0; i < num_color_channels; i++)
7211 fninfo.types[num_returns++] = ctx->f32;
7212
7213 /* Create the function. */
7214 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7215 &fninfo, 0);
7216 func = ctx->main_fn;
7217
7218 /* Copy inputs to outputs. This should be no-op, as the registers match,
7219 * but it will prevent the compiler from overwriting them unintentionally.
7220 */
7221 ret = ctx->return_value;
7222 for (i = 0; i < fninfo.num_params; i++) {
7223 LLVMValueRef p = LLVMGetParam(func, i);
7224 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7225 }
7226
7227 /* Polygon stippling. */
7228 if (key->ps_prolog.states.poly_stipple) {
7229 /* POS_FIXED_PT is always last. */
7230 unsigned pos = key->ps_prolog.num_input_sgprs +
7231 key->ps_prolog.num_input_vgprs - 1;
7232 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7233
7234 si_llvm_emit_polygon_stipple(ctx, list, pos);
7235 }
7236
7237 if (key->ps_prolog.states.bc_optimize_for_persp ||
7238 key->ps_prolog.states.bc_optimize_for_linear) {
7239 unsigned i, base = key->ps_prolog.num_input_sgprs;
7240 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7241
7242 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7243 * The hw doesn't compute CENTROID if the whole wave only
7244 * contains fully-covered quads.
7245 *
7246 * PRIM_MASK is after user SGPRs.
7247 */
7248 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7249 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7250 LLVMConstInt(ctx->i32, 31, 0), "");
7251 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7252 ctx->i1, "");
7253
7254 if (key->ps_prolog.states.bc_optimize_for_persp) {
7255 /* Read PERSP_CENTER. */
7256 for (i = 0; i < 2; i++)
7257 center[i] = LLVMGetParam(func, base + 2 + i);
7258 /* Read PERSP_CENTROID. */
7259 for (i = 0; i < 2; i++)
7260 centroid[i] = LLVMGetParam(func, base + 4 + i);
7261 /* Select PERSP_CENTROID. */
7262 for (i = 0; i < 2; i++) {
7263 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7264 center[i], centroid[i], "");
7265 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7266 tmp, base + 4 + i, "");
7267 }
7268 }
7269 if (key->ps_prolog.states.bc_optimize_for_linear) {
7270 /* Read LINEAR_CENTER. */
7271 for (i = 0; i < 2; i++)
7272 center[i] = LLVMGetParam(func, base + 8 + i);
7273 /* Read LINEAR_CENTROID. */
7274 for (i = 0; i < 2; i++)
7275 centroid[i] = LLVMGetParam(func, base + 10 + i);
7276 /* Select LINEAR_CENTROID. */
7277 for (i = 0; i < 2; i++) {
7278 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7279 center[i], centroid[i], "");
7280 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7281 tmp, base + 10 + i, "");
7282 }
7283 }
7284 }
7285
7286 /* Force per-sample interpolation. */
7287 if (key->ps_prolog.states.force_persp_sample_interp) {
7288 unsigned i, base = key->ps_prolog.num_input_sgprs;
7289 LLVMValueRef persp_sample[2];
7290
7291 /* Read PERSP_SAMPLE. */
7292 for (i = 0; i < 2; i++)
7293 persp_sample[i] = LLVMGetParam(func, base + i);
7294 /* Overwrite PERSP_CENTER. */
7295 for (i = 0; i < 2; i++)
7296 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7297 persp_sample[i], base + 2 + i, "");
7298 /* Overwrite PERSP_CENTROID. */
7299 for (i = 0; i < 2; i++)
7300 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7301 persp_sample[i], base + 4 + i, "");
7302 }
7303 if (key->ps_prolog.states.force_linear_sample_interp) {
7304 unsigned i, base = key->ps_prolog.num_input_sgprs;
7305 LLVMValueRef linear_sample[2];
7306
7307 /* Read LINEAR_SAMPLE. */
7308 for (i = 0; i < 2; i++)
7309 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7310 /* Overwrite LINEAR_CENTER. */
7311 for (i = 0; i < 2; i++)
7312 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7313 linear_sample[i], base + 8 + i, "");
7314 /* Overwrite LINEAR_CENTROID. */
7315 for (i = 0; i < 2; i++)
7316 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7317 linear_sample[i], base + 10 + i, "");
7318 }
7319
7320 /* Force center interpolation. */
7321 if (key->ps_prolog.states.force_persp_center_interp) {
7322 unsigned i, base = key->ps_prolog.num_input_sgprs;
7323 LLVMValueRef persp_center[2];
7324
7325 /* Read PERSP_CENTER. */
7326 for (i = 0; i < 2; i++)
7327 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7328 /* Overwrite PERSP_SAMPLE. */
7329 for (i = 0; i < 2; i++)
7330 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7331 persp_center[i], base + i, "");
7332 /* Overwrite PERSP_CENTROID. */
7333 for (i = 0; i < 2; i++)
7334 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7335 persp_center[i], base + 4 + i, "");
7336 }
7337 if (key->ps_prolog.states.force_linear_center_interp) {
7338 unsigned i, base = key->ps_prolog.num_input_sgprs;
7339 LLVMValueRef linear_center[2];
7340
7341 /* Read LINEAR_CENTER. */
7342 for (i = 0; i < 2; i++)
7343 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7344 /* Overwrite LINEAR_SAMPLE. */
7345 for (i = 0; i < 2; i++)
7346 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7347 linear_center[i], base + 6 + i, "");
7348 /* Overwrite LINEAR_CENTROID. */
7349 for (i = 0; i < 2; i++)
7350 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7351 linear_center[i], base + 10 + i, "");
7352 }
7353
7354 /* Interpolate colors. */
7355 unsigned color_out_idx = 0;
7356 for (i = 0; i < 2; i++) {
7357 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7358 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7359 key->ps_prolog.face_vgpr_index;
7360 LLVMValueRef interp[2], color[4];
7361 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7362
7363 if (!writemask)
7364 continue;
7365
7366 /* If the interpolation qualifier is not CONSTANT (-1). */
7367 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7368 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7369 key->ps_prolog.color_interp_vgpr_index[i];
7370
7371 /* Get the (i,j) updated by bc_optimize handling. */
7372 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7373 interp_vgpr, "");
7374 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7375 interp_vgpr + 1, "");
7376 interp_ij = lp_build_gather_values(&ctx->gallivm, interp, 2);
7377 }
7378
7379 /* Use the absolute location of the input. */
7380 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7381
7382 if (key->ps_prolog.states.color_two_side) {
7383 face = LLVMGetParam(func, face_vgpr);
7384 face = ac_to_integer(&ctx->ac, face);
7385 }
7386
7387 interp_fs_input(ctx,
7388 key->ps_prolog.color_attr_index[i],
7389 TGSI_SEMANTIC_COLOR, i,
7390 key->ps_prolog.num_interp_inputs,
7391 key->ps_prolog.colors_read, interp_ij,
7392 prim_mask, face, color);
7393
7394 while (writemask) {
7395 unsigned chan = u_bit_scan(&writemask);
7396 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7397 fninfo.num_params + color_out_idx++, "");
7398 }
7399 }
7400
7401 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7402 * says:
7403 *
7404 * "When per-sample shading is active due to the use of a fragment
7405 * input qualified by sample or due to the use of the gl_SampleID
7406 * or gl_SamplePosition variables, only the bit for the current
7407 * sample is set in gl_SampleMaskIn. When state specifies multiple
7408 * fragment shader invocations for a given fragment, the sample
7409 * mask for any single fragment shader invocation may specify a
7410 * subset of the covered samples for the fragment. In this case,
7411 * the bit corresponding to each covered sample will be set in
7412 * exactly one fragment shader invocation."
7413 *
7414 * The samplemask loaded by hardware is always the coverage of the
7415 * entire pixel/fragment, so mask bits out based on the sample ID.
7416 */
7417 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7418 /* The bit pattern matches that used by fixed function fragment
7419 * processing. */
7420 static const uint16_t ps_iter_masks[] = {
7421 0xffff, /* not used */
7422 0x5555,
7423 0x1111,
7424 0x0101,
7425 0x0001,
7426 };
7427 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7428
7429 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7430 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7431 key->ps_prolog.ancillary_vgpr_index;
7432 LLVMValueRef sampleid = unpack_param(ctx, ancillary_vgpr, 8, 4);
7433 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7434
7435 samplemask = ac_to_integer(&ctx->ac, samplemask);
7436 samplemask = LLVMBuildAnd(
7437 ctx->ac.builder,
7438 samplemask,
7439 LLVMBuildShl(ctx->ac.builder,
7440 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7441 sampleid, ""),
7442 "");
7443 samplemask = ac_to_float(&ctx->ac, samplemask);
7444
7445 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7446 ancillary_vgpr + 1, "");
7447 }
7448
7449 /* Tell LLVM to insert WQM instruction sequence when needed. */
7450 if (key->ps_prolog.wqm) {
7451 LLVMAddTargetDependentFunctionAttr(func,
7452 "amdgpu-ps-wqm-outputs", "");
7453 }
7454
7455 si_llvm_build_ret(ctx, ret);
7456 }
7457
7458 /**
7459 * Build the pixel shader epilog function. This handles everything that must be
7460 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7461 */
7462 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7463 union si_shader_part_key *key)
7464 {
7465 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7466 struct si_function_info fninfo;
7467 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7468 int i;
7469 struct si_ps_exports exp = {};
7470
7471 si_init_function_info(&fninfo);
7472
7473 /* Declare input SGPRs. */
7474 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7475 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7476 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7477 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7478 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7479
7480 /* Declare input VGPRs. */
7481 unsigned required_num_params =
7482 fninfo.num_sgpr_params +
7483 util_bitcount(key->ps_epilog.colors_written) * 4 +
7484 key->ps_epilog.writes_z +
7485 key->ps_epilog.writes_stencil +
7486 key->ps_epilog.writes_samplemask;
7487
7488 required_num_params = MAX2(required_num_params,
7489 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7490
7491 while (fninfo.num_params < required_num_params)
7492 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7493
7494 /* Create the function. */
7495 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7496 /* Disable elimination of unused inputs. */
7497 si_llvm_add_attribute(ctx->main_fn,
7498 "InitialPSInputAddr", 0xffffff);
7499
7500 /* Process colors. */
7501 unsigned vgpr = fninfo.num_sgpr_params;
7502 unsigned colors_written = key->ps_epilog.colors_written;
7503 int last_color_export = -1;
7504
7505 /* Find the last color export. */
7506 if (!key->ps_epilog.writes_z &&
7507 !key->ps_epilog.writes_stencil &&
7508 !key->ps_epilog.writes_samplemask) {
7509 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7510
7511 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7512 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7513 /* Just set this if any of the colorbuffers are enabled. */
7514 if (spi_format &
7515 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7516 last_color_export = 0;
7517 } else {
7518 for (i = 0; i < 8; i++)
7519 if (colors_written & (1 << i) &&
7520 (spi_format >> (i * 4)) & 0xf)
7521 last_color_export = i;
7522 }
7523 }
7524
7525 while (colors_written) {
7526 LLVMValueRef color[4];
7527 int mrt = u_bit_scan(&colors_written);
7528
7529 for (i = 0; i < 4; i++)
7530 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7531
7532 si_export_mrt_color(bld_base, color, mrt,
7533 fninfo.num_params - 1,
7534 mrt == last_color_export, &exp);
7535 }
7536
7537 /* Process depth, stencil, samplemask. */
7538 if (key->ps_epilog.writes_z)
7539 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7540 if (key->ps_epilog.writes_stencil)
7541 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7542 if (key->ps_epilog.writes_samplemask)
7543 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7544
7545 if (depth || stencil || samplemask)
7546 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7547 else if (last_color_export == -1)
7548 si_export_null(bld_base);
7549
7550 if (exp.num)
7551 si_emit_ps_exports(ctx, &exp);
7552
7553 /* Compile. */
7554 LLVMBuildRetVoid(ctx->ac.builder);
7555 }
7556
7557 /**
7558 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7559 */
7560 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7561 LLVMTargetMachineRef tm,
7562 struct si_shader *shader,
7563 struct pipe_debug_callback *debug)
7564 {
7565 union si_shader_part_key prolog_key;
7566 union si_shader_part_key epilog_key;
7567
7568 /* Get the prolog. */
7569 si_get_ps_prolog_key(shader, &prolog_key, true);
7570
7571 /* The prolog is a no-op if these aren't set. */
7572 if (si_need_ps_prolog(&prolog_key)) {
7573 shader->prolog =
7574 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7575 PIPE_SHADER_FRAGMENT, true,
7576 &prolog_key, tm, debug,
7577 si_build_ps_prolog_function,
7578 "Fragment Shader Prolog");
7579 if (!shader->prolog)
7580 return false;
7581 }
7582
7583 /* Get the epilog. */
7584 si_get_ps_epilog_key(shader, &epilog_key);
7585
7586 shader->epilog =
7587 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7588 PIPE_SHADER_FRAGMENT, false,
7589 &epilog_key, tm, debug,
7590 si_build_ps_epilog_function,
7591 "Fragment Shader Epilog");
7592 if (!shader->epilog)
7593 return false;
7594
7595 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7596 if (shader->key.part.ps.prolog.poly_stipple) {
7597 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7598 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7599 }
7600
7601 /* Set up the enable bits for per-sample shading if needed. */
7602 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7603 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7604 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7605 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7606 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7607 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7608 }
7609 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7610 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7611 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7612 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7613 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7614 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7615 }
7616 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7617 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7618 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7619 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7620 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7621 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7622 }
7623 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7624 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7625 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7626 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7627 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7628 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7629 }
7630
7631 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7632 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7633 !(shader->config.spi_ps_input_ena & 0xf)) {
7634 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7635 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7636 }
7637
7638 /* At least one pair of interpolation weights must be enabled. */
7639 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7640 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7641 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7642 }
7643
7644 /* Samplemask fixup requires the sample ID. */
7645 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7646 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7647 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7648 }
7649
7650 /* The sample mask input is always enabled, because the API shader always
7651 * passes it through to the epilog. Disable it here if it's unused.
7652 */
7653 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7654 !shader->selector->info.reads_samplemask)
7655 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7656
7657 return true;
7658 }
7659
7660 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7661 unsigned *lds_size)
7662 {
7663 /* SPI barrier management bug:
7664 * Make sure we have at least 4k of LDS in use to avoid the bug.
7665 * It applies to workgroup sizes of more than one wavefront.
7666 */
7667 if (sscreen->info.family == CHIP_BONAIRE ||
7668 sscreen->info.family == CHIP_KABINI ||
7669 sscreen->info.family == CHIP_MULLINS)
7670 *lds_size = MAX2(*lds_size, 8);
7671 }
7672
7673 static void si_fix_resource_usage(struct si_screen *sscreen,
7674 struct si_shader *shader)
7675 {
7676 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7677
7678 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7679
7680 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7681 si_get_max_workgroup_size(shader) > 64) {
7682 si_multiwave_lds_size_workaround(sscreen,
7683 &shader->config.lds_size);
7684 }
7685 }
7686
7687 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7688 struct si_shader *shader,
7689 struct pipe_debug_callback *debug)
7690 {
7691 struct si_shader_selector *sel = shader->selector;
7692 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7693 int r;
7694
7695 /* LS, ES, VS are compiled on demand if the main part hasn't been
7696 * compiled for that stage.
7697 *
7698 * Vertex shaders are compiled on demand when a vertex fetch
7699 * workaround must be applied.
7700 */
7701 if (shader->is_monolithic) {
7702 /* Monolithic shader (compiled as a whole, has many variants,
7703 * may take a long time to compile).
7704 */
7705 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7706 if (r)
7707 return r;
7708 } else {
7709 /* The shader consists of several parts:
7710 *
7711 * - the middle part is the user shader, it has 1 variant only
7712 * and it was compiled during the creation of the shader
7713 * selector
7714 * - the prolog part is inserted at the beginning
7715 * - the epilog part is inserted at the end
7716 *
7717 * The prolog and epilog have many (but simple) variants.
7718 *
7719 * Starting with gfx9, geometry and tessellation control
7720 * shaders also contain the prolog and user shader parts of
7721 * the previous shader stage.
7722 */
7723
7724 if (!mainp)
7725 return -1;
7726
7727 /* Copy the compiled TGSI shader data over. */
7728 shader->is_binary_shared = true;
7729 shader->binary = mainp->binary;
7730 shader->config = mainp->config;
7731 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7732 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7733 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7734 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
7735 memcpy(shader->info.vs_output_param_offset,
7736 mainp->info.vs_output_param_offset,
7737 sizeof(mainp->info.vs_output_param_offset));
7738 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7739 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7740 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7741
7742 /* Select prologs and/or epilogs. */
7743 switch (sel->type) {
7744 case PIPE_SHADER_VERTEX:
7745 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7746 return -1;
7747 break;
7748 case PIPE_SHADER_TESS_CTRL:
7749 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7750 return -1;
7751 break;
7752 case PIPE_SHADER_TESS_EVAL:
7753 break;
7754 case PIPE_SHADER_GEOMETRY:
7755 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
7756 return -1;
7757 break;
7758 case PIPE_SHADER_FRAGMENT:
7759 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7760 return -1;
7761
7762 /* Make sure we have at least as many VGPRs as there
7763 * are allocated inputs.
7764 */
7765 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7766 shader->info.num_input_vgprs);
7767 break;
7768 }
7769
7770 /* Update SGPR and VGPR counts. */
7771 if (shader->prolog) {
7772 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7773 shader->prolog->config.num_sgprs);
7774 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7775 shader->prolog->config.num_vgprs);
7776 }
7777 if (shader->previous_stage) {
7778 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7779 shader->previous_stage->config.num_sgprs);
7780 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7781 shader->previous_stage->config.num_vgprs);
7782 shader->config.spilled_sgprs =
7783 MAX2(shader->config.spilled_sgprs,
7784 shader->previous_stage->config.spilled_sgprs);
7785 shader->config.spilled_vgprs =
7786 MAX2(shader->config.spilled_vgprs,
7787 shader->previous_stage->config.spilled_vgprs);
7788 shader->config.private_mem_vgprs =
7789 MAX2(shader->config.private_mem_vgprs,
7790 shader->previous_stage->config.private_mem_vgprs);
7791 shader->config.scratch_bytes_per_wave =
7792 MAX2(shader->config.scratch_bytes_per_wave,
7793 shader->previous_stage->config.scratch_bytes_per_wave);
7794 shader->info.uses_instanceid |=
7795 shader->previous_stage->info.uses_instanceid;
7796 }
7797 if (shader->prolog2) {
7798 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7799 shader->prolog2->config.num_sgprs);
7800 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7801 shader->prolog2->config.num_vgprs);
7802 }
7803 if (shader->epilog) {
7804 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7805 shader->epilog->config.num_sgprs);
7806 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7807 shader->epilog->config.num_vgprs);
7808 }
7809 }
7810
7811 si_fix_resource_usage(sscreen, shader);
7812 si_shader_dump(sscreen, shader, debug, sel->info.processor,
7813 stderr, true);
7814
7815 /* Upload. */
7816 r = si_shader_binary_upload(sscreen, shader);
7817 if (r) {
7818 fprintf(stderr, "LLVM failed to upload shader\n");
7819 return r;
7820 }
7821
7822 return 0;
7823 }
7824
7825 void si_shader_destroy(struct si_shader *shader)
7826 {
7827 if (shader->scratch_bo)
7828 r600_resource_reference(&shader->scratch_bo, NULL);
7829
7830 r600_resource_reference(&shader->bo, NULL);
7831
7832 if (!shader->is_binary_shared)
7833 ac_shader_binary_clean(&shader->binary);
7834
7835 free(shader->shader_log);
7836 }