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[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_dump.h"
45
46 #include "si_pipe.h"
47 #include "si_shader.h"
48 #include "sid.h"
49
50 #include <errno.h>
51
52 static const char *scratch_rsrc_dword0_symbol =
53 "SCRATCH_RSRC_DWORD0";
54
55 static const char *scratch_rsrc_dword1_symbol =
56 "SCRATCH_RSRC_DWORD1";
57
58 struct si_shader_output_values
59 {
60 LLVMValueRef values[4];
61 unsigned name;
62 unsigned sid;
63 };
64
65 struct si_shader_context
66 {
67 struct radeon_llvm_context radeon_bld;
68 struct si_shader *shader;
69 struct si_screen *screen;
70 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
71 bool is_gs_copy_shader;
72 int param_streamout_config;
73 int param_streamout_write_index;
74 int param_streamout_offset[4];
75 int param_vertex_id;
76 int param_rel_auto_id;
77 int param_vs_prim_id;
78 int param_instance_id;
79 int param_tes_u;
80 int param_tes_v;
81 int param_tes_rel_patch_id;
82 int param_tes_patch_id;
83 int param_es2gs_offset;
84 LLVMTargetMachineRef tm;
85 LLVMValueRef const_md;
86 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
87 LLVMValueRef lds;
88 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
89 LLVMValueRef sampler_views[SI_NUM_SAMPLER_VIEWS];
90 LLVMValueRef sampler_states[SI_NUM_SAMPLER_STATES];
91 LLVMValueRef so_buffers[4];
92 LLVMValueRef esgs_ring;
93 LLVMValueRef gsvs_ring[4];
94 LLVMValueRef gs_next_vertex[4];
95 };
96
97 static struct si_shader_context * si_shader_context(
98 struct lp_build_tgsi_context * bld_base)
99 {
100 return (struct si_shader_context *)bld_base;
101 }
102
103
104 #define PERSPECTIVE_BASE 0
105 #define LINEAR_BASE 9
106
107 #define SAMPLE_OFFSET 0
108 #define CENTER_OFFSET 2
109 #define CENTROID_OFSET 4
110
111 #define USE_SGPR_MAX_SUFFIX_LEN 5
112 #define CONST_ADDR_SPACE 2
113 #define LOCAL_ADDR_SPACE 3
114 #define USER_SGPR_ADDR_SPACE 8
115
116
117 #define SENDMSG_GS 2
118 #define SENDMSG_GS_DONE 3
119
120 #define SENDMSG_GS_OP_NOP (0 << 4)
121 #define SENDMSG_GS_OP_CUT (1 << 4)
122 #define SENDMSG_GS_OP_EMIT (2 << 4)
123 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
124
125 /**
126 * Returns a unique index for a semantic name and index. The index must be
127 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
128 * calculated.
129 */
130 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
131 {
132 switch (semantic_name) {
133 case TGSI_SEMANTIC_POSITION:
134 return 0;
135 case TGSI_SEMANTIC_PSIZE:
136 return 1;
137 case TGSI_SEMANTIC_CLIPDIST:
138 assert(index <= 1);
139 return 2 + index;
140 case TGSI_SEMANTIC_GENERIC:
141 if (index <= 63-4)
142 return 4 + index;
143 else
144 /* same explanation as in the default statement,
145 * the only user hitting this is st/nine.
146 */
147 return 0;
148
149 /* patch indices are completely separate and thus start from 0 */
150 case TGSI_SEMANTIC_TESSOUTER:
151 return 0;
152 case TGSI_SEMANTIC_TESSINNER:
153 return 1;
154 case TGSI_SEMANTIC_PATCH:
155 return 2 + index;
156
157 default:
158 /* Don't fail here. The result of this function is only used
159 * for LS, TCS, TES, and GS, where legacy GL semantics can't
160 * occur, but this function is called for all vertex shaders
161 * before it's known whether LS will be compiled or not.
162 */
163 return 0;
164 }
165 }
166
167 /**
168 * Get the value of a shader input parameter and extract a bitfield.
169 */
170 static LLVMValueRef unpack_param(struct si_shader_context *si_shader_ctx,
171 unsigned param, unsigned rshift,
172 unsigned bitwidth)
173 {
174 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
175 LLVMValueRef value = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
176 param);
177
178 if (rshift)
179 value = LLVMBuildLShr(gallivm->builder, value,
180 lp_build_const_int32(gallivm, rshift), "");
181
182 if (rshift + bitwidth < 32) {
183 unsigned mask = (1 << bitwidth) - 1;
184 value = LLVMBuildAnd(gallivm->builder, value,
185 lp_build_const_int32(gallivm, mask), "");
186 }
187
188 return value;
189 }
190
191 static LLVMValueRef get_rel_patch_id(struct si_shader_context *si_shader_ctx)
192 {
193 switch (si_shader_ctx->type) {
194 case TGSI_PROCESSOR_TESS_CTRL:
195 return unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 0, 8);
196
197 case TGSI_PROCESSOR_TESS_EVAL:
198 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
199 si_shader_ctx->param_tes_rel_patch_id);
200
201 default:
202 assert(0);
203 return NULL;
204 }
205 }
206
207 /* Tessellation shaders pass outputs to the next shader using LDS.
208 *
209 * LS outputs = TCS inputs
210 * TCS outputs = TES inputs
211 *
212 * The LDS layout is:
213 * - TCS inputs for patch 0
214 * - TCS inputs for patch 1
215 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
216 * - ...
217 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
218 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
219 * - TCS outputs for patch 1
220 * - Per-patch TCS outputs for patch 1
221 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
222 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
223 * - ...
224 *
225 * All three shaders VS(LS), TCS, TES share the same LDS space.
226 */
227
228 static LLVMValueRef
229 get_tcs_in_patch_stride(struct si_shader_context *si_shader_ctx)
230 {
231 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX)
232 return unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
233 else if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
234 return unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
235 else {
236 assert(0);
237 return NULL;
238 }
239 }
240
241 static LLVMValueRef
242 get_tcs_out_patch_stride(struct si_shader_context *si_shader_ctx)
243 {
244 return unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
245 }
246
247 static LLVMValueRef
248 get_tcs_out_patch0_offset(struct si_shader_context *si_shader_ctx)
249 {
250 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
251 unpack_param(si_shader_ctx,
252 SI_PARAM_TCS_OUT_OFFSETS,
253 0, 16),
254 4);
255 }
256
257 static LLVMValueRef
258 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *si_shader_ctx)
259 {
260 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
261 unpack_param(si_shader_ctx,
262 SI_PARAM_TCS_OUT_OFFSETS,
263 16, 16),
264 4);
265 }
266
267 static LLVMValueRef
268 get_tcs_in_current_patch_offset(struct si_shader_context *si_shader_ctx)
269 {
270 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
271 LLVMValueRef patch_stride = get_tcs_in_patch_stride(si_shader_ctx);
272 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
273
274 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
275 }
276
277 static LLVMValueRef
278 get_tcs_out_current_patch_offset(struct si_shader_context *si_shader_ctx)
279 {
280 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
281 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(si_shader_ctx);
282 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
283 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
284
285 return LLVMBuildAdd(gallivm->builder, patch0_offset,
286 LLVMBuildMul(gallivm->builder, patch_stride,
287 rel_patch_id, ""),
288 "");
289 }
290
291 static LLVMValueRef
292 get_tcs_out_current_patch_data_offset(struct si_shader_context *si_shader_ctx)
293 {
294 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
295 LLVMValueRef patch0_patch_data_offset =
296 get_tcs_out_patch0_patch_data_offset(si_shader_ctx);
297 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
298 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
299
300 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
301 LLVMBuildMul(gallivm->builder, patch_stride,
302 rel_patch_id, ""),
303 "");
304 }
305
306 static void build_indexed_store(struct si_shader_context *si_shader_ctx,
307 LLVMValueRef base_ptr, LLVMValueRef index,
308 LLVMValueRef value)
309 {
310 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
311 struct gallivm_state *gallivm = bld_base->base.gallivm;
312 LLVMValueRef indices[2], pointer;
313
314 indices[0] = bld_base->uint_bld.zero;
315 indices[1] = index;
316
317 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
318 LLVMBuildStore(gallivm->builder, value, pointer);
319 }
320
321 /**
322 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
323 * It's equivalent to doing a load from &base_ptr[index].
324 *
325 * \param base_ptr Where the array starts.
326 * \param index The element index into the array.
327 */
328 static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
329 LLVMValueRef base_ptr, LLVMValueRef index)
330 {
331 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
332 struct gallivm_state *gallivm = bld_base->base.gallivm;
333 LLVMValueRef indices[2], pointer;
334
335 indices[0] = bld_base->uint_bld.zero;
336 indices[1] = index;
337
338 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
339 return LLVMBuildLoad(gallivm->builder, pointer, "");
340 }
341
342 /**
343 * Do a load from &base_ptr[index], but also add a flag that it's loading
344 * a constant.
345 */
346 static LLVMValueRef build_indexed_load_const(
347 struct si_shader_context * si_shader_ctx,
348 LLVMValueRef base_ptr, LLVMValueRef index)
349 {
350 LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
351 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
352 return result;
353 }
354
355 static LLVMValueRef get_instance_index_for_fetch(
356 struct radeon_llvm_context * radeon_bld,
357 unsigned divisor)
358 {
359 struct si_shader_context *si_shader_ctx =
360 si_shader_context(&radeon_bld->soa.bld_base);
361 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
362
363 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
364 si_shader_ctx->param_instance_id);
365
366 /* The division must be done before START_INSTANCE is added. */
367 if (divisor > 1)
368 result = LLVMBuildUDiv(gallivm->builder, result,
369 lp_build_const_int32(gallivm, divisor), "");
370
371 return LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
372 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
373 }
374
375 static void declare_input_vs(
376 struct radeon_llvm_context *radeon_bld,
377 unsigned input_index,
378 const struct tgsi_full_declaration *decl)
379 {
380 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
381 struct gallivm_state *gallivm = base->gallivm;
382 struct si_shader_context *si_shader_ctx =
383 si_shader_context(&radeon_bld->soa.bld_base);
384 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
385
386 unsigned chan;
387
388 LLVMValueRef t_list_ptr;
389 LLVMValueRef t_offset;
390 LLVMValueRef t_list;
391 LLVMValueRef attribute_offset;
392 LLVMValueRef buffer_index;
393 LLVMValueRef args[3];
394 LLVMTypeRef vec4_type;
395 LLVMValueRef input;
396
397 /* Load the T list */
398 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
399
400 t_offset = lp_build_const_int32(gallivm, input_index);
401
402 t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
403
404 /* Build the attribute offset */
405 attribute_offset = lp_build_const_int32(gallivm, 0);
406
407 if (divisor) {
408 /* Build index from instance ID, start instance and divisor */
409 si_shader_ctx->shader->uses_instanceid = true;
410 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
411 } else {
412 /* Load the buffer index for vertices. */
413 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
414 si_shader_ctx->param_vertex_id);
415 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
416 SI_PARAM_BASE_VERTEX);
417 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
418 }
419
420 vec4_type = LLVMVectorType(base->elem_type, 4);
421 args[0] = t_list;
422 args[1] = attribute_offset;
423 args[2] = buffer_index;
424 input = lp_build_intrinsic(gallivm->builder,
425 "llvm.SI.vs.load.input", vec4_type, args, 3,
426 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
427
428 /* Break up the vec4 into individual components */
429 for (chan = 0; chan < 4; chan++) {
430 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
431 /* XXX: Use a helper function for this. There is one in
432 * tgsi_llvm.c. */
433 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
434 LLVMBuildExtractElement(gallivm->builder,
435 input, llvm_chan, "");
436 }
437 }
438
439 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
440 unsigned swizzle)
441 {
442 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
443
444 if (swizzle > 0)
445 return bld_base->uint_bld.zero;
446
447 switch (si_shader_ctx->type) {
448 case TGSI_PROCESSOR_VERTEX:
449 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
450 si_shader_ctx->param_vs_prim_id);
451 case TGSI_PROCESSOR_TESS_CTRL:
452 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
453 SI_PARAM_PATCH_ID);
454 case TGSI_PROCESSOR_TESS_EVAL:
455 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
456 si_shader_ctx->param_tes_patch_id);
457 case TGSI_PROCESSOR_GEOMETRY:
458 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
459 SI_PARAM_PRIMITIVE_ID);
460 default:
461 assert(0);
462 return bld_base->uint_bld.zero;
463 }
464 }
465
466 /**
467 * Return the value of tgsi_ind_register for indexing.
468 * This is the indirect index with the constant offset added to it.
469 */
470 static LLVMValueRef get_indirect_index(struct si_shader_context *si_shader_ctx,
471 const struct tgsi_ind_register *ind,
472 int rel_index)
473 {
474 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
475 LLVMValueRef result;
476
477 result = si_shader_ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
478 result = LLVMBuildLoad(gallivm->builder, result, "");
479 result = LLVMBuildAdd(gallivm->builder, result,
480 lp_build_const_int32(gallivm, rel_index), "");
481 return result;
482 }
483
484 /**
485 * Calculate a dword address given an input or output register and a stride.
486 */
487 static LLVMValueRef get_dw_address(struct si_shader_context *si_shader_ctx,
488 const struct tgsi_full_dst_register *dst,
489 const struct tgsi_full_src_register *src,
490 LLVMValueRef vertex_dw_stride,
491 LLVMValueRef base_addr)
492 {
493 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
494 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
495 ubyte *name, *index, *array_first;
496 int first, param;
497 struct tgsi_full_dst_register reg;
498
499 /* Set the register description. The address computation is the same
500 * for sources and destinations. */
501 if (src) {
502 reg.Register.File = src->Register.File;
503 reg.Register.Index = src->Register.Index;
504 reg.Register.Indirect = src->Register.Indirect;
505 reg.Register.Dimension = src->Register.Dimension;
506 reg.Indirect = src->Indirect;
507 reg.Dimension = src->Dimension;
508 reg.DimIndirect = src->DimIndirect;
509 } else
510 reg = *dst;
511
512 /* If the register is 2-dimensional (e.g. an array of vertices
513 * in a primitive), calculate the base address of the vertex. */
514 if (reg.Register.Dimension) {
515 LLVMValueRef index;
516
517 if (reg.Dimension.Indirect)
518 index = get_indirect_index(si_shader_ctx, &reg.DimIndirect,
519 reg.Dimension.Index);
520 else
521 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
522
523 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
524 LLVMBuildMul(gallivm->builder, index,
525 vertex_dw_stride, ""), "");
526 }
527
528 /* Get information about the register. */
529 if (reg.Register.File == TGSI_FILE_INPUT) {
530 name = info->input_semantic_name;
531 index = info->input_semantic_index;
532 array_first = info->input_array_first;
533 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
534 name = info->output_semantic_name;
535 index = info->output_semantic_index;
536 array_first = info->output_array_first;
537 } else {
538 assert(0);
539 return NULL;
540 }
541
542 if (reg.Register.Indirect) {
543 /* Add the relative address of the element. */
544 LLVMValueRef ind_index;
545
546 if (reg.Indirect.ArrayID)
547 first = array_first[reg.Indirect.ArrayID];
548 else
549 first = reg.Register.Index;
550
551 ind_index = get_indirect_index(si_shader_ctx, &reg.Indirect,
552 reg.Register.Index - first);
553
554 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
555 LLVMBuildMul(gallivm->builder, ind_index,
556 lp_build_const_int32(gallivm, 4), ""), "");
557
558 param = si_shader_io_get_unique_index(name[first], index[first]);
559 } else {
560 param = si_shader_io_get_unique_index(name[reg.Register.Index],
561 index[reg.Register.Index]);
562 }
563
564 /* Add the base address of the element. */
565 return LLVMBuildAdd(gallivm->builder, base_addr,
566 lp_build_const_int32(gallivm, param * 4), "");
567 }
568
569 /**
570 * Load from LDS.
571 *
572 * \param type output value type
573 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
574 * \param dw_addr address in dwords
575 */
576 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
577 enum tgsi_opcode_type type, unsigned swizzle,
578 LLVMValueRef dw_addr)
579 {
580 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
581 struct gallivm_state *gallivm = bld_base->base.gallivm;
582 LLVMValueRef value;
583
584 if (swizzle == ~0) {
585 LLVMValueRef values[TGSI_NUM_CHANNELS];
586
587 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
588 values[chan] = lds_load(bld_base, type, chan, dw_addr);
589
590 return lp_build_gather_values(bld_base->base.gallivm, values,
591 TGSI_NUM_CHANNELS);
592 }
593
594 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
595 lp_build_const_int32(gallivm, swizzle));
596
597 value = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
598 if (type == TGSI_TYPE_DOUBLE) {
599 LLVMValueRef value2;
600 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
601 lp_build_const_int32(gallivm, swizzle + 1));
602 value2 = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
603 return radeon_llvm_emit_fetch_double(bld_base, value, value2);
604 }
605
606 return LLVMBuildBitCast(gallivm->builder, value,
607 tgsi2llvmtype(bld_base, type), "");
608 }
609
610 /**
611 * Store to LDS.
612 *
613 * \param swizzle offset (typically 0..3)
614 * \param dw_addr address in dwords
615 * \param value value to store
616 */
617 static void lds_store(struct lp_build_tgsi_context * bld_base,
618 unsigned swizzle, LLVMValueRef dw_addr,
619 LLVMValueRef value)
620 {
621 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
622 struct gallivm_state *gallivm = bld_base->base.gallivm;
623
624 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
625 lp_build_const_int32(gallivm, swizzle));
626
627 value = LLVMBuildBitCast(gallivm->builder, value,
628 LLVMInt32TypeInContext(gallivm->context), "");
629 build_indexed_store(si_shader_ctx, si_shader_ctx->lds,
630 dw_addr, value);
631 }
632
633 static LLVMValueRef fetch_input_tcs(
634 struct lp_build_tgsi_context *bld_base,
635 const struct tgsi_full_src_register *reg,
636 enum tgsi_opcode_type type, unsigned swizzle)
637 {
638 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
639 LLVMValueRef dw_addr, stride;
640
641 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
642 dw_addr = get_tcs_in_current_patch_offset(si_shader_ctx);
643 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
644
645 return lds_load(bld_base, type, swizzle, dw_addr);
646 }
647
648 static LLVMValueRef fetch_output_tcs(
649 struct lp_build_tgsi_context *bld_base,
650 const struct tgsi_full_src_register *reg,
651 enum tgsi_opcode_type type, unsigned swizzle)
652 {
653 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
654 LLVMValueRef dw_addr, stride;
655
656 if (reg->Register.Dimension) {
657 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
658 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
659 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
660 } else {
661 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
662 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
663 }
664
665 return lds_load(bld_base, type, swizzle, dw_addr);
666 }
667
668 static LLVMValueRef fetch_input_tes(
669 struct lp_build_tgsi_context *bld_base,
670 const struct tgsi_full_src_register *reg,
671 enum tgsi_opcode_type type, unsigned swizzle)
672 {
673 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
674 LLVMValueRef dw_addr, stride;
675
676 if (reg->Register.Dimension) {
677 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
678 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
679 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
680 } else {
681 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
682 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
683 }
684
685 return lds_load(bld_base, type, swizzle, dw_addr);
686 }
687
688 static void store_output_tcs(struct lp_build_tgsi_context * bld_base,
689 const struct tgsi_full_instruction * inst,
690 const struct tgsi_opcode_info * info,
691 LLVMValueRef dst[4])
692 {
693 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
694 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
695 unsigned chan_index;
696 LLVMValueRef dw_addr, stride;
697
698 /* Only handle per-patch and per-vertex outputs here.
699 * Vectors will be lowered to scalars and this function will be called again.
700 */
701 if (reg->Register.File != TGSI_FILE_OUTPUT ||
702 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
703 radeon_llvm_emit_store(bld_base, inst, info, dst);
704 return;
705 }
706
707 if (reg->Register.Dimension) {
708 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
709 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
710 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, stride, dw_addr);
711 } else {
712 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
713 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, NULL, dw_addr);
714 }
715
716 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
717 LLVMValueRef value = dst[chan_index];
718
719 if (inst->Instruction.Saturate)
720 value = radeon_llvm_saturate(bld_base, value);
721
722 lds_store(bld_base, chan_index, dw_addr, value);
723 }
724 }
725
726 static LLVMValueRef fetch_input_gs(
727 struct lp_build_tgsi_context *bld_base,
728 const struct tgsi_full_src_register *reg,
729 enum tgsi_opcode_type type,
730 unsigned swizzle)
731 {
732 struct lp_build_context *base = &bld_base->base;
733 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
734 struct si_shader *shader = si_shader_ctx->shader;
735 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
736 struct gallivm_state *gallivm = base->gallivm;
737 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
738 LLVMValueRef vtx_offset;
739 LLVMValueRef args[9];
740 unsigned vtx_offset_param;
741 struct tgsi_shader_info *info = &shader->selector->info;
742 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
743 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
744 unsigned param;
745 LLVMValueRef value;
746
747 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
748 return get_primitive_id(bld_base, swizzle);
749
750 if (!reg->Register.Dimension)
751 return NULL;
752
753 if (swizzle == ~0) {
754 LLVMValueRef values[TGSI_NUM_CHANNELS];
755 unsigned chan;
756 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
757 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
758 }
759 return lp_build_gather_values(bld_base->base.gallivm, values,
760 TGSI_NUM_CHANNELS);
761 }
762
763 /* Get the vertex offset parameter */
764 vtx_offset_param = reg->Dimension.Index;
765 if (vtx_offset_param < 2) {
766 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
767 } else {
768 assert(vtx_offset_param < 6);
769 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
770 }
771 vtx_offset = lp_build_mul_imm(uint,
772 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
773 vtx_offset_param),
774 4);
775
776 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
777 args[0] = si_shader_ctx->esgs_ring;
778 args[1] = vtx_offset;
779 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
780 args[3] = uint->zero;
781 args[4] = uint->one; /* OFFEN */
782 args[5] = uint->zero; /* IDXEN */
783 args[6] = uint->one; /* GLC */
784 args[7] = uint->zero; /* SLC */
785 args[8] = uint->zero; /* TFE */
786
787 value = lp_build_intrinsic(gallivm->builder,
788 "llvm.SI.buffer.load.dword.i32.i32",
789 i32, args, 9,
790 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
791 if (type == TGSI_TYPE_DOUBLE) {
792 LLVMValueRef value2;
793 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
794 value2 = lp_build_intrinsic(gallivm->builder,
795 "llvm.SI.buffer.load.dword.i32.i32",
796 i32, args, 9,
797 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
798 return radeon_llvm_emit_fetch_double(bld_base,
799 value, value2);
800 }
801 return LLVMBuildBitCast(gallivm->builder,
802 value,
803 tgsi2llvmtype(bld_base, type), "");
804 }
805
806 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
807 {
808 switch (interpolate) {
809 case TGSI_INTERPOLATE_CONSTANT:
810 return 0;
811
812 case TGSI_INTERPOLATE_LINEAR:
813 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
814 return SI_PARAM_LINEAR_SAMPLE;
815 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
816 return SI_PARAM_LINEAR_CENTROID;
817 else
818 return SI_PARAM_LINEAR_CENTER;
819 break;
820 case TGSI_INTERPOLATE_COLOR:
821 case TGSI_INTERPOLATE_PERSPECTIVE:
822 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
823 return SI_PARAM_PERSP_SAMPLE;
824 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
825 return SI_PARAM_PERSP_CENTROID;
826 else
827 return SI_PARAM_PERSP_CENTER;
828 break;
829 default:
830 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
831 return -1;
832 }
833 }
834
835 /* This shouldn't be used by explicit INTERP opcodes. */
836 static unsigned select_interp_param(struct si_shader_context *si_shader_ctx,
837 unsigned param)
838 {
839 if (!si_shader_ctx->shader->key.ps.force_persample_interp)
840 return param;
841
842 /* If the shader doesn't use center/centroid, just return the parameter.
843 *
844 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
845 * switch between center/centroid and sample without shader changes.
846 */
847 switch (param) {
848 case SI_PARAM_PERSP_CENTROID:
849 case SI_PARAM_PERSP_CENTER:
850 return SI_PARAM_PERSP_SAMPLE;
851
852 case SI_PARAM_LINEAR_CENTROID:
853 case SI_PARAM_LINEAR_CENTER:
854 return SI_PARAM_LINEAR_SAMPLE;
855
856 default:
857 return param;
858 }
859 }
860
861 /**
862 * Interpolate a fragment shader input.
863 *
864 * @param si_shader_ctx context
865 * @param input_index index of the input in hardware
866 * @param semantic_name TGSI_SEMANTIC_*
867 * @param semantic_index semantic index
868 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
869 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
870 * @param interp_param interpolation weights (i,j)
871 * @param prim_mask SI_PARAM_PRIM_MASK
872 * @param face SI_PARAM_FRONT_FACE
873 * @param result the return value (4 components)
874 */
875 static void interp_fs_input(struct si_shader_context *si_shader_ctx,
876 unsigned input_index,
877 unsigned semantic_name,
878 unsigned semantic_index,
879 unsigned num_interp_inputs,
880 unsigned colors_read_mask,
881 LLVMValueRef interp_param,
882 LLVMValueRef prim_mask,
883 LLVMValueRef face,
884 LLVMValueRef result[4])
885 {
886 struct lp_build_context *base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
887 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
888 struct gallivm_state *gallivm = base->gallivm;
889 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
890 const char * intr_name;
891 LLVMValueRef attr_number;
892
893 unsigned chan;
894
895 attr_number = lp_build_const_int32(gallivm, input_index);
896
897 /* fs.constant returns the param from the middle vertex, so it's not
898 * really useful for flat shading. It's meant to be used for custom
899 * interpolation (but the intrinsic can't fetch from the other two
900 * vertices).
901 *
902 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
903 * to do the right thing. The only reason we use fs.constant is that
904 * fs.interp cannot be used on integers, because they can be equal
905 * to NaN.
906 */
907 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
908
909 if (semantic_name == TGSI_SEMANTIC_COLOR &&
910 si_shader_ctx->shader->key.ps.color_two_side) {
911 LLVMValueRef args[4];
912 LLVMValueRef is_face_positive;
913 LLVMValueRef back_attr_number;
914
915 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
916 * otherwise it's at offset "num_inputs".
917 */
918 unsigned back_attr_offset = num_interp_inputs;
919 if (semantic_index == 1 && colors_read_mask & 0xf)
920 back_attr_offset += 1;
921
922 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
923
924 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
925 face, uint->zero, "");
926
927 args[2] = prim_mask;
928 args[3] = interp_param;
929 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
930 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
931 LLVMValueRef front, back;
932
933 args[0] = llvm_chan;
934 args[1] = attr_number;
935 front = lp_build_intrinsic(gallivm->builder, intr_name,
936 input_type, args, args[3] ? 4 : 3,
937 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
938
939 args[1] = back_attr_number;
940 back = lp_build_intrinsic(gallivm->builder, intr_name,
941 input_type, args, args[3] ? 4 : 3,
942 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
943
944 result[chan] = LLVMBuildSelect(gallivm->builder,
945 is_face_positive,
946 front,
947 back,
948 "");
949 }
950 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
951 LLVMValueRef args[4];
952
953 args[0] = uint->zero;
954 args[1] = attr_number;
955 args[2] = prim_mask;
956 args[3] = interp_param;
957 result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
958 input_type, args, args[3] ? 4 : 3,
959 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
960 result[1] =
961 result[2] = lp_build_const_float(gallivm, 0.0f);
962 result[3] = lp_build_const_float(gallivm, 1.0f);
963 } else {
964 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
965 LLVMValueRef args[4];
966 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
967
968 args[0] = llvm_chan;
969 args[1] = attr_number;
970 args[2] = prim_mask;
971 args[3] = interp_param;
972 result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
973 input_type, args, args[3] ? 4 : 3,
974 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
975 }
976 }
977 }
978
979 static void declare_input_fs(
980 struct radeon_llvm_context *radeon_bld,
981 unsigned input_index,
982 const struct tgsi_full_declaration *decl)
983 {
984 struct si_shader_context *si_shader_ctx =
985 si_shader_context(&radeon_bld->soa.bld_base);
986 struct si_shader *shader = si_shader_ctx->shader;
987 LLVMValueRef main_fn = radeon_bld->main_fn;
988 LLVMValueRef interp_param = NULL;
989 int interp_param_idx;
990
991 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
992 decl->Interp.Location);
993 if (interp_param_idx == -1)
994 return;
995 else if (interp_param_idx) {
996 interp_param_idx = select_interp_param(si_shader_ctx,
997 interp_param_idx);
998 interp_param = LLVMGetParam(main_fn, interp_param_idx);
999 }
1000
1001 interp_fs_input(si_shader_ctx, input_index, decl->Semantic.Name,
1002 decl->Semantic.Index, shader->selector->info.num_inputs,
1003 shader->selector->info.colors_read, interp_param,
1004 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1005 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1006 &radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)]);
1007 }
1008
1009 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1010 {
1011 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1012 SI_PARAM_ANCILLARY, 8, 4);
1013 }
1014
1015 /**
1016 * Load a dword from a constant buffer.
1017 */
1018 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1019 LLVMValueRef offset, LLVMTypeRef return_type)
1020 {
1021 LLVMValueRef args[2] = {resource, offset};
1022
1023 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1024 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1025 }
1026
1027 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1028 {
1029 struct si_shader_context *si_shader_ctx =
1030 si_shader_context(&radeon_bld->soa.bld_base);
1031 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1032 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1033 LLVMBuilderRef builder = gallivm->builder;
1034 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1035 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
1036 LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
1037
1038 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1039 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1040 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1041
1042 LLVMValueRef pos[4] = {
1043 buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
1044 buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
1045 lp_build_const_float(gallivm, 0),
1046 lp_build_const_float(gallivm, 0)
1047 };
1048
1049 return lp_build_gather_values(gallivm, pos, 4);
1050 }
1051
1052 static void declare_system_value(
1053 struct radeon_llvm_context * radeon_bld,
1054 unsigned index,
1055 const struct tgsi_full_declaration *decl)
1056 {
1057 struct si_shader_context *si_shader_ctx =
1058 si_shader_context(&radeon_bld->soa.bld_base);
1059 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1060 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1061 LLVMValueRef value = 0;
1062
1063 switch (decl->Semantic.Name) {
1064 case TGSI_SEMANTIC_INSTANCEID:
1065 value = LLVMGetParam(radeon_bld->main_fn,
1066 si_shader_ctx->param_instance_id);
1067 break;
1068
1069 case TGSI_SEMANTIC_VERTEXID:
1070 value = LLVMBuildAdd(gallivm->builder,
1071 LLVMGetParam(radeon_bld->main_fn,
1072 si_shader_ctx->param_vertex_id),
1073 LLVMGetParam(radeon_bld->main_fn,
1074 SI_PARAM_BASE_VERTEX), "");
1075 break;
1076
1077 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1078 value = LLVMGetParam(radeon_bld->main_fn,
1079 si_shader_ctx->param_vertex_id);
1080 break;
1081
1082 case TGSI_SEMANTIC_BASEVERTEX:
1083 value = LLVMGetParam(radeon_bld->main_fn,
1084 SI_PARAM_BASE_VERTEX);
1085 break;
1086
1087 case TGSI_SEMANTIC_INVOCATIONID:
1088 if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
1089 value = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1090 else if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY)
1091 value = LLVMGetParam(radeon_bld->main_fn,
1092 SI_PARAM_GS_INSTANCE_ID);
1093 else
1094 assert(!"INVOCATIONID not implemented");
1095 break;
1096
1097 case TGSI_SEMANTIC_POSITION:
1098 {
1099 LLVMValueRef pos[4] = {
1100 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1101 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1102 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1103 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1104 LLVMGetParam(radeon_bld->main_fn,
1105 SI_PARAM_POS_W_FLOAT)),
1106 };
1107 value = lp_build_gather_values(gallivm, pos, 4);
1108 break;
1109 }
1110
1111 case TGSI_SEMANTIC_FACE:
1112 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1113 break;
1114
1115 case TGSI_SEMANTIC_SAMPLEID:
1116 value = get_sample_id(radeon_bld);
1117 break;
1118
1119 case TGSI_SEMANTIC_SAMPLEPOS: {
1120 LLVMValueRef pos[4] = {
1121 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1122 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1123 lp_build_const_float(gallivm, 0),
1124 lp_build_const_float(gallivm, 0)
1125 };
1126 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1127 TGSI_OPCODE_FRC, pos[0]);
1128 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1129 TGSI_OPCODE_FRC, pos[1]);
1130 value = lp_build_gather_values(gallivm, pos, 4);
1131 break;
1132 }
1133
1134 case TGSI_SEMANTIC_SAMPLEMASK:
1135 /* This can only occur with the OpenGL Core profile, which
1136 * doesn't support smoothing.
1137 */
1138 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1139 break;
1140
1141 case TGSI_SEMANTIC_TESSCOORD:
1142 {
1143 LLVMValueRef coord[4] = {
1144 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_u),
1145 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_v),
1146 bld->zero,
1147 bld->zero
1148 };
1149
1150 /* For triangles, the vector should be (u, v, 1-u-v). */
1151 if (si_shader_ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1152 PIPE_PRIM_TRIANGLES)
1153 coord[2] = lp_build_sub(bld, bld->one,
1154 lp_build_add(bld, coord[0], coord[1]));
1155
1156 value = lp_build_gather_values(gallivm, coord, 4);
1157 break;
1158 }
1159
1160 case TGSI_SEMANTIC_VERTICESIN:
1161 value = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1162 break;
1163
1164 case TGSI_SEMANTIC_TESSINNER:
1165 case TGSI_SEMANTIC_TESSOUTER:
1166 {
1167 LLVMValueRef dw_addr;
1168 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1169
1170 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1171 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1172 lp_build_const_int32(gallivm, param * 4), "");
1173
1174 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1175 ~0, dw_addr);
1176 break;
1177 }
1178
1179 case TGSI_SEMANTIC_PRIMID:
1180 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1181 break;
1182
1183 default:
1184 assert(!"unknown system value");
1185 return;
1186 }
1187
1188 radeon_bld->system_values[index] = value;
1189 }
1190
1191 static LLVMValueRef fetch_constant(
1192 struct lp_build_tgsi_context * bld_base,
1193 const struct tgsi_full_src_register *reg,
1194 enum tgsi_opcode_type type,
1195 unsigned swizzle)
1196 {
1197 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1198 struct lp_build_context * base = &bld_base->base;
1199 const struct tgsi_ind_register *ireg = &reg->Indirect;
1200 unsigned buf, idx;
1201
1202 LLVMValueRef addr, bufp;
1203 LLVMValueRef result;
1204
1205 if (swizzle == LP_CHAN_ALL) {
1206 unsigned chan;
1207 LLVMValueRef values[4];
1208 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1209 values[chan] = fetch_constant(bld_base, reg, type, chan);
1210
1211 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1212 }
1213
1214 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1215 idx = reg->Register.Index * 4 + swizzle;
1216
1217 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1218 if (type != TGSI_TYPE_DOUBLE)
1219 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
1220 else {
1221 return radeon_llvm_emit_fetch_double(bld_base,
1222 si_shader_ctx->constants[buf][idx],
1223 si_shader_ctx->constants[buf][idx + 1]);
1224 }
1225 }
1226
1227 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1228 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1229 LLVMValueRef index;
1230 index = get_indirect_index(si_shader_ctx, &reg->DimIndirect,
1231 reg->Dimension.Index);
1232 bufp = build_indexed_load_const(si_shader_ctx, ptr, index);
1233 } else
1234 bufp = si_shader_ctx->const_buffers[buf];
1235
1236 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1237 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1238 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1239 addr = lp_build_add(&bld_base->uint_bld, addr,
1240 lp_build_const_int32(base->gallivm, idx * 4));
1241
1242 result = buffer_load_const(base->gallivm->builder, bufp,
1243 addr, bld_base->base.elem_type);
1244
1245 if (type != TGSI_TYPE_DOUBLE)
1246 result = bitcast(bld_base, type, result);
1247 else {
1248 LLVMValueRef addr2, result2;
1249 addr2 = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1250 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1251 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1252 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1253 lp_build_const_int32(base->gallivm, idx * 4));
1254
1255 result2 = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_buffers[buf],
1256 addr2, bld_base->base.elem_type);
1257
1258 result = radeon_llvm_emit_fetch_double(bld_base,
1259 result, result2);
1260 }
1261 return result;
1262 }
1263
1264 /* Upper 16 bits must be zero. */
1265 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1266 LLVMValueRef val[2])
1267 {
1268 return LLVMBuildOr(gallivm->builder, val[0],
1269 LLVMBuildShl(gallivm->builder, val[1],
1270 lp_build_const_int32(gallivm, 16),
1271 ""), "");
1272 }
1273
1274 /* Upper 16 bits are ignored and will be dropped. */
1275 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1276 LLVMValueRef val[2])
1277 {
1278 LLVMValueRef v[2] = {
1279 LLVMBuildAnd(gallivm->builder, val[0],
1280 lp_build_const_int32(gallivm, 0xffff), ""),
1281 val[1],
1282 };
1283 return si_llvm_pack_two_int16(gallivm, v);
1284 }
1285
1286 /* Initialize arguments for the shader export intrinsic */
1287 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1288 LLVMValueRef *values,
1289 unsigned target,
1290 LLVMValueRef *args)
1291 {
1292 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1293 struct lp_build_context *uint =
1294 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1295 struct lp_build_context *base = &bld_base->base;
1296 struct gallivm_state *gallivm = base->gallivm;
1297 LLVMBuilderRef builder = base->gallivm->builder;
1298 LLVMValueRef val[4];
1299 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1300 unsigned chan;
1301 bool is_int8;
1302
1303 /* Default is 0xf. Adjusted below depending on the format. */
1304 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1305
1306 /* Specify whether the EXEC mask represents the valid mask */
1307 args[1] = uint->zero;
1308
1309 /* Specify whether this is the last export */
1310 args[2] = uint->zero;
1311
1312 /* Specify the target we are exporting */
1313 args[3] = lp_build_const_int32(base->gallivm, target);
1314
1315 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
1316 const union si_shader_key *key = &si_shader_ctx->shader->key;
1317 unsigned col_formats = key->ps.spi_shader_col_format;
1318 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1319
1320 assert(cbuf >= 0 && cbuf < 8);
1321 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1322 is_int8 = (key->ps.color_is_int8 >> cbuf) & 0x1;
1323 }
1324
1325 args[4] = uint->zero; /* COMPR flag */
1326 args[5] = base->undef;
1327 args[6] = base->undef;
1328 args[7] = base->undef;
1329 args[8] = base->undef;
1330
1331 switch (spi_shader_col_format) {
1332 case V_028714_SPI_SHADER_ZERO:
1333 args[0] = uint->zero; /* writemask */
1334 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
1335 break;
1336
1337 case V_028714_SPI_SHADER_32_R:
1338 args[0] = uint->one; /* writemask */
1339 args[5] = values[0];
1340 break;
1341
1342 case V_028714_SPI_SHADER_32_GR:
1343 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
1344 args[5] = values[0];
1345 args[6] = values[1];
1346 break;
1347
1348 case V_028714_SPI_SHADER_32_AR:
1349 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
1350 args[5] = values[0];
1351 args[8] = values[3];
1352 break;
1353
1354 case V_028714_SPI_SHADER_FP16_ABGR:
1355 args[4] = uint->one; /* COMPR flag */
1356
1357 for (chan = 0; chan < 2; chan++) {
1358 LLVMValueRef pack_args[2] = {
1359 values[2 * chan],
1360 values[2 * chan + 1]
1361 };
1362 LLVMValueRef packed;
1363
1364 packed = lp_build_intrinsic(base->gallivm->builder,
1365 "llvm.SI.packf16",
1366 uint->elem_type, pack_args, 2,
1367 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1368 args[chan + 5] =
1369 LLVMBuildBitCast(base->gallivm->builder,
1370 packed, base->elem_type, "");
1371 }
1372 break;
1373
1374 case V_028714_SPI_SHADER_UNORM16_ABGR:
1375 for (chan = 0; chan < 4; chan++) {
1376 val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
1377 val[chan] = LLVMBuildFMul(builder, val[chan],
1378 lp_build_const_float(gallivm, 65535), "");
1379 val[chan] = LLVMBuildFAdd(builder, val[chan],
1380 lp_build_const_float(gallivm, 0.5), "");
1381 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1382 uint->elem_type, "");
1383 }
1384
1385 args[4] = uint->one; /* COMPR flag */
1386 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1387 si_llvm_pack_two_int16(gallivm, val));
1388 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1389 si_llvm_pack_two_int16(gallivm, val+2));
1390 break;
1391
1392 case V_028714_SPI_SHADER_SNORM16_ABGR:
1393 for (chan = 0; chan < 4; chan++) {
1394 /* Clamp between [-1, 1]. */
1395 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1396 values[chan],
1397 lp_build_const_float(gallivm, 1));
1398 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1399 val[chan],
1400 lp_build_const_float(gallivm, -1));
1401 /* Convert to a signed integer in [-32767, 32767]. */
1402 val[chan] = LLVMBuildFMul(builder, val[chan],
1403 lp_build_const_float(gallivm, 32767), "");
1404 /* If positive, add 0.5, else add -0.5. */
1405 val[chan] = LLVMBuildFAdd(builder, val[chan],
1406 LLVMBuildSelect(builder,
1407 LLVMBuildFCmp(builder, LLVMRealOGE,
1408 val[chan], base->zero, ""),
1409 lp_build_const_float(gallivm, 0.5),
1410 lp_build_const_float(gallivm, -0.5), ""), "");
1411 val[chan] = LLVMBuildFPToSI(builder, val[chan], uint->elem_type, "");
1412 }
1413
1414 args[4] = uint->one; /* COMPR flag */
1415 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1416 si_llvm_pack_two_int32_as_int16(gallivm, val));
1417 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1418 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1419 break;
1420
1421 case V_028714_SPI_SHADER_UINT16_ABGR: {
1422 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1423 255 : 65535);
1424 /* Clamp. */
1425 for (chan = 0; chan < 4; chan++) {
1426 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1427 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1428 val[chan], max);
1429 }
1430
1431 args[4] = uint->one; /* COMPR flag */
1432 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1433 si_llvm_pack_two_int16(gallivm, val));
1434 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1435 si_llvm_pack_two_int16(gallivm, val+2));
1436 break;
1437 }
1438
1439 case V_028714_SPI_SHADER_SINT16_ABGR: {
1440 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1441 127 : 32767);
1442 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
1443 -128 : -32768);
1444 /* Clamp. */
1445 for (chan = 0; chan < 4; chan++) {
1446 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1447 val[chan] = lp_build_emit_llvm_binary(bld_base,
1448 TGSI_OPCODE_IMIN,
1449 val[chan], max);
1450 val[chan] = lp_build_emit_llvm_binary(bld_base,
1451 TGSI_OPCODE_IMAX,
1452 val[chan], min);
1453 }
1454
1455 args[4] = uint->one; /* COMPR flag */
1456 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1457 si_llvm_pack_two_int32_as_int16(gallivm, val));
1458 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1459 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1460 break;
1461 }
1462
1463 case V_028714_SPI_SHADER_32_ABGR:
1464 memcpy(&args[5], values, sizeof(values[0]) * 4);
1465 break;
1466 }
1467 }
1468
1469 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1470 LLVMValueRef alpha)
1471 {
1472 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1473 struct gallivm_state *gallivm = bld_base->base.gallivm;
1474
1475 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
1476 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1477 SI_PARAM_ALPHA_REF);
1478
1479 LLVMValueRef alpha_pass =
1480 lp_build_cmp(&bld_base->base,
1481 si_shader_ctx->shader->key.ps.alpha_func,
1482 alpha, alpha_ref);
1483 LLVMValueRef arg =
1484 lp_build_select(&bld_base->base,
1485 alpha_pass,
1486 lp_build_const_float(gallivm, 1.0f),
1487 lp_build_const_float(gallivm, -1.0f));
1488
1489 lp_build_intrinsic(gallivm->builder,
1490 "llvm.AMDGPU.kill",
1491 LLVMVoidTypeInContext(gallivm->context),
1492 &arg, 1, 0);
1493 } else {
1494 lp_build_intrinsic(gallivm->builder,
1495 "llvm.AMDGPU.kilp",
1496 LLVMVoidTypeInContext(gallivm->context),
1497 NULL, 0, 0);
1498 }
1499 }
1500
1501 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1502 LLVMValueRef alpha)
1503 {
1504 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1505 struct gallivm_state *gallivm = bld_base->base.gallivm;
1506 LLVMValueRef coverage;
1507
1508 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1509 coverage = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1510 SI_PARAM_SAMPLE_COVERAGE);
1511 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1512
1513 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1514 bld_base->int_bld.elem_type,
1515 &coverage, 1, LLVMReadNoneAttribute);
1516
1517 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1518 bld_base->base.elem_type, "");
1519
1520 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1521 lp_build_const_float(gallivm,
1522 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1523
1524 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1525 }
1526
1527 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
1528 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1529 {
1530 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1531 struct lp_build_context *base = &bld_base->base;
1532 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1533 unsigned reg_index;
1534 unsigned chan;
1535 unsigned const_chan;
1536 LLVMValueRef base_elt;
1537 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1538 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
1539 LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
1540
1541 for (reg_index = 0; reg_index < 2; reg_index ++) {
1542 LLVMValueRef *args = pos[2 + reg_index];
1543
1544 args[5] =
1545 args[6] =
1546 args[7] =
1547 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1548
1549 /* Compute dot products of position and user clip plane vectors */
1550 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1551 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1552 args[1] = lp_build_const_int32(base->gallivm,
1553 ((reg_index * 4 + chan) * 4 +
1554 const_chan) * 4);
1555 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1556 args[1], base->elem_type);
1557 args[5 + chan] =
1558 lp_build_add(base, args[5 + chan],
1559 lp_build_mul(base, base_elt,
1560 out_elts[const_chan]));
1561 }
1562 }
1563
1564 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1565 args[1] = uint->zero;
1566 args[2] = uint->zero;
1567 args[3] = lp_build_const_int32(base->gallivm,
1568 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1569 args[4] = uint->zero;
1570 }
1571 }
1572
1573 static void si_dump_streamout(struct pipe_stream_output_info *so)
1574 {
1575 unsigned i;
1576
1577 if (so->num_outputs)
1578 fprintf(stderr, "STREAMOUT\n");
1579
1580 for (i = 0; i < so->num_outputs; i++) {
1581 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1582 so->output[i].start_component;
1583 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1584 i, so->output[i].output_buffer,
1585 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1586 so->output[i].register_index,
1587 mask & 1 ? "x" : "",
1588 mask & 2 ? "y" : "",
1589 mask & 4 ? "z" : "",
1590 mask & 8 ? "w" : "");
1591 }
1592 }
1593
1594 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1595 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1596 * or v4i32 (num_channels=3,4). */
1597 static void build_tbuffer_store(struct si_shader_context *shader,
1598 LLVMValueRef rsrc,
1599 LLVMValueRef vdata,
1600 unsigned num_channels,
1601 LLVMValueRef vaddr,
1602 LLVMValueRef soffset,
1603 unsigned inst_offset,
1604 unsigned dfmt,
1605 unsigned nfmt,
1606 unsigned offen,
1607 unsigned idxen,
1608 unsigned glc,
1609 unsigned slc,
1610 unsigned tfe)
1611 {
1612 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1613 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1614 LLVMValueRef args[] = {
1615 rsrc,
1616 vdata,
1617 LLVMConstInt(i32, num_channels, 0),
1618 vaddr,
1619 soffset,
1620 LLVMConstInt(i32, inst_offset, 0),
1621 LLVMConstInt(i32, dfmt, 0),
1622 LLVMConstInt(i32, nfmt, 0),
1623 LLVMConstInt(i32, offen, 0),
1624 LLVMConstInt(i32, idxen, 0),
1625 LLVMConstInt(i32, glc, 0),
1626 LLVMConstInt(i32, slc, 0),
1627 LLVMConstInt(i32, tfe, 0)
1628 };
1629
1630 /* The instruction offset field has 12 bits */
1631 assert(offen || inst_offset < (1 << 12));
1632
1633 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1634 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1635 const char *types[] = {"i32", "v2i32", "v4i32"};
1636 char name[256];
1637 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1638
1639 lp_build_intrinsic(gallivm->builder, name,
1640 LLVMVoidTypeInContext(gallivm->context),
1641 args, Elements(args), 0);
1642 }
1643
1644 static void build_tbuffer_store_dwords(struct si_shader_context *shader,
1645 LLVMValueRef rsrc,
1646 LLVMValueRef vdata,
1647 unsigned num_channels,
1648 LLVMValueRef vaddr,
1649 LLVMValueRef soffset,
1650 unsigned inst_offset)
1651 {
1652 static unsigned dfmt[] = {
1653 V_008F0C_BUF_DATA_FORMAT_32,
1654 V_008F0C_BUF_DATA_FORMAT_32_32,
1655 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1656 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1657 };
1658 assert(num_channels >= 1 && num_channels <= 4);
1659
1660 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
1661 inst_offset, dfmt[num_channels-1],
1662 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1663 }
1664
1665 /* On SI, the vertex shader is responsible for writing streamout data
1666 * to buffers. */
1667 static void si_llvm_emit_streamout(struct si_shader_context *shader,
1668 struct si_shader_output_values *outputs,
1669 unsigned noutput)
1670 {
1671 struct pipe_stream_output_info *so = &shader->shader->selector->so;
1672 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1673 LLVMBuilderRef builder = gallivm->builder;
1674 int i, j;
1675 struct lp_build_if_state if_ctx;
1676
1677 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1678
1679 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1680 LLVMValueRef so_vtx_count =
1681 unpack_param(shader, shader->param_streamout_config, 16, 7);
1682
1683 LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", i32,
1684 NULL, 0, LLVMReadNoneAttribute);
1685
1686 /* can_emit = tid < so_vtx_count; */
1687 LLVMValueRef can_emit =
1688 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1689
1690 LLVMValueRef stream_id =
1691 unpack_param(shader, shader->param_streamout_config, 24, 2);
1692
1693 /* Emit the streamout code conditionally. This actually avoids
1694 * out-of-bounds buffer access. The hw tells us via the SGPR
1695 * (so_vtx_count) which threads are allowed to emit streamout data. */
1696 lp_build_if(&if_ctx, gallivm, can_emit);
1697 {
1698 /* The buffer offset is computed as follows:
1699 * ByteOffset = streamout_offset[buffer_id]*4 +
1700 * (streamout_write_index + thread_id)*stride[buffer_id] +
1701 * attrib_offset
1702 */
1703
1704 LLVMValueRef so_write_index =
1705 LLVMGetParam(shader->radeon_bld.main_fn,
1706 shader->param_streamout_write_index);
1707
1708 /* Compute (streamout_write_index + thread_id). */
1709 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1710
1711 /* Compute the write offset for each enabled buffer. */
1712 LLVMValueRef so_write_offset[4] = {};
1713 for (i = 0; i < 4; i++) {
1714 if (!so->stride[i])
1715 continue;
1716
1717 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1718 shader->param_streamout_offset[i]);
1719 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1720
1721 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1722 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1723 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1724 }
1725
1726 /* Write streamout data. */
1727 for (i = 0; i < so->num_outputs; i++) {
1728 unsigned buf_idx = so->output[i].output_buffer;
1729 unsigned reg = so->output[i].register_index;
1730 unsigned start = so->output[i].start_component;
1731 unsigned num_comps = so->output[i].num_components;
1732 unsigned stream = so->output[i].stream;
1733 LLVMValueRef out[4];
1734 struct lp_build_if_state if_ctx_stream;
1735
1736 assert(num_comps && num_comps <= 4);
1737 if (!num_comps || num_comps > 4)
1738 continue;
1739
1740 if (reg >= noutput)
1741 continue;
1742
1743 /* Load the output as int. */
1744 for (j = 0; j < num_comps; j++) {
1745 out[j] = LLVMBuildBitCast(builder,
1746 outputs[reg].values[start+j],
1747 i32, "");
1748 }
1749
1750 /* Pack the output. */
1751 LLVMValueRef vdata = NULL;
1752
1753 switch (num_comps) {
1754 case 1: /* as i32 */
1755 vdata = out[0];
1756 break;
1757 case 2: /* as v2i32 */
1758 case 3: /* as v4i32 (aligned to 4) */
1759 case 4: /* as v4i32 */
1760 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1761 for (j = 0; j < num_comps; j++) {
1762 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1763 LLVMConstInt(i32, j, 0), "");
1764 }
1765 break;
1766 }
1767
1768 LLVMValueRef can_emit_stream =
1769 LLVMBuildICmp(builder, LLVMIntEQ,
1770 stream_id,
1771 lp_build_const_int32(gallivm, stream), "");
1772
1773 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1774 build_tbuffer_store_dwords(shader, shader->so_buffers[buf_idx],
1775 vdata, num_comps,
1776 so_write_offset[buf_idx],
1777 LLVMConstInt(i32, 0, 0),
1778 so->output[i].dst_offset*4);
1779 lp_build_endif(&if_ctx_stream);
1780 }
1781 }
1782 lp_build_endif(&if_ctx);
1783 }
1784
1785
1786 /* Generate export instructions for hardware VS shader stage */
1787 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1788 struct si_shader_output_values *outputs,
1789 unsigned noutput)
1790 {
1791 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1792 struct si_shader * shader = si_shader_ctx->shader;
1793 struct lp_build_context * base = &bld_base->base;
1794 struct lp_build_context * uint =
1795 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1796 LLVMValueRef args[9];
1797 LLVMValueRef pos_args[4][9] = { { 0 } };
1798 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1799 unsigned semantic_name, semantic_index;
1800 unsigned target;
1801 unsigned param_count = 0;
1802 unsigned pos_idx;
1803 int i;
1804
1805 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1806 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1807 }
1808
1809 for (i = 0; i < noutput; i++) {
1810 semantic_name = outputs[i].name;
1811 semantic_index = outputs[i].sid;
1812
1813 handle_semantic:
1814 /* Select the correct target */
1815 switch(semantic_name) {
1816 case TGSI_SEMANTIC_PSIZE:
1817 psize_value = outputs[i].values[0];
1818 continue;
1819 case TGSI_SEMANTIC_EDGEFLAG:
1820 edgeflag_value = outputs[i].values[0];
1821 continue;
1822 case TGSI_SEMANTIC_LAYER:
1823 layer_value = outputs[i].values[0];
1824 semantic_name = TGSI_SEMANTIC_GENERIC;
1825 goto handle_semantic;
1826 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1827 viewport_index_value = outputs[i].values[0];
1828 semantic_name = TGSI_SEMANTIC_GENERIC;
1829 goto handle_semantic;
1830 case TGSI_SEMANTIC_POSITION:
1831 target = V_008DFC_SQ_EXP_POS;
1832 break;
1833 case TGSI_SEMANTIC_COLOR:
1834 case TGSI_SEMANTIC_BCOLOR:
1835 target = V_008DFC_SQ_EXP_PARAM + param_count;
1836 shader->vs_output_param_offset[i] = param_count;
1837 param_count++;
1838 break;
1839 case TGSI_SEMANTIC_CLIPDIST:
1840 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1841 break;
1842 case TGSI_SEMANTIC_CLIPVERTEX:
1843 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1844 continue;
1845 case TGSI_SEMANTIC_PRIMID:
1846 case TGSI_SEMANTIC_FOG:
1847 case TGSI_SEMANTIC_TEXCOORD:
1848 case TGSI_SEMANTIC_GENERIC:
1849 target = V_008DFC_SQ_EXP_PARAM + param_count;
1850 shader->vs_output_param_offset[i] = param_count;
1851 param_count++;
1852 break;
1853 default:
1854 target = 0;
1855 fprintf(stderr,
1856 "Warning: SI unhandled vs output type:%d\n",
1857 semantic_name);
1858 }
1859
1860 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1861
1862 if (target >= V_008DFC_SQ_EXP_POS &&
1863 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1864 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1865 args, sizeof(args));
1866 } else {
1867 lp_build_intrinsic(base->gallivm->builder,
1868 "llvm.SI.export",
1869 LLVMVoidTypeInContext(base->gallivm->context),
1870 args, 9, 0);
1871 }
1872
1873 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1874 semantic_name = TGSI_SEMANTIC_GENERIC;
1875 goto handle_semantic;
1876 }
1877 }
1878
1879 shader->nr_param_exports = param_count;
1880
1881 /* We need to add the position output manually if it's missing. */
1882 if (!pos_args[0][0]) {
1883 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1884 pos_args[0][1] = uint->zero; /* EXEC mask */
1885 pos_args[0][2] = uint->zero; /* last export? */
1886 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1887 pos_args[0][4] = uint->zero; /* COMPR flag */
1888 pos_args[0][5] = base->zero; /* X */
1889 pos_args[0][6] = base->zero; /* Y */
1890 pos_args[0][7] = base->zero; /* Z */
1891 pos_args[0][8] = base->one; /* W */
1892 }
1893
1894 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1895 if (shader->selector->info.writes_psize ||
1896 shader->selector->info.writes_edgeflag ||
1897 shader->selector->info.writes_viewport_index ||
1898 shader->selector->info.writes_layer) {
1899 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1900 shader->selector->info.writes_psize |
1901 (shader->selector->info.writes_edgeflag << 1) |
1902 (shader->selector->info.writes_layer << 2) |
1903 (shader->selector->info.writes_viewport_index << 3));
1904 pos_args[1][1] = uint->zero; /* EXEC mask */
1905 pos_args[1][2] = uint->zero; /* last export? */
1906 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1907 pos_args[1][4] = uint->zero; /* COMPR flag */
1908 pos_args[1][5] = base->zero; /* X */
1909 pos_args[1][6] = base->zero; /* Y */
1910 pos_args[1][7] = base->zero; /* Z */
1911 pos_args[1][8] = base->zero; /* W */
1912
1913 if (shader->selector->info.writes_psize)
1914 pos_args[1][5] = psize_value;
1915
1916 if (shader->selector->info.writes_edgeflag) {
1917 /* The output is a float, but the hw expects an integer
1918 * with the first bit containing the edge flag. */
1919 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1920 edgeflag_value,
1921 bld_base->uint_bld.elem_type, "");
1922 edgeflag_value = lp_build_min(&bld_base->int_bld,
1923 edgeflag_value,
1924 bld_base->int_bld.one);
1925
1926 /* The LLVM intrinsic expects a float. */
1927 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1928 edgeflag_value,
1929 base->elem_type, "");
1930 }
1931
1932 if (shader->selector->info.writes_layer)
1933 pos_args[1][7] = layer_value;
1934
1935 if (shader->selector->info.writes_viewport_index)
1936 pos_args[1][8] = viewport_index_value;
1937 }
1938
1939 for (i = 0; i < 4; i++)
1940 if (pos_args[i][0])
1941 shader->nr_pos_exports++;
1942
1943 pos_idx = 0;
1944 for (i = 0; i < 4; i++) {
1945 if (!pos_args[i][0])
1946 continue;
1947
1948 /* Specify the target we are exporting */
1949 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1950
1951 if (pos_idx == shader->nr_pos_exports)
1952 /* Specify that this is the last export */
1953 pos_args[i][2] = uint->one;
1954
1955 lp_build_intrinsic(base->gallivm->builder,
1956 "llvm.SI.export",
1957 LLVMVoidTypeInContext(base->gallivm->context),
1958 pos_args[i], 9, 0);
1959 }
1960 }
1961
1962 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
1963 LLVMValueRef rel_patch_id,
1964 LLVMValueRef invocation_id,
1965 LLVMValueRef tcs_out_current_patch_data_offset)
1966 {
1967 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1968 struct gallivm_state *gallivm = bld_base->base.gallivm;
1969 struct si_shader *shader = si_shader_ctx->shader;
1970 unsigned tess_inner_index, tess_outer_index;
1971 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
1972 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
1973 unsigned stride, outer_comps, inner_comps, i;
1974 struct lp_build_if_state if_ctx;
1975
1976 /* Do this only for invocation 0, because the tess levels are per-patch,
1977 * not per-vertex.
1978 *
1979 * This can't jump, because invocation 0 executes this. It should
1980 * at least mask out the loads and stores for other invocations.
1981 */
1982 lp_build_if(&if_ctx, gallivm,
1983 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
1984 invocation_id, bld_base->uint_bld.zero, ""));
1985
1986 /* Determine the layout of one tess factor element in the buffer. */
1987 switch (shader->key.tcs.prim_mode) {
1988 case PIPE_PRIM_LINES:
1989 stride = 2; /* 2 dwords, 1 vec2 store */
1990 outer_comps = 2;
1991 inner_comps = 0;
1992 break;
1993 case PIPE_PRIM_TRIANGLES:
1994 stride = 4; /* 4 dwords, 1 vec4 store */
1995 outer_comps = 3;
1996 inner_comps = 1;
1997 break;
1998 case PIPE_PRIM_QUADS:
1999 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2000 outer_comps = 4;
2001 inner_comps = 2;
2002 break;
2003 default:
2004 assert(0);
2005 return;
2006 }
2007
2008 /* Load tess_inner and tess_outer from LDS.
2009 * Any invocation can write them, so we can't get them from a temporary.
2010 */
2011 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2012 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2013
2014 lds_base = tcs_out_current_patch_data_offset;
2015 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2016 lp_build_const_int32(gallivm,
2017 tess_inner_index * 4), "");
2018 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2019 lp_build_const_int32(gallivm,
2020 tess_outer_index * 4), "");
2021
2022 for (i = 0; i < outer_comps; i++)
2023 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2024 for (i = 0; i < inner_comps; i++)
2025 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2026
2027 /* Convert the outputs to vectors for stores. */
2028 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2029 vec1 = NULL;
2030
2031 if (stride > 4)
2032 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2033
2034 /* Get the buffer. */
2035 rw_buffers = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2036 SI_PARAM_RW_BUFFERS);
2037 buffer = build_indexed_load_const(si_shader_ctx, rw_buffers,
2038 lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR));
2039
2040 /* Get the offset. */
2041 tf_base = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2042 SI_PARAM_TESS_FACTOR_OFFSET);
2043 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2044 lp_build_const_int32(gallivm, 4 * stride), "");
2045
2046 /* Store the outputs. */
2047 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec0,
2048 MIN2(stride, 4), byteoffset, tf_base, 0);
2049 if (vec1)
2050 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec1,
2051 stride - 4, byteoffset, tf_base, 16);
2052 lp_build_endif(&if_ctx);
2053 }
2054
2055 /* This only writes the tessellation factor levels. */
2056 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2057 {
2058 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2059 LLVMValueRef invocation_id;
2060
2061 invocation_id = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
2062
2063 si_write_tess_factors(bld_base,
2064 get_rel_patch_id(si_shader_ctx),
2065 invocation_id,
2066 get_tcs_out_current_patch_data_offset(si_shader_ctx));
2067 }
2068
2069 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context * bld_base)
2070 {
2071 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2072 struct si_shader *shader = si_shader_ctx->shader;
2073 struct tgsi_shader_info *info = &shader->selector->info;
2074 struct gallivm_state *gallivm = bld_base->base.gallivm;
2075 unsigned i, chan;
2076 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2077 si_shader_ctx->param_rel_auto_id);
2078 LLVMValueRef vertex_dw_stride =
2079 unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2080 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2081 vertex_dw_stride, "");
2082
2083 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2084 * its inputs from it. */
2085 for (i = 0; i < info->num_outputs; i++) {
2086 LLVMValueRef *out_ptr = si_shader_ctx->radeon_bld.soa.outputs[i];
2087 unsigned name = info->output_semantic_name[i];
2088 unsigned index = info->output_semantic_index[i];
2089 int param = si_shader_io_get_unique_index(name, index);
2090 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2091 lp_build_const_int32(gallivm, param * 4), "");
2092
2093 for (chan = 0; chan < 4; chan++) {
2094 lds_store(bld_base, chan, dw_addr,
2095 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2096 }
2097 }
2098 }
2099
2100 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
2101 {
2102 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2103 struct gallivm_state *gallivm = bld_base->base.gallivm;
2104 struct si_shader *es = si_shader_ctx->shader;
2105 struct tgsi_shader_info *info = &es->selector->info;
2106 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2107 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2108 si_shader_ctx->param_es2gs_offset);
2109 unsigned chan;
2110 int i;
2111
2112 for (i = 0; i < info->num_outputs; i++) {
2113 LLVMValueRef *out_ptr =
2114 si_shader_ctx->radeon_bld.soa.outputs[i];
2115 int param_index;
2116
2117 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2118 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2119 continue;
2120
2121 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2122 info->output_semantic_index[i]);
2123
2124 for (chan = 0; chan < 4; chan++) {
2125 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2126 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2127
2128 build_tbuffer_store(si_shader_ctx,
2129 si_shader_ctx->esgs_ring,
2130 out_val, 1,
2131 LLVMGetUndef(i32), soffset,
2132 (4 * param_index + chan) * 4,
2133 V_008F0C_BUF_DATA_FORMAT_32,
2134 V_008F0C_BUF_NUM_FORMAT_UINT,
2135 0, 0, 1, 1, 0);
2136 }
2137 }
2138 }
2139
2140 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2141 {
2142 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2143 struct gallivm_state *gallivm = bld_base->base.gallivm;
2144 LLVMValueRef args[2];
2145
2146 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2147 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2148 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2149 LLVMVoidTypeInContext(gallivm->context), args, 2,
2150 LLVMNoUnwindAttribute);
2151 }
2152
2153 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
2154 {
2155 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2156 struct gallivm_state *gallivm = bld_base->base.gallivm;
2157 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
2158 struct si_shader_output_values *outputs = NULL;
2159 int i,j;
2160
2161 assert(!si_shader_ctx->is_gs_copy_shader);
2162
2163 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2164
2165 /* Vertex color clamping.
2166 *
2167 * This uses a state constant loaded in a user data SGPR and
2168 * an IF statement is added that clamps all colors if the constant
2169 * is true.
2170 */
2171 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
2172 struct lp_build_if_state if_ctx;
2173 LLVMValueRef cond = NULL;
2174 LLVMValueRef addr, val;
2175
2176 for (i = 0; i < info->num_outputs; i++) {
2177 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2178 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2179 continue;
2180
2181 /* We've found a color. */
2182 if (!cond) {
2183 /* The state is in the first bit of the user SGPR. */
2184 cond = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2185 SI_PARAM_VS_STATE_BITS);
2186 cond = LLVMBuildTrunc(gallivm->builder, cond,
2187 LLVMInt1TypeInContext(gallivm->context), "");
2188 lp_build_if(&if_ctx, gallivm, cond);
2189 }
2190
2191 for (j = 0; j < 4; j++) {
2192 addr = si_shader_ctx->radeon_bld.soa.outputs[i][j];
2193 val = LLVMBuildLoad(gallivm->builder, addr, "");
2194 val = radeon_llvm_saturate(bld_base, val);
2195 LLVMBuildStore(gallivm->builder, val, addr);
2196 }
2197 }
2198
2199 if (cond)
2200 lp_build_endif(&if_ctx);
2201 }
2202
2203 for (i = 0; i < info->num_outputs; i++) {
2204 outputs[i].name = info->output_semantic_name[i];
2205 outputs[i].sid = info->output_semantic_index[i];
2206
2207 for (j = 0; j < 4; j++)
2208 outputs[i].values[j] =
2209 LLVMBuildLoad(gallivm->builder,
2210 si_shader_ctx->radeon_bld.soa.outputs[i][j],
2211 "");
2212 }
2213
2214 /* Export PrimitiveID when PS needs it. */
2215 if (si_vs_exports_prim_id(si_shader_ctx->shader)) {
2216 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2217 outputs[i].sid = 0;
2218 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2219 get_primitive_id(bld_base, 0));
2220 outputs[i].values[1] = bld_base->base.undef;
2221 outputs[i].values[2] = bld_base->base.undef;
2222 outputs[i].values[3] = bld_base->base.undef;
2223 i++;
2224 }
2225
2226 si_llvm_export_vs(bld_base, outputs, i);
2227 FREE(outputs);
2228 }
2229
2230 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2231 LLVMValueRef depth, LLVMValueRef stencil,
2232 LLVMValueRef samplemask)
2233 {
2234 struct si_screen *sscreen = si_shader_context(bld_base)->screen;
2235 struct lp_build_context *base = &bld_base->base;
2236 struct lp_build_context *uint = &bld_base->uint_bld;
2237 LLVMValueRef args[9];
2238 unsigned mask = 0;
2239
2240 assert(depth || stencil || samplemask);
2241
2242 args[1] = uint->one; /* whether the EXEC mask is valid */
2243 args[2] = uint->one; /* DONE bit */
2244
2245 /* Specify the target we are exporting */
2246 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2247
2248 args[4] = uint->zero; /* COMP flag */
2249 args[5] = base->undef; /* R, depth */
2250 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2251 args[7] = base->undef; /* B, sample mask */
2252 args[8] = base->undef; /* A, alpha to mask */
2253
2254 if (depth) {
2255 args[5] = depth;
2256 mask |= 0x1;
2257 }
2258
2259 if (stencil) {
2260 args[6] = stencil;
2261 mask |= 0x2;
2262 }
2263
2264 if (samplemask) {
2265 args[7] = samplemask;
2266 mask |= 0x4;
2267 }
2268
2269 /* SI (except OLAND) has a bug that it only looks
2270 * at the X writemask component. */
2271 if (sscreen->b.chip_class == SI &&
2272 sscreen->b.family != CHIP_OLAND)
2273 mask |= 0x1;
2274
2275 /* Specify which components to enable */
2276 args[0] = lp_build_const_int32(base->gallivm, mask);
2277
2278 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2279 LLVMVoidTypeInContext(base->gallivm->context),
2280 args, 9, 0);
2281 }
2282
2283 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2284 LLVMValueRef *color, unsigned index,
2285 bool is_last)
2286 {
2287 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2288 struct lp_build_context *base = &bld_base->base;
2289 LLVMValueRef args[9];
2290 int i;
2291
2292 /* Clamp color */
2293 if (si_shader_ctx->shader->key.ps.clamp_color)
2294 for (i = 0; i < 4; i++)
2295 color[i] = radeon_llvm_saturate(bld_base, color[i]);
2296
2297 /* Alpha to one */
2298 if (si_shader_ctx->shader->key.ps.alpha_to_one)
2299 color[3] = base->one;
2300
2301 /* Alpha test */
2302 if (index == 0 &&
2303 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
2304 si_alpha_test(bld_base, color[3]);
2305
2306 /* Line & polygon smoothing */
2307 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
2308 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3]);
2309
2310 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2311 if (index == 0 &&
2312 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
2313 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
2314 si_llvm_init_export_args(bld_base, color,
2315 V_008DFC_SQ_EXP_MRT + c, args);
2316 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2317 LLVMVoidTypeInContext(base->gallivm->context),
2318 args, 9, 0);
2319 }
2320 }
2321
2322 /* Export */
2323 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2324 args);
2325 if (is_last) {
2326 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2327 args[2] = bld_base->uint_bld.one; /* DONE bit */
2328 }
2329 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2330 LLVMVoidTypeInContext(base->gallivm->context),
2331 args, 9, 0);
2332 }
2333
2334 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2335 {
2336 struct lp_build_context *base = &bld_base->base;
2337 struct lp_build_context *uint = &bld_base->uint_bld;
2338 LLVMValueRef args[9];
2339
2340 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
2341 args[1] = uint->one; /* whether the EXEC mask is valid */
2342 args[2] = uint->one; /* DONE bit */
2343 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2344 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
2345 args[5] = uint->undef; /* R */
2346 args[6] = uint->undef; /* G */
2347 args[7] = uint->undef; /* B */
2348 args[8] = uint->undef; /* A */
2349
2350 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2351 LLVMVoidTypeInContext(base->gallivm->context),
2352 args, 9, 0);
2353 }
2354
2355 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
2356 {
2357 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
2358 struct si_shader * shader = si_shader_ctx->shader;
2359 struct lp_build_context * base = &bld_base->base;
2360 struct tgsi_shader_info *info = &shader->selector->info;
2361 LLVMBuilderRef builder = base->gallivm->builder;
2362 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2363 int last_color_export = -1;
2364 int i;
2365
2366 /* If there are no outputs, add a dummy export. */
2367 if (!info->num_outputs) {
2368 si_export_null(bld_base);
2369 return;
2370 }
2371
2372 /* Determine the last export. If MRTZ is present, it's always last.
2373 * Otherwise, find the last color export.
2374 */
2375 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask)
2376 for (i = 0; i < info->num_outputs; i++)
2377 if (info->output_semantic_name[i] == TGSI_SEMANTIC_COLOR)
2378 last_color_export = i;
2379
2380 for (i = 0; i < info->num_outputs; i++) {
2381 unsigned semantic_name = info->output_semantic_name[i];
2382 unsigned semantic_index = info->output_semantic_index[i];
2383 unsigned j;
2384 LLVMValueRef color[4] = {};
2385
2386 /* Select the correct target */
2387 switch (semantic_name) {
2388 case TGSI_SEMANTIC_POSITION:
2389 depth = LLVMBuildLoad(builder,
2390 si_shader_ctx->radeon_bld.soa.outputs[i][2], "");
2391 break;
2392 case TGSI_SEMANTIC_STENCIL:
2393 stencil = LLVMBuildLoad(builder,
2394 si_shader_ctx->radeon_bld.soa.outputs[i][1], "");
2395 break;
2396 case TGSI_SEMANTIC_SAMPLEMASK:
2397 samplemask = LLVMBuildLoad(builder,
2398 si_shader_ctx->radeon_bld.soa.outputs[i][0], "");
2399 break;
2400 case TGSI_SEMANTIC_COLOR:
2401 for (j = 0; j < 4; j++)
2402 color[j] = LLVMBuildLoad(builder,
2403 si_shader_ctx->radeon_bld.soa.outputs[i][j], "");
2404
2405 si_export_mrt_color(bld_base, color, semantic_index,
2406 last_color_export == i);
2407 break;
2408 default:
2409 fprintf(stderr,
2410 "Warning: SI unhandled fs output type:%d\n",
2411 semantic_name);
2412 }
2413 }
2414
2415 if (depth || stencil || samplemask)
2416 si_export_mrt_z(bld_base, depth, stencil, samplemask);
2417 }
2418
2419 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2420 struct lp_build_tgsi_context * bld_base,
2421 struct lp_build_emit_data * emit_data);
2422
2423 static bool tgsi_is_array_sampler(unsigned target)
2424 {
2425 return target == TGSI_TEXTURE_1D_ARRAY ||
2426 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2427 target == TGSI_TEXTURE_2D_ARRAY ||
2428 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2429 target == TGSI_TEXTURE_CUBE_ARRAY ||
2430 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2431 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2432 }
2433
2434 static void set_tex_fetch_args(struct gallivm_state *gallivm,
2435 struct lp_build_emit_data *emit_data,
2436 unsigned opcode, unsigned target,
2437 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
2438 LLVMValueRef *param, unsigned count,
2439 unsigned dmask)
2440 {
2441 unsigned num_args;
2442 unsigned is_rect = target == TGSI_TEXTURE_RECT;
2443 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2444
2445 /* Pad to power of two vector */
2446 while (count < util_next_power_of_two(count))
2447 param[count++] = LLVMGetUndef(i32);
2448
2449 /* Texture coordinates. */
2450 if (count > 1)
2451 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
2452 else
2453 emit_data->args[0] = param[0];
2454
2455 /* Resource. */
2456 emit_data->args[1] = res_ptr;
2457 num_args = 2;
2458
2459 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
2460 emit_data->dst_type = LLVMVectorType(i32, 4);
2461 else {
2462 emit_data->dst_type = LLVMVectorType(
2463 LLVMFloatTypeInContext(gallivm->context), 4);
2464
2465 emit_data->args[num_args++] = samp_ptr;
2466 }
2467
2468 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
2469 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
2470 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
2471 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
2472 tgsi_is_array_sampler(target)); /* da */
2473 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
2474 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
2475 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
2476 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
2477
2478 emit_data->arg_count = num_args;
2479 }
2480
2481 static const struct lp_build_tgsi_action tex_action;
2482
2483 static void tex_fetch_ptrs(
2484 struct lp_build_tgsi_context * bld_base,
2485 struct lp_build_emit_data * emit_data,
2486 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
2487 {
2488 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2489 struct gallivm_state *gallivm = bld_base->base.gallivm;
2490 const struct tgsi_full_instruction * inst = emit_data->inst;
2491 unsigned target = inst->Texture.Texture;
2492 unsigned sampler_src;
2493 unsigned sampler_index;
2494
2495 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
2496 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
2497
2498 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
2499 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
2500 LLVMValueRef ind_index;
2501
2502 ind_index = get_indirect_index(si_shader_ctx, &reg->Indirect, reg->Register.Index);
2503
2504 *res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
2505 *res_ptr = build_indexed_load_const(si_shader_ctx, *res_ptr, ind_index);
2506
2507 *samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
2508 *samp_ptr = build_indexed_load_const(si_shader_ctx, *samp_ptr, ind_index);
2509
2510 if (target == TGSI_TEXTURE_2D_MSAA ||
2511 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2512 ind_index = LLVMBuildAdd(gallivm->builder, ind_index,
2513 lp_build_const_int32(gallivm,
2514 SI_FMASK_TEX_OFFSET), "");
2515 *fmask_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
2516 *fmask_ptr = build_indexed_load_const(si_shader_ctx, *fmask_ptr, ind_index);
2517 }
2518 } else {
2519 *res_ptr = si_shader_ctx->sampler_views[sampler_index];
2520 *samp_ptr = si_shader_ctx->sampler_states[sampler_index];
2521 *fmask_ptr = si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + sampler_index];
2522 }
2523 }
2524
2525 static void tex_fetch_args(
2526 struct lp_build_tgsi_context * bld_base,
2527 struct lp_build_emit_data * emit_data)
2528 {
2529 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2530 struct gallivm_state *gallivm = bld_base->base.gallivm;
2531 LLVMBuilderRef builder = gallivm->builder;
2532 const struct tgsi_full_instruction * inst = emit_data->inst;
2533 unsigned opcode = inst->Instruction.Opcode;
2534 unsigned target = inst->Texture.Texture;
2535 LLVMValueRef coords[5], derivs[6];
2536 LLVMValueRef address[16];
2537 int ref_pos;
2538 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
2539 unsigned count = 0;
2540 unsigned chan;
2541 unsigned num_deriv_channels = 0;
2542 bool has_offset = inst->Texture.NumOffsets > 0;
2543 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2544 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2545 unsigned dmask = 0xf;
2546
2547 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2548
2549 if (opcode == TGSI_OPCODE_TXQ) {
2550 if (target == TGSI_TEXTURE_BUFFER) {
2551 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2552
2553 /* Read the size from the buffer descriptor directly. */
2554 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2555 LLVMValueRef size = LLVMBuildExtractElement(builder, res,
2556 lp_build_const_int32(gallivm, 6), "");
2557
2558 if (si_shader_ctx->screen->b.chip_class >= VI) {
2559 /* On VI, the descriptor contains the size in bytes,
2560 * but TXQ must return the size in elements.
2561 * The stride is always non-zero for resources using TXQ.
2562 */
2563 LLVMValueRef stride =
2564 LLVMBuildExtractElement(builder, res,
2565 lp_build_const_int32(gallivm, 5), "");
2566 stride = LLVMBuildLShr(builder, stride,
2567 lp_build_const_int32(gallivm, 16), "");
2568 stride = LLVMBuildAnd(builder, stride,
2569 lp_build_const_int32(gallivm, 0x3FFF), "");
2570
2571 size = LLVMBuildUDiv(builder, size, stride, "");
2572 }
2573
2574 emit_data->args[0] = size;
2575 return;
2576 }
2577
2578 /* Textures - set the mip level. */
2579 address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2580
2581 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2582 NULL, address, count, 0xf);
2583 return;
2584 }
2585
2586 if (target == TGSI_TEXTURE_BUFFER) {
2587 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
2588 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
2589 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
2590 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
2591
2592 /* Bitcast and truncate v8i32 to v16i8. */
2593 LLVMValueRef res = res_ptr;
2594 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
2595 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
2596 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
2597
2598 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
2599 emit_data->args[0] = res;
2600 emit_data->args[1] = bld_base->uint_bld.zero;
2601 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
2602 emit_data->arg_count = 3;
2603 return;
2604 }
2605
2606 /* Fetch and project texture coordinates */
2607 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
2608 for (chan = 0; chan < 3; chan++ ) {
2609 coords[chan] = lp_build_emit_fetch(bld_base,
2610 emit_data->inst, 0,
2611 chan);
2612 if (opcode == TGSI_OPCODE_TXP)
2613 coords[chan] = lp_build_emit_llvm_binary(bld_base,
2614 TGSI_OPCODE_DIV,
2615 coords[chan],
2616 coords[3]);
2617 }
2618
2619 if (opcode == TGSI_OPCODE_TXP)
2620 coords[3] = bld_base->base.one;
2621
2622 /* Pack offsets. */
2623 if (has_offset && opcode != TGSI_OPCODE_TXF) {
2624 /* The offsets are six-bit signed integers packed like this:
2625 * X=[5:0], Y=[13:8], and Z=[21:16].
2626 */
2627 LLVMValueRef offset[3], pack;
2628
2629 assert(inst->Texture.NumOffsets == 1);
2630
2631 for (chan = 0; chan < 3; chan++) {
2632 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
2633 emit_data->inst, 0, chan);
2634 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
2635 lp_build_const_int32(gallivm, 0x3f), "");
2636 if (chan)
2637 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
2638 lp_build_const_int32(gallivm, chan*8), "");
2639 }
2640
2641 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
2642 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
2643 address[count++] = pack;
2644 }
2645
2646 /* Pack LOD bias value */
2647 if (opcode == TGSI_OPCODE_TXB)
2648 address[count++] = coords[3];
2649 if (opcode == TGSI_OPCODE_TXB2)
2650 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2651
2652 /* Pack depth comparison value */
2653 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
2654 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2655 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2656 } else {
2657 assert(ref_pos >= 0);
2658 address[count++] = coords[ref_pos];
2659 }
2660 }
2661
2662 /* Pack user derivatives */
2663 if (opcode == TGSI_OPCODE_TXD) {
2664 int param, num_src_deriv_channels;
2665
2666 switch (target) {
2667 case TGSI_TEXTURE_3D:
2668 num_src_deriv_channels = 3;
2669 num_deriv_channels = 3;
2670 break;
2671 case TGSI_TEXTURE_2D:
2672 case TGSI_TEXTURE_SHADOW2D:
2673 case TGSI_TEXTURE_RECT:
2674 case TGSI_TEXTURE_SHADOWRECT:
2675 case TGSI_TEXTURE_2D_ARRAY:
2676 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2677 num_src_deriv_channels = 2;
2678 num_deriv_channels = 2;
2679 break;
2680 case TGSI_TEXTURE_CUBE:
2681 case TGSI_TEXTURE_SHADOWCUBE:
2682 case TGSI_TEXTURE_CUBE_ARRAY:
2683 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
2684 /* Cube derivatives will be converted to 2D. */
2685 num_src_deriv_channels = 3;
2686 num_deriv_channels = 2;
2687 break;
2688 case TGSI_TEXTURE_1D:
2689 case TGSI_TEXTURE_SHADOW1D:
2690 case TGSI_TEXTURE_1D_ARRAY:
2691 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2692 num_src_deriv_channels = 1;
2693 num_deriv_channels = 1;
2694 break;
2695 default:
2696 unreachable("invalid target");
2697 }
2698
2699 for (param = 0; param < 2; param++)
2700 for (chan = 0; chan < num_src_deriv_channels; chan++)
2701 derivs[param * num_src_deriv_channels + chan] =
2702 lp_build_emit_fetch(bld_base, inst, param+1, chan);
2703 }
2704
2705 if (target == TGSI_TEXTURE_CUBE ||
2706 target == TGSI_TEXTURE_CUBE_ARRAY ||
2707 target == TGSI_TEXTURE_SHADOWCUBE ||
2708 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2709 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
2710
2711 if (opcode == TGSI_OPCODE_TXD)
2712 for (int i = 0; i < num_deriv_channels * 2; i++)
2713 address[count++] = derivs[i];
2714
2715 /* Pack texture coordinates */
2716 address[count++] = coords[0];
2717 if (num_coords > 1)
2718 address[count++] = coords[1];
2719 if (num_coords > 2)
2720 address[count++] = coords[2];
2721
2722 /* Pack LOD or sample index */
2723 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
2724 address[count++] = coords[3];
2725 else if (opcode == TGSI_OPCODE_TXL2)
2726 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2727
2728 if (count > 16) {
2729 assert(!"Cannot handle more than 16 texture address parameters");
2730 count = 16;
2731 }
2732
2733 for (chan = 0; chan < count; chan++ ) {
2734 address[chan] = LLVMBuildBitCast(gallivm->builder,
2735 address[chan], i32, "");
2736 }
2737
2738 /* Adjust the sample index according to FMASK.
2739 *
2740 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2741 * which is the identity mapping. Each nibble says which physical sample
2742 * should be fetched to get that sample.
2743 *
2744 * For example, 0x11111100 means there are only 2 samples stored and
2745 * the second sample covers 3/4 of the pixel. When reading samples 0
2746 * and 1, return physical sample 0 (determined by the first two 0s
2747 * in FMASK), otherwise return physical sample 1.
2748 *
2749 * The sample index should be adjusted as follows:
2750 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2751 */
2752 if (target == TGSI_TEXTURE_2D_MSAA ||
2753 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2754 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2755 struct lp_build_emit_data txf_emit_data = *emit_data;
2756 LLVMValueRef txf_address[4];
2757 unsigned txf_count = count;
2758 struct tgsi_full_instruction inst = {};
2759
2760 memcpy(txf_address, address, sizeof(txf_address));
2761
2762 if (target == TGSI_TEXTURE_2D_MSAA) {
2763 txf_address[2] = bld_base->uint_bld.zero;
2764 }
2765 txf_address[3] = bld_base->uint_bld.zero;
2766
2767 /* Read FMASK using TXF. */
2768 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
2769 inst.Texture.Texture = target;
2770 txf_emit_data.inst = &inst;
2771 txf_emit_data.chan = 0;
2772 set_tex_fetch_args(gallivm, &txf_emit_data, TGSI_OPCODE_TXF,
2773 target, fmask_ptr, NULL,
2774 txf_address, txf_count, 0xf);
2775 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
2776
2777 /* Initialize some constants. */
2778 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
2779 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
2780
2781 /* Apply the formula. */
2782 LLVMValueRef fmask =
2783 LLVMBuildExtractElement(gallivm->builder,
2784 txf_emit_data.output[0],
2785 uint_bld->zero, "");
2786
2787 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
2788
2789 LLVMValueRef sample_index4 =
2790 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
2791
2792 LLVMValueRef shifted_fmask =
2793 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
2794
2795 LLVMValueRef final_sample =
2796 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
2797
2798 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2799 * resource descriptor is 0 (invalid),
2800 */
2801 LLVMValueRef fmask_desc =
2802 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
2803 LLVMVectorType(uint_bld->elem_type, 8), "");
2804
2805 LLVMValueRef fmask_word1 =
2806 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
2807 uint_bld->one, "");
2808
2809 LLVMValueRef word1_is_nonzero =
2810 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
2811 fmask_word1, uint_bld->zero, "");
2812
2813 /* Replace the MSAA sample index. */
2814 address[sample_chan] =
2815 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
2816 final_sample, address[sample_chan], "");
2817 }
2818
2819 if (opcode == TGSI_OPCODE_TXF) {
2820 /* add tex offsets */
2821 if (inst->Texture.NumOffsets) {
2822 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2823 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
2824 const struct tgsi_texture_offset * off = inst->TexOffsets;
2825
2826 assert(inst->Texture.NumOffsets == 1);
2827
2828 switch (target) {
2829 case TGSI_TEXTURE_3D:
2830 address[2] = lp_build_add(uint_bld, address[2],
2831 bld->immediates[off->Index][off->SwizzleZ]);
2832 /* fall through */
2833 case TGSI_TEXTURE_2D:
2834 case TGSI_TEXTURE_SHADOW2D:
2835 case TGSI_TEXTURE_RECT:
2836 case TGSI_TEXTURE_SHADOWRECT:
2837 case TGSI_TEXTURE_2D_ARRAY:
2838 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2839 address[1] =
2840 lp_build_add(uint_bld, address[1],
2841 bld->immediates[off->Index][off->SwizzleY]);
2842 /* fall through */
2843 case TGSI_TEXTURE_1D:
2844 case TGSI_TEXTURE_SHADOW1D:
2845 case TGSI_TEXTURE_1D_ARRAY:
2846 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2847 address[0] =
2848 lp_build_add(uint_bld, address[0],
2849 bld->immediates[off->Index][off->SwizzleX]);
2850 break;
2851 /* texture offsets do not apply to other texture targets */
2852 }
2853 }
2854 }
2855
2856 if (opcode == TGSI_OPCODE_TG4) {
2857 unsigned gather_comp = 0;
2858
2859 /* DMASK was repurposed for GATHER4. 4 components are always
2860 * returned and DMASK works like a swizzle - it selects
2861 * the component to fetch. The only valid DMASK values are
2862 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2863 * (red,red,red,red) etc.) The ISA document doesn't mention
2864 * this.
2865 */
2866
2867 /* Get the component index from src1.x for Gather4. */
2868 if (!tgsi_is_shadow_target(target)) {
2869 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
2870 LLVMValueRef comp_imm;
2871 struct tgsi_src_register src1 = inst->Src[1].Register;
2872
2873 assert(src1.File == TGSI_FILE_IMMEDIATE);
2874
2875 comp_imm = imms[src1.Index][src1.SwizzleX];
2876 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
2877 gather_comp = CLAMP(gather_comp, 0, 3);
2878 }
2879
2880 dmask = 1 << gather_comp;
2881 }
2882
2883 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2884 samp_ptr, address, count, dmask);
2885 }
2886
2887 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2888 struct lp_build_tgsi_context * bld_base,
2889 struct lp_build_emit_data * emit_data)
2890 {
2891 struct lp_build_context * base = &bld_base->base;
2892 unsigned opcode = emit_data->inst->Instruction.Opcode;
2893 unsigned target = emit_data->inst->Texture.Texture;
2894 char intr_name[127];
2895 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
2896 bool is_shadow = tgsi_is_shadow_target(target);
2897 char type[64];
2898 const char *name = "llvm.SI.image.sample";
2899 const char *infix = "";
2900
2901 if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
2902 /* Just return the buffer size. */
2903 emit_data->output[emit_data->chan] = emit_data->args[0];
2904 return;
2905 }
2906
2907 if (target == TGSI_TEXTURE_BUFFER) {
2908 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2909 base->gallivm->builder,
2910 "llvm.SI.vs.load.input", emit_data->dst_type,
2911 emit_data->args, emit_data->arg_count,
2912 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2913 return;
2914 }
2915
2916 switch (opcode) {
2917 case TGSI_OPCODE_TXF:
2918 name = target == TGSI_TEXTURE_2D_MSAA ||
2919 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
2920 "llvm.SI.image.load" :
2921 "llvm.SI.image.load.mip";
2922 is_shadow = false;
2923 has_offset = false;
2924 break;
2925 case TGSI_OPCODE_TXQ:
2926 name = "llvm.SI.getresinfo";
2927 is_shadow = false;
2928 has_offset = false;
2929 break;
2930 case TGSI_OPCODE_LODQ:
2931 name = "llvm.SI.getlod";
2932 is_shadow = false;
2933 has_offset = false;
2934 break;
2935 case TGSI_OPCODE_TEX:
2936 case TGSI_OPCODE_TEX2:
2937 case TGSI_OPCODE_TXP:
2938 break;
2939 case TGSI_OPCODE_TXB:
2940 case TGSI_OPCODE_TXB2:
2941 infix = ".b";
2942 break;
2943 case TGSI_OPCODE_TXL:
2944 case TGSI_OPCODE_TXL2:
2945 infix = ".l";
2946 break;
2947 case TGSI_OPCODE_TXD:
2948 infix = ".d";
2949 break;
2950 case TGSI_OPCODE_TG4:
2951 name = "llvm.SI.gather4";
2952 break;
2953 default:
2954 assert(0);
2955 return;
2956 }
2957
2958 if (LLVMGetTypeKind(LLVMTypeOf(emit_data->args[0])) == LLVMVectorTypeKind)
2959 sprintf(type, ".v%ui32",
2960 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2961 else
2962 strcpy(type, ".i32");
2963
2964 /* Add the type and suffixes .c, .o if needed. */
2965 sprintf(intr_name, "%s%s%s%s%s",
2966 name, is_shadow ? ".c" : "", infix,
2967 has_offset ? ".o" : "", type);
2968
2969 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2970 base->gallivm->builder, intr_name, emit_data->dst_type,
2971 emit_data->args, emit_data->arg_count,
2972 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2973
2974 /* Divide the number of layers by 6 to get the number of cubes. */
2975 if (opcode == TGSI_OPCODE_TXQ &&
2976 (target == TGSI_TEXTURE_CUBE_ARRAY ||
2977 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
2978 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2979 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2980 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2981
2982 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2983 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2984 z = LLVMBuildSDiv(builder, z, six, "");
2985
2986 emit_data->output[emit_data->chan] =
2987 LLVMBuildInsertElement(builder, v4, z, two, "");
2988 }
2989 }
2990
2991 static void si_llvm_emit_txqs(
2992 const struct lp_build_tgsi_action * action,
2993 struct lp_build_tgsi_context * bld_base,
2994 struct lp_build_emit_data * emit_data)
2995 {
2996 struct gallivm_state *gallivm = bld_base->base.gallivm;
2997 LLVMBuilderRef builder = gallivm->builder;
2998 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2999 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
3000 LLVMValueRef res, samples;
3001 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
3002
3003 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
3004
3005
3006 /* Read the samples from the descriptor directly. */
3007 res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
3008 samples = LLVMBuildExtractElement(
3009 builder, res,
3010 lp_build_const_int32(gallivm, 3), "");
3011 samples = LLVMBuildLShr(builder, samples,
3012 lp_build_const_int32(gallivm, 16), "");
3013 samples = LLVMBuildAnd(builder, samples,
3014 lp_build_const_int32(gallivm, 0xf), "");
3015 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
3016 samples, "");
3017
3018 emit_data->output[emit_data->chan] = samples;
3019 }
3020
3021 /*
3022 * SI implements derivatives using the local data store (LDS)
3023 * All writes to the LDS happen in all executing threads at
3024 * the same time. TID is the Thread ID for the current
3025 * thread and is a value between 0 and 63, representing
3026 * the thread's position in the wavefront.
3027 *
3028 * For the pixel shader threads are grouped into quads of four pixels.
3029 * The TIDs of the pixels of a quad are:
3030 *
3031 * +------+------+
3032 * |4n + 0|4n + 1|
3033 * +------+------+
3034 * |4n + 2|4n + 3|
3035 * +------+------+
3036 *
3037 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
3038 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
3039 * the current pixel's column, and masking with 0xfffffffe yields the TID
3040 * of the left pixel of the current pixel's row.
3041 *
3042 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
3043 * adding 2 yields the TID of the pixel below the top pixel.
3044 */
3045 /* masks for thread ID. */
3046 #define TID_MASK_TOP_LEFT 0xfffffffc
3047 #define TID_MASK_TOP 0xfffffffd
3048 #define TID_MASK_LEFT 0xfffffffe
3049
3050 static void si_llvm_emit_ddxy(
3051 const struct lp_build_tgsi_action * action,
3052 struct lp_build_tgsi_context * bld_base,
3053 struct lp_build_emit_data * emit_data)
3054 {
3055 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3056 struct gallivm_state *gallivm = bld_base->base.gallivm;
3057 struct lp_build_context * base = &bld_base->base;
3058 const struct tgsi_full_instruction *inst = emit_data->inst;
3059 unsigned opcode = inst->Instruction.Opcode;
3060 LLVMValueRef indices[2];
3061 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
3062 LLVMValueRef tl, trbl, result[4];
3063 LLVMTypeRef i32;
3064 unsigned swizzle[4];
3065 unsigned c;
3066 int idx;
3067 unsigned mask;
3068
3069 i32 = LLVMInt32TypeInContext(gallivm->context);
3070
3071 indices[0] = bld_base->uint_bld.zero;
3072 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
3073 NULL, 0, LLVMReadNoneAttribute);
3074 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3075 indices, 2, "");
3076
3077 if (opcode == TGSI_OPCODE_DDX_FINE)
3078 mask = TID_MASK_LEFT;
3079 else if (opcode == TGSI_OPCODE_DDY_FINE)
3080 mask = TID_MASK_TOP;
3081 else
3082 mask = TID_MASK_TOP_LEFT;
3083
3084 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
3085 lp_build_const_int32(gallivm, mask), "");
3086 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3087 indices, 2, "");
3088
3089 /* for DDX we want to next X pixel, DDY next Y pixel. */
3090 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3091 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
3092 lp_build_const_int32(gallivm, idx), "");
3093 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3094 indices, 2, "");
3095
3096 for (c = 0; c < 4; ++c) {
3097 unsigned i;
3098
3099 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
3100 for (i = 0; i < c; ++i) {
3101 if (swizzle[i] == swizzle[c]) {
3102 result[c] = result[i];
3103 break;
3104 }
3105 }
3106 if (i != c)
3107 continue;
3108
3109 LLVMBuildStore(gallivm->builder,
3110 LLVMBuildBitCast(gallivm->builder,
3111 lp_build_emit_fetch(bld_base, inst, 0, c),
3112 i32, ""),
3113 store_ptr);
3114
3115 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
3116 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3117
3118 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
3119 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
3120
3121 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
3122 }
3123
3124 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
3125 }
3126
3127 /*
3128 * this takes an I,J coordinate pair,
3129 * and works out the X and Y derivatives.
3130 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3131 */
3132 static LLVMValueRef si_llvm_emit_ddxy_interp(
3133 struct lp_build_tgsi_context *bld_base,
3134 LLVMValueRef interp_ij)
3135 {
3136 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3137 struct gallivm_state *gallivm = bld_base->base.gallivm;
3138 struct lp_build_context *base = &bld_base->base;
3139 LLVMValueRef indices[2];
3140 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
3141 LLVMValueRef tl, tr, bl, result[4];
3142 LLVMTypeRef i32;
3143 unsigned c;
3144
3145 i32 = LLVMInt32TypeInContext(gallivm->context);
3146
3147 indices[0] = bld_base->uint_bld.zero;
3148 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
3149 NULL, 0, LLVMReadNoneAttribute);
3150 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3151 indices, 2, "");
3152
3153 temp = LLVMBuildAnd(gallivm->builder, indices[1],
3154 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
3155
3156 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
3157 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
3158
3159 indices[1] = temp;
3160 load_ptr_x = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3161 indices, 2, "");
3162
3163 indices[1] = temp2;
3164 load_ptr_y = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3165 indices, 2, "");
3166
3167 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
3168 lp_build_const_int32(gallivm, 1), "");
3169 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3170 indices, 2, "");
3171
3172 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
3173 lp_build_const_int32(gallivm, 2), "");
3174 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3175 indices, 2, "");
3176
3177 for (c = 0; c < 2; ++c) {
3178 LLVMValueRef store_val;
3179 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
3180
3181 store_val = LLVMBuildExtractElement(gallivm->builder,
3182 interp_ij, c_ll, "");
3183 LLVMBuildStore(gallivm->builder,
3184 store_val,
3185 store_ptr);
3186
3187 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
3188 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3189
3190 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
3191 tr = LLVMBuildBitCast(gallivm->builder, tr, base->elem_type, "");
3192
3193 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
3194
3195 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
3196 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3197
3198 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
3199 bl = LLVMBuildBitCast(gallivm->builder, bl, base->elem_type, "");
3200
3201 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
3202 }
3203
3204 return lp_build_gather_values(gallivm, result, 4);
3205 }
3206
3207 static void interp_fetch_args(
3208 struct lp_build_tgsi_context *bld_base,
3209 struct lp_build_emit_data *emit_data)
3210 {
3211 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3212 struct gallivm_state *gallivm = bld_base->base.gallivm;
3213 const struct tgsi_full_instruction *inst = emit_data->inst;
3214
3215 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3216 /* offset is in second src, first two channels */
3217 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3218 emit_data->inst, 1,
3219 TGSI_CHAN_X);
3220 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3221 emit_data->inst, 1,
3222 TGSI_CHAN_Y);
3223 emit_data->arg_count = 2;
3224 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3225 LLVMValueRef sample_position;
3226 LLVMValueRef sample_id;
3227 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
3228
3229 /* fetch sample ID, then fetch its sample position,
3230 * and place into first two channels.
3231 */
3232 sample_id = lp_build_emit_fetch(bld_base,
3233 emit_data->inst, 1, TGSI_CHAN_X);
3234 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
3235 LLVMInt32TypeInContext(gallivm->context),
3236 "");
3237 sample_position = load_sample_position(&si_shader_ctx->radeon_bld, sample_id);
3238
3239 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
3240 sample_position,
3241 lp_build_const_int32(gallivm, 0), "");
3242
3243 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
3244 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
3245 sample_position,
3246 lp_build_const_int32(gallivm, 1), "");
3247 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
3248 emit_data->arg_count = 2;
3249 }
3250 }
3251
3252 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3253 struct lp_build_tgsi_context *bld_base,
3254 struct lp_build_emit_data *emit_data)
3255 {
3256 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3257 struct si_shader *shader = si_shader_ctx->shader;
3258 struct gallivm_state *gallivm = bld_base->base.gallivm;
3259 LLVMValueRef interp_param;
3260 const struct tgsi_full_instruction *inst = emit_data->inst;
3261 const char *intr_name;
3262 int input_index = inst->Src[0].Register.Index;
3263 int chan;
3264 int i;
3265 LLVMValueRef attr_number;
3266 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
3267 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
3268 int interp_param_idx;
3269 unsigned interp = shader->selector->info.input_interpolate[input_index];
3270 unsigned location;
3271
3272 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
3273
3274 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3275 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3276 location = TGSI_INTERPOLATE_LOC_CENTER;
3277 else
3278 location = TGSI_INTERPOLATE_LOC_CENTROID;
3279
3280 interp_param_idx = lookup_interp_param_index(interp, location);
3281 if (interp_param_idx == -1)
3282 return;
3283 else if (interp_param_idx)
3284 interp_param = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, interp_param_idx);
3285 else
3286 interp_param = NULL;
3287
3288 attr_number = lp_build_const_int32(gallivm, input_index);
3289
3290 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3291 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3292 LLVMValueRef ij_out[2];
3293 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3294
3295 /*
3296 * take the I then J parameters, and the DDX/Y for it, and
3297 * calculate the IJ inputs for the interpolator.
3298 * temp1 = ddx * offset/sample.x + I;
3299 * interp_param.I = ddy * offset/sample.y + temp1;
3300 * temp1 = ddx * offset/sample.x + J;
3301 * interp_param.J = ddy * offset/sample.y + temp1;
3302 */
3303 for (i = 0; i < 2; i++) {
3304 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
3305 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
3306 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
3307 ddxy_out, ix_ll, "");
3308 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
3309 ddxy_out, iy_ll, "");
3310 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
3311 interp_param, ix_ll, "");
3312 LLVMValueRef temp1, temp2;
3313
3314 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
3315 LLVMFloatTypeInContext(gallivm->context), "");
3316
3317 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
3318
3319 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
3320
3321 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
3322
3323 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
3324
3325 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
3326 temp2,
3327 LLVMIntTypeInContext(gallivm->context, 32), "");
3328 }
3329 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
3330 }
3331
3332 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3333 for (chan = 0; chan < 2; chan++) {
3334 LLVMValueRef args[4];
3335 LLVMValueRef llvm_chan;
3336 unsigned schan;
3337
3338 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3339 llvm_chan = lp_build_const_int32(gallivm, schan);
3340
3341 args[0] = llvm_chan;
3342 args[1] = attr_number;
3343 args[2] = params;
3344 args[3] = interp_param;
3345
3346 emit_data->output[chan] =
3347 lp_build_intrinsic(gallivm->builder, intr_name,
3348 input_type, args, args[3] ? 4 : 3,
3349 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3350 }
3351 }
3352
3353 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
3354 struct lp_build_emit_data *emit_data)
3355 {
3356 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3357 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
3358 unsigned stream;
3359
3360 assert(src0.File == TGSI_FILE_IMMEDIATE);
3361
3362 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
3363 return stream;
3364 }
3365
3366 /* Emit one vertex from the geometry shader */
3367 static void si_llvm_emit_vertex(
3368 const struct lp_build_tgsi_action *action,
3369 struct lp_build_tgsi_context *bld_base,
3370 struct lp_build_emit_data *emit_data)
3371 {
3372 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3373 struct lp_build_context *uint = &bld_base->uint_bld;
3374 struct si_shader *shader = si_shader_ctx->shader;
3375 struct tgsi_shader_info *info = &shader->selector->info;
3376 struct gallivm_state *gallivm = bld_base->base.gallivm;
3377 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
3378 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3379 SI_PARAM_GS2VS_OFFSET);
3380 LLVMValueRef gs_next_vertex;
3381 LLVMValueRef can_emit, kill;
3382 LLVMValueRef args[2];
3383 unsigned chan;
3384 int i;
3385 unsigned stream;
3386
3387 stream = si_llvm_get_stream(bld_base, emit_data);
3388
3389 /* Write vertex attribute values to GSVS ring */
3390 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
3391 si_shader_ctx->gs_next_vertex[stream],
3392 "");
3393
3394 /* If this thread has already emitted the declared maximum number of
3395 * vertices, kill it: excessive vertex emissions are not supposed to
3396 * have any effect, and GS threads have no externally observable
3397 * effects other than emitting vertices.
3398 */
3399 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
3400 lp_build_const_int32(gallivm,
3401 shader->selector->gs_max_out_vertices), "");
3402 kill = lp_build_select(&bld_base->base, can_emit,
3403 lp_build_const_float(gallivm, 1.0f),
3404 lp_build_const_float(gallivm, -1.0f));
3405
3406 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
3407 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
3408
3409 for (i = 0; i < info->num_outputs; i++) {
3410 LLVMValueRef *out_ptr =
3411 si_shader_ctx->radeon_bld.soa.outputs[i];
3412
3413 for (chan = 0; chan < 4; chan++) {
3414 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3415 LLVMValueRef voffset =
3416 lp_build_const_int32(gallivm, (i * 4 + chan) *
3417 shader->selector->gs_max_out_vertices);
3418
3419 voffset = lp_build_add(uint, voffset, gs_next_vertex);
3420 voffset = lp_build_mul_imm(uint, voffset, 4);
3421
3422 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
3423
3424 build_tbuffer_store(si_shader_ctx,
3425 si_shader_ctx->gsvs_ring[stream],
3426 out_val, 1,
3427 voffset, soffset, 0,
3428 V_008F0C_BUF_DATA_FORMAT_32,
3429 V_008F0C_BUF_NUM_FORMAT_UINT,
3430 1, 0, 1, 1, 0);
3431 }
3432 }
3433 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
3434 lp_build_const_int32(gallivm, 1));
3435
3436 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex[stream]);
3437
3438 /* Signal vertex emission */
3439 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
3440 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3441 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3442 LLVMVoidTypeInContext(gallivm->context), args, 2,
3443 LLVMNoUnwindAttribute);
3444 }
3445
3446 /* Cut one primitive from the geometry shader */
3447 static void si_llvm_emit_primitive(
3448 const struct lp_build_tgsi_action *action,
3449 struct lp_build_tgsi_context *bld_base,
3450 struct lp_build_emit_data *emit_data)
3451 {
3452 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3453 struct gallivm_state *gallivm = bld_base->base.gallivm;
3454 LLVMValueRef args[2];
3455 unsigned stream;
3456
3457 /* Signal primitive cut */
3458 stream = si_llvm_get_stream(bld_base, emit_data);
3459 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
3460 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3461 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3462 LLVMVoidTypeInContext(gallivm->context), args, 2,
3463 LLVMNoUnwindAttribute);
3464 }
3465
3466 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
3467 struct lp_build_tgsi_context *bld_base,
3468 struct lp_build_emit_data *emit_data)
3469 {
3470 struct gallivm_state *gallivm = bld_base->base.gallivm;
3471
3472 lp_build_intrinsic(gallivm->builder,
3473 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
3474 : "llvm.AMDGPU.barrier.local",
3475 LLVMVoidTypeInContext(gallivm->context), NULL, 0,
3476 LLVMNoUnwindAttribute);
3477 }
3478
3479 static const struct lp_build_tgsi_action tex_action = {
3480 .fetch_args = tex_fetch_args,
3481 .emit = build_tex_intrinsic,
3482 };
3483
3484 static const struct lp_build_tgsi_action interp_action = {
3485 .fetch_args = interp_fetch_args,
3486 .emit = build_interp_intrinsic,
3487 };
3488
3489 static void create_meta_data(struct si_shader_context *si_shader_ctx)
3490 {
3491 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3492 LLVMValueRef args[3];
3493
3494 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
3495 args[1] = 0;
3496 args[2] = lp_build_const_int32(gallivm, 1);
3497
3498 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
3499 }
3500
3501 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3502 {
3503 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3504 CONST_ADDR_SPACE);
3505 }
3506
3507 static void declare_streamout_params(struct si_shader_context *si_shader_ctx,
3508 struct pipe_stream_output_info *so,
3509 LLVMTypeRef *params, LLVMTypeRef i32,
3510 unsigned *num_params)
3511 {
3512 int i;
3513
3514 /* Streamout SGPRs. */
3515 if (so->num_outputs) {
3516 params[si_shader_ctx->param_streamout_config = (*num_params)++] = i32;
3517 params[si_shader_ctx->param_streamout_write_index = (*num_params)++] = i32;
3518 }
3519 /* A streamout buffer offset is loaded if the stride is non-zero. */
3520 for (i = 0; i < 4; i++) {
3521 if (!so->stride[i])
3522 continue;
3523
3524 params[si_shader_ctx->param_streamout_offset[i] = (*num_params)++] = i32;
3525 }
3526 }
3527
3528 static void create_function(struct si_shader_context *si_shader_ctx)
3529 {
3530 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3531 struct gallivm_state *gallivm = bld_base->base.gallivm;
3532 struct si_shader *shader = si_shader_ctx->shader;
3533 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
3534 unsigned i, last_array_pointer, last_sgpr, num_params;
3535
3536 i8 = LLVMInt8TypeInContext(gallivm->context);
3537 i32 = LLVMInt32TypeInContext(gallivm->context);
3538 f32 = LLVMFloatTypeInContext(gallivm->context);
3539 v2i32 = LLVMVectorType(i32, 2);
3540 v3i32 = LLVMVectorType(i32, 3);
3541 v4i32 = LLVMVectorType(i32, 4);
3542 v8i32 = LLVMVectorType(i32, 8);
3543 v16i8 = LLVMVectorType(i8, 16);
3544
3545 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
3546 params[SI_PARAM_CONST_BUFFERS] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
3547 params[SI_PARAM_SAMPLER_STATES] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
3548 params[SI_PARAM_SAMPLER_VIEWS] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
3549 last_array_pointer = SI_PARAM_SAMPLER_VIEWS;
3550
3551 switch (si_shader_ctx->type) {
3552 case TGSI_PROCESSOR_VERTEX:
3553 params[SI_PARAM_VERTEX_BUFFERS] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
3554 last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
3555 params[SI_PARAM_BASE_VERTEX] = i32;
3556 params[SI_PARAM_START_INSTANCE] = i32;
3557 num_params = SI_PARAM_START_INSTANCE+1;
3558
3559 if (shader->key.vs.as_es) {
3560 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3561 } else if (shader->key.vs.as_ls) {
3562 params[SI_PARAM_LS_OUT_LAYOUT] = i32;
3563 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
3564 } else {
3565 if (si_shader_ctx->is_gs_copy_shader) {
3566 last_array_pointer = SI_PARAM_CONST_BUFFERS;
3567 num_params = SI_PARAM_CONST_BUFFERS+1;
3568 } else {
3569 params[SI_PARAM_VS_STATE_BITS] = i32;
3570 num_params = SI_PARAM_VS_STATE_BITS+1;
3571 }
3572
3573 /* The locations of the other parameters are assigned dynamically. */
3574 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3575 params, i32, &num_params);
3576 }
3577
3578 last_sgpr = num_params-1;
3579
3580 /* VGPRs */
3581 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
3582 params[si_shader_ctx->param_rel_auto_id = num_params++] = i32;
3583 params[si_shader_ctx->param_vs_prim_id = num_params++] = i32;
3584 params[si_shader_ctx->param_instance_id = num_params++] = i32;
3585 break;
3586
3587 case TGSI_PROCESSOR_TESS_CTRL:
3588 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3589 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3590 params[SI_PARAM_TCS_IN_LAYOUT] = i32;
3591 params[SI_PARAM_TESS_FACTOR_OFFSET] = i32;
3592 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
3593
3594 /* VGPRs */
3595 params[SI_PARAM_PATCH_ID] = i32;
3596 params[SI_PARAM_REL_IDS] = i32;
3597 num_params = SI_PARAM_REL_IDS+1;
3598 break;
3599
3600 case TGSI_PROCESSOR_TESS_EVAL:
3601 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3602 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3603 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
3604
3605 if (shader->key.tes.as_es) {
3606 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3607 } else {
3608 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3609 params, i32, &num_params);
3610 }
3611 last_sgpr = num_params - 1;
3612
3613 /* VGPRs */
3614 params[si_shader_ctx->param_tes_u = num_params++] = f32;
3615 params[si_shader_ctx->param_tes_v = num_params++] = f32;
3616 params[si_shader_ctx->param_tes_rel_patch_id = num_params++] = i32;
3617 params[si_shader_ctx->param_tes_patch_id = num_params++] = i32;
3618 break;
3619
3620 case TGSI_PROCESSOR_GEOMETRY:
3621 params[SI_PARAM_GS2VS_OFFSET] = i32;
3622 params[SI_PARAM_GS_WAVE_ID] = i32;
3623 last_sgpr = SI_PARAM_GS_WAVE_ID;
3624
3625 /* VGPRs */
3626 params[SI_PARAM_VTX0_OFFSET] = i32;
3627 params[SI_PARAM_VTX1_OFFSET] = i32;
3628 params[SI_PARAM_PRIMITIVE_ID] = i32;
3629 params[SI_PARAM_VTX2_OFFSET] = i32;
3630 params[SI_PARAM_VTX3_OFFSET] = i32;
3631 params[SI_PARAM_VTX4_OFFSET] = i32;
3632 params[SI_PARAM_VTX5_OFFSET] = i32;
3633 params[SI_PARAM_GS_INSTANCE_ID] = i32;
3634 num_params = SI_PARAM_GS_INSTANCE_ID+1;
3635 break;
3636
3637 case TGSI_PROCESSOR_FRAGMENT:
3638 params[SI_PARAM_ALPHA_REF] = f32;
3639 params[SI_PARAM_PRIM_MASK] = i32;
3640 last_sgpr = SI_PARAM_PRIM_MASK;
3641 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
3642 params[SI_PARAM_PERSP_CENTER] = v2i32;
3643 params[SI_PARAM_PERSP_CENTROID] = v2i32;
3644 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
3645 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
3646 params[SI_PARAM_LINEAR_CENTER] = v2i32;
3647 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
3648 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
3649 params[SI_PARAM_POS_X_FLOAT] = f32;
3650 params[SI_PARAM_POS_Y_FLOAT] = f32;
3651 params[SI_PARAM_POS_Z_FLOAT] = f32;
3652 params[SI_PARAM_POS_W_FLOAT] = f32;
3653 params[SI_PARAM_FRONT_FACE] = i32;
3654 params[SI_PARAM_ANCILLARY] = i32;
3655 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
3656 params[SI_PARAM_POS_FIXED_PT] = f32;
3657 num_params = SI_PARAM_POS_FIXED_PT+1;
3658 break;
3659
3660 default:
3661 assert(0 && "unimplemented shader");
3662 return;
3663 }
3664
3665 assert(num_params <= Elements(params));
3666 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
3667 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
3668
3669 for (i = 0; i <= last_sgpr; ++i) {
3670 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
3671
3672 /* We tell llvm that array inputs are passed by value to allow Sinking pass
3673 * to move load. Inputs are constant so this is fine. */
3674 if (i <= last_array_pointer)
3675 LLVMAddAttribute(P, LLVMByValAttribute);
3676 else
3677 LLVMAddAttribute(P, LLVMInRegAttribute);
3678 }
3679
3680 if (bld_base->info &&
3681 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
3682 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
3683 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
3684 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
3685 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
3686 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
3687 si_shader_ctx->lds =
3688 LLVMAddGlobalInAddressSpace(gallivm->module,
3689 LLVMArrayType(i32, 64),
3690 "ddxy_lds",
3691 LOCAL_ADDR_SPACE);
3692
3693 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
3694 si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
3695 si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL) {
3696 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
3697 unsigned vertex_data_dw_size = 32*32*4;
3698 unsigned patch_data_dw_size = 32*4;
3699 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
3700 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
3701 unsigned lds_dwords = patch_dw_size;
3702
3703 /* The actual size is computed outside of the shader to reduce
3704 * the number of shader variants. */
3705 si_shader_ctx->lds =
3706 LLVMAddGlobalInAddressSpace(gallivm->module,
3707 LLVMArrayType(i32, lds_dwords),
3708 "tess_lds",
3709 LOCAL_ADDR_SPACE);
3710 }
3711 }
3712
3713 static void preload_constants(struct si_shader_context *si_shader_ctx)
3714 {
3715 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3716 struct gallivm_state * gallivm = bld_base->base.gallivm;
3717 const struct tgsi_shader_info * info = bld_base->info;
3718 unsigned buf;
3719 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
3720
3721 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
3722 unsigned i, num_const = info->const_file_max[buf] + 1;
3723
3724 if (num_const == 0)
3725 continue;
3726
3727 /* Allocate space for the constant values */
3728 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
3729
3730 /* Load the resource descriptor */
3731 si_shader_ctx->const_buffers[buf] =
3732 build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
3733
3734 /* Load the constants, we rely on the code sinking to do the rest */
3735 for (i = 0; i < num_const * 4; ++i) {
3736 si_shader_ctx->constants[buf][i] =
3737 buffer_load_const(gallivm->builder,
3738 si_shader_ctx->const_buffers[buf],
3739 lp_build_const_int32(gallivm, i * 4),
3740 bld_base->base.elem_type);
3741 }
3742 }
3743 }
3744
3745 static void preload_samplers(struct si_shader_context *si_shader_ctx)
3746 {
3747 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3748 struct gallivm_state * gallivm = bld_base->base.gallivm;
3749 const struct tgsi_shader_info * info = bld_base->info;
3750
3751 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
3752
3753 LLVMValueRef res_ptr, samp_ptr;
3754 LLVMValueRef offset;
3755
3756 if (num_samplers == 0)
3757 return;
3758
3759 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
3760 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
3761
3762 /* Load the resources and samplers, we rely on the code sinking to do the rest */
3763 for (i = 0; i < num_samplers; ++i) {
3764 /* Resource */
3765 offset = lp_build_const_int32(gallivm, i);
3766 si_shader_ctx->sampler_views[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3767
3768 /* Sampler */
3769 offset = lp_build_const_int32(gallivm, i);
3770 si_shader_ctx->sampler_states[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
3771
3772 /* FMASK resource */
3773 if (info->is_msaa_sampler[i]) {
3774 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
3775 si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + i] =
3776 build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3777 }
3778 }
3779 }
3780
3781 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
3782 {
3783 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3784 struct gallivm_state * gallivm = bld_base->base.gallivm;
3785 unsigned i;
3786
3787 /* Streamout can only be used if the shader is compiled as VS. */
3788 if (!si_shader_ctx->shader->selector->so.num_outputs ||
3789 (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3790 (si_shader_ctx->shader->key.vs.as_es ||
3791 si_shader_ctx->shader->key.vs.as_ls)) ||
3792 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3793 si_shader_ctx->shader->key.tes.as_es))
3794 return;
3795
3796 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3797 SI_PARAM_RW_BUFFERS);
3798
3799 /* Load the resources, we rely on the code sinking to do the rest */
3800 for (i = 0; i < 4; ++i) {
3801 if (si_shader_ctx->shader->selector->so.stride[i]) {
3802 LLVMValueRef offset = lp_build_const_int32(gallivm,
3803 SI_SO_BUF_OFFSET + i);
3804
3805 si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3806 }
3807 }
3808 }
3809
3810 /**
3811 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
3812 * for later use.
3813 */
3814 static void preload_ring_buffers(struct si_shader_context *si_shader_ctx)
3815 {
3816 struct gallivm_state *gallivm =
3817 si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3818
3819 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3820 SI_PARAM_RW_BUFFERS);
3821
3822 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3823 si_shader_ctx->shader->key.vs.as_es) ||
3824 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3825 si_shader_ctx->shader->key.tes.as_es) ||
3826 si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3827 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
3828
3829 si_shader_ctx->esgs_ring =
3830 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3831 }
3832
3833 if (si_shader_ctx->is_gs_copy_shader) {
3834 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
3835
3836 si_shader_ctx->gsvs_ring[0] =
3837 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3838 }
3839 if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3840 int i;
3841 for (i = 0; i < 4; i++) {
3842 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i);
3843
3844 si_shader_ctx->gsvs_ring[i] =
3845 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3846 }
3847 }
3848 }
3849
3850 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
3851 struct si_shader_config *conf,
3852 unsigned symbol_offset)
3853 {
3854 unsigned i;
3855 const unsigned char *config =
3856 radeon_shader_binary_config_start(binary, symbol_offset);
3857
3858 /* XXX: We may be able to emit some of these values directly rather than
3859 * extracting fields to be emitted later.
3860 */
3861
3862 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
3863 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
3864 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
3865 switch (reg) {
3866 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
3867 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
3868 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
3869 case R_00B848_COMPUTE_PGM_RSRC1:
3870 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
3871 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
3872 conf->float_mode = G_00B028_FLOAT_MODE(value);
3873 conf->rsrc1 = value;
3874 break;
3875 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
3876 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
3877 break;
3878 case R_00B84C_COMPUTE_PGM_RSRC2:
3879 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
3880 conf->rsrc2 = value;
3881 break;
3882 case R_0286CC_SPI_PS_INPUT_ENA:
3883 conf->spi_ps_input_ena = value;
3884 break;
3885 case R_0286D0_SPI_PS_INPUT_ADDR:
3886 conf->spi_ps_input_addr = value;
3887 break;
3888 case R_0286E8_SPI_TMPRING_SIZE:
3889 case R_00B860_COMPUTE_TMPRING_SIZE:
3890 /* WAVESIZE is in units of 256 dwords. */
3891 conf->scratch_bytes_per_wave =
3892 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
3893 break;
3894 default:
3895 {
3896 static bool printed;
3897
3898 if (!printed) {
3899 fprintf(stderr, "Warning: LLVM emitted unknown "
3900 "config register: 0x%x\n", reg);
3901 printed = true;
3902 }
3903 }
3904 break;
3905 }
3906
3907 if (!conf->spi_ps_input_addr)
3908 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
3909 }
3910 }
3911
3912 void si_shader_apply_scratch_relocs(struct si_context *sctx,
3913 struct si_shader *shader,
3914 uint64_t scratch_va)
3915 {
3916 unsigned i;
3917 uint32_t scratch_rsrc_dword0 = scratch_va;
3918 uint32_t scratch_rsrc_dword1 =
3919 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
3920 | S_008F04_STRIDE(shader->config.scratch_bytes_per_wave / 64);
3921
3922 for (i = 0 ; i < shader->binary.reloc_count; i++) {
3923 const struct radeon_shader_reloc *reloc =
3924 &shader->binary.relocs[i];
3925 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
3926 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3927 &scratch_rsrc_dword0, 4);
3928 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
3929 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3930 &scratch_rsrc_dword1, 4);
3931 }
3932 }
3933 }
3934
3935 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
3936 {
3937 const struct radeon_shader_binary *binary = &shader->binary;
3938 unsigned code_size = binary->code_size + binary->rodata_size;
3939 unsigned char *ptr;
3940
3941 r600_resource_reference(&shader->bo, NULL);
3942 shader->bo = si_resource_create_custom(&sscreen->b.b,
3943 PIPE_USAGE_IMMUTABLE,
3944 code_size);
3945 if (!shader->bo)
3946 return -ENOMEM;
3947
3948 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
3949 PIPE_TRANSFER_READ_WRITE);
3950 util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
3951 if (binary->rodata_size > 0) {
3952 ptr += binary->code_size;
3953 util_memcpy_cpu_to_le32(ptr, binary->rodata,
3954 binary->rodata_size);
3955 }
3956
3957 sscreen->b.ws->buffer_unmap(shader->bo->buf);
3958 return 0;
3959 }
3960
3961 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
3962 struct pipe_debug_callback *debug)
3963 {
3964 char *line, *p;
3965 unsigned i, count;
3966
3967 if (binary->disasm_string) {
3968 fprintf(stderr, "\nShader Disassembly:\n\n");
3969 fprintf(stderr, "%s\n", binary->disasm_string);
3970
3971 if (debug && debug->debug_message) {
3972 /* Very long debug messages are cut off, so send the
3973 * disassembly one line at a time. This causes more
3974 * overhead, but on the plus side it simplifies
3975 * parsing of resulting logs.
3976 */
3977 pipe_debug_message(debug, SHADER_INFO,
3978 "Shader Disassembly Begin");
3979
3980 line = binary->disasm_string;
3981 while (*line) {
3982 p = strchrnul(line, '\n');
3983 count = p - line;
3984
3985 if (count) {
3986 pipe_debug_message(debug, SHADER_INFO,
3987 "%.*s", count, line);
3988 }
3989
3990 if (!*p)
3991 break;
3992 line = p + 1;
3993 }
3994
3995 pipe_debug_message(debug, SHADER_INFO,
3996 "Shader Disassembly End");
3997 }
3998 } else {
3999 fprintf(stderr, "SI CODE:\n");
4000 for (i = 0; i < binary->code_size; i += 4) {
4001 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i,
4002 binary->code[i + 3], binary->code[i + 2],
4003 binary->code[i + 1], binary->code[i]);
4004 }
4005 }
4006 }
4007
4008 static void si_shader_dump_stats(struct si_screen *sscreen,
4009 struct si_shader_config *conf,
4010 unsigned num_inputs,
4011 unsigned code_size,
4012 struct pipe_debug_callback *debug,
4013 unsigned processor)
4014 {
4015 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
4016 unsigned lds_per_wave = 0;
4017 unsigned max_simd_waves = 10;
4018
4019 /* Compute LDS usage for PS. */
4020 if (processor == TGSI_PROCESSOR_FRAGMENT) {
4021 /* The minimum usage per wave is (num_inputs * 36). The maximum
4022 * usage is (num_inputs * 36 * 16).
4023 * We can get anything in between and it varies between waves.
4024 *
4025 * Other stages don't know the size at compile time or don't
4026 * allocate LDS per wave, but instead they do it per thread group.
4027 */
4028 lds_per_wave = conf->lds_size * lds_increment +
4029 align(num_inputs * 36, lds_increment);
4030 }
4031
4032 /* Compute the per-SIMD wave counts. */
4033 if (conf->num_sgprs) {
4034 if (sscreen->b.chip_class >= VI)
4035 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
4036 else
4037 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
4038 }
4039
4040 if (conf->num_vgprs)
4041 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
4042
4043 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
4044 * that PS can use.
4045 */
4046 if (lds_per_wave)
4047 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
4048
4049 if (r600_can_dump_shader(&sscreen->b, processor)) {
4050 if (processor == TGSI_PROCESSOR_FRAGMENT) {
4051 fprintf(stderr, "*** SHADER CONFIG ***\n"
4052 "SPI_PS_INPUT_ADDR = 0x%04x\n"
4053 "SPI_PS_INPUT_ENA = 0x%04x\n",
4054 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
4055 }
4056
4057 fprintf(stderr, "*** SHADER STATS ***\n"
4058 "SGPRS: %d\n"
4059 "VGPRS: %d\n"
4060 "Code Size: %d bytes\n"
4061 "LDS: %d blocks\n"
4062 "Scratch: %d bytes per wave\n"
4063 "Max Waves: %d\n"
4064 "********************\n",
4065 conf->num_sgprs, conf->num_vgprs, code_size,
4066 conf->lds_size, conf->scratch_bytes_per_wave,
4067 max_simd_waves);
4068 }
4069
4070 pipe_debug_message(debug, SHADER_INFO,
4071 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
4072 "LDS: %d Scratch: %d Max Waves: %d",
4073 conf->num_sgprs, conf->num_vgprs, code_size,
4074 conf->lds_size, conf->scratch_bytes_per_wave,
4075 max_simd_waves);
4076 }
4077
4078 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
4079 struct pipe_debug_callback *debug, unsigned processor)
4080 {
4081 if (r600_can_dump_shader(&sscreen->b, processor))
4082 if (!(sscreen->b.debug_flags & DBG_NO_ASM))
4083 si_shader_dump_disassembly(&shader->binary, debug);
4084
4085 si_shader_dump_stats(sscreen, &shader->config,
4086 shader->selector ? shader->selector->info.num_inputs : 0,
4087 shader->binary.code_size, debug, processor);
4088 }
4089
4090 int si_compile_llvm(struct si_screen *sscreen,
4091 struct radeon_shader_binary *binary,
4092 struct si_shader_config *conf,
4093 LLVMTargetMachineRef tm,
4094 LLVMModuleRef mod,
4095 struct pipe_debug_callback *debug,
4096 unsigned processor,
4097 const char *name)
4098 {
4099 int r = 0;
4100 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
4101
4102 if (r600_can_dump_shader(&sscreen->b, processor)) {
4103 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
4104
4105 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
4106 fprintf(stderr, "%s LLVM IR:\n\n", name);
4107 LLVMDumpModule(mod);
4108 fprintf(stderr, "\n");
4109 }
4110 }
4111
4112 if (!si_replace_shader(count, binary)) {
4113 r = radeon_llvm_compile(mod, binary,
4114 r600_get_llvm_processor_name(sscreen->b.family), tm,
4115 debug);
4116 if (r)
4117 return r;
4118 }
4119
4120 si_shader_binary_read_config(binary, conf, 0);
4121
4122 /* Enable 64-bit and 16-bit denormals, because there is no performance
4123 * cost.
4124 *
4125 * If denormals are enabled, all floating-point output modifiers are
4126 * ignored.
4127 *
4128 * Don't enable denormals for 32-bit floats, because:
4129 * - Floating-point output modifiers would be ignored by the hw.
4130 * - Some opcodes don't support denormals, such as v_mad_f32. We would
4131 * have to stop using those.
4132 * - SI & CI would be very slow.
4133 */
4134 conf->float_mode |= V_00B028_FP_64_DENORMS;
4135
4136 FREE(binary->config);
4137 FREE(binary->global_symbol_offsets);
4138 binary->config = NULL;
4139 binary->global_symbol_offsets = NULL;
4140 return r;
4141 }
4142
4143 /* Generate code for the hardware VS shader stage to go with a geometry shader */
4144 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
4145 struct si_shader_context *si_shader_ctx,
4146 struct si_shader *gs,
4147 struct pipe_debug_callback *debug)
4148 {
4149 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
4150 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
4151 struct lp_build_context *base = &bld_base->base;
4152 struct lp_build_context *uint = &bld_base->uint_bld;
4153 struct si_shader_output_values *outputs;
4154 struct tgsi_shader_info *gsinfo = &gs->selector->info;
4155 LLVMValueRef args[9];
4156 int i, r;
4157
4158 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
4159
4160 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
4161 si_shader_ctx->is_gs_copy_shader = true;
4162
4163 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
4164
4165 create_meta_data(si_shader_ctx);
4166 create_function(si_shader_ctx);
4167 preload_streamout_buffers(si_shader_ctx);
4168 preload_ring_buffers(si_shader_ctx);
4169
4170 args[0] = si_shader_ctx->gsvs_ring[0];
4171 args[1] = lp_build_mul_imm(uint,
4172 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
4173 si_shader_ctx->param_vertex_id),
4174 4);
4175 args[3] = uint->zero;
4176 args[4] = uint->one; /* OFFEN */
4177 args[5] = uint->zero; /* IDXEN */
4178 args[6] = uint->one; /* GLC */
4179 args[7] = uint->one; /* SLC */
4180 args[8] = uint->zero; /* TFE */
4181
4182 /* Fetch vertex data from GSVS ring */
4183 for (i = 0; i < gsinfo->num_outputs; ++i) {
4184 unsigned chan;
4185
4186 outputs[i].name = gsinfo->output_semantic_name[i];
4187 outputs[i].sid = gsinfo->output_semantic_index[i];
4188
4189 for (chan = 0; chan < 4; chan++) {
4190 args[2] = lp_build_const_int32(gallivm,
4191 (i * 4 + chan) *
4192 gs->selector->gs_max_out_vertices * 16 * 4);
4193
4194 outputs[i].values[chan] =
4195 LLVMBuildBitCast(gallivm->builder,
4196 lp_build_intrinsic(gallivm->builder,
4197 "llvm.SI.buffer.load.dword.i32.i32",
4198 LLVMInt32TypeInContext(gallivm->context),
4199 args, 9,
4200 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
4201 base->elem_type, "");
4202 }
4203 }
4204
4205 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
4206
4207 LLVMBuildRetVoid(bld_base->base.gallivm->builder);
4208
4209 /* Dump LLVM IR before any optimization passes */
4210 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
4211 r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
4212 LLVMDumpModule(bld_base->base.gallivm->module);
4213
4214 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
4215
4216 r = si_compile_llvm(sscreen, &si_shader_ctx->shader->binary,
4217 &si_shader_ctx->shader->config, si_shader_ctx->tm,
4218 bld_base->base.gallivm->module,
4219 debug, TGSI_PROCESSOR_GEOMETRY,
4220 "GS Copy Shader");
4221 if (!r) {
4222 if (r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
4223 fprintf(stderr, "GS Copy Shader:\n");
4224 si_shader_dump(sscreen, si_shader_ctx->shader, debug,
4225 TGSI_PROCESSOR_GEOMETRY);
4226 r = si_shader_binary_upload(sscreen, si_shader_ctx->shader);
4227 }
4228
4229 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
4230
4231 FREE(outputs);
4232 return r;
4233 }
4234
4235 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
4236 {
4237 int i;
4238
4239 fprintf(f, "SHADER KEY\n");
4240
4241 switch (shader) {
4242 case PIPE_SHADER_VERTEX:
4243 fprintf(f, " instance_divisors = {");
4244 for (i = 0; i < Elements(key->vs.instance_divisors); i++)
4245 fprintf(f, !i ? "%u" : ", %u",
4246 key->vs.instance_divisors[i]);
4247 fprintf(f, "}\n");
4248 fprintf(f, " as_es = %u\n", key->vs.as_es);
4249 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
4250 fprintf(f, " export_prim_id = %u\n", key->vs.export_prim_id);
4251 break;
4252
4253 case PIPE_SHADER_TESS_CTRL:
4254 fprintf(f, " prim_mode = %u\n", key->tcs.prim_mode);
4255 break;
4256
4257 case PIPE_SHADER_TESS_EVAL:
4258 fprintf(f, " as_es = %u\n", key->tes.as_es);
4259 fprintf(f, " export_prim_id = %u\n", key->tes.export_prim_id);
4260 break;
4261
4262 case PIPE_SHADER_GEOMETRY:
4263 break;
4264
4265 case PIPE_SHADER_FRAGMENT:
4266 fprintf(f, " spi_shader_col_format = 0x%x\n", key->ps.spi_shader_col_format);
4267 fprintf(f, " last_cbuf = %u\n", key->ps.last_cbuf);
4268 fprintf(f, " color_two_side = %u\n", key->ps.color_two_side);
4269 fprintf(f, " alpha_func = %u\n", key->ps.alpha_func);
4270 fprintf(f, " alpha_to_one = %u\n", key->ps.alpha_to_one);
4271 fprintf(f, " poly_stipple = %u\n", key->ps.poly_stipple);
4272 fprintf(f, " clamp_color = %u\n", key->ps.clamp_color);
4273 break;
4274
4275 default:
4276 assert(0);
4277 }
4278 }
4279
4280 static void si_init_shader_ctx(struct si_shader_context *ctx,
4281 struct si_screen *sscreen,
4282 struct si_shader *shader,
4283 LLVMTargetMachineRef tm,
4284 struct tgsi_shader_info *info)
4285 {
4286 struct lp_build_tgsi_context *bld_base;
4287
4288 memset(ctx, 0, sizeof(*ctx));
4289 radeon_llvm_context_init(&ctx->radeon_bld);
4290 ctx->tm = tm;
4291 ctx->screen = sscreen;
4292 if (shader && shader->selector)
4293 ctx->type = shader->selector->info.processor;
4294 else
4295 ctx->type = -1;
4296 ctx->shader = shader;
4297
4298 bld_base = &ctx->radeon_bld.soa.bld_base;
4299 bld_base->info = info;
4300 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
4301
4302 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
4303 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
4304 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
4305
4306 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
4307 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
4308 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
4309 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
4310 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
4311 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
4312 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
4313 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
4314 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
4315 bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
4316 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
4317 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
4318 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
4319
4320 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
4321 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
4322 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
4323 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
4324
4325 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
4326 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
4327 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
4328
4329 if (HAVE_LLVM >= 0x0306) {
4330 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
4331 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
4332 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
4333 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
4334 }
4335 }
4336
4337 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
4338 struct si_shader *shader,
4339 struct pipe_debug_callback *debug)
4340 {
4341 struct si_shader_selector *sel = shader->selector;
4342 struct tgsi_token *tokens = sel->tokens;
4343 struct si_shader_context si_shader_ctx;
4344 struct lp_build_tgsi_context * bld_base;
4345 struct tgsi_shader_info stipple_shader_info;
4346 LLVMModuleRef mod;
4347 int r = 0;
4348 bool poly_stipple = sel->type == PIPE_SHADER_FRAGMENT &&
4349 shader->key.ps.poly_stipple;
4350
4351 if (poly_stipple) {
4352 tokens = util_pstipple_create_fragment_shader(tokens, NULL,
4353 SI_POLY_STIPPLE_SAMPLER,
4354 TGSI_FILE_SYSTEM_VALUE);
4355 tgsi_scan_shader(tokens, &stipple_shader_info);
4356 }
4357
4358 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
4359 * conversion fails. */
4360 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
4361 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
4362 si_dump_shader_key(sel->type, &shader->key, stderr);
4363 tgsi_dump(tokens, 0);
4364 si_dump_streamout(&sel->so);
4365 }
4366
4367 si_init_shader_ctx(&si_shader_ctx, sscreen, shader, tm,
4368 poly_stipple ? &stipple_shader_info : &sel->info);
4369
4370 shader->uses_instanceid = sel->info.uses_instanceid;
4371
4372 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
4373 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
4374
4375 switch (si_shader_ctx.type) {
4376 case TGSI_PROCESSOR_VERTEX:
4377 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
4378 if (shader->key.vs.as_ls)
4379 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
4380 else if (shader->key.vs.as_es)
4381 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4382 else
4383 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4384 break;
4385 case TGSI_PROCESSOR_TESS_CTRL:
4386 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
4387 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
4388 bld_base->emit_store = store_output_tcs;
4389 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
4390 break;
4391 case TGSI_PROCESSOR_TESS_EVAL:
4392 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
4393 if (shader->key.tes.as_es)
4394 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4395 else
4396 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4397 break;
4398 case TGSI_PROCESSOR_GEOMETRY:
4399 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
4400 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
4401 break;
4402 case TGSI_PROCESSOR_FRAGMENT:
4403 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
4404 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
4405 break;
4406 default:
4407 assert(!"Unsupported shader type");
4408 return -1;
4409 }
4410
4411 create_meta_data(&si_shader_ctx);
4412 create_function(&si_shader_ctx);
4413 preload_constants(&si_shader_ctx);
4414 preload_samplers(&si_shader_ctx);
4415 preload_streamout_buffers(&si_shader_ctx);
4416 preload_ring_buffers(&si_shader_ctx);
4417
4418 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4419 int i;
4420 for (i = 0; i < 4; i++) {
4421 si_shader_ctx.gs_next_vertex[i] =
4422 lp_build_alloca(bld_base->base.gallivm,
4423 bld_base->uint_bld.elem_type, "");
4424 }
4425 }
4426
4427 if (!lp_build_tgsi_llvm(bld_base, tokens)) {
4428 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
4429 goto out;
4430 }
4431
4432 LLVMBuildRetVoid(bld_base->base.gallivm->builder);
4433 mod = bld_base->base.gallivm->module;
4434
4435 /* Dump LLVM IR before any optimization passes */
4436 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
4437 r600_can_dump_shader(&sscreen->b, si_shader_ctx.type))
4438 LLVMDumpModule(mod);
4439
4440 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
4441
4442 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
4443 mod, debug, si_shader_ctx.type, "TGSI shader");
4444 if (r) {
4445 fprintf(stderr, "LLVM failed to compile shader\n");
4446 goto out;
4447 }
4448
4449 si_shader_dump(sscreen, shader, debug, si_shader_ctx.type);
4450
4451 r = si_shader_binary_upload(sscreen, shader);
4452 if (r) {
4453 fprintf(stderr, "LLVM failed to upload shader\n");
4454 goto out;
4455 }
4456
4457 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
4458
4459 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4460 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
4461 shader->gs_copy_shader->selector = shader->selector;
4462 si_shader_ctx.shader = shader->gs_copy_shader;
4463 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
4464 shader, debug))) {
4465 free(shader->gs_copy_shader);
4466 shader->gs_copy_shader = NULL;
4467 goto out;
4468 }
4469 }
4470
4471 out:
4472 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
4473 FREE(si_shader_ctx.constants[i]);
4474 if (poly_stipple)
4475 tgsi_free_tokens(tokens);
4476 return r;
4477 }
4478
4479 void si_shader_destroy(struct si_shader *shader)
4480 {
4481 if (shader->gs_copy_shader) {
4482 si_shader_destroy(shader->gs_copy_shader);
4483 FREE(shader->gs_copy_shader);
4484 }
4485
4486 if (shader->scratch_bo)
4487 r600_resource_reference(&shader->scratch_bo, NULL);
4488
4489 r600_resource_reference(&shader->bo, NULL);
4490
4491 radeon_shader_binary_clean(&shader->binary);
4492 }