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ac/radeonsi: add workgroup_ids to the abi
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "gallivm/lp_bld_const.h"
25 #include "gallivm/lp_bld_gather.h"
26 #include "gallivm/lp_bld_intr.h"
27 #include "gallivm/lp_bld_logic.h"
28 #include "gallivm/lp_bld_arit.h"
29 #include "gallivm/lp_bld_flow.h"
30 #include "gallivm/lp_bld_misc.h"
31 #include "util/u_memory.h"
32 #include "util/u_string.h"
33 #include "tgsi/tgsi_build.h"
34 #include "tgsi/tgsi_util.h"
35 #include "tgsi/tgsi_dump.h"
36
37 #include "ac_binary.h"
38 #include "ac_llvm_util.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41 #include "si_shader_internal.h"
42 #include "si_pipe.h"
43 #include "sid.h"
44
45 #include "compiler/nir/nir.h"
46
47 static const char *scratch_rsrc_dword0_symbol =
48 "SCRATCH_RSRC_DWORD0";
49
50 static const char *scratch_rsrc_dword1_symbol =
51 "SCRATCH_RSRC_DWORD1";
52
53 struct si_shader_output_values
54 {
55 LLVMValueRef values[4];
56 unsigned semantic_name;
57 unsigned semantic_index;
58 ubyte vertex_stream[4];
59 };
60
61 /**
62 * Used to collect types and other info about arguments of the LLVM function
63 * before the function is created.
64 */
65 struct si_function_info {
66 LLVMTypeRef types[100];
67 LLVMValueRef *assign[100];
68 unsigned num_sgpr_params;
69 unsigned num_params;
70 };
71
72 enum si_arg_regfile {
73 ARG_SGPR,
74 ARG_VGPR
75 };
76
77 static void si_init_shader_ctx(struct si_shader_context *ctx,
78 struct si_screen *sscreen,
79 LLVMTargetMachineRef tm);
80
81 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
82 struct lp_build_tgsi_context *bld_base,
83 struct lp_build_emit_data *emit_data);
84
85 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
86 FILE *f);
87
88 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
89 union si_shader_part_key *key);
90 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
91 union si_shader_part_key *key);
92 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
93 union si_shader_part_key *key);
94 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
95 union si_shader_part_key *key);
96
97 /* Ideally pass the sample mask input to the PS epilog as v14, which
98 * is its usual location, so that the shader doesn't have to add v_mov.
99 */
100 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
101
102 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
103 LLVMTypeRef type)
104 {
105 if (type == ctx->ac.i64 || type == ctx->ac.f64)
106 return true;
107
108 return false;
109 }
110
111 static bool is_merged_shader(struct si_shader *shader)
112 {
113 if (shader->selector->screen->info.chip_class <= VI)
114 return false;
115
116 return shader->key.as_ls ||
117 shader->key.as_es ||
118 shader->selector->type == PIPE_SHADER_TESS_CTRL ||
119 shader->selector->type == PIPE_SHADER_GEOMETRY;
120 }
121
122 static void si_init_function_info(struct si_function_info *fninfo)
123 {
124 fninfo->num_params = 0;
125 fninfo->num_sgpr_params = 0;
126 }
127
128 static unsigned add_arg_assign(struct si_function_info *fninfo,
129 enum si_arg_regfile regfile, LLVMTypeRef type,
130 LLVMValueRef *assign)
131 {
132 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
133
134 unsigned idx = fninfo->num_params++;
135 assert(idx < ARRAY_SIZE(fninfo->types));
136
137 if (regfile == ARG_SGPR)
138 fninfo->num_sgpr_params = fninfo->num_params;
139
140 fninfo->types[idx] = type;
141 fninfo->assign[idx] = assign;
142 return idx;
143 }
144
145 static unsigned add_arg(struct si_function_info *fninfo,
146 enum si_arg_regfile regfile, LLVMTypeRef type)
147 {
148 return add_arg_assign(fninfo, regfile, type, NULL);
149 }
150
151 static void add_arg_assign_checked(struct si_function_info *fninfo,
152 enum si_arg_regfile regfile, LLVMTypeRef type,
153 LLVMValueRef *assign, unsigned idx)
154 {
155 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
156 assert(actual == idx);
157 }
158
159 static void add_arg_checked(struct si_function_info *fninfo,
160 enum si_arg_regfile regfile, LLVMTypeRef type,
161 unsigned idx)
162 {
163 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
164 }
165
166 /**
167 * Returns a unique index for a per-patch semantic name and index. The index
168 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
169 * can be calculated.
170 */
171 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
172 {
173 switch (semantic_name) {
174 case TGSI_SEMANTIC_TESSOUTER:
175 return 0;
176 case TGSI_SEMANTIC_TESSINNER:
177 return 1;
178 case TGSI_SEMANTIC_PATCH:
179 assert(index < 30);
180 return 2 + index;
181
182 default:
183 assert(!"invalid semantic name");
184 return 0;
185 }
186 }
187
188 /**
189 * Returns a unique index for a semantic name and index. The index must be
190 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
191 * calculated.
192 */
193 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
194 {
195 switch (semantic_name) {
196 case TGSI_SEMANTIC_POSITION:
197 return 0;
198 case TGSI_SEMANTIC_GENERIC:
199 /* Since some shader stages use the the highest used IO index
200 * to determine the size to allocate for inputs/outputs
201 * (in LDS, tess and GS rings). GENERIC should be placed right
202 * after POSITION to make that size as small as possible.
203 */
204 if (index < SI_MAX_IO_GENERIC)
205 return 1 + index;
206
207 assert(!"invalid generic index");
208 return 0;
209 case TGSI_SEMANTIC_PSIZE:
210 return SI_MAX_IO_GENERIC + 1;
211 case TGSI_SEMANTIC_CLIPDIST:
212 assert(index <= 1);
213 return SI_MAX_IO_GENERIC + 2 + index;
214 case TGSI_SEMANTIC_FOG:
215 return SI_MAX_IO_GENERIC + 4;
216 case TGSI_SEMANTIC_LAYER:
217 return SI_MAX_IO_GENERIC + 5;
218 case TGSI_SEMANTIC_VIEWPORT_INDEX:
219 return SI_MAX_IO_GENERIC + 6;
220 case TGSI_SEMANTIC_PRIMID:
221 return SI_MAX_IO_GENERIC + 7;
222 case TGSI_SEMANTIC_COLOR: /* these alias */
223 case TGSI_SEMANTIC_BCOLOR:
224 assert(index < 2);
225 return SI_MAX_IO_GENERIC + 8 + index;
226 case TGSI_SEMANTIC_TEXCOORD:
227 assert(index < 8);
228 assert(SI_MAX_IO_GENERIC + 10 + index < 64);
229 return SI_MAX_IO_GENERIC + 10 + index;
230 default:
231 assert(!"invalid semantic name");
232 return 0;
233 }
234 }
235
236 /**
237 * Get the value of a shader input parameter and extract a bitfield.
238 */
239 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
240 LLVMValueRef value, unsigned rshift,
241 unsigned bitwidth)
242 {
243 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
244 value = ac_to_integer(&ctx->ac, value);
245
246 if (rshift)
247 value = LLVMBuildLShr(ctx->ac.builder, value,
248 LLVMConstInt(ctx->i32, rshift, 0), "");
249
250 if (rshift + bitwidth < 32) {
251 unsigned mask = (1 << bitwidth) - 1;
252 value = LLVMBuildAnd(ctx->ac.builder, value,
253 LLVMConstInt(ctx->i32, mask, 0), "");
254 }
255
256 return value;
257 }
258
259 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
260 unsigned param, unsigned rshift,
261 unsigned bitwidth)
262 {
263 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
264
265 return unpack_llvm_param(ctx, value, rshift, bitwidth);
266 }
267
268 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
269 {
270 switch (ctx->type) {
271 case PIPE_SHADER_TESS_CTRL:
272 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
273
274 case PIPE_SHADER_TESS_EVAL:
275 return LLVMGetParam(ctx->main_fn,
276 ctx->param_tes_rel_patch_id);
277
278 default:
279 assert(0);
280 return NULL;
281 }
282 }
283
284 /* Tessellation shaders pass outputs to the next shader using LDS.
285 *
286 * LS outputs = TCS inputs
287 * TCS outputs = TES inputs
288 *
289 * The LDS layout is:
290 * - TCS inputs for patch 0
291 * - TCS inputs for patch 1
292 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
293 * - ...
294 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
295 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
296 * - TCS outputs for patch 1
297 * - Per-patch TCS outputs for patch 1
298 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
299 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
300 * - ...
301 *
302 * All three shaders VS(LS), TCS, TES share the same LDS space.
303 */
304
305 static LLVMValueRef
306 get_tcs_in_patch_stride(struct si_shader_context *ctx)
307 {
308 return unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
309 }
310
311 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
312 {
313 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
314
315 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
316 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
317
318 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
319 }
320
321 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
322 {
323 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
324
325 return LLVMConstInt(ctx->i32, stride, 0);
326 }
327
328 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
329 {
330 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
331 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
332
333 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
334 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
335 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
336 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
337 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
338 num_patch_outputs * 4;
339 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
340 }
341
342 static LLVMValueRef
343 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
344 {
345 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
346 unpack_param(ctx,
347 ctx->param_tcs_out_lds_offsets,
348 0, 16),
349 4);
350 }
351
352 static LLVMValueRef
353 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
354 {
355 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
356 unpack_param(ctx,
357 ctx->param_tcs_out_lds_offsets,
358 16, 16),
359 4);
360 }
361
362 static LLVMValueRef
363 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
364 {
365 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
366 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
367
368 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
369 }
370
371 static LLVMValueRef
372 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
373 {
374 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
375 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
376 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
377
378 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
379 LLVMBuildMul(ctx->ac.builder, patch_stride,
380 rel_patch_id, ""),
381 "");
382 }
383
384 static LLVMValueRef
385 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
386 {
387 LLVMValueRef patch0_patch_data_offset =
388 get_tcs_out_patch0_patch_data_offset(ctx);
389 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
390 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
391
392 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
393 LLVMBuildMul(ctx->ac.builder, patch_stride,
394 rel_patch_id, ""),
395 "");
396 }
397
398 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
399 {
400 unsigned tcs_out_vertices =
401 ctx->shader->selector ?
402 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
403
404 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
405 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
406 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
407
408 return unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
409 }
410
411 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
412 {
413 unsigned stride;
414
415 switch (ctx->type) {
416 case PIPE_SHADER_VERTEX:
417 stride = util_last_bit64(ctx->shader->selector->outputs_written);
418 return LLVMConstInt(ctx->i32, stride * 4, 0);
419
420 case PIPE_SHADER_TESS_CTRL:
421 if (ctx->screen->info.chip_class >= GFX9 &&
422 ctx->shader->is_monolithic) {
423 stride = util_last_bit64(ctx->shader->key.part.tcs.ls->outputs_written);
424 return LLVMConstInt(ctx->i32, stride * 4, 0);
425 }
426 return unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
427
428 default:
429 assert(0);
430 return NULL;
431 }
432 }
433
434 static LLVMValueRef get_instance_index_for_fetch(
435 struct si_shader_context *ctx,
436 unsigned param_start_instance, LLVMValueRef divisor)
437 {
438 LLVMValueRef result = ctx->abi.instance_id;
439
440 /* The division must be done before START_INSTANCE is added. */
441 if (divisor != ctx->i32_1)
442 result = LLVMBuildUDiv(ctx->ac.builder, result, divisor, "");
443
444 return LLVMBuildAdd(ctx->ac.builder, result,
445 LLVMGetParam(ctx->main_fn, param_start_instance), "");
446 }
447
448 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
449 * to float. */
450 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
451 LLVMValueRef vec4,
452 unsigned double_index)
453 {
454 LLVMBuilderRef builder = ctx->ac.builder;
455 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->ac.context);
456 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
457 LLVMVectorType(f64, 2), "");
458 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
459 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
460 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
461 }
462
463 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
464 LLVMValueRef i32, unsigned index)
465 {
466 assert(index <= 1);
467
468 if (index == 1)
469 return LLVMBuildAShr(ctx->ac.builder, i32,
470 LLVMConstInt(ctx->i32, 16, 0), "");
471
472 return LLVMBuildSExt(ctx->ac.builder,
473 LLVMBuildTrunc(ctx->ac.builder, i32,
474 ctx->ac.i16, ""),
475 ctx->i32, "");
476 }
477
478 void si_llvm_load_input_vs(
479 struct si_shader_context *ctx,
480 unsigned input_index,
481 LLVMValueRef out[4])
482 {
483 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
484 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
485
486 if (vs_blit_property) {
487 LLVMValueRef vertex_id = ctx->abi.vertex_id;
488 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
489 LLVMIntULE, vertex_id,
490 ctx->i32_1, "");
491 /* Use LLVMIntNE, because we have 3 vertices and only
492 * the middle one should use y2.
493 */
494 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
495 LLVMIntNE, vertex_id,
496 ctx->i32_1, "");
497
498 if (input_index == 0) {
499 /* Position: */
500 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
501 ctx->param_vs_blit_inputs);
502 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
503 ctx->param_vs_blit_inputs + 1);
504
505 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
506 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
507 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
508 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
509
510 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
511 x1, x2, "");
512 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
513 y1, y2, "");
514
515 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
516 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
517 out[2] = LLVMGetParam(ctx->main_fn,
518 ctx->param_vs_blit_inputs + 2);
519 out[3] = ctx->ac.f32_1;
520 return;
521 }
522
523 /* Color or texture coordinates: */
524 assert(input_index == 1);
525
526 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
527 for (int i = 0; i < 4; i++) {
528 out[i] = LLVMGetParam(ctx->main_fn,
529 ctx->param_vs_blit_inputs + 3 + i);
530 }
531 } else {
532 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
533 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
534 ctx->param_vs_blit_inputs + 3);
535 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
536 ctx->param_vs_blit_inputs + 4);
537 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
538 ctx->param_vs_blit_inputs + 5);
539 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
540 ctx->param_vs_blit_inputs + 6);
541
542 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
543 x1, x2, "");
544 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
545 y1, y2, "");
546 out[2] = LLVMGetParam(ctx->main_fn,
547 ctx->param_vs_blit_inputs + 7);
548 out[3] = LLVMGetParam(ctx->main_fn,
549 ctx->param_vs_blit_inputs + 8);
550 }
551 return;
552 }
553
554 unsigned chan;
555 unsigned fix_fetch;
556 unsigned num_fetches;
557 unsigned fetch_stride;
558 unsigned num_channels;
559
560 LLVMValueRef t_list_ptr;
561 LLVMValueRef t_offset;
562 LLVMValueRef t_list;
563 LLVMValueRef vertex_index;
564 LLVMValueRef input[3];
565
566 /* Load the T list */
567 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
568
569 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
570
571 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
572
573 vertex_index = LLVMGetParam(ctx->main_fn,
574 ctx->param_vertex_index0 +
575 input_index);
576
577 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
578
579 /* Do multiple loads for special formats. */
580 switch (fix_fetch) {
581 case SI_FIX_FETCH_RGB_64_FLOAT:
582 num_fetches = 3; /* 3 2-dword loads */
583 fetch_stride = 8;
584 num_channels = 2;
585 break;
586 case SI_FIX_FETCH_RGBA_64_FLOAT:
587 num_fetches = 2; /* 2 4-dword loads */
588 fetch_stride = 16;
589 num_channels = 4;
590 break;
591 case SI_FIX_FETCH_RGB_8:
592 case SI_FIX_FETCH_RGB_8_INT:
593 num_fetches = 3;
594 fetch_stride = 1;
595 num_channels = 1;
596 break;
597 case SI_FIX_FETCH_RGB_16:
598 case SI_FIX_FETCH_RGB_16_INT:
599 num_fetches = 3;
600 fetch_stride = 2;
601 num_channels = 1;
602 break;
603 default:
604 num_fetches = 1;
605 fetch_stride = 0;
606 num_channels = util_last_bit(info->input_usage_mask[input_index]);
607 }
608
609 for (unsigned i = 0; i < num_fetches; i++) {
610 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
611
612 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
613 vertex_index, voffset,
614 num_channels, false, true);
615 input[i] = ac_build_expand_to_vec4(&ctx->ac, input[i], num_channels);
616 }
617
618 /* Break up the vec4 into individual components */
619 for (chan = 0; chan < 4; chan++) {
620 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
621 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
622 input[0], llvm_chan, "");
623 }
624
625 switch (fix_fetch) {
626 case SI_FIX_FETCH_A2_SNORM:
627 case SI_FIX_FETCH_A2_SSCALED:
628 case SI_FIX_FETCH_A2_SINT: {
629 /* The hardware returns an unsigned value; convert it to a
630 * signed one.
631 */
632 LLVMValueRef tmp = out[3];
633 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
634
635 /* First, recover the sign-extended signed integer value. */
636 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
637 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
638 else
639 tmp = ac_to_integer(&ctx->ac, tmp);
640
641 /* For the integer-like cases, do a natural sign extension.
642 *
643 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
644 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
645 * exponent.
646 */
647 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
648 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
649 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
650 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
651
652 /* Convert back to the right type. */
653 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
654 LLVMValueRef clamp;
655 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
656 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
657 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
658 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
659 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
660 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
661 }
662
663 out[3] = tmp;
664 break;
665 }
666 case SI_FIX_FETCH_RGBA_32_UNORM:
667 case SI_FIX_FETCH_RGBX_32_UNORM:
668 for (chan = 0; chan < 4; chan++) {
669 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
670 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
671 out[chan], ctx->f32, "");
672 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
673 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
674 }
675 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
676 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
677 out[3] = LLVMConstReal(ctx->f32, 1);
678 break;
679 case SI_FIX_FETCH_RGBA_32_SNORM:
680 case SI_FIX_FETCH_RGBX_32_SNORM:
681 case SI_FIX_FETCH_RGBA_32_FIXED:
682 case SI_FIX_FETCH_RGBX_32_FIXED: {
683 double scale;
684 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
685 scale = 1.0 / 0x10000;
686 else
687 scale = 1.0 / INT_MAX;
688
689 for (chan = 0; chan < 4; chan++) {
690 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
691 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
692 out[chan], ctx->f32, "");
693 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
694 LLVMConstReal(ctx->f32, scale), "");
695 }
696 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
697 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
698 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
699 out[3] = LLVMConstReal(ctx->f32, 1);
700 break;
701 }
702 case SI_FIX_FETCH_RGBA_32_USCALED:
703 for (chan = 0; chan < 4; chan++) {
704 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
705 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
706 out[chan], ctx->f32, "");
707 }
708 break;
709 case SI_FIX_FETCH_RGBA_32_SSCALED:
710 for (chan = 0; chan < 4; chan++) {
711 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
712 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
713 out[chan], ctx->f32, "");
714 }
715 break;
716 case SI_FIX_FETCH_RG_64_FLOAT:
717 for (chan = 0; chan < 2; chan++)
718 out[chan] = extract_double_to_float(ctx, input[0], chan);
719
720 out[2] = LLVMConstReal(ctx->f32, 0);
721 out[3] = LLVMConstReal(ctx->f32, 1);
722 break;
723 case SI_FIX_FETCH_RGB_64_FLOAT:
724 for (chan = 0; chan < 3; chan++)
725 out[chan] = extract_double_to_float(ctx, input[chan], 0);
726
727 out[3] = LLVMConstReal(ctx->f32, 1);
728 break;
729 case SI_FIX_FETCH_RGBA_64_FLOAT:
730 for (chan = 0; chan < 4; chan++) {
731 out[chan] = extract_double_to_float(ctx, input[chan / 2],
732 chan % 2);
733 }
734 break;
735 case SI_FIX_FETCH_RGB_8:
736 case SI_FIX_FETCH_RGB_8_INT:
737 case SI_FIX_FETCH_RGB_16:
738 case SI_FIX_FETCH_RGB_16_INT:
739 for (chan = 0; chan < 3; chan++) {
740 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
741 input[chan],
742 ctx->i32_0, "");
743 }
744 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
745 fix_fetch == SI_FIX_FETCH_RGB_16) {
746 out[3] = LLVMConstReal(ctx->f32, 1);
747 } else {
748 out[3] = ac_to_float(&ctx->ac, ctx->i32_1);
749 }
750 break;
751 }
752 }
753
754 static void declare_input_vs(
755 struct si_shader_context *ctx,
756 unsigned input_index,
757 const struct tgsi_full_declaration *decl,
758 LLVMValueRef out[4])
759 {
760 si_llvm_load_input_vs(ctx, input_index, out);
761 }
762
763 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
764 unsigned swizzle)
765 {
766 if (swizzle > 0)
767 return ctx->i32_0;
768
769 switch (ctx->type) {
770 case PIPE_SHADER_VERTEX:
771 return LLVMGetParam(ctx->main_fn,
772 ctx->param_vs_prim_id);
773 case PIPE_SHADER_TESS_CTRL:
774 return ctx->abi.tcs_patch_id;
775 case PIPE_SHADER_TESS_EVAL:
776 return ctx->abi.tes_patch_id;
777 case PIPE_SHADER_GEOMETRY:
778 return ctx->abi.gs_prim_id;
779 default:
780 assert(0);
781 return ctx->i32_0;
782 }
783 }
784
785 /**
786 * Return the value of tgsi_ind_register for indexing.
787 * This is the indirect index with the constant offset added to it.
788 */
789 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
790 const struct tgsi_ind_register *ind,
791 unsigned addr_mul,
792 int rel_index)
793 {
794 LLVMValueRef result;
795
796 if (ind->File == TGSI_FILE_ADDRESS) {
797 result = ctx->addrs[ind->Index][ind->Swizzle];
798 result = LLVMBuildLoad(ctx->ac.builder, result, "");
799 } else {
800 struct tgsi_full_src_register src = {};
801
802 src.Register.File = ind->File;
803 src.Register.Index = ind->Index;
804
805 /* Set the second index to 0 for constants. */
806 if (ind->File == TGSI_FILE_CONSTANT)
807 src.Register.Dimension = 1;
808
809 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
810 TGSI_TYPE_SIGNED,
811 ind->Swizzle);
812 result = ac_to_integer(&ctx->ac, result);
813 }
814
815 if (addr_mul != 1)
816 result = LLVMBuildMul(ctx->ac.builder, result,
817 LLVMConstInt(ctx->i32, addr_mul, 0), "");
818 result = LLVMBuildAdd(ctx->ac.builder, result,
819 LLVMConstInt(ctx->i32, rel_index, 0), "");
820 return result;
821 }
822
823 /**
824 * Like si_get_indirect_index, but restricts the return value to a (possibly
825 * undefined) value inside [0..num).
826 */
827 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
828 const struct tgsi_ind_register *ind,
829 int rel_index, unsigned num)
830 {
831 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
832
833 return si_llvm_bound_index(ctx, result, num);
834 }
835
836 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
837 LLVMValueRef vertex_dw_stride,
838 LLVMValueRef base_addr,
839 LLVMValueRef vertex_index,
840 LLVMValueRef param_index,
841 unsigned input_index,
842 ubyte *name,
843 ubyte *index,
844 bool is_patch)
845 {
846 if (vertex_dw_stride) {
847 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
848 LLVMBuildMul(ctx->ac.builder, vertex_index,
849 vertex_dw_stride, ""), "");
850 }
851
852 if (param_index) {
853 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
854 LLVMBuildMul(ctx->ac.builder, param_index,
855 LLVMConstInt(ctx->i32, 4, 0), ""), "");
856 }
857
858 int param = is_patch ?
859 si_shader_io_get_unique_index_patch(name[input_index],
860 index[input_index]) :
861 si_shader_io_get_unique_index(name[input_index],
862 index[input_index]);
863
864 /* Add the base address of the element. */
865 return LLVMBuildAdd(ctx->ac.builder, base_addr,
866 LLVMConstInt(ctx->i32, param * 4, 0), "");
867 }
868
869 /**
870 * Calculate a dword address given an input or output register and a stride.
871 */
872 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
873 const struct tgsi_full_dst_register *dst,
874 const struct tgsi_full_src_register *src,
875 LLVMValueRef vertex_dw_stride,
876 LLVMValueRef base_addr)
877 {
878 struct tgsi_shader_info *info = &ctx->shader->selector->info;
879 ubyte *name, *index, *array_first;
880 int input_index;
881 struct tgsi_full_dst_register reg;
882 LLVMValueRef vertex_index = NULL;
883 LLVMValueRef ind_index = NULL;
884
885 /* Set the register description. The address computation is the same
886 * for sources and destinations. */
887 if (src) {
888 reg.Register.File = src->Register.File;
889 reg.Register.Index = src->Register.Index;
890 reg.Register.Indirect = src->Register.Indirect;
891 reg.Register.Dimension = src->Register.Dimension;
892 reg.Indirect = src->Indirect;
893 reg.Dimension = src->Dimension;
894 reg.DimIndirect = src->DimIndirect;
895 } else
896 reg = *dst;
897
898 /* If the register is 2-dimensional (e.g. an array of vertices
899 * in a primitive), calculate the base address of the vertex. */
900 if (reg.Register.Dimension) {
901 if (reg.Dimension.Indirect)
902 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
903 1, reg.Dimension.Index);
904 else
905 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
906 }
907
908 /* Get information about the register. */
909 if (reg.Register.File == TGSI_FILE_INPUT) {
910 name = info->input_semantic_name;
911 index = info->input_semantic_index;
912 array_first = info->input_array_first;
913 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
914 name = info->output_semantic_name;
915 index = info->output_semantic_index;
916 array_first = info->output_array_first;
917 } else {
918 assert(0);
919 return NULL;
920 }
921
922 if (reg.Register.Indirect) {
923 /* Add the relative address of the element. */
924 if (reg.Indirect.ArrayID)
925 input_index = array_first[reg.Indirect.ArrayID];
926 else
927 input_index = reg.Register.Index;
928
929 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
930 1, reg.Register.Index - input_index);
931 } else {
932 input_index = reg.Register.Index;
933 }
934
935 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
936 base_addr, vertex_index,
937 ind_index, input_index,
938 name, index,
939 !reg.Register.Dimension);
940 }
941
942 /* The offchip buffer layout for TCS->TES is
943 *
944 * - attribute 0 of patch 0 vertex 0
945 * - attribute 0 of patch 0 vertex 1
946 * - attribute 0 of patch 0 vertex 2
947 * ...
948 * - attribute 0 of patch 1 vertex 0
949 * - attribute 0 of patch 1 vertex 1
950 * ...
951 * - attribute 1 of patch 0 vertex 0
952 * - attribute 1 of patch 0 vertex 1
953 * ...
954 * - per patch attribute 0 of patch 0
955 * - per patch attribute 0 of patch 1
956 * ...
957 *
958 * Note that every attribute has 4 components.
959 */
960 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
961 LLVMValueRef rel_patch_id,
962 LLVMValueRef vertex_index,
963 LLVMValueRef param_index)
964 {
965 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
966 LLVMValueRef param_stride, constant16;
967
968 vertices_per_patch = get_num_tcs_out_vertices(ctx);
969 num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
970 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
971 num_patches, "");
972
973 constant16 = LLVMConstInt(ctx->i32, 16, 0);
974 if (vertex_index) {
975 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
976 vertices_per_patch, "");
977
978 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
979 vertex_index, "");
980
981 param_stride = total_vertices;
982 } else {
983 base_addr = rel_patch_id;
984 param_stride = num_patches;
985 }
986
987 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
988 LLVMBuildMul(ctx->ac.builder, param_index,
989 param_stride, ""), "");
990
991 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
992
993 if (!vertex_index) {
994 LLVMValueRef patch_data_offset =
995 unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
996
997 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
998 patch_data_offset, "");
999 }
1000 return base_addr;
1001 }
1002
1003 /* This is a generic helper that can be shared by the NIR and TGSI backends */
1004 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
1005 struct si_shader_context *ctx,
1006 LLVMValueRef vertex_index,
1007 LLVMValueRef param_index,
1008 unsigned param_base,
1009 ubyte *name,
1010 ubyte *index,
1011 bool is_patch)
1012 {
1013 unsigned param_index_base;
1014
1015 param_index_base = is_patch ?
1016 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
1017 si_shader_io_get_unique_index(name[param_base], index[param_base]);
1018
1019 if (param_index) {
1020 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1021 LLVMConstInt(ctx->i32, param_index_base, 0),
1022 "");
1023 } else {
1024 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
1025 }
1026
1027 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
1028 vertex_index, param_index);
1029 }
1030
1031 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
1032 struct si_shader_context *ctx,
1033 const struct tgsi_full_dst_register *dst,
1034 const struct tgsi_full_src_register *src)
1035 {
1036 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1037 ubyte *name, *index, *array_first;
1038 struct tgsi_full_src_register reg;
1039 LLVMValueRef vertex_index = NULL;
1040 LLVMValueRef param_index = NULL;
1041 unsigned param_base;
1042
1043 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
1044
1045 if (reg.Register.Dimension) {
1046
1047 if (reg.Dimension.Indirect)
1048 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
1049 1, reg.Dimension.Index);
1050 else
1051 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
1052 }
1053
1054 /* Get information about the register. */
1055 if (reg.Register.File == TGSI_FILE_INPUT) {
1056 name = info->input_semantic_name;
1057 index = info->input_semantic_index;
1058 array_first = info->input_array_first;
1059 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1060 name = info->output_semantic_name;
1061 index = info->output_semantic_index;
1062 array_first = info->output_array_first;
1063 } else {
1064 assert(0);
1065 return NULL;
1066 }
1067
1068 if (reg.Register.Indirect) {
1069 if (reg.Indirect.ArrayID)
1070 param_base = array_first[reg.Indirect.ArrayID];
1071 else
1072 param_base = reg.Register.Index;
1073
1074 param_index = si_get_indirect_index(ctx, &reg.Indirect,
1075 1, reg.Register.Index - param_base);
1076
1077 } else {
1078 param_base = reg.Register.Index;
1079 }
1080
1081 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1082 param_index, param_base,
1083 name, index, !reg.Register.Dimension);
1084 }
1085
1086 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
1087 LLVMTypeRef type, unsigned swizzle,
1088 LLVMValueRef buffer, LLVMValueRef offset,
1089 LLVMValueRef base, bool can_speculate)
1090 {
1091 struct si_shader_context *ctx = si_shader_context(bld_base);
1092 LLVMValueRef value, value2;
1093 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
1094
1095 if (swizzle == ~0) {
1096 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1097 0, 1, 0, can_speculate, false);
1098
1099 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1100 }
1101
1102 if (!llvm_type_is_64bit(ctx, type)) {
1103 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1104 0, 1, 0, can_speculate, false);
1105
1106 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1107 return LLVMBuildExtractElement(ctx->ac.builder, value,
1108 LLVMConstInt(ctx->i32, swizzle, 0), "");
1109 }
1110
1111 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1112 swizzle * 4, 1, 0, can_speculate, false);
1113
1114 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1115 swizzle * 4 + 4, 1, 0, can_speculate, false);
1116
1117 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1118 }
1119
1120 /**
1121 * Load from LDS.
1122 *
1123 * \param type output value type
1124 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1125 * \param dw_addr address in dwords
1126 */
1127 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1128 LLVMTypeRef type, unsigned swizzle,
1129 LLVMValueRef dw_addr)
1130 {
1131 struct si_shader_context *ctx = si_shader_context(bld_base);
1132 LLVMValueRef value;
1133
1134 if (swizzle == ~0) {
1135 LLVMValueRef values[TGSI_NUM_CHANNELS];
1136
1137 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1138 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1139
1140 return lp_build_gather_values(&ctx->gallivm, values,
1141 TGSI_NUM_CHANNELS);
1142 }
1143
1144 /* Split 64-bit loads. */
1145 if (llvm_type_is_64bit(ctx, type)) {
1146 LLVMValueRef lo, hi;
1147
1148 lo = lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1149 hi = lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1150 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1151 }
1152
1153 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1154 LLVMConstInt(ctx->i32, swizzle, 0));
1155
1156 value = ac_lds_load(&ctx->ac, dw_addr);
1157
1158 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1159 }
1160
1161 /**
1162 * Store to LDS.
1163 *
1164 * \param swizzle offset (typically 0..3)
1165 * \param dw_addr address in dwords
1166 * \param value value to store
1167 */
1168 static void lds_store(struct si_shader_context *ctx,
1169 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1170 LLVMValueRef value)
1171 {
1172 dw_addr = lp_build_add(&ctx->bld_base.uint_bld, dw_addr,
1173 LLVMConstInt(ctx->i32, dw_offset_imm, 0));
1174
1175 ac_lds_store(&ctx->ac, dw_addr, value);
1176 }
1177
1178 static LLVMValueRef desc_from_addr_base64k(struct si_shader_context *ctx,
1179 unsigned param)
1180 {
1181 LLVMBuilderRef builder = ctx->ac.builder;
1182
1183 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1184 addr = LLVMBuildZExt(builder, addr, ctx->i64, "");
1185 addr = LLVMBuildShl(builder, addr, LLVMConstInt(ctx->i64, 16, 0), "");
1186
1187 uint64_t desc2 = 0xffffffff;
1188 uint64_t desc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1189 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1190 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1191 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1192 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1193 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1194 LLVMValueRef hi = LLVMConstInt(ctx->i64, desc2 | (desc3 << 32), 0);
1195
1196 LLVMValueRef desc = LLVMGetUndef(LLVMVectorType(ctx->i64, 2));
1197 desc = LLVMBuildInsertElement(builder, desc, addr, ctx->i32_0, "");
1198 desc = LLVMBuildInsertElement(builder, desc, hi, ctx->i32_1, "");
1199 return LLVMBuildBitCast(builder, desc, ctx->v4i32, "");
1200 }
1201
1202 static LLVMValueRef fetch_input_tcs(
1203 struct lp_build_tgsi_context *bld_base,
1204 const struct tgsi_full_src_register *reg,
1205 enum tgsi_opcode_type type, unsigned swizzle)
1206 {
1207 struct si_shader_context *ctx = si_shader_context(bld_base);
1208 LLVMValueRef dw_addr, stride;
1209
1210 stride = get_tcs_in_vertex_dw_stride(ctx);
1211 dw_addr = get_tcs_in_current_patch_offset(ctx);
1212 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1213
1214 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1215 }
1216
1217 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1218 LLVMValueRef vertex_index,
1219 LLVMValueRef param_index,
1220 unsigned const_index,
1221 unsigned location,
1222 unsigned driver_location,
1223 unsigned component,
1224 unsigned num_components,
1225 bool is_patch,
1226 bool is_compact,
1227 bool load_input)
1228 {
1229 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1230 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1231 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1232 LLVMValueRef dw_addr, stride;
1233
1234 driver_location = driver_location / 4;
1235
1236 if (load_input) {
1237 stride = get_tcs_in_vertex_dw_stride(ctx);
1238 dw_addr = get_tcs_in_current_patch_offset(ctx);
1239 } else {
1240 if (is_patch) {
1241 stride = NULL;
1242 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1243 } else {
1244 stride = get_tcs_out_vertex_dw_stride(ctx);
1245 dw_addr = get_tcs_out_current_patch_offset(ctx);
1246 }
1247 }
1248
1249 if (param_index) {
1250 /* Add the constant index to the indirect index */
1251 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1252 LLVMConstInt(ctx->i32, const_index, 0), "");
1253 } else {
1254 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1255 }
1256
1257 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1258 vertex_index, param_index,
1259 driver_location,
1260 info->input_semantic_name,
1261 info->input_semantic_index,
1262 is_patch);
1263
1264 LLVMValueRef value[4];
1265 for (unsigned i = 0; i < num_components + component; i++) {
1266 value[i] = lds_load(bld_base, ctx->i32, i, dw_addr);
1267 }
1268
1269 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1270 }
1271
1272 static LLVMValueRef fetch_output_tcs(
1273 struct lp_build_tgsi_context *bld_base,
1274 const struct tgsi_full_src_register *reg,
1275 enum tgsi_opcode_type type, unsigned swizzle)
1276 {
1277 struct si_shader_context *ctx = si_shader_context(bld_base);
1278 LLVMValueRef dw_addr, stride;
1279
1280 if (reg->Register.Dimension) {
1281 stride = get_tcs_out_vertex_dw_stride(ctx);
1282 dw_addr = get_tcs_out_current_patch_offset(ctx);
1283 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1284 } else {
1285 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1286 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1287 }
1288
1289 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1290 }
1291
1292 static LLVMValueRef fetch_input_tes(
1293 struct lp_build_tgsi_context *bld_base,
1294 const struct tgsi_full_src_register *reg,
1295 enum tgsi_opcode_type type, unsigned swizzle)
1296 {
1297 struct si_shader_context *ctx = si_shader_context(bld_base);
1298 LLVMValueRef buffer, base, addr;
1299
1300 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1301
1302 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1303 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1304
1305 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1306 buffer, base, addr, true);
1307 }
1308
1309 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1310 LLVMValueRef vertex_index,
1311 LLVMValueRef param_index,
1312 unsigned const_index,
1313 unsigned location,
1314 unsigned driver_location,
1315 unsigned component,
1316 unsigned num_components,
1317 bool is_patch,
1318 bool is_compact,
1319 bool load_input)
1320 {
1321 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1322 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1323 LLVMValueRef buffer, base, addr;
1324
1325 driver_location = driver_location / 4;
1326
1327 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1328
1329 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1330
1331 if (param_index) {
1332 /* Add the constant index to the indirect index */
1333 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1334 LLVMConstInt(ctx->i32, const_index, 0), "");
1335 } else {
1336 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1337 }
1338
1339 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1340 param_index, driver_location,
1341 info->input_semantic_name,
1342 info->input_semantic_index,
1343 is_patch);
1344
1345 /* TODO: This will generate rather ordinary llvm code, although it
1346 * should be easy for the optimiser to fix up. In future we might want
1347 * to refactor buffer_load(), but for now this maximises code sharing
1348 * between the NIR and TGSI backends.
1349 */
1350 LLVMValueRef value[4];
1351 for (unsigned i = component; i < num_components + component; i++) {
1352 value[i] = buffer_load(&ctx->bld_base, ctx->i32, i, buffer, base, addr, true);
1353 }
1354
1355 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1356 }
1357
1358 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1359 const struct tgsi_full_instruction *inst,
1360 const struct tgsi_opcode_info *info,
1361 unsigned index,
1362 LLVMValueRef dst[4])
1363 {
1364 struct si_shader_context *ctx = si_shader_context(bld_base);
1365 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1366 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1367 unsigned chan_index;
1368 LLVMValueRef dw_addr, stride;
1369 LLVMValueRef buffer, base, buf_addr;
1370 LLVMValueRef values[4];
1371 bool skip_lds_store;
1372 bool is_tess_factor = false, is_tess_inner = false;
1373
1374 /* Only handle per-patch and per-vertex outputs here.
1375 * Vectors will be lowered to scalars and this function will be called again.
1376 */
1377 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1378 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1379 si_llvm_emit_store(bld_base, inst, info, index, dst);
1380 return;
1381 }
1382
1383 if (reg->Register.Dimension) {
1384 stride = get_tcs_out_vertex_dw_stride(ctx);
1385 dw_addr = get_tcs_out_current_patch_offset(ctx);
1386 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1387 skip_lds_store = !sh_info->reads_pervertex_outputs;
1388 } else {
1389 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1390 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1391 skip_lds_store = !sh_info->reads_perpatch_outputs;
1392
1393 if (!reg->Register.Indirect) {
1394 int name = sh_info->output_semantic_name[reg->Register.Index];
1395
1396 /* Always write tess factors into LDS for the TCS epilog. */
1397 if (name == TGSI_SEMANTIC_TESSINNER ||
1398 name == TGSI_SEMANTIC_TESSOUTER) {
1399 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1400 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1401 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1402 is_tess_factor = true;
1403 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1404 }
1405 }
1406 }
1407
1408 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1409
1410 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1411 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1412
1413 uint32_t writemask = reg->Register.WriteMask;
1414 while (writemask) {
1415 chan_index = u_bit_scan(&writemask);
1416 LLVMValueRef value = dst[chan_index];
1417
1418 if (inst->Instruction.Saturate)
1419 value = ac_build_clamp(&ctx->ac, value);
1420
1421 /* Skip LDS stores if there is no LDS read of this output. */
1422 if (!skip_lds_store)
1423 lds_store(ctx, chan_index, dw_addr, value);
1424
1425 value = ac_to_integer(&ctx->ac, value);
1426 values[chan_index] = value;
1427
1428 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1429 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1430 buf_addr, base,
1431 4 * chan_index, 1, 0, true, false);
1432 }
1433
1434 /* Write tess factors into VGPRs for the epilog. */
1435 if (is_tess_factor &&
1436 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1437 if (!is_tess_inner) {
1438 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1439 ctx->invoc0_tess_factors[chan_index]);
1440 } else if (chan_index < 2) {
1441 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1442 ctx->invoc0_tess_factors[4 + chan_index]);
1443 }
1444 }
1445 }
1446
1447 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1448 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1449 values, 4);
1450 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1451 base, 0, 1, 0, true, false);
1452 }
1453 }
1454
1455 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1456 LLVMValueRef vertex_index,
1457 LLVMValueRef param_index,
1458 unsigned const_index,
1459 unsigned location,
1460 unsigned driver_location,
1461 LLVMValueRef src,
1462 unsigned component,
1463 bool is_patch,
1464 bool is_compact,
1465 unsigned writemask)
1466 {
1467 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1468 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1469 LLVMValueRef dw_addr, stride;
1470 LLVMValueRef buffer, base, addr;
1471 LLVMValueRef values[4];
1472 bool skip_lds_store;
1473 bool is_tess_factor = false, is_tess_inner = false;
1474
1475 driver_location = driver_location / 4;
1476
1477 if (param_index) {
1478 /* Add the constant index to the indirect index */
1479 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1480 LLVMConstInt(ctx->i32, const_index, 0), "");
1481 } else {
1482 if (const_index != 0)
1483 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1484 }
1485
1486 if (!is_patch) {
1487 stride = get_tcs_out_vertex_dw_stride(ctx);
1488 dw_addr = get_tcs_out_current_patch_offset(ctx);
1489 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1490 vertex_index, param_index,
1491 driver_location,
1492 info->output_semantic_name,
1493 info->output_semantic_index,
1494 is_patch);
1495
1496 skip_lds_store = !info->reads_pervertex_outputs;
1497 } else {
1498 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1499 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1500 vertex_index, param_index,
1501 driver_location,
1502 info->output_semantic_name,
1503 info->output_semantic_index,
1504 is_patch);
1505
1506 skip_lds_store = !info->reads_perpatch_outputs;
1507
1508 if (!param_index) {
1509 int name = info->output_semantic_name[driver_location];
1510
1511 /* Always write tess factors into LDS for the TCS epilog. */
1512 if (name == TGSI_SEMANTIC_TESSINNER ||
1513 name == TGSI_SEMANTIC_TESSOUTER) {
1514 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1515 skip_lds_store = !info->reads_tessfactor_outputs &&
1516 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1517 is_tess_factor = true;
1518 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1519 }
1520 }
1521 }
1522
1523 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1524
1525 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1526
1527 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1528 param_index, driver_location,
1529 info->output_semantic_name,
1530 info->output_semantic_index,
1531 is_patch);
1532
1533 for (unsigned chan = 0; chan < 4; chan++) {
1534 if (!(writemask & (1 << chan)))
1535 continue;
1536 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1537
1538 /* Skip LDS stores if there is no LDS read of this output. */
1539 if (!skip_lds_store)
1540 ac_lds_store(&ctx->ac, dw_addr, value);
1541
1542 value = ac_to_integer(&ctx->ac, value);
1543 values[chan] = value;
1544
1545 if (writemask != 0xF && !is_tess_factor) {
1546 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1547 addr, base,
1548 4 * chan, 1, 0, true, false);
1549 }
1550
1551 /* Write tess factors into VGPRs for the epilog. */
1552 if (is_tess_factor &&
1553 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1554 if (!is_tess_inner) {
1555 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1556 ctx->invoc0_tess_factors[chan]);
1557 } else if (chan < 2) {
1558 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1559 ctx->invoc0_tess_factors[4 + chan]);
1560 }
1561 }
1562 }
1563
1564 if (writemask == 0xF && !is_tess_factor) {
1565 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1566 values, 4);
1567 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1568 base, 0, 1, 0, true, false);
1569 }
1570 }
1571
1572 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1573 unsigned input_index,
1574 unsigned vtx_offset_param,
1575 LLVMTypeRef type,
1576 unsigned swizzle)
1577 {
1578 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1579 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1580 struct si_shader *shader = ctx->shader;
1581 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1582 LLVMValueRef vtx_offset, soffset;
1583 struct tgsi_shader_info *info = &shader->selector->info;
1584 unsigned semantic_name = info->input_semantic_name[input_index];
1585 unsigned semantic_index = info->input_semantic_index[input_index];
1586 unsigned param;
1587 LLVMValueRef value;
1588
1589 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1590
1591 /* GFX9 has the ESGS ring in LDS. */
1592 if (ctx->screen->info.chip_class >= GFX9) {
1593 unsigned index = vtx_offset_param;
1594
1595 switch (index / 2) {
1596 case 0:
1597 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx01_offset,
1598 index % 2 ? 16 : 0, 16);
1599 break;
1600 case 1:
1601 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx23_offset,
1602 index % 2 ? 16 : 0, 16);
1603 break;
1604 case 2:
1605 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx45_offset,
1606 index % 2 ? 16 : 0, 16);
1607 break;
1608 default:
1609 assert(0);
1610 return NULL;
1611 }
1612
1613 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1614 LLVMConstInt(ctx->i32, param * 4, 0), "");
1615 return lds_load(bld_base, type, swizzle, vtx_offset);
1616 }
1617
1618 /* GFX6: input load from the ESGS ring in memory. */
1619 if (swizzle == ~0) {
1620 LLVMValueRef values[TGSI_NUM_CHANNELS];
1621 unsigned chan;
1622 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1623 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1624 type, chan);
1625 }
1626 return lp_build_gather_values(&ctx->gallivm, values,
1627 TGSI_NUM_CHANNELS);
1628 }
1629
1630 /* Get the vertex offset parameter on GFX6. */
1631 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1632
1633 vtx_offset = lp_build_mul_imm(uint, gs_vtx_offset, 4);
1634
1635 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1636
1637 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1638 vtx_offset, soffset, 0, 1, 0, true, false);
1639 if (llvm_type_is_64bit(ctx, type)) {
1640 LLVMValueRef value2;
1641 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1642
1643 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1644 ctx->i32_0, vtx_offset, soffset,
1645 0, 1, 0, true, false);
1646 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1647 }
1648 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1649 }
1650
1651 static LLVMValueRef fetch_input_gs(
1652 struct lp_build_tgsi_context *bld_base,
1653 const struct tgsi_full_src_register *reg,
1654 enum tgsi_opcode_type type,
1655 unsigned swizzle)
1656 {
1657 struct si_shader_context *ctx = si_shader_context(bld_base);
1658 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1659
1660 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1661 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1662 return get_primitive_id(ctx, swizzle);
1663
1664 if (!reg->Register.Dimension)
1665 return NULL;
1666
1667 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1668 reg->Dimension.Index,
1669 tgsi2llvmtype(bld_base, type),
1670 swizzle);
1671 }
1672
1673 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1674 {
1675 switch (interpolate) {
1676 case TGSI_INTERPOLATE_CONSTANT:
1677 return 0;
1678
1679 case TGSI_INTERPOLATE_LINEAR:
1680 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1681 return SI_PARAM_LINEAR_SAMPLE;
1682 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1683 return SI_PARAM_LINEAR_CENTROID;
1684 else
1685 return SI_PARAM_LINEAR_CENTER;
1686 break;
1687 case TGSI_INTERPOLATE_COLOR:
1688 case TGSI_INTERPOLATE_PERSPECTIVE:
1689 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1690 return SI_PARAM_PERSP_SAMPLE;
1691 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1692 return SI_PARAM_PERSP_CENTROID;
1693 else
1694 return SI_PARAM_PERSP_CENTER;
1695 break;
1696 default:
1697 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1698 return -1;
1699 }
1700 }
1701
1702 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1703 unsigned attr_index, unsigned chan,
1704 LLVMValueRef prim_mask,
1705 LLVMValueRef i, LLVMValueRef j)
1706 {
1707 if (i || j) {
1708 return ac_build_fs_interp(&ctx->ac,
1709 LLVMConstInt(ctx->i32, chan, 0),
1710 LLVMConstInt(ctx->i32, attr_index, 0),
1711 prim_mask, i, j);
1712 }
1713 return ac_build_fs_interp_mov(&ctx->ac,
1714 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1715 LLVMConstInt(ctx->i32, chan, 0),
1716 LLVMConstInt(ctx->i32, attr_index, 0),
1717 prim_mask);
1718 }
1719
1720 /**
1721 * Interpolate a fragment shader input.
1722 *
1723 * @param ctx context
1724 * @param input_index index of the input in hardware
1725 * @param semantic_name TGSI_SEMANTIC_*
1726 * @param semantic_index semantic index
1727 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1728 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1729 * @param interp_param interpolation weights (i,j)
1730 * @param prim_mask SI_PARAM_PRIM_MASK
1731 * @param face SI_PARAM_FRONT_FACE
1732 * @param result the return value (4 components)
1733 */
1734 static void interp_fs_input(struct si_shader_context *ctx,
1735 unsigned input_index,
1736 unsigned semantic_name,
1737 unsigned semantic_index,
1738 unsigned num_interp_inputs,
1739 unsigned colors_read_mask,
1740 LLVMValueRef interp_param,
1741 LLVMValueRef prim_mask,
1742 LLVMValueRef face,
1743 LLVMValueRef result[4])
1744 {
1745 LLVMValueRef i = NULL, j = NULL;
1746 unsigned chan;
1747
1748 /* fs.constant returns the param from the middle vertex, so it's not
1749 * really useful for flat shading. It's meant to be used for custom
1750 * interpolation (but the intrinsic can't fetch from the other two
1751 * vertices).
1752 *
1753 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1754 * to do the right thing. The only reason we use fs.constant is that
1755 * fs.interp cannot be used on integers, because they can be equal
1756 * to NaN.
1757 *
1758 * When interp is false we will use fs.constant or for newer llvm,
1759 * amdgcn.interp.mov.
1760 */
1761 bool interp = interp_param != NULL;
1762
1763 if (interp) {
1764 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1765 LLVMVectorType(ctx->f32, 2), "");
1766
1767 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1768 ctx->i32_0, "");
1769 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1770 ctx->i32_1, "");
1771 }
1772
1773 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1774 ctx->shader->key.part.ps.prolog.color_two_side) {
1775 LLVMValueRef is_face_positive;
1776
1777 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1778 * otherwise it's at offset "num_inputs".
1779 */
1780 unsigned back_attr_offset = num_interp_inputs;
1781 if (semantic_index == 1 && colors_read_mask & 0xf)
1782 back_attr_offset += 1;
1783
1784 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1785 face, ctx->i32_0, "");
1786
1787 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1788 LLVMValueRef front, back;
1789
1790 front = si_build_fs_interp(ctx,
1791 input_index, chan,
1792 prim_mask, i, j);
1793 back = si_build_fs_interp(ctx,
1794 back_attr_offset, chan,
1795 prim_mask, i, j);
1796
1797 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1798 is_face_positive,
1799 front,
1800 back,
1801 "");
1802 }
1803 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1804 result[0] = si_build_fs_interp(ctx, input_index,
1805 0, prim_mask, i, j);
1806 result[1] =
1807 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1808 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1809 } else {
1810 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1811 result[chan] = si_build_fs_interp(ctx,
1812 input_index, chan,
1813 prim_mask, i, j);
1814 }
1815 }
1816 }
1817
1818 void si_llvm_load_input_fs(
1819 struct si_shader_context *ctx,
1820 unsigned input_index,
1821 LLVMValueRef out[4])
1822 {
1823 struct lp_build_context *base = &ctx->bld_base.base;
1824 struct si_shader *shader = ctx->shader;
1825 struct tgsi_shader_info *info = &shader->selector->info;
1826 LLVMValueRef main_fn = ctx->main_fn;
1827 LLVMValueRef interp_param = NULL;
1828 int interp_param_idx;
1829 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1830 unsigned semantic_index = info->input_semantic_index[input_index];
1831 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1832 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1833
1834 /* Get colors from input VGPRs (set by the prolog). */
1835 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1836 unsigned colors_read = shader->selector->info.colors_read;
1837 unsigned mask = colors_read >> (semantic_index * 4);
1838 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1839 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1840
1841 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1842 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1843 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1844 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1845 return;
1846 }
1847
1848 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1849 if (interp_param_idx == -1)
1850 return;
1851 else if (interp_param_idx) {
1852 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1853 }
1854
1855 interp_fs_input(ctx, input_index, semantic_name,
1856 semantic_index, 0, /* this param is unused */
1857 shader->selector->info.colors_read, interp_param,
1858 ctx->abi.prim_mask,
1859 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1860 &out[0]);
1861 }
1862
1863 static void declare_input_fs(
1864 struct si_shader_context *ctx,
1865 unsigned input_index,
1866 const struct tgsi_full_declaration *decl,
1867 LLVMValueRef out[4])
1868 {
1869 si_llvm_load_input_fs(ctx, input_index, out);
1870 }
1871
1872 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1873 {
1874 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1875 }
1876
1877
1878 /**
1879 * Load a dword from a constant buffer.
1880 */
1881 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1882 LLVMValueRef resource,
1883 LLVMValueRef offset)
1884 {
1885 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1886 0, 0, 0, true, true);
1887 }
1888
1889 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1890 {
1891 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1892 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1893 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1894 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1895 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1896
1897 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1898 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1899 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1900
1901 LLVMValueRef pos[4] = {
1902 buffer_load_const(ctx, resource, offset0),
1903 buffer_load_const(ctx, resource, offset1),
1904 LLVMConstReal(ctx->f32, 0),
1905 LLVMConstReal(ctx->f32, 0)
1906 };
1907
1908 return lp_build_gather_values(&ctx->gallivm, pos, 4);
1909 }
1910
1911 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi,
1912 LLVMTypeRef type,
1913 unsigned num_components)
1914 {
1915 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1916 struct lp_build_context *bld = &ctx->bld_base.base;
1917
1918 LLVMValueRef coord[4] = {
1919 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1920 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1921 ctx->ac.f32_0,
1922 ctx->ac.f32_0
1923 };
1924
1925 /* For triangles, the vector should be (u, v, 1-u-v). */
1926 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1927 PIPE_PRIM_TRIANGLES)
1928 coord[2] = lp_build_sub(bld, ctx->ac.f32_1,
1929 lp_build_add(bld, coord[0], coord[1]));
1930
1931 return lp_build_gather_values(&ctx->gallivm, coord, 4);
1932 }
1933
1934 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
1935 unsigned semantic_name)
1936 {
1937 LLVMValueRef buffer, base, addr;
1938
1939 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
1940
1941 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1942
1943 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1944 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1945 LLVMConstInt(ctx->i32, param, 0));
1946
1947 return buffer_load(&ctx->bld_base, ctx->f32,
1948 ~0, buffer, base, addr, true);
1949
1950 }
1951
1952 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
1953 unsigned varying_id)
1954 {
1955 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1956 unsigned semantic_name;
1957
1958 switch (varying_id) {
1959 case VARYING_SLOT_TESS_LEVEL_INNER:
1960 semantic_name = TGSI_SEMANTIC_TESSINNER;
1961 break;
1962 case VARYING_SLOT_TESS_LEVEL_OUTER:
1963 semantic_name = TGSI_SEMANTIC_TESSOUTER;
1964 break;
1965 default:
1966 unreachable("unknown tess level");
1967 }
1968
1969 return load_tess_level(ctx, semantic_name);
1970
1971 }
1972
1973 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
1974 {
1975 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1976 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1977 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6);
1978 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1979 return get_num_tcs_out_vertices(ctx);
1980 else
1981 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1982 }
1983
1984 void si_load_system_value(struct si_shader_context *ctx,
1985 unsigned index,
1986 const struct tgsi_full_declaration *decl)
1987 {
1988 LLVMValueRef value = 0;
1989
1990 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
1991
1992 switch (decl->Semantic.Name) {
1993 case TGSI_SEMANTIC_INSTANCEID:
1994 value = ctx->abi.instance_id;
1995 break;
1996
1997 case TGSI_SEMANTIC_VERTEXID:
1998 value = LLVMBuildAdd(ctx->ac.builder,
1999 ctx->abi.vertex_id,
2000 ctx->abi.base_vertex, "");
2001 break;
2002
2003 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2004 /* Unused. Clarify the meaning in indexed vs. non-indexed
2005 * draws if this is ever used again. */
2006 assert(false);
2007 break;
2008
2009 case TGSI_SEMANTIC_BASEVERTEX:
2010 {
2011 /* For non-indexed draws, the base vertex set by the driver
2012 * (for direct draws) or the CP (for indirect draws) is the
2013 * first vertex ID, but GLSL expects 0 to be returned.
2014 */
2015 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
2016 LLVMValueRef indexed;
2017
2018 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
2019 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
2020
2021 value = LLVMBuildSelect(ctx->ac.builder, indexed,
2022 ctx->abi.base_vertex, ctx->i32_0, "");
2023 break;
2024 }
2025
2026 case TGSI_SEMANTIC_BASEINSTANCE:
2027 value = ctx->abi.start_instance;
2028 break;
2029
2030 case TGSI_SEMANTIC_DRAWID:
2031 value = ctx->abi.draw_id;
2032 break;
2033
2034 case TGSI_SEMANTIC_INVOCATIONID:
2035 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2036 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2037 else if (ctx->type == PIPE_SHADER_GEOMETRY)
2038 value = ctx->abi.gs_invocation_id;
2039 else
2040 assert(!"INVOCATIONID not implemented");
2041 break;
2042
2043 case TGSI_SEMANTIC_POSITION:
2044 {
2045 LLVMValueRef pos[4] = {
2046 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2047 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2048 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2049 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
2050 LLVMGetParam(ctx->main_fn,
2051 SI_PARAM_POS_W_FLOAT)),
2052 };
2053 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
2054 break;
2055 }
2056
2057 case TGSI_SEMANTIC_FACE:
2058 value = ctx->abi.front_face;
2059 break;
2060
2061 case TGSI_SEMANTIC_SAMPLEID:
2062 value = get_sample_id(ctx);
2063 break;
2064
2065 case TGSI_SEMANTIC_SAMPLEPOS: {
2066 LLVMValueRef pos[4] = {
2067 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2068 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2069 LLVMConstReal(ctx->f32, 0),
2070 LLVMConstReal(ctx->f32, 0)
2071 };
2072 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
2073 TGSI_OPCODE_FRC, pos[0]);
2074 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
2075 TGSI_OPCODE_FRC, pos[1]);
2076 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
2077 break;
2078 }
2079
2080 case TGSI_SEMANTIC_SAMPLEMASK:
2081 /* This can only occur with the OpenGL Core profile, which
2082 * doesn't support smoothing.
2083 */
2084 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2085 break;
2086
2087 case TGSI_SEMANTIC_TESSCOORD:
2088 value = si_load_tess_coord(&ctx->abi, NULL, 4);
2089 break;
2090
2091 case TGSI_SEMANTIC_VERTICESIN:
2092 value = si_load_patch_vertices_in(&ctx->abi);
2093 break;
2094
2095 case TGSI_SEMANTIC_TESSINNER:
2096 case TGSI_SEMANTIC_TESSOUTER:
2097 value = load_tess_level(ctx, decl->Semantic.Name);
2098 break;
2099
2100 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
2101 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
2102 {
2103 LLVMValueRef buf, slot, val[4];
2104 int i, offset;
2105
2106 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
2107 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2108 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
2109 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
2110
2111 for (i = 0; i < 4; i++)
2112 val[i] = buffer_load_const(ctx, buf,
2113 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
2114 value = lp_build_gather_values(&ctx->gallivm, val, 4);
2115 break;
2116 }
2117
2118 case TGSI_SEMANTIC_PRIMID:
2119 value = get_primitive_id(ctx, 0);
2120 break;
2121
2122 case TGSI_SEMANTIC_GRID_SIZE:
2123 value = LLVMGetParam(ctx->main_fn, ctx->param_grid_size);
2124 break;
2125
2126 case TGSI_SEMANTIC_BLOCK_SIZE:
2127 {
2128 LLVMValueRef values[3];
2129 unsigned i;
2130 unsigned *properties = ctx->shader->selector->info.properties;
2131
2132 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
2133 unsigned sizes[3] = {
2134 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
2135 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
2136 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
2137 };
2138
2139 for (i = 0; i < 3; ++i)
2140 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
2141
2142 value = lp_build_gather_values(&ctx->gallivm, values, 3);
2143 } else {
2144 value = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
2145 }
2146 break;
2147 }
2148
2149 case TGSI_SEMANTIC_BLOCK_ID:
2150 {
2151 LLVMValueRef values[3];
2152
2153 for (int i = 0; i < 3; i++) {
2154 values[i] = ctx->i32_0;
2155 if (ctx->abi.workgroup_ids[i]) {
2156 values[i] = ctx->abi.workgroup_ids[i];
2157 }
2158 }
2159 value = lp_build_gather_values(&ctx->gallivm, values, 3);
2160 break;
2161 }
2162
2163 case TGSI_SEMANTIC_THREAD_ID:
2164 value = LLVMGetParam(ctx->main_fn, ctx->param_thread_id);
2165 break;
2166
2167 case TGSI_SEMANTIC_HELPER_INVOCATION:
2168 value = lp_build_intrinsic(ctx->ac.builder,
2169 "llvm.amdgcn.ps.live",
2170 ctx->i1, NULL, 0,
2171 LP_FUNC_ATTR_READNONE);
2172 value = LLVMBuildNot(ctx->ac.builder, value, "");
2173 value = LLVMBuildSExt(ctx->ac.builder, value, ctx->i32, "");
2174 break;
2175
2176 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2177 value = LLVMConstInt(ctx->i32, 64, 0);
2178 break;
2179
2180 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2181 value = ac_get_thread_id(&ctx->ac);
2182 break;
2183
2184 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2185 {
2186 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2187 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2188 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
2189 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2190 break;
2191 }
2192
2193 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2194 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2195 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2196 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2197 {
2198 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2199 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2200 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2201 /* All bits set except LSB */
2202 value = LLVMConstInt(ctx->i64, -2, 0);
2203 } else {
2204 /* All bits set */
2205 value = LLVMConstInt(ctx->i64, -1, 0);
2206 }
2207 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2208 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2209 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2210 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2211 value = LLVMBuildNot(ctx->ac.builder, value, "");
2212 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2213 break;
2214 }
2215
2216 default:
2217 assert(!"unknown system value");
2218 return;
2219 }
2220
2221 ctx->system_values[index] = value;
2222 }
2223
2224 void si_declare_compute_memory(struct si_shader_context *ctx,
2225 const struct tgsi_full_declaration *decl)
2226 {
2227 struct si_shader_selector *sel = ctx->shader->selector;
2228
2229 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_LOCAL_ADDR_SPACE);
2230 LLVMValueRef var;
2231
2232 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2233 assert(decl->Range.First == decl->Range.Last);
2234 assert(!ctx->ac.lds);
2235
2236 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2237 LLVMArrayType(ctx->i8, sel->local_size),
2238 "compute_lds",
2239 AC_LOCAL_ADDR_SPACE);
2240 LLVMSetAlignment(var, 4);
2241
2242 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2243 }
2244
2245 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2246 {
2247 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2248 ctx->param_const_and_shader_buffers);
2249
2250 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2251 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2252 }
2253
2254 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2255 {
2256 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2257 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2258
2259 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2260 index = LLVMBuildAdd(ctx->ac.builder, index,
2261 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2262
2263 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2264 }
2265
2266 static LLVMValueRef
2267 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2268 {
2269 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2270 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2271 ctx->param_const_and_shader_buffers);
2272
2273 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2274 index = LLVMBuildSub(ctx->ac.builder,
2275 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2276 index, "");
2277
2278 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2279 }
2280
2281 static LLVMValueRef fetch_constant(
2282 struct lp_build_tgsi_context *bld_base,
2283 const struct tgsi_full_src_register *reg,
2284 enum tgsi_opcode_type type,
2285 unsigned swizzle)
2286 {
2287 struct si_shader_context *ctx = si_shader_context(bld_base);
2288 struct si_shader_selector *sel = ctx->shader->selector;
2289 const struct tgsi_ind_register *ireg = &reg->Indirect;
2290 unsigned buf, idx;
2291
2292 LLVMValueRef addr, bufp;
2293
2294 if (swizzle == LP_CHAN_ALL) {
2295 unsigned chan;
2296 LLVMValueRef values[4];
2297 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2298 values[chan] = fetch_constant(bld_base, reg, type, chan);
2299
2300 return lp_build_gather_values(&ctx->gallivm, values, 4);
2301 }
2302
2303 /* Split 64-bit loads. */
2304 if (tgsi_type_is_64bit(type)) {
2305 LLVMValueRef lo, hi;
2306
2307 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2308 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle + 1);
2309 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2310 lo, hi);
2311 }
2312
2313 idx = reg->Register.Index * 4 + swizzle;
2314 if (reg->Register.Indirect) {
2315 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2316 } else {
2317 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2318 }
2319
2320 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2321 if (sel->info.const_buffers_declared == 1 &&
2322 sel->info.shader_buffers_declared == 0) {
2323 LLVMValueRef ptr =
2324 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2325
2326 /* This enables use of s_load_dword and flat_load_dword for const buffer 0
2327 * loads, and up to x4 load opcode merging. However, it leads to horrible
2328 * code reducing SIMD wave occupancy from 8 to 2 in many cases.
2329 *
2330 * Using s_buffer_load_dword (x1) seems to be the best option right now.
2331 *
2332 * LLVM 5.0 on SI doesn't insert a required s_nop between SALU setting
2333 * a descriptor and s_buffer_load_dword using it, so we can't expand
2334 * the pointer into a full descriptor like below. We have to use
2335 * s_load_dword instead. The only case when LLVM 5.0 would select
2336 * s_buffer_load_dword (that we have to prevent) is when we use use
2337 * a literal offset where we don't need bounds checking.
2338 */
2339 if (ctx->screen->info.chip_class == SI &&
2340 HAVE_LLVM < 0x0600 &&
2341 !reg->Register.Indirect) {
2342 addr = LLVMBuildLShr(ctx->ac.builder, addr, LLVMConstInt(ctx->i32, 2, 0), "");
2343 LLVMValueRef result = ac_build_load_invariant(&ctx->ac, ptr, addr);
2344 return bitcast(bld_base, type, result);
2345 }
2346
2347 /* Do the bounds checking with a descriptor, because
2348 * doing computation and manual bounds checking of 64-bit
2349 * addresses generates horrible VALU code with very high
2350 * VGPR usage and very low SIMD occupancy.
2351 */
2352 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->i64, "");
2353 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ctx->v2i32, "");
2354
2355 LLVMValueRef desc_elems[] = {
2356 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_0, ""),
2357 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_1, ""),
2358 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2359 LLVMConstInt(ctx->i32,
2360 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2361 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2362 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2363 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2364 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2365 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2366 };
2367 LLVMValueRef desc = ac_build_gather_values(&ctx->ac, desc_elems, 4);
2368 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2369 return bitcast(bld_base, type, result);
2370 }
2371
2372 assert(reg->Register.Dimension);
2373 buf = reg->Dimension.Index;
2374
2375 if (reg->Dimension.Indirect) {
2376 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2377 LLVMValueRef index;
2378 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2379 reg->Dimension.Index,
2380 ctx->num_const_buffers);
2381 index = LLVMBuildAdd(ctx->ac.builder, index,
2382 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2383 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2384 } else
2385 bufp = load_const_buffer_desc(ctx, buf);
2386
2387 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2388 }
2389
2390 /* Initialize arguments for the shader export intrinsic */
2391 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2392 LLVMValueRef *values,
2393 unsigned target,
2394 struct ac_export_args *args)
2395 {
2396 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2397 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2398 unsigned chan;
2399 bool is_int8, is_int10;
2400
2401 /* Default is 0xf. Adjusted below depending on the format. */
2402 args->enabled_channels = 0xf; /* writemask */
2403
2404 /* Specify whether the EXEC mask represents the valid mask */
2405 args->valid_mask = 0;
2406
2407 /* Specify whether this is the last export */
2408 args->done = 0;
2409
2410 /* Specify the target we are exporting */
2411 args->target = target;
2412
2413 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2414 const struct si_shader_key *key = &ctx->shader->key;
2415 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2416 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2417
2418 assert(cbuf >= 0 && cbuf < 8);
2419 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2420 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2421 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2422 }
2423
2424 args->compr = false;
2425 args->out[0] = f32undef;
2426 args->out[1] = f32undef;
2427 args->out[2] = f32undef;
2428 args->out[3] = f32undef;
2429
2430 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2431 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2432 unsigned bits, bool hi) = NULL;
2433
2434 switch (spi_shader_col_format) {
2435 case V_028714_SPI_SHADER_ZERO:
2436 args->enabled_channels = 0; /* writemask */
2437 args->target = V_008DFC_SQ_EXP_NULL;
2438 break;
2439
2440 case V_028714_SPI_SHADER_32_R:
2441 args->enabled_channels = 1; /* writemask */
2442 args->out[0] = values[0];
2443 break;
2444
2445 case V_028714_SPI_SHADER_32_GR:
2446 args->enabled_channels = 0x3; /* writemask */
2447 args->out[0] = values[0];
2448 args->out[1] = values[1];
2449 break;
2450
2451 case V_028714_SPI_SHADER_32_AR:
2452 args->enabled_channels = 0x9; /* writemask */
2453 args->out[0] = values[0];
2454 args->out[3] = values[3];
2455 break;
2456
2457 case V_028714_SPI_SHADER_FP16_ABGR:
2458 packf = ac_build_cvt_pkrtz_f16;
2459 break;
2460
2461 case V_028714_SPI_SHADER_UNORM16_ABGR:
2462 packf = ac_build_cvt_pknorm_u16;
2463 break;
2464
2465 case V_028714_SPI_SHADER_SNORM16_ABGR:
2466 packf = ac_build_cvt_pknorm_i16;
2467 break;
2468
2469 case V_028714_SPI_SHADER_UINT16_ABGR:
2470 packi = ac_build_cvt_pk_u16;
2471 break;
2472
2473 case V_028714_SPI_SHADER_SINT16_ABGR:
2474 packi = ac_build_cvt_pk_i16;
2475 break;
2476
2477 case V_028714_SPI_SHADER_32_ABGR:
2478 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2479 break;
2480 }
2481
2482 /* Pack f16 or norm_i16/u16. */
2483 if (packf) {
2484 for (chan = 0; chan < 2; chan++) {
2485 LLVMValueRef pack_args[2] = {
2486 values[2 * chan],
2487 values[2 * chan + 1]
2488 };
2489 LLVMValueRef packed;
2490
2491 packed = packf(&ctx->ac, pack_args);
2492 args->out[chan] = ac_to_float(&ctx->ac, packed);
2493 }
2494 args->compr = 1; /* COMPR flag */
2495 }
2496 /* Pack i16/u16. */
2497 if (packi) {
2498 for (chan = 0; chan < 2; chan++) {
2499 LLVMValueRef pack_args[2] = {
2500 ac_to_integer(&ctx->ac, values[2 * chan]),
2501 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2502 };
2503 LLVMValueRef packed;
2504
2505 packed = packi(&ctx->ac, pack_args,
2506 is_int8 ? 8 : is_int10 ? 10 : 16,
2507 chan == 1);
2508 args->out[chan] = ac_to_float(&ctx->ac, packed);
2509 }
2510 args->compr = 1; /* COMPR flag */
2511 }
2512 }
2513
2514 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2515 LLVMValueRef alpha)
2516 {
2517 struct si_shader_context *ctx = si_shader_context(bld_base);
2518
2519 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2520 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2521 [PIPE_FUNC_LESS] = LLVMRealOLT,
2522 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2523 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2524 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2525 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2526 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2527 };
2528 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2529 assert(cond);
2530
2531 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2532 SI_PARAM_ALPHA_REF);
2533 LLVMValueRef alpha_pass =
2534 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2535 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2536 } else {
2537 ac_build_kill_if_false(&ctx->ac, LLVMConstInt(ctx->i1, 0, 0));
2538 }
2539 }
2540
2541 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2542 LLVMValueRef alpha,
2543 unsigned samplemask_param)
2544 {
2545 struct si_shader_context *ctx = si_shader_context(bld_base);
2546 LLVMValueRef coverage;
2547
2548 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2549 coverage = LLVMGetParam(ctx->main_fn,
2550 samplemask_param);
2551 coverage = ac_to_integer(&ctx->ac, coverage);
2552
2553 coverage = lp_build_intrinsic(ctx->ac.builder, "llvm.ctpop.i32",
2554 ctx->i32,
2555 &coverage, 1, LP_FUNC_ATTR_READNONE);
2556
2557 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2558 ctx->f32, "");
2559
2560 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2561 LLVMConstReal(ctx->f32,
2562 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2563
2564 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2565 }
2566
2567 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2568 struct ac_export_args *pos, LLVMValueRef *out_elts)
2569 {
2570 unsigned reg_index;
2571 unsigned chan;
2572 unsigned const_chan;
2573 LLVMValueRef base_elt;
2574 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2575 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2576 SI_VS_CONST_CLIP_PLANES, 0);
2577 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2578
2579 for (reg_index = 0; reg_index < 2; reg_index ++) {
2580 struct ac_export_args *args = &pos[2 + reg_index];
2581
2582 args->out[0] =
2583 args->out[1] =
2584 args->out[2] =
2585 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2586
2587 /* Compute dot products of position and user clip plane vectors */
2588 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2589 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2590 LLVMValueRef addr =
2591 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2592 const_chan) * 4, 0);
2593 base_elt = buffer_load_const(ctx, const_resource,
2594 addr);
2595 args->out[chan] =
2596 lp_build_add(&ctx->bld_base.base, args->out[chan],
2597 lp_build_mul(&ctx->bld_base.base, base_elt,
2598 out_elts[const_chan]));
2599 }
2600 }
2601
2602 args->enabled_channels = 0xf;
2603 args->valid_mask = 0;
2604 args->done = 0;
2605 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2606 args->compr = 0;
2607 }
2608 }
2609
2610 static void si_dump_streamout(struct pipe_stream_output_info *so)
2611 {
2612 unsigned i;
2613
2614 if (so->num_outputs)
2615 fprintf(stderr, "STREAMOUT\n");
2616
2617 for (i = 0; i < so->num_outputs; i++) {
2618 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2619 so->output[i].start_component;
2620 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2621 i, so->output[i].output_buffer,
2622 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2623 so->output[i].register_index,
2624 mask & 1 ? "x" : "",
2625 mask & 2 ? "y" : "",
2626 mask & 4 ? "z" : "",
2627 mask & 8 ? "w" : "");
2628 }
2629 }
2630
2631 static void emit_streamout_output(struct si_shader_context *ctx,
2632 LLVMValueRef const *so_buffers,
2633 LLVMValueRef const *so_write_offsets,
2634 struct pipe_stream_output *stream_out,
2635 struct si_shader_output_values *shader_out)
2636 {
2637 unsigned buf_idx = stream_out->output_buffer;
2638 unsigned start = stream_out->start_component;
2639 unsigned num_comps = stream_out->num_components;
2640 LLVMValueRef out[4];
2641
2642 assert(num_comps && num_comps <= 4);
2643 if (!num_comps || num_comps > 4)
2644 return;
2645
2646 /* Load the output as int. */
2647 for (int j = 0; j < num_comps; j++) {
2648 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2649
2650 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2651 }
2652
2653 /* Pack the output. */
2654 LLVMValueRef vdata = NULL;
2655
2656 switch (num_comps) {
2657 case 1: /* as i32 */
2658 vdata = out[0];
2659 break;
2660 case 2: /* as v2i32 */
2661 case 3: /* as v4i32 (aligned to 4) */
2662 case 4: /* as v4i32 */
2663 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2664 for (int j = 0; j < num_comps; j++) {
2665 vdata = LLVMBuildInsertElement(ctx->ac.builder, vdata, out[j],
2666 LLVMConstInt(ctx->i32, j, 0), "");
2667 }
2668 break;
2669 }
2670
2671 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2672 vdata, num_comps,
2673 so_write_offsets[buf_idx],
2674 ctx->i32_0,
2675 stream_out->dst_offset * 4, 1, 1, true, false);
2676 }
2677
2678 /**
2679 * Write streamout data to buffers for vertex stream @p stream (different
2680 * vertex streams can occur for GS copy shaders).
2681 */
2682 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2683 struct si_shader_output_values *outputs,
2684 unsigned noutput, unsigned stream)
2685 {
2686 struct si_shader_selector *sel = ctx->shader->selector;
2687 struct pipe_stream_output_info *so = &sel->so;
2688 LLVMBuilderRef builder = ctx->ac.builder;
2689 int i;
2690 struct lp_build_if_state if_ctx;
2691
2692 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2693 LLVMValueRef so_vtx_count =
2694 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2695
2696 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2697
2698 /* can_emit = tid < so_vtx_count; */
2699 LLVMValueRef can_emit =
2700 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2701
2702 /* Emit the streamout code conditionally. This actually avoids
2703 * out-of-bounds buffer access. The hw tells us via the SGPR
2704 * (so_vtx_count) which threads are allowed to emit streamout data. */
2705 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2706 {
2707 /* The buffer offset is computed as follows:
2708 * ByteOffset = streamout_offset[buffer_id]*4 +
2709 * (streamout_write_index + thread_id)*stride[buffer_id] +
2710 * attrib_offset
2711 */
2712
2713 LLVMValueRef so_write_index =
2714 LLVMGetParam(ctx->main_fn,
2715 ctx->param_streamout_write_index);
2716
2717 /* Compute (streamout_write_index + thread_id). */
2718 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2719
2720 /* Load the descriptor and compute the write offset for each
2721 * enabled buffer. */
2722 LLVMValueRef so_write_offset[4] = {};
2723 LLVMValueRef so_buffers[4];
2724 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2725 ctx->param_rw_buffers);
2726
2727 for (i = 0; i < 4; i++) {
2728 if (!so->stride[i])
2729 continue;
2730
2731 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2732 SI_VS_STREAMOUT_BUF0 + i, 0);
2733
2734 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2735
2736 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2737 ctx->param_streamout_offset[i]);
2738 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2739
2740 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2741 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2742 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2743 }
2744
2745 /* Write streamout data. */
2746 for (i = 0; i < so->num_outputs; i++) {
2747 unsigned reg = so->output[i].register_index;
2748
2749 if (reg >= noutput)
2750 continue;
2751
2752 if (stream != so->output[i].stream)
2753 continue;
2754
2755 emit_streamout_output(ctx, so_buffers, so_write_offset,
2756 &so->output[i], &outputs[reg]);
2757 }
2758 }
2759 lp_build_endif(&if_ctx);
2760 }
2761
2762 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2763 LLVMValueRef *values)
2764 {
2765 struct ac_export_args args;
2766
2767 si_llvm_init_export_args(ctx, values,
2768 V_008DFC_SQ_EXP_PARAM + index, &args);
2769 ac_build_export(&ctx->ac, &args);
2770 }
2771
2772 static void si_build_param_exports(struct si_shader_context *ctx,
2773 struct si_shader_output_values *outputs,
2774 unsigned noutput)
2775 {
2776 struct si_shader *shader = ctx->shader;
2777 unsigned param_count = 0;
2778
2779 for (unsigned i = 0; i < noutput; i++) {
2780 unsigned semantic_name = outputs[i].semantic_name;
2781 unsigned semantic_index = outputs[i].semantic_index;
2782
2783 if (outputs[i].vertex_stream[0] != 0 &&
2784 outputs[i].vertex_stream[1] != 0 &&
2785 outputs[i].vertex_stream[2] != 0 &&
2786 outputs[i].vertex_stream[3] != 0)
2787 continue;
2788
2789 switch (semantic_name) {
2790 case TGSI_SEMANTIC_LAYER:
2791 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2792 case TGSI_SEMANTIC_CLIPDIST:
2793 case TGSI_SEMANTIC_COLOR:
2794 case TGSI_SEMANTIC_BCOLOR:
2795 case TGSI_SEMANTIC_PRIMID:
2796 case TGSI_SEMANTIC_FOG:
2797 case TGSI_SEMANTIC_TEXCOORD:
2798 case TGSI_SEMANTIC_GENERIC:
2799 break;
2800 default:
2801 continue;
2802 }
2803
2804 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2805 semantic_index < SI_MAX_IO_GENERIC) &&
2806 shader->key.opt.kill_outputs &
2807 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2808 continue;
2809
2810 si_export_param(ctx, param_count, outputs[i].values);
2811
2812 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2813 shader->info.vs_output_param_offset[i] = param_count++;
2814 }
2815
2816 shader->info.nr_param_exports = param_count;
2817 }
2818
2819 /* Generate export instructions for hardware VS shader stage */
2820 static void si_llvm_export_vs(struct si_shader_context *ctx,
2821 struct si_shader_output_values *outputs,
2822 unsigned noutput)
2823 {
2824 struct si_shader *shader = ctx->shader;
2825 struct ac_export_args pos_args[4] = {};
2826 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2827 unsigned pos_idx;
2828 int i;
2829
2830 /* Build position exports. */
2831 for (i = 0; i < noutput; i++) {
2832 switch (outputs[i].semantic_name) {
2833 case TGSI_SEMANTIC_POSITION:
2834 si_llvm_init_export_args(ctx, outputs[i].values,
2835 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2836 break;
2837 case TGSI_SEMANTIC_PSIZE:
2838 psize_value = outputs[i].values[0];
2839 break;
2840 case TGSI_SEMANTIC_LAYER:
2841 layer_value = outputs[i].values[0];
2842 break;
2843 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2844 viewport_index_value = outputs[i].values[0];
2845 break;
2846 case TGSI_SEMANTIC_EDGEFLAG:
2847 edgeflag_value = outputs[i].values[0];
2848 break;
2849 case TGSI_SEMANTIC_CLIPDIST:
2850 if (!shader->key.opt.clip_disable) {
2851 unsigned index = 2 + outputs[i].semantic_index;
2852 si_llvm_init_export_args(ctx, outputs[i].values,
2853 V_008DFC_SQ_EXP_POS + index,
2854 &pos_args[index]);
2855 }
2856 break;
2857 case TGSI_SEMANTIC_CLIPVERTEX:
2858 if (!shader->key.opt.clip_disable) {
2859 si_llvm_emit_clipvertex(ctx, pos_args,
2860 outputs[i].values);
2861 }
2862 break;
2863 }
2864 }
2865
2866 /* We need to add the position output manually if it's missing. */
2867 if (!pos_args[0].out[0]) {
2868 pos_args[0].enabled_channels = 0xf; /* writemask */
2869 pos_args[0].valid_mask = 0; /* EXEC mask */
2870 pos_args[0].done = 0; /* last export? */
2871 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2872 pos_args[0].compr = 0; /* COMPR flag */
2873 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2874 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2875 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2876 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2877 }
2878
2879 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2880 if (shader->selector->info.writes_psize ||
2881 shader->selector->info.writes_edgeflag ||
2882 shader->selector->info.writes_viewport_index ||
2883 shader->selector->info.writes_layer) {
2884 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2885 (shader->selector->info.writes_edgeflag << 1) |
2886 (shader->selector->info.writes_layer << 2);
2887
2888 pos_args[1].valid_mask = 0; /* EXEC mask */
2889 pos_args[1].done = 0; /* last export? */
2890 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2891 pos_args[1].compr = 0; /* COMPR flag */
2892 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2893 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2894 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2895 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2896
2897 if (shader->selector->info.writes_psize)
2898 pos_args[1].out[0] = psize_value;
2899
2900 if (shader->selector->info.writes_edgeflag) {
2901 /* The output is a float, but the hw expects an integer
2902 * with the first bit containing the edge flag. */
2903 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2904 edgeflag_value,
2905 ctx->i32, "");
2906 edgeflag_value = ac_build_umin(&ctx->ac,
2907 edgeflag_value,
2908 ctx->i32_1);
2909
2910 /* The LLVM intrinsic expects a float. */
2911 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2912 }
2913
2914 if (ctx->screen->info.chip_class >= GFX9) {
2915 /* GFX9 has the layer in out.z[10:0] and the viewport
2916 * index in out.z[19:16].
2917 */
2918 if (shader->selector->info.writes_layer)
2919 pos_args[1].out[2] = layer_value;
2920
2921 if (shader->selector->info.writes_viewport_index) {
2922 LLVMValueRef v = viewport_index_value;
2923
2924 v = ac_to_integer(&ctx->ac, v);
2925 v = LLVMBuildShl(ctx->ac.builder, v,
2926 LLVMConstInt(ctx->i32, 16, 0), "");
2927 v = LLVMBuildOr(ctx->ac.builder, v,
2928 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2929 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2930 pos_args[1].enabled_channels |= 1 << 2;
2931 }
2932 } else {
2933 if (shader->selector->info.writes_layer)
2934 pos_args[1].out[2] = layer_value;
2935
2936 if (shader->selector->info.writes_viewport_index) {
2937 pos_args[1].out[3] = viewport_index_value;
2938 pos_args[1].enabled_channels |= 1 << 3;
2939 }
2940 }
2941 }
2942
2943 for (i = 0; i < 4; i++)
2944 if (pos_args[i].out[0])
2945 shader->info.nr_pos_exports++;
2946
2947 pos_idx = 0;
2948 for (i = 0; i < 4; i++) {
2949 if (!pos_args[i].out[0])
2950 continue;
2951
2952 /* Specify the target we are exporting */
2953 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2954
2955 if (pos_idx == shader->info.nr_pos_exports)
2956 /* Specify that this is the last export */
2957 pos_args[i].done = 1;
2958
2959 ac_build_export(&ctx->ac, &pos_args[i]);
2960 }
2961
2962 /* Build parameter exports. */
2963 si_build_param_exports(ctx, outputs, noutput);
2964 }
2965
2966 /**
2967 * Forward all outputs from the vertex shader to the TES. This is only used
2968 * for the fixed function TCS.
2969 */
2970 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2971 {
2972 struct si_shader_context *ctx = si_shader_context(bld_base);
2973 LLVMValueRef invocation_id, buffer, buffer_offset;
2974 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2975 uint64_t inputs;
2976
2977 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2978 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
2979 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2980
2981 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
2982 lds_vertex_offset = LLVMBuildMul(ctx->ac.builder, invocation_id,
2983 lds_vertex_stride, "");
2984 lds_base = get_tcs_in_current_patch_offset(ctx);
2985 lds_base = LLVMBuildAdd(ctx->ac.builder, lds_base, lds_vertex_offset, "");
2986
2987 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
2988 while (inputs) {
2989 unsigned i = u_bit_scan64(&inputs);
2990
2991 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2992 LLVMConstInt(ctx->i32, 4 * i, 0),
2993 "");
2994
2995 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2996 get_rel_patch_id(ctx),
2997 invocation_id,
2998 LLVMConstInt(ctx->i32, i, 0));
2999
3000 LLVMValueRef value = lds_load(bld_base, ctx->ac.i32, ~0,
3001 lds_ptr);
3002
3003 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
3004 buffer_offset, 0, 1, 0, true, false);
3005 }
3006 }
3007
3008 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
3009 LLVMValueRef rel_patch_id,
3010 LLVMValueRef invocation_id,
3011 LLVMValueRef tcs_out_current_patch_data_offset,
3012 LLVMValueRef invoc0_tf_outer[4],
3013 LLVMValueRef invoc0_tf_inner[2])
3014 {
3015 struct si_shader_context *ctx = si_shader_context(bld_base);
3016 struct si_shader *shader = ctx->shader;
3017 unsigned tess_inner_index, tess_outer_index;
3018 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
3019 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3020 unsigned stride, outer_comps, inner_comps, i, offset;
3021 struct lp_build_if_state if_ctx, inner_if_ctx;
3022
3023 /* Add a barrier before loading tess factors from LDS. */
3024 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
3025 si_llvm_emit_barrier(NULL, bld_base, NULL);
3026
3027 /* Do this only for invocation 0, because the tess levels are per-patch,
3028 * not per-vertex.
3029 *
3030 * This can't jump, because invocation 0 executes this. It should
3031 * at least mask out the loads and stores for other invocations.
3032 */
3033 lp_build_if(&if_ctx, &ctx->gallivm,
3034 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3035 invocation_id, ctx->i32_0, ""));
3036
3037 /* Determine the layout of one tess factor element in the buffer. */
3038 switch (shader->key.part.tcs.epilog.prim_mode) {
3039 case PIPE_PRIM_LINES:
3040 stride = 2; /* 2 dwords, 1 vec2 store */
3041 outer_comps = 2;
3042 inner_comps = 0;
3043 break;
3044 case PIPE_PRIM_TRIANGLES:
3045 stride = 4; /* 4 dwords, 1 vec4 store */
3046 outer_comps = 3;
3047 inner_comps = 1;
3048 break;
3049 case PIPE_PRIM_QUADS:
3050 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3051 outer_comps = 4;
3052 inner_comps = 2;
3053 break;
3054 default:
3055 assert(0);
3056 return;
3057 }
3058
3059 for (i = 0; i < 4; i++) {
3060 inner[i] = LLVMGetUndef(ctx->i32);
3061 outer[i] = LLVMGetUndef(ctx->i32);
3062 }
3063
3064 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3065 /* Tess factors are in VGPRs. */
3066 for (i = 0; i < outer_comps; i++)
3067 outer[i] = out[i] = invoc0_tf_outer[i];
3068 for (i = 0; i < inner_comps; i++)
3069 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3070 } else {
3071 /* Load tess_inner and tess_outer from LDS.
3072 * Any invocation can write them, so we can't get them from a temporary.
3073 */
3074 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3075 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3076
3077 lds_base = tcs_out_current_patch_data_offset;
3078 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3079 LLVMConstInt(ctx->i32,
3080 tess_inner_index * 4, 0), "");
3081 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3082 LLVMConstInt(ctx->i32,
3083 tess_outer_index * 4, 0), "");
3084
3085 for (i = 0; i < outer_comps; i++) {
3086 outer[i] = out[i] =
3087 lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3088 }
3089 for (i = 0; i < inner_comps; i++) {
3090 inner[i] = out[outer_comps+i] =
3091 lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3092 }
3093 }
3094
3095 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3096 /* For isolines, the hardware expects tess factors in the
3097 * reverse order from what GLSL / TGSI specify.
3098 */
3099 LLVMValueRef tmp = out[0];
3100 out[0] = out[1];
3101 out[1] = tmp;
3102 }
3103
3104 /* Convert the outputs to vectors for stores. */
3105 vec0 = lp_build_gather_values(&ctx->gallivm, out, MIN2(stride, 4));
3106 vec1 = NULL;
3107
3108 if (stride > 4)
3109 vec1 = lp_build_gather_values(&ctx->gallivm, out+4, stride - 4);
3110
3111 /* Get the buffer. */
3112 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_factor_addr_base64k);
3113
3114 /* Get the offset. */
3115 tf_base = LLVMGetParam(ctx->main_fn,
3116 ctx->param_tcs_factor_offset);
3117 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3118 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3119
3120 lp_build_if(&inner_if_ctx, &ctx->gallivm,
3121 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3122 rel_patch_id, ctx->i32_0, ""));
3123
3124 /* Store the dynamic HS control word. */
3125 offset = 0;
3126 if (ctx->screen->info.chip_class <= VI) {
3127 ac_build_buffer_store_dword(&ctx->ac, buffer,
3128 LLVMConstInt(ctx->i32, 0x80000000, 0),
3129 1, ctx->i32_0, tf_base,
3130 offset, 1, 0, true, false);
3131 offset += 4;
3132 }
3133
3134 lp_build_endif(&inner_if_ctx);
3135
3136 /* Store the tessellation factors. */
3137 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3138 MIN2(stride, 4), byteoffset, tf_base,
3139 offset, 1, 0, true, false);
3140 offset += 16;
3141 if (vec1)
3142 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3143 stride - 4, byteoffset, tf_base,
3144 offset, 1, 0, true, false);
3145
3146 /* Store the tess factors into the offchip buffer if TES reads them. */
3147 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3148 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3149 LLVMValueRef tf_inner_offset;
3150 unsigned param_outer, param_inner;
3151
3152 buf = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
3153 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3154
3155 param_outer = si_shader_io_get_unique_index_patch(
3156 TGSI_SEMANTIC_TESSOUTER, 0);
3157 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3158 LLVMConstInt(ctx->i32, param_outer, 0));
3159
3160 outer_vec = lp_build_gather_values(&ctx->gallivm, outer,
3161 util_next_power_of_two(outer_comps));
3162
3163 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3164 outer_comps, tf_outer_offset,
3165 base, 0, 1, 0, true, false);
3166 if (inner_comps) {
3167 param_inner = si_shader_io_get_unique_index_patch(
3168 TGSI_SEMANTIC_TESSINNER, 0);
3169 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3170 LLVMConstInt(ctx->i32, param_inner, 0));
3171
3172 inner_vec = inner_comps == 1 ? inner[0] :
3173 lp_build_gather_values(&ctx->gallivm, inner, inner_comps);
3174 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3175 inner_comps, tf_inner_offset,
3176 base, 0, 1, 0, true, false);
3177 }
3178 }
3179
3180 lp_build_endif(&if_ctx);
3181 }
3182
3183 static LLVMValueRef
3184 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3185 unsigned param, unsigned return_index)
3186 {
3187 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3188 LLVMGetParam(ctx->main_fn, param),
3189 return_index, "");
3190 }
3191
3192 static LLVMValueRef
3193 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3194 unsigned param, unsigned return_index)
3195 {
3196 LLVMBuilderRef builder = ctx->ac.builder;
3197 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3198
3199 return LLVMBuildInsertValue(builder, ret,
3200 ac_to_float(&ctx->ac, p),
3201 return_index, "");
3202 }
3203
3204 static LLVMValueRef
3205 si_insert_input_ptr_as_2xi32(struct si_shader_context *ctx, LLVMValueRef ret,
3206 unsigned param, unsigned return_index)
3207 {
3208 LLVMBuilderRef builder = ctx->ac.builder;
3209 LLVMValueRef ptr, lo, hi;
3210
3211 ptr = LLVMGetParam(ctx->main_fn, param);
3212 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
3213 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
3214 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
3215 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
3216 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
3217 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
3218 }
3219
3220 /* This only writes the tessellation factor levels. */
3221 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
3222 unsigned max_outputs,
3223 LLVMValueRef *addrs)
3224 {
3225 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3226 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
3227 LLVMBuilderRef builder = ctx->ac.builder;
3228 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3229
3230 si_copy_tcs_inputs(bld_base);
3231
3232 rel_patch_id = get_rel_patch_id(ctx);
3233 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3234 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3235
3236 if (ctx->screen->info.chip_class >= GFX9) {
3237 LLVMBasicBlockRef blocks[2] = {
3238 LLVMGetInsertBlock(builder),
3239 ctx->merged_wrap_if_state.entry_block
3240 };
3241 LLVMValueRef values[2];
3242
3243 lp_build_endif(&ctx->merged_wrap_if_state);
3244
3245 values[0] = rel_patch_id;
3246 values[1] = LLVMGetUndef(ctx->i32);
3247 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3248
3249 values[0] = tf_lds_offset;
3250 values[1] = LLVMGetUndef(ctx->i32);
3251 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3252
3253 values[0] = invocation_id;
3254 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3255 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3256 }
3257
3258 /* Return epilog parameters from this function. */
3259 LLVMValueRef ret = ctx->return_value;
3260 unsigned vgpr;
3261
3262 if (ctx->screen->info.chip_class >= GFX9) {
3263 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3264 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3265 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3266 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3267 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3268 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
3269 /* Tess offchip and tess factor offsets are at the beginning. */
3270 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3271 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3272 vgpr = 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K + 1;
3273 } else {
3274 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3275 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3276 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3277 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3278 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3279 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K);
3280 /* Tess offchip and tess factor offsets are after user SGPRs. */
3281 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3282 GFX6_TCS_NUM_USER_SGPR);
3283 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3284 GFX6_TCS_NUM_USER_SGPR + 1);
3285 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3286 }
3287
3288 /* VGPRs */
3289 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3290 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3291 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3292
3293 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3294 * the invocation_id output does not alias the tcs_rel_ids input,
3295 * which saves a V_MOV on gfx9.
3296 */
3297 vgpr += 2;
3298
3299 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3300 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3301
3302 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3303 vgpr++; /* skip the tess factor LDS offset */
3304 for (unsigned i = 0; i < 6; i++) {
3305 LLVMValueRef value =
3306 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3307 value = ac_to_float(&ctx->ac, value);
3308 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3309 }
3310 } else {
3311 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3312 }
3313 ctx->return_value = ret;
3314 }
3315
3316 /* Pass TCS inputs from LS to TCS on GFX9. */
3317 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3318 {
3319 LLVMValueRef ret = ctx->return_value;
3320
3321 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3322 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3323 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3324 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3325
3326 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
3327 8 + SI_SGPR_RW_BUFFERS);
3328 ret = si_insert_input_ptr_as_2xi32(ctx, ret,
3329 ctx->param_bindless_samplers_and_images,
3330 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3331
3332 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3333 8 + SI_SGPR_VS_STATE_BITS);
3334 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3335 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3336 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3337 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3338 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3339 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3340 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3341 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3342 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3343 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
3344
3345 unsigned desc_param = ctx->param_tcs_factor_addr_base64k + 2;
3346 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
3347 8 + GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS);
3348 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
3349 8 + GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES);
3350
3351 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3352 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3353 ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
3354 vgpr++, "");
3355 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3356 ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
3357 vgpr++, "");
3358 ctx->return_value = ret;
3359 }
3360
3361 /* Pass GS inputs from ES to GS on GFX9. */
3362 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3363 {
3364 LLVMValueRef ret = ctx->return_value;
3365
3366 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3367 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3368 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3369
3370 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
3371 8 + SI_SGPR_RW_BUFFERS);
3372 ret = si_insert_input_ptr_as_2xi32(ctx, ret,
3373 ctx->param_bindless_samplers_and_images,
3374 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3375
3376 unsigned desc_param = ctx->param_vs_state_bits + 1;
3377 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
3378 8 + GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS);
3379 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
3380 8 + GFX9_SGPR_GS_SAMPLERS_AND_IMAGES);
3381
3382 unsigned vgpr = 8 + GFX9_GS_NUM_USER_SGPR;
3383 for (unsigned i = 0; i < 5; i++) {
3384 unsigned param = ctx->param_gs_vtx01_offset + i;
3385 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3386 }
3387 ctx->return_value = ret;
3388 }
3389
3390 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3391 unsigned max_outputs,
3392 LLVMValueRef *addrs)
3393 {
3394 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3395 struct si_shader *shader = ctx->shader;
3396 struct tgsi_shader_info *info = &shader->selector->info;
3397 unsigned i, chan;
3398 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3399 ctx->param_rel_auto_id);
3400 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3401 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3402 vertex_dw_stride, "");
3403
3404 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3405 * its inputs from it. */
3406 for (i = 0; i < info->num_outputs; i++) {
3407 unsigned name = info->output_semantic_name[i];
3408 unsigned index = info->output_semantic_index[i];
3409
3410 /* The ARB_shader_viewport_layer_array spec contains the
3411 * following issue:
3412 *
3413 * 2) What happens if gl_ViewportIndex or gl_Layer is
3414 * written in the vertex shader and a geometry shader is
3415 * present?
3416 *
3417 * RESOLVED: The value written by the last vertex processing
3418 * stage is used. If the last vertex processing stage
3419 * (vertex, tessellation evaluation or geometry) does not
3420 * statically assign to gl_ViewportIndex or gl_Layer, index
3421 * or layer zero is assumed.
3422 *
3423 * So writes to those outputs in VS-as-LS are simply ignored.
3424 */
3425 if (name == TGSI_SEMANTIC_LAYER ||
3426 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3427 continue;
3428
3429 int param = si_shader_io_get_unique_index(name, index);
3430 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3431 LLVMConstInt(ctx->i32, param * 4, 0), "");
3432
3433 for (chan = 0; chan < 4; chan++) {
3434 if (!(info->output_usagemask[i] & (1 << chan)))
3435 continue;
3436
3437 lds_store(ctx, chan, dw_addr,
3438 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3439 }
3440 }
3441
3442 if (ctx->screen->info.chip_class >= GFX9)
3443 si_set_ls_return_value_for_tcs(ctx);
3444 }
3445
3446 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3447 unsigned max_outputs,
3448 LLVMValueRef *addrs)
3449 {
3450 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3451 struct si_shader *es = ctx->shader;
3452 struct tgsi_shader_info *info = &es->selector->info;
3453 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3454 ctx->param_es2gs_offset);
3455 LLVMValueRef lds_base = NULL;
3456 unsigned chan;
3457 int i;
3458
3459 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3460 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3461 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3462 LLVMValueRef wave_idx = unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3463 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3464 LLVMBuildMul(ctx->ac.builder, wave_idx,
3465 LLVMConstInt(ctx->i32, 64, false), ""), "");
3466 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3467 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3468 }
3469
3470 for (i = 0; i < info->num_outputs; i++) {
3471 int param;
3472
3473 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3474 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3475 continue;
3476
3477 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3478 info->output_semantic_index[i]);
3479
3480 for (chan = 0; chan < 4; chan++) {
3481 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3482 out_val = ac_to_integer(&ctx->ac, out_val);
3483
3484 /* GFX9 has the ESGS ring in LDS. */
3485 if (ctx->screen->info.chip_class >= GFX9) {
3486 lds_store(ctx, param * 4 + chan, lds_base, out_val);
3487 continue;
3488 }
3489
3490 ac_build_buffer_store_dword(&ctx->ac,
3491 ctx->esgs_ring,
3492 out_val, 1, NULL, soffset,
3493 (4 * param + chan) * 4,
3494 1, 1, true, true);
3495 }
3496 }
3497
3498 if (ctx->screen->info.chip_class >= GFX9)
3499 si_set_es_return_value_for_gs(ctx);
3500 }
3501
3502 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3503 {
3504 if (ctx->screen->info.chip_class >= GFX9)
3505 return unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3506 else
3507 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3508 }
3509
3510 static void emit_gs_epilogue(struct si_shader_context *ctx)
3511 {
3512 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3513 si_get_gs_wave_id(ctx));
3514
3515 if (ctx->screen->info.chip_class >= GFX9)
3516 lp_build_endif(&ctx->merged_wrap_if_state);
3517 }
3518
3519 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3520 unsigned max_outputs,
3521 LLVMValueRef *addrs)
3522 {
3523 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3524 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3525
3526 assert(info->num_outputs <= max_outputs);
3527
3528 emit_gs_epilogue(ctx);
3529 }
3530
3531 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3532 {
3533 struct si_shader_context *ctx = si_shader_context(bld_base);
3534 emit_gs_epilogue(ctx);
3535 }
3536
3537 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3538 unsigned max_outputs,
3539 LLVMValueRef *addrs)
3540 {
3541 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3542 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3543 struct si_shader_output_values *outputs = NULL;
3544 int i,j;
3545
3546 assert(!ctx->shader->is_gs_copy_shader);
3547 assert(info->num_outputs <= max_outputs);
3548
3549 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3550
3551 /* Vertex color clamping.
3552 *
3553 * This uses a state constant loaded in a user data SGPR and
3554 * an IF statement is added that clamps all colors if the constant
3555 * is true.
3556 */
3557 if (ctx->type == PIPE_SHADER_VERTEX) {
3558 struct lp_build_if_state if_ctx;
3559 LLVMValueRef cond = NULL;
3560 LLVMValueRef addr, val;
3561
3562 for (i = 0; i < info->num_outputs; i++) {
3563 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3564 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3565 continue;
3566
3567 /* We've found a color. */
3568 if (!cond) {
3569 /* The state is in the first bit of the user SGPR. */
3570 cond = LLVMGetParam(ctx->main_fn,
3571 ctx->param_vs_state_bits);
3572 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3573 ctx->i1, "");
3574 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3575 }
3576
3577 for (j = 0; j < 4; j++) {
3578 addr = addrs[4 * i + j];
3579 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3580 val = ac_build_clamp(&ctx->ac, val);
3581 LLVMBuildStore(ctx->ac.builder, val, addr);
3582 }
3583 }
3584
3585 if (cond)
3586 lp_build_endif(&if_ctx);
3587 }
3588
3589 for (i = 0; i < info->num_outputs; i++) {
3590 outputs[i].semantic_name = info->output_semantic_name[i];
3591 outputs[i].semantic_index = info->output_semantic_index[i];
3592
3593 for (j = 0; j < 4; j++) {
3594 outputs[i].values[j] =
3595 LLVMBuildLoad(ctx->ac.builder,
3596 addrs[4 * i + j],
3597 "");
3598 outputs[i].vertex_stream[j] =
3599 (info->output_streams[i] >> (2 * j)) & 3;
3600 }
3601 }
3602
3603 if (ctx->shader->selector->so.num_outputs)
3604 si_llvm_emit_streamout(ctx, outputs, i, 0);
3605
3606 /* Export PrimitiveID. */
3607 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3608 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3609 outputs[i].semantic_index = 0;
3610 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3611 for (j = 1; j < 4; j++)
3612 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3613
3614 memset(outputs[i].vertex_stream, 0,
3615 sizeof(outputs[i].vertex_stream));
3616 i++;
3617 }
3618
3619 si_llvm_export_vs(ctx, outputs, i);
3620 FREE(outputs);
3621 }
3622
3623 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3624 {
3625 struct si_shader_context *ctx = si_shader_context(bld_base);
3626
3627 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3628 &ctx->outputs[0][0]);
3629 }
3630
3631 struct si_ps_exports {
3632 unsigned num;
3633 struct ac_export_args args[10];
3634 };
3635
3636 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3637 LLVMValueRef depth, LLVMValueRef stencil,
3638 LLVMValueRef samplemask, struct si_ps_exports *exp)
3639 {
3640 struct si_shader_context *ctx = si_shader_context(bld_base);
3641 struct ac_export_args args;
3642
3643 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3644
3645 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3646 }
3647
3648 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3649 LLVMValueRef *color, unsigned index,
3650 unsigned samplemask_param,
3651 bool is_last, struct si_ps_exports *exp)
3652 {
3653 struct si_shader_context *ctx = si_shader_context(bld_base);
3654 int i;
3655
3656 /* Clamp color */
3657 if (ctx->shader->key.part.ps.epilog.clamp_color)
3658 for (i = 0; i < 4; i++)
3659 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3660
3661 /* Alpha to one */
3662 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3663 color[3] = ctx->ac.f32_1;
3664
3665 /* Alpha test */
3666 if (index == 0 &&
3667 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3668 si_alpha_test(bld_base, color[3]);
3669
3670 /* Line & polygon smoothing */
3671 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3672 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3673 samplemask_param);
3674
3675 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3676 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3677 struct ac_export_args args[8];
3678 int c, last = -1;
3679
3680 /* Get the export arguments, also find out what the last one is. */
3681 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3682 si_llvm_init_export_args(ctx, color,
3683 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3684 if (args[c].enabled_channels)
3685 last = c;
3686 }
3687
3688 /* Emit all exports. */
3689 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3690 if (is_last && last == c) {
3691 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3692 args[c].done = 1; /* DONE bit */
3693 } else if (!args[c].enabled_channels)
3694 continue; /* unnecessary NULL export */
3695
3696 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3697 }
3698 } else {
3699 struct ac_export_args args;
3700
3701 /* Export */
3702 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3703 &args);
3704 if (is_last) {
3705 args.valid_mask = 1; /* whether the EXEC mask is valid */
3706 args.done = 1; /* DONE bit */
3707 } else if (!args.enabled_channels)
3708 return; /* unnecessary NULL export */
3709
3710 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3711 }
3712 }
3713
3714 static void si_emit_ps_exports(struct si_shader_context *ctx,
3715 struct si_ps_exports *exp)
3716 {
3717 for (unsigned i = 0; i < exp->num; i++)
3718 ac_build_export(&ctx->ac, &exp->args[i]);
3719 }
3720
3721 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3722 {
3723 struct si_shader_context *ctx = si_shader_context(bld_base);
3724 struct lp_build_context *base = &bld_base->base;
3725 struct ac_export_args args;
3726
3727 args.enabled_channels = 0x0; /* enabled channels */
3728 args.valid_mask = 1; /* whether the EXEC mask is valid */
3729 args.done = 1; /* DONE bit */
3730 args.target = V_008DFC_SQ_EXP_NULL;
3731 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
3732 args.out[0] = base->undef; /* R */
3733 args.out[1] = base->undef; /* G */
3734 args.out[2] = base->undef; /* B */
3735 args.out[3] = base->undef; /* A */
3736
3737 ac_build_export(&ctx->ac, &args);
3738 }
3739
3740 /**
3741 * Return PS outputs in this order:
3742 *
3743 * v[0:3] = color0.xyzw
3744 * v[4:7] = color1.xyzw
3745 * ...
3746 * vN+0 = Depth
3747 * vN+1 = Stencil
3748 * vN+2 = SampleMask
3749 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3750 *
3751 * The alpha-ref SGPR is returned via its original location.
3752 */
3753 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3754 unsigned max_outputs,
3755 LLVMValueRef *addrs)
3756 {
3757 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3758 struct si_shader *shader = ctx->shader;
3759 struct tgsi_shader_info *info = &shader->selector->info;
3760 LLVMBuilderRef builder = ctx->ac.builder;
3761 unsigned i, j, first_vgpr, vgpr;
3762
3763 LLVMValueRef color[8][4] = {};
3764 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3765 LLVMValueRef ret;
3766
3767 if (ctx->postponed_kill)
3768 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3769
3770 /* Read the output values. */
3771 for (i = 0; i < info->num_outputs; i++) {
3772 unsigned semantic_name = info->output_semantic_name[i];
3773 unsigned semantic_index = info->output_semantic_index[i];
3774
3775 switch (semantic_name) {
3776 case TGSI_SEMANTIC_COLOR:
3777 assert(semantic_index < 8);
3778 for (j = 0; j < 4; j++) {
3779 LLVMValueRef ptr = addrs[4 * i + j];
3780 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3781 color[semantic_index][j] = result;
3782 }
3783 break;
3784 case TGSI_SEMANTIC_POSITION:
3785 depth = LLVMBuildLoad(builder,
3786 addrs[4 * i + 2], "");
3787 break;
3788 case TGSI_SEMANTIC_STENCIL:
3789 stencil = LLVMBuildLoad(builder,
3790 addrs[4 * i + 1], "");
3791 break;
3792 case TGSI_SEMANTIC_SAMPLEMASK:
3793 samplemask = LLVMBuildLoad(builder,
3794 addrs[4 * i + 0], "");
3795 break;
3796 default:
3797 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3798 semantic_name);
3799 }
3800 }
3801
3802 /* Fill the return structure. */
3803 ret = ctx->return_value;
3804
3805 /* Set SGPRs. */
3806 ret = LLVMBuildInsertValue(builder, ret,
3807 ac_to_integer(&ctx->ac,
3808 LLVMGetParam(ctx->main_fn,
3809 SI_PARAM_ALPHA_REF)),
3810 SI_SGPR_ALPHA_REF, "");
3811
3812 /* Set VGPRs */
3813 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3814 for (i = 0; i < ARRAY_SIZE(color); i++) {
3815 if (!color[i][0])
3816 continue;
3817
3818 for (j = 0; j < 4; j++)
3819 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3820 }
3821 if (depth)
3822 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3823 if (stencil)
3824 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3825 if (samplemask)
3826 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3827
3828 /* Add the input sample mask for smoothing at the end. */
3829 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3830 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3831 ret = LLVMBuildInsertValue(builder, ret,
3832 LLVMGetParam(ctx->main_fn,
3833 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3834
3835 ctx->return_value = ret;
3836 }
3837
3838 static void membar_emit(
3839 const struct lp_build_tgsi_action *action,
3840 struct lp_build_tgsi_context *bld_base,
3841 struct lp_build_emit_data *emit_data)
3842 {
3843 struct si_shader_context *ctx = si_shader_context(bld_base);
3844 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3845 unsigned flags = LLVMConstIntGetZExtValue(src0);
3846 unsigned waitcnt = NOOP_WAITCNT;
3847
3848 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3849 waitcnt &= VM_CNT & LGKM_CNT;
3850
3851 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3852 TGSI_MEMBAR_SHADER_BUFFER |
3853 TGSI_MEMBAR_SHADER_IMAGE))
3854 waitcnt &= VM_CNT;
3855
3856 if (flags & TGSI_MEMBAR_SHARED)
3857 waitcnt &= LGKM_CNT;
3858
3859 if (waitcnt != NOOP_WAITCNT)
3860 ac_build_waitcnt(&ctx->ac, waitcnt);
3861 }
3862
3863 static void clock_emit(
3864 const struct lp_build_tgsi_action *action,
3865 struct lp_build_tgsi_context *bld_base,
3866 struct lp_build_emit_data *emit_data)
3867 {
3868 struct si_shader_context *ctx = si_shader_context(bld_base);
3869 LLVMValueRef tmp;
3870
3871 tmp = lp_build_intrinsic(ctx->ac.builder, "llvm.readcyclecounter",
3872 ctx->i64, NULL, 0, 0);
3873 tmp = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->v2i32, "");
3874
3875 emit_data->output[0] =
3876 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3877 emit_data->output[1] =
3878 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3879 }
3880
3881 static void si_llvm_emit_ddxy(
3882 const struct lp_build_tgsi_action *action,
3883 struct lp_build_tgsi_context *bld_base,
3884 struct lp_build_emit_data *emit_data)
3885 {
3886 struct si_shader_context *ctx = si_shader_context(bld_base);
3887 unsigned opcode = emit_data->info->opcode;
3888 LLVMValueRef val;
3889 int idx;
3890 unsigned mask;
3891
3892 if (opcode == TGSI_OPCODE_DDX_FINE)
3893 mask = AC_TID_MASK_LEFT;
3894 else if (opcode == TGSI_OPCODE_DDY_FINE)
3895 mask = AC_TID_MASK_TOP;
3896 else
3897 mask = AC_TID_MASK_TOP_LEFT;
3898
3899 /* for DDX we want to next X pixel, DDY next Y pixel. */
3900 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3901
3902 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3903 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3904 emit_data->output[emit_data->chan] = val;
3905 }
3906
3907 /*
3908 * this takes an I,J coordinate pair,
3909 * and works out the X and Y derivatives.
3910 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3911 */
3912 static LLVMValueRef si_llvm_emit_ddxy_interp(
3913 struct lp_build_tgsi_context *bld_base,
3914 LLVMValueRef interp_ij)
3915 {
3916 struct si_shader_context *ctx = si_shader_context(bld_base);
3917 LLVMValueRef result[4], a;
3918 unsigned i;
3919
3920 for (i = 0; i < 2; i++) {
3921 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
3922 LLVMConstInt(ctx->i32, i, 0), "");
3923 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
3924 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
3925 }
3926
3927 return lp_build_gather_values(&ctx->gallivm, result, 4);
3928 }
3929
3930 static void interp_fetch_args(
3931 struct lp_build_tgsi_context *bld_base,
3932 struct lp_build_emit_data *emit_data)
3933 {
3934 struct si_shader_context *ctx = si_shader_context(bld_base);
3935 const struct tgsi_full_instruction *inst = emit_data->inst;
3936
3937 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3938 /* offset is in second src, first two channels */
3939 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3940 emit_data->inst, 1,
3941 TGSI_CHAN_X);
3942 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3943 emit_data->inst, 1,
3944 TGSI_CHAN_Y);
3945 emit_data->arg_count = 2;
3946 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3947 LLVMValueRef sample_position;
3948 LLVMValueRef sample_id;
3949 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3950
3951 /* fetch sample ID, then fetch its sample position,
3952 * and place into first two channels.
3953 */
3954 sample_id = lp_build_emit_fetch(bld_base,
3955 emit_data->inst, 1, TGSI_CHAN_X);
3956 sample_id = ac_to_integer(&ctx->ac, sample_id);
3957
3958 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
3959 * Language 4.50 spec says about interpolateAtSample:
3960 *
3961 * "Returns the value of the input interpolant variable at
3962 * the location of sample number sample. If multisample
3963 * buffers are not available, the input variable will be
3964 * evaluated at the center of the pixel. If sample sample
3965 * does not exist, the position used to interpolate the
3966 * input variable is undefined."
3967 *
3968 * This means that sample_id values outside of the valid are
3969 * in fact valid input, and the usual mechanism for loading the
3970 * sample position doesn't work.
3971 */
3972 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
3973 LLVMValueRef center[4] = {
3974 LLVMConstReal(ctx->f32, 0.5),
3975 LLVMConstReal(ctx->f32, 0.5),
3976 ctx->ac.f32_0,
3977 ctx->ac.f32_0,
3978 };
3979
3980 sample_position = lp_build_gather_values(&ctx->gallivm, center, 4);
3981 } else {
3982 sample_position = load_sample_position(&ctx->abi, sample_id);
3983 }
3984
3985 emit_data->args[0] = LLVMBuildExtractElement(ctx->ac.builder,
3986 sample_position,
3987 ctx->i32_0, "");
3988
3989 emit_data->args[0] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[0], halfval, "");
3990 emit_data->args[1] = LLVMBuildExtractElement(ctx->ac.builder,
3991 sample_position,
3992 ctx->i32_1, "");
3993 emit_data->args[1] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[1], halfval, "");
3994 emit_data->arg_count = 2;
3995 }
3996 }
3997
3998 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3999 struct lp_build_tgsi_context *bld_base,
4000 struct lp_build_emit_data *emit_data)
4001 {
4002 struct si_shader_context *ctx = si_shader_context(bld_base);
4003 struct si_shader *shader = ctx->shader;
4004 const struct tgsi_shader_info *info = &shader->selector->info;
4005 LLVMValueRef interp_param;
4006 const struct tgsi_full_instruction *inst = emit_data->inst;
4007 const struct tgsi_full_src_register *input = &inst->Src[0];
4008 int input_base, input_array_size;
4009 int chan;
4010 int i;
4011 LLVMValueRef prim_mask = ctx->abi.prim_mask;
4012 LLVMValueRef array_idx;
4013 int interp_param_idx;
4014 unsigned interp;
4015 unsigned location;
4016
4017 assert(input->Register.File == TGSI_FILE_INPUT);
4018
4019 if (input->Register.Indirect) {
4020 unsigned array_id = input->Indirect.ArrayID;
4021
4022 if (array_id) {
4023 input_base = info->input_array_first[array_id];
4024 input_array_size = info->input_array_last[array_id] - input_base + 1;
4025 } else {
4026 input_base = inst->Src[0].Register.Index;
4027 input_array_size = info->num_inputs - input_base;
4028 }
4029
4030 array_idx = si_get_indirect_index(ctx, &input->Indirect,
4031 1, input->Register.Index - input_base);
4032 } else {
4033 input_base = inst->Src[0].Register.Index;
4034 input_array_size = 1;
4035 array_idx = ctx->i32_0;
4036 }
4037
4038 interp = shader->selector->info.input_interpolate[input_base];
4039
4040 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4041 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4042 location = TGSI_INTERPOLATE_LOC_CENTER;
4043 else
4044 location = TGSI_INTERPOLATE_LOC_CENTROID;
4045
4046 interp_param_idx = lookup_interp_param_index(interp, location);
4047 if (interp_param_idx == -1)
4048 return;
4049 else if (interp_param_idx)
4050 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4051 else
4052 interp_param = NULL;
4053
4054 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4055 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4056 LLVMValueRef ij_out[2];
4057 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
4058
4059 /*
4060 * take the I then J parameters, and the DDX/Y for it, and
4061 * calculate the IJ inputs for the interpolator.
4062 * temp1 = ddx * offset/sample.x + I;
4063 * interp_param.I = ddy * offset/sample.y + temp1;
4064 * temp1 = ddx * offset/sample.x + J;
4065 * interp_param.J = ddy * offset/sample.y + temp1;
4066 */
4067 for (i = 0; i < 2; i++) {
4068 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
4069 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
4070 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4071 ddxy_out, ix_ll, "");
4072 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4073 ddxy_out, iy_ll, "");
4074 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4075 interp_param, ix_ll, "");
4076 LLVMValueRef temp1, temp2;
4077
4078 interp_el = ac_to_float(&ctx->ac, interp_el);
4079
4080 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, emit_data->args[0], "");
4081
4082 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4083
4084 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, emit_data->args[1], "");
4085
4086 ij_out[i] = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4087 }
4088 interp_param = lp_build_gather_values(&ctx->gallivm, ij_out, 2);
4089 }
4090
4091 if (interp_param)
4092 interp_param = ac_to_float(&ctx->ac, interp_param);
4093
4094 for (chan = 0; chan < 4; chan++) {
4095 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
4096 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4097
4098 for (unsigned idx = 0; idx < input_array_size; ++idx) {
4099 LLVMValueRef v, i = NULL, j = NULL;
4100
4101 if (interp_param) {
4102 i = LLVMBuildExtractElement(
4103 ctx->ac.builder, interp_param, ctx->i32_0, "");
4104 j = LLVMBuildExtractElement(
4105 ctx->ac.builder, interp_param, ctx->i32_1, "");
4106 }
4107 v = si_build_fs_interp(ctx, input_base + idx, schan,
4108 prim_mask, i, j);
4109
4110 gather = LLVMBuildInsertElement(ctx->ac.builder,
4111 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
4112 }
4113
4114 emit_data->output[chan] = LLVMBuildExtractElement(
4115 ctx->ac.builder, gather, array_idx, "");
4116 }
4117 }
4118
4119 static void vote_all_emit(
4120 const struct lp_build_tgsi_action *action,
4121 struct lp_build_tgsi_context *bld_base,
4122 struct lp_build_emit_data *emit_data)
4123 {
4124 struct si_shader_context *ctx = si_shader_context(bld_base);
4125
4126 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
4127 emit_data->output[emit_data->chan] =
4128 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4129 }
4130
4131 static void vote_any_emit(
4132 const struct lp_build_tgsi_action *action,
4133 struct lp_build_tgsi_context *bld_base,
4134 struct lp_build_emit_data *emit_data)
4135 {
4136 struct si_shader_context *ctx = si_shader_context(bld_base);
4137
4138 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
4139 emit_data->output[emit_data->chan] =
4140 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4141 }
4142
4143 static void vote_eq_emit(
4144 const struct lp_build_tgsi_action *action,
4145 struct lp_build_tgsi_context *bld_base,
4146 struct lp_build_emit_data *emit_data)
4147 {
4148 struct si_shader_context *ctx = si_shader_context(bld_base);
4149
4150 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4151 emit_data->output[emit_data->chan] =
4152 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4153 }
4154
4155 static void ballot_emit(
4156 const struct lp_build_tgsi_action *action,
4157 struct lp_build_tgsi_context *bld_base,
4158 struct lp_build_emit_data *emit_data)
4159 {
4160 struct si_shader_context *ctx = si_shader_context(bld_base);
4161 LLVMBuilderRef builder = ctx->ac.builder;
4162 LLVMValueRef tmp;
4163
4164 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4165 tmp = ac_build_ballot(&ctx->ac, tmp);
4166 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4167
4168 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4169 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4170 }
4171
4172 static void read_invoc_fetch_args(
4173 struct lp_build_tgsi_context *bld_base,
4174 struct lp_build_emit_data *emit_data)
4175 {
4176 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4177 0, emit_data->src_chan);
4178
4179 /* Always read the source invocation (= lane) from the X channel. */
4180 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4181 1, TGSI_CHAN_X);
4182 emit_data->arg_count = 2;
4183 }
4184
4185 static void read_lane_emit(
4186 const struct lp_build_tgsi_action *action,
4187 struct lp_build_tgsi_context *bld_base,
4188 struct lp_build_emit_data *emit_data)
4189 {
4190 struct si_shader_context *ctx = si_shader_context(bld_base);
4191
4192 /* We currently have no other way to prevent LLVM from lifting the icmp
4193 * calls to a dominating basic block.
4194 */
4195 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4196
4197 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4198 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4199
4200 emit_data->output[emit_data->chan] =
4201 ac_build_intrinsic(&ctx->ac, action->intr_name,
4202 ctx->i32, emit_data->args, emit_data->arg_count,
4203 AC_FUNC_ATTR_READNONE |
4204 AC_FUNC_ATTR_CONVERGENT);
4205 }
4206
4207 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4208 struct lp_build_emit_data *emit_data)
4209 {
4210 struct si_shader_context *ctx = si_shader_context(bld_base);
4211 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4212 LLVMValueRef imm;
4213 unsigned stream;
4214
4215 assert(src0.File == TGSI_FILE_IMMEDIATE);
4216
4217 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4218 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4219 return stream;
4220 }
4221
4222 /* Emit one vertex from the geometry shader */
4223 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4224 unsigned stream,
4225 LLVMValueRef *addrs)
4226 {
4227 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4228 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4229 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
4230 struct si_shader *shader = ctx->shader;
4231 struct lp_build_if_state if_state;
4232 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4233 ctx->param_gs2vs_offset);
4234 LLVMValueRef gs_next_vertex;
4235 LLVMValueRef can_emit;
4236 unsigned chan, offset;
4237 int i;
4238
4239 /* Write vertex attribute values to GSVS ring */
4240 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4241 ctx->gs_next_vertex[stream],
4242 "");
4243
4244 /* If this thread has already emitted the declared maximum number of
4245 * vertices, skip the write: excessive vertex emissions are not
4246 * supposed to have any effect.
4247 *
4248 * If the shader has no writes to memory, kill it instead. This skips
4249 * further memory loads and may allow LLVM to skip to the end
4250 * altogether.
4251 */
4252 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4253 LLVMConstInt(ctx->i32,
4254 shader->selector->gs_max_out_vertices, 0), "");
4255
4256 bool use_kill = !info->writes_memory;
4257 if (use_kill) {
4258 ac_build_kill_if_false(&ctx->ac, can_emit);
4259 } else {
4260 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4261 }
4262
4263 offset = 0;
4264 for (i = 0; i < info->num_outputs; i++) {
4265 for (chan = 0; chan < 4; chan++) {
4266 if (!(info->output_usagemask[i] & (1 << chan)) ||
4267 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4268 continue;
4269
4270 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4271 LLVMValueRef voffset =
4272 LLVMConstInt(ctx->i32, offset *
4273 shader->selector->gs_max_out_vertices, 0);
4274 offset++;
4275
4276 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4277 voffset = lp_build_mul_imm(uint, voffset, 4);
4278
4279 out_val = ac_to_integer(&ctx->ac, out_val);
4280
4281 ac_build_buffer_store_dword(&ctx->ac,
4282 ctx->gsvs_ring[stream],
4283 out_val, 1,
4284 voffset, soffset, 0,
4285 1, 1, true, true);
4286 }
4287 }
4288
4289 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4290 ctx->i32_1);
4291
4292 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4293
4294 /* Signal vertex emission */
4295 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4296 si_get_gs_wave_id(ctx));
4297 if (!use_kill)
4298 lp_build_endif(&if_state);
4299 }
4300
4301 /* Emit one vertex from the geometry shader */
4302 static void si_tgsi_emit_vertex(
4303 const struct lp_build_tgsi_action *action,
4304 struct lp_build_tgsi_context *bld_base,
4305 struct lp_build_emit_data *emit_data)
4306 {
4307 struct si_shader_context *ctx = si_shader_context(bld_base);
4308 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4309
4310 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4311 }
4312
4313 /* Cut one primitive from the geometry shader */
4314 static void si_llvm_emit_primitive(struct ac_shader_abi *abi,
4315 unsigned stream)
4316 {
4317 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4318
4319 /* Signal primitive cut */
4320 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4321 si_get_gs_wave_id(ctx));
4322 }
4323
4324 /* Cut one primitive from the geometry shader */
4325 static void si_tgsi_emit_primitive(
4326 const struct lp_build_tgsi_action *action,
4327 struct lp_build_tgsi_context *bld_base,
4328 struct lp_build_emit_data *emit_data)
4329 {
4330 struct si_shader_context *ctx = si_shader_context(bld_base);
4331
4332 si_llvm_emit_primitive(&ctx->abi, si_llvm_get_stream(bld_base, emit_data));
4333 }
4334
4335 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4336 struct lp_build_tgsi_context *bld_base,
4337 struct lp_build_emit_data *emit_data)
4338 {
4339 struct si_shader_context *ctx = si_shader_context(bld_base);
4340
4341 /* SI only (thanks to a hw bug workaround):
4342 * The real barrier instruction isn’t needed, because an entire patch
4343 * always fits into a single wave.
4344 */
4345 if (ctx->screen->info.chip_class == SI &&
4346 ctx->type == PIPE_SHADER_TESS_CTRL) {
4347 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
4348 return;
4349 }
4350
4351 lp_build_intrinsic(ctx->ac.builder,
4352 "llvm.amdgcn.s.barrier",
4353 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
4354 }
4355
4356 static const struct lp_build_tgsi_action interp_action = {
4357 .fetch_args = interp_fetch_args,
4358 .emit = build_interp_intrinsic,
4359 };
4360
4361 static void si_create_function(struct si_shader_context *ctx,
4362 const char *name,
4363 LLVMTypeRef *returns, unsigned num_returns,
4364 struct si_function_info *fninfo,
4365 unsigned max_workgroup_size)
4366 {
4367 int i;
4368
4369 si_llvm_create_func(ctx, name, returns, num_returns,
4370 fninfo->types, fninfo->num_params);
4371 ctx->return_value = LLVMGetUndef(ctx->return_type);
4372
4373 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4374 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4375
4376 /* The combination of:
4377 * - noalias
4378 * - dereferenceable
4379 * - invariant.load
4380 * allows the optimization passes to move loads and reduces
4381 * SGPR spilling significantly.
4382 */
4383 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
4384
4385 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4386 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
4387 ac_add_attr_dereferenceable(P, UINT64_MAX);
4388 }
4389 }
4390
4391 for (i = 0; i < fninfo->num_params; ++i) {
4392 if (fninfo->assign[i])
4393 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4394 }
4395
4396 if (max_workgroup_size) {
4397 si_llvm_add_attribute(ctx->main_fn, "amdgpu-max-work-group-size",
4398 max_workgroup_size);
4399 }
4400 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4401 "no-signed-zeros-fp-math",
4402 "true");
4403
4404 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4405 /* These were copied from some LLVM test. */
4406 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4407 "less-precise-fpmad",
4408 "true");
4409 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4410 "no-infs-fp-math",
4411 "true");
4412 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4413 "no-nans-fp-math",
4414 "true");
4415 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4416 "unsafe-fp-math",
4417 "true");
4418 }
4419 }
4420
4421 static void declare_streamout_params(struct si_shader_context *ctx,
4422 struct pipe_stream_output_info *so,
4423 struct si_function_info *fninfo)
4424 {
4425 int i;
4426
4427 /* Streamout SGPRs. */
4428 if (so->num_outputs) {
4429 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4430 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4431 else
4432 ctx->param_streamout_config = fninfo->num_params - 1;
4433
4434 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4435 }
4436 /* A streamout buffer offset is loaded if the stride is non-zero. */
4437 for (i = 0; i < 4; i++) {
4438 if (!so->stride[i])
4439 continue;
4440
4441 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4442 }
4443 }
4444
4445 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4446 {
4447 switch (shader->selector->type) {
4448 case PIPE_SHADER_TESS_CTRL:
4449 /* Return this so that LLVM doesn't remove s_barrier
4450 * instructions on chips where we use s_barrier. */
4451 return shader->selector->screen->info.chip_class >= CIK ? 128 : 64;
4452
4453 case PIPE_SHADER_GEOMETRY:
4454 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4455
4456 case PIPE_SHADER_COMPUTE:
4457 break; /* see below */
4458
4459 default:
4460 return 0;
4461 }
4462
4463 const unsigned *properties = shader->selector->info.properties;
4464 unsigned max_work_group_size =
4465 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4466 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4467 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4468
4469 if (!max_work_group_size) {
4470 /* This is a variable group size compute shader,
4471 * compile it for the maximum possible group size.
4472 */
4473 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4474 }
4475 return max_work_group_size;
4476 }
4477
4478 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4479 struct si_function_info *fninfo,
4480 bool assign_params)
4481 {
4482 LLVMTypeRef const_shader_buf_type;
4483
4484 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4485 ctx->shader->selector->info.shader_buffers_declared == 0)
4486 const_shader_buf_type = ctx->f32;
4487 else
4488 const_shader_buf_type = ctx->v4i32;
4489
4490 unsigned const_and_shader_buffers =
4491 add_arg(fninfo, ARG_SGPR,
4492 ac_array_in_const_addr_space(const_shader_buf_type));
4493
4494 unsigned samplers_and_images =
4495 add_arg(fninfo, ARG_SGPR,
4496 ac_array_in_const_addr_space(ctx->v8i32));
4497
4498 if (assign_params) {
4499 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4500 ctx->param_samplers_and_images = samplers_and_images;
4501 }
4502 }
4503
4504 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4505 struct si_function_info *fninfo)
4506 {
4507 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4508 ac_array_in_const_addr_space(ctx->v4i32));
4509 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4510 ac_array_in_const_addr_space(ctx->v8i32));
4511 }
4512
4513 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4514 struct si_function_info *fninfo)
4515 {
4516 ctx->param_vertex_buffers = add_arg(fninfo, ARG_SGPR,
4517 ac_array_in_const_addr_space(ctx->v4i32));
4518 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4519 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4520 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4521 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4522 }
4523
4524 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4525 struct si_function_info *fninfo,
4526 unsigned *num_prolog_vgprs)
4527 {
4528 struct si_shader *shader = ctx->shader;
4529
4530 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4531 if (shader->key.as_ls) {
4532 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4533 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4534 } else {
4535 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4536 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4537 }
4538 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4539
4540 if (!shader->is_gs_copy_shader) {
4541 /* Vertex load indices. */
4542 ctx->param_vertex_index0 = fninfo->num_params;
4543 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4544 add_arg(fninfo, ARG_VGPR, ctx->i32);
4545 *num_prolog_vgprs += shader->selector->info.num_inputs;
4546 }
4547 }
4548
4549 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4550 struct si_function_info *fninfo)
4551 {
4552 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4553 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4554 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4555 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
4556 }
4557
4558 enum {
4559 /* Convenient merged shader definitions. */
4560 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4561 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4562 };
4563
4564 static void create_function(struct si_shader_context *ctx)
4565 {
4566 struct si_shader *shader = ctx->shader;
4567 struct si_function_info fninfo;
4568 LLVMTypeRef returns[16+32*4];
4569 unsigned i, num_return_sgprs;
4570 unsigned num_returns = 0;
4571 unsigned num_prolog_vgprs = 0;
4572 unsigned type = ctx->type;
4573 unsigned vs_blit_property =
4574 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4575
4576 si_init_function_info(&fninfo);
4577
4578 /* Set MERGED shaders. */
4579 if (ctx->screen->info.chip_class >= GFX9) {
4580 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4581 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4582 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4583 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4584 }
4585
4586 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4587
4588 switch (type) {
4589 case PIPE_SHADER_VERTEX:
4590 declare_global_desc_pointers(ctx, &fninfo);
4591
4592 if (vs_blit_property) {
4593 ctx->param_vs_blit_inputs = fninfo.num_params;
4594 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4595 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4596 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* depth */
4597
4598 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4599 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color0 */
4600 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color1 */
4601 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color2 */
4602 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color3 */
4603 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4604 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4605 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4606 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4607 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4608 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4609 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4610 }
4611
4612 /* VGPRs */
4613 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4614 break;
4615 }
4616
4617 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4618 declare_vs_specific_input_sgprs(ctx, &fninfo);
4619
4620 if (shader->key.as_es) {
4621 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4622 } else if (shader->key.as_ls) {
4623 /* no extra parameters */
4624 } else {
4625 if (shader->is_gs_copy_shader) {
4626 fninfo.num_params = ctx->param_rw_buffers + 1;
4627 fninfo.num_sgpr_params = fninfo.num_params;
4628 }
4629
4630 /* The locations of the other parameters are assigned dynamically. */
4631 declare_streamout_params(ctx, &shader->selector->so,
4632 &fninfo);
4633 }
4634
4635 /* VGPRs */
4636 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4637 break;
4638
4639 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4640 declare_global_desc_pointers(ctx, &fninfo);
4641 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4642 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4643 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4644 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4645 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4646 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4647 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4648 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4649 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4650
4651 /* VGPRs */
4652 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4653 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4654
4655 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4656 * placed after the user SGPRs.
4657 */
4658 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4659 returns[num_returns++] = ctx->i32; /* SGPRs */
4660 for (i = 0; i < 11; i++)
4661 returns[num_returns++] = ctx->f32; /* VGPRs */
4662 break;
4663
4664 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4665 /* Merged stages have 8 system SGPRs at the beginning. */
4666 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_LO_HS */
4667 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_HI_HS */
4668 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4669 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4670 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4671 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4672 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4673 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4674
4675 declare_global_desc_pointers(ctx, &fninfo);
4676 declare_per_stage_desc_pointers(ctx, &fninfo,
4677 ctx->type == PIPE_SHADER_VERTEX);
4678 declare_vs_specific_input_sgprs(ctx, &fninfo);
4679
4680 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4681 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4682 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4683 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4684 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4685 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4686
4687 declare_per_stage_desc_pointers(ctx, &fninfo,
4688 ctx->type == PIPE_SHADER_TESS_CTRL);
4689
4690 /* VGPRs (first TCS, then VS) */
4691 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4692 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4693
4694 if (ctx->type == PIPE_SHADER_VERTEX) {
4695 declare_vs_input_vgprs(ctx, &fninfo,
4696 &num_prolog_vgprs);
4697
4698 /* LS return values are inputs to the TCS main shader part. */
4699 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4700 returns[num_returns++] = ctx->i32; /* SGPRs */
4701 for (i = 0; i < 2; i++)
4702 returns[num_returns++] = ctx->f32; /* VGPRs */
4703 } else {
4704 /* TCS return values are inputs to the TCS epilog.
4705 *
4706 * param_tcs_offchip_offset, param_tcs_factor_offset,
4707 * param_tcs_offchip_layout, and param_rw_buffers
4708 * should be passed to the epilog.
4709 */
4710 for (i = 0; i <= 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K; i++)
4711 returns[num_returns++] = ctx->i32; /* SGPRs */
4712 for (i = 0; i < 11; i++)
4713 returns[num_returns++] = ctx->f32; /* VGPRs */
4714 }
4715 break;
4716
4717 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4718 /* Merged stages have 8 system SGPRs at the beginning. */
4719 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_LO_GS) */
4720 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_HI_GS) */
4721 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4722 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4723 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4724 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4725 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4726 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4727
4728 declare_global_desc_pointers(ctx, &fninfo);
4729 declare_per_stage_desc_pointers(ctx, &fninfo,
4730 (ctx->type == PIPE_SHADER_VERTEX ||
4731 ctx->type == PIPE_SHADER_TESS_EVAL));
4732 if (ctx->type == PIPE_SHADER_VERTEX) {
4733 declare_vs_specific_input_sgprs(ctx, &fninfo);
4734 } else {
4735 /* TESS_EVAL (and also GEOMETRY):
4736 * Declare as many input SGPRs as the VS has. */
4737 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4738 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4739 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4740 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4741 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4742 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4743 }
4744
4745 declare_per_stage_desc_pointers(ctx, &fninfo,
4746 ctx->type == PIPE_SHADER_GEOMETRY);
4747
4748 /* VGPRs (first GS, then VS/TES) */
4749 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4750 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4751 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4752 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4753 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4754
4755 if (ctx->type == PIPE_SHADER_VERTEX) {
4756 declare_vs_input_vgprs(ctx, &fninfo,
4757 &num_prolog_vgprs);
4758 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4759 declare_tes_input_vgprs(ctx, &fninfo);
4760 }
4761
4762 if (ctx->type == PIPE_SHADER_VERTEX ||
4763 ctx->type == PIPE_SHADER_TESS_EVAL) {
4764 /* ES return values are inputs to GS. */
4765 for (i = 0; i < 8 + GFX9_GS_NUM_USER_SGPR; i++)
4766 returns[num_returns++] = ctx->i32; /* SGPRs */
4767 for (i = 0; i < 5; i++)
4768 returns[num_returns++] = ctx->f32; /* VGPRs */
4769 }
4770 break;
4771
4772 case PIPE_SHADER_TESS_EVAL:
4773 declare_global_desc_pointers(ctx, &fninfo);
4774 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4775 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4776 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4777
4778 if (shader->key.as_es) {
4779 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4780 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4781 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4782 } else {
4783 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4784 declare_streamout_params(ctx, &shader->selector->so,
4785 &fninfo);
4786 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4787 }
4788
4789 /* VGPRs */
4790 declare_tes_input_vgprs(ctx, &fninfo);
4791 break;
4792
4793 case PIPE_SHADER_GEOMETRY:
4794 declare_global_desc_pointers(ctx, &fninfo);
4795 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4796 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4797 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4798
4799 /* VGPRs */
4800 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4801 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4802 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4803 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4804 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4805 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4806 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4807 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4808 break;
4809
4810 case PIPE_SHADER_FRAGMENT:
4811 declare_global_desc_pointers(ctx, &fninfo);
4812 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4813 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4814 add_arg_assign_checked(&fninfo, ARG_SGPR, ctx->i32,
4815 &ctx->abi.prim_mask, SI_PARAM_PRIM_MASK);
4816
4817 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4818 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4819 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4820 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4821 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4822 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4823 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4824 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4825 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4826 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4827 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4828 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4829 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4830 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4831 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4832 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4833 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4834 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4835 shader->info.face_vgpr_index = 20;
4836 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4837 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4838 shader->info.ancillary_vgpr_index = 21;
4839 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4840 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4841 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4842
4843 /* Color inputs from the prolog. */
4844 if (shader->selector->info.colors_read) {
4845 unsigned num_color_elements =
4846 util_bitcount(shader->selector->info.colors_read);
4847
4848 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4849 for (i = 0; i < num_color_elements; i++)
4850 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4851
4852 num_prolog_vgprs += num_color_elements;
4853 }
4854
4855 /* Outputs for the epilog. */
4856 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4857 num_returns =
4858 num_return_sgprs +
4859 util_bitcount(shader->selector->info.colors_written) * 4 +
4860 shader->selector->info.writes_z +
4861 shader->selector->info.writes_stencil +
4862 shader->selector->info.writes_samplemask +
4863 1 /* SampleMaskIn */;
4864
4865 num_returns = MAX2(num_returns,
4866 num_return_sgprs +
4867 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4868
4869 for (i = 0; i < num_return_sgprs; i++)
4870 returns[i] = ctx->i32;
4871 for (; i < num_returns; i++)
4872 returns[i] = ctx->f32;
4873 break;
4874
4875 case PIPE_SHADER_COMPUTE:
4876 declare_global_desc_pointers(ctx, &fninfo);
4877 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4878 if (shader->selector->info.uses_grid_size)
4879 ctx->param_grid_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4880 if (shader->selector->info.uses_block_size)
4881 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4882
4883 for (i = 0; i < 3; i++) {
4884 ctx->abi.workgroup_ids[i] = NULL;
4885 if (shader->selector->info.uses_block_id[i])
4886 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->abi.workgroup_ids[i]);
4887 }
4888
4889 ctx->param_thread_id = add_arg(&fninfo, ARG_VGPR, v3i32);
4890 break;
4891 default:
4892 assert(0 && "unimplemented shader");
4893 return;
4894 }
4895
4896 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4897 si_get_max_workgroup_size(shader));
4898
4899 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4900 if (ctx->type == PIPE_SHADER_FRAGMENT &&
4901 ctx->separate_prolog) {
4902 si_llvm_add_attribute(ctx->main_fn,
4903 "InitialPSInputAddr",
4904 S_0286D0_PERSP_SAMPLE_ENA(1) |
4905 S_0286D0_PERSP_CENTER_ENA(1) |
4906 S_0286D0_PERSP_CENTROID_ENA(1) |
4907 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4908 S_0286D0_LINEAR_CENTER_ENA(1) |
4909 S_0286D0_LINEAR_CENTROID_ENA(1) |
4910 S_0286D0_FRONT_FACE_ENA(1) |
4911 S_0286D0_ANCILLARY_ENA(1) |
4912 S_0286D0_POS_FIXED_PT_ENA(1));
4913 }
4914
4915 shader->info.num_input_sgprs = 0;
4916 shader->info.num_input_vgprs = 0;
4917
4918 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4919 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
4920
4921 for (; i < fninfo.num_params; ++i)
4922 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
4923
4924 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4925 shader->info.num_input_vgprs -= num_prolog_vgprs;
4926
4927 if (shader->key.as_ls ||
4928 ctx->type == PIPE_SHADER_TESS_CTRL ||
4929 /* GFX9 has the ESGS ring buffer in LDS. */
4930 type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY)
4931 ac_declare_lds_as_pointer(&ctx->ac);
4932 }
4933
4934 /**
4935 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4936 * for later use.
4937 */
4938 static void preload_ring_buffers(struct si_shader_context *ctx)
4939 {
4940 LLVMBuilderRef builder = ctx->ac.builder;
4941
4942 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
4943 ctx->param_rw_buffers);
4944
4945 if (ctx->screen->info.chip_class <= VI &&
4946 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
4947 unsigned ring =
4948 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
4949 : SI_ES_RING_ESGS;
4950 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
4951
4952 ctx->esgs_ring =
4953 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4954 }
4955
4956 if (ctx->shader->is_gs_copy_shader) {
4957 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4958
4959 ctx->gsvs_ring[0] =
4960 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4961 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
4962 const struct si_shader_selector *sel = ctx->shader->selector;
4963 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4964 LLVMValueRef base_ring;
4965
4966 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4967
4968 /* The conceptual layout of the GSVS ring is
4969 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4970 * but the real memory layout is swizzled across
4971 * threads:
4972 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4973 * t16v0c0 ..
4974 * Override the buffer descriptor accordingly.
4975 */
4976 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
4977 uint64_t stream_offset = 0;
4978
4979 for (unsigned stream = 0; stream < 4; ++stream) {
4980 unsigned num_components;
4981 unsigned stride;
4982 unsigned num_records;
4983 LLVMValueRef ring, tmp;
4984
4985 num_components = sel->info.num_stream_output_components[stream];
4986 if (!num_components)
4987 continue;
4988
4989 stride = 4 * num_components * sel->gs_max_out_vertices;
4990
4991 /* Limit on the stride field for <= CIK. */
4992 assert(stride < (1 << 14));
4993
4994 num_records = 64;
4995
4996 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
4997 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
4998 tmp = LLVMBuildAdd(builder, tmp,
4999 LLVMConstInt(ctx->i64,
5000 stream_offset, 0), "");
5001 stream_offset += stride * 64;
5002
5003 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5004 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5005 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5006 tmp = LLVMBuildOr(builder, tmp,
5007 LLVMConstInt(ctx->i32,
5008 S_008F04_STRIDE(stride) |
5009 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5010 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5011 ring = LLVMBuildInsertElement(builder, ring,
5012 LLVMConstInt(ctx->i32, num_records, 0),
5013 LLVMConstInt(ctx->i32, 2, 0), "");
5014 ring = LLVMBuildInsertElement(builder, ring,
5015 LLVMConstInt(ctx->i32,
5016 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5017 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5018 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5019 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5020 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5021 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5022 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5023 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5024 S_008F0C_ADD_TID_ENABLE(1),
5025 0),
5026 LLVMConstInt(ctx->i32, 3, 0), "");
5027
5028 ctx->gsvs_ring[stream] = ring;
5029 }
5030 }
5031 }
5032
5033 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5034 LLVMValueRef param_rw_buffers,
5035 unsigned param_pos_fixed_pt)
5036 {
5037 LLVMBuilderRef builder = ctx->ac.builder;
5038 LLVMValueRef slot, desc, offset, row, bit, address[2];
5039
5040 /* Use the fixed-point gl_FragCoord input.
5041 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5042 * per coordinate to get the repeating effect.
5043 */
5044 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5045 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5046
5047 /* Load the buffer descriptor. */
5048 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5049 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
5050
5051 /* The stipple pattern is 32x32, each row has 32 bits. */
5052 offset = LLVMBuildMul(builder, address[1],
5053 LLVMConstInt(ctx->i32, 4, 0), "");
5054 row = buffer_load_const(ctx, desc, offset);
5055 row = ac_to_integer(&ctx->ac, row);
5056 bit = LLVMBuildLShr(builder, row, address[0], "");
5057 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5058 ac_build_kill_if_false(&ctx->ac, bit);
5059 }
5060
5061 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5062 struct si_shader_config *conf,
5063 unsigned symbol_offset)
5064 {
5065 unsigned i;
5066 const unsigned char *config =
5067 ac_shader_binary_config_start(binary, symbol_offset);
5068 bool really_needs_scratch = false;
5069
5070 /* LLVM adds SGPR spills to the scratch size.
5071 * Find out if we really need the scratch buffer.
5072 */
5073 for (i = 0; i < binary->reloc_count; i++) {
5074 const struct ac_shader_reloc *reloc = &binary->relocs[i];
5075
5076 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5077 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5078 really_needs_scratch = true;
5079 break;
5080 }
5081 }
5082
5083 /* XXX: We may be able to emit some of these values directly rather than
5084 * extracting fields to be emitted later.
5085 */
5086
5087 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5088 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5089 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5090 switch (reg) {
5091 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5092 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5093 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5094 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
5095 case R_00B848_COMPUTE_PGM_RSRC1:
5096 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5097 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5098 conf->float_mode = G_00B028_FLOAT_MODE(value);
5099 conf->rsrc1 = value;
5100 break;
5101 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5102 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5103 break;
5104 case R_00B84C_COMPUTE_PGM_RSRC2:
5105 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5106 conf->rsrc2 = value;
5107 break;
5108 case R_0286CC_SPI_PS_INPUT_ENA:
5109 conf->spi_ps_input_ena = value;
5110 break;
5111 case R_0286D0_SPI_PS_INPUT_ADDR:
5112 conf->spi_ps_input_addr = value;
5113 break;
5114 case R_0286E8_SPI_TMPRING_SIZE:
5115 case R_00B860_COMPUTE_TMPRING_SIZE:
5116 /* WAVESIZE is in units of 256 dwords. */
5117 if (really_needs_scratch)
5118 conf->scratch_bytes_per_wave =
5119 G_00B860_WAVESIZE(value) * 256 * 4;
5120 break;
5121 case 0x4: /* SPILLED_SGPRS */
5122 conf->spilled_sgprs = value;
5123 break;
5124 case 0x8: /* SPILLED_VGPRS */
5125 conf->spilled_vgprs = value;
5126 break;
5127 default:
5128 {
5129 static bool printed;
5130
5131 if (!printed) {
5132 fprintf(stderr, "Warning: LLVM emitted unknown "
5133 "config register: 0x%x\n", reg);
5134 printed = true;
5135 }
5136 }
5137 break;
5138 }
5139 }
5140
5141 if (!conf->spi_ps_input_addr)
5142 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5143 }
5144
5145 void si_shader_apply_scratch_relocs(struct si_shader *shader,
5146 uint64_t scratch_va)
5147 {
5148 unsigned i;
5149 uint32_t scratch_rsrc_dword0 = scratch_va;
5150 uint32_t scratch_rsrc_dword1 =
5151 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5152
5153 /* Enable scratch coalescing. */
5154 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5155
5156 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5157 const struct ac_shader_reloc *reloc =
5158 &shader->binary.relocs[i];
5159 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5160 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5161 &scratch_rsrc_dword0, 4);
5162 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5163 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5164 &scratch_rsrc_dword1, 4);
5165 }
5166 }
5167 }
5168
5169 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
5170 {
5171 unsigned size = shader->binary.code_size;
5172
5173 if (shader->prolog)
5174 size += shader->prolog->binary.code_size;
5175 if (shader->previous_stage)
5176 size += shader->previous_stage->binary.code_size;
5177 if (shader->prolog2)
5178 size += shader->prolog2->binary.code_size;
5179 if (shader->epilog)
5180 size += shader->epilog->binary.code_size;
5181 return size;
5182 }
5183
5184 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5185 {
5186 const struct ac_shader_binary *prolog =
5187 shader->prolog ? &shader->prolog->binary : NULL;
5188 const struct ac_shader_binary *previous_stage =
5189 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5190 const struct ac_shader_binary *prolog2 =
5191 shader->prolog2 ? &shader->prolog2->binary : NULL;
5192 const struct ac_shader_binary *epilog =
5193 shader->epilog ? &shader->epilog->binary : NULL;
5194 const struct ac_shader_binary *mainb = &shader->binary;
5195 unsigned bo_size = si_get_shader_binary_size(shader) +
5196 (!epilog ? mainb->rodata_size : 0);
5197 unsigned char *ptr;
5198
5199 assert(!prolog || !prolog->rodata_size);
5200 assert(!previous_stage || !previous_stage->rodata_size);
5201 assert(!prolog2 || !prolog2->rodata_size);
5202 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5203 !mainb->rodata_size);
5204 assert(!epilog || !epilog->rodata_size);
5205
5206 r600_resource_reference(&shader->bo, NULL);
5207 shader->bo = (struct r600_resource*)
5208 si_aligned_buffer_create(&sscreen->b,
5209 sscreen->cpdma_prefetch_writes_memory ?
5210 0 : R600_RESOURCE_FLAG_READ_ONLY,
5211 PIPE_USAGE_IMMUTABLE,
5212 align(bo_size, SI_CPDMA_ALIGNMENT),
5213 256);
5214 if (!shader->bo)
5215 return -ENOMEM;
5216
5217 /* Upload. */
5218 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5219 PIPE_TRANSFER_READ_WRITE |
5220 PIPE_TRANSFER_UNSYNCHRONIZED);
5221
5222 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5223 * endian-independent. */
5224 if (prolog) {
5225 memcpy(ptr, prolog->code, prolog->code_size);
5226 ptr += prolog->code_size;
5227 }
5228 if (previous_stage) {
5229 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5230 ptr += previous_stage->code_size;
5231 }
5232 if (prolog2) {
5233 memcpy(ptr, prolog2->code, prolog2->code_size);
5234 ptr += prolog2->code_size;
5235 }
5236
5237 memcpy(ptr, mainb->code, mainb->code_size);
5238 ptr += mainb->code_size;
5239
5240 if (epilog)
5241 memcpy(ptr, epilog->code, epilog->code_size);
5242 else if (mainb->rodata_size > 0)
5243 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5244
5245 sscreen->ws->buffer_unmap(shader->bo->buf);
5246 return 0;
5247 }
5248
5249 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5250 struct pipe_debug_callback *debug,
5251 const char *name, FILE *file)
5252 {
5253 char *line, *p;
5254 unsigned i, count;
5255
5256 if (binary->disasm_string) {
5257 fprintf(file, "Shader %s disassembly:\n", name);
5258 fprintf(file, "%s", binary->disasm_string);
5259
5260 if (debug && debug->debug_message) {
5261 /* Very long debug messages are cut off, so send the
5262 * disassembly one line at a time. This causes more
5263 * overhead, but on the plus side it simplifies
5264 * parsing of resulting logs.
5265 */
5266 pipe_debug_message(debug, SHADER_INFO,
5267 "Shader Disassembly Begin");
5268
5269 line = binary->disasm_string;
5270 while (*line) {
5271 p = util_strchrnul(line, '\n');
5272 count = p - line;
5273
5274 if (count) {
5275 pipe_debug_message(debug, SHADER_INFO,
5276 "%.*s", count, line);
5277 }
5278
5279 if (!*p)
5280 break;
5281 line = p + 1;
5282 }
5283
5284 pipe_debug_message(debug, SHADER_INFO,
5285 "Shader Disassembly End");
5286 }
5287 } else {
5288 fprintf(file, "Shader %s binary:\n", name);
5289 for (i = 0; i < binary->code_size; i += 4) {
5290 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5291 binary->code[i + 3], binary->code[i + 2],
5292 binary->code[i + 1], binary->code[i]);
5293 }
5294 }
5295 }
5296
5297 static void si_calculate_max_simd_waves(struct si_shader *shader)
5298 {
5299 struct si_screen *sscreen = shader->selector->screen;
5300 struct si_shader_config *conf = &shader->config;
5301 unsigned num_inputs = shader->selector->info.num_inputs;
5302 unsigned lds_increment = sscreen->info.chip_class >= CIK ? 512 : 256;
5303 unsigned lds_per_wave = 0;
5304 unsigned max_simd_waves;
5305
5306 switch (sscreen->info.family) {
5307 /* These always have 8 waves: */
5308 case CHIP_POLARIS10:
5309 case CHIP_POLARIS11:
5310 case CHIP_POLARIS12:
5311 max_simd_waves = 8;
5312 break;
5313 default:
5314 max_simd_waves = 10;
5315 }
5316
5317 /* Compute LDS usage for PS. */
5318 switch (shader->selector->type) {
5319 case PIPE_SHADER_FRAGMENT:
5320 /* The minimum usage per wave is (num_inputs * 48). The maximum
5321 * usage is (num_inputs * 48 * 16).
5322 * We can get anything in between and it varies between waves.
5323 *
5324 * The 48 bytes per input for a single primitive is equal to
5325 * 4 bytes/component * 4 components/input * 3 points.
5326 *
5327 * Other stages don't know the size at compile time or don't
5328 * allocate LDS per wave, but instead they do it per thread group.
5329 */
5330 lds_per_wave = conf->lds_size * lds_increment +
5331 align(num_inputs * 48, lds_increment);
5332 break;
5333 case PIPE_SHADER_COMPUTE:
5334 if (shader->selector) {
5335 unsigned max_workgroup_size =
5336 si_get_max_workgroup_size(shader);
5337 lds_per_wave = (conf->lds_size * lds_increment) /
5338 DIV_ROUND_UP(max_workgroup_size, 64);
5339 }
5340 break;
5341 }
5342
5343 /* Compute the per-SIMD wave counts. */
5344 if (conf->num_sgprs) {
5345 if (sscreen->info.chip_class >= VI)
5346 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5347 else
5348 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5349 }
5350
5351 if (conf->num_vgprs)
5352 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5353
5354 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5355 * 16KB makes some SIMDs unoccupied). */
5356 if (lds_per_wave)
5357 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5358
5359 conf->max_simd_waves = max_simd_waves;
5360 }
5361
5362 void si_shader_dump_stats_for_shader_db(const struct si_shader *shader,
5363 struct pipe_debug_callback *debug)
5364 {
5365 const struct si_shader_config *conf = &shader->config;
5366
5367 pipe_debug_message(debug, SHADER_INFO,
5368 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5369 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5370 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5371 conf->num_sgprs, conf->num_vgprs,
5372 si_get_shader_binary_size(shader),
5373 conf->lds_size, conf->scratch_bytes_per_wave,
5374 conf->max_simd_waves, conf->spilled_sgprs,
5375 conf->spilled_vgprs, conf->private_mem_vgprs);
5376 }
5377
5378 static void si_shader_dump_stats(struct si_screen *sscreen,
5379 const struct si_shader *shader,
5380 unsigned processor,
5381 FILE *file,
5382 bool check_debug_option)
5383 {
5384 const struct si_shader_config *conf = &shader->config;
5385
5386 if (!check_debug_option ||
5387 si_can_dump_shader(sscreen, processor)) {
5388 if (processor == PIPE_SHADER_FRAGMENT) {
5389 fprintf(file, "*** SHADER CONFIG ***\n"
5390 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5391 "SPI_PS_INPUT_ENA = 0x%04x\n",
5392 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5393 }
5394
5395 fprintf(file, "*** SHADER STATS ***\n"
5396 "SGPRS: %d\n"
5397 "VGPRS: %d\n"
5398 "Spilled SGPRs: %d\n"
5399 "Spilled VGPRs: %d\n"
5400 "Private memory VGPRs: %d\n"
5401 "Code Size: %d bytes\n"
5402 "LDS: %d blocks\n"
5403 "Scratch: %d bytes per wave\n"
5404 "Max Waves: %d\n"
5405 "********************\n\n\n",
5406 conf->num_sgprs, conf->num_vgprs,
5407 conf->spilled_sgprs, conf->spilled_vgprs,
5408 conf->private_mem_vgprs,
5409 si_get_shader_binary_size(shader),
5410 conf->lds_size, conf->scratch_bytes_per_wave,
5411 conf->max_simd_waves);
5412 }
5413 }
5414
5415 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5416 {
5417 switch (processor) {
5418 case PIPE_SHADER_VERTEX:
5419 if (shader->key.as_es)
5420 return "Vertex Shader as ES";
5421 else if (shader->key.as_ls)
5422 return "Vertex Shader as LS";
5423 else
5424 return "Vertex Shader as VS";
5425 case PIPE_SHADER_TESS_CTRL:
5426 return "Tessellation Control Shader";
5427 case PIPE_SHADER_TESS_EVAL:
5428 if (shader->key.as_es)
5429 return "Tessellation Evaluation Shader as ES";
5430 else
5431 return "Tessellation Evaluation Shader as VS";
5432 case PIPE_SHADER_GEOMETRY:
5433 if (shader->is_gs_copy_shader)
5434 return "GS Copy Shader as VS";
5435 else
5436 return "Geometry Shader";
5437 case PIPE_SHADER_FRAGMENT:
5438 return "Pixel Shader";
5439 case PIPE_SHADER_COMPUTE:
5440 return "Compute Shader";
5441 default:
5442 return "Unknown Shader";
5443 }
5444 }
5445
5446 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5447 struct pipe_debug_callback *debug, unsigned processor,
5448 FILE *file, bool check_debug_option)
5449 {
5450 if (!check_debug_option ||
5451 si_can_dump_shader(sscreen, processor))
5452 si_dump_shader_key(processor, shader, file);
5453
5454 if (!check_debug_option && shader->binary.llvm_ir_string) {
5455 if (shader->previous_stage &&
5456 shader->previous_stage->binary.llvm_ir_string) {
5457 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5458 si_get_shader_name(shader, processor));
5459 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5460 }
5461
5462 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5463 si_get_shader_name(shader, processor));
5464 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5465 }
5466
5467 if (!check_debug_option ||
5468 (si_can_dump_shader(sscreen, processor) &&
5469 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5470 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5471
5472 if (shader->prolog)
5473 si_shader_dump_disassembly(&shader->prolog->binary,
5474 debug, "prolog", file);
5475 if (shader->previous_stage)
5476 si_shader_dump_disassembly(&shader->previous_stage->binary,
5477 debug, "previous stage", file);
5478 if (shader->prolog2)
5479 si_shader_dump_disassembly(&shader->prolog2->binary,
5480 debug, "prolog2", file);
5481
5482 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5483
5484 if (shader->epilog)
5485 si_shader_dump_disassembly(&shader->epilog->binary,
5486 debug, "epilog", file);
5487 fprintf(file, "\n");
5488 }
5489
5490 si_shader_dump_stats(sscreen, shader, processor, file,
5491 check_debug_option);
5492 }
5493
5494 static int si_compile_llvm(struct si_screen *sscreen,
5495 struct ac_shader_binary *binary,
5496 struct si_shader_config *conf,
5497 LLVMTargetMachineRef tm,
5498 LLVMModuleRef mod,
5499 struct pipe_debug_callback *debug,
5500 unsigned processor,
5501 const char *name)
5502 {
5503 int r = 0;
5504 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5505
5506 if (si_can_dump_shader(sscreen, processor)) {
5507 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5508
5509 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5510 fprintf(stderr, "%s LLVM IR:\n\n", name);
5511 ac_dump_module(mod);
5512 fprintf(stderr, "\n");
5513 }
5514 }
5515
5516 if (sscreen->record_llvm_ir) {
5517 char *ir = LLVMPrintModuleToString(mod);
5518 binary->llvm_ir_string = strdup(ir);
5519 LLVMDisposeMessage(ir);
5520 }
5521
5522 if (!si_replace_shader(count, binary)) {
5523 r = si_llvm_compile(mod, binary, tm, debug);
5524 if (r)
5525 return r;
5526 }
5527
5528 si_shader_binary_read_config(binary, conf, 0);
5529
5530 /* Enable 64-bit and 16-bit denormals, because there is no performance
5531 * cost.
5532 *
5533 * If denormals are enabled, all floating-point output modifiers are
5534 * ignored.
5535 *
5536 * Don't enable denormals for 32-bit floats, because:
5537 * - Floating-point output modifiers would be ignored by the hw.
5538 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5539 * have to stop using those.
5540 * - SI & CI would be very slow.
5541 */
5542 conf->float_mode |= V_00B028_FP_64_DENORMS;
5543
5544 FREE(binary->config);
5545 FREE(binary->global_symbol_offsets);
5546 binary->config = NULL;
5547 binary->global_symbol_offsets = NULL;
5548
5549 /* Some shaders can't have rodata because their binaries can be
5550 * concatenated.
5551 */
5552 if (binary->rodata_size &&
5553 (processor == PIPE_SHADER_VERTEX ||
5554 processor == PIPE_SHADER_TESS_CTRL ||
5555 processor == PIPE_SHADER_TESS_EVAL ||
5556 processor == PIPE_SHADER_FRAGMENT)) {
5557 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5558 return -EINVAL;
5559 }
5560
5561 return r;
5562 }
5563
5564 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5565 {
5566 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5567 LLVMBuildRetVoid(ctx->ac.builder);
5568 else
5569 LLVMBuildRet(ctx->ac.builder, ret);
5570 }
5571
5572 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5573 struct si_shader *
5574 si_generate_gs_copy_shader(struct si_screen *sscreen,
5575 LLVMTargetMachineRef tm,
5576 struct si_shader_selector *gs_selector,
5577 struct pipe_debug_callback *debug)
5578 {
5579 struct si_shader_context ctx;
5580 struct si_shader *shader;
5581 LLVMBuilderRef builder;
5582 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
5583 struct lp_build_context *uint = &bld_base->uint_bld;
5584 struct si_shader_output_values *outputs;
5585 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5586 int i, r;
5587
5588 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5589
5590 if (!outputs)
5591 return NULL;
5592
5593 shader = CALLOC_STRUCT(si_shader);
5594 if (!shader) {
5595 FREE(outputs);
5596 return NULL;
5597 }
5598
5599 /* We can leave the fence as permanently signaled because the GS copy
5600 * shader only becomes visible globally after it has been compiled. */
5601 util_queue_fence_init(&shader->ready);
5602
5603 shader->selector = gs_selector;
5604 shader->is_gs_copy_shader = true;
5605
5606 si_init_shader_ctx(&ctx, sscreen, tm);
5607 ctx.shader = shader;
5608 ctx.type = PIPE_SHADER_VERTEX;
5609
5610 builder = ctx.ac.builder;
5611
5612 create_function(&ctx);
5613 preload_ring_buffers(&ctx);
5614
5615 LLVMValueRef voffset =
5616 lp_build_mul_imm(uint, ctx.abi.vertex_id, 4);
5617
5618 /* Fetch the vertex stream ID.*/
5619 LLVMValueRef stream_id;
5620
5621 if (gs_selector->so.num_outputs)
5622 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5623 else
5624 stream_id = ctx.i32_0;
5625
5626 /* Fill in output information. */
5627 for (i = 0; i < gsinfo->num_outputs; ++i) {
5628 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5629 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5630
5631 for (int chan = 0; chan < 4; chan++) {
5632 outputs[i].vertex_stream[chan] =
5633 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5634 }
5635 }
5636
5637 LLVMBasicBlockRef end_bb;
5638 LLVMValueRef switch_inst;
5639
5640 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5641 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5642
5643 for (int stream = 0; stream < 4; stream++) {
5644 LLVMBasicBlockRef bb;
5645 unsigned offset;
5646
5647 if (!gsinfo->num_stream_output_components[stream])
5648 continue;
5649
5650 if (stream > 0 && !gs_selector->so.num_outputs)
5651 continue;
5652
5653 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5654 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5655 LLVMPositionBuilderAtEnd(builder, bb);
5656
5657 /* Fetch vertex data from GSVS ring */
5658 offset = 0;
5659 for (i = 0; i < gsinfo->num_outputs; ++i) {
5660 for (unsigned chan = 0; chan < 4; chan++) {
5661 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5662 outputs[i].vertex_stream[chan] != stream) {
5663 outputs[i].values[chan] = ctx.bld_base.base.undef;
5664 continue;
5665 }
5666
5667 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5668 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5669 offset++;
5670
5671 outputs[i].values[chan] =
5672 ac_build_buffer_load(&ctx.ac,
5673 ctx.gsvs_ring[0], 1,
5674 ctx.i32_0, voffset,
5675 soffset, 0, 1, 1,
5676 true, false);
5677 }
5678 }
5679
5680 /* Streamout and exports. */
5681 if (gs_selector->so.num_outputs) {
5682 si_llvm_emit_streamout(&ctx, outputs,
5683 gsinfo->num_outputs,
5684 stream);
5685 }
5686
5687 if (stream == 0)
5688 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5689
5690 LLVMBuildBr(builder, end_bb);
5691 }
5692
5693 LLVMPositionBuilderAtEnd(builder, end_bb);
5694
5695 LLVMBuildRetVoid(ctx.ac.builder);
5696
5697 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5698 si_llvm_optimize_module(&ctx);
5699
5700 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5701 &ctx.shader->config, ctx.tm,
5702 ctx.gallivm.module,
5703 debug, PIPE_SHADER_GEOMETRY,
5704 "GS Copy Shader");
5705 if (!r) {
5706 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5707 fprintf(stderr, "GS Copy Shader:\n");
5708 si_shader_dump(sscreen, ctx.shader, debug,
5709 PIPE_SHADER_GEOMETRY, stderr, true);
5710 r = si_shader_binary_upload(sscreen, ctx.shader);
5711 }
5712
5713 si_llvm_dispose(&ctx);
5714
5715 FREE(outputs);
5716
5717 if (r != 0) {
5718 FREE(shader);
5719 shader = NULL;
5720 }
5721 return shader;
5722 }
5723
5724 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5725 const struct si_vs_prolog_bits *prolog,
5726 const char *prefix, FILE *f)
5727 {
5728 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5729 prefix, prolog->instance_divisor_is_one);
5730 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5731 prefix, prolog->instance_divisor_is_fetched);
5732 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5733 prefix, prolog->ls_vgpr_fix);
5734
5735 fprintf(f, " mono.vs.fix_fetch = {");
5736 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5737 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5738 fprintf(f, "}\n");
5739 }
5740
5741 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5742 FILE *f)
5743 {
5744 const struct si_shader_key *key = &shader->key;
5745
5746 fprintf(f, "SHADER KEY\n");
5747
5748 switch (processor) {
5749 case PIPE_SHADER_VERTEX:
5750 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5751 "part.vs.prolog", f);
5752 fprintf(f, " as_es = %u\n", key->as_es);
5753 fprintf(f, " as_ls = %u\n", key->as_ls);
5754 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5755 key->mono.u.vs_export_prim_id);
5756 break;
5757
5758 case PIPE_SHADER_TESS_CTRL:
5759 if (shader->selector->screen->info.chip_class >= GFX9) {
5760 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5761 "part.tcs.ls_prolog", f);
5762 }
5763 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5764 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5765 break;
5766
5767 case PIPE_SHADER_TESS_EVAL:
5768 fprintf(f, " as_es = %u\n", key->as_es);
5769 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5770 key->mono.u.vs_export_prim_id);
5771 break;
5772
5773 case PIPE_SHADER_GEOMETRY:
5774 if (shader->is_gs_copy_shader)
5775 break;
5776
5777 if (shader->selector->screen->info.chip_class >= GFX9 &&
5778 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5779 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5780 "part.gs.vs_prolog", f);
5781 }
5782 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5783 break;
5784
5785 case PIPE_SHADER_COMPUTE:
5786 break;
5787
5788 case PIPE_SHADER_FRAGMENT:
5789 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5790 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5791 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5792 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5793 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5794 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5795 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5796 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5797 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5798 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5799 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5800 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5801 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5802 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5803 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5804 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5805 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5806 break;
5807
5808 default:
5809 assert(0);
5810 }
5811
5812 if ((processor == PIPE_SHADER_GEOMETRY ||
5813 processor == PIPE_SHADER_TESS_EVAL ||
5814 processor == PIPE_SHADER_VERTEX) &&
5815 !key->as_es && !key->as_ls) {
5816 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5817 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5818 }
5819 }
5820
5821 static void si_init_shader_ctx(struct si_shader_context *ctx,
5822 struct si_screen *sscreen,
5823 LLVMTargetMachineRef tm)
5824 {
5825 struct lp_build_tgsi_context *bld_base;
5826
5827 si_llvm_context_init(ctx, sscreen, tm);
5828
5829 bld_base = &ctx->bld_base;
5830 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5831
5832 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5833 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5834 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5835
5836 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5837
5838 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5839
5840 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5841 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5842 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5843 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5844
5845 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5846 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5847 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5848 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5849 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5850 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5851 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5852 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
5853 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5854
5855 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5856 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_tgsi_emit_primitive;
5857 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5858 }
5859
5860 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5861 {
5862 struct si_shader *shader = ctx->shader;
5863 struct tgsi_shader_info *info = &shader->selector->info;
5864
5865 if ((ctx->type != PIPE_SHADER_VERTEX &&
5866 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5867 shader->key.as_ls ||
5868 shader->key.as_es)
5869 return;
5870
5871 ac_optimize_vs_outputs(&ctx->ac,
5872 ctx->main_fn,
5873 shader->info.vs_output_param_offset,
5874 info->num_outputs,
5875 &shader->info.nr_param_exports);
5876 }
5877
5878 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
5879 {
5880 ctx->shader->config.private_mem_vgprs = 0;
5881
5882 /* Process all LLVM instructions. */
5883 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
5884 while (bb) {
5885 LLVMValueRef next = LLVMGetFirstInstruction(bb);
5886
5887 while (next) {
5888 LLVMValueRef inst = next;
5889 next = LLVMGetNextInstruction(next);
5890
5891 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
5892 continue;
5893
5894 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
5895 /* No idea why LLVM aligns allocas to 4 elements. */
5896 unsigned alignment = LLVMGetAlignment(inst);
5897 unsigned dw_size = align(ac_get_type_size(type) / 4, alignment);
5898 ctx->shader->config.private_mem_vgprs += dw_size;
5899 }
5900 bb = LLVMGetNextBasicBlock(bb);
5901 }
5902 }
5903
5904 static void si_init_exec_from_input(struct si_shader_context *ctx,
5905 unsigned param, unsigned bitoffset)
5906 {
5907 LLVMValueRef args[] = {
5908 LLVMGetParam(ctx->main_fn, param),
5909 LLVMConstInt(ctx->i32, bitoffset, 0),
5910 };
5911 lp_build_intrinsic(ctx->ac.builder,
5912 "llvm.amdgcn.init.exec.from.input",
5913 ctx->voidt, args, 2, LP_FUNC_ATTR_CONVERGENT);
5914 }
5915
5916 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
5917 const struct si_vs_prolog_bits *key)
5918 {
5919 /* VGPR initialization fixup for Vega10 and Raven is always done in the
5920 * VS prolog. */
5921 return sel->vs_needs_prolog || key->ls_vgpr_fix;
5922 }
5923
5924 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
5925 bool is_monolithic)
5926 {
5927 struct si_shader *shader = ctx->shader;
5928 struct si_shader_selector *sel = shader->selector;
5929 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5930
5931 // TODO clean all this up!
5932 switch (ctx->type) {
5933 case PIPE_SHADER_VERTEX:
5934 ctx->load_input = declare_input_vs;
5935 if (shader->key.as_ls)
5936 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
5937 else if (shader->key.as_es)
5938 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5939 else
5940 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5941 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5942 break;
5943 case PIPE_SHADER_TESS_CTRL:
5944 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5945 ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
5946 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5947 bld_base->emit_store = store_output_tcs;
5948 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
5949 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
5950 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
5951 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5952 break;
5953 case PIPE_SHADER_TESS_EVAL:
5954 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
5955 ctx->abi.load_tess_varyings = si_nir_load_input_tes;
5956 ctx->abi.load_tess_coord = si_load_tess_coord;
5957 ctx->abi.load_tess_level = si_load_tess_level;
5958 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
5959 if (shader->key.as_es)
5960 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5961 else
5962 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5963 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5964 break;
5965 case PIPE_SHADER_GEOMETRY:
5966 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
5967 ctx->abi.load_inputs = si_nir_load_input_gs;
5968 ctx->abi.emit_vertex = si_llvm_emit_vertex;
5969 ctx->abi.emit_primitive = si_llvm_emit_primitive;
5970 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
5971 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
5972 break;
5973 case PIPE_SHADER_FRAGMENT:
5974 ctx->load_input = declare_input_fs;
5975 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
5976 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5977 ctx->abi.lookup_interp_param = si_nir_lookup_interp_param;
5978 ctx->abi.load_sample_position = load_sample_position;
5979 break;
5980 case PIPE_SHADER_COMPUTE:
5981 break;
5982 default:
5983 assert(!"Unsupported shader type");
5984 return false;
5985 }
5986
5987 ctx->abi.load_ubo = load_ubo;
5988 ctx->abi.load_ssbo = load_ssbo;
5989
5990 create_function(ctx);
5991 preload_ring_buffers(ctx);
5992
5993 /* For GFX9 merged shaders:
5994 * - Set EXEC for the first shader. If the prolog is present, set
5995 * EXEC there instead.
5996 * - Add a barrier before the second shader.
5997 * - In the second shader, reset EXEC to ~0 and wrap the main part in
5998 * an if-statement. This is required for correctness in geometry
5999 * shaders, to ensure that empty GS waves do not send GS_EMIT and
6000 * GS_CUT messages.
6001 *
6002 * For monolithic merged shaders, the first shader is wrapped in an
6003 * if-block together with its prolog in si_build_wrapper_function.
6004 */
6005 if (ctx->screen->info.chip_class >= GFX9) {
6006 if (!is_monolithic &&
6007 sel->info.num_instructions > 1 && /* not empty shader */
6008 (shader->key.as_es || shader->key.as_ls) &&
6009 (ctx->type == PIPE_SHADER_TESS_EVAL ||
6010 (ctx->type == PIPE_SHADER_VERTEX &&
6011 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
6012 si_init_exec_from_input(ctx,
6013 ctx->param_merged_wave_info, 0);
6014 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6015 ctx->type == PIPE_SHADER_GEOMETRY) {
6016 if (!is_monolithic)
6017 ac_init_exec_full_mask(&ctx->ac);
6018
6019 /* The barrier must execute for all shaders in a
6020 * threadgroup.
6021 */
6022 si_llvm_emit_barrier(NULL, bld_base, NULL);
6023
6024 LLVMValueRef num_threads = unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
6025 LLVMValueRef ena =
6026 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
6027 ac_get_thread_id(&ctx->ac), num_threads, "");
6028 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
6029 }
6030 }
6031
6032 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
6033 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
6034 for (unsigned i = 0; i < 6; i++) {
6035 ctx->invoc0_tess_factors[i] =
6036 lp_build_alloca_undef(&ctx->gallivm, ctx->i32, "");
6037 }
6038 }
6039
6040 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6041 int i;
6042 for (i = 0; i < 4; i++) {
6043 ctx->gs_next_vertex[i] =
6044 lp_build_alloca(&ctx->gallivm,
6045 ctx->i32, "");
6046 }
6047 }
6048
6049 if (sel->force_correct_derivs_after_kill) {
6050 ctx->postponed_kill = lp_build_alloca_undef(&ctx->gallivm, ctx->i1, "");
6051 /* true = don't kill. */
6052 LLVMBuildStore(ctx->ac.builder, LLVMConstInt(ctx->i1, 1, 0),
6053 ctx->postponed_kill);
6054 }
6055
6056 if (sel->tokens) {
6057 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6058 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6059 return false;
6060 }
6061 } else {
6062 if (!si_nir_build_llvm(ctx, sel->nir)) {
6063 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
6064 return false;
6065 }
6066 }
6067
6068 si_llvm_build_ret(ctx, ctx->return_value);
6069 return true;
6070 }
6071
6072 /**
6073 * Compute the VS prolog key, which contains all the information needed to
6074 * build the VS prolog function, and set shader->info bits where needed.
6075 *
6076 * \param info Shader info of the vertex shader.
6077 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6078 * \param prolog_key Key of the VS prolog
6079 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6080 * \param key Output shader part key.
6081 */
6082 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
6083 unsigned num_input_sgprs,
6084 const struct si_vs_prolog_bits *prolog_key,
6085 struct si_shader *shader_out,
6086 union si_shader_part_key *key)
6087 {
6088 memset(key, 0, sizeof(*key));
6089 key->vs_prolog.states = *prolog_key;
6090 key->vs_prolog.num_input_sgprs = num_input_sgprs;
6091 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6092 key->vs_prolog.as_ls = shader_out->key.as_ls;
6093 key->vs_prolog.as_es = shader_out->key.as_es;
6094
6095 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
6096 key->vs_prolog.as_ls = 1;
6097 key->vs_prolog.num_merged_next_stage_vgprs = 2;
6098 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
6099 key->vs_prolog.as_es = 1;
6100 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6101 }
6102
6103 /* Enable loading the InstanceID VGPR. */
6104 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
6105
6106 if ((key->vs_prolog.states.instance_divisor_is_one |
6107 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
6108 shader_out->info.uses_instanceid = true;
6109 }
6110
6111 /**
6112 * Compute the PS prolog key, which contains all the information needed to
6113 * build the PS prolog function, and set related bits in shader->config.
6114 */
6115 static void si_get_ps_prolog_key(struct si_shader *shader,
6116 union si_shader_part_key *key,
6117 bool separate_prolog)
6118 {
6119 struct tgsi_shader_info *info = &shader->selector->info;
6120
6121 memset(key, 0, sizeof(*key));
6122 key->ps_prolog.states = shader->key.part.ps.prolog;
6123 key->ps_prolog.colors_read = info->colors_read;
6124 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6125 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6126 key->ps_prolog.wqm = info->uses_derivatives &&
6127 (key->ps_prolog.colors_read ||
6128 key->ps_prolog.states.force_persp_sample_interp ||
6129 key->ps_prolog.states.force_linear_sample_interp ||
6130 key->ps_prolog.states.force_persp_center_interp ||
6131 key->ps_prolog.states.force_linear_center_interp ||
6132 key->ps_prolog.states.bc_optimize_for_persp ||
6133 key->ps_prolog.states.bc_optimize_for_linear);
6134 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
6135
6136 if (info->colors_read) {
6137 unsigned *color = shader->selector->color_attr_index;
6138
6139 if (shader->key.part.ps.prolog.color_two_side) {
6140 /* BCOLORs are stored after the last input. */
6141 key->ps_prolog.num_interp_inputs = info->num_inputs;
6142 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6143 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6144 }
6145
6146 for (unsigned i = 0; i < 2; i++) {
6147 unsigned interp = info->input_interpolate[color[i]];
6148 unsigned location = info->input_interpolate_loc[color[i]];
6149
6150 if (!(info->colors_read & (0xf << i*4)))
6151 continue;
6152
6153 key->ps_prolog.color_attr_index[i] = color[i];
6154
6155 if (shader->key.part.ps.prolog.flatshade_colors &&
6156 interp == TGSI_INTERPOLATE_COLOR)
6157 interp = TGSI_INTERPOLATE_CONSTANT;
6158
6159 switch (interp) {
6160 case TGSI_INTERPOLATE_CONSTANT:
6161 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6162 break;
6163 case TGSI_INTERPOLATE_PERSPECTIVE:
6164 case TGSI_INTERPOLATE_COLOR:
6165 /* Force the interpolation location for colors here. */
6166 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6167 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6168 if (shader->key.part.ps.prolog.force_persp_center_interp)
6169 location = TGSI_INTERPOLATE_LOC_CENTER;
6170
6171 switch (location) {
6172 case TGSI_INTERPOLATE_LOC_SAMPLE:
6173 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6174 shader->config.spi_ps_input_ena |=
6175 S_0286CC_PERSP_SAMPLE_ENA(1);
6176 break;
6177 case TGSI_INTERPOLATE_LOC_CENTER:
6178 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6179 shader->config.spi_ps_input_ena |=
6180 S_0286CC_PERSP_CENTER_ENA(1);
6181 break;
6182 case TGSI_INTERPOLATE_LOC_CENTROID:
6183 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6184 shader->config.spi_ps_input_ena |=
6185 S_0286CC_PERSP_CENTROID_ENA(1);
6186 break;
6187 default:
6188 assert(0);
6189 }
6190 break;
6191 case TGSI_INTERPOLATE_LINEAR:
6192 /* Force the interpolation location for colors here. */
6193 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6194 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6195 if (shader->key.part.ps.prolog.force_linear_center_interp)
6196 location = TGSI_INTERPOLATE_LOC_CENTER;
6197
6198 /* The VGPR assignment for non-monolithic shaders
6199 * works because InitialPSInputAddr is set on the
6200 * main shader and PERSP_PULL_MODEL is never used.
6201 */
6202 switch (location) {
6203 case TGSI_INTERPOLATE_LOC_SAMPLE:
6204 key->ps_prolog.color_interp_vgpr_index[i] =
6205 separate_prolog ? 6 : 9;
6206 shader->config.spi_ps_input_ena |=
6207 S_0286CC_LINEAR_SAMPLE_ENA(1);
6208 break;
6209 case TGSI_INTERPOLATE_LOC_CENTER:
6210 key->ps_prolog.color_interp_vgpr_index[i] =
6211 separate_prolog ? 8 : 11;
6212 shader->config.spi_ps_input_ena |=
6213 S_0286CC_LINEAR_CENTER_ENA(1);
6214 break;
6215 case TGSI_INTERPOLATE_LOC_CENTROID:
6216 key->ps_prolog.color_interp_vgpr_index[i] =
6217 separate_prolog ? 10 : 13;
6218 shader->config.spi_ps_input_ena |=
6219 S_0286CC_LINEAR_CENTROID_ENA(1);
6220 break;
6221 default:
6222 assert(0);
6223 }
6224 break;
6225 default:
6226 assert(0);
6227 }
6228 }
6229 }
6230 }
6231
6232 /**
6233 * Check whether a PS prolog is required based on the key.
6234 */
6235 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6236 {
6237 return key->ps_prolog.colors_read ||
6238 key->ps_prolog.states.force_persp_sample_interp ||
6239 key->ps_prolog.states.force_linear_sample_interp ||
6240 key->ps_prolog.states.force_persp_center_interp ||
6241 key->ps_prolog.states.force_linear_center_interp ||
6242 key->ps_prolog.states.bc_optimize_for_persp ||
6243 key->ps_prolog.states.bc_optimize_for_linear ||
6244 key->ps_prolog.states.poly_stipple ||
6245 key->ps_prolog.states.samplemask_log_ps_iter;
6246 }
6247
6248 /**
6249 * Compute the PS epilog key, which contains all the information needed to
6250 * build the PS epilog function.
6251 */
6252 static void si_get_ps_epilog_key(struct si_shader *shader,
6253 union si_shader_part_key *key)
6254 {
6255 struct tgsi_shader_info *info = &shader->selector->info;
6256 memset(key, 0, sizeof(*key));
6257 key->ps_epilog.colors_written = info->colors_written;
6258 key->ps_epilog.writes_z = info->writes_z;
6259 key->ps_epilog.writes_stencil = info->writes_stencil;
6260 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6261 key->ps_epilog.states = shader->key.part.ps.epilog;
6262 }
6263
6264 /**
6265 * Build the GS prolog function. Rotate the input vertices for triangle strips
6266 * with adjacency.
6267 */
6268 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6269 union si_shader_part_key *key)
6270 {
6271 unsigned num_sgprs, num_vgprs;
6272 struct si_function_info fninfo;
6273 LLVMBuilderRef builder = ctx->ac.builder;
6274 LLVMTypeRef returns[48];
6275 LLVMValueRef func, ret;
6276
6277 si_init_function_info(&fninfo);
6278
6279 if (ctx->screen->info.chip_class >= GFX9) {
6280 num_sgprs = 8 + GFX9_GS_NUM_USER_SGPR;
6281 num_vgprs = 5; /* ES inputs are not needed by GS */
6282 } else {
6283 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6284 num_vgprs = 8;
6285 }
6286
6287 for (unsigned i = 0; i < num_sgprs; ++i) {
6288 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6289 returns[i] = ctx->i32;
6290 }
6291
6292 for (unsigned i = 0; i < num_vgprs; ++i) {
6293 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6294 returns[num_sgprs + i] = ctx->f32;
6295 }
6296
6297 /* Create the function. */
6298 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6299 &fninfo, 0);
6300 func = ctx->main_fn;
6301
6302 /* Set the full EXEC mask for the prolog, because we are only fiddling
6303 * with registers here. The main shader part will set the correct EXEC
6304 * mask.
6305 */
6306 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6307 ac_init_exec_full_mask(&ctx->ac);
6308
6309 /* Copy inputs to outputs. This should be no-op, as the registers match,
6310 * but it will prevent the compiler from overwriting them unintentionally.
6311 */
6312 ret = ctx->return_value;
6313 for (unsigned i = 0; i < num_sgprs; i++) {
6314 LLVMValueRef p = LLVMGetParam(func, i);
6315 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6316 }
6317 for (unsigned i = 0; i < num_vgprs; i++) {
6318 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6319 p = ac_to_float(&ctx->ac, p);
6320 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6321 }
6322
6323 if (key->gs_prolog.states.tri_strip_adj_fix) {
6324 /* Remap the input vertices for every other primitive. */
6325 const unsigned gfx6_vtx_params[6] = {
6326 num_sgprs,
6327 num_sgprs + 1,
6328 num_sgprs + 3,
6329 num_sgprs + 4,
6330 num_sgprs + 5,
6331 num_sgprs + 6
6332 };
6333 const unsigned gfx9_vtx_params[3] = {
6334 num_sgprs,
6335 num_sgprs + 1,
6336 num_sgprs + 4,
6337 };
6338 LLVMValueRef vtx_in[6], vtx_out[6];
6339 LLVMValueRef prim_id, rotate;
6340
6341 if (ctx->screen->info.chip_class >= GFX9) {
6342 for (unsigned i = 0; i < 3; i++) {
6343 vtx_in[i*2] = unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6344 vtx_in[i*2+1] = unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6345 }
6346 } else {
6347 for (unsigned i = 0; i < 6; i++)
6348 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6349 }
6350
6351 prim_id = LLVMGetParam(func, num_sgprs + 2);
6352 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6353
6354 for (unsigned i = 0; i < 6; ++i) {
6355 LLVMValueRef base, rotated;
6356 base = vtx_in[i];
6357 rotated = vtx_in[(i + 4) % 6];
6358 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6359 }
6360
6361 if (ctx->screen->info.chip_class >= GFX9) {
6362 for (unsigned i = 0; i < 3; i++) {
6363 LLVMValueRef hi, out;
6364
6365 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6366 LLVMConstInt(ctx->i32, 16, 0), "");
6367 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6368 out = ac_to_float(&ctx->ac, out);
6369 ret = LLVMBuildInsertValue(builder, ret, out,
6370 gfx9_vtx_params[i], "");
6371 }
6372 } else {
6373 for (unsigned i = 0; i < 6; i++) {
6374 LLVMValueRef out;
6375
6376 out = ac_to_float(&ctx->ac, vtx_out[i]);
6377 ret = LLVMBuildInsertValue(builder, ret, out,
6378 gfx6_vtx_params[i], "");
6379 }
6380 }
6381 }
6382
6383 LLVMBuildRet(builder, ret);
6384 }
6385
6386 /**
6387 * Given a list of shader part functions, build a wrapper function that
6388 * runs them in sequence to form a monolithic shader.
6389 */
6390 static void si_build_wrapper_function(struct si_shader_context *ctx,
6391 LLVMValueRef *parts,
6392 unsigned num_parts,
6393 unsigned main_part,
6394 unsigned next_shader_first_part)
6395 {
6396 LLVMBuilderRef builder = ctx->ac.builder;
6397 /* PS epilog has one arg per color component; gfx9 merged shader
6398 * prologs need to forward 32 user SGPRs.
6399 */
6400 struct si_function_info fninfo;
6401 LLVMValueRef initial[64], out[64];
6402 LLVMTypeRef function_type;
6403 unsigned num_first_params;
6404 unsigned num_out, initial_num_out;
6405 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6406 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6407 unsigned num_sgprs, num_vgprs;
6408 unsigned gprs;
6409 struct lp_build_if_state if_state;
6410
6411 si_init_function_info(&fninfo);
6412
6413 for (unsigned i = 0; i < num_parts; ++i) {
6414 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6415 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6416 }
6417
6418 /* The parameters of the wrapper function correspond to those of the
6419 * first part in terms of SGPRs and VGPRs, but we use the types of the
6420 * main part to get the right types. This is relevant for the
6421 * dereferenceable attribute on descriptor table pointers.
6422 */
6423 num_sgprs = 0;
6424 num_vgprs = 0;
6425
6426 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6427 num_first_params = LLVMCountParamTypes(function_type);
6428
6429 for (unsigned i = 0; i < num_first_params; ++i) {
6430 LLVMValueRef param = LLVMGetParam(parts[0], i);
6431
6432 if (ac_is_sgpr_param(param)) {
6433 assert(num_vgprs == 0);
6434 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6435 } else {
6436 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6437 }
6438 }
6439
6440 gprs = 0;
6441 while (gprs < num_sgprs + num_vgprs) {
6442 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6443 LLVMTypeRef type = LLVMTypeOf(param);
6444 unsigned size = ac_get_type_size(type) / 4;
6445
6446 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6447
6448 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6449 assert(gprs + size <= num_sgprs + num_vgprs &&
6450 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6451
6452 gprs += size;
6453 }
6454
6455 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6456 si_get_max_workgroup_size(ctx->shader));
6457
6458 if (is_merged_shader(ctx->shader))
6459 ac_init_exec_full_mask(&ctx->ac);
6460
6461 /* Record the arguments of the function as if they were an output of
6462 * a previous part.
6463 */
6464 num_out = 0;
6465 num_out_sgpr = 0;
6466
6467 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6468 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6469 LLVMTypeRef param_type = LLVMTypeOf(param);
6470 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6471 unsigned size = ac_get_type_size(param_type) / 4;
6472
6473 if (size == 1) {
6474 if (param_type != out_type)
6475 param = LLVMBuildBitCast(builder, param, out_type, "");
6476 out[num_out++] = param;
6477 } else {
6478 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6479
6480 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6481 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6482 param_type = ctx->i64;
6483 }
6484
6485 if (param_type != vector_type)
6486 param = LLVMBuildBitCast(builder, param, vector_type, "");
6487
6488 for (unsigned j = 0; j < size; ++j)
6489 out[num_out++] = LLVMBuildExtractElement(
6490 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6491 }
6492
6493 if (i < fninfo.num_sgpr_params)
6494 num_out_sgpr = num_out;
6495 }
6496
6497 memcpy(initial, out, sizeof(out));
6498 initial_num_out = num_out;
6499 initial_num_out_sgpr = num_out_sgpr;
6500
6501 /* Now chain the parts. */
6502 for (unsigned part = 0; part < num_parts; ++part) {
6503 LLVMValueRef in[48];
6504 LLVMValueRef ret;
6505 LLVMTypeRef ret_type;
6506 unsigned out_idx = 0;
6507 unsigned num_params = LLVMCountParams(parts[part]);
6508
6509 /* Merged shaders are executed conditionally depending
6510 * on the number of enabled threads passed in the input SGPRs. */
6511 if (is_merged_shader(ctx->shader) && part == 0) {
6512 LLVMValueRef ena, count = initial[3];
6513
6514 count = LLVMBuildAnd(builder, count,
6515 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6516 ena = LLVMBuildICmp(builder, LLVMIntULT,
6517 ac_get_thread_id(&ctx->ac), count, "");
6518 lp_build_if(&if_state, &ctx->gallivm, ena);
6519 }
6520
6521 /* Derive arguments for the next part from outputs of the
6522 * previous one.
6523 */
6524 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6525 LLVMValueRef param;
6526 LLVMTypeRef param_type;
6527 bool is_sgpr;
6528 unsigned param_size;
6529 LLVMValueRef arg = NULL;
6530
6531 param = LLVMGetParam(parts[part], param_idx);
6532 param_type = LLVMTypeOf(param);
6533 param_size = ac_get_type_size(param_type) / 4;
6534 is_sgpr = ac_is_sgpr_param(param);
6535
6536 if (is_sgpr)
6537 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
6538
6539 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6540 assert(is_sgpr || out_idx >= num_out_sgpr);
6541
6542 if (param_size == 1)
6543 arg = out[out_idx];
6544 else
6545 arg = lp_build_gather_values(&ctx->gallivm, &out[out_idx], param_size);
6546
6547 if (LLVMTypeOf(arg) != param_type) {
6548 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6549 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6550 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6551 } else {
6552 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6553 }
6554 }
6555
6556 in[param_idx] = arg;
6557 out_idx += param_size;
6558 }
6559
6560 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6561
6562 if (is_merged_shader(ctx->shader) &&
6563 part + 1 == next_shader_first_part) {
6564 lp_build_endif(&if_state);
6565
6566 /* The second half of the merged shader should use
6567 * the inputs from the toplevel (wrapper) function,
6568 * not the return value from the last call.
6569 *
6570 * That's because the last call was executed condi-
6571 * tionally, so we can't consume it in the main
6572 * block.
6573 */
6574 memcpy(out, initial, sizeof(initial));
6575 num_out = initial_num_out;
6576 num_out_sgpr = initial_num_out_sgpr;
6577 continue;
6578 }
6579
6580 /* Extract the returned GPRs. */
6581 ret_type = LLVMTypeOf(ret);
6582 num_out = 0;
6583 num_out_sgpr = 0;
6584
6585 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6586 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6587
6588 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6589
6590 for (unsigned i = 0; i < ret_size; ++i) {
6591 LLVMValueRef val =
6592 LLVMBuildExtractValue(builder, ret, i, "");
6593
6594 assert(num_out < ARRAY_SIZE(out));
6595 out[num_out++] = val;
6596
6597 if (LLVMTypeOf(val) == ctx->i32) {
6598 assert(num_out_sgpr + 1 == num_out);
6599 num_out_sgpr = num_out;
6600 }
6601 }
6602 }
6603 }
6604
6605 LLVMBuildRetVoid(builder);
6606 }
6607
6608 int si_compile_tgsi_shader(struct si_screen *sscreen,
6609 LLVMTargetMachineRef tm,
6610 struct si_shader *shader,
6611 bool is_monolithic,
6612 struct pipe_debug_callback *debug)
6613 {
6614 struct si_shader_selector *sel = shader->selector;
6615 struct si_shader_context ctx;
6616 int r = -1;
6617
6618 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6619 * conversion fails. */
6620 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6621 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6622 if (sel->tokens)
6623 tgsi_dump(sel->tokens, 0);
6624 else
6625 nir_print_shader(sel->nir, stderr);
6626 si_dump_streamout(&sel->so);
6627 }
6628
6629 si_init_shader_ctx(&ctx, sscreen, tm);
6630 si_llvm_context_set_tgsi(&ctx, shader);
6631 ctx.separate_prolog = !is_monolithic;
6632
6633 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6634 sizeof(shader->info.vs_output_param_offset));
6635
6636 shader->info.uses_instanceid = sel->info.uses_instanceid;
6637
6638 if (!si_compile_tgsi_main(&ctx, is_monolithic)) {
6639 si_llvm_dispose(&ctx);
6640 return -1;
6641 }
6642
6643 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6644 LLVMValueRef parts[2];
6645 bool need_prolog = sel->vs_needs_prolog;
6646
6647 parts[1] = ctx.main_fn;
6648
6649 if (need_prolog) {
6650 union si_shader_part_key prolog_key;
6651 si_get_vs_prolog_key(&sel->info,
6652 shader->info.num_input_sgprs,
6653 &shader->key.part.vs.prolog,
6654 shader, &prolog_key);
6655 si_build_vs_prolog_function(&ctx, &prolog_key);
6656 parts[0] = ctx.main_fn;
6657 }
6658
6659 si_build_wrapper_function(&ctx, parts + !need_prolog,
6660 1 + need_prolog, need_prolog, 0);
6661 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6662 if (sscreen->info.chip_class >= GFX9) {
6663 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6664 LLVMValueRef parts[4];
6665 bool vs_needs_prolog =
6666 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6667
6668 /* TCS main part */
6669 parts[2] = ctx.main_fn;
6670
6671 /* TCS epilog */
6672 union si_shader_part_key tcs_epilog_key;
6673 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6674 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6675 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6676 parts[3] = ctx.main_fn;
6677
6678 /* VS prolog */
6679 if (vs_needs_prolog) {
6680 union si_shader_part_key vs_prolog_key;
6681 si_get_vs_prolog_key(&ls->info,
6682 shader->info.num_input_sgprs,
6683 &shader->key.part.tcs.ls_prolog,
6684 shader, &vs_prolog_key);
6685 vs_prolog_key.vs_prolog.is_monolithic = true;
6686 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6687 parts[0] = ctx.main_fn;
6688 }
6689
6690 /* VS as LS main part */
6691 struct si_shader shader_ls = {};
6692 shader_ls.selector = ls;
6693 shader_ls.key.as_ls = 1;
6694 shader_ls.key.mono = shader->key.mono;
6695 shader_ls.key.opt = shader->key.opt;
6696 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6697
6698 if (!si_compile_tgsi_main(&ctx, true)) {
6699 si_llvm_dispose(&ctx);
6700 return -1;
6701 }
6702 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6703 parts[1] = ctx.main_fn;
6704
6705 /* Reset the shader context. */
6706 ctx.shader = shader;
6707 ctx.type = PIPE_SHADER_TESS_CTRL;
6708
6709 si_build_wrapper_function(&ctx,
6710 parts + !vs_needs_prolog,
6711 4 - !vs_needs_prolog, 0,
6712 vs_needs_prolog ? 2 : 1);
6713 } else {
6714 LLVMValueRef parts[2];
6715 union si_shader_part_key epilog_key;
6716
6717 parts[0] = ctx.main_fn;
6718
6719 memset(&epilog_key, 0, sizeof(epilog_key));
6720 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6721 si_build_tcs_epilog_function(&ctx, &epilog_key);
6722 parts[1] = ctx.main_fn;
6723
6724 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6725 }
6726 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6727 if (ctx.screen->info.chip_class >= GFX9) {
6728 struct si_shader_selector *es = shader->key.part.gs.es;
6729 LLVMValueRef es_prolog = NULL;
6730 LLVMValueRef es_main = NULL;
6731 LLVMValueRef gs_prolog = NULL;
6732 LLVMValueRef gs_main = ctx.main_fn;
6733
6734 /* GS prolog */
6735 union si_shader_part_key gs_prolog_key;
6736 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6737 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6738 gs_prolog_key.gs_prolog.is_monolithic = true;
6739 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6740 gs_prolog = ctx.main_fn;
6741
6742 /* ES prolog */
6743 if (es->vs_needs_prolog) {
6744 union si_shader_part_key vs_prolog_key;
6745 si_get_vs_prolog_key(&es->info,
6746 shader->info.num_input_sgprs,
6747 &shader->key.part.gs.vs_prolog,
6748 shader, &vs_prolog_key);
6749 vs_prolog_key.vs_prolog.is_monolithic = true;
6750 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6751 es_prolog = ctx.main_fn;
6752 }
6753
6754 /* ES main part */
6755 struct si_shader shader_es = {};
6756 shader_es.selector = es;
6757 shader_es.key.as_es = 1;
6758 shader_es.key.mono = shader->key.mono;
6759 shader_es.key.opt = shader->key.opt;
6760 si_llvm_context_set_tgsi(&ctx, &shader_es);
6761
6762 if (!si_compile_tgsi_main(&ctx, true)) {
6763 si_llvm_dispose(&ctx);
6764 return -1;
6765 }
6766 shader->info.uses_instanceid |= es->info.uses_instanceid;
6767 es_main = ctx.main_fn;
6768
6769 /* Reset the shader context. */
6770 ctx.shader = shader;
6771 ctx.type = PIPE_SHADER_GEOMETRY;
6772
6773 /* Prepare the array of shader parts. */
6774 LLVMValueRef parts[4];
6775 unsigned num_parts = 0, main_part, next_first_part;
6776
6777 if (es_prolog)
6778 parts[num_parts++] = es_prolog;
6779
6780 parts[main_part = num_parts++] = es_main;
6781 parts[next_first_part = num_parts++] = gs_prolog;
6782 parts[num_parts++] = gs_main;
6783
6784 si_build_wrapper_function(&ctx, parts, num_parts,
6785 main_part, next_first_part);
6786 } else {
6787 LLVMValueRef parts[2];
6788 union si_shader_part_key prolog_key;
6789
6790 parts[1] = ctx.main_fn;
6791
6792 memset(&prolog_key, 0, sizeof(prolog_key));
6793 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6794 si_build_gs_prolog_function(&ctx, &prolog_key);
6795 parts[0] = ctx.main_fn;
6796
6797 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6798 }
6799 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6800 LLVMValueRef parts[3];
6801 union si_shader_part_key prolog_key;
6802 union si_shader_part_key epilog_key;
6803 bool need_prolog;
6804
6805 si_get_ps_prolog_key(shader, &prolog_key, false);
6806 need_prolog = si_need_ps_prolog(&prolog_key);
6807
6808 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6809
6810 if (need_prolog) {
6811 si_build_ps_prolog_function(&ctx, &prolog_key);
6812 parts[0] = ctx.main_fn;
6813 }
6814
6815 si_get_ps_epilog_key(shader, &epilog_key);
6816 si_build_ps_epilog_function(&ctx, &epilog_key);
6817 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6818
6819 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6820 need_prolog ? 1 : 0, 0);
6821 }
6822
6823 si_llvm_optimize_module(&ctx);
6824
6825 /* Post-optimization transformations and analysis. */
6826 si_optimize_vs_outputs(&ctx);
6827
6828 if ((debug && debug->debug_message) ||
6829 si_can_dump_shader(sscreen, ctx.type))
6830 si_count_scratch_private_memory(&ctx);
6831
6832 /* Compile to bytecode. */
6833 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6834 ctx.gallivm.module, debug, ctx.type, "TGSI shader");
6835 si_llvm_dispose(&ctx);
6836 if (r) {
6837 fprintf(stderr, "LLVM failed to compile shader\n");
6838 return r;
6839 }
6840
6841 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6842 * LLVM 3.9svn has this bug.
6843 */
6844 if (sel->type == PIPE_SHADER_COMPUTE) {
6845 unsigned wave_size = 64;
6846 unsigned max_vgprs = 256;
6847 unsigned max_sgprs = sscreen->info.chip_class >= VI ? 800 : 512;
6848 unsigned max_sgprs_per_wave = 128;
6849 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6850 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6851 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6852
6853 max_vgprs = max_vgprs / min_waves_per_simd;
6854 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6855
6856 if (shader->config.num_sgprs > max_sgprs ||
6857 shader->config.num_vgprs > max_vgprs) {
6858 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6859 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6860 shader->config.num_sgprs, shader->config.num_vgprs,
6861 max_sgprs, max_vgprs);
6862
6863 /* Just terminate the process, because dependent
6864 * shaders can hang due to bad input data, but use
6865 * the env var to allow shader-db to work.
6866 */
6867 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6868 abort();
6869 }
6870 }
6871
6872 /* Add the scratch offset to input SGPRs. */
6873 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(shader))
6874 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6875
6876 /* Calculate the number of fragment input VGPRs. */
6877 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6878 shader->info.num_input_vgprs = 0;
6879 shader->info.face_vgpr_index = -1;
6880 shader->info.ancillary_vgpr_index = -1;
6881
6882 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6883 shader->info.num_input_vgprs += 2;
6884 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6885 shader->info.num_input_vgprs += 2;
6886 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6887 shader->info.num_input_vgprs += 2;
6888 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6889 shader->info.num_input_vgprs += 3;
6890 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6891 shader->info.num_input_vgprs += 2;
6892 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6893 shader->info.num_input_vgprs += 2;
6894 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6895 shader->info.num_input_vgprs += 2;
6896 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6897 shader->info.num_input_vgprs += 1;
6898 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6899 shader->info.num_input_vgprs += 1;
6900 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6901 shader->info.num_input_vgprs += 1;
6902 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6903 shader->info.num_input_vgprs += 1;
6904 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6905 shader->info.num_input_vgprs += 1;
6906 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6907 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6908 shader->info.num_input_vgprs += 1;
6909 }
6910 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
6911 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
6912 shader->info.num_input_vgprs += 1;
6913 }
6914 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6915 shader->info.num_input_vgprs += 1;
6916 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6917 shader->info.num_input_vgprs += 1;
6918 }
6919
6920 si_calculate_max_simd_waves(shader);
6921 si_shader_dump_stats_for_shader_db(shader, debug);
6922 return 0;
6923 }
6924
6925 /**
6926 * Create, compile and return a shader part (prolog or epilog).
6927 *
6928 * \param sscreen screen
6929 * \param list list of shader parts of the same category
6930 * \param type shader type
6931 * \param key shader part key
6932 * \param prolog whether the part being requested is a prolog
6933 * \param tm LLVM target machine
6934 * \param debug debug callback
6935 * \param build the callback responsible for building the main function
6936 * \return non-NULL on success
6937 */
6938 static struct si_shader_part *
6939 si_get_shader_part(struct si_screen *sscreen,
6940 struct si_shader_part **list,
6941 enum pipe_shader_type type,
6942 bool prolog,
6943 union si_shader_part_key *key,
6944 LLVMTargetMachineRef tm,
6945 struct pipe_debug_callback *debug,
6946 void (*build)(struct si_shader_context *,
6947 union si_shader_part_key *),
6948 const char *name)
6949 {
6950 struct si_shader_part *result;
6951
6952 mtx_lock(&sscreen->shader_parts_mutex);
6953
6954 /* Find existing. */
6955 for (result = *list; result; result = result->next) {
6956 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6957 mtx_unlock(&sscreen->shader_parts_mutex);
6958 return result;
6959 }
6960 }
6961
6962 /* Compile a new one. */
6963 result = CALLOC_STRUCT(si_shader_part);
6964 result->key = *key;
6965
6966 struct si_shader shader = {};
6967 struct si_shader_context ctx;
6968
6969 si_init_shader_ctx(&ctx, sscreen, tm);
6970 ctx.shader = &shader;
6971 ctx.type = type;
6972
6973 switch (type) {
6974 case PIPE_SHADER_VERTEX:
6975 shader.key.as_ls = key->vs_prolog.as_ls;
6976 shader.key.as_es = key->vs_prolog.as_es;
6977 break;
6978 case PIPE_SHADER_TESS_CTRL:
6979 assert(!prolog);
6980 shader.key.part.tcs.epilog = key->tcs_epilog.states;
6981 break;
6982 case PIPE_SHADER_GEOMETRY:
6983 assert(prolog);
6984 break;
6985 case PIPE_SHADER_FRAGMENT:
6986 if (prolog)
6987 shader.key.part.ps.prolog = key->ps_prolog.states;
6988 else
6989 shader.key.part.ps.epilog = key->ps_epilog.states;
6990 break;
6991 default:
6992 unreachable("bad shader part");
6993 }
6994
6995 build(&ctx, key);
6996
6997 /* Compile. */
6998 si_llvm_optimize_module(&ctx);
6999
7000 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7001 ctx.ac.module, debug, ctx.type, name)) {
7002 FREE(result);
7003 result = NULL;
7004 goto out;
7005 }
7006
7007 result->next = *list;
7008 *list = result;
7009
7010 out:
7011 si_llvm_dispose(&ctx);
7012 mtx_unlock(&sscreen->shader_parts_mutex);
7013 return result;
7014 }
7015
7016 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
7017 {
7018 LLVMValueRef ptr[2], list;
7019 bool is_merged_shader =
7020 ctx->screen->info.chip_class >= GFX9 &&
7021 (ctx->type == PIPE_SHADER_TESS_CTRL ||
7022 ctx->type == PIPE_SHADER_GEOMETRY ||
7023 ctx->shader->key.as_ls || ctx->shader->key.as_es);
7024
7025 /* Get the pointer to rw buffers. */
7026 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7027 ptr[1] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS_HI);
7028 list = lp_build_gather_values(&ctx->gallivm, ptr, 2);
7029 list = LLVMBuildBitCast(ctx->ac.builder, list, ctx->i64, "");
7030 list = LLVMBuildIntToPtr(ctx->ac.builder, list,
7031 ac_array_in_const_addr_space(ctx->v4i32), "");
7032 return list;
7033 }
7034
7035 /**
7036 * Build the vertex shader prolog function.
7037 *
7038 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7039 * All inputs are returned unmodified. The vertex load indices are
7040 * stored after them, which will be used by the API VS for fetching inputs.
7041 *
7042 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7043 * input_v0,
7044 * input_v1,
7045 * input_v2,
7046 * input_v3,
7047 * (VertexID + BaseVertex),
7048 * (InstanceID + StartInstance),
7049 * (InstanceID / 2 + StartInstance)
7050 */
7051 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7052 union si_shader_part_key *key)
7053 {
7054 struct si_function_info fninfo;
7055 LLVMTypeRef *returns;
7056 LLVMValueRef ret, func;
7057 int num_returns, i;
7058 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
7059 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
7060 LLVMValueRef input_vgprs[9];
7061 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
7062 num_input_vgprs;
7063 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
7064
7065 si_init_function_info(&fninfo);
7066
7067 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7068 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
7069 sizeof(LLVMTypeRef));
7070 num_returns = 0;
7071
7072 /* Declare input and output SGPRs. */
7073 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7074 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7075 returns[num_returns++] = ctx->i32;
7076 }
7077
7078 /* Preloaded VGPRs (outputs must be floats) */
7079 for (i = 0; i < num_input_vgprs; i++) {
7080 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
7081 returns[num_returns++] = ctx->f32;
7082 }
7083
7084 /* Vertex load indices. */
7085 for (i = 0; i <= key->vs_prolog.last_input; i++)
7086 returns[num_returns++] = ctx->f32;
7087
7088 /* Create the function. */
7089 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
7090 func = ctx->main_fn;
7091
7092 if (key->vs_prolog.num_merged_next_stage_vgprs) {
7093 if (!key->vs_prolog.is_monolithic)
7094 si_init_exec_from_input(ctx, 3, 0);
7095
7096 if (key->vs_prolog.as_ls &&
7097 ctx->screen->has_ls_vgpr_init_bug) {
7098 /* If there are no HS threads, SPI loads the LS VGPRs
7099 * starting at VGPR 0. Shift them back to where they
7100 * belong.
7101 */
7102 LLVMValueRef has_hs_threads =
7103 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
7104 unpack_param(ctx, 3, 8, 8),
7105 ctx->i32_0, "");
7106
7107 for (i = 4; i > 0; --i) {
7108 input_vgprs[i + 1] =
7109 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
7110 input_vgprs[i + 1],
7111 input_vgprs[i - 1], "");
7112 }
7113 }
7114 }
7115
7116 ctx->abi.vertex_id = input_vgprs[first_vs_vgpr];
7117 ctx->abi.instance_id = input_vgprs[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)];
7118
7119 /* Copy inputs to outputs. This should be no-op, as the registers match,
7120 * but it will prevent the compiler from overwriting them unintentionally.
7121 */
7122 ret = ctx->return_value;
7123 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7124 LLVMValueRef p = LLVMGetParam(func, i);
7125 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7126 }
7127 for (i = 0; i < num_input_vgprs; i++) {
7128 LLVMValueRef p = input_vgprs[i];
7129 p = ac_to_float(&ctx->ac, p);
7130 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
7131 key->vs_prolog.num_input_sgprs + i, "");
7132 }
7133
7134 /* Compute vertex load indices from instance divisors. */
7135 LLVMValueRef instance_divisor_constbuf = NULL;
7136
7137 if (key->vs_prolog.states.instance_divisor_is_fetched) {
7138 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7139 LLVMValueRef buf_index =
7140 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
7141 instance_divisor_constbuf =
7142 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
7143 }
7144
7145 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7146 bool divisor_is_one =
7147 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
7148 bool divisor_is_fetched =
7149 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
7150 LLVMValueRef index;
7151
7152 if (divisor_is_one || divisor_is_fetched) {
7153 LLVMValueRef divisor = ctx->i32_1;
7154
7155 if (divisor_is_fetched) {
7156 divisor = buffer_load_const(ctx, instance_divisor_constbuf,
7157 LLVMConstInt(ctx->i32, i * 4, 0));
7158 divisor = ac_to_integer(&ctx->ac, divisor);
7159 }
7160
7161 /* InstanceID / Divisor + StartInstance */
7162 index = get_instance_index_for_fetch(ctx,
7163 user_sgpr_base +
7164 SI_SGPR_START_INSTANCE,
7165 divisor);
7166 } else {
7167 /* VertexID + BaseVertex */
7168 index = LLVMBuildAdd(ctx->ac.builder,
7169 ctx->abi.vertex_id,
7170 LLVMGetParam(func, user_sgpr_base +
7171 SI_SGPR_BASE_VERTEX), "");
7172 }
7173
7174 index = ac_to_float(&ctx->ac, index);
7175 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7176 fninfo.num_params + i, "");
7177 }
7178
7179 si_llvm_build_ret(ctx, ret);
7180 }
7181
7182 static bool si_get_vs_prolog(struct si_screen *sscreen,
7183 LLVMTargetMachineRef tm,
7184 struct si_shader *shader,
7185 struct pipe_debug_callback *debug,
7186 struct si_shader *main_part,
7187 const struct si_vs_prolog_bits *key)
7188 {
7189 struct si_shader_selector *vs = main_part->selector;
7190
7191 if (!si_vs_needs_prolog(vs, key))
7192 return true;
7193
7194 /* Get the prolog. */
7195 union si_shader_part_key prolog_key;
7196 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7197 key, shader, &prolog_key);
7198
7199 shader->prolog =
7200 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7201 PIPE_SHADER_VERTEX, true, &prolog_key, tm,
7202 debug, si_build_vs_prolog_function,
7203 "Vertex Shader Prolog");
7204 return shader->prolog != NULL;
7205 }
7206
7207 /**
7208 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7209 */
7210 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7211 LLVMTargetMachineRef tm,
7212 struct si_shader *shader,
7213 struct pipe_debug_callback *debug)
7214 {
7215 return si_get_vs_prolog(sscreen, tm, shader, debug, shader,
7216 &shader->key.part.vs.prolog);
7217 }
7218
7219 /**
7220 * Compile the TCS epilog function. This writes tesselation factors to memory
7221 * based on the output primitive type of the tesselator (determined by TES).
7222 */
7223 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7224 union si_shader_part_key *key)
7225 {
7226 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7227 struct si_function_info fninfo;
7228 LLVMValueRef func;
7229
7230 si_init_function_info(&fninfo);
7231
7232 if (ctx->screen->info.chip_class >= GFX9) {
7233 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7234 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7235 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7236 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7237 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7238 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7239 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7240 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7241 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7242 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7243 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7244 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7245 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7246 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7247 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7248 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7249 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7250 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7251 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7252 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7253 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7254 } else {
7255 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7256 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7257 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7258 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7259 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7260 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7261 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7262 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7263 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7264 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7265 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7266 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7267 }
7268
7269 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7270 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7271 unsigned tess_factors_idx =
7272 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7273 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7274 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7275
7276 for (unsigned i = 0; i < 6; i++)
7277 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7278
7279 /* Create the function. */
7280 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7281 ctx->screen->info.chip_class >= CIK ? 128 : 64);
7282 ac_declare_lds_as_pointer(&ctx->ac);
7283 func = ctx->main_fn;
7284
7285 LLVMValueRef invoc0_tess_factors[6];
7286 for (unsigned i = 0; i < 6; i++)
7287 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7288
7289 si_write_tess_factors(bld_base,
7290 LLVMGetParam(func, tess_factors_idx),
7291 LLVMGetParam(func, tess_factors_idx + 1),
7292 LLVMGetParam(func, tess_factors_idx + 2),
7293 invoc0_tess_factors, invoc0_tess_factors + 4);
7294
7295 LLVMBuildRetVoid(ctx->ac.builder);
7296 }
7297
7298 /**
7299 * Select and compile (or reuse) TCS parts (epilog).
7300 */
7301 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7302 LLVMTargetMachineRef tm,
7303 struct si_shader *shader,
7304 struct pipe_debug_callback *debug)
7305 {
7306 if (sscreen->info.chip_class >= GFX9) {
7307 struct si_shader *ls_main_part =
7308 shader->key.part.tcs.ls->main_shader_part_ls;
7309
7310 if (!si_get_vs_prolog(sscreen, tm, shader, debug, ls_main_part,
7311 &shader->key.part.tcs.ls_prolog))
7312 return false;
7313
7314 shader->previous_stage = ls_main_part;
7315 }
7316
7317 /* Get the epilog. */
7318 union si_shader_part_key epilog_key;
7319 memset(&epilog_key, 0, sizeof(epilog_key));
7320 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7321
7322 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7323 PIPE_SHADER_TESS_CTRL, false,
7324 &epilog_key, tm, debug,
7325 si_build_tcs_epilog_function,
7326 "Tessellation Control Shader Epilog");
7327 return shader->epilog != NULL;
7328 }
7329
7330 /**
7331 * Select and compile (or reuse) GS parts (prolog).
7332 */
7333 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7334 LLVMTargetMachineRef tm,
7335 struct si_shader *shader,
7336 struct pipe_debug_callback *debug)
7337 {
7338 if (sscreen->info.chip_class >= GFX9) {
7339 struct si_shader *es_main_part =
7340 shader->key.part.gs.es->main_shader_part_es;
7341
7342 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7343 !si_get_vs_prolog(sscreen, tm, shader, debug, es_main_part,
7344 &shader->key.part.gs.vs_prolog))
7345 return false;
7346
7347 shader->previous_stage = es_main_part;
7348 }
7349
7350 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7351 return true;
7352
7353 union si_shader_part_key prolog_key;
7354 memset(&prolog_key, 0, sizeof(prolog_key));
7355 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7356
7357 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7358 PIPE_SHADER_GEOMETRY, true,
7359 &prolog_key, tm, debug,
7360 si_build_gs_prolog_function,
7361 "Geometry Shader Prolog");
7362 return shader->prolog2 != NULL;
7363 }
7364
7365 /**
7366 * Build the pixel shader prolog function. This handles:
7367 * - two-side color selection and interpolation
7368 * - overriding interpolation parameters for the API PS
7369 * - polygon stippling
7370 *
7371 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7372 * overriden by other states. (e.g. per-sample interpolation)
7373 * Interpolated colors are stored after the preloaded VGPRs.
7374 */
7375 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7376 union si_shader_part_key *key)
7377 {
7378 struct si_function_info fninfo;
7379 LLVMValueRef ret, func;
7380 int num_returns, i, num_color_channels;
7381
7382 assert(si_need_ps_prolog(key));
7383
7384 si_init_function_info(&fninfo);
7385
7386 /* Declare inputs. */
7387 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7388 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7389
7390 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7391 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7392
7393 /* Declare outputs (same as inputs + add colors if needed) */
7394 num_returns = fninfo.num_params;
7395 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7396 for (i = 0; i < num_color_channels; i++)
7397 fninfo.types[num_returns++] = ctx->f32;
7398
7399 /* Create the function. */
7400 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7401 &fninfo, 0);
7402 func = ctx->main_fn;
7403
7404 /* Copy inputs to outputs. This should be no-op, as the registers match,
7405 * but it will prevent the compiler from overwriting them unintentionally.
7406 */
7407 ret = ctx->return_value;
7408 for (i = 0; i < fninfo.num_params; i++) {
7409 LLVMValueRef p = LLVMGetParam(func, i);
7410 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7411 }
7412
7413 /* Polygon stippling. */
7414 if (key->ps_prolog.states.poly_stipple) {
7415 /* POS_FIXED_PT is always last. */
7416 unsigned pos = key->ps_prolog.num_input_sgprs +
7417 key->ps_prolog.num_input_vgprs - 1;
7418 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7419
7420 si_llvm_emit_polygon_stipple(ctx, list, pos);
7421 }
7422
7423 if (key->ps_prolog.states.bc_optimize_for_persp ||
7424 key->ps_prolog.states.bc_optimize_for_linear) {
7425 unsigned i, base = key->ps_prolog.num_input_sgprs;
7426 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7427
7428 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7429 * The hw doesn't compute CENTROID if the whole wave only
7430 * contains fully-covered quads.
7431 *
7432 * PRIM_MASK is after user SGPRs.
7433 */
7434 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7435 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7436 LLVMConstInt(ctx->i32, 31, 0), "");
7437 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7438 ctx->i1, "");
7439
7440 if (key->ps_prolog.states.bc_optimize_for_persp) {
7441 /* Read PERSP_CENTER. */
7442 for (i = 0; i < 2; i++)
7443 center[i] = LLVMGetParam(func, base + 2 + i);
7444 /* Read PERSP_CENTROID. */
7445 for (i = 0; i < 2; i++)
7446 centroid[i] = LLVMGetParam(func, base + 4 + i);
7447 /* Select PERSP_CENTROID. */
7448 for (i = 0; i < 2; i++) {
7449 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7450 center[i], centroid[i], "");
7451 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7452 tmp, base + 4 + i, "");
7453 }
7454 }
7455 if (key->ps_prolog.states.bc_optimize_for_linear) {
7456 /* Read LINEAR_CENTER. */
7457 for (i = 0; i < 2; i++)
7458 center[i] = LLVMGetParam(func, base + 8 + i);
7459 /* Read LINEAR_CENTROID. */
7460 for (i = 0; i < 2; i++)
7461 centroid[i] = LLVMGetParam(func, base + 10 + i);
7462 /* Select LINEAR_CENTROID. */
7463 for (i = 0; i < 2; i++) {
7464 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7465 center[i], centroid[i], "");
7466 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7467 tmp, base + 10 + i, "");
7468 }
7469 }
7470 }
7471
7472 /* Force per-sample interpolation. */
7473 if (key->ps_prolog.states.force_persp_sample_interp) {
7474 unsigned i, base = key->ps_prolog.num_input_sgprs;
7475 LLVMValueRef persp_sample[2];
7476
7477 /* Read PERSP_SAMPLE. */
7478 for (i = 0; i < 2; i++)
7479 persp_sample[i] = LLVMGetParam(func, base + i);
7480 /* Overwrite PERSP_CENTER. */
7481 for (i = 0; i < 2; i++)
7482 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7483 persp_sample[i], base + 2 + i, "");
7484 /* Overwrite PERSP_CENTROID. */
7485 for (i = 0; i < 2; i++)
7486 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7487 persp_sample[i], base + 4 + i, "");
7488 }
7489 if (key->ps_prolog.states.force_linear_sample_interp) {
7490 unsigned i, base = key->ps_prolog.num_input_sgprs;
7491 LLVMValueRef linear_sample[2];
7492
7493 /* Read LINEAR_SAMPLE. */
7494 for (i = 0; i < 2; i++)
7495 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7496 /* Overwrite LINEAR_CENTER. */
7497 for (i = 0; i < 2; i++)
7498 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7499 linear_sample[i], base + 8 + i, "");
7500 /* Overwrite LINEAR_CENTROID. */
7501 for (i = 0; i < 2; i++)
7502 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7503 linear_sample[i], base + 10 + i, "");
7504 }
7505
7506 /* Force center interpolation. */
7507 if (key->ps_prolog.states.force_persp_center_interp) {
7508 unsigned i, base = key->ps_prolog.num_input_sgprs;
7509 LLVMValueRef persp_center[2];
7510
7511 /* Read PERSP_CENTER. */
7512 for (i = 0; i < 2; i++)
7513 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7514 /* Overwrite PERSP_SAMPLE. */
7515 for (i = 0; i < 2; i++)
7516 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7517 persp_center[i], base + i, "");
7518 /* Overwrite PERSP_CENTROID. */
7519 for (i = 0; i < 2; i++)
7520 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7521 persp_center[i], base + 4 + i, "");
7522 }
7523 if (key->ps_prolog.states.force_linear_center_interp) {
7524 unsigned i, base = key->ps_prolog.num_input_sgprs;
7525 LLVMValueRef linear_center[2];
7526
7527 /* Read LINEAR_CENTER. */
7528 for (i = 0; i < 2; i++)
7529 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7530 /* Overwrite LINEAR_SAMPLE. */
7531 for (i = 0; i < 2; i++)
7532 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7533 linear_center[i], base + 6 + i, "");
7534 /* Overwrite LINEAR_CENTROID. */
7535 for (i = 0; i < 2; i++)
7536 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7537 linear_center[i], base + 10 + i, "");
7538 }
7539
7540 /* Interpolate colors. */
7541 unsigned color_out_idx = 0;
7542 for (i = 0; i < 2; i++) {
7543 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7544 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7545 key->ps_prolog.face_vgpr_index;
7546 LLVMValueRef interp[2], color[4];
7547 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7548
7549 if (!writemask)
7550 continue;
7551
7552 /* If the interpolation qualifier is not CONSTANT (-1). */
7553 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7554 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7555 key->ps_prolog.color_interp_vgpr_index[i];
7556
7557 /* Get the (i,j) updated by bc_optimize handling. */
7558 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7559 interp_vgpr, "");
7560 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7561 interp_vgpr + 1, "");
7562 interp_ij = lp_build_gather_values(&ctx->gallivm, interp, 2);
7563 }
7564
7565 /* Use the absolute location of the input. */
7566 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7567
7568 if (key->ps_prolog.states.color_two_side) {
7569 face = LLVMGetParam(func, face_vgpr);
7570 face = ac_to_integer(&ctx->ac, face);
7571 }
7572
7573 interp_fs_input(ctx,
7574 key->ps_prolog.color_attr_index[i],
7575 TGSI_SEMANTIC_COLOR, i,
7576 key->ps_prolog.num_interp_inputs,
7577 key->ps_prolog.colors_read, interp_ij,
7578 prim_mask, face, color);
7579
7580 while (writemask) {
7581 unsigned chan = u_bit_scan(&writemask);
7582 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7583 fninfo.num_params + color_out_idx++, "");
7584 }
7585 }
7586
7587 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7588 * says:
7589 *
7590 * "When per-sample shading is active due to the use of a fragment
7591 * input qualified by sample or due to the use of the gl_SampleID
7592 * or gl_SamplePosition variables, only the bit for the current
7593 * sample is set in gl_SampleMaskIn. When state specifies multiple
7594 * fragment shader invocations for a given fragment, the sample
7595 * mask for any single fragment shader invocation may specify a
7596 * subset of the covered samples for the fragment. In this case,
7597 * the bit corresponding to each covered sample will be set in
7598 * exactly one fragment shader invocation."
7599 *
7600 * The samplemask loaded by hardware is always the coverage of the
7601 * entire pixel/fragment, so mask bits out based on the sample ID.
7602 */
7603 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7604 /* The bit pattern matches that used by fixed function fragment
7605 * processing. */
7606 static const uint16_t ps_iter_masks[] = {
7607 0xffff, /* not used */
7608 0x5555,
7609 0x1111,
7610 0x0101,
7611 0x0001,
7612 };
7613 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7614
7615 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7616 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7617 key->ps_prolog.ancillary_vgpr_index;
7618 LLVMValueRef sampleid = unpack_param(ctx, ancillary_vgpr, 8, 4);
7619 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7620
7621 samplemask = ac_to_integer(&ctx->ac, samplemask);
7622 samplemask = LLVMBuildAnd(
7623 ctx->ac.builder,
7624 samplemask,
7625 LLVMBuildShl(ctx->ac.builder,
7626 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7627 sampleid, ""),
7628 "");
7629 samplemask = ac_to_float(&ctx->ac, samplemask);
7630
7631 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7632 ancillary_vgpr + 1, "");
7633 }
7634
7635 /* Tell LLVM to insert WQM instruction sequence when needed. */
7636 if (key->ps_prolog.wqm) {
7637 LLVMAddTargetDependentFunctionAttr(func,
7638 "amdgpu-ps-wqm-outputs", "");
7639 }
7640
7641 si_llvm_build_ret(ctx, ret);
7642 }
7643
7644 /**
7645 * Build the pixel shader epilog function. This handles everything that must be
7646 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7647 */
7648 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7649 union si_shader_part_key *key)
7650 {
7651 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7652 struct si_function_info fninfo;
7653 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7654 int i;
7655 struct si_ps_exports exp = {};
7656
7657 si_init_function_info(&fninfo);
7658
7659 /* Declare input SGPRs. */
7660 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7661 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7662 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7663 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7664 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7665
7666 /* Declare input VGPRs. */
7667 unsigned required_num_params =
7668 fninfo.num_sgpr_params +
7669 util_bitcount(key->ps_epilog.colors_written) * 4 +
7670 key->ps_epilog.writes_z +
7671 key->ps_epilog.writes_stencil +
7672 key->ps_epilog.writes_samplemask;
7673
7674 required_num_params = MAX2(required_num_params,
7675 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7676
7677 while (fninfo.num_params < required_num_params)
7678 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7679
7680 /* Create the function. */
7681 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7682 /* Disable elimination of unused inputs. */
7683 si_llvm_add_attribute(ctx->main_fn,
7684 "InitialPSInputAddr", 0xffffff);
7685
7686 /* Process colors. */
7687 unsigned vgpr = fninfo.num_sgpr_params;
7688 unsigned colors_written = key->ps_epilog.colors_written;
7689 int last_color_export = -1;
7690
7691 /* Find the last color export. */
7692 if (!key->ps_epilog.writes_z &&
7693 !key->ps_epilog.writes_stencil &&
7694 !key->ps_epilog.writes_samplemask) {
7695 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7696
7697 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7698 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7699 /* Just set this if any of the colorbuffers are enabled. */
7700 if (spi_format &
7701 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7702 last_color_export = 0;
7703 } else {
7704 for (i = 0; i < 8; i++)
7705 if (colors_written & (1 << i) &&
7706 (spi_format >> (i * 4)) & 0xf)
7707 last_color_export = i;
7708 }
7709 }
7710
7711 while (colors_written) {
7712 LLVMValueRef color[4];
7713 int mrt = u_bit_scan(&colors_written);
7714
7715 for (i = 0; i < 4; i++)
7716 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7717
7718 si_export_mrt_color(bld_base, color, mrt,
7719 fninfo.num_params - 1,
7720 mrt == last_color_export, &exp);
7721 }
7722
7723 /* Process depth, stencil, samplemask. */
7724 if (key->ps_epilog.writes_z)
7725 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7726 if (key->ps_epilog.writes_stencil)
7727 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7728 if (key->ps_epilog.writes_samplemask)
7729 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7730
7731 if (depth || stencil || samplemask)
7732 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7733 else if (last_color_export == -1)
7734 si_export_null(bld_base);
7735
7736 if (exp.num)
7737 si_emit_ps_exports(ctx, &exp);
7738
7739 /* Compile. */
7740 LLVMBuildRetVoid(ctx->ac.builder);
7741 }
7742
7743 /**
7744 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7745 */
7746 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7747 LLVMTargetMachineRef tm,
7748 struct si_shader *shader,
7749 struct pipe_debug_callback *debug)
7750 {
7751 union si_shader_part_key prolog_key;
7752 union si_shader_part_key epilog_key;
7753
7754 /* Get the prolog. */
7755 si_get_ps_prolog_key(shader, &prolog_key, true);
7756
7757 /* The prolog is a no-op if these aren't set. */
7758 if (si_need_ps_prolog(&prolog_key)) {
7759 shader->prolog =
7760 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7761 PIPE_SHADER_FRAGMENT, true,
7762 &prolog_key, tm, debug,
7763 si_build_ps_prolog_function,
7764 "Fragment Shader Prolog");
7765 if (!shader->prolog)
7766 return false;
7767 }
7768
7769 /* Get the epilog. */
7770 si_get_ps_epilog_key(shader, &epilog_key);
7771
7772 shader->epilog =
7773 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7774 PIPE_SHADER_FRAGMENT, false,
7775 &epilog_key, tm, debug,
7776 si_build_ps_epilog_function,
7777 "Fragment Shader Epilog");
7778 if (!shader->epilog)
7779 return false;
7780
7781 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7782 if (shader->key.part.ps.prolog.poly_stipple) {
7783 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7784 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7785 }
7786
7787 /* Set up the enable bits for per-sample shading if needed. */
7788 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7789 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7790 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7791 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7792 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7793 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7794 }
7795 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7796 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7797 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7798 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7799 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7800 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7801 }
7802 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7803 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7804 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7805 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7806 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7807 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7808 }
7809 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7810 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7811 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7812 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7813 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7814 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7815 }
7816
7817 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7818 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7819 !(shader->config.spi_ps_input_ena & 0xf)) {
7820 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7821 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7822 }
7823
7824 /* At least one pair of interpolation weights must be enabled. */
7825 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7826 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7827 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7828 }
7829
7830 /* Samplemask fixup requires the sample ID. */
7831 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7832 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7833 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7834 }
7835
7836 /* The sample mask input is always enabled, because the API shader always
7837 * passes it through to the epilog. Disable it here if it's unused.
7838 */
7839 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7840 !shader->selector->info.reads_samplemask)
7841 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7842
7843 return true;
7844 }
7845
7846 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7847 unsigned *lds_size)
7848 {
7849 /* SPI barrier management bug:
7850 * Make sure we have at least 4k of LDS in use to avoid the bug.
7851 * It applies to workgroup sizes of more than one wavefront.
7852 */
7853 if (sscreen->info.family == CHIP_BONAIRE ||
7854 sscreen->info.family == CHIP_KABINI ||
7855 sscreen->info.family == CHIP_MULLINS)
7856 *lds_size = MAX2(*lds_size, 8);
7857 }
7858
7859 static void si_fix_resource_usage(struct si_screen *sscreen,
7860 struct si_shader *shader)
7861 {
7862 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7863
7864 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7865
7866 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7867 si_get_max_workgroup_size(shader) > 64) {
7868 si_multiwave_lds_size_workaround(sscreen,
7869 &shader->config.lds_size);
7870 }
7871 }
7872
7873 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7874 struct si_shader *shader,
7875 struct pipe_debug_callback *debug)
7876 {
7877 struct si_shader_selector *sel = shader->selector;
7878 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7879 int r;
7880
7881 /* LS, ES, VS are compiled on demand if the main part hasn't been
7882 * compiled for that stage.
7883 *
7884 * Vertex shaders are compiled on demand when a vertex fetch
7885 * workaround must be applied.
7886 */
7887 if (shader->is_monolithic) {
7888 /* Monolithic shader (compiled as a whole, has many variants,
7889 * may take a long time to compile).
7890 */
7891 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7892 if (r)
7893 return r;
7894 } else {
7895 /* The shader consists of several parts:
7896 *
7897 * - the middle part is the user shader, it has 1 variant only
7898 * and it was compiled during the creation of the shader
7899 * selector
7900 * - the prolog part is inserted at the beginning
7901 * - the epilog part is inserted at the end
7902 *
7903 * The prolog and epilog have many (but simple) variants.
7904 *
7905 * Starting with gfx9, geometry and tessellation control
7906 * shaders also contain the prolog and user shader parts of
7907 * the previous shader stage.
7908 */
7909
7910 if (!mainp)
7911 return -1;
7912
7913 /* Copy the compiled TGSI shader data over. */
7914 shader->is_binary_shared = true;
7915 shader->binary = mainp->binary;
7916 shader->config = mainp->config;
7917 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7918 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7919 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7920 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
7921 memcpy(shader->info.vs_output_param_offset,
7922 mainp->info.vs_output_param_offset,
7923 sizeof(mainp->info.vs_output_param_offset));
7924 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7925 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7926 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7927
7928 /* Select prologs and/or epilogs. */
7929 switch (sel->type) {
7930 case PIPE_SHADER_VERTEX:
7931 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7932 return -1;
7933 break;
7934 case PIPE_SHADER_TESS_CTRL:
7935 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7936 return -1;
7937 break;
7938 case PIPE_SHADER_TESS_EVAL:
7939 break;
7940 case PIPE_SHADER_GEOMETRY:
7941 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
7942 return -1;
7943 break;
7944 case PIPE_SHADER_FRAGMENT:
7945 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7946 return -1;
7947
7948 /* Make sure we have at least as many VGPRs as there
7949 * are allocated inputs.
7950 */
7951 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7952 shader->info.num_input_vgprs);
7953 break;
7954 }
7955
7956 /* Update SGPR and VGPR counts. */
7957 if (shader->prolog) {
7958 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7959 shader->prolog->config.num_sgprs);
7960 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7961 shader->prolog->config.num_vgprs);
7962 }
7963 if (shader->previous_stage) {
7964 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7965 shader->previous_stage->config.num_sgprs);
7966 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7967 shader->previous_stage->config.num_vgprs);
7968 shader->config.spilled_sgprs =
7969 MAX2(shader->config.spilled_sgprs,
7970 shader->previous_stage->config.spilled_sgprs);
7971 shader->config.spilled_vgprs =
7972 MAX2(shader->config.spilled_vgprs,
7973 shader->previous_stage->config.spilled_vgprs);
7974 shader->config.private_mem_vgprs =
7975 MAX2(shader->config.private_mem_vgprs,
7976 shader->previous_stage->config.private_mem_vgprs);
7977 shader->config.scratch_bytes_per_wave =
7978 MAX2(shader->config.scratch_bytes_per_wave,
7979 shader->previous_stage->config.scratch_bytes_per_wave);
7980 shader->info.uses_instanceid |=
7981 shader->previous_stage->info.uses_instanceid;
7982 }
7983 if (shader->prolog2) {
7984 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7985 shader->prolog2->config.num_sgprs);
7986 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7987 shader->prolog2->config.num_vgprs);
7988 }
7989 if (shader->epilog) {
7990 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7991 shader->epilog->config.num_sgprs);
7992 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7993 shader->epilog->config.num_vgprs);
7994 }
7995 si_calculate_max_simd_waves(shader);
7996 }
7997
7998 si_fix_resource_usage(sscreen, shader);
7999 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8000 stderr, true);
8001
8002 /* Upload. */
8003 r = si_shader_binary_upload(sscreen, shader);
8004 if (r) {
8005 fprintf(stderr, "LLVM failed to upload shader\n");
8006 return r;
8007 }
8008
8009 return 0;
8010 }
8011
8012 void si_shader_destroy(struct si_shader *shader)
8013 {
8014 if (shader->scratch_bo)
8015 r600_resource_reference(&shader->scratch_bo, NULL);
8016
8017 r600_resource_reference(&shader->bo, NULL);
8018
8019 if (!shader->is_binary_shared)
8020 ac_shader_binary_clean(&shader->binary);
8021
8022 free(shader->shader_log);
8023 }