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[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "gallivm/lp_bld_const.h"
25 #include "gallivm/lp_bld_gather.h"
26 #include "gallivm/lp_bld_intr.h"
27 #include "gallivm/lp_bld_logic.h"
28 #include "gallivm/lp_bld_arit.h"
29 #include "gallivm/lp_bld_flow.h"
30 #include "gallivm/lp_bld_misc.h"
31 #include "util/u_memory.h"
32 #include "util/u_string.h"
33 #include "tgsi/tgsi_build.h"
34 #include "tgsi/tgsi_util.h"
35 #include "tgsi/tgsi_dump.h"
36
37 #include "ac_binary.h"
38 #include "ac_llvm_util.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41 #include "si_shader_internal.h"
42 #include "si_pipe.h"
43 #include "sid.h"
44
45 #include "compiler/nir/nir.h"
46
47 static const char *scratch_rsrc_dword0_symbol =
48 "SCRATCH_RSRC_DWORD0";
49
50 static const char *scratch_rsrc_dword1_symbol =
51 "SCRATCH_RSRC_DWORD1";
52
53 struct si_shader_output_values
54 {
55 LLVMValueRef values[4];
56 unsigned semantic_name;
57 unsigned semantic_index;
58 ubyte vertex_stream[4];
59 };
60
61 /**
62 * Used to collect types and other info about arguments of the LLVM function
63 * before the function is created.
64 */
65 struct si_function_info {
66 LLVMTypeRef types[100];
67 LLVMValueRef *assign[100];
68 unsigned num_sgpr_params;
69 unsigned num_params;
70 };
71
72 enum si_arg_regfile {
73 ARG_SGPR,
74 ARG_VGPR
75 };
76
77 static void si_init_shader_ctx(struct si_shader_context *ctx,
78 struct si_screen *sscreen,
79 LLVMTargetMachineRef tm);
80
81 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
82 struct lp_build_tgsi_context *bld_base,
83 struct lp_build_emit_data *emit_data);
84
85 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
86 FILE *f);
87
88 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
89 union si_shader_part_key *key);
90 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
91 union si_shader_part_key *key);
92 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
93 union si_shader_part_key *key);
94 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
95 union si_shader_part_key *key);
96
97 /* Ideally pass the sample mask input to the PS epilog as v14, which
98 * is its usual location, so that the shader doesn't have to add v_mov.
99 */
100 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
101
102 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
103 LLVMTypeRef type)
104 {
105 if (type == ctx->ac.i64 || type == ctx->ac.f64)
106 return true;
107
108 return false;
109 }
110
111 static bool is_merged_shader(struct si_shader *shader)
112 {
113 if (shader->selector->screen->info.chip_class <= VI)
114 return false;
115
116 return shader->key.as_ls ||
117 shader->key.as_es ||
118 shader->selector->type == PIPE_SHADER_TESS_CTRL ||
119 shader->selector->type == PIPE_SHADER_GEOMETRY;
120 }
121
122 static void si_init_function_info(struct si_function_info *fninfo)
123 {
124 fninfo->num_params = 0;
125 fninfo->num_sgpr_params = 0;
126 }
127
128 static unsigned add_arg_assign(struct si_function_info *fninfo,
129 enum si_arg_regfile regfile, LLVMTypeRef type,
130 LLVMValueRef *assign)
131 {
132 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
133
134 unsigned idx = fninfo->num_params++;
135 assert(idx < ARRAY_SIZE(fninfo->types));
136
137 if (regfile == ARG_SGPR)
138 fninfo->num_sgpr_params = fninfo->num_params;
139
140 fninfo->types[idx] = type;
141 fninfo->assign[idx] = assign;
142 return idx;
143 }
144
145 static unsigned add_arg(struct si_function_info *fninfo,
146 enum si_arg_regfile regfile, LLVMTypeRef type)
147 {
148 return add_arg_assign(fninfo, regfile, type, NULL);
149 }
150
151 static void add_arg_assign_checked(struct si_function_info *fninfo,
152 enum si_arg_regfile regfile, LLVMTypeRef type,
153 LLVMValueRef *assign, unsigned idx)
154 {
155 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
156 assert(actual == idx);
157 }
158
159 static void add_arg_checked(struct si_function_info *fninfo,
160 enum si_arg_regfile regfile, LLVMTypeRef type,
161 unsigned idx)
162 {
163 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
164 }
165
166 /**
167 * Returns a unique index for a per-patch semantic name and index. The index
168 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
169 * can be calculated.
170 */
171 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
172 {
173 switch (semantic_name) {
174 case TGSI_SEMANTIC_TESSOUTER:
175 return 0;
176 case TGSI_SEMANTIC_TESSINNER:
177 return 1;
178 case TGSI_SEMANTIC_PATCH:
179 assert(index < 30);
180 return 2 + index;
181
182 default:
183 assert(!"invalid semantic name");
184 return 0;
185 }
186 }
187
188 /**
189 * Returns a unique index for a semantic name and index. The index must be
190 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
191 * calculated.
192 */
193 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
194 {
195 switch (semantic_name) {
196 case TGSI_SEMANTIC_POSITION:
197 return 0;
198 case TGSI_SEMANTIC_GENERIC:
199 /* Since some shader stages use the the highest used IO index
200 * to determine the size to allocate for inputs/outputs
201 * (in LDS, tess and GS rings). GENERIC should be placed right
202 * after POSITION to make that size as small as possible.
203 */
204 if (index < SI_MAX_IO_GENERIC)
205 return 1 + index;
206
207 assert(!"invalid generic index");
208 return 0;
209 case TGSI_SEMANTIC_PSIZE:
210 return SI_MAX_IO_GENERIC + 1;
211 case TGSI_SEMANTIC_CLIPDIST:
212 assert(index <= 1);
213 return SI_MAX_IO_GENERIC + 2 + index;
214 case TGSI_SEMANTIC_FOG:
215 return SI_MAX_IO_GENERIC + 4;
216 case TGSI_SEMANTIC_LAYER:
217 return SI_MAX_IO_GENERIC + 5;
218 case TGSI_SEMANTIC_VIEWPORT_INDEX:
219 return SI_MAX_IO_GENERIC + 6;
220 case TGSI_SEMANTIC_PRIMID:
221 return SI_MAX_IO_GENERIC + 7;
222 case TGSI_SEMANTIC_COLOR: /* these alias */
223 case TGSI_SEMANTIC_BCOLOR:
224 assert(index < 2);
225 return SI_MAX_IO_GENERIC + 8 + index;
226 case TGSI_SEMANTIC_TEXCOORD:
227 assert(index < 8);
228 assert(SI_MAX_IO_GENERIC + 10 + index < 64);
229 return SI_MAX_IO_GENERIC + 10 + index;
230 default:
231 assert(!"invalid semantic name");
232 return 0;
233 }
234 }
235
236 /**
237 * Get the value of a shader input parameter and extract a bitfield.
238 */
239 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
240 LLVMValueRef value, unsigned rshift,
241 unsigned bitwidth)
242 {
243 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
244 value = ac_to_integer(&ctx->ac, value);
245
246 if (rshift)
247 value = LLVMBuildLShr(ctx->ac.builder, value,
248 LLVMConstInt(ctx->i32, rshift, 0), "");
249
250 if (rshift + bitwidth < 32) {
251 unsigned mask = (1 << bitwidth) - 1;
252 value = LLVMBuildAnd(ctx->ac.builder, value,
253 LLVMConstInt(ctx->i32, mask, 0), "");
254 }
255
256 return value;
257 }
258
259 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
260 unsigned param, unsigned rshift,
261 unsigned bitwidth)
262 {
263 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
264
265 return unpack_llvm_param(ctx, value, rshift, bitwidth);
266 }
267
268 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
269 {
270 switch (ctx->type) {
271 case PIPE_SHADER_TESS_CTRL:
272 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
273
274 case PIPE_SHADER_TESS_EVAL:
275 return LLVMGetParam(ctx->main_fn,
276 ctx->param_tes_rel_patch_id);
277
278 default:
279 assert(0);
280 return NULL;
281 }
282 }
283
284 /* Tessellation shaders pass outputs to the next shader using LDS.
285 *
286 * LS outputs = TCS inputs
287 * TCS outputs = TES inputs
288 *
289 * The LDS layout is:
290 * - TCS inputs for patch 0
291 * - TCS inputs for patch 1
292 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
293 * - ...
294 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
295 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
296 * - TCS outputs for patch 1
297 * - Per-patch TCS outputs for patch 1
298 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
299 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
300 * - ...
301 *
302 * All three shaders VS(LS), TCS, TES share the same LDS space.
303 */
304
305 static LLVMValueRef
306 get_tcs_in_patch_stride(struct si_shader_context *ctx)
307 {
308 return unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
309 }
310
311 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
312 {
313 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
314
315 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
316 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
317
318 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
319 }
320
321 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
322 {
323 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
324
325 return LLVMConstInt(ctx->i32, stride, 0);
326 }
327
328 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
329 {
330 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
331 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
332
333 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
334 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
335 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
336 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
337 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
338 num_patch_outputs * 4;
339 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
340 }
341
342 static LLVMValueRef
343 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
344 {
345 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
346 unpack_param(ctx,
347 ctx->param_tcs_out_lds_offsets,
348 0, 16),
349 4);
350 }
351
352 static LLVMValueRef
353 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
354 {
355 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
356 unpack_param(ctx,
357 ctx->param_tcs_out_lds_offsets,
358 16, 16),
359 4);
360 }
361
362 static LLVMValueRef
363 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
364 {
365 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
366 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
367
368 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
369 }
370
371 static LLVMValueRef
372 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
373 {
374 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
375 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
376 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
377
378 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
379 LLVMBuildMul(ctx->ac.builder, patch_stride,
380 rel_patch_id, ""),
381 "");
382 }
383
384 static LLVMValueRef
385 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
386 {
387 LLVMValueRef patch0_patch_data_offset =
388 get_tcs_out_patch0_patch_data_offset(ctx);
389 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
390 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
391
392 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
393 LLVMBuildMul(ctx->ac.builder, patch_stride,
394 rel_patch_id, ""),
395 "");
396 }
397
398 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
399 {
400 unsigned tcs_out_vertices =
401 ctx->shader->selector ?
402 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
403
404 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
405 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
406 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
407
408 return unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
409 }
410
411 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
412 {
413 unsigned stride;
414
415 switch (ctx->type) {
416 case PIPE_SHADER_VERTEX:
417 stride = util_last_bit64(ctx->shader->selector->outputs_written);
418 return LLVMConstInt(ctx->i32, stride * 4, 0);
419
420 case PIPE_SHADER_TESS_CTRL:
421 if (ctx->screen->info.chip_class >= GFX9 &&
422 ctx->shader->is_monolithic) {
423 stride = util_last_bit64(ctx->shader->key.part.tcs.ls->outputs_written);
424 return LLVMConstInt(ctx->i32, stride * 4, 0);
425 }
426 return unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
427
428 default:
429 assert(0);
430 return NULL;
431 }
432 }
433
434 static LLVMValueRef get_instance_index_for_fetch(
435 struct si_shader_context *ctx,
436 unsigned param_start_instance, LLVMValueRef divisor)
437 {
438 LLVMValueRef result = ctx->abi.instance_id;
439
440 /* The division must be done before START_INSTANCE is added. */
441 if (divisor != ctx->i32_1)
442 result = LLVMBuildUDiv(ctx->ac.builder, result, divisor, "");
443
444 return LLVMBuildAdd(ctx->ac.builder, result,
445 LLVMGetParam(ctx->main_fn, param_start_instance), "");
446 }
447
448 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
449 * to float. */
450 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
451 LLVMValueRef vec4,
452 unsigned double_index)
453 {
454 LLVMBuilderRef builder = ctx->ac.builder;
455 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->ac.context);
456 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
457 LLVMVectorType(f64, 2), "");
458 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
459 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
460 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
461 }
462
463 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
464 LLVMValueRef i32, unsigned index)
465 {
466 assert(index <= 1);
467
468 if (index == 1)
469 return LLVMBuildAShr(ctx->ac.builder, i32,
470 LLVMConstInt(ctx->i32, 16, 0), "");
471
472 return LLVMBuildSExt(ctx->ac.builder,
473 LLVMBuildTrunc(ctx->ac.builder, i32,
474 ctx->ac.i16, ""),
475 ctx->i32, "");
476 }
477
478 void si_llvm_load_input_vs(
479 struct si_shader_context *ctx,
480 unsigned input_index,
481 LLVMValueRef out[4])
482 {
483 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
484 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
485
486 if (vs_blit_property) {
487 LLVMValueRef vertex_id = ctx->abi.vertex_id;
488 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
489 LLVMIntULE, vertex_id,
490 ctx->i32_1, "");
491 /* Use LLVMIntNE, because we have 3 vertices and only
492 * the middle one should use y2.
493 */
494 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
495 LLVMIntNE, vertex_id,
496 ctx->i32_1, "");
497
498 if (input_index == 0) {
499 /* Position: */
500 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
501 ctx->param_vs_blit_inputs);
502 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
503 ctx->param_vs_blit_inputs + 1);
504
505 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
506 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
507 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
508 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
509
510 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
511 x1, x2, "");
512 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
513 y1, y2, "");
514
515 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
516 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
517 out[2] = LLVMGetParam(ctx->main_fn,
518 ctx->param_vs_blit_inputs + 2);
519 out[3] = ctx->ac.f32_1;
520 return;
521 }
522
523 /* Color or texture coordinates: */
524 assert(input_index == 1);
525
526 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
527 for (int i = 0; i < 4; i++) {
528 out[i] = LLVMGetParam(ctx->main_fn,
529 ctx->param_vs_blit_inputs + 3 + i);
530 }
531 } else {
532 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
533 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
534 ctx->param_vs_blit_inputs + 3);
535 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
536 ctx->param_vs_blit_inputs + 4);
537 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
538 ctx->param_vs_blit_inputs + 5);
539 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
540 ctx->param_vs_blit_inputs + 6);
541
542 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
543 x1, x2, "");
544 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
545 y1, y2, "");
546 out[2] = LLVMGetParam(ctx->main_fn,
547 ctx->param_vs_blit_inputs + 7);
548 out[3] = LLVMGetParam(ctx->main_fn,
549 ctx->param_vs_blit_inputs + 8);
550 }
551 return;
552 }
553
554 unsigned chan;
555 unsigned fix_fetch;
556 unsigned num_fetches;
557 unsigned fetch_stride;
558 unsigned num_channels;
559
560 LLVMValueRef t_list_ptr;
561 LLVMValueRef t_offset;
562 LLVMValueRef t_list;
563 LLVMValueRef vertex_index;
564 LLVMValueRef input[3];
565
566 /* Load the T list */
567 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
568
569 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
570
571 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
572
573 vertex_index = LLVMGetParam(ctx->main_fn,
574 ctx->param_vertex_index0 +
575 input_index);
576
577 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
578
579 /* Do multiple loads for special formats. */
580 switch (fix_fetch) {
581 case SI_FIX_FETCH_RGB_64_FLOAT:
582 num_fetches = 3; /* 3 2-dword loads */
583 fetch_stride = 8;
584 num_channels = 2;
585 break;
586 case SI_FIX_FETCH_RGBA_64_FLOAT:
587 num_fetches = 2; /* 2 4-dword loads */
588 fetch_stride = 16;
589 num_channels = 4;
590 break;
591 case SI_FIX_FETCH_RGB_8:
592 case SI_FIX_FETCH_RGB_8_INT:
593 num_fetches = 3;
594 fetch_stride = 1;
595 num_channels = 1;
596 break;
597 case SI_FIX_FETCH_RGB_16:
598 case SI_FIX_FETCH_RGB_16_INT:
599 num_fetches = 3;
600 fetch_stride = 2;
601 num_channels = 1;
602 break;
603 default:
604 num_fetches = 1;
605 fetch_stride = 0;
606 num_channels = util_last_bit(info->input_usage_mask[input_index]);
607 }
608
609 for (unsigned i = 0; i < num_fetches; i++) {
610 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
611
612 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
613 vertex_index, voffset,
614 num_channels, false, true);
615 input[i] = ac_build_expand_to_vec4(&ctx->ac, input[i], num_channels);
616 }
617
618 /* Break up the vec4 into individual components */
619 for (chan = 0; chan < 4; chan++) {
620 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
621 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
622 input[0], llvm_chan, "");
623 }
624
625 switch (fix_fetch) {
626 case SI_FIX_FETCH_A2_SNORM:
627 case SI_FIX_FETCH_A2_SSCALED:
628 case SI_FIX_FETCH_A2_SINT: {
629 /* The hardware returns an unsigned value; convert it to a
630 * signed one.
631 */
632 LLVMValueRef tmp = out[3];
633 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
634
635 /* First, recover the sign-extended signed integer value. */
636 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
637 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
638 else
639 tmp = ac_to_integer(&ctx->ac, tmp);
640
641 /* For the integer-like cases, do a natural sign extension.
642 *
643 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
644 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
645 * exponent.
646 */
647 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
648 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
649 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
650 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
651
652 /* Convert back to the right type. */
653 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
654 LLVMValueRef clamp;
655 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
656 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
657 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
658 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
659 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
660 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
661 }
662
663 out[3] = tmp;
664 break;
665 }
666 case SI_FIX_FETCH_RGBA_32_UNORM:
667 case SI_FIX_FETCH_RGBX_32_UNORM:
668 for (chan = 0; chan < 4; chan++) {
669 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
670 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
671 out[chan], ctx->f32, "");
672 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
673 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
674 }
675 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
676 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
677 out[3] = LLVMConstReal(ctx->f32, 1);
678 break;
679 case SI_FIX_FETCH_RGBA_32_SNORM:
680 case SI_FIX_FETCH_RGBX_32_SNORM:
681 case SI_FIX_FETCH_RGBA_32_FIXED:
682 case SI_FIX_FETCH_RGBX_32_FIXED: {
683 double scale;
684 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
685 scale = 1.0 / 0x10000;
686 else
687 scale = 1.0 / INT_MAX;
688
689 for (chan = 0; chan < 4; chan++) {
690 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
691 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
692 out[chan], ctx->f32, "");
693 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
694 LLVMConstReal(ctx->f32, scale), "");
695 }
696 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
697 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
698 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
699 out[3] = LLVMConstReal(ctx->f32, 1);
700 break;
701 }
702 case SI_FIX_FETCH_RGBA_32_USCALED:
703 for (chan = 0; chan < 4; chan++) {
704 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
705 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
706 out[chan], ctx->f32, "");
707 }
708 break;
709 case SI_FIX_FETCH_RGBA_32_SSCALED:
710 for (chan = 0; chan < 4; chan++) {
711 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
712 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
713 out[chan], ctx->f32, "");
714 }
715 break;
716 case SI_FIX_FETCH_RG_64_FLOAT:
717 for (chan = 0; chan < 2; chan++)
718 out[chan] = extract_double_to_float(ctx, input[0], chan);
719
720 out[2] = LLVMConstReal(ctx->f32, 0);
721 out[3] = LLVMConstReal(ctx->f32, 1);
722 break;
723 case SI_FIX_FETCH_RGB_64_FLOAT:
724 for (chan = 0; chan < 3; chan++)
725 out[chan] = extract_double_to_float(ctx, input[chan], 0);
726
727 out[3] = LLVMConstReal(ctx->f32, 1);
728 break;
729 case SI_FIX_FETCH_RGBA_64_FLOAT:
730 for (chan = 0; chan < 4; chan++) {
731 out[chan] = extract_double_to_float(ctx, input[chan / 2],
732 chan % 2);
733 }
734 break;
735 case SI_FIX_FETCH_RGB_8:
736 case SI_FIX_FETCH_RGB_8_INT:
737 case SI_FIX_FETCH_RGB_16:
738 case SI_FIX_FETCH_RGB_16_INT:
739 for (chan = 0; chan < 3; chan++) {
740 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
741 input[chan],
742 ctx->i32_0, "");
743 }
744 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
745 fix_fetch == SI_FIX_FETCH_RGB_16) {
746 out[3] = LLVMConstReal(ctx->f32, 1);
747 } else {
748 out[3] = ac_to_float(&ctx->ac, ctx->i32_1);
749 }
750 break;
751 }
752 }
753
754 static void declare_input_vs(
755 struct si_shader_context *ctx,
756 unsigned input_index,
757 const struct tgsi_full_declaration *decl,
758 LLVMValueRef out[4])
759 {
760 si_llvm_load_input_vs(ctx, input_index, out);
761 }
762
763 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
764 unsigned swizzle)
765 {
766 if (swizzle > 0)
767 return ctx->i32_0;
768
769 switch (ctx->type) {
770 case PIPE_SHADER_VERTEX:
771 return LLVMGetParam(ctx->main_fn,
772 ctx->param_vs_prim_id);
773 case PIPE_SHADER_TESS_CTRL:
774 return ctx->abi.tcs_patch_id;
775 case PIPE_SHADER_TESS_EVAL:
776 return ctx->abi.tes_patch_id;
777 case PIPE_SHADER_GEOMETRY:
778 return ctx->abi.gs_prim_id;
779 default:
780 assert(0);
781 return ctx->i32_0;
782 }
783 }
784
785 /**
786 * Return the value of tgsi_ind_register for indexing.
787 * This is the indirect index with the constant offset added to it.
788 */
789 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
790 const struct tgsi_ind_register *ind,
791 unsigned addr_mul,
792 int rel_index)
793 {
794 LLVMValueRef result;
795
796 if (ind->File == TGSI_FILE_ADDRESS) {
797 result = ctx->addrs[ind->Index][ind->Swizzle];
798 result = LLVMBuildLoad(ctx->ac.builder, result, "");
799 } else {
800 struct tgsi_full_src_register src = {};
801
802 src.Register.File = ind->File;
803 src.Register.Index = ind->Index;
804
805 /* Set the second index to 0 for constants. */
806 if (ind->File == TGSI_FILE_CONSTANT)
807 src.Register.Dimension = 1;
808
809 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
810 TGSI_TYPE_SIGNED,
811 ind->Swizzle);
812 result = ac_to_integer(&ctx->ac, result);
813 }
814
815 if (addr_mul != 1)
816 result = LLVMBuildMul(ctx->ac.builder, result,
817 LLVMConstInt(ctx->i32, addr_mul, 0), "");
818 result = LLVMBuildAdd(ctx->ac.builder, result,
819 LLVMConstInt(ctx->i32, rel_index, 0), "");
820 return result;
821 }
822
823 /**
824 * Like si_get_indirect_index, but restricts the return value to a (possibly
825 * undefined) value inside [0..num).
826 */
827 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
828 const struct tgsi_ind_register *ind,
829 int rel_index, unsigned num)
830 {
831 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
832
833 return si_llvm_bound_index(ctx, result, num);
834 }
835
836 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
837 LLVMValueRef vertex_dw_stride,
838 LLVMValueRef base_addr,
839 LLVMValueRef vertex_index,
840 LLVMValueRef param_index,
841 unsigned input_index,
842 ubyte *name,
843 ubyte *index,
844 bool is_patch)
845 {
846 if (vertex_dw_stride) {
847 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
848 LLVMBuildMul(ctx->ac.builder, vertex_index,
849 vertex_dw_stride, ""), "");
850 }
851
852 if (param_index) {
853 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
854 LLVMBuildMul(ctx->ac.builder, param_index,
855 LLVMConstInt(ctx->i32, 4, 0), ""), "");
856 }
857
858 int param = is_patch ?
859 si_shader_io_get_unique_index_patch(name[input_index],
860 index[input_index]) :
861 si_shader_io_get_unique_index(name[input_index],
862 index[input_index]);
863
864 /* Add the base address of the element. */
865 return LLVMBuildAdd(ctx->ac.builder, base_addr,
866 LLVMConstInt(ctx->i32, param * 4, 0), "");
867 }
868
869 /**
870 * Calculate a dword address given an input or output register and a stride.
871 */
872 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
873 const struct tgsi_full_dst_register *dst,
874 const struct tgsi_full_src_register *src,
875 LLVMValueRef vertex_dw_stride,
876 LLVMValueRef base_addr)
877 {
878 struct tgsi_shader_info *info = &ctx->shader->selector->info;
879 ubyte *name, *index, *array_first;
880 int input_index;
881 struct tgsi_full_dst_register reg;
882 LLVMValueRef vertex_index = NULL;
883 LLVMValueRef ind_index = NULL;
884
885 /* Set the register description. The address computation is the same
886 * for sources and destinations. */
887 if (src) {
888 reg.Register.File = src->Register.File;
889 reg.Register.Index = src->Register.Index;
890 reg.Register.Indirect = src->Register.Indirect;
891 reg.Register.Dimension = src->Register.Dimension;
892 reg.Indirect = src->Indirect;
893 reg.Dimension = src->Dimension;
894 reg.DimIndirect = src->DimIndirect;
895 } else
896 reg = *dst;
897
898 /* If the register is 2-dimensional (e.g. an array of vertices
899 * in a primitive), calculate the base address of the vertex. */
900 if (reg.Register.Dimension) {
901 if (reg.Dimension.Indirect)
902 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
903 1, reg.Dimension.Index);
904 else
905 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
906 }
907
908 /* Get information about the register. */
909 if (reg.Register.File == TGSI_FILE_INPUT) {
910 name = info->input_semantic_name;
911 index = info->input_semantic_index;
912 array_first = info->input_array_first;
913 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
914 name = info->output_semantic_name;
915 index = info->output_semantic_index;
916 array_first = info->output_array_first;
917 } else {
918 assert(0);
919 return NULL;
920 }
921
922 if (reg.Register.Indirect) {
923 /* Add the relative address of the element. */
924 if (reg.Indirect.ArrayID)
925 input_index = array_first[reg.Indirect.ArrayID];
926 else
927 input_index = reg.Register.Index;
928
929 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
930 1, reg.Register.Index - input_index);
931 } else {
932 input_index = reg.Register.Index;
933 }
934
935 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
936 base_addr, vertex_index,
937 ind_index, input_index,
938 name, index,
939 !reg.Register.Dimension);
940 }
941
942 /* The offchip buffer layout for TCS->TES is
943 *
944 * - attribute 0 of patch 0 vertex 0
945 * - attribute 0 of patch 0 vertex 1
946 * - attribute 0 of patch 0 vertex 2
947 * ...
948 * - attribute 0 of patch 1 vertex 0
949 * - attribute 0 of patch 1 vertex 1
950 * ...
951 * - attribute 1 of patch 0 vertex 0
952 * - attribute 1 of patch 0 vertex 1
953 * ...
954 * - per patch attribute 0 of patch 0
955 * - per patch attribute 0 of patch 1
956 * ...
957 *
958 * Note that every attribute has 4 components.
959 */
960 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
961 LLVMValueRef rel_patch_id,
962 LLVMValueRef vertex_index,
963 LLVMValueRef param_index)
964 {
965 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
966 LLVMValueRef param_stride, constant16;
967
968 vertices_per_patch = get_num_tcs_out_vertices(ctx);
969 num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
970 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
971 num_patches, "");
972
973 constant16 = LLVMConstInt(ctx->i32, 16, 0);
974 if (vertex_index) {
975 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
976 vertices_per_patch, "");
977
978 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
979 vertex_index, "");
980
981 param_stride = total_vertices;
982 } else {
983 base_addr = rel_patch_id;
984 param_stride = num_patches;
985 }
986
987 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
988 LLVMBuildMul(ctx->ac.builder, param_index,
989 param_stride, ""), "");
990
991 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
992
993 if (!vertex_index) {
994 LLVMValueRef patch_data_offset =
995 unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
996
997 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
998 patch_data_offset, "");
999 }
1000 return base_addr;
1001 }
1002
1003 /* This is a generic helper that can be shared by the NIR and TGSI backends */
1004 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
1005 struct si_shader_context *ctx,
1006 LLVMValueRef vertex_index,
1007 LLVMValueRef param_index,
1008 unsigned param_base,
1009 ubyte *name,
1010 ubyte *index,
1011 bool is_patch)
1012 {
1013 unsigned param_index_base;
1014
1015 param_index_base = is_patch ?
1016 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
1017 si_shader_io_get_unique_index(name[param_base], index[param_base]);
1018
1019 if (param_index) {
1020 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1021 LLVMConstInt(ctx->i32, param_index_base, 0),
1022 "");
1023 } else {
1024 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
1025 }
1026
1027 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
1028 vertex_index, param_index);
1029 }
1030
1031 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
1032 struct si_shader_context *ctx,
1033 const struct tgsi_full_dst_register *dst,
1034 const struct tgsi_full_src_register *src)
1035 {
1036 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1037 ubyte *name, *index, *array_first;
1038 struct tgsi_full_src_register reg;
1039 LLVMValueRef vertex_index = NULL;
1040 LLVMValueRef param_index = NULL;
1041 unsigned param_base;
1042
1043 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
1044
1045 if (reg.Register.Dimension) {
1046
1047 if (reg.Dimension.Indirect)
1048 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
1049 1, reg.Dimension.Index);
1050 else
1051 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
1052 }
1053
1054 /* Get information about the register. */
1055 if (reg.Register.File == TGSI_FILE_INPUT) {
1056 name = info->input_semantic_name;
1057 index = info->input_semantic_index;
1058 array_first = info->input_array_first;
1059 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1060 name = info->output_semantic_name;
1061 index = info->output_semantic_index;
1062 array_first = info->output_array_first;
1063 } else {
1064 assert(0);
1065 return NULL;
1066 }
1067
1068 if (reg.Register.Indirect) {
1069 if (reg.Indirect.ArrayID)
1070 param_base = array_first[reg.Indirect.ArrayID];
1071 else
1072 param_base = reg.Register.Index;
1073
1074 param_index = si_get_indirect_index(ctx, &reg.Indirect,
1075 1, reg.Register.Index - param_base);
1076
1077 } else {
1078 param_base = reg.Register.Index;
1079 }
1080
1081 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1082 param_index, param_base,
1083 name, index, !reg.Register.Dimension);
1084 }
1085
1086 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
1087 LLVMTypeRef type, unsigned swizzle,
1088 LLVMValueRef buffer, LLVMValueRef offset,
1089 LLVMValueRef base, bool can_speculate)
1090 {
1091 struct si_shader_context *ctx = si_shader_context(bld_base);
1092 LLVMValueRef value, value2;
1093 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
1094
1095 if (swizzle == ~0) {
1096 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1097 0, 1, 0, can_speculate, false);
1098
1099 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1100 }
1101
1102 if (!llvm_type_is_64bit(ctx, type)) {
1103 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1104 0, 1, 0, can_speculate, false);
1105
1106 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1107 return LLVMBuildExtractElement(ctx->ac.builder, value,
1108 LLVMConstInt(ctx->i32, swizzle, 0), "");
1109 }
1110
1111 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1112 swizzle * 4, 1, 0, can_speculate, false);
1113
1114 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1115 swizzle * 4 + 4, 1, 0, can_speculate, false);
1116
1117 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1118 }
1119
1120 /**
1121 * Load from LDS.
1122 *
1123 * \param type output value type
1124 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1125 * \param dw_addr address in dwords
1126 */
1127 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1128 LLVMTypeRef type, unsigned swizzle,
1129 LLVMValueRef dw_addr)
1130 {
1131 struct si_shader_context *ctx = si_shader_context(bld_base);
1132 LLVMValueRef value;
1133
1134 if (swizzle == ~0) {
1135 LLVMValueRef values[TGSI_NUM_CHANNELS];
1136
1137 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1138 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1139
1140 return lp_build_gather_values(&ctx->gallivm, values,
1141 TGSI_NUM_CHANNELS);
1142 }
1143
1144 /* Split 64-bit loads. */
1145 if (llvm_type_is_64bit(ctx, type)) {
1146 LLVMValueRef lo, hi;
1147
1148 lo = lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1149 hi = lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1150 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1151 }
1152
1153 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1154 LLVMConstInt(ctx->i32, swizzle, 0));
1155
1156 value = ac_lds_load(&ctx->ac, dw_addr);
1157
1158 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1159 }
1160
1161 /**
1162 * Store to LDS.
1163 *
1164 * \param swizzle offset (typically 0..3)
1165 * \param dw_addr address in dwords
1166 * \param value value to store
1167 */
1168 static void lds_store(struct si_shader_context *ctx,
1169 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1170 LLVMValueRef value)
1171 {
1172 dw_addr = lp_build_add(&ctx->bld_base.uint_bld, dw_addr,
1173 LLVMConstInt(ctx->i32, dw_offset_imm, 0));
1174
1175 ac_lds_store(&ctx->ac, dw_addr, value);
1176 }
1177
1178 enum si_tess_ring {
1179 TCS_FACTOR_RING,
1180 TESS_OFFCHIP_RING_TCS,
1181 TESS_OFFCHIP_RING_TES,
1182 };
1183
1184 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
1185 enum si_tess_ring ring)
1186 {
1187 LLVMBuilderRef builder = ctx->ac.builder;
1188 unsigned param = ring == TESS_OFFCHIP_RING_TES ? ctx->param_tes_offchip_addr :
1189 ctx->param_tcs_out_lds_layout;
1190 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1191
1192 /* TCS only receives high 13 bits of the address. */
1193 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
1194 addr = LLVMBuildAnd(builder, addr,
1195 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
1196 }
1197
1198 if (ring == TCS_FACTOR_RING) {
1199 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
1200 addr = LLVMBuildAdd(builder, addr,
1201 LLVMConstInt(ctx->i32, tf_offset, 0), "");
1202 }
1203
1204 LLVMValueRef desc[4];
1205 desc[0] = addr;
1206 desc[1] = LLVMConstInt(ctx->i32,
1207 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1208 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
1209 desc[3] = LLVMConstInt(ctx->i32,
1210 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1211 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1212 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1213 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1214 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1215 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0);
1216
1217 return ac_build_gather_values(&ctx->ac, desc, 4);
1218 }
1219
1220 static LLVMValueRef fetch_input_tcs(
1221 struct lp_build_tgsi_context *bld_base,
1222 const struct tgsi_full_src_register *reg,
1223 enum tgsi_opcode_type type, unsigned swizzle)
1224 {
1225 struct si_shader_context *ctx = si_shader_context(bld_base);
1226 LLVMValueRef dw_addr, stride;
1227
1228 stride = get_tcs_in_vertex_dw_stride(ctx);
1229 dw_addr = get_tcs_in_current_patch_offset(ctx);
1230 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1231
1232 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1233 }
1234
1235 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1236 LLVMTypeRef type,
1237 LLVMValueRef vertex_index,
1238 LLVMValueRef param_index,
1239 unsigned const_index,
1240 unsigned location,
1241 unsigned driver_location,
1242 unsigned component,
1243 unsigned num_components,
1244 bool is_patch,
1245 bool is_compact,
1246 bool load_input)
1247 {
1248 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1249 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1250 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1251 LLVMValueRef dw_addr, stride;
1252
1253 driver_location = driver_location / 4;
1254
1255 if (load_input) {
1256 stride = get_tcs_in_vertex_dw_stride(ctx);
1257 dw_addr = get_tcs_in_current_patch_offset(ctx);
1258 } else {
1259 if (is_patch) {
1260 stride = NULL;
1261 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1262 } else {
1263 stride = get_tcs_out_vertex_dw_stride(ctx);
1264 dw_addr = get_tcs_out_current_patch_offset(ctx);
1265 }
1266 }
1267
1268 if (param_index) {
1269 /* Add the constant index to the indirect index */
1270 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1271 LLVMConstInt(ctx->i32, const_index, 0), "");
1272 } else {
1273 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1274 }
1275
1276 ubyte *names;
1277 ubyte *indices;
1278 if (load_input) {
1279 names = info->input_semantic_name;
1280 indices = info->input_semantic_index;
1281 } else {
1282 names = info->output_semantic_name;
1283 indices = info->output_semantic_index;
1284 }
1285
1286 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1287 vertex_index, param_index,
1288 driver_location,
1289 names, indices,
1290 is_patch);
1291
1292 LLVMValueRef value[4];
1293 for (unsigned i = 0; i < num_components + component; i++) {
1294 value[i] = lds_load(bld_base, type, i, dw_addr);
1295 }
1296
1297 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1298 }
1299
1300 static LLVMValueRef fetch_output_tcs(
1301 struct lp_build_tgsi_context *bld_base,
1302 const struct tgsi_full_src_register *reg,
1303 enum tgsi_opcode_type type, unsigned swizzle)
1304 {
1305 struct si_shader_context *ctx = si_shader_context(bld_base);
1306 LLVMValueRef dw_addr, stride;
1307
1308 if (reg->Register.Dimension) {
1309 stride = get_tcs_out_vertex_dw_stride(ctx);
1310 dw_addr = get_tcs_out_current_patch_offset(ctx);
1311 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1312 } else {
1313 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1314 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1315 }
1316
1317 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1318 }
1319
1320 static LLVMValueRef fetch_input_tes(
1321 struct lp_build_tgsi_context *bld_base,
1322 const struct tgsi_full_src_register *reg,
1323 enum tgsi_opcode_type type, unsigned swizzle)
1324 {
1325 struct si_shader_context *ctx = si_shader_context(bld_base);
1326 LLVMValueRef buffer, base, addr;
1327
1328 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TES);
1329
1330 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1331 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1332
1333 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1334 buffer, base, addr, true);
1335 }
1336
1337 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1338 LLVMTypeRef type,
1339 LLVMValueRef vertex_index,
1340 LLVMValueRef param_index,
1341 unsigned const_index,
1342 unsigned location,
1343 unsigned driver_location,
1344 unsigned component,
1345 unsigned num_components,
1346 bool is_patch,
1347 bool is_compact,
1348 bool load_input)
1349 {
1350 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1351 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1352 LLVMValueRef buffer, base, addr;
1353
1354 driver_location = driver_location / 4;
1355
1356 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TES);
1357
1358 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1359
1360 if (param_index) {
1361 /* Add the constant index to the indirect index */
1362 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1363 LLVMConstInt(ctx->i32, const_index, 0), "");
1364 } else {
1365 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1366 }
1367
1368 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1369 param_index, driver_location,
1370 info->input_semantic_name,
1371 info->input_semantic_index,
1372 is_patch);
1373
1374 /* TODO: This will generate rather ordinary llvm code, although it
1375 * should be easy for the optimiser to fix up. In future we might want
1376 * to refactor buffer_load(), but for now this maximises code sharing
1377 * between the NIR and TGSI backends.
1378 */
1379 LLVMValueRef value[4];
1380 for (unsigned i = component; i < num_components + component; i++) {
1381 value[i] = buffer_load(&ctx->bld_base, type, i, buffer, base, addr, true);
1382 }
1383
1384 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1385 }
1386
1387 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1388 const struct tgsi_full_instruction *inst,
1389 const struct tgsi_opcode_info *info,
1390 unsigned index,
1391 LLVMValueRef dst[4])
1392 {
1393 struct si_shader_context *ctx = si_shader_context(bld_base);
1394 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1395 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1396 unsigned chan_index;
1397 LLVMValueRef dw_addr, stride;
1398 LLVMValueRef buffer, base, buf_addr;
1399 LLVMValueRef values[4];
1400 bool skip_lds_store;
1401 bool is_tess_factor = false, is_tess_inner = false;
1402
1403 /* Only handle per-patch and per-vertex outputs here.
1404 * Vectors will be lowered to scalars and this function will be called again.
1405 */
1406 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1407 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1408 si_llvm_emit_store(bld_base, inst, info, index, dst);
1409 return;
1410 }
1411
1412 if (reg->Register.Dimension) {
1413 stride = get_tcs_out_vertex_dw_stride(ctx);
1414 dw_addr = get_tcs_out_current_patch_offset(ctx);
1415 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1416 skip_lds_store = !sh_info->reads_pervertex_outputs;
1417 } else {
1418 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1419 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1420 skip_lds_store = !sh_info->reads_perpatch_outputs;
1421
1422 if (!reg->Register.Indirect) {
1423 int name = sh_info->output_semantic_name[reg->Register.Index];
1424
1425 /* Always write tess factors into LDS for the TCS epilog. */
1426 if (name == TGSI_SEMANTIC_TESSINNER ||
1427 name == TGSI_SEMANTIC_TESSOUTER) {
1428 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1429 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1430 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1431 is_tess_factor = true;
1432 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1433 }
1434 }
1435 }
1436
1437 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1438
1439 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1440 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1441
1442 uint32_t writemask = reg->Register.WriteMask;
1443 while (writemask) {
1444 chan_index = u_bit_scan(&writemask);
1445 LLVMValueRef value = dst[chan_index];
1446
1447 if (inst->Instruction.Saturate)
1448 value = ac_build_clamp(&ctx->ac, value);
1449
1450 /* Skip LDS stores if there is no LDS read of this output. */
1451 if (!skip_lds_store)
1452 lds_store(ctx, chan_index, dw_addr, value);
1453
1454 value = ac_to_integer(&ctx->ac, value);
1455 values[chan_index] = value;
1456
1457 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1458 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1459 buf_addr, base,
1460 4 * chan_index, 1, 0, true, false);
1461 }
1462
1463 /* Write tess factors into VGPRs for the epilog. */
1464 if (is_tess_factor &&
1465 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1466 if (!is_tess_inner) {
1467 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1468 ctx->invoc0_tess_factors[chan_index]);
1469 } else if (chan_index < 2) {
1470 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1471 ctx->invoc0_tess_factors[4 + chan_index]);
1472 }
1473 }
1474 }
1475
1476 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1477 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1478 values, 4);
1479 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1480 base, 0, 1, 0, true, false);
1481 }
1482 }
1483
1484 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1485 LLVMValueRef vertex_index,
1486 LLVMValueRef param_index,
1487 unsigned const_index,
1488 unsigned location,
1489 unsigned driver_location,
1490 LLVMValueRef src,
1491 unsigned component,
1492 bool is_patch,
1493 bool is_compact,
1494 unsigned writemask)
1495 {
1496 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1497 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1498 LLVMValueRef dw_addr, stride;
1499 LLVMValueRef buffer, base, addr;
1500 LLVMValueRef values[4];
1501 bool skip_lds_store;
1502 bool is_tess_factor = false, is_tess_inner = false;
1503
1504 driver_location = driver_location / 4;
1505
1506 if (param_index) {
1507 /* Add the constant index to the indirect index */
1508 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1509 LLVMConstInt(ctx->i32, const_index, 0), "");
1510 } else {
1511 if (const_index != 0)
1512 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1513 }
1514
1515 if (!is_patch) {
1516 stride = get_tcs_out_vertex_dw_stride(ctx);
1517 dw_addr = get_tcs_out_current_patch_offset(ctx);
1518 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1519 vertex_index, param_index,
1520 driver_location,
1521 info->output_semantic_name,
1522 info->output_semantic_index,
1523 is_patch);
1524
1525 skip_lds_store = !info->reads_pervertex_outputs;
1526 } else {
1527 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1528 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1529 vertex_index, param_index,
1530 driver_location,
1531 info->output_semantic_name,
1532 info->output_semantic_index,
1533 is_patch);
1534
1535 skip_lds_store = !info->reads_perpatch_outputs;
1536
1537 if (!param_index) {
1538 int name = info->output_semantic_name[driver_location];
1539
1540 /* Always write tess factors into LDS for the TCS epilog. */
1541 if (name == TGSI_SEMANTIC_TESSINNER ||
1542 name == TGSI_SEMANTIC_TESSOUTER) {
1543 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1544 skip_lds_store = !info->reads_tessfactor_outputs &&
1545 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1546 is_tess_factor = true;
1547 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1548 }
1549 }
1550 }
1551
1552 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1553
1554 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1555
1556 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1557 param_index, driver_location,
1558 info->output_semantic_name,
1559 info->output_semantic_index,
1560 is_patch);
1561
1562 for (unsigned chan = 0; chan < 4; chan++) {
1563 if (!(writemask & (1 << chan)))
1564 continue;
1565 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1566
1567 /* Skip LDS stores if there is no LDS read of this output. */
1568 if (!skip_lds_store)
1569 ac_lds_store(&ctx->ac, dw_addr, value);
1570
1571 value = ac_to_integer(&ctx->ac, value);
1572 values[chan] = value;
1573
1574 if (writemask != 0xF && !is_tess_factor) {
1575 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1576 addr, base,
1577 4 * chan, 1, 0, true, false);
1578 }
1579
1580 /* Write tess factors into VGPRs for the epilog. */
1581 if (is_tess_factor &&
1582 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1583 if (!is_tess_inner) {
1584 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1585 ctx->invoc0_tess_factors[chan]);
1586 } else if (chan < 2) {
1587 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1588 ctx->invoc0_tess_factors[4 + chan]);
1589 }
1590 }
1591 }
1592
1593 if (writemask == 0xF && !is_tess_factor) {
1594 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1595 values, 4);
1596 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1597 base, 0, 1, 0, true, false);
1598 }
1599 }
1600
1601 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1602 unsigned input_index,
1603 unsigned vtx_offset_param,
1604 LLVMTypeRef type,
1605 unsigned swizzle)
1606 {
1607 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1608 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1609 struct si_shader *shader = ctx->shader;
1610 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1611 LLVMValueRef vtx_offset, soffset;
1612 struct tgsi_shader_info *info = &shader->selector->info;
1613 unsigned semantic_name = info->input_semantic_name[input_index];
1614 unsigned semantic_index = info->input_semantic_index[input_index];
1615 unsigned param;
1616 LLVMValueRef value;
1617
1618 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1619
1620 /* GFX9 has the ESGS ring in LDS. */
1621 if (ctx->screen->info.chip_class >= GFX9) {
1622 unsigned index = vtx_offset_param;
1623
1624 switch (index / 2) {
1625 case 0:
1626 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx01_offset,
1627 index % 2 ? 16 : 0, 16);
1628 break;
1629 case 1:
1630 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx23_offset,
1631 index % 2 ? 16 : 0, 16);
1632 break;
1633 case 2:
1634 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx45_offset,
1635 index % 2 ? 16 : 0, 16);
1636 break;
1637 default:
1638 assert(0);
1639 return NULL;
1640 }
1641
1642 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1643 LLVMConstInt(ctx->i32, param * 4, 0), "");
1644 return lds_load(bld_base, type, swizzle, vtx_offset);
1645 }
1646
1647 /* GFX6: input load from the ESGS ring in memory. */
1648 if (swizzle == ~0) {
1649 LLVMValueRef values[TGSI_NUM_CHANNELS];
1650 unsigned chan;
1651 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1652 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1653 type, chan);
1654 }
1655 return lp_build_gather_values(&ctx->gallivm, values,
1656 TGSI_NUM_CHANNELS);
1657 }
1658
1659 /* Get the vertex offset parameter on GFX6. */
1660 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1661
1662 vtx_offset = lp_build_mul_imm(uint, gs_vtx_offset, 4);
1663
1664 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1665
1666 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1667 vtx_offset, soffset, 0, 1, 0, true, false);
1668 if (llvm_type_is_64bit(ctx, type)) {
1669 LLVMValueRef value2;
1670 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1671
1672 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1673 ctx->i32_0, vtx_offset, soffset,
1674 0, 1, 0, true, false);
1675 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1676 }
1677 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1678 }
1679
1680 static LLVMValueRef fetch_input_gs(
1681 struct lp_build_tgsi_context *bld_base,
1682 const struct tgsi_full_src_register *reg,
1683 enum tgsi_opcode_type type,
1684 unsigned swizzle)
1685 {
1686 struct si_shader_context *ctx = si_shader_context(bld_base);
1687 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1688
1689 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1690 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1691 return get_primitive_id(ctx, swizzle);
1692
1693 if (!reg->Register.Dimension)
1694 return NULL;
1695
1696 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1697 reg->Dimension.Index,
1698 tgsi2llvmtype(bld_base, type),
1699 swizzle);
1700 }
1701
1702 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1703 {
1704 switch (interpolate) {
1705 case TGSI_INTERPOLATE_CONSTANT:
1706 return 0;
1707
1708 case TGSI_INTERPOLATE_LINEAR:
1709 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1710 return SI_PARAM_LINEAR_SAMPLE;
1711 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1712 return SI_PARAM_LINEAR_CENTROID;
1713 else
1714 return SI_PARAM_LINEAR_CENTER;
1715 break;
1716 case TGSI_INTERPOLATE_COLOR:
1717 case TGSI_INTERPOLATE_PERSPECTIVE:
1718 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1719 return SI_PARAM_PERSP_SAMPLE;
1720 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1721 return SI_PARAM_PERSP_CENTROID;
1722 else
1723 return SI_PARAM_PERSP_CENTER;
1724 break;
1725 default:
1726 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1727 return -1;
1728 }
1729 }
1730
1731 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1732 unsigned attr_index, unsigned chan,
1733 LLVMValueRef prim_mask,
1734 LLVMValueRef i, LLVMValueRef j)
1735 {
1736 if (i || j) {
1737 return ac_build_fs_interp(&ctx->ac,
1738 LLVMConstInt(ctx->i32, chan, 0),
1739 LLVMConstInt(ctx->i32, attr_index, 0),
1740 prim_mask, i, j);
1741 }
1742 return ac_build_fs_interp_mov(&ctx->ac,
1743 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1744 LLVMConstInt(ctx->i32, chan, 0),
1745 LLVMConstInt(ctx->i32, attr_index, 0),
1746 prim_mask);
1747 }
1748
1749 /**
1750 * Interpolate a fragment shader input.
1751 *
1752 * @param ctx context
1753 * @param input_index index of the input in hardware
1754 * @param semantic_name TGSI_SEMANTIC_*
1755 * @param semantic_index semantic index
1756 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1757 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1758 * @param interp_param interpolation weights (i,j)
1759 * @param prim_mask SI_PARAM_PRIM_MASK
1760 * @param face SI_PARAM_FRONT_FACE
1761 * @param result the return value (4 components)
1762 */
1763 static void interp_fs_input(struct si_shader_context *ctx,
1764 unsigned input_index,
1765 unsigned semantic_name,
1766 unsigned semantic_index,
1767 unsigned num_interp_inputs,
1768 unsigned colors_read_mask,
1769 LLVMValueRef interp_param,
1770 LLVMValueRef prim_mask,
1771 LLVMValueRef face,
1772 LLVMValueRef result[4])
1773 {
1774 LLVMValueRef i = NULL, j = NULL;
1775 unsigned chan;
1776
1777 /* fs.constant returns the param from the middle vertex, so it's not
1778 * really useful for flat shading. It's meant to be used for custom
1779 * interpolation (but the intrinsic can't fetch from the other two
1780 * vertices).
1781 *
1782 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1783 * to do the right thing. The only reason we use fs.constant is that
1784 * fs.interp cannot be used on integers, because they can be equal
1785 * to NaN.
1786 *
1787 * When interp is false we will use fs.constant or for newer llvm,
1788 * amdgcn.interp.mov.
1789 */
1790 bool interp = interp_param != NULL;
1791
1792 if (interp) {
1793 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1794 LLVMVectorType(ctx->f32, 2), "");
1795
1796 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1797 ctx->i32_0, "");
1798 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1799 ctx->i32_1, "");
1800 }
1801
1802 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1803 ctx->shader->key.part.ps.prolog.color_two_side) {
1804 LLVMValueRef is_face_positive;
1805
1806 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1807 * otherwise it's at offset "num_inputs".
1808 */
1809 unsigned back_attr_offset = num_interp_inputs;
1810 if (semantic_index == 1 && colors_read_mask & 0xf)
1811 back_attr_offset += 1;
1812
1813 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1814 face, ctx->i32_0, "");
1815
1816 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1817 LLVMValueRef front, back;
1818
1819 front = si_build_fs_interp(ctx,
1820 input_index, chan,
1821 prim_mask, i, j);
1822 back = si_build_fs_interp(ctx,
1823 back_attr_offset, chan,
1824 prim_mask, i, j);
1825
1826 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1827 is_face_positive,
1828 front,
1829 back,
1830 "");
1831 }
1832 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1833 result[0] = si_build_fs_interp(ctx, input_index,
1834 0, prim_mask, i, j);
1835 result[1] =
1836 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1837 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1838 } else {
1839 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1840 result[chan] = si_build_fs_interp(ctx,
1841 input_index, chan,
1842 prim_mask, i, j);
1843 }
1844 }
1845 }
1846
1847 void si_llvm_load_input_fs(
1848 struct si_shader_context *ctx,
1849 unsigned input_index,
1850 LLVMValueRef out[4])
1851 {
1852 struct lp_build_context *base = &ctx->bld_base.base;
1853 struct si_shader *shader = ctx->shader;
1854 struct tgsi_shader_info *info = &shader->selector->info;
1855 LLVMValueRef main_fn = ctx->main_fn;
1856 LLVMValueRef interp_param = NULL;
1857 int interp_param_idx;
1858 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1859 unsigned semantic_index = info->input_semantic_index[input_index];
1860 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1861 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1862
1863 /* Get colors from input VGPRs (set by the prolog). */
1864 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1865 unsigned colors_read = shader->selector->info.colors_read;
1866 unsigned mask = colors_read >> (semantic_index * 4);
1867 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1868 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1869
1870 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1871 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1872 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1873 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1874 return;
1875 }
1876
1877 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1878 if (interp_param_idx == -1)
1879 return;
1880 else if (interp_param_idx) {
1881 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1882 }
1883
1884 interp_fs_input(ctx, input_index, semantic_name,
1885 semantic_index, 0, /* this param is unused */
1886 shader->selector->info.colors_read, interp_param,
1887 ctx->abi.prim_mask,
1888 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1889 &out[0]);
1890 }
1891
1892 static void declare_input_fs(
1893 struct si_shader_context *ctx,
1894 unsigned input_index,
1895 const struct tgsi_full_declaration *decl,
1896 LLVMValueRef out[4])
1897 {
1898 si_llvm_load_input_fs(ctx, input_index, out);
1899 }
1900
1901 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1902 {
1903 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1904 }
1905
1906 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1907 {
1908 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1909
1910 LLVMValueRef values[3];
1911 LLVMValueRef result;
1912 unsigned i;
1913 unsigned *properties = ctx->shader->selector->info.properties;
1914
1915 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1916 unsigned sizes[3] = {
1917 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1918 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1919 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1920 };
1921
1922 for (i = 0; i < 3; ++i)
1923 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1924
1925 result = lp_build_gather_values(&ctx->gallivm, values, 3);
1926 } else {
1927 result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1928 }
1929
1930 return result;
1931 }
1932
1933 /**
1934 * Load a dword from a constant buffer.
1935 */
1936 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1937 LLVMValueRef resource,
1938 LLVMValueRef offset)
1939 {
1940 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1941 0, 0, 0, true, true);
1942 }
1943
1944 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1945 {
1946 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1947 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1948 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1949 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1950 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1951
1952 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1953 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1954 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1955
1956 LLVMValueRef pos[4] = {
1957 buffer_load_const(ctx, resource, offset0),
1958 buffer_load_const(ctx, resource, offset1),
1959 LLVMConstReal(ctx->f32, 0),
1960 LLVMConstReal(ctx->f32, 0)
1961 };
1962
1963 return lp_build_gather_values(&ctx->gallivm, pos, 4);
1964 }
1965
1966 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1967 {
1968 return abi->sample_coverage;
1969 }
1970
1971 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
1972 {
1973 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1974 struct lp_build_context *bld = &ctx->bld_base.base;
1975
1976 LLVMValueRef coord[4] = {
1977 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1978 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1979 ctx->ac.f32_0,
1980 ctx->ac.f32_0
1981 };
1982
1983 /* For triangles, the vector should be (u, v, 1-u-v). */
1984 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1985 PIPE_PRIM_TRIANGLES)
1986 coord[2] = lp_build_sub(bld, ctx->ac.f32_1,
1987 lp_build_add(bld, coord[0], coord[1]));
1988
1989 return lp_build_gather_values(&ctx->gallivm, coord, 4);
1990 }
1991
1992 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
1993 unsigned semantic_name)
1994 {
1995 LLVMValueRef buffer, base, addr;
1996
1997 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
1998
1999 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TES);
2000
2001 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2002 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
2003 LLVMConstInt(ctx->i32, param, 0));
2004
2005 return buffer_load(&ctx->bld_base, ctx->f32,
2006 ~0, buffer, base, addr, true);
2007
2008 }
2009
2010 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
2011 unsigned varying_id)
2012 {
2013 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2014 unsigned semantic_name;
2015
2016 switch (varying_id) {
2017 case VARYING_SLOT_TESS_LEVEL_INNER:
2018 semantic_name = TGSI_SEMANTIC_TESSINNER;
2019 break;
2020 case VARYING_SLOT_TESS_LEVEL_OUTER:
2021 semantic_name = TGSI_SEMANTIC_TESSOUTER;
2022 break;
2023 default:
2024 unreachable("unknown tess level");
2025 }
2026
2027 return load_tess_level(ctx, semantic_name);
2028
2029 }
2030
2031 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
2032 {
2033 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2034 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2035 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
2036 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
2037 return get_num_tcs_out_vertices(ctx);
2038 else
2039 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2040 }
2041
2042 void si_load_system_value(struct si_shader_context *ctx,
2043 unsigned index,
2044 const struct tgsi_full_declaration *decl)
2045 {
2046 LLVMValueRef value = 0;
2047
2048 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
2049
2050 switch (decl->Semantic.Name) {
2051 case TGSI_SEMANTIC_INSTANCEID:
2052 value = ctx->abi.instance_id;
2053 break;
2054
2055 case TGSI_SEMANTIC_VERTEXID:
2056 value = LLVMBuildAdd(ctx->ac.builder,
2057 ctx->abi.vertex_id,
2058 ctx->abi.base_vertex, "");
2059 break;
2060
2061 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2062 /* Unused. Clarify the meaning in indexed vs. non-indexed
2063 * draws if this is ever used again. */
2064 assert(false);
2065 break;
2066
2067 case TGSI_SEMANTIC_BASEVERTEX:
2068 {
2069 /* For non-indexed draws, the base vertex set by the driver
2070 * (for direct draws) or the CP (for indirect draws) is the
2071 * first vertex ID, but GLSL expects 0 to be returned.
2072 */
2073 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
2074 LLVMValueRef indexed;
2075
2076 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
2077 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
2078
2079 value = LLVMBuildSelect(ctx->ac.builder, indexed,
2080 ctx->abi.base_vertex, ctx->i32_0, "");
2081 break;
2082 }
2083
2084 case TGSI_SEMANTIC_BASEINSTANCE:
2085 value = ctx->abi.start_instance;
2086 break;
2087
2088 case TGSI_SEMANTIC_DRAWID:
2089 value = ctx->abi.draw_id;
2090 break;
2091
2092 case TGSI_SEMANTIC_INVOCATIONID:
2093 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2094 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2095 else if (ctx->type == PIPE_SHADER_GEOMETRY)
2096 value = ctx->abi.gs_invocation_id;
2097 else
2098 assert(!"INVOCATIONID not implemented");
2099 break;
2100
2101 case TGSI_SEMANTIC_POSITION:
2102 {
2103 LLVMValueRef pos[4] = {
2104 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2105 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2106 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2107 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
2108 LLVMGetParam(ctx->main_fn,
2109 SI_PARAM_POS_W_FLOAT)),
2110 };
2111 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
2112 break;
2113 }
2114
2115 case TGSI_SEMANTIC_FACE:
2116 value = ctx->abi.front_face;
2117 break;
2118
2119 case TGSI_SEMANTIC_SAMPLEID:
2120 value = get_sample_id(ctx);
2121 break;
2122
2123 case TGSI_SEMANTIC_SAMPLEPOS: {
2124 LLVMValueRef pos[4] = {
2125 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2126 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2127 LLVMConstReal(ctx->f32, 0),
2128 LLVMConstReal(ctx->f32, 0)
2129 };
2130 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
2131 TGSI_OPCODE_FRC, pos[0]);
2132 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
2133 TGSI_OPCODE_FRC, pos[1]);
2134 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
2135 break;
2136 }
2137
2138 case TGSI_SEMANTIC_SAMPLEMASK:
2139 /* This can only occur with the OpenGL Core profile, which
2140 * doesn't support smoothing.
2141 */
2142 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2143 break;
2144
2145 case TGSI_SEMANTIC_TESSCOORD:
2146 value = si_load_tess_coord(&ctx->abi);
2147 break;
2148
2149 case TGSI_SEMANTIC_VERTICESIN:
2150 value = si_load_patch_vertices_in(&ctx->abi);
2151 break;
2152
2153 case TGSI_SEMANTIC_TESSINNER:
2154 case TGSI_SEMANTIC_TESSOUTER:
2155 value = load_tess_level(ctx, decl->Semantic.Name);
2156 break;
2157
2158 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
2159 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
2160 {
2161 LLVMValueRef buf, slot, val[4];
2162 int i, offset;
2163
2164 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
2165 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2166 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
2167 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
2168
2169 for (i = 0; i < 4; i++)
2170 val[i] = buffer_load_const(ctx, buf,
2171 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
2172 value = lp_build_gather_values(&ctx->gallivm, val, 4);
2173 break;
2174 }
2175
2176 case TGSI_SEMANTIC_PRIMID:
2177 value = get_primitive_id(ctx, 0);
2178 break;
2179
2180 case TGSI_SEMANTIC_GRID_SIZE:
2181 value = ctx->abi.num_work_groups;
2182 break;
2183
2184 case TGSI_SEMANTIC_BLOCK_SIZE:
2185 value = get_block_size(&ctx->abi);
2186 break;
2187
2188 case TGSI_SEMANTIC_BLOCK_ID:
2189 {
2190 LLVMValueRef values[3];
2191
2192 for (int i = 0; i < 3; i++) {
2193 values[i] = ctx->i32_0;
2194 if (ctx->abi.workgroup_ids[i]) {
2195 values[i] = ctx->abi.workgroup_ids[i];
2196 }
2197 }
2198 value = lp_build_gather_values(&ctx->gallivm, values, 3);
2199 break;
2200 }
2201
2202 case TGSI_SEMANTIC_THREAD_ID:
2203 value = ctx->abi.local_invocation_ids;
2204 break;
2205
2206 case TGSI_SEMANTIC_HELPER_INVOCATION:
2207 value = lp_build_intrinsic(ctx->ac.builder,
2208 "llvm.amdgcn.ps.live",
2209 ctx->i1, NULL, 0,
2210 LP_FUNC_ATTR_READNONE);
2211 value = LLVMBuildNot(ctx->ac.builder, value, "");
2212 value = LLVMBuildSExt(ctx->ac.builder, value, ctx->i32, "");
2213 break;
2214
2215 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2216 value = LLVMConstInt(ctx->i32, 64, 0);
2217 break;
2218
2219 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2220 value = ac_get_thread_id(&ctx->ac);
2221 break;
2222
2223 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2224 {
2225 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2226 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2227 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
2228 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2229 break;
2230 }
2231
2232 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2233 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2234 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2235 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2236 {
2237 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2238 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2239 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2240 /* All bits set except LSB */
2241 value = LLVMConstInt(ctx->i64, -2, 0);
2242 } else {
2243 /* All bits set */
2244 value = LLVMConstInt(ctx->i64, -1, 0);
2245 }
2246 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2247 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2248 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2249 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2250 value = LLVMBuildNot(ctx->ac.builder, value, "");
2251 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2252 break;
2253 }
2254
2255 default:
2256 assert(!"unknown system value");
2257 return;
2258 }
2259
2260 ctx->system_values[index] = value;
2261 }
2262
2263 void si_declare_compute_memory(struct si_shader_context *ctx)
2264 {
2265 struct si_shader_selector *sel = ctx->shader->selector;
2266
2267 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_LOCAL_ADDR_SPACE);
2268 LLVMValueRef var;
2269
2270 assert(!ctx->ac.lds);
2271
2272 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2273 LLVMArrayType(ctx->i8, sel->local_size),
2274 "compute_lds",
2275 AC_LOCAL_ADDR_SPACE);
2276 LLVMSetAlignment(var, 4);
2277
2278 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2279 }
2280
2281 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
2282 const struct tgsi_full_declaration *decl)
2283 {
2284 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2285 assert(decl->Range.First == decl->Range.Last);
2286
2287 si_declare_compute_memory(ctx);
2288 }
2289
2290 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2291 {
2292 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2293 ctx->param_const_and_shader_buffers);
2294
2295 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2296 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2297 }
2298
2299 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2300 {
2301 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2302 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2303
2304 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2305 index = LLVMBuildAdd(ctx->ac.builder, index,
2306 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2307
2308 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2309 }
2310
2311 static LLVMValueRef
2312 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2313 {
2314 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2315 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2316 ctx->param_const_and_shader_buffers);
2317
2318 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2319 index = LLVMBuildSub(ctx->ac.builder,
2320 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2321 index, "");
2322
2323 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2324 }
2325
2326 static LLVMValueRef fetch_constant(
2327 struct lp_build_tgsi_context *bld_base,
2328 const struct tgsi_full_src_register *reg,
2329 enum tgsi_opcode_type type,
2330 unsigned swizzle)
2331 {
2332 struct si_shader_context *ctx = si_shader_context(bld_base);
2333 struct si_shader_selector *sel = ctx->shader->selector;
2334 const struct tgsi_ind_register *ireg = &reg->Indirect;
2335 unsigned buf, idx;
2336
2337 LLVMValueRef addr, bufp;
2338
2339 if (swizzle == LP_CHAN_ALL) {
2340 unsigned chan;
2341 LLVMValueRef values[4];
2342 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2343 values[chan] = fetch_constant(bld_base, reg, type, chan);
2344
2345 return lp_build_gather_values(&ctx->gallivm, values, 4);
2346 }
2347
2348 /* Split 64-bit loads. */
2349 if (tgsi_type_is_64bit(type)) {
2350 LLVMValueRef lo, hi;
2351
2352 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2353 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle + 1);
2354 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2355 lo, hi);
2356 }
2357
2358 idx = reg->Register.Index * 4 + swizzle;
2359 if (reg->Register.Indirect) {
2360 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2361 } else {
2362 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2363 }
2364
2365 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2366 if (sel->info.const_buffers_declared == 1 &&
2367 sel->info.shader_buffers_declared == 0) {
2368 LLVMValueRef ptr =
2369 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2370
2371 /* This enables use of s_load_dword and flat_load_dword for const buffer 0
2372 * loads, and up to x4 load opcode merging. However, it leads to horrible
2373 * code reducing SIMD wave occupancy from 8 to 2 in many cases.
2374 *
2375 * Using s_buffer_load_dword (x1) seems to be the best option right now.
2376 *
2377 * LLVM 5.0 on SI doesn't insert a required s_nop between SALU setting
2378 * a descriptor and s_buffer_load_dword using it, so we can't expand
2379 * the pointer into a full descriptor like below. We have to use
2380 * s_load_dword instead. The only case when LLVM 5.0 would select
2381 * s_buffer_load_dword (that we have to prevent) is when we use use
2382 * a literal offset where we don't need bounds checking.
2383 */
2384 if (ctx->screen->info.chip_class == SI &&
2385 HAVE_LLVM < 0x0600 &&
2386 !reg->Register.Indirect) {
2387 addr = LLVMBuildLShr(ctx->ac.builder, addr, LLVMConstInt(ctx->i32, 2, 0), "");
2388 LLVMValueRef result = ac_build_load_invariant(&ctx->ac, ptr, addr);
2389 return bitcast(bld_base, type, result);
2390 }
2391
2392 /* Do the bounds checking with a descriptor, because
2393 * doing computation and manual bounds checking of 64-bit
2394 * addresses generates horrible VALU code with very high
2395 * VGPR usage and very low SIMD occupancy.
2396 */
2397 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->i64, "");
2398 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ctx->v2i32, "");
2399
2400 LLVMValueRef desc_elems[] = {
2401 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_0, ""),
2402 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_1, ""),
2403 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2404 LLVMConstInt(ctx->i32,
2405 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2406 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2407 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2408 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2409 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2410 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2411 };
2412 LLVMValueRef desc = ac_build_gather_values(&ctx->ac, desc_elems, 4);
2413 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2414 return bitcast(bld_base, type, result);
2415 }
2416
2417 assert(reg->Register.Dimension);
2418 buf = reg->Dimension.Index;
2419
2420 if (reg->Dimension.Indirect) {
2421 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2422 LLVMValueRef index;
2423 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2424 reg->Dimension.Index,
2425 ctx->num_const_buffers);
2426 index = LLVMBuildAdd(ctx->ac.builder, index,
2427 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2428 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2429 } else
2430 bufp = load_const_buffer_desc(ctx, buf);
2431
2432 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2433 }
2434
2435 /* Initialize arguments for the shader export intrinsic */
2436 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2437 LLVMValueRef *values,
2438 unsigned target,
2439 struct ac_export_args *args)
2440 {
2441 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2442 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2443 unsigned chan;
2444 bool is_int8, is_int10;
2445
2446 /* Default is 0xf. Adjusted below depending on the format. */
2447 args->enabled_channels = 0xf; /* writemask */
2448
2449 /* Specify whether the EXEC mask represents the valid mask */
2450 args->valid_mask = 0;
2451
2452 /* Specify whether this is the last export */
2453 args->done = 0;
2454
2455 /* Specify the target we are exporting */
2456 args->target = target;
2457
2458 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2459 const struct si_shader_key *key = &ctx->shader->key;
2460 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2461 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2462
2463 assert(cbuf >= 0 && cbuf < 8);
2464 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2465 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2466 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2467 }
2468
2469 args->compr = false;
2470 args->out[0] = f32undef;
2471 args->out[1] = f32undef;
2472 args->out[2] = f32undef;
2473 args->out[3] = f32undef;
2474
2475 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2476 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2477 unsigned bits, bool hi) = NULL;
2478
2479 switch (spi_shader_col_format) {
2480 case V_028714_SPI_SHADER_ZERO:
2481 args->enabled_channels = 0; /* writemask */
2482 args->target = V_008DFC_SQ_EXP_NULL;
2483 break;
2484
2485 case V_028714_SPI_SHADER_32_R:
2486 args->enabled_channels = 1; /* writemask */
2487 args->out[0] = values[0];
2488 break;
2489
2490 case V_028714_SPI_SHADER_32_GR:
2491 args->enabled_channels = 0x3; /* writemask */
2492 args->out[0] = values[0];
2493 args->out[1] = values[1];
2494 break;
2495
2496 case V_028714_SPI_SHADER_32_AR:
2497 args->enabled_channels = 0x9; /* writemask */
2498 args->out[0] = values[0];
2499 args->out[3] = values[3];
2500 break;
2501
2502 case V_028714_SPI_SHADER_FP16_ABGR:
2503 packf = ac_build_cvt_pkrtz_f16;
2504 break;
2505
2506 case V_028714_SPI_SHADER_UNORM16_ABGR:
2507 packf = ac_build_cvt_pknorm_u16;
2508 break;
2509
2510 case V_028714_SPI_SHADER_SNORM16_ABGR:
2511 packf = ac_build_cvt_pknorm_i16;
2512 break;
2513
2514 case V_028714_SPI_SHADER_UINT16_ABGR:
2515 packi = ac_build_cvt_pk_u16;
2516 break;
2517
2518 case V_028714_SPI_SHADER_SINT16_ABGR:
2519 packi = ac_build_cvt_pk_i16;
2520 break;
2521
2522 case V_028714_SPI_SHADER_32_ABGR:
2523 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2524 break;
2525 }
2526
2527 /* Pack f16 or norm_i16/u16. */
2528 if (packf) {
2529 for (chan = 0; chan < 2; chan++) {
2530 LLVMValueRef pack_args[2] = {
2531 values[2 * chan],
2532 values[2 * chan + 1]
2533 };
2534 LLVMValueRef packed;
2535
2536 packed = packf(&ctx->ac, pack_args);
2537 args->out[chan] = ac_to_float(&ctx->ac, packed);
2538 }
2539 args->compr = 1; /* COMPR flag */
2540 }
2541 /* Pack i16/u16. */
2542 if (packi) {
2543 for (chan = 0; chan < 2; chan++) {
2544 LLVMValueRef pack_args[2] = {
2545 ac_to_integer(&ctx->ac, values[2 * chan]),
2546 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2547 };
2548 LLVMValueRef packed;
2549
2550 packed = packi(&ctx->ac, pack_args,
2551 is_int8 ? 8 : is_int10 ? 10 : 16,
2552 chan == 1);
2553 args->out[chan] = ac_to_float(&ctx->ac, packed);
2554 }
2555 args->compr = 1; /* COMPR flag */
2556 }
2557 }
2558
2559 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2560 LLVMValueRef alpha)
2561 {
2562 struct si_shader_context *ctx = si_shader_context(bld_base);
2563
2564 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2565 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2566 [PIPE_FUNC_LESS] = LLVMRealOLT,
2567 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2568 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2569 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2570 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2571 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2572 };
2573 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2574 assert(cond);
2575
2576 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2577 SI_PARAM_ALPHA_REF);
2578 LLVMValueRef alpha_pass =
2579 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2580 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2581 } else {
2582 ac_build_kill_if_false(&ctx->ac, LLVMConstInt(ctx->i1, 0, 0));
2583 }
2584 }
2585
2586 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2587 LLVMValueRef alpha,
2588 unsigned samplemask_param)
2589 {
2590 struct si_shader_context *ctx = si_shader_context(bld_base);
2591 LLVMValueRef coverage;
2592
2593 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2594 coverage = LLVMGetParam(ctx->main_fn,
2595 samplemask_param);
2596 coverage = ac_to_integer(&ctx->ac, coverage);
2597
2598 coverage = lp_build_intrinsic(ctx->ac.builder, "llvm.ctpop.i32",
2599 ctx->i32,
2600 &coverage, 1, LP_FUNC_ATTR_READNONE);
2601
2602 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2603 ctx->f32, "");
2604
2605 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2606 LLVMConstReal(ctx->f32,
2607 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2608
2609 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2610 }
2611
2612 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2613 struct ac_export_args *pos, LLVMValueRef *out_elts)
2614 {
2615 unsigned reg_index;
2616 unsigned chan;
2617 unsigned const_chan;
2618 LLVMValueRef base_elt;
2619 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2620 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2621 SI_VS_CONST_CLIP_PLANES, 0);
2622 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2623
2624 for (reg_index = 0; reg_index < 2; reg_index ++) {
2625 struct ac_export_args *args = &pos[2 + reg_index];
2626
2627 args->out[0] =
2628 args->out[1] =
2629 args->out[2] =
2630 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2631
2632 /* Compute dot products of position and user clip plane vectors */
2633 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2634 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2635 LLVMValueRef addr =
2636 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2637 const_chan) * 4, 0);
2638 base_elt = buffer_load_const(ctx, const_resource,
2639 addr);
2640 args->out[chan] =
2641 lp_build_add(&ctx->bld_base.base, args->out[chan],
2642 lp_build_mul(&ctx->bld_base.base, base_elt,
2643 out_elts[const_chan]));
2644 }
2645 }
2646
2647 args->enabled_channels = 0xf;
2648 args->valid_mask = 0;
2649 args->done = 0;
2650 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2651 args->compr = 0;
2652 }
2653 }
2654
2655 static void si_dump_streamout(struct pipe_stream_output_info *so)
2656 {
2657 unsigned i;
2658
2659 if (so->num_outputs)
2660 fprintf(stderr, "STREAMOUT\n");
2661
2662 for (i = 0; i < so->num_outputs; i++) {
2663 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2664 so->output[i].start_component;
2665 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2666 i, so->output[i].output_buffer,
2667 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2668 so->output[i].register_index,
2669 mask & 1 ? "x" : "",
2670 mask & 2 ? "y" : "",
2671 mask & 4 ? "z" : "",
2672 mask & 8 ? "w" : "");
2673 }
2674 }
2675
2676 static void emit_streamout_output(struct si_shader_context *ctx,
2677 LLVMValueRef const *so_buffers,
2678 LLVMValueRef const *so_write_offsets,
2679 struct pipe_stream_output *stream_out,
2680 struct si_shader_output_values *shader_out)
2681 {
2682 unsigned buf_idx = stream_out->output_buffer;
2683 unsigned start = stream_out->start_component;
2684 unsigned num_comps = stream_out->num_components;
2685 LLVMValueRef out[4];
2686
2687 assert(num_comps && num_comps <= 4);
2688 if (!num_comps || num_comps > 4)
2689 return;
2690
2691 /* Load the output as int. */
2692 for (int j = 0; j < num_comps; j++) {
2693 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2694
2695 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2696 }
2697
2698 /* Pack the output. */
2699 LLVMValueRef vdata = NULL;
2700
2701 switch (num_comps) {
2702 case 1: /* as i32 */
2703 vdata = out[0];
2704 break;
2705 case 2: /* as v2i32 */
2706 case 3: /* as v4i32 (aligned to 4) */
2707 case 4: /* as v4i32 */
2708 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2709 for (int j = 0; j < num_comps; j++) {
2710 vdata = LLVMBuildInsertElement(ctx->ac.builder, vdata, out[j],
2711 LLVMConstInt(ctx->i32, j, 0), "");
2712 }
2713 break;
2714 }
2715
2716 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2717 vdata, num_comps,
2718 so_write_offsets[buf_idx],
2719 ctx->i32_0,
2720 stream_out->dst_offset * 4, 1, 1, true, false);
2721 }
2722
2723 /**
2724 * Write streamout data to buffers for vertex stream @p stream (different
2725 * vertex streams can occur for GS copy shaders).
2726 */
2727 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2728 struct si_shader_output_values *outputs,
2729 unsigned noutput, unsigned stream)
2730 {
2731 struct si_shader_selector *sel = ctx->shader->selector;
2732 struct pipe_stream_output_info *so = &sel->so;
2733 LLVMBuilderRef builder = ctx->ac.builder;
2734 int i;
2735 struct lp_build_if_state if_ctx;
2736
2737 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2738 LLVMValueRef so_vtx_count =
2739 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2740
2741 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2742
2743 /* can_emit = tid < so_vtx_count; */
2744 LLVMValueRef can_emit =
2745 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2746
2747 /* Emit the streamout code conditionally. This actually avoids
2748 * out-of-bounds buffer access. The hw tells us via the SGPR
2749 * (so_vtx_count) which threads are allowed to emit streamout data. */
2750 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2751 {
2752 /* The buffer offset is computed as follows:
2753 * ByteOffset = streamout_offset[buffer_id]*4 +
2754 * (streamout_write_index + thread_id)*stride[buffer_id] +
2755 * attrib_offset
2756 */
2757
2758 LLVMValueRef so_write_index =
2759 LLVMGetParam(ctx->main_fn,
2760 ctx->param_streamout_write_index);
2761
2762 /* Compute (streamout_write_index + thread_id). */
2763 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2764
2765 /* Load the descriptor and compute the write offset for each
2766 * enabled buffer. */
2767 LLVMValueRef so_write_offset[4] = {};
2768 LLVMValueRef so_buffers[4];
2769 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2770 ctx->param_rw_buffers);
2771
2772 for (i = 0; i < 4; i++) {
2773 if (!so->stride[i])
2774 continue;
2775
2776 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2777 SI_VS_STREAMOUT_BUF0 + i, 0);
2778
2779 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2780
2781 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2782 ctx->param_streamout_offset[i]);
2783 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2784
2785 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2786 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2787 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2788 }
2789
2790 /* Write streamout data. */
2791 for (i = 0; i < so->num_outputs; i++) {
2792 unsigned reg = so->output[i].register_index;
2793
2794 if (reg >= noutput)
2795 continue;
2796
2797 if (stream != so->output[i].stream)
2798 continue;
2799
2800 emit_streamout_output(ctx, so_buffers, so_write_offset,
2801 &so->output[i], &outputs[reg]);
2802 }
2803 }
2804 lp_build_endif(&if_ctx);
2805 }
2806
2807 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2808 LLVMValueRef *values)
2809 {
2810 struct ac_export_args args;
2811
2812 si_llvm_init_export_args(ctx, values,
2813 V_008DFC_SQ_EXP_PARAM + index, &args);
2814 ac_build_export(&ctx->ac, &args);
2815 }
2816
2817 static void si_build_param_exports(struct si_shader_context *ctx,
2818 struct si_shader_output_values *outputs,
2819 unsigned noutput)
2820 {
2821 struct si_shader *shader = ctx->shader;
2822 unsigned param_count = 0;
2823
2824 for (unsigned i = 0; i < noutput; i++) {
2825 unsigned semantic_name = outputs[i].semantic_name;
2826 unsigned semantic_index = outputs[i].semantic_index;
2827
2828 if (outputs[i].vertex_stream[0] != 0 &&
2829 outputs[i].vertex_stream[1] != 0 &&
2830 outputs[i].vertex_stream[2] != 0 &&
2831 outputs[i].vertex_stream[3] != 0)
2832 continue;
2833
2834 switch (semantic_name) {
2835 case TGSI_SEMANTIC_LAYER:
2836 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2837 case TGSI_SEMANTIC_CLIPDIST:
2838 case TGSI_SEMANTIC_COLOR:
2839 case TGSI_SEMANTIC_BCOLOR:
2840 case TGSI_SEMANTIC_PRIMID:
2841 case TGSI_SEMANTIC_FOG:
2842 case TGSI_SEMANTIC_TEXCOORD:
2843 case TGSI_SEMANTIC_GENERIC:
2844 break;
2845 default:
2846 continue;
2847 }
2848
2849 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2850 semantic_index < SI_MAX_IO_GENERIC) &&
2851 shader->key.opt.kill_outputs &
2852 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2853 continue;
2854
2855 si_export_param(ctx, param_count, outputs[i].values);
2856
2857 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2858 shader->info.vs_output_param_offset[i] = param_count++;
2859 }
2860
2861 shader->info.nr_param_exports = param_count;
2862 }
2863
2864 /* Generate export instructions for hardware VS shader stage */
2865 static void si_llvm_export_vs(struct si_shader_context *ctx,
2866 struct si_shader_output_values *outputs,
2867 unsigned noutput)
2868 {
2869 struct si_shader *shader = ctx->shader;
2870 struct ac_export_args pos_args[4] = {};
2871 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2872 unsigned pos_idx;
2873 int i;
2874
2875 /* Build position exports. */
2876 for (i = 0; i < noutput; i++) {
2877 switch (outputs[i].semantic_name) {
2878 case TGSI_SEMANTIC_POSITION:
2879 si_llvm_init_export_args(ctx, outputs[i].values,
2880 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2881 break;
2882 case TGSI_SEMANTIC_PSIZE:
2883 psize_value = outputs[i].values[0];
2884 break;
2885 case TGSI_SEMANTIC_LAYER:
2886 layer_value = outputs[i].values[0];
2887 break;
2888 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2889 viewport_index_value = outputs[i].values[0];
2890 break;
2891 case TGSI_SEMANTIC_EDGEFLAG:
2892 edgeflag_value = outputs[i].values[0];
2893 break;
2894 case TGSI_SEMANTIC_CLIPDIST:
2895 if (!shader->key.opt.clip_disable) {
2896 unsigned index = 2 + outputs[i].semantic_index;
2897 si_llvm_init_export_args(ctx, outputs[i].values,
2898 V_008DFC_SQ_EXP_POS + index,
2899 &pos_args[index]);
2900 }
2901 break;
2902 case TGSI_SEMANTIC_CLIPVERTEX:
2903 if (!shader->key.opt.clip_disable) {
2904 si_llvm_emit_clipvertex(ctx, pos_args,
2905 outputs[i].values);
2906 }
2907 break;
2908 }
2909 }
2910
2911 /* We need to add the position output manually if it's missing. */
2912 if (!pos_args[0].out[0]) {
2913 pos_args[0].enabled_channels = 0xf; /* writemask */
2914 pos_args[0].valid_mask = 0; /* EXEC mask */
2915 pos_args[0].done = 0; /* last export? */
2916 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2917 pos_args[0].compr = 0; /* COMPR flag */
2918 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2919 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2920 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2921 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2922 }
2923
2924 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2925 if (shader->selector->info.writes_psize ||
2926 shader->selector->info.writes_edgeflag ||
2927 shader->selector->info.writes_viewport_index ||
2928 shader->selector->info.writes_layer) {
2929 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2930 (shader->selector->info.writes_edgeflag << 1) |
2931 (shader->selector->info.writes_layer << 2);
2932
2933 pos_args[1].valid_mask = 0; /* EXEC mask */
2934 pos_args[1].done = 0; /* last export? */
2935 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2936 pos_args[1].compr = 0; /* COMPR flag */
2937 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2938 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2939 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2940 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2941
2942 if (shader->selector->info.writes_psize)
2943 pos_args[1].out[0] = psize_value;
2944
2945 if (shader->selector->info.writes_edgeflag) {
2946 /* The output is a float, but the hw expects an integer
2947 * with the first bit containing the edge flag. */
2948 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2949 edgeflag_value,
2950 ctx->i32, "");
2951 edgeflag_value = ac_build_umin(&ctx->ac,
2952 edgeflag_value,
2953 ctx->i32_1);
2954
2955 /* The LLVM intrinsic expects a float. */
2956 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2957 }
2958
2959 if (ctx->screen->info.chip_class >= GFX9) {
2960 /* GFX9 has the layer in out.z[10:0] and the viewport
2961 * index in out.z[19:16].
2962 */
2963 if (shader->selector->info.writes_layer)
2964 pos_args[1].out[2] = layer_value;
2965
2966 if (shader->selector->info.writes_viewport_index) {
2967 LLVMValueRef v = viewport_index_value;
2968
2969 v = ac_to_integer(&ctx->ac, v);
2970 v = LLVMBuildShl(ctx->ac.builder, v,
2971 LLVMConstInt(ctx->i32, 16, 0), "");
2972 v = LLVMBuildOr(ctx->ac.builder, v,
2973 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2974 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2975 pos_args[1].enabled_channels |= 1 << 2;
2976 }
2977 } else {
2978 if (shader->selector->info.writes_layer)
2979 pos_args[1].out[2] = layer_value;
2980
2981 if (shader->selector->info.writes_viewport_index) {
2982 pos_args[1].out[3] = viewport_index_value;
2983 pos_args[1].enabled_channels |= 1 << 3;
2984 }
2985 }
2986 }
2987
2988 for (i = 0; i < 4; i++)
2989 if (pos_args[i].out[0])
2990 shader->info.nr_pos_exports++;
2991
2992 pos_idx = 0;
2993 for (i = 0; i < 4; i++) {
2994 if (!pos_args[i].out[0])
2995 continue;
2996
2997 /* Specify the target we are exporting */
2998 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2999
3000 if (pos_idx == shader->info.nr_pos_exports)
3001 /* Specify that this is the last export */
3002 pos_args[i].done = 1;
3003
3004 ac_build_export(&ctx->ac, &pos_args[i]);
3005 }
3006
3007 /* Build parameter exports. */
3008 si_build_param_exports(ctx, outputs, noutput);
3009 }
3010
3011 /**
3012 * Forward all outputs from the vertex shader to the TES. This is only used
3013 * for the fixed function TCS.
3014 */
3015 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
3016 {
3017 struct si_shader_context *ctx = si_shader_context(bld_base);
3018 LLVMValueRef invocation_id, buffer, buffer_offset;
3019 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
3020 uint64_t inputs;
3021
3022 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3023 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3024 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3025
3026 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
3027 lds_vertex_offset = LLVMBuildMul(ctx->ac.builder, invocation_id,
3028 lds_vertex_stride, "");
3029 lds_base = get_tcs_in_current_patch_offset(ctx);
3030 lds_base = LLVMBuildAdd(ctx->ac.builder, lds_base, lds_vertex_offset, "");
3031
3032 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
3033 while (inputs) {
3034 unsigned i = u_bit_scan64(&inputs);
3035
3036 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
3037 LLVMConstInt(ctx->i32, 4 * i, 0),
3038 "");
3039
3040 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
3041 get_rel_patch_id(ctx),
3042 invocation_id,
3043 LLVMConstInt(ctx->i32, i, 0));
3044
3045 LLVMValueRef value = lds_load(bld_base, ctx->ac.i32, ~0,
3046 lds_ptr);
3047
3048 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
3049 buffer_offset, 0, 1, 0, true, false);
3050 }
3051 }
3052
3053 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
3054 LLVMValueRef rel_patch_id,
3055 LLVMValueRef invocation_id,
3056 LLVMValueRef tcs_out_current_patch_data_offset,
3057 LLVMValueRef invoc0_tf_outer[4],
3058 LLVMValueRef invoc0_tf_inner[2])
3059 {
3060 struct si_shader_context *ctx = si_shader_context(bld_base);
3061 struct si_shader *shader = ctx->shader;
3062 unsigned tess_inner_index, tess_outer_index;
3063 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
3064 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3065 unsigned stride, outer_comps, inner_comps, i, offset;
3066 struct lp_build_if_state if_ctx, inner_if_ctx;
3067
3068 /* Add a barrier before loading tess factors from LDS. */
3069 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
3070 si_llvm_emit_barrier(NULL, bld_base, NULL);
3071
3072 /* Do this only for invocation 0, because the tess levels are per-patch,
3073 * not per-vertex.
3074 *
3075 * This can't jump, because invocation 0 executes this. It should
3076 * at least mask out the loads and stores for other invocations.
3077 */
3078 lp_build_if(&if_ctx, &ctx->gallivm,
3079 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3080 invocation_id, ctx->i32_0, ""));
3081
3082 /* Determine the layout of one tess factor element in the buffer. */
3083 switch (shader->key.part.tcs.epilog.prim_mode) {
3084 case PIPE_PRIM_LINES:
3085 stride = 2; /* 2 dwords, 1 vec2 store */
3086 outer_comps = 2;
3087 inner_comps = 0;
3088 break;
3089 case PIPE_PRIM_TRIANGLES:
3090 stride = 4; /* 4 dwords, 1 vec4 store */
3091 outer_comps = 3;
3092 inner_comps = 1;
3093 break;
3094 case PIPE_PRIM_QUADS:
3095 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3096 outer_comps = 4;
3097 inner_comps = 2;
3098 break;
3099 default:
3100 assert(0);
3101 return;
3102 }
3103
3104 for (i = 0; i < 4; i++) {
3105 inner[i] = LLVMGetUndef(ctx->i32);
3106 outer[i] = LLVMGetUndef(ctx->i32);
3107 }
3108
3109 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3110 /* Tess factors are in VGPRs. */
3111 for (i = 0; i < outer_comps; i++)
3112 outer[i] = out[i] = invoc0_tf_outer[i];
3113 for (i = 0; i < inner_comps; i++)
3114 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3115 } else {
3116 /* Load tess_inner and tess_outer from LDS.
3117 * Any invocation can write them, so we can't get them from a temporary.
3118 */
3119 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3120 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3121
3122 lds_base = tcs_out_current_patch_data_offset;
3123 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3124 LLVMConstInt(ctx->i32,
3125 tess_inner_index * 4, 0), "");
3126 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3127 LLVMConstInt(ctx->i32,
3128 tess_outer_index * 4, 0), "");
3129
3130 for (i = 0; i < outer_comps; i++) {
3131 outer[i] = out[i] =
3132 lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3133 }
3134 for (i = 0; i < inner_comps; i++) {
3135 inner[i] = out[outer_comps+i] =
3136 lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3137 }
3138 }
3139
3140 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3141 /* For isolines, the hardware expects tess factors in the
3142 * reverse order from what GLSL / TGSI specify.
3143 */
3144 LLVMValueRef tmp = out[0];
3145 out[0] = out[1];
3146 out[1] = tmp;
3147 }
3148
3149 /* Convert the outputs to vectors for stores. */
3150 vec0 = lp_build_gather_values(&ctx->gallivm, out, MIN2(stride, 4));
3151 vec1 = NULL;
3152
3153 if (stride > 4)
3154 vec1 = lp_build_gather_values(&ctx->gallivm, out+4, stride - 4);
3155
3156 /* Get the buffer. */
3157 buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
3158
3159 /* Get the offset. */
3160 tf_base = LLVMGetParam(ctx->main_fn,
3161 ctx->param_tcs_factor_offset);
3162 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3163 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3164
3165 lp_build_if(&inner_if_ctx, &ctx->gallivm,
3166 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3167 rel_patch_id, ctx->i32_0, ""));
3168
3169 /* Store the dynamic HS control word. */
3170 offset = 0;
3171 if (ctx->screen->info.chip_class <= VI) {
3172 ac_build_buffer_store_dword(&ctx->ac, buffer,
3173 LLVMConstInt(ctx->i32, 0x80000000, 0),
3174 1, ctx->i32_0, tf_base,
3175 offset, 1, 0, true, false);
3176 offset += 4;
3177 }
3178
3179 lp_build_endif(&inner_if_ctx);
3180
3181 /* Store the tessellation factors. */
3182 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3183 MIN2(stride, 4), byteoffset, tf_base,
3184 offset, 1, 0, true, false);
3185 offset += 16;
3186 if (vec1)
3187 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3188 stride - 4, byteoffset, tf_base,
3189 offset, 1, 0, true, false);
3190
3191 /* Store the tess factors into the offchip buffer if TES reads them. */
3192 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3193 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3194 LLVMValueRef tf_inner_offset;
3195 unsigned param_outer, param_inner;
3196
3197 buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3198 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3199
3200 param_outer = si_shader_io_get_unique_index_patch(
3201 TGSI_SEMANTIC_TESSOUTER, 0);
3202 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3203 LLVMConstInt(ctx->i32, param_outer, 0));
3204
3205 outer_vec = lp_build_gather_values(&ctx->gallivm, outer,
3206 util_next_power_of_two(outer_comps));
3207
3208 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3209 outer_comps, tf_outer_offset,
3210 base, 0, 1, 0, true, false);
3211 if (inner_comps) {
3212 param_inner = si_shader_io_get_unique_index_patch(
3213 TGSI_SEMANTIC_TESSINNER, 0);
3214 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3215 LLVMConstInt(ctx->i32, param_inner, 0));
3216
3217 inner_vec = inner_comps == 1 ? inner[0] :
3218 lp_build_gather_values(&ctx->gallivm, inner, inner_comps);
3219 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3220 inner_comps, tf_inner_offset,
3221 base, 0, 1, 0, true, false);
3222 }
3223 }
3224
3225 lp_build_endif(&if_ctx);
3226 }
3227
3228 static LLVMValueRef
3229 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3230 unsigned param, unsigned return_index)
3231 {
3232 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3233 LLVMGetParam(ctx->main_fn, param),
3234 return_index, "");
3235 }
3236
3237 static LLVMValueRef
3238 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3239 unsigned param, unsigned return_index)
3240 {
3241 LLVMBuilderRef builder = ctx->ac.builder;
3242 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3243
3244 return LLVMBuildInsertValue(builder, ret,
3245 ac_to_float(&ctx->ac, p),
3246 return_index, "");
3247 }
3248
3249 static LLVMValueRef
3250 si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret,
3251 unsigned param, unsigned return_index)
3252 {
3253 LLVMBuilderRef builder = ctx->ac.builder;
3254 LLVMValueRef ptr, lo, hi;
3255
3256 if (HAVE_32BIT_POINTERS) {
3257 ptr = LLVMGetParam(ctx->main_fn, param);
3258 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i32, "");
3259 return LLVMBuildInsertValue(builder, ret, ptr, return_index, "");
3260 }
3261
3262 ptr = LLVMGetParam(ctx->main_fn, param);
3263 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
3264 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
3265 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
3266 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
3267 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
3268 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
3269 }
3270
3271 /* This only writes the tessellation factor levels. */
3272 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
3273 unsigned max_outputs,
3274 LLVMValueRef *addrs)
3275 {
3276 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3277 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
3278 LLVMBuilderRef builder = ctx->ac.builder;
3279 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3280
3281 si_copy_tcs_inputs(bld_base);
3282
3283 rel_patch_id = get_rel_patch_id(ctx);
3284 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3285 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3286
3287 if (ctx->screen->info.chip_class >= GFX9) {
3288 LLVMBasicBlockRef blocks[2] = {
3289 LLVMGetInsertBlock(builder),
3290 ctx->merged_wrap_if_state.entry_block
3291 };
3292 LLVMValueRef values[2];
3293
3294 lp_build_endif(&ctx->merged_wrap_if_state);
3295
3296 values[0] = rel_patch_id;
3297 values[1] = LLVMGetUndef(ctx->i32);
3298 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3299
3300 values[0] = tf_lds_offset;
3301 values[1] = LLVMGetUndef(ctx->i32);
3302 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3303
3304 values[0] = invocation_id;
3305 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3306 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3307 }
3308
3309 /* Return epilog parameters from this function. */
3310 LLVMValueRef ret = ctx->return_value;
3311 unsigned vgpr;
3312
3313 if (ctx->screen->info.chip_class >= GFX9) {
3314 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3315 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3316 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3317 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3318 /* Tess offchip and tess factor offsets are at the beginning. */
3319 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3320 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3321 vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
3322 } else {
3323 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3324 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3325 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3326 GFX6_SGPR_TCS_OUT_LAYOUT);
3327 /* Tess offchip and tess factor offsets are after user SGPRs. */
3328 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3329 GFX6_TCS_NUM_USER_SGPR);
3330 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3331 GFX6_TCS_NUM_USER_SGPR + 1);
3332 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3333 }
3334
3335 /* VGPRs */
3336 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3337 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3338 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3339
3340 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3341 * the invocation_id output does not alias the tcs_rel_ids input,
3342 * which saves a V_MOV on gfx9.
3343 */
3344 vgpr += 2;
3345
3346 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3347 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3348
3349 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3350 vgpr++; /* skip the tess factor LDS offset */
3351 for (unsigned i = 0; i < 6; i++) {
3352 LLVMValueRef value =
3353 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3354 value = ac_to_float(&ctx->ac, value);
3355 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3356 }
3357 } else {
3358 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3359 }
3360 ctx->return_value = ret;
3361 }
3362
3363 /* Pass TCS inputs from LS to TCS on GFX9. */
3364 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3365 {
3366 LLVMValueRef ret = ctx->return_value;
3367
3368 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3369 if (HAVE_32BIT_POINTERS)
3370 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3371 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3372 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3373 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3374 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3375
3376 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3377 8 + SI_SGPR_RW_BUFFERS);
3378 ret = si_insert_input_ptr(ctx, ret,
3379 ctx->param_bindless_samplers_and_images,
3380 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3381
3382 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3383 8 + SI_SGPR_VS_STATE_BITS);
3384
3385 #if !HAVE_32BIT_POINTERS
3386 ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 1,
3387 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
3388 #endif
3389
3390 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3391 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3392 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3393 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3394 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3395 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3396
3397 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3398 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3399 ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
3400 vgpr++, "");
3401 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3402 ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
3403 vgpr++, "");
3404 ctx->return_value = ret;
3405 }
3406
3407 /* Pass GS inputs from ES to GS on GFX9. */
3408 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3409 {
3410 LLVMValueRef ret = ctx->return_value;
3411
3412 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3413 if (HAVE_32BIT_POINTERS)
3414 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3415 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3416 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3417 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3418
3419 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3420 8 + SI_SGPR_RW_BUFFERS);
3421 ret = si_insert_input_ptr(ctx, ret,
3422 ctx->param_bindless_samplers_and_images,
3423 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3424
3425 #if !HAVE_32BIT_POINTERS
3426 ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 1,
3427 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
3428 #endif
3429
3430 unsigned vgpr = 8 + GFX9_GS_NUM_USER_SGPR;
3431 for (unsigned i = 0; i < 5; i++) {
3432 unsigned param = ctx->param_gs_vtx01_offset + i;
3433 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3434 }
3435 ctx->return_value = ret;
3436 }
3437
3438 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3439 unsigned max_outputs,
3440 LLVMValueRef *addrs)
3441 {
3442 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3443 struct si_shader *shader = ctx->shader;
3444 struct tgsi_shader_info *info = &shader->selector->info;
3445 unsigned i, chan;
3446 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3447 ctx->param_rel_auto_id);
3448 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3449 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3450 vertex_dw_stride, "");
3451
3452 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3453 * its inputs from it. */
3454 for (i = 0; i < info->num_outputs; i++) {
3455 unsigned name = info->output_semantic_name[i];
3456 unsigned index = info->output_semantic_index[i];
3457
3458 /* The ARB_shader_viewport_layer_array spec contains the
3459 * following issue:
3460 *
3461 * 2) What happens if gl_ViewportIndex or gl_Layer is
3462 * written in the vertex shader and a geometry shader is
3463 * present?
3464 *
3465 * RESOLVED: The value written by the last vertex processing
3466 * stage is used. If the last vertex processing stage
3467 * (vertex, tessellation evaluation or geometry) does not
3468 * statically assign to gl_ViewportIndex or gl_Layer, index
3469 * or layer zero is assumed.
3470 *
3471 * So writes to those outputs in VS-as-LS are simply ignored.
3472 */
3473 if (name == TGSI_SEMANTIC_LAYER ||
3474 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3475 continue;
3476
3477 int param = si_shader_io_get_unique_index(name, index);
3478 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3479 LLVMConstInt(ctx->i32, param * 4, 0), "");
3480
3481 for (chan = 0; chan < 4; chan++) {
3482 if (!(info->output_usagemask[i] & (1 << chan)))
3483 continue;
3484
3485 lds_store(ctx, chan, dw_addr,
3486 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3487 }
3488 }
3489
3490 if (ctx->screen->info.chip_class >= GFX9)
3491 si_set_ls_return_value_for_tcs(ctx);
3492 }
3493
3494 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3495 unsigned max_outputs,
3496 LLVMValueRef *addrs)
3497 {
3498 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3499 struct si_shader *es = ctx->shader;
3500 struct tgsi_shader_info *info = &es->selector->info;
3501 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3502 ctx->param_es2gs_offset);
3503 LLVMValueRef lds_base = NULL;
3504 unsigned chan;
3505 int i;
3506
3507 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3508 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3509 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3510 LLVMValueRef wave_idx = unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3511 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3512 LLVMBuildMul(ctx->ac.builder, wave_idx,
3513 LLVMConstInt(ctx->i32, 64, false), ""), "");
3514 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3515 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3516 }
3517
3518 for (i = 0; i < info->num_outputs; i++) {
3519 int param;
3520
3521 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3522 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3523 continue;
3524
3525 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3526 info->output_semantic_index[i]);
3527
3528 for (chan = 0; chan < 4; chan++) {
3529 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3530 out_val = ac_to_integer(&ctx->ac, out_val);
3531
3532 /* GFX9 has the ESGS ring in LDS. */
3533 if (ctx->screen->info.chip_class >= GFX9) {
3534 lds_store(ctx, param * 4 + chan, lds_base, out_val);
3535 continue;
3536 }
3537
3538 ac_build_buffer_store_dword(&ctx->ac,
3539 ctx->esgs_ring,
3540 out_val, 1, NULL, soffset,
3541 (4 * param + chan) * 4,
3542 1, 1, true, true);
3543 }
3544 }
3545
3546 if (ctx->screen->info.chip_class >= GFX9)
3547 si_set_es_return_value_for_gs(ctx);
3548 }
3549
3550 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3551 {
3552 if (ctx->screen->info.chip_class >= GFX9)
3553 return unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3554 else
3555 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3556 }
3557
3558 static void emit_gs_epilogue(struct si_shader_context *ctx)
3559 {
3560 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3561 si_get_gs_wave_id(ctx));
3562
3563 if (ctx->screen->info.chip_class >= GFX9)
3564 lp_build_endif(&ctx->merged_wrap_if_state);
3565 }
3566
3567 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3568 unsigned max_outputs,
3569 LLVMValueRef *addrs)
3570 {
3571 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3572 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3573
3574 assert(info->num_outputs <= max_outputs);
3575
3576 emit_gs_epilogue(ctx);
3577 }
3578
3579 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3580 {
3581 struct si_shader_context *ctx = si_shader_context(bld_base);
3582 emit_gs_epilogue(ctx);
3583 }
3584
3585 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3586 unsigned max_outputs,
3587 LLVMValueRef *addrs)
3588 {
3589 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3590 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3591 struct si_shader_output_values *outputs = NULL;
3592 int i,j;
3593
3594 assert(!ctx->shader->is_gs_copy_shader);
3595 assert(info->num_outputs <= max_outputs);
3596
3597 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3598
3599 /* Vertex color clamping.
3600 *
3601 * This uses a state constant loaded in a user data SGPR and
3602 * an IF statement is added that clamps all colors if the constant
3603 * is true.
3604 */
3605 if (ctx->type == PIPE_SHADER_VERTEX) {
3606 struct lp_build_if_state if_ctx;
3607 LLVMValueRef cond = NULL;
3608 LLVMValueRef addr, val;
3609
3610 for (i = 0; i < info->num_outputs; i++) {
3611 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3612 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3613 continue;
3614
3615 /* We've found a color. */
3616 if (!cond) {
3617 /* The state is in the first bit of the user SGPR. */
3618 cond = LLVMGetParam(ctx->main_fn,
3619 ctx->param_vs_state_bits);
3620 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3621 ctx->i1, "");
3622 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3623 }
3624
3625 for (j = 0; j < 4; j++) {
3626 addr = addrs[4 * i + j];
3627 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3628 val = ac_build_clamp(&ctx->ac, val);
3629 LLVMBuildStore(ctx->ac.builder, val, addr);
3630 }
3631 }
3632
3633 if (cond)
3634 lp_build_endif(&if_ctx);
3635 }
3636
3637 for (i = 0; i < info->num_outputs; i++) {
3638 outputs[i].semantic_name = info->output_semantic_name[i];
3639 outputs[i].semantic_index = info->output_semantic_index[i];
3640
3641 for (j = 0; j < 4; j++) {
3642 outputs[i].values[j] =
3643 LLVMBuildLoad(ctx->ac.builder,
3644 addrs[4 * i + j],
3645 "");
3646 outputs[i].vertex_stream[j] =
3647 (info->output_streams[i] >> (2 * j)) & 3;
3648 }
3649 }
3650
3651 if (ctx->shader->selector->so.num_outputs)
3652 si_llvm_emit_streamout(ctx, outputs, i, 0);
3653
3654 /* Export PrimitiveID. */
3655 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3656 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3657 outputs[i].semantic_index = 0;
3658 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3659 for (j = 1; j < 4; j++)
3660 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3661
3662 memset(outputs[i].vertex_stream, 0,
3663 sizeof(outputs[i].vertex_stream));
3664 i++;
3665 }
3666
3667 si_llvm_export_vs(ctx, outputs, i);
3668 FREE(outputs);
3669 }
3670
3671 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3672 {
3673 struct si_shader_context *ctx = si_shader_context(bld_base);
3674
3675 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3676 &ctx->outputs[0][0]);
3677 }
3678
3679 struct si_ps_exports {
3680 unsigned num;
3681 struct ac_export_args args[10];
3682 };
3683
3684 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3685 LLVMValueRef depth, LLVMValueRef stencil,
3686 LLVMValueRef samplemask, struct si_ps_exports *exp)
3687 {
3688 struct si_shader_context *ctx = si_shader_context(bld_base);
3689 struct ac_export_args args;
3690
3691 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3692
3693 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3694 }
3695
3696 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3697 LLVMValueRef *color, unsigned index,
3698 unsigned samplemask_param,
3699 bool is_last, struct si_ps_exports *exp)
3700 {
3701 struct si_shader_context *ctx = si_shader_context(bld_base);
3702 int i;
3703
3704 /* Clamp color */
3705 if (ctx->shader->key.part.ps.epilog.clamp_color)
3706 for (i = 0; i < 4; i++)
3707 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3708
3709 /* Alpha to one */
3710 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3711 color[3] = ctx->ac.f32_1;
3712
3713 /* Alpha test */
3714 if (index == 0 &&
3715 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3716 si_alpha_test(bld_base, color[3]);
3717
3718 /* Line & polygon smoothing */
3719 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3720 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3721 samplemask_param);
3722
3723 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3724 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3725 struct ac_export_args args[8];
3726 int c, last = -1;
3727
3728 /* Get the export arguments, also find out what the last one is. */
3729 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3730 si_llvm_init_export_args(ctx, color,
3731 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3732 if (args[c].enabled_channels)
3733 last = c;
3734 }
3735
3736 /* Emit all exports. */
3737 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3738 if (is_last && last == c) {
3739 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3740 args[c].done = 1; /* DONE bit */
3741 } else if (!args[c].enabled_channels)
3742 continue; /* unnecessary NULL export */
3743
3744 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3745 }
3746 } else {
3747 struct ac_export_args args;
3748
3749 /* Export */
3750 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3751 &args);
3752 if (is_last) {
3753 args.valid_mask = 1; /* whether the EXEC mask is valid */
3754 args.done = 1; /* DONE bit */
3755 } else if (!args.enabled_channels)
3756 return; /* unnecessary NULL export */
3757
3758 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3759 }
3760 }
3761
3762 static void si_emit_ps_exports(struct si_shader_context *ctx,
3763 struct si_ps_exports *exp)
3764 {
3765 for (unsigned i = 0; i < exp->num; i++)
3766 ac_build_export(&ctx->ac, &exp->args[i]);
3767 }
3768
3769 /**
3770 * Return PS outputs in this order:
3771 *
3772 * v[0:3] = color0.xyzw
3773 * v[4:7] = color1.xyzw
3774 * ...
3775 * vN+0 = Depth
3776 * vN+1 = Stencil
3777 * vN+2 = SampleMask
3778 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3779 *
3780 * The alpha-ref SGPR is returned via its original location.
3781 */
3782 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3783 unsigned max_outputs,
3784 LLVMValueRef *addrs)
3785 {
3786 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3787 struct si_shader *shader = ctx->shader;
3788 struct tgsi_shader_info *info = &shader->selector->info;
3789 LLVMBuilderRef builder = ctx->ac.builder;
3790 unsigned i, j, first_vgpr, vgpr;
3791
3792 LLVMValueRef color[8][4] = {};
3793 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3794 LLVMValueRef ret;
3795
3796 if (ctx->postponed_kill)
3797 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3798
3799 /* Read the output values. */
3800 for (i = 0; i < info->num_outputs; i++) {
3801 unsigned semantic_name = info->output_semantic_name[i];
3802 unsigned semantic_index = info->output_semantic_index[i];
3803
3804 switch (semantic_name) {
3805 case TGSI_SEMANTIC_COLOR:
3806 assert(semantic_index < 8);
3807 for (j = 0; j < 4; j++) {
3808 LLVMValueRef ptr = addrs[4 * i + j];
3809 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3810 color[semantic_index][j] = result;
3811 }
3812 break;
3813 case TGSI_SEMANTIC_POSITION:
3814 depth = LLVMBuildLoad(builder,
3815 addrs[4 * i + 2], "");
3816 break;
3817 case TGSI_SEMANTIC_STENCIL:
3818 stencil = LLVMBuildLoad(builder,
3819 addrs[4 * i + 1], "");
3820 break;
3821 case TGSI_SEMANTIC_SAMPLEMASK:
3822 samplemask = LLVMBuildLoad(builder,
3823 addrs[4 * i + 0], "");
3824 break;
3825 default:
3826 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3827 semantic_name);
3828 }
3829 }
3830
3831 /* Fill the return structure. */
3832 ret = ctx->return_value;
3833
3834 /* Set SGPRs. */
3835 ret = LLVMBuildInsertValue(builder, ret,
3836 ac_to_integer(&ctx->ac,
3837 LLVMGetParam(ctx->main_fn,
3838 SI_PARAM_ALPHA_REF)),
3839 SI_SGPR_ALPHA_REF, "");
3840
3841 /* Set VGPRs */
3842 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3843 for (i = 0; i < ARRAY_SIZE(color); i++) {
3844 if (!color[i][0])
3845 continue;
3846
3847 for (j = 0; j < 4; j++)
3848 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3849 }
3850 if (depth)
3851 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3852 if (stencil)
3853 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3854 if (samplemask)
3855 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3856
3857 /* Add the input sample mask for smoothing at the end. */
3858 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3859 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3860 ret = LLVMBuildInsertValue(builder, ret,
3861 LLVMGetParam(ctx->main_fn,
3862 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3863
3864 ctx->return_value = ret;
3865 }
3866
3867 static void membar_emit(
3868 const struct lp_build_tgsi_action *action,
3869 struct lp_build_tgsi_context *bld_base,
3870 struct lp_build_emit_data *emit_data)
3871 {
3872 struct si_shader_context *ctx = si_shader_context(bld_base);
3873 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3874 unsigned flags = LLVMConstIntGetZExtValue(src0);
3875 unsigned waitcnt = NOOP_WAITCNT;
3876
3877 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3878 waitcnt &= VM_CNT & LGKM_CNT;
3879
3880 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3881 TGSI_MEMBAR_SHADER_BUFFER |
3882 TGSI_MEMBAR_SHADER_IMAGE))
3883 waitcnt &= VM_CNT;
3884
3885 if (flags & TGSI_MEMBAR_SHARED)
3886 waitcnt &= LGKM_CNT;
3887
3888 if (waitcnt != NOOP_WAITCNT)
3889 ac_build_waitcnt(&ctx->ac, waitcnt);
3890 }
3891
3892 static void clock_emit(
3893 const struct lp_build_tgsi_action *action,
3894 struct lp_build_tgsi_context *bld_base,
3895 struct lp_build_emit_data *emit_data)
3896 {
3897 struct si_shader_context *ctx = si_shader_context(bld_base);
3898 LLVMValueRef tmp = ac_build_shader_clock(&ctx->ac);
3899
3900 emit_data->output[0] =
3901 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3902 emit_data->output[1] =
3903 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3904 }
3905
3906 static void si_llvm_emit_ddxy(
3907 const struct lp_build_tgsi_action *action,
3908 struct lp_build_tgsi_context *bld_base,
3909 struct lp_build_emit_data *emit_data)
3910 {
3911 struct si_shader_context *ctx = si_shader_context(bld_base);
3912 unsigned opcode = emit_data->info->opcode;
3913 LLVMValueRef val;
3914 int idx;
3915 unsigned mask;
3916
3917 if (opcode == TGSI_OPCODE_DDX_FINE)
3918 mask = AC_TID_MASK_LEFT;
3919 else if (opcode == TGSI_OPCODE_DDY_FINE)
3920 mask = AC_TID_MASK_TOP;
3921 else
3922 mask = AC_TID_MASK_TOP_LEFT;
3923
3924 /* for DDX we want to next X pixel, DDY next Y pixel. */
3925 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3926
3927 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3928 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3929 emit_data->output[emit_data->chan] = val;
3930 }
3931
3932 /*
3933 * this takes an I,J coordinate pair,
3934 * and works out the X and Y derivatives.
3935 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3936 */
3937 static LLVMValueRef si_llvm_emit_ddxy_interp(
3938 struct lp_build_tgsi_context *bld_base,
3939 LLVMValueRef interp_ij)
3940 {
3941 struct si_shader_context *ctx = si_shader_context(bld_base);
3942 LLVMValueRef result[4], a;
3943 unsigned i;
3944
3945 for (i = 0; i < 2; i++) {
3946 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
3947 LLVMConstInt(ctx->i32, i, 0), "");
3948 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
3949 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
3950 }
3951
3952 return lp_build_gather_values(&ctx->gallivm, result, 4);
3953 }
3954
3955 static void interp_fetch_args(
3956 struct lp_build_tgsi_context *bld_base,
3957 struct lp_build_emit_data *emit_data)
3958 {
3959 struct si_shader_context *ctx = si_shader_context(bld_base);
3960 const struct tgsi_full_instruction *inst = emit_data->inst;
3961
3962 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3963 /* offset is in second src, first two channels */
3964 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3965 emit_data->inst, 1,
3966 TGSI_CHAN_X);
3967 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3968 emit_data->inst, 1,
3969 TGSI_CHAN_Y);
3970 emit_data->arg_count = 2;
3971 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3972 LLVMValueRef sample_position;
3973 LLVMValueRef sample_id;
3974 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3975
3976 /* fetch sample ID, then fetch its sample position,
3977 * and place into first two channels.
3978 */
3979 sample_id = lp_build_emit_fetch(bld_base,
3980 emit_data->inst, 1, TGSI_CHAN_X);
3981 sample_id = ac_to_integer(&ctx->ac, sample_id);
3982
3983 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
3984 * Language 4.50 spec says about interpolateAtSample:
3985 *
3986 * "Returns the value of the input interpolant variable at
3987 * the location of sample number sample. If multisample
3988 * buffers are not available, the input variable will be
3989 * evaluated at the center of the pixel. If sample sample
3990 * does not exist, the position used to interpolate the
3991 * input variable is undefined."
3992 *
3993 * This means that sample_id values outside of the valid are
3994 * in fact valid input, and the usual mechanism for loading the
3995 * sample position doesn't work.
3996 */
3997 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
3998 LLVMValueRef center[4] = {
3999 LLVMConstReal(ctx->f32, 0.5),
4000 LLVMConstReal(ctx->f32, 0.5),
4001 ctx->ac.f32_0,
4002 ctx->ac.f32_0,
4003 };
4004
4005 sample_position = lp_build_gather_values(&ctx->gallivm, center, 4);
4006 } else {
4007 sample_position = load_sample_position(&ctx->abi, sample_id);
4008 }
4009
4010 emit_data->args[0] = LLVMBuildExtractElement(ctx->ac.builder,
4011 sample_position,
4012 ctx->i32_0, "");
4013
4014 emit_data->args[0] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[0], halfval, "");
4015 emit_data->args[1] = LLVMBuildExtractElement(ctx->ac.builder,
4016 sample_position,
4017 ctx->i32_1, "");
4018 emit_data->args[1] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[1], halfval, "");
4019 emit_data->arg_count = 2;
4020 }
4021 }
4022
4023 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
4024 struct lp_build_tgsi_context *bld_base,
4025 struct lp_build_emit_data *emit_data)
4026 {
4027 struct si_shader_context *ctx = si_shader_context(bld_base);
4028 struct si_shader *shader = ctx->shader;
4029 const struct tgsi_shader_info *info = &shader->selector->info;
4030 LLVMValueRef interp_param;
4031 const struct tgsi_full_instruction *inst = emit_data->inst;
4032 const struct tgsi_full_src_register *input = &inst->Src[0];
4033 int input_base, input_array_size;
4034 int chan;
4035 int i;
4036 LLVMValueRef prim_mask = ctx->abi.prim_mask;
4037 LLVMValueRef array_idx;
4038 int interp_param_idx;
4039 unsigned interp;
4040 unsigned location;
4041
4042 assert(input->Register.File == TGSI_FILE_INPUT);
4043
4044 if (input->Register.Indirect) {
4045 unsigned array_id = input->Indirect.ArrayID;
4046
4047 if (array_id) {
4048 input_base = info->input_array_first[array_id];
4049 input_array_size = info->input_array_last[array_id] - input_base + 1;
4050 } else {
4051 input_base = inst->Src[0].Register.Index;
4052 input_array_size = info->num_inputs - input_base;
4053 }
4054
4055 array_idx = si_get_indirect_index(ctx, &input->Indirect,
4056 1, input->Register.Index - input_base);
4057 } else {
4058 input_base = inst->Src[0].Register.Index;
4059 input_array_size = 1;
4060 array_idx = ctx->i32_0;
4061 }
4062
4063 interp = shader->selector->info.input_interpolate[input_base];
4064
4065 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4066 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4067 location = TGSI_INTERPOLATE_LOC_CENTER;
4068 else
4069 location = TGSI_INTERPOLATE_LOC_CENTROID;
4070
4071 interp_param_idx = lookup_interp_param_index(interp, location);
4072 if (interp_param_idx == -1)
4073 return;
4074 else if (interp_param_idx)
4075 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4076 else
4077 interp_param = NULL;
4078
4079 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4080 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4081 LLVMValueRef ij_out[2];
4082 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
4083
4084 /*
4085 * take the I then J parameters, and the DDX/Y for it, and
4086 * calculate the IJ inputs for the interpolator.
4087 * temp1 = ddx * offset/sample.x + I;
4088 * interp_param.I = ddy * offset/sample.y + temp1;
4089 * temp1 = ddx * offset/sample.x + J;
4090 * interp_param.J = ddy * offset/sample.y + temp1;
4091 */
4092 for (i = 0; i < 2; i++) {
4093 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
4094 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
4095 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4096 ddxy_out, ix_ll, "");
4097 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4098 ddxy_out, iy_ll, "");
4099 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4100 interp_param, ix_ll, "");
4101 LLVMValueRef temp1, temp2;
4102
4103 interp_el = ac_to_float(&ctx->ac, interp_el);
4104
4105 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, emit_data->args[0], "");
4106
4107 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4108
4109 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, emit_data->args[1], "");
4110
4111 ij_out[i] = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4112 }
4113 interp_param = lp_build_gather_values(&ctx->gallivm, ij_out, 2);
4114 }
4115
4116 if (interp_param)
4117 interp_param = ac_to_float(&ctx->ac, interp_param);
4118
4119 for (chan = 0; chan < 4; chan++) {
4120 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
4121 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4122
4123 for (unsigned idx = 0; idx < input_array_size; ++idx) {
4124 LLVMValueRef v, i = NULL, j = NULL;
4125
4126 if (interp_param) {
4127 i = LLVMBuildExtractElement(
4128 ctx->ac.builder, interp_param, ctx->i32_0, "");
4129 j = LLVMBuildExtractElement(
4130 ctx->ac.builder, interp_param, ctx->i32_1, "");
4131 }
4132 v = si_build_fs_interp(ctx, input_base + idx, schan,
4133 prim_mask, i, j);
4134
4135 gather = LLVMBuildInsertElement(ctx->ac.builder,
4136 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
4137 }
4138
4139 emit_data->output[chan] = LLVMBuildExtractElement(
4140 ctx->ac.builder, gather, array_idx, "");
4141 }
4142 }
4143
4144 static void vote_all_emit(
4145 const struct lp_build_tgsi_action *action,
4146 struct lp_build_tgsi_context *bld_base,
4147 struct lp_build_emit_data *emit_data)
4148 {
4149 struct si_shader_context *ctx = si_shader_context(bld_base);
4150
4151 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
4152 emit_data->output[emit_data->chan] =
4153 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4154 }
4155
4156 static void vote_any_emit(
4157 const struct lp_build_tgsi_action *action,
4158 struct lp_build_tgsi_context *bld_base,
4159 struct lp_build_emit_data *emit_data)
4160 {
4161 struct si_shader_context *ctx = si_shader_context(bld_base);
4162
4163 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
4164 emit_data->output[emit_data->chan] =
4165 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4166 }
4167
4168 static void vote_eq_emit(
4169 const struct lp_build_tgsi_action *action,
4170 struct lp_build_tgsi_context *bld_base,
4171 struct lp_build_emit_data *emit_data)
4172 {
4173 struct si_shader_context *ctx = si_shader_context(bld_base);
4174
4175 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4176 emit_data->output[emit_data->chan] =
4177 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4178 }
4179
4180 static void ballot_emit(
4181 const struct lp_build_tgsi_action *action,
4182 struct lp_build_tgsi_context *bld_base,
4183 struct lp_build_emit_data *emit_data)
4184 {
4185 struct si_shader_context *ctx = si_shader_context(bld_base);
4186 LLVMBuilderRef builder = ctx->ac.builder;
4187 LLVMValueRef tmp;
4188
4189 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4190 tmp = ac_build_ballot(&ctx->ac, tmp);
4191 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4192
4193 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4194 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4195 }
4196
4197 static void read_invoc_fetch_args(
4198 struct lp_build_tgsi_context *bld_base,
4199 struct lp_build_emit_data *emit_data)
4200 {
4201 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4202 0, emit_data->src_chan);
4203
4204 /* Always read the source invocation (= lane) from the X channel. */
4205 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4206 1, TGSI_CHAN_X);
4207 emit_data->arg_count = 2;
4208 }
4209
4210 static void read_lane_emit(
4211 const struct lp_build_tgsi_action *action,
4212 struct lp_build_tgsi_context *bld_base,
4213 struct lp_build_emit_data *emit_data)
4214 {
4215 struct si_shader_context *ctx = si_shader_context(bld_base);
4216
4217 /* We currently have no other way to prevent LLVM from lifting the icmp
4218 * calls to a dominating basic block.
4219 */
4220 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4221
4222 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4223 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4224
4225 emit_data->output[emit_data->chan] =
4226 ac_build_intrinsic(&ctx->ac, action->intr_name,
4227 ctx->i32, emit_data->args, emit_data->arg_count,
4228 AC_FUNC_ATTR_READNONE |
4229 AC_FUNC_ATTR_CONVERGENT);
4230 }
4231
4232 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4233 struct lp_build_emit_data *emit_data)
4234 {
4235 struct si_shader_context *ctx = si_shader_context(bld_base);
4236 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4237 LLVMValueRef imm;
4238 unsigned stream;
4239
4240 assert(src0.File == TGSI_FILE_IMMEDIATE);
4241
4242 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4243 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4244 return stream;
4245 }
4246
4247 /* Emit one vertex from the geometry shader */
4248 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4249 unsigned stream,
4250 LLVMValueRef *addrs)
4251 {
4252 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4253 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4254 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
4255 struct si_shader *shader = ctx->shader;
4256 struct lp_build_if_state if_state;
4257 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4258 ctx->param_gs2vs_offset);
4259 LLVMValueRef gs_next_vertex;
4260 LLVMValueRef can_emit;
4261 unsigned chan, offset;
4262 int i;
4263
4264 /* Write vertex attribute values to GSVS ring */
4265 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4266 ctx->gs_next_vertex[stream],
4267 "");
4268
4269 /* If this thread has already emitted the declared maximum number of
4270 * vertices, skip the write: excessive vertex emissions are not
4271 * supposed to have any effect.
4272 *
4273 * If the shader has no writes to memory, kill it instead. This skips
4274 * further memory loads and may allow LLVM to skip to the end
4275 * altogether.
4276 */
4277 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4278 LLVMConstInt(ctx->i32,
4279 shader->selector->gs_max_out_vertices, 0), "");
4280
4281 bool use_kill = !info->writes_memory;
4282 if (use_kill) {
4283 ac_build_kill_if_false(&ctx->ac, can_emit);
4284 } else {
4285 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4286 }
4287
4288 offset = 0;
4289 for (i = 0; i < info->num_outputs; i++) {
4290 for (chan = 0; chan < 4; chan++) {
4291 if (!(info->output_usagemask[i] & (1 << chan)) ||
4292 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4293 continue;
4294
4295 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4296 LLVMValueRef voffset =
4297 LLVMConstInt(ctx->i32, offset *
4298 shader->selector->gs_max_out_vertices, 0);
4299 offset++;
4300
4301 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4302 voffset = lp_build_mul_imm(uint, voffset, 4);
4303
4304 out_val = ac_to_integer(&ctx->ac, out_val);
4305
4306 ac_build_buffer_store_dword(&ctx->ac,
4307 ctx->gsvs_ring[stream],
4308 out_val, 1,
4309 voffset, soffset, 0,
4310 1, 1, true, true);
4311 }
4312 }
4313
4314 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4315 ctx->i32_1);
4316
4317 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4318
4319 /* Signal vertex emission */
4320 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4321 si_get_gs_wave_id(ctx));
4322 if (!use_kill)
4323 lp_build_endif(&if_state);
4324 }
4325
4326 /* Emit one vertex from the geometry shader */
4327 static void si_tgsi_emit_vertex(
4328 const struct lp_build_tgsi_action *action,
4329 struct lp_build_tgsi_context *bld_base,
4330 struct lp_build_emit_data *emit_data)
4331 {
4332 struct si_shader_context *ctx = si_shader_context(bld_base);
4333 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4334
4335 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4336 }
4337
4338 /* Cut one primitive from the geometry shader */
4339 static void si_llvm_emit_primitive(struct ac_shader_abi *abi,
4340 unsigned stream)
4341 {
4342 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4343
4344 /* Signal primitive cut */
4345 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4346 si_get_gs_wave_id(ctx));
4347 }
4348
4349 /* Cut one primitive from the geometry shader */
4350 static void si_tgsi_emit_primitive(
4351 const struct lp_build_tgsi_action *action,
4352 struct lp_build_tgsi_context *bld_base,
4353 struct lp_build_emit_data *emit_data)
4354 {
4355 struct si_shader_context *ctx = si_shader_context(bld_base);
4356
4357 si_llvm_emit_primitive(&ctx->abi, si_llvm_get_stream(bld_base, emit_data));
4358 }
4359
4360 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4361 struct lp_build_tgsi_context *bld_base,
4362 struct lp_build_emit_data *emit_data)
4363 {
4364 struct si_shader_context *ctx = si_shader_context(bld_base);
4365
4366 /* SI only (thanks to a hw bug workaround):
4367 * The real barrier instruction isn’t needed, because an entire patch
4368 * always fits into a single wave.
4369 */
4370 if (ctx->screen->info.chip_class == SI &&
4371 ctx->type == PIPE_SHADER_TESS_CTRL) {
4372 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
4373 return;
4374 }
4375
4376 lp_build_intrinsic(ctx->ac.builder,
4377 "llvm.amdgcn.s.barrier",
4378 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
4379 }
4380
4381 static const struct lp_build_tgsi_action interp_action = {
4382 .fetch_args = interp_fetch_args,
4383 .emit = build_interp_intrinsic,
4384 };
4385
4386 static void si_create_function(struct si_shader_context *ctx,
4387 const char *name,
4388 LLVMTypeRef *returns, unsigned num_returns,
4389 struct si_function_info *fninfo,
4390 unsigned max_workgroup_size)
4391 {
4392 int i;
4393
4394 si_llvm_create_func(ctx, name, returns, num_returns,
4395 fninfo->types, fninfo->num_params);
4396 ctx->return_value = LLVMGetUndef(ctx->return_type);
4397
4398 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4399 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4400
4401 /* The combination of:
4402 * - noalias
4403 * - dereferenceable
4404 * - invariant.load
4405 * allows the optimization passes to move loads and reduces
4406 * SGPR spilling significantly.
4407 */
4408 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
4409
4410 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4411 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
4412 ac_add_attr_dereferenceable(P, UINT64_MAX);
4413 }
4414 }
4415
4416 for (i = 0; i < fninfo->num_params; ++i) {
4417 if (fninfo->assign[i])
4418 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4419 }
4420
4421 si_llvm_add_attribute(ctx->main_fn, "amdgpu-32bit-address-high-bits",
4422 ctx->screen->info.address32_hi);
4423
4424 if (max_workgroup_size) {
4425 si_llvm_add_attribute(ctx->main_fn, "amdgpu-max-work-group-size",
4426 max_workgroup_size);
4427 }
4428 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4429 "no-signed-zeros-fp-math",
4430 "true");
4431
4432 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4433 /* These were copied from some LLVM test. */
4434 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4435 "less-precise-fpmad",
4436 "true");
4437 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4438 "no-infs-fp-math",
4439 "true");
4440 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4441 "no-nans-fp-math",
4442 "true");
4443 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4444 "unsafe-fp-math",
4445 "true");
4446 }
4447 }
4448
4449 static void declare_streamout_params(struct si_shader_context *ctx,
4450 struct pipe_stream_output_info *so,
4451 struct si_function_info *fninfo)
4452 {
4453 int i;
4454
4455 /* Streamout SGPRs. */
4456 if (so->num_outputs) {
4457 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4458 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4459 else
4460 ctx->param_streamout_config = fninfo->num_params - 1;
4461
4462 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4463 }
4464 /* A streamout buffer offset is loaded if the stride is non-zero. */
4465 for (i = 0; i < 4; i++) {
4466 if (!so->stride[i])
4467 continue;
4468
4469 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4470 }
4471 }
4472
4473 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4474 {
4475 switch (shader->selector->type) {
4476 case PIPE_SHADER_TESS_CTRL:
4477 /* Return this so that LLVM doesn't remove s_barrier
4478 * instructions on chips where we use s_barrier. */
4479 return shader->selector->screen->info.chip_class >= CIK ? 128 : 64;
4480
4481 case PIPE_SHADER_GEOMETRY:
4482 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4483
4484 case PIPE_SHADER_COMPUTE:
4485 break; /* see below */
4486
4487 default:
4488 return 0;
4489 }
4490
4491 const unsigned *properties = shader->selector->info.properties;
4492 unsigned max_work_group_size =
4493 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4494 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4495 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4496
4497 if (!max_work_group_size) {
4498 /* This is a variable group size compute shader,
4499 * compile it for the maximum possible group size.
4500 */
4501 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4502 }
4503 return max_work_group_size;
4504 }
4505
4506 static void declare_const_and_shader_buffers(struct si_shader_context *ctx,
4507 struct si_function_info *fninfo,
4508 bool assign_params)
4509 {
4510 LLVMTypeRef const_shader_buf_type;
4511
4512 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4513 ctx->shader->selector->info.shader_buffers_declared == 0)
4514 const_shader_buf_type = ctx->f32;
4515 else
4516 const_shader_buf_type = ctx->v4i32;
4517
4518 unsigned const_and_shader_buffers =
4519 add_arg(fninfo, ARG_SGPR,
4520 ac_array_in_const32_addr_space(const_shader_buf_type));
4521
4522 if (assign_params)
4523 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4524 }
4525
4526 static void declare_samplers_and_images(struct si_shader_context *ctx,
4527 struct si_function_info *fninfo,
4528 bool assign_params)
4529 {
4530 unsigned samplers_and_images =
4531 add_arg(fninfo, ARG_SGPR,
4532 ac_array_in_const32_addr_space(ctx->v8i32));
4533
4534 if (assign_params)
4535 ctx->param_samplers_and_images = samplers_and_images;
4536 }
4537
4538 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4539 struct si_function_info *fninfo,
4540 bool assign_params)
4541 {
4542 declare_const_and_shader_buffers(ctx, fninfo, assign_params);
4543 declare_samplers_and_images(ctx, fninfo, assign_params);
4544 }
4545
4546 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4547 struct si_function_info *fninfo)
4548 {
4549 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4550 ac_array_in_const32_addr_space(ctx->v4i32));
4551 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4552 ac_array_in_const32_addr_space(ctx->v8i32));
4553 }
4554
4555 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4556 struct si_function_info *fninfo)
4557 {
4558 ctx->param_vertex_buffers = add_arg(fninfo, ARG_SGPR,
4559 ac_array_in_const32_addr_space(ctx->v4i32));
4560 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4561 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4562 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4563 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4564 }
4565
4566 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4567 struct si_function_info *fninfo,
4568 unsigned *num_prolog_vgprs)
4569 {
4570 struct si_shader *shader = ctx->shader;
4571
4572 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4573 if (shader->key.as_ls) {
4574 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4575 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4576 } else {
4577 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4578 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4579 }
4580 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4581
4582 if (!shader->is_gs_copy_shader) {
4583 /* Vertex load indices. */
4584 ctx->param_vertex_index0 = fninfo->num_params;
4585 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4586 add_arg(fninfo, ARG_VGPR, ctx->i32);
4587 *num_prolog_vgprs += shader->selector->info.num_inputs;
4588 }
4589 }
4590
4591 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4592 struct si_function_info *fninfo)
4593 {
4594 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4595 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4596 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4597 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
4598 }
4599
4600 enum {
4601 /* Convenient merged shader definitions. */
4602 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4603 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4604 };
4605
4606 static void create_function(struct si_shader_context *ctx)
4607 {
4608 struct si_shader *shader = ctx->shader;
4609 struct si_function_info fninfo;
4610 LLVMTypeRef returns[16+32*4];
4611 unsigned i, num_return_sgprs;
4612 unsigned num_returns = 0;
4613 unsigned num_prolog_vgprs = 0;
4614 unsigned type = ctx->type;
4615 unsigned vs_blit_property =
4616 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4617
4618 si_init_function_info(&fninfo);
4619
4620 /* Set MERGED shaders. */
4621 if (ctx->screen->info.chip_class >= GFX9) {
4622 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4623 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4624 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4625 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4626 }
4627
4628 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4629
4630 switch (type) {
4631 case PIPE_SHADER_VERTEX:
4632 declare_global_desc_pointers(ctx, &fninfo);
4633
4634 if (vs_blit_property) {
4635 ctx->param_vs_blit_inputs = fninfo.num_params;
4636 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4637 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4638 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* depth */
4639
4640 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4641 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color0 */
4642 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color1 */
4643 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color2 */
4644 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color3 */
4645 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4646 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4647 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4648 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4649 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4650 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4651 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4652 }
4653
4654 /* VGPRs */
4655 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4656 break;
4657 }
4658
4659 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4660 declare_vs_specific_input_sgprs(ctx, &fninfo);
4661
4662 if (shader->key.as_es) {
4663 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4664 } else if (shader->key.as_ls) {
4665 /* no extra parameters */
4666 } else {
4667 if (shader->is_gs_copy_shader) {
4668 fninfo.num_params = ctx->param_rw_buffers + 1;
4669 fninfo.num_sgpr_params = fninfo.num_params;
4670 }
4671
4672 /* The locations of the other parameters are assigned dynamically. */
4673 declare_streamout_params(ctx, &shader->selector->so,
4674 &fninfo);
4675 }
4676
4677 /* VGPRs */
4678 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4679 break;
4680
4681 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4682 declare_global_desc_pointers(ctx, &fninfo);
4683 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4684 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4685 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4686 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4687 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4688 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4689 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4690
4691 /* VGPRs */
4692 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4693 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4694
4695 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4696 * placed after the user SGPRs.
4697 */
4698 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4699 returns[num_returns++] = ctx->i32; /* SGPRs */
4700 for (i = 0; i < 11; i++)
4701 returns[num_returns++] = ctx->f32; /* VGPRs */
4702 break;
4703
4704 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4705 /* Merged stages have 8 system SGPRs at the beginning. */
4706 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
4707 if (HAVE_32BIT_POINTERS) {
4708 declare_per_stage_desc_pointers(ctx, &fninfo,
4709 ctx->type == PIPE_SHADER_TESS_CTRL);
4710 } else {
4711 declare_const_and_shader_buffers(ctx, &fninfo,
4712 ctx->type == PIPE_SHADER_TESS_CTRL);
4713 }
4714 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4715 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4716 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4717 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4718 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4719 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4720
4721 declare_global_desc_pointers(ctx, &fninfo);
4722 declare_per_stage_desc_pointers(ctx, &fninfo,
4723 ctx->type == PIPE_SHADER_VERTEX);
4724 declare_vs_specific_input_sgprs(ctx, &fninfo);
4725
4726 if (!HAVE_32BIT_POINTERS) {
4727 declare_samplers_and_images(ctx, &fninfo,
4728 ctx->type == PIPE_SHADER_TESS_CTRL);
4729 }
4730 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4731 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4732 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4733
4734 /* VGPRs (first TCS, then VS) */
4735 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4736 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4737
4738 if (ctx->type == PIPE_SHADER_VERTEX) {
4739 declare_vs_input_vgprs(ctx, &fninfo,
4740 &num_prolog_vgprs);
4741
4742 /* LS return values are inputs to the TCS main shader part. */
4743 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4744 returns[num_returns++] = ctx->i32; /* SGPRs */
4745 for (i = 0; i < 2; i++)
4746 returns[num_returns++] = ctx->f32; /* VGPRs */
4747 } else {
4748 /* TCS return values are inputs to the TCS epilog.
4749 *
4750 * param_tcs_offchip_offset, param_tcs_factor_offset,
4751 * param_tcs_offchip_layout, and param_rw_buffers
4752 * should be passed to the epilog.
4753 */
4754 for (i = 0; i <= 8 + GFX9_SGPR_TCS_OUT_LAYOUT; i++)
4755 returns[num_returns++] = ctx->i32; /* SGPRs */
4756 for (i = 0; i < 11; i++)
4757 returns[num_returns++] = ctx->f32; /* VGPRs */
4758 }
4759 break;
4760
4761 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4762 /* Merged stages have 8 system SGPRs at the beginning. */
4763 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
4764 if (HAVE_32BIT_POINTERS) {
4765 declare_per_stage_desc_pointers(ctx, &fninfo,
4766 ctx->type == PIPE_SHADER_GEOMETRY);
4767 } else {
4768 declare_const_and_shader_buffers(ctx, &fninfo,
4769 ctx->type == PIPE_SHADER_GEOMETRY);
4770 }
4771 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4772 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4773 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4774 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4775 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4776 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4777
4778 declare_global_desc_pointers(ctx, &fninfo);
4779 declare_per_stage_desc_pointers(ctx, &fninfo,
4780 (ctx->type == PIPE_SHADER_VERTEX ||
4781 ctx->type == PIPE_SHADER_TESS_EVAL));
4782 if (ctx->type == PIPE_SHADER_VERTEX) {
4783 declare_vs_specific_input_sgprs(ctx, &fninfo);
4784 } else {
4785 /* TESS_EVAL (and also GEOMETRY):
4786 * Declare as many input SGPRs as the VS has. */
4787 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4788 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4789 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4790 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4791 if (!HAVE_32BIT_POINTERS)
4792 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4793 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4794 }
4795
4796 if (!HAVE_32BIT_POINTERS) {
4797 declare_samplers_and_images(ctx, &fninfo,
4798 ctx->type == PIPE_SHADER_GEOMETRY);
4799 }
4800
4801 /* VGPRs (first GS, then VS/TES) */
4802 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4803 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4804 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4805 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4806 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4807
4808 if (ctx->type == PIPE_SHADER_VERTEX) {
4809 declare_vs_input_vgprs(ctx, &fninfo,
4810 &num_prolog_vgprs);
4811 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4812 declare_tes_input_vgprs(ctx, &fninfo);
4813 }
4814
4815 if (ctx->type == PIPE_SHADER_VERTEX ||
4816 ctx->type == PIPE_SHADER_TESS_EVAL) {
4817 /* ES return values are inputs to GS. */
4818 for (i = 0; i < 8 + GFX9_GS_NUM_USER_SGPR; i++)
4819 returns[num_returns++] = ctx->i32; /* SGPRs */
4820 for (i = 0; i < 5; i++)
4821 returns[num_returns++] = ctx->f32; /* VGPRs */
4822 }
4823 break;
4824
4825 case PIPE_SHADER_TESS_EVAL:
4826 declare_global_desc_pointers(ctx, &fninfo);
4827 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4828 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4829 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4830
4831 if (shader->key.as_es) {
4832 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4833 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4834 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4835 } else {
4836 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4837 declare_streamout_params(ctx, &shader->selector->so,
4838 &fninfo);
4839 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4840 }
4841
4842 /* VGPRs */
4843 declare_tes_input_vgprs(ctx, &fninfo);
4844 break;
4845
4846 case PIPE_SHADER_GEOMETRY:
4847 declare_global_desc_pointers(ctx, &fninfo);
4848 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4849 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4850 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4851
4852 /* VGPRs */
4853 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4854 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4855 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4856 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4857 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4858 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4859 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4860 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4861 break;
4862
4863 case PIPE_SHADER_FRAGMENT:
4864 declare_global_desc_pointers(ctx, &fninfo);
4865 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4866 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4867 add_arg_assign_checked(&fninfo, ARG_SGPR, ctx->i32,
4868 &ctx->abi.prim_mask, SI_PARAM_PRIM_MASK);
4869
4870 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4871 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4872 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4873 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4874 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4875 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4876 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4877 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4878 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4879 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4880 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4881 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4882 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4883 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4884 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4885 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4886 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4887 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4888 shader->info.face_vgpr_index = 20;
4889 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4890 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4891 shader->info.ancillary_vgpr_index = 21;
4892 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4893 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4894 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4895
4896 /* Color inputs from the prolog. */
4897 if (shader->selector->info.colors_read) {
4898 unsigned num_color_elements =
4899 util_bitcount(shader->selector->info.colors_read);
4900
4901 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4902 for (i = 0; i < num_color_elements; i++)
4903 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4904
4905 num_prolog_vgprs += num_color_elements;
4906 }
4907
4908 /* Outputs for the epilog. */
4909 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4910 num_returns =
4911 num_return_sgprs +
4912 util_bitcount(shader->selector->info.colors_written) * 4 +
4913 shader->selector->info.writes_z +
4914 shader->selector->info.writes_stencil +
4915 shader->selector->info.writes_samplemask +
4916 1 /* SampleMaskIn */;
4917
4918 num_returns = MAX2(num_returns,
4919 num_return_sgprs +
4920 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4921
4922 for (i = 0; i < num_return_sgprs; i++)
4923 returns[i] = ctx->i32;
4924 for (; i < num_returns; i++)
4925 returns[i] = ctx->f32;
4926 break;
4927
4928 case PIPE_SHADER_COMPUTE:
4929 declare_global_desc_pointers(ctx, &fninfo);
4930 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4931 if (shader->selector->info.uses_grid_size)
4932 add_arg_assign(&fninfo, ARG_SGPR, v3i32, &ctx->abi.num_work_groups);
4933 if (shader->selector->info.uses_block_size)
4934 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4935
4936 for (i = 0; i < 3; i++) {
4937 ctx->abi.workgroup_ids[i] = NULL;
4938 if (shader->selector->info.uses_block_id[i])
4939 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->abi.workgroup_ids[i]);
4940 }
4941
4942 add_arg_assign(&fninfo, ARG_VGPR, v3i32, &ctx->abi.local_invocation_ids);
4943 break;
4944 default:
4945 assert(0 && "unimplemented shader");
4946 return;
4947 }
4948
4949 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4950 si_get_max_workgroup_size(shader));
4951
4952 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4953 if (ctx->type == PIPE_SHADER_FRAGMENT &&
4954 ctx->separate_prolog) {
4955 si_llvm_add_attribute(ctx->main_fn,
4956 "InitialPSInputAddr",
4957 S_0286D0_PERSP_SAMPLE_ENA(1) |
4958 S_0286D0_PERSP_CENTER_ENA(1) |
4959 S_0286D0_PERSP_CENTROID_ENA(1) |
4960 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4961 S_0286D0_LINEAR_CENTER_ENA(1) |
4962 S_0286D0_LINEAR_CENTROID_ENA(1) |
4963 S_0286D0_FRONT_FACE_ENA(1) |
4964 S_0286D0_ANCILLARY_ENA(1) |
4965 S_0286D0_POS_FIXED_PT_ENA(1));
4966 }
4967
4968 shader->info.num_input_sgprs = 0;
4969 shader->info.num_input_vgprs = 0;
4970
4971 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4972 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
4973
4974 for (; i < fninfo.num_params; ++i)
4975 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
4976
4977 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4978 shader->info.num_input_vgprs -= num_prolog_vgprs;
4979
4980 if (shader->key.as_ls ||
4981 ctx->type == PIPE_SHADER_TESS_CTRL ||
4982 /* GFX9 has the ESGS ring buffer in LDS. */
4983 type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY)
4984 ac_declare_lds_as_pointer(&ctx->ac);
4985 }
4986
4987 /**
4988 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4989 * for later use.
4990 */
4991 static void preload_ring_buffers(struct si_shader_context *ctx)
4992 {
4993 LLVMBuilderRef builder = ctx->ac.builder;
4994
4995 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
4996 ctx->param_rw_buffers);
4997
4998 if (ctx->screen->info.chip_class <= VI &&
4999 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
5000 unsigned ring =
5001 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5002 : SI_ES_RING_ESGS;
5003 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
5004
5005 ctx->esgs_ring =
5006 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5007 }
5008
5009 if (ctx->shader->is_gs_copy_shader) {
5010 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5011
5012 ctx->gsvs_ring[0] =
5013 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5014 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5015 const struct si_shader_selector *sel = ctx->shader->selector;
5016 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5017 LLVMValueRef base_ring;
5018
5019 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5020
5021 /* The conceptual layout of the GSVS ring is
5022 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5023 * but the real memory layout is swizzled across
5024 * threads:
5025 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5026 * t16v0c0 ..
5027 * Override the buffer descriptor accordingly.
5028 */
5029 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5030 uint64_t stream_offset = 0;
5031
5032 for (unsigned stream = 0; stream < 4; ++stream) {
5033 unsigned num_components;
5034 unsigned stride;
5035 unsigned num_records;
5036 LLVMValueRef ring, tmp;
5037
5038 num_components = sel->info.num_stream_output_components[stream];
5039 if (!num_components)
5040 continue;
5041
5042 stride = 4 * num_components * sel->gs_max_out_vertices;
5043
5044 /* Limit on the stride field for <= CIK. */
5045 assert(stride < (1 << 14));
5046
5047 num_records = 64;
5048
5049 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5050 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
5051 tmp = LLVMBuildAdd(builder, tmp,
5052 LLVMConstInt(ctx->i64,
5053 stream_offset, 0), "");
5054 stream_offset += stride * 64;
5055
5056 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5057 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5058 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5059 tmp = LLVMBuildOr(builder, tmp,
5060 LLVMConstInt(ctx->i32,
5061 S_008F04_STRIDE(stride) |
5062 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5063 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5064 ring = LLVMBuildInsertElement(builder, ring,
5065 LLVMConstInt(ctx->i32, num_records, 0),
5066 LLVMConstInt(ctx->i32, 2, 0), "");
5067 ring = LLVMBuildInsertElement(builder, ring,
5068 LLVMConstInt(ctx->i32,
5069 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5070 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5071 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5072 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5073 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5074 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5075 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5076 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5077 S_008F0C_ADD_TID_ENABLE(1),
5078 0),
5079 LLVMConstInt(ctx->i32, 3, 0), "");
5080
5081 ctx->gsvs_ring[stream] = ring;
5082 }
5083 }
5084 }
5085
5086 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5087 LLVMValueRef param_rw_buffers,
5088 unsigned param_pos_fixed_pt)
5089 {
5090 LLVMBuilderRef builder = ctx->ac.builder;
5091 LLVMValueRef slot, desc, offset, row, bit, address[2];
5092
5093 /* Use the fixed-point gl_FragCoord input.
5094 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5095 * per coordinate to get the repeating effect.
5096 */
5097 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5098 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5099
5100 /* Load the buffer descriptor. */
5101 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5102 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
5103
5104 /* The stipple pattern is 32x32, each row has 32 bits. */
5105 offset = LLVMBuildMul(builder, address[1],
5106 LLVMConstInt(ctx->i32, 4, 0), "");
5107 row = buffer_load_const(ctx, desc, offset);
5108 row = ac_to_integer(&ctx->ac, row);
5109 bit = LLVMBuildLShr(builder, row, address[0], "");
5110 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5111 ac_build_kill_if_false(&ctx->ac, bit);
5112 }
5113
5114 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5115 struct si_shader_config *conf,
5116 unsigned symbol_offset)
5117 {
5118 unsigned i;
5119 const unsigned char *config =
5120 ac_shader_binary_config_start(binary, symbol_offset);
5121 bool really_needs_scratch = false;
5122
5123 /* LLVM adds SGPR spills to the scratch size.
5124 * Find out if we really need the scratch buffer.
5125 */
5126 for (i = 0; i < binary->reloc_count; i++) {
5127 const struct ac_shader_reloc *reloc = &binary->relocs[i];
5128
5129 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5130 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5131 really_needs_scratch = true;
5132 break;
5133 }
5134 }
5135
5136 /* XXX: We may be able to emit some of these values directly rather than
5137 * extracting fields to be emitted later.
5138 */
5139
5140 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5141 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5142 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5143 switch (reg) {
5144 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5145 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5146 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5147 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
5148 case R_00B848_COMPUTE_PGM_RSRC1:
5149 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5150 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5151 conf->float_mode = G_00B028_FLOAT_MODE(value);
5152 conf->rsrc1 = value;
5153 break;
5154 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5155 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5156 break;
5157 case R_00B84C_COMPUTE_PGM_RSRC2:
5158 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5159 conf->rsrc2 = value;
5160 break;
5161 case R_0286CC_SPI_PS_INPUT_ENA:
5162 conf->spi_ps_input_ena = value;
5163 break;
5164 case R_0286D0_SPI_PS_INPUT_ADDR:
5165 conf->spi_ps_input_addr = value;
5166 break;
5167 case R_0286E8_SPI_TMPRING_SIZE:
5168 case R_00B860_COMPUTE_TMPRING_SIZE:
5169 /* WAVESIZE is in units of 256 dwords. */
5170 if (really_needs_scratch)
5171 conf->scratch_bytes_per_wave =
5172 G_00B860_WAVESIZE(value) * 256 * 4;
5173 break;
5174 case 0x4: /* SPILLED_SGPRS */
5175 conf->spilled_sgprs = value;
5176 break;
5177 case 0x8: /* SPILLED_VGPRS */
5178 conf->spilled_vgprs = value;
5179 break;
5180 default:
5181 {
5182 static bool printed;
5183
5184 if (!printed) {
5185 fprintf(stderr, "Warning: LLVM emitted unknown "
5186 "config register: 0x%x\n", reg);
5187 printed = true;
5188 }
5189 }
5190 break;
5191 }
5192 }
5193
5194 if (!conf->spi_ps_input_addr)
5195 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5196 }
5197
5198 void si_shader_apply_scratch_relocs(struct si_shader *shader,
5199 uint64_t scratch_va)
5200 {
5201 unsigned i;
5202 uint32_t scratch_rsrc_dword0 = scratch_va;
5203 uint32_t scratch_rsrc_dword1 =
5204 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5205
5206 /* Enable scratch coalescing. */
5207 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5208
5209 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5210 const struct ac_shader_reloc *reloc =
5211 &shader->binary.relocs[i];
5212 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5213 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5214 &scratch_rsrc_dword0, 4);
5215 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5216 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5217 &scratch_rsrc_dword1, 4);
5218 }
5219 }
5220 }
5221
5222 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
5223 {
5224 unsigned size = shader->binary.code_size;
5225
5226 if (shader->prolog)
5227 size += shader->prolog->binary.code_size;
5228 if (shader->previous_stage)
5229 size += shader->previous_stage->binary.code_size;
5230 if (shader->prolog2)
5231 size += shader->prolog2->binary.code_size;
5232 if (shader->epilog)
5233 size += shader->epilog->binary.code_size;
5234 return size;
5235 }
5236
5237 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5238 {
5239 const struct ac_shader_binary *prolog =
5240 shader->prolog ? &shader->prolog->binary : NULL;
5241 const struct ac_shader_binary *previous_stage =
5242 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5243 const struct ac_shader_binary *prolog2 =
5244 shader->prolog2 ? &shader->prolog2->binary : NULL;
5245 const struct ac_shader_binary *epilog =
5246 shader->epilog ? &shader->epilog->binary : NULL;
5247 const struct ac_shader_binary *mainb = &shader->binary;
5248 unsigned bo_size = si_get_shader_binary_size(shader) +
5249 (!epilog ? mainb->rodata_size : 0);
5250 unsigned char *ptr;
5251
5252 assert(!prolog || !prolog->rodata_size);
5253 assert(!previous_stage || !previous_stage->rodata_size);
5254 assert(!prolog2 || !prolog2->rodata_size);
5255 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5256 !mainb->rodata_size);
5257 assert(!epilog || !epilog->rodata_size);
5258
5259 r600_resource_reference(&shader->bo, NULL);
5260 shader->bo = (struct r600_resource*)
5261 si_aligned_buffer_create(&sscreen->b,
5262 sscreen->cpdma_prefetch_writes_memory ?
5263 0 : R600_RESOURCE_FLAG_READ_ONLY,
5264 PIPE_USAGE_IMMUTABLE,
5265 align(bo_size, SI_CPDMA_ALIGNMENT),
5266 256);
5267 if (!shader->bo)
5268 return -ENOMEM;
5269
5270 /* Upload. */
5271 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5272 PIPE_TRANSFER_READ_WRITE |
5273 PIPE_TRANSFER_UNSYNCHRONIZED);
5274
5275 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5276 * endian-independent. */
5277 if (prolog) {
5278 memcpy(ptr, prolog->code, prolog->code_size);
5279 ptr += prolog->code_size;
5280 }
5281 if (previous_stage) {
5282 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5283 ptr += previous_stage->code_size;
5284 }
5285 if (prolog2) {
5286 memcpy(ptr, prolog2->code, prolog2->code_size);
5287 ptr += prolog2->code_size;
5288 }
5289
5290 memcpy(ptr, mainb->code, mainb->code_size);
5291 ptr += mainb->code_size;
5292
5293 if (epilog)
5294 memcpy(ptr, epilog->code, epilog->code_size);
5295 else if (mainb->rodata_size > 0)
5296 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5297
5298 sscreen->ws->buffer_unmap(shader->bo->buf);
5299 return 0;
5300 }
5301
5302 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5303 struct pipe_debug_callback *debug,
5304 const char *name, FILE *file)
5305 {
5306 char *line, *p;
5307 unsigned i, count;
5308
5309 if (binary->disasm_string) {
5310 fprintf(file, "Shader %s disassembly:\n", name);
5311 fprintf(file, "%s", binary->disasm_string);
5312
5313 if (debug && debug->debug_message) {
5314 /* Very long debug messages are cut off, so send the
5315 * disassembly one line at a time. This causes more
5316 * overhead, but on the plus side it simplifies
5317 * parsing of resulting logs.
5318 */
5319 pipe_debug_message(debug, SHADER_INFO,
5320 "Shader Disassembly Begin");
5321
5322 line = binary->disasm_string;
5323 while (*line) {
5324 p = util_strchrnul(line, '\n');
5325 count = p - line;
5326
5327 if (count) {
5328 pipe_debug_message(debug, SHADER_INFO,
5329 "%.*s", count, line);
5330 }
5331
5332 if (!*p)
5333 break;
5334 line = p + 1;
5335 }
5336
5337 pipe_debug_message(debug, SHADER_INFO,
5338 "Shader Disassembly End");
5339 }
5340 } else {
5341 fprintf(file, "Shader %s binary:\n", name);
5342 for (i = 0; i < binary->code_size; i += 4) {
5343 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5344 binary->code[i + 3], binary->code[i + 2],
5345 binary->code[i + 1], binary->code[i]);
5346 }
5347 }
5348 }
5349
5350 static void si_calculate_max_simd_waves(struct si_shader *shader)
5351 {
5352 struct si_screen *sscreen = shader->selector->screen;
5353 struct si_shader_config *conf = &shader->config;
5354 unsigned num_inputs = shader->selector->info.num_inputs;
5355 unsigned lds_increment = sscreen->info.chip_class >= CIK ? 512 : 256;
5356 unsigned lds_per_wave = 0;
5357 unsigned max_simd_waves;
5358
5359 switch (sscreen->info.family) {
5360 /* These always have 8 waves: */
5361 case CHIP_POLARIS10:
5362 case CHIP_POLARIS11:
5363 case CHIP_POLARIS12:
5364 max_simd_waves = 8;
5365 break;
5366 default:
5367 max_simd_waves = 10;
5368 }
5369
5370 /* Compute LDS usage for PS. */
5371 switch (shader->selector->type) {
5372 case PIPE_SHADER_FRAGMENT:
5373 /* The minimum usage per wave is (num_inputs * 48). The maximum
5374 * usage is (num_inputs * 48 * 16).
5375 * We can get anything in between and it varies between waves.
5376 *
5377 * The 48 bytes per input for a single primitive is equal to
5378 * 4 bytes/component * 4 components/input * 3 points.
5379 *
5380 * Other stages don't know the size at compile time or don't
5381 * allocate LDS per wave, but instead they do it per thread group.
5382 */
5383 lds_per_wave = conf->lds_size * lds_increment +
5384 align(num_inputs * 48, lds_increment);
5385 break;
5386 case PIPE_SHADER_COMPUTE:
5387 if (shader->selector) {
5388 unsigned max_workgroup_size =
5389 si_get_max_workgroup_size(shader);
5390 lds_per_wave = (conf->lds_size * lds_increment) /
5391 DIV_ROUND_UP(max_workgroup_size, 64);
5392 }
5393 break;
5394 }
5395
5396 /* Compute the per-SIMD wave counts. */
5397 if (conf->num_sgprs) {
5398 if (sscreen->info.chip_class >= VI)
5399 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5400 else
5401 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5402 }
5403
5404 if (conf->num_vgprs)
5405 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5406
5407 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5408 * 16KB makes some SIMDs unoccupied). */
5409 if (lds_per_wave)
5410 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5411
5412 conf->max_simd_waves = max_simd_waves;
5413 }
5414
5415 void si_shader_dump_stats_for_shader_db(const struct si_shader *shader,
5416 struct pipe_debug_callback *debug)
5417 {
5418 const struct si_shader_config *conf = &shader->config;
5419
5420 pipe_debug_message(debug, SHADER_INFO,
5421 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5422 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5423 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5424 conf->num_sgprs, conf->num_vgprs,
5425 si_get_shader_binary_size(shader),
5426 conf->lds_size, conf->scratch_bytes_per_wave,
5427 conf->max_simd_waves, conf->spilled_sgprs,
5428 conf->spilled_vgprs, conf->private_mem_vgprs);
5429 }
5430
5431 static void si_shader_dump_stats(struct si_screen *sscreen,
5432 const struct si_shader *shader,
5433 unsigned processor,
5434 FILE *file,
5435 bool check_debug_option)
5436 {
5437 const struct si_shader_config *conf = &shader->config;
5438
5439 if (!check_debug_option ||
5440 si_can_dump_shader(sscreen, processor)) {
5441 if (processor == PIPE_SHADER_FRAGMENT) {
5442 fprintf(file, "*** SHADER CONFIG ***\n"
5443 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5444 "SPI_PS_INPUT_ENA = 0x%04x\n",
5445 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5446 }
5447
5448 fprintf(file, "*** SHADER STATS ***\n"
5449 "SGPRS: %d\n"
5450 "VGPRS: %d\n"
5451 "Spilled SGPRs: %d\n"
5452 "Spilled VGPRs: %d\n"
5453 "Private memory VGPRs: %d\n"
5454 "Code Size: %d bytes\n"
5455 "LDS: %d blocks\n"
5456 "Scratch: %d bytes per wave\n"
5457 "Max Waves: %d\n"
5458 "********************\n\n\n",
5459 conf->num_sgprs, conf->num_vgprs,
5460 conf->spilled_sgprs, conf->spilled_vgprs,
5461 conf->private_mem_vgprs,
5462 si_get_shader_binary_size(shader),
5463 conf->lds_size, conf->scratch_bytes_per_wave,
5464 conf->max_simd_waves);
5465 }
5466 }
5467
5468 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5469 {
5470 switch (processor) {
5471 case PIPE_SHADER_VERTEX:
5472 if (shader->key.as_es)
5473 return "Vertex Shader as ES";
5474 else if (shader->key.as_ls)
5475 return "Vertex Shader as LS";
5476 else
5477 return "Vertex Shader as VS";
5478 case PIPE_SHADER_TESS_CTRL:
5479 return "Tessellation Control Shader";
5480 case PIPE_SHADER_TESS_EVAL:
5481 if (shader->key.as_es)
5482 return "Tessellation Evaluation Shader as ES";
5483 else
5484 return "Tessellation Evaluation Shader as VS";
5485 case PIPE_SHADER_GEOMETRY:
5486 if (shader->is_gs_copy_shader)
5487 return "GS Copy Shader as VS";
5488 else
5489 return "Geometry Shader";
5490 case PIPE_SHADER_FRAGMENT:
5491 return "Pixel Shader";
5492 case PIPE_SHADER_COMPUTE:
5493 return "Compute Shader";
5494 default:
5495 return "Unknown Shader";
5496 }
5497 }
5498
5499 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5500 struct pipe_debug_callback *debug, unsigned processor,
5501 FILE *file, bool check_debug_option)
5502 {
5503 if (!check_debug_option ||
5504 si_can_dump_shader(sscreen, processor))
5505 si_dump_shader_key(processor, shader, file);
5506
5507 if (!check_debug_option && shader->binary.llvm_ir_string) {
5508 if (shader->previous_stage &&
5509 shader->previous_stage->binary.llvm_ir_string) {
5510 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5511 si_get_shader_name(shader, processor));
5512 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5513 }
5514
5515 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5516 si_get_shader_name(shader, processor));
5517 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5518 }
5519
5520 if (!check_debug_option ||
5521 (si_can_dump_shader(sscreen, processor) &&
5522 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5523 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5524
5525 if (shader->prolog)
5526 si_shader_dump_disassembly(&shader->prolog->binary,
5527 debug, "prolog", file);
5528 if (shader->previous_stage)
5529 si_shader_dump_disassembly(&shader->previous_stage->binary,
5530 debug, "previous stage", file);
5531 if (shader->prolog2)
5532 si_shader_dump_disassembly(&shader->prolog2->binary,
5533 debug, "prolog2", file);
5534
5535 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5536
5537 if (shader->epilog)
5538 si_shader_dump_disassembly(&shader->epilog->binary,
5539 debug, "epilog", file);
5540 fprintf(file, "\n");
5541 }
5542
5543 si_shader_dump_stats(sscreen, shader, processor, file,
5544 check_debug_option);
5545 }
5546
5547 static int si_compile_llvm(struct si_screen *sscreen,
5548 struct ac_shader_binary *binary,
5549 struct si_shader_config *conf,
5550 LLVMTargetMachineRef tm,
5551 LLVMModuleRef mod,
5552 struct pipe_debug_callback *debug,
5553 unsigned processor,
5554 const char *name)
5555 {
5556 int r = 0;
5557 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5558
5559 if (si_can_dump_shader(sscreen, processor)) {
5560 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5561
5562 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5563 fprintf(stderr, "%s LLVM IR:\n\n", name);
5564 ac_dump_module(mod);
5565 fprintf(stderr, "\n");
5566 }
5567 }
5568
5569 if (sscreen->record_llvm_ir) {
5570 char *ir = LLVMPrintModuleToString(mod);
5571 binary->llvm_ir_string = strdup(ir);
5572 LLVMDisposeMessage(ir);
5573 }
5574
5575 if (!si_replace_shader(count, binary)) {
5576 r = si_llvm_compile(mod, binary, tm, debug);
5577 if (r)
5578 return r;
5579 }
5580
5581 si_shader_binary_read_config(binary, conf, 0);
5582
5583 /* Enable 64-bit and 16-bit denormals, because there is no performance
5584 * cost.
5585 *
5586 * If denormals are enabled, all floating-point output modifiers are
5587 * ignored.
5588 *
5589 * Don't enable denormals for 32-bit floats, because:
5590 * - Floating-point output modifiers would be ignored by the hw.
5591 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5592 * have to stop using those.
5593 * - SI & CI would be very slow.
5594 */
5595 conf->float_mode |= V_00B028_FP_64_DENORMS;
5596
5597 FREE(binary->config);
5598 FREE(binary->global_symbol_offsets);
5599 binary->config = NULL;
5600 binary->global_symbol_offsets = NULL;
5601
5602 /* Some shaders can't have rodata because their binaries can be
5603 * concatenated.
5604 */
5605 if (binary->rodata_size &&
5606 (processor == PIPE_SHADER_VERTEX ||
5607 processor == PIPE_SHADER_TESS_CTRL ||
5608 processor == PIPE_SHADER_TESS_EVAL ||
5609 processor == PIPE_SHADER_FRAGMENT)) {
5610 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5611 return -EINVAL;
5612 }
5613
5614 return r;
5615 }
5616
5617 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5618 {
5619 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5620 LLVMBuildRetVoid(ctx->ac.builder);
5621 else
5622 LLVMBuildRet(ctx->ac.builder, ret);
5623 }
5624
5625 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5626 struct si_shader *
5627 si_generate_gs_copy_shader(struct si_screen *sscreen,
5628 LLVMTargetMachineRef tm,
5629 struct si_shader_selector *gs_selector,
5630 struct pipe_debug_callback *debug)
5631 {
5632 struct si_shader_context ctx;
5633 struct si_shader *shader;
5634 LLVMBuilderRef builder;
5635 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
5636 struct lp_build_context *uint = &bld_base->uint_bld;
5637 struct si_shader_output_values *outputs;
5638 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5639 int i, r;
5640
5641 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5642
5643 if (!outputs)
5644 return NULL;
5645
5646 shader = CALLOC_STRUCT(si_shader);
5647 if (!shader) {
5648 FREE(outputs);
5649 return NULL;
5650 }
5651
5652 /* We can leave the fence as permanently signaled because the GS copy
5653 * shader only becomes visible globally after it has been compiled. */
5654 util_queue_fence_init(&shader->ready);
5655
5656 shader->selector = gs_selector;
5657 shader->is_gs_copy_shader = true;
5658
5659 si_init_shader_ctx(&ctx, sscreen, tm);
5660 ctx.shader = shader;
5661 ctx.type = PIPE_SHADER_VERTEX;
5662
5663 builder = ctx.ac.builder;
5664
5665 create_function(&ctx);
5666 preload_ring_buffers(&ctx);
5667
5668 LLVMValueRef voffset =
5669 lp_build_mul_imm(uint, ctx.abi.vertex_id, 4);
5670
5671 /* Fetch the vertex stream ID.*/
5672 LLVMValueRef stream_id;
5673
5674 if (gs_selector->so.num_outputs)
5675 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5676 else
5677 stream_id = ctx.i32_0;
5678
5679 /* Fill in output information. */
5680 for (i = 0; i < gsinfo->num_outputs; ++i) {
5681 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5682 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5683
5684 for (int chan = 0; chan < 4; chan++) {
5685 outputs[i].vertex_stream[chan] =
5686 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5687 }
5688 }
5689
5690 LLVMBasicBlockRef end_bb;
5691 LLVMValueRef switch_inst;
5692
5693 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5694 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5695
5696 for (int stream = 0; stream < 4; stream++) {
5697 LLVMBasicBlockRef bb;
5698 unsigned offset;
5699
5700 if (!gsinfo->num_stream_output_components[stream])
5701 continue;
5702
5703 if (stream > 0 && !gs_selector->so.num_outputs)
5704 continue;
5705
5706 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5707 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5708 LLVMPositionBuilderAtEnd(builder, bb);
5709
5710 /* Fetch vertex data from GSVS ring */
5711 offset = 0;
5712 for (i = 0; i < gsinfo->num_outputs; ++i) {
5713 for (unsigned chan = 0; chan < 4; chan++) {
5714 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5715 outputs[i].vertex_stream[chan] != stream) {
5716 outputs[i].values[chan] = ctx.bld_base.base.undef;
5717 continue;
5718 }
5719
5720 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5721 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5722 offset++;
5723
5724 outputs[i].values[chan] =
5725 ac_build_buffer_load(&ctx.ac,
5726 ctx.gsvs_ring[0], 1,
5727 ctx.i32_0, voffset,
5728 soffset, 0, 1, 1,
5729 true, false);
5730 }
5731 }
5732
5733 /* Streamout and exports. */
5734 if (gs_selector->so.num_outputs) {
5735 si_llvm_emit_streamout(&ctx, outputs,
5736 gsinfo->num_outputs,
5737 stream);
5738 }
5739
5740 if (stream == 0)
5741 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5742
5743 LLVMBuildBr(builder, end_bb);
5744 }
5745
5746 LLVMPositionBuilderAtEnd(builder, end_bb);
5747
5748 LLVMBuildRetVoid(ctx.ac.builder);
5749
5750 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5751 si_llvm_optimize_module(&ctx);
5752
5753 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5754 &ctx.shader->config, ctx.tm,
5755 ctx.gallivm.module,
5756 debug, PIPE_SHADER_GEOMETRY,
5757 "GS Copy Shader");
5758 if (!r) {
5759 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5760 fprintf(stderr, "GS Copy Shader:\n");
5761 si_shader_dump(sscreen, ctx.shader, debug,
5762 PIPE_SHADER_GEOMETRY, stderr, true);
5763 r = si_shader_binary_upload(sscreen, ctx.shader);
5764 }
5765
5766 si_llvm_dispose(&ctx);
5767
5768 FREE(outputs);
5769
5770 if (r != 0) {
5771 FREE(shader);
5772 shader = NULL;
5773 }
5774 return shader;
5775 }
5776
5777 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5778 const struct si_vs_prolog_bits *prolog,
5779 const char *prefix, FILE *f)
5780 {
5781 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5782 prefix, prolog->instance_divisor_is_one);
5783 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5784 prefix, prolog->instance_divisor_is_fetched);
5785 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5786 prefix, prolog->ls_vgpr_fix);
5787
5788 fprintf(f, " mono.vs.fix_fetch = {");
5789 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5790 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5791 fprintf(f, "}\n");
5792 }
5793
5794 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5795 FILE *f)
5796 {
5797 const struct si_shader_key *key = &shader->key;
5798
5799 fprintf(f, "SHADER KEY\n");
5800
5801 switch (processor) {
5802 case PIPE_SHADER_VERTEX:
5803 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5804 "part.vs.prolog", f);
5805 fprintf(f, " as_es = %u\n", key->as_es);
5806 fprintf(f, " as_ls = %u\n", key->as_ls);
5807 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5808 key->mono.u.vs_export_prim_id);
5809 break;
5810
5811 case PIPE_SHADER_TESS_CTRL:
5812 if (shader->selector->screen->info.chip_class >= GFX9) {
5813 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5814 "part.tcs.ls_prolog", f);
5815 }
5816 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5817 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5818 break;
5819
5820 case PIPE_SHADER_TESS_EVAL:
5821 fprintf(f, " as_es = %u\n", key->as_es);
5822 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5823 key->mono.u.vs_export_prim_id);
5824 break;
5825
5826 case PIPE_SHADER_GEOMETRY:
5827 if (shader->is_gs_copy_shader)
5828 break;
5829
5830 if (shader->selector->screen->info.chip_class >= GFX9 &&
5831 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5832 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5833 "part.gs.vs_prolog", f);
5834 }
5835 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5836 break;
5837
5838 case PIPE_SHADER_COMPUTE:
5839 break;
5840
5841 case PIPE_SHADER_FRAGMENT:
5842 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5843 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5844 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5845 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5846 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5847 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5848 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5849 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5850 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5851 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5852 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5853 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5854 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5855 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5856 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5857 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5858 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5859 break;
5860
5861 default:
5862 assert(0);
5863 }
5864
5865 if ((processor == PIPE_SHADER_GEOMETRY ||
5866 processor == PIPE_SHADER_TESS_EVAL ||
5867 processor == PIPE_SHADER_VERTEX) &&
5868 !key->as_es && !key->as_ls) {
5869 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5870 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5871 }
5872 }
5873
5874 static void si_init_shader_ctx(struct si_shader_context *ctx,
5875 struct si_screen *sscreen,
5876 LLVMTargetMachineRef tm)
5877 {
5878 struct lp_build_tgsi_context *bld_base;
5879
5880 si_llvm_context_init(ctx, sscreen, tm);
5881
5882 bld_base = &ctx->bld_base;
5883 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5884
5885 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5886 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5887 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5888
5889 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5890
5891 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5892
5893 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5894 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5895 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5896 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5897
5898 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5899 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5900 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5901 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5902 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5903 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5904 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5905 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
5906 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5907
5908 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5909 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_tgsi_emit_primitive;
5910 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5911 }
5912
5913 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5914 {
5915 struct si_shader *shader = ctx->shader;
5916 struct tgsi_shader_info *info = &shader->selector->info;
5917
5918 if ((ctx->type != PIPE_SHADER_VERTEX &&
5919 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5920 shader->key.as_ls ||
5921 shader->key.as_es)
5922 return;
5923
5924 ac_optimize_vs_outputs(&ctx->ac,
5925 ctx->main_fn,
5926 shader->info.vs_output_param_offset,
5927 info->num_outputs,
5928 &shader->info.nr_param_exports);
5929 }
5930
5931 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
5932 {
5933 ctx->shader->config.private_mem_vgprs = 0;
5934
5935 /* Process all LLVM instructions. */
5936 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
5937 while (bb) {
5938 LLVMValueRef next = LLVMGetFirstInstruction(bb);
5939
5940 while (next) {
5941 LLVMValueRef inst = next;
5942 next = LLVMGetNextInstruction(next);
5943
5944 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
5945 continue;
5946
5947 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
5948 /* No idea why LLVM aligns allocas to 4 elements. */
5949 unsigned alignment = LLVMGetAlignment(inst);
5950 unsigned dw_size = align(ac_get_type_size(type) / 4, alignment);
5951 ctx->shader->config.private_mem_vgprs += dw_size;
5952 }
5953 bb = LLVMGetNextBasicBlock(bb);
5954 }
5955 }
5956
5957 static void si_init_exec_from_input(struct si_shader_context *ctx,
5958 unsigned param, unsigned bitoffset)
5959 {
5960 LLVMValueRef args[] = {
5961 LLVMGetParam(ctx->main_fn, param),
5962 LLVMConstInt(ctx->i32, bitoffset, 0),
5963 };
5964 lp_build_intrinsic(ctx->ac.builder,
5965 "llvm.amdgcn.init.exec.from.input",
5966 ctx->voidt, args, 2, LP_FUNC_ATTR_CONVERGENT);
5967 }
5968
5969 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
5970 const struct si_vs_prolog_bits *key)
5971 {
5972 /* VGPR initialization fixup for Vega10 and Raven is always done in the
5973 * VS prolog. */
5974 return sel->vs_needs_prolog || key->ls_vgpr_fix;
5975 }
5976
5977 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
5978 bool is_monolithic)
5979 {
5980 struct si_shader *shader = ctx->shader;
5981 struct si_shader_selector *sel = shader->selector;
5982 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5983
5984 // TODO clean all this up!
5985 switch (ctx->type) {
5986 case PIPE_SHADER_VERTEX:
5987 ctx->load_input = declare_input_vs;
5988 if (shader->key.as_ls)
5989 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
5990 else if (shader->key.as_es)
5991 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5992 else
5993 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5994 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5995 break;
5996 case PIPE_SHADER_TESS_CTRL:
5997 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5998 ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
5999 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6000 bld_base->emit_store = store_output_tcs;
6001 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
6002 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
6003 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6004 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6005 break;
6006 case PIPE_SHADER_TESS_EVAL:
6007 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6008 ctx->abi.load_tess_varyings = si_nir_load_input_tes;
6009 ctx->abi.load_tess_coord = si_load_tess_coord;
6010 ctx->abi.load_tess_level = si_load_tess_level;
6011 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6012 if (shader->key.as_es)
6013 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6014 else
6015 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6016 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6017 break;
6018 case PIPE_SHADER_GEOMETRY:
6019 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6020 ctx->abi.load_inputs = si_nir_load_input_gs;
6021 ctx->abi.emit_vertex = si_llvm_emit_vertex;
6022 ctx->abi.emit_primitive = si_llvm_emit_primitive;
6023 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
6024 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
6025 break;
6026 case PIPE_SHADER_FRAGMENT:
6027 ctx->load_input = declare_input_fs;
6028 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
6029 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6030 ctx->abi.lookup_interp_param = si_nir_lookup_interp_param;
6031 ctx->abi.load_sample_position = load_sample_position;
6032 ctx->abi.load_sample_mask_in = load_sample_mask_in;
6033 break;
6034 case PIPE_SHADER_COMPUTE:
6035 ctx->abi.load_local_group_size = get_block_size;
6036 break;
6037 default:
6038 assert(!"Unsupported shader type");
6039 return false;
6040 }
6041
6042 ctx->abi.load_ubo = load_ubo;
6043 ctx->abi.load_ssbo = load_ssbo;
6044
6045 create_function(ctx);
6046 preload_ring_buffers(ctx);
6047
6048 /* For GFX9 merged shaders:
6049 * - Set EXEC for the first shader. If the prolog is present, set
6050 * EXEC there instead.
6051 * - Add a barrier before the second shader.
6052 * - In the second shader, reset EXEC to ~0 and wrap the main part in
6053 * an if-statement. This is required for correctness in geometry
6054 * shaders, to ensure that empty GS waves do not send GS_EMIT and
6055 * GS_CUT messages.
6056 *
6057 * For monolithic merged shaders, the first shader is wrapped in an
6058 * if-block together with its prolog in si_build_wrapper_function.
6059 */
6060 if (ctx->screen->info.chip_class >= GFX9) {
6061 if (!is_monolithic &&
6062 sel->info.num_instructions > 1 && /* not empty shader */
6063 (shader->key.as_es || shader->key.as_ls) &&
6064 (ctx->type == PIPE_SHADER_TESS_EVAL ||
6065 (ctx->type == PIPE_SHADER_VERTEX &&
6066 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
6067 si_init_exec_from_input(ctx,
6068 ctx->param_merged_wave_info, 0);
6069 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6070 ctx->type == PIPE_SHADER_GEOMETRY) {
6071 if (!is_monolithic)
6072 ac_init_exec_full_mask(&ctx->ac);
6073
6074 /* The barrier must execute for all shaders in a
6075 * threadgroup.
6076 */
6077 si_llvm_emit_barrier(NULL, bld_base, NULL);
6078
6079 LLVMValueRef num_threads = unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
6080 LLVMValueRef ena =
6081 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
6082 ac_get_thread_id(&ctx->ac), num_threads, "");
6083 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
6084 }
6085 }
6086
6087 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
6088 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
6089 for (unsigned i = 0; i < 6; i++) {
6090 ctx->invoc0_tess_factors[i] =
6091 lp_build_alloca_undef(&ctx->gallivm, ctx->i32, "");
6092 }
6093 }
6094
6095 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6096 int i;
6097 for (i = 0; i < 4; i++) {
6098 ctx->gs_next_vertex[i] =
6099 lp_build_alloca(&ctx->gallivm,
6100 ctx->i32, "");
6101 }
6102 }
6103
6104 if (sel->force_correct_derivs_after_kill) {
6105 ctx->postponed_kill = lp_build_alloca_undef(&ctx->gallivm, ctx->i1, "");
6106 /* true = don't kill. */
6107 LLVMBuildStore(ctx->ac.builder, LLVMConstInt(ctx->i1, 1, 0),
6108 ctx->postponed_kill);
6109 }
6110
6111 if (sel->tokens) {
6112 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6113 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6114 return false;
6115 }
6116 } else {
6117 if (!si_nir_build_llvm(ctx, sel->nir)) {
6118 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
6119 return false;
6120 }
6121 }
6122
6123 si_llvm_build_ret(ctx, ctx->return_value);
6124 return true;
6125 }
6126
6127 /**
6128 * Compute the VS prolog key, which contains all the information needed to
6129 * build the VS prolog function, and set shader->info bits where needed.
6130 *
6131 * \param info Shader info of the vertex shader.
6132 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6133 * \param prolog_key Key of the VS prolog
6134 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6135 * \param key Output shader part key.
6136 */
6137 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
6138 unsigned num_input_sgprs,
6139 const struct si_vs_prolog_bits *prolog_key,
6140 struct si_shader *shader_out,
6141 union si_shader_part_key *key)
6142 {
6143 memset(key, 0, sizeof(*key));
6144 key->vs_prolog.states = *prolog_key;
6145 key->vs_prolog.num_input_sgprs = num_input_sgprs;
6146 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6147 key->vs_prolog.as_ls = shader_out->key.as_ls;
6148 key->vs_prolog.as_es = shader_out->key.as_es;
6149
6150 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
6151 key->vs_prolog.as_ls = 1;
6152 key->vs_prolog.num_merged_next_stage_vgprs = 2;
6153 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
6154 key->vs_prolog.as_es = 1;
6155 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6156 }
6157
6158 /* Enable loading the InstanceID VGPR. */
6159 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
6160
6161 if ((key->vs_prolog.states.instance_divisor_is_one |
6162 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
6163 shader_out->info.uses_instanceid = true;
6164 }
6165
6166 /**
6167 * Compute the PS prolog key, which contains all the information needed to
6168 * build the PS prolog function, and set related bits in shader->config.
6169 */
6170 static void si_get_ps_prolog_key(struct si_shader *shader,
6171 union si_shader_part_key *key,
6172 bool separate_prolog)
6173 {
6174 struct tgsi_shader_info *info = &shader->selector->info;
6175
6176 memset(key, 0, sizeof(*key));
6177 key->ps_prolog.states = shader->key.part.ps.prolog;
6178 key->ps_prolog.colors_read = info->colors_read;
6179 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6180 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6181 key->ps_prolog.wqm = info->uses_derivatives &&
6182 (key->ps_prolog.colors_read ||
6183 key->ps_prolog.states.force_persp_sample_interp ||
6184 key->ps_prolog.states.force_linear_sample_interp ||
6185 key->ps_prolog.states.force_persp_center_interp ||
6186 key->ps_prolog.states.force_linear_center_interp ||
6187 key->ps_prolog.states.bc_optimize_for_persp ||
6188 key->ps_prolog.states.bc_optimize_for_linear);
6189 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
6190
6191 if (info->colors_read) {
6192 unsigned *color = shader->selector->color_attr_index;
6193
6194 if (shader->key.part.ps.prolog.color_two_side) {
6195 /* BCOLORs are stored after the last input. */
6196 key->ps_prolog.num_interp_inputs = info->num_inputs;
6197 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6198 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6199 }
6200
6201 for (unsigned i = 0; i < 2; i++) {
6202 unsigned interp = info->input_interpolate[color[i]];
6203 unsigned location = info->input_interpolate_loc[color[i]];
6204
6205 if (!(info->colors_read & (0xf << i*4)))
6206 continue;
6207
6208 key->ps_prolog.color_attr_index[i] = color[i];
6209
6210 if (shader->key.part.ps.prolog.flatshade_colors &&
6211 interp == TGSI_INTERPOLATE_COLOR)
6212 interp = TGSI_INTERPOLATE_CONSTANT;
6213
6214 switch (interp) {
6215 case TGSI_INTERPOLATE_CONSTANT:
6216 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6217 break;
6218 case TGSI_INTERPOLATE_PERSPECTIVE:
6219 case TGSI_INTERPOLATE_COLOR:
6220 /* Force the interpolation location for colors here. */
6221 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6222 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6223 if (shader->key.part.ps.prolog.force_persp_center_interp)
6224 location = TGSI_INTERPOLATE_LOC_CENTER;
6225
6226 switch (location) {
6227 case TGSI_INTERPOLATE_LOC_SAMPLE:
6228 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6229 shader->config.spi_ps_input_ena |=
6230 S_0286CC_PERSP_SAMPLE_ENA(1);
6231 break;
6232 case TGSI_INTERPOLATE_LOC_CENTER:
6233 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6234 shader->config.spi_ps_input_ena |=
6235 S_0286CC_PERSP_CENTER_ENA(1);
6236 break;
6237 case TGSI_INTERPOLATE_LOC_CENTROID:
6238 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6239 shader->config.spi_ps_input_ena |=
6240 S_0286CC_PERSP_CENTROID_ENA(1);
6241 break;
6242 default:
6243 assert(0);
6244 }
6245 break;
6246 case TGSI_INTERPOLATE_LINEAR:
6247 /* Force the interpolation location for colors here. */
6248 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6249 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6250 if (shader->key.part.ps.prolog.force_linear_center_interp)
6251 location = TGSI_INTERPOLATE_LOC_CENTER;
6252
6253 /* The VGPR assignment for non-monolithic shaders
6254 * works because InitialPSInputAddr is set on the
6255 * main shader and PERSP_PULL_MODEL is never used.
6256 */
6257 switch (location) {
6258 case TGSI_INTERPOLATE_LOC_SAMPLE:
6259 key->ps_prolog.color_interp_vgpr_index[i] =
6260 separate_prolog ? 6 : 9;
6261 shader->config.spi_ps_input_ena |=
6262 S_0286CC_LINEAR_SAMPLE_ENA(1);
6263 break;
6264 case TGSI_INTERPOLATE_LOC_CENTER:
6265 key->ps_prolog.color_interp_vgpr_index[i] =
6266 separate_prolog ? 8 : 11;
6267 shader->config.spi_ps_input_ena |=
6268 S_0286CC_LINEAR_CENTER_ENA(1);
6269 break;
6270 case TGSI_INTERPOLATE_LOC_CENTROID:
6271 key->ps_prolog.color_interp_vgpr_index[i] =
6272 separate_prolog ? 10 : 13;
6273 shader->config.spi_ps_input_ena |=
6274 S_0286CC_LINEAR_CENTROID_ENA(1);
6275 break;
6276 default:
6277 assert(0);
6278 }
6279 break;
6280 default:
6281 assert(0);
6282 }
6283 }
6284 }
6285 }
6286
6287 /**
6288 * Check whether a PS prolog is required based on the key.
6289 */
6290 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6291 {
6292 return key->ps_prolog.colors_read ||
6293 key->ps_prolog.states.force_persp_sample_interp ||
6294 key->ps_prolog.states.force_linear_sample_interp ||
6295 key->ps_prolog.states.force_persp_center_interp ||
6296 key->ps_prolog.states.force_linear_center_interp ||
6297 key->ps_prolog.states.bc_optimize_for_persp ||
6298 key->ps_prolog.states.bc_optimize_for_linear ||
6299 key->ps_prolog.states.poly_stipple ||
6300 key->ps_prolog.states.samplemask_log_ps_iter;
6301 }
6302
6303 /**
6304 * Compute the PS epilog key, which contains all the information needed to
6305 * build the PS epilog function.
6306 */
6307 static void si_get_ps_epilog_key(struct si_shader *shader,
6308 union si_shader_part_key *key)
6309 {
6310 struct tgsi_shader_info *info = &shader->selector->info;
6311 memset(key, 0, sizeof(*key));
6312 key->ps_epilog.colors_written = info->colors_written;
6313 key->ps_epilog.writes_z = info->writes_z;
6314 key->ps_epilog.writes_stencil = info->writes_stencil;
6315 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6316 key->ps_epilog.states = shader->key.part.ps.epilog;
6317 }
6318
6319 /**
6320 * Build the GS prolog function. Rotate the input vertices for triangle strips
6321 * with adjacency.
6322 */
6323 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6324 union si_shader_part_key *key)
6325 {
6326 unsigned num_sgprs, num_vgprs;
6327 struct si_function_info fninfo;
6328 LLVMBuilderRef builder = ctx->ac.builder;
6329 LLVMTypeRef returns[48];
6330 LLVMValueRef func, ret;
6331
6332 si_init_function_info(&fninfo);
6333
6334 if (ctx->screen->info.chip_class >= GFX9) {
6335 num_sgprs = 8 + GFX9_GS_NUM_USER_SGPR;
6336 num_vgprs = 5; /* ES inputs are not needed by GS */
6337 } else {
6338 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6339 num_vgprs = 8;
6340 }
6341
6342 for (unsigned i = 0; i < num_sgprs; ++i) {
6343 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6344 returns[i] = ctx->i32;
6345 }
6346
6347 for (unsigned i = 0; i < num_vgprs; ++i) {
6348 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6349 returns[num_sgprs + i] = ctx->f32;
6350 }
6351
6352 /* Create the function. */
6353 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6354 &fninfo, 0);
6355 func = ctx->main_fn;
6356
6357 /* Set the full EXEC mask for the prolog, because we are only fiddling
6358 * with registers here. The main shader part will set the correct EXEC
6359 * mask.
6360 */
6361 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6362 ac_init_exec_full_mask(&ctx->ac);
6363
6364 /* Copy inputs to outputs. This should be no-op, as the registers match,
6365 * but it will prevent the compiler from overwriting them unintentionally.
6366 */
6367 ret = ctx->return_value;
6368 for (unsigned i = 0; i < num_sgprs; i++) {
6369 LLVMValueRef p = LLVMGetParam(func, i);
6370 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6371 }
6372 for (unsigned i = 0; i < num_vgprs; i++) {
6373 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6374 p = ac_to_float(&ctx->ac, p);
6375 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6376 }
6377
6378 if (key->gs_prolog.states.tri_strip_adj_fix) {
6379 /* Remap the input vertices for every other primitive. */
6380 const unsigned gfx6_vtx_params[6] = {
6381 num_sgprs,
6382 num_sgprs + 1,
6383 num_sgprs + 3,
6384 num_sgprs + 4,
6385 num_sgprs + 5,
6386 num_sgprs + 6
6387 };
6388 const unsigned gfx9_vtx_params[3] = {
6389 num_sgprs,
6390 num_sgprs + 1,
6391 num_sgprs + 4,
6392 };
6393 LLVMValueRef vtx_in[6], vtx_out[6];
6394 LLVMValueRef prim_id, rotate;
6395
6396 if (ctx->screen->info.chip_class >= GFX9) {
6397 for (unsigned i = 0; i < 3; i++) {
6398 vtx_in[i*2] = unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6399 vtx_in[i*2+1] = unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6400 }
6401 } else {
6402 for (unsigned i = 0; i < 6; i++)
6403 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6404 }
6405
6406 prim_id = LLVMGetParam(func, num_sgprs + 2);
6407 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6408
6409 for (unsigned i = 0; i < 6; ++i) {
6410 LLVMValueRef base, rotated;
6411 base = vtx_in[i];
6412 rotated = vtx_in[(i + 4) % 6];
6413 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6414 }
6415
6416 if (ctx->screen->info.chip_class >= GFX9) {
6417 for (unsigned i = 0; i < 3; i++) {
6418 LLVMValueRef hi, out;
6419
6420 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6421 LLVMConstInt(ctx->i32, 16, 0), "");
6422 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6423 out = ac_to_float(&ctx->ac, out);
6424 ret = LLVMBuildInsertValue(builder, ret, out,
6425 gfx9_vtx_params[i], "");
6426 }
6427 } else {
6428 for (unsigned i = 0; i < 6; i++) {
6429 LLVMValueRef out;
6430
6431 out = ac_to_float(&ctx->ac, vtx_out[i]);
6432 ret = LLVMBuildInsertValue(builder, ret, out,
6433 gfx6_vtx_params[i], "");
6434 }
6435 }
6436 }
6437
6438 LLVMBuildRet(builder, ret);
6439 }
6440
6441 /**
6442 * Given a list of shader part functions, build a wrapper function that
6443 * runs them in sequence to form a monolithic shader.
6444 */
6445 static void si_build_wrapper_function(struct si_shader_context *ctx,
6446 LLVMValueRef *parts,
6447 unsigned num_parts,
6448 unsigned main_part,
6449 unsigned next_shader_first_part)
6450 {
6451 LLVMBuilderRef builder = ctx->ac.builder;
6452 /* PS epilog has one arg per color component; gfx9 merged shader
6453 * prologs need to forward 32 user SGPRs.
6454 */
6455 struct si_function_info fninfo;
6456 LLVMValueRef initial[64], out[64];
6457 LLVMTypeRef function_type;
6458 unsigned num_first_params;
6459 unsigned num_out, initial_num_out;
6460 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6461 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6462 unsigned num_sgprs, num_vgprs;
6463 unsigned gprs;
6464 struct lp_build_if_state if_state;
6465
6466 si_init_function_info(&fninfo);
6467
6468 for (unsigned i = 0; i < num_parts; ++i) {
6469 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6470 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6471 }
6472
6473 /* The parameters of the wrapper function correspond to those of the
6474 * first part in terms of SGPRs and VGPRs, but we use the types of the
6475 * main part to get the right types. This is relevant for the
6476 * dereferenceable attribute on descriptor table pointers.
6477 */
6478 num_sgprs = 0;
6479 num_vgprs = 0;
6480
6481 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6482 num_first_params = LLVMCountParamTypes(function_type);
6483
6484 for (unsigned i = 0; i < num_first_params; ++i) {
6485 LLVMValueRef param = LLVMGetParam(parts[0], i);
6486
6487 if (ac_is_sgpr_param(param)) {
6488 assert(num_vgprs == 0);
6489 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6490 } else {
6491 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6492 }
6493 }
6494
6495 gprs = 0;
6496 while (gprs < num_sgprs + num_vgprs) {
6497 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6498 LLVMTypeRef type = LLVMTypeOf(param);
6499 unsigned size = ac_get_type_size(type) / 4;
6500
6501 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6502
6503 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6504 assert(gprs + size <= num_sgprs + num_vgprs &&
6505 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6506
6507 gprs += size;
6508 }
6509
6510 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6511 si_get_max_workgroup_size(ctx->shader));
6512
6513 if (is_merged_shader(ctx->shader))
6514 ac_init_exec_full_mask(&ctx->ac);
6515
6516 /* Record the arguments of the function as if they were an output of
6517 * a previous part.
6518 */
6519 num_out = 0;
6520 num_out_sgpr = 0;
6521
6522 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6523 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6524 LLVMTypeRef param_type = LLVMTypeOf(param);
6525 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6526 unsigned size = ac_get_type_size(param_type) / 4;
6527
6528 if (size == 1) {
6529 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6530 param = LLVMBuildPtrToInt(builder, param, ctx->i32, "");
6531 param_type = ctx->i32;
6532 }
6533
6534 if (param_type != out_type)
6535 param = LLVMBuildBitCast(builder, param, out_type, "");
6536 out[num_out++] = param;
6537 } else {
6538 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6539
6540 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6541 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6542 param_type = ctx->i64;
6543 }
6544
6545 if (param_type != vector_type)
6546 param = LLVMBuildBitCast(builder, param, vector_type, "");
6547
6548 for (unsigned j = 0; j < size; ++j)
6549 out[num_out++] = LLVMBuildExtractElement(
6550 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6551 }
6552
6553 if (i < fninfo.num_sgpr_params)
6554 num_out_sgpr = num_out;
6555 }
6556
6557 memcpy(initial, out, sizeof(out));
6558 initial_num_out = num_out;
6559 initial_num_out_sgpr = num_out_sgpr;
6560
6561 /* Now chain the parts. */
6562 for (unsigned part = 0; part < num_parts; ++part) {
6563 LLVMValueRef in[48];
6564 LLVMValueRef ret;
6565 LLVMTypeRef ret_type;
6566 unsigned out_idx = 0;
6567 unsigned num_params = LLVMCountParams(parts[part]);
6568
6569 /* Merged shaders are executed conditionally depending
6570 * on the number of enabled threads passed in the input SGPRs. */
6571 if (is_merged_shader(ctx->shader) && part == 0) {
6572 LLVMValueRef ena, count = initial[3];
6573
6574 count = LLVMBuildAnd(builder, count,
6575 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6576 ena = LLVMBuildICmp(builder, LLVMIntULT,
6577 ac_get_thread_id(&ctx->ac), count, "");
6578 lp_build_if(&if_state, &ctx->gallivm, ena);
6579 }
6580
6581 /* Derive arguments for the next part from outputs of the
6582 * previous one.
6583 */
6584 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6585 LLVMValueRef param;
6586 LLVMTypeRef param_type;
6587 bool is_sgpr;
6588 unsigned param_size;
6589 LLVMValueRef arg = NULL;
6590
6591 param = LLVMGetParam(parts[part], param_idx);
6592 param_type = LLVMTypeOf(param);
6593 param_size = ac_get_type_size(param_type) / 4;
6594 is_sgpr = ac_is_sgpr_param(param);
6595
6596 if (is_sgpr)
6597 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
6598
6599 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6600 assert(is_sgpr || out_idx >= num_out_sgpr);
6601
6602 if (param_size == 1)
6603 arg = out[out_idx];
6604 else
6605 arg = lp_build_gather_values(&ctx->gallivm, &out[out_idx], param_size);
6606
6607 if (LLVMTypeOf(arg) != param_type) {
6608 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6609 if (LLVMGetPointerAddressSpace(param_type) ==
6610 AC_CONST_32BIT_ADDR_SPACE) {
6611 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
6612 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6613 } else {
6614 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6615 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6616 }
6617 } else {
6618 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6619 }
6620 }
6621
6622 in[param_idx] = arg;
6623 out_idx += param_size;
6624 }
6625
6626 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6627
6628 if (is_merged_shader(ctx->shader) &&
6629 part + 1 == next_shader_first_part) {
6630 lp_build_endif(&if_state);
6631
6632 /* The second half of the merged shader should use
6633 * the inputs from the toplevel (wrapper) function,
6634 * not the return value from the last call.
6635 *
6636 * That's because the last call was executed condi-
6637 * tionally, so we can't consume it in the main
6638 * block.
6639 */
6640 memcpy(out, initial, sizeof(initial));
6641 num_out = initial_num_out;
6642 num_out_sgpr = initial_num_out_sgpr;
6643 continue;
6644 }
6645
6646 /* Extract the returned GPRs. */
6647 ret_type = LLVMTypeOf(ret);
6648 num_out = 0;
6649 num_out_sgpr = 0;
6650
6651 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6652 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6653
6654 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6655
6656 for (unsigned i = 0; i < ret_size; ++i) {
6657 LLVMValueRef val =
6658 LLVMBuildExtractValue(builder, ret, i, "");
6659
6660 assert(num_out < ARRAY_SIZE(out));
6661 out[num_out++] = val;
6662
6663 if (LLVMTypeOf(val) == ctx->i32) {
6664 assert(num_out_sgpr + 1 == num_out);
6665 num_out_sgpr = num_out;
6666 }
6667 }
6668 }
6669 }
6670
6671 LLVMBuildRetVoid(builder);
6672 }
6673
6674 int si_compile_tgsi_shader(struct si_screen *sscreen,
6675 LLVMTargetMachineRef tm,
6676 struct si_shader *shader,
6677 bool is_monolithic,
6678 struct pipe_debug_callback *debug)
6679 {
6680 struct si_shader_selector *sel = shader->selector;
6681 struct si_shader_context ctx;
6682 int r = -1;
6683
6684 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6685 * conversion fails. */
6686 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6687 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6688 if (sel->tokens)
6689 tgsi_dump(sel->tokens, 0);
6690 else
6691 nir_print_shader(sel->nir, stderr);
6692 si_dump_streamout(&sel->so);
6693 }
6694
6695 si_init_shader_ctx(&ctx, sscreen, tm);
6696 si_llvm_context_set_tgsi(&ctx, shader);
6697 ctx.separate_prolog = !is_monolithic;
6698
6699 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6700 sizeof(shader->info.vs_output_param_offset));
6701
6702 shader->info.uses_instanceid = sel->info.uses_instanceid;
6703
6704 if (!si_compile_tgsi_main(&ctx, is_monolithic)) {
6705 si_llvm_dispose(&ctx);
6706 return -1;
6707 }
6708
6709 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6710 LLVMValueRef parts[2];
6711 bool need_prolog = sel->vs_needs_prolog;
6712
6713 parts[1] = ctx.main_fn;
6714
6715 if (need_prolog) {
6716 union si_shader_part_key prolog_key;
6717 si_get_vs_prolog_key(&sel->info,
6718 shader->info.num_input_sgprs,
6719 &shader->key.part.vs.prolog,
6720 shader, &prolog_key);
6721 si_build_vs_prolog_function(&ctx, &prolog_key);
6722 parts[0] = ctx.main_fn;
6723 }
6724
6725 si_build_wrapper_function(&ctx, parts + !need_prolog,
6726 1 + need_prolog, need_prolog, 0);
6727 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6728 if (sscreen->info.chip_class >= GFX9) {
6729 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6730 LLVMValueRef parts[4];
6731 bool vs_needs_prolog =
6732 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6733
6734 /* TCS main part */
6735 parts[2] = ctx.main_fn;
6736
6737 /* TCS epilog */
6738 union si_shader_part_key tcs_epilog_key;
6739 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6740 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6741 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6742 parts[3] = ctx.main_fn;
6743
6744 /* VS prolog */
6745 if (vs_needs_prolog) {
6746 union si_shader_part_key vs_prolog_key;
6747 si_get_vs_prolog_key(&ls->info,
6748 shader->info.num_input_sgprs,
6749 &shader->key.part.tcs.ls_prolog,
6750 shader, &vs_prolog_key);
6751 vs_prolog_key.vs_prolog.is_monolithic = true;
6752 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6753 parts[0] = ctx.main_fn;
6754 }
6755
6756 /* VS as LS main part */
6757 struct si_shader shader_ls = {};
6758 shader_ls.selector = ls;
6759 shader_ls.key.as_ls = 1;
6760 shader_ls.key.mono = shader->key.mono;
6761 shader_ls.key.opt = shader->key.opt;
6762 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6763
6764 if (!si_compile_tgsi_main(&ctx, true)) {
6765 si_llvm_dispose(&ctx);
6766 return -1;
6767 }
6768 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6769 parts[1] = ctx.main_fn;
6770
6771 /* Reset the shader context. */
6772 ctx.shader = shader;
6773 ctx.type = PIPE_SHADER_TESS_CTRL;
6774
6775 si_build_wrapper_function(&ctx,
6776 parts + !vs_needs_prolog,
6777 4 - !vs_needs_prolog, 0,
6778 vs_needs_prolog ? 2 : 1);
6779 } else {
6780 LLVMValueRef parts[2];
6781 union si_shader_part_key epilog_key;
6782
6783 parts[0] = ctx.main_fn;
6784
6785 memset(&epilog_key, 0, sizeof(epilog_key));
6786 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6787 si_build_tcs_epilog_function(&ctx, &epilog_key);
6788 parts[1] = ctx.main_fn;
6789
6790 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6791 }
6792 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6793 if (ctx.screen->info.chip_class >= GFX9) {
6794 struct si_shader_selector *es = shader->key.part.gs.es;
6795 LLVMValueRef es_prolog = NULL;
6796 LLVMValueRef es_main = NULL;
6797 LLVMValueRef gs_prolog = NULL;
6798 LLVMValueRef gs_main = ctx.main_fn;
6799
6800 /* GS prolog */
6801 union si_shader_part_key gs_prolog_key;
6802 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6803 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6804 gs_prolog_key.gs_prolog.is_monolithic = true;
6805 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6806 gs_prolog = ctx.main_fn;
6807
6808 /* ES prolog */
6809 if (es->vs_needs_prolog) {
6810 union si_shader_part_key vs_prolog_key;
6811 si_get_vs_prolog_key(&es->info,
6812 shader->info.num_input_sgprs,
6813 &shader->key.part.gs.vs_prolog,
6814 shader, &vs_prolog_key);
6815 vs_prolog_key.vs_prolog.is_monolithic = true;
6816 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6817 es_prolog = ctx.main_fn;
6818 }
6819
6820 /* ES main part */
6821 struct si_shader shader_es = {};
6822 shader_es.selector = es;
6823 shader_es.key.as_es = 1;
6824 shader_es.key.mono = shader->key.mono;
6825 shader_es.key.opt = shader->key.opt;
6826 si_llvm_context_set_tgsi(&ctx, &shader_es);
6827
6828 if (!si_compile_tgsi_main(&ctx, true)) {
6829 si_llvm_dispose(&ctx);
6830 return -1;
6831 }
6832 shader->info.uses_instanceid |= es->info.uses_instanceid;
6833 es_main = ctx.main_fn;
6834
6835 /* Reset the shader context. */
6836 ctx.shader = shader;
6837 ctx.type = PIPE_SHADER_GEOMETRY;
6838
6839 /* Prepare the array of shader parts. */
6840 LLVMValueRef parts[4];
6841 unsigned num_parts = 0, main_part, next_first_part;
6842
6843 if (es_prolog)
6844 parts[num_parts++] = es_prolog;
6845
6846 parts[main_part = num_parts++] = es_main;
6847 parts[next_first_part = num_parts++] = gs_prolog;
6848 parts[num_parts++] = gs_main;
6849
6850 si_build_wrapper_function(&ctx, parts, num_parts,
6851 main_part, next_first_part);
6852 } else {
6853 LLVMValueRef parts[2];
6854 union si_shader_part_key prolog_key;
6855
6856 parts[1] = ctx.main_fn;
6857
6858 memset(&prolog_key, 0, sizeof(prolog_key));
6859 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6860 si_build_gs_prolog_function(&ctx, &prolog_key);
6861 parts[0] = ctx.main_fn;
6862
6863 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6864 }
6865 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6866 LLVMValueRef parts[3];
6867 union si_shader_part_key prolog_key;
6868 union si_shader_part_key epilog_key;
6869 bool need_prolog;
6870
6871 si_get_ps_prolog_key(shader, &prolog_key, false);
6872 need_prolog = si_need_ps_prolog(&prolog_key);
6873
6874 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6875
6876 if (need_prolog) {
6877 si_build_ps_prolog_function(&ctx, &prolog_key);
6878 parts[0] = ctx.main_fn;
6879 }
6880
6881 si_get_ps_epilog_key(shader, &epilog_key);
6882 si_build_ps_epilog_function(&ctx, &epilog_key);
6883 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6884
6885 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6886 need_prolog ? 1 : 0, 0);
6887 }
6888
6889 si_llvm_optimize_module(&ctx);
6890
6891 /* Post-optimization transformations and analysis. */
6892 si_optimize_vs_outputs(&ctx);
6893
6894 if ((debug && debug->debug_message) ||
6895 si_can_dump_shader(sscreen, ctx.type))
6896 si_count_scratch_private_memory(&ctx);
6897
6898 /* Compile to bytecode. */
6899 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6900 ctx.gallivm.module, debug, ctx.type, "TGSI shader");
6901 si_llvm_dispose(&ctx);
6902 if (r) {
6903 fprintf(stderr, "LLVM failed to compile shader\n");
6904 return r;
6905 }
6906
6907 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6908 * LLVM 3.9svn has this bug.
6909 */
6910 if (sel->type == PIPE_SHADER_COMPUTE) {
6911 unsigned wave_size = 64;
6912 unsigned max_vgprs = 256;
6913 unsigned max_sgprs = sscreen->info.chip_class >= VI ? 800 : 512;
6914 unsigned max_sgprs_per_wave = 128;
6915 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6916 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6917 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6918
6919 max_vgprs = max_vgprs / min_waves_per_simd;
6920 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6921
6922 if (shader->config.num_sgprs > max_sgprs ||
6923 shader->config.num_vgprs > max_vgprs) {
6924 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6925 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6926 shader->config.num_sgprs, shader->config.num_vgprs,
6927 max_sgprs, max_vgprs);
6928
6929 /* Just terminate the process, because dependent
6930 * shaders can hang due to bad input data, but use
6931 * the env var to allow shader-db to work.
6932 */
6933 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6934 abort();
6935 }
6936 }
6937
6938 /* Add the scratch offset to input SGPRs. */
6939 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(shader))
6940 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6941
6942 /* Calculate the number of fragment input VGPRs. */
6943 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6944 shader->info.num_input_vgprs = 0;
6945 shader->info.face_vgpr_index = -1;
6946 shader->info.ancillary_vgpr_index = -1;
6947
6948 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6949 shader->info.num_input_vgprs += 2;
6950 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6951 shader->info.num_input_vgprs += 2;
6952 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6953 shader->info.num_input_vgprs += 2;
6954 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6955 shader->info.num_input_vgprs += 3;
6956 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6957 shader->info.num_input_vgprs += 2;
6958 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6959 shader->info.num_input_vgprs += 2;
6960 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6961 shader->info.num_input_vgprs += 2;
6962 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6963 shader->info.num_input_vgprs += 1;
6964 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6965 shader->info.num_input_vgprs += 1;
6966 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6967 shader->info.num_input_vgprs += 1;
6968 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6969 shader->info.num_input_vgprs += 1;
6970 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6971 shader->info.num_input_vgprs += 1;
6972 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6973 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6974 shader->info.num_input_vgprs += 1;
6975 }
6976 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
6977 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
6978 shader->info.num_input_vgprs += 1;
6979 }
6980 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6981 shader->info.num_input_vgprs += 1;
6982 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6983 shader->info.num_input_vgprs += 1;
6984 }
6985
6986 si_calculate_max_simd_waves(shader);
6987 si_shader_dump_stats_for_shader_db(shader, debug);
6988 return 0;
6989 }
6990
6991 /**
6992 * Create, compile and return a shader part (prolog or epilog).
6993 *
6994 * \param sscreen screen
6995 * \param list list of shader parts of the same category
6996 * \param type shader type
6997 * \param key shader part key
6998 * \param prolog whether the part being requested is a prolog
6999 * \param tm LLVM target machine
7000 * \param debug debug callback
7001 * \param build the callback responsible for building the main function
7002 * \return non-NULL on success
7003 */
7004 static struct si_shader_part *
7005 si_get_shader_part(struct si_screen *sscreen,
7006 struct si_shader_part **list,
7007 enum pipe_shader_type type,
7008 bool prolog,
7009 union si_shader_part_key *key,
7010 LLVMTargetMachineRef tm,
7011 struct pipe_debug_callback *debug,
7012 void (*build)(struct si_shader_context *,
7013 union si_shader_part_key *),
7014 const char *name)
7015 {
7016 struct si_shader_part *result;
7017
7018 mtx_lock(&sscreen->shader_parts_mutex);
7019
7020 /* Find existing. */
7021 for (result = *list; result; result = result->next) {
7022 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7023 mtx_unlock(&sscreen->shader_parts_mutex);
7024 return result;
7025 }
7026 }
7027
7028 /* Compile a new one. */
7029 result = CALLOC_STRUCT(si_shader_part);
7030 result->key = *key;
7031
7032 struct si_shader shader = {};
7033 struct si_shader_context ctx;
7034
7035 si_init_shader_ctx(&ctx, sscreen, tm);
7036 ctx.shader = &shader;
7037 ctx.type = type;
7038
7039 switch (type) {
7040 case PIPE_SHADER_VERTEX:
7041 shader.key.as_ls = key->vs_prolog.as_ls;
7042 shader.key.as_es = key->vs_prolog.as_es;
7043 break;
7044 case PIPE_SHADER_TESS_CTRL:
7045 assert(!prolog);
7046 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7047 break;
7048 case PIPE_SHADER_GEOMETRY:
7049 assert(prolog);
7050 break;
7051 case PIPE_SHADER_FRAGMENT:
7052 if (prolog)
7053 shader.key.part.ps.prolog = key->ps_prolog.states;
7054 else
7055 shader.key.part.ps.epilog = key->ps_epilog.states;
7056 break;
7057 default:
7058 unreachable("bad shader part");
7059 }
7060
7061 build(&ctx, key);
7062
7063 /* Compile. */
7064 si_llvm_optimize_module(&ctx);
7065
7066 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7067 ctx.ac.module, debug, ctx.type, name)) {
7068 FREE(result);
7069 result = NULL;
7070 goto out;
7071 }
7072
7073 result->next = *list;
7074 *list = result;
7075
7076 out:
7077 si_llvm_dispose(&ctx);
7078 mtx_unlock(&sscreen->shader_parts_mutex);
7079 return result;
7080 }
7081
7082 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
7083 {
7084 LLVMValueRef ptr[2], list;
7085 bool is_merged_shader =
7086 ctx->screen->info.chip_class >= GFX9 &&
7087 (ctx->type == PIPE_SHADER_TESS_CTRL ||
7088 ctx->type == PIPE_SHADER_GEOMETRY ||
7089 ctx->shader->key.as_ls || ctx->shader->key.as_es);
7090
7091 if (HAVE_32BIT_POINTERS) {
7092 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7093 list = LLVMBuildIntToPtr(ctx->ac.builder, ptr[0],
7094 ac_array_in_const32_addr_space(ctx->v4i32), "");
7095 return list;
7096 }
7097
7098 /* Get the pointer to rw buffers. */
7099 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7100 ptr[1] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS + 1);
7101 list = lp_build_gather_values(&ctx->gallivm, ptr, 2);
7102 list = LLVMBuildBitCast(ctx->ac.builder, list, ctx->i64, "");
7103 list = LLVMBuildIntToPtr(ctx->ac.builder, list,
7104 ac_array_in_const_addr_space(ctx->v4i32), "");
7105 return list;
7106 }
7107
7108 /**
7109 * Build the vertex shader prolog function.
7110 *
7111 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7112 * All inputs are returned unmodified. The vertex load indices are
7113 * stored after them, which will be used by the API VS for fetching inputs.
7114 *
7115 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7116 * input_v0,
7117 * input_v1,
7118 * input_v2,
7119 * input_v3,
7120 * (VertexID + BaseVertex),
7121 * (InstanceID + StartInstance),
7122 * (InstanceID / 2 + StartInstance)
7123 */
7124 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7125 union si_shader_part_key *key)
7126 {
7127 struct si_function_info fninfo;
7128 LLVMTypeRef *returns;
7129 LLVMValueRef ret, func;
7130 int num_returns, i;
7131 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
7132 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
7133 LLVMValueRef input_vgprs[9];
7134 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
7135 num_input_vgprs;
7136 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
7137
7138 si_init_function_info(&fninfo);
7139
7140 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7141 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
7142 sizeof(LLVMTypeRef));
7143 num_returns = 0;
7144
7145 /* Declare input and output SGPRs. */
7146 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7147 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7148 returns[num_returns++] = ctx->i32;
7149 }
7150
7151 /* Preloaded VGPRs (outputs must be floats) */
7152 for (i = 0; i < num_input_vgprs; i++) {
7153 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
7154 returns[num_returns++] = ctx->f32;
7155 }
7156
7157 /* Vertex load indices. */
7158 for (i = 0; i <= key->vs_prolog.last_input; i++)
7159 returns[num_returns++] = ctx->f32;
7160
7161 /* Create the function. */
7162 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
7163 func = ctx->main_fn;
7164
7165 if (key->vs_prolog.num_merged_next_stage_vgprs) {
7166 if (!key->vs_prolog.is_monolithic)
7167 si_init_exec_from_input(ctx, 3, 0);
7168
7169 if (key->vs_prolog.as_ls &&
7170 ctx->screen->has_ls_vgpr_init_bug) {
7171 /* If there are no HS threads, SPI loads the LS VGPRs
7172 * starting at VGPR 0. Shift them back to where they
7173 * belong.
7174 */
7175 LLVMValueRef has_hs_threads =
7176 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
7177 unpack_param(ctx, 3, 8, 8),
7178 ctx->i32_0, "");
7179
7180 for (i = 4; i > 0; --i) {
7181 input_vgprs[i + 1] =
7182 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
7183 input_vgprs[i + 1],
7184 input_vgprs[i - 1], "");
7185 }
7186 }
7187 }
7188
7189 ctx->abi.vertex_id = input_vgprs[first_vs_vgpr];
7190 ctx->abi.instance_id = input_vgprs[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)];
7191
7192 /* Copy inputs to outputs. This should be no-op, as the registers match,
7193 * but it will prevent the compiler from overwriting them unintentionally.
7194 */
7195 ret = ctx->return_value;
7196 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7197 LLVMValueRef p = LLVMGetParam(func, i);
7198 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7199 }
7200 for (i = 0; i < num_input_vgprs; i++) {
7201 LLVMValueRef p = input_vgprs[i];
7202 p = ac_to_float(&ctx->ac, p);
7203 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
7204 key->vs_prolog.num_input_sgprs + i, "");
7205 }
7206
7207 /* Compute vertex load indices from instance divisors. */
7208 LLVMValueRef instance_divisor_constbuf = NULL;
7209
7210 if (key->vs_prolog.states.instance_divisor_is_fetched) {
7211 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7212 LLVMValueRef buf_index =
7213 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
7214 instance_divisor_constbuf =
7215 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
7216 }
7217
7218 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7219 bool divisor_is_one =
7220 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
7221 bool divisor_is_fetched =
7222 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
7223 LLVMValueRef index;
7224
7225 if (divisor_is_one || divisor_is_fetched) {
7226 LLVMValueRef divisor = ctx->i32_1;
7227
7228 if (divisor_is_fetched) {
7229 divisor = buffer_load_const(ctx, instance_divisor_constbuf,
7230 LLVMConstInt(ctx->i32, i * 4, 0));
7231 divisor = ac_to_integer(&ctx->ac, divisor);
7232 }
7233
7234 /* InstanceID / Divisor + StartInstance */
7235 index = get_instance_index_for_fetch(ctx,
7236 user_sgpr_base +
7237 SI_SGPR_START_INSTANCE,
7238 divisor);
7239 } else {
7240 /* VertexID + BaseVertex */
7241 index = LLVMBuildAdd(ctx->ac.builder,
7242 ctx->abi.vertex_id,
7243 LLVMGetParam(func, user_sgpr_base +
7244 SI_SGPR_BASE_VERTEX), "");
7245 }
7246
7247 index = ac_to_float(&ctx->ac, index);
7248 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7249 fninfo.num_params + i, "");
7250 }
7251
7252 si_llvm_build_ret(ctx, ret);
7253 }
7254
7255 static bool si_get_vs_prolog(struct si_screen *sscreen,
7256 LLVMTargetMachineRef tm,
7257 struct si_shader *shader,
7258 struct pipe_debug_callback *debug,
7259 struct si_shader *main_part,
7260 const struct si_vs_prolog_bits *key)
7261 {
7262 struct si_shader_selector *vs = main_part->selector;
7263
7264 if (!si_vs_needs_prolog(vs, key))
7265 return true;
7266
7267 /* Get the prolog. */
7268 union si_shader_part_key prolog_key;
7269 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7270 key, shader, &prolog_key);
7271
7272 shader->prolog =
7273 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7274 PIPE_SHADER_VERTEX, true, &prolog_key, tm,
7275 debug, si_build_vs_prolog_function,
7276 "Vertex Shader Prolog");
7277 return shader->prolog != NULL;
7278 }
7279
7280 /**
7281 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7282 */
7283 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7284 LLVMTargetMachineRef tm,
7285 struct si_shader *shader,
7286 struct pipe_debug_callback *debug)
7287 {
7288 return si_get_vs_prolog(sscreen, tm, shader, debug, shader,
7289 &shader->key.part.vs.prolog);
7290 }
7291
7292 /**
7293 * Compile the TCS epilog function. This writes tesselation factors to memory
7294 * based on the output primitive type of the tesselator (determined by TES).
7295 */
7296 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7297 union si_shader_part_key *key)
7298 {
7299 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7300 struct si_function_info fninfo;
7301 LLVMValueRef func;
7302
7303 si_init_function_info(&fninfo);
7304
7305 if (ctx->screen->info.chip_class >= GFX9) {
7306 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7307 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7308 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7309 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7310 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7311 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7312 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7313 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7314 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7315 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7316 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7317 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7318 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7319 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7320 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7321 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7322 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7323 if (!HAVE_32BIT_POINTERS)
7324 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7325 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7326 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7327 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7328 } else {
7329 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7330 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7331 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7332 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7333 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7334 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7335 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7336 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7337 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7338 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7339 }
7340
7341 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7342 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7343 unsigned tess_factors_idx =
7344 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7345 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7346 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7347
7348 for (unsigned i = 0; i < 6; i++)
7349 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7350
7351 /* Create the function. */
7352 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7353 ctx->screen->info.chip_class >= CIK ? 128 : 64);
7354 ac_declare_lds_as_pointer(&ctx->ac);
7355 func = ctx->main_fn;
7356
7357 LLVMValueRef invoc0_tess_factors[6];
7358 for (unsigned i = 0; i < 6; i++)
7359 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7360
7361 si_write_tess_factors(bld_base,
7362 LLVMGetParam(func, tess_factors_idx),
7363 LLVMGetParam(func, tess_factors_idx + 1),
7364 LLVMGetParam(func, tess_factors_idx + 2),
7365 invoc0_tess_factors, invoc0_tess_factors + 4);
7366
7367 LLVMBuildRetVoid(ctx->ac.builder);
7368 }
7369
7370 /**
7371 * Select and compile (or reuse) TCS parts (epilog).
7372 */
7373 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7374 LLVMTargetMachineRef tm,
7375 struct si_shader *shader,
7376 struct pipe_debug_callback *debug)
7377 {
7378 if (sscreen->info.chip_class >= GFX9) {
7379 struct si_shader *ls_main_part =
7380 shader->key.part.tcs.ls->main_shader_part_ls;
7381
7382 if (!si_get_vs_prolog(sscreen, tm, shader, debug, ls_main_part,
7383 &shader->key.part.tcs.ls_prolog))
7384 return false;
7385
7386 shader->previous_stage = ls_main_part;
7387 }
7388
7389 /* Get the epilog. */
7390 union si_shader_part_key epilog_key;
7391 memset(&epilog_key, 0, sizeof(epilog_key));
7392 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7393
7394 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7395 PIPE_SHADER_TESS_CTRL, false,
7396 &epilog_key, tm, debug,
7397 si_build_tcs_epilog_function,
7398 "Tessellation Control Shader Epilog");
7399 return shader->epilog != NULL;
7400 }
7401
7402 /**
7403 * Select and compile (or reuse) GS parts (prolog).
7404 */
7405 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7406 LLVMTargetMachineRef tm,
7407 struct si_shader *shader,
7408 struct pipe_debug_callback *debug)
7409 {
7410 if (sscreen->info.chip_class >= GFX9) {
7411 struct si_shader *es_main_part =
7412 shader->key.part.gs.es->main_shader_part_es;
7413
7414 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7415 !si_get_vs_prolog(sscreen, tm, shader, debug, es_main_part,
7416 &shader->key.part.gs.vs_prolog))
7417 return false;
7418
7419 shader->previous_stage = es_main_part;
7420 }
7421
7422 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7423 return true;
7424
7425 union si_shader_part_key prolog_key;
7426 memset(&prolog_key, 0, sizeof(prolog_key));
7427 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7428
7429 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7430 PIPE_SHADER_GEOMETRY, true,
7431 &prolog_key, tm, debug,
7432 si_build_gs_prolog_function,
7433 "Geometry Shader Prolog");
7434 return shader->prolog2 != NULL;
7435 }
7436
7437 /**
7438 * Build the pixel shader prolog function. This handles:
7439 * - two-side color selection and interpolation
7440 * - overriding interpolation parameters for the API PS
7441 * - polygon stippling
7442 *
7443 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7444 * overriden by other states. (e.g. per-sample interpolation)
7445 * Interpolated colors are stored after the preloaded VGPRs.
7446 */
7447 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7448 union si_shader_part_key *key)
7449 {
7450 struct si_function_info fninfo;
7451 LLVMValueRef ret, func;
7452 int num_returns, i, num_color_channels;
7453
7454 assert(si_need_ps_prolog(key));
7455
7456 si_init_function_info(&fninfo);
7457
7458 /* Declare inputs. */
7459 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7460 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7461
7462 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7463 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7464
7465 /* Declare outputs (same as inputs + add colors if needed) */
7466 num_returns = fninfo.num_params;
7467 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7468 for (i = 0; i < num_color_channels; i++)
7469 fninfo.types[num_returns++] = ctx->f32;
7470
7471 /* Create the function. */
7472 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7473 &fninfo, 0);
7474 func = ctx->main_fn;
7475
7476 /* Copy inputs to outputs. This should be no-op, as the registers match,
7477 * but it will prevent the compiler from overwriting them unintentionally.
7478 */
7479 ret = ctx->return_value;
7480 for (i = 0; i < fninfo.num_params; i++) {
7481 LLVMValueRef p = LLVMGetParam(func, i);
7482 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7483 }
7484
7485 /* Polygon stippling. */
7486 if (key->ps_prolog.states.poly_stipple) {
7487 /* POS_FIXED_PT is always last. */
7488 unsigned pos = key->ps_prolog.num_input_sgprs +
7489 key->ps_prolog.num_input_vgprs - 1;
7490 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7491
7492 si_llvm_emit_polygon_stipple(ctx, list, pos);
7493 }
7494
7495 if (key->ps_prolog.states.bc_optimize_for_persp ||
7496 key->ps_prolog.states.bc_optimize_for_linear) {
7497 unsigned i, base = key->ps_prolog.num_input_sgprs;
7498 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7499
7500 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7501 * The hw doesn't compute CENTROID if the whole wave only
7502 * contains fully-covered quads.
7503 *
7504 * PRIM_MASK is after user SGPRs.
7505 */
7506 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7507 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7508 LLVMConstInt(ctx->i32, 31, 0), "");
7509 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7510 ctx->i1, "");
7511
7512 if (key->ps_prolog.states.bc_optimize_for_persp) {
7513 /* Read PERSP_CENTER. */
7514 for (i = 0; i < 2; i++)
7515 center[i] = LLVMGetParam(func, base + 2 + i);
7516 /* Read PERSP_CENTROID. */
7517 for (i = 0; i < 2; i++)
7518 centroid[i] = LLVMGetParam(func, base + 4 + i);
7519 /* Select PERSP_CENTROID. */
7520 for (i = 0; i < 2; i++) {
7521 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7522 center[i], centroid[i], "");
7523 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7524 tmp, base + 4 + i, "");
7525 }
7526 }
7527 if (key->ps_prolog.states.bc_optimize_for_linear) {
7528 /* Read LINEAR_CENTER. */
7529 for (i = 0; i < 2; i++)
7530 center[i] = LLVMGetParam(func, base + 8 + i);
7531 /* Read LINEAR_CENTROID. */
7532 for (i = 0; i < 2; i++)
7533 centroid[i] = LLVMGetParam(func, base + 10 + i);
7534 /* Select LINEAR_CENTROID. */
7535 for (i = 0; i < 2; i++) {
7536 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7537 center[i], centroid[i], "");
7538 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7539 tmp, base + 10 + i, "");
7540 }
7541 }
7542 }
7543
7544 /* Force per-sample interpolation. */
7545 if (key->ps_prolog.states.force_persp_sample_interp) {
7546 unsigned i, base = key->ps_prolog.num_input_sgprs;
7547 LLVMValueRef persp_sample[2];
7548
7549 /* Read PERSP_SAMPLE. */
7550 for (i = 0; i < 2; i++)
7551 persp_sample[i] = LLVMGetParam(func, base + i);
7552 /* Overwrite PERSP_CENTER. */
7553 for (i = 0; i < 2; i++)
7554 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7555 persp_sample[i], base + 2 + i, "");
7556 /* Overwrite PERSP_CENTROID. */
7557 for (i = 0; i < 2; i++)
7558 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7559 persp_sample[i], base + 4 + i, "");
7560 }
7561 if (key->ps_prolog.states.force_linear_sample_interp) {
7562 unsigned i, base = key->ps_prolog.num_input_sgprs;
7563 LLVMValueRef linear_sample[2];
7564
7565 /* Read LINEAR_SAMPLE. */
7566 for (i = 0; i < 2; i++)
7567 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7568 /* Overwrite LINEAR_CENTER. */
7569 for (i = 0; i < 2; i++)
7570 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7571 linear_sample[i], base + 8 + i, "");
7572 /* Overwrite LINEAR_CENTROID. */
7573 for (i = 0; i < 2; i++)
7574 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7575 linear_sample[i], base + 10 + i, "");
7576 }
7577
7578 /* Force center interpolation. */
7579 if (key->ps_prolog.states.force_persp_center_interp) {
7580 unsigned i, base = key->ps_prolog.num_input_sgprs;
7581 LLVMValueRef persp_center[2];
7582
7583 /* Read PERSP_CENTER. */
7584 for (i = 0; i < 2; i++)
7585 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7586 /* Overwrite PERSP_SAMPLE. */
7587 for (i = 0; i < 2; i++)
7588 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7589 persp_center[i], base + i, "");
7590 /* Overwrite PERSP_CENTROID. */
7591 for (i = 0; i < 2; i++)
7592 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7593 persp_center[i], base + 4 + i, "");
7594 }
7595 if (key->ps_prolog.states.force_linear_center_interp) {
7596 unsigned i, base = key->ps_prolog.num_input_sgprs;
7597 LLVMValueRef linear_center[2];
7598
7599 /* Read LINEAR_CENTER. */
7600 for (i = 0; i < 2; i++)
7601 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7602 /* Overwrite LINEAR_SAMPLE. */
7603 for (i = 0; i < 2; i++)
7604 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7605 linear_center[i], base + 6 + i, "");
7606 /* Overwrite LINEAR_CENTROID. */
7607 for (i = 0; i < 2; i++)
7608 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7609 linear_center[i], base + 10 + i, "");
7610 }
7611
7612 /* Interpolate colors. */
7613 unsigned color_out_idx = 0;
7614 for (i = 0; i < 2; i++) {
7615 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7616 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7617 key->ps_prolog.face_vgpr_index;
7618 LLVMValueRef interp[2], color[4];
7619 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7620
7621 if (!writemask)
7622 continue;
7623
7624 /* If the interpolation qualifier is not CONSTANT (-1). */
7625 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7626 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7627 key->ps_prolog.color_interp_vgpr_index[i];
7628
7629 /* Get the (i,j) updated by bc_optimize handling. */
7630 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7631 interp_vgpr, "");
7632 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7633 interp_vgpr + 1, "");
7634 interp_ij = lp_build_gather_values(&ctx->gallivm, interp, 2);
7635 }
7636
7637 /* Use the absolute location of the input. */
7638 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7639
7640 if (key->ps_prolog.states.color_two_side) {
7641 face = LLVMGetParam(func, face_vgpr);
7642 face = ac_to_integer(&ctx->ac, face);
7643 }
7644
7645 interp_fs_input(ctx,
7646 key->ps_prolog.color_attr_index[i],
7647 TGSI_SEMANTIC_COLOR, i,
7648 key->ps_prolog.num_interp_inputs,
7649 key->ps_prolog.colors_read, interp_ij,
7650 prim_mask, face, color);
7651
7652 while (writemask) {
7653 unsigned chan = u_bit_scan(&writemask);
7654 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7655 fninfo.num_params + color_out_idx++, "");
7656 }
7657 }
7658
7659 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7660 * says:
7661 *
7662 * "When per-sample shading is active due to the use of a fragment
7663 * input qualified by sample or due to the use of the gl_SampleID
7664 * or gl_SamplePosition variables, only the bit for the current
7665 * sample is set in gl_SampleMaskIn. When state specifies multiple
7666 * fragment shader invocations for a given fragment, the sample
7667 * mask for any single fragment shader invocation may specify a
7668 * subset of the covered samples for the fragment. In this case,
7669 * the bit corresponding to each covered sample will be set in
7670 * exactly one fragment shader invocation."
7671 *
7672 * The samplemask loaded by hardware is always the coverage of the
7673 * entire pixel/fragment, so mask bits out based on the sample ID.
7674 */
7675 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7676 /* The bit pattern matches that used by fixed function fragment
7677 * processing. */
7678 static const uint16_t ps_iter_masks[] = {
7679 0xffff, /* not used */
7680 0x5555,
7681 0x1111,
7682 0x0101,
7683 0x0001,
7684 };
7685 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7686
7687 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7688 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7689 key->ps_prolog.ancillary_vgpr_index;
7690 LLVMValueRef sampleid = unpack_param(ctx, ancillary_vgpr, 8, 4);
7691 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7692
7693 samplemask = ac_to_integer(&ctx->ac, samplemask);
7694 samplemask = LLVMBuildAnd(
7695 ctx->ac.builder,
7696 samplemask,
7697 LLVMBuildShl(ctx->ac.builder,
7698 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7699 sampleid, ""),
7700 "");
7701 samplemask = ac_to_float(&ctx->ac, samplemask);
7702
7703 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7704 ancillary_vgpr + 1, "");
7705 }
7706
7707 /* Tell LLVM to insert WQM instruction sequence when needed. */
7708 if (key->ps_prolog.wqm) {
7709 LLVMAddTargetDependentFunctionAttr(func,
7710 "amdgpu-ps-wqm-outputs", "");
7711 }
7712
7713 si_llvm_build_ret(ctx, ret);
7714 }
7715
7716 /**
7717 * Build the pixel shader epilog function. This handles everything that must be
7718 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7719 */
7720 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7721 union si_shader_part_key *key)
7722 {
7723 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7724 struct si_function_info fninfo;
7725 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7726 int i;
7727 struct si_ps_exports exp = {};
7728
7729 si_init_function_info(&fninfo);
7730
7731 /* Declare input SGPRs. */
7732 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7733 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7734 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7735 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7736 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7737
7738 /* Declare input VGPRs. */
7739 unsigned required_num_params =
7740 fninfo.num_sgpr_params +
7741 util_bitcount(key->ps_epilog.colors_written) * 4 +
7742 key->ps_epilog.writes_z +
7743 key->ps_epilog.writes_stencil +
7744 key->ps_epilog.writes_samplemask;
7745
7746 required_num_params = MAX2(required_num_params,
7747 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7748
7749 while (fninfo.num_params < required_num_params)
7750 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7751
7752 /* Create the function. */
7753 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7754 /* Disable elimination of unused inputs. */
7755 si_llvm_add_attribute(ctx->main_fn,
7756 "InitialPSInputAddr", 0xffffff);
7757
7758 /* Process colors. */
7759 unsigned vgpr = fninfo.num_sgpr_params;
7760 unsigned colors_written = key->ps_epilog.colors_written;
7761 int last_color_export = -1;
7762
7763 /* Find the last color export. */
7764 if (!key->ps_epilog.writes_z &&
7765 !key->ps_epilog.writes_stencil &&
7766 !key->ps_epilog.writes_samplemask) {
7767 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7768
7769 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7770 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7771 /* Just set this if any of the colorbuffers are enabled. */
7772 if (spi_format &
7773 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7774 last_color_export = 0;
7775 } else {
7776 for (i = 0; i < 8; i++)
7777 if (colors_written & (1 << i) &&
7778 (spi_format >> (i * 4)) & 0xf)
7779 last_color_export = i;
7780 }
7781 }
7782
7783 while (colors_written) {
7784 LLVMValueRef color[4];
7785 int mrt = u_bit_scan(&colors_written);
7786
7787 for (i = 0; i < 4; i++)
7788 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7789
7790 si_export_mrt_color(bld_base, color, mrt,
7791 fninfo.num_params - 1,
7792 mrt == last_color_export, &exp);
7793 }
7794
7795 /* Process depth, stencil, samplemask. */
7796 if (key->ps_epilog.writes_z)
7797 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7798 if (key->ps_epilog.writes_stencil)
7799 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7800 if (key->ps_epilog.writes_samplemask)
7801 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7802
7803 if (depth || stencil || samplemask)
7804 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7805 else if (last_color_export == -1)
7806 ac_build_export_null(&ctx->ac);
7807
7808 if (exp.num)
7809 si_emit_ps_exports(ctx, &exp);
7810
7811 /* Compile. */
7812 LLVMBuildRetVoid(ctx->ac.builder);
7813 }
7814
7815 /**
7816 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7817 */
7818 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7819 LLVMTargetMachineRef tm,
7820 struct si_shader *shader,
7821 struct pipe_debug_callback *debug)
7822 {
7823 union si_shader_part_key prolog_key;
7824 union si_shader_part_key epilog_key;
7825
7826 /* Get the prolog. */
7827 si_get_ps_prolog_key(shader, &prolog_key, true);
7828
7829 /* The prolog is a no-op if these aren't set. */
7830 if (si_need_ps_prolog(&prolog_key)) {
7831 shader->prolog =
7832 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7833 PIPE_SHADER_FRAGMENT, true,
7834 &prolog_key, tm, debug,
7835 si_build_ps_prolog_function,
7836 "Fragment Shader Prolog");
7837 if (!shader->prolog)
7838 return false;
7839 }
7840
7841 /* Get the epilog. */
7842 si_get_ps_epilog_key(shader, &epilog_key);
7843
7844 shader->epilog =
7845 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7846 PIPE_SHADER_FRAGMENT, false,
7847 &epilog_key, tm, debug,
7848 si_build_ps_epilog_function,
7849 "Fragment Shader Epilog");
7850 if (!shader->epilog)
7851 return false;
7852
7853 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7854 if (shader->key.part.ps.prolog.poly_stipple) {
7855 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7856 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7857 }
7858
7859 /* Set up the enable bits for per-sample shading if needed. */
7860 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7861 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7862 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7863 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7864 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7865 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7866 }
7867 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7868 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7869 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7870 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7871 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7872 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7873 }
7874 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7875 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7876 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7877 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7878 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7879 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7880 }
7881 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7882 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7883 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7884 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7885 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7886 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7887 }
7888
7889 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7890 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7891 !(shader->config.spi_ps_input_ena & 0xf)) {
7892 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7893 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7894 }
7895
7896 /* At least one pair of interpolation weights must be enabled. */
7897 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7898 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7899 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7900 }
7901
7902 /* Samplemask fixup requires the sample ID. */
7903 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7904 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7905 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7906 }
7907
7908 /* The sample mask input is always enabled, because the API shader always
7909 * passes it through to the epilog. Disable it here if it's unused.
7910 */
7911 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7912 !shader->selector->info.reads_samplemask)
7913 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7914
7915 return true;
7916 }
7917
7918 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7919 unsigned *lds_size)
7920 {
7921 /* SPI barrier management bug:
7922 * Make sure we have at least 4k of LDS in use to avoid the bug.
7923 * It applies to workgroup sizes of more than one wavefront.
7924 */
7925 if (sscreen->info.family == CHIP_BONAIRE ||
7926 sscreen->info.family == CHIP_KABINI ||
7927 sscreen->info.family == CHIP_MULLINS)
7928 *lds_size = MAX2(*lds_size, 8);
7929 }
7930
7931 static void si_fix_resource_usage(struct si_screen *sscreen,
7932 struct si_shader *shader)
7933 {
7934 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7935
7936 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7937
7938 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7939 si_get_max_workgroup_size(shader) > 64) {
7940 si_multiwave_lds_size_workaround(sscreen,
7941 &shader->config.lds_size);
7942 }
7943 }
7944
7945 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7946 struct si_shader *shader,
7947 struct pipe_debug_callback *debug)
7948 {
7949 struct si_shader_selector *sel = shader->selector;
7950 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7951 int r;
7952
7953 /* LS, ES, VS are compiled on demand if the main part hasn't been
7954 * compiled for that stage.
7955 *
7956 * Vertex shaders are compiled on demand when a vertex fetch
7957 * workaround must be applied.
7958 */
7959 if (shader->is_monolithic) {
7960 /* Monolithic shader (compiled as a whole, has many variants,
7961 * may take a long time to compile).
7962 */
7963 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7964 if (r)
7965 return r;
7966 } else {
7967 /* The shader consists of several parts:
7968 *
7969 * - the middle part is the user shader, it has 1 variant only
7970 * and it was compiled during the creation of the shader
7971 * selector
7972 * - the prolog part is inserted at the beginning
7973 * - the epilog part is inserted at the end
7974 *
7975 * The prolog and epilog have many (but simple) variants.
7976 *
7977 * Starting with gfx9, geometry and tessellation control
7978 * shaders also contain the prolog and user shader parts of
7979 * the previous shader stage.
7980 */
7981
7982 if (!mainp)
7983 return -1;
7984
7985 /* Copy the compiled TGSI shader data over. */
7986 shader->is_binary_shared = true;
7987 shader->binary = mainp->binary;
7988 shader->config = mainp->config;
7989 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7990 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7991 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7992 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
7993 memcpy(shader->info.vs_output_param_offset,
7994 mainp->info.vs_output_param_offset,
7995 sizeof(mainp->info.vs_output_param_offset));
7996 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7997 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7998 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7999
8000 /* Select prologs and/or epilogs. */
8001 switch (sel->type) {
8002 case PIPE_SHADER_VERTEX:
8003 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
8004 return -1;
8005 break;
8006 case PIPE_SHADER_TESS_CTRL:
8007 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
8008 return -1;
8009 break;
8010 case PIPE_SHADER_TESS_EVAL:
8011 break;
8012 case PIPE_SHADER_GEOMETRY:
8013 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
8014 return -1;
8015 break;
8016 case PIPE_SHADER_FRAGMENT:
8017 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8018 return -1;
8019
8020 /* Make sure we have at least as many VGPRs as there
8021 * are allocated inputs.
8022 */
8023 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8024 shader->info.num_input_vgprs);
8025 break;
8026 }
8027
8028 /* Update SGPR and VGPR counts. */
8029 if (shader->prolog) {
8030 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8031 shader->prolog->config.num_sgprs);
8032 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8033 shader->prolog->config.num_vgprs);
8034 }
8035 if (shader->previous_stage) {
8036 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8037 shader->previous_stage->config.num_sgprs);
8038 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8039 shader->previous_stage->config.num_vgprs);
8040 shader->config.spilled_sgprs =
8041 MAX2(shader->config.spilled_sgprs,
8042 shader->previous_stage->config.spilled_sgprs);
8043 shader->config.spilled_vgprs =
8044 MAX2(shader->config.spilled_vgprs,
8045 shader->previous_stage->config.spilled_vgprs);
8046 shader->config.private_mem_vgprs =
8047 MAX2(shader->config.private_mem_vgprs,
8048 shader->previous_stage->config.private_mem_vgprs);
8049 shader->config.scratch_bytes_per_wave =
8050 MAX2(shader->config.scratch_bytes_per_wave,
8051 shader->previous_stage->config.scratch_bytes_per_wave);
8052 shader->info.uses_instanceid |=
8053 shader->previous_stage->info.uses_instanceid;
8054 }
8055 if (shader->prolog2) {
8056 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8057 shader->prolog2->config.num_sgprs);
8058 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8059 shader->prolog2->config.num_vgprs);
8060 }
8061 if (shader->epilog) {
8062 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8063 shader->epilog->config.num_sgprs);
8064 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8065 shader->epilog->config.num_vgprs);
8066 }
8067 si_calculate_max_simd_waves(shader);
8068 }
8069
8070 si_fix_resource_usage(sscreen, shader);
8071 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8072 stderr, true);
8073
8074 /* Upload. */
8075 r = si_shader_binary_upload(sscreen, shader);
8076 if (r) {
8077 fprintf(stderr, "LLVM failed to upload shader\n");
8078 return r;
8079 }
8080
8081 return 0;
8082 }
8083
8084 void si_shader_destroy(struct si_shader *shader)
8085 {
8086 if (shader->scratch_bo)
8087 r600_resource_reference(&shader->scratch_bo, NULL);
8088
8089 r600_resource_reference(&shader->bo, NULL);
8090
8091 if (!shader->is_binary_shared)
8092 ac_shader_binary_clean(&shader->binary);
8093
8094 free(shader->shader_log);
8095 }