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radeonsi: statically declare resource and sampler arrays
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "radeon/radeon_llvm.h"
36 #include "radeon/radeon_llvm_emit.h"
37 #include "util/u_memory.h"
38 #include "tgsi/tgsi_parse.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "si_pipe.h"
43 #include "si_shader.h"
44 #include "sid.h"
45
46 #include <errno.h>
47
48 struct si_shader_output_values
49 {
50 LLVMValueRef values[4];
51 unsigned name;
52 unsigned sid;
53 };
54
55 struct si_shader_context
56 {
57 struct radeon_llvm_context radeon_bld;
58 struct tgsi_parse_context parse;
59 struct tgsi_token * tokens;
60 struct si_shader *shader;
61 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
62 int param_streamout_config;
63 int param_streamout_write_index;
64 int param_streamout_offset[4];
65 int param_vertex_id;
66 int param_instance_id;
67 LLVMValueRef const_md;
68 LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
69 LLVMValueRef ddxy_lds;
70 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
71 LLVMValueRef resources[SI_NUM_SAMPLER_VIEWS];
72 LLVMValueRef samplers[SI_NUM_SAMPLER_STATES];
73 LLVMValueRef so_buffers[4];
74 LLVMValueRef gs_next_vertex;
75 };
76
77 static struct si_shader_context * si_shader_context(
78 struct lp_build_tgsi_context * bld_base)
79 {
80 return (struct si_shader_context *)bld_base;
81 }
82
83
84 #define PERSPECTIVE_BASE 0
85 #define LINEAR_BASE 9
86
87 #define SAMPLE_OFFSET 0
88 #define CENTER_OFFSET 2
89 #define CENTROID_OFSET 4
90
91 #define USE_SGPR_MAX_SUFFIX_LEN 5
92 #define CONST_ADDR_SPACE 2
93 #define LOCAL_ADDR_SPACE 3
94 #define USER_SGPR_ADDR_SPACE 8
95
96
97 #define SENDMSG_GS 2
98 #define SENDMSG_GS_DONE 3
99
100 #define SENDMSG_GS_OP_NOP (0 << 4)
101 #define SENDMSG_GS_OP_CUT (1 << 4)
102 #define SENDMSG_GS_OP_EMIT (2 << 4)
103 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
104
105 /**
106 * Returns a unique index for a semantic name and index. The index must be
107 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
108 * calculated.
109 */
110 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
111 {
112 switch (semantic_name) {
113 case TGSI_SEMANTIC_POSITION:
114 return 0;
115 case TGSI_SEMANTIC_PSIZE:
116 return 1;
117 case TGSI_SEMANTIC_CLIPDIST:
118 assert(index <= 1);
119 return 2 + index;
120 case TGSI_SEMANTIC_CLIPVERTEX:
121 return 4;
122 case TGSI_SEMANTIC_COLOR:
123 assert(index <= 1);
124 return 5 + index;
125 case TGSI_SEMANTIC_BCOLOR:
126 assert(index <= 1);
127 return 7 + index;
128 case TGSI_SEMANTIC_FOG:
129 return 9;
130 case TGSI_SEMANTIC_EDGEFLAG:
131 return 10;
132 case TGSI_SEMANTIC_GENERIC:
133 assert(index <= 63-11);
134 return 11 + index;
135 default:
136 assert(0);
137 return 63;
138 }
139 }
140
141 /**
142 * Given a semantic name and index of a parameter and a mask of used parameters
143 * (inputs or outputs), return the index of the parameter in the list of all
144 * used parameters.
145 *
146 * For example, assume this list of parameters:
147 * POSITION, PSIZE, GENERIC0, GENERIC2
148 * which has the mask:
149 * 11000000000101
150 * Then:
151 * querying POSITION returns 0,
152 * querying PSIZE returns 1,
153 * querying GENERIC0 returns 2,
154 * querying GENERIC2 returns 3.
155 *
156 * Which can be used as an offset to a parameter buffer in units of vec4s.
157 */
158 static int get_param_index(unsigned semantic_name, unsigned index,
159 uint64_t mask)
160 {
161 unsigned unique_index = si_shader_io_get_unique_index(semantic_name, index);
162 int i, param_index = 0;
163
164 /* If not present... */
165 if (!((1llu << unique_index) & mask))
166 return -1;
167
168 for (i = 0; mask; i++) {
169 uint64_t bit = 1llu << i;
170
171 if (bit & mask) {
172 if (i == unique_index)
173 return param_index;
174
175 mask &= ~bit;
176 param_index++;
177 }
178 }
179
180 assert(!"unreachable");
181 return -1;
182 }
183
184 /**
185 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
186 *
187 * @param offset The offset parameter specifies the number of
188 * elements to offset, not the number of bytes or dwords. An element is the
189 * the type pointed to by the base_ptr parameter (e.g. int is the element of
190 * an int* pointer)
191 *
192 * When LLVM lowers the load instruction, it will convert the element offset
193 * into a dword offset automatically.
194 *
195 */
196 static LLVMValueRef build_indexed_load(
197 struct si_shader_context * si_shader_ctx,
198 LLVMValueRef base_ptr,
199 LLVMValueRef offset)
200 {
201 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
202
203 LLVMValueRef indices[2] = {
204 LLVMConstInt(LLVMInt64TypeInContext(base->gallivm->context), 0, false),
205 offset
206 };
207 LLVMValueRef computed_ptr = LLVMBuildGEP(
208 base->gallivm->builder, base_ptr, indices, 2, "");
209
210 LLVMValueRef result = LLVMBuildLoad(base->gallivm->builder, computed_ptr, "");
211 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
212 return result;
213 }
214
215 static LLVMValueRef get_instance_index_for_fetch(
216 struct radeon_llvm_context * radeon_bld,
217 unsigned divisor)
218 {
219 struct si_shader_context *si_shader_ctx =
220 si_shader_context(&radeon_bld->soa.bld_base);
221 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
222
223 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
224 si_shader_ctx->param_instance_id);
225 result = LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
226 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
227
228 if (divisor > 1)
229 result = LLVMBuildUDiv(gallivm->builder, result,
230 lp_build_const_int32(gallivm, divisor), "");
231
232 return result;
233 }
234
235 static void declare_input_vs(
236 struct radeon_llvm_context *radeon_bld,
237 unsigned input_index,
238 const struct tgsi_full_declaration *decl)
239 {
240 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
241 struct gallivm_state *gallivm = base->gallivm;
242 struct si_shader_context *si_shader_ctx =
243 si_shader_context(&radeon_bld->soa.bld_base);
244 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
245
246 unsigned chan;
247
248 LLVMValueRef t_list_ptr;
249 LLVMValueRef t_offset;
250 LLVMValueRef t_list;
251 LLVMValueRef attribute_offset;
252 LLVMValueRef buffer_index;
253 LLVMValueRef args[3];
254 LLVMTypeRef vec4_type;
255 LLVMValueRef input;
256
257 /* Load the T list */
258 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
259
260 t_offset = lp_build_const_int32(gallivm, input_index);
261
262 t_list = build_indexed_load(si_shader_ctx, t_list_ptr, t_offset);
263
264 /* Build the attribute offset */
265 attribute_offset = lp_build_const_int32(gallivm, 0);
266
267 if (divisor) {
268 /* Build index from instance ID, start instance and divisor */
269 si_shader_ctx->shader->uses_instanceid = true;
270 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
271 } else {
272 /* Load the buffer index for vertices. */
273 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
274 si_shader_ctx->param_vertex_id);
275 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
276 SI_PARAM_BASE_VERTEX);
277 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
278 }
279
280 vec4_type = LLVMVectorType(base->elem_type, 4);
281 args[0] = t_list;
282 args[1] = attribute_offset;
283 args[2] = buffer_index;
284 input = build_intrinsic(gallivm->builder,
285 "llvm.SI.vs.load.input", vec4_type, args, 3,
286 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
287
288 /* Break up the vec4 into individual components */
289 for (chan = 0; chan < 4; chan++) {
290 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
291 /* XXX: Use a helper function for this. There is one in
292 * tgsi_llvm.c. */
293 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
294 LLVMBuildExtractElement(gallivm->builder,
295 input, llvm_chan, "");
296 }
297 }
298
299 static LLVMValueRef fetch_input_gs(
300 struct lp_build_tgsi_context *bld_base,
301 const struct tgsi_full_src_register *reg,
302 enum tgsi_opcode_type type,
303 unsigned swizzle)
304 {
305 struct lp_build_context *base = &bld_base->base;
306 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
307 struct si_shader *shader = si_shader_ctx->shader;
308 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
309 struct gallivm_state *gallivm = base->gallivm;
310 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
311 LLVMValueRef vtx_offset;
312 LLVMValueRef t_list_ptr;
313 LLVMValueRef t_list;
314 LLVMValueRef args[9];
315 unsigned vtx_offset_param;
316 struct tgsi_shader_info *info = &shader->selector->info;
317 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
318 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
319
320 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID) {
321 if (swizzle == 0)
322 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
323 SI_PARAM_PRIMITIVE_ID);
324 else
325 return uint->zero;
326 }
327
328 if (!reg->Register.Dimension)
329 return NULL;
330
331 if (swizzle == ~0) {
332 LLVMValueRef values[TGSI_NUM_CHANNELS];
333 unsigned chan;
334 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
335 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
336 }
337 return lp_build_gather_values(bld_base->base.gallivm, values,
338 TGSI_NUM_CHANNELS);
339 }
340
341 /* Get the vertex offset parameter */
342 vtx_offset_param = reg->Dimension.Index;
343 if (vtx_offset_param < 2) {
344 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
345 } else {
346 assert(vtx_offset_param < 6);
347 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
348 }
349 vtx_offset = lp_build_mul_imm(uint,
350 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
351 vtx_offset_param),
352 4);
353
354 /* Load the ESGS ring resource descriptor */
355 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
356 SI_PARAM_RW_BUFFERS);
357 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
358 lp_build_const_int32(gallivm, SI_RING_ESGS));
359
360 args[0] = t_list;
361 args[1] = vtx_offset;
362 args[2] = lp_build_const_int32(gallivm,
363 (get_param_index(semantic_name, semantic_index,
364 shader->selector->gs_used_inputs) * 4 +
365 swizzle) * 256);
366 args[3] = uint->zero;
367 args[4] = uint->one; /* OFFEN */
368 args[5] = uint->zero; /* IDXEN */
369 args[6] = uint->one; /* GLC */
370 args[7] = uint->zero; /* SLC */
371 args[8] = uint->zero; /* TFE */
372
373 return LLVMBuildBitCast(gallivm->builder,
374 build_intrinsic(gallivm->builder,
375 "llvm.SI.buffer.load.dword.i32.i32",
376 i32, args, 9,
377 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
378 tgsi2llvmtype(bld_base, type), "");
379 }
380
381 static void declare_input_fs(
382 struct radeon_llvm_context *radeon_bld,
383 unsigned input_index,
384 const struct tgsi_full_declaration *decl)
385 {
386 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
387 struct si_shader_context *si_shader_ctx =
388 si_shader_context(&radeon_bld->soa.bld_base);
389 struct si_shader *shader = si_shader_ctx->shader;
390 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
391 struct gallivm_state *gallivm = base->gallivm;
392 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
393 LLVMValueRef main_fn = radeon_bld->main_fn;
394
395 LLVMValueRef interp_param;
396 const char * intr_name;
397
398 /* This value is:
399 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
400 * quad begins a new primitive. Bit 0 always needs
401 * to be unset)
402 * [32:16] ParamOffset
403 *
404 */
405 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
406 LLVMValueRef attr_number;
407
408 unsigned chan;
409
410 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
411 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
412 unsigned soa_index =
413 radeon_llvm_reg_index_soa(input_index, chan);
414 radeon_bld->inputs[soa_index] =
415 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
416
417 if (chan == 3)
418 /* RCP for fragcoord.w */
419 radeon_bld->inputs[soa_index] =
420 LLVMBuildFDiv(gallivm->builder,
421 lp_build_const_float(gallivm, 1.0f),
422 radeon_bld->inputs[soa_index],
423 "");
424 }
425 return;
426 }
427
428 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
429 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
430 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
431 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
432 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
433 lp_build_const_float(gallivm, 0.0f);
434 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
435 lp_build_const_float(gallivm, 1.0f);
436
437 return;
438 }
439
440 shader->ps_input_param_offset[input_index] = shader->nparam++;
441 attr_number = lp_build_const_int32(gallivm,
442 shader->ps_input_param_offset[input_index]);
443
444 switch (decl->Interp.Interpolate) {
445 case TGSI_INTERPOLATE_CONSTANT:
446 interp_param = 0;
447 break;
448 case TGSI_INTERPOLATE_LINEAR:
449 if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_SAMPLE)
450 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_SAMPLE);
451 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
452 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
453 else
454 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
455 break;
456 case TGSI_INTERPOLATE_COLOR:
457 if (si_shader_ctx->shader->key.ps.flatshade) {
458 interp_param = 0;
459 break;
460 }
461 /* fall through to perspective */
462 case TGSI_INTERPOLATE_PERSPECTIVE:
463 if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_SAMPLE)
464 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_SAMPLE);
465 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
466 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
467 else
468 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
469 break;
470 default:
471 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
472 return;
473 }
474
475 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
476
477 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
478 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
479 si_shader_ctx->shader->key.ps.color_two_side) {
480 LLVMValueRef args[4];
481 LLVMValueRef face, is_face_positive;
482 LLVMValueRef back_attr_number =
483 lp_build_const_int32(gallivm,
484 shader->ps_input_param_offset[input_index] + 1);
485
486 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
487
488 is_face_positive = LLVMBuildFCmp(gallivm->builder,
489 LLVMRealUGT, face,
490 lp_build_const_float(gallivm, 0.0f),
491 "");
492
493 args[2] = params;
494 args[3] = interp_param;
495 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
496 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
497 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
498 LLVMValueRef front, back;
499
500 args[0] = llvm_chan;
501 args[1] = attr_number;
502 front = build_intrinsic(gallivm->builder, intr_name,
503 input_type, args, args[3] ? 4 : 3,
504 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
505
506 args[1] = back_attr_number;
507 back = build_intrinsic(gallivm->builder, intr_name,
508 input_type, args, args[3] ? 4 : 3,
509 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
510
511 radeon_bld->inputs[soa_index] =
512 LLVMBuildSelect(gallivm->builder,
513 is_face_positive,
514 front,
515 back,
516 "");
517 }
518
519 shader->nparam++;
520 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
521 LLVMValueRef args[4];
522
523 args[0] = uint->zero;
524 args[1] = attr_number;
525 args[2] = params;
526 args[3] = interp_param;
527 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
528 build_intrinsic(gallivm->builder, intr_name,
529 input_type, args, args[3] ? 4 : 3,
530 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
531 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
532 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
533 lp_build_const_float(gallivm, 0.0f);
534 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
535 lp_build_const_float(gallivm, 1.0f);
536 } else {
537 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
538 LLVMValueRef args[4];
539 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
540 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
541 args[0] = llvm_chan;
542 args[1] = attr_number;
543 args[2] = params;
544 args[3] = interp_param;
545 radeon_bld->inputs[soa_index] =
546 build_intrinsic(gallivm->builder, intr_name,
547 input_type, args, args[3] ? 4 : 3,
548 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
549 }
550 }
551 }
552
553 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
554 {
555 struct gallivm_state *gallivm = &radeon_bld->gallivm;
556 LLVMValueRef value = LLVMGetParam(radeon_bld->main_fn,
557 SI_PARAM_ANCILLARY);
558 value = LLVMBuildLShr(gallivm->builder, value,
559 lp_build_const_int32(gallivm, 8), "");
560 value = LLVMBuildAnd(gallivm->builder, value,
561 lp_build_const_int32(gallivm, 0xf), "");
562 return value;
563 }
564
565 static LLVMValueRef load_const(LLVMBuilderRef builder, LLVMValueRef resource,
566 LLVMValueRef offset, LLVMTypeRef return_type)
567 {
568 LLVMValueRef args[2] = {resource, offset};
569
570 return build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
571 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
572 }
573
574 static void declare_system_value(
575 struct radeon_llvm_context * radeon_bld,
576 unsigned index,
577 const struct tgsi_full_declaration *decl)
578 {
579 struct si_shader_context *si_shader_ctx =
580 si_shader_context(&radeon_bld->soa.bld_base);
581 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
582 struct gallivm_state *gallivm = &radeon_bld->gallivm;
583 LLVMValueRef value = 0;
584
585 switch (decl->Semantic.Name) {
586 case TGSI_SEMANTIC_INSTANCEID:
587 value = LLVMGetParam(radeon_bld->main_fn,
588 si_shader_ctx->param_instance_id);
589 break;
590
591 case TGSI_SEMANTIC_VERTEXID:
592 value = LLVMGetParam(radeon_bld->main_fn,
593 si_shader_ctx->param_vertex_id);
594 break;
595
596 case TGSI_SEMANTIC_SAMPLEID:
597 value = get_sample_id(radeon_bld);
598 break;
599
600 case TGSI_SEMANTIC_SAMPLEPOS:
601 {
602 LLVMBuilderRef builder = gallivm->builder;
603 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
604 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
605 LLVMValueRef resource = build_indexed_load(si_shader_ctx, desc, buf_index);
606
607 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
608 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, get_sample_id(radeon_bld), 8);
609 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
610
611 LLVMValueRef pos[4] = {
612 load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
613 load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
614 lp_build_const_float(gallivm, 0),
615 lp_build_const_float(gallivm, 0)
616 };
617 value = lp_build_gather_values(gallivm, pos, 4);
618 break;
619 }
620
621 default:
622 assert(!"unknown system value");
623 return;
624 }
625
626 radeon_bld->system_values[index] = value;
627 }
628
629 static LLVMValueRef fetch_constant(
630 struct lp_build_tgsi_context * bld_base,
631 const struct tgsi_full_src_register *reg,
632 enum tgsi_opcode_type type,
633 unsigned swizzle)
634 {
635 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
636 struct lp_build_context * base = &bld_base->base;
637 const struct tgsi_ind_register *ireg = &reg->Indirect;
638 unsigned buf, idx;
639
640 LLVMValueRef addr;
641 LLVMValueRef result;
642
643 if (swizzle == LP_CHAN_ALL) {
644 unsigned chan;
645 LLVMValueRef values[4];
646 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
647 values[chan] = fetch_constant(bld_base, reg, type, chan);
648
649 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
650 }
651
652 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
653 idx = reg->Register.Index * 4 + swizzle;
654
655 if (!reg->Register.Indirect)
656 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
657
658 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
659 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
660 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
661 addr = lp_build_add(&bld_base->uint_bld, addr,
662 lp_build_const_int32(base->gallivm, idx * 4));
663
664 result = load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
665 addr, base->elem_type);
666
667 return bitcast(bld_base, type, result);
668 }
669
670 /* Initialize arguments for the shader export intrinsic */
671 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
672 LLVMValueRef *values,
673 unsigned target,
674 LLVMValueRef *args)
675 {
676 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
677 struct lp_build_context *uint =
678 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
679 struct lp_build_context *base = &bld_base->base;
680 unsigned compressed = 0;
681 unsigned chan;
682
683 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
684 int cbuf = target - V_008DFC_SQ_EXP_MRT;
685
686 if (cbuf >= 0 && cbuf < 8) {
687 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
688
689 if (compressed)
690 si_shader_ctx->shader->spi_shader_col_format |=
691 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
692 else
693 si_shader_ctx->shader->spi_shader_col_format |=
694 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
695
696 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
697 }
698 }
699
700 if (compressed) {
701 /* Pixel shader needs to pack output values before export */
702 for (chan = 0; chan < 2; chan++ ) {
703 args[0] = values[2 * chan];
704 args[1] = values[2 * chan + 1];
705 args[chan + 5] =
706 build_intrinsic(base->gallivm->builder,
707 "llvm.SI.packf16",
708 LLVMInt32TypeInContext(base->gallivm->context),
709 args, 2,
710 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
711 args[chan + 7] = args[chan + 5] =
712 LLVMBuildBitCast(base->gallivm->builder,
713 args[chan + 5],
714 LLVMFloatTypeInContext(base->gallivm->context),
715 "");
716 }
717
718 /* Set COMPR flag */
719 args[4] = uint->one;
720 } else {
721 for (chan = 0; chan < 4; chan++ )
722 /* +5 because the first output value will be
723 * the 6th argument to the intrinsic. */
724 args[chan + 5] = values[chan];
725
726 /* Clear COMPR flag */
727 args[4] = uint->zero;
728 }
729
730 /* XXX: This controls which components of the output
731 * registers actually get exported. (e.g bit 0 means export
732 * X component, bit 1 means export Y component, etc.) I'm
733 * hard coding this to 0xf for now. In the future, we might
734 * want to do something else. */
735 args[0] = lp_build_const_int32(base->gallivm, 0xf);
736
737 /* Specify whether the EXEC mask represents the valid mask */
738 args[1] = uint->zero;
739
740 /* Specify whether this is the last export */
741 args[2] = uint->zero;
742
743 /* Specify the target we are exporting */
744 args[3] = lp_build_const_int32(base->gallivm, target);
745
746 /* XXX: We probably need to keep track of the output
747 * values, so we know what we are passing to the next
748 * stage. */
749 }
750
751 /* Load from output pointers and initialize arguments for the shader export intrinsic */
752 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
753 LLVMValueRef *out_ptr,
754 unsigned target,
755 LLVMValueRef *args)
756 {
757 struct gallivm_state *gallivm = bld_base->base.gallivm;
758 LLVMValueRef values[4];
759 int i;
760
761 for (i = 0; i < 4; i++)
762 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
763
764 si_llvm_init_export_args(bld_base, values, target, args);
765 }
766
767 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
768 LLVMValueRef *out_ptr)
769 {
770 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
771 struct gallivm_state *gallivm = bld_base->base.gallivm;
772
773 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
774 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
775 SI_PARAM_ALPHA_REF);
776
777 LLVMValueRef alpha_pass =
778 lp_build_cmp(&bld_base->base,
779 si_shader_ctx->shader->key.ps.alpha_func,
780 LLVMBuildLoad(gallivm->builder, out_ptr[3], ""),
781 alpha_ref);
782 LLVMValueRef arg =
783 lp_build_select(&bld_base->base,
784 alpha_pass,
785 lp_build_const_float(gallivm, 1.0f),
786 lp_build_const_float(gallivm, -1.0f));
787
788 build_intrinsic(gallivm->builder,
789 "llvm.AMDGPU.kill",
790 LLVMVoidTypeInContext(gallivm->context),
791 &arg, 1, 0);
792 } else {
793 build_intrinsic(gallivm->builder,
794 "llvm.AMDGPU.kilp",
795 LLVMVoidTypeInContext(gallivm->context),
796 NULL, 0, 0);
797 }
798
799 si_shader_ctx->shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
800 }
801
802 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
803 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
804 {
805 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
806 struct si_shader *shader = si_shader_ctx->shader;
807 struct lp_build_context *base = &bld_base->base;
808 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
809 unsigned reg_index;
810 unsigned chan;
811 unsigned const_chan;
812 LLVMValueRef base_elt;
813 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
814 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
815 LLVMValueRef const_resource = build_indexed_load(si_shader_ctx, ptr, constbuf_index);
816
817 for (reg_index = 0; reg_index < 2; reg_index ++) {
818 LLVMValueRef *args = pos[2 + reg_index];
819
820 shader->clip_dist_write |= 0xf << (4 * reg_index);
821
822 args[5] =
823 args[6] =
824 args[7] =
825 args[8] = lp_build_const_float(base->gallivm, 0.0f);
826
827 /* Compute dot products of position and user clip plane vectors */
828 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
829 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
830 args[1] = lp_build_const_int32(base->gallivm,
831 ((reg_index * 4 + chan) * 4 +
832 const_chan) * 4);
833 base_elt = load_const(base->gallivm->builder, const_resource,
834 args[1], base->elem_type);
835 args[5 + chan] =
836 lp_build_add(base, args[5 + chan],
837 lp_build_mul(base, base_elt,
838 out_elts[const_chan]));
839 }
840 }
841
842 args[0] = lp_build_const_int32(base->gallivm, 0xf);
843 args[1] = uint->zero;
844 args[2] = uint->zero;
845 args[3] = lp_build_const_int32(base->gallivm,
846 V_008DFC_SQ_EXP_POS + 2 + reg_index);
847 args[4] = uint->zero;
848 }
849 }
850
851 static void si_dump_streamout(struct pipe_stream_output_info *so)
852 {
853 unsigned i;
854
855 if (so->num_outputs)
856 fprintf(stderr, "STREAMOUT\n");
857
858 for (i = 0; i < so->num_outputs; i++) {
859 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
860 so->output[i].start_component;
861 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
862 i, so->output[i].output_buffer,
863 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
864 so->output[i].register_index,
865 mask & 1 ? "x" : "",
866 mask & 2 ? "y" : "",
867 mask & 4 ? "z" : "",
868 mask & 8 ? "w" : "");
869 }
870 }
871
872 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
873 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
874 * or v4i32 (num_channels=3,4). */
875 static void build_tbuffer_store(struct si_shader_context *shader,
876 LLVMValueRef rsrc,
877 LLVMValueRef vdata,
878 unsigned num_channels,
879 LLVMValueRef vaddr,
880 LLVMValueRef soffset,
881 unsigned inst_offset,
882 unsigned dfmt,
883 unsigned nfmt,
884 unsigned offen,
885 unsigned idxen,
886 unsigned glc,
887 unsigned slc,
888 unsigned tfe)
889 {
890 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
891 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
892 LLVMValueRef args[] = {
893 rsrc,
894 vdata,
895 LLVMConstInt(i32, num_channels, 0),
896 vaddr,
897 soffset,
898 LLVMConstInt(i32, inst_offset, 0),
899 LLVMConstInt(i32, dfmt, 0),
900 LLVMConstInt(i32, nfmt, 0),
901 LLVMConstInt(i32, offen, 0),
902 LLVMConstInt(i32, idxen, 0),
903 LLVMConstInt(i32, glc, 0),
904 LLVMConstInt(i32, slc, 0),
905 LLVMConstInt(i32, tfe, 0)
906 };
907
908 /* The instruction offset field has 12 bits */
909 assert(offen || inst_offset < (1 << 12));
910
911 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
912 unsigned func = CLAMP(num_channels, 1, 3) - 1;
913 const char *types[] = {"i32", "v2i32", "v4i32"};
914 char name[256];
915 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
916
917 lp_build_intrinsic(gallivm->builder, name,
918 LLVMVoidTypeInContext(gallivm->context),
919 args, Elements(args));
920 }
921
922 static void build_streamout_store(struct si_shader_context *shader,
923 LLVMValueRef rsrc,
924 LLVMValueRef vdata,
925 unsigned num_channels,
926 LLVMValueRef vaddr,
927 LLVMValueRef soffset,
928 unsigned inst_offset)
929 {
930 static unsigned dfmt[] = {
931 V_008F0C_BUF_DATA_FORMAT_32,
932 V_008F0C_BUF_DATA_FORMAT_32_32,
933 V_008F0C_BUF_DATA_FORMAT_32_32_32,
934 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
935 };
936 assert(num_channels >= 1 && num_channels <= 4);
937
938 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
939 inst_offset, dfmt[num_channels-1],
940 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
941 }
942
943 /* On SI, the vertex shader is responsible for writing streamout data
944 * to buffers. */
945 static void si_llvm_emit_streamout(struct si_shader_context *shader,
946 struct si_shader_output_values *outputs,
947 unsigned noutput)
948 {
949 struct pipe_stream_output_info *so = &shader->shader->selector->so;
950 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
951 LLVMBuilderRef builder = gallivm->builder;
952 int i, j;
953 struct lp_build_if_state if_ctx;
954
955 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
956
957 LLVMValueRef so_param =
958 LLVMGetParam(shader->radeon_bld.main_fn,
959 shader->param_streamout_config);
960
961 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
962 LLVMValueRef so_vtx_count =
963 LLVMBuildAnd(builder,
964 LLVMBuildLShr(builder, so_param,
965 LLVMConstInt(i32, 16, 0), ""),
966 LLVMConstInt(i32, 127, 0), "");
967
968 LLVMValueRef tid = build_intrinsic(builder, "llvm.SI.tid", i32,
969 NULL, 0, LLVMReadNoneAttribute);
970
971 /* can_emit = tid < so_vtx_count; */
972 LLVMValueRef can_emit =
973 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
974
975 /* Emit the streamout code conditionally. This actually avoids
976 * out-of-bounds buffer access. The hw tells us via the SGPR
977 * (so_vtx_count) which threads are allowed to emit streamout data. */
978 lp_build_if(&if_ctx, gallivm, can_emit);
979 {
980 /* The buffer offset is computed as follows:
981 * ByteOffset = streamout_offset[buffer_id]*4 +
982 * (streamout_write_index + thread_id)*stride[buffer_id] +
983 * attrib_offset
984 */
985
986 LLVMValueRef so_write_index =
987 LLVMGetParam(shader->radeon_bld.main_fn,
988 shader->param_streamout_write_index);
989
990 /* Compute (streamout_write_index + thread_id). */
991 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
992
993 /* Compute the write offset for each enabled buffer. */
994 LLVMValueRef so_write_offset[4] = {};
995 for (i = 0; i < 4; i++) {
996 if (!so->stride[i])
997 continue;
998
999 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1000 shader->param_streamout_offset[i]);
1001 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1002
1003 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1004 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1005 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1006 }
1007
1008 /* Write streamout data. */
1009 for (i = 0; i < so->num_outputs; i++) {
1010 unsigned buf_idx = so->output[i].output_buffer;
1011 unsigned reg = so->output[i].register_index;
1012 unsigned start = so->output[i].start_component;
1013 unsigned num_comps = so->output[i].num_components;
1014 LLVMValueRef out[4];
1015
1016 assert(num_comps && num_comps <= 4);
1017 if (!num_comps || num_comps > 4)
1018 continue;
1019
1020 if (reg >= noutput)
1021 continue;
1022
1023 /* Load the output as int. */
1024 for (j = 0; j < num_comps; j++) {
1025 out[j] = LLVMBuildBitCast(builder,
1026 outputs[reg].values[start+j],
1027 i32, "");
1028 }
1029
1030 /* Pack the output. */
1031 LLVMValueRef vdata = NULL;
1032
1033 switch (num_comps) {
1034 case 1: /* as i32 */
1035 vdata = out[0];
1036 break;
1037 case 2: /* as v2i32 */
1038 case 3: /* as v4i32 (aligned to 4) */
1039 case 4: /* as v4i32 */
1040 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1041 for (j = 0; j < num_comps; j++) {
1042 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1043 LLVMConstInt(i32, j, 0), "");
1044 }
1045 break;
1046 }
1047
1048 build_streamout_store(shader, shader->so_buffers[buf_idx],
1049 vdata, num_comps,
1050 so_write_offset[buf_idx],
1051 LLVMConstInt(i32, 0, 0),
1052 so->output[i].dst_offset*4);
1053 }
1054 }
1055 lp_build_endif(&if_ctx);
1056 }
1057
1058
1059 /* Generate export instructions for hardware VS shader stage */
1060 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1061 struct si_shader_output_values *outputs,
1062 unsigned noutput)
1063 {
1064 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1065 struct si_shader * shader = si_shader_ctx->shader;
1066 struct lp_build_context * base = &bld_base->base;
1067 struct lp_build_context * uint =
1068 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1069 LLVMValueRef args[9];
1070 LLVMValueRef pos_args[4][9] = { { 0 } };
1071 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL;
1072 unsigned semantic_name, semantic_index;
1073 unsigned target;
1074 unsigned param_count = 0;
1075 unsigned pos_idx;
1076 int i;
1077
1078 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1079 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1080 }
1081
1082 for (i = 0; i < noutput; i++) {
1083 semantic_name = outputs[i].name;
1084 semantic_index = outputs[i].sid;
1085
1086 handle_semantic:
1087 /* Select the correct target */
1088 switch(semantic_name) {
1089 case TGSI_SEMANTIC_PSIZE:
1090 shader->vs_out_misc_write = true;
1091 shader->vs_out_point_size = true;
1092 psize_value = outputs[i].values[0];
1093 continue;
1094 case TGSI_SEMANTIC_EDGEFLAG:
1095 shader->vs_out_misc_write = true;
1096 shader->vs_out_edgeflag = true;
1097 edgeflag_value = outputs[i].values[0];
1098 continue;
1099 case TGSI_SEMANTIC_LAYER:
1100 shader->vs_out_misc_write = true;
1101 shader->vs_out_layer = true;
1102 layer_value = outputs[i].values[0];
1103 continue;
1104 case TGSI_SEMANTIC_POSITION:
1105 target = V_008DFC_SQ_EXP_POS;
1106 break;
1107 case TGSI_SEMANTIC_COLOR:
1108 case TGSI_SEMANTIC_BCOLOR:
1109 target = V_008DFC_SQ_EXP_PARAM + param_count;
1110 shader->vs_output_param_offset[i] = param_count;
1111 param_count++;
1112 break;
1113 case TGSI_SEMANTIC_CLIPDIST:
1114 shader->clip_dist_write |=
1115 0xf << (semantic_index * 4);
1116 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1117 break;
1118 case TGSI_SEMANTIC_CLIPVERTEX:
1119 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1120 continue;
1121 case TGSI_SEMANTIC_PRIMID:
1122 case TGSI_SEMANTIC_FOG:
1123 case TGSI_SEMANTIC_GENERIC:
1124 target = V_008DFC_SQ_EXP_PARAM + param_count;
1125 shader->vs_output_param_offset[i] = param_count;
1126 param_count++;
1127 break;
1128 default:
1129 target = 0;
1130 fprintf(stderr,
1131 "Warning: SI unhandled vs output type:%d\n",
1132 semantic_name);
1133 }
1134
1135 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1136
1137 if (target >= V_008DFC_SQ_EXP_POS &&
1138 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1139 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1140 args, sizeof(args));
1141 } else {
1142 lp_build_intrinsic(base->gallivm->builder,
1143 "llvm.SI.export",
1144 LLVMVoidTypeInContext(base->gallivm->context),
1145 args, 9);
1146 }
1147
1148 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1149 semantic_name = TGSI_SEMANTIC_GENERIC;
1150 goto handle_semantic;
1151 }
1152 }
1153
1154 /* We need to add the position output manually if it's missing. */
1155 if (!pos_args[0][0]) {
1156 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1157 pos_args[0][1] = uint->zero; /* EXEC mask */
1158 pos_args[0][2] = uint->zero; /* last export? */
1159 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1160 pos_args[0][4] = uint->zero; /* COMPR flag */
1161 pos_args[0][5] = base->zero; /* X */
1162 pos_args[0][6] = base->zero; /* Y */
1163 pos_args[0][7] = base->zero; /* Z */
1164 pos_args[0][8] = base->one; /* W */
1165 }
1166
1167 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1168 if (shader->vs_out_misc_write) {
1169 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1170 shader->vs_out_point_size |
1171 (shader->vs_out_edgeflag << 1) |
1172 (shader->vs_out_layer << 2));
1173 pos_args[1][1] = uint->zero; /* EXEC mask */
1174 pos_args[1][2] = uint->zero; /* last export? */
1175 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1176 pos_args[1][4] = uint->zero; /* COMPR flag */
1177 pos_args[1][5] = base->zero; /* X */
1178 pos_args[1][6] = base->zero; /* Y */
1179 pos_args[1][7] = base->zero; /* Z */
1180 pos_args[1][8] = base->zero; /* W */
1181
1182 if (shader->vs_out_point_size)
1183 pos_args[1][5] = psize_value;
1184
1185 if (shader->vs_out_edgeflag) {
1186 /* The output is a float, but the hw expects an integer
1187 * with the first bit containing the edge flag. */
1188 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1189 edgeflag_value,
1190 bld_base->uint_bld.elem_type, "");
1191 edgeflag_value = lp_build_min(&bld_base->int_bld,
1192 edgeflag_value,
1193 bld_base->int_bld.one);
1194
1195 /* The LLVM intrinsic expects a float. */
1196 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1197 edgeflag_value,
1198 base->elem_type, "");
1199 }
1200
1201 if (shader->vs_out_layer)
1202 pos_args[1][7] = layer_value;
1203 }
1204
1205 for (i = 0; i < 4; i++)
1206 if (pos_args[i][0])
1207 shader->nr_pos_exports++;
1208
1209 pos_idx = 0;
1210 for (i = 0; i < 4; i++) {
1211 if (!pos_args[i][0])
1212 continue;
1213
1214 /* Specify the target we are exporting */
1215 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1216
1217 if (pos_idx == shader->nr_pos_exports)
1218 /* Specify that this is the last export */
1219 pos_args[i][2] = uint->one;
1220
1221 lp_build_intrinsic(base->gallivm->builder,
1222 "llvm.SI.export",
1223 LLVMVoidTypeInContext(base->gallivm->context),
1224 pos_args[i], 9);
1225 }
1226 }
1227
1228 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1229 {
1230 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1231 struct gallivm_state *gallivm = bld_base->base.gallivm;
1232 struct si_shader *es = si_shader_ctx->shader;
1233 struct tgsi_shader_info *info = &es->selector->info;
1234 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1235 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1236 SI_PARAM_ES2GS_OFFSET);
1237 LLVMValueRef t_list_ptr;
1238 LLVMValueRef t_list;
1239 unsigned chan;
1240 int i;
1241
1242 /* Load the ESGS ring resource descriptor */
1243 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1244 SI_PARAM_RW_BUFFERS);
1245 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
1246 lp_build_const_int32(gallivm, SI_RING_ESGS));
1247
1248 for (i = 0; i < info->num_outputs; i++) {
1249 LLVMValueRef *out_ptr =
1250 si_shader_ctx->radeon_bld.soa.outputs[i];
1251 int param_index = get_param_index(info->output_semantic_name[i],
1252 info->output_semantic_index[i],
1253 es->key.vs.gs_used_inputs);
1254
1255 if (param_index < 0)
1256 continue;
1257
1258 for (chan = 0; chan < 4; chan++) {
1259 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1260 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1261
1262 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
1263 LLVMGetUndef(i32), soffset,
1264 (4 * param_index + chan) * 4,
1265 V_008F0C_BUF_DATA_FORMAT_32,
1266 V_008F0C_BUF_NUM_FORMAT_UINT,
1267 0, 0, 1, 1, 0);
1268 }
1269 }
1270 }
1271
1272 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
1273 {
1274 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1275 struct gallivm_state *gallivm = bld_base->base.gallivm;
1276 LLVMValueRef args[2];
1277
1278 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
1279 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1280 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1281 LLVMVoidTypeInContext(gallivm->context), args, 2,
1282 LLVMNoUnwindAttribute);
1283 }
1284
1285 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
1286 {
1287 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1288 struct gallivm_state *gallivm = bld_base->base.gallivm;
1289 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
1290 struct si_shader_output_values *outputs = NULL;
1291 int i,j;
1292
1293 outputs = MALLOC(info->num_outputs * sizeof(outputs[0]));
1294
1295 for (i = 0; i < info->num_outputs; i++) {
1296 outputs[i].name = info->output_semantic_name[i];
1297 outputs[i].sid = info->output_semantic_index[i];
1298
1299 for (j = 0; j < 4; j++)
1300 outputs[i].values[j] =
1301 LLVMBuildLoad(gallivm->builder,
1302 si_shader_ctx->radeon_bld.soa.outputs[i][j],
1303 "");
1304 }
1305
1306 si_llvm_export_vs(bld_base, outputs, info->num_outputs);
1307 FREE(outputs);
1308 }
1309
1310 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
1311 {
1312 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1313 struct si_shader * shader = si_shader_ctx->shader;
1314 struct lp_build_context * base = &bld_base->base;
1315 struct lp_build_context * uint = &bld_base->uint_bld;
1316 struct tgsi_shader_info *info = &shader->selector->info;
1317 LLVMValueRef args[9];
1318 LLVMValueRef last_args[9] = { 0 };
1319 int depth_index = -1, stencil_index = -1, samplemask_index = -1;
1320 int i;
1321
1322 for (i = 0; i < info->num_outputs; i++) {
1323 unsigned semantic_name = info->output_semantic_name[i];
1324 unsigned semantic_index = info->output_semantic_index[i];
1325 unsigned target;
1326
1327 /* Select the correct target */
1328 switch (semantic_name) {
1329 case TGSI_SEMANTIC_POSITION:
1330 depth_index = i;
1331 continue;
1332 case TGSI_SEMANTIC_STENCIL:
1333 stencil_index = i;
1334 continue;
1335 case TGSI_SEMANTIC_SAMPLEMASK:
1336 samplemask_index = i;
1337 continue;
1338 case TGSI_SEMANTIC_COLOR:
1339 target = V_008DFC_SQ_EXP_MRT + semantic_index;
1340 if (si_shader_ctx->shader->key.ps.alpha_to_one)
1341 LLVMBuildStore(bld_base->base.gallivm->builder,
1342 bld_base->base.one,
1343 si_shader_ctx->radeon_bld.soa.outputs[i][3]);
1344
1345 if (semantic_index == 0 &&
1346 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
1347 si_alpha_test(bld_base,
1348 si_shader_ctx->radeon_bld.soa.outputs[i]);
1349 break;
1350 default:
1351 target = 0;
1352 fprintf(stderr,
1353 "Warning: SI unhandled fs output type:%d\n",
1354 semantic_name);
1355 }
1356
1357 si_llvm_init_export_args_load(bld_base,
1358 si_shader_ctx->radeon_bld.soa.outputs[i],
1359 target, args);
1360
1361 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1362 /* If there is an export instruction waiting to be emitted, do so now. */
1363 if (last_args[0]) {
1364 lp_build_intrinsic(base->gallivm->builder,
1365 "llvm.SI.export",
1366 LLVMVoidTypeInContext(base->gallivm->context),
1367 last_args, 9);
1368 }
1369
1370 /* This instruction will be emitted at the end of the shader. */
1371 memcpy(last_args, args, sizeof(args));
1372
1373 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
1374 if (shader->selector->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1375 semantic_index == 0 &&
1376 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
1377 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
1378 si_llvm_init_export_args_load(bld_base,
1379 si_shader_ctx->radeon_bld.soa.outputs[i],
1380 V_008DFC_SQ_EXP_MRT + c, args);
1381 lp_build_intrinsic(base->gallivm->builder,
1382 "llvm.SI.export",
1383 LLVMVoidTypeInContext(base->gallivm->context),
1384 args, 9);
1385 }
1386 }
1387 } else {
1388 lp_build_intrinsic(base->gallivm->builder,
1389 "llvm.SI.export",
1390 LLVMVoidTypeInContext(base->gallivm->context),
1391 args, 9);
1392 }
1393 }
1394
1395 if (depth_index >= 0 || stencil_index >= 0 || samplemask_index >= 0) {
1396 LLVMValueRef out_ptr;
1397 unsigned mask = 0;
1398
1399 /* Specify the target we are exporting */
1400 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
1401
1402 args[5] = base->zero; /* R, depth */
1403 args[6] = base->zero; /* G, stencil test value[0:7], stencil op value[8:15] */
1404 args[7] = base->zero; /* B, sample mask */
1405 args[8] = base->zero; /* A, alpha to mask */
1406
1407 if (depth_index >= 0) {
1408 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
1409 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1410 mask |= 0x1;
1411 si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1412 }
1413
1414 if (stencil_index >= 0) {
1415 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
1416 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1417 /* Only setting the stencil component bit (0x2) here
1418 * breaks some stencil piglit tests
1419 */
1420 mask |= 0x3;
1421 si_shader_ctx->shader->db_shader_control |=
1422 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
1423 }
1424
1425 if (samplemask_index >= 0) {
1426 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[samplemask_index][0];
1427 args[7] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1428 mask |= 0xf; /* Set all components. */
1429 si_shader_ctx->shader->db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(1);
1430 }
1431
1432 if (samplemask_index >= 0)
1433 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
1434 else if (stencil_index >= 0)
1435 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
1436 else
1437 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
1438
1439 /* Specify which components to enable */
1440 args[0] = lp_build_const_int32(base->gallivm, mask);
1441
1442 args[1] =
1443 args[2] =
1444 args[4] = uint->zero;
1445
1446 if (last_args[0])
1447 lp_build_intrinsic(base->gallivm->builder,
1448 "llvm.SI.export",
1449 LLVMVoidTypeInContext(base->gallivm->context),
1450 args, 9);
1451 else
1452 memcpy(last_args, args, sizeof(args));
1453 }
1454
1455 if (!last_args[0]) {
1456 /* Specify which components to enable */
1457 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
1458
1459 /* Specify the target we are exporting */
1460 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
1461
1462 /* Set COMPR flag to zero to export data as 32-bit */
1463 last_args[4] = uint->zero;
1464
1465 /* dummy bits */
1466 last_args[5]= uint->zero;
1467 last_args[6]= uint->zero;
1468 last_args[7]= uint->zero;
1469 last_args[8]= uint->zero;
1470 }
1471
1472 /* Specify whether the EXEC mask represents the valid mask */
1473 last_args[1] = uint->one;
1474
1475 /* Specify that this is the last export */
1476 last_args[2] = lp_build_const_int32(base->gallivm, 1);
1477
1478 lp_build_intrinsic(base->gallivm->builder,
1479 "llvm.SI.export",
1480 LLVMVoidTypeInContext(base->gallivm->context),
1481 last_args, 9);
1482 }
1483
1484 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1485 struct lp_build_tgsi_context * bld_base,
1486 struct lp_build_emit_data * emit_data);
1487
1488 static bool tgsi_is_shadow_sampler(unsigned target)
1489 {
1490 return target == TGSI_TEXTURE_SHADOW1D ||
1491 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1492 target == TGSI_TEXTURE_SHADOW2D ||
1493 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1494 target == TGSI_TEXTURE_SHADOWCUBE ||
1495 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
1496 target == TGSI_TEXTURE_SHADOWRECT;
1497 }
1498
1499 static const struct lp_build_tgsi_action tex_action;
1500
1501 static void tex_fetch_args(
1502 struct lp_build_tgsi_context * bld_base,
1503 struct lp_build_emit_data * emit_data)
1504 {
1505 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1506 struct gallivm_state *gallivm = bld_base->base.gallivm;
1507 const struct tgsi_full_instruction * inst = emit_data->inst;
1508 unsigned opcode = inst->Instruction.Opcode;
1509 unsigned target = inst->Texture.Texture;
1510 LLVMValueRef coords[4];
1511 LLVMValueRef address[16];
1512 int ref_pos;
1513 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
1514 unsigned count = 0;
1515 unsigned chan;
1516 unsigned sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1517 unsigned sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
1518 bool has_offset = HAVE_LLVM >= 0x0305 ? inst->Texture.NumOffsets > 0 : false;
1519
1520 if (target == TGSI_TEXTURE_BUFFER) {
1521 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
1522 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
1523 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
1524 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
1525
1526 /* Bitcast and truncate v8i32 to v16i8. */
1527 LLVMValueRef res = si_shader_ctx->resources[sampler_index];
1528 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
1529 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.zero, "");
1530 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
1531
1532 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
1533 emit_data->args[0] = res;
1534 emit_data->args[1] = bld_base->uint_bld.zero;
1535 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
1536 emit_data->arg_count = 3;
1537 return;
1538 }
1539
1540 /* Fetch and project texture coordinates */
1541 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1542 for (chan = 0; chan < 3; chan++ ) {
1543 coords[chan] = lp_build_emit_fetch(bld_base,
1544 emit_data->inst, 0,
1545 chan);
1546 if (opcode == TGSI_OPCODE_TXP)
1547 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1548 TGSI_OPCODE_DIV,
1549 coords[chan],
1550 coords[3]);
1551 }
1552
1553 if (opcode == TGSI_OPCODE_TXP)
1554 coords[3] = bld_base->base.one;
1555
1556 /* Pack offsets. */
1557 if (has_offset && opcode != TGSI_OPCODE_TXF) {
1558 /* The offsets are six-bit signed integers packed like this:
1559 * X=[5:0], Y=[13:8], and Z=[21:16].
1560 */
1561 LLVMValueRef offset[3], pack;
1562
1563 assert(inst->Texture.NumOffsets == 1);
1564
1565 for (chan = 0; chan < 3; chan++) {
1566 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
1567 emit_data->inst, 0, chan);
1568 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
1569 lp_build_const_int32(gallivm, 0x3f), "");
1570 if (chan)
1571 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
1572 lp_build_const_int32(gallivm, chan*8), "");
1573 }
1574
1575 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
1576 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
1577 address[count++] = pack;
1578 }
1579
1580 /* Pack LOD bias value */
1581 if (opcode == TGSI_OPCODE_TXB)
1582 address[count++] = coords[3];
1583 if (opcode == TGSI_OPCODE_TXB2)
1584 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1585
1586 /* Pack depth comparison value */
1587 if (tgsi_is_shadow_sampler(target) && opcode != TGSI_OPCODE_LODQ) {
1588 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1589 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1590 } else {
1591 assert(ref_pos >= 0);
1592 address[count++] = coords[ref_pos];
1593 }
1594 }
1595
1596 if (target == TGSI_TEXTURE_CUBE ||
1597 target == TGSI_TEXTURE_CUBE_ARRAY ||
1598 target == TGSI_TEXTURE_SHADOWCUBE ||
1599 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1600 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
1601
1602 /* Pack user derivatives */
1603 if (opcode == TGSI_OPCODE_TXD) {
1604 int num_deriv_channels, param;
1605
1606 switch (target) {
1607 case TGSI_TEXTURE_3D:
1608 num_deriv_channels = 3;
1609 break;
1610 case TGSI_TEXTURE_2D:
1611 case TGSI_TEXTURE_SHADOW2D:
1612 case TGSI_TEXTURE_RECT:
1613 case TGSI_TEXTURE_SHADOWRECT:
1614 case TGSI_TEXTURE_2D_ARRAY:
1615 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1616 case TGSI_TEXTURE_CUBE:
1617 case TGSI_TEXTURE_SHADOWCUBE:
1618 case TGSI_TEXTURE_CUBE_ARRAY:
1619 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1620 num_deriv_channels = 2;
1621 break;
1622 case TGSI_TEXTURE_1D:
1623 case TGSI_TEXTURE_SHADOW1D:
1624 case TGSI_TEXTURE_1D_ARRAY:
1625 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1626 num_deriv_channels = 1;
1627 break;
1628 default:
1629 assert(0); /* no other targets are valid here */
1630 }
1631
1632 for (param = 1; param <= 2; param++)
1633 for (chan = 0; chan < num_deriv_channels; chan++)
1634 address[count++] = lp_build_emit_fetch(bld_base, inst, param, chan);
1635 }
1636
1637 /* Pack texture coordinates */
1638 address[count++] = coords[0];
1639 if (num_coords > 1)
1640 address[count++] = coords[1];
1641 if (num_coords > 2)
1642 address[count++] = coords[2];
1643
1644 /* Pack LOD or sample index */
1645 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1646 address[count++] = coords[3];
1647 else if (opcode == TGSI_OPCODE_TXL2)
1648 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1649
1650 if (count > 16) {
1651 assert(!"Cannot handle more than 16 texture address parameters");
1652 count = 16;
1653 }
1654
1655 for (chan = 0; chan < count; chan++ ) {
1656 address[chan] = LLVMBuildBitCast(gallivm->builder,
1657 address[chan],
1658 LLVMInt32TypeInContext(gallivm->context),
1659 "");
1660 }
1661
1662 /* Adjust the sample index according to FMASK.
1663 *
1664 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1665 * which is the identity mapping. Each nibble says which physical sample
1666 * should be fetched to get that sample.
1667 *
1668 * For example, 0x11111100 means there are only 2 samples stored and
1669 * the second sample covers 3/4 of the pixel. When reading samples 0
1670 * and 1, return physical sample 0 (determined by the first two 0s
1671 * in FMASK), otherwise return physical sample 1.
1672 *
1673 * The sample index should be adjusted as follows:
1674 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1675 */
1676 if (target == TGSI_TEXTURE_2D_MSAA ||
1677 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1678 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1679 struct lp_build_emit_data txf_emit_data = *emit_data;
1680 LLVMValueRef txf_address[4];
1681 unsigned txf_count = count;
1682 struct tgsi_full_instruction inst = {};
1683
1684 memcpy(txf_address, address, sizeof(txf_address));
1685
1686 if (target == TGSI_TEXTURE_2D_MSAA) {
1687 txf_address[2] = bld_base->uint_bld.zero;
1688 }
1689 txf_address[3] = bld_base->uint_bld.zero;
1690
1691 /* Pad to a power-of-two size. */
1692 while (txf_count < util_next_power_of_two(txf_count))
1693 txf_address[txf_count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1694
1695 /* Read FMASK using TXF. */
1696 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
1697 inst.Texture.Texture = target == TGSI_TEXTURE_2D_MSAA ? TGSI_TEXTURE_2D : TGSI_TEXTURE_2D_ARRAY;
1698 txf_emit_data.inst = &inst;
1699 txf_emit_data.chan = 0;
1700 txf_emit_data.dst_type = LLVMVectorType(
1701 LLVMInt32TypeInContext(gallivm->context), 4);
1702 txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
1703 txf_emit_data.args[1] = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
1704 txf_emit_data.args[2] = lp_build_const_int32(gallivm, inst.Texture.Texture);
1705 txf_emit_data.arg_count = 3;
1706
1707 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
1708
1709 /* Initialize some constants. */
1710 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
1711 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
1712
1713 /* Apply the formula. */
1714 LLVMValueRef fmask =
1715 LLVMBuildExtractElement(gallivm->builder,
1716 txf_emit_data.output[0],
1717 uint_bld->zero, "");
1718
1719 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1720
1721 LLVMValueRef sample_index4 =
1722 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1723
1724 LLVMValueRef shifted_fmask =
1725 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1726
1727 LLVMValueRef final_sample =
1728 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1729
1730 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1731 * resource descriptor is 0 (invalid),
1732 */
1733 LLVMValueRef fmask_desc =
1734 LLVMBuildBitCast(gallivm->builder,
1735 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index],
1736 LLVMVectorType(uint_bld->elem_type, 8), "");
1737
1738 LLVMValueRef fmask_word1 =
1739 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1740 uint_bld->one, "");
1741
1742 LLVMValueRef word1_is_nonzero =
1743 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1744 fmask_word1, uint_bld->zero, "");
1745
1746 /* Replace the MSAA sample index. */
1747 address[sample_chan] =
1748 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1749 final_sample, address[sample_chan], "");
1750 }
1751
1752 /* Resource */
1753 emit_data->args[1] = si_shader_ctx->resources[sampler_index];
1754
1755 if (opcode == TGSI_OPCODE_TXF) {
1756 /* add tex offsets */
1757 if (inst->Texture.NumOffsets) {
1758 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1759 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
1760 const struct tgsi_texture_offset * off = inst->TexOffsets;
1761
1762 assert(inst->Texture.NumOffsets == 1);
1763
1764 switch (target) {
1765 case TGSI_TEXTURE_3D:
1766 address[2] = lp_build_add(uint_bld, address[2],
1767 bld->immediates[off->Index][off->SwizzleZ]);
1768 /* fall through */
1769 case TGSI_TEXTURE_2D:
1770 case TGSI_TEXTURE_SHADOW2D:
1771 case TGSI_TEXTURE_RECT:
1772 case TGSI_TEXTURE_SHADOWRECT:
1773 case TGSI_TEXTURE_2D_ARRAY:
1774 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1775 address[1] =
1776 lp_build_add(uint_bld, address[1],
1777 bld->immediates[off->Index][off->SwizzleY]);
1778 /* fall through */
1779 case TGSI_TEXTURE_1D:
1780 case TGSI_TEXTURE_SHADOW1D:
1781 case TGSI_TEXTURE_1D_ARRAY:
1782 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1783 address[0] =
1784 lp_build_add(uint_bld, address[0],
1785 bld->immediates[off->Index][off->SwizzleX]);
1786 break;
1787 /* texture offsets do not apply to other texture targets */
1788 }
1789 }
1790
1791 emit_data->args[2] = lp_build_const_int32(gallivm, target);
1792 emit_data->arg_count = 3;
1793
1794 emit_data->dst_type = LLVMVectorType(
1795 LLVMInt32TypeInContext(gallivm->context),
1796 4);
1797 } else if (opcode == TGSI_OPCODE_TG4 ||
1798 opcode == TGSI_OPCODE_LODQ ||
1799 has_offset) {
1800 unsigned is_array = target == TGSI_TEXTURE_1D_ARRAY ||
1801 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1802 target == TGSI_TEXTURE_2D_ARRAY ||
1803 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1804 target == TGSI_TEXTURE_CUBE_ARRAY ||
1805 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY;
1806 unsigned is_rect = target == TGSI_TEXTURE_RECT;
1807 unsigned dmask = 0xf;
1808
1809 if (opcode == TGSI_OPCODE_TG4) {
1810 unsigned gather_comp = 0;
1811
1812 /* DMASK was repurposed for GATHER4. 4 components are always
1813 * returned and DMASK works like a swizzle - it selects
1814 * the component to fetch. The only valid DMASK values are
1815 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1816 * (red,red,red,red) etc.) The ISA document doesn't mention
1817 * this.
1818 */
1819
1820 /* Get the component index from src1.x for Gather4. */
1821 if (!tgsi_is_shadow_sampler(target)) {
1822 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
1823 LLVMValueRef comp_imm;
1824 struct tgsi_src_register src1 = inst->Src[1].Register;
1825
1826 assert(src1.File == TGSI_FILE_IMMEDIATE);
1827
1828 comp_imm = imms[src1.Index][src1.SwizzleX];
1829 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1830 gather_comp = CLAMP(gather_comp, 0, 3);
1831 }
1832
1833 dmask = 1 << gather_comp;
1834 }
1835
1836 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1837 emit_data->args[3] = lp_build_const_int32(gallivm, dmask);
1838 emit_data->args[4] = lp_build_const_int32(gallivm, is_rect); /* unorm */
1839 emit_data->args[5] = lp_build_const_int32(gallivm, 0); /* r128 */
1840 emit_data->args[6] = lp_build_const_int32(gallivm, is_array); /* da */
1841 emit_data->args[7] = lp_build_const_int32(gallivm, 0); /* glc */
1842 emit_data->args[8] = lp_build_const_int32(gallivm, 0); /* slc */
1843 emit_data->args[9] = lp_build_const_int32(gallivm, 0); /* tfe */
1844 emit_data->args[10] = lp_build_const_int32(gallivm, 0); /* lwe */
1845
1846 emit_data->arg_count = 11;
1847
1848 emit_data->dst_type = LLVMVectorType(
1849 LLVMFloatTypeInContext(gallivm->context),
1850 4);
1851 } else {
1852 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1853 emit_data->args[3] = lp_build_const_int32(gallivm, target);
1854 emit_data->arg_count = 4;
1855
1856 emit_data->dst_type = LLVMVectorType(
1857 LLVMFloatTypeInContext(gallivm->context),
1858 4);
1859 }
1860
1861 /* The fetch opcode has been converted to a 2D array fetch.
1862 * This simplifies the LLVM backend. */
1863 if (target == TGSI_TEXTURE_CUBE_ARRAY)
1864 target = TGSI_TEXTURE_2D_ARRAY;
1865 else if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1866 target = TGSI_TEXTURE_SHADOW2D_ARRAY;
1867
1868 /* Pad to power of two vector */
1869 while (count < util_next_power_of_two(count))
1870 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1871
1872 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
1873 }
1874
1875 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1876 struct lp_build_tgsi_context * bld_base,
1877 struct lp_build_emit_data * emit_data)
1878 {
1879 struct lp_build_context * base = &bld_base->base;
1880 unsigned opcode = emit_data->inst->Instruction.Opcode;
1881 unsigned target = emit_data->inst->Texture.Texture;
1882 char intr_name[127];
1883 bool has_offset = HAVE_LLVM >= 0x0305 ?
1884 emit_data->inst->Texture.NumOffsets > 0 : false;
1885
1886 if (target == TGSI_TEXTURE_BUFFER) {
1887 emit_data->output[emit_data->chan] = build_intrinsic(
1888 base->gallivm->builder,
1889 "llvm.SI.vs.load.input", emit_data->dst_type,
1890 emit_data->args, emit_data->arg_count,
1891 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1892 return;
1893 }
1894
1895 if (opcode == TGSI_OPCODE_TG4 ||
1896 opcode == TGSI_OPCODE_LODQ ||
1897 (opcode != TGSI_OPCODE_TXF && has_offset)) {
1898 bool is_shadow = tgsi_is_shadow_sampler(target);
1899 const char *name = "llvm.SI.image.sample";
1900 const char *infix = "";
1901
1902 switch (opcode) {
1903 case TGSI_OPCODE_TEX:
1904 case TGSI_OPCODE_TEX2:
1905 case TGSI_OPCODE_TXP:
1906 break;
1907 case TGSI_OPCODE_TXB:
1908 case TGSI_OPCODE_TXB2:
1909 infix = ".b";
1910 break;
1911 case TGSI_OPCODE_TXL:
1912 case TGSI_OPCODE_TXL2:
1913 infix = ".l";
1914 break;
1915 case TGSI_OPCODE_TXD:
1916 infix = ".d";
1917 break;
1918 case TGSI_OPCODE_TG4:
1919 name = "llvm.SI.gather4";
1920 break;
1921 case TGSI_OPCODE_LODQ:
1922 name = "llvm.SI.getlod";
1923 is_shadow = false;
1924 has_offset = false;
1925 break;
1926 default:
1927 assert(0);
1928 return;
1929 }
1930
1931 /* Add the type and suffixes .c, .o if needed. */
1932 sprintf(intr_name, "%s%s%s%s.v%ui32", name,
1933 is_shadow ? ".c" : "", infix, has_offset ? ".o" : "",
1934 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
1935
1936 emit_data->output[emit_data->chan] = build_intrinsic(
1937 base->gallivm->builder, intr_name, emit_data->dst_type,
1938 emit_data->args, emit_data->arg_count,
1939 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1940 } else {
1941 LLVMTypeRef i8, v16i8, v32i8;
1942 const char *name;
1943
1944 switch (opcode) {
1945 case TGSI_OPCODE_TEX:
1946 case TGSI_OPCODE_TEX2:
1947 case TGSI_OPCODE_TXP:
1948 name = "llvm.SI.sample";
1949 break;
1950 case TGSI_OPCODE_TXB:
1951 case TGSI_OPCODE_TXB2:
1952 name = "llvm.SI.sampleb";
1953 break;
1954 case TGSI_OPCODE_TXD:
1955 name = "llvm.SI.sampled";
1956 break;
1957 case TGSI_OPCODE_TXF:
1958 name = "llvm.SI.imageload";
1959 break;
1960 case TGSI_OPCODE_TXL:
1961 case TGSI_OPCODE_TXL2:
1962 name = "llvm.SI.samplel";
1963 break;
1964 default:
1965 assert(0);
1966 return;
1967 }
1968
1969 i8 = LLVMInt8TypeInContext(base->gallivm->context);
1970 v16i8 = LLVMVectorType(i8, 16);
1971 v32i8 = LLVMVectorType(i8, 32);
1972
1973 emit_data->args[1] = LLVMBuildBitCast(base->gallivm->builder,
1974 emit_data->args[1], v32i8, "");
1975 if (opcode != TGSI_OPCODE_TXF) {
1976 emit_data->args[2] = LLVMBuildBitCast(base->gallivm->builder,
1977 emit_data->args[2], v16i8, "");
1978 }
1979
1980 sprintf(intr_name, "%s.v%ui32", name,
1981 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
1982
1983 emit_data->output[emit_data->chan] = build_intrinsic(
1984 base->gallivm->builder, intr_name, emit_data->dst_type,
1985 emit_data->args, emit_data->arg_count,
1986 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1987 }
1988 }
1989
1990 static void txq_fetch_args(
1991 struct lp_build_tgsi_context * bld_base,
1992 struct lp_build_emit_data * emit_data)
1993 {
1994 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1995 const struct tgsi_full_instruction *inst = emit_data->inst;
1996 struct gallivm_state *gallivm = bld_base->base.gallivm;
1997 unsigned target = inst->Texture.Texture;
1998
1999 if (target == TGSI_TEXTURE_BUFFER) {
2000 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2001 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2002
2003 /* Read the size from the buffer descriptor directly. */
2004 LLVMValueRef size = si_shader_ctx->resources[inst->Src[1].Register.Index];
2005 size = LLVMBuildBitCast(gallivm->builder, size, v8i32, "");
2006 size = LLVMBuildExtractElement(gallivm->builder, size,
2007 lp_build_const_int32(gallivm, 2), "");
2008 emit_data->args[0] = size;
2009 return;
2010 }
2011
2012 /* Mip level */
2013 emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2014
2015 /* Resource */
2016 emit_data->args[1] = si_shader_ctx->resources[inst->Src[1].Register.Index];
2017
2018 /* Texture target */
2019 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2020 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2021 target = TGSI_TEXTURE_2D_ARRAY;
2022
2023 emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
2024 target);
2025
2026 emit_data->arg_count = 3;
2027
2028 emit_data->dst_type = LLVMVectorType(
2029 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
2030 4);
2031 }
2032
2033 static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
2034 struct lp_build_tgsi_context * bld_base,
2035 struct lp_build_emit_data * emit_data)
2036 {
2037 unsigned target = emit_data->inst->Texture.Texture;
2038
2039 if (target == TGSI_TEXTURE_BUFFER) {
2040 /* Just return the buffer size. */
2041 emit_data->output[emit_data->chan] = emit_data->args[0];
2042 return;
2043 }
2044
2045 build_tgsi_intrinsic_nomem(action, bld_base, emit_data);
2046
2047 /* Divide the number of layers by 6 to get the number of cubes. */
2048 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2049 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2050 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2051 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2052 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2053
2054 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2055 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2056 z = LLVMBuildSDiv(builder, z, six, "");
2057
2058 emit_data->output[emit_data->chan] =
2059 LLVMBuildInsertElement(builder, v4, z, two, "");
2060 }
2061 }
2062
2063 static void si_llvm_emit_ddxy(
2064 const struct lp_build_tgsi_action * action,
2065 struct lp_build_tgsi_context * bld_base,
2066 struct lp_build_emit_data * emit_data)
2067 {
2068 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2069 struct gallivm_state *gallivm = bld_base->base.gallivm;
2070 struct lp_build_context * base = &bld_base->base;
2071 const struct tgsi_full_instruction *inst = emit_data->inst;
2072 unsigned opcode = inst->Instruction.Opcode;
2073 LLVMValueRef indices[2];
2074 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2075 LLVMValueRef tl, trbl, result[4];
2076 LLVMTypeRef i32;
2077 unsigned swizzle[4];
2078 unsigned c;
2079
2080 i32 = LLVMInt32TypeInContext(gallivm->context);
2081
2082 indices[0] = bld_base->uint_bld.zero;
2083 indices[1] = build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2084 NULL, 0, LLVMReadNoneAttribute);
2085 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2086 indices, 2, "");
2087
2088 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2089 lp_build_const_int32(gallivm, 0xfffffffc), "");
2090 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2091 indices, 2, "");
2092
2093 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
2094 lp_build_const_int32(gallivm,
2095 opcode == TGSI_OPCODE_DDX ? 1 : 2),
2096 "");
2097 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2098 indices, 2, "");
2099
2100 for (c = 0; c < 4; ++c) {
2101 unsigned i;
2102
2103 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
2104 for (i = 0; i < c; ++i) {
2105 if (swizzle[i] == swizzle[c]) {
2106 result[c] = result[i];
2107 break;
2108 }
2109 }
2110 if (i != c)
2111 continue;
2112
2113 LLVMBuildStore(gallivm->builder,
2114 LLVMBuildBitCast(gallivm->builder,
2115 lp_build_emit_fetch(bld_base, inst, 0, c),
2116 i32, ""),
2117 store_ptr);
2118
2119 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
2120 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
2121
2122 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
2123 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
2124
2125 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
2126 }
2127
2128 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
2129 }
2130
2131 /* Emit one vertex from the geometry shader */
2132 static void si_llvm_emit_vertex(
2133 const struct lp_build_tgsi_action *action,
2134 struct lp_build_tgsi_context *bld_base,
2135 struct lp_build_emit_data *emit_data)
2136 {
2137 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2138 struct lp_build_context *uint = &bld_base->uint_bld;
2139 struct si_shader *shader = si_shader_ctx->shader;
2140 struct tgsi_shader_info *info = &shader->selector->info;
2141 struct gallivm_state *gallivm = bld_base->base.gallivm;
2142 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2143 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2144 SI_PARAM_GS2VS_OFFSET);
2145 LLVMValueRef gs_next_vertex;
2146 LLVMValueRef can_emit, kill;
2147 LLVMValueRef t_list_ptr;
2148 LLVMValueRef t_list;
2149 LLVMValueRef args[2];
2150 unsigned chan;
2151 int i;
2152
2153 /* Load the GSVS ring resource descriptor */
2154 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2155 SI_PARAM_RW_BUFFERS);
2156 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
2157 lp_build_const_int32(gallivm, SI_RING_GSVS));
2158
2159 /* Write vertex attribute values to GSVS ring */
2160 gs_next_vertex = LLVMBuildLoad(gallivm->builder, si_shader_ctx->gs_next_vertex, "");
2161
2162 /* If this thread has already emitted the declared maximum number of
2163 * vertices, kill it: excessive vertex emissions are not supposed to
2164 * have any effect, and GS threads have no externally observable
2165 * effects other than emitting vertices.
2166 */
2167 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
2168 lp_build_const_int32(gallivm,
2169 shader->selector->gs_max_out_vertices), "");
2170 kill = lp_build_select(&bld_base->base, can_emit,
2171 lp_build_const_float(gallivm, 1.0f),
2172 lp_build_const_float(gallivm, -1.0f));
2173 build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2174 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
2175
2176 for (i = 0; i < info->num_outputs; i++) {
2177 LLVMValueRef *out_ptr =
2178 si_shader_ctx->radeon_bld.soa.outputs[i];
2179
2180 for (chan = 0; chan < 4; chan++) {
2181 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2182 LLVMValueRef voffset =
2183 lp_build_const_int32(gallivm, (i * 4 + chan) *
2184 shader->selector->gs_max_out_vertices);
2185
2186 voffset = lp_build_add(uint, voffset, gs_next_vertex);
2187 voffset = lp_build_mul_imm(uint, voffset, 4);
2188
2189 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2190
2191 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
2192 voffset, soffset, 0,
2193 V_008F0C_BUF_DATA_FORMAT_32,
2194 V_008F0C_BUF_NUM_FORMAT_UINT,
2195 1, 0, 1, 1, 0);
2196 }
2197 }
2198 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
2199 lp_build_const_int32(gallivm, 1));
2200 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex);
2201
2202 /* Signal vertex emission */
2203 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS);
2204 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2205 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2206 LLVMVoidTypeInContext(gallivm->context), args, 2,
2207 LLVMNoUnwindAttribute);
2208 }
2209
2210 /* Cut one primitive from the geometry shader */
2211 static void si_llvm_emit_primitive(
2212 const struct lp_build_tgsi_action *action,
2213 struct lp_build_tgsi_context *bld_base,
2214 struct lp_build_emit_data *emit_data)
2215 {
2216 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2217 struct gallivm_state *gallivm = bld_base->base.gallivm;
2218 LLVMValueRef args[2];
2219
2220 /* Signal primitive cut */
2221 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS);
2222 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2223 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2224 LLVMVoidTypeInContext(gallivm->context), args, 2,
2225 LLVMNoUnwindAttribute);
2226 }
2227
2228 static const struct lp_build_tgsi_action tex_action = {
2229 .fetch_args = tex_fetch_args,
2230 .emit = build_tex_intrinsic,
2231 };
2232
2233 static const struct lp_build_tgsi_action txq_action = {
2234 .fetch_args = txq_fetch_args,
2235 .emit = build_txq_intrinsic,
2236 .intr_name = "llvm.SI.resinfo"
2237 };
2238
2239 static void create_meta_data(struct si_shader_context *si_shader_ctx)
2240 {
2241 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2242 LLVMValueRef args[3];
2243
2244 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
2245 args[1] = 0;
2246 args[2] = lp_build_const_int32(gallivm, 1);
2247
2248 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
2249 }
2250
2251 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
2252 {
2253 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
2254 CONST_ADDR_SPACE);
2255 }
2256
2257 static void create_function(struct si_shader_context *si_shader_ctx)
2258 {
2259 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2260 struct gallivm_state *gallivm = bld_base->base.gallivm;
2261 struct si_shader *shader = si_shader_ctx->shader;
2262 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
2263 unsigned i, last_array_pointer, last_sgpr, num_params;
2264
2265 i8 = LLVMInt8TypeInContext(gallivm->context);
2266 i32 = LLVMInt32TypeInContext(gallivm->context);
2267 f32 = LLVMFloatTypeInContext(gallivm->context);
2268 v2i32 = LLVMVectorType(i32, 2);
2269 v3i32 = LLVMVectorType(i32, 3);
2270 v4i32 = LLVMVectorType(i32, 4);
2271 v8i32 = LLVMVectorType(i32, 8);
2272 v16i8 = LLVMVectorType(i8, 16);
2273
2274 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
2275 params[SI_PARAM_CONST] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
2276 params[SI_PARAM_SAMPLER] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
2277 params[SI_PARAM_RESOURCE] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
2278 last_array_pointer = SI_PARAM_RESOURCE;
2279
2280 switch (si_shader_ctx->type) {
2281 case TGSI_PROCESSOR_VERTEX:
2282 params[SI_PARAM_VERTEX_BUFFER] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
2283 last_array_pointer = SI_PARAM_VERTEX_BUFFER;
2284 params[SI_PARAM_BASE_VERTEX] = i32;
2285 params[SI_PARAM_START_INSTANCE] = i32;
2286 num_params = SI_PARAM_START_INSTANCE+1;
2287
2288 if (shader->key.vs.as_es) {
2289 params[SI_PARAM_ES2GS_OFFSET] = i32;
2290 num_params++;
2291 } else {
2292 if (shader->is_gs_copy_shader) {
2293 last_array_pointer = SI_PARAM_CONST;
2294 num_params = SI_PARAM_CONST+1;
2295 }
2296
2297 /* The locations of the other parameters are assigned dynamically. */
2298
2299 /* Streamout SGPRs. */
2300 if (shader->selector->so.num_outputs) {
2301 params[si_shader_ctx->param_streamout_config = num_params++] = i32;
2302 params[si_shader_ctx->param_streamout_write_index = num_params++] = i32;
2303 }
2304 /* A streamout buffer offset is loaded if the stride is non-zero. */
2305 for (i = 0; i < 4; i++) {
2306 if (!shader->selector->so.stride[i])
2307 continue;
2308
2309 params[si_shader_ctx->param_streamout_offset[i] = num_params++] = i32;
2310 }
2311 }
2312
2313 last_sgpr = num_params-1;
2314
2315 /* VGPRs */
2316 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
2317 params[num_params++] = i32; /* unused*/
2318 params[num_params++] = i32; /* unused */
2319 params[si_shader_ctx->param_instance_id = num_params++] = i32;
2320 break;
2321
2322 case TGSI_PROCESSOR_GEOMETRY:
2323 params[SI_PARAM_GS2VS_OFFSET] = i32;
2324 params[SI_PARAM_GS_WAVE_ID] = i32;
2325 last_sgpr = SI_PARAM_GS_WAVE_ID;
2326
2327 /* VGPRs */
2328 params[SI_PARAM_VTX0_OFFSET] = i32;
2329 params[SI_PARAM_VTX1_OFFSET] = i32;
2330 params[SI_PARAM_PRIMITIVE_ID] = i32;
2331 params[SI_PARAM_VTX2_OFFSET] = i32;
2332 params[SI_PARAM_VTX3_OFFSET] = i32;
2333 params[SI_PARAM_VTX4_OFFSET] = i32;
2334 params[SI_PARAM_VTX5_OFFSET] = i32;
2335 params[SI_PARAM_GS_INSTANCE_ID] = i32;
2336 num_params = SI_PARAM_GS_INSTANCE_ID+1;
2337 break;
2338
2339 case TGSI_PROCESSOR_FRAGMENT:
2340 params[SI_PARAM_ALPHA_REF] = f32;
2341 params[SI_PARAM_PRIM_MASK] = i32;
2342 last_sgpr = SI_PARAM_PRIM_MASK;
2343 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
2344 params[SI_PARAM_PERSP_CENTER] = v2i32;
2345 params[SI_PARAM_PERSP_CENTROID] = v2i32;
2346 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
2347 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
2348 params[SI_PARAM_LINEAR_CENTER] = v2i32;
2349 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
2350 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
2351 params[SI_PARAM_POS_X_FLOAT] = f32;
2352 params[SI_PARAM_POS_Y_FLOAT] = f32;
2353 params[SI_PARAM_POS_Z_FLOAT] = f32;
2354 params[SI_PARAM_POS_W_FLOAT] = f32;
2355 params[SI_PARAM_FRONT_FACE] = f32;
2356 params[SI_PARAM_ANCILLARY] = i32;
2357 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
2358 params[SI_PARAM_POS_FIXED_PT] = f32;
2359 num_params = SI_PARAM_POS_FIXED_PT+1;
2360 break;
2361
2362 default:
2363 assert(0 && "unimplemented shader");
2364 return;
2365 }
2366
2367 assert(num_params <= Elements(params));
2368 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
2369 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
2370
2371 for (i = 0; i <= last_sgpr; ++i) {
2372 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
2373
2374 /* We tell llvm that array inputs are passed by value to allow Sinking pass
2375 * to move load. Inputs are constant so this is fine. */
2376 if (i <= last_array_pointer)
2377 LLVMAddAttribute(P, LLVMByValAttribute);
2378 else
2379 LLVMAddAttribute(P, LLVMInRegAttribute);
2380 }
2381
2382 if (bld_base->info &&
2383 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
2384 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0))
2385 si_shader_ctx->ddxy_lds =
2386 LLVMAddGlobalInAddressSpace(gallivm->module,
2387 LLVMArrayType(i32, 64),
2388 "ddxy_lds",
2389 LOCAL_ADDR_SPACE);
2390 }
2391
2392 static void preload_constants(struct si_shader_context *si_shader_ctx)
2393 {
2394 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2395 struct gallivm_state * gallivm = bld_base->base.gallivm;
2396 const struct tgsi_shader_info * info = bld_base->info;
2397 unsigned buf;
2398 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
2399
2400 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
2401 unsigned i, num_const = info->const_file_max[buf] + 1;
2402
2403 if (num_const == 0)
2404 continue;
2405
2406 /* Allocate space for the constant values */
2407 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
2408
2409 /* Load the resource descriptor */
2410 si_shader_ctx->const_resource[buf] =
2411 build_indexed_load(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
2412
2413 /* Load the constants, we rely on the code sinking to do the rest */
2414 for (i = 0; i < num_const * 4; ++i) {
2415 si_shader_ctx->constants[buf][i] =
2416 load_const(gallivm->builder,
2417 si_shader_ctx->const_resource[buf],
2418 lp_build_const_int32(gallivm, i * 4),
2419 bld_base->base.elem_type);
2420 }
2421 }
2422 }
2423
2424 static void preload_samplers(struct si_shader_context *si_shader_ctx)
2425 {
2426 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2427 struct gallivm_state * gallivm = bld_base->base.gallivm;
2428 const struct tgsi_shader_info * info = bld_base->info;
2429
2430 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
2431
2432 LLVMValueRef res_ptr, samp_ptr;
2433 LLVMValueRef offset;
2434
2435 if (num_samplers == 0)
2436 return;
2437
2438 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2439 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2440
2441 /* Load the resources and samplers, we rely on the code sinking to do the rest */
2442 for (i = 0; i < num_samplers; ++i) {
2443 /* Resource */
2444 offset = lp_build_const_int32(gallivm, i);
2445 si_shader_ctx->resources[i] = build_indexed_load(si_shader_ctx, res_ptr, offset);
2446
2447 /* Sampler */
2448 offset = lp_build_const_int32(gallivm, i);
2449 si_shader_ctx->samplers[i] = build_indexed_load(si_shader_ctx, samp_ptr, offset);
2450
2451 /* FMASK resource */
2452 if (info->is_msaa_sampler[i]) {
2453 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
2454 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + i] =
2455 build_indexed_load(si_shader_ctx, res_ptr, offset);
2456 }
2457 }
2458 }
2459
2460 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
2461 {
2462 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2463 struct gallivm_state * gallivm = bld_base->base.gallivm;
2464 unsigned i;
2465
2466 if (si_shader_ctx->type != TGSI_PROCESSOR_VERTEX ||
2467 si_shader_ctx->shader->key.vs.as_es ||
2468 !si_shader_ctx->shader->selector->so.num_outputs)
2469 return;
2470
2471 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2472 SI_PARAM_RW_BUFFERS);
2473
2474 /* Load the resources, we rely on the code sinking to do the rest */
2475 for (i = 0; i < 4; ++i) {
2476 if (si_shader_ctx->shader->selector->so.stride[i]) {
2477 LLVMValueRef offset = lp_build_const_int32(gallivm,
2478 SI_SO_BUF_OFFSET + i);
2479
2480 si_shader_ctx->so_buffers[i] = build_indexed_load(si_shader_ctx, buf_ptr, offset);
2481 }
2482 }
2483 }
2484
2485 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
2486 LLVMModuleRef mod)
2487 {
2488 unsigned r; /* llvm_compile result */
2489 unsigned i;
2490 unsigned char *ptr;
2491 struct radeon_shader_binary binary;
2492 bool dump = r600_can_dump_shader(&sscreen->b,
2493 shader->selector ? shader->selector->tokens : NULL);
2494 const char * gpu_family = r600_get_llvm_processor_name(sscreen->b.family);
2495 unsigned code_size;
2496
2497 /* Use LLVM to compile shader */
2498 memset(&binary, 0, sizeof(binary));
2499 r = radeon_llvm_compile(mod, &binary, gpu_family, dump);
2500
2501 /* Output binary dump if rscreen->debug_flags are set */
2502 if (dump && ! binary.disassembled) {
2503 fprintf(stderr, "SI CODE:\n");
2504 for (i = 0; i < binary.code_size; i+=4 ) {
2505 fprintf(stderr, "%02x%02x%02x%02x\n", binary.code[i + 3],
2506 binary.code[i + 2], binary.code[i + 1],
2507 binary.code[i]);
2508 }
2509 }
2510
2511 /* XXX: We may be able to emit some of these values directly rather than
2512 * extracting fields to be emitted later.
2513 */
2514 /* Parse config data in compiled binary */
2515 for (i = 0; i < binary.config_size; i+= 8) {
2516 unsigned reg = util_le32_to_cpu(*(uint32_t*)(binary.config + i));
2517 unsigned value = util_le32_to_cpu(*(uint32_t*)(binary.config + i + 4));
2518 switch (reg) {
2519 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
2520 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
2521 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
2522 case R_00B848_COMPUTE_PGM_RSRC1:
2523 shader->num_sgprs = (G_00B028_SGPRS(value) + 1) * 8;
2524 shader->num_vgprs = (G_00B028_VGPRS(value) + 1) * 4;
2525 break;
2526 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
2527 shader->lds_size = G_00B02C_EXTRA_LDS_SIZE(value);
2528 break;
2529 case R_00B84C_COMPUTE_PGM_RSRC2:
2530 shader->lds_size = G_00B84C_LDS_SIZE(value);
2531 break;
2532 case R_0286CC_SPI_PS_INPUT_ENA:
2533 shader->spi_ps_input_ena = value;
2534 break;
2535 case R_00B860_COMPUTE_TMPRING_SIZE:
2536 /* WAVESIZE is in units of 256 dwords. */
2537 shader->scratch_bytes_per_wave =
2538 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
2539 break;
2540 default:
2541 fprintf(stderr, "Warning: Compiler emitted unknown "
2542 "config register: 0x%x\n", reg);
2543 break;
2544 }
2545 }
2546
2547 /* copy new shader */
2548 code_size = binary.code_size + binary.rodata_size;
2549 r600_resource_reference(&shader->bo, NULL);
2550 shader->bo = si_resource_create_custom(&sscreen->b.b, PIPE_USAGE_IMMUTABLE,
2551 code_size);
2552 if (shader->bo == NULL) {
2553 return -ENOMEM;
2554 }
2555
2556 ptr = sscreen->b.ws->buffer_map(shader->bo->cs_buf, NULL, PIPE_TRANSFER_WRITE);
2557 util_memcpy_cpu_to_le32(ptr, binary.code, binary.code_size);
2558 if (binary.rodata_size > 0) {
2559 ptr += binary.code_size;
2560 util_memcpy_cpu_to_le32(ptr, binary.rodata, binary.rodata_size);
2561 }
2562
2563 sscreen->b.ws->buffer_unmap(shader->bo->cs_buf);
2564
2565 free(binary.code);
2566 free(binary.config);
2567 free(binary.rodata);
2568
2569 return r;
2570 }
2571
2572 /* Generate code for the hardware VS shader stage to go with a geometry shader */
2573 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
2574 struct si_shader_context *si_shader_ctx,
2575 struct si_shader *gs, bool dump)
2576 {
2577 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
2578 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2579 struct lp_build_context *base = &bld_base->base;
2580 struct lp_build_context *uint = &bld_base->uint_bld;
2581 struct si_shader *shader = si_shader_ctx->shader;
2582 struct si_shader_output_values *outputs;
2583 struct tgsi_shader_info *gsinfo = &gs->selector->info;
2584 LLVMValueRef t_list_ptr, t_list;
2585 LLVMValueRef args[9];
2586 int i, r;
2587
2588 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
2589
2590 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
2591 shader->is_gs_copy_shader = true;
2592
2593 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
2594
2595 create_meta_data(si_shader_ctx);
2596 create_function(si_shader_ctx);
2597 preload_streamout_buffers(si_shader_ctx);
2598
2599 /* Load the GSVS ring resource descriptor */
2600 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2601 SI_PARAM_RW_BUFFERS);
2602 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
2603 lp_build_const_int32(gallivm, SI_RING_GSVS));
2604
2605 args[0] = t_list;
2606 args[1] = lp_build_mul_imm(uint,
2607 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2608 si_shader_ctx->param_vertex_id),
2609 4);
2610 args[3] = uint->zero;
2611 args[4] = uint->one; /* OFFEN */
2612 args[5] = uint->zero; /* IDXEN */
2613 args[6] = uint->one; /* GLC */
2614 args[7] = uint->one; /* SLC */
2615 args[8] = uint->zero; /* TFE */
2616
2617 /* Fetch vertex data from GSVS ring */
2618 for (i = 0; i < gsinfo->num_outputs; ++i) {
2619 unsigned chan;
2620
2621 outputs[i].name = gsinfo->output_semantic_name[i];
2622 outputs[i].sid = gsinfo->output_semantic_index[i];
2623
2624 for (chan = 0; chan < 4; chan++) {
2625 args[2] = lp_build_const_int32(gallivm,
2626 (i * 4 + chan) *
2627 gs->selector->gs_max_out_vertices * 16 * 4);
2628
2629 outputs[i].values[chan] =
2630 LLVMBuildBitCast(gallivm->builder,
2631 build_intrinsic(gallivm->builder,
2632 "llvm.SI.buffer.load.dword.i32.i32",
2633 LLVMInt32TypeInContext(gallivm->context),
2634 args, 9,
2635 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
2636 base->elem_type, "");
2637 }
2638 }
2639
2640 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
2641
2642 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
2643
2644 if (dump)
2645 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
2646
2647 r = si_compile_llvm(sscreen, si_shader_ctx->shader,
2648 bld_base->base.gallivm->module);
2649
2650 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
2651
2652 FREE(outputs);
2653 return r;
2654 }
2655
2656 int si_shader_create(struct si_screen *sscreen, struct si_shader *shader)
2657 {
2658 struct si_shader_selector *sel = shader->selector;
2659 struct si_shader_context si_shader_ctx;
2660 struct lp_build_tgsi_context * bld_base;
2661 LLVMModuleRef mod;
2662 int r = 0;
2663 bool dump = r600_can_dump_shader(&sscreen->b, sel->tokens);
2664
2665 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2666 * conversion fails. */
2667 if (dump) {
2668 tgsi_dump(sel->tokens, 0);
2669 si_dump_streamout(&sel->so);
2670 }
2671
2672 assert(shader->nparam == 0);
2673
2674 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
2675 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
2676 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
2677
2678 if (sel->info.uses_kill)
2679 shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
2680
2681 shader->uses_instanceid = sel->info.uses_instanceid;
2682 bld_base->info = &sel->info;
2683 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
2684
2685 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
2686 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
2687 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
2688 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
2689 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
2690 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
2691 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
2692 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
2693 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
2694 bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
2695 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
2696 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
2697
2698 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
2699 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
2700
2701 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
2702 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
2703
2704 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
2705 si_shader_ctx.tokens = sel->tokens;
2706 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
2707 si_shader_ctx.shader = shader;
2708 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
2709
2710 switch (si_shader_ctx.type) {
2711 case TGSI_PROCESSOR_VERTEX:
2712 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
2713 if (shader->key.vs.as_es) {
2714 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
2715 } else {
2716 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
2717 }
2718 break;
2719 case TGSI_PROCESSOR_GEOMETRY:
2720 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
2721 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
2722 break;
2723 case TGSI_PROCESSOR_FRAGMENT:
2724 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
2725 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
2726
2727 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2728 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2729 shader->db_shader_control |=
2730 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2731 break;
2732 case TGSI_FS_DEPTH_LAYOUT_LESS:
2733 shader->db_shader_control |=
2734 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2735 break;
2736 }
2737 break;
2738 default:
2739 assert(!"Unsupported shader type");
2740 return -1;
2741 }
2742
2743 create_meta_data(&si_shader_ctx);
2744 create_function(&si_shader_ctx);
2745 preload_constants(&si_shader_ctx);
2746 preload_samplers(&si_shader_ctx);
2747 preload_streamout_buffers(&si_shader_ctx);
2748
2749 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2750 si_shader_ctx.gs_next_vertex =
2751 lp_build_alloca(bld_base->base.gallivm,
2752 bld_base->uint_bld.elem_type, "");
2753 }
2754
2755 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
2756 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
2757 goto out;
2758 }
2759
2760 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
2761
2762 mod = bld_base->base.gallivm->module;
2763 r = si_compile_llvm(sscreen, shader, mod);
2764 if (r) {
2765 fprintf(stderr, "LLVM failed to compile shader\n");
2766 goto out;
2767 }
2768
2769 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
2770
2771 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2772 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
2773 shader->gs_copy_shader->selector = shader->selector;
2774 shader->gs_copy_shader->key = shader->key;
2775 si_shader_ctx.shader = shader->gs_copy_shader;
2776 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
2777 shader, dump))) {
2778 free(shader->gs_copy_shader);
2779 shader->gs_copy_shader = NULL;
2780 goto out;
2781 }
2782 }
2783
2784 tgsi_parse_free(&si_shader_ctx.parse);
2785
2786 out:
2787 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
2788 FREE(si_shader_ctx.constants[i]);
2789
2790 return r;
2791 }
2792
2793 void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader)
2794 {
2795 if (shader->gs_copy_shader)
2796 si_shader_destroy(ctx, shader->gs_copy_shader);
2797
2798 r600_resource_reference(&shader->bo, NULL);
2799 r600_resource_reference(&shader->scratch_bo, NULL);
2800 }