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radeonsi: Don't modify PA_SC_RASTER_CONFIG register value if rb_mask == 0
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "radeon/radeon_llvm.h"
36 #include "radeon/radeon_elf_util.h"
37 #include "radeon/radeon_llvm_emit.h"
38 #include "util/u_memory.h"
39 #include "tgsi/tgsi_parse.h"
40 #include "tgsi/tgsi_util.h"
41 #include "tgsi/tgsi_dump.h"
42
43 #include "si_pipe.h"
44 #include "si_shader.h"
45 #include "sid.h"
46
47 #include <errno.h>
48
49 struct si_shader_output_values
50 {
51 LLVMValueRef values[4];
52 unsigned name;
53 unsigned sid;
54 };
55
56 struct si_shader_context
57 {
58 struct radeon_llvm_context radeon_bld;
59 struct tgsi_parse_context parse;
60 struct tgsi_token * tokens;
61 struct si_shader *shader;
62 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
63 int param_streamout_config;
64 int param_streamout_write_index;
65 int param_streamout_offset[4];
66 int param_vertex_id;
67 int param_instance_id;
68 LLVMValueRef const_md;
69 LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
70 LLVMValueRef ddxy_lds;
71 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
72 LLVMValueRef resources[SI_NUM_SAMPLER_VIEWS];
73 LLVMValueRef samplers[SI_NUM_SAMPLER_STATES];
74 LLVMValueRef so_buffers[4];
75 LLVMValueRef esgs_ring;
76 LLVMValueRef gsvs_ring;
77 LLVMValueRef gs_next_vertex;
78 };
79
80 static struct si_shader_context * si_shader_context(
81 struct lp_build_tgsi_context * bld_base)
82 {
83 return (struct si_shader_context *)bld_base;
84 }
85
86
87 #define PERSPECTIVE_BASE 0
88 #define LINEAR_BASE 9
89
90 #define SAMPLE_OFFSET 0
91 #define CENTER_OFFSET 2
92 #define CENTROID_OFSET 4
93
94 #define USE_SGPR_MAX_SUFFIX_LEN 5
95 #define CONST_ADDR_SPACE 2
96 #define LOCAL_ADDR_SPACE 3
97 #define USER_SGPR_ADDR_SPACE 8
98
99
100 #define SENDMSG_GS 2
101 #define SENDMSG_GS_DONE 3
102
103 #define SENDMSG_GS_OP_NOP (0 << 4)
104 #define SENDMSG_GS_OP_CUT (1 << 4)
105 #define SENDMSG_GS_OP_EMIT (2 << 4)
106 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
107
108 /**
109 * Returns a unique index for a semantic name and index. The index must be
110 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
111 * calculated.
112 */
113 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
114 {
115 switch (semantic_name) {
116 case TGSI_SEMANTIC_POSITION:
117 return 0;
118 case TGSI_SEMANTIC_PSIZE:
119 return 1;
120 case TGSI_SEMANTIC_CLIPDIST:
121 assert(index <= 1);
122 return 2 + index;
123 case TGSI_SEMANTIC_CLIPVERTEX:
124 return 4;
125 case TGSI_SEMANTIC_COLOR:
126 assert(index <= 1);
127 return 5 + index;
128 case TGSI_SEMANTIC_BCOLOR:
129 assert(index <= 1);
130 return 7 + index;
131 case TGSI_SEMANTIC_FOG:
132 return 9;
133 case TGSI_SEMANTIC_EDGEFLAG:
134 return 10;
135 case TGSI_SEMANTIC_GENERIC:
136 assert(index <= 63-11);
137 return 11 + index;
138 default:
139 assert(0);
140 return 63;
141 }
142 }
143
144 /**
145 * Given a semantic name and index of a parameter and a mask of used parameters
146 * (inputs or outputs), return the index of the parameter in the list of all
147 * used parameters.
148 *
149 * For example, assume this list of parameters:
150 * POSITION, PSIZE, GENERIC0, GENERIC2
151 * which has the mask:
152 * 11000000000101
153 * Then:
154 * querying POSITION returns 0,
155 * querying PSIZE returns 1,
156 * querying GENERIC0 returns 2,
157 * querying GENERIC2 returns 3.
158 *
159 * Which can be used as an offset to a parameter buffer in units of vec4s.
160 */
161 static int get_param_index(unsigned semantic_name, unsigned index,
162 uint64_t mask)
163 {
164 unsigned unique_index = si_shader_io_get_unique_index(semantic_name, index);
165 int i, param_index = 0;
166
167 /* If not present... */
168 if (!((1llu << unique_index) & mask))
169 return -1;
170
171 for (i = 0; mask; i++) {
172 uint64_t bit = 1llu << i;
173
174 if (bit & mask) {
175 if (i == unique_index)
176 return param_index;
177
178 mask &= ~bit;
179 param_index++;
180 }
181 }
182
183 assert(!"unreachable");
184 return -1;
185 }
186
187 /**
188 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
189 * It's equivalent to doing a load from &base_ptr[index].
190 *
191 * \param base_ptr Where the array starts.
192 * \param index The element index into the array.
193 */
194 static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
195 LLVMValueRef base_ptr, LLVMValueRef index)
196 {
197 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
198 struct gallivm_state *gallivm = bld_base->base.gallivm;
199 LLVMValueRef indices[2], pointer;
200
201 indices[0] = bld_base->uint_bld.zero;
202 indices[1] = index;
203
204 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
205 return LLVMBuildLoad(gallivm->builder, pointer, "");
206 }
207
208 /**
209 * Do a load from &base_ptr[index], but also add a flag that it's loading
210 * a constant.
211 */
212 static LLVMValueRef build_indexed_load_const(
213 struct si_shader_context * si_shader_ctx,
214 LLVMValueRef base_ptr, LLVMValueRef index)
215 {
216 LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
217 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
218 return result;
219 }
220
221 static LLVMValueRef get_instance_index_for_fetch(
222 struct radeon_llvm_context * radeon_bld,
223 unsigned divisor)
224 {
225 struct si_shader_context *si_shader_ctx =
226 si_shader_context(&radeon_bld->soa.bld_base);
227 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
228
229 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
230 si_shader_ctx->param_instance_id);
231 result = LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
232 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
233
234 if (divisor > 1)
235 result = LLVMBuildUDiv(gallivm->builder, result,
236 lp_build_const_int32(gallivm, divisor), "");
237
238 return result;
239 }
240
241 static void declare_input_vs(
242 struct radeon_llvm_context *radeon_bld,
243 unsigned input_index,
244 const struct tgsi_full_declaration *decl)
245 {
246 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
247 struct gallivm_state *gallivm = base->gallivm;
248 struct si_shader_context *si_shader_ctx =
249 si_shader_context(&radeon_bld->soa.bld_base);
250 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
251
252 unsigned chan;
253
254 LLVMValueRef t_list_ptr;
255 LLVMValueRef t_offset;
256 LLVMValueRef t_list;
257 LLVMValueRef attribute_offset;
258 LLVMValueRef buffer_index;
259 LLVMValueRef args[3];
260 LLVMTypeRef vec4_type;
261 LLVMValueRef input;
262
263 /* Load the T list */
264 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
265
266 t_offset = lp_build_const_int32(gallivm, input_index);
267
268 t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
269
270 /* Build the attribute offset */
271 attribute_offset = lp_build_const_int32(gallivm, 0);
272
273 if (divisor) {
274 /* Build index from instance ID, start instance and divisor */
275 si_shader_ctx->shader->uses_instanceid = true;
276 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
277 } else {
278 /* Load the buffer index for vertices. */
279 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
280 si_shader_ctx->param_vertex_id);
281 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
282 SI_PARAM_BASE_VERTEX);
283 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
284 }
285
286 vec4_type = LLVMVectorType(base->elem_type, 4);
287 args[0] = t_list;
288 args[1] = attribute_offset;
289 args[2] = buffer_index;
290 input = build_intrinsic(gallivm->builder,
291 "llvm.SI.vs.load.input", vec4_type, args, 3,
292 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
293
294 /* Break up the vec4 into individual components */
295 for (chan = 0; chan < 4; chan++) {
296 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
297 /* XXX: Use a helper function for this. There is one in
298 * tgsi_llvm.c. */
299 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
300 LLVMBuildExtractElement(gallivm->builder,
301 input, llvm_chan, "");
302 }
303 }
304
305 static LLVMValueRef fetch_input_gs(
306 struct lp_build_tgsi_context *bld_base,
307 const struct tgsi_full_src_register *reg,
308 enum tgsi_opcode_type type,
309 unsigned swizzle)
310 {
311 struct lp_build_context *base = &bld_base->base;
312 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
313 struct si_shader *shader = si_shader_ctx->shader;
314 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
315 struct gallivm_state *gallivm = base->gallivm;
316 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
317 LLVMValueRef vtx_offset;
318 LLVMValueRef args[9];
319 unsigned vtx_offset_param;
320 struct tgsi_shader_info *info = &shader->selector->info;
321 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
322 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
323
324 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID) {
325 if (swizzle == 0)
326 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
327 SI_PARAM_PRIMITIVE_ID);
328 else
329 return uint->zero;
330 }
331
332 if (!reg->Register.Dimension)
333 return NULL;
334
335 if (swizzle == ~0) {
336 LLVMValueRef values[TGSI_NUM_CHANNELS];
337 unsigned chan;
338 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
339 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
340 }
341 return lp_build_gather_values(bld_base->base.gallivm, values,
342 TGSI_NUM_CHANNELS);
343 }
344
345 /* Get the vertex offset parameter */
346 vtx_offset_param = reg->Dimension.Index;
347 if (vtx_offset_param < 2) {
348 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
349 } else {
350 assert(vtx_offset_param < 6);
351 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
352 }
353 vtx_offset = lp_build_mul_imm(uint,
354 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
355 vtx_offset_param),
356 4);
357
358 args[0] = si_shader_ctx->esgs_ring;
359 args[1] = vtx_offset;
360 args[2] = lp_build_const_int32(gallivm,
361 (get_param_index(semantic_name, semantic_index,
362 shader->selector->gs_used_inputs) * 4 +
363 swizzle) * 256);
364 args[3] = uint->zero;
365 args[4] = uint->one; /* OFFEN */
366 args[5] = uint->zero; /* IDXEN */
367 args[6] = uint->one; /* GLC */
368 args[7] = uint->zero; /* SLC */
369 args[8] = uint->zero; /* TFE */
370
371 return LLVMBuildBitCast(gallivm->builder,
372 build_intrinsic(gallivm->builder,
373 "llvm.SI.buffer.load.dword.i32.i32",
374 i32, args, 9,
375 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
376 tgsi2llvmtype(bld_base, type), "");
377 }
378
379 static void declare_input_fs(
380 struct radeon_llvm_context *radeon_bld,
381 unsigned input_index,
382 const struct tgsi_full_declaration *decl)
383 {
384 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
385 struct si_shader_context *si_shader_ctx =
386 si_shader_context(&radeon_bld->soa.bld_base);
387 struct si_shader *shader = si_shader_ctx->shader;
388 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
389 struct gallivm_state *gallivm = base->gallivm;
390 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
391 LLVMValueRef main_fn = radeon_bld->main_fn;
392
393 LLVMValueRef interp_param;
394 const char * intr_name;
395
396 /* This value is:
397 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
398 * quad begins a new primitive. Bit 0 always needs
399 * to be unset)
400 * [32:16] ParamOffset
401 *
402 */
403 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
404 LLVMValueRef attr_number;
405
406 unsigned chan;
407
408 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
409 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
410 unsigned soa_index =
411 radeon_llvm_reg_index_soa(input_index, chan);
412 radeon_bld->inputs[soa_index] =
413 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
414
415 if (chan == 3)
416 /* RCP for fragcoord.w */
417 radeon_bld->inputs[soa_index] =
418 LLVMBuildFDiv(gallivm->builder,
419 lp_build_const_float(gallivm, 1.0f),
420 radeon_bld->inputs[soa_index],
421 "");
422 }
423 return;
424 }
425
426 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
427 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
428 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
429 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
430 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
431 lp_build_const_float(gallivm, 0.0f);
432 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
433 lp_build_const_float(gallivm, 1.0f);
434
435 return;
436 }
437
438 shader->ps_input_param_offset[input_index] = shader->nparam++;
439 attr_number = lp_build_const_int32(gallivm,
440 shader->ps_input_param_offset[input_index]);
441
442 switch (decl->Interp.Interpolate) {
443 case TGSI_INTERPOLATE_CONSTANT:
444 interp_param = 0;
445 break;
446 case TGSI_INTERPOLATE_LINEAR:
447 if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_SAMPLE)
448 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_SAMPLE);
449 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
450 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
451 else
452 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
453 break;
454 case TGSI_INTERPOLATE_COLOR:
455 if (si_shader_ctx->shader->key.ps.flatshade) {
456 interp_param = 0;
457 break;
458 }
459 /* fall through to perspective */
460 case TGSI_INTERPOLATE_PERSPECTIVE:
461 if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_SAMPLE)
462 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_SAMPLE);
463 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
464 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
465 else
466 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
467 break;
468 default:
469 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
470 return;
471 }
472
473 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
474
475 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
476 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
477 si_shader_ctx->shader->key.ps.color_two_side) {
478 LLVMValueRef args[4];
479 LLVMValueRef face, is_face_positive;
480 LLVMValueRef back_attr_number =
481 lp_build_const_int32(gallivm,
482 shader->ps_input_param_offset[input_index] + 1);
483
484 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
485
486 is_face_positive = LLVMBuildFCmp(gallivm->builder,
487 LLVMRealUGT, face,
488 lp_build_const_float(gallivm, 0.0f),
489 "");
490
491 args[2] = params;
492 args[3] = interp_param;
493 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
494 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
495 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
496 LLVMValueRef front, back;
497
498 args[0] = llvm_chan;
499 args[1] = attr_number;
500 front = build_intrinsic(gallivm->builder, intr_name,
501 input_type, args, args[3] ? 4 : 3,
502 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
503
504 args[1] = back_attr_number;
505 back = build_intrinsic(gallivm->builder, intr_name,
506 input_type, args, args[3] ? 4 : 3,
507 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
508
509 radeon_bld->inputs[soa_index] =
510 LLVMBuildSelect(gallivm->builder,
511 is_face_positive,
512 front,
513 back,
514 "");
515 }
516
517 shader->nparam++;
518 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
519 LLVMValueRef args[4];
520
521 args[0] = uint->zero;
522 args[1] = attr_number;
523 args[2] = params;
524 args[3] = interp_param;
525 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
526 build_intrinsic(gallivm->builder, intr_name,
527 input_type, args, args[3] ? 4 : 3,
528 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
529 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
530 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
531 lp_build_const_float(gallivm, 0.0f);
532 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
533 lp_build_const_float(gallivm, 1.0f);
534 } else {
535 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
536 LLVMValueRef args[4];
537 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
538 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
539 args[0] = llvm_chan;
540 args[1] = attr_number;
541 args[2] = params;
542 args[3] = interp_param;
543 radeon_bld->inputs[soa_index] =
544 build_intrinsic(gallivm->builder, intr_name,
545 input_type, args, args[3] ? 4 : 3,
546 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
547 }
548 }
549 }
550
551 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
552 {
553 struct gallivm_state *gallivm = &radeon_bld->gallivm;
554 LLVMValueRef value = LLVMGetParam(radeon_bld->main_fn,
555 SI_PARAM_ANCILLARY);
556 value = LLVMBuildLShr(gallivm->builder, value,
557 lp_build_const_int32(gallivm, 8), "");
558 value = LLVMBuildAnd(gallivm->builder, value,
559 lp_build_const_int32(gallivm, 0xf), "");
560 return value;
561 }
562
563 /**
564 * Load a dword from a constant buffer.
565 */
566 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
567 LLVMValueRef offset, LLVMTypeRef return_type)
568 {
569 LLVMValueRef args[2] = {resource, offset};
570
571 return build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
572 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
573 }
574
575 static void declare_system_value(
576 struct radeon_llvm_context * radeon_bld,
577 unsigned index,
578 const struct tgsi_full_declaration *decl)
579 {
580 struct si_shader_context *si_shader_ctx =
581 si_shader_context(&radeon_bld->soa.bld_base);
582 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
583 struct gallivm_state *gallivm = &radeon_bld->gallivm;
584 LLVMValueRef value = 0;
585
586 switch (decl->Semantic.Name) {
587 case TGSI_SEMANTIC_INSTANCEID:
588 value = LLVMGetParam(radeon_bld->main_fn,
589 si_shader_ctx->param_instance_id);
590 break;
591
592 case TGSI_SEMANTIC_VERTEXID:
593 value = LLVMGetParam(radeon_bld->main_fn,
594 si_shader_ctx->param_vertex_id);
595 break;
596
597 case TGSI_SEMANTIC_SAMPLEID:
598 value = get_sample_id(radeon_bld);
599 break;
600
601 case TGSI_SEMANTIC_SAMPLEPOS:
602 {
603 LLVMBuilderRef builder = gallivm->builder;
604 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
605 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
606 LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
607
608 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
609 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, get_sample_id(radeon_bld), 8);
610 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
611
612 LLVMValueRef pos[4] = {
613 buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
614 buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
615 lp_build_const_float(gallivm, 0),
616 lp_build_const_float(gallivm, 0)
617 };
618 value = lp_build_gather_values(gallivm, pos, 4);
619 break;
620 }
621
622 default:
623 assert(!"unknown system value");
624 return;
625 }
626
627 radeon_bld->system_values[index] = value;
628 }
629
630 static LLVMValueRef fetch_constant(
631 struct lp_build_tgsi_context * bld_base,
632 const struct tgsi_full_src_register *reg,
633 enum tgsi_opcode_type type,
634 unsigned swizzle)
635 {
636 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
637 struct lp_build_context * base = &bld_base->base;
638 const struct tgsi_ind_register *ireg = &reg->Indirect;
639 unsigned buf, idx;
640
641 LLVMValueRef addr;
642 LLVMValueRef result;
643
644 if (swizzle == LP_CHAN_ALL) {
645 unsigned chan;
646 LLVMValueRef values[4];
647 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
648 values[chan] = fetch_constant(bld_base, reg, type, chan);
649
650 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
651 }
652
653 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
654 idx = reg->Register.Index * 4 + swizzle;
655
656 if (!reg->Register.Indirect)
657 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
658
659 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
660 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
661 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
662 addr = lp_build_add(&bld_base->uint_bld, addr,
663 lp_build_const_int32(base->gallivm, idx * 4));
664
665 result = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
666 addr, base->elem_type);
667
668 return bitcast(bld_base, type, result);
669 }
670
671 /* Initialize arguments for the shader export intrinsic */
672 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
673 LLVMValueRef *values,
674 unsigned target,
675 LLVMValueRef *args)
676 {
677 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
678 struct lp_build_context *uint =
679 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
680 struct lp_build_context *base = &bld_base->base;
681 unsigned compressed = 0;
682 unsigned chan;
683
684 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
685 int cbuf = target - V_008DFC_SQ_EXP_MRT;
686
687 if (cbuf >= 0 && cbuf < 8) {
688 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
689
690 if (compressed)
691 si_shader_ctx->shader->spi_shader_col_format |=
692 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
693 else
694 si_shader_ctx->shader->spi_shader_col_format |=
695 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
696
697 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
698 }
699 }
700
701 if (compressed) {
702 /* Pixel shader needs to pack output values before export */
703 for (chan = 0; chan < 2; chan++ ) {
704 args[0] = values[2 * chan];
705 args[1] = values[2 * chan + 1];
706 args[chan + 5] =
707 build_intrinsic(base->gallivm->builder,
708 "llvm.SI.packf16",
709 LLVMInt32TypeInContext(base->gallivm->context),
710 args, 2,
711 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
712 args[chan + 7] = args[chan + 5] =
713 LLVMBuildBitCast(base->gallivm->builder,
714 args[chan + 5],
715 LLVMFloatTypeInContext(base->gallivm->context),
716 "");
717 }
718
719 /* Set COMPR flag */
720 args[4] = uint->one;
721 } else {
722 for (chan = 0; chan < 4; chan++ )
723 /* +5 because the first output value will be
724 * the 6th argument to the intrinsic. */
725 args[chan + 5] = values[chan];
726
727 /* Clear COMPR flag */
728 args[4] = uint->zero;
729 }
730
731 /* XXX: This controls which components of the output
732 * registers actually get exported. (e.g bit 0 means export
733 * X component, bit 1 means export Y component, etc.) I'm
734 * hard coding this to 0xf for now. In the future, we might
735 * want to do something else. */
736 args[0] = lp_build_const_int32(base->gallivm, 0xf);
737
738 /* Specify whether the EXEC mask represents the valid mask */
739 args[1] = uint->zero;
740
741 /* Specify whether this is the last export */
742 args[2] = uint->zero;
743
744 /* Specify the target we are exporting */
745 args[3] = lp_build_const_int32(base->gallivm, target);
746
747 /* XXX: We probably need to keep track of the output
748 * values, so we know what we are passing to the next
749 * stage. */
750 }
751
752 /* Load from output pointers and initialize arguments for the shader export intrinsic */
753 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
754 LLVMValueRef *out_ptr,
755 unsigned target,
756 LLVMValueRef *args)
757 {
758 struct gallivm_state *gallivm = bld_base->base.gallivm;
759 LLVMValueRef values[4];
760 int i;
761
762 for (i = 0; i < 4; i++)
763 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
764
765 si_llvm_init_export_args(bld_base, values, target, args);
766 }
767
768 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
769 LLVMValueRef *out_ptr)
770 {
771 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
772 struct gallivm_state *gallivm = bld_base->base.gallivm;
773
774 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
775 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
776 SI_PARAM_ALPHA_REF);
777
778 LLVMValueRef alpha_pass =
779 lp_build_cmp(&bld_base->base,
780 si_shader_ctx->shader->key.ps.alpha_func,
781 LLVMBuildLoad(gallivm->builder, out_ptr[3], ""),
782 alpha_ref);
783 LLVMValueRef arg =
784 lp_build_select(&bld_base->base,
785 alpha_pass,
786 lp_build_const_float(gallivm, 1.0f),
787 lp_build_const_float(gallivm, -1.0f));
788
789 build_intrinsic(gallivm->builder,
790 "llvm.AMDGPU.kill",
791 LLVMVoidTypeInContext(gallivm->context),
792 &arg, 1, 0);
793 } else {
794 build_intrinsic(gallivm->builder,
795 "llvm.AMDGPU.kilp",
796 LLVMVoidTypeInContext(gallivm->context),
797 NULL, 0, 0);
798 }
799
800 si_shader_ctx->shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
801 }
802
803 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
804 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
805 {
806 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
807 struct lp_build_context *base = &bld_base->base;
808 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
809 unsigned reg_index;
810 unsigned chan;
811 unsigned const_chan;
812 LLVMValueRef base_elt;
813 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
814 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
815 LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
816
817 for (reg_index = 0; reg_index < 2; reg_index ++) {
818 LLVMValueRef *args = pos[2 + reg_index];
819
820 args[5] =
821 args[6] =
822 args[7] =
823 args[8] = lp_build_const_float(base->gallivm, 0.0f);
824
825 /* Compute dot products of position and user clip plane vectors */
826 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
827 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
828 args[1] = lp_build_const_int32(base->gallivm,
829 ((reg_index * 4 + chan) * 4 +
830 const_chan) * 4);
831 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
832 args[1], base->elem_type);
833 args[5 + chan] =
834 lp_build_add(base, args[5 + chan],
835 lp_build_mul(base, base_elt,
836 out_elts[const_chan]));
837 }
838 }
839
840 args[0] = lp_build_const_int32(base->gallivm, 0xf);
841 args[1] = uint->zero;
842 args[2] = uint->zero;
843 args[3] = lp_build_const_int32(base->gallivm,
844 V_008DFC_SQ_EXP_POS + 2 + reg_index);
845 args[4] = uint->zero;
846 }
847 }
848
849 static void si_dump_streamout(struct pipe_stream_output_info *so)
850 {
851 unsigned i;
852
853 if (so->num_outputs)
854 fprintf(stderr, "STREAMOUT\n");
855
856 for (i = 0; i < so->num_outputs; i++) {
857 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
858 so->output[i].start_component;
859 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
860 i, so->output[i].output_buffer,
861 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
862 so->output[i].register_index,
863 mask & 1 ? "x" : "",
864 mask & 2 ? "y" : "",
865 mask & 4 ? "z" : "",
866 mask & 8 ? "w" : "");
867 }
868 }
869
870 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
871 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
872 * or v4i32 (num_channels=3,4). */
873 static void build_tbuffer_store(struct si_shader_context *shader,
874 LLVMValueRef rsrc,
875 LLVMValueRef vdata,
876 unsigned num_channels,
877 LLVMValueRef vaddr,
878 LLVMValueRef soffset,
879 unsigned inst_offset,
880 unsigned dfmt,
881 unsigned nfmt,
882 unsigned offen,
883 unsigned idxen,
884 unsigned glc,
885 unsigned slc,
886 unsigned tfe)
887 {
888 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
889 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
890 LLVMValueRef args[] = {
891 rsrc,
892 vdata,
893 LLVMConstInt(i32, num_channels, 0),
894 vaddr,
895 soffset,
896 LLVMConstInt(i32, inst_offset, 0),
897 LLVMConstInt(i32, dfmt, 0),
898 LLVMConstInt(i32, nfmt, 0),
899 LLVMConstInt(i32, offen, 0),
900 LLVMConstInt(i32, idxen, 0),
901 LLVMConstInt(i32, glc, 0),
902 LLVMConstInt(i32, slc, 0),
903 LLVMConstInt(i32, tfe, 0)
904 };
905
906 /* The instruction offset field has 12 bits */
907 assert(offen || inst_offset < (1 << 12));
908
909 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
910 unsigned func = CLAMP(num_channels, 1, 3) - 1;
911 const char *types[] = {"i32", "v2i32", "v4i32"};
912 char name[256];
913 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
914
915 lp_build_intrinsic(gallivm->builder, name,
916 LLVMVoidTypeInContext(gallivm->context),
917 args, Elements(args));
918 }
919
920 static void build_streamout_store(struct si_shader_context *shader,
921 LLVMValueRef rsrc,
922 LLVMValueRef vdata,
923 unsigned num_channels,
924 LLVMValueRef vaddr,
925 LLVMValueRef soffset,
926 unsigned inst_offset)
927 {
928 static unsigned dfmt[] = {
929 V_008F0C_BUF_DATA_FORMAT_32,
930 V_008F0C_BUF_DATA_FORMAT_32_32,
931 V_008F0C_BUF_DATA_FORMAT_32_32_32,
932 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
933 };
934 assert(num_channels >= 1 && num_channels <= 4);
935
936 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
937 inst_offset, dfmt[num_channels-1],
938 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
939 }
940
941 /* On SI, the vertex shader is responsible for writing streamout data
942 * to buffers. */
943 static void si_llvm_emit_streamout(struct si_shader_context *shader,
944 struct si_shader_output_values *outputs,
945 unsigned noutput)
946 {
947 struct pipe_stream_output_info *so = &shader->shader->selector->so;
948 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
949 LLVMBuilderRef builder = gallivm->builder;
950 int i, j;
951 struct lp_build_if_state if_ctx;
952
953 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
954
955 LLVMValueRef so_param =
956 LLVMGetParam(shader->radeon_bld.main_fn,
957 shader->param_streamout_config);
958
959 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
960 LLVMValueRef so_vtx_count =
961 LLVMBuildAnd(builder,
962 LLVMBuildLShr(builder, so_param,
963 LLVMConstInt(i32, 16, 0), ""),
964 LLVMConstInt(i32, 127, 0), "");
965
966 LLVMValueRef tid = build_intrinsic(builder, "llvm.SI.tid", i32,
967 NULL, 0, LLVMReadNoneAttribute);
968
969 /* can_emit = tid < so_vtx_count; */
970 LLVMValueRef can_emit =
971 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
972
973 /* Emit the streamout code conditionally. This actually avoids
974 * out-of-bounds buffer access. The hw tells us via the SGPR
975 * (so_vtx_count) which threads are allowed to emit streamout data. */
976 lp_build_if(&if_ctx, gallivm, can_emit);
977 {
978 /* The buffer offset is computed as follows:
979 * ByteOffset = streamout_offset[buffer_id]*4 +
980 * (streamout_write_index + thread_id)*stride[buffer_id] +
981 * attrib_offset
982 */
983
984 LLVMValueRef so_write_index =
985 LLVMGetParam(shader->radeon_bld.main_fn,
986 shader->param_streamout_write_index);
987
988 /* Compute (streamout_write_index + thread_id). */
989 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
990
991 /* Compute the write offset for each enabled buffer. */
992 LLVMValueRef so_write_offset[4] = {};
993 for (i = 0; i < 4; i++) {
994 if (!so->stride[i])
995 continue;
996
997 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
998 shader->param_streamout_offset[i]);
999 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1000
1001 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1002 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1003 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1004 }
1005
1006 /* Write streamout data. */
1007 for (i = 0; i < so->num_outputs; i++) {
1008 unsigned buf_idx = so->output[i].output_buffer;
1009 unsigned reg = so->output[i].register_index;
1010 unsigned start = so->output[i].start_component;
1011 unsigned num_comps = so->output[i].num_components;
1012 LLVMValueRef out[4];
1013
1014 assert(num_comps && num_comps <= 4);
1015 if (!num_comps || num_comps > 4)
1016 continue;
1017
1018 if (reg >= noutput)
1019 continue;
1020
1021 /* Load the output as int. */
1022 for (j = 0; j < num_comps; j++) {
1023 out[j] = LLVMBuildBitCast(builder,
1024 outputs[reg].values[start+j],
1025 i32, "");
1026 }
1027
1028 /* Pack the output. */
1029 LLVMValueRef vdata = NULL;
1030
1031 switch (num_comps) {
1032 case 1: /* as i32 */
1033 vdata = out[0];
1034 break;
1035 case 2: /* as v2i32 */
1036 case 3: /* as v4i32 (aligned to 4) */
1037 case 4: /* as v4i32 */
1038 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1039 for (j = 0; j < num_comps; j++) {
1040 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1041 LLVMConstInt(i32, j, 0), "");
1042 }
1043 break;
1044 }
1045
1046 build_streamout_store(shader, shader->so_buffers[buf_idx],
1047 vdata, num_comps,
1048 so_write_offset[buf_idx],
1049 LLVMConstInt(i32, 0, 0),
1050 so->output[i].dst_offset*4);
1051 }
1052 }
1053 lp_build_endif(&if_ctx);
1054 }
1055
1056
1057 /* Generate export instructions for hardware VS shader stage */
1058 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1059 struct si_shader_output_values *outputs,
1060 unsigned noutput)
1061 {
1062 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1063 struct si_shader * shader = si_shader_ctx->shader;
1064 struct lp_build_context * base = &bld_base->base;
1065 struct lp_build_context * uint =
1066 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1067 LLVMValueRef args[9];
1068 LLVMValueRef pos_args[4][9] = { { 0 } };
1069 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL;
1070 unsigned semantic_name, semantic_index;
1071 unsigned target;
1072 unsigned param_count = 0;
1073 unsigned pos_idx;
1074 int i;
1075
1076 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1077 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1078 }
1079
1080 for (i = 0; i < noutput; i++) {
1081 semantic_name = outputs[i].name;
1082 semantic_index = outputs[i].sid;
1083
1084 handle_semantic:
1085 /* Select the correct target */
1086 switch(semantic_name) {
1087 case TGSI_SEMANTIC_PSIZE:
1088 psize_value = outputs[i].values[0];
1089 continue;
1090 case TGSI_SEMANTIC_EDGEFLAG:
1091 edgeflag_value = outputs[i].values[0];
1092 continue;
1093 case TGSI_SEMANTIC_LAYER:
1094 layer_value = outputs[i].values[0];
1095 continue;
1096 case TGSI_SEMANTIC_POSITION:
1097 target = V_008DFC_SQ_EXP_POS;
1098 break;
1099 case TGSI_SEMANTIC_COLOR:
1100 case TGSI_SEMANTIC_BCOLOR:
1101 target = V_008DFC_SQ_EXP_PARAM + param_count;
1102 shader->vs_output_param_offset[i] = param_count;
1103 param_count++;
1104 break;
1105 case TGSI_SEMANTIC_CLIPDIST:
1106 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1107 break;
1108 case TGSI_SEMANTIC_CLIPVERTEX:
1109 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1110 continue;
1111 case TGSI_SEMANTIC_PRIMID:
1112 case TGSI_SEMANTIC_FOG:
1113 case TGSI_SEMANTIC_GENERIC:
1114 target = V_008DFC_SQ_EXP_PARAM + param_count;
1115 shader->vs_output_param_offset[i] = param_count;
1116 param_count++;
1117 break;
1118 default:
1119 target = 0;
1120 fprintf(stderr,
1121 "Warning: SI unhandled vs output type:%d\n",
1122 semantic_name);
1123 }
1124
1125 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1126
1127 if (target >= V_008DFC_SQ_EXP_POS &&
1128 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1129 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1130 args, sizeof(args));
1131 } else {
1132 lp_build_intrinsic(base->gallivm->builder,
1133 "llvm.SI.export",
1134 LLVMVoidTypeInContext(base->gallivm->context),
1135 args, 9);
1136 }
1137
1138 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1139 semantic_name = TGSI_SEMANTIC_GENERIC;
1140 goto handle_semantic;
1141 }
1142 }
1143
1144 /* We need to add the position output manually if it's missing. */
1145 if (!pos_args[0][0]) {
1146 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1147 pos_args[0][1] = uint->zero; /* EXEC mask */
1148 pos_args[0][2] = uint->zero; /* last export? */
1149 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1150 pos_args[0][4] = uint->zero; /* COMPR flag */
1151 pos_args[0][5] = base->zero; /* X */
1152 pos_args[0][6] = base->zero; /* Y */
1153 pos_args[0][7] = base->zero; /* Z */
1154 pos_args[0][8] = base->one; /* W */
1155 }
1156
1157 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1158 if (shader->selector->info.writes_psize ||
1159 shader->selector->info.writes_edgeflag ||
1160 shader->selector->info.writes_layer) {
1161 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1162 shader->selector->info.writes_psize |
1163 (shader->selector->info.writes_edgeflag << 1) |
1164 (shader->selector->info.writes_layer << 2));
1165 pos_args[1][1] = uint->zero; /* EXEC mask */
1166 pos_args[1][2] = uint->zero; /* last export? */
1167 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1168 pos_args[1][4] = uint->zero; /* COMPR flag */
1169 pos_args[1][5] = base->zero; /* X */
1170 pos_args[1][6] = base->zero; /* Y */
1171 pos_args[1][7] = base->zero; /* Z */
1172 pos_args[1][8] = base->zero; /* W */
1173
1174 if (shader->selector->info.writes_psize)
1175 pos_args[1][5] = psize_value;
1176
1177 if (shader->selector->info.writes_edgeflag) {
1178 /* The output is a float, but the hw expects an integer
1179 * with the first bit containing the edge flag. */
1180 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1181 edgeflag_value,
1182 bld_base->uint_bld.elem_type, "");
1183 edgeflag_value = lp_build_min(&bld_base->int_bld,
1184 edgeflag_value,
1185 bld_base->int_bld.one);
1186
1187 /* The LLVM intrinsic expects a float. */
1188 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1189 edgeflag_value,
1190 base->elem_type, "");
1191 }
1192
1193 if (shader->selector->info.writes_layer)
1194 pos_args[1][7] = layer_value;
1195 }
1196
1197 for (i = 0; i < 4; i++)
1198 if (pos_args[i][0])
1199 shader->nr_pos_exports++;
1200
1201 pos_idx = 0;
1202 for (i = 0; i < 4; i++) {
1203 if (!pos_args[i][0])
1204 continue;
1205
1206 /* Specify the target we are exporting */
1207 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1208
1209 if (pos_idx == shader->nr_pos_exports)
1210 /* Specify that this is the last export */
1211 pos_args[i][2] = uint->one;
1212
1213 lp_build_intrinsic(base->gallivm->builder,
1214 "llvm.SI.export",
1215 LLVMVoidTypeInContext(base->gallivm->context),
1216 pos_args[i], 9);
1217 }
1218 }
1219
1220 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1221 {
1222 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1223 struct gallivm_state *gallivm = bld_base->base.gallivm;
1224 struct si_shader *es = si_shader_ctx->shader;
1225 struct tgsi_shader_info *info = &es->selector->info;
1226 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1227 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1228 SI_PARAM_ES2GS_OFFSET);
1229 unsigned chan;
1230 int i;
1231
1232 for (i = 0; i < info->num_outputs; i++) {
1233 LLVMValueRef *out_ptr =
1234 si_shader_ctx->radeon_bld.soa.outputs[i];
1235 int param_index = get_param_index(info->output_semantic_name[i],
1236 info->output_semantic_index[i],
1237 es->key.vs.gs_used_inputs);
1238
1239 if (param_index < 0)
1240 continue;
1241
1242 for (chan = 0; chan < 4; chan++) {
1243 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1244 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1245
1246 build_tbuffer_store(si_shader_ctx,
1247 si_shader_ctx->esgs_ring,
1248 out_val, 1,
1249 LLVMGetUndef(i32), soffset,
1250 (4 * param_index + chan) * 4,
1251 V_008F0C_BUF_DATA_FORMAT_32,
1252 V_008F0C_BUF_NUM_FORMAT_UINT,
1253 0, 0, 1, 1, 0);
1254 }
1255 }
1256 }
1257
1258 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
1259 {
1260 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1261 struct gallivm_state *gallivm = bld_base->base.gallivm;
1262 LLVMValueRef args[2];
1263
1264 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
1265 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1266 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1267 LLVMVoidTypeInContext(gallivm->context), args, 2,
1268 LLVMNoUnwindAttribute);
1269 }
1270
1271 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
1272 {
1273 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1274 struct gallivm_state *gallivm = bld_base->base.gallivm;
1275 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
1276 struct si_shader_output_values *outputs = NULL;
1277 int i,j;
1278
1279 outputs = MALLOC(info->num_outputs * sizeof(outputs[0]));
1280
1281 for (i = 0; i < info->num_outputs; i++) {
1282 outputs[i].name = info->output_semantic_name[i];
1283 outputs[i].sid = info->output_semantic_index[i];
1284
1285 for (j = 0; j < 4; j++)
1286 outputs[i].values[j] =
1287 LLVMBuildLoad(gallivm->builder,
1288 si_shader_ctx->radeon_bld.soa.outputs[i][j],
1289 "");
1290 }
1291
1292 si_llvm_export_vs(bld_base, outputs, info->num_outputs);
1293 FREE(outputs);
1294 }
1295
1296 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
1297 {
1298 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1299 struct si_shader * shader = si_shader_ctx->shader;
1300 struct lp_build_context * base = &bld_base->base;
1301 struct lp_build_context * uint = &bld_base->uint_bld;
1302 struct tgsi_shader_info *info = &shader->selector->info;
1303 LLVMValueRef args[9];
1304 LLVMValueRef last_args[9] = { 0 };
1305 int depth_index = -1, stencil_index = -1, samplemask_index = -1;
1306 int i;
1307
1308 for (i = 0; i < info->num_outputs; i++) {
1309 unsigned semantic_name = info->output_semantic_name[i];
1310 unsigned semantic_index = info->output_semantic_index[i];
1311 unsigned target;
1312
1313 /* Select the correct target */
1314 switch (semantic_name) {
1315 case TGSI_SEMANTIC_POSITION:
1316 depth_index = i;
1317 continue;
1318 case TGSI_SEMANTIC_STENCIL:
1319 stencil_index = i;
1320 continue;
1321 case TGSI_SEMANTIC_SAMPLEMASK:
1322 samplemask_index = i;
1323 continue;
1324 case TGSI_SEMANTIC_COLOR:
1325 target = V_008DFC_SQ_EXP_MRT + semantic_index;
1326 if (si_shader_ctx->shader->key.ps.alpha_to_one)
1327 LLVMBuildStore(bld_base->base.gallivm->builder,
1328 bld_base->base.one,
1329 si_shader_ctx->radeon_bld.soa.outputs[i][3]);
1330
1331 if (semantic_index == 0 &&
1332 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
1333 si_alpha_test(bld_base,
1334 si_shader_ctx->radeon_bld.soa.outputs[i]);
1335 break;
1336 default:
1337 target = 0;
1338 fprintf(stderr,
1339 "Warning: SI unhandled fs output type:%d\n",
1340 semantic_name);
1341 }
1342
1343 si_llvm_init_export_args_load(bld_base,
1344 si_shader_ctx->radeon_bld.soa.outputs[i],
1345 target, args);
1346
1347 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1348 /* If there is an export instruction waiting to be emitted, do so now. */
1349 if (last_args[0]) {
1350 lp_build_intrinsic(base->gallivm->builder,
1351 "llvm.SI.export",
1352 LLVMVoidTypeInContext(base->gallivm->context),
1353 last_args, 9);
1354 }
1355
1356 /* This instruction will be emitted at the end of the shader. */
1357 memcpy(last_args, args, sizeof(args));
1358
1359 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
1360 if (shader->selector->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1361 semantic_index == 0 &&
1362 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
1363 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
1364 si_llvm_init_export_args_load(bld_base,
1365 si_shader_ctx->radeon_bld.soa.outputs[i],
1366 V_008DFC_SQ_EXP_MRT + c, args);
1367 lp_build_intrinsic(base->gallivm->builder,
1368 "llvm.SI.export",
1369 LLVMVoidTypeInContext(base->gallivm->context),
1370 args, 9);
1371 }
1372 }
1373 } else {
1374 lp_build_intrinsic(base->gallivm->builder,
1375 "llvm.SI.export",
1376 LLVMVoidTypeInContext(base->gallivm->context),
1377 args, 9);
1378 }
1379 }
1380
1381 if (depth_index >= 0 || stencil_index >= 0 || samplemask_index >= 0) {
1382 LLVMValueRef out_ptr;
1383 unsigned mask = 0;
1384
1385 /* Specify the target we are exporting */
1386 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
1387
1388 args[5] = base->zero; /* R, depth */
1389 args[6] = base->zero; /* G, stencil test value[0:7], stencil op value[8:15] */
1390 args[7] = base->zero; /* B, sample mask */
1391 args[8] = base->zero; /* A, alpha to mask */
1392
1393 if (depth_index >= 0) {
1394 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
1395 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1396 mask |= 0x1;
1397 si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1398 }
1399
1400 if (stencil_index >= 0) {
1401 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
1402 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1403 /* Only setting the stencil component bit (0x2) here
1404 * breaks some stencil piglit tests
1405 */
1406 mask |= 0x3;
1407 si_shader_ctx->shader->db_shader_control |=
1408 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
1409 }
1410
1411 if (samplemask_index >= 0) {
1412 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[samplemask_index][0];
1413 args[7] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1414 mask |= 0xf; /* Set all components. */
1415 si_shader_ctx->shader->db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(1);
1416 }
1417
1418 if (samplemask_index >= 0)
1419 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
1420 else if (stencil_index >= 0)
1421 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
1422 else
1423 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
1424
1425 /* Specify which components to enable */
1426 args[0] = lp_build_const_int32(base->gallivm, mask);
1427
1428 args[1] =
1429 args[2] =
1430 args[4] = uint->zero;
1431
1432 if (last_args[0])
1433 lp_build_intrinsic(base->gallivm->builder,
1434 "llvm.SI.export",
1435 LLVMVoidTypeInContext(base->gallivm->context),
1436 args, 9);
1437 else
1438 memcpy(last_args, args, sizeof(args));
1439 }
1440
1441 if (!last_args[0]) {
1442 /* Specify which components to enable */
1443 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
1444
1445 /* Specify the target we are exporting */
1446 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
1447
1448 /* Set COMPR flag to zero to export data as 32-bit */
1449 last_args[4] = uint->zero;
1450
1451 /* dummy bits */
1452 last_args[5]= uint->zero;
1453 last_args[6]= uint->zero;
1454 last_args[7]= uint->zero;
1455 last_args[8]= uint->zero;
1456 }
1457
1458 /* Specify whether the EXEC mask represents the valid mask */
1459 last_args[1] = uint->one;
1460
1461 /* Specify that this is the last export */
1462 last_args[2] = lp_build_const_int32(base->gallivm, 1);
1463
1464 lp_build_intrinsic(base->gallivm->builder,
1465 "llvm.SI.export",
1466 LLVMVoidTypeInContext(base->gallivm->context),
1467 last_args, 9);
1468 }
1469
1470 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1471 struct lp_build_tgsi_context * bld_base,
1472 struct lp_build_emit_data * emit_data);
1473
1474 static bool tgsi_is_shadow_sampler(unsigned target)
1475 {
1476 return target == TGSI_TEXTURE_SHADOW1D ||
1477 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1478 target == TGSI_TEXTURE_SHADOW2D ||
1479 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1480 target == TGSI_TEXTURE_SHADOWCUBE ||
1481 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
1482 target == TGSI_TEXTURE_SHADOWRECT;
1483 }
1484
1485 static const struct lp_build_tgsi_action tex_action;
1486
1487 static void tex_fetch_args(
1488 struct lp_build_tgsi_context * bld_base,
1489 struct lp_build_emit_data * emit_data)
1490 {
1491 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1492 struct gallivm_state *gallivm = bld_base->base.gallivm;
1493 const struct tgsi_full_instruction * inst = emit_data->inst;
1494 unsigned opcode = inst->Instruction.Opcode;
1495 unsigned target = inst->Texture.Texture;
1496 LLVMValueRef coords[4];
1497 LLVMValueRef address[16];
1498 int ref_pos;
1499 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
1500 unsigned count = 0;
1501 unsigned chan;
1502 unsigned sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1503 unsigned sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
1504 bool has_offset = HAVE_LLVM >= 0x0305 ? inst->Texture.NumOffsets > 0 : false;
1505
1506 if (target == TGSI_TEXTURE_BUFFER) {
1507 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
1508 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
1509 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
1510 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
1511
1512 /* Bitcast and truncate v8i32 to v16i8. */
1513 LLVMValueRef res = si_shader_ctx->resources[sampler_index];
1514 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
1515 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.zero, "");
1516 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
1517
1518 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
1519 emit_data->args[0] = res;
1520 emit_data->args[1] = bld_base->uint_bld.zero;
1521 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
1522 emit_data->arg_count = 3;
1523 return;
1524 }
1525
1526 /* Fetch and project texture coordinates */
1527 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1528 for (chan = 0; chan < 3; chan++ ) {
1529 coords[chan] = lp_build_emit_fetch(bld_base,
1530 emit_data->inst, 0,
1531 chan);
1532 if (opcode == TGSI_OPCODE_TXP)
1533 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1534 TGSI_OPCODE_DIV,
1535 coords[chan],
1536 coords[3]);
1537 }
1538
1539 if (opcode == TGSI_OPCODE_TXP)
1540 coords[3] = bld_base->base.one;
1541
1542 /* Pack offsets. */
1543 if (has_offset && opcode != TGSI_OPCODE_TXF) {
1544 /* The offsets are six-bit signed integers packed like this:
1545 * X=[5:0], Y=[13:8], and Z=[21:16].
1546 */
1547 LLVMValueRef offset[3], pack;
1548
1549 assert(inst->Texture.NumOffsets == 1);
1550
1551 for (chan = 0; chan < 3; chan++) {
1552 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
1553 emit_data->inst, 0, chan);
1554 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
1555 lp_build_const_int32(gallivm, 0x3f), "");
1556 if (chan)
1557 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
1558 lp_build_const_int32(gallivm, chan*8), "");
1559 }
1560
1561 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
1562 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
1563 address[count++] = pack;
1564 }
1565
1566 /* Pack LOD bias value */
1567 if (opcode == TGSI_OPCODE_TXB)
1568 address[count++] = coords[3];
1569 if (opcode == TGSI_OPCODE_TXB2)
1570 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1571
1572 /* Pack depth comparison value */
1573 if (tgsi_is_shadow_sampler(target) && opcode != TGSI_OPCODE_LODQ) {
1574 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1575 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1576 } else {
1577 assert(ref_pos >= 0);
1578 address[count++] = coords[ref_pos];
1579 }
1580 }
1581
1582 if (target == TGSI_TEXTURE_CUBE ||
1583 target == TGSI_TEXTURE_CUBE_ARRAY ||
1584 target == TGSI_TEXTURE_SHADOWCUBE ||
1585 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1586 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
1587
1588 /* Pack user derivatives */
1589 if (opcode == TGSI_OPCODE_TXD) {
1590 int num_deriv_channels, param;
1591
1592 switch (target) {
1593 case TGSI_TEXTURE_3D:
1594 num_deriv_channels = 3;
1595 break;
1596 case TGSI_TEXTURE_2D:
1597 case TGSI_TEXTURE_SHADOW2D:
1598 case TGSI_TEXTURE_RECT:
1599 case TGSI_TEXTURE_SHADOWRECT:
1600 case TGSI_TEXTURE_2D_ARRAY:
1601 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1602 case TGSI_TEXTURE_CUBE:
1603 case TGSI_TEXTURE_SHADOWCUBE:
1604 case TGSI_TEXTURE_CUBE_ARRAY:
1605 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1606 num_deriv_channels = 2;
1607 break;
1608 case TGSI_TEXTURE_1D:
1609 case TGSI_TEXTURE_SHADOW1D:
1610 case TGSI_TEXTURE_1D_ARRAY:
1611 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1612 num_deriv_channels = 1;
1613 break;
1614 default:
1615 assert(0); /* no other targets are valid here */
1616 }
1617
1618 for (param = 1; param <= 2; param++)
1619 for (chan = 0; chan < num_deriv_channels; chan++)
1620 address[count++] = lp_build_emit_fetch(bld_base, inst, param, chan);
1621 }
1622
1623 /* Pack texture coordinates */
1624 address[count++] = coords[0];
1625 if (num_coords > 1)
1626 address[count++] = coords[1];
1627 if (num_coords > 2)
1628 address[count++] = coords[2];
1629
1630 /* Pack LOD or sample index */
1631 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1632 address[count++] = coords[3];
1633 else if (opcode == TGSI_OPCODE_TXL2)
1634 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1635
1636 if (count > 16) {
1637 assert(!"Cannot handle more than 16 texture address parameters");
1638 count = 16;
1639 }
1640
1641 for (chan = 0; chan < count; chan++ ) {
1642 address[chan] = LLVMBuildBitCast(gallivm->builder,
1643 address[chan],
1644 LLVMInt32TypeInContext(gallivm->context),
1645 "");
1646 }
1647
1648 /* Adjust the sample index according to FMASK.
1649 *
1650 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1651 * which is the identity mapping. Each nibble says which physical sample
1652 * should be fetched to get that sample.
1653 *
1654 * For example, 0x11111100 means there are only 2 samples stored and
1655 * the second sample covers 3/4 of the pixel. When reading samples 0
1656 * and 1, return physical sample 0 (determined by the first two 0s
1657 * in FMASK), otherwise return physical sample 1.
1658 *
1659 * The sample index should be adjusted as follows:
1660 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1661 */
1662 if (target == TGSI_TEXTURE_2D_MSAA ||
1663 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1664 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1665 struct lp_build_emit_data txf_emit_data = *emit_data;
1666 LLVMValueRef txf_address[4];
1667 unsigned txf_count = count;
1668 struct tgsi_full_instruction inst = {};
1669
1670 memcpy(txf_address, address, sizeof(txf_address));
1671
1672 if (target == TGSI_TEXTURE_2D_MSAA) {
1673 txf_address[2] = bld_base->uint_bld.zero;
1674 }
1675 txf_address[3] = bld_base->uint_bld.zero;
1676
1677 /* Pad to a power-of-two size. */
1678 while (txf_count < util_next_power_of_two(txf_count))
1679 txf_address[txf_count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1680
1681 /* Read FMASK using TXF. */
1682 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
1683 inst.Texture.Texture = target == TGSI_TEXTURE_2D_MSAA ? TGSI_TEXTURE_2D : TGSI_TEXTURE_2D_ARRAY;
1684 txf_emit_data.inst = &inst;
1685 txf_emit_data.chan = 0;
1686 txf_emit_data.dst_type = LLVMVectorType(
1687 LLVMInt32TypeInContext(gallivm->context), 4);
1688 txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
1689 txf_emit_data.args[1] = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
1690 txf_emit_data.args[2] = lp_build_const_int32(gallivm, inst.Texture.Texture);
1691 txf_emit_data.arg_count = 3;
1692
1693 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
1694
1695 /* Initialize some constants. */
1696 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
1697 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
1698
1699 /* Apply the formula. */
1700 LLVMValueRef fmask =
1701 LLVMBuildExtractElement(gallivm->builder,
1702 txf_emit_data.output[0],
1703 uint_bld->zero, "");
1704
1705 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1706
1707 LLVMValueRef sample_index4 =
1708 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1709
1710 LLVMValueRef shifted_fmask =
1711 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1712
1713 LLVMValueRef final_sample =
1714 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1715
1716 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1717 * resource descriptor is 0 (invalid),
1718 */
1719 LLVMValueRef fmask_desc =
1720 LLVMBuildBitCast(gallivm->builder,
1721 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index],
1722 LLVMVectorType(uint_bld->elem_type, 8), "");
1723
1724 LLVMValueRef fmask_word1 =
1725 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1726 uint_bld->one, "");
1727
1728 LLVMValueRef word1_is_nonzero =
1729 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1730 fmask_word1, uint_bld->zero, "");
1731
1732 /* Replace the MSAA sample index. */
1733 address[sample_chan] =
1734 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1735 final_sample, address[sample_chan], "");
1736 }
1737
1738 /* Resource */
1739 emit_data->args[1] = si_shader_ctx->resources[sampler_index];
1740
1741 if (opcode == TGSI_OPCODE_TXF) {
1742 /* add tex offsets */
1743 if (inst->Texture.NumOffsets) {
1744 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1745 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
1746 const struct tgsi_texture_offset * off = inst->TexOffsets;
1747
1748 assert(inst->Texture.NumOffsets == 1);
1749
1750 switch (target) {
1751 case TGSI_TEXTURE_3D:
1752 address[2] = lp_build_add(uint_bld, address[2],
1753 bld->immediates[off->Index][off->SwizzleZ]);
1754 /* fall through */
1755 case TGSI_TEXTURE_2D:
1756 case TGSI_TEXTURE_SHADOW2D:
1757 case TGSI_TEXTURE_RECT:
1758 case TGSI_TEXTURE_SHADOWRECT:
1759 case TGSI_TEXTURE_2D_ARRAY:
1760 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1761 address[1] =
1762 lp_build_add(uint_bld, address[1],
1763 bld->immediates[off->Index][off->SwizzleY]);
1764 /* fall through */
1765 case TGSI_TEXTURE_1D:
1766 case TGSI_TEXTURE_SHADOW1D:
1767 case TGSI_TEXTURE_1D_ARRAY:
1768 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1769 address[0] =
1770 lp_build_add(uint_bld, address[0],
1771 bld->immediates[off->Index][off->SwizzleX]);
1772 break;
1773 /* texture offsets do not apply to other texture targets */
1774 }
1775 }
1776
1777 emit_data->args[2] = lp_build_const_int32(gallivm, target);
1778 emit_data->arg_count = 3;
1779
1780 emit_data->dst_type = LLVMVectorType(
1781 LLVMInt32TypeInContext(gallivm->context),
1782 4);
1783 } else if (opcode == TGSI_OPCODE_TG4 ||
1784 opcode == TGSI_OPCODE_LODQ ||
1785 has_offset) {
1786 unsigned is_array = target == TGSI_TEXTURE_1D_ARRAY ||
1787 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1788 target == TGSI_TEXTURE_2D_ARRAY ||
1789 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1790 target == TGSI_TEXTURE_CUBE_ARRAY ||
1791 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY;
1792 unsigned is_rect = target == TGSI_TEXTURE_RECT;
1793 unsigned dmask = 0xf;
1794
1795 if (opcode == TGSI_OPCODE_TG4) {
1796 unsigned gather_comp = 0;
1797
1798 /* DMASK was repurposed for GATHER4. 4 components are always
1799 * returned and DMASK works like a swizzle - it selects
1800 * the component to fetch. The only valid DMASK values are
1801 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1802 * (red,red,red,red) etc.) The ISA document doesn't mention
1803 * this.
1804 */
1805
1806 /* Get the component index from src1.x for Gather4. */
1807 if (!tgsi_is_shadow_sampler(target)) {
1808 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
1809 LLVMValueRef comp_imm;
1810 struct tgsi_src_register src1 = inst->Src[1].Register;
1811
1812 assert(src1.File == TGSI_FILE_IMMEDIATE);
1813
1814 comp_imm = imms[src1.Index][src1.SwizzleX];
1815 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1816 gather_comp = CLAMP(gather_comp, 0, 3);
1817 }
1818
1819 dmask = 1 << gather_comp;
1820 }
1821
1822 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1823 emit_data->args[3] = lp_build_const_int32(gallivm, dmask);
1824 emit_data->args[4] = lp_build_const_int32(gallivm, is_rect); /* unorm */
1825 emit_data->args[5] = lp_build_const_int32(gallivm, 0); /* r128 */
1826 emit_data->args[6] = lp_build_const_int32(gallivm, is_array); /* da */
1827 emit_data->args[7] = lp_build_const_int32(gallivm, 0); /* glc */
1828 emit_data->args[8] = lp_build_const_int32(gallivm, 0); /* slc */
1829 emit_data->args[9] = lp_build_const_int32(gallivm, 0); /* tfe */
1830 emit_data->args[10] = lp_build_const_int32(gallivm, 0); /* lwe */
1831
1832 emit_data->arg_count = 11;
1833
1834 emit_data->dst_type = LLVMVectorType(
1835 LLVMFloatTypeInContext(gallivm->context),
1836 4);
1837 } else {
1838 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1839 emit_data->args[3] = lp_build_const_int32(gallivm, target);
1840 emit_data->arg_count = 4;
1841
1842 emit_data->dst_type = LLVMVectorType(
1843 LLVMFloatTypeInContext(gallivm->context),
1844 4);
1845 }
1846
1847 /* The fetch opcode has been converted to a 2D array fetch.
1848 * This simplifies the LLVM backend. */
1849 if (target == TGSI_TEXTURE_CUBE_ARRAY)
1850 target = TGSI_TEXTURE_2D_ARRAY;
1851 else if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1852 target = TGSI_TEXTURE_SHADOW2D_ARRAY;
1853
1854 /* Pad to power of two vector */
1855 while (count < util_next_power_of_two(count))
1856 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1857
1858 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
1859 }
1860
1861 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1862 struct lp_build_tgsi_context * bld_base,
1863 struct lp_build_emit_data * emit_data)
1864 {
1865 struct lp_build_context * base = &bld_base->base;
1866 unsigned opcode = emit_data->inst->Instruction.Opcode;
1867 unsigned target = emit_data->inst->Texture.Texture;
1868 char intr_name[127];
1869 bool has_offset = HAVE_LLVM >= 0x0305 ?
1870 emit_data->inst->Texture.NumOffsets > 0 : false;
1871
1872 if (target == TGSI_TEXTURE_BUFFER) {
1873 emit_data->output[emit_data->chan] = build_intrinsic(
1874 base->gallivm->builder,
1875 "llvm.SI.vs.load.input", emit_data->dst_type,
1876 emit_data->args, emit_data->arg_count,
1877 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1878 return;
1879 }
1880
1881 if (opcode == TGSI_OPCODE_TG4 ||
1882 opcode == TGSI_OPCODE_LODQ ||
1883 (opcode != TGSI_OPCODE_TXF && has_offset)) {
1884 bool is_shadow = tgsi_is_shadow_sampler(target);
1885 const char *name = "llvm.SI.image.sample";
1886 const char *infix = "";
1887
1888 switch (opcode) {
1889 case TGSI_OPCODE_TEX:
1890 case TGSI_OPCODE_TEX2:
1891 case TGSI_OPCODE_TXP:
1892 break;
1893 case TGSI_OPCODE_TXB:
1894 case TGSI_OPCODE_TXB2:
1895 infix = ".b";
1896 break;
1897 case TGSI_OPCODE_TXL:
1898 case TGSI_OPCODE_TXL2:
1899 infix = ".l";
1900 break;
1901 case TGSI_OPCODE_TXD:
1902 infix = ".d";
1903 break;
1904 case TGSI_OPCODE_TG4:
1905 name = "llvm.SI.gather4";
1906 break;
1907 case TGSI_OPCODE_LODQ:
1908 name = "llvm.SI.getlod";
1909 is_shadow = false;
1910 has_offset = false;
1911 break;
1912 default:
1913 assert(0);
1914 return;
1915 }
1916
1917 /* Add the type and suffixes .c, .o if needed. */
1918 sprintf(intr_name, "%s%s%s%s.v%ui32", name,
1919 is_shadow ? ".c" : "", infix, has_offset ? ".o" : "",
1920 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
1921
1922 emit_data->output[emit_data->chan] = build_intrinsic(
1923 base->gallivm->builder, intr_name, emit_data->dst_type,
1924 emit_data->args, emit_data->arg_count,
1925 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1926 } else {
1927 LLVMTypeRef i8, v16i8, v32i8;
1928 const char *name;
1929
1930 switch (opcode) {
1931 case TGSI_OPCODE_TEX:
1932 case TGSI_OPCODE_TEX2:
1933 case TGSI_OPCODE_TXP:
1934 name = "llvm.SI.sample";
1935 break;
1936 case TGSI_OPCODE_TXB:
1937 case TGSI_OPCODE_TXB2:
1938 name = "llvm.SI.sampleb";
1939 break;
1940 case TGSI_OPCODE_TXD:
1941 name = "llvm.SI.sampled";
1942 break;
1943 case TGSI_OPCODE_TXF:
1944 name = "llvm.SI.imageload";
1945 break;
1946 case TGSI_OPCODE_TXL:
1947 case TGSI_OPCODE_TXL2:
1948 name = "llvm.SI.samplel";
1949 break;
1950 default:
1951 assert(0);
1952 return;
1953 }
1954
1955 i8 = LLVMInt8TypeInContext(base->gallivm->context);
1956 v16i8 = LLVMVectorType(i8, 16);
1957 v32i8 = LLVMVectorType(i8, 32);
1958
1959 emit_data->args[1] = LLVMBuildBitCast(base->gallivm->builder,
1960 emit_data->args[1], v32i8, "");
1961 if (opcode != TGSI_OPCODE_TXF) {
1962 emit_data->args[2] = LLVMBuildBitCast(base->gallivm->builder,
1963 emit_data->args[2], v16i8, "");
1964 }
1965
1966 sprintf(intr_name, "%s.v%ui32", name,
1967 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
1968
1969 emit_data->output[emit_data->chan] = build_intrinsic(
1970 base->gallivm->builder, intr_name, emit_data->dst_type,
1971 emit_data->args, emit_data->arg_count,
1972 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1973 }
1974 }
1975
1976 static void txq_fetch_args(
1977 struct lp_build_tgsi_context * bld_base,
1978 struct lp_build_emit_data * emit_data)
1979 {
1980 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1981 const struct tgsi_full_instruction *inst = emit_data->inst;
1982 struct gallivm_state *gallivm = bld_base->base.gallivm;
1983 unsigned target = inst->Texture.Texture;
1984
1985 if (target == TGSI_TEXTURE_BUFFER) {
1986 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1987 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
1988
1989 /* Read the size from the buffer descriptor directly. */
1990 LLVMValueRef size = si_shader_ctx->resources[inst->Src[1].Register.Index];
1991 size = LLVMBuildBitCast(gallivm->builder, size, v8i32, "");
1992 size = LLVMBuildExtractElement(gallivm->builder, size,
1993 lp_build_const_int32(gallivm, 2), "");
1994 emit_data->args[0] = size;
1995 return;
1996 }
1997
1998 /* Mip level */
1999 emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2000
2001 /* Resource */
2002 emit_data->args[1] = si_shader_ctx->resources[inst->Src[1].Register.Index];
2003
2004 /* Texture target */
2005 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2006 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2007 target = TGSI_TEXTURE_2D_ARRAY;
2008
2009 emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
2010 target);
2011
2012 emit_data->arg_count = 3;
2013
2014 emit_data->dst_type = LLVMVectorType(
2015 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
2016 4);
2017 }
2018
2019 static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
2020 struct lp_build_tgsi_context * bld_base,
2021 struct lp_build_emit_data * emit_data)
2022 {
2023 unsigned target = emit_data->inst->Texture.Texture;
2024
2025 if (target == TGSI_TEXTURE_BUFFER) {
2026 /* Just return the buffer size. */
2027 emit_data->output[emit_data->chan] = emit_data->args[0];
2028 return;
2029 }
2030
2031 build_tgsi_intrinsic_nomem(action, bld_base, emit_data);
2032
2033 /* Divide the number of layers by 6 to get the number of cubes. */
2034 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2035 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2036 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2037 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2038 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2039
2040 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2041 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2042 z = LLVMBuildSDiv(builder, z, six, "");
2043
2044 emit_data->output[emit_data->chan] =
2045 LLVMBuildInsertElement(builder, v4, z, two, "");
2046 }
2047 }
2048
2049 static void si_llvm_emit_ddxy(
2050 const struct lp_build_tgsi_action * action,
2051 struct lp_build_tgsi_context * bld_base,
2052 struct lp_build_emit_data * emit_data)
2053 {
2054 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2055 struct gallivm_state *gallivm = bld_base->base.gallivm;
2056 struct lp_build_context * base = &bld_base->base;
2057 const struct tgsi_full_instruction *inst = emit_data->inst;
2058 unsigned opcode = inst->Instruction.Opcode;
2059 LLVMValueRef indices[2];
2060 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2061 LLVMValueRef tl, trbl, result[4];
2062 LLVMTypeRef i32;
2063 unsigned swizzle[4];
2064 unsigned c;
2065
2066 i32 = LLVMInt32TypeInContext(gallivm->context);
2067
2068 indices[0] = bld_base->uint_bld.zero;
2069 indices[1] = build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2070 NULL, 0, LLVMReadNoneAttribute);
2071 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2072 indices, 2, "");
2073
2074 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2075 lp_build_const_int32(gallivm, 0xfffffffc), "");
2076 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2077 indices, 2, "");
2078
2079 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
2080 lp_build_const_int32(gallivm,
2081 opcode == TGSI_OPCODE_DDX ? 1 : 2),
2082 "");
2083 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2084 indices, 2, "");
2085
2086 for (c = 0; c < 4; ++c) {
2087 unsigned i;
2088
2089 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
2090 for (i = 0; i < c; ++i) {
2091 if (swizzle[i] == swizzle[c]) {
2092 result[c] = result[i];
2093 break;
2094 }
2095 }
2096 if (i != c)
2097 continue;
2098
2099 LLVMBuildStore(gallivm->builder,
2100 LLVMBuildBitCast(gallivm->builder,
2101 lp_build_emit_fetch(bld_base, inst, 0, c),
2102 i32, ""),
2103 store_ptr);
2104
2105 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
2106 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
2107
2108 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
2109 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
2110
2111 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
2112 }
2113
2114 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
2115 }
2116
2117 /* Emit one vertex from the geometry shader */
2118 static void si_llvm_emit_vertex(
2119 const struct lp_build_tgsi_action *action,
2120 struct lp_build_tgsi_context *bld_base,
2121 struct lp_build_emit_data *emit_data)
2122 {
2123 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2124 struct lp_build_context *uint = &bld_base->uint_bld;
2125 struct si_shader *shader = si_shader_ctx->shader;
2126 struct tgsi_shader_info *info = &shader->selector->info;
2127 struct gallivm_state *gallivm = bld_base->base.gallivm;
2128 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2129 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2130 SI_PARAM_GS2VS_OFFSET);
2131 LLVMValueRef gs_next_vertex;
2132 LLVMValueRef can_emit, kill;
2133 LLVMValueRef args[2];
2134 unsigned chan;
2135 int i;
2136
2137 /* Write vertex attribute values to GSVS ring */
2138 gs_next_vertex = LLVMBuildLoad(gallivm->builder, si_shader_ctx->gs_next_vertex, "");
2139
2140 /* If this thread has already emitted the declared maximum number of
2141 * vertices, kill it: excessive vertex emissions are not supposed to
2142 * have any effect, and GS threads have no externally observable
2143 * effects other than emitting vertices.
2144 */
2145 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
2146 lp_build_const_int32(gallivm,
2147 shader->selector->gs_max_out_vertices), "");
2148 kill = lp_build_select(&bld_base->base, can_emit,
2149 lp_build_const_float(gallivm, 1.0f),
2150 lp_build_const_float(gallivm, -1.0f));
2151 build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2152 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
2153
2154 for (i = 0; i < info->num_outputs; i++) {
2155 LLVMValueRef *out_ptr =
2156 si_shader_ctx->radeon_bld.soa.outputs[i];
2157
2158 for (chan = 0; chan < 4; chan++) {
2159 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2160 LLVMValueRef voffset =
2161 lp_build_const_int32(gallivm, (i * 4 + chan) *
2162 shader->selector->gs_max_out_vertices);
2163
2164 voffset = lp_build_add(uint, voffset, gs_next_vertex);
2165 voffset = lp_build_mul_imm(uint, voffset, 4);
2166
2167 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2168
2169 build_tbuffer_store(si_shader_ctx,
2170 si_shader_ctx->gsvs_ring,
2171 out_val, 1,
2172 voffset, soffset, 0,
2173 V_008F0C_BUF_DATA_FORMAT_32,
2174 V_008F0C_BUF_NUM_FORMAT_UINT,
2175 1, 0, 1, 1, 0);
2176 }
2177 }
2178 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
2179 lp_build_const_int32(gallivm, 1));
2180 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex);
2181
2182 /* Signal vertex emission */
2183 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS);
2184 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2185 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2186 LLVMVoidTypeInContext(gallivm->context), args, 2,
2187 LLVMNoUnwindAttribute);
2188 }
2189
2190 /* Cut one primitive from the geometry shader */
2191 static void si_llvm_emit_primitive(
2192 const struct lp_build_tgsi_action *action,
2193 struct lp_build_tgsi_context *bld_base,
2194 struct lp_build_emit_data *emit_data)
2195 {
2196 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2197 struct gallivm_state *gallivm = bld_base->base.gallivm;
2198 LLVMValueRef args[2];
2199
2200 /* Signal primitive cut */
2201 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS);
2202 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2203 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2204 LLVMVoidTypeInContext(gallivm->context), args, 2,
2205 LLVMNoUnwindAttribute);
2206 }
2207
2208 static const struct lp_build_tgsi_action tex_action = {
2209 .fetch_args = tex_fetch_args,
2210 .emit = build_tex_intrinsic,
2211 };
2212
2213 static const struct lp_build_tgsi_action txq_action = {
2214 .fetch_args = txq_fetch_args,
2215 .emit = build_txq_intrinsic,
2216 .intr_name = "llvm.SI.resinfo"
2217 };
2218
2219 static void create_meta_data(struct si_shader_context *si_shader_ctx)
2220 {
2221 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2222 LLVMValueRef args[3];
2223
2224 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
2225 args[1] = 0;
2226 args[2] = lp_build_const_int32(gallivm, 1);
2227
2228 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
2229 }
2230
2231 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
2232 {
2233 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
2234 CONST_ADDR_SPACE);
2235 }
2236
2237 static void create_function(struct si_shader_context *si_shader_ctx)
2238 {
2239 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2240 struct gallivm_state *gallivm = bld_base->base.gallivm;
2241 struct si_shader *shader = si_shader_ctx->shader;
2242 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
2243 unsigned i, last_array_pointer, last_sgpr, num_params;
2244
2245 i8 = LLVMInt8TypeInContext(gallivm->context);
2246 i32 = LLVMInt32TypeInContext(gallivm->context);
2247 f32 = LLVMFloatTypeInContext(gallivm->context);
2248 v2i32 = LLVMVectorType(i32, 2);
2249 v3i32 = LLVMVectorType(i32, 3);
2250 v4i32 = LLVMVectorType(i32, 4);
2251 v8i32 = LLVMVectorType(i32, 8);
2252 v16i8 = LLVMVectorType(i8, 16);
2253
2254 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
2255 params[SI_PARAM_CONST] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
2256 params[SI_PARAM_SAMPLER] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
2257 params[SI_PARAM_RESOURCE] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
2258 last_array_pointer = SI_PARAM_RESOURCE;
2259
2260 switch (si_shader_ctx->type) {
2261 case TGSI_PROCESSOR_VERTEX:
2262 params[SI_PARAM_VERTEX_BUFFER] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
2263 last_array_pointer = SI_PARAM_VERTEX_BUFFER;
2264 params[SI_PARAM_BASE_VERTEX] = i32;
2265 params[SI_PARAM_START_INSTANCE] = i32;
2266 num_params = SI_PARAM_START_INSTANCE+1;
2267
2268 if (shader->key.vs.as_es) {
2269 params[SI_PARAM_ES2GS_OFFSET] = i32;
2270 num_params++;
2271 } else {
2272 if (shader->is_gs_copy_shader) {
2273 last_array_pointer = SI_PARAM_CONST;
2274 num_params = SI_PARAM_CONST+1;
2275 }
2276
2277 /* The locations of the other parameters are assigned dynamically. */
2278
2279 /* Streamout SGPRs. */
2280 if (shader->selector->so.num_outputs) {
2281 params[si_shader_ctx->param_streamout_config = num_params++] = i32;
2282 params[si_shader_ctx->param_streamout_write_index = num_params++] = i32;
2283 }
2284 /* A streamout buffer offset is loaded if the stride is non-zero. */
2285 for (i = 0; i < 4; i++) {
2286 if (!shader->selector->so.stride[i])
2287 continue;
2288
2289 params[si_shader_ctx->param_streamout_offset[i] = num_params++] = i32;
2290 }
2291 }
2292
2293 last_sgpr = num_params-1;
2294
2295 /* VGPRs */
2296 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
2297 params[num_params++] = i32; /* unused*/
2298 params[num_params++] = i32; /* unused */
2299 params[si_shader_ctx->param_instance_id = num_params++] = i32;
2300 break;
2301
2302 case TGSI_PROCESSOR_GEOMETRY:
2303 params[SI_PARAM_GS2VS_OFFSET] = i32;
2304 params[SI_PARAM_GS_WAVE_ID] = i32;
2305 last_sgpr = SI_PARAM_GS_WAVE_ID;
2306
2307 /* VGPRs */
2308 params[SI_PARAM_VTX0_OFFSET] = i32;
2309 params[SI_PARAM_VTX1_OFFSET] = i32;
2310 params[SI_PARAM_PRIMITIVE_ID] = i32;
2311 params[SI_PARAM_VTX2_OFFSET] = i32;
2312 params[SI_PARAM_VTX3_OFFSET] = i32;
2313 params[SI_PARAM_VTX4_OFFSET] = i32;
2314 params[SI_PARAM_VTX5_OFFSET] = i32;
2315 params[SI_PARAM_GS_INSTANCE_ID] = i32;
2316 num_params = SI_PARAM_GS_INSTANCE_ID+1;
2317 break;
2318
2319 case TGSI_PROCESSOR_FRAGMENT:
2320 params[SI_PARAM_ALPHA_REF] = f32;
2321 params[SI_PARAM_PRIM_MASK] = i32;
2322 last_sgpr = SI_PARAM_PRIM_MASK;
2323 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
2324 params[SI_PARAM_PERSP_CENTER] = v2i32;
2325 params[SI_PARAM_PERSP_CENTROID] = v2i32;
2326 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
2327 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
2328 params[SI_PARAM_LINEAR_CENTER] = v2i32;
2329 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
2330 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
2331 params[SI_PARAM_POS_X_FLOAT] = f32;
2332 params[SI_PARAM_POS_Y_FLOAT] = f32;
2333 params[SI_PARAM_POS_Z_FLOAT] = f32;
2334 params[SI_PARAM_POS_W_FLOAT] = f32;
2335 params[SI_PARAM_FRONT_FACE] = f32;
2336 params[SI_PARAM_ANCILLARY] = i32;
2337 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
2338 params[SI_PARAM_POS_FIXED_PT] = f32;
2339 num_params = SI_PARAM_POS_FIXED_PT+1;
2340 break;
2341
2342 default:
2343 assert(0 && "unimplemented shader");
2344 return;
2345 }
2346
2347 assert(num_params <= Elements(params));
2348 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
2349 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
2350
2351 for (i = 0; i <= last_sgpr; ++i) {
2352 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
2353
2354 /* We tell llvm that array inputs are passed by value to allow Sinking pass
2355 * to move load. Inputs are constant so this is fine. */
2356 if (i <= last_array_pointer)
2357 LLVMAddAttribute(P, LLVMByValAttribute);
2358 else
2359 LLVMAddAttribute(P, LLVMInRegAttribute);
2360 }
2361
2362 if (bld_base->info &&
2363 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
2364 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0))
2365 si_shader_ctx->ddxy_lds =
2366 LLVMAddGlobalInAddressSpace(gallivm->module,
2367 LLVMArrayType(i32, 64),
2368 "ddxy_lds",
2369 LOCAL_ADDR_SPACE);
2370 }
2371
2372 static void preload_constants(struct si_shader_context *si_shader_ctx)
2373 {
2374 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2375 struct gallivm_state * gallivm = bld_base->base.gallivm;
2376 const struct tgsi_shader_info * info = bld_base->info;
2377 unsigned buf;
2378 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
2379
2380 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
2381 unsigned i, num_const = info->const_file_max[buf] + 1;
2382
2383 if (num_const == 0)
2384 continue;
2385
2386 /* Allocate space for the constant values */
2387 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
2388
2389 /* Load the resource descriptor */
2390 si_shader_ctx->const_resource[buf] =
2391 build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
2392
2393 /* Load the constants, we rely on the code sinking to do the rest */
2394 for (i = 0; i < num_const * 4; ++i) {
2395 si_shader_ctx->constants[buf][i] =
2396 buffer_load_const(gallivm->builder,
2397 si_shader_ctx->const_resource[buf],
2398 lp_build_const_int32(gallivm, i * 4),
2399 bld_base->base.elem_type);
2400 }
2401 }
2402 }
2403
2404 static void preload_samplers(struct si_shader_context *si_shader_ctx)
2405 {
2406 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2407 struct gallivm_state * gallivm = bld_base->base.gallivm;
2408 const struct tgsi_shader_info * info = bld_base->info;
2409
2410 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
2411
2412 LLVMValueRef res_ptr, samp_ptr;
2413 LLVMValueRef offset;
2414
2415 if (num_samplers == 0)
2416 return;
2417
2418 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2419 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2420
2421 /* Load the resources and samplers, we rely on the code sinking to do the rest */
2422 for (i = 0; i < num_samplers; ++i) {
2423 /* Resource */
2424 offset = lp_build_const_int32(gallivm, i);
2425 si_shader_ctx->resources[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
2426
2427 /* Sampler */
2428 offset = lp_build_const_int32(gallivm, i);
2429 si_shader_ctx->samplers[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
2430
2431 /* FMASK resource */
2432 if (info->is_msaa_sampler[i]) {
2433 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
2434 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + i] =
2435 build_indexed_load_const(si_shader_ctx, res_ptr, offset);
2436 }
2437 }
2438 }
2439
2440 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
2441 {
2442 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2443 struct gallivm_state * gallivm = bld_base->base.gallivm;
2444 unsigned i;
2445
2446 if (si_shader_ctx->type != TGSI_PROCESSOR_VERTEX ||
2447 si_shader_ctx->shader->key.vs.as_es ||
2448 !si_shader_ctx->shader->selector->so.num_outputs)
2449 return;
2450
2451 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2452 SI_PARAM_RW_BUFFERS);
2453
2454 /* Load the resources, we rely on the code sinking to do the rest */
2455 for (i = 0; i < 4; ++i) {
2456 if (si_shader_ctx->shader->selector->so.stride[i]) {
2457 LLVMValueRef offset = lp_build_const_int32(gallivm,
2458 SI_SO_BUF_OFFSET + i);
2459
2460 si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
2461 }
2462 }
2463 }
2464
2465 /**
2466 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
2467 * for later use.
2468 */
2469 static void preload_ring_buffers(struct si_shader_context *si_shader_ctx)
2470 {
2471 struct gallivm_state *gallivm =
2472 si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2473
2474 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2475 SI_PARAM_RW_BUFFERS);
2476
2477 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
2478 si_shader_ctx->shader->key.vs.as_es) ||
2479 si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
2480 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
2481
2482 si_shader_ctx->esgs_ring =
2483 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
2484 }
2485
2486 if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY ||
2487 si_shader_ctx->shader->is_gs_copy_shader) {
2488 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
2489
2490 si_shader_ctx->gsvs_ring =
2491 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
2492 }
2493 }
2494
2495 void si_shader_binary_read_config(const struct radeon_shader_binary *binary,
2496 struct si_shader *shader,
2497 unsigned symbol_offset)
2498 {
2499 unsigned i;
2500 const unsigned char *config =
2501 radeon_shader_binary_config_start(binary, symbol_offset);
2502
2503 /* XXX: We may be able to emit some of these values directly rather than
2504 * extracting fields to be emitted later.
2505 */
2506
2507 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
2508 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
2509 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
2510 switch (reg) {
2511 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
2512 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
2513 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
2514 case R_00B848_COMPUTE_PGM_RSRC1:
2515 shader->num_sgprs = MAX2(shader->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
2516 shader->num_vgprs = MAX2(shader->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
2517 break;
2518 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
2519 shader->lds_size = MAX2(shader->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
2520 break;
2521 case R_00B84C_COMPUTE_PGM_RSRC2:
2522 shader->lds_size = MAX2(shader->lds_size, G_00B84C_LDS_SIZE(value));
2523 break;
2524 case R_0286CC_SPI_PS_INPUT_ENA:
2525 shader->spi_ps_input_ena = value;
2526 break;
2527 case R_00B860_COMPUTE_TMPRING_SIZE:
2528 /* WAVESIZE is in units of 256 dwords. */
2529 shader->scratch_bytes_per_wave =
2530 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
2531 break;
2532 default:
2533 fprintf(stderr, "Warning: Compiler emitted unknown "
2534 "config register: 0x%x\n", reg);
2535 break;
2536 }
2537 }
2538 }
2539
2540 int si_shader_binary_read(struct si_screen *sscreen,
2541 struct si_shader *shader,
2542 const struct radeon_shader_binary *binary)
2543 {
2544
2545 unsigned i;
2546 unsigned code_size;
2547 unsigned char *ptr;
2548 bool dump = r600_can_dump_shader(&sscreen->b,
2549 shader->selector ? shader->selector->tokens : NULL);
2550
2551 if (dump && !binary->disassembled) {
2552 fprintf(stderr, "SI CODE:\n");
2553 for (i = 0; i < binary->code_size; i+=4 ) {
2554 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i, binary->code[i + 3],
2555 binary->code[i + 2], binary->code[i + 1],
2556 binary->code[i]);
2557 }
2558 }
2559
2560 si_shader_binary_read_config(binary, shader, 0);
2561
2562 /* copy new shader */
2563 code_size = binary->code_size + binary->rodata_size;
2564 r600_resource_reference(&shader->bo, NULL);
2565 shader->bo = si_resource_create_custom(&sscreen->b.b, PIPE_USAGE_IMMUTABLE,
2566 code_size);
2567 if (shader->bo == NULL) {
2568 return -ENOMEM;
2569 }
2570
2571
2572 ptr = sscreen->b.ws->buffer_map(shader->bo->cs_buf, NULL, PIPE_TRANSFER_READ_WRITE);
2573 util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
2574 if (binary->rodata_size > 0) {
2575 ptr += binary->code_size;
2576 util_memcpy_cpu_to_le32(ptr, binary->rodata, binary->rodata_size);
2577 }
2578
2579 sscreen->b.ws->buffer_unmap(shader->bo->cs_buf);
2580
2581 return 0;
2582 }
2583
2584 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
2585 LLVMModuleRef mod)
2586 {
2587 int r = 0;
2588 struct radeon_shader_binary binary;
2589 bool dump = r600_can_dump_shader(&sscreen->b,
2590 shader->selector ? shader->selector->tokens : NULL);
2591 memset(&binary, 0, sizeof(binary));
2592 r = radeon_llvm_compile(mod, &binary,
2593 r600_get_llvm_processor_name(sscreen->b.family), dump);
2594
2595 if (r) {
2596 return r;
2597 }
2598 r = si_shader_binary_read(sscreen, shader, &binary);
2599 FREE(binary.code);
2600 FREE(binary.config);
2601 FREE(binary.rodata);
2602 return r;
2603 }
2604
2605 /* Generate code for the hardware VS shader stage to go with a geometry shader */
2606 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
2607 struct si_shader_context *si_shader_ctx,
2608 struct si_shader *gs, bool dump)
2609 {
2610 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
2611 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2612 struct lp_build_context *base = &bld_base->base;
2613 struct lp_build_context *uint = &bld_base->uint_bld;
2614 struct si_shader *shader = si_shader_ctx->shader;
2615 struct si_shader_output_values *outputs;
2616 struct tgsi_shader_info *gsinfo = &gs->selector->info;
2617 LLVMValueRef args[9];
2618 int i, r;
2619
2620 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
2621
2622 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
2623 shader->is_gs_copy_shader = true;
2624
2625 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
2626
2627 create_meta_data(si_shader_ctx);
2628 create_function(si_shader_ctx);
2629 preload_streamout_buffers(si_shader_ctx);
2630 preload_ring_buffers(si_shader_ctx);
2631
2632 args[0] = si_shader_ctx->gsvs_ring;
2633 args[1] = lp_build_mul_imm(uint,
2634 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2635 si_shader_ctx->param_vertex_id),
2636 4);
2637 args[3] = uint->zero;
2638 args[4] = uint->one; /* OFFEN */
2639 args[5] = uint->zero; /* IDXEN */
2640 args[6] = uint->one; /* GLC */
2641 args[7] = uint->one; /* SLC */
2642 args[8] = uint->zero; /* TFE */
2643
2644 /* Fetch vertex data from GSVS ring */
2645 for (i = 0; i < gsinfo->num_outputs; ++i) {
2646 unsigned chan;
2647
2648 outputs[i].name = gsinfo->output_semantic_name[i];
2649 outputs[i].sid = gsinfo->output_semantic_index[i];
2650
2651 for (chan = 0; chan < 4; chan++) {
2652 args[2] = lp_build_const_int32(gallivm,
2653 (i * 4 + chan) *
2654 gs->selector->gs_max_out_vertices * 16 * 4);
2655
2656 outputs[i].values[chan] =
2657 LLVMBuildBitCast(gallivm->builder,
2658 build_intrinsic(gallivm->builder,
2659 "llvm.SI.buffer.load.dword.i32.i32",
2660 LLVMInt32TypeInContext(gallivm->context),
2661 args, 9,
2662 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
2663 base->elem_type, "");
2664 }
2665 }
2666
2667 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
2668
2669 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
2670
2671 if (dump)
2672 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
2673
2674 r = si_compile_llvm(sscreen, si_shader_ctx->shader,
2675 bld_base->base.gallivm->module);
2676
2677 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
2678
2679 FREE(outputs);
2680 return r;
2681 }
2682
2683 int si_shader_create(struct si_screen *sscreen, struct si_shader *shader)
2684 {
2685 struct si_shader_selector *sel = shader->selector;
2686 struct si_shader_context si_shader_ctx;
2687 struct lp_build_tgsi_context * bld_base;
2688 LLVMModuleRef mod;
2689 int r = 0;
2690 bool dump = r600_can_dump_shader(&sscreen->b, sel->tokens);
2691
2692 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2693 * conversion fails. */
2694 if (dump) {
2695 tgsi_dump(sel->tokens, 0);
2696 si_dump_streamout(&sel->so);
2697 }
2698
2699 assert(shader->nparam == 0);
2700
2701 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
2702 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
2703 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
2704
2705 if (sel->info.uses_kill)
2706 shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
2707
2708 shader->uses_instanceid = sel->info.uses_instanceid;
2709 bld_base->info = &sel->info;
2710 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
2711
2712 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
2713 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
2714 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
2715 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
2716 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
2717 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
2718 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
2719 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
2720 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
2721 bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
2722 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
2723 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
2724
2725 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
2726 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
2727
2728 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
2729 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
2730
2731 if (HAVE_LLVM >= 0x0306) {
2732 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
2733 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
2734 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
2735 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
2736 }
2737
2738 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
2739 si_shader_ctx.tokens = sel->tokens;
2740 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
2741 si_shader_ctx.shader = shader;
2742 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
2743
2744 switch (si_shader_ctx.type) {
2745 case TGSI_PROCESSOR_VERTEX:
2746 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
2747 if (shader->key.vs.as_es) {
2748 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
2749 } else {
2750 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
2751 }
2752 break;
2753 case TGSI_PROCESSOR_GEOMETRY:
2754 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
2755 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
2756 break;
2757 case TGSI_PROCESSOR_FRAGMENT:
2758 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
2759 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
2760
2761 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2762 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2763 shader->db_shader_control |=
2764 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2765 break;
2766 case TGSI_FS_DEPTH_LAYOUT_LESS:
2767 shader->db_shader_control |=
2768 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2769 break;
2770 }
2771 break;
2772 default:
2773 assert(!"Unsupported shader type");
2774 return -1;
2775 }
2776
2777 create_meta_data(&si_shader_ctx);
2778 create_function(&si_shader_ctx);
2779 preload_constants(&si_shader_ctx);
2780 preload_samplers(&si_shader_ctx);
2781 preload_streamout_buffers(&si_shader_ctx);
2782 preload_ring_buffers(&si_shader_ctx);
2783
2784 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2785 si_shader_ctx.gs_next_vertex =
2786 lp_build_alloca(bld_base->base.gallivm,
2787 bld_base->uint_bld.elem_type, "");
2788 }
2789
2790 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
2791 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
2792 goto out;
2793 }
2794
2795 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
2796
2797 mod = bld_base->base.gallivm->module;
2798 r = si_compile_llvm(sscreen, shader, mod);
2799 if (r) {
2800 fprintf(stderr, "LLVM failed to compile shader\n");
2801 goto out;
2802 }
2803
2804 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
2805
2806 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2807 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
2808 shader->gs_copy_shader->selector = shader->selector;
2809 shader->gs_copy_shader->key = shader->key;
2810 si_shader_ctx.shader = shader->gs_copy_shader;
2811 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
2812 shader, dump))) {
2813 free(shader->gs_copy_shader);
2814 shader->gs_copy_shader = NULL;
2815 goto out;
2816 }
2817 }
2818
2819 tgsi_parse_free(&si_shader_ctx.parse);
2820
2821 out:
2822 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
2823 FREE(si_shader_ctx.constants[i]);
2824
2825 return r;
2826 }
2827
2828 void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader)
2829 {
2830 if (shader->gs_copy_shader)
2831 si_shader_destroy(ctx, shader->gs_copy_shader);
2832
2833 r600_resource_reference(&shader->bo, NULL);
2834 r600_resource_reference(&shader->scratch_bo, NULL);
2835 }