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[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "util/u_memory.h"
26 #include "util/u_string.h"
27 #include "tgsi/tgsi_build.h"
28 #include "tgsi/tgsi_util.h"
29 #include "tgsi/tgsi_dump.h"
30
31 #include "ac_exp_param.h"
32 #include "ac_shader_util.h"
33 #include "ac_llvm_util.h"
34 #include "si_shader_internal.h"
35 #include "si_pipe.h"
36 #include "sid.h"
37
38 #include "compiler/nir/nir.h"
39
40 static const char *scratch_rsrc_dword0_symbol =
41 "SCRATCH_RSRC_DWORD0";
42
43 static const char *scratch_rsrc_dword1_symbol =
44 "SCRATCH_RSRC_DWORD1";
45
46 struct si_shader_output_values
47 {
48 LLVMValueRef values[4];
49 unsigned semantic_name;
50 unsigned semantic_index;
51 ubyte vertex_stream[4];
52 };
53
54 /**
55 * Used to collect types and other info about arguments of the LLVM function
56 * before the function is created.
57 */
58 struct si_function_info {
59 LLVMTypeRef types[100];
60 LLVMValueRef *assign[100];
61 unsigned num_sgpr_params;
62 unsigned num_params;
63 };
64
65 enum si_arg_regfile {
66 ARG_SGPR,
67 ARG_VGPR
68 };
69
70 static void si_init_shader_ctx(struct si_shader_context *ctx,
71 struct si_screen *sscreen,
72 struct ac_llvm_compiler *compiler);
73
74 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
75 struct lp_build_tgsi_context *bld_base,
76 struct lp_build_emit_data *emit_data);
77
78 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
79 FILE *f);
80
81 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
82 union si_shader_part_key *key);
83 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
84 union si_shader_part_key *key);
85 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
86 union si_shader_part_key *key);
87 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
88 union si_shader_part_key *key);
89
90 /* Ideally pass the sample mask input to the PS epilog as v14, which
91 * is its usual location, so that the shader doesn't have to add v_mov.
92 */
93 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
94
95 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
96 LLVMTypeRef type)
97 {
98 if (type == ctx->ac.i64 || type == ctx->ac.f64)
99 return true;
100
101 return false;
102 }
103
104 static bool is_merged_shader(struct si_shader_context *ctx)
105 {
106 if (ctx->screen->info.chip_class <= VI)
107 return false;
108
109 return ctx->shader->key.as_ls ||
110 ctx->shader->key.as_es ||
111 ctx->type == PIPE_SHADER_TESS_CTRL ||
112 ctx->type == PIPE_SHADER_GEOMETRY;
113 }
114
115 static void si_init_function_info(struct si_function_info *fninfo)
116 {
117 fninfo->num_params = 0;
118 fninfo->num_sgpr_params = 0;
119 }
120
121 static unsigned add_arg_assign(struct si_function_info *fninfo,
122 enum si_arg_regfile regfile, LLVMTypeRef type,
123 LLVMValueRef *assign)
124 {
125 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
126
127 unsigned idx = fninfo->num_params++;
128 assert(idx < ARRAY_SIZE(fninfo->types));
129
130 if (regfile == ARG_SGPR)
131 fninfo->num_sgpr_params = fninfo->num_params;
132
133 fninfo->types[idx] = type;
134 fninfo->assign[idx] = assign;
135 return idx;
136 }
137
138 static unsigned add_arg(struct si_function_info *fninfo,
139 enum si_arg_regfile regfile, LLVMTypeRef type)
140 {
141 return add_arg_assign(fninfo, regfile, type, NULL);
142 }
143
144 static void add_arg_assign_checked(struct si_function_info *fninfo,
145 enum si_arg_regfile regfile, LLVMTypeRef type,
146 LLVMValueRef *assign, unsigned idx)
147 {
148 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
149 assert(actual == idx);
150 }
151
152 static void add_arg_checked(struct si_function_info *fninfo,
153 enum si_arg_regfile regfile, LLVMTypeRef type,
154 unsigned idx)
155 {
156 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
157 }
158
159 /**
160 * Returns a unique index for a per-patch semantic name and index. The index
161 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
162 * can be calculated.
163 */
164 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
165 {
166 switch (semantic_name) {
167 case TGSI_SEMANTIC_TESSOUTER:
168 return 0;
169 case TGSI_SEMANTIC_TESSINNER:
170 return 1;
171 case TGSI_SEMANTIC_PATCH:
172 assert(index < 30);
173 return 2 + index;
174
175 default:
176 assert(!"invalid semantic name");
177 return 0;
178 }
179 }
180
181 /**
182 * Returns a unique index for a semantic name and index. The index must be
183 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
184 * calculated.
185 */
186 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index,
187 unsigned is_varying)
188 {
189 switch (semantic_name) {
190 case TGSI_SEMANTIC_POSITION:
191 return 0;
192 case TGSI_SEMANTIC_GENERIC:
193 /* Since some shader stages use the the highest used IO index
194 * to determine the size to allocate for inputs/outputs
195 * (in LDS, tess and GS rings). GENERIC should be placed right
196 * after POSITION to make that size as small as possible.
197 */
198 if (index < SI_MAX_IO_GENERIC)
199 return 1 + index;
200
201 assert(!"invalid generic index");
202 return 0;
203 case TGSI_SEMANTIC_PSIZE:
204 return SI_MAX_IO_GENERIC + 1;
205 case TGSI_SEMANTIC_CLIPDIST:
206 assert(index <= 1);
207 return SI_MAX_IO_GENERIC + 2 + index;
208 case TGSI_SEMANTIC_FOG:
209 return SI_MAX_IO_GENERIC + 4;
210 case TGSI_SEMANTIC_LAYER:
211 return SI_MAX_IO_GENERIC + 5;
212 case TGSI_SEMANTIC_VIEWPORT_INDEX:
213 return SI_MAX_IO_GENERIC + 6;
214 case TGSI_SEMANTIC_PRIMID:
215 return SI_MAX_IO_GENERIC + 7;
216 case TGSI_SEMANTIC_COLOR:
217 assert(index < 2);
218 return SI_MAX_IO_GENERIC + 8 + index;
219 case TGSI_SEMANTIC_BCOLOR:
220 assert(index < 2);
221 /* If it's a varying, COLOR and BCOLOR alias. */
222 if (is_varying)
223 return SI_MAX_IO_GENERIC + 8 + index;
224 else
225 return SI_MAX_IO_GENERIC + 10 + index;
226 case TGSI_SEMANTIC_TEXCOORD:
227 assert(index < 8);
228 STATIC_ASSERT(SI_MAX_IO_GENERIC + 12 + 8 <= 63);
229 return SI_MAX_IO_GENERIC + 12 + index;
230 case TGSI_SEMANTIC_CLIPVERTEX:
231 return 63;
232 default:
233 fprintf(stderr, "invalid semantic name = %u\n", semantic_name);
234 assert(!"invalid semantic name");
235 return 0;
236 }
237 }
238
239 /**
240 * Get the value of a shader input parameter and extract a bitfield.
241 */
242 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
243 LLVMValueRef value, unsigned rshift,
244 unsigned bitwidth)
245 {
246 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
247 value = ac_to_integer(&ctx->ac, value);
248
249 if (rshift)
250 value = LLVMBuildLShr(ctx->ac.builder, value,
251 LLVMConstInt(ctx->i32, rshift, 0), "");
252
253 if (rshift + bitwidth < 32) {
254 unsigned mask = (1 << bitwidth) - 1;
255 value = LLVMBuildAnd(ctx->ac.builder, value,
256 LLVMConstInt(ctx->i32, mask, 0), "");
257 }
258
259 return value;
260 }
261
262 LLVMValueRef si_unpack_param(struct si_shader_context *ctx,
263 unsigned param, unsigned rshift,
264 unsigned bitwidth)
265 {
266 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
267
268 return unpack_llvm_param(ctx, value, rshift, bitwidth);
269 }
270
271 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
272 {
273 switch (ctx->type) {
274 case PIPE_SHADER_TESS_CTRL:
275 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
276
277 case PIPE_SHADER_TESS_EVAL:
278 return LLVMGetParam(ctx->main_fn,
279 ctx->param_tes_rel_patch_id);
280
281 default:
282 assert(0);
283 return NULL;
284 }
285 }
286
287 /* Tessellation shaders pass outputs to the next shader using LDS.
288 *
289 * LS outputs = TCS inputs
290 * TCS outputs = TES inputs
291 *
292 * The LDS layout is:
293 * - TCS inputs for patch 0
294 * - TCS inputs for patch 1
295 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
296 * - ...
297 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
298 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
299 * - TCS outputs for patch 1
300 * - Per-patch TCS outputs for patch 1
301 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
302 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
303 * - ...
304 *
305 * All three shaders VS(LS), TCS, TES share the same LDS space.
306 */
307
308 static LLVMValueRef
309 get_tcs_in_patch_stride(struct si_shader_context *ctx)
310 {
311 return si_unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
312 }
313
314 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
315 {
316 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
317
318 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
319 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
320
321 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
322 }
323
324 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
325 {
326 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
327
328 return LLVMConstInt(ctx->i32, stride, 0);
329 }
330
331 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
332 {
333 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
334 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
335
336 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
337 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
338 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
339 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
340 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
341 num_patch_outputs * 4;
342 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
343 }
344
345 static LLVMValueRef
346 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
347 {
348 return LLVMBuildMul(ctx->ac.builder,
349 si_unpack_param(ctx,
350 ctx->param_tcs_out_lds_offsets,
351 0, 16),
352 LLVMConstInt(ctx->i32, 4, 0), "");
353 }
354
355 static LLVMValueRef
356 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
357 {
358 return LLVMBuildMul(ctx->ac.builder,
359 si_unpack_param(ctx,
360 ctx->param_tcs_out_lds_offsets,
361 16, 16),
362 LLVMConstInt(ctx->i32, 4, 0), "");
363 }
364
365 static LLVMValueRef
366 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
367 {
368 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
369 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
370
371 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
372 }
373
374 static LLVMValueRef
375 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
376 {
377 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
378 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
379 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
380
381 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_offset);
382 }
383
384 static LLVMValueRef
385 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
386 {
387 LLVMValueRef patch0_patch_data_offset =
388 get_tcs_out_patch0_patch_data_offset(ctx);
389 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
390 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
391
392 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_patch_data_offset);
393 }
394
395 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
396 {
397 unsigned tcs_out_vertices =
398 ctx->shader->selector ?
399 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
400
401 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
402 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
403 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
404
405 return si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
406 }
407
408 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
409 {
410 unsigned stride;
411
412 switch (ctx->type) {
413 case PIPE_SHADER_VERTEX:
414 stride = ctx->shader->selector->lshs_vertex_stride / 4;
415 return LLVMConstInt(ctx->i32, stride, 0);
416
417 case PIPE_SHADER_TESS_CTRL:
418 if (ctx->screen->info.chip_class >= GFX9 &&
419 ctx->shader->is_monolithic) {
420 stride = ctx->shader->key.part.tcs.ls->lshs_vertex_stride / 4;
421 return LLVMConstInt(ctx->i32, stride, 0);
422 }
423 return si_unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
424
425 default:
426 assert(0);
427 return NULL;
428 }
429 }
430
431 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
432 * to float. */
433 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
434 LLVMValueRef vec4,
435 unsigned double_index)
436 {
437 LLVMBuilderRef builder = ctx->ac.builder;
438 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->ac.context);
439 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
440 LLVMVectorType(f64, 2), "");
441 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
442 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
443 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
444 }
445
446 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
447 LLVMValueRef i32, unsigned index)
448 {
449 assert(index <= 1);
450
451 if (index == 1)
452 return LLVMBuildAShr(ctx->ac.builder, i32,
453 LLVMConstInt(ctx->i32, 16, 0), "");
454
455 return LLVMBuildSExt(ctx->ac.builder,
456 LLVMBuildTrunc(ctx->ac.builder, i32,
457 ctx->ac.i16, ""),
458 ctx->i32, "");
459 }
460
461 void si_llvm_load_input_vs(
462 struct si_shader_context *ctx,
463 unsigned input_index,
464 LLVMValueRef out[4])
465 {
466 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
467 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
468
469 if (vs_blit_property) {
470 LLVMValueRef vertex_id = ctx->abi.vertex_id;
471 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
472 LLVMIntULE, vertex_id,
473 ctx->i32_1, "");
474 /* Use LLVMIntNE, because we have 3 vertices and only
475 * the middle one should use y2.
476 */
477 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
478 LLVMIntNE, vertex_id,
479 ctx->i32_1, "");
480
481 if (input_index == 0) {
482 /* Position: */
483 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
484 ctx->param_vs_blit_inputs);
485 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
486 ctx->param_vs_blit_inputs + 1);
487
488 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
489 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
490 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
491 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
492
493 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
494 x1, x2, "");
495 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
496 y1, y2, "");
497
498 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
499 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
500 out[2] = LLVMGetParam(ctx->main_fn,
501 ctx->param_vs_blit_inputs + 2);
502 out[3] = ctx->ac.f32_1;
503 return;
504 }
505
506 /* Color or texture coordinates: */
507 assert(input_index == 1);
508
509 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
510 for (int i = 0; i < 4; i++) {
511 out[i] = LLVMGetParam(ctx->main_fn,
512 ctx->param_vs_blit_inputs + 3 + i);
513 }
514 } else {
515 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
516 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
517 ctx->param_vs_blit_inputs + 3);
518 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
519 ctx->param_vs_blit_inputs + 4);
520 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
521 ctx->param_vs_blit_inputs + 5);
522 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
523 ctx->param_vs_blit_inputs + 6);
524
525 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
526 x1, x2, "");
527 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
528 y1, y2, "");
529 out[2] = LLVMGetParam(ctx->main_fn,
530 ctx->param_vs_blit_inputs + 7);
531 out[3] = LLVMGetParam(ctx->main_fn,
532 ctx->param_vs_blit_inputs + 8);
533 }
534 return;
535 }
536
537 unsigned chan;
538 unsigned fix_fetch;
539 unsigned num_fetches;
540 unsigned fetch_stride;
541 unsigned num_channels;
542
543 LLVMValueRef t_list_ptr;
544 LLVMValueRef t_offset;
545 LLVMValueRef t_list;
546 LLVMValueRef vertex_index;
547 LLVMValueRef input[3];
548
549 /* Load the T list */
550 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
551
552 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
553
554 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
555
556 vertex_index = LLVMGetParam(ctx->main_fn,
557 ctx->param_vertex_index0 +
558 input_index);
559
560 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
561
562 /* Do multiple loads for special formats. */
563 switch (fix_fetch) {
564 case SI_FIX_FETCH_RGB_64_FLOAT:
565 num_fetches = 3; /* 3 2-dword loads */
566 fetch_stride = 8;
567 num_channels = 2;
568 break;
569 case SI_FIX_FETCH_RGBA_64_FLOAT:
570 num_fetches = 2; /* 2 4-dword loads */
571 fetch_stride = 16;
572 num_channels = 4;
573 break;
574 case SI_FIX_FETCH_RGB_8:
575 case SI_FIX_FETCH_RGB_8_INT:
576 num_fetches = 3;
577 fetch_stride = 1;
578 num_channels = 1;
579 break;
580 case SI_FIX_FETCH_RGB_16:
581 case SI_FIX_FETCH_RGB_16_INT:
582 num_fetches = 3;
583 fetch_stride = 2;
584 num_channels = 1;
585 break;
586 default:
587 num_fetches = 1;
588 fetch_stride = 0;
589 num_channels = util_last_bit(info->input_usage_mask[input_index]);
590 }
591
592 for (unsigned i = 0; i < num_fetches; i++) {
593 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
594
595 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
596 vertex_index, voffset,
597 num_channels, false, true);
598 input[i] = ac_build_expand_to_vec4(&ctx->ac, input[i], num_channels);
599 }
600
601 /* Break up the vec4 into individual components */
602 for (chan = 0; chan < 4; chan++) {
603 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
604 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
605 input[0], llvm_chan, "");
606 }
607
608 switch (fix_fetch) {
609 case SI_FIX_FETCH_A2_SNORM:
610 case SI_FIX_FETCH_A2_SSCALED:
611 case SI_FIX_FETCH_A2_SINT: {
612 /* The hardware returns an unsigned value; convert it to a
613 * signed one.
614 */
615 LLVMValueRef tmp = out[3];
616 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
617
618 /* First, recover the sign-extended signed integer value. */
619 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
620 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
621 else
622 tmp = ac_to_integer(&ctx->ac, tmp);
623
624 /* For the integer-like cases, do a natural sign extension.
625 *
626 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
627 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
628 * exponent.
629 */
630 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
631 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
632 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
633 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
634
635 /* Convert back to the right type. */
636 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
637 LLVMValueRef clamp;
638 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
639 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
640 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
641 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
642 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
643 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
644 }
645
646 out[3] = tmp;
647 break;
648 }
649 case SI_FIX_FETCH_RGBA_32_UNORM:
650 case SI_FIX_FETCH_RGBX_32_UNORM:
651 for (chan = 0; chan < 4; chan++) {
652 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
653 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
654 out[chan], ctx->f32, "");
655 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
656 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
657 }
658 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
659 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
660 out[3] = LLVMConstReal(ctx->f32, 1);
661 break;
662 case SI_FIX_FETCH_RGBA_32_SNORM:
663 case SI_FIX_FETCH_RGBX_32_SNORM:
664 case SI_FIX_FETCH_RGBA_32_FIXED:
665 case SI_FIX_FETCH_RGBX_32_FIXED: {
666 double scale;
667 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
668 scale = 1.0 / 0x10000;
669 else
670 scale = 1.0 / INT_MAX;
671
672 for (chan = 0; chan < 4; chan++) {
673 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
674 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
675 out[chan], ctx->f32, "");
676 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
677 LLVMConstReal(ctx->f32, scale), "");
678 }
679 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
680 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
681 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
682 out[3] = LLVMConstReal(ctx->f32, 1);
683 break;
684 }
685 case SI_FIX_FETCH_RGBA_32_USCALED:
686 for (chan = 0; chan < 4; chan++) {
687 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
688 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
689 out[chan], ctx->f32, "");
690 }
691 break;
692 case SI_FIX_FETCH_RGBA_32_SSCALED:
693 for (chan = 0; chan < 4; chan++) {
694 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
695 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
696 out[chan], ctx->f32, "");
697 }
698 break;
699 case SI_FIX_FETCH_RG_64_FLOAT:
700 for (chan = 0; chan < 2; chan++)
701 out[chan] = extract_double_to_float(ctx, input[0], chan);
702
703 out[2] = LLVMConstReal(ctx->f32, 0);
704 out[3] = LLVMConstReal(ctx->f32, 1);
705 break;
706 case SI_FIX_FETCH_RGB_64_FLOAT:
707 for (chan = 0; chan < 3; chan++)
708 out[chan] = extract_double_to_float(ctx, input[chan], 0);
709
710 out[3] = LLVMConstReal(ctx->f32, 1);
711 break;
712 case SI_FIX_FETCH_RGBA_64_FLOAT:
713 for (chan = 0; chan < 4; chan++) {
714 out[chan] = extract_double_to_float(ctx, input[chan / 2],
715 chan % 2);
716 }
717 break;
718 case SI_FIX_FETCH_RGB_8:
719 case SI_FIX_FETCH_RGB_8_INT:
720 case SI_FIX_FETCH_RGB_16:
721 case SI_FIX_FETCH_RGB_16_INT:
722 for (chan = 0; chan < 3; chan++) {
723 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
724 input[chan],
725 ctx->i32_0, "");
726 }
727 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
728 fix_fetch == SI_FIX_FETCH_RGB_16) {
729 out[3] = LLVMConstReal(ctx->f32, 1);
730 } else {
731 out[3] = ac_to_float(&ctx->ac, ctx->i32_1);
732 }
733 break;
734 }
735 }
736
737 static void declare_input_vs(
738 struct si_shader_context *ctx,
739 unsigned input_index,
740 const struct tgsi_full_declaration *decl,
741 LLVMValueRef out[4])
742 {
743 si_llvm_load_input_vs(ctx, input_index, out);
744 }
745
746 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
747 unsigned swizzle)
748 {
749 if (swizzle > 0)
750 return ctx->i32_0;
751
752 switch (ctx->type) {
753 case PIPE_SHADER_VERTEX:
754 return LLVMGetParam(ctx->main_fn,
755 ctx->param_vs_prim_id);
756 case PIPE_SHADER_TESS_CTRL:
757 return ctx->abi.tcs_patch_id;
758 case PIPE_SHADER_TESS_EVAL:
759 return ctx->abi.tes_patch_id;
760 case PIPE_SHADER_GEOMETRY:
761 return ctx->abi.gs_prim_id;
762 default:
763 assert(0);
764 return ctx->i32_0;
765 }
766 }
767
768 /**
769 * Return the value of tgsi_ind_register for indexing.
770 * This is the indirect index with the constant offset added to it.
771 */
772 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
773 const struct tgsi_ind_register *ind,
774 unsigned addr_mul,
775 int rel_index)
776 {
777 LLVMValueRef result;
778
779 if (ind->File == TGSI_FILE_ADDRESS) {
780 result = ctx->addrs[ind->Index][ind->Swizzle];
781 result = LLVMBuildLoad(ctx->ac.builder, result, "");
782 } else {
783 struct tgsi_full_src_register src = {};
784
785 src.Register.File = ind->File;
786 src.Register.Index = ind->Index;
787
788 /* Set the second index to 0 for constants. */
789 if (ind->File == TGSI_FILE_CONSTANT)
790 src.Register.Dimension = 1;
791
792 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
793 TGSI_TYPE_SIGNED,
794 ind->Swizzle);
795 result = ac_to_integer(&ctx->ac, result);
796 }
797
798 return ac_build_imad(&ctx->ac, result, LLVMConstInt(ctx->i32, addr_mul, 0),
799 LLVMConstInt(ctx->i32, rel_index, 0));
800 }
801
802 /**
803 * Like si_get_indirect_index, but restricts the return value to a (possibly
804 * undefined) value inside [0..num).
805 */
806 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
807 const struct tgsi_ind_register *ind,
808 int rel_index, unsigned num)
809 {
810 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
811
812 return si_llvm_bound_index(ctx, result, num);
813 }
814
815 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
816 LLVMValueRef vertex_dw_stride,
817 LLVMValueRef base_addr,
818 LLVMValueRef vertex_index,
819 LLVMValueRef param_index,
820 unsigned input_index,
821 ubyte *name,
822 ubyte *index,
823 bool is_patch)
824 {
825 if (vertex_dw_stride) {
826 base_addr = ac_build_imad(&ctx->ac, vertex_index,
827 vertex_dw_stride, base_addr);
828 }
829
830 if (param_index) {
831 base_addr = ac_build_imad(&ctx->ac, param_index,
832 LLVMConstInt(ctx->i32, 4, 0), base_addr);
833 }
834
835 int param = is_patch ?
836 si_shader_io_get_unique_index_patch(name[input_index],
837 index[input_index]) :
838 si_shader_io_get_unique_index(name[input_index],
839 index[input_index], false);
840
841 /* Add the base address of the element. */
842 return LLVMBuildAdd(ctx->ac.builder, base_addr,
843 LLVMConstInt(ctx->i32, param * 4, 0), "");
844 }
845
846 /**
847 * Calculate a dword address given an input or output register and a stride.
848 */
849 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
850 const struct tgsi_full_dst_register *dst,
851 const struct tgsi_full_src_register *src,
852 LLVMValueRef vertex_dw_stride,
853 LLVMValueRef base_addr)
854 {
855 struct tgsi_shader_info *info = &ctx->shader->selector->info;
856 ubyte *name, *index, *array_first;
857 int input_index;
858 struct tgsi_full_dst_register reg;
859 LLVMValueRef vertex_index = NULL;
860 LLVMValueRef ind_index = NULL;
861
862 /* Set the register description. The address computation is the same
863 * for sources and destinations. */
864 if (src) {
865 reg.Register.File = src->Register.File;
866 reg.Register.Index = src->Register.Index;
867 reg.Register.Indirect = src->Register.Indirect;
868 reg.Register.Dimension = src->Register.Dimension;
869 reg.Indirect = src->Indirect;
870 reg.Dimension = src->Dimension;
871 reg.DimIndirect = src->DimIndirect;
872 } else
873 reg = *dst;
874
875 /* If the register is 2-dimensional (e.g. an array of vertices
876 * in a primitive), calculate the base address of the vertex. */
877 if (reg.Register.Dimension) {
878 if (reg.Dimension.Indirect)
879 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
880 1, reg.Dimension.Index);
881 else
882 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
883 }
884
885 /* Get information about the register. */
886 if (reg.Register.File == TGSI_FILE_INPUT) {
887 name = info->input_semantic_name;
888 index = info->input_semantic_index;
889 array_first = info->input_array_first;
890 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
891 name = info->output_semantic_name;
892 index = info->output_semantic_index;
893 array_first = info->output_array_first;
894 } else {
895 assert(0);
896 return NULL;
897 }
898
899 if (reg.Register.Indirect) {
900 /* Add the relative address of the element. */
901 if (reg.Indirect.ArrayID)
902 input_index = array_first[reg.Indirect.ArrayID];
903 else
904 input_index = reg.Register.Index;
905
906 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
907 1, reg.Register.Index - input_index);
908 } else {
909 input_index = reg.Register.Index;
910 }
911
912 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
913 base_addr, vertex_index,
914 ind_index, input_index,
915 name, index,
916 !reg.Register.Dimension);
917 }
918
919 /* The offchip buffer layout for TCS->TES is
920 *
921 * - attribute 0 of patch 0 vertex 0
922 * - attribute 0 of patch 0 vertex 1
923 * - attribute 0 of patch 0 vertex 2
924 * ...
925 * - attribute 0 of patch 1 vertex 0
926 * - attribute 0 of patch 1 vertex 1
927 * ...
928 * - attribute 1 of patch 0 vertex 0
929 * - attribute 1 of patch 0 vertex 1
930 * ...
931 * - per patch attribute 0 of patch 0
932 * - per patch attribute 0 of patch 1
933 * ...
934 *
935 * Note that every attribute has 4 components.
936 */
937 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
938 LLVMValueRef rel_patch_id,
939 LLVMValueRef vertex_index,
940 LLVMValueRef param_index)
941 {
942 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
943 LLVMValueRef param_stride, constant16;
944
945 vertices_per_patch = get_num_tcs_out_vertices(ctx);
946 num_patches = si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
947 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
948 num_patches, "");
949
950 constant16 = LLVMConstInt(ctx->i32, 16, 0);
951 if (vertex_index) {
952 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
953 vertices_per_patch, vertex_index);
954 param_stride = total_vertices;
955 } else {
956 base_addr = rel_patch_id;
957 param_stride = num_patches;
958 }
959
960 base_addr = ac_build_imad(&ctx->ac, param_index, param_stride, base_addr);
961 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
962
963 if (!vertex_index) {
964 LLVMValueRef patch_data_offset =
965 si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
966
967 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
968 patch_data_offset, "");
969 }
970 return base_addr;
971 }
972
973 /* This is a generic helper that can be shared by the NIR and TGSI backends */
974 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
975 struct si_shader_context *ctx,
976 LLVMValueRef vertex_index,
977 LLVMValueRef param_index,
978 unsigned param_base,
979 ubyte *name,
980 ubyte *index,
981 bool is_patch)
982 {
983 unsigned param_index_base;
984
985 param_index_base = is_patch ?
986 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
987 si_shader_io_get_unique_index(name[param_base], index[param_base], false);
988
989 if (param_index) {
990 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
991 LLVMConstInt(ctx->i32, param_index_base, 0),
992 "");
993 } else {
994 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
995 }
996
997 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
998 vertex_index, param_index);
999 }
1000
1001 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
1002 struct si_shader_context *ctx,
1003 const struct tgsi_full_dst_register *dst,
1004 const struct tgsi_full_src_register *src)
1005 {
1006 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1007 ubyte *name, *index, *array_first;
1008 struct tgsi_full_src_register reg;
1009 LLVMValueRef vertex_index = NULL;
1010 LLVMValueRef param_index = NULL;
1011 unsigned param_base;
1012
1013 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
1014
1015 if (reg.Register.Dimension) {
1016
1017 if (reg.Dimension.Indirect)
1018 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
1019 1, reg.Dimension.Index);
1020 else
1021 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
1022 }
1023
1024 /* Get information about the register. */
1025 if (reg.Register.File == TGSI_FILE_INPUT) {
1026 name = info->input_semantic_name;
1027 index = info->input_semantic_index;
1028 array_first = info->input_array_first;
1029 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1030 name = info->output_semantic_name;
1031 index = info->output_semantic_index;
1032 array_first = info->output_array_first;
1033 } else {
1034 assert(0);
1035 return NULL;
1036 }
1037
1038 if (reg.Register.Indirect) {
1039 if (reg.Indirect.ArrayID)
1040 param_base = array_first[reg.Indirect.ArrayID];
1041 else
1042 param_base = reg.Register.Index;
1043
1044 param_index = si_get_indirect_index(ctx, &reg.Indirect,
1045 1, reg.Register.Index - param_base);
1046
1047 } else {
1048 param_base = reg.Register.Index;
1049 }
1050
1051 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1052 param_index, param_base,
1053 name, index, !reg.Register.Dimension);
1054 }
1055
1056 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
1057 LLVMTypeRef type, unsigned swizzle,
1058 LLVMValueRef buffer, LLVMValueRef offset,
1059 LLVMValueRef base, bool can_speculate)
1060 {
1061 struct si_shader_context *ctx = si_shader_context(bld_base);
1062 LLVMValueRef value, value2;
1063 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
1064
1065 if (swizzle == ~0) {
1066 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1067 0, 1, 0, can_speculate, false);
1068
1069 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1070 }
1071
1072 if (!llvm_type_is_64bit(ctx, type)) {
1073 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1074 0, 1, 0, can_speculate, false);
1075
1076 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1077 return LLVMBuildExtractElement(ctx->ac.builder, value,
1078 LLVMConstInt(ctx->i32, swizzle, 0), "");
1079 }
1080
1081 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1082 swizzle * 4, 1, 0, can_speculate, false);
1083
1084 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1085 swizzle * 4 + 4, 1, 0, can_speculate, false);
1086
1087 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1088 }
1089
1090 /**
1091 * Load from LDS.
1092 *
1093 * \param type output value type
1094 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1095 * \param dw_addr address in dwords
1096 */
1097 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1098 LLVMTypeRef type, unsigned swizzle,
1099 LLVMValueRef dw_addr)
1100 {
1101 struct si_shader_context *ctx = si_shader_context(bld_base);
1102 LLVMValueRef value;
1103
1104 if (swizzle == ~0) {
1105 LLVMValueRef values[TGSI_NUM_CHANNELS];
1106
1107 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1108 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1109
1110 return ac_build_gather_values(&ctx->ac, values,
1111 TGSI_NUM_CHANNELS);
1112 }
1113
1114 /* Split 64-bit loads. */
1115 if (llvm_type_is_64bit(ctx, type)) {
1116 LLVMValueRef lo, hi;
1117
1118 lo = lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1119 hi = lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1120 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1121 }
1122
1123 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1124 LLVMConstInt(ctx->i32, swizzle, 0), "");
1125
1126 value = ac_lds_load(&ctx->ac, dw_addr);
1127
1128 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1129 }
1130
1131 /**
1132 * Store to LDS.
1133 *
1134 * \param swizzle offset (typically 0..3)
1135 * \param dw_addr address in dwords
1136 * \param value value to store
1137 */
1138 static void lds_store(struct si_shader_context *ctx,
1139 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1140 LLVMValueRef value)
1141 {
1142 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1143 LLVMConstInt(ctx->i32, dw_offset_imm, 0), "");
1144
1145 ac_lds_store(&ctx->ac, dw_addr, value);
1146 }
1147
1148 enum si_tess_ring {
1149 TCS_FACTOR_RING,
1150 TESS_OFFCHIP_RING_TCS,
1151 TESS_OFFCHIP_RING_TES,
1152 };
1153
1154 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
1155 enum si_tess_ring ring)
1156 {
1157 LLVMBuilderRef builder = ctx->ac.builder;
1158 unsigned param = ring == TESS_OFFCHIP_RING_TES ? ctx->param_tes_offchip_addr :
1159 ctx->param_tcs_out_lds_layout;
1160 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1161
1162 /* TCS only receives high 13 bits of the address. */
1163 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
1164 addr = LLVMBuildAnd(builder, addr,
1165 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
1166 }
1167
1168 if (ring == TCS_FACTOR_RING) {
1169 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
1170 addr = LLVMBuildAdd(builder, addr,
1171 LLVMConstInt(ctx->i32, tf_offset, 0), "");
1172 }
1173
1174 LLVMValueRef desc[4];
1175 desc[0] = addr;
1176 desc[1] = LLVMConstInt(ctx->i32,
1177 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1178 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
1179 desc[3] = LLVMConstInt(ctx->i32,
1180 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1181 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1182 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1183 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1184 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1185 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0);
1186
1187 return ac_build_gather_values(&ctx->ac, desc, 4);
1188 }
1189
1190 static LLVMValueRef fetch_input_tcs(
1191 struct lp_build_tgsi_context *bld_base,
1192 const struct tgsi_full_src_register *reg,
1193 enum tgsi_opcode_type type, unsigned swizzle_in)
1194 {
1195 struct si_shader_context *ctx = si_shader_context(bld_base);
1196 LLVMValueRef dw_addr, stride;
1197 unsigned swizzle = swizzle_in & 0xffff;
1198 stride = get_tcs_in_vertex_dw_stride(ctx);
1199 dw_addr = get_tcs_in_current_patch_offset(ctx);
1200 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1201
1202 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1203 }
1204
1205 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1206 LLVMTypeRef type,
1207 LLVMValueRef vertex_index,
1208 LLVMValueRef param_index,
1209 unsigned const_index,
1210 unsigned location,
1211 unsigned driver_location,
1212 unsigned component,
1213 unsigned num_components,
1214 bool is_patch,
1215 bool is_compact,
1216 bool load_input)
1217 {
1218 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1219 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1220 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1221 LLVMValueRef dw_addr, stride;
1222
1223 driver_location = driver_location / 4;
1224
1225 if (load_input) {
1226 stride = get_tcs_in_vertex_dw_stride(ctx);
1227 dw_addr = get_tcs_in_current_patch_offset(ctx);
1228 } else {
1229 if (is_patch) {
1230 stride = NULL;
1231 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1232 } else {
1233 stride = get_tcs_out_vertex_dw_stride(ctx);
1234 dw_addr = get_tcs_out_current_patch_offset(ctx);
1235 }
1236 }
1237
1238 if (param_index) {
1239 /* Add the constant index to the indirect index */
1240 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1241 LLVMConstInt(ctx->i32, const_index, 0), "");
1242 } else {
1243 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1244 }
1245
1246 ubyte *names;
1247 ubyte *indices;
1248 if (load_input) {
1249 names = info->input_semantic_name;
1250 indices = info->input_semantic_index;
1251 } else {
1252 names = info->output_semantic_name;
1253 indices = info->output_semantic_index;
1254 }
1255
1256 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1257 vertex_index, param_index,
1258 driver_location,
1259 names, indices,
1260 is_patch);
1261
1262 LLVMValueRef value[4];
1263 for (unsigned i = 0; i < num_components; i++) {
1264 unsigned offset = i;
1265 if (llvm_type_is_64bit(ctx, type))
1266 offset *= 2;
1267
1268 offset += component;
1269 value[i + component] = lds_load(bld_base, type, offset, dw_addr);
1270 }
1271
1272 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1273 }
1274
1275 static LLVMValueRef fetch_output_tcs(
1276 struct lp_build_tgsi_context *bld_base,
1277 const struct tgsi_full_src_register *reg,
1278 enum tgsi_opcode_type type, unsigned swizzle_in)
1279 {
1280 struct si_shader_context *ctx = si_shader_context(bld_base);
1281 LLVMValueRef dw_addr, stride;
1282 unsigned swizzle = (swizzle_in & 0xffff);
1283
1284 if (reg->Register.Dimension) {
1285 stride = get_tcs_out_vertex_dw_stride(ctx);
1286 dw_addr = get_tcs_out_current_patch_offset(ctx);
1287 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1288 } else {
1289 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1290 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1291 }
1292
1293 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1294 }
1295
1296 static LLVMValueRef fetch_input_tes(
1297 struct lp_build_tgsi_context *bld_base,
1298 const struct tgsi_full_src_register *reg,
1299 enum tgsi_opcode_type type, unsigned swizzle_in)
1300 {
1301 struct si_shader_context *ctx = si_shader_context(bld_base);
1302 LLVMValueRef base, addr;
1303 unsigned swizzle = (swizzle_in & 0xffff);
1304
1305 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1306 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1307
1308 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1309 ctx->tess_offchip_ring, base, addr, true);
1310 }
1311
1312 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1313 LLVMTypeRef type,
1314 LLVMValueRef vertex_index,
1315 LLVMValueRef param_index,
1316 unsigned const_index,
1317 unsigned location,
1318 unsigned driver_location,
1319 unsigned component,
1320 unsigned num_components,
1321 bool is_patch,
1322 bool is_compact,
1323 bool load_input)
1324 {
1325 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1326 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1327 LLVMValueRef base, addr;
1328
1329 driver_location = driver_location / 4;
1330
1331 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1332
1333 if (param_index) {
1334 /* Add the constant index to the indirect index */
1335 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1336 LLVMConstInt(ctx->i32, const_index, 0), "");
1337 } else {
1338 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1339 }
1340
1341 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1342 param_index, driver_location,
1343 info->input_semantic_name,
1344 info->input_semantic_index,
1345 is_patch);
1346
1347 /* TODO: This will generate rather ordinary llvm code, although it
1348 * should be easy for the optimiser to fix up. In future we might want
1349 * to refactor buffer_load(), but for now this maximises code sharing
1350 * between the NIR and TGSI backends.
1351 */
1352 LLVMValueRef value[4];
1353 for (unsigned i = 0; i < num_components; i++) {
1354 unsigned offset = i;
1355 if (llvm_type_is_64bit(ctx, type))
1356 offset *= 2;
1357
1358 offset += component;
1359 value[i + component] = buffer_load(&ctx->bld_base, type, offset,
1360 ctx->tess_offchip_ring, base, addr, true);
1361 }
1362
1363 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1364 }
1365
1366 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1367 const struct tgsi_full_instruction *inst,
1368 const struct tgsi_opcode_info *info,
1369 unsigned index,
1370 LLVMValueRef dst[4])
1371 {
1372 struct si_shader_context *ctx = si_shader_context(bld_base);
1373 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1374 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1375 unsigned chan_index;
1376 LLVMValueRef dw_addr, stride;
1377 LLVMValueRef buffer, base, buf_addr;
1378 LLVMValueRef values[4];
1379 bool skip_lds_store;
1380 bool is_tess_factor = false, is_tess_inner = false;
1381
1382 /* Only handle per-patch and per-vertex outputs here.
1383 * Vectors will be lowered to scalars and this function will be called again.
1384 */
1385 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1386 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1387 si_llvm_emit_store(bld_base, inst, info, index, dst);
1388 return;
1389 }
1390
1391 if (reg->Register.Dimension) {
1392 stride = get_tcs_out_vertex_dw_stride(ctx);
1393 dw_addr = get_tcs_out_current_patch_offset(ctx);
1394 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1395 skip_lds_store = !sh_info->reads_pervertex_outputs;
1396 } else {
1397 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1398 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1399 skip_lds_store = !sh_info->reads_perpatch_outputs;
1400
1401 if (!reg->Register.Indirect) {
1402 int name = sh_info->output_semantic_name[reg->Register.Index];
1403
1404 /* Always write tess factors into LDS for the TCS epilog. */
1405 if (name == TGSI_SEMANTIC_TESSINNER ||
1406 name == TGSI_SEMANTIC_TESSOUTER) {
1407 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1408 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1409 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1410 is_tess_factor = true;
1411 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1412 }
1413 }
1414 }
1415
1416 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1417
1418 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1419 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1420
1421 uint32_t writemask = reg->Register.WriteMask;
1422 while (writemask) {
1423 chan_index = u_bit_scan(&writemask);
1424 LLVMValueRef value = dst[chan_index];
1425
1426 if (inst->Instruction.Saturate)
1427 value = ac_build_clamp(&ctx->ac, value);
1428
1429 /* Skip LDS stores if there is no LDS read of this output. */
1430 if (!skip_lds_store)
1431 lds_store(ctx, chan_index, dw_addr, value);
1432
1433 value = ac_to_integer(&ctx->ac, value);
1434 values[chan_index] = value;
1435
1436 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1437 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1438 buf_addr, base,
1439 4 * chan_index, 1, 0, true, false);
1440 }
1441
1442 /* Write tess factors into VGPRs for the epilog. */
1443 if (is_tess_factor &&
1444 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1445 if (!is_tess_inner) {
1446 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1447 ctx->invoc0_tess_factors[chan_index]);
1448 } else if (chan_index < 2) {
1449 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1450 ctx->invoc0_tess_factors[4 + chan_index]);
1451 }
1452 }
1453 }
1454
1455 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1456 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1457 values, 4);
1458 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1459 base, 0, 1, 0, true, false);
1460 }
1461 }
1462
1463 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1464 const struct nir_variable *var,
1465 LLVMValueRef vertex_index,
1466 LLVMValueRef param_index,
1467 unsigned const_index,
1468 LLVMValueRef src,
1469 unsigned writemask)
1470 {
1471 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1472 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1473 const unsigned component = var->data.location_frac;
1474 const bool is_patch = var->data.patch;
1475 unsigned driver_location = var->data.driver_location;
1476 LLVMValueRef dw_addr, stride;
1477 LLVMValueRef buffer, base, addr;
1478 LLVMValueRef values[4];
1479 bool skip_lds_store;
1480 bool is_tess_factor = false, is_tess_inner = false;
1481
1482 driver_location = driver_location / 4;
1483
1484 if (param_index) {
1485 /* Add the constant index to the indirect index */
1486 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1487 LLVMConstInt(ctx->i32, const_index, 0), "");
1488 } else {
1489 if (const_index != 0)
1490 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1491 }
1492
1493 if (!is_patch) {
1494 stride = get_tcs_out_vertex_dw_stride(ctx);
1495 dw_addr = get_tcs_out_current_patch_offset(ctx);
1496 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1497 vertex_index, param_index,
1498 driver_location,
1499 info->output_semantic_name,
1500 info->output_semantic_index,
1501 is_patch);
1502
1503 skip_lds_store = !info->reads_pervertex_outputs;
1504 } else {
1505 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1506 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1507 vertex_index, param_index,
1508 driver_location,
1509 info->output_semantic_name,
1510 info->output_semantic_index,
1511 is_patch);
1512
1513 skip_lds_store = !info->reads_perpatch_outputs;
1514
1515 if (!param_index) {
1516 int name = info->output_semantic_name[driver_location];
1517
1518 /* Always write tess factors into LDS for the TCS epilog. */
1519 if (name == TGSI_SEMANTIC_TESSINNER ||
1520 name == TGSI_SEMANTIC_TESSOUTER) {
1521 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1522 skip_lds_store = !info->reads_tessfactor_outputs &&
1523 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1524 is_tess_factor = true;
1525 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1526 }
1527 }
1528 }
1529
1530 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1531
1532 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1533
1534 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1535 param_index, driver_location,
1536 info->output_semantic_name,
1537 info->output_semantic_index,
1538 is_patch);
1539
1540 for (unsigned chan = 0; chan < 4; chan++) {
1541 if (!(writemask & (1 << chan)))
1542 continue;
1543 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1544
1545 /* Skip LDS stores if there is no LDS read of this output. */
1546 if (!skip_lds_store)
1547 lds_store(ctx, chan, dw_addr, value);
1548
1549 value = ac_to_integer(&ctx->ac, value);
1550 values[chan] = value;
1551
1552 if (writemask != 0xF && !is_tess_factor) {
1553 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1554 addr, base,
1555 4 * chan, 1, 0, true, false);
1556 }
1557
1558 /* Write tess factors into VGPRs for the epilog. */
1559 if (is_tess_factor &&
1560 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1561 if (!is_tess_inner) {
1562 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1563 ctx->invoc0_tess_factors[chan]);
1564 } else if (chan < 2) {
1565 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1566 ctx->invoc0_tess_factors[4 + chan]);
1567 }
1568 }
1569 }
1570
1571 if (writemask == 0xF && !is_tess_factor) {
1572 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1573 values, 4);
1574 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1575 base, 0, 1, 0, true, false);
1576 }
1577 }
1578
1579 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1580 unsigned input_index,
1581 unsigned vtx_offset_param,
1582 LLVMTypeRef type,
1583 unsigned swizzle)
1584 {
1585 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1586 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1587 struct si_shader *shader = ctx->shader;
1588 LLVMValueRef vtx_offset, soffset;
1589 struct tgsi_shader_info *info = &shader->selector->info;
1590 unsigned semantic_name = info->input_semantic_name[input_index];
1591 unsigned semantic_index = info->input_semantic_index[input_index];
1592 unsigned param;
1593 LLVMValueRef value;
1594
1595 param = si_shader_io_get_unique_index(semantic_name, semantic_index, false);
1596
1597 /* GFX9 has the ESGS ring in LDS. */
1598 if (ctx->screen->info.chip_class >= GFX9) {
1599 unsigned index = vtx_offset_param;
1600
1601 switch (index / 2) {
1602 case 0:
1603 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx01_offset,
1604 index % 2 ? 16 : 0, 16);
1605 break;
1606 case 1:
1607 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx23_offset,
1608 index % 2 ? 16 : 0, 16);
1609 break;
1610 case 2:
1611 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx45_offset,
1612 index % 2 ? 16 : 0, 16);
1613 break;
1614 default:
1615 assert(0);
1616 return NULL;
1617 }
1618
1619 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1620 LLVMConstInt(ctx->i32, param * 4, 0), "");
1621 return lds_load(bld_base, type, swizzle, vtx_offset);
1622 }
1623
1624 /* GFX6: input load from the ESGS ring in memory. */
1625 if (swizzle == ~0) {
1626 LLVMValueRef values[TGSI_NUM_CHANNELS];
1627 unsigned chan;
1628 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1629 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1630 type, chan);
1631 }
1632 return ac_build_gather_values(&ctx->ac, values,
1633 TGSI_NUM_CHANNELS);
1634 }
1635
1636 /* Get the vertex offset parameter on GFX6. */
1637 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1638
1639 vtx_offset = LLVMBuildMul(ctx->ac.builder, gs_vtx_offset,
1640 LLVMConstInt(ctx->i32, 4, 0), "");
1641
1642 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1643
1644 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1645 vtx_offset, soffset, 0, 1, 0, true, false);
1646 if (llvm_type_is_64bit(ctx, type)) {
1647 LLVMValueRef value2;
1648 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1649
1650 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1651 ctx->i32_0, vtx_offset, soffset,
1652 0, 1, 0, true, false);
1653 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1654 }
1655 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1656 }
1657
1658 static LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
1659 unsigned location,
1660 unsigned driver_location,
1661 unsigned component,
1662 unsigned num_components,
1663 unsigned vertex_index,
1664 unsigned const_index,
1665 LLVMTypeRef type)
1666 {
1667 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1668
1669 LLVMValueRef value[4];
1670 for (unsigned i = 0; i < num_components; i++) {
1671 unsigned offset = i;
1672 if (llvm_type_is_64bit(ctx, type))
1673 offset *= 2;
1674
1675 offset += component;
1676 value[i + component] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4,
1677 vertex_index, type, offset);
1678 }
1679
1680 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1681 }
1682
1683 static LLVMValueRef fetch_input_gs(
1684 struct lp_build_tgsi_context *bld_base,
1685 const struct tgsi_full_src_register *reg,
1686 enum tgsi_opcode_type type,
1687 unsigned swizzle_in)
1688 {
1689 struct si_shader_context *ctx = si_shader_context(bld_base);
1690 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1691 unsigned swizzle = swizzle_in & 0xffff;
1692
1693 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1694 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1695 return get_primitive_id(ctx, swizzle);
1696
1697 if (!reg->Register.Dimension)
1698 return NULL;
1699
1700 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1701 reg->Dimension.Index,
1702 tgsi2llvmtype(bld_base, type),
1703 swizzle);
1704 }
1705
1706 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1707 {
1708 switch (interpolate) {
1709 case TGSI_INTERPOLATE_CONSTANT:
1710 return 0;
1711
1712 case TGSI_INTERPOLATE_LINEAR:
1713 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1714 return SI_PARAM_LINEAR_SAMPLE;
1715 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1716 return SI_PARAM_LINEAR_CENTROID;
1717 else
1718 return SI_PARAM_LINEAR_CENTER;
1719 break;
1720 case TGSI_INTERPOLATE_COLOR:
1721 case TGSI_INTERPOLATE_PERSPECTIVE:
1722 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1723 return SI_PARAM_PERSP_SAMPLE;
1724 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1725 return SI_PARAM_PERSP_CENTROID;
1726 else
1727 return SI_PARAM_PERSP_CENTER;
1728 break;
1729 default:
1730 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1731 return -1;
1732 }
1733 }
1734
1735 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1736 unsigned attr_index, unsigned chan,
1737 LLVMValueRef prim_mask,
1738 LLVMValueRef i, LLVMValueRef j)
1739 {
1740 if (i || j) {
1741 return ac_build_fs_interp(&ctx->ac,
1742 LLVMConstInt(ctx->i32, chan, 0),
1743 LLVMConstInt(ctx->i32, attr_index, 0),
1744 prim_mask, i, j);
1745 }
1746 return ac_build_fs_interp_mov(&ctx->ac,
1747 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1748 LLVMConstInt(ctx->i32, chan, 0),
1749 LLVMConstInt(ctx->i32, attr_index, 0),
1750 prim_mask);
1751 }
1752
1753 /**
1754 * Interpolate a fragment shader input.
1755 *
1756 * @param ctx context
1757 * @param input_index index of the input in hardware
1758 * @param semantic_name TGSI_SEMANTIC_*
1759 * @param semantic_index semantic index
1760 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1761 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1762 * @param interp_param interpolation weights (i,j)
1763 * @param prim_mask SI_PARAM_PRIM_MASK
1764 * @param face SI_PARAM_FRONT_FACE
1765 * @param result the return value (4 components)
1766 */
1767 static void interp_fs_input(struct si_shader_context *ctx,
1768 unsigned input_index,
1769 unsigned semantic_name,
1770 unsigned semantic_index,
1771 unsigned num_interp_inputs,
1772 unsigned colors_read_mask,
1773 LLVMValueRef interp_param,
1774 LLVMValueRef prim_mask,
1775 LLVMValueRef face,
1776 LLVMValueRef result[4])
1777 {
1778 LLVMValueRef i = NULL, j = NULL;
1779 unsigned chan;
1780
1781 /* fs.constant returns the param from the middle vertex, so it's not
1782 * really useful for flat shading. It's meant to be used for custom
1783 * interpolation (but the intrinsic can't fetch from the other two
1784 * vertices).
1785 *
1786 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1787 * to do the right thing. The only reason we use fs.constant is that
1788 * fs.interp cannot be used on integers, because they can be equal
1789 * to NaN.
1790 *
1791 * When interp is false we will use fs.constant or for newer llvm,
1792 * amdgcn.interp.mov.
1793 */
1794 bool interp = interp_param != NULL;
1795
1796 if (interp) {
1797 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1798 LLVMVectorType(ctx->f32, 2), "");
1799
1800 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1801 ctx->i32_0, "");
1802 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1803 ctx->i32_1, "");
1804 }
1805
1806 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1807 ctx->shader->key.part.ps.prolog.color_two_side) {
1808 LLVMValueRef is_face_positive;
1809
1810 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1811 * otherwise it's at offset "num_inputs".
1812 */
1813 unsigned back_attr_offset = num_interp_inputs;
1814 if (semantic_index == 1 && colors_read_mask & 0xf)
1815 back_attr_offset += 1;
1816
1817 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1818 face, ctx->i32_0, "");
1819
1820 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1821 LLVMValueRef front, back;
1822
1823 front = si_build_fs_interp(ctx,
1824 input_index, chan,
1825 prim_mask, i, j);
1826 back = si_build_fs_interp(ctx,
1827 back_attr_offset, chan,
1828 prim_mask, i, j);
1829
1830 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1831 is_face_positive,
1832 front,
1833 back,
1834 "");
1835 }
1836 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1837 result[0] = si_build_fs_interp(ctx, input_index,
1838 0, prim_mask, i, j);
1839 result[1] =
1840 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1841 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1842 } else {
1843 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1844 result[chan] = si_build_fs_interp(ctx,
1845 input_index, chan,
1846 prim_mask, i, j);
1847 }
1848 }
1849 }
1850
1851 void si_llvm_load_input_fs(
1852 struct si_shader_context *ctx,
1853 unsigned input_index,
1854 LLVMValueRef out[4])
1855 {
1856 struct si_shader *shader = ctx->shader;
1857 struct tgsi_shader_info *info = &shader->selector->info;
1858 LLVMValueRef main_fn = ctx->main_fn;
1859 LLVMValueRef interp_param = NULL;
1860 int interp_param_idx;
1861 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1862 unsigned semantic_index = info->input_semantic_index[input_index];
1863 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1864 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1865
1866 /* Get colors from input VGPRs (set by the prolog). */
1867 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1868 unsigned colors_read = shader->selector->info.colors_read;
1869 unsigned mask = colors_read >> (semantic_index * 4);
1870 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1871 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1872 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1873
1874 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1875 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1876 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1877 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1878 return;
1879 }
1880
1881 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1882 if (interp_param_idx == -1)
1883 return;
1884 else if (interp_param_idx) {
1885 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1886 }
1887
1888 interp_fs_input(ctx, input_index, semantic_name,
1889 semantic_index, 0, /* this param is unused */
1890 shader->selector->info.colors_read, interp_param,
1891 ctx->abi.prim_mask,
1892 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1893 &out[0]);
1894 }
1895
1896 static void declare_input_fs(
1897 struct si_shader_context *ctx,
1898 unsigned input_index,
1899 const struct tgsi_full_declaration *decl,
1900 LLVMValueRef out[4])
1901 {
1902 si_llvm_load_input_fs(ctx, input_index, out);
1903 }
1904
1905 LLVMValueRef si_get_sample_id(struct si_shader_context *ctx)
1906 {
1907 return si_unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1908 }
1909
1910 static LLVMValueRef get_base_vertex(struct ac_shader_abi *abi)
1911 {
1912 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1913
1914 /* For non-indexed draws, the base vertex set by the driver
1915 * (for direct draws) or the CP (for indirect draws) is the
1916 * first vertex ID, but GLSL expects 0 to be returned.
1917 */
1918 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn,
1919 ctx->param_vs_state_bits);
1920 LLVMValueRef indexed;
1921
1922 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1923 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1924
1925 return LLVMBuildSelect(ctx->ac.builder, indexed, ctx->abi.base_vertex,
1926 ctx->i32_0, "");
1927 }
1928
1929 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1930 {
1931 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1932
1933 LLVMValueRef values[3];
1934 LLVMValueRef result;
1935 unsigned i;
1936 unsigned *properties = ctx->shader->selector->info.properties;
1937
1938 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1939 unsigned sizes[3] = {
1940 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1941 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1942 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1943 };
1944
1945 for (i = 0; i < 3; ++i)
1946 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1947
1948 result = ac_build_gather_values(&ctx->ac, values, 3);
1949 } else {
1950 result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1951 }
1952
1953 return result;
1954 }
1955
1956 /**
1957 * Load a dword from a constant buffer.
1958 */
1959 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1960 LLVMValueRef resource,
1961 LLVMValueRef offset)
1962 {
1963 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1964 0, 0, 0, true, true);
1965 }
1966
1967 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1968 {
1969 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1970 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1971 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1972 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1973
1974 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1975 LLVMValueRef offset0 = LLVMBuildMul(ctx->ac.builder, sample_id, LLVMConstInt(ctx->i32, 8, 0), "");
1976 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1977
1978 LLVMValueRef pos[4] = {
1979 buffer_load_const(ctx, resource, offset0),
1980 buffer_load_const(ctx, resource, offset1),
1981 LLVMConstReal(ctx->f32, 0),
1982 LLVMConstReal(ctx->f32, 0)
1983 };
1984
1985 return ac_build_gather_values(&ctx->ac, pos, 4);
1986 }
1987
1988 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1989 {
1990 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1991 return ac_to_integer(&ctx->ac, abi->sample_coverage);
1992 }
1993
1994 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
1995 {
1996 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1997 LLVMValueRef coord[4] = {
1998 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1999 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
2000 ctx->ac.f32_0,
2001 ctx->ac.f32_0
2002 };
2003
2004 /* For triangles, the vector should be (u, v, 1-u-v). */
2005 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
2006 PIPE_PRIM_TRIANGLES) {
2007 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
2008 LLVMBuildFAdd(ctx->ac.builder,
2009 coord[0], coord[1], ""), "");
2010 }
2011 return ac_build_gather_values(&ctx->ac, coord, 4);
2012 }
2013
2014 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
2015 unsigned semantic_name)
2016 {
2017 LLVMValueRef base, addr;
2018
2019 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
2020
2021 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2022 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
2023 LLVMConstInt(ctx->i32, param, 0));
2024
2025 return buffer_load(&ctx->bld_base, ctx->f32,
2026 ~0, ctx->tess_offchip_ring, base, addr, true);
2027
2028 }
2029
2030 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
2031 unsigned varying_id)
2032 {
2033 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2034 unsigned semantic_name;
2035
2036 switch (varying_id) {
2037 case VARYING_SLOT_TESS_LEVEL_INNER:
2038 semantic_name = TGSI_SEMANTIC_TESSINNER;
2039 break;
2040 case VARYING_SLOT_TESS_LEVEL_OUTER:
2041 semantic_name = TGSI_SEMANTIC_TESSOUTER;
2042 break;
2043 default:
2044 unreachable("unknown tess level");
2045 }
2046
2047 return load_tess_level(ctx, semantic_name);
2048
2049 }
2050
2051 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
2052 {
2053 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2054 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2055 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
2056 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
2057 return get_num_tcs_out_vertices(ctx);
2058 else
2059 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2060 }
2061
2062 void si_load_system_value(struct si_shader_context *ctx,
2063 unsigned index,
2064 const struct tgsi_full_declaration *decl)
2065 {
2066 LLVMValueRef value = 0;
2067
2068 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
2069
2070 switch (decl->Semantic.Name) {
2071 case TGSI_SEMANTIC_INSTANCEID:
2072 value = ctx->abi.instance_id;
2073 break;
2074
2075 case TGSI_SEMANTIC_VERTEXID:
2076 value = LLVMBuildAdd(ctx->ac.builder,
2077 ctx->abi.vertex_id,
2078 ctx->abi.base_vertex, "");
2079 break;
2080
2081 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2082 /* Unused. Clarify the meaning in indexed vs. non-indexed
2083 * draws if this is ever used again. */
2084 assert(false);
2085 break;
2086
2087 case TGSI_SEMANTIC_BASEVERTEX:
2088 value = get_base_vertex(&ctx->abi);
2089 break;
2090
2091 case TGSI_SEMANTIC_BASEINSTANCE:
2092 value = ctx->abi.start_instance;
2093 break;
2094
2095 case TGSI_SEMANTIC_DRAWID:
2096 value = ctx->abi.draw_id;
2097 break;
2098
2099 case TGSI_SEMANTIC_INVOCATIONID:
2100 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2101 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2102 else if (ctx->type == PIPE_SHADER_GEOMETRY)
2103 value = ctx->abi.gs_invocation_id;
2104 else
2105 assert(!"INVOCATIONID not implemented");
2106 break;
2107
2108 case TGSI_SEMANTIC_POSITION:
2109 {
2110 LLVMValueRef pos[4] = {
2111 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2112 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2113 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2114 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2115 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT)),
2116 };
2117 value = ac_build_gather_values(&ctx->ac, pos, 4);
2118 break;
2119 }
2120
2121 case TGSI_SEMANTIC_FACE:
2122 value = ctx->abi.front_face;
2123 break;
2124
2125 case TGSI_SEMANTIC_SAMPLEID:
2126 value = si_get_sample_id(ctx);
2127 break;
2128
2129 case TGSI_SEMANTIC_SAMPLEPOS: {
2130 LLVMValueRef pos[4] = {
2131 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2132 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2133 LLVMConstReal(ctx->f32, 0),
2134 LLVMConstReal(ctx->f32, 0)
2135 };
2136 pos[0] = ac_build_fract(&ctx->ac, pos[0], 32);
2137 pos[1] = ac_build_fract(&ctx->ac, pos[1], 32);
2138 value = ac_build_gather_values(&ctx->ac, pos, 4);
2139 break;
2140 }
2141
2142 case TGSI_SEMANTIC_SAMPLEMASK:
2143 /* This can only occur with the OpenGL Core profile, which
2144 * doesn't support smoothing.
2145 */
2146 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2147 break;
2148
2149 case TGSI_SEMANTIC_TESSCOORD:
2150 value = si_load_tess_coord(&ctx->abi);
2151 break;
2152
2153 case TGSI_SEMANTIC_VERTICESIN:
2154 value = si_load_patch_vertices_in(&ctx->abi);
2155 break;
2156
2157 case TGSI_SEMANTIC_TESSINNER:
2158 case TGSI_SEMANTIC_TESSOUTER:
2159 value = load_tess_level(ctx, decl->Semantic.Name);
2160 break;
2161
2162 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
2163 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
2164 {
2165 LLVMValueRef buf, slot, val[4];
2166 int i, offset;
2167
2168 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
2169 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2170 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
2171 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
2172
2173 for (i = 0; i < 4; i++)
2174 val[i] = buffer_load_const(ctx, buf,
2175 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
2176 value = ac_build_gather_values(&ctx->ac, val, 4);
2177 break;
2178 }
2179
2180 case TGSI_SEMANTIC_PRIMID:
2181 value = get_primitive_id(ctx, 0);
2182 break;
2183
2184 case TGSI_SEMANTIC_GRID_SIZE:
2185 value = ctx->abi.num_work_groups;
2186 break;
2187
2188 case TGSI_SEMANTIC_BLOCK_SIZE:
2189 value = get_block_size(&ctx->abi);
2190 break;
2191
2192 case TGSI_SEMANTIC_BLOCK_ID:
2193 {
2194 LLVMValueRef values[3];
2195
2196 for (int i = 0; i < 3; i++) {
2197 values[i] = ctx->i32_0;
2198 if (ctx->abi.workgroup_ids[i]) {
2199 values[i] = ctx->abi.workgroup_ids[i];
2200 }
2201 }
2202 value = ac_build_gather_values(&ctx->ac, values, 3);
2203 break;
2204 }
2205
2206 case TGSI_SEMANTIC_THREAD_ID:
2207 value = ctx->abi.local_invocation_ids;
2208 break;
2209
2210 case TGSI_SEMANTIC_HELPER_INVOCATION:
2211 value = ac_build_intrinsic(&ctx->ac,
2212 "llvm.amdgcn.ps.live",
2213 ctx->i1, NULL, 0,
2214 AC_FUNC_ATTR_READNONE);
2215 value = LLVMBuildNot(ctx->ac.builder, value, "");
2216 value = LLVMBuildSExt(ctx->ac.builder, value, ctx->i32, "");
2217 break;
2218
2219 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2220 value = LLVMConstInt(ctx->i32, 64, 0);
2221 break;
2222
2223 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2224 value = ac_get_thread_id(&ctx->ac);
2225 break;
2226
2227 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2228 {
2229 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2230 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2231 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
2232 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2233 break;
2234 }
2235
2236 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2237 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2238 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2239 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2240 {
2241 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2242 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2243 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2244 /* All bits set except LSB */
2245 value = LLVMConstInt(ctx->i64, -2, 0);
2246 } else {
2247 /* All bits set */
2248 value = LLVMConstInt(ctx->i64, -1, 0);
2249 }
2250 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2251 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2252 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2253 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2254 value = LLVMBuildNot(ctx->ac.builder, value, "");
2255 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2256 break;
2257 }
2258
2259 case TGSI_SEMANTIC_CS_USER_DATA:
2260 value = LLVMGetParam(ctx->main_fn, ctx->param_cs_user_data);
2261 break;
2262
2263 default:
2264 assert(!"unknown system value");
2265 return;
2266 }
2267
2268 ctx->system_values[index] = value;
2269 }
2270
2271 void si_declare_compute_memory(struct si_shader_context *ctx)
2272 {
2273 struct si_shader_selector *sel = ctx->shader->selector;
2274 unsigned lds_size = sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE];
2275
2276 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_ADDR_SPACE_LDS);
2277 LLVMValueRef var;
2278
2279 assert(!ctx->ac.lds);
2280
2281 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2282 LLVMArrayType(ctx->i8, lds_size),
2283 "compute_lds",
2284 AC_ADDR_SPACE_LDS);
2285 LLVMSetAlignment(var, 4);
2286
2287 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2288 }
2289
2290 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
2291 const struct tgsi_full_declaration *decl)
2292 {
2293 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2294 assert(decl->Range.First == decl->Range.Last);
2295
2296 si_declare_compute_memory(ctx);
2297 }
2298
2299 static LLVMValueRef load_const_buffer_desc_fast_path(struct si_shader_context *ctx)
2300 {
2301 LLVMValueRef ptr =
2302 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2303 struct si_shader_selector *sel = ctx->shader->selector;
2304
2305 /* Do the bounds checking with a descriptor, because
2306 * doing computation and manual bounds checking of 64-bit
2307 * addresses generates horrible VALU code with very high
2308 * VGPR usage and very low SIMD occupancy.
2309 */
2310 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->ac.intptr, "");
2311
2312 LLVMValueRef desc0, desc1;
2313 if (HAVE_32BIT_POINTERS) {
2314 desc0 = ptr;
2315 desc1 = LLVMConstInt(ctx->i32,
2316 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
2317 } else {
2318 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ctx->v2i32, "");
2319 desc0 = LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_0, "");
2320 desc1 = LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_1, "");
2321 /* Mask out all bits except BASE_ADDRESS_HI. */
2322 desc1 = LLVMBuildAnd(ctx->ac.builder, desc1,
2323 LLVMConstInt(ctx->i32, ~C_008F04_BASE_ADDRESS_HI, 0), "");
2324 }
2325
2326 LLVMValueRef desc_elems[] = {
2327 desc0,
2328 desc1,
2329 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2330 LLVMConstInt(ctx->i32,
2331 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2332 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2333 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2334 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2335 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2336 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2337 };
2338
2339 return ac_build_gather_values(&ctx->ac, desc_elems, 4);
2340 }
2341
2342 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2343 {
2344 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2345 ctx->param_const_and_shader_buffers);
2346
2347 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2348 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2349 }
2350
2351 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2352 {
2353 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2354 struct si_shader_selector *sel = ctx->shader->selector;
2355
2356 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2357
2358 if (sel->info.const_buffers_declared == 1 &&
2359 sel->info.shader_buffers_declared == 0) {
2360 return load_const_buffer_desc_fast_path(ctx);
2361 }
2362
2363 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2364 index = LLVMBuildAdd(ctx->ac.builder, index,
2365 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2366
2367 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2368 }
2369
2370 static LLVMValueRef
2371 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2372 {
2373 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2374 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2375 ctx->param_const_and_shader_buffers);
2376
2377 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2378 index = LLVMBuildSub(ctx->ac.builder,
2379 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2380 index, "");
2381
2382 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2383 }
2384
2385 static LLVMValueRef fetch_constant(
2386 struct lp_build_tgsi_context *bld_base,
2387 const struct tgsi_full_src_register *reg,
2388 enum tgsi_opcode_type type,
2389 unsigned swizzle_in)
2390 {
2391 struct si_shader_context *ctx = si_shader_context(bld_base);
2392 struct si_shader_selector *sel = ctx->shader->selector;
2393 const struct tgsi_ind_register *ireg = &reg->Indirect;
2394 unsigned buf, idx;
2395 unsigned swizzle = swizzle_in & 0xffff;
2396
2397 LLVMValueRef addr, bufp;
2398
2399 if (swizzle_in == LP_CHAN_ALL) {
2400 unsigned chan;
2401 LLVMValueRef values[4];
2402 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2403 values[chan] = fetch_constant(bld_base, reg, type, chan);
2404
2405 return ac_build_gather_values(&ctx->ac, values, 4);
2406 }
2407
2408 /* Split 64-bit loads. */
2409 if (tgsi_type_is_64bit(type)) {
2410 LLVMValueRef lo, hi;
2411
2412 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2413 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, (swizzle_in >> 16));
2414 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2415 lo, hi);
2416 }
2417
2418 idx = reg->Register.Index * 4 + swizzle;
2419 if (reg->Register.Indirect) {
2420 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2421 } else {
2422 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2423 }
2424
2425 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2426 if (sel->info.const_buffers_declared == 1 &&
2427 sel->info.shader_buffers_declared == 0) {
2428 LLVMValueRef desc = load_const_buffer_desc_fast_path(ctx);
2429 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2430 return bitcast(bld_base, type, result);
2431 }
2432
2433 assert(reg->Register.Dimension);
2434 buf = reg->Dimension.Index;
2435
2436 if (reg->Dimension.Indirect) {
2437 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2438 LLVMValueRef index;
2439 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2440 reg->Dimension.Index,
2441 ctx->num_const_buffers);
2442 index = LLVMBuildAdd(ctx->ac.builder, index,
2443 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2444 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2445 } else
2446 bufp = load_const_buffer_desc(ctx, buf);
2447
2448 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2449 }
2450
2451 /* Initialize arguments for the shader export intrinsic */
2452 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2453 LLVMValueRef *values,
2454 unsigned target,
2455 struct ac_export_args *args)
2456 {
2457 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2458 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2459 unsigned chan;
2460 bool is_int8, is_int10;
2461
2462 /* Default is 0xf. Adjusted below depending on the format. */
2463 args->enabled_channels = 0xf; /* writemask */
2464
2465 /* Specify whether the EXEC mask represents the valid mask */
2466 args->valid_mask = 0;
2467
2468 /* Specify whether this is the last export */
2469 args->done = 0;
2470
2471 /* Specify the target we are exporting */
2472 args->target = target;
2473
2474 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2475 const struct si_shader_key *key = &ctx->shader->key;
2476 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2477 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2478
2479 assert(cbuf >= 0 && cbuf < 8);
2480 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2481 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2482 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2483 }
2484
2485 args->compr = false;
2486 args->out[0] = f32undef;
2487 args->out[1] = f32undef;
2488 args->out[2] = f32undef;
2489 args->out[3] = f32undef;
2490
2491 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2492 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2493 unsigned bits, bool hi) = NULL;
2494
2495 switch (spi_shader_col_format) {
2496 case V_028714_SPI_SHADER_ZERO:
2497 args->enabled_channels = 0; /* writemask */
2498 args->target = V_008DFC_SQ_EXP_NULL;
2499 break;
2500
2501 case V_028714_SPI_SHADER_32_R:
2502 args->enabled_channels = 1; /* writemask */
2503 args->out[0] = values[0];
2504 break;
2505
2506 case V_028714_SPI_SHADER_32_GR:
2507 args->enabled_channels = 0x3; /* writemask */
2508 args->out[0] = values[0];
2509 args->out[1] = values[1];
2510 break;
2511
2512 case V_028714_SPI_SHADER_32_AR:
2513 args->enabled_channels = 0x9; /* writemask */
2514 args->out[0] = values[0];
2515 args->out[3] = values[3];
2516 break;
2517
2518 case V_028714_SPI_SHADER_FP16_ABGR:
2519 packf = ac_build_cvt_pkrtz_f16;
2520 break;
2521
2522 case V_028714_SPI_SHADER_UNORM16_ABGR:
2523 packf = ac_build_cvt_pknorm_u16;
2524 break;
2525
2526 case V_028714_SPI_SHADER_SNORM16_ABGR:
2527 packf = ac_build_cvt_pknorm_i16;
2528 break;
2529
2530 case V_028714_SPI_SHADER_UINT16_ABGR:
2531 packi = ac_build_cvt_pk_u16;
2532 break;
2533
2534 case V_028714_SPI_SHADER_SINT16_ABGR:
2535 packi = ac_build_cvt_pk_i16;
2536 break;
2537
2538 case V_028714_SPI_SHADER_32_ABGR:
2539 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2540 break;
2541 }
2542
2543 /* Pack f16 or norm_i16/u16. */
2544 if (packf) {
2545 for (chan = 0; chan < 2; chan++) {
2546 LLVMValueRef pack_args[2] = {
2547 values[2 * chan],
2548 values[2 * chan + 1]
2549 };
2550 LLVMValueRef packed;
2551
2552 packed = packf(&ctx->ac, pack_args);
2553 args->out[chan] = ac_to_float(&ctx->ac, packed);
2554 }
2555 args->compr = 1; /* COMPR flag */
2556 }
2557 /* Pack i16/u16. */
2558 if (packi) {
2559 for (chan = 0; chan < 2; chan++) {
2560 LLVMValueRef pack_args[2] = {
2561 ac_to_integer(&ctx->ac, values[2 * chan]),
2562 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2563 };
2564 LLVMValueRef packed;
2565
2566 packed = packi(&ctx->ac, pack_args,
2567 is_int8 ? 8 : is_int10 ? 10 : 16,
2568 chan == 1);
2569 args->out[chan] = ac_to_float(&ctx->ac, packed);
2570 }
2571 args->compr = 1; /* COMPR flag */
2572 }
2573 }
2574
2575 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2576 LLVMValueRef alpha)
2577 {
2578 struct si_shader_context *ctx = si_shader_context(bld_base);
2579
2580 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2581 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2582 [PIPE_FUNC_LESS] = LLVMRealOLT,
2583 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2584 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2585 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2586 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2587 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2588 };
2589 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2590 assert(cond);
2591
2592 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2593 SI_PARAM_ALPHA_REF);
2594 LLVMValueRef alpha_pass =
2595 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2596 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2597 } else {
2598 ac_build_kill_if_false(&ctx->ac, ctx->i1false);
2599 }
2600 }
2601
2602 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2603 LLVMValueRef alpha,
2604 unsigned samplemask_param)
2605 {
2606 struct si_shader_context *ctx = si_shader_context(bld_base);
2607 LLVMValueRef coverage;
2608
2609 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2610 coverage = LLVMGetParam(ctx->main_fn,
2611 samplemask_param);
2612 coverage = ac_to_integer(&ctx->ac, coverage);
2613
2614 coverage = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32",
2615 ctx->i32,
2616 &coverage, 1, AC_FUNC_ATTR_READNONE);
2617
2618 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2619 ctx->f32, "");
2620
2621 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2622 LLVMConstReal(ctx->f32,
2623 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2624
2625 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2626 }
2627
2628 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2629 struct ac_export_args *pos, LLVMValueRef *out_elts)
2630 {
2631 unsigned reg_index;
2632 unsigned chan;
2633 unsigned const_chan;
2634 LLVMValueRef base_elt;
2635 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2636 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2637 SI_VS_CONST_CLIP_PLANES, 0);
2638 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2639
2640 for (reg_index = 0; reg_index < 2; reg_index ++) {
2641 struct ac_export_args *args = &pos[2 + reg_index];
2642
2643 args->out[0] =
2644 args->out[1] =
2645 args->out[2] =
2646 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2647
2648 /* Compute dot products of position and user clip plane vectors */
2649 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2650 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2651 LLVMValueRef addr =
2652 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2653 const_chan) * 4, 0);
2654 base_elt = buffer_load_const(ctx, const_resource,
2655 addr);
2656 args->out[chan] = ac_build_fmad(&ctx->ac, base_elt,
2657 out_elts[const_chan], args->out[chan]);
2658 }
2659 }
2660
2661 args->enabled_channels = 0xf;
2662 args->valid_mask = 0;
2663 args->done = 0;
2664 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2665 args->compr = 0;
2666 }
2667 }
2668
2669 static void si_dump_streamout(struct pipe_stream_output_info *so)
2670 {
2671 unsigned i;
2672
2673 if (so->num_outputs)
2674 fprintf(stderr, "STREAMOUT\n");
2675
2676 for (i = 0; i < so->num_outputs; i++) {
2677 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2678 so->output[i].start_component;
2679 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2680 i, so->output[i].output_buffer,
2681 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2682 so->output[i].register_index,
2683 mask & 1 ? "x" : "",
2684 mask & 2 ? "y" : "",
2685 mask & 4 ? "z" : "",
2686 mask & 8 ? "w" : "");
2687 }
2688 }
2689
2690 static void emit_streamout_output(struct si_shader_context *ctx,
2691 LLVMValueRef const *so_buffers,
2692 LLVMValueRef const *so_write_offsets,
2693 struct pipe_stream_output *stream_out,
2694 struct si_shader_output_values *shader_out)
2695 {
2696 unsigned buf_idx = stream_out->output_buffer;
2697 unsigned start = stream_out->start_component;
2698 unsigned num_comps = stream_out->num_components;
2699 LLVMValueRef out[4];
2700
2701 assert(num_comps && num_comps <= 4);
2702 if (!num_comps || num_comps > 4)
2703 return;
2704
2705 /* Load the output as int. */
2706 for (int j = 0; j < num_comps; j++) {
2707 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2708
2709 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2710 }
2711
2712 /* Pack the output. */
2713 LLVMValueRef vdata = NULL;
2714
2715 switch (num_comps) {
2716 case 1: /* as i32 */
2717 vdata = out[0];
2718 break;
2719 case 2: /* as v2i32 */
2720 case 3: /* as v4i32 (aligned to 4) */
2721 out[3] = LLVMGetUndef(ctx->i32);
2722 /* fall through */
2723 case 4: /* as v4i32 */
2724 vdata = ac_build_gather_values(&ctx->ac, out, util_next_power_of_two(num_comps));
2725 break;
2726 }
2727
2728 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2729 vdata, num_comps,
2730 so_write_offsets[buf_idx],
2731 ctx->i32_0,
2732 stream_out->dst_offset * 4, 1, 1, true, false);
2733 }
2734
2735 /**
2736 * Write streamout data to buffers for vertex stream @p stream (different
2737 * vertex streams can occur for GS copy shaders).
2738 */
2739 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2740 struct si_shader_output_values *outputs,
2741 unsigned noutput, unsigned stream)
2742 {
2743 struct si_shader_selector *sel = ctx->shader->selector;
2744 struct pipe_stream_output_info *so = &sel->so;
2745 LLVMBuilderRef builder = ctx->ac.builder;
2746 int i;
2747 struct lp_build_if_state if_ctx;
2748
2749 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2750 LLVMValueRef so_vtx_count =
2751 si_unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2752
2753 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2754
2755 /* can_emit = tid < so_vtx_count; */
2756 LLVMValueRef can_emit =
2757 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2758
2759 /* Emit the streamout code conditionally. This actually avoids
2760 * out-of-bounds buffer access. The hw tells us via the SGPR
2761 * (so_vtx_count) which threads are allowed to emit streamout data. */
2762 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2763 {
2764 /* The buffer offset is computed as follows:
2765 * ByteOffset = streamout_offset[buffer_id]*4 +
2766 * (streamout_write_index + thread_id)*stride[buffer_id] +
2767 * attrib_offset
2768 */
2769
2770 LLVMValueRef so_write_index =
2771 LLVMGetParam(ctx->main_fn,
2772 ctx->param_streamout_write_index);
2773
2774 /* Compute (streamout_write_index + thread_id). */
2775 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2776
2777 /* Load the descriptor and compute the write offset for each
2778 * enabled buffer. */
2779 LLVMValueRef so_write_offset[4] = {};
2780 LLVMValueRef so_buffers[4];
2781 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2782 ctx->param_rw_buffers);
2783
2784 for (i = 0; i < 4; i++) {
2785 if (!so->stride[i])
2786 continue;
2787
2788 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2789 SI_VS_STREAMOUT_BUF0 + i, 0);
2790
2791 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2792
2793 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2794 ctx->param_streamout_offset[i]);
2795 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2796
2797 so_write_offset[i] = ac_build_imad(&ctx->ac, so_write_index,
2798 LLVMConstInt(ctx->i32, so->stride[i]*4, 0),
2799 so_offset);
2800 }
2801
2802 /* Write streamout data. */
2803 for (i = 0; i < so->num_outputs; i++) {
2804 unsigned reg = so->output[i].register_index;
2805
2806 if (reg >= noutput)
2807 continue;
2808
2809 if (stream != so->output[i].stream)
2810 continue;
2811
2812 emit_streamout_output(ctx, so_buffers, so_write_offset,
2813 &so->output[i], &outputs[reg]);
2814 }
2815 }
2816 lp_build_endif(&if_ctx);
2817 }
2818
2819 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2820 LLVMValueRef *values)
2821 {
2822 struct ac_export_args args;
2823
2824 si_llvm_init_export_args(ctx, values,
2825 V_008DFC_SQ_EXP_PARAM + index, &args);
2826 ac_build_export(&ctx->ac, &args);
2827 }
2828
2829 static void si_build_param_exports(struct si_shader_context *ctx,
2830 struct si_shader_output_values *outputs,
2831 unsigned noutput)
2832 {
2833 struct si_shader *shader = ctx->shader;
2834 unsigned param_count = 0;
2835
2836 for (unsigned i = 0; i < noutput; i++) {
2837 unsigned semantic_name = outputs[i].semantic_name;
2838 unsigned semantic_index = outputs[i].semantic_index;
2839
2840 if (outputs[i].vertex_stream[0] != 0 &&
2841 outputs[i].vertex_stream[1] != 0 &&
2842 outputs[i].vertex_stream[2] != 0 &&
2843 outputs[i].vertex_stream[3] != 0)
2844 continue;
2845
2846 switch (semantic_name) {
2847 case TGSI_SEMANTIC_LAYER:
2848 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2849 case TGSI_SEMANTIC_CLIPDIST:
2850 case TGSI_SEMANTIC_COLOR:
2851 case TGSI_SEMANTIC_BCOLOR:
2852 case TGSI_SEMANTIC_PRIMID:
2853 case TGSI_SEMANTIC_FOG:
2854 case TGSI_SEMANTIC_TEXCOORD:
2855 case TGSI_SEMANTIC_GENERIC:
2856 break;
2857 default:
2858 continue;
2859 }
2860
2861 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2862 semantic_index < SI_MAX_IO_GENERIC) &&
2863 shader->key.opt.kill_outputs &
2864 (1ull << si_shader_io_get_unique_index(semantic_name,
2865 semantic_index, true)))
2866 continue;
2867
2868 si_export_param(ctx, param_count, outputs[i].values);
2869
2870 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2871 shader->info.vs_output_param_offset[i] = param_count++;
2872 }
2873
2874 shader->info.nr_param_exports = param_count;
2875 }
2876
2877 /* Generate export instructions for hardware VS shader stage */
2878 static void si_llvm_export_vs(struct si_shader_context *ctx,
2879 struct si_shader_output_values *outputs,
2880 unsigned noutput)
2881 {
2882 struct si_shader *shader = ctx->shader;
2883 struct ac_export_args pos_args[4] = {};
2884 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2885 unsigned pos_idx;
2886 int i;
2887
2888 /* Build position exports. */
2889 for (i = 0; i < noutput; i++) {
2890 switch (outputs[i].semantic_name) {
2891 case TGSI_SEMANTIC_POSITION:
2892 si_llvm_init_export_args(ctx, outputs[i].values,
2893 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2894 break;
2895 case TGSI_SEMANTIC_PSIZE:
2896 psize_value = outputs[i].values[0];
2897 break;
2898 case TGSI_SEMANTIC_LAYER:
2899 layer_value = outputs[i].values[0];
2900 break;
2901 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2902 viewport_index_value = outputs[i].values[0];
2903 break;
2904 case TGSI_SEMANTIC_EDGEFLAG:
2905 edgeflag_value = outputs[i].values[0];
2906 break;
2907 case TGSI_SEMANTIC_CLIPDIST:
2908 if (!shader->key.opt.clip_disable) {
2909 unsigned index = 2 + outputs[i].semantic_index;
2910 si_llvm_init_export_args(ctx, outputs[i].values,
2911 V_008DFC_SQ_EXP_POS + index,
2912 &pos_args[index]);
2913 }
2914 break;
2915 case TGSI_SEMANTIC_CLIPVERTEX:
2916 if (!shader->key.opt.clip_disable) {
2917 si_llvm_emit_clipvertex(ctx, pos_args,
2918 outputs[i].values);
2919 }
2920 break;
2921 }
2922 }
2923
2924 /* We need to add the position output manually if it's missing. */
2925 if (!pos_args[0].out[0]) {
2926 pos_args[0].enabled_channels = 0xf; /* writemask */
2927 pos_args[0].valid_mask = 0; /* EXEC mask */
2928 pos_args[0].done = 0; /* last export? */
2929 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2930 pos_args[0].compr = 0; /* COMPR flag */
2931 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2932 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2933 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2934 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2935 }
2936
2937 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2938 if (shader->selector->info.writes_psize ||
2939 shader->selector->info.writes_edgeflag ||
2940 shader->selector->info.writes_viewport_index ||
2941 shader->selector->info.writes_layer) {
2942 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2943 (shader->selector->info.writes_edgeflag << 1) |
2944 (shader->selector->info.writes_layer << 2);
2945
2946 pos_args[1].valid_mask = 0; /* EXEC mask */
2947 pos_args[1].done = 0; /* last export? */
2948 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2949 pos_args[1].compr = 0; /* COMPR flag */
2950 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2951 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2952 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2953 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2954
2955 if (shader->selector->info.writes_psize)
2956 pos_args[1].out[0] = psize_value;
2957
2958 if (shader->selector->info.writes_edgeflag) {
2959 /* The output is a float, but the hw expects an integer
2960 * with the first bit containing the edge flag. */
2961 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2962 edgeflag_value,
2963 ctx->i32, "");
2964 edgeflag_value = ac_build_umin(&ctx->ac,
2965 edgeflag_value,
2966 ctx->i32_1);
2967
2968 /* The LLVM intrinsic expects a float. */
2969 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2970 }
2971
2972 if (ctx->screen->info.chip_class >= GFX9) {
2973 /* GFX9 has the layer in out.z[10:0] and the viewport
2974 * index in out.z[19:16].
2975 */
2976 if (shader->selector->info.writes_layer)
2977 pos_args[1].out[2] = layer_value;
2978
2979 if (shader->selector->info.writes_viewport_index) {
2980 LLVMValueRef v = viewport_index_value;
2981
2982 v = ac_to_integer(&ctx->ac, v);
2983 v = LLVMBuildShl(ctx->ac.builder, v,
2984 LLVMConstInt(ctx->i32, 16, 0), "");
2985 v = LLVMBuildOr(ctx->ac.builder, v,
2986 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2987 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2988 pos_args[1].enabled_channels |= 1 << 2;
2989 }
2990 } else {
2991 if (shader->selector->info.writes_layer)
2992 pos_args[1].out[2] = layer_value;
2993
2994 if (shader->selector->info.writes_viewport_index) {
2995 pos_args[1].out[3] = viewport_index_value;
2996 pos_args[1].enabled_channels |= 1 << 3;
2997 }
2998 }
2999 }
3000
3001 for (i = 0; i < 4; i++)
3002 if (pos_args[i].out[0])
3003 shader->info.nr_pos_exports++;
3004
3005 pos_idx = 0;
3006 for (i = 0; i < 4; i++) {
3007 if (!pos_args[i].out[0])
3008 continue;
3009
3010 /* Specify the target we are exporting */
3011 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
3012
3013 if (pos_idx == shader->info.nr_pos_exports)
3014 /* Specify that this is the last export */
3015 pos_args[i].done = 1;
3016
3017 ac_build_export(&ctx->ac, &pos_args[i]);
3018 }
3019
3020 /* Build parameter exports. */
3021 si_build_param_exports(ctx, outputs, noutput);
3022 }
3023
3024 /**
3025 * Forward all outputs from the vertex shader to the TES. This is only used
3026 * for the fixed function TCS.
3027 */
3028 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
3029 {
3030 struct si_shader_context *ctx = si_shader_context(bld_base);
3031 LLVMValueRef invocation_id, buffer, buffer_offset;
3032 LLVMValueRef lds_vertex_stride, lds_base;
3033 uint64_t inputs;
3034
3035 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3036 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3037 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3038
3039 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
3040 lds_base = get_tcs_in_current_patch_offset(ctx);
3041 lds_base = ac_build_imad(&ctx->ac, invocation_id, lds_vertex_stride,
3042 lds_base);
3043
3044 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
3045 while (inputs) {
3046 unsigned i = u_bit_scan64(&inputs);
3047
3048 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
3049 LLVMConstInt(ctx->i32, 4 * i, 0),
3050 "");
3051
3052 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
3053 get_rel_patch_id(ctx),
3054 invocation_id,
3055 LLVMConstInt(ctx->i32, i, 0));
3056
3057 LLVMValueRef value = lds_load(bld_base, ctx->ac.i32, ~0,
3058 lds_ptr);
3059
3060 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
3061 buffer_offset, 0, 1, 0, true, false);
3062 }
3063 }
3064
3065 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
3066 LLVMValueRef rel_patch_id,
3067 LLVMValueRef invocation_id,
3068 LLVMValueRef tcs_out_current_patch_data_offset,
3069 LLVMValueRef invoc0_tf_outer[4],
3070 LLVMValueRef invoc0_tf_inner[2])
3071 {
3072 struct si_shader_context *ctx = si_shader_context(bld_base);
3073 struct si_shader *shader = ctx->shader;
3074 unsigned tess_inner_index, tess_outer_index;
3075 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
3076 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3077 unsigned stride, outer_comps, inner_comps, i, offset;
3078 struct lp_build_if_state if_ctx, inner_if_ctx;
3079
3080 /* Add a barrier before loading tess factors from LDS. */
3081 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
3082 si_llvm_emit_barrier(NULL, bld_base, NULL);
3083
3084 /* Do this only for invocation 0, because the tess levels are per-patch,
3085 * not per-vertex.
3086 *
3087 * This can't jump, because invocation 0 executes this. It should
3088 * at least mask out the loads and stores for other invocations.
3089 */
3090 lp_build_if(&if_ctx, &ctx->gallivm,
3091 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3092 invocation_id, ctx->i32_0, ""));
3093
3094 /* Determine the layout of one tess factor element in the buffer. */
3095 switch (shader->key.part.tcs.epilog.prim_mode) {
3096 case PIPE_PRIM_LINES:
3097 stride = 2; /* 2 dwords, 1 vec2 store */
3098 outer_comps = 2;
3099 inner_comps = 0;
3100 break;
3101 case PIPE_PRIM_TRIANGLES:
3102 stride = 4; /* 4 dwords, 1 vec4 store */
3103 outer_comps = 3;
3104 inner_comps = 1;
3105 break;
3106 case PIPE_PRIM_QUADS:
3107 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3108 outer_comps = 4;
3109 inner_comps = 2;
3110 break;
3111 default:
3112 assert(0);
3113 return;
3114 }
3115
3116 for (i = 0; i < 4; i++) {
3117 inner[i] = LLVMGetUndef(ctx->i32);
3118 outer[i] = LLVMGetUndef(ctx->i32);
3119 }
3120
3121 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3122 /* Tess factors are in VGPRs. */
3123 for (i = 0; i < outer_comps; i++)
3124 outer[i] = out[i] = invoc0_tf_outer[i];
3125 for (i = 0; i < inner_comps; i++)
3126 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3127 } else {
3128 /* Load tess_inner and tess_outer from LDS.
3129 * Any invocation can write them, so we can't get them from a temporary.
3130 */
3131 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3132 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3133
3134 lds_base = tcs_out_current_patch_data_offset;
3135 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3136 LLVMConstInt(ctx->i32,
3137 tess_inner_index * 4, 0), "");
3138 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3139 LLVMConstInt(ctx->i32,
3140 tess_outer_index * 4, 0), "");
3141
3142 for (i = 0; i < outer_comps; i++) {
3143 outer[i] = out[i] =
3144 lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3145 }
3146 for (i = 0; i < inner_comps; i++) {
3147 inner[i] = out[outer_comps+i] =
3148 lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3149 }
3150 }
3151
3152 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3153 /* For isolines, the hardware expects tess factors in the
3154 * reverse order from what GLSL / TGSI specify.
3155 */
3156 LLVMValueRef tmp = out[0];
3157 out[0] = out[1];
3158 out[1] = tmp;
3159 }
3160
3161 /* Convert the outputs to vectors for stores. */
3162 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3163 vec1 = NULL;
3164
3165 if (stride > 4)
3166 vec1 = ac_build_gather_values(&ctx->ac, out+4, stride - 4);
3167
3168 /* Get the buffer. */
3169 buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
3170
3171 /* Get the offset. */
3172 tf_base = LLVMGetParam(ctx->main_fn,
3173 ctx->param_tcs_factor_offset);
3174 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3175 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3176
3177 lp_build_if(&inner_if_ctx, &ctx->gallivm,
3178 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3179 rel_patch_id, ctx->i32_0, ""));
3180
3181 /* Store the dynamic HS control word. */
3182 offset = 0;
3183 if (ctx->screen->info.chip_class <= VI) {
3184 ac_build_buffer_store_dword(&ctx->ac, buffer,
3185 LLVMConstInt(ctx->i32, 0x80000000, 0),
3186 1, ctx->i32_0, tf_base,
3187 offset, 1, 0, true, false);
3188 offset += 4;
3189 }
3190
3191 lp_build_endif(&inner_if_ctx);
3192
3193 /* Store the tessellation factors. */
3194 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3195 MIN2(stride, 4), byteoffset, tf_base,
3196 offset, 1, 0, true, false);
3197 offset += 16;
3198 if (vec1)
3199 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3200 stride - 4, byteoffset, tf_base,
3201 offset, 1, 0, true, false);
3202
3203 /* Store the tess factors into the offchip buffer if TES reads them. */
3204 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3205 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3206 LLVMValueRef tf_inner_offset;
3207 unsigned param_outer, param_inner;
3208
3209 buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3210 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3211
3212 param_outer = si_shader_io_get_unique_index_patch(
3213 TGSI_SEMANTIC_TESSOUTER, 0);
3214 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3215 LLVMConstInt(ctx->i32, param_outer, 0));
3216
3217 outer_vec = ac_build_gather_values(&ctx->ac, outer,
3218 util_next_power_of_two(outer_comps));
3219
3220 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3221 outer_comps, tf_outer_offset,
3222 base, 0, 1, 0, true, false);
3223 if (inner_comps) {
3224 param_inner = si_shader_io_get_unique_index_patch(
3225 TGSI_SEMANTIC_TESSINNER, 0);
3226 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3227 LLVMConstInt(ctx->i32, param_inner, 0));
3228
3229 inner_vec = inner_comps == 1 ? inner[0] :
3230 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3231 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3232 inner_comps, tf_inner_offset,
3233 base, 0, 1, 0, true, false);
3234 }
3235 }
3236
3237 lp_build_endif(&if_ctx);
3238 }
3239
3240 static LLVMValueRef
3241 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3242 unsigned param, unsigned return_index)
3243 {
3244 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3245 LLVMGetParam(ctx->main_fn, param),
3246 return_index, "");
3247 }
3248
3249 static LLVMValueRef
3250 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3251 unsigned param, unsigned return_index)
3252 {
3253 LLVMBuilderRef builder = ctx->ac.builder;
3254 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3255
3256 return LLVMBuildInsertValue(builder, ret,
3257 ac_to_float(&ctx->ac, p),
3258 return_index, "");
3259 }
3260
3261 static LLVMValueRef
3262 si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret,
3263 unsigned param, unsigned return_index)
3264 {
3265 LLVMBuilderRef builder = ctx->ac.builder;
3266 LLVMValueRef ptr, lo, hi;
3267
3268 if (HAVE_32BIT_POINTERS) {
3269 ptr = LLVMGetParam(ctx->main_fn, param);
3270 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i32, "");
3271 return LLVMBuildInsertValue(builder, ret, ptr, return_index, "");
3272 }
3273
3274 ptr = LLVMGetParam(ctx->main_fn, param);
3275 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
3276 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
3277 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
3278 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
3279 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
3280 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
3281 }
3282
3283 /* This only writes the tessellation factor levels. */
3284 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
3285 unsigned max_outputs,
3286 LLVMValueRef *addrs)
3287 {
3288 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3289 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
3290 LLVMBuilderRef builder = ctx->ac.builder;
3291 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3292
3293 si_copy_tcs_inputs(bld_base);
3294
3295 rel_patch_id = get_rel_patch_id(ctx);
3296 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3297 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3298
3299 if (ctx->screen->info.chip_class >= GFX9) {
3300 LLVMBasicBlockRef blocks[2] = {
3301 LLVMGetInsertBlock(builder),
3302 ctx->merged_wrap_if_state.entry_block
3303 };
3304 LLVMValueRef values[2];
3305
3306 lp_build_endif(&ctx->merged_wrap_if_state);
3307
3308 values[0] = rel_patch_id;
3309 values[1] = LLVMGetUndef(ctx->i32);
3310 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3311
3312 values[0] = tf_lds_offset;
3313 values[1] = LLVMGetUndef(ctx->i32);
3314 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3315
3316 values[0] = invocation_id;
3317 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3318 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3319 }
3320
3321 /* Return epilog parameters from this function. */
3322 LLVMValueRef ret = ctx->return_value;
3323 unsigned vgpr;
3324
3325 if (ctx->screen->info.chip_class >= GFX9) {
3326 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3327 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3328 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3329 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3330 /* Tess offchip and tess factor offsets are at the beginning. */
3331 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3332 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3333 vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
3334 } else {
3335 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3336 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3337 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3338 GFX6_SGPR_TCS_OUT_LAYOUT);
3339 /* Tess offchip and tess factor offsets are after user SGPRs. */
3340 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3341 GFX6_TCS_NUM_USER_SGPR);
3342 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3343 GFX6_TCS_NUM_USER_SGPR + 1);
3344 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3345 }
3346
3347 /* VGPRs */
3348 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3349 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3350 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3351
3352 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3353 * the invocation_id output does not alias the tcs_rel_ids input,
3354 * which saves a V_MOV on gfx9.
3355 */
3356 vgpr += 2;
3357
3358 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3359 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3360
3361 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3362 vgpr++; /* skip the tess factor LDS offset */
3363 for (unsigned i = 0; i < 6; i++) {
3364 LLVMValueRef value =
3365 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3366 value = ac_to_float(&ctx->ac, value);
3367 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3368 }
3369 } else {
3370 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3371 }
3372 ctx->return_value = ret;
3373 }
3374
3375 /* Pass TCS inputs from LS to TCS on GFX9. */
3376 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3377 {
3378 LLVMValueRef ret = ctx->return_value;
3379
3380 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3381 if (HAVE_32BIT_POINTERS)
3382 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3383 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3384 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3385 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3386 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3387
3388 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3389 8 + SI_SGPR_RW_BUFFERS);
3390 ret = si_insert_input_ptr(ctx, ret,
3391 ctx->param_bindless_samplers_and_images,
3392 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3393
3394 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3395 8 + SI_SGPR_VS_STATE_BITS);
3396
3397 #if !HAVE_32BIT_POINTERS
3398 ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 4,
3399 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
3400 #endif
3401
3402 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3403 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3404 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3405 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3406 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3407 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3408
3409 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3410 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3411 ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
3412 vgpr++, "");
3413 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3414 ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
3415 vgpr++, "");
3416 ctx->return_value = ret;
3417 }
3418
3419 /* Pass GS inputs from ES to GS on GFX9. */
3420 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3421 {
3422 LLVMValueRef ret = ctx->return_value;
3423
3424 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3425 if (HAVE_32BIT_POINTERS)
3426 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3427 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3428 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3429 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3430
3431 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3432 8 + SI_SGPR_RW_BUFFERS);
3433 ret = si_insert_input_ptr(ctx, ret,
3434 ctx->param_bindless_samplers_and_images,
3435 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3436
3437 #if !HAVE_32BIT_POINTERS
3438 ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 4,
3439 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
3440 #endif
3441
3442 unsigned vgpr;
3443 if (ctx->type == PIPE_SHADER_VERTEX)
3444 vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
3445 else
3446 vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
3447
3448 for (unsigned i = 0; i < 5; i++) {
3449 unsigned param = ctx->param_gs_vtx01_offset + i;
3450 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3451 }
3452 ctx->return_value = ret;
3453 }
3454
3455 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3456 unsigned max_outputs,
3457 LLVMValueRef *addrs)
3458 {
3459 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3460 struct si_shader *shader = ctx->shader;
3461 struct tgsi_shader_info *info = &shader->selector->info;
3462 unsigned i, chan;
3463 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3464 ctx->param_rel_auto_id);
3465 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3466 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3467 vertex_dw_stride, "");
3468
3469 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3470 * its inputs from it. */
3471 for (i = 0; i < info->num_outputs; i++) {
3472 unsigned name = info->output_semantic_name[i];
3473 unsigned index = info->output_semantic_index[i];
3474
3475 /* The ARB_shader_viewport_layer_array spec contains the
3476 * following issue:
3477 *
3478 * 2) What happens if gl_ViewportIndex or gl_Layer is
3479 * written in the vertex shader and a geometry shader is
3480 * present?
3481 *
3482 * RESOLVED: The value written by the last vertex processing
3483 * stage is used. If the last vertex processing stage
3484 * (vertex, tessellation evaluation or geometry) does not
3485 * statically assign to gl_ViewportIndex or gl_Layer, index
3486 * or layer zero is assumed.
3487 *
3488 * So writes to those outputs in VS-as-LS are simply ignored.
3489 */
3490 if (name == TGSI_SEMANTIC_LAYER ||
3491 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3492 continue;
3493
3494 int param = si_shader_io_get_unique_index(name, index, false);
3495 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3496 LLVMConstInt(ctx->i32, param * 4, 0), "");
3497
3498 for (chan = 0; chan < 4; chan++) {
3499 if (!(info->output_usagemask[i] & (1 << chan)))
3500 continue;
3501
3502 lds_store(ctx, chan, dw_addr,
3503 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3504 }
3505 }
3506
3507 if (ctx->screen->info.chip_class >= GFX9)
3508 si_set_ls_return_value_for_tcs(ctx);
3509 }
3510
3511 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3512 unsigned max_outputs,
3513 LLVMValueRef *addrs)
3514 {
3515 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3516 struct si_shader *es = ctx->shader;
3517 struct tgsi_shader_info *info = &es->selector->info;
3518 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3519 ctx->param_es2gs_offset);
3520 LLVMValueRef lds_base = NULL;
3521 unsigned chan;
3522 int i;
3523
3524 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3525 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3526 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3527 LLVMValueRef wave_idx = si_unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3528 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3529 LLVMBuildMul(ctx->ac.builder, wave_idx,
3530 LLVMConstInt(ctx->i32, 64, false), ""), "");
3531 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3532 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3533 }
3534
3535 for (i = 0; i < info->num_outputs; i++) {
3536 int param;
3537
3538 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3539 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3540 continue;
3541
3542 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3543 info->output_semantic_index[i], false);
3544
3545 for (chan = 0; chan < 4; chan++) {
3546 if (!(info->output_usagemask[i] & (1 << chan)))
3547 continue;
3548
3549 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3550 out_val = ac_to_integer(&ctx->ac, out_val);
3551
3552 /* GFX9 has the ESGS ring in LDS. */
3553 if (ctx->screen->info.chip_class >= GFX9) {
3554 lds_store(ctx, param * 4 + chan, lds_base, out_val);
3555 continue;
3556 }
3557
3558 ac_build_buffer_store_dword(&ctx->ac,
3559 ctx->esgs_ring,
3560 out_val, 1, NULL, soffset,
3561 (4 * param + chan) * 4,
3562 1, 1, true, true);
3563 }
3564 }
3565
3566 if (ctx->screen->info.chip_class >= GFX9)
3567 si_set_es_return_value_for_gs(ctx);
3568 }
3569
3570 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3571 {
3572 if (ctx->screen->info.chip_class >= GFX9)
3573 return si_unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3574 else
3575 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3576 }
3577
3578 static void emit_gs_epilogue(struct si_shader_context *ctx)
3579 {
3580 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3581 si_get_gs_wave_id(ctx));
3582
3583 if (ctx->screen->info.chip_class >= GFX9)
3584 lp_build_endif(&ctx->merged_wrap_if_state);
3585 }
3586
3587 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3588 unsigned max_outputs,
3589 LLVMValueRef *addrs)
3590 {
3591 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3592 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3593
3594 assert(info->num_outputs <= max_outputs);
3595
3596 emit_gs_epilogue(ctx);
3597 }
3598
3599 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3600 {
3601 struct si_shader_context *ctx = si_shader_context(bld_base);
3602 emit_gs_epilogue(ctx);
3603 }
3604
3605 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3606 unsigned max_outputs,
3607 LLVMValueRef *addrs)
3608 {
3609 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3610 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3611 struct si_shader_output_values *outputs = NULL;
3612 int i,j;
3613
3614 assert(!ctx->shader->is_gs_copy_shader);
3615 assert(info->num_outputs <= max_outputs);
3616
3617 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3618
3619 /* Vertex color clamping.
3620 *
3621 * This uses a state constant loaded in a user data SGPR and
3622 * an IF statement is added that clamps all colors if the constant
3623 * is true.
3624 */
3625 struct lp_build_if_state if_ctx;
3626 LLVMValueRef cond = NULL;
3627 LLVMValueRef addr, val;
3628
3629 for (i = 0; i < info->num_outputs; i++) {
3630 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3631 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3632 continue;
3633
3634 /* We've found a color. */
3635 if (!cond) {
3636 /* The state is in the first bit of the user SGPR. */
3637 cond = LLVMGetParam(ctx->main_fn,
3638 ctx->param_vs_state_bits);
3639 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3640 ctx->i1, "");
3641 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3642 }
3643
3644 for (j = 0; j < 4; j++) {
3645 addr = addrs[4 * i + j];
3646 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3647 val = ac_build_clamp(&ctx->ac, val);
3648 LLVMBuildStore(ctx->ac.builder, val, addr);
3649 }
3650 }
3651
3652 if (cond)
3653 lp_build_endif(&if_ctx);
3654
3655 for (i = 0; i < info->num_outputs; i++) {
3656 outputs[i].semantic_name = info->output_semantic_name[i];
3657 outputs[i].semantic_index = info->output_semantic_index[i];
3658
3659 for (j = 0; j < 4; j++) {
3660 outputs[i].values[j] =
3661 LLVMBuildLoad(ctx->ac.builder,
3662 addrs[4 * i + j],
3663 "");
3664 outputs[i].vertex_stream[j] =
3665 (info->output_streams[i] >> (2 * j)) & 3;
3666 }
3667 }
3668
3669 if (ctx->shader->selector->so.num_outputs)
3670 si_llvm_emit_streamout(ctx, outputs, i, 0);
3671
3672 /* Export PrimitiveID. */
3673 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3674 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3675 outputs[i].semantic_index = 0;
3676 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3677 for (j = 1; j < 4; j++)
3678 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3679
3680 memset(outputs[i].vertex_stream, 0,
3681 sizeof(outputs[i].vertex_stream));
3682 i++;
3683 }
3684
3685 si_llvm_export_vs(ctx, outputs, i);
3686 FREE(outputs);
3687 }
3688
3689 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3690 {
3691 struct si_shader_context *ctx = si_shader_context(bld_base);
3692
3693 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3694 &ctx->outputs[0][0]);
3695 }
3696
3697 struct si_ps_exports {
3698 unsigned num;
3699 struct ac_export_args args[10];
3700 };
3701
3702 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3703 LLVMValueRef depth, LLVMValueRef stencil,
3704 LLVMValueRef samplemask, struct si_ps_exports *exp)
3705 {
3706 struct si_shader_context *ctx = si_shader_context(bld_base);
3707 struct ac_export_args args;
3708
3709 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3710
3711 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3712 }
3713
3714 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3715 LLVMValueRef *color, unsigned index,
3716 unsigned samplemask_param,
3717 bool is_last, struct si_ps_exports *exp)
3718 {
3719 struct si_shader_context *ctx = si_shader_context(bld_base);
3720 int i;
3721
3722 /* Clamp color */
3723 if (ctx->shader->key.part.ps.epilog.clamp_color)
3724 for (i = 0; i < 4; i++)
3725 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3726
3727 /* Alpha to one */
3728 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3729 color[3] = ctx->ac.f32_1;
3730
3731 /* Alpha test */
3732 if (index == 0 &&
3733 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3734 si_alpha_test(bld_base, color[3]);
3735
3736 /* Line & polygon smoothing */
3737 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3738 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3739 samplemask_param);
3740
3741 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3742 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3743 struct ac_export_args args[8];
3744 int c, last = -1;
3745
3746 /* Get the export arguments, also find out what the last one is. */
3747 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3748 si_llvm_init_export_args(ctx, color,
3749 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3750 if (args[c].enabled_channels)
3751 last = c;
3752 }
3753
3754 /* Emit all exports. */
3755 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3756 if (is_last && last == c) {
3757 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3758 args[c].done = 1; /* DONE bit */
3759 } else if (!args[c].enabled_channels)
3760 continue; /* unnecessary NULL export */
3761
3762 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3763 }
3764 } else {
3765 struct ac_export_args args;
3766
3767 /* Export */
3768 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3769 &args);
3770 if (is_last) {
3771 args.valid_mask = 1; /* whether the EXEC mask is valid */
3772 args.done = 1; /* DONE bit */
3773 } else if (!args.enabled_channels)
3774 return; /* unnecessary NULL export */
3775
3776 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3777 }
3778 }
3779
3780 static void si_emit_ps_exports(struct si_shader_context *ctx,
3781 struct si_ps_exports *exp)
3782 {
3783 for (unsigned i = 0; i < exp->num; i++)
3784 ac_build_export(&ctx->ac, &exp->args[i]);
3785 }
3786
3787 /**
3788 * Return PS outputs in this order:
3789 *
3790 * v[0:3] = color0.xyzw
3791 * v[4:7] = color1.xyzw
3792 * ...
3793 * vN+0 = Depth
3794 * vN+1 = Stencil
3795 * vN+2 = SampleMask
3796 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3797 *
3798 * The alpha-ref SGPR is returned via its original location.
3799 */
3800 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3801 unsigned max_outputs,
3802 LLVMValueRef *addrs)
3803 {
3804 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3805 struct si_shader *shader = ctx->shader;
3806 struct tgsi_shader_info *info = &shader->selector->info;
3807 LLVMBuilderRef builder = ctx->ac.builder;
3808 unsigned i, j, first_vgpr, vgpr;
3809
3810 LLVMValueRef color[8][4] = {};
3811 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3812 LLVMValueRef ret;
3813
3814 if (ctx->postponed_kill)
3815 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3816
3817 /* Read the output values. */
3818 for (i = 0; i < info->num_outputs; i++) {
3819 unsigned semantic_name = info->output_semantic_name[i];
3820 unsigned semantic_index = info->output_semantic_index[i];
3821
3822 switch (semantic_name) {
3823 case TGSI_SEMANTIC_COLOR:
3824 assert(semantic_index < 8);
3825 for (j = 0; j < 4; j++) {
3826 LLVMValueRef ptr = addrs[4 * i + j];
3827 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3828 color[semantic_index][j] = result;
3829 }
3830 break;
3831 case TGSI_SEMANTIC_POSITION:
3832 depth = LLVMBuildLoad(builder,
3833 addrs[4 * i + 2], "");
3834 break;
3835 case TGSI_SEMANTIC_STENCIL:
3836 stencil = LLVMBuildLoad(builder,
3837 addrs[4 * i + 1], "");
3838 break;
3839 case TGSI_SEMANTIC_SAMPLEMASK:
3840 samplemask = LLVMBuildLoad(builder,
3841 addrs[4 * i + 0], "");
3842 break;
3843 default:
3844 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3845 semantic_name);
3846 }
3847 }
3848
3849 /* Fill the return structure. */
3850 ret = ctx->return_value;
3851
3852 /* Set SGPRs. */
3853 ret = LLVMBuildInsertValue(builder, ret,
3854 ac_to_integer(&ctx->ac,
3855 LLVMGetParam(ctx->main_fn,
3856 SI_PARAM_ALPHA_REF)),
3857 SI_SGPR_ALPHA_REF, "");
3858
3859 /* Set VGPRs */
3860 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3861 for (i = 0; i < ARRAY_SIZE(color); i++) {
3862 if (!color[i][0])
3863 continue;
3864
3865 for (j = 0; j < 4; j++)
3866 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3867 }
3868 if (depth)
3869 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3870 if (stencil)
3871 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3872 if (samplemask)
3873 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3874
3875 /* Add the input sample mask for smoothing at the end. */
3876 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3877 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3878 ret = LLVMBuildInsertValue(builder, ret,
3879 LLVMGetParam(ctx->main_fn,
3880 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3881
3882 ctx->return_value = ret;
3883 }
3884
3885 static void membar_emit(
3886 const struct lp_build_tgsi_action *action,
3887 struct lp_build_tgsi_context *bld_base,
3888 struct lp_build_emit_data *emit_data)
3889 {
3890 struct si_shader_context *ctx = si_shader_context(bld_base);
3891 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3892 unsigned flags = LLVMConstIntGetZExtValue(src0);
3893 unsigned waitcnt = NOOP_WAITCNT;
3894
3895 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3896 waitcnt &= VM_CNT & LGKM_CNT;
3897
3898 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3899 TGSI_MEMBAR_SHADER_BUFFER |
3900 TGSI_MEMBAR_SHADER_IMAGE))
3901 waitcnt &= VM_CNT;
3902
3903 if (flags & TGSI_MEMBAR_SHARED)
3904 waitcnt &= LGKM_CNT;
3905
3906 if (waitcnt != NOOP_WAITCNT)
3907 ac_build_waitcnt(&ctx->ac, waitcnt);
3908 }
3909
3910 static void clock_emit(
3911 const struct lp_build_tgsi_action *action,
3912 struct lp_build_tgsi_context *bld_base,
3913 struct lp_build_emit_data *emit_data)
3914 {
3915 struct si_shader_context *ctx = si_shader_context(bld_base);
3916 LLVMValueRef tmp = ac_build_shader_clock(&ctx->ac);
3917
3918 emit_data->output[0] =
3919 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3920 emit_data->output[1] =
3921 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3922 }
3923
3924 static void si_llvm_emit_ddxy(
3925 const struct lp_build_tgsi_action *action,
3926 struct lp_build_tgsi_context *bld_base,
3927 struct lp_build_emit_data *emit_data)
3928 {
3929 struct si_shader_context *ctx = si_shader_context(bld_base);
3930 unsigned opcode = emit_data->info->opcode;
3931 LLVMValueRef val;
3932 int idx;
3933 unsigned mask;
3934
3935 if (opcode == TGSI_OPCODE_DDX_FINE)
3936 mask = AC_TID_MASK_LEFT;
3937 else if (opcode == TGSI_OPCODE_DDY_FINE)
3938 mask = AC_TID_MASK_TOP;
3939 else
3940 mask = AC_TID_MASK_TOP_LEFT;
3941
3942 /* for DDX we want to next X pixel, DDY next Y pixel. */
3943 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3944
3945 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3946 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3947 emit_data->output[emit_data->chan] = val;
3948 }
3949
3950 /*
3951 * this takes an I,J coordinate pair,
3952 * and works out the X and Y derivatives.
3953 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3954 */
3955 static LLVMValueRef si_llvm_emit_ddxy_interp(
3956 struct lp_build_tgsi_context *bld_base,
3957 LLVMValueRef interp_ij)
3958 {
3959 struct si_shader_context *ctx = si_shader_context(bld_base);
3960 LLVMValueRef result[4], a;
3961 unsigned i;
3962
3963 for (i = 0; i < 2; i++) {
3964 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
3965 LLVMConstInt(ctx->i32, i, 0), "");
3966 result[i] = ac_build_ddxy(&ctx->ac, AC_TID_MASK_TOP_LEFT, 1,
3967 ac_to_integer(&ctx->ac, a)); /* DDX */
3968 result[2+i] = ac_build_ddxy(&ctx->ac, AC_TID_MASK_TOP_LEFT, 2,
3969 ac_to_integer(&ctx->ac, a)); /* DDY */
3970 }
3971
3972 return ac_build_gather_values(&ctx->ac, result, 4);
3973 }
3974
3975 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3976 struct lp_build_tgsi_context *bld_base,
3977 struct lp_build_emit_data *emit_data)
3978 {
3979 struct si_shader_context *ctx = si_shader_context(bld_base);
3980 struct si_shader *shader = ctx->shader;
3981 const struct tgsi_shader_info *info = &shader->selector->info;
3982 LLVMValueRef interp_param;
3983 const struct tgsi_full_instruction *inst = emit_data->inst;
3984 const struct tgsi_full_src_register *input = &inst->Src[0];
3985 int input_base, input_array_size;
3986 int chan;
3987 int i;
3988 LLVMValueRef prim_mask = ctx->abi.prim_mask;
3989 LLVMValueRef array_idx, offset_x = NULL, offset_y = NULL;
3990 int interp_param_idx;
3991 unsigned interp;
3992 unsigned location;
3993
3994 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3995 /* offset is in second src, first two channels */
3996 offset_x = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
3997 TGSI_CHAN_X);
3998 offset_y = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
3999 TGSI_CHAN_Y);
4000 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4001 LLVMValueRef sample_position;
4002 LLVMValueRef sample_id;
4003 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
4004
4005 /* fetch sample ID, then fetch its sample position,
4006 * and place into first two channels.
4007 */
4008 sample_id = lp_build_emit_fetch(bld_base,
4009 emit_data->inst, 1, TGSI_CHAN_X);
4010 sample_id = ac_to_integer(&ctx->ac, sample_id);
4011
4012 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
4013 * Language 4.50 spec says about interpolateAtSample:
4014 *
4015 * "Returns the value of the input interpolant variable at
4016 * the location of sample number sample. If multisample
4017 * buffers are not available, the input variable will be
4018 * evaluated at the center of the pixel. If sample sample
4019 * does not exist, the position used to interpolate the
4020 * input variable is undefined."
4021 *
4022 * This means that sample_id values outside of the valid are
4023 * in fact valid input, and the usual mechanism for loading the
4024 * sample position doesn't work.
4025 */
4026 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
4027 LLVMValueRef center[4] = {
4028 LLVMConstReal(ctx->f32, 0.5),
4029 LLVMConstReal(ctx->f32, 0.5),
4030 ctx->ac.f32_0,
4031 ctx->ac.f32_0,
4032 };
4033
4034 sample_position = ac_build_gather_values(&ctx->ac, center, 4);
4035 } else {
4036 sample_position = load_sample_position(&ctx->abi, sample_id);
4037 }
4038
4039 offset_x = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
4040 ctx->i32_0, "");
4041
4042 offset_x = LLVMBuildFSub(ctx->ac.builder, offset_x, halfval, "");
4043 offset_y = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
4044 ctx->i32_1, "");
4045 offset_y = LLVMBuildFSub(ctx->ac.builder, offset_y, halfval, "");
4046 }
4047
4048 assert(input->Register.File == TGSI_FILE_INPUT);
4049
4050 if (input->Register.Indirect) {
4051 unsigned array_id = input->Indirect.ArrayID;
4052
4053 if (array_id) {
4054 input_base = info->input_array_first[array_id];
4055 input_array_size = info->input_array_last[array_id] - input_base + 1;
4056 } else {
4057 input_base = inst->Src[0].Register.Index;
4058 input_array_size = info->num_inputs - input_base;
4059 }
4060
4061 array_idx = si_get_indirect_index(ctx, &input->Indirect,
4062 1, input->Register.Index - input_base);
4063 } else {
4064 input_base = inst->Src[0].Register.Index;
4065 input_array_size = 1;
4066 array_idx = ctx->i32_0;
4067 }
4068
4069 interp = shader->selector->info.input_interpolate[input_base];
4070
4071 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4072 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4073 location = TGSI_INTERPOLATE_LOC_CENTER;
4074 else
4075 location = TGSI_INTERPOLATE_LOC_CENTROID;
4076
4077 interp_param_idx = lookup_interp_param_index(interp, location);
4078 if (interp_param_idx == -1)
4079 return;
4080 else if (interp_param_idx)
4081 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4082 else
4083 interp_param = NULL;
4084
4085 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4086 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4087 LLVMValueRef ij_out[2];
4088 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
4089
4090 /*
4091 * take the I then J parameters, and the DDX/Y for it, and
4092 * calculate the IJ inputs for the interpolator.
4093 * temp1 = ddx * offset/sample.x + I;
4094 * interp_param.I = ddy * offset/sample.y + temp1;
4095 * temp1 = ddx * offset/sample.x + J;
4096 * interp_param.J = ddy * offset/sample.y + temp1;
4097 */
4098 for (i = 0; i < 2; i++) {
4099 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
4100 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
4101 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4102 ddxy_out, ix_ll, "");
4103 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4104 ddxy_out, iy_ll, "");
4105 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4106 interp_param, ix_ll, "");
4107 LLVMValueRef temp;
4108
4109 interp_el = ac_to_float(&ctx->ac, interp_el);
4110
4111 temp = ac_build_fmad(&ctx->ac, ddx_el, offset_x, interp_el);
4112 ij_out[i] = ac_build_fmad(&ctx->ac, ddy_el, offset_y, temp);
4113 }
4114 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4115 }
4116
4117 if (interp_param)
4118 interp_param = ac_to_float(&ctx->ac, interp_param);
4119
4120 for (chan = 0; chan < 4; chan++) {
4121 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
4122 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4123
4124 for (unsigned idx = 0; idx < input_array_size; ++idx) {
4125 LLVMValueRef v, i = NULL, j = NULL;
4126
4127 if (interp_param) {
4128 i = LLVMBuildExtractElement(
4129 ctx->ac.builder, interp_param, ctx->i32_0, "");
4130 j = LLVMBuildExtractElement(
4131 ctx->ac.builder, interp_param, ctx->i32_1, "");
4132 }
4133 v = si_build_fs_interp(ctx, input_base + idx, schan,
4134 prim_mask, i, j);
4135
4136 gather = LLVMBuildInsertElement(ctx->ac.builder,
4137 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
4138 }
4139
4140 emit_data->output[chan] = LLVMBuildExtractElement(
4141 ctx->ac.builder, gather, array_idx, "");
4142 }
4143 }
4144
4145 static void vote_all_emit(
4146 const struct lp_build_tgsi_action *action,
4147 struct lp_build_tgsi_context *bld_base,
4148 struct lp_build_emit_data *emit_data)
4149 {
4150 struct si_shader_context *ctx = si_shader_context(bld_base);
4151
4152 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
4153 emit_data->output[emit_data->chan] =
4154 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4155 }
4156
4157 static void vote_any_emit(
4158 const struct lp_build_tgsi_action *action,
4159 struct lp_build_tgsi_context *bld_base,
4160 struct lp_build_emit_data *emit_data)
4161 {
4162 struct si_shader_context *ctx = si_shader_context(bld_base);
4163
4164 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
4165 emit_data->output[emit_data->chan] =
4166 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4167 }
4168
4169 static void vote_eq_emit(
4170 const struct lp_build_tgsi_action *action,
4171 struct lp_build_tgsi_context *bld_base,
4172 struct lp_build_emit_data *emit_data)
4173 {
4174 struct si_shader_context *ctx = si_shader_context(bld_base);
4175
4176 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4177 emit_data->output[emit_data->chan] =
4178 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4179 }
4180
4181 static void ballot_emit(
4182 const struct lp_build_tgsi_action *action,
4183 struct lp_build_tgsi_context *bld_base,
4184 struct lp_build_emit_data *emit_data)
4185 {
4186 struct si_shader_context *ctx = si_shader_context(bld_base);
4187 LLVMBuilderRef builder = ctx->ac.builder;
4188 LLVMValueRef tmp;
4189
4190 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4191 tmp = ac_build_ballot(&ctx->ac, tmp);
4192 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4193
4194 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4195 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4196 }
4197
4198 static void read_lane_emit(
4199 const struct lp_build_tgsi_action *action,
4200 struct lp_build_tgsi_context *bld_base,
4201 struct lp_build_emit_data *emit_data)
4202 {
4203 struct si_shader_context *ctx = si_shader_context(bld_base);
4204
4205 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_READ_INVOC) {
4206 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4207 0, emit_data->src_chan);
4208
4209 /* Always read the source invocation (= lane) from the X channel. */
4210 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4211 1, TGSI_CHAN_X);
4212 emit_data->arg_count = 2;
4213 }
4214
4215 /* We currently have no other way to prevent LLVM from lifting the icmp
4216 * calls to a dominating basic block.
4217 */
4218 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4219
4220 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4221 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4222
4223 emit_data->output[emit_data->chan] =
4224 ac_build_intrinsic(&ctx->ac, action->intr_name,
4225 ctx->i32, emit_data->args, emit_data->arg_count,
4226 AC_FUNC_ATTR_READNONE |
4227 AC_FUNC_ATTR_CONVERGENT);
4228 }
4229
4230 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4231 struct lp_build_emit_data *emit_data)
4232 {
4233 struct si_shader_context *ctx = si_shader_context(bld_base);
4234 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4235 LLVMValueRef imm;
4236 unsigned stream;
4237
4238 assert(src0.File == TGSI_FILE_IMMEDIATE);
4239
4240 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4241 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4242 return stream;
4243 }
4244
4245 /* Emit one vertex from the geometry shader */
4246 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4247 unsigned stream,
4248 LLVMValueRef *addrs)
4249 {
4250 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4251 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4252 struct si_shader *shader = ctx->shader;
4253 struct lp_build_if_state if_state;
4254 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4255 ctx->param_gs2vs_offset);
4256 LLVMValueRef gs_next_vertex;
4257 LLVMValueRef can_emit;
4258 unsigned chan, offset;
4259 int i;
4260
4261 /* Write vertex attribute values to GSVS ring */
4262 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4263 ctx->gs_next_vertex[stream],
4264 "");
4265
4266 /* If this thread has already emitted the declared maximum number of
4267 * vertices, skip the write: excessive vertex emissions are not
4268 * supposed to have any effect.
4269 *
4270 * If the shader has no writes to memory, kill it instead. This skips
4271 * further memory loads and may allow LLVM to skip to the end
4272 * altogether.
4273 */
4274 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4275 LLVMConstInt(ctx->i32,
4276 shader->selector->gs_max_out_vertices, 0), "");
4277
4278 bool use_kill = !info->writes_memory;
4279 if (use_kill) {
4280 ac_build_kill_if_false(&ctx->ac, can_emit);
4281 } else {
4282 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4283 }
4284
4285 offset = 0;
4286 for (i = 0; i < info->num_outputs; i++) {
4287 for (chan = 0; chan < 4; chan++) {
4288 if (!(info->output_usagemask[i] & (1 << chan)) ||
4289 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4290 continue;
4291
4292 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4293 LLVMValueRef voffset =
4294 LLVMConstInt(ctx->i32, offset *
4295 shader->selector->gs_max_out_vertices, 0);
4296 offset++;
4297
4298 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4299 voffset = LLVMBuildMul(ctx->ac.builder, voffset,
4300 LLVMConstInt(ctx->i32, 4, 0), "");
4301
4302 out_val = ac_to_integer(&ctx->ac, out_val);
4303
4304 ac_build_buffer_store_dword(&ctx->ac,
4305 ctx->gsvs_ring[stream],
4306 out_val, 1,
4307 voffset, soffset, 0,
4308 1, 1, true, true);
4309 }
4310 }
4311
4312 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex, ctx->i32_1, "");
4313 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4314
4315 /* Signal vertex emission if vertex data was written. */
4316 if (offset) {
4317 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4318 si_get_gs_wave_id(ctx));
4319 }
4320
4321 if (!use_kill)
4322 lp_build_endif(&if_state);
4323 }
4324
4325 /* Emit one vertex from the geometry shader */
4326 static void si_tgsi_emit_vertex(
4327 const struct lp_build_tgsi_action *action,
4328 struct lp_build_tgsi_context *bld_base,
4329 struct lp_build_emit_data *emit_data)
4330 {
4331 struct si_shader_context *ctx = si_shader_context(bld_base);
4332 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4333
4334 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4335 }
4336
4337 /* Cut one primitive from the geometry shader */
4338 static void si_llvm_emit_primitive(struct ac_shader_abi *abi,
4339 unsigned stream)
4340 {
4341 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4342
4343 /* Signal primitive cut */
4344 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4345 si_get_gs_wave_id(ctx));
4346 }
4347
4348 /* Cut one primitive from the geometry shader */
4349 static void si_tgsi_emit_primitive(
4350 const struct lp_build_tgsi_action *action,
4351 struct lp_build_tgsi_context *bld_base,
4352 struct lp_build_emit_data *emit_data)
4353 {
4354 struct si_shader_context *ctx = si_shader_context(bld_base);
4355
4356 si_llvm_emit_primitive(&ctx->abi, si_llvm_get_stream(bld_base, emit_data));
4357 }
4358
4359 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4360 struct lp_build_tgsi_context *bld_base,
4361 struct lp_build_emit_data *emit_data)
4362 {
4363 struct si_shader_context *ctx = si_shader_context(bld_base);
4364
4365 /* SI only (thanks to a hw bug workaround):
4366 * The real barrier instruction isn’t needed, because an entire patch
4367 * always fits into a single wave.
4368 */
4369 if (ctx->screen->info.chip_class == SI &&
4370 ctx->type == PIPE_SHADER_TESS_CTRL) {
4371 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
4372 return;
4373 }
4374
4375 ac_build_s_barrier(&ctx->ac);
4376 }
4377
4378 static void si_create_function(struct si_shader_context *ctx,
4379 const char *name,
4380 LLVMTypeRef *returns, unsigned num_returns,
4381 struct si_function_info *fninfo,
4382 unsigned max_workgroup_size)
4383 {
4384 int i;
4385
4386 si_llvm_create_func(ctx, name, returns, num_returns,
4387 fninfo->types, fninfo->num_params);
4388 ctx->return_value = LLVMGetUndef(ctx->return_type);
4389
4390 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4391 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4392
4393 /* The combination of:
4394 * - noalias
4395 * - dereferenceable
4396 * - invariant.load
4397 * allows the optimization passes to move loads and reduces
4398 * SGPR spilling significantly.
4399 */
4400 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4401 AC_FUNC_ATTR_INREG);
4402
4403 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4404 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4405 AC_FUNC_ATTR_NOALIAS);
4406 ac_add_attr_dereferenceable(P, UINT64_MAX);
4407 }
4408 }
4409
4410 for (i = 0; i < fninfo->num_params; ++i) {
4411 if (fninfo->assign[i])
4412 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4413 }
4414
4415 if (ctx->screen->info.address32_hi) {
4416 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4417 "amdgpu-32bit-address-high-bits",
4418 ctx->screen->info.address32_hi);
4419 }
4420
4421 if (max_workgroup_size) {
4422 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4423 "amdgpu-max-work-group-size",
4424 max_workgroup_size);
4425 }
4426 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4427 "no-signed-zeros-fp-math",
4428 "true");
4429
4430 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4431 /* These were copied from some LLVM test. */
4432 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4433 "less-precise-fpmad",
4434 "true");
4435 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4436 "no-infs-fp-math",
4437 "true");
4438 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4439 "no-nans-fp-math",
4440 "true");
4441 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4442 "unsafe-fp-math",
4443 "true");
4444 }
4445 }
4446
4447 static void declare_streamout_params(struct si_shader_context *ctx,
4448 struct pipe_stream_output_info *so,
4449 struct si_function_info *fninfo)
4450 {
4451 int i;
4452
4453 /* Streamout SGPRs. */
4454 if (so->num_outputs) {
4455 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4456 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4457 else
4458 ctx->param_streamout_config = fninfo->num_params - 1;
4459
4460 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4461 }
4462 /* A streamout buffer offset is loaded if the stride is non-zero. */
4463 for (i = 0; i < 4; i++) {
4464 if (!so->stride[i])
4465 continue;
4466
4467 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4468 }
4469 }
4470
4471 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4472 {
4473 switch (shader->selector->type) {
4474 case PIPE_SHADER_TESS_CTRL:
4475 /* Return this so that LLVM doesn't remove s_barrier
4476 * instructions on chips where we use s_barrier. */
4477 return shader->selector->screen->info.chip_class >= CIK ? 128 : 64;
4478
4479 case PIPE_SHADER_GEOMETRY:
4480 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4481
4482 case PIPE_SHADER_COMPUTE:
4483 break; /* see below */
4484
4485 default:
4486 return 0;
4487 }
4488
4489 const unsigned *properties = shader->selector->info.properties;
4490 unsigned max_work_group_size =
4491 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4492 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4493 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4494
4495 if (!max_work_group_size) {
4496 /* This is a variable group size compute shader,
4497 * compile it for the maximum possible group size.
4498 */
4499 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4500 }
4501 return max_work_group_size;
4502 }
4503
4504 static void declare_const_and_shader_buffers(struct si_shader_context *ctx,
4505 struct si_function_info *fninfo,
4506 bool assign_params)
4507 {
4508 LLVMTypeRef const_shader_buf_type;
4509
4510 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4511 ctx->shader->selector->info.shader_buffers_declared == 0)
4512 const_shader_buf_type = ctx->f32;
4513 else
4514 const_shader_buf_type = ctx->v4i32;
4515
4516 unsigned const_and_shader_buffers =
4517 add_arg(fninfo, ARG_SGPR,
4518 ac_array_in_const32_addr_space(const_shader_buf_type));
4519
4520 if (assign_params)
4521 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4522 }
4523
4524 static void declare_samplers_and_images(struct si_shader_context *ctx,
4525 struct si_function_info *fninfo,
4526 bool assign_params)
4527 {
4528 unsigned samplers_and_images =
4529 add_arg(fninfo, ARG_SGPR,
4530 ac_array_in_const32_addr_space(ctx->v8i32));
4531
4532 if (assign_params)
4533 ctx->param_samplers_and_images = samplers_and_images;
4534 }
4535
4536 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4537 struct si_function_info *fninfo,
4538 bool assign_params)
4539 {
4540 declare_const_and_shader_buffers(ctx, fninfo, assign_params);
4541 declare_samplers_and_images(ctx, fninfo, assign_params);
4542 }
4543
4544 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4545 struct si_function_info *fninfo)
4546 {
4547 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4548 ac_array_in_const32_addr_space(ctx->v4i32));
4549 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4550 ac_array_in_const32_addr_space(ctx->v8i32));
4551 }
4552
4553 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4554 struct si_function_info *fninfo)
4555 {
4556 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4557 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4558 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4559 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4560 }
4561
4562 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4563 struct si_function_info *fninfo,
4564 unsigned *num_prolog_vgprs)
4565 {
4566 struct si_shader *shader = ctx->shader;
4567
4568 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4569 if (shader->key.as_ls) {
4570 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4571 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4572 } else {
4573 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4574 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4575 }
4576 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4577
4578 if (!shader->is_gs_copy_shader) {
4579 /* Vertex load indices. */
4580 ctx->param_vertex_index0 = fninfo->num_params;
4581 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4582 add_arg(fninfo, ARG_VGPR, ctx->i32);
4583 *num_prolog_vgprs += shader->selector->info.num_inputs;
4584 }
4585 }
4586
4587 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4588 struct si_function_info *fninfo)
4589 {
4590 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4591 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4592 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4593 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
4594 }
4595
4596 enum {
4597 /* Convenient merged shader definitions. */
4598 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4599 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4600 };
4601
4602 static void create_function(struct si_shader_context *ctx)
4603 {
4604 struct si_shader *shader = ctx->shader;
4605 struct si_function_info fninfo;
4606 LLVMTypeRef returns[16+32*4];
4607 unsigned i, num_return_sgprs;
4608 unsigned num_returns = 0;
4609 unsigned num_prolog_vgprs = 0;
4610 unsigned type = ctx->type;
4611 unsigned vs_blit_property =
4612 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4613
4614 si_init_function_info(&fninfo);
4615
4616 /* Set MERGED shaders. */
4617 if (ctx->screen->info.chip_class >= GFX9) {
4618 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4619 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4620 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4621 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4622 }
4623
4624 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4625
4626 switch (type) {
4627 case PIPE_SHADER_VERTEX:
4628 declare_global_desc_pointers(ctx, &fninfo);
4629
4630 if (vs_blit_property) {
4631 ctx->param_vs_blit_inputs = fninfo.num_params;
4632 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4633 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4634 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* depth */
4635
4636 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4637 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color0 */
4638 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color1 */
4639 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color2 */
4640 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color3 */
4641 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4642 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4643 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4644 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4645 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4646 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4647 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4648 }
4649
4650 /* VGPRs */
4651 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4652 break;
4653 }
4654
4655 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4656 declare_vs_specific_input_sgprs(ctx, &fninfo);
4657 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4658 ac_array_in_const32_addr_space(ctx->v4i32));
4659
4660 if (shader->key.as_es) {
4661 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4662 } else if (shader->key.as_ls) {
4663 /* no extra parameters */
4664 } else {
4665 if (shader->is_gs_copy_shader) {
4666 fninfo.num_params = ctx->param_vs_state_bits + 1;
4667 fninfo.num_sgpr_params = fninfo.num_params;
4668 }
4669
4670 /* The locations of the other parameters are assigned dynamically. */
4671 declare_streamout_params(ctx, &shader->selector->so,
4672 &fninfo);
4673 }
4674
4675 /* VGPRs */
4676 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4677 break;
4678
4679 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4680 declare_global_desc_pointers(ctx, &fninfo);
4681 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4682 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4683 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4684 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4685 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4686 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4687 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4688
4689 /* VGPRs */
4690 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4691 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4692
4693 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4694 * placed after the user SGPRs.
4695 */
4696 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4697 returns[num_returns++] = ctx->i32; /* SGPRs */
4698 for (i = 0; i < 11; i++)
4699 returns[num_returns++] = ctx->f32; /* VGPRs */
4700 break;
4701
4702 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4703 /* Merged stages have 8 system SGPRs at the beginning. */
4704 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
4705 if (HAVE_32BIT_POINTERS) {
4706 declare_per_stage_desc_pointers(ctx, &fninfo,
4707 ctx->type == PIPE_SHADER_TESS_CTRL);
4708 } else {
4709 declare_const_and_shader_buffers(ctx, &fninfo,
4710 ctx->type == PIPE_SHADER_TESS_CTRL);
4711 }
4712 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4713 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4714 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4715 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4716 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4717 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4718
4719 declare_global_desc_pointers(ctx, &fninfo);
4720 declare_per_stage_desc_pointers(ctx, &fninfo,
4721 ctx->type == PIPE_SHADER_VERTEX);
4722 declare_vs_specific_input_sgprs(ctx, &fninfo);
4723
4724 if (!HAVE_32BIT_POINTERS) {
4725 declare_samplers_and_images(ctx, &fninfo,
4726 ctx->type == PIPE_SHADER_TESS_CTRL);
4727 }
4728 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4729 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4730 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4731 if (!HAVE_32BIT_POINTERS) /* Align to 2 dwords. */
4732 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4733 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4734 ac_array_in_const32_addr_space(ctx->v4i32));
4735
4736 /* VGPRs (first TCS, then VS) */
4737 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4738 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4739
4740 if (ctx->type == PIPE_SHADER_VERTEX) {
4741 declare_vs_input_vgprs(ctx, &fninfo,
4742 &num_prolog_vgprs);
4743
4744 /* LS return values are inputs to the TCS main shader part. */
4745 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4746 returns[num_returns++] = ctx->i32; /* SGPRs */
4747 for (i = 0; i < 2; i++)
4748 returns[num_returns++] = ctx->f32; /* VGPRs */
4749 } else {
4750 /* TCS return values are inputs to the TCS epilog.
4751 *
4752 * param_tcs_offchip_offset, param_tcs_factor_offset,
4753 * param_tcs_offchip_layout, and param_rw_buffers
4754 * should be passed to the epilog.
4755 */
4756 for (i = 0; i <= 8 + GFX9_SGPR_TCS_OUT_LAYOUT; i++)
4757 returns[num_returns++] = ctx->i32; /* SGPRs */
4758 for (i = 0; i < 11; i++)
4759 returns[num_returns++] = ctx->f32; /* VGPRs */
4760 }
4761 break;
4762
4763 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4764 /* Merged stages have 8 system SGPRs at the beginning. */
4765 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
4766 if (HAVE_32BIT_POINTERS) {
4767 declare_per_stage_desc_pointers(ctx, &fninfo,
4768 ctx->type == PIPE_SHADER_GEOMETRY);
4769 } else {
4770 declare_const_and_shader_buffers(ctx, &fninfo,
4771 ctx->type == PIPE_SHADER_GEOMETRY);
4772 }
4773 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4774 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4775 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4776 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4777 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4778 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4779
4780 declare_global_desc_pointers(ctx, &fninfo);
4781 declare_per_stage_desc_pointers(ctx, &fninfo,
4782 (ctx->type == PIPE_SHADER_VERTEX ||
4783 ctx->type == PIPE_SHADER_TESS_EVAL));
4784 if (ctx->type == PIPE_SHADER_VERTEX) {
4785 declare_vs_specific_input_sgprs(ctx, &fninfo);
4786 } else {
4787 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4788 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4789 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4790 /* Declare as many input SGPRs as the VS has. */
4791 if (!HAVE_32BIT_POINTERS)
4792 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4793 }
4794
4795 if (!HAVE_32BIT_POINTERS) {
4796 declare_samplers_and_images(ctx, &fninfo,
4797 ctx->type == PIPE_SHADER_GEOMETRY);
4798 }
4799 if (ctx->type == PIPE_SHADER_VERTEX) {
4800 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4801 ac_array_in_const32_addr_space(ctx->v4i32));
4802 }
4803
4804 /* VGPRs (first GS, then VS/TES) */
4805 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4806 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4807 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4808 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4809 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4810
4811 if (ctx->type == PIPE_SHADER_VERTEX) {
4812 declare_vs_input_vgprs(ctx, &fninfo,
4813 &num_prolog_vgprs);
4814 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4815 declare_tes_input_vgprs(ctx, &fninfo);
4816 }
4817
4818 if (ctx->type == PIPE_SHADER_VERTEX ||
4819 ctx->type == PIPE_SHADER_TESS_EVAL) {
4820 unsigned num_user_sgprs;
4821
4822 if (ctx->type == PIPE_SHADER_VERTEX)
4823 num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR;
4824 else
4825 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
4826
4827 /* ES return values are inputs to GS. */
4828 for (i = 0; i < 8 + num_user_sgprs; i++)
4829 returns[num_returns++] = ctx->i32; /* SGPRs */
4830 for (i = 0; i < 5; i++)
4831 returns[num_returns++] = ctx->f32; /* VGPRs */
4832 }
4833 break;
4834
4835 case PIPE_SHADER_TESS_EVAL:
4836 declare_global_desc_pointers(ctx, &fninfo);
4837 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4838 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4839 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4840 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4841
4842 if (shader->key.as_es) {
4843 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4844 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4845 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4846 } else {
4847 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4848 declare_streamout_params(ctx, &shader->selector->so,
4849 &fninfo);
4850 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4851 }
4852
4853 /* VGPRs */
4854 declare_tes_input_vgprs(ctx, &fninfo);
4855 break;
4856
4857 case PIPE_SHADER_GEOMETRY:
4858 declare_global_desc_pointers(ctx, &fninfo);
4859 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4860 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4861 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4862
4863 /* VGPRs */
4864 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4865 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4866 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4867 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4868 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4869 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4870 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4871 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4872 break;
4873
4874 case PIPE_SHADER_FRAGMENT:
4875 declare_global_desc_pointers(ctx, &fninfo);
4876 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4877 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4878 add_arg_assign_checked(&fninfo, ARG_SGPR, ctx->i32,
4879 &ctx->abi.prim_mask, SI_PARAM_PRIM_MASK);
4880
4881 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4882 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4883 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4884 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4885 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4886 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4887 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4888 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4889 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4890 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4891 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4892 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4893 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4894 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4895 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4896 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4897 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4898 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4899 shader->info.face_vgpr_index = 20;
4900 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4901 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4902 shader->info.ancillary_vgpr_index = 21;
4903 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4904 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4905 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4906
4907 /* Color inputs from the prolog. */
4908 if (shader->selector->info.colors_read) {
4909 unsigned num_color_elements =
4910 util_bitcount(shader->selector->info.colors_read);
4911
4912 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4913 for (i = 0; i < num_color_elements; i++)
4914 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4915
4916 num_prolog_vgprs += num_color_elements;
4917 }
4918
4919 /* Outputs for the epilog. */
4920 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4921 num_returns =
4922 num_return_sgprs +
4923 util_bitcount(shader->selector->info.colors_written) * 4 +
4924 shader->selector->info.writes_z +
4925 shader->selector->info.writes_stencil +
4926 shader->selector->info.writes_samplemask +
4927 1 /* SampleMaskIn */;
4928
4929 num_returns = MAX2(num_returns,
4930 num_return_sgprs +
4931 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4932
4933 for (i = 0; i < num_return_sgprs; i++)
4934 returns[i] = ctx->i32;
4935 for (; i < num_returns; i++)
4936 returns[i] = ctx->f32;
4937 break;
4938
4939 case PIPE_SHADER_COMPUTE:
4940 declare_global_desc_pointers(ctx, &fninfo);
4941 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4942 if (shader->selector->info.uses_grid_size)
4943 add_arg_assign(&fninfo, ARG_SGPR, v3i32, &ctx->abi.num_work_groups);
4944 if (shader->selector->info.uses_block_size &&
4945 shader->selector->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
4946 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4947
4948 unsigned cs_user_data_dwords =
4949 shader->selector->info.properties[TGSI_PROPERTY_CS_USER_DATA_DWORDS];
4950 if (cs_user_data_dwords) {
4951 ctx->param_cs_user_data = add_arg(&fninfo, ARG_SGPR,
4952 LLVMVectorType(ctx->i32, cs_user_data_dwords));
4953 }
4954
4955 for (i = 0; i < 3; i++) {
4956 ctx->abi.workgroup_ids[i] = NULL;
4957 if (shader->selector->info.uses_block_id[i])
4958 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->abi.workgroup_ids[i]);
4959 }
4960
4961 add_arg_assign(&fninfo, ARG_VGPR, v3i32, &ctx->abi.local_invocation_ids);
4962 break;
4963 default:
4964 assert(0 && "unimplemented shader");
4965 return;
4966 }
4967
4968 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4969 si_get_max_workgroup_size(shader));
4970
4971 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4972 if (ctx->type == PIPE_SHADER_FRAGMENT && !ctx->shader->is_monolithic) {
4973 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4974 "InitialPSInputAddr",
4975 S_0286D0_PERSP_SAMPLE_ENA(1) |
4976 S_0286D0_PERSP_CENTER_ENA(1) |
4977 S_0286D0_PERSP_CENTROID_ENA(1) |
4978 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4979 S_0286D0_LINEAR_CENTER_ENA(1) |
4980 S_0286D0_LINEAR_CENTROID_ENA(1) |
4981 S_0286D0_FRONT_FACE_ENA(1) |
4982 S_0286D0_ANCILLARY_ENA(1) |
4983 S_0286D0_POS_FIXED_PT_ENA(1));
4984 }
4985
4986 shader->info.num_input_sgprs = 0;
4987 shader->info.num_input_vgprs = 0;
4988
4989 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4990 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
4991
4992 for (; i < fninfo.num_params; ++i)
4993 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
4994
4995 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4996 shader->info.num_input_vgprs -= num_prolog_vgprs;
4997
4998 if (shader->key.as_ls ||
4999 ctx->type == PIPE_SHADER_TESS_CTRL ||
5000 /* GFX9 has the ESGS ring buffer in LDS. */
5001 type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY)
5002 ac_declare_lds_as_pointer(&ctx->ac);
5003 }
5004
5005 /**
5006 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5007 * for later use.
5008 */
5009 static void preload_ring_buffers(struct si_shader_context *ctx)
5010 {
5011 LLVMBuilderRef builder = ctx->ac.builder;
5012
5013 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5014 ctx->param_rw_buffers);
5015
5016 if (ctx->screen->info.chip_class <= VI &&
5017 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
5018 unsigned ring =
5019 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5020 : SI_ES_RING_ESGS;
5021 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
5022
5023 ctx->esgs_ring =
5024 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5025 }
5026
5027 if (ctx->shader->is_gs_copy_shader) {
5028 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5029
5030 ctx->gsvs_ring[0] =
5031 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5032 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5033 const struct si_shader_selector *sel = ctx->shader->selector;
5034 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5035 LLVMValueRef base_ring;
5036
5037 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5038
5039 /* The conceptual layout of the GSVS ring is
5040 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5041 * but the real memory layout is swizzled across
5042 * threads:
5043 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5044 * t16v0c0 ..
5045 * Override the buffer descriptor accordingly.
5046 */
5047 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5048 uint64_t stream_offset = 0;
5049
5050 for (unsigned stream = 0; stream < 4; ++stream) {
5051 unsigned num_components;
5052 unsigned stride;
5053 unsigned num_records;
5054 LLVMValueRef ring, tmp;
5055
5056 num_components = sel->info.num_stream_output_components[stream];
5057 if (!num_components)
5058 continue;
5059
5060 stride = 4 * num_components * sel->gs_max_out_vertices;
5061
5062 /* Limit on the stride field for <= CIK. */
5063 assert(stride < (1 << 14));
5064
5065 num_records = 64;
5066
5067 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5068 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
5069 tmp = LLVMBuildAdd(builder, tmp,
5070 LLVMConstInt(ctx->i64,
5071 stream_offset, 0), "");
5072 stream_offset += stride * 64;
5073
5074 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5075 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5076 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5077 tmp = LLVMBuildOr(builder, tmp,
5078 LLVMConstInt(ctx->i32,
5079 S_008F04_STRIDE(stride) |
5080 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5081 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5082 ring = LLVMBuildInsertElement(builder, ring,
5083 LLVMConstInt(ctx->i32, num_records, 0),
5084 LLVMConstInt(ctx->i32, 2, 0), "");
5085 ring = LLVMBuildInsertElement(builder, ring,
5086 LLVMConstInt(ctx->i32,
5087 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5088 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5089 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5090 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5091 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5092 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5093 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5094 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5095 S_008F0C_ADD_TID_ENABLE(1),
5096 0),
5097 LLVMConstInt(ctx->i32, 3, 0), "");
5098
5099 ctx->gsvs_ring[stream] = ring;
5100 }
5101 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
5102 ctx->tess_offchip_ring = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TES);
5103 }
5104 }
5105
5106 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5107 LLVMValueRef param_rw_buffers,
5108 unsigned param_pos_fixed_pt)
5109 {
5110 LLVMBuilderRef builder = ctx->ac.builder;
5111 LLVMValueRef slot, desc, offset, row, bit, address[2];
5112
5113 /* Use the fixed-point gl_FragCoord input.
5114 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5115 * per coordinate to get the repeating effect.
5116 */
5117 address[0] = si_unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5118 address[1] = si_unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5119
5120 /* Load the buffer descriptor. */
5121 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5122 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
5123
5124 /* The stipple pattern is 32x32, each row has 32 bits. */
5125 offset = LLVMBuildMul(builder, address[1],
5126 LLVMConstInt(ctx->i32, 4, 0), "");
5127 row = buffer_load_const(ctx, desc, offset);
5128 row = ac_to_integer(&ctx->ac, row);
5129 bit = LLVMBuildLShr(builder, row, address[0], "");
5130 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5131 ac_build_kill_if_false(&ctx->ac, bit);
5132 }
5133
5134 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5135 struct si_shader_config *conf,
5136 unsigned symbol_offset)
5137 {
5138 unsigned i;
5139 const unsigned char *config =
5140 ac_shader_binary_config_start(binary, symbol_offset);
5141 bool really_needs_scratch = false;
5142
5143 /* LLVM adds SGPR spills to the scratch size.
5144 * Find out if we really need the scratch buffer.
5145 */
5146 for (i = 0; i < binary->reloc_count; i++) {
5147 const struct ac_shader_reloc *reloc = &binary->relocs[i];
5148
5149 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5150 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5151 really_needs_scratch = true;
5152 break;
5153 }
5154 }
5155
5156 /* XXX: We may be able to emit some of these values directly rather than
5157 * extracting fields to be emitted later.
5158 */
5159
5160 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5161 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5162 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5163 switch (reg) {
5164 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5165 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5166 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5167 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
5168 case R_00B848_COMPUTE_PGM_RSRC1:
5169 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5170 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5171 conf->float_mode = G_00B028_FLOAT_MODE(value);
5172 conf->rsrc1 = value;
5173 break;
5174 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5175 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5176 break;
5177 case R_00B84C_COMPUTE_PGM_RSRC2:
5178 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5179 conf->rsrc2 = value;
5180 break;
5181 case R_0286CC_SPI_PS_INPUT_ENA:
5182 conf->spi_ps_input_ena = value;
5183 break;
5184 case R_0286D0_SPI_PS_INPUT_ADDR:
5185 conf->spi_ps_input_addr = value;
5186 break;
5187 case R_0286E8_SPI_TMPRING_SIZE:
5188 case R_00B860_COMPUTE_TMPRING_SIZE:
5189 /* WAVESIZE is in units of 256 dwords. */
5190 if (really_needs_scratch)
5191 conf->scratch_bytes_per_wave =
5192 G_00B860_WAVESIZE(value) * 256 * 4;
5193 break;
5194 case 0x4: /* SPILLED_SGPRS */
5195 conf->spilled_sgprs = value;
5196 break;
5197 case 0x8: /* SPILLED_VGPRS */
5198 conf->spilled_vgprs = value;
5199 break;
5200 default:
5201 {
5202 static bool printed;
5203
5204 if (!printed) {
5205 fprintf(stderr, "Warning: LLVM emitted unknown "
5206 "config register: 0x%x\n", reg);
5207 printed = true;
5208 }
5209 }
5210 break;
5211 }
5212 }
5213
5214 if (!conf->spi_ps_input_addr)
5215 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5216 }
5217
5218 void si_shader_apply_scratch_relocs(struct si_shader *shader,
5219 uint64_t scratch_va)
5220 {
5221 unsigned i;
5222 uint32_t scratch_rsrc_dword0 = scratch_va;
5223 uint32_t scratch_rsrc_dword1 =
5224 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5225
5226 /* Enable scratch coalescing. */
5227 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5228
5229 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5230 const struct ac_shader_reloc *reloc =
5231 &shader->binary.relocs[i];
5232 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5233 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5234 &scratch_rsrc_dword0, 4);
5235 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5236 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5237 &scratch_rsrc_dword1, 4);
5238 }
5239 }
5240 }
5241
5242 /* For the UMR disassembler. */
5243 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
5244 #define DEBUGGER_NUM_MARKERS 5
5245
5246 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
5247 {
5248 unsigned size = shader->binary.code_size;
5249
5250 if (shader->prolog)
5251 size += shader->prolog->binary.code_size;
5252 if (shader->previous_stage)
5253 size += shader->previous_stage->binary.code_size;
5254 if (shader->prolog2)
5255 size += shader->prolog2->binary.code_size;
5256 if (shader->epilog)
5257 size += shader->epilog->binary.code_size;
5258 return size + DEBUGGER_NUM_MARKERS * 4;
5259 }
5260
5261 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5262 {
5263 const struct ac_shader_binary *prolog =
5264 shader->prolog ? &shader->prolog->binary : NULL;
5265 const struct ac_shader_binary *previous_stage =
5266 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5267 const struct ac_shader_binary *prolog2 =
5268 shader->prolog2 ? &shader->prolog2->binary : NULL;
5269 const struct ac_shader_binary *epilog =
5270 shader->epilog ? &shader->epilog->binary : NULL;
5271 const struct ac_shader_binary *mainb = &shader->binary;
5272 unsigned bo_size = si_get_shader_binary_size(shader) +
5273 (!epilog ? mainb->rodata_size : 0);
5274 unsigned char *ptr;
5275
5276 assert(!prolog || !prolog->rodata_size);
5277 assert(!previous_stage || !previous_stage->rodata_size);
5278 assert(!prolog2 || !prolog2->rodata_size);
5279 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5280 !mainb->rodata_size);
5281 assert(!epilog || !epilog->rodata_size);
5282
5283 r600_resource_reference(&shader->bo, NULL);
5284 shader->bo = si_aligned_buffer_create(&sscreen->b,
5285 sscreen->cpdma_prefetch_writes_memory ?
5286 0 : SI_RESOURCE_FLAG_READ_ONLY,
5287 PIPE_USAGE_IMMUTABLE,
5288 align(bo_size, SI_CPDMA_ALIGNMENT),
5289 256);
5290 if (!shader->bo)
5291 return -ENOMEM;
5292
5293 /* Upload. */
5294 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5295 PIPE_TRANSFER_READ_WRITE |
5296 PIPE_TRANSFER_UNSYNCHRONIZED |
5297 RADEON_TRANSFER_TEMPORARY);
5298
5299 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5300 * endian-independent. */
5301 if (prolog) {
5302 memcpy(ptr, prolog->code, prolog->code_size);
5303 ptr += prolog->code_size;
5304 }
5305 if (previous_stage) {
5306 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5307 ptr += previous_stage->code_size;
5308 }
5309 if (prolog2) {
5310 memcpy(ptr, prolog2->code, prolog2->code_size);
5311 ptr += prolog2->code_size;
5312 }
5313
5314 memcpy(ptr, mainb->code, mainb->code_size);
5315 ptr += mainb->code_size;
5316
5317 if (epilog) {
5318 memcpy(ptr, epilog->code, epilog->code_size);
5319 ptr += epilog->code_size;
5320 } else if (mainb->rodata_size > 0) {
5321 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5322 ptr += mainb->rodata_size;
5323 }
5324
5325 /* Add end-of-code markers for the UMR disassembler. */
5326 uint32_t *ptr32 = (uint32_t*)ptr;
5327 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
5328 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
5329
5330 sscreen->ws->buffer_unmap(shader->bo->buf);
5331 return 0;
5332 }
5333
5334 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5335 struct pipe_debug_callback *debug,
5336 const char *name, FILE *file)
5337 {
5338 char *line, *p;
5339 unsigned i, count;
5340
5341 if (binary->disasm_string) {
5342 fprintf(file, "Shader %s disassembly:\n", name);
5343 fprintf(file, "%s", binary->disasm_string);
5344
5345 if (debug && debug->debug_message) {
5346 /* Very long debug messages are cut off, so send the
5347 * disassembly one line at a time. This causes more
5348 * overhead, but on the plus side it simplifies
5349 * parsing of resulting logs.
5350 */
5351 pipe_debug_message(debug, SHADER_INFO,
5352 "Shader Disassembly Begin");
5353
5354 line = binary->disasm_string;
5355 while (*line) {
5356 p = util_strchrnul(line, '\n');
5357 count = p - line;
5358
5359 if (count) {
5360 pipe_debug_message(debug, SHADER_INFO,
5361 "%.*s", count, line);
5362 }
5363
5364 if (!*p)
5365 break;
5366 line = p + 1;
5367 }
5368
5369 pipe_debug_message(debug, SHADER_INFO,
5370 "Shader Disassembly End");
5371 }
5372 } else {
5373 fprintf(file, "Shader %s binary:\n", name);
5374 for (i = 0; i < binary->code_size; i += 4) {
5375 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5376 binary->code[i + 3], binary->code[i + 2],
5377 binary->code[i + 1], binary->code[i]);
5378 }
5379 }
5380 }
5381
5382 static void si_calculate_max_simd_waves(struct si_shader *shader)
5383 {
5384 struct si_screen *sscreen = shader->selector->screen;
5385 struct si_shader_config *conf = &shader->config;
5386 unsigned num_inputs = shader->selector->info.num_inputs;
5387 unsigned lds_increment = sscreen->info.chip_class >= CIK ? 512 : 256;
5388 unsigned lds_per_wave = 0;
5389 unsigned max_simd_waves;
5390
5391 max_simd_waves = ac_get_max_simd_waves(sscreen->info.family);
5392
5393 /* Compute LDS usage for PS. */
5394 switch (shader->selector->type) {
5395 case PIPE_SHADER_FRAGMENT:
5396 /* The minimum usage per wave is (num_inputs * 48). The maximum
5397 * usage is (num_inputs * 48 * 16).
5398 * We can get anything in between and it varies between waves.
5399 *
5400 * The 48 bytes per input for a single primitive is equal to
5401 * 4 bytes/component * 4 components/input * 3 points.
5402 *
5403 * Other stages don't know the size at compile time or don't
5404 * allocate LDS per wave, but instead they do it per thread group.
5405 */
5406 lds_per_wave = conf->lds_size * lds_increment +
5407 align(num_inputs * 48, lds_increment);
5408 break;
5409 case PIPE_SHADER_COMPUTE:
5410 if (shader->selector) {
5411 unsigned max_workgroup_size =
5412 si_get_max_workgroup_size(shader);
5413 lds_per_wave = (conf->lds_size * lds_increment) /
5414 DIV_ROUND_UP(max_workgroup_size, 64);
5415 }
5416 break;
5417 }
5418
5419 /* Compute the per-SIMD wave counts. */
5420 if (conf->num_sgprs) {
5421 if (sscreen->info.chip_class >= VI)
5422 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5423 else
5424 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5425 }
5426
5427 if (conf->num_vgprs)
5428 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5429
5430 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5431 * 16KB makes some SIMDs unoccupied). */
5432 if (lds_per_wave)
5433 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5434
5435 conf->max_simd_waves = max_simd_waves;
5436 }
5437
5438 void si_shader_dump_stats_for_shader_db(const struct si_shader *shader,
5439 struct pipe_debug_callback *debug)
5440 {
5441 const struct si_shader_config *conf = &shader->config;
5442
5443 pipe_debug_message(debug, SHADER_INFO,
5444 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5445 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5446 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5447 conf->num_sgprs, conf->num_vgprs,
5448 si_get_shader_binary_size(shader),
5449 conf->lds_size, conf->scratch_bytes_per_wave,
5450 conf->max_simd_waves, conf->spilled_sgprs,
5451 conf->spilled_vgprs, conf->private_mem_vgprs);
5452 }
5453
5454 static void si_shader_dump_stats(struct si_screen *sscreen,
5455 const struct si_shader *shader,
5456 unsigned processor,
5457 FILE *file,
5458 bool check_debug_option)
5459 {
5460 const struct si_shader_config *conf = &shader->config;
5461
5462 if (!check_debug_option ||
5463 si_can_dump_shader(sscreen, processor)) {
5464 if (processor == PIPE_SHADER_FRAGMENT) {
5465 fprintf(file, "*** SHADER CONFIG ***\n"
5466 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5467 "SPI_PS_INPUT_ENA = 0x%04x\n",
5468 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5469 }
5470
5471 fprintf(file, "*** SHADER STATS ***\n"
5472 "SGPRS: %d\n"
5473 "VGPRS: %d\n"
5474 "Spilled SGPRs: %d\n"
5475 "Spilled VGPRs: %d\n"
5476 "Private memory VGPRs: %d\n"
5477 "Code Size: %d bytes\n"
5478 "LDS: %d blocks\n"
5479 "Scratch: %d bytes per wave\n"
5480 "Max Waves: %d\n"
5481 "********************\n\n\n",
5482 conf->num_sgprs, conf->num_vgprs,
5483 conf->spilled_sgprs, conf->spilled_vgprs,
5484 conf->private_mem_vgprs,
5485 si_get_shader_binary_size(shader),
5486 conf->lds_size, conf->scratch_bytes_per_wave,
5487 conf->max_simd_waves);
5488 }
5489 }
5490
5491 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5492 {
5493 switch (processor) {
5494 case PIPE_SHADER_VERTEX:
5495 if (shader->key.as_es)
5496 return "Vertex Shader as ES";
5497 else if (shader->key.as_ls)
5498 return "Vertex Shader as LS";
5499 else
5500 return "Vertex Shader as VS";
5501 case PIPE_SHADER_TESS_CTRL:
5502 return "Tessellation Control Shader";
5503 case PIPE_SHADER_TESS_EVAL:
5504 if (shader->key.as_es)
5505 return "Tessellation Evaluation Shader as ES";
5506 else
5507 return "Tessellation Evaluation Shader as VS";
5508 case PIPE_SHADER_GEOMETRY:
5509 if (shader->is_gs_copy_shader)
5510 return "GS Copy Shader as VS";
5511 else
5512 return "Geometry Shader";
5513 case PIPE_SHADER_FRAGMENT:
5514 return "Pixel Shader";
5515 case PIPE_SHADER_COMPUTE:
5516 return "Compute Shader";
5517 default:
5518 return "Unknown Shader";
5519 }
5520 }
5521
5522 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5523 struct pipe_debug_callback *debug, unsigned processor,
5524 FILE *file, bool check_debug_option)
5525 {
5526 if (!check_debug_option ||
5527 si_can_dump_shader(sscreen, processor))
5528 si_dump_shader_key(processor, shader, file);
5529
5530 if (!check_debug_option && shader->binary.llvm_ir_string) {
5531 if (shader->previous_stage &&
5532 shader->previous_stage->binary.llvm_ir_string) {
5533 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5534 si_get_shader_name(shader, processor));
5535 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5536 }
5537
5538 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5539 si_get_shader_name(shader, processor));
5540 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5541 }
5542
5543 if (!check_debug_option ||
5544 (si_can_dump_shader(sscreen, processor) &&
5545 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5546 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5547
5548 if (shader->prolog)
5549 si_shader_dump_disassembly(&shader->prolog->binary,
5550 debug, "prolog", file);
5551 if (shader->previous_stage)
5552 si_shader_dump_disassembly(&shader->previous_stage->binary,
5553 debug, "previous stage", file);
5554 if (shader->prolog2)
5555 si_shader_dump_disassembly(&shader->prolog2->binary,
5556 debug, "prolog2", file);
5557
5558 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5559
5560 if (shader->epilog)
5561 si_shader_dump_disassembly(&shader->epilog->binary,
5562 debug, "epilog", file);
5563 fprintf(file, "\n");
5564 }
5565
5566 si_shader_dump_stats(sscreen, shader, processor, file,
5567 check_debug_option);
5568 }
5569
5570 static int si_compile_llvm(struct si_screen *sscreen,
5571 struct ac_shader_binary *binary,
5572 struct si_shader_config *conf,
5573 struct ac_llvm_compiler *compiler,
5574 LLVMModuleRef mod,
5575 struct pipe_debug_callback *debug,
5576 unsigned processor,
5577 const char *name,
5578 bool less_optimized)
5579 {
5580 int r = 0;
5581 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5582
5583 if (si_can_dump_shader(sscreen, processor)) {
5584 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5585
5586 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5587 fprintf(stderr, "%s LLVM IR:\n\n", name);
5588 ac_dump_module(mod);
5589 fprintf(stderr, "\n");
5590 }
5591 }
5592
5593 if (sscreen->record_llvm_ir) {
5594 char *ir = LLVMPrintModuleToString(mod);
5595 binary->llvm_ir_string = strdup(ir);
5596 LLVMDisposeMessage(ir);
5597 }
5598
5599 if (!si_replace_shader(count, binary)) {
5600 r = si_llvm_compile(mod, binary, compiler, debug,
5601 less_optimized);
5602 if (r)
5603 return r;
5604 }
5605
5606 si_shader_binary_read_config(binary, conf, 0);
5607
5608 /* Enable 64-bit and 16-bit denormals, because there is no performance
5609 * cost.
5610 *
5611 * If denormals are enabled, all floating-point output modifiers are
5612 * ignored.
5613 *
5614 * Don't enable denormals for 32-bit floats, because:
5615 * - Floating-point output modifiers would be ignored by the hw.
5616 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5617 * have to stop using those.
5618 * - SI & CI would be very slow.
5619 */
5620 conf->float_mode |= V_00B028_FP_64_DENORMS;
5621
5622 FREE(binary->config);
5623 FREE(binary->global_symbol_offsets);
5624 binary->config = NULL;
5625 binary->global_symbol_offsets = NULL;
5626
5627 /* Some shaders can't have rodata because their binaries can be
5628 * concatenated.
5629 */
5630 if (binary->rodata_size &&
5631 (processor == PIPE_SHADER_VERTEX ||
5632 processor == PIPE_SHADER_TESS_CTRL ||
5633 processor == PIPE_SHADER_TESS_EVAL ||
5634 processor == PIPE_SHADER_FRAGMENT)) {
5635 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5636 return -EINVAL;
5637 }
5638
5639 return r;
5640 }
5641
5642 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5643 {
5644 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5645 LLVMBuildRetVoid(ctx->ac.builder);
5646 else
5647 LLVMBuildRet(ctx->ac.builder, ret);
5648 }
5649
5650 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5651 struct si_shader *
5652 si_generate_gs_copy_shader(struct si_screen *sscreen,
5653 struct ac_llvm_compiler *compiler,
5654 struct si_shader_selector *gs_selector,
5655 struct pipe_debug_callback *debug)
5656 {
5657 struct si_shader_context ctx;
5658 struct si_shader *shader;
5659 LLVMBuilderRef builder;
5660 struct si_shader_output_values outputs[SI_MAX_VS_OUTPUTS];
5661 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5662 int i, r;
5663
5664
5665 shader = CALLOC_STRUCT(si_shader);
5666 if (!shader)
5667 return NULL;
5668
5669 /* We can leave the fence as permanently signaled because the GS copy
5670 * shader only becomes visible globally after it has been compiled. */
5671 util_queue_fence_init(&shader->ready);
5672
5673 shader->selector = gs_selector;
5674 shader->is_gs_copy_shader = true;
5675
5676 si_init_shader_ctx(&ctx, sscreen, compiler);
5677 ctx.shader = shader;
5678 ctx.type = PIPE_SHADER_VERTEX;
5679
5680 builder = ctx.ac.builder;
5681
5682 create_function(&ctx);
5683 preload_ring_buffers(&ctx);
5684
5685 LLVMValueRef voffset =
5686 LLVMBuildMul(ctx.ac.builder, ctx.abi.vertex_id,
5687 LLVMConstInt(ctx.i32, 4, 0), "");
5688
5689 /* Fetch the vertex stream ID.*/
5690 LLVMValueRef stream_id;
5691
5692 if (gs_selector->so.num_outputs)
5693 stream_id = si_unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5694 else
5695 stream_id = ctx.i32_0;
5696
5697 /* Fill in output information. */
5698 for (i = 0; i < gsinfo->num_outputs; ++i) {
5699 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5700 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5701
5702 for (int chan = 0; chan < 4; chan++) {
5703 outputs[i].vertex_stream[chan] =
5704 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5705 }
5706 }
5707
5708 LLVMBasicBlockRef end_bb;
5709 LLVMValueRef switch_inst;
5710
5711 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5712 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5713
5714 for (int stream = 0; stream < 4; stream++) {
5715 LLVMBasicBlockRef bb;
5716 unsigned offset;
5717
5718 if (!gsinfo->num_stream_output_components[stream])
5719 continue;
5720
5721 if (stream > 0 && !gs_selector->so.num_outputs)
5722 continue;
5723
5724 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5725 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5726 LLVMPositionBuilderAtEnd(builder, bb);
5727
5728 /* Fetch vertex data from GSVS ring */
5729 offset = 0;
5730 for (i = 0; i < gsinfo->num_outputs; ++i) {
5731 for (unsigned chan = 0; chan < 4; chan++) {
5732 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5733 outputs[i].vertex_stream[chan] != stream) {
5734 outputs[i].values[chan] = LLVMGetUndef(ctx.f32);
5735 continue;
5736 }
5737
5738 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5739 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5740 offset++;
5741
5742 outputs[i].values[chan] =
5743 ac_build_buffer_load(&ctx.ac,
5744 ctx.gsvs_ring[0], 1,
5745 ctx.i32_0, voffset,
5746 soffset, 0, 1, 1,
5747 true, false);
5748 }
5749 }
5750
5751 /* Streamout and exports. */
5752 if (gs_selector->so.num_outputs) {
5753 si_llvm_emit_streamout(&ctx, outputs,
5754 gsinfo->num_outputs,
5755 stream);
5756 }
5757
5758 if (stream == 0) {
5759 /* Vertex color clamping.
5760 *
5761 * This uses a state constant loaded in a user data SGPR and
5762 * an IF statement is added that clamps all colors if the constant
5763 * is true.
5764 */
5765 struct lp_build_if_state if_ctx;
5766 LLVMValueRef v[2], cond = NULL;
5767 LLVMBasicBlockRef blocks[2];
5768
5769 for (unsigned i = 0; i < gsinfo->num_outputs; i++) {
5770 if (gsinfo->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
5771 gsinfo->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
5772 continue;
5773
5774 /* We've found a color. */
5775 if (!cond) {
5776 /* The state is in the first bit of the user SGPR. */
5777 cond = LLVMGetParam(ctx.main_fn,
5778 ctx.param_vs_state_bits);
5779 cond = LLVMBuildTrunc(ctx.ac.builder, cond,
5780 ctx.i1, "");
5781 lp_build_if(&if_ctx, &ctx.gallivm, cond);
5782 /* Remember blocks for Phi. */
5783 blocks[0] = if_ctx.true_block;
5784 blocks[1] = if_ctx.entry_block;
5785 }
5786
5787 for (unsigned j = 0; j < 4; j++) {
5788 /* Insert clamp into the true block. */
5789 v[0] = ac_build_clamp(&ctx.ac, outputs[i].values[j]);
5790 v[1] = outputs[i].values[j];
5791
5792 /* Insert Phi into the endif block. */
5793 LLVMPositionBuilderAtEnd(ctx.ac.builder, if_ctx.merge_block);
5794 outputs[i].values[j] = ac_build_phi(&ctx.ac, ctx.f32, 2, v, blocks);
5795 LLVMPositionBuilderAtEnd(ctx.ac.builder, if_ctx.true_block);
5796 }
5797 }
5798 if (cond)
5799 lp_build_endif(&if_ctx);
5800
5801 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5802 }
5803
5804 LLVMBuildBr(builder, end_bb);
5805 }
5806
5807 LLVMPositionBuilderAtEnd(builder, end_bb);
5808
5809 LLVMBuildRetVoid(ctx.ac.builder);
5810
5811 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5812 si_llvm_optimize_module(&ctx);
5813
5814 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5815 &ctx.shader->config, ctx.compiler,
5816 ctx.ac.module,
5817 debug, PIPE_SHADER_GEOMETRY,
5818 "GS Copy Shader", false);
5819 if (!r) {
5820 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5821 fprintf(stderr, "GS Copy Shader:\n");
5822 si_shader_dump(sscreen, ctx.shader, debug,
5823 PIPE_SHADER_GEOMETRY, stderr, true);
5824 r = si_shader_binary_upload(sscreen, ctx.shader);
5825 }
5826
5827 si_llvm_dispose(&ctx);
5828
5829 if (r != 0) {
5830 FREE(shader);
5831 shader = NULL;
5832 }
5833 return shader;
5834 }
5835
5836 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5837 const struct si_vs_prolog_bits *prolog,
5838 const char *prefix, FILE *f)
5839 {
5840 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5841 prefix, prolog->instance_divisor_is_one);
5842 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5843 prefix, prolog->instance_divisor_is_fetched);
5844 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5845 prefix, prolog->ls_vgpr_fix);
5846
5847 fprintf(f, " mono.vs.fix_fetch = {");
5848 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5849 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5850 fprintf(f, "}\n");
5851 }
5852
5853 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5854 FILE *f)
5855 {
5856 const struct si_shader_key *key = &shader->key;
5857
5858 fprintf(f, "SHADER KEY\n");
5859
5860 switch (processor) {
5861 case PIPE_SHADER_VERTEX:
5862 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5863 "part.vs.prolog", f);
5864 fprintf(f, " as_es = %u\n", key->as_es);
5865 fprintf(f, " as_ls = %u\n", key->as_ls);
5866 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5867 key->mono.u.vs_export_prim_id);
5868 break;
5869
5870 case PIPE_SHADER_TESS_CTRL:
5871 if (shader->selector->screen->info.chip_class >= GFX9) {
5872 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5873 "part.tcs.ls_prolog", f);
5874 }
5875 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5876 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5877 break;
5878
5879 case PIPE_SHADER_TESS_EVAL:
5880 fprintf(f, " as_es = %u\n", key->as_es);
5881 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5882 key->mono.u.vs_export_prim_id);
5883 break;
5884
5885 case PIPE_SHADER_GEOMETRY:
5886 if (shader->is_gs_copy_shader)
5887 break;
5888
5889 if (shader->selector->screen->info.chip_class >= GFX9 &&
5890 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5891 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5892 "part.gs.vs_prolog", f);
5893 }
5894 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5895 break;
5896
5897 case PIPE_SHADER_COMPUTE:
5898 break;
5899
5900 case PIPE_SHADER_FRAGMENT:
5901 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5902 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5903 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5904 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5905 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5906 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5907 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5908 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5909 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5910 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5911 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5912 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5913 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5914 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5915 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5916 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5917 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5918 break;
5919
5920 default:
5921 assert(0);
5922 }
5923
5924 if ((processor == PIPE_SHADER_GEOMETRY ||
5925 processor == PIPE_SHADER_TESS_EVAL ||
5926 processor == PIPE_SHADER_VERTEX) &&
5927 !key->as_es && !key->as_ls) {
5928 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5929 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5930 }
5931 }
5932
5933 static void si_init_shader_ctx(struct si_shader_context *ctx,
5934 struct si_screen *sscreen,
5935 struct ac_llvm_compiler *compiler)
5936 {
5937 struct lp_build_tgsi_context *bld_base;
5938
5939 si_llvm_context_init(ctx, sscreen, compiler);
5940
5941 bld_base = &ctx->bld_base;
5942 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5943
5944 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID].emit = build_interp_intrinsic;
5945 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE].emit = build_interp_intrinsic;
5946 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET].emit = build_interp_intrinsic;
5947
5948 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5949
5950 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5951
5952 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5953 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5954 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5955 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5956
5957 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5958 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5959 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5960 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5961 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5962 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5963 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5964 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5965
5966 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5967 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_tgsi_emit_primitive;
5968 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5969 }
5970
5971 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5972 {
5973 struct si_shader *shader = ctx->shader;
5974 struct tgsi_shader_info *info = &shader->selector->info;
5975
5976 if ((ctx->type != PIPE_SHADER_VERTEX &&
5977 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5978 shader->key.as_ls ||
5979 shader->key.as_es)
5980 return;
5981
5982 ac_optimize_vs_outputs(&ctx->ac,
5983 ctx->main_fn,
5984 shader->info.vs_output_param_offset,
5985 info->num_outputs,
5986 &shader->info.nr_param_exports);
5987 }
5988
5989 static void si_init_exec_from_input(struct si_shader_context *ctx,
5990 unsigned param, unsigned bitoffset)
5991 {
5992 LLVMValueRef args[] = {
5993 LLVMGetParam(ctx->main_fn, param),
5994 LLVMConstInt(ctx->i32, bitoffset, 0),
5995 };
5996 ac_build_intrinsic(&ctx->ac,
5997 "llvm.amdgcn.init.exec.from.input",
5998 ctx->voidt, args, 2, AC_FUNC_ATTR_CONVERGENT);
5999 }
6000
6001 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
6002 const struct si_vs_prolog_bits *key)
6003 {
6004 /* VGPR initialization fixup for Vega10 and Raven is always done in the
6005 * VS prolog. */
6006 return sel->vs_needs_prolog || key->ls_vgpr_fix;
6007 }
6008
6009 static bool si_compile_tgsi_main(struct si_shader_context *ctx)
6010 {
6011 struct si_shader *shader = ctx->shader;
6012 struct si_shader_selector *sel = shader->selector;
6013 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6014
6015 // TODO clean all this up!
6016 switch (ctx->type) {
6017 case PIPE_SHADER_VERTEX:
6018 ctx->load_input = declare_input_vs;
6019 if (shader->key.as_ls)
6020 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
6021 else if (shader->key.as_es)
6022 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6023 else
6024 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6025 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6026 ctx->abi.load_base_vertex = get_base_vertex;
6027 break;
6028 case PIPE_SHADER_TESS_CTRL:
6029 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6030 ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
6031 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6032 bld_base->emit_store = store_output_tcs;
6033 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
6034 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
6035 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6036 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6037 break;
6038 case PIPE_SHADER_TESS_EVAL:
6039 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6040 ctx->abi.load_tess_varyings = si_nir_load_input_tes;
6041 ctx->abi.load_tess_coord = si_load_tess_coord;
6042 ctx->abi.load_tess_level = si_load_tess_level;
6043 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6044 if (shader->key.as_es)
6045 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6046 else
6047 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6048 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6049 break;
6050 case PIPE_SHADER_GEOMETRY:
6051 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6052 ctx->abi.load_inputs = si_nir_load_input_gs;
6053 ctx->abi.emit_vertex = si_llvm_emit_vertex;
6054 ctx->abi.emit_primitive = si_llvm_emit_primitive;
6055 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
6056 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
6057 break;
6058 case PIPE_SHADER_FRAGMENT:
6059 ctx->load_input = declare_input_fs;
6060 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
6061 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6062 ctx->abi.lookup_interp_param = si_nir_lookup_interp_param;
6063 ctx->abi.load_sample_position = load_sample_position;
6064 ctx->abi.load_sample_mask_in = load_sample_mask_in;
6065 ctx->abi.emit_kill = si_llvm_emit_kill;
6066 break;
6067 case PIPE_SHADER_COMPUTE:
6068 ctx->abi.load_local_group_size = get_block_size;
6069 break;
6070 default:
6071 assert(!"Unsupported shader type");
6072 return false;
6073 }
6074
6075 ctx->abi.load_ubo = load_ubo;
6076 ctx->abi.load_ssbo = load_ssbo;
6077
6078 create_function(ctx);
6079 preload_ring_buffers(ctx);
6080
6081 /* For GFX9 merged shaders:
6082 * - Set EXEC for the first shader. If the prolog is present, set
6083 * EXEC there instead.
6084 * - Add a barrier before the second shader.
6085 * - In the second shader, reset EXEC to ~0 and wrap the main part in
6086 * an if-statement. This is required for correctness in geometry
6087 * shaders, to ensure that empty GS waves do not send GS_EMIT and
6088 * GS_CUT messages.
6089 *
6090 * For monolithic merged shaders, the first shader is wrapped in an
6091 * if-block together with its prolog in si_build_wrapper_function.
6092 */
6093 if (ctx->screen->info.chip_class >= GFX9) {
6094 if (!shader->is_monolithic &&
6095 sel->info.num_instructions > 1 && /* not empty shader */
6096 (shader->key.as_es || shader->key.as_ls) &&
6097 (ctx->type == PIPE_SHADER_TESS_EVAL ||
6098 (ctx->type == PIPE_SHADER_VERTEX &&
6099 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
6100 si_init_exec_from_input(ctx,
6101 ctx->param_merged_wave_info, 0);
6102 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6103 ctx->type == PIPE_SHADER_GEOMETRY) {
6104 if (!shader->is_monolithic)
6105 ac_init_exec_full_mask(&ctx->ac);
6106
6107 LLVMValueRef num_threads = si_unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
6108 LLVMValueRef ena =
6109 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
6110 ac_get_thread_id(&ctx->ac), num_threads, "");
6111 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
6112
6113 /* The barrier must execute for all shaders in a
6114 * threadgroup.
6115 *
6116 * Execute the barrier inside the conditional block,
6117 * so that empty waves can jump directly to s_endpgm,
6118 * which will also signal the barrier.
6119 *
6120 * If the shader is TCS and the TCS epilog is present
6121 * and contains a barrier, it will wait there and then
6122 * reach s_endpgm.
6123 */
6124 si_llvm_emit_barrier(NULL, bld_base, NULL);
6125 }
6126 }
6127
6128 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
6129 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
6130 for (unsigned i = 0; i < 6; i++) {
6131 ctx->invoc0_tess_factors[i] =
6132 ac_build_alloca_undef(&ctx->ac, ctx->i32, "");
6133 }
6134 }
6135
6136 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6137 int i;
6138 for (i = 0; i < 4; i++) {
6139 ctx->gs_next_vertex[i] =
6140 ac_build_alloca(&ctx->ac, ctx->i32, "");
6141 }
6142 }
6143
6144 if (sel->force_correct_derivs_after_kill) {
6145 ctx->postponed_kill = ac_build_alloca_undef(&ctx->ac, ctx->i1, "");
6146 /* true = don't kill. */
6147 LLVMBuildStore(ctx->ac.builder, ctx->i1true,
6148 ctx->postponed_kill);
6149 }
6150
6151 if (sel->tokens) {
6152 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6153 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6154 return false;
6155 }
6156 } else {
6157 if (!si_nir_build_llvm(ctx, sel->nir)) {
6158 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
6159 return false;
6160 }
6161 }
6162
6163 si_llvm_build_ret(ctx, ctx->return_value);
6164 return true;
6165 }
6166
6167 /**
6168 * Compute the VS prolog key, which contains all the information needed to
6169 * build the VS prolog function, and set shader->info bits where needed.
6170 *
6171 * \param info Shader info of the vertex shader.
6172 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6173 * \param prolog_key Key of the VS prolog
6174 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6175 * \param key Output shader part key.
6176 */
6177 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
6178 unsigned num_input_sgprs,
6179 const struct si_vs_prolog_bits *prolog_key,
6180 struct si_shader *shader_out,
6181 union si_shader_part_key *key)
6182 {
6183 memset(key, 0, sizeof(*key));
6184 key->vs_prolog.states = *prolog_key;
6185 key->vs_prolog.num_input_sgprs = num_input_sgprs;
6186 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6187 key->vs_prolog.as_ls = shader_out->key.as_ls;
6188 key->vs_prolog.as_es = shader_out->key.as_es;
6189
6190 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
6191 key->vs_prolog.as_ls = 1;
6192 key->vs_prolog.num_merged_next_stage_vgprs = 2;
6193 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
6194 key->vs_prolog.as_es = 1;
6195 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6196 }
6197
6198 /* Enable loading the InstanceID VGPR. */
6199 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
6200
6201 if ((key->vs_prolog.states.instance_divisor_is_one |
6202 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
6203 shader_out->info.uses_instanceid = true;
6204 }
6205
6206 /**
6207 * Compute the PS prolog key, which contains all the information needed to
6208 * build the PS prolog function, and set related bits in shader->config.
6209 */
6210 static void si_get_ps_prolog_key(struct si_shader *shader,
6211 union si_shader_part_key *key,
6212 bool separate_prolog)
6213 {
6214 struct tgsi_shader_info *info = &shader->selector->info;
6215
6216 memset(key, 0, sizeof(*key));
6217 key->ps_prolog.states = shader->key.part.ps.prolog;
6218 key->ps_prolog.colors_read = info->colors_read;
6219 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6220 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6221 key->ps_prolog.wqm = info->uses_derivatives &&
6222 (key->ps_prolog.colors_read ||
6223 key->ps_prolog.states.force_persp_sample_interp ||
6224 key->ps_prolog.states.force_linear_sample_interp ||
6225 key->ps_prolog.states.force_persp_center_interp ||
6226 key->ps_prolog.states.force_linear_center_interp ||
6227 key->ps_prolog.states.bc_optimize_for_persp ||
6228 key->ps_prolog.states.bc_optimize_for_linear);
6229 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
6230
6231 if (info->colors_read) {
6232 unsigned *color = shader->selector->color_attr_index;
6233
6234 if (shader->key.part.ps.prolog.color_two_side) {
6235 /* BCOLORs are stored after the last input. */
6236 key->ps_prolog.num_interp_inputs = info->num_inputs;
6237 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6238 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6239 }
6240
6241 for (unsigned i = 0; i < 2; i++) {
6242 unsigned interp = info->input_interpolate[color[i]];
6243 unsigned location = info->input_interpolate_loc[color[i]];
6244
6245 if (!(info->colors_read & (0xf << i*4)))
6246 continue;
6247
6248 key->ps_prolog.color_attr_index[i] = color[i];
6249
6250 if (shader->key.part.ps.prolog.flatshade_colors &&
6251 interp == TGSI_INTERPOLATE_COLOR)
6252 interp = TGSI_INTERPOLATE_CONSTANT;
6253
6254 switch (interp) {
6255 case TGSI_INTERPOLATE_CONSTANT:
6256 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6257 break;
6258 case TGSI_INTERPOLATE_PERSPECTIVE:
6259 case TGSI_INTERPOLATE_COLOR:
6260 /* Force the interpolation location for colors here. */
6261 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6262 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6263 if (shader->key.part.ps.prolog.force_persp_center_interp)
6264 location = TGSI_INTERPOLATE_LOC_CENTER;
6265
6266 switch (location) {
6267 case TGSI_INTERPOLATE_LOC_SAMPLE:
6268 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6269 shader->config.spi_ps_input_ena |=
6270 S_0286CC_PERSP_SAMPLE_ENA(1);
6271 break;
6272 case TGSI_INTERPOLATE_LOC_CENTER:
6273 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6274 shader->config.spi_ps_input_ena |=
6275 S_0286CC_PERSP_CENTER_ENA(1);
6276 break;
6277 case TGSI_INTERPOLATE_LOC_CENTROID:
6278 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6279 shader->config.spi_ps_input_ena |=
6280 S_0286CC_PERSP_CENTROID_ENA(1);
6281 break;
6282 default:
6283 assert(0);
6284 }
6285 break;
6286 case TGSI_INTERPOLATE_LINEAR:
6287 /* Force the interpolation location for colors here. */
6288 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6289 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6290 if (shader->key.part.ps.prolog.force_linear_center_interp)
6291 location = TGSI_INTERPOLATE_LOC_CENTER;
6292
6293 /* The VGPR assignment for non-monolithic shaders
6294 * works because InitialPSInputAddr is set on the
6295 * main shader and PERSP_PULL_MODEL is never used.
6296 */
6297 switch (location) {
6298 case TGSI_INTERPOLATE_LOC_SAMPLE:
6299 key->ps_prolog.color_interp_vgpr_index[i] =
6300 separate_prolog ? 6 : 9;
6301 shader->config.spi_ps_input_ena |=
6302 S_0286CC_LINEAR_SAMPLE_ENA(1);
6303 break;
6304 case TGSI_INTERPOLATE_LOC_CENTER:
6305 key->ps_prolog.color_interp_vgpr_index[i] =
6306 separate_prolog ? 8 : 11;
6307 shader->config.spi_ps_input_ena |=
6308 S_0286CC_LINEAR_CENTER_ENA(1);
6309 break;
6310 case TGSI_INTERPOLATE_LOC_CENTROID:
6311 key->ps_prolog.color_interp_vgpr_index[i] =
6312 separate_prolog ? 10 : 13;
6313 shader->config.spi_ps_input_ena |=
6314 S_0286CC_LINEAR_CENTROID_ENA(1);
6315 break;
6316 default:
6317 assert(0);
6318 }
6319 break;
6320 default:
6321 assert(0);
6322 }
6323 }
6324 }
6325 }
6326
6327 /**
6328 * Check whether a PS prolog is required based on the key.
6329 */
6330 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6331 {
6332 return key->ps_prolog.colors_read ||
6333 key->ps_prolog.states.force_persp_sample_interp ||
6334 key->ps_prolog.states.force_linear_sample_interp ||
6335 key->ps_prolog.states.force_persp_center_interp ||
6336 key->ps_prolog.states.force_linear_center_interp ||
6337 key->ps_prolog.states.bc_optimize_for_persp ||
6338 key->ps_prolog.states.bc_optimize_for_linear ||
6339 key->ps_prolog.states.poly_stipple ||
6340 key->ps_prolog.states.samplemask_log_ps_iter;
6341 }
6342
6343 /**
6344 * Compute the PS epilog key, which contains all the information needed to
6345 * build the PS epilog function.
6346 */
6347 static void si_get_ps_epilog_key(struct si_shader *shader,
6348 union si_shader_part_key *key)
6349 {
6350 struct tgsi_shader_info *info = &shader->selector->info;
6351 memset(key, 0, sizeof(*key));
6352 key->ps_epilog.colors_written = info->colors_written;
6353 key->ps_epilog.writes_z = info->writes_z;
6354 key->ps_epilog.writes_stencil = info->writes_stencil;
6355 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6356 key->ps_epilog.states = shader->key.part.ps.epilog;
6357 }
6358
6359 /**
6360 * Build the GS prolog function. Rotate the input vertices for triangle strips
6361 * with adjacency.
6362 */
6363 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6364 union si_shader_part_key *key)
6365 {
6366 unsigned num_sgprs, num_vgprs;
6367 struct si_function_info fninfo;
6368 LLVMBuilderRef builder = ctx->ac.builder;
6369 LLVMTypeRef returns[48];
6370 LLVMValueRef func, ret;
6371
6372 si_init_function_info(&fninfo);
6373
6374 if (ctx->screen->info.chip_class >= GFX9) {
6375 if (key->gs_prolog.states.gfx9_prev_is_vs)
6376 num_sgprs = 8 + GFX9_VSGS_NUM_USER_SGPR;
6377 else
6378 num_sgprs = 8 + GFX9_TESGS_NUM_USER_SGPR;
6379 num_vgprs = 5; /* ES inputs are not needed by GS */
6380 } else {
6381 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6382 num_vgprs = 8;
6383 }
6384
6385 for (unsigned i = 0; i < num_sgprs; ++i) {
6386 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6387 returns[i] = ctx->i32;
6388 }
6389
6390 for (unsigned i = 0; i < num_vgprs; ++i) {
6391 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6392 returns[num_sgprs + i] = ctx->f32;
6393 }
6394
6395 /* Create the function. */
6396 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6397 &fninfo, 0);
6398 func = ctx->main_fn;
6399
6400 /* Set the full EXEC mask for the prolog, because we are only fiddling
6401 * with registers here. The main shader part will set the correct EXEC
6402 * mask.
6403 */
6404 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6405 ac_init_exec_full_mask(&ctx->ac);
6406
6407 /* Copy inputs to outputs. This should be no-op, as the registers match,
6408 * but it will prevent the compiler from overwriting them unintentionally.
6409 */
6410 ret = ctx->return_value;
6411 for (unsigned i = 0; i < num_sgprs; i++) {
6412 LLVMValueRef p = LLVMGetParam(func, i);
6413 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6414 }
6415 for (unsigned i = 0; i < num_vgprs; i++) {
6416 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6417 p = ac_to_float(&ctx->ac, p);
6418 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6419 }
6420
6421 if (key->gs_prolog.states.tri_strip_adj_fix) {
6422 /* Remap the input vertices for every other primitive. */
6423 const unsigned gfx6_vtx_params[6] = {
6424 num_sgprs,
6425 num_sgprs + 1,
6426 num_sgprs + 3,
6427 num_sgprs + 4,
6428 num_sgprs + 5,
6429 num_sgprs + 6
6430 };
6431 const unsigned gfx9_vtx_params[3] = {
6432 num_sgprs,
6433 num_sgprs + 1,
6434 num_sgprs + 4,
6435 };
6436 LLVMValueRef vtx_in[6], vtx_out[6];
6437 LLVMValueRef prim_id, rotate;
6438
6439 if (ctx->screen->info.chip_class >= GFX9) {
6440 for (unsigned i = 0; i < 3; i++) {
6441 vtx_in[i*2] = si_unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6442 vtx_in[i*2+1] = si_unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6443 }
6444 } else {
6445 for (unsigned i = 0; i < 6; i++)
6446 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6447 }
6448
6449 prim_id = LLVMGetParam(func, num_sgprs + 2);
6450 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6451
6452 for (unsigned i = 0; i < 6; ++i) {
6453 LLVMValueRef base, rotated;
6454 base = vtx_in[i];
6455 rotated = vtx_in[(i + 4) % 6];
6456 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6457 }
6458
6459 if (ctx->screen->info.chip_class >= GFX9) {
6460 for (unsigned i = 0; i < 3; i++) {
6461 LLVMValueRef hi, out;
6462
6463 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6464 LLVMConstInt(ctx->i32, 16, 0), "");
6465 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6466 out = ac_to_float(&ctx->ac, out);
6467 ret = LLVMBuildInsertValue(builder, ret, out,
6468 gfx9_vtx_params[i], "");
6469 }
6470 } else {
6471 for (unsigned i = 0; i < 6; i++) {
6472 LLVMValueRef out;
6473
6474 out = ac_to_float(&ctx->ac, vtx_out[i]);
6475 ret = LLVMBuildInsertValue(builder, ret, out,
6476 gfx6_vtx_params[i], "");
6477 }
6478 }
6479 }
6480
6481 LLVMBuildRet(builder, ret);
6482 }
6483
6484 /**
6485 * Given a list of shader part functions, build a wrapper function that
6486 * runs them in sequence to form a monolithic shader.
6487 */
6488 static void si_build_wrapper_function(struct si_shader_context *ctx,
6489 LLVMValueRef *parts,
6490 unsigned num_parts,
6491 unsigned main_part,
6492 unsigned next_shader_first_part)
6493 {
6494 LLVMBuilderRef builder = ctx->ac.builder;
6495 /* PS epilog has one arg per color component; gfx9 merged shader
6496 * prologs need to forward 32 user SGPRs.
6497 */
6498 struct si_function_info fninfo;
6499 LLVMValueRef initial[64], out[64];
6500 LLVMTypeRef function_type;
6501 unsigned num_first_params;
6502 unsigned num_out, initial_num_out;
6503 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6504 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6505 unsigned num_sgprs, num_vgprs;
6506 unsigned gprs;
6507 struct lp_build_if_state if_state;
6508
6509 si_init_function_info(&fninfo);
6510
6511 for (unsigned i = 0; i < num_parts; ++i) {
6512 ac_add_function_attr(ctx->ac.context, parts[i], -1,
6513 AC_FUNC_ATTR_ALWAYSINLINE);
6514 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6515 }
6516
6517 /* The parameters of the wrapper function correspond to those of the
6518 * first part in terms of SGPRs and VGPRs, but we use the types of the
6519 * main part to get the right types. This is relevant for the
6520 * dereferenceable attribute on descriptor table pointers.
6521 */
6522 num_sgprs = 0;
6523 num_vgprs = 0;
6524
6525 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6526 num_first_params = LLVMCountParamTypes(function_type);
6527
6528 for (unsigned i = 0; i < num_first_params; ++i) {
6529 LLVMValueRef param = LLVMGetParam(parts[0], i);
6530
6531 if (ac_is_sgpr_param(param)) {
6532 assert(num_vgprs == 0);
6533 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6534 } else {
6535 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6536 }
6537 }
6538
6539 gprs = 0;
6540 while (gprs < num_sgprs + num_vgprs) {
6541 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6542 LLVMTypeRef type = LLVMTypeOf(param);
6543 unsigned size = ac_get_type_size(type) / 4;
6544
6545 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6546
6547 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6548 assert(gprs + size <= num_sgprs + num_vgprs &&
6549 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6550
6551 gprs += size;
6552 }
6553
6554 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6555 si_get_max_workgroup_size(ctx->shader));
6556
6557 if (is_merged_shader(ctx))
6558 ac_init_exec_full_mask(&ctx->ac);
6559
6560 /* Record the arguments of the function as if they were an output of
6561 * a previous part.
6562 */
6563 num_out = 0;
6564 num_out_sgpr = 0;
6565
6566 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6567 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6568 LLVMTypeRef param_type = LLVMTypeOf(param);
6569 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6570 unsigned size = ac_get_type_size(param_type) / 4;
6571
6572 if (size == 1) {
6573 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6574 param = LLVMBuildPtrToInt(builder, param, ctx->i32, "");
6575 param_type = ctx->i32;
6576 }
6577
6578 if (param_type != out_type)
6579 param = LLVMBuildBitCast(builder, param, out_type, "");
6580 out[num_out++] = param;
6581 } else {
6582 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6583
6584 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6585 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6586 param_type = ctx->i64;
6587 }
6588
6589 if (param_type != vector_type)
6590 param = LLVMBuildBitCast(builder, param, vector_type, "");
6591
6592 for (unsigned j = 0; j < size; ++j)
6593 out[num_out++] = LLVMBuildExtractElement(
6594 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6595 }
6596
6597 if (i < fninfo.num_sgpr_params)
6598 num_out_sgpr = num_out;
6599 }
6600
6601 memcpy(initial, out, sizeof(out));
6602 initial_num_out = num_out;
6603 initial_num_out_sgpr = num_out_sgpr;
6604
6605 /* Now chain the parts. */
6606 for (unsigned part = 0; part < num_parts; ++part) {
6607 LLVMValueRef in[48];
6608 LLVMValueRef ret;
6609 LLVMTypeRef ret_type;
6610 unsigned out_idx = 0;
6611 unsigned num_params = LLVMCountParams(parts[part]);
6612
6613 /* Merged shaders are executed conditionally depending
6614 * on the number of enabled threads passed in the input SGPRs. */
6615 if (is_merged_shader(ctx) && part == 0) {
6616 LLVMValueRef ena, count = initial[3];
6617
6618 count = LLVMBuildAnd(builder, count,
6619 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6620 ena = LLVMBuildICmp(builder, LLVMIntULT,
6621 ac_get_thread_id(&ctx->ac), count, "");
6622 lp_build_if(&if_state, &ctx->gallivm, ena);
6623 }
6624
6625 /* Derive arguments for the next part from outputs of the
6626 * previous one.
6627 */
6628 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6629 LLVMValueRef param;
6630 LLVMTypeRef param_type;
6631 bool is_sgpr;
6632 unsigned param_size;
6633 LLVMValueRef arg = NULL;
6634
6635 param = LLVMGetParam(parts[part], param_idx);
6636 param_type = LLVMTypeOf(param);
6637 param_size = ac_get_type_size(param_type) / 4;
6638 is_sgpr = ac_is_sgpr_param(param);
6639
6640 if (is_sgpr) {
6641 ac_add_function_attr(ctx->ac.context, parts[part],
6642 param_idx + 1, AC_FUNC_ATTR_INREG);
6643 } else if (out_idx < num_out_sgpr) {
6644 /* Skip returned SGPRs the current part doesn't
6645 * declare on the input. */
6646 out_idx = num_out_sgpr;
6647 }
6648
6649 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6650
6651 if (param_size == 1)
6652 arg = out[out_idx];
6653 else
6654 arg = ac_build_gather_values(&ctx->ac, &out[out_idx], param_size);
6655
6656 if (LLVMTypeOf(arg) != param_type) {
6657 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6658 if (LLVMGetPointerAddressSpace(param_type) ==
6659 AC_ADDR_SPACE_CONST_32BIT) {
6660 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
6661 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6662 } else {
6663 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6664 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6665 }
6666 } else {
6667 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6668 }
6669 }
6670
6671 in[param_idx] = arg;
6672 out_idx += param_size;
6673 }
6674
6675 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6676
6677 if (is_merged_shader(ctx) &&
6678 part + 1 == next_shader_first_part) {
6679 lp_build_endif(&if_state);
6680
6681 /* The second half of the merged shader should use
6682 * the inputs from the toplevel (wrapper) function,
6683 * not the return value from the last call.
6684 *
6685 * That's because the last call was executed condi-
6686 * tionally, so we can't consume it in the main
6687 * block.
6688 */
6689 memcpy(out, initial, sizeof(initial));
6690 num_out = initial_num_out;
6691 num_out_sgpr = initial_num_out_sgpr;
6692 continue;
6693 }
6694
6695 /* Extract the returned GPRs. */
6696 ret_type = LLVMTypeOf(ret);
6697 num_out = 0;
6698 num_out_sgpr = 0;
6699
6700 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6701 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6702
6703 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6704
6705 for (unsigned i = 0; i < ret_size; ++i) {
6706 LLVMValueRef val =
6707 LLVMBuildExtractValue(builder, ret, i, "");
6708
6709 assert(num_out < ARRAY_SIZE(out));
6710 out[num_out++] = val;
6711
6712 if (LLVMTypeOf(val) == ctx->i32) {
6713 assert(num_out_sgpr + 1 == num_out);
6714 num_out_sgpr = num_out;
6715 }
6716 }
6717 }
6718 }
6719
6720 LLVMBuildRetVoid(builder);
6721 }
6722
6723 static bool si_should_optimize_less(struct ac_llvm_compiler *compiler,
6724 struct si_shader_selector *sel)
6725 {
6726 if (!compiler->low_opt_passes)
6727 return false;
6728
6729 /* Assume a slow CPU. */
6730 assert(!sel->screen->info.has_dedicated_vram &&
6731 sel->screen->info.chip_class <= VI);
6732
6733 /* For a crazy dEQP test containing 2597 memory opcodes, mostly
6734 * buffer stores. */
6735 return sel->type == PIPE_SHADER_COMPUTE &&
6736 sel->info.num_memory_instructions > 1000;
6737 }
6738
6739 int si_compile_tgsi_shader(struct si_screen *sscreen,
6740 struct ac_llvm_compiler *compiler,
6741 struct si_shader *shader,
6742 struct pipe_debug_callback *debug)
6743 {
6744 struct si_shader_selector *sel = shader->selector;
6745 struct si_shader_context ctx;
6746 int r = -1;
6747
6748 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6749 * conversion fails. */
6750 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6751 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6752 if (sel->tokens)
6753 tgsi_dump(sel->tokens, 0);
6754 else
6755 nir_print_shader(sel->nir, stderr);
6756 si_dump_streamout(&sel->so);
6757 }
6758
6759 si_init_shader_ctx(&ctx, sscreen, compiler);
6760 si_llvm_context_set_tgsi(&ctx, shader);
6761
6762 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6763 sizeof(shader->info.vs_output_param_offset));
6764
6765 shader->info.uses_instanceid = sel->info.uses_instanceid;
6766
6767 if (!si_compile_tgsi_main(&ctx)) {
6768 si_llvm_dispose(&ctx);
6769 return -1;
6770 }
6771
6772 if (shader->is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6773 LLVMValueRef parts[2];
6774 bool need_prolog = sel->vs_needs_prolog;
6775
6776 parts[1] = ctx.main_fn;
6777
6778 if (need_prolog) {
6779 union si_shader_part_key prolog_key;
6780 si_get_vs_prolog_key(&sel->info,
6781 shader->info.num_input_sgprs,
6782 &shader->key.part.vs.prolog,
6783 shader, &prolog_key);
6784 si_build_vs_prolog_function(&ctx, &prolog_key);
6785 parts[0] = ctx.main_fn;
6786 }
6787
6788 si_build_wrapper_function(&ctx, parts + !need_prolog,
6789 1 + need_prolog, need_prolog, 0);
6790 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6791 if (sscreen->info.chip_class >= GFX9) {
6792 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6793 LLVMValueRef parts[4];
6794 bool vs_needs_prolog =
6795 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6796
6797 /* TCS main part */
6798 parts[2] = ctx.main_fn;
6799
6800 /* TCS epilog */
6801 union si_shader_part_key tcs_epilog_key;
6802 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6803 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6804 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6805 parts[3] = ctx.main_fn;
6806
6807 /* VS as LS main part */
6808 struct si_shader shader_ls = {};
6809 shader_ls.selector = ls;
6810 shader_ls.key.as_ls = 1;
6811 shader_ls.key.mono = shader->key.mono;
6812 shader_ls.key.opt = shader->key.opt;
6813 shader_ls.is_monolithic = true;
6814 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6815
6816 if (!si_compile_tgsi_main(&ctx)) {
6817 si_llvm_dispose(&ctx);
6818 return -1;
6819 }
6820 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6821 parts[1] = ctx.main_fn;
6822
6823 /* LS prolog */
6824 if (vs_needs_prolog) {
6825 union si_shader_part_key vs_prolog_key;
6826 si_get_vs_prolog_key(&ls->info,
6827 shader_ls.info.num_input_sgprs,
6828 &shader->key.part.tcs.ls_prolog,
6829 shader, &vs_prolog_key);
6830 vs_prolog_key.vs_prolog.is_monolithic = true;
6831 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6832 parts[0] = ctx.main_fn;
6833 }
6834
6835 /* Reset the shader context. */
6836 ctx.shader = shader;
6837 ctx.type = PIPE_SHADER_TESS_CTRL;
6838
6839 si_build_wrapper_function(&ctx,
6840 parts + !vs_needs_prolog,
6841 4 - !vs_needs_prolog, vs_needs_prolog,
6842 vs_needs_prolog ? 2 : 1);
6843 } else {
6844 LLVMValueRef parts[2];
6845 union si_shader_part_key epilog_key;
6846
6847 parts[0] = ctx.main_fn;
6848
6849 memset(&epilog_key, 0, sizeof(epilog_key));
6850 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6851 si_build_tcs_epilog_function(&ctx, &epilog_key);
6852 parts[1] = ctx.main_fn;
6853
6854 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6855 }
6856 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6857 if (ctx.screen->info.chip_class >= GFX9) {
6858 struct si_shader_selector *es = shader->key.part.gs.es;
6859 LLVMValueRef es_prolog = NULL;
6860 LLVMValueRef es_main = NULL;
6861 LLVMValueRef gs_prolog = NULL;
6862 LLVMValueRef gs_main = ctx.main_fn;
6863
6864 /* GS prolog */
6865 union si_shader_part_key gs_prolog_key;
6866 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6867 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6868 gs_prolog_key.gs_prolog.is_monolithic = true;
6869 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6870 gs_prolog = ctx.main_fn;
6871
6872 /* ES main part */
6873 struct si_shader shader_es = {};
6874 shader_es.selector = es;
6875 shader_es.key.as_es = 1;
6876 shader_es.key.mono = shader->key.mono;
6877 shader_es.key.opt = shader->key.opt;
6878 shader_es.is_monolithic = true;
6879 si_llvm_context_set_tgsi(&ctx, &shader_es);
6880
6881 if (!si_compile_tgsi_main(&ctx)) {
6882 si_llvm_dispose(&ctx);
6883 return -1;
6884 }
6885 shader->info.uses_instanceid |= es->info.uses_instanceid;
6886 es_main = ctx.main_fn;
6887
6888 /* ES prolog */
6889 if (es->vs_needs_prolog) {
6890 union si_shader_part_key vs_prolog_key;
6891 si_get_vs_prolog_key(&es->info,
6892 shader_es.info.num_input_sgprs,
6893 &shader->key.part.gs.vs_prolog,
6894 shader, &vs_prolog_key);
6895 vs_prolog_key.vs_prolog.is_monolithic = true;
6896 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6897 es_prolog = ctx.main_fn;
6898 }
6899
6900 /* Reset the shader context. */
6901 ctx.shader = shader;
6902 ctx.type = PIPE_SHADER_GEOMETRY;
6903
6904 /* Prepare the array of shader parts. */
6905 LLVMValueRef parts[4];
6906 unsigned num_parts = 0, main_part, next_first_part;
6907
6908 if (es_prolog)
6909 parts[num_parts++] = es_prolog;
6910
6911 parts[main_part = num_parts++] = es_main;
6912 parts[next_first_part = num_parts++] = gs_prolog;
6913 parts[num_parts++] = gs_main;
6914
6915 si_build_wrapper_function(&ctx, parts, num_parts,
6916 main_part, next_first_part);
6917 } else {
6918 LLVMValueRef parts[2];
6919 union si_shader_part_key prolog_key;
6920
6921 parts[1] = ctx.main_fn;
6922
6923 memset(&prolog_key, 0, sizeof(prolog_key));
6924 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6925 si_build_gs_prolog_function(&ctx, &prolog_key);
6926 parts[0] = ctx.main_fn;
6927
6928 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6929 }
6930 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6931 LLVMValueRef parts[3];
6932 union si_shader_part_key prolog_key;
6933 union si_shader_part_key epilog_key;
6934 bool need_prolog;
6935
6936 si_get_ps_prolog_key(shader, &prolog_key, false);
6937 need_prolog = si_need_ps_prolog(&prolog_key);
6938
6939 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6940
6941 if (need_prolog) {
6942 si_build_ps_prolog_function(&ctx, &prolog_key);
6943 parts[0] = ctx.main_fn;
6944 }
6945
6946 si_get_ps_epilog_key(shader, &epilog_key);
6947 si_build_ps_epilog_function(&ctx, &epilog_key);
6948 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6949
6950 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6951 need_prolog ? 1 : 0, 0);
6952 }
6953
6954 si_llvm_optimize_module(&ctx);
6955
6956 /* Post-optimization transformations and analysis. */
6957 si_optimize_vs_outputs(&ctx);
6958
6959 if ((debug && debug->debug_message) ||
6960 si_can_dump_shader(sscreen, ctx.type)) {
6961 ctx.shader->config.private_mem_vgprs =
6962 ac_count_scratch_private_memory(ctx.main_fn);
6963 }
6964
6965 /* Make sure the input is a pointer and not integer followed by inttoptr. */
6966 assert(LLVMGetTypeKind(LLVMTypeOf(LLVMGetParam(ctx.main_fn, 0))) ==
6967 LLVMPointerTypeKind);
6968
6969 /* Compile to bytecode. */
6970 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, compiler,
6971 ctx.ac.module, debug, ctx.type,
6972 si_get_shader_name(shader, ctx.type),
6973 si_should_optimize_less(compiler, shader->selector));
6974 si_llvm_dispose(&ctx);
6975 if (r) {
6976 fprintf(stderr, "LLVM failed to compile shader\n");
6977 return r;
6978 }
6979
6980 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6981 * LLVM 3.9svn has this bug.
6982 */
6983 if (sel->type == PIPE_SHADER_COMPUTE) {
6984 unsigned wave_size = 64;
6985 unsigned max_vgprs = 256;
6986 unsigned max_sgprs = sscreen->info.chip_class >= VI ? 800 : 512;
6987 unsigned max_sgprs_per_wave = 128;
6988 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6989 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6990 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6991
6992 max_vgprs = max_vgprs / min_waves_per_simd;
6993 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6994
6995 if (shader->config.num_sgprs > max_sgprs ||
6996 shader->config.num_vgprs > max_vgprs) {
6997 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6998 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6999 shader->config.num_sgprs, shader->config.num_vgprs,
7000 max_sgprs, max_vgprs);
7001
7002 /* Just terminate the process, because dependent
7003 * shaders can hang due to bad input data, but use
7004 * the env var to allow shader-db to work.
7005 */
7006 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7007 abort();
7008 }
7009 }
7010
7011 /* Add the scratch offset to input SGPRs. */
7012 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(&ctx))
7013 shader->info.num_input_sgprs += 1; /* scratch byte offset */
7014
7015 /* Calculate the number of fragment input VGPRs. */
7016 if (ctx.type == PIPE_SHADER_FRAGMENT) {
7017 shader->info.num_input_vgprs = 0;
7018 shader->info.face_vgpr_index = -1;
7019 shader->info.ancillary_vgpr_index = -1;
7020
7021 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7022 shader->info.num_input_vgprs += 2;
7023 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
7024 shader->info.num_input_vgprs += 2;
7025 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
7026 shader->info.num_input_vgprs += 2;
7027 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
7028 shader->info.num_input_vgprs += 3;
7029 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7030 shader->info.num_input_vgprs += 2;
7031 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7032 shader->info.num_input_vgprs += 2;
7033 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7034 shader->info.num_input_vgprs += 2;
7035 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7036 shader->info.num_input_vgprs += 1;
7037 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7038 shader->info.num_input_vgprs += 1;
7039 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7040 shader->info.num_input_vgprs += 1;
7041 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7042 shader->info.num_input_vgprs += 1;
7043 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7044 shader->info.num_input_vgprs += 1;
7045 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7046 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7047 shader->info.num_input_vgprs += 1;
7048 }
7049 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
7050 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
7051 shader->info.num_input_vgprs += 1;
7052 }
7053 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7054 shader->info.num_input_vgprs += 1;
7055 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7056 shader->info.num_input_vgprs += 1;
7057 }
7058
7059 si_calculate_max_simd_waves(shader);
7060 si_shader_dump_stats_for_shader_db(shader, debug);
7061 return 0;
7062 }
7063
7064 /**
7065 * Create, compile and return a shader part (prolog or epilog).
7066 *
7067 * \param sscreen screen
7068 * \param list list of shader parts of the same category
7069 * \param type shader type
7070 * \param key shader part key
7071 * \param prolog whether the part being requested is a prolog
7072 * \param tm LLVM target machine
7073 * \param debug debug callback
7074 * \param build the callback responsible for building the main function
7075 * \return non-NULL on success
7076 */
7077 static struct si_shader_part *
7078 si_get_shader_part(struct si_screen *sscreen,
7079 struct si_shader_part **list,
7080 enum pipe_shader_type type,
7081 bool prolog,
7082 union si_shader_part_key *key,
7083 struct ac_llvm_compiler *compiler,
7084 struct pipe_debug_callback *debug,
7085 void (*build)(struct si_shader_context *,
7086 union si_shader_part_key *),
7087 const char *name)
7088 {
7089 struct si_shader_part *result;
7090
7091 mtx_lock(&sscreen->shader_parts_mutex);
7092
7093 /* Find existing. */
7094 for (result = *list; result; result = result->next) {
7095 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7096 mtx_unlock(&sscreen->shader_parts_mutex);
7097 return result;
7098 }
7099 }
7100
7101 /* Compile a new one. */
7102 result = CALLOC_STRUCT(si_shader_part);
7103 result->key = *key;
7104
7105 struct si_shader shader = {};
7106 struct si_shader_context ctx;
7107
7108 si_init_shader_ctx(&ctx, sscreen, compiler);
7109 ctx.shader = &shader;
7110 ctx.type = type;
7111
7112 switch (type) {
7113 case PIPE_SHADER_VERTEX:
7114 shader.key.as_ls = key->vs_prolog.as_ls;
7115 shader.key.as_es = key->vs_prolog.as_es;
7116 break;
7117 case PIPE_SHADER_TESS_CTRL:
7118 assert(!prolog);
7119 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7120 break;
7121 case PIPE_SHADER_GEOMETRY:
7122 assert(prolog);
7123 break;
7124 case PIPE_SHADER_FRAGMENT:
7125 if (prolog)
7126 shader.key.part.ps.prolog = key->ps_prolog.states;
7127 else
7128 shader.key.part.ps.epilog = key->ps_epilog.states;
7129 break;
7130 default:
7131 unreachable("bad shader part");
7132 }
7133
7134 build(&ctx, key);
7135
7136 /* Compile. */
7137 si_llvm_optimize_module(&ctx);
7138
7139 if (si_compile_llvm(sscreen, &result->binary, &result->config, compiler,
7140 ctx.ac.module, debug, ctx.type, name, false)) {
7141 FREE(result);
7142 result = NULL;
7143 goto out;
7144 }
7145
7146 result->next = *list;
7147 *list = result;
7148
7149 out:
7150 si_llvm_dispose(&ctx);
7151 mtx_unlock(&sscreen->shader_parts_mutex);
7152 return result;
7153 }
7154
7155 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
7156 {
7157 LLVMValueRef ptr[2], list;
7158 bool merged_shader = is_merged_shader(ctx);
7159
7160 if (HAVE_32BIT_POINTERS) {
7161 ptr[0] = LLVMGetParam(ctx->main_fn, (merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7162 list = LLVMBuildIntToPtr(ctx->ac.builder, ptr[0],
7163 ac_array_in_const32_addr_space(ctx->v4i32), "");
7164 return list;
7165 }
7166
7167 /* Get the pointer to rw buffers. */
7168 ptr[0] = LLVMGetParam(ctx->main_fn, (merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7169 ptr[1] = LLVMGetParam(ctx->main_fn, (merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS + 1);
7170 list = ac_build_gather_values(&ctx->ac, ptr, 2);
7171 list = LLVMBuildBitCast(ctx->ac.builder, list, ctx->i64, "");
7172 list = LLVMBuildIntToPtr(ctx->ac.builder, list,
7173 ac_array_in_const_addr_space(ctx->v4i32), "");
7174 return list;
7175 }
7176
7177 /**
7178 * Build the vertex shader prolog function.
7179 *
7180 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7181 * All inputs are returned unmodified. The vertex load indices are
7182 * stored after them, which will be used by the API VS for fetching inputs.
7183 *
7184 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7185 * input_v0,
7186 * input_v1,
7187 * input_v2,
7188 * input_v3,
7189 * (VertexID + BaseVertex),
7190 * (InstanceID + StartInstance),
7191 * (InstanceID / 2 + StartInstance)
7192 */
7193 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7194 union si_shader_part_key *key)
7195 {
7196 struct si_function_info fninfo;
7197 LLVMTypeRef *returns;
7198 LLVMValueRef ret, func;
7199 int num_returns, i;
7200 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
7201 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
7202 LLVMValueRef input_vgprs[9];
7203 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
7204 num_input_vgprs;
7205 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
7206
7207 si_init_function_info(&fninfo);
7208
7209 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7210 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
7211 sizeof(LLVMTypeRef));
7212 num_returns = 0;
7213
7214 /* Declare input and output SGPRs. */
7215 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7216 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7217 returns[num_returns++] = ctx->i32;
7218 }
7219
7220 /* Preloaded VGPRs (outputs must be floats) */
7221 for (i = 0; i < num_input_vgprs; i++) {
7222 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
7223 returns[num_returns++] = ctx->f32;
7224 }
7225
7226 /* Vertex load indices. */
7227 for (i = 0; i <= key->vs_prolog.last_input; i++)
7228 returns[num_returns++] = ctx->f32;
7229
7230 /* Create the function. */
7231 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
7232 func = ctx->main_fn;
7233
7234 if (key->vs_prolog.num_merged_next_stage_vgprs) {
7235 if (!key->vs_prolog.is_monolithic)
7236 si_init_exec_from_input(ctx, 3, 0);
7237
7238 if (key->vs_prolog.as_ls &&
7239 ctx->screen->has_ls_vgpr_init_bug) {
7240 /* If there are no HS threads, SPI loads the LS VGPRs
7241 * starting at VGPR 0. Shift them back to where they
7242 * belong.
7243 */
7244 LLVMValueRef has_hs_threads =
7245 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
7246 si_unpack_param(ctx, 3, 8, 8),
7247 ctx->i32_0, "");
7248
7249 for (i = 4; i > 0; --i) {
7250 input_vgprs[i + 1] =
7251 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
7252 input_vgprs[i + 1],
7253 input_vgprs[i - 1], "");
7254 }
7255 }
7256 }
7257
7258 ctx->abi.vertex_id = input_vgprs[first_vs_vgpr];
7259 ctx->abi.instance_id = input_vgprs[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)];
7260
7261 /* Copy inputs to outputs. This should be no-op, as the registers match,
7262 * but it will prevent the compiler from overwriting them unintentionally.
7263 */
7264 ret = ctx->return_value;
7265 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7266 LLVMValueRef p = LLVMGetParam(func, i);
7267 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7268 }
7269 for (i = 0; i < num_input_vgprs; i++) {
7270 LLVMValueRef p = input_vgprs[i];
7271 p = ac_to_float(&ctx->ac, p);
7272 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
7273 key->vs_prolog.num_input_sgprs + i, "");
7274 }
7275
7276 /* Compute vertex load indices from instance divisors. */
7277 LLVMValueRef instance_divisor_constbuf = NULL;
7278
7279 if (key->vs_prolog.states.instance_divisor_is_fetched) {
7280 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7281 LLVMValueRef buf_index =
7282 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
7283 instance_divisor_constbuf =
7284 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
7285 }
7286
7287 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7288 bool divisor_is_one =
7289 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
7290 bool divisor_is_fetched =
7291 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
7292 LLVMValueRef index = NULL;
7293
7294 if (divisor_is_one) {
7295 index = ctx->abi.instance_id;
7296 } else if (divisor_is_fetched) {
7297 LLVMValueRef udiv_factors[4];
7298
7299 for (unsigned j = 0; j < 4; j++) {
7300 udiv_factors[j] =
7301 buffer_load_const(ctx, instance_divisor_constbuf,
7302 LLVMConstInt(ctx->i32, i*16 + j*4, 0));
7303 udiv_factors[j] = ac_to_integer(&ctx->ac, udiv_factors[j]);
7304 }
7305 /* The faster NUW version doesn't work when InstanceID == UINT_MAX.
7306 * Such InstanceID might not be achievable in a reasonable time though.
7307 */
7308 index = ac_build_fast_udiv_nuw(&ctx->ac, ctx->abi.instance_id,
7309 udiv_factors[0], udiv_factors[1],
7310 udiv_factors[2], udiv_factors[3]);
7311 }
7312
7313 if (divisor_is_one || divisor_is_fetched) {
7314 /* Add StartInstance. */
7315 index = LLVMBuildAdd(ctx->ac.builder, index,
7316 LLVMGetParam(ctx->main_fn, user_sgpr_base +
7317 SI_SGPR_START_INSTANCE), "");
7318 } else {
7319 /* VertexID + BaseVertex */
7320 index = LLVMBuildAdd(ctx->ac.builder,
7321 ctx->abi.vertex_id,
7322 LLVMGetParam(func, user_sgpr_base +
7323 SI_SGPR_BASE_VERTEX), "");
7324 }
7325
7326 index = ac_to_float(&ctx->ac, index);
7327 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7328 fninfo.num_params + i, "");
7329 }
7330
7331 si_llvm_build_ret(ctx, ret);
7332 }
7333
7334 static bool si_get_vs_prolog(struct si_screen *sscreen,
7335 struct ac_llvm_compiler *compiler,
7336 struct si_shader *shader,
7337 struct pipe_debug_callback *debug,
7338 struct si_shader *main_part,
7339 const struct si_vs_prolog_bits *key)
7340 {
7341 struct si_shader_selector *vs = main_part->selector;
7342
7343 if (!si_vs_needs_prolog(vs, key))
7344 return true;
7345
7346 /* Get the prolog. */
7347 union si_shader_part_key prolog_key;
7348 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7349 key, shader, &prolog_key);
7350
7351 shader->prolog =
7352 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7353 PIPE_SHADER_VERTEX, true, &prolog_key, compiler,
7354 debug, si_build_vs_prolog_function,
7355 "Vertex Shader Prolog");
7356 return shader->prolog != NULL;
7357 }
7358
7359 /**
7360 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7361 */
7362 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7363 struct ac_llvm_compiler *compiler,
7364 struct si_shader *shader,
7365 struct pipe_debug_callback *debug)
7366 {
7367 return si_get_vs_prolog(sscreen, compiler, shader, debug, shader,
7368 &shader->key.part.vs.prolog);
7369 }
7370
7371 /**
7372 * Compile the TCS epilog function. This writes tesselation factors to memory
7373 * based on the output primitive type of the tesselator (determined by TES).
7374 */
7375 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7376 union si_shader_part_key *key)
7377 {
7378 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7379 struct si_function_info fninfo;
7380 LLVMValueRef func;
7381
7382 si_init_function_info(&fninfo);
7383
7384 if (ctx->screen->info.chip_class >= GFX9) {
7385 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7386 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7387 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7388 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7389 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7390 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7391 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7392 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7393 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7394 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7395 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7396 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7397 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7398 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7399 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7400 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7401 if (!HAVE_32BIT_POINTERS)
7402 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7403 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7404 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7405 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7406 } else {
7407 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7408 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7409 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7410 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7411 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7412 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7413 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7414 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7415 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7416 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7417 }
7418
7419 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7420 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7421 unsigned tess_factors_idx =
7422 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7423 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7424 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7425
7426 for (unsigned i = 0; i < 6; i++)
7427 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7428
7429 /* Create the function. */
7430 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7431 ctx->screen->info.chip_class >= CIK ? 128 : 64);
7432 ac_declare_lds_as_pointer(&ctx->ac);
7433 func = ctx->main_fn;
7434
7435 LLVMValueRef invoc0_tess_factors[6];
7436 for (unsigned i = 0; i < 6; i++)
7437 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7438
7439 si_write_tess_factors(bld_base,
7440 LLVMGetParam(func, tess_factors_idx),
7441 LLVMGetParam(func, tess_factors_idx + 1),
7442 LLVMGetParam(func, tess_factors_idx + 2),
7443 invoc0_tess_factors, invoc0_tess_factors + 4);
7444
7445 LLVMBuildRetVoid(ctx->ac.builder);
7446 }
7447
7448 /**
7449 * Select and compile (or reuse) TCS parts (epilog).
7450 */
7451 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7452 struct ac_llvm_compiler *compiler,
7453 struct si_shader *shader,
7454 struct pipe_debug_callback *debug)
7455 {
7456 if (sscreen->info.chip_class >= GFX9) {
7457 struct si_shader *ls_main_part =
7458 shader->key.part.tcs.ls->main_shader_part_ls;
7459
7460 if (!si_get_vs_prolog(sscreen, compiler, shader, debug, ls_main_part,
7461 &shader->key.part.tcs.ls_prolog))
7462 return false;
7463
7464 shader->previous_stage = ls_main_part;
7465 }
7466
7467 /* Get the epilog. */
7468 union si_shader_part_key epilog_key;
7469 memset(&epilog_key, 0, sizeof(epilog_key));
7470 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7471
7472 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7473 PIPE_SHADER_TESS_CTRL, false,
7474 &epilog_key, compiler, debug,
7475 si_build_tcs_epilog_function,
7476 "Tessellation Control Shader Epilog");
7477 return shader->epilog != NULL;
7478 }
7479
7480 /**
7481 * Select and compile (or reuse) GS parts (prolog).
7482 */
7483 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7484 struct ac_llvm_compiler *compiler,
7485 struct si_shader *shader,
7486 struct pipe_debug_callback *debug)
7487 {
7488 if (sscreen->info.chip_class >= GFX9) {
7489 struct si_shader *es_main_part =
7490 shader->key.part.gs.es->main_shader_part_es;
7491
7492 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7493 !si_get_vs_prolog(sscreen, compiler, shader, debug, es_main_part,
7494 &shader->key.part.gs.vs_prolog))
7495 return false;
7496
7497 shader->previous_stage = es_main_part;
7498 }
7499
7500 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7501 return true;
7502
7503 union si_shader_part_key prolog_key;
7504 memset(&prolog_key, 0, sizeof(prolog_key));
7505 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7506
7507 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7508 PIPE_SHADER_GEOMETRY, true,
7509 &prolog_key, compiler, debug,
7510 si_build_gs_prolog_function,
7511 "Geometry Shader Prolog");
7512 return shader->prolog2 != NULL;
7513 }
7514
7515 /**
7516 * Build the pixel shader prolog function. This handles:
7517 * - two-side color selection and interpolation
7518 * - overriding interpolation parameters for the API PS
7519 * - polygon stippling
7520 *
7521 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7522 * overriden by other states. (e.g. per-sample interpolation)
7523 * Interpolated colors are stored after the preloaded VGPRs.
7524 */
7525 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7526 union si_shader_part_key *key)
7527 {
7528 struct si_function_info fninfo;
7529 LLVMValueRef ret, func;
7530 int num_returns, i, num_color_channels;
7531
7532 assert(si_need_ps_prolog(key));
7533
7534 si_init_function_info(&fninfo);
7535
7536 /* Declare inputs. */
7537 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7538 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7539
7540 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7541 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7542
7543 /* Declare outputs (same as inputs + add colors if needed) */
7544 num_returns = fninfo.num_params;
7545 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7546 for (i = 0; i < num_color_channels; i++)
7547 fninfo.types[num_returns++] = ctx->f32;
7548
7549 /* Create the function. */
7550 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7551 &fninfo, 0);
7552 func = ctx->main_fn;
7553
7554 /* Copy inputs to outputs. This should be no-op, as the registers match,
7555 * but it will prevent the compiler from overwriting them unintentionally.
7556 */
7557 ret = ctx->return_value;
7558 for (i = 0; i < fninfo.num_params; i++) {
7559 LLVMValueRef p = LLVMGetParam(func, i);
7560 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7561 }
7562
7563 /* Polygon stippling. */
7564 if (key->ps_prolog.states.poly_stipple) {
7565 /* POS_FIXED_PT is always last. */
7566 unsigned pos = key->ps_prolog.num_input_sgprs +
7567 key->ps_prolog.num_input_vgprs - 1;
7568 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7569
7570 si_llvm_emit_polygon_stipple(ctx, list, pos);
7571 }
7572
7573 if (key->ps_prolog.states.bc_optimize_for_persp ||
7574 key->ps_prolog.states.bc_optimize_for_linear) {
7575 unsigned i, base = key->ps_prolog.num_input_sgprs;
7576 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7577
7578 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7579 * The hw doesn't compute CENTROID if the whole wave only
7580 * contains fully-covered quads.
7581 *
7582 * PRIM_MASK is after user SGPRs.
7583 */
7584 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7585 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7586 LLVMConstInt(ctx->i32, 31, 0), "");
7587 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7588 ctx->i1, "");
7589
7590 if (key->ps_prolog.states.bc_optimize_for_persp) {
7591 /* Read PERSP_CENTER. */
7592 for (i = 0; i < 2; i++)
7593 center[i] = LLVMGetParam(func, base + 2 + i);
7594 /* Read PERSP_CENTROID. */
7595 for (i = 0; i < 2; i++)
7596 centroid[i] = LLVMGetParam(func, base + 4 + i);
7597 /* Select PERSP_CENTROID. */
7598 for (i = 0; i < 2; i++) {
7599 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7600 center[i], centroid[i], "");
7601 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7602 tmp, base + 4 + i, "");
7603 }
7604 }
7605 if (key->ps_prolog.states.bc_optimize_for_linear) {
7606 /* Read LINEAR_CENTER. */
7607 for (i = 0; i < 2; i++)
7608 center[i] = LLVMGetParam(func, base + 8 + i);
7609 /* Read LINEAR_CENTROID. */
7610 for (i = 0; i < 2; i++)
7611 centroid[i] = LLVMGetParam(func, base + 10 + i);
7612 /* Select LINEAR_CENTROID. */
7613 for (i = 0; i < 2; i++) {
7614 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7615 center[i], centroid[i], "");
7616 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7617 tmp, base + 10 + i, "");
7618 }
7619 }
7620 }
7621
7622 /* Force per-sample interpolation. */
7623 if (key->ps_prolog.states.force_persp_sample_interp) {
7624 unsigned i, base = key->ps_prolog.num_input_sgprs;
7625 LLVMValueRef persp_sample[2];
7626
7627 /* Read PERSP_SAMPLE. */
7628 for (i = 0; i < 2; i++)
7629 persp_sample[i] = LLVMGetParam(func, base + i);
7630 /* Overwrite PERSP_CENTER. */
7631 for (i = 0; i < 2; i++)
7632 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7633 persp_sample[i], base + 2 + i, "");
7634 /* Overwrite PERSP_CENTROID. */
7635 for (i = 0; i < 2; i++)
7636 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7637 persp_sample[i], base + 4 + i, "");
7638 }
7639 if (key->ps_prolog.states.force_linear_sample_interp) {
7640 unsigned i, base = key->ps_prolog.num_input_sgprs;
7641 LLVMValueRef linear_sample[2];
7642
7643 /* Read LINEAR_SAMPLE. */
7644 for (i = 0; i < 2; i++)
7645 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7646 /* Overwrite LINEAR_CENTER. */
7647 for (i = 0; i < 2; i++)
7648 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7649 linear_sample[i], base + 8 + i, "");
7650 /* Overwrite LINEAR_CENTROID. */
7651 for (i = 0; i < 2; i++)
7652 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7653 linear_sample[i], base + 10 + i, "");
7654 }
7655
7656 /* Force center interpolation. */
7657 if (key->ps_prolog.states.force_persp_center_interp) {
7658 unsigned i, base = key->ps_prolog.num_input_sgprs;
7659 LLVMValueRef persp_center[2];
7660
7661 /* Read PERSP_CENTER. */
7662 for (i = 0; i < 2; i++)
7663 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7664 /* Overwrite PERSP_SAMPLE. */
7665 for (i = 0; i < 2; i++)
7666 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7667 persp_center[i], base + i, "");
7668 /* Overwrite PERSP_CENTROID. */
7669 for (i = 0; i < 2; i++)
7670 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7671 persp_center[i], base + 4 + i, "");
7672 }
7673 if (key->ps_prolog.states.force_linear_center_interp) {
7674 unsigned i, base = key->ps_prolog.num_input_sgprs;
7675 LLVMValueRef linear_center[2];
7676
7677 /* Read LINEAR_CENTER. */
7678 for (i = 0; i < 2; i++)
7679 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7680 /* Overwrite LINEAR_SAMPLE. */
7681 for (i = 0; i < 2; i++)
7682 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7683 linear_center[i], base + 6 + i, "");
7684 /* Overwrite LINEAR_CENTROID. */
7685 for (i = 0; i < 2; i++)
7686 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7687 linear_center[i], base + 10 + i, "");
7688 }
7689
7690 /* Interpolate colors. */
7691 unsigned color_out_idx = 0;
7692 for (i = 0; i < 2; i++) {
7693 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7694 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7695 key->ps_prolog.face_vgpr_index;
7696 LLVMValueRef interp[2], color[4];
7697 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7698
7699 if (!writemask)
7700 continue;
7701
7702 /* If the interpolation qualifier is not CONSTANT (-1). */
7703 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7704 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7705 key->ps_prolog.color_interp_vgpr_index[i];
7706
7707 /* Get the (i,j) updated by bc_optimize handling. */
7708 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7709 interp_vgpr, "");
7710 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7711 interp_vgpr + 1, "");
7712 interp_ij = ac_build_gather_values(&ctx->ac, interp, 2);
7713 }
7714
7715 /* Use the absolute location of the input. */
7716 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7717
7718 if (key->ps_prolog.states.color_two_side) {
7719 face = LLVMGetParam(func, face_vgpr);
7720 face = ac_to_integer(&ctx->ac, face);
7721 }
7722
7723 interp_fs_input(ctx,
7724 key->ps_prolog.color_attr_index[i],
7725 TGSI_SEMANTIC_COLOR, i,
7726 key->ps_prolog.num_interp_inputs,
7727 key->ps_prolog.colors_read, interp_ij,
7728 prim_mask, face, color);
7729
7730 while (writemask) {
7731 unsigned chan = u_bit_scan(&writemask);
7732 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7733 fninfo.num_params + color_out_idx++, "");
7734 }
7735 }
7736
7737 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7738 * says:
7739 *
7740 * "When per-sample shading is active due to the use of a fragment
7741 * input qualified by sample or due to the use of the gl_SampleID
7742 * or gl_SamplePosition variables, only the bit for the current
7743 * sample is set in gl_SampleMaskIn. When state specifies multiple
7744 * fragment shader invocations for a given fragment, the sample
7745 * mask for any single fragment shader invocation may specify a
7746 * subset of the covered samples for the fragment. In this case,
7747 * the bit corresponding to each covered sample will be set in
7748 * exactly one fragment shader invocation."
7749 *
7750 * The samplemask loaded by hardware is always the coverage of the
7751 * entire pixel/fragment, so mask bits out based on the sample ID.
7752 */
7753 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7754 /* The bit pattern matches that used by fixed function fragment
7755 * processing. */
7756 static const uint16_t ps_iter_masks[] = {
7757 0xffff, /* not used */
7758 0x5555,
7759 0x1111,
7760 0x0101,
7761 0x0001,
7762 };
7763 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7764
7765 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7766 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7767 key->ps_prolog.ancillary_vgpr_index;
7768 LLVMValueRef sampleid = si_unpack_param(ctx, ancillary_vgpr, 8, 4);
7769 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7770
7771 samplemask = ac_to_integer(&ctx->ac, samplemask);
7772 samplemask = LLVMBuildAnd(
7773 ctx->ac.builder,
7774 samplemask,
7775 LLVMBuildShl(ctx->ac.builder,
7776 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7777 sampleid, ""),
7778 "");
7779 samplemask = ac_to_float(&ctx->ac, samplemask);
7780
7781 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7782 ancillary_vgpr + 1, "");
7783 }
7784
7785 /* Tell LLVM to insert WQM instruction sequence when needed. */
7786 if (key->ps_prolog.wqm) {
7787 LLVMAddTargetDependentFunctionAttr(func,
7788 "amdgpu-ps-wqm-outputs", "");
7789 }
7790
7791 si_llvm_build_ret(ctx, ret);
7792 }
7793
7794 /**
7795 * Build the pixel shader epilog function. This handles everything that must be
7796 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7797 */
7798 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7799 union si_shader_part_key *key)
7800 {
7801 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7802 struct si_function_info fninfo;
7803 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7804 int i;
7805 struct si_ps_exports exp = {};
7806
7807 si_init_function_info(&fninfo);
7808
7809 /* Declare input SGPRs. */
7810 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7811 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7812 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7813 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7814 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7815
7816 /* Declare input VGPRs. */
7817 unsigned required_num_params =
7818 fninfo.num_sgpr_params +
7819 util_bitcount(key->ps_epilog.colors_written) * 4 +
7820 key->ps_epilog.writes_z +
7821 key->ps_epilog.writes_stencil +
7822 key->ps_epilog.writes_samplemask;
7823
7824 required_num_params = MAX2(required_num_params,
7825 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7826
7827 while (fninfo.num_params < required_num_params)
7828 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7829
7830 /* Create the function. */
7831 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7832 /* Disable elimination of unused inputs. */
7833 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
7834 "InitialPSInputAddr", 0xffffff);
7835
7836 /* Process colors. */
7837 unsigned vgpr = fninfo.num_sgpr_params;
7838 unsigned colors_written = key->ps_epilog.colors_written;
7839 int last_color_export = -1;
7840
7841 /* Find the last color export. */
7842 if (!key->ps_epilog.writes_z &&
7843 !key->ps_epilog.writes_stencil &&
7844 !key->ps_epilog.writes_samplemask) {
7845 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7846
7847 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7848 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7849 /* Just set this if any of the colorbuffers are enabled. */
7850 if (spi_format &
7851 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7852 last_color_export = 0;
7853 } else {
7854 for (i = 0; i < 8; i++)
7855 if (colors_written & (1 << i) &&
7856 (spi_format >> (i * 4)) & 0xf)
7857 last_color_export = i;
7858 }
7859 }
7860
7861 while (colors_written) {
7862 LLVMValueRef color[4];
7863 int mrt = u_bit_scan(&colors_written);
7864
7865 for (i = 0; i < 4; i++)
7866 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7867
7868 si_export_mrt_color(bld_base, color, mrt,
7869 fninfo.num_params - 1,
7870 mrt == last_color_export, &exp);
7871 }
7872
7873 /* Process depth, stencil, samplemask. */
7874 if (key->ps_epilog.writes_z)
7875 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7876 if (key->ps_epilog.writes_stencil)
7877 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7878 if (key->ps_epilog.writes_samplemask)
7879 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7880
7881 if (depth || stencil || samplemask)
7882 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7883 else if (last_color_export == -1)
7884 ac_build_export_null(&ctx->ac);
7885
7886 if (exp.num)
7887 si_emit_ps_exports(ctx, &exp);
7888
7889 /* Compile. */
7890 LLVMBuildRetVoid(ctx->ac.builder);
7891 }
7892
7893 /**
7894 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7895 */
7896 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7897 struct ac_llvm_compiler *compiler,
7898 struct si_shader *shader,
7899 struct pipe_debug_callback *debug)
7900 {
7901 union si_shader_part_key prolog_key;
7902 union si_shader_part_key epilog_key;
7903
7904 /* Get the prolog. */
7905 si_get_ps_prolog_key(shader, &prolog_key, true);
7906
7907 /* The prolog is a no-op if these aren't set. */
7908 if (si_need_ps_prolog(&prolog_key)) {
7909 shader->prolog =
7910 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7911 PIPE_SHADER_FRAGMENT, true,
7912 &prolog_key, compiler, debug,
7913 si_build_ps_prolog_function,
7914 "Fragment Shader Prolog");
7915 if (!shader->prolog)
7916 return false;
7917 }
7918
7919 /* Get the epilog. */
7920 si_get_ps_epilog_key(shader, &epilog_key);
7921
7922 shader->epilog =
7923 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7924 PIPE_SHADER_FRAGMENT, false,
7925 &epilog_key, compiler, debug,
7926 si_build_ps_epilog_function,
7927 "Fragment Shader Epilog");
7928 if (!shader->epilog)
7929 return false;
7930
7931 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7932 if (shader->key.part.ps.prolog.poly_stipple) {
7933 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7934 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7935 }
7936
7937 /* Set up the enable bits for per-sample shading if needed. */
7938 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7939 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7940 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7941 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7942 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7943 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7944 }
7945 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7946 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7947 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7948 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7949 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7950 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7951 }
7952 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7953 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7954 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7955 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7956 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7957 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7958 }
7959 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7960 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7961 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7962 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7963 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7964 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7965 }
7966
7967 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7968 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7969 !(shader->config.spi_ps_input_ena & 0xf)) {
7970 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7971 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7972 }
7973
7974 /* At least one pair of interpolation weights must be enabled. */
7975 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7976 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7977 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7978 }
7979
7980 /* Samplemask fixup requires the sample ID. */
7981 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7982 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7983 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7984 }
7985
7986 /* The sample mask input is always enabled, because the API shader always
7987 * passes it through to the epilog. Disable it here if it's unused.
7988 */
7989 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7990 !shader->selector->info.reads_samplemask)
7991 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7992
7993 return true;
7994 }
7995
7996 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7997 unsigned *lds_size)
7998 {
7999 /* If tessellation is all offchip and on-chip GS isn't used, this
8000 * workaround is not needed.
8001 */
8002 return;
8003
8004 /* SPI barrier management bug:
8005 * Make sure we have at least 4k of LDS in use to avoid the bug.
8006 * It applies to workgroup sizes of more than one wavefront.
8007 */
8008 if (sscreen->info.family == CHIP_BONAIRE ||
8009 sscreen->info.family == CHIP_KABINI ||
8010 sscreen->info.family == CHIP_MULLINS)
8011 *lds_size = MAX2(*lds_size, 8);
8012 }
8013
8014 static void si_fix_resource_usage(struct si_screen *sscreen,
8015 struct si_shader *shader)
8016 {
8017 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
8018
8019 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
8020
8021 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
8022 si_get_max_workgroup_size(shader) > 64) {
8023 si_multiwave_lds_size_workaround(sscreen,
8024 &shader->config.lds_size);
8025 }
8026 }
8027
8028 int si_shader_create(struct si_screen *sscreen, struct ac_llvm_compiler *compiler,
8029 struct si_shader *shader,
8030 struct pipe_debug_callback *debug)
8031 {
8032 struct si_shader_selector *sel = shader->selector;
8033 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
8034 int r;
8035
8036 /* LS, ES, VS are compiled on demand if the main part hasn't been
8037 * compiled for that stage.
8038 *
8039 * Vertex shaders are compiled on demand when a vertex fetch
8040 * workaround must be applied.
8041 */
8042 if (shader->is_monolithic) {
8043 /* Monolithic shader (compiled as a whole, has many variants,
8044 * may take a long time to compile).
8045 */
8046 r = si_compile_tgsi_shader(sscreen, compiler, shader, debug);
8047 if (r)
8048 return r;
8049 } else {
8050 /* The shader consists of several parts:
8051 *
8052 * - the middle part is the user shader, it has 1 variant only
8053 * and it was compiled during the creation of the shader
8054 * selector
8055 * - the prolog part is inserted at the beginning
8056 * - the epilog part is inserted at the end
8057 *
8058 * The prolog and epilog have many (but simple) variants.
8059 *
8060 * Starting with gfx9, geometry and tessellation control
8061 * shaders also contain the prolog and user shader parts of
8062 * the previous shader stage.
8063 */
8064
8065 if (!mainp)
8066 return -1;
8067
8068 /* Copy the compiled TGSI shader data over. */
8069 shader->is_binary_shared = true;
8070 shader->binary = mainp->binary;
8071 shader->config = mainp->config;
8072 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8073 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8074 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8075 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
8076 memcpy(shader->info.vs_output_param_offset,
8077 mainp->info.vs_output_param_offset,
8078 sizeof(mainp->info.vs_output_param_offset));
8079 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8080 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8081 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8082
8083 /* Select prologs and/or epilogs. */
8084 switch (sel->type) {
8085 case PIPE_SHADER_VERTEX:
8086 if (!si_shader_select_vs_parts(sscreen, compiler, shader, debug))
8087 return -1;
8088 break;
8089 case PIPE_SHADER_TESS_CTRL:
8090 if (!si_shader_select_tcs_parts(sscreen, compiler, shader, debug))
8091 return -1;
8092 break;
8093 case PIPE_SHADER_TESS_EVAL:
8094 break;
8095 case PIPE_SHADER_GEOMETRY:
8096 if (!si_shader_select_gs_parts(sscreen, compiler, shader, debug))
8097 return -1;
8098 break;
8099 case PIPE_SHADER_FRAGMENT:
8100 if (!si_shader_select_ps_parts(sscreen, compiler, shader, debug))
8101 return -1;
8102
8103 /* Make sure we have at least as many VGPRs as there
8104 * are allocated inputs.
8105 */
8106 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8107 shader->info.num_input_vgprs);
8108 break;
8109 }
8110
8111 /* Update SGPR and VGPR counts. */
8112 if (shader->prolog) {
8113 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8114 shader->prolog->config.num_sgprs);
8115 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8116 shader->prolog->config.num_vgprs);
8117 }
8118 if (shader->previous_stage) {
8119 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8120 shader->previous_stage->config.num_sgprs);
8121 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8122 shader->previous_stage->config.num_vgprs);
8123 shader->config.spilled_sgprs =
8124 MAX2(shader->config.spilled_sgprs,
8125 shader->previous_stage->config.spilled_sgprs);
8126 shader->config.spilled_vgprs =
8127 MAX2(shader->config.spilled_vgprs,
8128 shader->previous_stage->config.spilled_vgprs);
8129 shader->config.private_mem_vgprs =
8130 MAX2(shader->config.private_mem_vgprs,
8131 shader->previous_stage->config.private_mem_vgprs);
8132 shader->config.scratch_bytes_per_wave =
8133 MAX2(shader->config.scratch_bytes_per_wave,
8134 shader->previous_stage->config.scratch_bytes_per_wave);
8135 shader->info.uses_instanceid |=
8136 shader->previous_stage->info.uses_instanceid;
8137 }
8138 if (shader->prolog2) {
8139 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8140 shader->prolog2->config.num_sgprs);
8141 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8142 shader->prolog2->config.num_vgprs);
8143 }
8144 if (shader->epilog) {
8145 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8146 shader->epilog->config.num_sgprs);
8147 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8148 shader->epilog->config.num_vgprs);
8149 }
8150 si_calculate_max_simd_waves(shader);
8151 }
8152
8153 si_fix_resource_usage(sscreen, shader);
8154 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8155 stderr, true);
8156
8157 /* Upload. */
8158 r = si_shader_binary_upload(sscreen, shader);
8159 if (r) {
8160 fprintf(stderr, "LLVM failed to upload shader\n");
8161 return r;
8162 }
8163
8164 return 0;
8165 }
8166
8167 void si_shader_destroy(struct si_shader *shader)
8168 {
8169 if (shader->scratch_bo)
8170 r600_resource_reference(&shader->scratch_bo, NULL);
8171
8172 r600_resource_reference(&shader->bo, NULL);
8173
8174 if (!shader->is_binary_shared)
8175 ac_shader_binary_clean(&shader->binary);
8176
8177 free(shader->shader_log);
8178 }