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[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_dump.h"
45
46 #include "si_pipe.h"
47 #include "si_shader.h"
48 #include "sid.h"
49
50 #include <errno.h>
51
52 static const char *scratch_rsrc_dword0_symbol =
53 "SCRATCH_RSRC_DWORD0";
54
55 static const char *scratch_rsrc_dword1_symbol =
56 "SCRATCH_RSRC_DWORD1";
57
58 struct si_shader_output_values
59 {
60 LLVMValueRef values[4];
61 unsigned name;
62 unsigned sid;
63 };
64
65 struct si_shader_context
66 {
67 struct radeon_llvm_context radeon_bld;
68 struct si_shader *shader;
69 struct si_screen *screen;
70 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
71 bool is_gs_copy_shader;
72 int param_streamout_config;
73 int param_streamout_write_index;
74 int param_streamout_offset[4];
75 int param_vertex_id;
76 int param_rel_auto_id;
77 int param_vs_prim_id;
78 int param_instance_id;
79 int param_tes_u;
80 int param_tes_v;
81 int param_tes_rel_patch_id;
82 int param_tes_patch_id;
83 int param_es2gs_offset;
84 LLVMTargetMachineRef tm;
85 LLVMValueRef const_md;
86 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
87 LLVMValueRef lds;
88 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
89 LLVMValueRef sampler_views[SI_NUM_SAMPLER_VIEWS];
90 LLVMValueRef sampler_states[SI_NUM_SAMPLER_STATES];
91 LLVMValueRef so_buffers[4];
92 LLVMValueRef esgs_ring;
93 LLVMValueRef gsvs_ring[4];
94 LLVMValueRef gs_next_vertex[4];
95 };
96
97 static struct si_shader_context * si_shader_context(
98 struct lp_build_tgsi_context * bld_base)
99 {
100 return (struct si_shader_context *)bld_base;
101 }
102
103
104 #define PERSPECTIVE_BASE 0
105 #define LINEAR_BASE 9
106
107 #define SAMPLE_OFFSET 0
108 #define CENTER_OFFSET 2
109 #define CENTROID_OFSET 4
110
111 #define USE_SGPR_MAX_SUFFIX_LEN 5
112 #define CONST_ADDR_SPACE 2
113 #define LOCAL_ADDR_SPACE 3
114 #define USER_SGPR_ADDR_SPACE 8
115
116
117 #define SENDMSG_GS 2
118 #define SENDMSG_GS_DONE 3
119
120 #define SENDMSG_GS_OP_NOP (0 << 4)
121 #define SENDMSG_GS_OP_CUT (1 << 4)
122 #define SENDMSG_GS_OP_EMIT (2 << 4)
123 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
124
125 /**
126 * Returns a unique index for a semantic name and index. The index must be
127 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
128 * calculated.
129 */
130 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
131 {
132 switch (semantic_name) {
133 case TGSI_SEMANTIC_POSITION:
134 return 0;
135 case TGSI_SEMANTIC_PSIZE:
136 return 1;
137 case TGSI_SEMANTIC_CLIPDIST:
138 assert(index <= 1);
139 return 2 + index;
140 case TGSI_SEMANTIC_GENERIC:
141 if (index <= 63-4)
142 return 4 + index;
143 else
144 /* same explanation as in the default statement,
145 * the only user hitting this is st/nine.
146 */
147 return 0;
148
149 /* patch indices are completely separate and thus start from 0 */
150 case TGSI_SEMANTIC_TESSOUTER:
151 return 0;
152 case TGSI_SEMANTIC_TESSINNER:
153 return 1;
154 case TGSI_SEMANTIC_PATCH:
155 return 2 + index;
156
157 default:
158 /* Don't fail here. The result of this function is only used
159 * for LS, TCS, TES, and GS, where legacy GL semantics can't
160 * occur, but this function is called for all vertex shaders
161 * before it's known whether LS will be compiled or not.
162 */
163 return 0;
164 }
165 }
166
167 /**
168 * Get the value of a shader input parameter and extract a bitfield.
169 */
170 static LLVMValueRef unpack_param(struct si_shader_context *si_shader_ctx,
171 unsigned param, unsigned rshift,
172 unsigned bitwidth)
173 {
174 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
175 LLVMValueRef value = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
176 param);
177
178 if (rshift)
179 value = LLVMBuildLShr(gallivm->builder, value,
180 lp_build_const_int32(gallivm, rshift), "");
181
182 if (rshift + bitwidth < 32) {
183 unsigned mask = (1 << bitwidth) - 1;
184 value = LLVMBuildAnd(gallivm->builder, value,
185 lp_build_const_int32(gallivm, mask), "");
186 }
187
188 return value;
189 }
190
191 static LLVMValueRef get_rel_patch_id(struct si_shader_context *si_shader_ctx)
192 {
193 switch (si_shader_ctx->type) {
194 case TGSI_PROCESSOR_TESS_CTRL:
195 return unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 0, 8);
196
197 case TGSI_PROCESSOR_TESS_EVAL:
198 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
199 si_shader_ctx->param_tes_rel_patch_id);
200
201 default:
202 assert(0);
203 return NULL;
204 }
205 }
206
207 /* Tessellation shaders pass outputs to the next shader using LDS.
208 *
209 * LS outputs = TCS inputs
210 * TCS outputs = TES inputs
211 *
212 * The LDS layout is:
213 * - TCS inputs for patch 0
214 * - TCS inputs for patch 1
215 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
216 * - ...
217 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
218 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
219 * - TCS outputs for patch 1
220 * - Per-patch TCS outputs for patch 1
221 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
222 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
223 * - ...
224 *
225 * All three shaders VS(LS), TCS, TES share the same LDS space.
226 */
227
228 static LLVMValueRef
229 get_tcs_in_patch_stride(struct si_shader_context *si_shader_ctx)
230 {
231 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX)
232 return unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
233 else if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
234 return unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
235 else {
236 assert(0);
237 return NULL;
238 }
239 }
240
241 static LLVMValueRef
242 get_tcs_out_patch_stride(struct si_shader_context *si_shader_ctx)
243 {
244 return unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
245 }
246
247 static LLVMValueRef
248 get_tcs_out_patch0_offset(struct si_shader_context *si_shader_ctx)
249 {
250 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
251 unpack_param(si_shader_ctx,
252 SI_PARAM_TCS_OUT_OFFSETS,
253 0, 16),
254 4);
255 }
256
257 static LLVMValueRef
258 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *si_shader_ctx)
259 {
260 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
261 unpack_param(si_shader_ctx,
262 SI_PARAM_TCS_OUT_OFFSETS,
263 16, 16),
264 4);
265 }
266
267 static LLVMValueRef
268 get_tcs_in_current_patch_offset(struct si_shader_context *si_shader_ctx)
269 {
270 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
271 LLVMValueRef patch_stride = get_tcs_in_patch_stride(si_shader_ctx);
272 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
273
274 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
275 }
276
277 static LLVMValueRef
278 get_tcs_out_current_patch_offset(struct si_shader_context *si_shader_ctx)
279 {
280 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
281 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(si_shader_ctx);
282 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
283 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
284
285 return LLVMBuildAdd(gallivm->builder, patch0_offset,
286 LLVMBuildMul(gallivm->builder, patch_stride,
287 rel_patch_id, ""),
288 "");
289 }
290
291 static LLVMValueRef
292 get_tcs_out_current_patch_data_offset(struct si_shader_context *si_shader_ctx)
293 {
294 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
295 LLVMValueRef patch0_patch_data_offset =
296 get_tcs_out_patch0_patch_data_offset(si_shader_ctx);
297 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
298 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
299
300 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
301 LLVMBuildMul(gallivm->builder, patch_stride,
302 rel_patch_id, ""),
303 "");
304 }
305
306 static void build_indexed_store(struct si_shader_context *si_shader_ctx,
307 LLVMValueRef base_ptr, LLVMValueRef index,
308 LLVMValueRef value)
309 {
310 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
311 struct gallivm_state *gallivm = bld_base->base.gallivm;
312 LLVMValueRef indices[2], pointer;
313
314 indices[0] = bld_base->uint_bld.zero;
315 indices[1] = index;
316
317 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
318 LLVMBuildStore(gallivm->builder, value, pointer);
319 }
320
321 /**
322 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
323 * It's equivalent to doing a load from &base_ptr[index].
324 *
325 * \param base_ptr Where the array starts.
326 * \param index The element index into the array.
327 */
328 static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
329 LLVMValueRef base_ptr, LLVMValueRef index)
330 {
331 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
332 struct gallivm_state *gallivm = bld_base->base.gallivm;
333 LLVMValueRef indices[2], pointer;
334
335 indices[0] = bld_base->uint_bld.zero;
336 indices[1] = index;
337
338 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
339 return LLVMBuildLoad(gallivm->builder, pointer, "");
340 }
341
342 /**
343 * Do a load from &base_ptr[index], but also add a flag that it's loading
344 * a constant.
345 */
346 static LLVMValueRef build_indexed_load_const(
347 struct si_shader_context * si_shader_ctx,
348 LLVMValueRef base_ptr, LLVMValueRef index)
349 {
350 LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
351 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
352 return result;
353 }
354
355 static LLVMValueRef get_instance_index_for_fetch(
356 struct radeon_llvm_context * radeon_bld,
357 unsigned divisor)
358 {
359 struct si_shader_context *si_shader_ctx =
360 si_shader_context(&radeon_bld->soa.bld_base);
361 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
362
363 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
364 si_shader_ctx->param_instance_id);
365
366 /* The division must be done before START_INSTANCE is added. */
367 if (divisor > 1)
368 result = LLVMBuildUDiv(gallivm->builder, result,
369 lp_build_const_int32(gallivm, divisor), "");
370
371 return LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
372 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
373 }
374
375 static void declare_input_vs(
376 struct radeon_llvm_context *radeon_bld,
377 unsigned input_index,
378 const struct tgsi_full_declaration *decl)
379 {
380 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
381 struct gallivm_state *gallivm = base->gallivm;
382 struct si_shader_context *si_shader_ctx =
383 si_shader_context(&radeon_bld->soa.bld_base);
384 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
385
386 unsigned chan;
387
388 LLVMValueRef t_list_ptr;
389 LLVMValueRef t_offset;
390 LLVMValueRef t_list;
391 LLVMValueRef attribute_offset;
392 LLVMValueRef buffer_index;
393 LLVMValueRef args[3];
394 LLVMTypeRef vec4_type;
395 LLVMValueRef input;
396
397 /* Load the T list */
398 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
399
400 t_offset = lp_build_const_int32(gallivm, input_index);
401
402 t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
403
404 /* Build the attribute offset */
405 attribute_offset = lp_build_const_int32(gallivm, 0);
406
407 if (divisor) {
408 /* Build index from instance ID, start instance and divisor */
409 si_shader_ctx->shader->uses_instanceid = true;
410 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
411 } else {
412 /* Load the buffer index for vertices. */
413 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
414 si_shader_ctx->param_vertex_id);
415 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
416 SI_PARAM_BASE_VERTEX);
417 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
418 }
419
420 vec4_type = LLVMVectorType(base->elem_type, 4);
421 args[0] = t_list;
422 args[1] = attribute_offset;
423 args[2] = buffer_index;
424 input = lp_build_intrinsic(gallivm->builder,
425 "llvm.SI.vs.load.input", vec4_type, args, 3,
426 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
427
428 /* Break up the vec4 into individual components */
429 for (chan = 0; chan < 4; chan++) {
430 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
431 /* XXX: Use a helper function for this. There is one in
432 * tgsi_llvm.c. */
433 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
434 LLVMBuildExtractElement(gallivm->builder,
435 input, llvm_chan, "");
436 }
437 }
438
439 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
440 unsigned swizzle)
441 {
442 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
443
444 if (swizzle > 0)
445 return bld_base->uint_bld.zero;
446
447 switch (si_shader_ctx->type) {
448 case TGSI_PROCESSOR_VERTEX:
449 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
450 si_shader_ctx->param_vs_prim_id);
451 case TGSI_PROCESSOR_TESS_CTRL:
452 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
453 SI_PARAM_PATCH_ID);
454 case TGSI_PROCESSOR_TESS_EVAL:
455 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
456 si_shader_ctx->param_tes_patch_id);
457 case TGSI_PROCESSOR_GEOMETRY:
458 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
459 SI_PARAM_PRIMITIVE_ID);
460 default:
461 assert(0);
462 return bld_base->uint_bld.zero;
463 }
464 }
465
466 /**
467 * Return the value of tgsi_ind_register for indexing.
468 * This is the indirect index with the constant offset added to it.
469 */
470 static LLVMValueRef get_indirect_index(struct si_shader_context *si_shader_ctx,
471 const struct tgsi_ind_register *ind,
472 int rel_index)
473 {
474 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
475 LLVMValueRef result;
476
477 result = si_shader_ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
478 result = LLVMBuildLoad(gallivm->builder, result, "");
479 result = LLVMBuildAdd(gallivm->builder, result,
480 lp_build_const_int32(gallivm, rel_index), "");
481 return result;
482 }
483
484 /**
485 * Calculate a dword address given an input or output register and a stride.
486 */
487 static LLVMValueRef get_dw_address(struct si_shader_context *si_shader_ctx,
488 const struct tgsi_full_dst_register *dst,
489 const struct tgsi_full_src_register *src,
490 LLVMValueRef vertex_dw_stride,
491 LLVMValueRef base_addr)
492 {
493 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
494 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
495 ubyte *name, *index, *array_first;
496 int first, param;
497 struct tgsi_full_dst_register reg;
498
499 /* Set the register description. The address computation is the same
500 * for sources and destinations. */
501 if (src) {
502 reg.Register.File = src->Register.File;
503 reg.Register.Index = src->Register.Index;
504 reg.Register.Indirect = src->Register.Indirect;
505 reg.Register.Dimension = src->Register.Dimension;
506 reg.Indirect = src->Indirect;
507 reg.Dimension = src->Dimension;
508 reg.DimIndirect = src->DimIndirect;
509 } else
510 reg = *dst;
511
512 /* If the register is 2-dimensional (e.g. an array of vertices
513 * in a primitive), calculate the base address of the vertex. */
514 if (reg.Register.Dimension) {
515 LLVMValueRef index;
516
517 if (reg.Dimension.Indirect)
518 index = get_indirect_index(si_shader_ctx, &reg.DimIndirect,
519 reg.Dimension.Index);
520 else
521 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
522
523 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
524 LLVMBuildMul(gallivm->builder, index,
525 vertex_dw_stride, ""), "");
526 }
527
528 /* Get information about the register. */
529 if (reg.Register.File == TGSI_FILE_INPUT) {
530 name = info->input_semantic_name;
531 index = info->input_semantic_index;
532 array_first = info->input_array_first;
533 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
534 name = info->output_semantic_name;
535 index = info->output_semantic_index;
536 array_first = info->output_array_first;
537 } else {
538 assert(0);
539 return NULL;
540 }
541
542 if (reg.Register.Indirect) {
543 /* Add the relative address of the element. */
544 LLVMValueRef ind_index;
545
546 if (reg.Indirect.ArrayID)
547 first = array_first[reg.Indirect.ArrayID];
548 else
549 first = reg.Register.Index;
550
551 ind_index = get_indirect_index(si_shader_ctx, &reg.Indirect,
552 reg.Register.Index - first);
553
554 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
555 LLVMBuildMul(gallivm->builder, ind_index,
556 lp_build_const_int32(gallivm, 4), ""), "");
557
558 param = si_shader_io_get_unique_index(name[first], index[first]);
559 } else {
560 param = si_shader_io_get_unique_index(name[reg.Register.Index],
561 index[reg.Register.Index]);
562 }
563
564 /* Add the base address of the element. */
565 return LLVMBuildAdd(gallivm->builder, base_addr,
566 lp_build_const_int32(gallivm, param * 4), "");
567 }
568
569 /**
570 * Load from LDS.
571 *
572 * \param type output value type
573 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
574 * \param dw_addr address in dwords
575 */
576 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
577 enum tgsi_opcode_type type, unsigned swizzle,
578 LLVMValueRef dw_addr)
579 {
580 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
581 struct gallivm_state *gallivm = bld_base->base.gallivm;
582 LLVMValueRef value;
583
584 if (swizzle == ~0) {
585 LLVMValueRef values[TGSI_NUM_CHANNELS];
586
587 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
588 values[chan] = lds_load(bld_base, type, chan, dw_addr);
589
590 return lp_build_gather_values(bld_base->base.gallivm, values,
591 TGSI_NUM_CHANNELS);
592 }
593
594 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
595 lp_build_const_int32(gallivm, swizzle));
596
597 value = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
598 if (type == TGSI_TYPE_DOUBLE) {
599 LLVMValueRef value2;
600 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
601 lp_build_const_int32(gallivm, swizzle + 1));
602 value2 = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
603 return radeon_llvm_emit_fetch_double(bld_base, value, value2);
604 }
605
606 return LLVMBuildBitCast(gallivm->builder, value,
607 tgsi2llvmtype(bld_base, type), "");
608 }
609
610 /**
611 * Store to LDS.
612 *
613 * \param swizzle offset (typically 0..3)
614 * \param dw_addr address in dwords
615 * \param value value to store
616 */
617 static void lds_store(struct lp_build_tgsi_context * bld_base,
618 unsigned swizzle, LLVMValueRef dw_addr,
619 LLVMValueRef value)
620 {
621 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
622 struct gallivm_state *gallivm = bld_base->base.gallivm;
623
624 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
625 lp_build_const_int32(gallivm, swizzle));
626
627 value = LLVMBuildBitCast(gallivm->builder, value,
628 LLVMInt32TypeInContext(gallivm->context), "");
629 build_indexed_store(si_shader_ctx, si_shader_ctx->lds,
630 dw_addr, value);
631 }
632
633 static LLVMValueRef fetch_input_tcs(
634 struct lp_build_tgsi_context *bld_base,
635 const struct tgsi_full_src_register *reg,
636 enum tgsi_opcode_type type, unsigned swizzle)
637 {
638 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
639 LLVMValueRef dw_addr, stride;
640
641 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
642 dw_addr = get_tcs_in_current_patch_offset(si_shader_ctx);
643 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
644
645 return lds_load(bld_base, type, swizzle, dw_addr);
646 }
647
648 static LLVMValueRef fetch_output_tcs(
649 struct lp_build_tgsi_context *bld_base,
650 const struct tgsi_full_src_register *reg,
651 enum tgsi_opcode_type type, unsigned swizzle)
652 {
653 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
654 LLVMValueRef dw_addr, stride;
655
656 if (reg->Register.Dimension) {
657 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
658 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
659 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
660 } else {
661 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
662 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
663 }
664
665 return lds_load(bld_base, type, swizzle, dw_addr);
666 }
667
668 static LLVMValueRef fetch_input_tes(
669 struct lp_build_tgsi_context *bld_base,
670 const struct tgsi_full_src_register *reg,
671 enum tgsi_opcode_type type, unsigned swizzle)
672 {
673 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
674 LLVMValueRef dw_addr, stride;
675
676 if (reg->Register.Dimension) {
677 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
678 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
679 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
680 } else {
681 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
682 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
683 }
684
685 return lds_load(bld_base, type, swizzle, dw_addr);
686 }
687
688 static void store_output_tcs(struct lp_build_tgsi_context * bld_base,
689 const struct tgsi_full_instruction * inst,
690 const struct tgsi_opcode_info * info,
691 LLVMValueRef dst[4])
692 {
693 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
694 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
695 unsigned chan_index;
696 LLVMValueRef dw_addr, stride;
697
698 /* Only handle per-patch and per-vertex outputs here.
699 * Vectors will be lowered to scalars and this function will be called again.
700 */
701 if (reg->Register.File != TGSI_FILE_OUTPUT ||
702 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
703 radeon_llvm_emit_store(bld_base, inst, info, dst);
704 return;
705 }
706
707 if (reg->Register.Dimension) {
708 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
709 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
710 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, stride, dw_addr);
711 } else {
712 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
713 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, NULL, dw_addr);
714 }
715
716 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
717 LLVMValueRef value = dst[chan_index];
718
719 if (inst->Instruction.Saturate)
720 value = radeon_llvm_saturate(bld_base, value);
721
722 lds_store(bld_base, chan_index, dw_addr, value);
723 }
724 }
725
726 static LLVMValueRef fetch_input_gs(
727 struct lp_build_tgsi_context *bld_base,
728 const struct tgsi_full_src_register *reg,
729 enum tgsi_opcode_type type,
730 unsigned swizzle)
731 {
732 struct lp_build_context *base = &bld_base->base;
733 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
734 struct si_shader *shader = si_shader_ctx->shader;
735 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
736 struct gallivm_state *gallivm = base->gallivm;
737 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
738 LLVMValueRef vtx_offset;
739 LLVMValueRef args[9];
740 unsigned vtx_offset_param;
741 struct tgsi_shader_info *info = &shader->selector->info;
742 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
743 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
744 unsigned param;
745 LLVMValueRef value;
746
747 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
748 return get_primitive_id(bld_base, swizzle);
749
750 if (!reg->Register.Dimension)
751 return NULL;
752
753 if (swizzle == ~0) {
754 LLVMValueRef values[TGSI_NUM_CHANNELS];
755 unsigned chan;
756 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
757 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
758 }
759 return lp_build_gather_values(bld_base->base.gallivm, values,
760 TGSI_NUM_CHANNELS);
761 }
762
763 /* Get the vertex offset parameter */
764 vtx_offset_param = reg->Dimension.Index;
765 if (vtx_offset_param < 2) {
766 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
767 } else {
768 assert(vtx_offset_param < 6);
769 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
770 }
771 vtx_offset = lp_build_mul_imm(uint,
772 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
773 vtx_offset_param),
774 4);
775
776 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
777 args[0] = si_shader_ctx->esgs_ring;
778 args[1] = vtx_offset;
779 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
780 args[3] = uint->zero;
781 args[4] = uint->one; /* OFFEN */
782 args[5] = uint->zero; /* IDXEN */
783 args[6] = uint->one; /* GLC */
784 args[7] = uint->zero; /* SLC */
785 args[8] = uint->zero; /* TFE */
786
787 value = lp_build_intrinsic(gallivm->builder,
788 "llvm.SI.buffer.load.dword.i32.i32",
789 i32, args, 9,
790 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
791 if (type == TGSI_TYPE_DOUBLE) {
792 LLVMValueRef value2;
793 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
794 value2 = lp_build_intrinsic(gallivm->builder,
795 "llvm.SI.buffer.load.dword.i32.i32",
796 i32, args, 9,
797 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
798 return radeon_llvm_emit_fetch_double(bld_base,
799 value, value2);
800 }
801 return LLVMBuildBitCast(gallivm->builder,
802 value,
803 tgsi2llvmtype(bld_base, type), "");
804 }
805
806 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
807 {
808 switch (interpolate) {
809 case TGSI_INTERPOLATE_CONSTANT:
810 return 0;
811
812 case TGSI_INTERPOLATE_LINEAR:
813 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
814 return SI_PARAM_LINEAR_SAMPLE;
815 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
816 return SI_PARAM_LINEAR_CENTROID;
817 else
818 return SI_PARAM_LINEAR_CENTER;
819 break;
820 case TGSI_INTERPOLATE_COLOR:
821 case TGSI_INTERPOLATE_PERSPECTIVE:
822 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
823 return SI_PARAM_PERSP_SAMPLE;
824 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
825 return SI_PARAM_PERSP_CENTROID;
826 else
827 return SI_PARAM_PERSP_CENTER;
828 break;
829 default:
830 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
831 return -1;
832 }
833 }
834
835 /* This shouldn't be used by explicit INTERP opcodes. */
836 static unsigned select_interp_param(struct si_shader_context *si_shader_ctx,
837 unsigned param)
838 {
839 if (!si_shader_ctx->shader->key.ps.force_persample_interp)
840 return param;
841
842 /* If the shader doesn't use center/centroid, just return the parameter.
843 *
844 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
845 * switch between center/centroid and sample without shader changes.
846 */
847 switch (param) {
848 case SI_PARAM_PERSP_CENTROID:
849 case SI_PARAM_PERSP_CENTER:
850 return SI_PARAM_PERSP_SAMPLE;
851
852 case SI_PARAM_LINEAR_CENTROID:
853 case SI_PARAM_LINEAR_CENTER:
854 return SI_PARAM_LINEAR_SAMPLE;
855
856 default:
857 return param;
858 }
859 }
860
861 /**
862 * Interpolate a fragment shader input.
863 *
864 * @param si_shader_ctx context
865 * @param input_index index of the input in hardware
866 * @param semantic_name TGSI_SEMANTIC_*
867 * @param semantic_index semantic index
868 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
869 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
870 * @param interp_param interpolation weights (i,j)
871 * @param prim_mask SI_PARAM_PRIM_MASK
872 * @param face SI_PARAM_FRONT_FACE
873 * @param result the return value (4 components)
874 */
875 static void interp_fs_input(struct si_shader_context *si_shader_ctx,
876 unsigned input_index,
877 unsigned semantic_name,
878 unsigned semantic_index,
879 unsigned num_interp_inputs,
880 unsigned colors_read_mask,
881 LLVMValueRef interp_param,
882 LLVMValueRef prim_mask,
883 LLVMValueRef face,
884 LLVMValueRef result[4])
885 {
886 struct lp_build_context *base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
887 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
888 struct gallivm_state *gallivm = base->gallivm;
889 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
890 const char * intr_name;
891 LLVMValueRef attr_number;
892
893 unsigned chan;
894
895 attr_number = lp_build_const_int32(gallivm, input_index);
896
897 /* fs.constant returns the param from the middle vertex, so it's not
898 * really useful for flat shading. It's meant to be used for custom
899 * interpolation (but the intrinsic can't fetch from the other two
900 * vertices).
901 *
902 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
903 * to do the right thing. The only reason we use fs.constant is that
904 * fs.interp cannot be used on integers, because they can be equal
905 * to NaN.
906 */
907 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
908
909 if (semantic_name == TGSI_SEMANTIC_COLOR &&
910 si_shader_ctx->shader->key.ps.color_two_side) {
911 LLVMValueRef args[4];
912 LLVMValueRef is_face_positive;
913 LLVMValueRef back_attr_number;
914
915 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
916 * otherwise it's at offset "num_inputs".
917 */
918 unsigned back_attr_offset = num_interp_inputs;
919 if (semantic_index == 1 && colors_read_mask & 0xf)
920 back_attr_offset += 1;
921
922 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
923
924 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
925 face, uint->zero, "");
926
927 args[2] = prim_mask;
928 args[3] = interp_param;
929 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
930 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
931 LLVMValueRef front, back;
932
933 args[0] = llvm_chan;
934 args[1] = attr_number;
935 front = lp_build_intrinsic(gallivm->builder, intr_name,
936 input_type, args, args[3] ? 4 : 3,
937 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
938
939 args[1] = back_attr_number;
940 back = lp_build_intrinsic(gallivm->builder, intr_name,
941 input_type, args, args[3] ? 4 : 3,
942 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
943
944 result[chan] = LLVMBuildSelect(gallivm->builder,
945 is_face_positive,
946 front,
947 back,
948 "");
949 }
950 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
951 LLVMValueRef args[4];
952
953 args[0] = uint->zero;
954 args[1] = attr_number;
955 args[2] = prim_mask;
956 args[3] = interp_param;
957 result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
958 input_type, args, args[3] ? 4 : 3,
959 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
960 result[1] =
961 result[2] = lp_build_const_float(gallivm, 0.0f);
962 result[3] = lp_build_const_float(gallivm, 1.0f);
963 } else {
964 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
965 LLVMValueRef args[4];
966 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
967
968 args[0] = llvm_chan;
969 args[1] = attr_number;
970 args[2] = prim_mask;
971 args[3] = interp_param;
972 result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
973 input_type, args, args[3] ? 4 : 3,
974 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
975 }
976 }
977 }
978
979 static void declare_input_fs(
980 struct radeon_llvm_context *radeon_bld,
981 unsigned input_index,
982 const struct tgsi_full_declaration *decl)
983 {
984 struct si_shader_context *si_shader_ctx =
985 si_shader_context(&radeon_bld->soa.bld_base);
986 struct si_shader *shader = si_shader_ctx->shader;
987 LLVMValueRef main_fn = radeon_bld->main_fn;
988 LLVMValueRef interp_param = NULL;
989 int interp_param_idx;
990
991 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
992 decl->Interp.Location);
993 if (interp_param_idx == -1)
994 return;
995 else if (interp_param_idx) {
996 interp_param_idx = select_interp_param(si_shader_ctx,
997 interp_param_idx);
998 interp_param = LLVMGetParam(main_fn, interp_param_idx);
999 }
1000
1001 interp_fs_input(si_shader_ctx, input_index, decl->Semantic.Name,
1002 decl->Semantic.Index, shader->selector->info.num_inputs,
1003 shader->selector->info.colors_read, interp_param,
1004 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1005 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1006 &radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)]);
1007 }
1008
1009 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1010 {
1011 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1012 SI_PARAM_ANCILLARY, 8, 4);
1013 }
1014
1015 /**
1016 * Load a dword from a constant buffer.
1017 */
1018 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1019 LLVMValueRef offset, LLVMTypeRef return_type)
1020 {
1021 LLVMValueRef args[2] = {resource, offset};
1022
1023 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1024 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1025 }
1026
1027 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1028 {
1029 struct si_shader_context *si_shader_ctx =
1030 si_shader_context(&radeon_bld->soa.bld_base);
1031 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1032 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1033 LLVMBuilderRef builder = gallivm->builder;
1034 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1035 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
1036 LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
1037
1038 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1039 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1040 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1041
1042 LLVMValueRef pos[4] = {
1043 buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
1044 buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
1045 lp_build_const_float(gallivm, 0),
1046 lp_build_const_float(gallivm, 0)
1047 };
1048
1049 return lp_build_gather_values(gallivm, pos, 4);
1050 }
1051
1052 static void declare_system_value(
1053 struct radeon_llvm_context * radeon_bld,
1054 unsigned index,
1055 const struct tgsi_full_declaration *decl)
1056 {
1057 struct si_shader_context *si_shader_ctx =
1058 si_shader_context(&radeon_bld->soa.bld_base);
1059 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1060 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1061 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1062 LLVMValueRef value = 0;
1063
1064 switch (decl->Semantic.Name) {
1065 case TGSI_SEMANTIC_INSTANCEID:
1066 value = LLVMGetParam(radeon_bld->main_fn,
1067 si_shader_ctx->param_instance_id);
1068 break;
1069
1070 case TGSI_SEMANTIC_VERTEXID:
1071 value = LLVMBuildAdd(gallivm->builder,
1072 LLVMGetParam(radeon_bld->main_fn,
1073 si_shader_ctx->param_vertex_id),
1074 LLVMGetParam(radeon_bld->main_fn,
1075 SI_PARAM_BASE_VERTEX), "");
1076 break;
1077
1078 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1079 value = LLVMGetParam(radeon_bld->main_fn,
1080 si_shader_ctx->param_vertex_id);
1081 break;
1082
1083 case TGSI_SEMANTIC_BASEVERTEX:
1084 value = LLVMGetParam(radeon_bld->main_fn,
1085 SI_PARAM_BASE_VERTEX);
1086 break;
1087
1088 case TGSI_SEMANTIC_INVOCATIONID:
1089 if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
1090 value = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1091 else if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY)
1092 value = LLVMGetParam(radeon_bld->main_fn,
1093 SI_PARAM_GS_INSTANCE_ID);
1094 else
1095 assert(!"INVOCATIONID not implemented");
1096 break;
1097
1098 case TGSI_SEMANTIC_POSITION:
1099 {
1100 LLVMValueRef pos[4] = {
1101 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1102 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1103 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1104 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1105 LLVMGetParam(radeon_bld->main_fn,
1106 SI_PARAM_POS_W_FLOAT)),
1107 };
1108 value = lp_build_gather_values(gallivm, pos, 4);
1109 break;
1110 }
1111
1112 case TGSI_SEMANTIC_FACE:
1113 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1114 break;
1115
1116 case TGSI_SEMANTIC_SAMPLEID:
1117 value = get_sample_id(radeon_bld);
1118 break;
1119
1120 case TGSI_SEMANTIC_SAMPLEPOS: {
1121 LLVMValueRef pos[4] = {
1122 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1123 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1124 lp_build_const_float(gallivm, 0),
1125 lp_build_const_float(gallivm, 0)
1126 };
1127 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1128 TGSI_OPCODE_FRC, pos[0]);
1129 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1130 TGSI_OPCODE_FRC, pos[1]);
1131 value = lp_build_gather_values(gallivm, pos, 4);
1132 break;
1133 }
1134
1135 case TGSI_SEMANTIC_SAMPLEMASK:
1136 /* Smoothing isn't MSAA in GL, but it's MSAA in hardware.
1137 * Therefore, force gl_SampleMaskIn to 1 for GL. */
1138 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
1139 value = uint_bld->one;
1140 else
1141 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1142 break;
1143
1144 case TGSI_SEMANTIC_TESSCOORD:
1145 {
1146 LLVMValueRef coord[4] = {
1147 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_u),
1148 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_v),
1149 bld->zero,
1150 bld->zero
1151 };
1152
1153 /* For triangles, the vector should be (u, v, 1-u-v). */
1154 if (si_shader_ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1155 PIPE_PRIM_TRIANGLES)
1156 coord[2] = lp_build_sub(bld, bld->one,
1157 lp_build_add(bld, coord[0], coord[1]));
1158
1159 value = lp_build_gather_values(gallivm, coord, 4);
1160 break;
1161 }
1162
1163 case TGSI_SEMANTIC_VERTICESIN:
1164 value = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1165 break;
1166
1167 case TGSI_SEMANTIC_TESSINNER:
1168 case TGSI_SEMANTIC_TESSOUTER:
1169 {
1170 LLVMValueRef dw_addr;
1171 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1172
1173 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1174 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1175 lp_build_const_int32(gallivm, param * 4), "");
1176
1177 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1178 ~0, dw_addr);
1179 break;
1180 }
1181
1182 case TGSI_SEMANTIC_PRIMID:
1183 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1184 break;
1185
1186 default:
1187 assert(!"unknown system value");
1188 return;
1189 }
1190
1191 radeon_bld->system_values[index] = value;
1192 }
1193
1194 static LLVMValueRef fetch_constant(
1195 struct lp_build_tgsi_context * bld_base,
1196 const struct tgsi_full_src_register *reg,
1197 enum tgsi_opcode_type type,
1198 unsigned swizzle)
1199 {
1200 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1201 struct lp_build_context * base = &bld_base->base;
1202 const struct tgsi_ind_register *ireg = &reg->Indirect;
1203 unsigned buf, idx;
1204
1205 LLVMValueRef addr, bufp;
1206 LLVMValueRef result;
1207
1208 if (swizzle == LP_CHAN_ALL) {
1209 unsigned chan;
1210 LLVMValueRef values[4];
1211 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1212 values[chan] = fetch_constant(bld_base, reg, type, chan);
1213
1214 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1215 }
1216
1217 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1218 idx = reg->Register.Index * 4 + swizzle;
1219
1220 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1221 if (type != TGSI_TYPE_DOUBLE)
1222 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
1223 else {
1224 return radeon_llvm_emit_fetch_double(bld_base,
1225 si_shader_ctx->constants[buf][idx],
1226 si_shader_ctx->constants[buf][idx + 1]);
1227 }
1228 }
1229
1230 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1231 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1232 LLVMValueRef index;
1233 index = get_indirect_index(si_shader_ctx, &reg->DimIndirect,
1234 reg->Dimension.Index);
1235 bufp = build_indexed_load_const(si_shader_ctx, ptr, index);
1236 } else
1237 bufp = si_shader_ctx->const_buffers[buf];
1238
1239 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1240 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1241 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1242 addr = lp_build_add(&bld_base->uint_bld, addr,
1243 lp_build_const_int32(base->gallivm, idx * 4));
1244
1245 result = buffer_load_const(base->gallivm->builder, bufp,
1246 addr, bld_base->base.elem_type);
1247
1248 if (type != TGSI_TYPE_DOUBLE)
1249 result = bitcast(bld_base, type, result);
1250 else {
1251 LLVMValueRef addr2, result2;
1252 addr2 = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1253 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1254 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1255 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1256 lp_build_const_int32(base->gallivm, idx * 4));
1257
1258 result2 = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_buffers[buf],
1259 addr2, bld_base->base.elem_type);
1260
1261 result = radeon_llvm_emit_fetch_double(bld_base,
1262 result, result2);
1263 }
1264 return result;
1265 }
1266
1267 /* Upper 16 bits must be zero. */
1268 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1269 LLVMValueRef val[2])
1270 {
1271 return LLVMBuildOr(gallivm->builder, val[0],
1272 LLVMBuildShl(gallivm->builder, val[1],
1273 lp_build_const_int32(gallivm, 16),
1274 ""), "");
1275 }
1276
1277 /* Upper 16 bits are ignored and will be dropped. */
1278 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1279 LLVMValueRef val[2])
1280 {
1281 LLVMValueRef v[2] = {
1282 LLVMBuildAnd(gallivm->builder, val[0],
1283 lp_build_const_int32(gallivm, 0xffff), ""),
1284 val[1],
1285 };
1286 return si_llvm_pack_two_int16(gallivm, v);
1287 }
1288
1289 /* Initialize arguments for the shader export intrinsic */
1290 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1291 LLVMValueRef *values,
1292 unsigned target,
1293 LLVMValueRef *args)
1294 {
1295 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1296 struct lp_build_context *uint =
1297 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1298 struct lp_build_context *base = &bld_base->base;
1299 struct gallivm_state *gallivm = base->gallivm;
1300 LLVMBuilderRef builder = base->gallivm->builder;
1301 LLVMValueRef val[4];
1302 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1303 unsigned chan;
1304 bool is_int8;
1305
1306 /* Default is 0xf. Adjusted below depending on the format. */
1307 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1308
1309 /* Specify whether the EXEC mask represents the valid mask */
1310 args[1] = uint->zero;
1311
1312 /* Specify whether this is the last export */
1313 args[2] = uint->zero;
1314
1315 /* Specify the target we are exporting */
1316 args[3] = lp_build_const_int32(base->gallivm, target);
1317
1318 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
1319 const union si_shader_key *key = &si_shader_ctx->shader->key;
1320 unsigned col_formats = key->ps.spi_shader_col_format;
1321 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1322
1323 assert(cbuf >= 0 && cbuf < 8);
1324 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1325 is_int8 = (key->ps.color_is_int8 >> cbuf) & 0x1;
1326 }
1327
1328 args[4] = uint->zero; /* COMPR flag */
1329 args[5] = base->undef;
1330 args[6] = base->undef;
1331 args[7] = base->undef;
1332 args[8] = base->undef;
1333
1334 switch (spi_shader_col_format) {
1335 case V_028714_SPI_SHADER_ZERO:
1336 args[0] = uint->zero; /* writemask */
1337 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
1338 break;
1339
1340 case V_028714_SPI_SHADER_32_R:
1341 args[0] = uint->one; /* writemask */
1342 args[5] = values[0];
1343 break;
1344
1345 case V_028714_SPI_SHADER_32_GR:
1346 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
1347 args[5] = values[0];
1348 args[6] = values[1];
1349 break;
1350
1351 case V_028714_SPI_SHADER_32_AR:
1352 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
1353 args[5] = values[0];
1354 args[8] = values[3];
1355 break;
1356
1357 case V_028714_SPI_SHADER_FP16_ABGR:
1358 args[4] = uint->one; /* COMPR flag */
1359
1360 for (chan = 0; chan < 2; chan++) {
1361 LLVMValueRef pack_args[2] = {
1362 values[2 * chan],
1363 values[2 * chan + 1]
1364 };
1365 LLVMValueRef packed;
1366
1367 packed = lp_build_intrinsic(base->gallivm->builder,
1368 "llvm.SI.packf16",
1369 uint->elem_type, pack_args, 2,
1370 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1371 args[chan + 5] =
1372 LLVMBuildBitCast(base->gallivm->builder,
1373 packed, base->elem_type, "");
1374 }
1375 break;
1376
1377 case V_028714_SPI_SHADER_UNORM16_ABGR:
1378 for (chan = 0; chan < 4; chan++) {
1379 val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
1380 val[chan] = LLVMBuildFMul(builder, val[chan],
1381 lp_build_const_float(gallivm, 65535), "");
1382 val[chan] = LLVMBuildFAdd(builder, val[chan],
1383 lp_build_const_float(gallivm, 0.5), "");
1384 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1385 uint->elem_type, "");
1386 }
1387
1388 args[4] = uint->one; /* COMPR flag */
1389 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1390 si_llvm_pack_two_int16(gallivm, val));
1391 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1392 si_llvm_pack_two_int16(gallivm, val+2));
1393 break;
1394
1395 case V_028714_SPI_SHADER_SNORM16_ABGR:
1396 for (chan = 0; chan < 4; chan++) {
1397 /* Clamp between [-1, 1]. */
1398 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1399 values[chan],
1400 lp_build_const_float(gallivm, 1));
1401 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1402 val[chan],
1403 lp_build_const_float(gallivm, -1));
1404 /* Convert to a signed integer in [-32767, 32767]. */
1405 val[chan] = LLVMBuildFMul(builder, val[chan],
1406 lp_build_const_float(gallivm, 32767), "");
1407 /* If positive, add 0.5, else add -0.5. */
1408 val[chan] = LLVMBuildFAdd(builder, val[chan],
1409 LLVMBuildSelect(builder,
1410 LLVMBuildFCmp(builder, LLVMRealOGE,
1411 val[chan], base->zero, ""),
1412 lp_build_const_float(gallivm, 0.5),
1413 lp_build_const_float(gallivm, -0.5), ""), "");
1414 val[chan] = LLVMBuildFPToSI(builder, val[chan], uint->elem_type, "");
1415 }
1416
1417 args[4] = uint->one; /* COMPR flag */
1418 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1419 si_llvm_pack_two_int32_as_int16(gallivm, val));
1420 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1421 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1422 break;
1423
1424 case V_028714_SPI_SHADER_UINT16_ABGR: {
1425 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1426 255 : 65535);
1427 /* Clamp. */
1428 for (chan = 0; chan < 4; chan++) {
1429 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1430 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1431 val[chan], max);
1432 }
1433
1434 args[4] = uint->one; /* COMPR flag */
1435 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1436 si_llvm_pack_two_int16(gallivm, val));
1437 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1438 si_llvm_pack_two_int16(gallivm, val+2));
1439 break;
1440 }
1441
1442 case V_028714_SPI_SHADER_SINT16_ABGR: {
1443 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1444 127 : 32767);
1445 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
1446 -128 : -32768);
1447 /* Clamp. */
1448 for (chan = 0; chan < 4; chan++) {
1449 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1450 val[chan] = lp_build_emit_llvm_binary(bld_base,
1451 TGSI_OPCODE_IMIN,
1452 val[chan], max);
1453 val[chan] = lp_build_emit_llvm_binary(bld_base,
1454 TGSI_OPCODE_IMAX,
1455 val[chan], min);
1456 }
1457
1458 args[4] = uint->one; /* COMPR flag */
1459 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1460 si_llvm_pack_two_int32_as_int16(gallivm, val));
1461 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1462 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1463 break;
1464 }
1465
1466 case V_028714_SPI_SHADER_32_ABGR:
1467 memcpy(&args[5], values, sizeof(values[0]) * 4);
1468 break;
1469 }
1470 }
1471
1472 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1473 LLVMValueRef alpha)
1474 {
1475 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1476 struct gallivm_state *gallivm = bld_base->base.gallivm;
1477
1478 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
1479 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1480 SI_PARAM_ALPHA_REF);
1481
1482 LLVMValueRef alpha_pass =
1483 lp_build_cmp(&bld_base->base,
1484 si_shader_ctx->shader->key.ps.alpha_func,
1485 alpha, alpha_ref);
1486 LLVMValueRef arg =
1487 lp_build_select(&bld_base->base,
1488 alpha_pass,
1489 lp_build_const_float(gallivm, 1.0f),
1490 lp_build_const_float(gallivm, -1.0f));
1491
1492 lp_build_intrinsic(gallivm->builder,
1493 "llvm.AMDGPU.kill",
1494 LLVMVoidTypeInContext(gallivm->context),
1495 &arg, 1, 0);
1496 } else {
1497 lp_build_intrinsic(gallivm->builder,
1498 "llvm.AMDGPU.kilp",
1499 LLVMVoidTypeInContext(gallivm->context),
1500 NULL, 0, 0);
1501 }
1502 }
1503
1504 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1505 LLVMValueRef alpha)
1506 {
1507 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1508 struct gallivm_state *gallivm = bld_base->base.gallivm;
1509 LLVMValueRef coverage;
1510
1511 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1512 coverage = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1513 SI_PARAM_SAMPLE_COVERAGE);
1514 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1515
1516 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1517 bld_base->int_bld.elem_type,
1518 &coverage, 1, LLVMReadNoneAttribute);
1519
1520 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1521 bld_base->base.elem_type, "");
1522
1523 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1524 lp_build_const_float(gallivm,
1525 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1526
1527 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1528 }
1529
1530 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
1531 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1532 {
1533 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1534 struct lp_build_context *base = &bld_base->base;
1535 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1536 unsigned reg_index;
1537 unsigned chan;
1538 unsigned const_chan;
1539 LLVMValueRef base_elt;
1540 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1541 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
1542 LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
1543
1544 for (reg_index = 0; reg_index < 2; reg_index ++) {
1545 LLVMValueRef *args = pos[2 + reg_index];
1546
1547 args[5] =
1548 args[6] =
1549 args[7] =
1550 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1551
1552 /* Compute dot products of position and user clip plane vectors */
1553 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1554 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1555 args[1] = lp_build_const_int32(base->gallivm,
1556 ((reg_index * 4 + chan) * 4 +
1557 const_chan) * 4);
1558 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1559 args[1], base->elem_type);
1560 args[5 + chan] =
1561 lp_build_add(base, args[5 + chan],
1562 lp_build_mul(base, base_elt,
1563 out_elts[const_chan]));
1564 }
1565 }
1566
1567 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1568 args[1] = uint->zero;
1569 args[2] = uint->zero;
1570 args[3] = lp_build_const_int32(base->gallivm,
1571 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1572 args[4] = uint->zero;
1573 }
1574 }
1575
1576 static void si_dump_streamout(struct pipe_stream_output_info *so)
1577 {
1578 unsigned i;
1579
1580 if (so->num_outputs)
1581 fprintf(stderr, "STREAMOUT\n");
1582
1583 for (i = 0; i < so->num_outputs; i++) {
1584 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1585 so->output[i].start_component;
1586 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1587 i, so->output[i].output_buffer,
1588 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1589 so->output[i].register_index,
1590 mask & 1 ? "x" : "",
1591 mask & 2 ? "y" : "",
1592 mask & 4 ? "z" : "",
1593 mask & 8 ? "w" : "");
1594 }
1595 }
1596
1597 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1598 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1599 * or v4i32 (num_channels=3,4). */
1600 static void build_tbuffer_store(struct si_shader_context *shader,
1601 LLVMValueRef rsrc,
1602 LLVMValueRef vdata,
1603 unsigned num_channels,
1604 LLVMValueRef vaddr,
1605 LLVMValueRef soffset,
1606 unsigned inst_offset,
1607 unsigned dfmt,
1608 unsigned nfmt,
1609 unsigned offen,
1610 unsigned idxen,
1611 unsigned glc,
1612 unsigned slc,
1613 unsigned tfe)
1614 {
1615 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1616 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1617 LLVMValueRef args[] = {
1618 rsrc,
1619 vdata,
1620 LLVMConstInt(i32, num_channels, 0),
1621 vaddr,
1622 soffset,
1623 LLVMConstInt(i32, inst_offset, 0),
1624 LLVMConstInt(i32, dfmt, 0),
1625 LLVMConstInt(i32, nfmt, 0),
1626 LLVMConstInt(i32, offen, 0),
1627 LLVMConstInt(i32, idxen, 0),
1628 LLVMConstInt(i32, glc, 0),
1629 LLVMConstInt(i32, slc, 0),
1630 LLVMConstInt(i32, tfe, 0)
1631 };
1632
1633 /* The instruction offset field has 12 bits */
1634 assert(offen || inst_offset < (1 << 12));
1635
1636 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1637 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1638 const char *types[] = {"i32", "v2i32", "v4i32"};
1639 char name[256];
1640 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1641
1642 lp_build_intrinsic(gallivm->builder, name,
1643 LLVMVoidTypeInContext(gallivm->context),
1644 args, Elements(args), 0);
1645 }
1646
1647 static void build_tbuffer_store_dwords(struct si_shader_context *shader,
1648 LLVMValueRef rsrc,
1649 LLVMValueRef vdata,
1650 unsigned num_channels,
1651 LLVMValueRef vaddr,
1652 LLVMValueRef soffset,
1653 unsigned inst_offset)
1654 {
1655 static unsigned dfmt[] = {
1656 V_008F0C_BUF_DATA_FORMAT_32,
1657 V_008F0C_BUF_DATA_FORMAT_32_32,
1658 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1659 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1660 };
1661 assert(num_channels >= 1 && num_channels <= 4);
1662
1663 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
1664 inst_offset, dfmt[num_channels-1],
1665 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1666 }
1667
1668 /* On SI, the vertex shader is responsible for writing streamout data
1669 * to buffers. */
1670 static void si_llvm_emit_streamout(struct si_shader_context *shader,
1671 struct si_shader_output_values *outputs,
1672 unsigned noutput)
1673 {
1674 struct pipe_stream_output_info *so = &shader->shader->selector->so;
1675 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1676 LLVMBuilderRef builder = gallivm->builder;
1677 int i, j;
1678 struct lp_build_if_state if_ctx;
1679
1680 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1681
1682 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1683 LLVMValueRef so_vtx_count =
1684 unpack_param(shader, shader->param_streamout_config, 16, 7);
1685
1686 LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", i32,
1687 NULL, 0, LLVMReadNoneAttribute);
1688
1689 /* can_emit = tid < so_vtx_count; */
1690 LLVMValueRef can_emit =
1691 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1692
1693 LLVMValueRef stream_id =
1694 unpack_param(shader, shader->param_streamout_config, 24, 2);
1695
1696 /* Emit the streamout code conditionally. This actually avoids
1697 * out-of-bounds buffer access. The hw tells us via the SGPR
1698 * (so_vtx_count) which threads are allowed to emit streamout data. */
1699 lp_build_if(&if_ctx, gallivm, can_emit);
1700 {
1701 /* The buffer offset is computed as follows:
1702 * ByteOffset = streamout_offset[buffer_id]*4 +
1703 * (streamout_write_index + thread_id)*stride[buffer_id] +
1704 * attrib_offset
1705 */
1706
1707 LLVMValueRef so_write_index =
1708 LLVMGetParam(shader->radeon_bld.main_fn,
1709 shader->param_streamout_write_index);
1710
1711 /* Compute (streamout_write_index + thread_id). */
1712 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1713
1714 /* Compute the write offset for each enabled buffer. */
1715 LLVMValueRef so_write_offset[4] = {};
1716 for (i = 0; i < 4; i++) {
1717 if (!so->stride[i])
1718 continue;
1719
1720 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1721 shader->param_streamout_offset[i]);
1722 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1723
1724 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1725 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1726 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1727 }
1728
1729 /* Write streamout data. */
1730 for (i = 0; i < so->num_outputs; i++) {
1731 unsigned buf_idx = so->output[i].output_buffer;
1732 unsigned reg = so->output[i].register_index;
1733 unsigned start = so->output[i].start_component;
1734 unsigned num_comps = so->output[i].num_components;
1735 unsigned stream = so->output[i].stream;
1736 LLVMValueRef out[4];
1737 struct lp_build_if_state if_ctx_stream;
1738
1739 assert(num_comps && num_comps <= 4);
1740 if (!num_comps || num_comps > 4)
1741 continue;
1742
1743 if (reg >= noutput)
1744 continue;
1745
1746 /* Load the output as int. */
1747 for (j = 0; j < num_comps; j++) {
1748 out[j] = LLVMBuildBitCast(builder,
1749 outputs[reg].values[start+j],
1750 i32, "");
1751 }
1752
1753 /* Pack the output. */
1754 LLVMValueRef vdata = NULL;
1755
1756 switch (num_comps) {
1757 case 1: /* as i32 */
1758 vdata = out[0];
1759 break;
1760 case 2: /* as v2i32 */
1761 case 3: /* as v4i32 (aligned to 4) */
1762 case 4: /* as v4i32 */
1763 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1764 for (j = 0; j < num_comps; j++) {
1765 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1766 LLVMConstInt(i32, j, 0), "");
1767 }
1768 break;
1769 }
1770
1771 LLVMValueRef can_emit_stream =
1772 LLVMBuildICmp(builder, LLVMIntEQ,
1773 stream_id,
1774 lp_build_const_int32(gallivm, stream), "");
1775
1776 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1777 build_tbuffer_store_dwords(shader, shader->so_buffers[buf_idx],
1778 vdata, num_comps,
1779 so_write_offset[buf_idx],
1780 LLVMConstInt(i32, 0, 0),
1781 so->output[i].dst_offset*4);
1782 lp_build_endif(&if_ctx_stream);
1783 }
1784 }
1785 lp_build_endif(&if_ctx);
1786 }
1787
1788
1789 /* Generate export instructions for hardware VS shader stage */
1790 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1791 struct si_shader_output_values *outputs,
1792 unsigned noutput)
1793 {
1794 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1795 struct si_shader * shader = si_shader_ctx->shader;
1796 struct lp_build_context * base = &bld_base->base;
1797 struct lp_build_context * uint =
1798 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1799 LLVMValueRef args[9];
1800 LLVMValueRef pos_args[4][9] = { { 0 } };
1801 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1802 unsigned semantic_name, semantic_index;
1803 unsigned target;
1804 unsigned param_count = 0;
1805 unsigned pos_idx;
1806 int i;
1807
1808 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1809 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1810 }
1811
1812 for (i = 0; i < noutput; i++) {
1813 semantic_name = outputs[i].name;
1814 semantic_index = outputs[i].sid;
1815
1816 handle_semantic:
1817 /* Select the correct target */
1818 switch(semantic_name) {
1819 case TGSI_SEMANTIC_PSIZE:
1820 psize_value = outputs[i].values[0];
1821 continue;
1822 case TGSI_SEMANTIC_EDGEFLAG:
1823 edgeflag_value = outputs[i].values[0];
1824 continue;
1825 case TGSI_SEMANTIC_LAYER:
1826 layer_value = outputs[i].values[0];
1827 semantic_name = TGSI_SEMANTIC_GENERIC;
1828 goto handle_semantic;
1829 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1830 viewport_index_value = outputs[i].values[0];
1831 semantic_name = TGSI_SEMANTIC_GENERIC;
1832 goto handle_semantic;
1833 case TGSI_SEMANTIC_POSITION:
1834 target = V_008DFC_SQ_EXP_POS;
1835 break;
1836 case TGSI_SEMANTIC_COLOR:
1837 case TGSI_SEMANTIC_BCOLOR:
1838 target = V_008DFC_SQ_EXP_PARAM + param_count;
1839 shader->vs_output_param_offset[i] = param_count;
1840 param_count++;
1841 break;
1842 case TGSI_SEMANTIC_CLIPDIST:
1843 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1844 break;
1845 case TGSI_SEMANTIC_CLIPVERTEX:
1846 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1847 continue;
1848 case TGSI_SEMANTIC_PRIMID:
1849 case TGSI_SEMANTIC_FOG:
1850 case TGSI_SEMANTIC_TEXCOORD:
1851 case TGSI_SEMANTIC_GENERIC:
1852 target = V_008DFC_SQ_EXP_PARAM + param_count;
1853 shader->vs_output_param_offset[i] = param_count;
1854 param_count++;
1855 break;
1856 default:
1857 target = 0;
1858 fprintf(stderr,
1859 "Warning: SI unhandled vs output type:%d\n",
1860 semantic_name);
1861 }
1862
1863 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1864
1865 if (target >= V_008DFC_SQ_EXP_POS &&
1866 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1867 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1868 args, sizeof(args));
1869 } else {
1870 lp_build_intrinsic(base->gallivm->builder,
1871 "llvm.SI.export",
1872 LLVMVoidTypeInContext(base->gallivm->context),
1873 args, 9, 0);
1874 }
1875
1876 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1877 semantic_name = TGSI_SEMANTIC_GENERIC;
1878 goto handle_semantic;
1879 }
1880 }
1881
1882 shader->nr_param_exports = param_count;
1883
1884 /* We need to add the position output manually if it's missing. */
1885 if (!pos_args[0][0]) {
1886 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1887 pos_args[0][1] = uint->zero; /* EXEC mask */
1888 pos_args[0][2] = uint->zero; /* last export? */
1889 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1890 pos_args[0][4] = uint->zero; /* COMPR flag */
1891 pos_args[0][5] = base->zero; /* X */
1892 pos_args[0][6] = base->zero; /* Y */
1893 pos_args[0][7] = base->zero; /* Z */
1894 pos_args[0][8] = base->one; /* W */
1895 }
1896
1897 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1898 if (shader->selector->info.writes_psize ||
1899 shader->selector->info.writes_edgeflag ||
1900 shader->selector->info.writes_viewport_index ||
1901 shader->selector->info.writes_layer) {
1902 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1903 shader->selector->info.writes_psize |
1904 (shader->selector->info.writes_edgeflag << 1) |
1905 (shader->selector->info.writes_layer << 2) |
1906 (shader->selector->info.writes_viewport_index << 3));
1907 pos_args[1][1] = uint->zero; /* EXEC mask */
1908 pos_args[1][2] = uint->zero; /* last export? */
1909 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1910 pos_args[1][4] = uint->zero; /* COMPR flag */
1911 pos_args[1][5] = base->zero; /* X */
1912 pos_args[1][6] = base->zero; /* Y */
1913 pos_args[1][7] = base->zero; /* Z */
1914 pos_args[1][8] = base->zero; /* W */
1915
1916 if (shader->selector->info.writes_psize)
1917 pos_args[1][5] = psize_value;
1918
1919 if (shader->selector->info.writes_edgeflag) {
1920 /* The output is a float, but the hw expects an integer
1921 * with the first bit containing the edge flag. */
1922 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1923 edgeflag_value,
1924 bld_base->uint_bld.elem_type, "");
1925 edgeflag_value = lp_build_min(&bld_base->int_bld,
1926 edgeflag_value,
1927 bld_base->int_bld.one);
1928
1929 /* The LLVM intrinsic expects a float. */
1930 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1931 edgeflag_value,
1932 base->elem_type, "");
1933 }
1934
1935 if (shader->selector->info.writes_layer)
1936 pos_args[1][7] = layer_value;
1937
1938 if (shader->selector->info.writes_viewport_index)
1939 pos_args[1][8] = viewport_index_value;
1940 }
1941
1942 for (i = 0; i < 4; i++)
1943 if (pos_args[i][0])
1944 shader->nr_pos_exports++;
1945
1946 pos_idx = 0;
1947 for (i = 0; i < 4; i++) {
1948 if (!pos_args[i][0])
1949 continue;
1950
1951 /* Specify the target we are exporting */
1952 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1953
1954 if (pos_idx == shader->nr_pos_exports)
1955 /* Specify that this is the last export */
1956 pos_args[i][2] = uint->one;
1957
1958 lp_build_intrinsic(base->gallivm->builder,
1959 "llvm.SI.export",
1960 LLVMVoidTypeInContext(base->gallivm->context),
1961 pos_args[i], 9, 0);
1962 }
1963 }
1964
1965 /* This only writes the tessellation factor levels. */
1966 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
1967 {
1968 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1969 struct gallivm_state *gallivm = bld_base->base.gallivm;
1970 struct si_shader *shader = si_shader_ctx->shader;
1971 unsigned tess_inner_index, tess_outer_index;
1972 LLVMValueRef lds_base, lds_inner, lds_outer;
1973 LLVMValueRef tf_base, rel_patch_id, byteoffset, buffer, rw_buffers;
1974 LLVMValueRef out[6], vec0, vec1, invocation_id;
1975 unsigned stride, outer_comps, inner_comps, i;
1976 struct lp_build_if_state if_ctx;
1977
1978 invocation_id = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1979
1980 /* Do this only for invocation 0, because the tess levels are per-patch,
1981 * not per-vertex.
1982 *
1983 * This can't jump, because invocation 0 executes this. It should
1984 * at least mask out the loads and stores for other invocations.
1985 */
1986 lp_build_if(&if_ctx, gallivm,
1987 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
1988 invocation_id, bld_base->uint_bld.zero, ""));
1989
1990 /* Determine the layout of one tess factor element in the buffer. */
1991 switch (shader->key.tcs.prim_mode) {
1992 case PIPE_PRIM_LINES:
1993 stride = 2; /* 2 dwords, 1 vec2 store */
1994 outer_comps = 2;
1995 inner_comps = 0;
1996 break;
1997 case PIPE_PRIM_TRIANGLES:
1998 stride = 4; /* 4 dwords, 1 vec4 store */
1999 outer_comps = 3;
2000 inner_comps = 1;
2001 break;
2002 case PIPE_PRIM_QUADS:
2003 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2004 outer_comps = 4;
2005 inner_comps = 2;
2006 break;
2007 default:
2008 assert(0);
2009 return;
2010 }
2011
2012 /* Load tess_inner and tess_outer from LDS.
2013 * Any invocation can write them, so we can't get them from a temporary.
2014 */
2015 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2016 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2017
2018 lds_base = get_tcs_out_current_patch_data_offset(si_shader_ctx);
2019 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2020 lp_build_const_int32(gallivm,
2021 tess_inner_index * 4), "");
2022 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2023 lp_build_const_int32(gallivm,
2024 tess_outer_index * 4), "");
2025
2026 for (i = 0; i < outer_comps; i++)
2027 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2028 for (i = 0; i < inner_comps; i++)
2029 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2030
2031 /* Convert the outputs to vectors for stores. */
2032 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2033 vec1 = NULL;
2034
2035 if (stride > 4)
2036 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2037
2038 /* Get the buffer. */
2039 rw_buffers = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2040 SI_PARAM_RW_BUFFERS);
2041 buffer = build_indexed_load_const(si_shader_ctx, rw_buffers,
2042 lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR));
2043
2044 /* Get the offset. */
2045 tf_base = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2046 SI_PARAM_TESS_FACTOR_OFFSET);
2047 rel_patch_id = get_rel_patch_id(si_shader_ctx);
2048 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2049 lp_build_const_int32(gallivm, 4 * stride), "");
2050
2051 /* Store the outputs. */
2052 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec0,
2053 MIN2(stride, 4), byteoffset, tf_base, 0);
2054 if (vec1)
2055 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec1,
2056 stride - 4, byteoffset, tf_base, 16);
2057 lp_build_endif(&if_ctx);
2058 }
2059
2060 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context * bld_base)
2061 {
2062 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2063 struct si_shader *shader = si_shader_ctx->shader;
2064 struct tgsi_shader_info *info = &shader->selector->info;
2065 struct gallivm_state *gallivm = bld_base->base.gallivm;
2066 unsigned i, chan;
2067 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2068 si_shader_ctx->param_rel_auto_id);
2069 LLVMValueRef vertex_dw_stride =
2070 unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2071 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2072 vertex_dw_stride, "");
2073
2074 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2075 * its inputs from it. */
2076 for (i = 0; i < info->num_outputs; i++) {
2077 LLVMValueRef *out_ptr = si_shader_ctx->radeon_bld.soa.outputs[i];
2078 unsigned name = info->output_semantic_name[i];
2079 unsigned index = info->output_semantic_index[i];
2080 int param = si_shader_io_get_unique_index(name, index);
2081 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2082 lp_build_const_int32(gallivm, param * 4), "");
2083
2084 for (chan = 0; chan < 4; chan++) {
2085 lds_store(bld_base, chan, dw_addr,
2086 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2087 }
2088 }
2089 }
2090
2091 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
2092 {
2093 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2094 struct gallivm_state *gallivm = bld_base->base.gallivm;
2095 struct si_shader *es = si_shader_ctx->shader;
2096 struct tgsi_shader_info *info = &es->selector->info;
2097 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2098 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2099 si_shader_ctx->param_es2gs_offset);
2100 unsigned chan;
2101 int i;
2102
2103 for (i = 0; i < info->num_outputs; i++) {
2104 LLVMValueRef *out_ptr =
2105 si_shader_ctx->radeon_bld.soa.outputs[i];
2106 int param_index;
2107
2108 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2109 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2110 continue;
2111
2112 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2113 info->output_semantic_index[i]);
2114
2115 for (chan = 0; chan < 4; chan++) {
2116 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2117 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2118
2119 build_tbuffer_store(si_shader_ctx,
2120 si_shader_ctx->esgs_ring,
2121 out_val, 1,
2122 LLVMGetUndef(i32), soffset,
2123 (4 * param_index + chan) * 4,
2124 V_008F0C_BUF_DATA_FORMAT_32,
2125 V_008F0C_BUF_NUM_FORMAT_UINT,
2126 0, 0, 1, 1, 0);
2127 }
2128 }
2129 }
2130
2131 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2132 {
2133 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2134 struct gallivm_state *gallivm = bld_base->base.gallivm;
2135 LLVMValueRef args[2];
2136
2137 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2138 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2139 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2140 LLVMVoidTypeInContext(gallivm->context), args, 2,
2141 LLVMNoUnwindAttribute);
2142 }
2143
2144 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
2145 {
2146 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2147 struct gallivm_state *gallivm = bld_base->base.gallivm;
2148 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
2149 struct si_shader_output_values *outputs = NULL;
2150 int i,j;
2151
2152 assert(!si_shader_ctx->is_gs_copy_shader);
2153
2154 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2155
2156 /* Vertex color clamping.
2157 *
2158 * This uses a state constant loaded in a user data SGPR and
2159 * an IF statement is added that clamps all colors if the constant
2160 * is true.
2161 */
2162 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
2163 struct lp_build_if_state if_ctx;
2164 LLVMValueRef cond = NULL;
2165 LLVMValueRef addr, val;
2166
2167 for (i = 0; i < info->num_outputs; i++) {
2168 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2169 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2170 continue;
2171
2172 /* We've found a color. */
2173 if (!cond) {
2174 /* The state is in the first bit of the user SGPR. */
2175 cond = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2176 SI_PARAM_VS_STATE_BITS);
2177 cond = LLVMBuildTrunc(gallivm->builder, cond,
2178 LLVMInt1TypeInContext(gallivm->context), "");
2179 lp_build_if(&if_ctx, gallivm, cond);
2180 }
2181
2182 for (j = 0; j < 4; j++) {
2183 addr = si_shader_ctx->radeon_bld.soa.outputs[i][j];
2184 val = LLVMBuildLoad(gallivm->builder, addr, "");
2185 val = radeon_llvm_saturate(bld_base, val);
2186 LLVMBuildStore(gallivm->builder, val, addr);
2187 }
2188 }
2189
2190 if (cond)
2191 lp_build_endif(&if_ctx);
2192 }
2193
2194 for (i = 0; i < info->num_outputs; i++) {
2195 outputs[i].name = info->output_semantic_name[i];
2196 outputs[i].sid = info->output_semantic_index[i];
2197
2198 for (j = 0; j < 4; j++)
2199 outputs[i].values[j] =
2200 LLVMBuildLoad(gallivm->builder,
2201 si_shader_ctx->radeon_bld.soa.outputs[i][j],
2202 "");
2203 }
2204
2205 /* Export PrimitiveID when PS needs it. */
2206 if (si_vs_exports_prim_id(si_shader_ctx->shader)) {
2207 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2208 outputs[i].sid = 0;
2209 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2210 get_primitive_id(bld_base, 0));
2211 outputs[i].values[1] = bld_base->base.undef;
2212 outputs[i].values[2] = bld_base->base.undef;
2213 outputs[i].values[3] = bld_base->base.undef;
2214 i++;
2215 }
2216
2217 si_llvm_export_vs(bld_base, outputs, i);
2218 FREE(outputs);
2219 }
2220
2221 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2222 LLVMValueRef depth, LLVMValueRef stencil,
2223 LLVMValueRef samplemask)
2224 {
2225 struct si_screen *sscreen = si_shader_context(bld_base)->screen;
2226 struct lp_build_context *base = &bld_base->base;
2227 struct lp_build_context *uint = &bld_base->uint_bld;
2228 LLVMValueRef args[9];
2229 unsigned mask = 0;
2230
2231 assert(depth || stencil || samplemask);
2232
2233 args[1] = uint->one; /* whether the EXEC mask is valid */
2234 args[2] = uint->one; /* DONE bit */
2235
2236 /* Specify the target we are exporting */
2237 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2238
2239 args[4] = uint->zero; /* COMP flag */
2240 args[5] = base->undef; /* R, depth */
2241 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2242 args[7] = base->undef; /* B, sample mask */
2243 args[8] = base->undef; /* A, alpha to mask */
2244
2245 if (depth) {
2246 args[5] = depth;
2247 mask |= 0x1;
2248 }
2249
2250 if (stencil) {
2251 args[6] = stencil;
2252 mask |= 0x2;
2253 }
2254
2255 if (samplemask) {
2256 args[7] = samplemask;
2257 mask |= 0x4;
2258 }
2259
2260 /* SI (except OLAND) has a bug that it only looks
2261 * at the X writemask component. */
2262 if (sscreen->b.chip_class == SI &&
2263 sscreen->b.family != CHIP_OLAND)
2264 mask |= 0x1;
2265
2266 /* Specify which components to enable */
2267 args[0] = lp_build_const_int32(base->gallivm, mask);
2268
2269 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2270 LLVMVoidTypeInContext(base->gallivm->context),
2271 args, 9, 0);
2272 }
2273
2274 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2275 LLVMValueRef *color, unsigned index,
2276 bool is_last)
2277 {
2278 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2279 struct lp_build_context *base = &bld_base->base;
2280 LLVMValueRef args[9];
2281 int i;
2282
2283 /* Clamp color */
2284 if (si_shader_ctx->shader->key.ps.clamp_color)
2285 for (i = 0; i < 4; i++)
2286 color[i] = radeon_llvm_saturate(bld_base, color[i]);
2287
2288 /* Alpha to one */
2289 if (si_shader_ctx->shader->key.ps.alpha_to_one)
2290 color[3] = base->one;
2291
2292 /* Alpha test */
2293 if (index == 0 &&
2294 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
2295 si_alpha_test(bld_base, color[3]);
2296
2297 /* Line & polygon smoothing */
2298 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
2299 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3]);
2300
2301 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2302 if (index == 0 &&
2303 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
2304 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
2305 si_llvm_init_export_args(bld_base, color,
2306 V_008DFC_SQ_EXP_MRT + c, args);
2307 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2308 LLVMVoidTypeInContext(base->gallivm->context),
2309 args, 9, 0);
2310 }
2311 }
2312
2313 /* Export */
2314 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2315 args);
2316 if (is_last) {
2317 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2318 args[2] = bld_base->uint_bld.one; /* DONE bit */
2319 }
2320 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2321 LLVMVoidTypeInContext(base->gallivm->context),
2322 args, 9, 0);
2323 }
2324
2325 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2326 {
2327 struct lp_build_context *base = &bld_base->base;
2328 struct lp_build_context *uint = &bld_base->uint_bld;
2329 LLVMValueRef args[9];
2330
2331 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
2332 args[1] = uint->one; /* whether the EXEC mask is valid */
2333 args[2] = uint->one; /* DONE bit */
2334 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2335 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
2336 args[5] = uint->undef; /* R */
2337 args[6] = uint->undef; /* G */
2338 args[7] = uint->undef; /* B */
2339 args[8] = uint->undef; /* A */
2340
2341 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2342 LLVMVoidTypeInContext(base->gallivm->context),
2343 args, 9, 0);
2344 }
2345
2346 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
2347 {
2348 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
2349 struct si_shader * shader = si_shader_ctx->shader;
2350 struct lp_build_context * base = &bld_base->base;
2351 struct tgsi_shader_info *info = &shader->selector->info;
2352 LLVMBuilderRef builder = base->gallivm->builder;
2353 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2354 int last_color_export = -1;
2355 int i;
2356
2357 /* If there are no outputs, add a dummy export. */
2358 if (!info->num_outputs) {
2359 si_export_null(bld_base);
2360 return;
2361 }
2362
2363 /* Determine the last export. If MRTZ is present, it's always last.
2364 * Otherwise, find the last color export.
2365 */
2366 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask)
2367 for (i = 0; i < info->num_outputs; i++)
2368 if (info->output_semantic_name[i] == TGSI_SEMANTIC_COLOR)
2369 last_color_export = i;
2370
2371 for (i = 0; i < info->num_outputs; i++) {
2372 unsigned semantic_name = info->output_semantic_name[i];
2373 unsigned semantic_index = info->output_semantic_index[i];
2374 unsigned j;
2375 LLVMValueRef color[4] = {};
2376
2377 /* Select the correct target */
2378 switch (semantic_name) {
2379 case TGSI_SEMANTIC_POSITION:
2380 depth = LLVMBuildLoad(builder,
2381 si_shader_ctx->radeon_bld.soa.outputs[i][2], "");
2382 break;
2383 case TGSI_SEMANTIC_STENCIL:
2384 stencil = LLVMBuildLoad(builder,
2385 si_shader_ctx->radeon_bld.soa.outputs[i][1], "");
2386 break;
2387 case TGSI_SEMANTIC_SAMPLEMASK:
2388 samplemask = LLVMBuildLoad(builder,
2389 si_shader_ctx->radeon_bld.soa.outputs[i][0], "");
2390 break;
2391 case TGSI_SEMANTIC_COLOR:
2392 for (j = 0; j < 4; j++)
2393 color[j] = LLVMBuildLoad(builder,
2394 si_shader_ctx->radeon_bld.soa.outputs[i][j], "");
2395
2396 si_export_mrt_color(bld_base, color, semantic_index,
2397 last_color_export == i);
2398 break;
2399 default:
2400 fprintf(stderr,
2401 "Warning: SI unhandled fs output type:%d\n",
2402 semantic_name);
2403 }
2404 }
2405
2406 if (depth || stencil || samplemask)
2407 si_export_mrt_z(bld_base, depth, stencil, samplemask);
2408 }
2409
2410 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2411 struct lp_build_tgsi_context * bld_base,
2412 struct lp_build_emit_data * emit_data);
2413
2414 static bool tgsi_is_array_sampler(unsigned target)
2415 {
2416 return target == TGSI_TEXTURE_1D_ARRAY ||
2417 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2418 target == TGSI_TEXTURE_2D_ARRAY ||
2419 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2420 target == TGSI_TEXTURE_CUBE_ARRAY ||
2421 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2422 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2423 }
2424
2425 static void set_tex_fetch_args(struct gallivm_state *gallivm,
2426 struct lp_build_emit_data *emit_data,
2427 unsigned opcode, unsigned target,
2428 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
2429 LLVMValueRef *param, unsigned count,
2430 unsigned dmask)
2431 {
2432 unsigned num_args;
2433 unsigned is_rect = target == TGSI_TEXTURE_RECT;
2434 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2435
2436 /* Pad to power of two vector */
2437 while (count < util_next_power_of_two(count))
2438 param[count++] = LLVMGetUndef(i32);
2439
2440 /* Texture coordinates. */
2441 if (count > 1)
2442 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
2443 else
2444 emit_data->args[0] = param[0];
2445
2446 /* Resource. */
2447 emit_data->args[1] = res_ptr;
2448 num_args = 2;
2449
2450 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
2451 emit_data->dst_type = LLVMVectorType(i32, 4);
2452 else {
2453 emit_data->dst_type = LLVMVectorType(
2454 LLVMFloatTypeInContext(gallivm->context), 4);
2455
2456 emit_data->args[num_args++] = samp_ptr;
2457 }
2458
2459 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
2460 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
2461 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
2462 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
2463 tgsi_is_array_sampler(target)); /* da */
2464 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
2465 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
2466 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
2467 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
2468
2469 emit_data->arg_count = num_args;
2470 }
2471
2472 static const struct lp_build_tgsi_action tex_action;
2473
2474 static void tex_fetch_ptrs(
2475 struct lp_build_tgsi_context * bld_base,
2476 struct lp_build_emit_data * emit_data,
2477 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
2478 {
2479 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2480 struct gallivm_state *gallivm = bld_base->base.gallivm;
2481 const struct tgsi_full_instruction * inst = emit_data->inst;
2482 unsigned target = inst->Texture.Texture;
2483 unsigned sampler_src;
2484 unsigned sampler_index;
2485
2486 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
2487 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
2488
2489 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
2490 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
2491 LLVMValueRef ind_index;
2492
2493 ind_index = get_indirect_index(si_shader_ctx, &reg->Indirect, reg->Register.Index);
2494
2495 *res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
2496 *res_ptr = build_indexed_load_const(si_shader_ctx, *res_ptr, ind_index);
2497
2498 *samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
2499 *samp_ptr = build_indexed_load_const(si_shader_ctx, *samp_ptr, ind_index);
2500
2501 if (target == TGSI_TEXTURE_2D_MSAA ||
2502 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2503 ind_index = LLVMBuildAdd(gallivm->builder, ind_index,
2504 lp_build_const_int32(gallivm,
2505 SI_FMASK_TEX_OFFSET), "");
2506 *fmask_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
2507 *fmask_ptr = build_indexed_load_const(si_shader_ctx, *fmask_ptr, ind_index);
2508 }
2509 } else {
2510 *res_ptr = si_shader_ctx->sampler_views[sampler_index];
2511 *samp_ptr = si_shader_ctx->sampler_states[sampler_index];
2512 *fmask_ptr = si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + sampler_index];
2513 }
2514 }
2515
2516 static void tex_fetch_args(
2517 struct lp_build_tgsi_context * bld_base,
2518 struct lp_build_emit_data * emit_data)
2519 {
2520 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2521 struct gallivm_state *gallivm = bld_base->base.gallivm;
2522 LLVMBuilderRef builder = gallivm->builder;
2523 const struct tgsi_full_instruction * inst = emit_data->inst;
2524 unsigned opcode = inst->Instruction.Opcode;
2525 unsigned target = inst->Texture.Texture;
2526 LLVMValueRef coords[5], derivs[6];
2527 LLVMValueRef address[16];
2528 int ref_pos;
2529 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
2530 unsigned count = 0;
2531 unsigned chan;
2532 unsigned num_deriv_channels = 0;
2533 bool has_offset = inst->Texture.NumOffsets > 0;
2534 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2535 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2536 unsigned dmask = 0xf;
2537
2538 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2539
2540 if (opcode == TGSI_OPCODE_TXQ) {
2541 if (target == TGSI_TEXTURE_BUFFER) {
2542 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2543
2544 /* Read the size from the buffer descriptor directly. */
2545 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2546 LLVMValueRef size = LLVMBuildExtractElement(builder, res,
2547 lp_build_const_int32(gallivm, 6), "");
2548
2549 if (si_shader_ctx->screen->b.chip_class >= VI) {
2550 /* On VI, the descriptor contains the size in bytes,
2551 * but TXQ must return the size in elements.
2552 * The stride is always non-zero for resources using TXQ.
2553 */
2554 LLVMValueRef stride =
2555 LLVMBuildExtractElement(builder, res,
2556 lp_build_const_int32(gallivm, 5), "");
2557 stride = LLVMBuildLShr(builder, stride,
2558 lp_build_const_int32(gallivm, 16), "");
2559 stride = LLVMBuildAnd(builder, stride,
2560 lp_build_const_int32(gallivm, 0x3FFF), "");
2561
2562 size = LLVMBuildUDiv(builder, size, stride, "");
2563 }
2564
2565 emit_data->args[0] = size;
2566 return;
2567 }
2568
2569 /* Textures - set the mip level. */
2570 address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2571
2572 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2573 NULL, address, count, 0xf);
2574 return;
2575 }
2576
2577 if (target == TGSI_TEXTURE_BUFFER) {
2578 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
2579 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
2580 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
2581 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
2582
2583 /* Bitcast and truncate v8i32 to v16i8. */
2584 LLVMValueRef res = res_ptr;
2585 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
2586 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
2587 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
2588
2589 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
2590 emit_data->args[0] = res;
2591 emit_data->args[1] = bld_base->uint_bld.zero;
2592 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
2593 emit_data->arg_count = 3;
2594 return;
2595 }
2596
2597 /* Fetch and project texture coordinates */
2598 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
2599 for (chan = 0; chan < 3; chan++ ) {
2600 coords[chan] = lp_build_emit_fetch(bld_base,
2601 emit_data->inst, 0,
2602 chan);
2603 if (opcode == TGSI_OPCODE_TXP)
2604 coords[chan] = lp_build_emit_llvm_binary(bld_base,
2605 TGSI_OPCODE_DIV,
2606 coords[chan],
2607 coords[3]);
2608 }
2609
2610 if (opcode == TGSI_OPCODE_TXP)
2611 coords[3] = bld_base->base.one;
2612
2613 /* Pack offsets. */
2614 if (has_offset && opcode != TGSI_OPCODE_TXF) {
2615 /* The offsets are six-bit signed integers packed like this:
2616 * X=[5:0], Y=[13:8], and Z=[21:16].
2617 */
2618 LLVMValueRef offset[3], pack;
2619
2620 assert(inst->Texture.NumOffsets == 1);
2621
2622 for (chan = 0; chan < 3; chan++) {
2623 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
2624 emit_data->inst, 0, chan);
2625 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
2626 lp_build_const_int32(gallivm, 0x3f), "");
2627 if (chan)
2628 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
2629 lp_build_const_int32(gallivm, chan*8), "");
2630 }
2631
2632 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
2633 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
2634 address[count++] = pack;
2635 }
2636
2637 /* Pack LOD bias value */
2638 if (opcode == TGSI_OPCODE_TXB)
2639 address[count++] = coords[3];
2640 if (opcode == TGSI_OPCODE_TXB2)
2641 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2642
2643 /* Pack depth comparison value */
2644 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
2645 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2646 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2647 } else {
2648 assert(ref_pos >= 0);
2649 address[count++] = coords[ref_pos];
2650 }
2651 }
2652
2653 /* Pack user derivatives */
2654 if (opcode == TGSI_OPCODE_TXD) {
2655 int param, num_src_deriv_channels;
2656
2657 switch (target) {
2658 case TGSI_TEXTURE_3D:
2659 num_src_deriv_channels = 3;
2660 num_deriv_channels = 3;
2661 break;
2662 case TGSI_TEXTURE_2D:
2663 case TGSI_TEXTURE_SHADOW2D:
2664 case TGSI_TEXTURE_RECT:
2665 case TGSI_TEXTURE_SHADOWRECT:
2666 case TGSI_TEXTURE_2D_ARRAY:
2667 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2668 num_src_deriv_channels = 2;
2669 num_deriv_channels = 2;
2670 break;
2671 case TGSI_TEXTURE_CUBE:
2672 case TGSI_TEXTURE_SHADOWCUBE:
2673 case TGSI_TEXTURE_CUBE_ARRAY:
2674 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
2675 /* Cube derivatives will be converted to 2D. */
2676 num_src_deriv_channels = 3;
2677 num_deriv_channels = 2;
2678 break;
2679 case TGSI_TEXTURE_1D:
2680 case TGSI_TEXTURE_SHADOW1D:
2681 case TGSI_TEXTURE_1D_ARRAY:
2682 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2683 num_src_deriv_channels = 1;
2684 num_deriv_channels = 1;
2685 break;
2686 default:
2687 unreachable("invalid target");
2688 }
2689
2690 for (param = 0; param < 2; param++)
2691 for (chan = 0; chan < num_src_deriv_channels; chan++)
2692 derivs[param * num_src_deriv_channels + chan] =
2693 lp_build_emit_fetch(bld_base, inst, param+1, chan);
2694 }
2695
2696 if (target == TGSI_TEXTURE_CUBE ||
2697 target == TGSI_TEXTURE_CUBE_ARRAY ||
2698 target == TGSI_TEXTURE_SHADOWCUBE ||
2699 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2700 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
2701
2702 if (opcode == TGSI_OPCODE_TXD)
2703 for (int i = 0; i < num_deriv_channels * 2; i++)
2704 address[count++] = derivs[i];
2705
2706 /* Pack texture coordinates */
2707 address[count++] = coords[0];
2708 if (num_coords > 1)
2709 address[count++] = coords[1];
2710 if (num_coords > 2)
2711 address[count++] = coords[2];
2712
2713 /* Pack LOD or sample index */
2714 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
2715 address[count++] = coords[3];
2716 else if (opcode == TGSI_OPCODE_TXL2)
2717 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2718
2719 if (count > 16) {
2720 assert(!"Cannot handle more than 16 texture address parameters");
2721 count = 16;
2722 }
2723
2724 for (chan = 0; chan < count; chan++ ) {
2725 address[chan] = LLVMBuildBitCast(gallivm->builder,
2726 address[chan], i32, "");
2727 }
2728
2729 /* Adjust the sample index according to FMASK.
2730 *
2731 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2732 * which is the identity mapping. Each nibble says which physical sample
2733 * should be fetched to get that sample.
2734 *
2735 * For example, 0x11111100 means there are only 2 samples stored and
2736 * the second sample covers 3/4 of the pixel. When reading samples 0
2737 * and 1, return physical sample 0 (determined by the first two 0s
2738 * in FMASK), otherwise return physical sample 1.
2739 *
2740 * The sample index should be adjusted as follows:
2741 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2742 */
2743 if (target == TGSI_TEXTURE_2D_MSAA ||
2744 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2745 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2746 struct lp_build_emit_data txf_emit_data = *emit_data;
2747 LLVMValueRef txf_address[4];
2748 unsigned txf_count = count;
2749 struct tgsi_full_instruction inst = {};
2750
2751 memcpy(txf_address, address, sizeof(txf_address));
2752
2753 if (target == TGSI_TEXTURE_2D_MSAA) {
2754 txf_address[2] = bld_base->uint_bld.zero;
2755 }
2756 txf_address[3] = bld_base->uint_bld.zero;
2757
2758 /* Read FMASK using TXF. */
2759 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
2760 inst.Texture.Texture = target;
2761 txf_emit_data.inst = &inst;
2762 txf_emit_data.chan = 0;
2763 set_tex_fetch_args(gallivm, &txf_emit_data, TGSI_OPCODE_TXF,
2764 target, fmask_ptr, NULL,
2765 txf_address, txf_count, 0xf);
2766 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
2767
2768 /* Initialize some constants. */
2769 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
2770 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
2771
2772 /* Apply the formula. */
2773 LLVMValueRef fmask =
2774 LLVMBuildExtractElement(gallivm->builder,
2775 txf_emit_data.output[0],
2776 uint_bld->zero, "");
2777
2778 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
2779
2780 LLVMValueRef sample_index4 =
2781 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
2782
2783 LLVMValueRef shifted_fmask =
2784 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
2785
2786 LLVMValueRef final_sample =
2787 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
2788
2789 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2790 * resource descriptor is 0 (invalid),
2791 */
2792 LLVMValueRef fmask_desc =
2793 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
2794 LLVMVectorType(uint_bld->elem_type, 8), "");
2795
2796 LLVMValueRef fmask_word1 =
2797 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
2798 uint_bld->one, "");
2799
2800 LLVMValueRef word1_is_nonzero =
2801 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
2802 fmask_word1, uint_bld->zero, "");
2803
2804 /* Replace the MSAA sample index. */
2805 address[sample_chan] =
2806 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
2807 final_sample, address[sample_chan], "");
2808 }
2809
2810 if (opcode == TGSI_OPCODE_TXF) {
2811 /* add tex offsets */
2812 if (inst->Texture.NumOffsets) {
2813 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2814 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
2815 const struct tgsi_texture_offset * off = inst->TexOffsets;
2816
2817 assert(inst->Texture.NumOffsets == 1);
2818
2819 switch (target) {
2820 case TGSI_TEXTURE_3D:
2821 address[2] = lp_build_add(uint_bld, address[2],
2822 bld->immediates[off->Index][off->SwizzleZ]);
2823 /* fall through */
2824 case TGSI_TEXTURE_2D:
2825 case TGSI_TEXTURE_SHADOW2D:
2826 case TGSI_TEXTURE_RECT:
2827 case TGSI_TEXTURE_SHADOWRECT:
2828 case TGSI_TEXTURE_2D_ARRAY:
2829 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2830 address[1] =
2831 lp_build_add(uint_bld, address[1],
2832 bld->immediates[off->Index][off->SwizzleY]);
2833 /* fall through */
2834 case TGSI_TEXTURE_1D:
2835 case TGSI_TEXTURE_SHADOW1D:
2836 case TGSI_TEXTURE_1D_ARRAY:
2837 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2838 address[0] =
2839 lp_build_add(uint_bld, address[0],
2840 bld->immediates[off->Index][off->SwizzleX]);
2841 break;
2842 /* texture offsets do not apply to other texture targets */
2843 }
2844 }
2845 }
2846
2847 if (opcode == TGSI_OPCODE_TG4) {
2848 unsigned gather_comp = 0;
2849
2850 /* DMASK was repurposed for GATHER4. 4 components are always
2851 * returned and DMASK works like a swizzle - it selects
2852 * the component to fetch. The only valid DMASK values are
2853 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2854 * (red,red,red,red) etc.) The ISA document doesn't mention
2855 * this.
2856 */
2857
2858 /* Get the component index from src1.x for Gather4. */
2859 if (!tgsi_is_shadow_target(target)) {
2860 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
2861 LLVMValueRef comp_imm;
2862 struct tgsi_src_register src1 = inst->Src[1].Register;
2863
2864 assert(src1.File == TGSI_FILE_IMMEDIATE);
2865
2866 comp_imm = imms[src1.Index][src1.SwizzleX];
2867 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
2868 gather_comp = CLAMP(gather_comp, 0, 3);
2869 }
2870
2871 dmask = 1 << gather_comp;
2872 }
2873
2874 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2875 samp_ptr, address, count, dmask);
2876 }
2877
2878 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2879 struct lp_build_tgsi_context * bld_base,
2880 struct lp_build_emit_data * emit_data)
2881 {
2882 struct lp_build_context * base = &bld_base->base;
2883 unsigned opcode = emit_data->inst->Instruction.Opcode;
2884 unsigned target = emit_data->inst->Texture.Texture;
2885 char intr_name[127];
2886 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
2887 bool is_shadow = tgsi_is_shadow_target(target);
2888 char type[64];
2889 const char *name = "llvm.SI.image.sample";
2890 const char *infix = "";
2891
2892 if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
2893 /* Just return the buffer size. */
2894 emit_data->output[emit_data->chan] = emit_data->args[0];
2895 return;
2896 }
2897
2898 if (target == TGSI_TEXTURE_BUFFER) {
2899 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2900 base->gallivm->builder,
2901 "llvm.SI.vs.load.input", emit_data->dst_type,
2902 emit_data->args, emit_data->arg_count,
2903 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2904 return;
2905 }
2906
2907 switch (opcode) {
2908 case TGSI_OPCODE_TXF:
2909 name = target == TGSI_TEXTURE_2D_MSAA ||
2910 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
2911 "llvm.SI.image.load" :
2912 "llvm.SI.image.load.mip";
2913 is_shadow = false;
2914 has_offset = false;
2915 break;
2916 case TGSI_OPCODE_TXQ:
2917 name = "llvm.SI.getresinfo";
2918 is_shadow = false;
2919 has_offset = false;
2920 break;
2921 case TGSI_OPCODE_LODQ:
2922 name = "llvm.SI.getlod";
2923 is_shadow = false;
2924 has_offset = false;
2925 break;
2926 case TGSI_OPCODE_TEX:
2927 case TGSI_OPCODE_TEX2:
2928 case TGSI_OPCODE_TXP:
2929 break;
2930 case TGSI_OPCODE_TXB:
2931 case TGSI_OPCODE_TXB2:
2932 infix = ".b";
2933 break;
2934 case TGSI_OPCODE_TXL:
2935 case TGSI_OPCODE_TXL2:
2936 infix = ".l";
2937 break;
2938 case TGSI_OPCODE_TXD:
2939 infix = ".d";
2940 break;
2941 case TGSI_OPCODE_TG4:
2942 name = "llvm.SI.gather4";
2943 break;
2944 default:
2945 assert(0);
2946 return;
2947 }
2948
2949 if (LLVMGetTypeKind(LLVMTypeOf(emit_data->args[0])) == LLVMVectorTypeKind)
2950 sprintf(type, ".v%ui32",
2951 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2952 else
2953 strcpy(type, ".i32");
2954
2955 /* Add the type and suffixes .c, .o if needed. */
2956 sprintf(intr_name, "%s%s%s%s%s",
2957 name, is_shadow ? ".c" : "", infix,
2958 has_offset ? ".o" : "", type);
2959
2960 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2961 base->gallivm->builder, intr_name, emit_data->dst_type,
2962 emit_data->args, emit_data->arg_count,
2963 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2964
2965 /* Divide the number of layers by 6 to get the number of cubes. */
2966 if (opcode == TGSI_OPCODE_TXQ &&
2967 (target == TGSI_TEXTURE_CUBE_ARRAY ||
2968 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
2969 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2970 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2971 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2972
2973 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2974 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2975 z = LLVMBuildSDiv(builder, z, six, "");
2976
2977 emit_data->output[emit_data->chan] =
2978 LLVMBuildInsertElement(builder, v4, z, two, "");
2979 }
2980 }
2981
2982 static void si_llvm_emit_txqs(
2983 const struct lp_build_tgsi_action * action,
2984 struct lp_build_tgsi_context * bld_base,
2985 struct lp_build_emit_data * emit_data)
2986 {
2987 struct gallivm_state *gallivm = bld_base->base.gallivm;
2988 LLVMBuilderRef builder = gallivm->builder;
2989 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2990 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2991 LLVMValueRef res, samples;
2992 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2993
2994 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2995
2996
2997 /* Read the samples from the descriptor directly. */
2998 res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2999 samples = LLVMBuildExtractElement(
3000 builder, res,
3001 lp_build_const_int32(gallivm, 3), "");
3002 samples = LLVMBuildLShr(builder, samples,
3003 lp_build_const_int32(gallivm, 16), "");
3004 samples = LLVMBuildAnd(builder, samples,
3005 lp_build_const_int32(gallivm, 0xf), "");
3006 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
3007 samples, "");
3008
3009 emit_data->output[emit_data->chan] = samples;
3010 }
3011
3012 /*
3013 * SI implements derivatives using the local data store (LDS)
3014 * All writes to the LDS happen in all executing threads at
3015 * the same time. TID is the Thread ID for the current
3016 * thread and is a value between 0 and 63, representing
3017 * the thread's position in the wavefront.
3018 *
3019 * For the pixel shader threads are grouped into quads of four pixels.
3020 * The TIDs of the pixels of a quad are:
3021 *
3022 * +------+------+
3023 * |4n + 0|4n + 1|
3024 * +------+------+
3025 * |4n + 2|4n + 3|
3026 * +------+------+
3027 *
3028 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
3029 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
3030 * the current pixel's column, and masking with 0xfffffffe yields the TID
3031 * of the left pixel of the current pixel's row.
3032 *
3033 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
3034 * adding 2 yields the TID of the pixel below the top pixel.
3035 */
3036 /* masks for thread ID. */
3037 #define TID_MASK_TOP_LEFT 0xfffffffc
3038 #define TID_MASK_TOP 0xfffffffd
3039 #define TID_MASK_LEFT 0xfffffffe
3040
3041 static void si_llvm_emit_ddxy(
3042 const struct lp_build_tgsi_action * action,
3043 struct lp_build_tgsi_context * bld_base,
3044 struct lp_build_emit_data * emit_data)
3045 {
3046 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3047 struct gallivm_state *gallivm = bld_base->base.gallivm;
3048 struct lp_build_context * base = &bld_base->base;
3049 const struct tgsi_full_instruction *inst = emit_data->inst;
3050 unsigned opcode = inst->Instruction.Opcode;
3051 LLVMValueRef indices[2];
3052 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
3053 LLVMValueRef tl, trbl, result[4];
3054 LLVMTypeRef i32;
3055 unsigned swizzle[4];
3056 unsigned c;
3057 int idx;
3058 unsigned mask;
3059
3060 i32 = LLVMInt32TypeInContext(gallivm->context);
3061
3062 indices[0] = bld_base->uint_bld.zero;
3063 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
3064 NULL, 0, LLVMReadNoneAttribute);
3065 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3066 indices, 2, "");
3067
3068 if (opcode == TGSI_OPCODE_DDX_FINE)
3069 mask = TID_MASK_LEFT;
3070 else if (opcode == TGSI_OPCODE_DDY_FINE)
3071 mask = TID_MASK_TOP;
3072 else
3073 mask = TID_MASK_TOP_LEFT;
3074
3075 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
3076 lp_build_const_int32(gallivm, mask), "");
3077 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3078 indices, 2, "");
3079
3080 /* for DDX we want to next X pixel, DDY next Y pixel. */
3081 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3082 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
3083 lp_build_const_int32(gallivm, idx), "");
3084 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3085 indices, 2, "");
3086
3087 for (c = 0; c < 4; ++c) {
3088 unsigned i;
3089
3090 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
3091 for (i = 0; i < c; ++i) {
3092 if (swizzle[i] == swizzle[c]) {
3093 result[c] = result[i];
3094 break;
3095 }
3096 }
3097 if (i != c)
3098 continue;
3099
3100 LLVMBuildStore(gallivm->builder,
3101 LLVMBuildBitCast(gallivm->builder,
3102 lp_build_emit_fetch(bld_base, inst, 0, c),
3103 i32, ""),
3104 store_ptr);
3105
3106 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
3107 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3108
3109 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
3110 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
3111
3112 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
3113 }
3114
3115 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
3116 }
3117
3118 /*
3119 * this takes an I,J coordinate pair,
3120 * and works out the X and Y derivatives.
3121 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3122 */
3123 static LLVMValueRef si_llvm_emit_ddxy_interp(
3124 struct lp_build_tgsi_context *bld_base,
3125 LLVMValueRef interp_ij)
3126 {
3127 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3128 struct gallivm_state *gallivm = bld_base->base.gallivm;
3129 struct lp_build_context *base = &bld_base->base;
3130 LLVMValueRef indices[2];
3131 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
3132 LLVMValueRef tl, tr, bl, result[4];
3133 LLVMTypeRef i32;
3134 unsigned c;
3135
3136 i32 = LLVMInt32TypeInContext(gallivm->context);
3137
3138 indices[0] = bld_base->uint_bld.zero;
3139 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
3140 NULL, 0, LLVMReadNoneAttribute);
3141 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3142 indices, 2, "");
3143
3144 temp = LLVMBuildAnd(gallivm->builder, indices[1],
3145 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
3146
3147 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
3148 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
3149
3150 indices[1] = temp;
3151 load_ptr_x = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3152 indices, 2, "");
3153
3154 indices[1] = temp2;
3155 load_ptr_y = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3156 indices, 2, "");
3157
3158 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
3159 lp_build_const_int32(gallivm, 1), "");
3160 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3161 indices, 2, "");
3162
3163 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
3164 lp_build_const_int32(gallivm, 2), "");
3165 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3166 indices, 2, "");
3167
3168 for (c = 0; c < 2; ++c) {
3169 LLVMValueRef store_val;
3170 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
3171
3172 store_val = LLVMBuildExtractElement(gallivm->builder,
3173 interp_ij, c_ll, "");
3174 LLVMBuildStore(gallivm->builder,
3175 store_val,
3176 store_ptr);
3177
3178 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
3179 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3180
3181 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
3182 tr = LLVMBuildBitCast(gallivm->builder, tr, base->elem_type, "");
3183
3184 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
3185
3186 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
3187 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3188
3189 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
3190 bl = LLVMBuildBitCast(gallivm->builder, bl, base->elem_type, "");
3191
3192 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
3193 }
3194
3195 return lp_build_gather_values(gallivm, result, 4);
3196 }
3197
3198 static void interp_fetch_args(
3199 struct lp_build_tgsi_context *bld_base,
3200 struct lp_build_emit_data *emit_data)
3201 {
3202 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3203 struct gallivm_state *gallivm = bld_base->base.gallivm;
3204 const struct tgsi_full_instruction *inst = emit_data->inst;
3205
3206 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3207 /* offset is in second src, first two channels */
3208 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3209 emit_data->inst, 1,
3210 TGSI_CHAN_X);
3211 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3212 emit_data->inst, 1,
3213 TGSI_CHAN_Y);
3214 emit_data->arg_count = 2;
3215 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3216 LLVMValueRef sample_position;
3217 LLVMValueRef sample_id;
3218 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
3219
3220 /* fetch sample ID, then fetch its sample position,
3221 * and place into first two channels.
3222 */
3223 sample_id = lp_build_emit_fetch(bld_base,
3224 emit_data->inst, 1, TGSI_CHAN_X);
3225 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
3226 LLVMInt32TypeInContext(gallivm->context),
3227 "");
3228 sample_position = load_sample_position(&si_shader_ctx->radeon_bld, sample_id);
3229
3230 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
3231 sample_position,
3232 lp_build_const_int32(gallivm, 0), "");
3233
3234 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
3235 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
3236 sample_position,
3237 lp_build_const_int32(gallivm, 1), "");
3238 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
3239 emit_data->arg_count = 2;
3240 }
3241 }
3242
3243 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3244 struct lp_build_tgsi_context *bld_base,
3245 struct lp_build_emit_data *emit_data)
3246 {
3247 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3248 struct si_shader *shader = si_shader_ctx->shader;
3249 struct gallivm_state *gallivm = bld_base->base.gallivm;
3250 LLVMValueRef interp_param;
3251 const struct tgsi_full_instruction *inst = emit_data->inst;
3252 const char *intr_name;
3253 int input_index = inst->Src[0].Register.Index;
3254 int chan;
3255 int i;
3256 LLVMValueRef attr_number;
3257 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
3258 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
3259 int interp_param_idx;
3260 unsigned interp = shader->selector->info.input_interpolate[input_index];
3261 unsigned location;
3262
3263 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
3264
3265 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3266 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3267 location = TGSI_INTERPOLATE_LOC_CENTER;
3268 else
3269 location = TGSI_INTERPOLATE_LOC_CENTROID;
3270
3271 interp_param_idx = lookup_interp_param_index(interp, location);
3272 if (interp_param_idx == -1)
3273 return;
3274 else if (interp_param_idx)
3275 interp_param = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, interp_param_idx);
3276 else
3277 interp_param = NULL;
3278
3279 attr_number = lp_build_const_int32(gallivm, input_index);
3280
3281 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3282 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3283 LLVMValueRef ij_out[2];
3284 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3285
3286 /*
3287 * take the I then J parameters, and the DDX/Y for it, and
3288 * calculate the IJ inputs for the interpolator.
3289 * temp1 = ddx * offset/sample.x + I;
3290 * interp_param.I = ddy * offset/sample.y + temp1;
3291 * temp1 = ddx * offset/sample.x + J;
3292 * interp_param.J = ddy * offset/sample.y + temp1;
3293 */
3294 for (i = 0; i < 2; i++) {
3295 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
3296 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
3297 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
3298 ddxy_out, ix_ll, "");
3299 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
3300 ddxy_out, iy_ll, "");
3301 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
3302 interp_param, ix_ll, "");
3303 LLVMValueRef temp1, temp2;
3304
3305 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
3306 LLVMFloatTypeInContext(gallivm->context), "");
3307
3308 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
3309
3310 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
3311
3312 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
3313
3314 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
3315
3316 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
3317 temp2,
3318 LLVMIntTypeInContext(gallivm->context, 32), "");
3319 }
3320 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
3321 }
3322
3323 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3324 for (chan = 0; chan < 2; chan++) {
3325 LLVMValueRef args[4];
3326 LLVMValueRef llvm_chan;
3327 unsigned schan;
3328
3329 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3330 llvm_chan = lp_build_const_int32(gallivm, schan);
3331
3332 args[0] = llvm_chan;
3333 args[1] = attr_number;
3334 args[2] = params;
3335 args[3] = interp_param;
3336
3337 emit_data->output[chan] =
3338 lp_build_intrinsic(gallivm->builder, intr_name,
3339 input_type, args, args[3] ? 4 : 3,
3340 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3341 }
3342 }
3343
3344 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
3345 struct lp_build_emit_data *emit_data)
3346 {
3347 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3348 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
3349 unsigned stream;
3350
3351 assert(src0.File == TGSI_FILE_IMMEDIATE);
3352
3353 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
3354 return stream;
3355 }
3356
3357 /* Emit one vertex from the geometry shader */
3358 static void si_llvm_emit_vertex(
3359 const struct lp_build_tgsi_action *action,
3360 struct lp_build_tgsi_context *bld_base,
3361 struct lp_build_emit_data *emit_data)
3362 {
3363 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3364 struct lp_build_context *uint = &bld_base->uint_bld;
3365 struct si_shader *shader = si_shader_ctx->shader;
3366 struct tgsi_shader_info *info = &shader->selector->info;
3367 struct gallivm_state *gallivm = bld_base->base.gallivm;
3368 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
3369 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3370 SI_PARAM_GS2VS_OFFSET);
3371 LLVMValueRef gs_next_vertex;
3372 LLVMValueRef can_emit, kill;
3373 LLVMValueRef args[2];
3374 unsigned chan;
3375 int i;
3376 unsigned stream;
3377
3378 stream = si_llvm_get_stream(bld_base, emit_data);
3379
3380 /* Write vertex attribute values to GSVS ring */
3381 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
3382 si_shader_ctx->gs_next_vertex[stream],
3383 "");
3384
3385 /* If this thread has already emitted the declared maximum number of
3386 * vertices, kill it: excessive vertex emissions are not supposed to
3387 * have any effect, and GS threads have no externally observable
3388 * effects other than emitting vertices.
3389 */
3390 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
3391 lp_build_const_int32(gallivm,
3392 shader->selector->gs_max_out_vertices), "");
3393 kill = lp_build_select(&bld_base->base, can_emit,
3394 lp_build_const_float(gallivm, 1.0f),
3395 lp_build_const_float(gallivm, -1.0f));
3396
3397 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
3398 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
3399
3400 for (i = 0; i < info->num_outputs; i++) {
3401 LLVMValueRef *out_ptr =
3402 si_shader_ctx->radeon_bld.soa.outputs[i];
3403
3404 for (chan = 0; chan < 4; chan++) {
3405 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3406 LLVMValueRef voffset =
3407 lp_build_const_int32(gallivm, (i * 4 + chan) *
3408 shader->selector->gs_max_out_vertices);
3409
3410 voffset = lp_build_add(uint, voffset, gs_next_vertex);
3411 voffset = lp_build_mul_imm(uint, voffset, 4);
3412
3413 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
3414
3415 build_tbuffer_store(si_shader_ctx,
3416 si_shader_ctx->gsvs_ring[stream],
3417 out_val, 1,
3418 voffset, soffset, 0,
3419 V_008F0C_BUF_DATA_FORMAT_32,
3420 V_008F0C_BUF_NUM_FORMAT_UINT,
3421 1, 0, 1, 1, 0);
3422 }
3423 }
3424 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
3425 lp_build_const_int32(gallivm, 1));
3426
3427 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex[stream]);
3428
3429 /* Signal vertex emission */
3430 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
3431 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3432 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3433 LLVMVoidTypeInContext(gallivm->context), args, 2,
3434 LLVMNoUnwindAttribute);
3435 }
3436
3437 /* Cut one primitive from the geometry shader */
3438 static void si_llvm_emit_primitive(
3439 const struct lp_build_tgsi_action *action,
3440 struct lp_build_tgsi_context *bld_base,
3441 struct lp_build_emit_data *emit_data)
3442 {
3443 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3444 struct gallivm_state *gallivm = bld_base->base.gallivm;
3445 LLVMValueRef args[2];
3446 unsigned stream;
3447
3448 /* Signal primitive cut */
3449 stream = si_llvm_get_stream(bld_base, emit_data);
3450 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
3451 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3452 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3453 LLVMVoidTypeInContext(gallivm->context), args, 2,
3454 LLVMNoUnwindAttribute);
3455 }
3456
3457 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
3458 struct lp_build_tgsi_context *bld_base,
3459 struct lp_build_emit_data *emit_data)
3460 {
3461 struct gallivm_state *gallivm = bld_base->base.gallivm;
3462
3463 lp_build_intrinsic(gallivm->builder,
3464 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
3465 : "llvm.AMDGPU.barrier.local",
3466 LLVMVoidTypeInContext(gallivm->context), NULL, 0,
3467 LLVMNoUnwindAttribute);
3468 }
3469
3470 static const struct lp_build_tgsi_action tex_action = {
3471 .fetch_args = tex_fetch_args,
3472 .emit = build_tex_intrinsic,
3473 };
3474
3475 static const struct lp_build_tgsi_action interp_action = {
3476 .fetch_args = interp_fetch_args,
3477 .emit = build_interp_intrinsic,
3478 };
3479
3480 static void create_meta_data(struct si_shader_context *si_shader_ctx)
3481 {
3482 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3483 LLVMValueRef args[3];
3484
3485 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
3486 args[1] = 0;
3487 args[2] = lp_build_const_int32(gallivm, 1);
3488
3489 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
3490 }
3491
3492 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3493 {
3494 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3495 CONST_ADDR_SPACE);
3496 }
3497
3498 static void declare_streamout_params(struct si_shader_context *si_shader_ctx,
3499 struct pipe_stream_output_info *so,
3500 LLVMTypeRef *params, LLVMTypeRef i32,
3501 unsigned *num_params)
3502 {
3503 int i;
3504
3505 /* Streamout SGPRs. */
3506 if (so->num_outputs) {
3507 params[si_shader_ctx->param_streamout_config = (*num_params)++] = i32;
3508 params[si_shader_ctx->param_streamout_write_index = (*num_params)++] = i32;
3509 }
3510 /* A streamout buffer offset is loaded if the stride is non-zero. */
3511 for (i = 0; i < 4; i++) {
3512 if (!so->stride[i])
3513 continue;
3514
3515 params[si_shader_ctx->param_streamout_offset[i] = (*num_params)++] = i32;
3516 }
3517 }
3518
3519 static void create_function(struct si_shader_context *si_shader_ctx)
3520 {
3521 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3522 struct gallivm_state *gallivm = bld_base->base.gallivm;
3523 struct si_shader *shader = si_shader_ctx->shader;
3524 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
3525 unsigned i, last_array_pointer, last_sgpr, num_params;
3526
3527 i8 = LLVMInt8TypeInContext(gallivm->context);
3528 i32 = LLVMInt32TypeInContext(gallivm->context);
3529 f32 = LLVMFloatTypeInContext(gallivm->context);
3530 v2i32 = LLVMVectorType(i32, 2);
3531 v3i32 = LLVMVectorType(i32, 3);
3532 v4i32 = LLVMVectorType(i32, 4);
3533 v8i32 = LLVMVectorType(i32, 8);
3534 v16i8 = LLVMVectorType(i8, 16);
3535
3536 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
3537 params[SI_PARAM_CONST_BUFFERS] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
3538 params[SI_PARAM_SAMPLER_STATES] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
3539 params[SI_PARAM_SAMPLER_VIEWS] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
3540 last_array_pointer = SI_PARAM_SAMPLER_VIEWS;
3541
3542 switch (si_shader_ctx->type) {
3543 case TGSI_PROCESSOR_VERTEX:
3544 params[SI_PARAM_VERTEX_BUFFERS] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
3545 last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
3546 params[SI_PARAM_BASE_VERTEX] = i32;
3547 params[SI_PARAM_START_INSTANCE] = i32;
3548 num_params = SI_PARAM_START_INSTANCE+1;
3549
3550 if (shader->key.vs.as_es) {
3551 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3552 } else if (shader->key.vs.as_ls) {
3553 params[SI_PARAM_LS_OUT_LAYOUT] = i32;
3554 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
3555 } else {
3556 if (si_shader_ctx->is_gs_copy_shader) {
3557 last_array_pointer = SI_PARAM_CONST_BUFFERS;
3558 num_params = SI_PARAM_CONST_BUFFERS+1;
3559 } else {
3560 params[SI_PARAM_VS_STATE_BITS] = i32;
3561 num_params = SI_PARAM_VS_STATE_BITS+1;
3562 }
3563
3564 /* The locations of the other parameters are assigned dynamically. */
3565 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3566 params, i32, &num_params);
3567 }
3568
3569 last_sgpr = num_params-1;
3570
3571 /* VGPRs */
3572 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
3573 params[si_shader_ctx->param_rel_auto_id = num_params++] = i32;
3574 params[si_shader_ctx->param_vs_prim_id = num_params++] = i32;
3575 params[si_shader_ctx->param_instance_id = num_params++] = i32;
3576 break;
3577
3578 case TGSI_PROCESSOR_TESS_CTRL:
3579 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3580 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3581 params[SI_PARAM_TCS_IN_LAYOUT] = i32;
3582 params[SI_PARAM_TESS_FACTOR_OFFSET] = i32;
3583 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
3584
3585 /* VGPRs */
3586 params[SI_PARAM_PATCH_ID] = i32;
3587 params[SI_PARAM_REL_IDS] = i32;
3588 num_params = SI_PARAM_REL_IDS+1;
3589 break;
3590
3591 case TGSI_PROCESSOR_TESS_EVAL:
3592 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3593 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3594 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
3595
3596 if (shader->key.tes.as_es) {
3597 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3598 } else {
3599 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3600 params, i32, &num_params);
3601 }
3602 last_sgpr = num_params - 1;
3603
3604 /* VGPRs */
3605 params[si_shader_ctx->param_tes_u = num_params++] = f32;
3606 params[si_shader_ctx->param_tes_v = num_params++] = f32;
3607 params[si_shader_ctx->param_tes_rel_patch_id = num_params++] = i32;
3608 params[si_shader_ctx->param_tes_patch_id = num_params++] = i32;
3609 break;
3610
3611 case TGSI_PROCESSOR_GEOMETRY:
3612 params[SI_PARAM_GS2VS_OFFSET] = i32;
3613 params[SI_PARAM_GS_WAVE_ID] = i32;
3614 last_sgpr = SI_PARAM_GS_WAVE_ID;
3615
3616 /* VGPRs */
3617 params[SI_PARAM_VTX0_OFFSET] = i32;
3618 params[SI_PARAM_VTX1_OFFSET] = i32;
3619 params[SI_PARAM_PRIMITIVE_ID] = i32;
3620 params[SI_PARAM_VTX2_OFFSET] = i32;
3621 params[SI_PARAM_VTX3_OFFSET] = i32;
3622 params[SI_PARAM_VTX4_OFFSET] = i32;
3623 params[SI_PARAM_VTX5_OFFSET] = i32;
3624 params[SI_PARAM_GS_INSTANCE_ID] = i32;
3625 num_params = SI_PARAM_GS_INSTANCE_ID+1;
3626 break;
3627
3628 case TGSI_PROCESSOR_FRAGMENT:
3629 params[SI_PARAM_ALPHA_REF] = f32;
3630 params[SI_PARAM_PRIM_MASK] = i32;
3631 last_sgpr = SI_PARAM_PRIM_MASK;
3632 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
3633 params[SI_PARAM_PERSP_CENTER] = v2i32;
3634 params[SI_PARAM_PERSP_CENTROID] = v2i32;
3635 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
3636 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
3637 params[SI_PARAM_LINEAR_CENTER] = v2i32;
3638 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
3639 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
3640 params[SI_PARAM_POS_X_FLOAT] = f32;
3641 params[SI_PARAM_POS_Y_FLOAT] = f32;
3642 params[SI_PARAM_POS_Z_FLOAT] = f32;
3643 params[SI_PARAM_POS_W_FLOAT] = f32;
3644 params[SI_PARAM_FRONT_FACE] = i32;
3645 params[SI_PARAM_ANCILLARY] = i32;
3646 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
3647 params[SI_PARAM_POS_FIXED_PT] = f32;
3648 num_params = SI_PARAM_POS_FIXED_PT+1;
3649 break;
3650
3651 default:
3652 assert(0 && "unimplemented shader");
3653 return;
3654 }
3655
3656 assert(num_params <= Elements(params));
3657 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
3658 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
3659
3660 if (shader->dx10_clamp_mode)
3661 LLVMAddTargetDependentFunctionAttr(si_shader_ctx->radeon_bld.main_fn,
3662 "enable-no-nans-fp-math", "true");
3663
3664 for (i = 0; i <= last_sgpr; ++i) {
3665 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
3666
3667 /* We tell llvm that array inputs are passed by value to allow Sinking pass
3668 * to move load. Inputs are constant so this is fine. */
3669 if (i <= last_array_pointer)
3670 LLVMAddAttribute(P, LLVMByValAttribute);
3671 else
3672 LLVMAddAttribute(P, LLVMInRegAttribute);
3673 }
3674
3675 if (bld_base->info &&
3676 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
3677 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
3678 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
3679 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
3680 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
3681 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
3682 si_shader_ctx->lds =
3683 LLVMAddGlobalInAddressSpace(gallivm->module,
3684 LLVMArrayType(i32, 64),
3685 "ddxy_lds",
3686 LOCAL_ADDR_SPACE);
3687
3688 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
3689 si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
3690 si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL) {
3691 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
3692 unsigned vertex_data_dw_size = 32*32*4;
3693 unsigned patch_data_dw_size = 32*4;
3694 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
3695 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
3696 unsigned lds_dwords = patch_dw_size;
3697
3698 /* The actual size is computed outside of the shader to reduce
3699 * the number of shader variants. */
3700 si_shader_ctx->lds =
3701 LLVMAddGlobalInAddressSpace(gallivm->module,
3702 LLVMArrayType(i32, lds_dwords),
3703 "tess_lds",
3704 LOCAL_ADDR_SPACE);
3705 }
3706 }
3707
3708 static void preload_constants(struct si_shader_context *si_shader_ctx)
3709 {
3710 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3711 struct gallivm_state * gallivm = bld_base->base.gallivm;
3712 const struct tgsi_shader_info * info = bld_base->info;
3713 unsigned buf;
3714 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
3715
3716 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
3717 unsigned i, num_const = info->const_file_max[buf] + 1;
3718
3719 if (num_const == 0)
3720 continue;
3721
3722 /* Allocate space for the constant values */
3723 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
3724
3725 /* Load the resource descriptor */
3726 si_shader_ctx->const_buffers[buf] =
3727 build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
3728
3729 /* Load the constants, we rely on the code sinking to do the rest */
3730 for (i = 0; i < num_const * 4; ++i) {
3731 si_shader_ctx->constants[buf][i] =
3732 buffer_load_const(gallivm->builder,
3733 si_shader_ctx->const_buffers[buf],
3734 lp_build_const_int32(gallivm, i * 4),
3735 bld_base->base.elem_type);
3736 }
3737 }
3738 }
3739
3740 static void preload_samplers(struct si_shader_context *si_shader_ctx)
3741 {
3742 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3743 struct gallivm_state * gallivm = bld_base->base.gallivm;
3744 const struct tgsi_shader_info * info = bld_base->info;
3745
3746 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
3747
3748 LLVMValueRef res_ptr, samp_ptr;
3749 LLVMValueRef offset;
3750
3751 if (num_samplers == 0)
3752 return;
3753
3754 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
3755 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
3756
3757 /* Load the resources and samplers, we rely on the code sinking to do the rest */
3758 for (i = 0; i < num_samplers; ++i) {
3759 /* Resource */
3760 offset = lp_build_const_int32(gallivm, i);
3761 si_shader_ctx->sampler_views[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3762
3763 /* Sampler */
3764 offset = lp_build_const_int32(gallivm, i);
3765 si_shader_ctx->sampler_states[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
3766
3767 /* FMASK resource */
3768 if (info->is_msaa_sampler[i]) {
3769 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
3770 si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + i] =
3771 build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3772 }
3773 }
3774 }
3775
3776 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
3777 {
3778 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3779 struct gallivm_state * gallivm = bld_base->base.gallivm;
3780 unsigned i;
3781
3782 /* Streamout can only be used if the shader is compiled as VS. */
3783 if (!si_shader_ctx->shader->selector->so.num_outputs ||
3784 (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3785 (si_shader_ctx->shader->key.vs.as_es ||
3786 si_shader_ctx->shader->key.vs.as_ls)) ||
3787 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3788 si_shader_ctx->shader->key.tes.as_es))
3789 return;
3790
3791 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3792 SI_PARAM_RW_BUFFERS);
3793
3794 /* Load the resources, we rely on the code sinking to do the rest */
3795 for (i = 0; i < 4; ++i) {
3796 if (si_shader_ctx->shader->selector->so.stride[i]) {
3797 LLVMValueRef offset = lp_build_const_int32(gallivm,
3798 SI_SO_BUF_OFFSET + i);
3799
3800 si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3801 }
3802 }
3803 }
3804
3805 /**
3806 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
3807 * for later use.
3808 */
3809 static void preload_ring_buffers(struct si_shader_context *si_shader_ctx)
3810 {
3811 struct gallivm_state *gallivm =
3812 si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3813
3814 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3815 SI_PARAM_RW_BUFFERS);
3816
3817 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3818 si_shader_ctx->shader->key.vs.as_es) ||
3819 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3820 si_shader_ctx->shader->key.tes.as_es) ||
3821 si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3822 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
3823
3824 si_shader_ctx->esgs_ring =
3825 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3826 }
3827
3828 if (si_shader_ctx->is_gs_copy_shader) {
3829 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
3830
3831 si_shader_ctx->gsvs_ring[0] =
3832 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3833 }
3834 if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3835 int i;
3836 for (i = 0; i < 4; i++) {
3837 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i);
3838
3839 si_shader_ctx->gsvs_ring[i] =
3840 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3841 }
3842 }
3843 }
3844
3845 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
3846 struct si_shader_config *conf,
3847 unsigned symbol_offset)
3848 {
3849 unsigned i;
3850 const unsigned char *config =
3851 radeon_shader_binary_config_start(binary, symbol_offset);
3852
3853 /* XXX: We may be able to emit some of these values directly rather than
3854 * extracting fields to be emitted later.
3855 */
3856
3857 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
3858 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
3859 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
3860 switch (reg) {
3861 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
3862 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
3863 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
3864 case R_00B848_COMPUTE_PGM_RSRC1:
3865 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
3866 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
3867 conf->float_mode = G_00B028_FLOAT_MODE(value);
3868 conf->rsrc1 = value;
3869 break;
3870 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
3871 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
3872 break;
3873 case R_00B84C_COMPUTE_PGM_RSRC2:
3874 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
3875 conf->rsrc2 = value;
3876 break;
3877 case R_0286CC_SPI_PS_INPUT_ENA:
3878 conf->spi_ps_input_ena = value;
3879 break;
3880 case R_0286D0_SPI_PS_INPUT_ADDR:
3881 /* Not used yet, but will be in the future */
3882 break;
3883 case R_0286E8_SPI_TMPRING_SIZE:
3884 case R_00B860_COMPUTE_TMPRING_SIZE:
3885 /* WAVESIZE is in units of 256 dwords. */
3886 conf->scratch_bytes_per_wave =
3887 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
3888 break;
3889 default:
3890 {
3891 static bool printed;
3892
3893 if (!printed) {
3894 fprintf(stderr, "Warning: LLVM emitted unknown "
3895 "config register: 0x%x\n", reg);
3896 printed = true;
3897 }
3898 }
3899 break;
3900 }
3901 }
3902 }
3903
3904 void si_shader_apply_scratch_relocs(struct si_context *sctx,
3905 struct si_shader *shader,
3906 uint64_t scratch_va)
3907 {
3908 unsigned i;
3909 uint32_t scratch_rsrc_dword0 = scratch_va;
3910 uint32_t scratch_rsrc_dword1 =
3911 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
3912 | S_008F04_STRIDE(shader->config.scratch_bytes_per_wave / 64);
3913
3914 for (i = 0 ; i < shader->binary.reloc_count; i++) {
3915 const struct radeon_shader_reloc *reloc =
3916 &shader->binary.relocs[i];
3917 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
3918 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3919 &scratch_rsrc_dword0, 4);
3920 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
3921 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3922 &scratch_rsrc_dword1, 4);
3923 }
3924 }
3925 }
3926
3927 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
3928 {
3929 const struct radeon_shader_binary *binary = &shader->binary;
3930 unsigned code_size = binary->code_size + binary->rodata_size;
3931 unsigned char *ptr;
3932
3933 r600_resource_reference(&shader->bo, NULL);
3934 shader->bo = si_resource_create_custom(&sscreen->b.b,
3935 PIPE_USAGE_IMMUTABLE,
3936 code_size);
3937 if (!shader->bo)
3938 return -ENOMEM;
3939
3940 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
3941 PIPE_TRANSFER_READ_WRITE);
3942 util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
3943 if (binary->rodata_size > 0) {
3944 ptr += binary->code_size;
3945 util_memcpy_cpu_to_le32(ptr, binary->rodata,
3946 binary->rodata_size);
3947 }
3948
3949 sscreen->b.ws->buffer_unmap(shader->bo->buf);
3950 return 0;
3951 }
3952
3953 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
3954 struct pipe_debug_callback *debug)
3955 {
3956 char *line, *p;
3957 unsigned i, count;
3958
3959 if (binary->disasm_string) {
3960 fprintf(stderr, "\nShader Disassembly:\n\n");
3961 fprintf(stderr, "%s\n", binary->disasm_string);
3962
3963 if (debug && debug->debug_message) {
3964 /* Very long debug messages are cut off, so send the
3965 * disassembly one line at a time. This causes more
3966 * overhead, but on the plus side it simplifies
3967 * parsing of resulting logs.
3968 */
3969 pipe_debug_message(debug, SHADER_INFO,
3970 "Shader Disassembly Begin");
3971
3972 line = binary->disasm_string;
3973 while (*line) {
3974 p = strchrnul(line, '\n');
3975 count = p - line;
3976
3977 if (count) {
3978 pipe_debug_message(debug, SHADER_INFO,
3979 "%.*s", count, line);
3980 }
3981
3982 if (!*p)
3983 break;
3984 line = p + 1;
3985 }
3986
3987 pipe_debug_message(debug, SHADER_INFO,
3988 "Shader Disassembly End");
3989 }
3990 } else {
3991 fprintf(stderr, "SI CODE:\n");
3992 for (i = 0; i < binary->code_size; i += 4) {
3993 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i,
3994 binary->code[i + 3], binary->code[i + 2],
3995 binary->code[i + 1], binary->code[i]);
3996 }
3997 }
3998 }
3999
4000 static void si_shader_dump_stats(struct si_screen *sscreen,
4001 struct si_shader_config *conf,
4002 unsigned num_inputs,
4003 unsigned code_size,
4004 struct pipe_debug_callback *debug,
4005 unsigned processor)
4006 {
4007 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
4008 unsigned lds_per_wave = 0;
4009 unsigned max_simd_waves = 10;
4010
4011 /* Compute LDS usage for PS. */
4012 if (processor == TGSI_PROCESSOR_FRAGMENT) {
4013 /* The minimum usage per wave is (num_inputs * 36). The maximum
4014 * usage is (num_inputs * 36 * 16).
4015 * We can get anything in between and it varies between waves.
4016 *
4017 * Other stages don't know the size at compile time or don't
4018 * allocate LDS per wave, but instead they do it per thread group.
4019 */
4020 lds_per_wave = conf->lds_size * lds_increment +
4021 align(num_inputs * 36, lds_increment);
4022 }
4023
4024 /* Compute the per-SIMD wave counts. */
4025 if (conf->num_sgprs) {
4026 if (sscreen->b.chip_class >= VI)
4027 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
4028 else
4029 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
4030 }
4031
4032 if (conf->num_vgprs)
4033 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
4034
4035 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
4036 * that PS can use.
4037 */
4038 if (lds_per_wave)
4039 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
4040
4041 if (r600_can_dump_shader(&sscreen->b, processor)) {
4042 fprintf(stderr, "*** SHADER STATS ***\n"
4043 "SGPRS: %d\n"
4044 "VGPRS: %d\n"
4045 "Code Size: %d bytes\n"
4046 "LDS: %d blocks\n"
4047 "Scratch: %d bytes per wave\n"
4048 "Max Waves: %d\n"
4049 "********************\n",
4050 conf->num_sgprs, conf->num_vgprs, code_size,
4051 conf->lds_size, conf->scratch_bytes_per_wave,
4052 max_simd_waves);
4053 }
4054
4055 pipe_debug_message(debug, SHADER_INFO,
4056 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
4057 "LDS: %d Scratch: %d Max Waves: %d",
4058 conf->num_sgprs, conf->num_vgprs, code_size,
4059 conf->lds_size, conf->scratch_bytes_per_wave,
4060 max_simd_waves);
4061 }
4062
4063 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
4064 struct pipe_debug_callback *debug, unsigned processor)
4065 {
4066 if (r600_can_dump_shader(&sscreen->b, processor))
4067 if (!(sscreen->b.debug_flags & DBG_NO_ASM))
4068 si_shader_dump_disassembly(&shader->binary, debug);
4069
4070 si_shader_dump_stats(sscreen, &shader->config,
4071 shader->selector ? shader->selector->info.num_inputs : 0,
4072 shader->binary.code_size, debug, processor);
4073 }
4074
4075 int si_compile_llvm(struct si_screen *sscreen,
4076 struct radeon_shader_binary *binary,
4077 struct si_shader_config *conf,
4078 LLVMTargetMachineRef tm,
4079 LLVMModuleRef mod,
4080 struct pipe_debug_callback *debug,
4081 unsigned processor)
4082 {
4083 int r = 0;
4084 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
4085
4086 if (r600_can_dump_shader(&sscreen->b, processor)) {
4087 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
4088
4089 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR)))
4090 LLVMDumpModule(mod);
4091 }
4092
4093 if (!si_replace_shader(count, binary)) {
4094 r = radeon_llvm_compile(mod, binary,
4095 r600_get_llvm_processor_name(sscreen->b.family), tm,
4096 debug);
4097 if (r)
4098 return r;
4099 }
4100
4101 si_shader_binary_read_config(binary, conf, 0);
4102
4103 FREE(binary->config);
4104 FREE(binary->global_symbol_offsets);
4105 binary->config = NULL;
4106 binary->global_symbol_offsets = NULL;
4107 return r;
4108 }
4109
4110 /* Generate code for the hardware VS shader stage to go with a geometry shader */
4111 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
4112 struct si_shader_context *si_shader_ctx,
4113 struct si_shader *gs, bool dump,
4114 struct pipe_debug_callback *debug)
4115 {
4116 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
4117 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
4118 struct lp_build_context *base = &bld_base->base;
4119 struct lp_build_context *uint = &bld_base->uint_bld;
4120 struct si_shader_output_values *outputs;
4121 struct tgsi_shader_info *gsinfo = &gs->selector->info;
4122 LLVMValueRef args[9];
4123 int i, r;
4124
4125 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
4126
4127 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
4128 si_shader_ctx->is_gs_copy_shader = true;
4129
4130 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
4131
4132 create_meta_data(si_shader_ctx);
4133 create_function(si_shader_ctx);
4134 preload_streamout_buffers(si_shader_ctx);
4135 preload_ring_buffers(si_shader_ctx);
4136
4137 args[0] = si_shader_ctx->gsvs_ring[0];
4138 args[1] = lp_build_mul_imm(uint,
4139 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
4140 si_shader_ctx->param_vertex_id),
4141 4);
4142 args[3] = uint->zero;
4143 args[4] = uint->one; /* OFFEN */
4144 args[5] = uint->zero; /* IDXEN */
4145 args[6] = uint->one; /* GLC */
4146 args[7] = uint->one; /* SLC */
4147 args[8] = uint->zero; /* TFE */
4148
4149 /* Fetch vertex data from GSVS ring */
4150 for (i = 0; i < gsinfo->num_outputs; ++i) {
4151 unsigned chan;
4152
4153 outputs[i].name = gsinfo->output_semantic_name[i];
4154 outputs[i].sid = gsinfo->output_semantic_index[i];
4155
4156 for (chan = 0; chan < 4; chan++) {
4157 args[2] = lp_build_const_int32(gallivm,
4158 (i * 4 + chan) *
4159 gs->selector->gs_max_out_vertices * 16 * 4);
4160
4161 outputs[i].values[chan] =
4162 LLVMBuildBitCast(gallivm->builder,
4163 lp_build_intrinsic(gallivm->builder,
4164 "llvm.SI.buffer.load.dword.i32.i32",
4165 LLVMInt32TypeInContext(gallivm->context),
4166 args, 9,
4167 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
4168 base->elem_type, "");
4169 }
4170 }
4171
4172 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
4173
4174 LLVMBuildRetVoid(bld_base->base.gallivm->builder);
4175
4176 /* Dump LLVM IR before any optimization passes */
4177 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
4178 r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
4179 LLVMDumpModule(bld_base->base.gallivm->module);
4180
4181 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
4182
4183 if (dump)
4184 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
4185
4186 r = si_compile_llvm(sscreen, &si_shader_ctx->shader->binary,
4187 &si_shader_ctx->shader->config, si_shader_ctx->tm,
4188 bld_base->base.gallivm->module,
4189 debug, TGSI_PROCESSOR_GEOMETRY);
4190 if (!r) {
4191 si_shader_dump(sscreen, si_shader_ctx->shader, debug,
4192 TGSI_PROCESSOR_GEOMETRY);
4193 r = si_shader_binary_upload(sscreen, si_shader_ctx->shader);
4194 }
4195
4196 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
4197
4198 FREE(outputs);
4199 return r;
4200 }
4201
4202 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
4203 {
4204 int i;
4205
4206 fprintf(f, "SHADER KEY\n");
4207
4208 switch (shader) {
4209 case PIPE_SHADER_VERTEX:
4210 fprintf(f, " instance_divisors = {");
4211 for (i = 0; i < Elements(key->vs.instance_divisors); i++)
4212 fprintf(f, !i ? "%u" : ", %u",
4213 key->vs.instance_divisors[i]);
4214 fprintf(f, "}\n");
4215 fprintf(f, " as_es = %u\n", key->vs.as_es);
4216 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
4217 fprintf(f, " export_prim_id = %u\n", key->vs.export_prim_id);
4218 break;
4219
4220 case PIPE_SHADER_TESS_CTRL:
4221 fprintf(f, " prim_mode = %u\n", key->tcs.prim_mode);
4222 break;
4223
4224 case PIPE_SHADER_TESS_EVAL:
4225 fprintf(f, " as_es = %u\n", key->tes.as_es);
4226 fprintf(f, " export_prim_id = %u\n", key->tes.export_prim_id);
4227 break;
4228
4229 case PIPE_SHADER_GEOMETRY:
4230 break;
4231
4232 case PIPE_SHADER_FRAGMENT:
4233 fprintf(f, " spi_shader_col_format = 0x%x\n", key->ps.spi_shader_col_format);
4234 fprintf(f, " last_cbuf = %u\n", key->ps.last_cbuf);
4235 fprintf(f, " color_two_side = %u\n", key->ps.color_two_side);
4236 fprintf(f, " alpha_func = %u\n", key->ps.alpha_func);
4237 fprintf(f, " alpha_to_one = %u\n", key->ps.alpha_to_one);
4238 fprintf(f, " poly_stipple = %u\n", key->ps.poly_stipple);
4239 fprintf(f, " clamp_color = %u\n", key->ps.clamp_color);
4240 break;
4241
4242 default:
4243 assert(0);
4244 }
4245 }
4246
4247 static void si_init_shader_ctx(struct si_shader_context *ctx,
4248 struct si_screen *sscreen,
4249 struct si_shader *shader,
4250 LLVMTargetMachineRef tm,
4251 struct tgsi_shader_info *info)
4252 {
4253 struct lp_build_tgsi_context *bld_base;
4254
4255 memset(ctx, 0, sizeof(*ctx));
4256 radeon_llvm_context_init(&ctx->radeon_bld);
4257 ctx->tm = tm;
4258 ctx->screen = sscreen;
4259 if (shader && shader->selector)
4260 ctx->type = shader->selector->info.processor;
4261 else
4262 ctx->type = -1;
4263 ctx->shader = shader;
4264
4265 bld_base = &ctx->radeon_bld.soa.bld_base;
4266 bld_base->info = info;
4267 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
4268
4269 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
4270 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
4271 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
4272
4273 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
4274 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
4275 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
4276 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
4277 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
4278 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
4279 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
4280 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
4281 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
4282 bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
4283 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
4284 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
4285 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
4286
4287 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
4288 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
4289 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
4290 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
4291
4292 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
4293 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
4294 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
4295
4296 if (HAVE_LLVM >= 0x0306) {
4297 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
4298 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
4299 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
4300 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
4301 }
4302 }
4303
4304 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
4305 struct si_shader *shader,
4306 struct pipe_debug_callback *debug)
4307 {
4308 struct si_shader_selector *sel = shader->selector;
4309 struct tgsi_token *tokens = sel->tokens;
4310 struct si_shader_context si_shader_ctx;
4311 struct lp_build_tgsi_context * bld_base;
4312 struct tgsi_shader_info stipple_shader_info;
4313 LLVMModuleRef mod;
4314 int r = 0;
4315 bool poly_stipple = sel->type == PIPE_SHADER_FRAGMENT &&
4316 shader->key.ps.poly_stipple;
4317 bool dump = r600_can_dump_shader(&sscreen->b, sel->info.processor);
4318
4319 if (poly_stipple) {
4320 tokens = util_pstipple_create_fragment_shader(tokens, NULL,
4321 SI_POLY_STIPPLE_SAMPLER,
4322 TGSI_FILE_SYSTEM_VALUE);
4323 tgsi_scan_shader(tokens, &stipple_shader_info);
4324 }
4325
4326 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
4327 * conversion fails. */
4328 if (dump && !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
4329 si_dump_shader_key(sel->type, &shader->key, stderr);
4330 tgsi_dump(tokens, 0);
4331 si_dump_streamout(&sel->so);
4332 }
4333
4334 si_init_shader_ctx(&si_shader_ctx, sscreen, shader, tm,
4335 poly_stipple ? &stipple_shader_info : &sel->info);
4336
4337 if (sel->type != PIPE_SHADER_COMPUTE)
4338 shader->dx10_clamp_mode = true;
4339
4340 shader->uses_instanceid = sel->info.uses_instanceid;
4341
4342 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
4343 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
4344
4345 switch (si_shader_ctx.type) {
4346 case TGSI_PROCESSOR_VERTEX:
4347 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
4348 if (shader->key.vs.as_ls)
4349 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
4350 else if (shader->key.vs.as_es)
4351 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4352 else
4353 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4354 break;
4355 case TGSI_PROCESSOR_TESS_CTRL:
4356 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
4357 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
4358 bld_base->emit_store = store_output_tcs;
4359 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
4360 break;
4361 case TGSI_PROCESSOR_TESS_EVAL:
4362 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
4363 if (shader->key.tes.as_es)
4364 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4365 else
4366 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4367 break;
4368 case TGSI_PROCESSOR_GEOMETRY:
4369 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
4370 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
4371 break;
4372 case TGSI_PROCESSOR_FRAGMENT:
4373 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
4374 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
4375 break;
4376 default:
4377 assert(!"Unsupported shader type");
4378 return -1;
4379 }
4380
4381 create_meta_data(&si_shader_ctx);
4382 create_function(&si_shader_ctx);
4383 preload_constants(&si_shader_ctx);
4384 preload_samplers(&si_shader_ctx);
4385 preload_streamout_buffers(&si_shader_ctx);
4386 preload_ring_buffers(&si_shader_ctx);
4387
4388 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4389 int i;
4390 for (i = 0; i < 4; i++) {
4391 si_shader_ctx.gs_next_vertex[i] =
4392 lp_build_alloca(bld_base->base.gallivm,
4393 bld_base->uint_bld.elem_type, "");
4394 }
4395 }
4396
4397 if (!lp_build_tgsi_llvm(bld_base, tokens)) {
4398 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
4399 goto out;
4400 }
4401
4402 LLVMBuildRetVoid(bld_base->base.gallivm->builder);
4403 mod = bld_base->base.gallivm->module;
4404
4405 /* Dump LLVM IR before any optimization passes */
4406 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
4407 r600_can_dump_shader(&sscreen->b, si_shader_ctx.type))
4408 LLVMDumpModule(mod);
4409
4410 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
4411
4412 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
4413 mod, debug, si_shader_ctx.type);
4414 if (r) {
4415 fprintf(stderr, "LLVM failed to compile shader\n");
4416 goto out;
4417 }
4418
4419 si_shader_dump(sscreen, shader, debug, si_shader_ctx.type);
4420
4421 r = si_shader_binary_upload(sscreen, shader);
4422 if (r) {
4423 fprintf(stderr, "LLVM failed to upload shader\n");
4424 goto out;
4425 }
4426
4427 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
4428
4429 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4430 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
4431 shader->gs_copy_shader->selector = shader->selector;
4432 si_shader_ctx.shader = shader->gs_copy_shader;
4433 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
4434 shader, dump, debug))) {
4435 free(shader->gs_copy_shader);
4436 shader->gs_copy_shader = NULL;
4437 goto out;
4438 }
4439 }
4440
4441 out:
4442 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
4443 FREE(si_shader_ctx.constants[i]);
4444 if (poly_stipple)
4445 tgsi_free_tokens(tokens);
4446 return r;
4447 }
4448
4449 void si_shader_destroy(struct si_shader *shader)
4450 {
4451 if (shader->gs_copy_shader) {
4452 si_shader_destroy(shader->gs_copy_shader);
4453 FREE(shader->gs_copy_shader);
4454 }
4455
4456 if (shader->scratch_bo)
4457 r600_resource_reference(&shader->scratch_bo, NULL);
4458
4459 r600_resource_reference(&shader->bo, NULL);
4460
4461 radeon_shader_binary_clean(&shader->binary);
4462 }