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radeonsi: cosmetic changes in si_shader.c
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "gallivm/lp_bld_misc.h"
37 #include "radeon/r600_cs.h"
38 #include "radeon/radeon_llvm.h"
39 #include "radeon/radeon_elf_util.h"
40 #include "radeon/radeon_llvm_emit.h"
41 #include "util/u_memory.h"
42 #include "util/u_string.h"
43 #include "tgsi/tgsi_parse.h"
44 #include "tgsi/tgsi_build.h"
45 #include "tgsi/tgsi_util.h"
46 #include "tgsi/tgsi_dump.h"
47
48 #include "si_pipe.h"
49 #include "si_shader.h"
50 #include "sid.h"
51
52 #include <errno.h>
53
54 static const char *scratch_rsrc_dword0_symbol =
55 "SCRATCH_RSRC_DWORD0";
56
57 static const char *scratch_rsrc_dword1_symbol =
58 "SCRATCH_RSRC_DWORD1";
59
60 struct si_shader_output_values
61 {
62 LLVMValueRef values[4];
63 unsigned name;
64 unsigned sid;
65 };
66
67 struct si_shader_context
68 {
69 struct radeon_llvm_context radeon_bld;
70 struct si_shader *shader;
71 struct si_screen *screen;
72
73 unsigned type; /* PIPE_SHADER_* specifies the type of shader. */
74 bool is_gs_copy_shader;
75
76 /* Whether to generate the optimized shader variant compiled as a whole
77 * (without a prolog and epilog)
78 */
79 bool is_monolithic;
80
81 int param_streamout_config;
82 int param_streamout_write_index;
83 int param_streamout_offset[4];
84 int param_vertex_id;
85 int param_rel_auto_id;
86 int param_vs_prim_id;
87 int param_instance_id;
88 int param_vertex_index0;
89 int param_tes_u;
90 int param_tes_v;
91 int param_tes_rel_patch_id;
92 int param_tes_patch_id;
93 int param_es2gs_offset;
94 int param_oc_lds;
95
96 /* Sets a bit if the dynamic HS control word was 0x80000000. The bit is
97 * 0x800000 for VS, 0x1 for ES.
98 */
99 int param_tess_offchip;
100
101 LLVMTargetMachineRef tm;
102
103 unsigned invariant_load_md_kind;
104 unsigned range_md_kind;
105 unsigned uniform_md_kind;
106 LLVMValueRef empty_md;
107
108 /* Preloaded descriptors. */
109 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
110 LLVMValueRef shader_buffers[SI_NUM_SHADER_BUFFERS];
111 LLVMValueRef sampler_views[SI_NUM_SAMPLERS];
112 LLVMValueRef sampler_states[SI_NUM_SAMPLERS];
113 LLVMValueRef fmasks[SI_NUM_SAMPLERS];
114 LLVMValueRef images[SI_NUM_IMAGES];
115 LLVMValueRef esgs_ring;
116 LLVMValueRef gsvs_ring[4];
117
118 LLVMValueRef lds;
119 LLVMValueRef gs_next_vertex[4];
120 LLVMValueRef return_value;
121
122 LLVMTypeRef voidt;
123 LLVMTypeRef i1;
124 LLVMTypeRef i8;
125 LLVMTypeRef i32;
126 LLVMTypeRef i64;
127 LLVMTypeRef i128;
128 LLVMTypeRef f32;
129 LLVMTypeRef v16i8;
130 LLVMTypeRef v2i32;
131 LLVMTypeRef v4i32;
132 LLVMTypeRef v4f32;
133 LLVMTypeRef v8i32;
134
135 LLVMValueRef shared_memory;
136 };
137
138 static struct si_shader_context *si_shader_context(
139 struct lp_build_tgsi_context *bld_base)
140 {
141 return (struct si_shader_context *)bld_base;
142 }
143
144 static void si_init_shader_ctx(struct si_shader_context *ctx,
145 struct si_screen *sscreen,
146 struct si_shader *shader,
147 LLVMTargetMachineRef tm);
148
149 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
150 struct lp_build_tgsi_context *bld_base,
151 struct lp_build_emit_data *emit_data);
152
153 static void si_dump_shader_key(unsigned shader, union si_shader_key *key,
154 FILE *f);
155
156 /* Ideally pass the sample mask input to the PS epilog as v13, which
157 * is its usual location, so that the shader doesn't have to add v_mov.
158 */
159 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
160
161 /* The VS location of the PrimitiveID input is the same in the epilog,
162 * so that the main shader part doesn't have to move it.
163 */
164 #define VS_EPILOG_PRIMID_LOC 2
165
166 #define PERSPECTIVE_BASE 0
167 #define LINEAR_BASE 9
168
169 #define SAMPLE_OFFSET 0
170 #define CENTER_OFFSET 2
171 #define CENTROID_OFSET 4
172
173 #define USE_SGPR_MAX_SUFFIX_LEN 5
174 #define CONST_ADDR_SPACE 2
175 #define LOCAL_ADDR_SPACE 3
176 #define USER_SGPR_ADDR_SPACE 8
177
178
179 #define SENDMSG_GS 2
180 #define SENDMSG_GS_DONE 3
181
182 #define SENDMSG_GS_OP_NOP (0 << 4)
183 #define SENDMSG_GS_OP_CUT (1 << 4)
184 #define SENDMSG_GS_OP_EMIT (2 << 4)
185 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
186
187 /**
188 * Returns a unique index for a semantic name and index. The index must be
189 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
190 * calculated.
191 */
192 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
193 {
194 switch (semantic_name) {
195 case TGSI_SEMANTIC_POSITION:
196 return 0;
197 case TGSI_SEMANTIC_PSIZE:
198 return 1;
199 case TGSI_SEMANTIC_CLIPDIST:
200 assert(index <= 1);
201 return 2 + index;
202 case TGSI_SEMANTIC_GENERIC:
203 if (index <= 63-4)
204 return 4 + index;
205 else
206 /* same explanation as in the default statement,
207 * the only user hitting this is st/nine.
208 */
209 return 0;
210
211 /* patch indices are completely separate and thus start from 0 */
212 case TGSI_SEMANTIC_TESSOUTER:
213 return 0;
214 case TGSI_SEMANTIC_TESSINNER:
215 return 1;
216 case TGSI_SEMANTIC_PATCH:
217 return 2 + index;
218
219 default:
220 /* Don't fail here. The result of this function is only used
221 * for LS, TCS, TES, and GS, where legacy GL semantics can't
222 * occur, but this function is called for all vertex shaders
223 * before it's known whether LS will be compiled or not.
224 */
225 return 0;
226 }
227 }
228
229 /**
230 * Get the value of a shader input parameter and extract a bitfield.
231 */
232 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
233 unsigned param, unsigned rshift,
234 unsigned bitwidth)
235 {
236 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
237 LLVMValueRef value = LLVMGetParam(ctx->radeon_bld.main_fn,
238 param);
239
240 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
241 value = bitcast(&ctx->radeon_bld.soa.bld_base,
242 TGSI_TYPE_UNSIGNED, value);
243
244 if (rshift)
245 value = LLVMBuildLShr(gallivm->builder, value,
246 lp_build_const_int32(gallivm, rshift), "");
247
248 if (rshift + bitwidth < 32) {
249 unsigned mask = (1 << bitwidth) - 1;
250 value = LLVMBuildAnd(gallivm->builder, value,
251 lp_build_const_int32(gallivm, mask), "");
252 }
253
254 return value;
255 }
256
257 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
258 {
259 switch (ctx->type) {
260 case PIPE_SHADER_TESS_CTRL:
261 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
262
263 case PIPE_SHADER_TESS_EVAL:
264 return LLVMGetParam(ctx->radeon_bld.main_fn,
265 ctx->param_tes_rel_patch_id);
266
267 default:
268 assert(0);
269 return NULL;
270 }
271 }
272
273 /* Tessellation shaders pass outputs to the next shader using LDS.
274 *
275 * LS outputs = TCS inputs
276 * TCS outputs = TES inputs
277 *
278 * The LDS layout is:
279 * - TCS inputs for patch 0
280 * - TCS inputs for patch 1
281 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
282 * - ...
283 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
284 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
285 * - TCS outputs for patch 1
286 * - Per-patch TCS outputs for patch 1
287 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
288 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
289 * - ...
290 *
291 * All three shaders VS(LS), TCS, TES share the same LDS space.
292 */
293
294 static LLVMValueRef
295 get_tcs_in_patch_stride(struct si_shader_context *ctx)
296 {
297 if (ctx->type == PIPE_SHADER_VERTEX)
298 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
299 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
300 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
301 else {
302 assert(0);
303 return NULL;
304 }
305 }
306
307 static LLVMValueRef
308 get_tcs_out_patch_stride(struct si_shader_context *ctx)
309 {
310 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
311 }
312
313 static LLVMValueRef
314 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
315 {
316 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
317 unpack_param(ctx,
318 SI_PARAM_TCS_OUT_OFFSETS,
319 0, 16),
320 4);
321 }
322
323 static LLVMValueRef
324 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
325 {
326 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
327 unpack_param(ctx,
328 SI_PARAM_TCS_OUT_OFFSETS,
329 16, 16),
330 4);
331 }
332
333 static LLVMValueRef
334 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
335 {
336 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
337 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
338 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
339
340 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
341 }
342
343 static LLVMValueRef
344 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
345 {
346 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
347 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
348 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
349 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
350
351 return LLVMBuildAdd(gallivm->builder, patch0_offset,
352 LLVMBuildMul(gallivm->builder, patch_stride,
353 rel_patch_id, ""),
354 "");
355 }
356
357 static LLVMValueRef
358 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
359 {
360 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
361 LLVMValueRef patch0_patch_data_offset =
362 get_tcs_out_patch0_patch_data_offset(ctx);
363 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
364 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
365
366 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
367 LLVMBuildMul(gallivm->builder, patch_stride,
368 rel_patch_id, ""),
369 "");
370 }
371
372 static void build_indexed_store(struct si_shader_context *ctx,
373 LLVMValueRef base_ptr, LLVMValueRef index,
374 LLVMValueRef value)
375 {
376 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
377 struct gallivm_state *gallivm = bld_base->base.gallivm;
378 LLVMValueRef indices[2], pointer;
379
380 indices[0] = bld_base->uint_bld.zero;
381 indices[1] = index;
382
383 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
384 LLVMBuildStore(gallivm->builder, value, pointer);
385 }
386
387 /**
388 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
389 * It's equivalent to doing a load from &base_ptr[index].
390 *
391 * \param base_ptr Where the array starts.
392 * \param index The element index into the array.
393 * \param uniform Whether the base_ptr and index can be assumed to be
394 * dynamically uniform
395 */
396 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
397 LLVMValueRef base_ptr, LLVMValueRef index,
398 bool uniform)
399 {
400 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
401 struct gallivm_state *gallivm = bld_base->base.gallivm;
402 LLVMValueRef indices[2], pointer;
403
404 indices[0] = bld_base->uint_bld.zero;
405 indices[1] = index;
406
407 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
408 if (uniform)
409 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
410 return LLVMBuildLoad(gallivm->builder, pointer, "");
411 }
412
413 /**
414 * Do a load from &base_ptr[index], but also add a flag that it's loading
415 * a constant from a dynamically uniform index.
416 */
417 static LLVMValueRef build_indexed_load_const(
418 struct si_shader_context *ctx,
419 LLVMValueRef base_ptr, LLVMValueRef index)
420 {
421 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
422 LLVMSetMetadata(result, ctx->invariant_load_md_kind, ctx->empty_md);
423 return result;
424 }
425
426 static LLVMValueRef get_instance_index_for_fetch(
427 struct radeon_llvm_context *radeon_bld,
428 unsigned param_start_instance, unsigned divisor)
429 {
430 struct si_shader_context *ctx =
431 si_shader_context(&radeon_bld->soa.bld_base);
432 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
433
434 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
435 ctx->param_instance_id);
436
437 /* The division must be done before START_INSTANCE is added. */
438 if (divisor > 1)
439 result = LLVMBuildUDiv(gallivm->builder, result,
440 lp_build_const_int32(gallivm, divisor), "");
441
442 return LLVMBuildAdd(gallivm->builder, result,
443 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
444 }
445
446 static void declare_input_vs(
447 struct radeon_llvm_context *radeon_bld,
448 unsigned input_index,
449 const struct tgsi_full_declaration *decl)
450 {
451 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
452 struct gallivm_state *gallivm = base->gallivm;
453 struct si_shader_context *ctx =
454 si_shader_context(&radeon_bld->soa.bld_base);
455 unsigned divisor =
456 ctx->shader->key.vs.prolog.instance_divisors[input_index];
457
458 unsigned chan;
459
460 LLVMValueRef t_list_ptr;
461 LLVMValueRef t_offset;
462 LLVMValueRef t_list;
463 LLVMValueRef attribute_offset;
464 LLVMValueRef buffer_index;
465 LLVMValueRef args[3];
466 LLVMValueRef input;
467
468 /* Load the T list */
469 t_list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
470
471 t_offset = lp_build_const_int32(gallivm, input_index);
472
473 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
474
475 /* Build the attribute offset */
476 attribute_offset = lp_build_const_int32(gallivm, 0);
477
478 if (!ctx->is_monolithic) {
479 buffer_index = LLVMGetParam(radeon_bld->main_fn,
480 ctx->param_vertex_index0 +
481 input_index);
482 } else if (divisor) {
483 /* Build index from instance ID, start instance and divisor */
484 ctx->shader->info.uses_instanceid = true;
485 buffer_index = get_instance_index_for_fetch(&ctx->radeon_bld,
486 SI_PARAM_START_INSTANCE,
487 divisor);
488 } else {
489 /* Load the buffer index for vertices. */
490 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
491 ctx->param_vertex_id);
492 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
493 SI_PARAM_BASE_VERTEX);
494 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
495 }
496
497 args[0] = t_list;
498 args[1] = attribute_offset;
499 args[2] = buffer_index;
500 input = lp_build_intrinsic(gallivm->builder,
501 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
502 LLVMReadNoneAttribute);
503
504 /* Break up the vec4 into individual components */
505 for (chan = 0; chan < 4; chan++) {
506 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
507 /* XXX: Use a helper function for this. There is one in
508 * tgsi_llvm.c. */
509 ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
510 LLVMBuildExtractElement(gallivm->builder,
511 input, llvm_chan, "");
512 }
513 }
514
515 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
516 unsigned swizzle)
517 {
518 struct si_shader_context *ctx = si_shader_context(bld_base);
519
520 if (swizzle > 0)
521 return bld_base->uint_bld.zero;
522
523 switch (ctx->type) {
524 case PIPE_SHADER_VERTEX:
525 return LLVMGetParam(ctx->radeon_bld.main_fn,
526 ctx->param_vs_prim_id);
527 case PIPE_SHADER_TESS_CTRL:
528 return LLVMGetParam(ctx->radeon_bld.main_fn,
529 SI_PARAM_PATCH_ID);
530 case PIPE_SHADER_TESS_EVAL:
531 return LLVMGetParam(ctx->radeon_bld.main_fn,
532 ctx->param_tes_patch_id);
533 case PIPE_SHADER_GEOMETRY:
534 return LLVMGetParam(ctx->radeon_bld.main_fn,
535 SI_PARAM_PRIMITIVE_ID);
536 default:
537 assert(0);
538 return bld_base->uint_bld.zero;
539 }
540 }
541
542 /**
543 * Return the value of tgsi_ind_register for indexing.
544 * This is the indirect index with the constant offset added to it.
545 */
546 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
547 const struct tgsi_ind_register *ind,
548 int rel_index)
549 {
550 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
551 LLVMValueRef result;
552
553 result = ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
554 result = LLVMBuildLoad(gallivm->builder, result, "");
555 result = LLVMBuildAdd(gallivm->builder, result,
556 lp_build_const_int32(gallivm, rel_index), "");
557 return result;
558 }
559
560 /**
561 * Like get_indirect_index, but restricts the return value to a (possibly
562 * undefined) value inside [0..num).
563 */
564 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
565 const struct tgsi_ind_register *ind,
566 int rel_index, unsigned num)
567 {
568 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
569
570 /* LLVM 3.8: If indirect resource indexing is used:
571 * - SI & CIK hang
572 * - VI crashes
573 */
574 if (HAVE_LLVM <= 0x0308)
575 return LLVMGetUndef(ctx->i32);
576
577 return radeon_llvm_bound_index(&ctx->radeon_bld, result, num);
578 }
579
580
581 /**
582 * Calculate a dword address given an input or output register and a stride.
583 */
584 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
585 const struct tgsi_full_dst_register *dst,
586 const struct tgsi_full_src_register *src,
587 LLVMValueRef vertex_dw_stride,
588 LLVMValueRef base_addr)
589 {
590 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
591 struct tgsi_shader_info *info = &ctx->shader->selector->info;
592 ubyte *name, *index, *array_first;
593 int first, param;
594 struct tgsi_full_dst_register reg;
595
596 /* Set the register description. The address computation is the same
597 * for sources and destinations. */
598 if (src) {
599 reg.Register.File = src->Register.File;
600 reg.Register.Index = src->Register.Index;
601 reg.Register.Indirect = src->Register.Indirect;
602 reg.Register.Dimension = src->Register.Dimension;
603 reg.Indirect = src->Indirect;
604 reg.Dimension = src->Dimension;
605 reg.DimIndirect = src->DimIndirect;
606 } else
607 reg = *dst;
608
609 /* If the register is 2-dimensional (e.g. an array of vertices
610 * in a primitive), calculate the base address of the vertex. */
611 if (reg.Register.Dimension) {
612 LLVMValueRef index;
613
614 if (reg.Dimension.Indirect)
615 index = get_indirect_index(ctx, &reg.DimIndirect,
616 reg.Dimension.Index);
617 else
618 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
619
620 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
621 LLVMBuildMul(gallivm->builder, index,
622 vertex_dw_stride, ""), "");
623 }
624
625 /* Get information about the register. */
626 if (reg.Register.File == TGSI_FILE_INPUT) {
627 name = info->input_semantic_name;
628 index = info->input_semantic_index;
629 array_first = info->input_array_first;
630 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
631 name = info->output_semantic_name;
632 index = info->output_semantic_index;
633 array_first = info->output_array_first;
634 } else {
635 assert(0);
636 return NULL;
637 }
638
639 if (reg.Register.Indirect) {
640 /* Add the relative address of the element. */
641 LLVMValueRef ind_index;
642
643 if (reg.Indirect.ArrayID)
644 first = array_first[reg.Indirect.ArrayID];
645 else
646 first = reg.Register.Index;
647
648 ind_index = get_indirect_index(ctx, &reg.Indirect,
649 reg.Register.Index - first);
650
651 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
652 LLVMBuildMul(gallivm->builder, ind_index,
653 lp_build_const_int32(gallivm, 4), ""), "");
654
655 param = si_shader_io_get_unique_index(name[first], index[first]);
656 } else {
657 param = si_shader_io_get_unique_index(name[reg.Register.Index],
658 index[reg.Register.Index]);
659 }
660
661 /* Add the base address of the element. */
662 return LLVMBuildAdd(gallivm->builder, base_addr,
663 lp_build_const_int32(gallivm, param * 4), "");
664 }
665
666 /* The offchip buffer layout for TCS->TES is
667 *
668 * - attribute 0 of patch 0 vertex 0
669 * - attribute 0 of patch 0 vertex 1
670 * - attribute 0 of patch 0 vertex 2
671 * ...
672 * - attribute 0 of patch 1 vertex 0
673 * - attribute 0 of patch 1 vertex 1
674 * ...
675 * - attribute 1 of patch 0 vertex 0
676 * - attribute 1 of patch 0 vertex 1
677 * ...
678 * - per patch attribute 0 of patch 0
679 * - per patch attribute 0 of patch 1
680 * ...
681 *
682 * Note that every attribute has 4 components.
683 */
684 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
685 LLVMValueRef vertex_index,
686 LLVMValueRef param_index)
687 {
688 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
689 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
690 LLVMValueRef param_stride, constant16;
691
692 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
693 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
694 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
695 num_patches, "");
696
697 constant16 = lp_build_const_int32(gallivm, 16);
698 if (vertex_index) {
699 base_addr = LLVMBuildMul(gallivm->builder, get_rel_patch_id(ctx),
700 vertices_per_patch, "");
701
702 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
703 vertex_index, "");
704
705 param_stride = total_vertices;
706 } else {
707 base_addr = get_rel_patch_id(ctx);
708 param_stride = num_patches;
709 }
710
711 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
712 LLVMBuildMul(gallivm->builder, param_index,
713 param_stride, ""), "");
714
715 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
716
717 if (!vertex_index) {
718 LLVMValueRef patch_data_offset =
719 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
720
721 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
722 patch_data_offset, "");
723 }
724 return base_addr;
725 }
726
727 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
728 struct si_shader_context *ctx,
729 const struct tgsi_full_dst_register *dst,
730 const struct tgsi_full_src_register *src)
731 {
732 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
733 struct tgsi_shader_info *info = &ctx->shader->selector->info;
734 ubyte *name, *index, *array_first;
735 struct tgsi_full_src_register reg;
736 LLVMValueRef vertex_index = NULL;
737 LLVMValueRef param_index = NULL;
738 unsigned param_index_base, param_base;
739
740 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
741
742 if (reg.Register.Dimension) {
743
744 if (reg.Dimension.Indirect)
745 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
746 reg.Dimension.Index);
747 else
748 vertex_index = lp_build_const_int32(gallivm,
749 reg.Dimension.Index);
750 }
751
752 /* Get information about the register. */
753 if (reg.Register.File == TGSI_FILE_INPUT) {
754 name = info->input_semantic_name;
755 index = info->input_semantic_index;
756 array_first = info->input_array_first;
757 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
758 name = info->output_semantic_name;
759 index = info->output_semantic_index;
760 array_first = info->output_array_first;
761 } else {
762 assert(0);
763 return NULL;
764 }
765
766 if (reg.Register.Indirect) {
767 if (reg.Indirect.ArrayID)
768 param_base = array_first[reg.Indirect.ArrayID];
769 else
770 param_base = reg.Register.Index;
771
772 param_index = get_indirect_index(ctx, &reg.Indirect,
773 reg.Register.Index - param_base);
774
775 } else {
776 param_base = reg.Register.Index;
777 param_index = lp_build_const_int32(gallivm, 0);
778 }
779
780 param_index_base = si_shader_io_get_unique_index(name[param_base],
781 index[param_base]);
782
783 param_index = LLVMBuildAdd(gallivm->builder, param_index,
784 lp_build_const_int32(gallivm, param_index_base),
785 "");
786
787 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
788 }
789
790 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
791 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
792 * or v4i32 (num_channels=3,4). */
793 static void build_tbuffer_store(struct si_shader_context *ctx,
794 LLVMValueRef rsrc,
795 LLVMValueRef vdata,
796 unsigned num_channels,
797 LLVMValueRef vaddr,
798 LLVMValueRef soffset,
799 unsigned inst_offset,
800 unsigned dfmt,
801 unsigned nfmt,
802 unsigned offen,
803 unsigned idxen,
804 unsigned glc,
805 unsigned slc,
806 unsigned tfe)
807 {
808 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
809 LLVMValueRef args[] = {
810 rsrc,
811 vdata,
812 LLVMConstInt(ctx->i32, num_channels, 0),
813 vaddr,
814 soffset,
815 LLVMConstInt(ctx->i32, inst_offset, 0),
816 LLVMConstInt(ctx->i32, dfmt, 0),
817 LLVMConstInt(ctx->i32, nfmt, 0),
818 LLVMConstInt(ctx->i32, offen, 0),
819 LLVMConstInt(ctx->i32, idxen, 0),
820 LLVMConstInt(ctx->i32, glc, 0),
821 LLVMConstInt(ctx->i32, slc, 0),
822 LLVMConstInt(ctx->i32, tfe, 0)
823 };
824
825 /* The instruction offset field has 12 bits */
826 assert(offen || inst_offset < (1 << 12));
827
828 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
829 unsigned func = CLAMP(num_channels, 1, 3) - 1;
830 const char *types[] = {"i32", "v2i32", "v4i32"};
831 char name[256];
832 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
833
834 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
835 args, ARRAY_SIZE(args), 0);
836 }
837
838 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
839 LLVMValueRef rsrc,
840 LLVMValueRef vdata,
841 unsigned num_channels,
842 LLVMValueRef vaddr,
843 LLVMValueRef soffset,
844 unsigned inst_offset)
845 {
846 static unsigned dfmt[] = {
847 V_008F0C_BUF_DATA_FORMAT_32,
848 V_008F0C_BUF_DATA_FORMAT_32_32,
849 V_008F0C_BUF_DATA_FORMAT_32_32_32,
850 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
851 };
852 assert(num_channels >= 1 && num_channels <= 4);
853
854 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
855 inst_offset, dfmt[num_channels-1],
856 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
857 }
858
859 static LLVMValueRef build_buffer_load(struct si_shader_context *ctx,
860 LLVMValueRef rsrc,
861 int num_channels,
862 LLVMValueRef vindex,
863 LLVMValueRef voffset,
864 LLVMValueRef soffset,
865 unsigned inst_offset,
866 unsigned glc,
867 unsigned slc)
868 {
869 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
870 unsigned func = CLAMP(num_channels, 1, 3) - 1;
871
872 if (HAVE_LLVM >= 0x309) {
873 LLVMValueRef args[] = {
874 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, ""),
875 vindex ? vindex : LLVMConstInt(ctx->i32, 0, 0),
876 LLVMConstInt(ctx->i32, inst_offset, 0),
877 LLVMConstInt(ctx->i1, glc, 0),
878 LLVMConstInt(ctx->i1, slc, 0)
879 };
880
881 LLVMTypeRef types[] = {ctx->f32, LLVMVectorType(ctx->f32, 2),
882 ctx->v4f32};
883 const char *type_names[] = {"f32", "v2f32", "v4f32"};
884 char name[256];
885
886 if (voffset) {
887 args[2] = LLVMBuildAdd(gallivm->builder, args[2], voffset,
888 "");
889 }
890
891 if (soffset) {
892 args[2] = LLVMBuildAdd(gallivm->builder, args[2], soffset,
893 "");
894 }
895
896 snprintf(name, sizeof(name), "llvm.amdgcn.buffer.load.%s",
897 type_names[func]);
898
899 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
900 ARRAY_SIZE(args), LLVMReadOnlyAttribute);
901 } else {
902 LLVMValueRef args[] = {
903 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v16i8, ""),
904 voffset ? voffset : vindex,
905 soffset,
906 LLVMConstInt(ctx->i32, inst_offset, 0),
907 LLVMConstInt(ctx->i32, voffset ? 1 : 0, 0), // offen
908 LLVMConstInt(ctx->i32, vindex ? 1 : 0, 0), //idxen
909 LLVMConstInt(ctx->i32, glc, 0),
910 LLVMConstInt(ctx->i32, slc, 0),
911 LLVMConstInt(ctx->i32, 0, 0), // TFE
912 };
913
914 LLVMTypeRef types[] = {ctx->i32, LLVMVectorType(ctx->i32, 2),
915 ctx->v4i32};
916 const char *type_names[] = {"i32", "v2i32", "v4i32"};
917 const char *arg_type = "i32";
918 char name[256];
919
920 if (voffset && vindex) {
921 LLVMValueRef vaddr[] = {vindex, voffset};
922
923 arg_type = "v2i32";
924 args[1] = lp_build_gather_values(gallivm, vaddr, 2);
925 }
926
927 snprintf(name, sizeof(name), "llvm.SI.buffer.load.dword.%s.%s",
928 type_names[func], arg_type);
929
930 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
931 ARRAY_SIZE(args), LLVMReadOnlyAttribute);
932 }
933 }
934
935 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
936 enum tgsi_opcode_type type, unsigned swizzle,
937 LLVMValueRef buffer, LLVMValueRef offset,
938 LLVMValueRef base)
939 {
940 struct si_shader_context *ctx = si_shader_context(bld_base);
941 struct gallivm_state *gallivm = bld_base->base.gallivm;
942 LLVMValueRef value, value2;
943 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
944 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
945
946 if (swizzle == ~0) {
947 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
948 0, 1, 0);
949
950 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
951 }
952
953 if (!tgsi_type_is_64bit(type)) {
954 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
955 0, 1, 0);
956
957 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
958 return LLVMBuildExtractElement(gallivm->builder, value,
959 lp_build_const_int32(gallivm, swizzle), "");
960 }
961
962 value = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
963 swizzle * 4, 1, 0);
964
965 value2 = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
966 swizzle * 4 + 4, 1, 0);
967
968 return radeon_llvm_emit_fetch_64bit(bld_base, type, value, value2);
969 }
970
971 /**
972 * Load from LDS.
973 *
974 * \param type output value type
975 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
976 * \param dw_addr address in dwords
977 */
978 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
979 enum tgsi_opcode_type type, unsigned swizzle,
980 LLVMValueRef dw_addr)
981 {
982 struct si_shader_context *ctx = si_shader_context(bld_base);
983 struct gallivm_state *gallivm = bld_base->base.gallivm;
984 LLVMValueRef value;
985
986 if (swizzle == ~0) {
987 LLVMValueRef values[TGSI_NUM_CHANNELS];
988
989 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
990 values[chan] = lds_load(bld_base, type, chan, dw_addr);
991
992 return lp_build_gather_values(bld_base->base.gallivm, values,
993 TGSI_NUM_CHANNELS);
994 }
995
996 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
997 lp_build_const_int32(gallivm, swizzle));
998
999 value = build_indexed_load(ctx, ctx->lds, dw_addr, false);
1000 if (tgsi_type_is_64bit(type)) {
1001 LLVMValueRef value2;
1002 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1003 lp_build_const_int32(gallivm, swizzle + 1));
1004 value2 = build_indexed_load(ctx, ctx->lds, dw_addr, false);
1005 return radeon_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1006 }
1007
1008 return LLVMBuildBitCast(gallivm->builder, value,
1009 tgsi2llvmtype(bld_base, type), "");
1010 }
1011
1012 /**
1013 * Store to LDS.
1014 *
1015 * \param swizzle offset (typically 0..3)
1016 * \param dw_addr address in dwords
1017 * \param value value to store
1018 */
1019 static void lds_store(struct lp_build_tgsi_context *bld_base,
1020 unsigned swizzle, LLVMValueRef dw_addr,
1021 LLVMValueRef value)
1022 {
1023 struct si_shader_context *ctx = si_shader_context(bld_base);
1024 struct gallivm_state *gallivm = bld_base->base.gallivm;
1025
1026 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1027 lp_build_const_int32(gallivm, swizzle));
1028
1029 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1030 build_indexed_store(ctx, ctx->lds,
1031 dw_addr, value);
1032 }
1033
1034 static LLVMValueRef fetch_input_tcs(
1035 struct lp_build_tgsi_context *bld_base,
1036 const struct tgsi_full_src_register *reg,
1037 enum tgsi_opcode_type type, unsigned swizzle)
1038 {
1039 struct si_shader_context *ctx = si_shader_context(bld_base);
1040 LLVMValueRef dw_addr, stride;
1041
1042 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
1043 dw_addr = get_tcs_in_current_patch_offset(ctx);
1044 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1045
1046 return lds_load(bld_base, type, swizzle, dw_addr);
1047 }
1048
1049 static LLVMValueRef fetch_output_tcs(
1050 struct lp_build_tgsi_context *bld_base,
1051 const struct tgsi_full_src_register *reg,
1052 enum tgsi_opcode_type type, unsigned swizzle)
1053 {
1054 struct si_shader_context *ctx = si_shader_context(bld_base);
1055 LLVMValueRef dw_addr, stride;
1056
1057 if (reg->Register.Dimension) {
1058 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1059 dw_addr = get_tcs_out_current_patch_offset(ctx);
1060 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1061 } else {
1062 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1063 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1064 }
1065
1066 return lds_load(bld_base, type, swizzle, dw_addr);
1067 }
1068
1069 static LLVMValueRef fetch_input_tes(
1070 struct lp_build_tgsi_context *bld_base,
1071 const struct tgsi_full_src_register *reg,
1072 enum tgsi_opcode_type type, unsigned swizzle)
1073 {
1074 struct si_shader_context *ctx = si_shader_context(bld_base);
1075 struct gallivm_state *gallivm = bld_base->base.gallivm;
1076 LLVMValueRef rw_buffers, buffer, base, addr;
1077
1078 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1079 SI_PARAM_RW_BUFFERS);
1080 buffer = build_indexed_load_const(ctx, rw_buffers,
1081 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1082
1083 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1084 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1085
1086 return buffer_load(bld_base, type, swizzle, buffer, base, addr);
1087 }
1088
1089 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1090 const struct tgsi_full_instruction *inst,
1091 const struct tgsi_opcode_info *info,
1092 LLVMValueRef dst[4])
1093 {
1094 struct si_shader_context *ctx = si_shader_context(bld_base);
1095 struct gallivm_state *gallivm = bld_base->base.gallivm;
1096 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
1097 unsigned chan_index;
1098 LLVMValueRef dw_addr, stride;
1099 LLVMValueRef rw_buffers, buffer, base, buf_addr;
1100 LLVMValueRef values[4];
1101
1102 /* Only handle per-patch and per-vertex outputs here.
1103 * Vectors will be lowered to scalars and this function will be called again.
1104 */
1105 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1106 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1107 radeon_llvm_emit_store(bld_base, inst, info, dst);
1108 return;
1109 }
1110
1111 if (reg->Register.Dimension) {
1112 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1113 dw_addr = get_tcs_out_current_patch_offset(ctx);
1114 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1115 } else {
1116 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1117 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1118 }
1119
1120 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1121 SI_PARAM_RW_BUFFERS);
1122 buffer = build_indexed_load_const(ctx, rw_buffers,
1123 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1124
1125 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1126 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1127
1128
1129 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1130 LLVMValueRef value = dst[chan_index];
1131
1132 if (inst->Instruction.Saturate)
1133 value = radeon_llvm_saturate(bld_base, value);
1134
1135 lds_store(bld_base, chan_index, dw_addr, value);
1136
1137 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1138 values[chan_index] = value;
1139
1140 if (inst->Dst[0].Register.WriteMask != 0xF) {
1141 build_tbuffer_store_dwords(ctx, buffer, value, 1,
1142 buf_addr, base,
1143 4 * chan_index);
1144 }
1145 }
1146
1147 if (inst->Dst[0].Register.WriteMask == 0xF) {
1148 LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
1149 values, 4);
1150 build_tbuffer_store_dwords(ctx, buffer, value, 4, buf_addr,
1151 base, 0);
1152 }
1153 }
1154
1155 static LLVMValueRef fetch_input_gs(
1156 struct lp_build_tgsi_context *bld_base,
1157 const struct tgsi_full_src_register *reg,
1158 enum tgsi_opcode_type type,
1159 unsigned swizzle)
1160 {
1161 struct lp_build_context *base = &bld_base->base;
1162 struct si_shader_context *ctx = si_shader_context(bld_base);
1163 struct si_shader *shader = ctx->shader;
1164 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1165 struct gallivm_state *gallivm = base->gallivm;
1166 LLVMValueRef vtx_offset;
1167 LLVMValueRef args[9];
1168 unsigned vtx_offset_param;
1169 struct tgsi_shader_info *info = &shader->selector->info;
1170 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1171 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1172 unsigned param;
1173 LLVMValueRef value;
1174
1175 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1176 return get_primitive_id(bld_base, swizzle);
1177
1178 if (!reg->Register.Dimension)
1179 return NULL;
1180
1181 if (swizzle == ~0) {
1182 LLVMValueRef values[TGSI_NUM_CHANNELS];
1183 unsigned chan;
1184 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1185 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1186 }
1187 return lp_build_gather_values(bld_base->base.gallivm, values,
1188 TGSI_NUM_CHANNELS);
1189 }
1190
1191 /* Get the vertex offset parameter */
1192 vtx_offset_param = reg->Dimension.Index;
1193 if (vtx_offset_param < 2) {
1194 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1195 } else {
1196 assert(vtx_offset_param < 6);
1197 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1198 }
1199 vtx_offset = lp_build_mul_imm(uint,
1200 LLVMGetParam(ctx->radeon_bld.main_fn,
1201 vtx_offset_param),
1202 4);
1203
1204 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1205 args[0] = ctx->esgs_ring;
1206 args[1] = vtx_offset;
1207 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
1208 args[3] = uint->zero;
1209 args[4] = uint->one; /* OFFEN */
1210 args[5] = uint->zero; /* IDXEN */
1211 args[6] = uint->one; /* GLC */
1212 args[7] = uint->zero; /* SLC */
1213 args[8] = uint->zero; /* TFE */
1214
1215 value = lp_build_intrinsic(gallivm->builder,
1216 "llvm.SI.buffer.load.dword.i32.i32",
1217 ctx->i32, args, 9,
1218 LLVMReadOnlyAttribute);
1219 if (tgsi_type_is_64bit(type)) {
1220 LLVMValueRef value2;
1221 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
1222 value2 = lp_build_intrinsic(gallivm->builder,
1223 "llvm.SI.buffer.load.dword.i32.i32",
1224 ctx->i32, args, 9,
1225 LLVMReadOnlyAttribute);
1226 return radeon_llvm_emit_fetch_64bit(bld_base, type,
1227 value, value2);
1228 }
1229 return LLVMBuildBitCast(gallivm->builder,
1230 value,
1231 tgsi2llvmtype(bld_base, type), "");
1232 }
1233
1234 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1235 {
1236 switch (interpolate) {
1237 case TGSI_INTERPOLATE_CONSTANT:
1238 return 0;
1239
1240 case TGSI_INTERPOLATE_LINEAR:
1241 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1242 return SI_PARAM_LINEAR_SAMPLE;
1243 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1244 return SI_PARAM_LINEAR_CENTROID;
1245 else
1246 return SI_PARAM_LINEAR_CENTER;
1247 break;
1248 case TGSI_INTERPOLATE_COLOR:
1249 case TGSI_INTERPOLATE_PERSPECTIVE:
1250 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1251 return SI_PARAM_PERSP_SAMPLE;
1252 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1253 return SI_PARAM_PERSP_CENTROID;
1254 else
1255 return SI_PARAM_PERSP_CENTER;
1256 break;
1257 default:
1258 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1259 return -1;
1260 }
1261 }
1262
1263 /* This shouldn't be used by explicit INTERP opcodes. */
1264 static unsigned select_interp_param(struct si_shader_context *ctx,
1265 unsigned param)
1266 {
1267 if (!ctx->is_monolithic)
1268 return param;
1269
1270 if (ctx->shader->key.ps.prolog.force_persp_sample_interp) {
1271 switch (param) {
1272 case SI_PARAM_PERSP_CENTROID:
1273 case SI_PARAM_PERSP_CENTER:
1274 return SI_PARAM_PERSP_SAMPLE;
1275 }
1276 }
1277 if (ctx->shader->key.ps.prolog.force_linear_sample_interp) {
1278 switch (param) {
1279 case SI_PARAM_LINEAR_CENTROID:
1280 case SI_PARAM_LINEAR_CENTER:
1281 return SI_PARAM_LINEAR_SAMPLE;
1282 }
1283 }
1284 if (ctx->shader->key.ps.prolog.force_persp_center_interp) {
1285 switch (param) {
1286 case SI_PARAM_PERSP_CENTROID:
1287 case SI_PARAM_PERSP_SAMPLE:
1288 return SI_PARAM_PERSP_CENTER;
1289 }
1290 }
1291 if (ctx->shader->key.ps.prolog.force_linear_center_interp) {
1292 switch (param) {
1293 case SI_PARAM_LINEAR_CENTROID:
1294 case SI_PARAM_LINEAR_SAMPLE:
1295 return SI_PARAM_LINEAR_CENTER;
1296 }
1297 }
1298
1299 return param;
1300 }
1301
1302 /**
1303 * Interpolate a fragment shader input.
1304 *
1305 * @param ctx context
1306 * @param input_index index of the input in hardware
1307 * @param semantic_name TGSI_SEMANTIC_*
1308 * @param semantic_index semantic index
1309 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1310 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1311 * @param interp_param interpolation weights (i,j)
1312 * @param prim_mask SI_PARAM_PRIM_MASK
1313 * @param face SI_PARAM_FRONT_FACE
1314 * @param result the return value (4 components)
1315 */
1316 static void interp_fs_input(struct si_shader_context *ctx,
1317 unsigned input_index,
1318 unsigned semantic_name,
1319 unsigned semantic_index,
1320 unsigned num_interp_inputs,
1321 unsigned colors_read_mask,
1322 LLVMValueRef interp_param,
1323 LLVMValueRef prim_mask,
1324 LLVMValueRef face,
1325 LLVMValueRef result[4])
1326 {
1327 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
1328 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1329 struct gallivm_state *gallivm = base->gallivm;
1330 const char *intr_name;
1331 LLVMValueRef attr_number;
1332
1333 unsigned chan;
1334
1335 attr_number = lp_build_const_int32(gallivm, input_index);
1336
1337 /* fs.constant returns the param from the middle vertex, so it's not
1338 * really useful for flat shading. It's meant to be used for custom
1339 * interpolation (but the intrinsic can't fetch from the other two
1340 * vertices).
1341 *
1342 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1343 * to do the right thing. The only reason we use fs.constant is that
1344 * fs.interp cannot be used on integers, because they can be equal
1345 * to NaN.
1346 */
1347 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
1348
1349 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1350 ctx->shader->key.ps.prolog.color_two_side) {
1351 LLVMValueRef args[4];
1352 LLVMValueRef is_face_positive;
1353 LLVMValueRef back_attr_number;
1354
1355 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1356 * otherwise it's at offset "num_inputs".
1357 */
1358 unsigned back_attr_offset = num_interp_inputs;
1359 if (semantic_index == 1 && colors_read_mask & 0xf)
1360 back_attr_offset += 1;
1361
1362 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1363
1364 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1365 face, uint->zero, "");
1366
1367 args[2] = prim_mask;
1368 args[3] = interp_param;
1369 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1370 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1371 LLVMValueRef front, back;
1372
1373 args[0] = llvm_chan;
1374 args[1] = attr_number;
1375 front = lp_build_intrinsic(gallivm->builder, intr_name,
1376 ctx->f32, args, args[3] ? 4 : 3,
1377 LLVMReadNoneAttribute);
1378
1379 args[1] = back_attr_number;
1380 back = lp_build_intrinsic(gallivm->builder, intr_name,
1381 ctx->f32, args, args[3] ? 4 : 3,
1382 LLVMReadNoneAttribute);
1383
1384 result[chan] = LLVMBuildSelect(gallivm->builder,
1385 is_face_positive,
1386 front,
1387 back,
1388 "");
1389 }
1390 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1391 LLVMValueRef args[4];
1392
1393 args[0] = uint->zero;
1394 args[1] = attr_number;
1395 args[2] = prim_mask;
1396 args[3] = interp_param;
1397 result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
1398 ctx->f32, args, args[3] ? 4 : 3,
1399 LLVMReadNoneAttribute);
1400 result[1] =
1401 result[2] = lp_build_const_float(gallivm, 0.0f);
1402 result[3] = lp_build_const_float(gallivm, 1.0f);
1403 } else {
1404 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1405 LLVMValueRef args[4];
1406 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1407
1408 args[0] = llvm_chan;
1409 args[1] = attr_number;
1410 args[2] = prim_mask;
1411 args[3] = interp_param;
1412 result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
1413 ctx->f32, args, args[3] ? 4 : 3,
1414 LLVMReadNoneAttribute);
1415 }
1416 }
1417 }
1418
1419 /* LLVMGetParam with bc_optimize resolved. */
1420 static LLVMValueRef get_interp_param(struct si_shader_context *ctx,
1421 int interp_param_idx)
1422 {
1423 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
1424 LLVMValueRef main_fn = ctx->radeon_bld.main_fn;
1425 LLVMValueRef param = NULL;
1426
1427 /* Handle PRIM_MASK[31] (bc_optimize). */
1428 if (ctx->is_monolithic &&
1429 ((ctx->shader->key.ps.prolog.bc_optimize_for_persp &&
1430 interp_param_idx == SI_PARAM_PERSP_CENTROID) ||
1431 (ctx->shader->key.ps.prolog.bc_optimize_for_linear &&
1432 interp_param_idx == SI_PARAM_LINEAR_CENTROID))) {
1433 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
1434 * The hw doesn't compute CENTROID if the whole wave only
1435 * contains fully-covered quads.
1436 */
1437 LLVMValueRef bc_optimize =
1438 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
1439 bc_optimize = LLVMBuildLShr(builder,
1440 bc_optimize,
1441 LLVMConstInt(ctx->i32, 31, 0), "");
1442 bc_optimize = LLVMBuildTrunc(builder, bc_optimize, ctx->i1, "");
1443
1444 if (ctx->shader->key.ps.prolog.bc_optimize_for_persp &&
1445 interp_param_idx == SI_PARAM_PERSP_CENTROID) {
1446 param = LLVMBuildSelect(builder, bc_optimize,
1447 LLVMGetParam(main_fn,
1448 SI_PARAM_PERSP_CENTER),
1449 LLVMGetParam(main_fn,
1450 SI_PARAM_PERSP_CENTROID),
1451 "");
1452 }
1453 if (ctx->shader->key.ps.prolog.bc_optimize_for_linear &&
1454 interp_param_idx == SI_PARAM_LINEAR_CENTROID) {
1455 param = LLVMBuildSelect(builder, bc_optimize,
1456 LLVMGetParam(main_fn,
1457 SI_PARAM_LINEAR_CENTER),
1458 LLVMGetParam(main_fn,
1459 SI_PARAM_LINEAR_CENTROID),
1460 "");
1461 }
1462 }
1463
1464 if (!param)
1465 param = LLVMGetParam(main_fn, interp_param_idx);
1466 return param;
1467 }
1468
1469 static void declare_input_fs(
1470 struct radeon_llvm_context *radeon_bld,
1471 unsigned input_index,
1472 const struct tgsi_full_declaration *decl)
1473 {
1474 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
1475 struct si_shader_context *ctx =
1476 si_shader_context(&radeon_bld->soa.bld_base);
1477 struct si_shader *shader = ctx->shader;
1478 LLVMValueRef main_fn = radeon_bld->main_fn;
1479 LLVMValueRef interp_param = NULL;
1480 int interp_param_idx;
1481
1482 /* Get colors from input VGPRs (set by the prolog). */
1483 if (!ctx->is_monolithic &&
1484 decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1485 unsigned i = decl->Semantic.Index;
1486 unsigned colors_read = shader->selector->info.colors_read;
1487 unsigned mask = colors_read >> (i * 4);
1488 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1489 (i ? util_bitcount(colors_read & 0xf) : 0);
1490
1491 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
1492 mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1493 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
1494 mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1495 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
1496 mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1497 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
1498 mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1499 return;
1500 }
1501
1502 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1503 decl->Interp.Location);
1504 if (interp_param_idx == -1)
1505 return;
1506 else if (interp_param_idx) {
1507 interp_param_idx = select_interp_param(ctx,
1508 interp_param_idx);
1509 interp_param = get_interp_param(ctx, interp_param_idx);
1510 }
1511
1512 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
1513 decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR &&
1514 ctx->shader->key.ps.prolog.flatshade_colors)
1515 interp_param = NULL; /* load the constant color */
1516
1517 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1518 decl->Semantic.Index, shader->selector->info.num_inputs,
1519 shader->selector->info.colors_read, interp_param,
1520 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1521 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1522 &radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)]);
1523 }
1524
1525 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1526 {
1527 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1528 SI_PARAM_ANCILLARY, 8, 4);
1529 }
1530
1531 /**
1532 * Set range metadata on an instruction. This can only be used on load and
1533 * call instructions. If you know an instruction can only produce the values
1534 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1535 * \p lo is the minimum value inclusive.
1536 * \p hi is the maximum value exclusive.
1537 */
1538 static void set_range_metadata(struct si_shader_context *ctx,
1539 LLVMValueRef value, unsigned lo, unsigned hi)
1540 {
1541 LLVMValueRef range_md, md_args[2];
1542 LLVMTypeRef type = LLVMTypeOf(value);
1543 LLVMContextRef context = LLVMGetTypeContext(type);
1544
1545 md_args[0] = LLVMConstInt(type, lo, false);
1546 md_args[1] = LLVMConstInt(type, hi, false);
1547 range_md = LLVMMDNodeInContext(context, md_args, 2);
1548 LLVMSetMetadata(value, ctx->range_md_kind, range_md);
1549 }
1550
1551 static LLVMValueRef get_thread_id(struct si_shader_context *ctx)
1552 {
1553 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1554 LLVMValueRef tid;
1555
1556 if (HAVE_LLVM < 0x0308) {
1557 tid = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid",
1558 ctx->i32, NULL, 0, LLVMReadNoneAttribute);
1559 } else {
1560 LLVMValueRef tid_args[2];
1561 tid_args[0] = lp_build_const_int32(gallivm, 0xffffffff);
1562 tid_args[1] = lp_build_const_int32(gallivm, 0);
1563 tid_args[1] = lp_build_intrinsic(gallivm->builder,
1564 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1565 tid_args, 2, LLVMReadNoneAttribute);
1566
1567 tid = lp_build_intrinsic(gallivm->builder,
1568 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1569 tid_args, 2, LLVMReadNoneAttribute);
1570 }
1571 set_range_metadata(ctx, tid, 0, 64);
1572 return tid;
1573 }
1574
1575 /**
1576 * Load a dword from a constant buffer.
1577 */
1578 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1579 LLVMValueRef resource,
1580 LLVMValueRef offset)
1581 {
1582 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
1583 LLVMValueRef args[2] = {resource, offset};
1584
1585 return lp_build_intrinsic(builder, "llvm.SI.load.const", ctx->f32, args, 2,
1586 LLVMReadNoneAttribute);
1587 }
1588
1589 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1590 {
1591 struct si_shader_context *ctx =
1592 si_shader_context(&radeon_bld->soa.bld_base);
1593 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1594 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1595 LLVMBuilderRef builder = gallivm->builder;
1596 LLVMValueRef desc = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1597 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1598 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1599
1600 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1601 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1602 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1603
1604 LLVMValueRef pos[4] = {
1605 buffer_load_const(ctx, resource, offset0),
1606 buffer_load_const(ctx, resource, offset1),
1607 lp_build_const_float(gallivm, 0),
1608 lp_build_const_float(gallivm, 0)
1609 };
1610
1611 return lp_build_gather_values(gallivm, pos, 4);
1612 }
1613
1614 static void declare_system_value(
1615 struct radeon_llvm_context *radeon_bld,
1616 unsigned index,
1617 const struct tgsi_full_declaration *decl)
1618 {
1619 struct si_shader_context *ctx =
1620 si_shader_context(&radeon_bld->soa.bld_base);
1621 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1622 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1623 LLVMValueRef value = 0;
1624
1625 switch (decl->Semantic.Name) {
1626 case TGSI_SEMANTIC_INSTANCEID:
1627 value = LLVMGetParam(radeon_bld->main_fn,
1628 ctx->param_instance_id);
1629 break;
1630
1631 case TGSI_SEMANTIC_VERTEXID:
1632 value = LLVMBuildAdd(gallivm->builder,
1633 LLVMGetParam(radeon_bld->main_fn,
1634 ctx->param_vertex_id),
1635 LLVMGetParam(radeon_bld->main_fn,
1636 SI_PARAM_BASE_VERTEX), "");
1637 break;
1638
1639 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1640 value = LLVMGetParam(radeon_bld->main_fn,
1641 ctx->param_vertex_id);
1642 break;
1643
1644 case TGSI_SEMANTIC_BASEVERTEX:
1645 value = LLVMGetParam(radeon_bld->main_fn,
1646 SI_PARAM_BASE_VERTEX);
1647 break;
1648
1649 case TGSI_SEMANTIC_BASEINSTANCE:
1650 value = LLVMGetParam(radeon_bld->main_fn,
1651 SI_PARAM_START_INSTANCE);
1652 break;
1653
1654 case TGSI_SEMANTIC_DRAWID:
1655 value = LLVMGetParam(radeon_bld->main_fn,
1656 SI_PARAM_DRAWID);
1657 break;
1658
1659 case TGSI_SEMANTIC_INVOCATIONID:
1660 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1661 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1662 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1663 value = LLVMGetParam(radeon_bld->main_fn,
1664 SI_PARAM_GS_INSTANCE_ID);
1665 else
1666 assert(!"INVOCATIONID not implemented");
1667 break;
1668
1669 case TGSI_SEMANTIC_POSITION:
1670 {
1671 LLVMValueRef pos[4] = {
1672 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1673 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1674 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1675 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1676 LLVMGetParam(radeon_bld->main_fn,
1677 SI_PARAM_POS_W_FLOAT)),
1678 };
1679 value = lp_build_gather_values(gallivm, pos, 4);
1680 break;
1681 }
1682
1683 case TGSI_SEMANTIC_FACE:
1684 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1685 break;
1686
1687 case TGSI_SEMANTIC_SAMPLEID:
1688 value = get_sample_id(radeon_bld);
1689 break;
1690
1691 case TGSI_SEMANTIC_SAMPLEPOS: {
1692 LLVMValueRef pos[4] = {
1693 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1694 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1695 lp_build_const_float(gallivm, 0),
1696 lp_build_const_float(gallivm, 0)
1697 };
1698 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1699 TGSI_OPCODE_FRC, pos[0]);
1700 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1701 TGSI_OPCODE_FRC, pos[1]);
1702 value = lp_build_gather_values(gallivm, pos, 4);
1703 break;
1704 }
1705
1706 case TGSI_SEMANTIC_SAMPLEMASK:
1707 /* This can only occur with the OpenGL Core profile, which
1708 * doesn't support smoothing.
1709 */
1710 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1711 break;
1712
1713 case TGSI_SEMANTIC_TESSCOORD:
1714 {
1715 LLVMValueRef coord[4] = {
1716 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1717 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1718 bld->zero,
1719 bld->zero
1720 };
1721
1722 /* For triangles, the vector should be (u, v, 1-u-v). */
1723 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1724 PIPE_PRIM_TRIANGLES)
1725 coord[2] = lp_build_sub(bld, bld->one,
1726 lp_build_add(bld, coord[0], coord[1]));
1727
1728 value = lp_build_gather_values(gallivm, coord, 4);
1729 break;
1730 }
1731
1732 case TGSI_SEMANTIC_VERTICESIN:
1733 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1734 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1735 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1736 value = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 7);
1737 else
1738 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1739 break;
1740
1741 case TGSI_SEMANTIC_TESSINNER:
1742 case TGSI_SEMANTIC_TESSOUTER:
1743 {
1744 LLVMValueRef rw_buffers, buffer, base, addr;
1745 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1746
1747 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1748 SI_PARAM_RW_BUFFERS);
1749 buffer = build_indexed_load_const(ctx, rw_buffers,
1750 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1751
1752 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1753 addr = get_tcs_tes_buffer_address(ctx, NULL,
1754 lp_build_const_int32(gallivm, param));
1755
1756 value = buffer_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1757 ~0, buffer, base, addr);
1758
1759 break;
1760 }
1761
1762 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1763 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1764 {
1765 LLVMValueRef buf, slot, val[4];
1766 int i, offset;
1767
1768 slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
1769 buf = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1770 buf = build_indexed_load_const(ctx, buf, slot);
1771 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1772
1773 for (i = 0; i < 4; i++)
1774 val[i] = buffer_load_const(ctx, buf,
1775 lp_build_const_int32(gallivm, (offset + i) * 4));
1776 value = lp_build_gather_values(gallivm, val, 4);
1777 break;
1778 }
1779
1780 case TGSI_SEMANTIC_PRIMID:
1781 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1782 break;
1783
1784 case TGSI_SEMANTIC_GRID_SIZE:
1785 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1786 break;
1787
1788 case TGSI_SEMANTIC_BLOCK_SIZE:
1789 {
1790 LLVMValueRef values[3];
1791 unsigned i;
1792 unsigned *properties = ctx->shader->selector->info.properties;
1793 unsigned sizes[3] = {
1794 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1795 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1796 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1797 };
1798
1799 for (i = 0; i < 3; ++i)
1800 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1801
1802 value = lp_build_gather_values(gallivm, values, 3);
1803 break;
1804 }
1805
1806 case TGSI_SEMANTIC_BLOCK_ID:
1807 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1808 break;
1809
1810 case TGSI_SEMANTIC_THREAD_ID:
1811 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1812 break;
1813
1814 #if HAVE_LLVM >= 0x0309
1815 case TGSI_SEMANTIC_HELPER_INVOCATION:
1816 value = lp_build_intrinsic(gallivm->builder,
1817 "llvm.amdgcn.ps.live",
1818 ctx->i1, NULL, 0,
1819 LLVMReadNoneAttribute);
1820 value = LLVMBuildNot(gallivm->builder, value, "");
1821 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1822 break;
1823 #endif
1824
1825 default:
1826 assert(!"unknown system value");
1827 return;
1828 }
1829
1830 radeon_bld->system_values[index] = value;
1831 }
1832
1833 static void declare_compute_memory(struct radeon_llvm_context *radeon_bld,
1834 const struct tgsi_full_declaration *decl)
1835 {
1836 struct si_shader_context *ctx =
1837 si_shader_context(&radeon_bld->soa.bld_base);
1838 struct si_shader_selector *sel = ctx->shader->selector;
1839 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1840
1841 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1842 LLVMValueRef var;
1843
1844 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1845 assert(decl->Range.First == decl->Range.Last);
1846 assert(!ctx->shared_memory);
1847
1848 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1849 LLVMArrayType(ctx->i8, sel->local_size),
1850 "compute_lds",
1851 LOCAL_ADDR_SPACE);
1852 LLVMSetAlignment(var, 4);
1853
1854 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1855 }
1856
1857 static LLVMValueRef fetch_constant(
1858 struct lp_build_tgsi_context *bld_base,
1859 const struct tgsi_full_src_register *reg,
1860 enum tgsi_opcode_type type,
1861 unsigned swizzle)
1862 {
1863 struct si_shader_context *ctx = si_shader_context(bld_base);
1864 struct lp_build_context *base = &bld_base->base;
1865 const struct tgsi_ind_register *ireg = &reg->Indirect;
1866 unsigned buf, idx;
1867
1868 LLVMValueRef addr, bufp;
1869 LLVMValueRef result;
1870
1871 if (swizzle == LP_CHAN_ALL) {
1872 unsigned chan;
1873 LLVMValueRef values[4];
1874 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1875 values[chan] = fetch_constant(bld_base, reg, type, chan);
1876
1877 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1878 }
1879
1880 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1881 idx = reg->Register.Index * 4 + swizzle;
1882
1883 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1884 LLVMValueRef c0, c1;
1885
1886 c0 = buffer_load_const(ctx, ctx->const_buffers[buf],
1887 LLVMConstInt(ctx->i32, idx * 4, 0));
1888
1889 if (!tgsi_type_is_64bit(type))
1890 return bitcast(bld_base, type, c0);
1891 else {
1892 c1 = buffer_load_const(ctx, ctx->const_buffers[buf],
1893 LLVMConstInt(ctx->i32,
1894 (idx + 1) * 4, 0));
1895 return radeon_llvm_emit_fetch_64bit(bld_base, type,
1896 c0, c1);
1897 }
1898 }
1899
1900 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1901 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1902 LLVMValueRef index;
1903 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1904 reg->Dimension.Index,
1905 SI_NUM_CONST_BUFFERS);
1906 bufp = build_indexed_load_const(ctx, ptr, index);
1907 } else
1908 bufp = ctx->const_buffers[buf];
1909
1910 addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1911 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1912 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1913 addr = lp_build_add(&bld_base->uint_bld, addr,
1914 lp_build_const_int32(base->gallivm, idx * 4));
1915
1916 result = buffer_load_const(ctx, bufp, addr);
1917
1918 if (!tgsi_type_is_64bit(type))
1919 result = bitcast(bld_base, type, result);
1920 else {
1921 LLVMValueRef addr2, result2;
1922 addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1923 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1924 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1925 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1926 lp_build_const_int32(base->gallivm, idx * 4));
1927
1928 result2 = buffer_load_const(ctx, bufp, addr2);
1929
1930 result = radeon_llvm_emit_fetch_64bit(bld_base, type,
1931 result, result2);
1932 }
1933 return result;
1934 }
1935
1936 /* Upper 16 bits must be zero. */
1937 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1938 LLVMValueRef val[2])
1939 {
1940 return LLVMBuildOr(gallivm->builder, val[0],
1941 LLVMBuildShl(gallivm->builder, val[1],
1942 lp_build_const_int32(gallivm, 16),
1943 ""), "");
1944 }
1945
1946 /* Upper 16 bits are ignored and will be dropped. */
1947 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1948 LLVMValueRef val[2])
1949 {
1950 LLVMValueRef v[2] = {
1951 LLVMBuildAnd(gallivm->builder, val[0],
1952 lp_build_const_int32(gallivm, 0xffff), ""),
1953 val[1],
1954 };
1955 return si_llvm_pack_two_int16(gallivm, v);
1956 }
1957
1958 /* Initialize arguments for the shader export intrinsic */
1959 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1960 LLVMValueRef *values,
1961 unsigned target,
1962 LLVMValueRef *args)
1963 {
1964 struct si_shader_context *ctx = si_shader_context(bld_base);
1965 struct lp_build_context *uint =
1966 &ctx->radeon_bld.soa.bld_base.uint_bld;
1967 struct lp_build_context *base = &bld_base->base;
1968 struct gallivm_state *gallivm = base->gallivm;
1969 LLVMBuilderRef builder = base->gallivm->builder;
1970 LLVMValueRef val[4];
1971 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1972 unsigned chan;
1973 bool is_int8;
1974
1975 /* Default is 0xf. Adjusted below depending on the format. */
1976 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1977
1978 /* Specify whether the EXEC mask represents the valid mask */
1979 args[1] = uint->zero;
1980
1981 /* Specify whether this is the last export */
1982 args[2] = uint->zero;
1983
1984 /* Specify the target we are exporting */
1985 args[3] = lp_build_const_int32(base->gallivm, target);
1986
1987 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1988 const union si_shader_key *key = &ctx->shader->key;
1989 unsigned col_formats = key->ps.epilog.spi_shader_col_format;
1990 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1991
1992 assert(cbuf >= 0 && cbuf < 8);
1993 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1994 is_int8 = (key->ps.epilog.color_is_int8 >> cbuf) & 0x1;
1995 }
1996
1997 args[4] = uint->zero; /* COMPR flag */
1998 args[5] = base->undef;
1999 args[6] = base->undef;
2000 args[7] = base->undef;
2001 args[8] = base->undef;
2002
2003 switch (spi_shader_col_format) {
2004 case V_028714_SPI_SHADER_ZERO:
2005 args[0] = uint->zero; /* writemask */
2006 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2007 break;
2008
2009 case V_028714_SPI_SHADER_32_R:
2010 args[0] = uint->one; /* writemask */
2011 args[5] = values[0];
2012 break;
2013
2014 case V_028714_SPI_SHADER_32_GR:
2015 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
2016 args[5] = values[0];
2017 args[6] = values[1];
2018 break;
2019
2020 case V_028714_SPI_SHADER_32_AR:
2021 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
2022 args[5] = values[0];
2023 args[8] = values[3];
2024 break;
2025
2026 case V_028714_SPI_SHADER_FP16_ABGR:
2027 args[4] = uint->one; /* COMPR flag */
2028
2029 for (chan = 0; chan < 2; chan++) {
2030 LLVMValueRef pack_args[2] = {
2031 values[2 * chan],
2032 values[2 * chan + 1]
2033 };
2034 LLVMValueRef packed;
2035
2036 packed = lp_build_intrinsic(base->gallivm->builder,
2037 "llvm.SI.packf16",
2038 ctx->i32, pack_args, 2,
2039 LLVMReadNoneAttribute);
2040 args[chan + 5] =
2041 LLVMBuildBitCast(base->gallivm->builder,
2042 packed, ctx->f32, "");
2043 }
2044 break;
2045
2046 case V_028714_SPI_SHADER_UNORM16_ABGR:
2047 for (chan = 0; chan < 4; chan++) {
2048 val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
2049 val[chan] = LLVMBuildFMul(builder, val[chan],
2050 lp_build_const_float(gallivm, 65535), "");
2051 val[chan] = LLVMBuildFAdd(builder, val[chan],
2052 lp_build_const_float(gallivm, 0.5), "");
2053 val[chan] = LLVMBuildFPToUI(builder, val[chan],
2054 ctx->i32, "");
2055 }
2056
2057 args[4] = uint->one; /* COMPR flag */
2058 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2059 si_llvm_pack_two_int16(gallivm, val));
2060 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2061 si_llvm_pack_two_int16(gallivm, val+2));
2062 break;
2063
2064 case V_028714_SPI_SHADER_SNORM16_ABGR:
2065 for (chan = 0; chan < 4; chan++) {
2066 /* Clamp between [-1, 1]. */
2067 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
2068 values[chan],
2069 lp_build_const_float(gallivm, 1));
2070 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
2071 val[chan],
2072 lp_build_const_float(gallivm, -1));
2073 /* Convert to a signed integer in [-32767, 32767]. */
2074 val[chan] = LLVMBuildFMul(builder, val[chan],
2075 lp_build_const_float(gallivm, 32767), "");
2076 /* If positive, add 0.5, else add -0.5. */
2077 val[chan] = LLVMBuildFAdd(builder, val[chan],
2078 LLVMBuildSelect(builder,
2079 LLVMBuildFCmp(builder, LLVMRealOGE,
2080 val[chan], base->zero, ""),
2081 lp_build_const_float(gallivm, 0.5),
2082 lp_build_const_float(gallivm, -0.5), ""), "");
2083 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2084 }
2085
2086 args[4] = uint->one; /* COMPR flag */
2087 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2088 si_llvm_pack_two_int32_as_int16(gallivm, val));
2089 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2090 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2091 break;
2092
2093 case V_028714_SPI_SHADER_UINT16_ABGR: {
2094 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2095 255 : 65535);
2096 /* Clamp. */
2097 for (chan = 0; chan < 4; chan++) {
2098 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2099 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
2100 val[chan], max);
2101 }
2102
2103 args[4] = uint->one; /* COMPR flag */
2104 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2105 si_llvm_pack_two_int16(gallivm, val));
2106 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2107 si_llvm_pack_two_int16(gallivm, val+2));
2108 break;
2109 }
2110
2111 case V_028714_SPI_SHADER_SINT16_ABGR: {
2112 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2113 127 : 32767);
2114 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
2115 -128 : -32768);
2116 /* Clamp. */
2117 for (chan = 0; chan < 4; chan++) {
2118 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2119 val[chan] = lp_build_emit_llvm_binary(bld_base,
2120 TGSI_OPCODE_IMIN,
2121 val[chan], max);
2122 val[chan] = lp_build_emit_llvm_binary(bld_base,
2123 TGSI_OPCODE_IMAX,
2124 val[chan], min);
2125 }
2126
2127 args[4] = uint->one; /* COMPR flag */
2128 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2129 si_llvm_pack_two_int32_as_int16(gallivm, val));
2130 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2131 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2132 break;
2133 }
2134
2135 case V_028714_SPI_SHADER_32_ABGR:
2136 memcpy(&args[5], values, sizeof(values[0]) * 4);
2137 break;
2138 }
2139 }
2140
2141 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2142 LLVMValueRef alpha)
2143 {
2144 struct si_shader_context *ctx = si_shader_context(bld_base);
2145 struct gallivm_state *gallivm = bld_base->base.gallivm;
2146
2147 if (ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2148 LLVMValueRef alpha_ref = LLVMGetParam(ctx->radeon_bld.main_fn,
2149 SI_PARAM_ALPHA_REF);
2150
2151 LLVMValueRef alpha_pass =
2152 lp_build_cmp(&bld_base->base,
2153 ctx->shader->key.ps.epilog.alpha_func,
2154 alpha, alpha_ref);
2155 LLVMValueRef arg =
2156 lp_build_select(&bld_base->base,
2157 alpha_pass,
2158 lp_build_const_float(gallivm, 1.0f),
2159 lp_build_const_float(gallivm, -1.0f));
2160
2161 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2162 ctx->voidt, &arg, 1, 0);
2163 } else {
2164 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
2165 ctx->voidt, NULL, 0, 0);
2166 }
2167 }
2168
2169 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2170 LLVMValueRef alpha,
2171 unsigned samplemask_param)
2172 {
2173 struct si_shader_context *ctx = si_shader_context(bld_base);
2174 struct gallivm_state *gallivm = bld_base->base.gallivm;
2175 LLVMValueRef coverage;
2176
2177 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2178 coverage = LLVMGetParam(ctx->radeon_bld.main_fn,
2179 samplemask_param);
2180 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
2181
2182 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
2183 ctx->i32,
2184 &coverage, 1, LLVMReadNoneAttribute);
2185
2186 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
2187 ctx->f32, "");
2188
2189 coverage = LLVMBuildFMul(gallivm->builder, coverage,
2190 lp_build_const_float(gallivm,
2191 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2192
2193 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
2194 }
2195
2196 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2197 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
2198 {
2199 struct si_shader_context *ctx = si_shader_context(bld_base);
2200 struct lp_build_context *base = &bld_base->base;
2201 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
2202 unsigned reg_index;
2203 unsigned chan;
2204 unsigned const_chan;
2205 LLVMValueRef base_elt;
2206 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
2207 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
2208 SI_VS_CONST_CLIP_PLANES);
2209 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
2210
2211 for (reg_index = 0; reg_index < 2; reg_index ++) {
2212 LLVMValueRef *args = pos[2 + reg_index];
2213
2214 args[5] =
2215 args[6] =
2216 args[7] =
2217 args[8] = lp_build_const_float(base->gallivm, 0.0f);
2218
2219 /* Compute dot products of position and user clip plane vectors */
2220 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2221 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2222 args[1] = lp_build_const_int32(base->gallivm,
2223 ((reg_index * 4 + chan) * 4 +
2224 const_chan) * 4);
2225 base_elt = buffer_load_const(ctx, const_resource,
2226 args[1]);
2227 args[5 + chan] =
2228 lp_build_add(base, args[5 + chan],
2229 lp_build_mul(base, base_elt,
2230 out_elts[const_chan]));
2231 }
2232 }
2233
2234 args[0] = lp_build_const_int32(base->gallivm, 0xf);
2235 args[1] = uint->zero;
2236 args[2] = uint->zero;
2237 args[3] = lp_build_const_int32(base->gallivm,
2238 V_008DFC_SQ_EXP_POS + 2 + reg_index);
2239 args[4] = uint->zero;
2240 }
2241 }
2242
2243 static void si_dump_streamout(struct pipe_stream_output_info *so)
2244 {
2245 unsigned i;
2246
2247 if (so->num_outputs)
2248 fprintf(stderr, "STREAMOUT\n");
2249
2250 for (i = 0; i < so->num_outputs; i++) {
2251 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2252 so->output[i].start_component;
2253 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2254 i, so->output[i].output_buffer,
2255 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2256 so->output[i].register_index,
2257 mask & 1 ? "x" : "",
2258 mask & 2 ? "y" : "",
2259 mask & 4 ? "z" : "",
2260 mask & 8 ? "w" : "");
2261 }
2262 }
2263
2264 /* On SI, the vertex shader is responsible for writing streamout data
2265 * to buffers. */
2266 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2267 struct si_shader_output_values *outputs,
2268 unsigned noutput)
2269 {
2270 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
2271 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
2272 LLVMBuilderRef builder = gallivm->builder;
2273 int i, j;
2274 struct lp_build_if_state if_ctx;
2275 LLVMValueRef so_buffers[4];
2276 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
2277 SI_PARAM_RW_BUFFERS);
2278
2279 /* Load the descriptors. */
2280 for (i = 0; i < 4; ++i) {
2281 if (ctx->shader->selector->so.stride[i]) {
2282 LLVMValueRef offset = lp_build_const_int32(gallivm,
2283 SI_VS_STREAMOUT_BUF0 + i);
2284
2285 so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
2286 }
2287 }
2288
2289 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2290 LLVMValueRef so_vtx_count =
2291 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2292
2293 LLVMValueRef tid = get_thread_id(ctx);
2294
2295 /* can_emit = tid < so_vtx_count; */
2296 LLVMValueRef can_emit =
2297 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2298
2299 LLVMValueRef stream_id =
2300 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
2301
2302 /* Emit the streamout code conditionally. This actually avoids
2303 * out-of-bounds buffer access. The hw tells us via the SGPR
2304 * (so_vtx_count) which threads are allowed to emit streamout data. */
2305 lp_build_if(&if_ctx, gallivm, can_emit);
2306 {
2307 /* The buffer offset is computed as follows:
2308 * ByteOffset = streamout_offset[buffer_id]*4 +
2309 * (streamout_write_index + thread_id)*stride[buffer_id] +
2310 * attrib_offset
2311 */
2312
2313 LLVMValueRef so_write_index =
2314 LLVMGetParam(ctx->radeon_bld.main_fn,
2315 ctx->param_streamout_write_index);
2316
2317 /* Compute (streamout_write_index + thread_id). */
2318 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2319
2320 /* Compute the write offset for each enabled buffer. */
2321 LLVMValueRef so_write_offset[4] = {};
2322 for (i = 0; i < 4; i++) {
2323 if (!so->stride[i])
2324 continue;
2325
2326 LLVMValueRef so_offset = LLVMGetParam(ctx->radeon_bld.main_fn,
2327 ctx->param_streamout_offset[i]);
2328 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2329
2330 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2331 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2332 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2333 }
2334
2335 /* Write streamout data. */
2336 for (i = 0; i < so->num_outputs; i++) {
2337 unsigned buf_idx = so->output[i].output_buffer;
2338 unsigned reg = so->output[i].register_index;
2339 unsigned start = so->output[i].start_component;
2340 unsigned num_comps = so->output[i].num_components;
2341 unsigned stream = so->output[i].stream;
2342 LLVMValueRef out[4];
2343 struct lp_build_if_state if_ctx_stream;
2344
2345 assert(num_comps && num_comps <= 4);
2346 if (!num_comps || num_comps > 4)
2347 continue;
2348
2349 if (reg >= noutput)
2350 continue;
2351
2352 /* Load the output as int. */
2353 for (j = 0; j < num_comps; j++) {
2354 out[j] = LLVMBuildBitCast(builder,
2355 outputs[reg].values[start+j],
2356 ctx->i32, "");
2357 }
2358
2359 /* Pack the output. */
2360 LLVMValueRef vdata = NULL;
2361
2362 switch (num_comps) {
2363 case 1: /* as i32 */
2364 vdata = out[0];
2365 break;
2366 case 2: /* as v2i32 */
2367 case 3: /* as v4i32 (aligned to 4) */
2368 case 4: /* as v4i32 */
2369 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2370 for (j = 0; j < num_comps; j++) {
2371 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2372 LLVMConstInt(ctx->i32, j, 0), "");
2373 }
2374 break;
2375 }
2376
2377 LLVMValueRef can_emit_stream =
2378 LLVMBuildICmp(builder, LLVMIntEQ,
2379 stream_id,
2380 lp_build_const_int32(gallivm, stream), "");
2381
2382 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
2383 build_tbuffer_store_dwords(ctx, so_buffers[buf_idx],
2384 vdata, num_comps,
2385 so_write_offset[buf_idx],
2386 LLVMConstInt(ctx->i32, 0, 0),
2387 so->output[i].dst_offset*4);
2388 lp_build_endif(&if_ctx_stream);
2389 }
2390 }
2391 lp_build_endif(&if_ctx);
2392 }
2393
2394
2395 /* Generate export instructions for hardware VS shader stage */
2396 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2397 struct si_shader_output_values *outputs,
2398 unsigned noutput)
2399 {
2400 struct si_shader_context *ctx = si_shader_context(bld_base);
2401 struct si_shader *shader = ctx->shader;
2402 struct lp_build_context *base = &bld_base->base;
2403 struct lp_build_context *uint =
2404 &ctx->radeon_bld.soa.bld_base.uint_bld;
2405 LLVMValueRef args[9];
2406 LLVMValueRef pos_args[4][9] = { { 0 } };
2407 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2408 unsigned semantic_name, semantic_index;
2409 unsigned target;
2410 unsigned param_count = 0;
2411 unsigned pos_idx;
2412 int i;
2413
2414 if (outputs && ctx->shader->selector->so.num_outputs) {
2415 si_llvm_emit_streamout(ctx, outputs, noutput);
2416 }
2417
2418 for (i = 0; i < noutput; i++) {
2419 semantic_name = outputs[i].name;
2420 semantic_index = outputs[i].sid;
2421
2422 handle_semantic:
2423 /* Select the correct target */
2424 switch(semantic_name) {
2425 case TGSI_SEMANTIC_PSIZE:
2426 psize_value = outputs[i].values[0];
2427 continue;
2428 case TGSI_SEMANTIC_EDGEFLAG:
2429 edgeflag_value = outputs[i].values[0];
2430 continue;
2431 case TGSI_SEMANTIC_LAYER:
2432 layer_value = outputs[i].values[0];
2433 semantic_name = TGSI_SEMANTIC_GENERIC;
2434 goto handle_semantic;
2435 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2436 viewport_index_value = outputs[i].values[0];
2437 semantic_name = TGSI_SEMANTIC_GENERIC;
2438 goto handle_semantic;
2439 case TGSI_SEMANTIC_POSITION:
2440 target = V_008DFC_SQ_EXP_POS;
2441 break;
2442 case TGSI_SEMANTIC_COLOR:
2443 case TGSI_SEMANTIC_BCOLOR:
2444 target = V_008DFC_SQ_EXP_PARAM + param_count;
2445 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2446 shader->info.vs_output_param_offset[i] = param_count;
2447 param_count++;
2448 break;
2449 case TGSI_SEMANTIC_CLIPDIST:
2450 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2451 break;
2452 case TGSI_SEMANTIC_CLIPVERTEX:
2453 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2454 continue;
2455 case TGSI_SEMANTIC_PRIMID:
2456 case TGSI_SEMANTIC_FOG:
2457 case TGSI_SEMANTIC_TEXCOORD:
2458 case TGSI_SEMANTIC_GENERIC:
2459 target = V_008DFC_SQ_EXP_PARAM + param_count;
2460 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2461 shader->info.vs_output_param_offset[i] = param_count;
2462 param_count++;
2463 break;
2464 default:
2465 target = 0;
2466 fprintf(stderr,
2467 "Warning: SI unhandled vs output type:%d\n",
2468 semantic_name);
2469 }
2470
2471 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
2472
2473 if (target >= V_008DFC_SQ_EXP_POS &&
2474 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2475 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
2476 args, sizeof(args));
2477 } else {
2478 lp_build_intrinsic(base->gallivm->builder,
2479 "llvm.SI.export", ctx->voidt,
2480 args, 9, 0);
2481 }
2482
2483 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2484 semantic_name = TGSI_SEMANTIC_GENERIC;
2485 goto handle_semantic;
2486 }
2487 }
2488
2489 shader->info.nr_param_exports = param_count;
2490
2491 /* We need to add the position output manually if it's missing. */
2492 if (!pos_args[0][0]) {
2493 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
2494 pos_args[0][1] = uint->zero; /* EXEC mask */
2495 pos_args[0][2] = uint->zero; /* last export? */
2496 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
2497 pos_args[0][4] = uint->zero; /* COMPR flag */
2498 pos_args[0][5] = base->zero; /* X */
2499 pos_args[0][6] = base->zero; /* Y */
2500 pos_args[0][7] = base->zero; /* Z */
2501 pos_args[0][8] = base->one; /* W */
2502 }
2503
2504 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2505 if (shader->selector->info.writes_psize ||
2506 shader->selector->info.writes_edgeflag ||
2507 shader->selector->info.writes_viewport_index ||
2508 shader->selector->info.writes_layer) {
2509 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
2510 shader->selector->info.writes_psize |
2511 (shader->selector->info.writes_edgeflag << 1) |
2512 (shader->selector->info.writes_layer << 2) |
2513 (shader->selector->info.writes_viewport_index << 3));
2514 pos_args[1][1] = uint->zero; /* EXEC mask */
2515 pos_args[1][2] = uint->zero; /* last export? */
2516 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
2517 pos_args[1][4] = uint->zero; /* COMPR flag */
2518 pos_args[1][5] = base->zero; /* X */
2519 pos_args[1][6] = base->zero; /* Y */
2520 pos_args[1][7] = base->zero; /* Z */
2521 pos_args[1][8] = base->zero; /* W */
2522
2523 if (shader->selector->info.writes_psize)
2524 pos_args[1][5] = psize_value;
2525
2526 if (shader->selector->info.writes_edgeflag) {
2527 /* The output is a float, but the hw expects an integer
2528 * with the first bit containing the edge flag. */
2529 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2530 edgeflag_value,
2531 ctx->i32, "");
2532 edgeflag_value = lp_build_min(&bld_base->int_bld,
2533 edgeflag_value,
2534 bld_base->int_bld.one);
2535
2536 /* The LLVM intrinsic expects a float. */
2537 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
2538 edgeflag_value,
2539 ctx->f32, "");
2540 }
2541
2542 if (shader->selector->info.writes_layer)
2543 pos_args[1][7] = layer_value;
2544
2545 if (shader->selector->info.writes_viewport_index)
2546 pos_args[1][8] = viewport_index_value;
2547 }
2548
2549 for (i = 0; i < 4; i++)
2550 if (pos_args[i][0])
2551 shader->info.nr_pos_exports++;
2552
2553 pos_idx = 0;
2554 for (i = 0; i < 4; i++) {
2555 if (!pos_args[i][0])
2556 continue;
2557
2558 /* Specify the target we are exporting */
2559 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2560
2561 if (pos_idx == shader->info.nr_pos_exports)
2562 /* Specify that this is the last export */
2563 pos_args[i][2] = uint->one;
2564
2565 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2566 ctx->voidt, pos_args[i], 9, 0);
2567 }
2568 }
2569
2570 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2571 {
2572 struct si_shader_context *ctx = si_shader_context(bld_base);
2573 struct gallivm_state *gallivm = bld_base->base.gallivm;
2574 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2575 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2576 uint64_t inputs;
2577
2578 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2579
2580 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
2581 buffer = build_indexed_load_const(ctx, rw_buffers,
2582 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
2583
2584 buffer_offset = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
2585
2586 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
2587 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2588 lds_vertex_stride, "");
2589 lds_base = get_tcs_in_current_patch_offset(ctx);
2590 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2591
2592 inputs = ctx->shader->key.tcs.epilog.inputs_to_copy;
2593 while (inputs) {
2594 unsigned i = u_bit_scan64(&inputs);
2595
2596 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2597 lp_build_const_int32(gallivm, 4 * i),
2598 "");
2599
2600 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2601 invocation_id,
2602 lp_build_const_int32(gallivm, i));
2603
2604 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2605 lds_ptr);
2606
2607 build_tbuffer_store_dwords(ctx, buffer, value, 4, buffer_addr,
2608 buffer_offset, 0);
2609 }
2610 }
2611
2612 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2613 LLVMValueRef rel_patch_id,
2614 LLVMValueRef invocation_id,
2615 LLVMValueRef tcs_out_current_patch_data_offset)
2616 {
2617 struct si_shader_context *ctx = si_shader_context(bld_base);
2618 struct gallivm_state *gallivm = bld_base->base.gallivm;
2619 struct si_shader *shader = ctx->shader;
2620 unsigned tess_inner_index, tess_outer_index;
2621 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2622 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2623 unsigned stride, outer_comps, inner_comps, i;
2624 struct lp_build_if_state if_ctx, inner_if_ctx;
2625
2626 si_llvm_emit_barrier(NULL, bld_base, NULL);
2627
2628 /* Do this only for invocation 0, because the tess levels are per-patch,
2629 * not per-vertex.
2630 *
2631 * This can't jump, because invocation 0 executes this. It should
2632 * at least mask out the loads and stores for other invocations.
2633 */
2634 lp_build_if(&if_ctx, gallivm,
2635 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2636 invocation_id, bld_base->uint_bld.zero, ""));
2637
2638 /* Determine the layout of one tess factor element in the buffer. */
2639 switch (shader->key.tcs.epilog.prim_mode) {
2640 case PIPE_PRIM_LINES:
2641 stride = 2; /* 2 dwords, 1 vec2 store */
2642 outer_comps = 2;
2643 inner_comps = 0;
2644 break;
2645 case PIPE_PRIM_TRIANGLES:
2646 stride = 4; /* 4 dwords, 1 vec4 store */
2647 outer_comps = 3;
2648 inner_comps = 1;
2649 break;
2650 case PIPE_PRIM_QUADS:
2651 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2652 outer_comps = 4;
2653 inner_comps = 2;
2654 break;
2655 default:
2656 assert(0);
2657 return;
2658 }
2659
2660 /* Load tess_inner and tess_outer from LDS.
2661 * Any invocation can write them, so we can't get them from a temporary.
2662 */
2663 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2664 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2665
2666 lds_base = tcs_out_current_patch_data_offset;
2667 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2668 lp_build_const_int32(gallivm,
2669 tess_inner_index * 4), "");
2670 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2671 lp_build_const_int32(gallivm,
2672 tess_outer_index * 4), "");
2673
2674 for (i = 0; i < outer_comps; i++)
2675 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2676 for (i = 0; i < inner_comps; i++)
2677 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2678
2679 /* Convert the outputs to vectors for stores. */
2680 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2681 vec1 = NULL;
2682
2683 if (stride > 4)
2684 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2685
2686 /* Get the buffer. */
2687 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2688 SI_PARAM_RW_BUFFERS);
2689 buffer = build_indexed_load_const(ctx, rw_buffers,
2690 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2691
2692 /* Get the offset. */
2693 tf_base = LLVMGetParam(ctx->radeon_bld.main_fn,
2694 SI_PARAM_TESS_FACTOR_OFFSET);
2695 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2696 lp_build_const_int32(gallivm, 4 * stride), "");
2697
2698 lp_build_if(&inner_if_ctx, gallivm,
2699 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2700 rel_patch_id, bld_base->uint_bld.zero, ""));
2701
2702 /* Store the dynamic HS control word. */
2703 build_tbuffer_store_dwords(ctx, buffer,
2704 lp_build_const_int32(gallivm, 0x80000000),
2705 1, lp_build_const_int32(gallivm, 0), tf_base, 0);
2706
2707 lp_build_endif(&inner_if_ctx);
2708
2709 /* Store the tessellation factors. */
2710 build_tbuffer_store_dwords(ctx, buffer, vec0,
2711 MIN2(stride, 4), byteoffset, tf_base, 4);
2712 if (vec1)
2713 build_tbuffer_store_dwords(ctx, buffer, vec1,
2714 stride - 4, byteoffset, tf_base, 20);
2715 lp_build_endif(&if_ctx);
2716 }
2717
2718 /* This only writes the tessellation factor levels. */
2719 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2720 {
2721 struct si_shader_context *ctx = si_shader_context(bld_base);
2722 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2723
2724 rel_patch_id = get_rel_patch_id(ctx);
2725 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2726 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2727
2728 if (!ctx->is_monolithic) {
2729 /* Return epilog parameters from this function. */
2730 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2731 LLVMValueRef ret = ctx->return_value;
2732 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2733 unsigned vgpr;
2734
2735 /* RW_BUFFERS pointer */
2736 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2737 SI_PARAM_RW_BUFFERS);
2738 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2739 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2740 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2741 bld_base->uint_bld.zero, "");
2742 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2743 bld_base->uint_bld.one, "");
2744 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2745 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2746
2747 /* Tess factor buffer soffset is after user SGPRs. */
2748 tf_soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2749 SI_PARAM_TESS_FACTOR_OFFSET);
2750 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2751 SI_TCS_NUM_USER_SGPR + 1, "");
2752
2753 /* VGPRs */
2754 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2755 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2756 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2757
2758 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2759 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2760 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2761 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2762 ctx->return_value = ret;
2763 return;
2764 }
2765
2766 si_copy_tcs_inputs(bld_base);
2767 si_write_tess_factors(bld_base, rel_patch_id, invocation_id, tf_lds_offset);
2768 }
2769
2770 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2771 {
2772 struct si_shader_context *ctx = si_shader_context(bld_base);
2773 struct si_shader *shader = ctx->shader;
2774 struct tgsi_shader_info *info = &shader->selector->info;
2775 struct gallivm_state *gallivm = bld_base->base.gallivm;
2776 unsigned i, chan;
2777 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
2778 ctx->param_rel_auto_id);
2779 LLVMValueRef vertex_dw_stride =
2780 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2781 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2782 vertex_dw_stride, "");
2783
2784 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2785 * its inputs from it. */
2786 for (i = 0; i < info->num_outputs; i++) {
2787 LLVMValueRef *out_ptr = ctx->radeon_bld.soa.outputs[i];
2788 unsigned name = info->output_semantic_name[i];
2789 unsigned index = info->output_semantic_index[i];
2790 int param = si_shader_io_get_unique_index(name, index);
2791 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2792 lp_build_const_int32(gallivm, param * 4), "");
2793
2794 for (chan = 0; chan < 4; chan++) {
2795 lds_store(bld_base, chan, dw_addr,
2796 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2797 }
2798 }
2799 }
2800
2801 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2802 {
2803 struct si_shader_context *ctx = si_shader_context(bld_base);
2804 struct gallivm_state *gallivm = bld_base->base.gallivm;
2805 struct si_shader *es = ctx->shader;
2806 struct tgsi_shader_info *info = &es->selector->info;
2807 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2808 ctx->param_es2gs_offset);
2809 unsigned chan;
2810 int i;
2811
2812 for (i = 0; i < info->num_outputs; i++) {
2813 LLVMValueRef *out_ptr =
2814 ctx->radeon_bld.soa.outputs[i];
2815 int param_index;
2816
2817 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2818 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2819 continue;
2820
2821 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2822 info->output_semantic_index[i]);
2823
2824 for (chan = 0; chan < 4; chan++) {
2825 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2826 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2827
2828 build_tbuffer_store(ctx,
2829 ctx->esgs_ring,
2830 out_val, 1,
2831 LLVMGetUndef(ctx->i32), soffset,
2832 (4 * param_index + chan) * 4,
2833 V_008F0C_BUF_DATA_FORMAT_32,
2834 V_008F0C_BUF_NUM_FORMAT_UINT,
2835 0, 0, 1, 1, 0);
2836 }
2837 }
2838 }
2839
2840 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2841 {
2842 struct si_shader_context *ctx = si_shader_context(bld_base);
2843 struct gallivm_state *gallivm = bld_base->base.gallivm;
2844 LLVMValueRef args[2];
2845
2846 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2847 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2848 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2849 ctx->voidt, args, 2, 0);
2850 }
2851
2852 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2853 {
2854 struct si_shader_context *ctx = si_shader_context(bld_base);
2855 struct gallivm_state *gallivm = bld_base->base.gallivm;
2856 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2857 struct si_shader_output_values *outputs = NULL;
2858 int i,j;
2859
2860 assert(!ctx->is_gs_copy_shader);
2861
2862 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2863
2864 /* Vertex color clamping.
2865 *
2866 * This uses a state constant loaded in a user data SGPR and
2867 * an IF statement is added that clamps all colors if the constant
2868 * is true.
2869 */
2870 if (ctx->type == PIPE_SHADER_VERTEX) {
2871 struct lp_build_if_state if_ctx;
2872 LLVMValueRef cond = NULL;
2873 LLVMValueRef addr, val;
2874
2875 for (i = 0; i < info->num_outputs; i++) {
2876 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2877 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2878 continue;
2879
2880 /* We've found a color. */
2881 if (!cond) {
2882 /* The state is in the first bit of the user SGPR. */
2883 cond = LLVMGetParam(ctx->radeon_bld.main_fn,
2884 SI_PARAM_VS_STATE_BITS);
2885 cond = LLVMBuildTrunc(gallivm->builder, cond,
2886 ctx->i1, "");
2887 lp_build_if(&if_ctx, gallivm, cond);
2888 }
2889
2890 for (j = 0; j < 4; j++) {
2891 addr = ctx->radeon_bld.soa.outputs[i][j];
2892 val = LLVMBuildLoad(gallivm->builder, addr, "");
2893 val = radeon_llvm_saturate(bld_base, val);
2894 LLVMBuildStore(gallivm->builder, val, addr);
2895 }
2896 }
2897
2898 if (cond)
2899 lp_build_endif(&if_ctx);
2900 }
2901
2902 for (i = 0; i < info->num_outputs; i++) {
2903 outputs[i].name = info->output_semantic_name[i];
2904 outputs[i].sid = info->output_semantic_index[i];
2905
2906 for (j = 0; j < 4; j++)
2907 outputs[i].values[j] =
2908 LLVMBuildLoad(gallivm->builder,
2909 ctx->radeon_bld.soa.outputs[i][j],
2910 "");
2911 }
2912
2913 if (ctx->is_monolithic) {
2914 /* Export PrimitiveID when PS needs it. */
2915 if (si_vs_exports_prim_id(ctx->shader)) {
2916 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2917 outputs[i].sid = 0;
2918 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2919 get_primitive_id(bld_base, 0));
2920 outputs[i].values[1] = bld_base->base.undef;
2921 outputs[i].values[2] = bld_base->base.undef;
2922 outputs[i].values[3] = bld_base->base.undef;
2923 i++;
2924 }
2925 } else {
2926 /* Return the primitive ID from the LLVM function. */
2927 ctx->return_value =
2928 LLVMBuildInsertValue(gallivm->builder,
2929 ctx->return_value,
2930 bitcast(bld_base, TGSI_TYPE_FLOAT,
2931 get_primitive_id(bld_base, 0)),
2932 VS_EPILOG_PRIMID_LOC, "");
2933 }
2934
2935 si_llvm_export_vs(bld_base, outputs, i);
2936 FREE(outputs);
2937 }
2938
2939 struct si_ps_exports {
2940 unsigned num;
2941 LLVMValueRef args[10][9];
2942 };
2943
2944 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
2945 bool writes_samplemask)
2946 {
2947 if (writes_z) {
2948 /* Z needs 32 bits. */
2949 if (writes_samplemask)
2950 return V_028710_SPI_SHADER_32_ABGR;
2951 else if (writes_stencil)
2952 return V_028710_SPI_SHADER_32_GR;
2953 else
2954 return V_028710_SPI_SHADER_32_R;
2955 } else if (writes_stencil || writes_samplemask) {
2956 /* Both stencil and sample mask need only 16 bits. */
2957 return V_028710_SPI_SHADER_UINT16_ABGR;
2958 } else {
2959 return V_028710_SPI_SHADER_ZERO;
2960 }
2961 }
2962
2963 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2964 LLVMValueRef depth, LLVMValueRef stencil,
2965 LLVMValueRef samplemask, struct si_ps_exports *exp)
2966 {
2967 struct si_shader_context *ctx = si_shader_context(bld_base);
2968 struct lp_build_context *base = &bld_base->base;
2969 struct lp_build_context *uint = &bld_base->uint_bld;
2970 LLVMValueRef args[9];
2971 unsigned mask = 0;
2972 unsigned format = si_get_spi_shader_z_format(depth != NULL,
2973 stencil != NULL,
2974 samplemask != NULL);
2975
2976 assert(depth || stencil || samplemask);
2977
2978 args[1] = uint->one; /* whether the EXEC mask is valid */
2979 args[2] = uint->one; /* DONE bit */
2980
2981 /* Specify the target we are exporting */
2982 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2983
2984 args[4] = uint->zero; /* COMP flag */
2985 args[5] = base->undef; /* R, depth */
2986 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2987 args[7] = base->undef; /* B, sample mask */
2988 args[8] = base->undef; /* A, alpha to mask */
2989
2990 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
2991 assert(!depth);
2992 args[4] = uint->one; /* COMPR flag */
2993
2994 if (stencil) {
2995 /* Stencil should be in X[23:16]. */
2996 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
2997 stencil = LLVMBuildShl(base->gallivm->builder, stencil,
2998 LLVMConstInt(ctx->i32, 16, 0), "");
2999 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
3000 mask |= 0x3;
3001 }
3002 if (samplemask) {
3003 /* SampleMask should be in Y[15:0]. */
3004 args[6] = samplemask;
3005 mask |= 0xc;
3006 }
3007 } else {
3008 if (depth) {
3009 args[5] = depth;
3010 mask |= 0x1;
3011 }
3012 if (stencil) {
3013 args[6] = stencil;
3014 mask |= 0x2;
3015 }
3016 if (samplemask) {
3017 args[7] = samplemask;
3018 mask |= 0x4;
3019 }
3020 }
3021
3022 /* SI (except OLAND) has a bug that it only looks
3023 * at the X writemask component. */
3024 if (ctx->screen->b.chip_class == SI &&
3025 ctx->screen->b.family != CHIP_OLAND)
3026 mask |= 0x1;
3027
3028 /* Specify which components to enable */
3029 args[0] = lp_build_const_int32(base->gallivm, mask);
3030
3031 memcpy(exp->args[exp->num++], args, sizeof(args));
3032 }
3033
3034 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3035 LLVMValueRef *color, unsigned index,
3036 unsigned samplemask_param,
3037 bool is_last, struct si_ps_exports *exp)
3038 {
3039 struct si_shader_context *ctx = si_shader_context(bld_base);
3040 struct lp_build_context *base = &bld_base->base;
3041 int i;
3042
3043 /* Clamp color */
3044 if (ctx->shader->key.ps.epilog.clamp_color)
3045 for (i = 0; i < 4; i++)
3046 color[i] = radeon_llvm_saturate(bld_base, color[i]);
3047
3048 /* Alpha to one */
3049 if (ctx->shader->key.ps.epilog.alpha_to_one)
3050 color[3] = base->one;
3051
3052 /* Alpha test */
3053 if (index == 0 &&
3054 ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3055 si_alpha_test(bld_base, color[3]);
3056
3057 /* Line & polygon smoothing */
3058 if (ctx->shader->key.ps.epilog.poly_line_smoothing)
3059 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3060 samplemask_param);
3061
3062 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3063 if (ctx->shader->key.ps.epilog.last_cbuf > 0) {
3064 LLVMValueRef args[8][9];
3065 int c, last = -1;
3066
3067 /* Get the export arguments, also find out what the last one is. */
3068 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
3069 si_llvm_init_export_args(bld_base, color,
3070 V_008DFC_SQ_EXP_MRT + c, args[c]);
3071 if (args[c][0] != bld_base->uint_bld.zero)
3072 last = c;
3073 }
3074
3075 /* Emit all exports. */
3076 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
3077 if (is_last && last == c) {
3078 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3079 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
3080 } else if (args[c][0] == bld_base->uint_bld.zero)
3081 continue; /* unnecessary NULL export */
3082
3083 memcpy(exp->args[exp->num++], args[c], sizeof(args[c]));
3084 }
3085 } else {
3086 LLVMValueRef args[9];
3087
3088 /* Export */
3089 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
3090 args);
3091 if (is_last) {
3092 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3093 args[2] = bld_base->uint_bld.one; /* DONE bit */
3094 } else if (args[0] == bld_base->uint_bld.zero)
3095 return; /* unnecessary NULL export */
3096
3097 memcpy(exp->args[exp->num++], args, sizeof(args));
3098 }
3099 }
3100
3101 static void si_emit_ps_exports(struct si_shader_context *ctx,
3102 struct si_ps_exports *exp)
3103 {
3104 for (unsigned i = 0; i < exp->num; i++)
3105 lp_build_intrinsic(ctx->radeon_bld.gallivm.builder,
3106 "llvm.SI.export", ctx->voidt,
3107 exp->args[i], 9, 0);
3108 }
3109
3110 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3111 {
3112 struct si_shader_context *ctx = si_shader_context(bld_base);
3113 struct lp_build_context *base = &bld_base->base;
3114 struct lp_build_context *uint = &bld_base->uint_bld;
3115 LLVMValueRef args[9];
3116
3117 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
3118 args[1] = uint->one; /* whether the EXEC mask is valid */
3119 args[2] = uint->one; /* DONE bit */
3120 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
3121 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
3122 args[5] = base->undef; /* R */
3123 args[6] = base->undef; /* G */
3124 args[7] = base->undef; /* B */
3125 args[8] = base->undef; /* A */
3126
3127 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
3128 ctx->voidt, args, 9, 0);
3129 }
3130
3131 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context *bld_base)
3132 {
3133 struct si_shader_context *ctx = si_shader_context(bld_base);
3134 struct si_shader *shader = ctx->shader;
3135 struct lp_build_context *base = &bld_base->base;
3136 struct tgsi_shader_info *info = &shader->selector->info;
3137 LLVMBuilderRef builder = base->gallivm->builder;
3138 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3139 int last_color_export = -1;
3140 int i;
3141 struct si_ps_exports exp = {};
3142
3143 /* Determine the last export. If MRTZ is present, it's always last.
3144 * Otherwise, find the last color export.
3145 */
3146 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask) {
3147 unsigned spi_format = shader->key.ps.epilog.spi_shader_col_format;
3148
3149 /* Don't export NULL and return if alpha-test is enabled. */
3150 if (shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS &&
3151 shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER &&
3152 (spi_format & 0xf) == 0)
3153 spi_format |= V_028714_SPI_SHADER_32_AR;
3154
3155 for (i = 0; i < info->num_outputs; i++) {
3156 unsigned index = info->output_semantic_index[i];
3157
3158 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR)
3159 continue;
3160
3161 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3162 if (shader->key.ps.epilog.last_cbuf > 0) {
3163 /* Just set this if any of the colorbuffers are enabled. */
3164 if (spi_format &
3165 ((1llu << (4 * (shader->key.ps.epilog.last_cbuf + 1))) - 1))
3166 last_color_export = i;
3167 continue;
3168 }
3169
3170 if ((spi_format >> (index * 4)) & 0xf)
3171 last_color_export = i;
3172 }
3173
3174 /* If there are no outputs, export NULL. */
3175 if (last_color_export == -1) {
3176 si_export_null(bld_base);
3177 return;
3178 }
3179 }
3180
3181 for (i = 0; i < info->num_outputs; i++) {
3182 unsigned semantic_name = info->output_semantic_name[i];
3183 unsigned semantic_index = info->output_semantic_index[i];
3184 unsigned j;
3185 LLVMValueRef color[4] = {};
3186
3187 /* Select the correct target */
3188 switch (semantic_name) {
3189 case TGSI_SEMANTIC_POSITION:
3190 depth = LLVMBuildLoad(builder,
3191 ctx->radeon_bld.soa.outputs[i][2], "");
3192 break;
3193 case TGSI_SEMANTIC_STENCIL:
3194 stencil = LLVMBuildLoad(builder,
3195 ctx->radeon_bld.soa.outputs[i][1], "");
3196 break;
3197 case TGSI_SEMANTIC_SAMPLEMASK:
3198 samplemask = LLVMBuildLoad(builder,
3199 ctx->radeon_bld.soa.outputs[i][0], "");
3200 break;
3201 case TGSI_SEMANTIC_COLOR:
3202 for (j = 0; j < 4; j++)
3203 color[j] = LLVMBuildLoad(builder,
3204 ctx->radeon_bld.soa.outputs[i][j], "");
3205
3206 si_export_mrt_color(bld_base, color, semantic_index,
3207 SI_PARAM_SAMPLE_COVERAGE,
3208 last_color_export == i, &exp);
3209 break;
3210 default:
3211 fprintf(stderr,
3212 "Warning: SI unhandled fs output type:%d\n",
3213 semantic_name);
3214 }
3215 }
3216
3217 if (depth || stencil || samplemask)
3218 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
3219
3220 si_emit_ps_exports(ctx, &exp);
3221 }
3222
3223 /**
3224 * Return PS outputs in this order:
3225 *
3226 * v[0:3] = color0.xyzw
3227 * v[4:7] = color1.xyzw
3228 * ...
3229 * vN+0 = Depth
3230 * vN+1 = Stencil
3231 * vN+2 = SampleMask
3232 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3233 *
3234 * The alpha-ref SGPR is returned via its original location.
3235 */
3236 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
3237 {
3238 struct si_shader_context *ctx = si_shader_context(bld_base);
3239 struct si_shader *shader = ctx->shader;
3240 struct lp_build_context *base = &bld_base->base;
3241 struct tgsi_shader_info *info = &shader->selector->info;
3242 LLVMBuilderRef builder = base->gallivm->builder;
3243 unsigned i, j, first_vgpr, vgpr;
3244
3245 LLVMValueRef color[8][4] = {};
3246 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3247 LLVMValueRef ret;
3248
3249 /* Read the output values. */
3250 for (i = 0; i < info->num_outputs; i++) {
3251 unsigned semantic_name = info->output_semantic_name[i];
3252 unsigned semantic_index = info->output_semantic_index[i];
3253
3254 switch (semantic_name) {
3255 case TGSI_SEMANTIC_COLOR:
3256 assert(semantic_index < 8);
3257 for (j = 0; j < 4; j++) {
3258 LLVMValueRef ptr = ctx->radeon_bld.soa.outputs[i][j];
3259 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3260 color[semantic_index][j] = result;
3261 }
3262 break;
3263 case TGSI_SEMANTIC_POSITION:
3264 depth = LLVMBuildLoad(builder,
3265 ctx->radeon_bld.soa.outputs[i][2], "");
3266 break;
3267 case TGSI_SEMANTIC_STENCIL:
3268 stencil = LLVMBuildLoad(builder,
3269 ctx->radeon_bld.soa.outputs[i][1], "");
3270 break;
3271 case TGSI_SEMANTIC_SAMPLEMASK:
3272 samplemask = LLVMBuildLoad(builder,
3273 ctx->radeon_bld.soa.outputs[i][0], "");
3274 break;
3275 default:
3276 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3277 semantic_name);
3278 }
3279 }
3280
3281 /* Fill the return structure. */
3282 ret = ctx->return_value;
3283
3284 /* Set SGPRs. */
3285 ret = LLVMBuildInsertValue(builder, ret,
3286 bitcast(bld_base, TGSI_TYPE_SIGNED,
3287 LLVMGetParam(ctx->radeon_bld.main_fn,
3288 SI_PARAM_ALPHA_REF)),
3289 SI_SGPR_ALPHA_REF, "");
3290
3291 /* Set VGPRs */
3292 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3293 for (i = 0; i < ARRAY_SIZE(color); i++) {
3294 if (!color[i][0])
3295 continue;
3296
3297 for (j = 0; j < 4; j++)
3298 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3299 }
3300 if (depth)
3301 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3302 if (stencil)
3303 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3304 if (samplemask)
3305 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3306
3307 /* Add the input sample mask for smoothing at the end. */
3308 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3309 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3310 ret = LLVMBuildInsertValue(builder, ret,
3311 LLVMGetParam(ctx->radeon_bld.main_fn,
3312 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3313
3314 ctx->return_value = ret;
3315 }
3316
3317 /**
3318 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3319 * buffer in number of elements and return it as an i32.
3320 */
3321 static LLVMValueRef get_buffer_size(
3322 struct lp_build_tgsi_context *bld_base,
3323 LLVMValueRef descriptor)
3324 {
3325 struct si_shader_context *ctx = si_shader_context(bld_base);
3326 struct gallivm_state *gallivm = bld_base->base.gallivm;
3327 LLVMBuilderRef builder = gallivm->builder;
3328 LLVMValueRef size =
3329 LLVMBuildExtractElement(builder, descriptor,
3330 lp_build_const_int32(gallivm, 6), "");
3331
3332 if (ctx->screen->b.chip_class >= VI) {
3333 /* On VI, the descriptor contains the size in bytes,
3334 * but TXQ must return the size in elements.
3335 * The stride is always non-zero for resources using TXQ.
3336 */
3337 LLVMValueRef stride =
3338 LLVMBuildExtractElement(builder, descriptor,
3339 lp_build_const_int32(gallivm, 5), "");
3340 stride = LLVMBuildLShr(builder, stride,
3341 lp_build_const_int32(gallivm, 16), "");
3342 stride = LLVMBuildAnd(builder, stride,
3343 lp_build_const_int32(gallivm, 0x3FFF), "");
3344
3345 size = LLVMBuildUDiv(builder, size, stride, "");
3346 }
3347
3348 return size;
3349 }
3350
3351 /**
3352 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
3353 * intrinsic names).
3354 */
3355 static void build_int_type_name(
3356 LLVMTypeRef type,
3357 char *buf, unsigned bufsize)
3358 {
3359 assert(bufsize >= 6);
3360
3361 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
3362 snprintf(buf, bufsize, "v%ui32",
3363 LLVMGetVectorSize(type));
3364 else
3365 strcpy(buf, "i32");
3366 }
3367
3368 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3369 struct lp_build_tgsi_context *bld_base,
3370 struct lp_build_emit_data *emit_data);
3371
3372 /* Prevent optimizations (at least of memory accesses) across the current
3373 * point in the program by emitting empty inline assembly that is marked as
3374 * having side effects.
3375 */
3376 static void emit_optimization_barrier(struct si_shader_context *ctx)
3377 {
3378 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
3379 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3380 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
3381 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3382 }
3383
3384 static void emit_waitcnt(struct si_shader_context *ctx)
3385 {
3386 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3387 LLVMBuilderRef builder = gallivm->builder;
3388 LLVMValueRef args[1] = {
3389 lp_build_const_int32(gallivm, 0xf70)
3390 };
3391 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3392 ctx->voidt, args, 1, 0);
3393 }
3394
3395 static void membar_emit(
3396 const struct lp_build_tgsi_action *action,
3397 struct lp_build_tgsi_context *bld_base,
3398 struct lp_build_emit_data *emit_data)
3399 {
3400 struct si_shader_context *ctx = si_shader_context(bld_base);
3401
3402 emit_waitcnt(ctx);
3403 }
3404
3405 static LLVMValueRef
3406 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3407 const struct tgsi_full_src_register *reg)
3408 {
3409 LLVMValueRef ind_index;
3410 LLVMValueRef rsrc_ptr;
3411
3412 if (!reg->Register.Indirect)
3413 return ctx->shader_buffers[reg->Register.Index];
3414
3415 ind_index = get_bounded_indirect_index(ctx, &reg->Indirect,
3416 reg->Register.Index,
3417 SI_NUM_SHADER_BUFFERS);
3418
3419 rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_SHADER_BUFFERS);
3420 return build_indexed_load_const(ctx, rsrc_ptr, ind_index);
3421 }
3422
3423 static bool tgsi_is_array_sampler(unsigned target)
3424 {
3425 return target == TGSI_TEXTURE_1D_ARRAY ||
3426 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3427 target == TGSI_TEXTURE_2D_ARRAY ||
3428 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3429 target == TGSI_TEXTURE_CUBE_ARRAY ||
3430 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3431 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3432 }
3433
3434 static bool tgsi_is_array_image(unsigned target)
3435 {
3436 return target == TGSI_TEXTURE_3D ||
3437 target == TGSI_TEXTURE_CUBE ||
3438 target == TGSI_TEXTURE_1D_ARRAY ||
3439 target == TGSI_TEXTURE_2D_ARRAY ||
3440 target == TGSI_TEXTURE_CUBE_ARRAY ||
3441 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3442 }
3443
3444 /**
3445 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3446 *
3447 * At least on Tonga, executing image stores on images with DCC enabled and
3448 * non-trivial can eventually lead to lockups. This can occur when an
3449 * application binds an image as read-only but then uses a shader that writes
3450 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3451 * program termination) in this case, but it doesn't cost much to be a bit
3452 * nicer: disabling DCC in the shader still leads to undefined results but
3453 * avoids the lockup.
3454 */
3455 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3456 LLVMValueRef rsrc)
3457 {
3458 if (ctx->screen->b.chip_class <= CIK) {
3459 return rsrc;
3460 } else {
3461 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
3462 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3463 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3464 LLVMValueRef tmp;
3465
3466 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3467 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3468 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3469 }
3470 }
3471
3472 /**
3473 * Load the resource descriptor for \p image.
3474 */
3475 static void
3476 image_fetch_rsrc(
3477 struct lp_build_tgsi_context *bld_base,
3478 const struct tgsi_full_src_register *image,
3479 bool dcc_off,
3480 LLVMValueRef *rsrc)
3481 {
3482 struct si_shader_context *ctx = si_shader_context(bld_base);
3483
3484 assert(image->Register.File == TGSI_FILE_IMAGE);
3485
3486 if (!image->Register.Indirect) {
3487 /* Fast path: use preloaded resources */
3488 *rsrc = ctx->images[image->Register.Index];
3489 } else {
3490 /* Indexing and manual load */
3491 LLVMValueRef ind_index;
3492 LLVMValueRef rsrc_ptr;
3493 LLVMValueRef tmp;
3494
3495 /* From the GL_ARB_shader_image_load_store extension spec:
3496 *
3497 * If a shader performs an image load, store, or atomic
3498 * operation using an image variable declared as an array,
3499 * and if the index used to select an individual element is
3500 * negative or greater than or equal to the size of the
3501 * array, the results of the operation are undefined but may
3502 * not lead to termination.
3503 */
3504 ind_index = get_bounded_indirect_index(ctx, &image->Indirect,
3505 image->Register.Index,
3506 SI_NUM_IMAGES);
3507
3508 rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
3509 tmp = build_indexed_load_const(ctx, rsrc_ptr, ind_index);
3510 if (dcc_off)
3511 tmp = force_dcc_off(ctx, tmp);
3512 *rsrc = tmp;
3513 }
3514 }
3515
3516 static LLVMValueRef image_fetch_coords(
3517 struct lp_build_tgsi_context *bld_base,
3518 const struct tgsi_full_instruction *inst,
3519 unsigned src)
3520 {
3521 struct gallivm_state *gallivm = bld_base->base.gallivm;
3522 LLVMBuilderRef builder = gallivm->builder;
3523 unsigned target = inst->Memory.Texture;
3524 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3525 LLVMValueRef coords[4];
3526 LLVMValueRef tmp;
3527 int chan;
3528
3529 for (chan = 0; chan < num_coords; ++chan) {
3530 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3531 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3532 coords[chan] = tmp;
3533 }
3534
3535 if (num_coords == 1)
3536 return coords[0];
3537
3538 if (num_coords == 3) {
3539 /* LLVM has difficulties lowering 3-element vectors. */
3540 coords[3] = bld_base->uint_bld.undef;
3541 num_coords = 4;
3542 }
3543
3544 return lp_build_gather_values(gallivm, coords, num_coords);
3545 }
3546
3547 /**
3548 * Append the extra mode bits that are used by image load and store.
3549 */
3550 static void image_append_args(
3551 struct si_shader_context *ctx,
3552 struct lp_build_emit_data * emit_data,
3553 unsigned target,
3554 bool atomic)
3555 {
3556 const struct tgsi_full_instruction *inst = emit_data->inst;
3557 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3558 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3559
3560 emit_data->args[emit_data->arg_count++] = i1false; /* r128 */
3561 emit_data->args[emit_data->arg_count++] =
3562 tgsi_is_array_image(target) ? i1true : i1false; /* da */
3563 if (!atomic) {
3564 emit_data->args[emit_data->arg_count++] =
3565 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3566 i1true : i1false; /* glc */
3567 }
3568 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3569 }
3570
3571 /**
3572 * Given a 256 bit resource, extract the top half (which stores the buffer
3573 * resource in the case of textures and images).
3574 */
3575 static LLVMValueRef extract_rsrc_top_half(
3576 struct si_shader_context *ctx,
3577 LLVMValueRef rsrc)
3578 {
3579 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3580 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
3581 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
3582
3583 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, v2i128, "");
3584 rsrc = LLVMBuildExtractElement(gallivm->builder, rsrc, bld_base->uint_bld.one, "");
3585 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, "");
3586
3587 return rsrc;
3588 }
3589
3590 /**
3591 * Append the resource and indexing arguments for buffer intrinsics.
3592 *
3593 * \param rsrc the v4i32 buffer resource
3594 * \param index index into the buffer (stride-based)
3595 * \param offset byte offset into the buffer
3596 */
3597 static void buffer_append_args(
3598 struct si_shader_context *ctx,
3599 struct lp_build_emit_data *emit_data,
3600 LLVMValueRef rsrc,
3601 LLVMValueRef index,
3602 LLVMValueRef offset,
3603 bool atomic)
3604 {
3605 const struct tgsi_full_instruction *inst = emit_data->inst;
3606 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3607 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3608
3609 emit_data->args[emit_data->arg_count++] = rsrc;
3610 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3611 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3612 if (!atomic) {
3613 emit_data->args[emit_data->arg_count++] =
3614 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3615 i1true : i1false; /* glc */
3616 }
3617 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3618 }
3619
3620 static void load_fetch_args(
3621 struct lp_build_tgsi_context * bld_base,
3622 struct lp_build_emit_data * emit_data)
3623 {
3624 struct si_shader_context *ctx = si_shader_context(bld_base);
3625 struct gallivm_state *gallivm = bld_base->base.gallivm;
3626 const struct tgsi_full_instruction * inst = emit_data->inst;
3627 unsigned target = inst->Memory.Texture;
3628 LLVMValueRef rsrc;
3629
3630 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3631
3632 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3633 LLVMBuilderRef builder = gallivm->builder;
3634 LLVMValueRef offset;
3635 LLVMValueRef tmp;
3636
3637 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3638
3639 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3640 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3641
3642 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3643 offset, false);
3644 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3645 LLVMValueRef coords;
3646
3647 image_fetch_rsrc(bld_base, &inst->Src[0], false, &rsrc);
3648 coords = image_fetch_coords(bld_base, inst, 1);
3649
3650 if (target == TGSI_TEXTURE_BUFFER) {
3651 rsrc = extract_rsrc_top_half(ctx, rsrc);
3652 buffer_append_args(ctx, emit_data, rsrc, coords,
3653 bld_base->uint_bld.zero, false);
3654 } else {
3655 emit_data->args[0] = coords;
3656 emit_data->args[1] = rsrc;
3657 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3658 emit_data->arg_count = 3;
3659
3660 image_append_args(ctx, emit_data, target, false);
3661 }
3662 }
3663 }
3664
3665 static void load_emit_buffer(struct si_shader_context *ctx,
3666 struct lp_build_emit_data *emit_data)
3667 {
3668 const struct tgsi_full_instruction *inst = emit_data->inst;
3669 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3670 LLVMBuilderRef builder = gallivm->builder;
3671 uint writemask = inst->Dst[0].Register.WriteMask;
3672 uint count = util_last_bit(writemask);
3673 const char *intrinsic_name;
3674 LLVMTypeRef dst_type;
3675
3676 switch (count) {
3677 case 1:
3678 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3679 dst_type = ctx->f32;
3680 break;
3681 case 2:
3682 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3683 dst_type = LLVMVectorType(ctx->f32, 2);
3684 break;
3685 default: // 3 & 4
3686 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3687 dst_type = ctx->v4f32;
3688 count = 4;
3689 }
3690
3691 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3692 builder, intrinsic_name, dst_type,
3693 emit_data->args, emit_data->arg_count,
3694 LLVMReadOnlyAttribute);
3695 }
3696
3697 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3698 const struct tgsi_full_instruction *inst,
3699 LLVMTypeRef type, int arg)
3700 {
3701 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3702 LLVMBuilderRef builder = gallivm->builder;
3703 LLVMValueRef offset, ptr;
3704 int addr_space;
3705
3706 offset = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, arg, 0);
3707 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3708
3709 ptr = ctx->shared_memory;
3710 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3711 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3712 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3713
3714 return ptr;
3715 }
3716
3717 static void load_emit_memory(
3718 struct si_shader_context *ctx,
3719 struct lp_build_emit_data *emit_data)
3720 {
3721 const struct tgsi_full_instruction *inst = emit_data->inst;
3722 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3723 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3724 LLVMBuilderRef builder = gallivm->builder;
3725 unsigned writemask = inst->Dst[0].Register.WriteMask;
3726 LLVMValueRef channels[4], ptr, derived_ptr, index;
3727 int chan;
3728
3729 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3730
3731 for (chan = 0; chan < 4; ++chan) {
3732 if (!(writemask & (1 << chan))) {
3733 channels[chan] = LLVMGetUndef(base->elem_type);
3734 continue;
3735 }
3736
3737 index = lp_build_const_int32(gallivm, chan);
3738 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3739 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3740 }
3741 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3742 }
3743
3744 static void load_emit(
3745 const struct lp_build_tgsi_action *action,
3746 struct lp_build_tgsi_context *bld_base,
3747 struct lp_build_emit_data *emit_data)
3748 {
3749 struct si_shader_context *ctx = si_shader_context(bld_base);
3750 struct gallivm_state *gallivm = bld_base->base.gallivm;
3751 LLVMBuilderRef builder = gallivm->builder;
3752 const struct tgsi_full_instruction * inst = emit_data->inst;
3753 char intrinsic_name[32];
3754 char coords_type[8];
3755
3756 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3757 load_emit_memory(ctx, emit_data);
3758 return;
3759 }
3760
3761 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3762 emit_waitcnt(ctx);
3763
3764 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3765 load_emit_buffer(ctx, emit_data);
3766 return;
3767 }
3768
3769 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3770 emit_data->output[emit_data->chan] =
3771 lp_build_intrinsic(
3772 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3773 emit_data->args, emit_data->arg_count,
3774 LLVMReadOnlyAttribute);
3775 } else {
3776 build_int_type_name(LLVMTypeOf(emit_data->args[0]),
3777 coords_type, sizeof(coords_type));
3778
3779 snprintf(intrinsic_name, sizeof(intrinsic_name),
3780 "llvm.amdgcn.image.load.%s", coords_type);
3781
3782 emit_data->output[emit_data->chan] =
3783 lp_build_intrinsic(
3784 builder, intrinsic_name, emit_data->dst_type,
3785 emit_data->args, emit_data->arg_count,
3786 LLVMReadOnlyAttribute);
3787 }
3788 }
3789
3790 static void store_fetch_args(
3791 struct lp_build_tgsi_context * bld_base,
3792 struct lp_build_emit_data * emit_data)
3793 {
3794 struct si_shader_context *ctx = si_shader_context(bld_base);
3795 struct gallivm_state *gallivm = bld_base->base.gallivm;
3796 LLVMBuilderRef builder = gallivm->builder;
3797 const struct tgsi_full_instruction * inst = emit_data->inst;
3798 struct tgsi_full_src_register memory;
3799 LLVMValueRef chans[4];
3800 LLVMValueRef data;
3801 LLVMValueRef rsrc;
3802 unsigned chan;
3803
3804 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3805
3806 for (chan = 0; chan < 4; ++chan) {
3807 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3808 }
3809 data = lp_build_gather_values(gallivm, chans, 4);
3810
3811 emit_data->args[emit_data->arg_count++] = data;
3812
3813 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3814
3815 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3816 LLVMValueRef offset;
3817 LLVMValueRef tmp;
3818
3819 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3820
3821 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3822 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3823
3824 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3825 offset, false);
3826 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3827 unsigned target = inst->Memory.Texture;
3828 LLVMValueRef coords;
3829
3830 coords = image_fetch_coords(bld_base, inst, 0);
3831
3832 if (target == TGSI_TEXTURE_BUFFER) {
3833 image_fetch_rsrc(bld_base, &memory, false, &rsrc);
3834
3835 rsrc = extract_rsrc_top_half(ctx, rsrc);
3836 buffer_append_args(ctx, emit_data, rsrc, coords,
3837 bld_base->uint_bld.zero, false);
3838 } else {
3839 emit_data->args[1] = coords;
3840 image_fetch_rsrc(bld_base, &memory, true, &emit_data->args[2]);
3841 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3842 emit_data->arg_count = 4;
3843
3844 image_append_args(ctx, emit_data, target, false);
3845 }
3846 }
3847 }
3848
3849 static void store_emit_buffer(
3850 struct si_shader_context *ctx,
3851 struct lp_build_emit_data *emit_data)
3852 {
3853 const struct tgsi_full_instruction *inst = emit_data->inst;
3854 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3855 LLVMBuilderRef builder = gallivm->builder;
3856 struct lp_build_context *uint_bld = &ctx->radeon_bld.soa.bld_base.uint_bld;
3857 LLVMValueRef base_data = emit_data->args[0];
3858 LLVMValueRef base_offset = emit_data->args[3];
3859 unsigned writemask = inst->Dst[0].Register.WriteMask;
3860
3861 while (writemask) {
3862 int start, count;
3863 const char *intrinsic_name;
3864 LLVMValueRef data;
3865 LLVMValueRef offset;
3866 LLVMValueRef tmp;
3867
3868 u_bit_scan_consecutive_range(&writemask, &start, &count);
3869
3870 /* Due to an LLVM limitation, split 3-element writes
3871 * into a 2-element and a 1-element write. */
3872 if (count == 3) {
3873 writemask |= 1 << (start + 2);
3874 count = 2;
3875 }
3876
3877 if (count == 4) {
3878 data = base_data;
3879 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3880 } else if (count == 2) {
3881 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3882
3883 tmp = LLVMBuildExtractElement(
3884 builder, base_data,
3885 lp_build_const_int32(gallivm, start), "");
3886 data = LLVMBuildInsertElement(
3887 builder, LLVMGetUndef(v2f32), tmp,
3888 uint_bld->zero, "");
3889
3890 tmp = LLVMBuildExtractElement(
3891 builder, base_data,
3892 lp_build_const_int32(gallivm, start + 1), "");
3893 data = LLVMBuildInsertElement(
3894 builder, data, tmp, uint_bld->one, "");
3895
3896 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3897 } else {
3898 assert(count == 1);
3899 data = LLVMBuildExtractElement(
3900 builder, base_data,
3901 lp_build_const_int32(gallivm, start), "");
3902 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3903 }
3904
3905 offset = base_offset;
3906 if (start != 0) {
3907 offset = LLVMBuildAdd(
3908 builder, offset,
3909 lp_build_const_int32(gallivm, start * 4), "");
3910 }
3911
3912 emit_data->args[0] = data;
3913 emit_data->args[3] = offset;
3914
3915 lp_build_intrinsic(
3916 builder, intrinsic_name, emit_data->dst_type,
3917 emit_data->args, emit_data->arg_count, 0);
3918 }
3919 }
3920
3921 static void store_emit_memory(
3922 struct si_shader_context *ctx,
3923 struct lp_build_emit_data *emit_data)
3924 {
3925 const struct tgsi_full_instruction *inst = emit_data->inst;
3926 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3927 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3928 LLVMBuilderRef builder = gallivm->builder;
3929 unsigned writemask = inst->Dst[0].Register.WriteMask;
3930 LLVMValueRef ptr, derived_ptr, data, index;
3931 int chan;
3932
3933 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3934
3935 for (chan = 0; chan < 4; ++chan) {
3936 if (!(writemask & (1 << chan))) {
3937 continue;
3938 }
3939 data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 1, chan);
3940 index = lp_build_const_int32(gallivm, chan);
3941 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3942 LLVMBuildStore(builder, data, derived_ptr);
3943 }
3944 }
3945
3946 static void store_emit(
3947 const struct lp_build_tgsi_action *action,
3948 struct lp_build_tgsi_context *bld_base,
3949 struct lp_build_emit_data *emit_data)
3950 {
3951 struct si_shader_context *ctx = si_shader_context(bld_base);
3952 struct gallivm_state *gallivm = bld_base->base.gallivm;
3953 LLVMBuilderRef builder = gallivm->builder;
3954 const struct tgsi_full_instruction * inst = emit_data->inst;
3955 unsigned target = inst->Memory.Texture;
3956 char intrinsic_name[32];
3957 char coords_type[8];
3958
3959 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3960 store_emit_memory(ctx, emit_data);
3961 return;
3962 }
3963
3964 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3965 emit_waitcnt(ctx);
3966
3967 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3968 store_emit_buffer(ctx, emit_data);
3969 return;
3970 }
3971
3972 if (target == TGSI_TEXTURE_BUFFER) {
3973 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3974 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3975 emit_data->dst_type, emit_data->args,
3976 emit_data->arg_count, 0);
3977 } else {
3978 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
3979 coords_type, sizeof(coords_type));
3980 snprintf(intrinsic_name, sizeof(intrinsic_name),
3981 "llvm.amdgcn.image.store.%s", coords_type);
3982
3983 emit_data->output[emit_data->chan] =
3984 lp_build_intrinsic(
3985 builder, intrinsic_name, emit_data->dst_type,
3986 emit_data->args, emit_data->arg_count, 0);
3987 }
3988 }
3989
3990 static void atomic_fetch_args(
3991 struct lp_build_tgsi_context * bld_base,
3992 struct lp_build_emit_data * emit_data)
3993 {
3994 struct si_shader_context *ctx = si_shader_context(bld_base);
3995 struct gallivm_state *gallivm = bld_base->base.gallivm;
3996 LLVMBuilderRef builder = gallivm->builder;
3997 const struct tgsi_full_instruction * inst = emit_data->inst;
3998 LLVMValueRef data1, data2;
3999 LLVMValueRef rsrc;
4000 LLVMValueRef tmp;
4001
4002 emit_data->dst_type = bld_base->base.elem_type;
4003
4004 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
4005 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
4006
4007 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4008 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
4009 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
4010 }
4011
4012 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
4013 * of arguments, which is reversed relative to TGSI (and GLSL)
4014 */
4015 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4016 emit_data->args[emit_data->arg_count++] = data2;
4017 emit_data->args[emit_data->arg_count++] = data1;
4018
4019 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4020 LLVMValueRef offset;
4021
4022 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
4023
4024 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
4025 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
4026
4027 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
4028 offset, true);
4029 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
4030 unsigned target = inst->Memory.Texture;
4031 LLVMValueRef coords;
4032
4033 image_fetch_rsrc(bld_base, &inst->Src[0],
4034 target != TGSI_TEXTURE_BUFFER, &rsrc);
4035 coords = image_fetch_coords(bld_base, inst, 1);
4036
4037 if (target == TGSI_TEXTURE_BUFFER) {
4038 rsrc = extract_rsrc_top_half(ctx, rsrc);
4039 buffer_append_args(ctx, emit_data, rsrc, coords,
4040 bld_base->uint_bld.zero, true);
4041 } else {
4042 emit_data->args[emit_data->arg_count++] = coords;
4043 emit_data->args[emit_data->arg_count++] = rsrc;
4044
4045 image_append_args(ctx, emit_data, target, true);
4046 }
4047 }
4048 }
4049
4050 static void atomic_emit_memory(struct si_shader_context *ctx,
4051 struct lp_build_emit_data *emit_data) {
4052 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4053 LLVMBuilderRef builder = gallivm->builder;
4054 const struct tgsi_full_instruction * inst = emit_data->inst;
4055 LLVMValueRef ptr, result, arg;
4056
4057 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
4058
4059 arg = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 2, 0);
4060 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
4061
4062 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4063 LLVMValueRef new_data;
4064 new_data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base,
4065 inst, 3, 0);
4066
4067 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
4068
4069 #if HAVE_LLVM >= 0x309
4070 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
4071 LLVMAtomicOrderingSequentiallyConsistent,
4072 LLVMAtomicOrderingSequentiallyConsistent,
4073 false);
4074 #endif
4075
4076 result = LLVMBuildExtractValue(builder, result, 0, "");
4077 } else {
4078 LLVMAtomicRMWBinOp op;
4079
4080 switch(inst->Instruction.Opcode) {
4081 case TGSI_OPCODE_ATOMUADD:
4082 op = LLVMAtomicRMWBinOpAdd;
4083 break;
4084 case TGSI_OPCODE_ATOMXCHG:
4085 op = LLVMAtomicRMWBinOpXchg;
4086 break;
4087 case TGSI_OPCODE_ATOMAND:
4088 op = LLVMAtomicRMWBinOpAnd;
4089 break;
4090 case TGSI_OPCODE_ATOMOR:
4091 op = LLVMAtomicRMWBinOpOr;
4092 break;
4093 case TGSI_OPCODE_ATOMXOR:
4094 op = LLVMAtomicRMWBinOpXor;
4095 break;
4096 case TGSI_OPCODE_ATOMUMIN:
4097 op = LLVMAtomicRMWBinOpUMin;
4098 break;
4099 case TGSI_OPCODE_ATOMUMAX:
4100 op = LLVMAtomicRMWBinOpUMax;
4101 break;
4102 case TGSI_OPCODE_ATOMIMIN:
4103 op = LLVMAtomicRMWBinOpMin;
4104 break;
4105 case TGSI_OPCODE_ATOMIMAX:
4106 op = LLVMAtomicRMWBinOpMax;
4107 break;
4108 default:
4109 unreachable("unknown atomic opcode");
4110 }
4111
4112 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
4113 LLVMAtomicOrderingSequentiallyConsistent,
4114 false);
4115 }
4116 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
4117 }
4118
4119 static void atomic_emit(
4120 const struct lp_build_tgsi_action *action,
4121 struct lp_build_tgsi_context *bld_base,
4122 struct lp_build_emit_data *emit_data)
4123 {
4124 struct si_shader_context *ctx = si_shader_context(bld_base);
4125 struct gallivm_state *gallivm = bld_base->base.gallivm;
4126 LLVMBuilderRef builder = gallivm->builder;
4127 const struct tgsi_full_instruction * inst = emit_data->inst;
4128 char intrinsic_name[40];
4129 LLVMValueRef tmp;
4130
4131 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
4132 atomic_emit_memory(ctx, emit_data);
4133 return;
4134 }
4135
4136 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
4137 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4138 snprintf(intrinsic_name, sizeof(intrinsic_name),
4139 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
4140 } else {
4141 char coords_type[8];
4142
4143 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
4144 coords_type, sizeof(coords_type));
4145 snprintf(intrinsic_name, sizeof(intrinsic_name),
4146 "llvm.amdgcn.image.atomic.%s.%s",
4147 action->intr_name, coords_type);
4148 }
4149
4150 tmp = lp_build_intrinsic(
4151 builder, intrinsic_name, bld_base->uint_bld.elem_type,
4152 emit_data->args, emit_data->arg_count, 0);
4153 emit_data->output[emit_data->chan] =
4154 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
4155 }
4156
4157 static void resq_fetch_args(
4158 struct lp_build_tgsi_context * bld_base,
4159 struct lp_build_emit_data * emit_data)
4160 {
4161 struct si_shader_context *ctx = si_shader_context(bld_base);
4162 struct gallivm_state *gallivm = bld_base->base.gallivm;
4163 const struct tgsi_full_instruction *inst = emit_data->inst;
4164 const struct tgsi_full_src_register *reg = &inst->Src[0];
4165
4166 emit_data->dst_type = ctx->v4i32;
4167
4168 if (reg->Register.File == TGSI_FILE_BUFFER) {
4169 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4170 emit_data->arg_count = 1;
4171 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4172 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[0]);
4173 emit_data->arg_count = 1;
4174 } else {
4175 emit_data->args[0] = bld_base->uint_bld.zero; /* mip level */
4176 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[1]);
4177 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
4178 emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
4179 emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
4180 emit_data->args[5] = tgsi_is_array_image(inst->Memory.Texture) ?
4181 bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da */
4182 emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
4183 emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
4184 emit_data->args[8] = bld_base->uint_bld.zero; /* tfe */
4185 emit_data->args[9] = bld_base->uint_bld.zero; /* lwe */
4186 emit_data->arg_count = 10;
4187 }
4188 }
4189
4190 static void resq_emit(
4191 const struct lp_build_tgsi_action *action,
4192 struct lp_build_tgsi_context *bld_base,
4193 struct lp_build_emit_data *emit_data)
4194 {
4195 struct gallivm_state *gallivm = bld_base->base.gallivm;
4196 LLVMBuilderRef builder = gallivm->builder;
4197 const struct tgsi_full_instruction *inst = emit_data->inst;
4198 LLVMValueRef out;
4199
4200 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4201 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4202 lp_build_const_int32(gallivm, 2), "");
4203 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4204 out = get_buffer_size(bld_base, emit_data->args[0]);
4205 } else {
4206 out = lp_build_intrinsic(
4207 builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
4208 emit_data->args, emit_data->arg_count,
4209 LLVMReadNoneAttribute);
4210
4211 /* Divide the number of layers by 6 to get the number of cubes. */
4212 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
4213 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
4214 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
4215
4216 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4217 z = LLVMBuildSDiv(builder, z, imm6, "");
4218 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4219 }
4220 }
4221
4222 emit_data->output[emit_data->chan] = out;
4223 }
4224
4225 static void set_tex_fetch_args(struct si_shader_context *ctx,
4226 struct lp_build_emit_data *emit_data,
4227 unsigned opcode, unsigned target,
4228 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4229 LLVMValueRef *param, unsigned count,
4230 unsigned dmask)
4231 {
4232 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4233 unsigned num_args;
4234 unsigned is_rect = target == TGSI_TEXTURE_RECT;
4235
4236 /* Pad to power of two vector */
4237 while (count < util_next_power_of_two(count))
4238 param[count++] = LLVMGetUndef(ctx->i32);
4239
4240 /* Texture coordinates. */
4241 if (count > 1)
4242 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
4243 else
4244 emit_data->args[0] = param[0];
4245
4246 /* Resource. */
4247 emit_data->args[1] = res_ptr;
4248 num_args = 2;
4249
4250 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
4251 emit_data->dst_type = ctx->v4i32;
4252 else {
4253 emit_data->dst_type = ctx->v4f32;
4254
4255 emit_data->args[num_args++] = samp_ptr;
4256 }
4257
4258 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
4259 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
4260 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
4261 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
4262 tgsi_is_array_sampler(target)); /* da */
4263 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
4264 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
4265 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
4266 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
4267
4268 emit_data->arg_count = num_args;
4269 }
4270
4271 static const struct lp_build_tgsi_action tex_action;
4272
4273 enum desc_type {
4274 DESC_IMAGE,
4275 DESC_FMASK,
4276 DESC_SAMPLER
4277 };
4278
4279 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
4280 {
4281 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
4282 CONST_ADDR_SPACE);
4283 }
4284
4285 /**
4286 * Load an image view, fmask view. or sampler state descriptor.
4287 */
4288 static LLVMValueRef get_sampler_desc_custom(struct si_shader_context *ctx,
4289 LLVMValueRef list, LLVMValueRef index,
4290 enum desc_type type)
4291 {
4292 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4293 LLVMBuilderRef builder = gallivm->builder;
4294
4295 switch (type) {
4296 case DESC_IMAGE:
4297 /* The image is at [0:7]. */
4298 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4299 break;
4300 case DESC_FMASK:
4301 /* The FMASK is at [8:15]. */
4302 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4303 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4304 break;
4305 case DESC_SAMPLER:
4306 /* The sampler state is at [12:15]. */
4307 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4308 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4309 list = LLVMBuildPointerCast(builder, list,
4310 const_array(ctx->v4i32, 0), "");
4311 break;
4312 }
4313
4314 return build_indexed_load_const(ctx, list, index);
4315 }
4316
4317 static LLVMValueRef get_sampler_desc(struct si_shader_context *ctx,
4318 LLVMValueRef index, enum desc_type type)
4319 {
4320 LLVMValueRef list = LLVMGetParam(ctx->radeon_bld.main_fn,
4321 SI_PARAM_SAMPLERS);
4322
4323 return get_sampler_desc_custom(ctx, list, index, type);
4324 }
4325
4326 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4327 *
4328 * SI-CI:
4329 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4330 * filtering manually. The driver sets img7 to a mask clearing
4331 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4332 * s_and_b32 samp0, samp0, img7
4333 *
4334 * VI:
4335 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4336 */
4337 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4338 LLVMValueRef res, LLVMValueRef samp)
4339 {
4340 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
4341 LLVMValueRef img7, samp0;
4342
4343 if (ctx->screen->b.chip_class >= VI)
4344 return samp;
4345
4346 img7 = LLVMBuildExtractElement(builder, res,
4347 LLVMConstInt(ctx->i32, 7, 0), "");
4348 samp0 = LLVMBuildExtractElement(builder, samp,
4349 LLVMConstInt(ctx->i32, 0, 0), "");
4350 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4351 return LLVMBuildInsertElement(builder, samp, samp0,
4352 LLVMConstInt(ctx->i32, 0, 0), "");
4353 }
4354
4355 static void tex_fetch_ptrs(
4356 struct lp_build_tgsi_context *bld_base,
4357 struct lp_build_emit_data *emit_data,
4358 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4359 {
4360 struct si_shader_context *ctx = si_shader_context(bld_base);
4361 const struct tgsi_full_instruction *inst = emit_data->inst;
4362 unsigned target = inst->Texture.Texture;
4363 unsigned sampler_src;
4364 unsigned sampler_index;
4365
4366 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4367 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
4368
4369 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
4370 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
4371 LLVMValueRef ind_index;
4372
4373 ind_index = get_bounded_indirect_index(ctx,
4374 &reg->Indirect,
4375 reg->Register.Index,
4376 SI_NUM_SAMPLERS);
4377
4378 *res_ptr = get_sampler_desc(ctx, ind_index, DESC_IMAGE);
4379
4380 if (target == TGSI_TEXTURE_2D_MSAA ||
4381 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4382 if (samp_ptr)
4383 *samp_ptr = NULL;
4384 if (fmask_ptr)
4385 *fmask_ptr = get_sampler_desc(ctx, ind_index, DESC_FMASK);
4386 } else {
4387 if (samp_ptr) {
4388 *samp_ptr = get_sampler_desc(ctx, ind_index, DESC_SAMPLER);
4389 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4390 }
4391 if (fmask_ptr)
4392 *fmask_ptr = NULL;
4393 }
4394 } else {
4395 *res_ptr = ctx->sampler_views[sampler_index];
4396 if (samp_ptr)
4397 *samp_ptr = ctx->sampler_states[sampler_index];
4398 if (fmask_ptr)
4399 *fmask_ptr = ctx->fmasks[sampler_index];
4400 }
4401 }
4402
4403 static void txq_fetch_args(
4404 struct lp_build_tgsi_context *bld_base,
4405 struct lp_build_emit_data *emit_data)
4406 {
4407 struct si_shader_context *ctx = si_shader_context(bld_base);
4408 struct gallivm_state *gallivm = bld_base->base.gallivm;
4409 LLVMBuilderRef builder = gallivm->builder;
4410 const struct tgsi_full_instruction *inst = emit_data->inst;
4411 unsigned target = inst->Texture.Texture;
4412 LLVMValueRef res_ptr;
4413 LLVMValueRef address;
4414
4415 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4416
4417 if (target == TGSI_TEXTURE_BUFFER) {
4418 /* Read the size from the buffer descriptor directly. */
4419 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4420 emit_data->args[0] = get_buffer_size(bld_base, res);
4421 return;
4422 }
4423
4424 /* Textures - set the mip level. */
4425 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4426
4427 set_tex_fetch_args(ctx, emit_data, TGSI_OPCODE_TXQ, target, res_ptr,
4428 NULL, &address, 1, 0xf);
4429 }
4430
4431 static void txq_emit(const struct lp_build_tgsi_action *action,
4432 struct lp_build_tgsi_context *bld_base,
4433 struct lp_build_emit_data *emit_data)
4434 {
4435 struct lp_build_context *base = &bld_base->base;
4436 unsigned target = emit_data->inst->Texture.Texture;
4437
4438 if (target == TGSI_TEXTURE_BUFFER) {
4439 /* Just return the buffer size. */
4440 emit_data->output[emit_data->chan] = emit_data->args[0];
4441 return;
4442 }
4443
4444 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4445 base->gallivm->builder, "llvm.SI.getresinfo.i32",
4446 emit_data->dst_type, emit_data->args, emit_data->arg_count,
4447 LLVMReadNoneAttribute);
4448
4449 /* Divide the number of layers by 6 to get the number of cubes. */
4450 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4451 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4452 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4453 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4454 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4455
4456 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4457 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4458 z = LLVMBuildSDiv(builder, z, six, "");
4459
4460 emit_data->output[emit_data->chan] =
4461 LLVMBuildInsertElement(builder, v4, z, two, "");
4462 }
4463 }
4464
4465 static void tex_fetch_args(
4466 struct lp_build_tgsi_context *bld_base,
4467 struct lp_build_emit_data *emit_data)
4468 {
4469 struct si_shader_context *ctx = si_shader_context(bld_base);
4470 struct gallivm_state *gallivm = bld_base->base.gallivm;
4471 const struct tgsi_full_instruction *inst = emit_data->inst;
4472 unsigned opcode = inst->Instruction.Opcode;
4473 unsigned target = inst->Texture.Texture;
4474 LLVMValueRef coords[5], derivs[6];
4475 LLVMValueRef address[16];
4476 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4477 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4478 unsigned count = 0;
4479 unsigned chan;
4480 unsigned num_deriv_channels = 0;
4481 bool has_offset = inst->Texture.NumOffsets > 0;
4482 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4483 unsigned dmask = 0xf;
4484
4485 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4486
4487 if (target == TGSI_TEXTURE_BUFFER) {
4488 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
4489
4490 /* Bitcast and truncate v8i32 to v16i8. */
4491 LLVMValueRef res = res_ptr;
4492 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
4493 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
4494 res = LLVMBuildBitCast(gallivm->builder, res, ctx->v16i8, "");
4495
4496 emit_data->dst_type = ctx->v4f32;
4497 emit_data->args[0] = res;
4498 emit_data->args[1] = bld_base->uint_bld.zero;
4499 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4500 emit_data->arg_count = 3;
4501 return;
4502 }
4503
4504 /* Fetch and project texture coordinates */
4505 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4506 for (chan = 0; chan < 3; chan++ ) {
4507 coords[chan] = lp_build_emit_fetch(bld_base,
4508 emit_data->inst, 0,
4509 chan);
4510 if (opcode == TGSI_OPCODE_TXP)
4511 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4512 TGSI_OPCODE_DIV,
4513 coords[chan],
4514 coords[3]);
4515 }
4516
4517 if (opcode == TGSI_OPCODE_TXP)
4518 coords[3] = bld_base->base.one;
4519
4520 /* Pack offsets. */
4521 if (has_offset && opcode != TGSI_OPCODE_TXF) {
4522 /* The offsets are six-bit signed integers packed like this:
4523 * X=[5:0], Y=[13:8], and Z=[21:16].
4524 */
4525 LLVMValueRef offset[3], pack;
4526
4527 assert(inst->Texture.NumOffsets == 1);
4528
4529 for (chan = 0; chan < 3; chan++) {
4530 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4531 emit_data->inst, 0, chan);
4532 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4533 lp_build_const_int32(gallivm, 0x3f), "");
4534 if (chan)
4535 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4536 lp_build_const_int32(gallivm, chan*8), "");
4537 }
4538
4539 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4540 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4541 address[count++] = pack;
4542 }
4543
4544 /* Pack LOD bias value */
4545 if (opcode == TGSI_OPCODE_TXB)
4546 address[count++] = coords[3];
4547 if (opcode == TGSI_OPCODE_TXB2)
4548 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4549
4550 /* Pack depth comparison value */
4551 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4552 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4553 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4554 } else {
4555 assert(ref_pos >= 0);
4556 address[count++] = coords[ref_pos];
4557 }
4558 }
4559
4560 /* Pack user derivatives */
4561 if (opcode == TGSI_OPCODE_TXD) {
4562 int param, num_src_deriv_channels;
4563
4564 switch (target) {
4565 case TGSI_TEXTURE_3D:
4566 num_src_deriv_channels = 3;
4567 num_deriv_channels = 3;
4568 break;
4569 case TGSI_TEXTURE_2D:
4570 case TGSI_TEXTURE_SHADOW2D:
4571 case TGSI_TEXTURE_RECT:
4572 case TGSI_TEXTURE_SHADOWRECT:
4573 case TGSI_TEXTURE_2D_ARRAY:
4574 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4575 num_src_deriv_channels = 2;
4576 num_deriv_channels = 2;
4577 break;
4578 case TGSI_TEXTURE_CUBE:
4579 case TGSI_TEXTURE_SHADOWCUBE:
4580 case TGSI_TEXTURE_CUBE_ARRAY:
4581 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4582 /* Cube derivatives will be converted to 2D. */
4583 num_src_deriv_channels = 3;
4584 num_deriv_channels = 2;
4585 break;
4586 case TGSI_TEXTURE_1D:
4587 case TGSI_TEXTURE_SHADOW1D:
4588 case TGSI_TEXTURE_1D_ARRAY:
4589 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4590 num_src_deriv_channels = 1;
4591 num_deriv_channels = 1;
4592 break;
4593 default:
4594 unreachable("invalid target");
4595 }
4596
4597 for (param = 0; param < 2; param++)
4598 for (chan = 0; chan < num_src_deriv_channels; chan++)
4599 derivs[param * num_src_deriv_channels + chan] =
4600 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4601 }
4602
4603 if (target == TGSI_TEXTURE_CUBE ||
4604 target == TGSI_TEXTURE_CUBE_ARRAY ||
4605 target == TGSI_TEXTURE_SHADOWCUBE ||
4606 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4607 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
4608
4609 if (opcode == TGSI_OPCODE_TXD)
4610 for (int i = 0; i < num_deriv_channels * 2; i++)
4611 address[count++] = derivs[i];
4612
4613 /* Pack texture coordinates */
4614 address[count++] = coords[0];
4615 if (num_coords > 1)
4616 address[count++] = coords[1];
4617 if (num_coords > 2)
4618 address[count++] = coords[2];
4619
4620 /* Pack LOD or sample index */
4621 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4622 address[count++] = coords[3];
4623 else if (opcode == TGSI_OPCODE_TXL2)
4624 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4625
4626 if (count > 16) {
4627 assert(!"Cannot handle more than 16 texture address parameters");
4628 count = 16;
4629 }
4630
4631 for (chan = 0; chan < count; chan++ ) {
4632 address[chan] = LLVMBuildBitCast(gallivm->builder,
4633 address[chan], ctx->i32, "");
4634 }
4635
4636 /* Adjust the sample index according to FMASK.
4637 *
4638 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4639 * which is the identity mapping. Each nibble says which physical sample
4640 * should be fetched to get that sample.
4641 *
4642 * For example, 0x11111100 means there are only 2 samples stored and
4643 * the second sample covers 3/4 of the pixel. When reading samples 0
4644 * and 1, return physical sample 0 (determined by the first two 0s
4645 * in FMASK), otherwise return physical sample 1.
4646 *
4647 * The sample index should be adjusted as follows:
4648 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4649 */
4650 if (target == TGSI_TEXTURE_2D_MSAA ||
4651 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4652 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4653 struct lp_build_emit_data txf_emit_data = *emit_data;
4654 LLVMValueRef txf_address[4];
4655 unsigned txf_count = count;
4656 struct tgsi_full_instruction inst = {};
4657
4658 memcpy(txf_address, address, sizeof(txf_address));
4659
4660 if (target == TGSI_TEXTURE_2D_MSAA) {
4661 txf_address[2] = bld_base->uint_bld.zero;
4662 }
4663 txf_address[3] = bld_base->uint_bld.zero;
4664
4665 /* Read FMASK using TXF. */
4666 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4667 inst.Texture.Texture = target;
4668 txf_emit_data.inst = &inst;
4669 txf_emit_data.chan = 0;
4670 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
4671 target, fmask_ptr, NULL,
4672 txf_address, txf_count, 0xf);
4673 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4674
4675 /* Initialize some constants. */
4676 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4677 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4678
4679 /* Apply the formula. */
4680 LLVMValueRef fmask =
4681 LLVMBuildExtractElement(gallivm->builder,
4682 txf_emit_data.output[0],
4683 uint_bld->zero, "");
4684
4685 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4686
4687 LLVMValueRef sample_index4 =
4688 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4689
4690 LLVMValueRef shifted_fmask =
4691 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4692
4693 LLVMValueRef final_sample =
4694 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4695
4696 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4697 * resource descriptor is 0 (invalid),
4698 */
4699 LLVMValueRef fmask_desc =
4700 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4701 ctx->v8i32, "");
4702
4703 LLVMValueRef fmask_word1 =
4704 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4705 uint_bld->one, "");
4706
4707 LLVMValueRef word1_is_nonzero =
4708 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4709 fmask_word1, uint_bld->zero, "");
4710
4711 /* Replace the MSAA sample index. */
4712 address[sample_chan] =
4713 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4714 final_sample, address[sample_chan], "");
4715 }
4716
4717 if (opcode == TGSI_OPCODE_TXF) {
4718 /* add tex offsets */
4719 if (inst->Texture.NumOffsets) {
4720 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4721 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
4722 const struct tgsi_texture_offset *off = inst->TexOffsets;
4723
4724 assert(inst->Texture.NumOffsets == 1);
4725
4726 switch (target) {
4727 case TGSI_TEXTURE_3D:
4728 address[2] = lp_build_add(uint_bld, address[2],
4729 bld->immediates[off->Index][off->SwizzleZ]);
4730 /* fall through */
4731 case TGSI_TEXTURE_2D:
4732 case TGSI_TEXTURE_SHADOW2D:
4733 case TGSI_TEXTURE_RECT:
4734 case TGSI_TEXTURE_SHADOWRECT:
4735 case TGSI_TEXTURE_2D_ARRAY:
4736 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4737 address[1] =
4738 lp_build_add(uint_bld, address[1],
4739 bld->immediates[off->Index][off->SwizzleY]);
4740 /* fall through */
4741 case TGSI_TEXTURE_1D:
4742 case TGSI_TEXTURE_SHADOW1D:
4743 case TGSI_TEXTURE_1D_ARRAY:
4744 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4745 address[0] =
4746 lp_build_add(uint_bld, address[0],
4747 bld->immediates[off->Index][off->SwizzleX]);
4748 break;
4749 /* texture offsets do not apply to other texture targets */
4750 }
4751 }
4752 }
4753
4754 if (opcode == TGSI_OPCODE_TG4) {
4755 unsigned gather_comp = 0;
4756
4757 /* DMASK was repurposed for GATHER4. 4 components are always
4758 * returned and DMASK works like a swizzle - it selects
4759 * the component to fetch. The only valid DMASK values are
4760 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4761 * (red,red,red,red) etc.) The ISA document doesn't mention
4762 * this.
4763 */
4764
4765 /* Get the component index from src1.x for Gather4. */
4766 if (!tgsi_is_shadow_target(target)) {
4767 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4768 LLVMValueRef comp_imm;
4769 struct tgsi_src_register src1 = inst->Src[1].Register;
4770
4771 assert(src1.File == TGSI_FILE_IMMEDIATE);
4772
4773 comp_imm = imms[src1.Index][src1.SwizzleX];
4774 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4775 gather_comp = CLAMP(gather_comp, 0, 3);
4776 }
4777
4778 dmask = 1 << gather_comp;
4779 }
4780
4781 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
4782 samp_ptr, address, count, dmask);
4783 }
4784
4785 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
4786 * incorrectly forces nearest filtering if the texture format is integer.
4787 * The only effect it has on Gather4, which always returns 4 texels for
4788 * bilinear filtering, is that the final coordinates are off by 0.5 of
4789 * the texel size.
4790 *
4791 * The workaround is to subtract 0.5 from the unnormalized coordinates,
4792 * or (0.5 / size) from the normalized coordinates.
4793 */
4794 static void si_lower_gather4_integer(struct si_shader_context *ctx,
4795 struct lp_build_emit_data *emit_data,
4796 const char *intr_name,
4797 unsigned coord_vgpr_index)
4798 {
4799 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
4800 LLVMValueRef coord = emit_data->args[0];
4801 LLVMValueRef half_texel[2];
4802 int c;
4803
4804 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_RECT ||
4805 emit_data->inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
4806 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
4807 } else {
4808 struct tgsi_full_instruction txq_inst = {};
4809 struct lp_build_emit_data txq_emit_data = {};
4810
4811 /* Query the texture size. */
4812 txq_inst.Texture.Texture = emit_data->inst->Texture.Texture;
4813 txq_emit_data.inst = &txq_inst;
4814 txq_emit_data.dst_type = ctx->v4i32;
4815 set_tex_fetch_args(ctx, &txq_emit_data, TGSI_OPCODE_TXQ,
4816 txq_inst.Texture.Texture,
4817 emit_data->args[1], NULL,
4818 &ctx->radeon_bld.soa.bld_base.uint_bld.zero,
4819 1, 0xf);
4820 txq_emit(NULL, &ctx->radeon_bld.soa.bld_base, &txq_emit_data);
4821
4822 /* Compute -0.5 / size. */
4823 for (c = 0; c < 2; c++) {
4824 half_texel[c] =
4825 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
4826 LLVMConstInt(ctx->i32, c, 0), "");
4827 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
4828 half_texel[c] =
4829 lp_build_emit_llvm_unary(&ctx->radeon_bld.soa.bld_base,
4830 TGSI_OPCODE_RCP, half_texel[c]);
4831 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
4832 LLVMConstReal(ctx->f32, -0.5), "");
4833 }
4834 }
4835
4836 for (c = 0; c < 2; c++) {
4837 LLVMValueRef tmp;
4838 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
4839
4840 tmp = LLVMBuildExtractElement(builder, coord, index, "");
4841 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4842 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
4843 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4844 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
4845 }
4846
4847 emit_data->args[0] = coord;
4848 emit_data->output[emit_data->chan] =
4849 lp_build_intrinsic(builder, intr_name, emit_data->dst_type,
4850 emit_data->args, emit_data->arg_count,
4851 LLVMReadNoneAttribute);
4852 }
4853
4854 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4855 struct lp_build_tgsi_context *bld_base,
4856 struct lp_build_emit_data *emit_data)
4857 {
4858 struct si_shader_context *ctx = si_shader_context(bld_base);
4859 struct lp_build_context *base = &bld_base->base;
4860 const struct tgsi_full_instruction *inst = emit_data->inst;
4861 unsigned opcode = inst->Instruction.Opcode;
4862 unsigned target = inst->Texture.Texture;
4863 char intr_name[127];
4864 bool has_offset = inst->Texture.NumOffsets > 0;
4865 bool is_shadow = tgsi_is_shadow_target(target);
4866 char type[64];
4867 const char *name = "llvm.SI.image.sample";
4868 const char *infix = "";
4869
4870 if (target == TGSI_TEXTURE_BUFFER) {
4871 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4872 base->gallivm->builder,
4873 "llvm.SI.vs.load.input", emit_data->dst_type,
4874 emit_data->args, emit_data->arg_count,
4875 LLVMReadNoneAttribute);
4876 return;
4877 }
4878
4879 switch (opcode) {
4880 case TGSI_OPCODE_TXF:
4881 name = target == TGSI_TEXTURE_2D_MSAA ||
4882 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4883 "llvm.SI.image.load" :
4884 "llvm.SI.image.load.mip";
4885 is_shadow = false;
4886 has_offset = false;
4887 break;
4888 case TGSI_OPCODE_LODQ:
4889 name = "llvm.SI.getlod";
4890 is_shadow = false;
4891 has_offset = false;
4892 break;
4893 case TGSI_OPCODE_TEX:
4894 case TGSI_OPCODE_TEX2:
4895 case TGSI_OPCODE_TXP:
4896 if (ctx->type != PIPE_SHADER_FRAGMENT)
4897 infix = ".lz";
4898 break;
4899 case TGSI_OPCODE_TXB:
4900 case TGSI_OPCODE_TXB2:
4901 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4902 infix = ".b";
4903 break;
4904 case TGSI_OPCODE_TXL:
4905 case TGSI_OPCODE_TXL2:
4906 infix = ".l";
4907 break;
4908 case TGSI_OPCODE_TXD:
4909 infix = ".d";
4910 break;
4911 case TGSI_OPCODE_TG4:
4912 name = "llvm.SI.gather4";
4913 infix = ".lz";
4914 break;
4915 default:
4916 assert(0);
4917 return;
4918 }
4919
4920 /* Add the type and suffixes .c, .o if needed. */
4921 build_int_type_name(LLVMTypeOf(emit_data->args[0]), type, sizeof(type));
4922 sprintf(intr_name, "%s%s%s%s.%s",
4923 name, is_shadow ? ".c" : "", infix,
4924 has_offset ? ".o" : "", type);
4925
4926 /* The hardware needs special lowering for Gather4 with integer formats. */
4927 if (opcode == TGSI_OPCODE_TG4) {
4928 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4929 /* This will also work with non-constant indexing because of how
4930 * glsl_to_tgsi works and we intent to preserve that behavior.
4931 */
4932 const unsigned src_idx = 2;
4933 unsigned sampler = inst->Src[src_idx].Register.Index;
4934
4935 assert(inst->Src[src_idx].Register.File == TGSI_FILE_SAMPLER);
4936
4937 if (info->sampler_type[sampler] == TGSI_RETURN_TYPE_SINT ||
4938 info->sampler_type[sampler] == TGSI_RETURN_TYPE_UINT) {
4939 /* Texture coordinates start after:
4940 * {offset, bias, z-compare, derivatives}
4941 * Only the offset and z-compare can occur here.
4942 */
4943 si_lower_gather4_integer(ctx, emit_data, intr_name,
4944 (int)has_offset + (int)is_shadow);
4945 return;
4946 }
4947 }
4948
4949 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4950 base->gallivm->builder, intr_name, emit_data->dst_type,
4951 emit_data->args, emit_data->arg_count,
4952 LLVMReadNoneAttribute);
4953 }
4954
4955 static void si_llvm_emit_txqs(
4956 const struct lp_build_tgsi_action *action,
4957 struct lp_build_tgsi_context *bld_base,
4958 struct lp_build_emit_data *emit_data)
4959 {
4960 struct si_shader_context *ctx = si_shader_context(bld_base);
4961 struct gallivm_state *gallivm = bld_base->base.gallivm;
4962 LLVMBuilderRef builder = gallivm->builder;
4963 LLVMValueRef res, samples;
4964 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4965
4966 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4967
4968
4969 /* Read the samples from the descriptor directly. */
4970 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4971 samples = LLVMBuildExtractElement(
4972 builder, res,
4973 lp_build_const_int32(gallivm, 3), "");
4974 samples = LLVMBuildLShr(builder, samples,
4975 lp_build_const_int32(gallivm, 16), "");
4976 samples = LLVMBuildAnd(builder, samples,
4977 lp_build_const_int32(gallivm, 0xf), "");
4978 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
4979 samples, "");
4980
4981 emit_data->output[emit_data->chan] = samples;
4982 }
4983
4984 /*
4985 * SI implements derivatives using the local data store (LDS)
4986 * All writes to the LDS happen in all executing threads at
4987 * the same time. TID is the Thread ID for the current
4988 * thread and is a value between 0 and 63, representing
4989 * the thread's position in the wavefront.
4990 *
4991 * For the pixel shader threads are grouped into quads of four pixels.
4992 * The TIDs of the pixels of a quad are:
4993 *
4994 * +------+------+
4995 * |4n + 0|4n + 1|
4996 * +------+------+
4997 * |4n + 2|4n + 3|
4998 * +------+------+
4999 *
5000 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
5001 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
5002 * the current pixel's column, and masking with 0xfffffffe yields the TID
5003 * of the left pixel of the current pixel's row.
5004 *
5005 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
5006 * adding 2 yields the TID of the pixel below the top pixel.
5007 */
5008 /* masks for thread ID. */
5009 #define TID_MASK_TOP_LEFT 0xfffffffc
5010 #define TID_MASK_TOP 0xfffffffd
5011 #define TID_MASK_LEFT 0xfffffffe
5012
5013 static void si_llvm_emit_ddxy(
5014 const struct lp_build_tgsi_action *action,
5015 struct lp_build_tgsi_context *bld_base,
5016 struct lp_build_emit_data *emit_data)
5017 {
5018 struct si_shader_context *ctx = si_shader_context(bld_base);
5019 struct gallivm_state *gallivm = bld_base->base.gallivm;
5020 const struct tgsi_full_instruction *inst = emit_data->inst;
5021 unsigned opcode = inst->Instruction.Opcode;
5022 LLVMValueRef indices[2];
5023 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
5024 LLVMValueRef tl, trbl, result[4];
5025 LLVMValueRef tl_tid, trbl_tid;
5026 unsigned swizzle[4];
5027 unsigned c;
5028 int idx;
5029 unsigned mask;
5030
5031 indices[0] = bld_base->uint_bld.zero;
5032 indices[1] = get_thread_id(ctx);
5033 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
5034 indices, 2, "");
5035
5036 if (opcode == TGSI_OPCODE_DDX_FINE)
5037 mask = TID_MASK_LEFT;
5038 else if (opcode == TGSI_OPCODE_DDY_FINE)
5039 mask = TID_MASK_TOP;
5040 else
5041 mask = TID_MASK_TOP_LEFT;
5042
5043 tl_tid = LLVMBuildAnd(gallivm->builder, indices[1],
5044 lp_build_const_int32(gallivm, mask), "");
5045 indices[1] = tl_tid;
5046 load_ptr0 = LLVMBuildGEP(gallivm->builder, ctx->lds,
5047 indices, 2, "");
5048
5049 /* for DDX we want to next X pixel, DDY next Y pixel. */
5050 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
5051 trbl_tid = LLVMBuildAdd(gallivm->builder, indices[1],
5052 lp_build_const_int32(gallivm, idx), "");
5053 indices[1] = trbl_tid;
5054 load_ptr1 = LLVMBuildGEP(gallivm->builder, ctx->lds,
5055 indices, 2, "");
5056
5057 for (c = 0; c < 4; ++c) {
5058 unsigned i;
5059 LLVMValueRef val;
5060 LLVMValueRef args[2];
5061
5062 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
5063 for (i = 0; i < c; ++i) {
5064 if (swizzle[i] == swizzle[c]) {
5065 result[c] = result[i];
5066 break;
5067 }
5068 }
5069 if (i != c)
5070 continue;
5071
5072 val = LLVMBuildBitCast(gallivm->builder,
5073 lp_build_emit_fetch(bld_base, inst, 0, c),
5074 ctx->i32, "");
5075
5076 if ((HAVE_LLVM >= 0x0309) && ctx->screen->b.family >= CHIP_TONGA) {
5077
5078 args[0] = LLVMBuildMul(gallivm->builder, tl_tid,
5079 lp_build_const_int32(gallivm, 4), "");
5080 args[1] = val;
5081 tl = lp_build_intrinsic(gallivm->builder,
5082 "llvm.amdgcn.ds.bpermute", ctx->i32,
5083 args, 2, LLVMReadNoneAttribute);
5084
5085 args[0] = LLVMBuildMul(gallivm->builder, trbl_tid,
5086 lp_build_const_int32(gallivm, 4), "");
5087 trbl = lp_build_intrinsic(gallivm->builder,
5088 "llvm.amdgcn.ds.bpermute", ctx->i32,
5089 args, 2, LLVMReadNoneAttribute);
5090 } else {
5091 LLVMBuildStore(gallivm->builder, val, store_ptr);
5092 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
5093 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
5094 }
5095 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
5096 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
5097 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
5098 }
5099
5100 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
5101 }
5102
5103 /*
5104 * this takes an I,J coordinate pair,
5105 * and works out the X and Y derivatives.
5106 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
5107 */
5108 static LLVMValueRef si_llvm_emit_ddxy_interp(
5109 struct lp_build_tgsi_context *bld_base,
5110 LLVMValueRef interp_ij)
5111 {
5112 struct si_shader_context *ctx = si_shader_context(bld_base);
5113 struct gallivm_state *gallivm = bld_base->base.gallivm;
5114 LLVMValueRef indices[2];
5115 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
5116 LLVMValueRef tl, tr, bl, result[4];
5117 unsigned c;
5118
5119 indices[0] = bld_base->uint_bld.zero;
5120 indices[1] = get_thread_id(ctx);
5121 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
5122 indices, 2, "");
5123
5124 temp = LLVMBuildAnd(gallivm->builder, indices[1],
5125 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
5126
5127 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
5128 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
5129
5130 indices[1] = temp;
5131 load_ptr_x = LLVMBuildGEP(gallivm->builder, ctx->lds,
5132 indices, 2, "");
5133
5134 indices[1] = temp2;
5135 load_ptr_y = LLVMBuildGEP(gallivm->builder, ctx->lds,
5136 indices, 2, "");
5137
5138 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
5139 lp_build_const_int32(gallivm, 1), "");
5140 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, ctx->lds,
5141 indices, 2, "");
5142
5143 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
5144 lp_build_const_int32(gallivm, 2), "");
5145 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, ctx->lds,
5146 indices, 2, "");
5147
5148 for (c = 0; c < 2; ++c) {
5149 LLVMValueRef store_val;
5150 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
5151
5152 store_val = LLVMBuildExtractElement(gallivm->builder,
5153 interp_ij, c_ll, "");
5154 LLVMBuildStore(gallivm->builder,
5155 store_val,
5156 store_ptr);
5157
5158 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
5159 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
5160
5161 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
5162 tr = LLVMBuildBitCast(gallivm->builder, tr, ctx->f32, "");
5163
5164 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
5165
5166 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
5167 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
5168
5169 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
5170 bl = LLVMBuildBitCast(gallivm->builder, bl, ctx->f32, "");
5171
5172 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
5173 }
5174
5175 return lp_build_gather_values(gallivm, result, 4);
5176 }
5177
5178 static void interp_fetch_args(
5179 struct lp_build_tgsi_context *bld_base,
5180 struct lp_build_emit_data *emit_data)
5181 {
5182 struct si_shader_context *ctx = si_shader_context(bld_base);
5183 struct gallivm_state *gallivm = bld_base->base.gallivm;
5184 const struct tgsi_full_instruction *inst = emit_data->inst;
5185
5186 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
5187 /* offset is in second src, first two channels */
5188 emit_data->args[0] = lp_build_emit_fetch(bld_base,
5189 emit_data->inst, 1,
5190 TGSI_CHAN_X);
5191 emit_data->args[1] = lp_build_emit_fetch(bld_base,
5192 emit_data->inst, 1,
5193 TGSI_CHAN_Y);
5194 emit_data->arg_count = 2;
5195 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5196 LLVMValueRef sample_position;
5197 LLVMValueRef sample_id;
5198 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
5199
5200 /* fetch sample ID, then fetch its sample position,
5201 * and place into first two channels.
5202 */
5203 sample_id = lp_build_emit_fetch(bld_base,
5204 emit_data->inst, 1, TGSI_CHAN_X);
5205 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
5206 ctx->i32, "");
5207 sample_position = load_sample_position(&ctx->radeon_bld, sample_id);
5208
5209 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
5210 sample_position,
5211 lp_build_const_int32(gallivm, 0), "");
5212
5213 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
5214 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
5215 sample_position,
5216 lp_build_const_int32(gallivm, 1), "");
5217 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
5218 emit_data->arg_count = 2;
5219 }
5220 }
5221
5222 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
5223 struct lp_build_tgsi_context *bld_base,
5224 struct lp_build_emit_data *emit_data)
5225 {
5226 struct si_shader_context *ctx = si_shader_context(bld_base);
5227 struct si_shader *shader = ctx->shader;
5228 struct gallivm_state *gallivm = bld_base->base.gallivm;
5229 LLVMValueRef interp_param;
5230 const struct tgsi_full_instruction *inst = emit_data->inst;
5231 const char *intr_name;
5232 int input_index = inst->Src[0].Register.Index;
5233 int chan;
5234 int i;
5235 LLVMValueRef attr_number;
5236 LLVMValueRef params = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
5237 int interp_param_idx;
5238 unsigned interp = shader->selector->info.input_interpolate[input_index];
5239 unsigned location;
5240
5241 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5242
5243 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5244 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
5245 location = TGSI_INTERPOLATE_LOC_CENTER;
5246 else
5247 location = TGSI_INTERPOLATE_LOC_CENTROID;
5248
5249 interp_param_idx = lookup_interp_param_index(interp, location);
5250 if (interp_param_idx == -1)
5251 return;
5252 else if (interp_param_idx)
5253 interp_param = get_interp_param(ctx, interp_param_idx);
5254 else
5255 interp_param = NULL;
5256
5257 attr_number = lp_build_const_int32(gallivm, input_index);
5258
5259 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5260 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5261 LLVMValueRef ij_out[2];
5262 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
5263
5264 /*
5265 * take the I then J parameters, and the DDX/Y for it, and
5266 * calculate the IJ inputs for the interpolator.
5267 * temp1 = ddx * offset/sample.x + I;
5268 * interp_param.I = ddy * offset/sample.y + temp1;
5269 * temp1 = ddx * offset/sample.x + J;
5270 * interp_param.J = ddy * offset/sample.y + temp1;
5271 */
5272 for (i = 0; i < 2; i++) {
5273 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
5274 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
5275 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
5276 ddxy_out, ix_ll, "");
5277 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
5278 ddxy_out, iy_ll, "");
5279 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5280 interp_param, ix_ll, "");
5281 LLVMValueRef temp1, temp2;
5282
5283 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5284 ctx->f32, "");
5285
5286 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5287
5288 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5289
5290 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5291
5292 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5293
5294 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
5295 temp2, ctx->i32, "");
5296 }
5297 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
5298 }
5299
5300 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
5301 for (chan = 0; chan < 2; chan++) {
5302 LLVMValueRef args[4];
5303 LLVMValueRef llvm_chan;
5304 unsigned schan;
5305
5306 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5307 llvm_chan = lp_build_const_int32(gallivm, schan);
5308
5309 args[0] = llvm_chan;
5310 args[1] = attr_number;
5311 args[2] = params;
5312 args[3] = interp_param;
5313
5314 emit_data->output[chan] =
5315 lp_build_intrinsic(gallivm->builder, intr_name,
5316 ctx->f32, args, args[3] ? 4 : 3,
5317 LLVMReadNoneAttribute);
5318 }
5319 }
5320
5321 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5322 struct lp_build_emit_data *emit_data)
5323 {
5324 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
5325 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5326 unsigned stream;
5327
5328 assert(src0.File == TGSI_FILE_IMMEDIATE);
5329
5330 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
5331 return stream;
5332 }
5333
5334 /* Emit one vertex from the geometry shader */
5335 static void si_llvm_emit_vertex(
5336 const struct lp_build_tgsi_action *action,
5337 struct lp_build_tgsi_context *bld_base,
5338 struct lp_build_emit_data *emit_data)
5339 {
5340 struct si_shader_context *ctx = si_shader_context(bld_base);
5341 struct lp_build_context *uint = &bld_base->uint_bld;
5342 struct si_shader *shader = ctx->shader;
5343 struct tgsi_shader_info *info = &shader->selector->info;
5344 struct gallivm_state *gallivm = bld_base->base.gallivm;
5345 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
5346 SI_PARAM_GS2VS_OFFSET);
5347 LLVMValueRef gs_next_vertex;
5348 LLVMValueRef can_emit, kill;
5349 LLVMValueRef args[2];
5350 unsigned chan;
5351 int i;
5352 unsigned stream;
5353
5354 stream = si_llvm_get_stream(bld_base, emit_data);
5355
5356 /* Write vertex attribute values to GSVS ring */
5357 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5358 ctx->gs_next_vertex[stream],
5359 "");
5360
5361 /* If this thread has already emitted the declared maximum number of
5362 * vertices, kill it: excessive vertex emissions are not supposed to
5363 * have any effect, and GS threads have no externally observable
5364 * effects other than emitting vertices.
5365 */
5366 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
5367 lp_build_const_int32(gallivm,
5368 shader->selector->gs_max_out_vertices), "");
5369 kill = lp_build_select(&bld_base->base, can_emit,
5370 lp_build_const_float(gallivm, 1.0f),
5371 lp_build_const_float(gallivm, -1.0f));
5372
5373 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
5374 ctx->voidt, &kill, 1, 0);
5375
5376 for (i = 0; i < info->num_outputs; i++) {
5377 LLVMValueRef *out_ptr =
5378 ctx->radeon_bld.soa.outputs[i];
5379
5380 for (chan = 0; chan < 4; chan++) {
5381 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5382 LLVMValueRef voffset =
5383 lp_build_const_int32(gallivm, (i * 4 + chan) *
5384 shader->selector->gs_max_out_vertices);
5385
5386 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5387 voffset = lp_build_mul_imm(uint, voffset, 4);
5388
5389 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5390
5391 build_tbuffer_store(ctx,
5392 ctx->gsvs_ring[stream],
5393 out_val, 1,
5394 voffset, soffset, 0,
5395 V_008F0C_BUF_DATA_FORMAT_32,
5396 V_008F0C_BUF_NUM_FORMAT_UINT,
5397 1, 0, 1, 1, 0);
5398 }
5399 }
5400 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5401 lp_build_const_int32(gallivm, 1));
5402
5403 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5404
5405 /* Signal vertex emission */
5406 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
5407 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
5408 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5409 ctx->voidt, args, 2, 0);
5410 }
5411
5412 /* Cut one primitive from the geometry shader */
5413 static void si_llvm_emit_primitive(
5414 const struct lp_build_tgsi_action *action,
5415 struct lp_build_tgsi_context *bld_base,
5416 struct lp_build_emit_data *emit_data)
5417 {
5418 struct si_shader_context *ctx = si_shader_context(bld_base);
5419 struct gallivm_state *gallivm = bld_base->base.gallivm;
5420 LLVMValueRef args[2];
5421 unsigned stream;
5422
5423 /* Signal primitive cut */
5424 stream = si_llvm_get_stream(bld_base, emit_data);
5425 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
5426 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
5427 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5428 ctx->voidt, args, 2, 0);
5429 }
5430
5431 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5432 struct lp_build_tgsi_context *bld_base,
5433 struct lp_build_emit_data *emit_data)
5434 {
5435 struct si_shader_context *ctx = si_shader_context(bld_base);
5436 struct gallivm_state *gallivm = bld_base->base.gallivm;
5437
5438 /* The real barrier instruction isn’t needed, because an entire patch
5439 * always fits into a single wave.
5440 */
5441 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
5442 emit_optimization_barrier(ctx);
5443 return;
5444 }
5445
5446 lp_build_intrinsic(gallivm->builder,
5447 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5448 : "llvm.AMDGPU.barrier.local",
5449 ctx->voidt, NULL, 0, 0);
5450 }
5451
5452 static const struct lp_build_tgsi_action tex_action = {
5453 .fetch_args = tex_fetch_args,
5454 .emit = build_tex_intrinsic,
5455 };
5456
5457 static const struct lp_build_tgsi_action interp_action = {
5458 .fetch_args = interp_fetch_args,
5459 .emit = build_interp_intrinsic,
5460 };
5461
5462 static void si_create_function(struct si_shader_context *ctx,
5463 LLVMTypeRef *returns, unsigned num_returns,
5464 LLVMTypeRef *params, unsigned num_params,
5465 int last_sgpr)
5466 {
5467 int i;
5468
5469 radeon_llvm_create_func(&ctx->radeon_bld, returns, num_returns,
5470 params, num_params);
5471 radeon_llvm_shader_type(ctx->radeon_bld.main_fn, ctx->type);
5472 ctx->return_value = LLVMGetUndef(ctx->radeon_bld.return_type);
5473
5474 for (i = 0; i <= last_sgpr; ++i) {
5475 LLVMValueRef P = LLVMGetParam(ctx->radeon_bld.main_fn, i);
5476
5477 /* The combination of:
5478 * - ByVal
5479 * - dereferenceable
5480 * - invariant.load
5481 * allows the optimization passes to move loads and reduces
5482 * SGPR spilling significantly.
5483 */
5484 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
5485 LLVMAddAttribute(P, LLVMByValAttribute);
5486 lp_add_attr_dereferenceable(P, UINT64_MAX);
5487 } else
5488 LLVMAddAttribute(P, LLVMInRegAttribute);
5489 }
5490
5491 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5492 /* These were copied from some LLVM test. */
5493 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5494 "less-precise-fpmad",
5495 "true");
5496 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5497 "no-infs-fp-math",
5498 "true");
5499 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5500 "no-nans-fp-math",
5501 "true");
5502 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5503 "unsafe-fp-math",
5504 "true");
5505 }
5506 }
5507
5508 static void create_meta_data(struct si_shader_context *ctx)
5509 {
5510 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
5511
5512 ctx->invariant_load_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5513 "invariant.load", 14);
5514 ctx->range_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5515 "range", 5);
5516 ctx->uniform_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5517 "amdgpu.uniform", 14);
5518
5519 ctx->empty_md = LLVMMDNodeInContext(gallivm->context, NULL, 0);
5520 }
5521
5522 static void declare_streamout_params(struct si_shader_context *ctx,
5523 struct pipe_stream_output_info *so,
5524 LLVMTypeRef *params, LLVMTypeRef i32,
5525 unsigned *num_params)
5526 {
5527 int i;
5528
5529 /* Streamout SGPRs. */
5530 if (so->num_outputs) {
5531 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5532 params[ctx->param_streamout_config = (*num_params)++] = i32;
5533 else
5534 ctx->param_streamout_config = ctx->param_tess_offchip;
5535
5536 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5537 }
5538 /* A streamout buffer offset is loaded if the stride is non-zero. */
5539 for (i = 0; i < 4; i++) {
5540 if (!so->stride[i])
5541 continue;
5542
5543 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5544 }
5545 }
5546
5547 static unsigned llvm_get_type_size(LLVMTypeRef type)
5548 {
5549 LLVMTypeKind kind = LLVMGetTypeKind(type);
5550
5551 switch (kind) {
5552 case LLVMIntegerTypeKind:
5553 return LLVMGetIntTypeWidth(type) / 8;
5554 case LLVMFloatTypeKind:
5555 return 4;
5556 case LLVMPointerTypeKind:
5557 return 8;
5558 case LLVMVectorTypeKind:
5559 return LLVMGetVectorSize(type) *
5560 llvm_get_type_size(LLVMGetElementType(type));
5561 default:
5562 assert(0);
5563 return 0;
5564 }
5565 }
5566
5567 static void declare_tess_lds(struct si_shader_context *ctx)
5568 {
5569 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5570 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5571 struct lp_build_context *uint = &bld_base->uint_bld;
5572
5573 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5574 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, uint->zero,
5575 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
5576 "tess_lds");
5577 }
5578
5579 static void create_function(struct si_shader_context *ctx)
5580 {
5581 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5582 struct gallivm_state *gallivm = bld_base->base.gallivm;
5583 struct si_shader *shader = ctx->shader;
5584 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
5585 LLVMTypeRef returns[16+32*4];
5586 unsigned i, last_sgpr, num_params, num_return_sgprs;
5587 unsigned num_returns = 0;
5588
5589 v3i32 = LLVMVectorType(ctx->i32, 3);
5590
5591 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5592 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5593 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5594 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5595 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5596
5597 switch (ctx->type) {
5598 case PIPE_SHADER_VERTEX:
5599 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
5600 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5601 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5602 params[SI_PARAM_DRAWID] = ctx->i32;
5603 num_params = SI_PARAM_DRAWID+1;
5604
5605 if (shader->key.vs.as_es) {
5606 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5607 } else if (shader->key.vs.as_ls) {
5608 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
5609 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
5610 } else {
5611 if (ctx->is_gs_copy_shader) {
5612 num_params = SI_PARAM_RW_BUFFERS+1;
5613 } else {
5614 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5615 num_params = SI_PARAM_VS_STATE_BITS+1;
5616 }
5617
5618 /* The locations of the other parameters are assigned dynamically. */
5619 declare_streamout_params(ctx, &shader->selector->so,
5620 params, ctx->i32, &num_params);
5621 }
5622
5623 last_sgpr = num_params-1;
5624
5625 /* VGPRs */
5626 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5627 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5628 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5629 params[ctx->param_instance_id = num_params++] = ctx->i32;
5630
5631 if (!ctx->is_monolithic &&
5632 !ctx->is_gs_copy_shader) {
5633 /* Vertex load indices. */
5634 ctx->param_vertex_index0 = num_params;
5635
5636 for (i = 0; i < shader->selector->info.num_inputs; i++)
5637 params[num_params++] = ctx->i32;
5638
5639 /* PrimitiveID output. */
5640 if (!shader->key.vs.as_es && !shader->key.vs.as_ls)
5641 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5642 returns[num_returns++] = ctx->f32;
5643 }
5644 break;
5645
5646 case PIPE_SHADER_TESS_CTRL:
5647 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5648 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5649 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5650 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5651 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5652 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5653 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5654
5655 /* VGPRs */
5656 params[SI_PARAM_PATCH_ID] = ctx->i32;
5657 params[SI_PARAM_REL_IDS] = ctx->i32;
5658 num_params = SI_PARAM_REL_IDS+1;
5659
5660 if (!ctx->is_monolithic) {
5661 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5662 * placed after the user SGPRs.
5663 */
5664 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5665 returns[num_returns++] = ctx->i32; /* SGPRs */
5666
5667 for (i = 0; i < 3; i++)
5668 returns[num_returns++] = ctx->f32; /* VGPRs */
5669 }
5670 break;
5671
5672 case PIPE_SHADER_TESS_EVAL:
5673 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5674 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5675
5676 if (shader->key.tes.as_es) {
5677 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5678 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5679 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5680 } else {
5681 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5682 declare_streamout_params(ctx, &shader->selector->so,
5683 params, ctx->i32, &num_params);
5684 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5685 }
5686 last_sgpr = num_params - 1;
5687
5688 /* VGPRs */
5689 params[ctx->param_tes_u = num_params++] = ctx->f32;
5690 params[ctx->param_tes_v = num_params++] = ctx->f32;
5691 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5692 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5693
5694 /* PrimitiveID output. */
5695 if (!ctx->is_monolithic && !shader->key.tes.as_es)
5696 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5697 returns[num_returns++] = ctx->f32;
5698 break;
5699
5700 case PIPE_SHADER_GEOMETRY:
5701 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5702 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5703 last_sgpr = SI_PARAM_GS_WAVE_ID;
5704
5705 /* VGPRs */
5706 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5707 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5708 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5709 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5710 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5711 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5712 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5713 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5714 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5715 break;
5716
5717 case PIPE_SHADER_FRAGMENT:
5718 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5719 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5720 last_sgpr = SI_PARAM_PRIM_MASK;
5721 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5722 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5723 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5724 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5725 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5726 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5727 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5728 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5729 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5730 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5731 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5732 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5733 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5734 params[SI_PARAM_ANCILLARY] = ctx->i32;
5735 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5736 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5737 num_params = SI_PARAM_POS_FIXED_PT+1;
5738
5739 if (!ctx->is_monolithic) {
5740 /* Color inputs from the prolog. */
5741 if (shader->selector->info.colors_read) {
5742 unsigned num_color_elements =
5743 util_bitcount(shader->selector->info.colors_read);
5744
5745 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5746 for (i = 0; i < num_color_elements; i++)
5747 params[num_params++] = ctx->f32;
5748 }
5749
5750 /* Outputs for the epilog. */
5751 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5752 num_returns =
5753 num_return_sgprs +
5754 util_bitcount(shader->selector->info.colors_written) * 4 +
5755 shader->selector->info.writes_z +
5756 shader->selector->info.writes_stencil +
5757 shader->selector->info.writes_samplemask +
5758 1 /* SampleMaskIn */;
5759
5760 num_returns = MAX2(num_returns,
5761 num_return_sgprs +
5762 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5763
5764 for (i = 0; i < num_return_sgprs; i++)
5765 returns[i] = ctx->i32;
5766 for (; i < num_returns; i++)
5767 returns[i] = ctx->f32;
5768 }
5769 break;
5770
5771 case PIPE_SHADER_COMPUTE:
5772 params[SI_PARAM_GRID_SIZE] = v3i32;
5773 params[SI_PARAM_BLOCK_ID] = v3i32;
5774 last_sgpr = SI_PARAM_BLOCK_ID;
5775
5776 params[SI_PARAM_THREAD_ID] = v3i32;
5777 num_params = SI_PARAM_THREAD_ID + 1;
5778 break;
5779 default:
5780 assert(0 && "unimplemented shader");
5781 return;
5782 }
5783
5784 assert(num_params <= ARRAY_SIZE(params));
5785
5786 si_create_function(ctx, returns, num_returns, params,
5787 num_params, last_sgpr);
5788
5789 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5790 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5791 !ctx->is_monolithic) {
5792 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5793 "InitialPSInputAddr",
5794 S_0286D0_PERSP_SAMPLE_ENA(1) |
5795 S_0286D0_PERSP_CENTER_ENA(1) |
5796 S_0286D0_PERSP_CENTROID_ENA(1) |
5797 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5798 S_0286D0_LINEAR_CENTER_ENA(1) |
5799 S_0286D0_LINEAR_CENTROID_ENA(1) |
5800 S_0286D0_FRONT_FACE_ENA(1) |
5801 S_0286D0_POS_FIXED_PT_ENA(1));
5802 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5803 const unsigned *properties = shader->selector->info.properties;
5804 unsigned max_work_group_size =
5805 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5806 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5807 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5808
5809 assert(max_work_group_size);
5810
5811 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5812 "amdgpu-max-work-group-size",
5813 max_work_group_size);
5814 }
5815
5816 shader->info.num_input_sgprs = 0;
5817 shader->info.num_input_vgprs = 0;
5818
5819 for (i = 0; i <= last_sgpr; ++i)
5820 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5821
5822 /* Unused fragment shader inputs are eliminated by the compiler,
5823 * so we don't know yet how many there will be.
5824 */
5825 if (ctx->type != PIPE_SHADER_FRAGMENT)
5826 for (; i < num_params; ++i)
5827 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5828
5829 if (bld_base->info &&
5830 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5831 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5832 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5833 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5834 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5835 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5836 ctx->lds =
5837 LLVMAddGlobalInAddressSpace(gallivm->module,
5838 LLVMArrayType(ctx->i32, 64),
5839 "ddxy_lds",
5840 LOCAL_ADDR_SPACE);
5841
5842 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.vs.as_ls) ||
5843 ctx->type == PIPE_SHADER_TESS_CTRL ||
5844 ctx->type == PIPE_SHADER_TESS_EVAL)
5845 declare_tess_lds(ctx);
5846 }
5847
5848 static void preload_constant_buffers(struct si_shader_context *ctx)
5849 {
5850 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5851 struct gallivm_state *gallivm = bld_base->base.gallivm;
5852 const struct tgsi_shader_info *info = bld_base->info;
5853 unsigned buf;
5854 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
5855
5856 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
5857 if (info->const_file_max[buf] == -1)
5858 continue;
5859
5860 /* Load the resource descriptor */
5861 ctx->const_buffers[buf] =
5862 build_indexed_load_const(ctx, ptr, lp_build_const_int32(gallivm, buf));
5863 }
5864 }
5865
5866 static void preload_shader_buffers(struct si_shader_context *ctx)
5867 {
5868 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5869 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_SHADER_BUFFERS);
5870 int buf, maxbuf;
5871
5872 maxbuf = MIN2(ctx->shader->selector->info.file_max[TGSI_FILE_BUFFER],
5873 SI_NUM_SHADER_BUFFERS - 1);
5874 for (buf = 0; buf <= maxbuf; ++buf) {
5875 ctx->shader_buffers[buf] =
5876 build_indexed_load_const(
5877 ctx, ptr, lp_build_const_int32(gallivm, buf));
5878 }
5879 }
5880
5881 static void preload_samplers(struct si_shader_context *ctx)
5882 {
5883 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5884 struct gallivm_state *gallivm = bld_base->base.gallivm;
5885 const struct tgsi_shader_info *info = bld_base->info;
5886 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
5887 LLVMValueRef offset;
5888
5889 if (num_samplers == 0)
5890 return;
5891
5892 /* Load the resources and samplers, we rely on the code sinking to do the rest */
5893 for (i = 0; i < num_samplers; ++i) {
5894 /* Resource */
5895 offset = lp_build_const_int32(gallivm, i);
5896 ctx->sampler_views[i] =
5897 get_sampler_desc(ctx, offset, DESC_IMAGE);
5898
5899 /* FMASK resource */
5900 if (info->is_msaa_sampler[i])
5901 ctx->fmasks[i] =
5902 get_sampler_desc(ctx, offset, DESC_FMASK);
5903 else {
5904 ctx->sampler_states[i] =
5905 get_sampler_desc(ctx, offset, DESC_SAMPLER);
5906 ctx->sampler_states[i] =
5907 sici_fix_sampler_aniso(ctx, ctx->sampler_views[i],
5908 ctx->sampler_states[i]);
5909 }
5910 }
5911 }
5912
5913 static void preload_images(struct si_shader_context *ctx)
5914 {
5915 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5916 struct tgsi_shader_info *info = &ctx->shader->selector->info;
5917 struct gallivm_state *gallivm = bld_base->base.gallivm;
5918 unsigned num_images = bld_base->info->file_max[TGSI_FILE_IMAGE] + 1;
5919 LLVMValueRef res_ptr;
5920 unsigned i;
5921
5922 if (num_images == 0)
5923 return;
5924
5925 res_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
5926
5927 for (i = 0; i < num_images; ++i) {
5928 /* Rely on LLVM to shrink the load for buffer resources. */
5929 LLVMValueRef rsrc =
5930 build_indexed_load_const(ctx, res_ptr,
5931 lp_build_const_int32(gallivm, i));
5932
5933 if (info->images_writemask & (1 << i) &&
5934 !(info->images_buffers & (1 << i)))
5935 rsrc = force_dcc_off(ctx, rsrc);
5936
5937 ctx->images[i] = rsrc;
5938 }
5939 }
5940
5941 /**
5942 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5943 * for later use.
5944 */
5945 static void preload_ring_buffers(struct si_shader_context *ctx)
5946 {
5947 struct gallivm_state *gallivm =
5948 ctx->radeon_bld.soa.bld_base.base.gallivm;
5949
5950 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
5951 SI_PARAM_RW_BUFFERS);
5952
5953 if ((ctx->type == PIPE_SHADER_VERTEX &&
5954 ctx->shader->key.vs.as_es) ||
5955 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5956 ctx->shader->key.tes.as_es) ||
5957 ctx->type == PIPE_SHADER_GEOMETRY) {
5958 unsigned ring =
5959 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5960 : SI_ES_RING_ESGS;
5961 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5962
5963 ctx->esgs_ring =
5964 build_indexed_load_const(ctx, buf_ptr, offset);
5965 }
5966
5967 if (ctx->is_gs_copy_shader) {
5968 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_VS_RING_GSVS);
5969
5970 ctx->gsvs_ring[0] =
5971 build_indexed_load_const(ctx, buf_ptr, offset);
5972 }
5973 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5974 int i;
5975 for (i = 0; i < 4; i++) {
5976 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_GS_RING_GSVS0 + i);
5977
5978 ctx->gsvs_ring[i] =
5979 build_indexed_load_const(ctx, buf_ptr, offset);
5980 }
5981 }
5982 }
5983
5984 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5985 LLVMValueRef param_rw_buffers,
5986 unsigned param_pos_fixed_pt)
5987 {
5988 struct lp_build_tgsi_context *bld_base =
5989 &ctx->radeon_bld.soa.bld_base;
5990 struct gallivm_state *gallivm = bld_base->base.gallivm;
5991 LLVMBuilderRef builder = gallivm->builder;
5992 LLVMValueRef slot, desc, offset, row, bit, address[2];
5993
5994 /* Use the fixed-point gl_FragCoord input.
5995 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5996 * per coordinate to get the repeating effect.
5997 */
5998 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5999 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
6000
6001 /* Load the buffer descriptor. */
6002 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
6003 desc = build_indexed_load_const(ctx, param_rw_buffers, slot);
6004
6005 /* The stipple pattern is 32x32, each row has 32 bits. */
6006 offset = LLVMBuildMul(builder, address[1],
6007 LLVMConstInt(ctx->i32, 4, 0), "");
6008 row = buffer_load_const(ctx, desc, offset);
6009 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
6010 bit = LLVMBuildLShr(builder, row, address[0], "");
6011 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
6012
6013 /* The intrinsic kills the thread if arg < 0. */
6014 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
6015 LLVMConstReal(ctx->f32, -1), "");
6016 lp_build_intrinsic(builder, "llvm.AMDGPU.kill", ctx->voidt, &bit, 1, 0);
6017 }
6018
6019 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
6020 struct si_shader_config *conf,
6021 unsigned symbol_offset)
6022 {
6023 unsigned i;
6024 const unsigned char *config =
6025 radeon_shader_binary_config_start(binary, symbol_offset);
6026 bool really_needs_scratch = false;
6027
6028 /* LLVM adds SGPR spills to the scratch size.
6029 * Find out if we really need the scratch buffer.
6030 */
6031 for (i = 0; i < binary->reloc_count; i++) {
6032 const struct radeon_shader_reloc *reloc = &binary->relocs[i];
6033
6034 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
6035 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
6036 really_needs_scratch = true;
6037 break;
6038 }
6039 }
6040
6041 /* XXX: We may be able to emit some of these values directly rather than
6042 * extracting fields to be emitted later.
6043 */
6044
6045 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
6046 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
6047 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
6048 switch (reg) {
6049 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
6050 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
6051 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
6052 case R_00B848_COMPUTE_PGM_RSRC1:
6053 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
6054 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
6055 conf->float_mode = G_00B028_FLOAT_MODE(value);
6056 conf->rsrc1 = value;
6057 break;
6058 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
6059 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
6060 break;
6061 case R_00B84C_COMPUTE_PGM_RSRC2:
6062 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
6063 conf->rsrc2 = value;
6064 break;
6065 case R_0286CC_SPI_PS_INPUT_ENA:
6066 conf->spi_ps_input_ena = value;
6067 break;
6068 case R_0286D0_SPI_PS_INPUT_ADDR:
6069 conf->spi_ps_input_addr = value;
6070 break;
6071 case R_0286E8_SPI_TMPRING_SIZE:
6072 case R_00B860_COMPUTE_TMPRING_SIZE:
6073 /* WAVESIZE is in units of 256 dwords. */
6074 if (really_needs_scratch)
6075 conf->scratch_bytes_per_wave =
6076 G_00B860_WAVESIZE(value) * 256 * 4;
6077 break;
6078 case 0x4: /* SPILLED_SGPRS */
6079 conf->spilled_sgprs = value;
6080 break;
6081 case 0x8: /* SPILLED_VGPRS */
6082 conf->spilled_vgprs = value;
6083 break;
6084 default:
6085 {
6086 static bool printed;
6087
6088 if (!printed) {
6089 fprintf(stderr, "Warning: LLVM emitted unknown "
6090 "config register: 0x%x\n", reg);
6091 printed = true;
6092 }
6093 }
6094 break;
6095 }
6096 }
6097
6098 if (!conf->spi_ps_input_addr)
6099 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
6100 }
6101
6102 void si_shader_apply_scratch_relocs(struct si_context *sctx,
6103 struct si_shader *shader,
6104 struct si_shader_config *config,
6105 uint64_t scratch_va)
6106 {
6107 unsigned i;
6108 uint32_t scratch_rsrc_dword0 = scratch_va;
6109 uint32_t scratch_rsrc_dword1 =
6110 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
6111
6112 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
6113 * correctly.
6114 */
6115 if (HAVE_LLVM >= 0x0309)
6116 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
6117 else
6118 scratch_rsrc_dword1 |=
6119 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
6120
6121 for (i = 0 ; i < shader->binary.reloc_count; i++) {
6122 const struct radeon_shader_reloc *reloc =
6123 &shader->binary.relocs[i];
6124 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
6125 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
6126 &scratch_rsrc_dword0, 4);
6127 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
6128 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
6129 &scratch_rsrc_dword1, 4);
6130 }
6131 }
6132 }
6133
6134 static unsigned si_get_shader_binary_size(struct si_shader *shader)
6135 {
6136 unsigned size = shader->binary.code_size;
6137
6138 if (shader->prolog)
6139 size += shader->prolog->binary.code_size;
6140 if (shader->epilog)
6141 size += shader->epilog->binary.code_size;
6142 return size;
6143 }
6144
6145 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
6146 {
6147 const struct radeon_shader_binary *prolog =
6148 shader->prolog ? &shader->prolog->binary : NULL;
6149 const struct radeon_shader_binary *epilog =
6150 shader->epilog ? &shader->epilog->binary : NULL;
6151 const struct radeon_shader_binary *mainb = &shader->binary;
6152 unsigned bo_size = si_get_shader_binary_size(shader) +
6153 (!epilog ? mainb->rodata_size : 0);
6154 unsigned char *ptr;
6155
6156 assert(!prolog || !prolog->rodata_size);
6157 assert((!prolog && !epilog) || !mainb->rodata_size);
6158 assert(!epilog || !epilog->rodata_size);
6159
6160 r600_resource_reference(&shader->bo, NULL);
6161 shader->bo = si_resource_create_custom(&sscreen->b.b,
6162 PIPE_USAGE_IMMUTABLE,
6163 bo_size);
6164 if (!shader->bo)
6165 return -ENOMEM;
6166
6167 /* Upload. */
6168 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
6169 PIPE_TRANSFER_READ_WRITE);
6170
6171 if (prolog) {
6172 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
6173 ptr += prolog->code_size;
6174 }
6175
6176 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
6177 ptr += mainb->code_size;
6178
6179 if (epilog)
6180 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
6181 else if (mainb->rodata_size > 0)
6182 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
6183
6184 sscreen->b.ws->buffer_unmap(shader->bo->buf);
6185 return 0;
6186 }
6187
6188 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
6189 struct pipe_debug_callback *debug,
6190 const char *name, FILE *file)
6191 {
6192 char *line, *p;
6193 unsigned i, count;
6194
6195 if (binary->disasm_string) {
6196 fprintf(file, "Shader %s disassembly:\n", name);
6197 fprintf(file, "%s", binary->disasm_string);
6198
6199 if (debug && debug->debug_message) {
6200 /* Very long debug messages are cut off, so send the
6201 * disassembly one line at a time. This causes more
6202 * overhead, but on the plus side it simplifies
6203 * parsing of resulting logs.
6204 */
6205 pipe_debug_message(debug, SHADER_INFO,
6206 "Shader Disassembly Begin");
6207
6208 line = binary->disasm_string;
6209 while (*line) {
6210 p = util_strchrnul(line, '\n');
6211 count = p - line;
6212
6213 if (count) {
6214 pipe_debug_message(debug, SHADER_INFO,
6215 "%.*s", count, line);
6216 }
6217
6218 if (!*p)
6219 break;
6220 line = p + 1;
6221 }
6222
6223 pipe_debug_message(debug, SHADER_INFO,
6224 "Shader Disassembly End");
6225 }
6226 } else {
6227 fprintf(file, "Shader %s binary:\n", name);
6228 for (i = 0; i < binary->code_size; i += 4) {
6229 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
6230 binary->code[i + 3], binary->code[i + 2],
6231 binary->code[i + 1], binary->code[i]);
6232 }
6233 }
6234 }
6235
6236 static void si_shader_dump_stats(struct si_screen *sscreen,
6237 struct si_shader_config *conf,
6238 unsigned num_inputs,
6239 unsigned code_size,
6240 struct pipe_debug_callback *debug,
6241 unsigned processor,
6242 FILE *file)
6243 {
6244 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
6245 unsigned lds_per_wave = 0;
6246 unsigned max_simd_waves = 10;
6247
6248 /* Compute LDS usage for PS. */
6249 if (processor == PIPE_SHADER_FRAGMENT) {
6250 /* The minimum usage per wave is (num_inputs * 48). The maximum
6251 * usage is (num_inputs * 48 * 16).
6252 * We can get anything in between and it varies between waves.
6253 *
6254 * The 48 bytes per input for a single primitive is equal to
6255 * 4 bytes/component * 4 components/input * 3 points.
6256 *
6257 * Other stages don't know the size at compile time or don't
6258 * allocate LDS per wave, but instead they do it per thread group.
6259 */
6260 lds_per_wave = conf->lds_size * lds_increment +
6261 align(num_inputs * 48, lds_increment);
6262 }
6263
6264 /* Compute the per-SIMD wave counts. */
6265 if (conf->num_sgprs) {
6266 if (sscreen->b.chip_class >= VI)
6267 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
6268 else
6269 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
6270 }
6271
6272 if (conf->num_vgprs)
6273 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
6274
6275 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
6276 * that PS can use.
6277 */
6278 if (lds_per_wave)
6279 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
6280
6281 if (file != stderr ||
6282 r600_can_dump_shader(&sscreen->b, processor)) {
6283 if (processor == PIPE_SHADER_FRAGMENT) {
6284 fprintf(file, "*** SHADER CONFIG ***\n"
6285 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6286 "SPI_PS_INPUT_ENA = 0x%04x\n",
6287 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
6288 }
6289
6290 fprintf(file, "*** SHADER STATS ***\n"
6291 "SGPRS: %d\n"
6292 "VGPRS: %d\n"
6293 "Spilled SGPRs: %d\n"
6294 "Spilled VGPRs: %d\n"
6295 "Code Size: %d bytes\n"
6296 "LDS: %d blocks\n"
6297 "Scratch: %d bytes per wave\n"
6298 "Max Waves: %d\n"
6299 "********************\n\n\n",
6300 conf->num_sgprs, conf->num_vgprs,
6301 conf->spilled_sgprs, conf->spilled_vgprs, code_size,
6302 conf->lds_size, conf->scratch_bytes_per_wave,
6303 max_simd_waves);
6304 }
6305
6306 pipe_debug_message(debug, SHADER_INFO,
6307 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6308 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
6309 "Spilled VGPRs: %d",
6310 conf->num_sgprs, conf->num_vgprs, code_size,
6311 conf->lds_size, conf->scratch_bytes_per_wave,
6312 max_simd_waves, conf->spilled_sgprs,
6313 conf->spilled_vgprs);
6314 }
6315
6316 static const char *si_get_shader_name(struct si_shader *shader,
6317 unsigned processor)
6318 {
6319 switch (processor) {
6320 case PIPE_SHADER_VERTEX:
6321 if (shader->key.vs.as_es)
6322 return "Vertex Shader as ES";
6323 else if (shader->key.vs.as_ls)
6324 return "Vertex Shader as LS";
6325 else
6326 return "Vertex Shader as VS";
6327 case PIPE_SHADER_TESS_CTRL:
6328 return "Tessellation Control Shader";
6329 case PIPE_SHADER_TESS_EVAL:
6330 if (shader->key.tes.as_es)
6331 return "Tessellation Evaluation Shader as ES";
6332 else
6333 return "Tessellation Evaluation Shader as VS";
6334 case PIPE_SHADER_GEOMETRY:
6335 if (shader->gs_copy_shader == NULL)
6336 return "GS Copy Shader as VS";
6337 else
6338 return "Geometry Shader";
6339 case PIPE_SHADER_FRAGMENT:
6340 return "Pixel Shader";
6341 case PIPE_SHADER_COMPUTE:
6342 return "Compute Shader";
6343 default:
6344 return "Unknown Shader";
6345 }
6346 }
6347
6348 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6349 struct pipe_debug_callback *debug, unsigned processor,
6350 FILE *file)
6351 {
6352 if (file != stderr ||
6353 r600_can_dump_shader(&sscreen->b, processor))
6354 si_dump_shader_key(processor, &shader->key, file);
6355
6356 if (file != stderr && shader->binary.llvm_ir_string) {
6357 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
6358 si_get_shader_name(shader, processor));
6359 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
6360 }
6361
6362 if (file != stderr ||
6363 (r600_can_dump_shader(&sscreen->b, processor) &&
6364 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6365 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6366
6367 if (shader->prolog)
6368 si_shader_dump_disassembly(&shader->prolog->binary,
6369 debug, "prolog", file);
6370
6371 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6372
6373 if (shader->epilog)
6374 si_shader_dump_disassembly(&shader->epilog->binary,
6375 debug, "epilog", file);
6376 fprintf(file, "\n");
6377 }
6378
6379 si_shader_dump_stats(sscreen, &shader->config,
6380 shader->selector ? shader->selector->info.num_inputs : 0,
6381 si_get_shader_binary_size(shader), debug, processor,
6382 file);
6383 }
6384
6385 int si_compile_llvm(struct si_screen *sscreen,
6386 struct radeon_shader_binary *binary,
6387 struct si_shader_config *conf,
6388 LLVMTargetMachineRef tm,
6389 LLVMModuleRef mod,
6390 struct pipe_debug_callback *debug,
6391 unsigned processor,
6392 const char *name)
6393 {
6394 int r = 0;
6395 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6396
6397 if (r600_can_dump_shader(&sscreen->b, processor)) {
6398 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6399
6400 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6401 fprintf(stderr, "%s LLVM IR:\n\n", name);
6402 LLVMDumpModule(mod);
6403 fprintf(stderr, "\n");
6404 }
6405 }
6406
6407 if (sscreen->record_llvm_ir) {
6408 char *ir = LLVMPrintModuleToString(mod);
6409 binary->llvm_ir_string = strdup(ir);
6410 LLVMDisposeMessage(ir);
6411 }
6412
6413 if (!si_replace_shader(count, binary)) {
6414 r = radeon_llvm_compile(mod, binary, tm, debug);
6415 if (r)
6416 return r;
6417 }
6418
6419 si_shader_binary_read_config(binary, conf, 0);
6420
6421 /* Enable 64-bit and 16-bit denormals, because there is no performance
6422 * cost.
6423 *
6424 * If denormals are enabled, all floating-point output modifiers are
6425 * ignored.
6426 *
6427 * Don't enable denormals for 32-bit floats, because:
6428 * - Floating-point output modifiers would be ignored by the hw.
6429 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6430 * have to stop using those.
6431 * - SI & CI would be very slow.
6432 */
6433 conf->float_mode |= V_00B028_FP_64_DENORMS;
6434
6435 FREE(binary->config);
6436 FREE(binary->global_symbol_offsets);
6437 binary->config = NULL;
6438 binary->global_symbol_offsets = NULL;
6439
6440 /* Some shaders can't have rodata because their binaries can be
6441 * concatenated.
6442 */
6443 if (binary->rodata_size &&
6444 (processor == PIPE_SHADER_VERTEX ||
6445 processor == PIPE_SHADER_TESS_CTRL ||
6446 processor == PIPE_SHADER_TESS_EVAL ||
6447 processor == PIPE_SHADER_FRAGMENT)) {
6448 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6449 return -EINVAL;
6450 }
6451
6452 return r;
6453 }
6454
6455 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6456 {
6457 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6458 LLVMBuildRetVoid(ctx->radeon_bld.gallivm.builder);
6459 else
6460 LLVMBuildRet(ctx->radeon_bld.gallivm.builder, ret);
6461 }
6462
6463 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6464 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
6465 struct si_shader_context *ctx,
6466 struct si_shader *gs,
6467 struct pipe_debug_callback *debug)
6468 {
6469 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
6470 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
6471 struct lp_build_context *uint = &bld_base->uint_bld;
6472 struct si_shader_output_values *outputs;
6473 struct tgsi_shader_info *gsinfo = &gs->selector->info;
6474 LLVMValueRef args[9];
6475 int i, r;
6476
6477 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6478
6479 si_init_shader_ctx(ctx, sscreen, ctx->shader, ctx->tm);
6480 ctx->type = PIPE_SHADER_VERTEX;
6481 ctx->is_gs_copy_shader = true;
6482
6483 create_meta_data(ctx);
6484 create_function(ctx);
6485 preload_ring_buffers(ctx);
6486
6487 args[0] = ctx->gsvs_ring[0];
6488 args[1] = lp_build_mul_imm(uint,
6489 LLVMGetParam(ctx->radeon_bld.main_fn,
6490 ctx->param_vertex_id),
6491 4);
6492 args[3] = uint->zero;
6493 args[4] = uint->one; /* OFFEN */
6494 args[5] = uint->zero; /* IDXEN */
6495 args[6] = uint->one; /* GLC */
6496 args[7] = uint->one; /* SLC */
6497 args[8] = uint->zero; /* TFE */
6498
6499 /* Fetch vertex data from GSVS ring */
6500 for (i = 0; i < gsinfo->num_outputs; ++i) {
6501 unsigned chan;
6502
6503 outputs[i].name = gsinfo->output_semantic_name[i];
6504 outputs[i].sid = gsinfo->output_semantic_index[i];
6505
6506 for (chan = 0; chan < 4; chan++) {
6507 args[2] = lp_build_const_int32(gallivm,
6508 (i * 4 + chan) *
6509 gs->selector->gs_max_out_vertices * 16 * 4);
6510
6511 outputs[i].values[chan] =
6512 LLVMBuildBitCast(gallivm->builder,
6513 lp_build_intrinsic(gallivm->builder,
6514 "llvm.SI.buffer.load.dword.i32.i32",
6515 ctx->i32, args, 9,
6516 LLVMReadOnlyAttribute),
6517 ctx->f32, "");
6518 }
6519 }
6520
6521 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6522
6523 LLVMBuildRetVoid(gallivm->builder);
6524
6525 /* Dump LLVM IR before any optimization passes */
6526 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6527 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6528 LLVMDumpModule(bld_base->base.gallivm->module);
6529
6530 radeon_llvm_finalize_module(&ctx->radeon_bld);
6531
6532 r = si_compile_llvm(sscreen, &ctx->shader->binary,
6533 &ctx->shader->config, ctx->tm,
6534 bld_base->base.gallivm->module,
6535 debug, PIPE_SHADER_GEOMETRY,
6536 "GS Copy Shader");
6537 if (!r) {
6538 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6539 fprintf(stderr, "GS Copy Shader:\n");
6540 si_shader_dump(sscreen, ctx->shader, debug,
6541 PIPE_SHADER_GEOMETRY, stderr);
6542 r = si_shader_binary_upload(sscreen, ctx->shader);
6543 }
6544
6545 radeon_llvm_dispose(&ctx->radeon_bld);
6546
6547 FREE(outputs);
6548 return r;
6549 }
6550
6551 static void si_dump_shader_key(unsigned shader, union si_shader_key *key,
6552 FILE *f)
6553 {
6554 int i;
6555
6556 fprintf(f, "SHADER KEY\n");
6557
6558 switch (shader) {
6559 case PIPE_SHADER_VERTEX:
6560 fprintf(f, " instance_divisors = {");
6561 for (i = 0; i < ARRAY_SIZE(key->vs.prolog.instance_divisors); i++)
6562 fprintf(f, !i ? "%u" : ", %u",
6563 key->vs.prolog.instance_divisors[i]);
6564 fprintf(f, "}\n");
6565 fprintf(f, " as_es = %u\n", key->vs.as_es);
6566 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
6567 fprintf(f, " export_prim_id = %u\n", key->vs.epilog.export_prim_id);
6568 break;
6569
6570 case PIPE_SHADER_TESS_CTRL:
6571 fprintf(f, " prim_mode = %u\n", key->tcs.epilog.prim_mode);
6572 break;
6573
6574 case PIPE_SHADER_TESS_EVAL:
6575 fprintf(f, " as_es = %u\n", key->tes.as_es);
6576 fprintf(f, " export_prim_id = %u\n", key->tes.epilog.export_prim_id);
6577 break;
6578
6579 case PIPE_SHADER_GEOMETRY:
6580 case PIPE_SHADER_COMPUTE:
6581 break;
6582
6583 case PIPE_SHADER_FRAGMENT:
6584 fprintf(f, " prolog.color_two_side = %u\n", key->ps.prolog.color_two_side);
6585 fprintf(f, " prolog.flatshade_colors = %u\n", key->ps.prolog.flatshade_colors);
6586 fprintf(f, " prolog.poly_stipple = %u\n", key->ps.prolog.poly_stipple);
6587 fprintf(f, " prolog.force_persp_sample_interp = %u\n", key->ps.prolog.force_persp_sample_interp);
6588 fprintf(f, " prolog.force_linear_sample_interp = %u\n", key->ps.prolog.force_linear_sample_interp);
6589 fprintf(f, " prolog.force_persp_center_interp = %u\n", key->ps.prolog.force_persp_center_interp);
6590 fprintf(f, " prolog.force_linear_center_interp = %u\n", key->ps.prolog.force_linear_center_interp);
6591 fprintf(f, " prolog.bc_optimize_for_persp = %u\n", key->ps.prolog.bc_optimize_for_persp);
6592 fprintf(f, " prolog.bc_optimize_for_linear = %u\n", key->ps.prolog.bc_optimize_for_linear);
6593 fprintf(f, " epilog.spi_shader_col_format = 0x%x\n", key->ps.epilog.spi_shader_col_format);
6594 fprintf(f, " epilog.color_is_int8 = 0x%X\n", key->ps.epilog.color_is_int8);
6595 fprintf(f, " epilog.last_cbuf = %u\n", key->ps.epilog.last_cbuf);
6596 fprintf(f, " epilog.alpha_func = %u\n", key->ps.epilog.alpha_func);
6597 fprintf(f, " epilog.alpha_to_one = %u\n", key->ps.epilog.alpha_to_one);
6598 fprintf(f, " epilog.poly_line_smoothing = %u\n", key->ps.epilog.poly_line_smoothing);
6599 fprintf(f, " epilog.clamp_color = %u\n", key->ps.epilog.clamp_color);
6600 break;
6601
6602 default:
6603 assert(0);
6604 }
6605 }
6606
6607 static void si_init_shader_ctx(struct si_shader_context *ctx,
6608 struct si_screen *sscreen,
6609 struct si_shader *shader,
6610 LLVMTargetMachineRef tm)
6611 {
6612 struct lp_build_tgsi_context *bld_base;
6613 struct lp_build_tgsi_action tmpl = {};
6614
6615 memset(ctx, 0, sizeof(*ctx));
6616 radeon_llvm_context_init(
6617 &ctx->radeon_bld, "amdgcn--",
6618 (shader && shader->selector) ? &shader->selector->info : NULL,
6619 (shader && shader->selector) ? shader->selector->tokens : NULL);
6620 ctx->tm = tm;
6621 ctx->screen = sscreen;
6622 if (shader && shader->selector)
6623 ctx->type = shader->selector->info.processor;
6624 else
6625 ctx->type = -1;
6626 ctx->shader = shader;
6627
6628 ctx->voidt = LLVMVoidTypeInContext(ctx->radeon_bld.gallivm.context);
6629 ctx->i1 = LLVMInt1TypeInContext(ctx->radeon_bld.gallivm.context);
6630 ctx->i8 = LLVMInt8TypeInContext(ctx->radeon_bld.gallivm.context);
6631 ctx->i32 = LLVMInt32TypeInContext(ctx->radeon_bld.gallivm.context);
6632 ctx->i64 = LLVMInt64TypeInContext(ctx->radeon_bld.gallivm.context);
6633 ctx->i128 = LLVMIntTypeInContext(ctx->radeon_bld.gallivm.context, 128);
6634 ctx->f32 = LLVMFloatTypeInContext(ctx->radeon_bld.gallivm.context);
6635 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
6636 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
6637 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
6638 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
6639 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
6640
6641 bld_base = &ctx->radeon_bld.soa.bld_base;
6642 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6643
6644 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6645 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6646 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6647
6648 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6649 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6650 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6651 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6652 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6653 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6654 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6655 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6656 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6657 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6658 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6659 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6660 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6661 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6662
6663 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6664 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6665 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6666 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6667 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6668 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6669
6670 tmpl.fetch_args = atomic_fetch_args;
6671 tmpl.emit = atomic_emit;
6672 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6673 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6674 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6675 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6676 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6677 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6678 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6679 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6680 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6681 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6682 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6683 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6684 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6685 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6686 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6687 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6688 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6689 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6690 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6691 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6692
6693 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6694
6695 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6696 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6697 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6698 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6699
6700 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6701 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6702 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6703
6704 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
6705 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
6706 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
6707 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
6708 }
6709
6710 int si_compile_tgsi_shader(struct si_screen *sscreen,
6711 LLVMTargetMachineRef tm,
6712 struct si_shader *shader,
6713 bool is_monolithic,
6714 struct pipe_debug_callback *debug)
6715 {
6716 struct si_shader_selector *sel = shader->selector;
6717 struct si_shader_context ctx;
6718 struct lp_build_tgsi_context *bld_base;
6719 LLVMModuleRef mod;
6720 int r = 0;
6721
6722 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6723 * conversion fails. */
6724 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
6725 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
6726 tgsi_dump(sel->tokens, 0);
6727 si_dump_streamout(&sel->so);
6728 }
6729
6730 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6731 ctx.is_monolithic = is_monolithic;
6732
6733 shader->info.uses_instanceid = sel->info.uses_instanceid;
6734
6735 bld_base = &ctx.radeon_bld.soa.bld_base;
6736 ctx.radeon_bld.load_system_value = declare_system_value;
6737
6738 switch (ctx.type) {
6739 case PIPE_SHADER_VERTEX:
6740 ctx.radeon_bld.load_input = declare_input_vs;
6741 if (shader->key.vs.as_ls)
6742 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6743 else if (shader->key.vs.as_es)
6744 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6745 else
6746 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6747 break;
6748 case PIPE_SHADER_TESS_CTRL:
6749 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6750 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6751 bld_base->emit_store = store_output_tcs;
6752 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6753 break;
6754 case PIPE_SHADER_TESS_EVAL:
6755 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6756 if (shader->key.tes.as_es)
6757 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6758 else
6759 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6760 break;
6761 case PIPE_SHADER_GEOMETRY:
6762 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6763 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6764 break;
6765 case PIPE_SHADER_FRAGMENT:
6766 ctx.radeon_bld.load_input = declare_input_fs;
6767 if (is_monolithic)
6768 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
6769 else
6770 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6771 break;
6772 case PIPE_SHADER_COMPUTE:
6773 ctx.radeon_bld.declare_memory_region = declare_compute_memory;
6774 break;
6775 default:
6776 assert(!"Unsupported shader type");
6777 return -1;
6778 }
6779
6780 create_meta_data(&ctx);
6781 create_function(&ctx);
6782 preload_constant_buffers(&ctx);
6783 preload_shader_buffers(&ctx);
6784 preload_samplers(&ctx);
6785 preload_images(&ctx);
6786 preload_ring_buffers(&ctx);
6787
6788 if (ctx.is_monolithic && sel->type == PIPE_SHADER_FRAGMENT &&
6789 shader->key.ps.prolog.poly_stipple) {
6790 LLVMValueRef list = LLVMGetParam(ctx.radeon_bld.main_fn,
6791 SI_PARAM_RW_BUFFERS);
6792 si_llvm_emit_polygon_stipple(&ctx, list,
6793 SI_PARAM_POS_FIXED_PT);
6794 }
6795
6796 if (ctx.type == PIPE_SHADER_GEOMETRY) {
6797 int i;
6798 for (i = 0; i < 4; i++) {
6799 ctx.gs_next_vertex[i] =
6800 lp_build_alloca(bld_base->base.gallivm,
6801 ctx.i32, "");
6802 }
6803 }
6804
6805 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6806 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6807 goto out;
6808 }
6809
6810 si_llvm_build_ret(&ctx, ctx.return_value);
6811 mod = bld_base->base.gallivm->module;
6812
6813 /* Dump LLVM IR before any optimization passes */
6814 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6815 r600_can_dump_shader(&sscreen->b, ctx.type))
6816 LLVMDumpModule(mod);
6817
6818 radeon_llvm_finalize_module(&ctx.radeon_bld);
6819
6820 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6821 mod, debug, ctx.type, "TGSI shader");
6822 if (r) {
6823 fprintf(stderr, "LLVM failed to compile shader\n");
6824 goto out;
6825 }
6826
6827 radeon_llvm_dispose(&ctx.radeon_bld);
6828
6829 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6830 * LLVM 3.9svn has this bug.
6831 */
6832 if (sel->type == PIPE_SHADER_COMPUTE) {
6833 unsigned *props = sel->info.properties;
6834 unsigned wave_size = 64;
6835 unsigned max_vgprs = 256;
6836 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
6837 unsigned max_sgprs_per_wave = 128;
6838 unsigned min_waves_per_cu =
6839 DIV_ROUND_UP(props[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
6840 props[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
6841 props[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH],
6842 wave_size);
6843 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6844
6845 max_vgprs = max_vgprs / min_waves_per_simd;
6846 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6847
6848 if (shader->config.num_sgprs > max_sgprs ||
6849 shader->config.num_vgprs > max_vgprs) {
6850 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6851 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6852 shader->config.num_sgprs, shader->config.num_vgprs,
6853 max_sgprs, max_vgprs);
6854
6855 /* Just terminate the process, because dependent
6856 * shaders can hang due to bad input data, but use
6857 * the env var to allow shader-db to work.
6858 */
6859 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6860 abort();
6861 }
6862 }
6863
6864 /* Add the scratch offset to input SGPRs. */
6865 if (shader->config.scratch_bytes_per_wave)
6866 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6867
6868 /* Calculate the number of fragment input VGPRs. */
6869 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6870 shader->info.num_input_vgprs = 0;
6871 shader->info.face_vgpr_index = -1;
6872
6873 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6874 shader->info.num_input_vgprs += 2;
6875 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6876 shader->info.num_input_vgprs += 2;
6877 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6878 shader->info.num_input_vgprs += 2;
6879 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6880 shader->info.num_input_vgprs += 3;
6881 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6882 shader->info.num_input_vgprs += 2;
6883 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6884 shader->info.num_input_vgprs += 2;
6885 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6886 shader->info.num_input_vgprs += 2;
6887 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6888 shader->info.num_input_vgprs += 1;
6889 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6890 shader->info.num_input_vgprs += 1;
6891 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6892 shader->info.num_input_vgprs += 1;
6893 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6894 shader->info.num_input_vgprs += 1;
6895 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6896 shader->info.num_input_vgprs += 1;
6897 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6898 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6899 shader->info.num_input_vgprs += 1;
6900 }
6901 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
6902 shader->info.num_input_vgprs += 1;
6903 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6904 shader->info.num_input_vgprs += 1;
6905 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6906 shader->info.num_input_vgprs += 1;
6907 }
6908
6909 if (ctx.type == PIPE_SHADER_GEOMETRY) {
6910 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
6911 shader->gs_copy_shader->selector = shader->selector;
6912 ctx.shader = shader->gs_copy_shader;
6913 if ((r = si_generate_gs_copy_shader(sscreen, &ctx,
6914 shader, debug))) {
6915 free(shader->gs_copy_shader);
6916 shader->gs_copy_shader = NULL;
6917 goto out;
6918 }
6919 }
6920
6921 out:
6922 return r;
6923 }
6924
6925 /**
6926 * Create, compile and return a shader part (prolog or epilog).
6927 *
6928 * \param sscreen screen
6929 * \param list list of shader parts of the same category
6930 * \param key shader part key
6931 * \param tm LLVM target machine
6932 * \param debug debug callback
6933 * \param compile the callback responsible for compilation
6934 * \return non-NULL on success
6935 */
6936 static struct si_shader_part *
6937 si_get_shader_part(struct si_screen *sscreen,
6938 struct si_shader_part **list,
6939 union si_shader_part_key *key,
6940 LLVMTargetMachineRef tm,
6941 struct pipe_debug_callback *debug,
6942 bool (*compile)(struct si_screen *,
6943 LLVMTargetMachineRef,
6944 struct pipe_debug_callback *,
6945 struct si_shader_part *))
6946 {
6947 struct si_shader_part *result;
6948
6949 pipe_mutex_lock(sscreen->shader_parts_mutex);
6950
6951 /* Find existing. */
6952 for (result = *list; result; result = result->next) {
6953 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6954 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6955 return result;
6956 }
6957 }
6958
6959 /* Compile a new one. */
6960 result = CALLOC_STRUCT(si_shader_part);
6961 result->key = *key;
6962 if (!compile(sscreen, tm, debug, result)) {
6963 FREE(result);
6964 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6965 return NULL;
6966 }
6967
6968 result->next = *list;
6969 *list = result;
6970 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6971 return result;
6972 }
6973
6974 /**
6975 * Create a vertex shader prolog.
6976 *
6977 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6978 * All inputs are returned unmodified. The vertex load indices are
6979 * stored after them, which will used by the API VS for fetching inputs.
6980 *
6981 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6982 * input_v0,
6983 * input_v1,
6984 * input_v2,
6985 * input_v3,
6986 * (VertexID + BaseVertex),
6987 * (InstanceID + StartInstance),
6988 * (InstanceID / 2 + StartInstance)
6989 */
6990 static bool si_compile_vs_prolog(struct si_screen *sscreen,
6991 LLVMTargetMachineRef tm,
6992 struct pipe_debug_callback *debug,
6993 struct si_shader_part *out)
6994 {
6995 union si_shader_part_key *key = &out->key;
6996 struct si_shader shader = {};
6997 struct si_shader_context ctx;
6998 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6999 LLVMTypeRef *params, *returns;
7000 LLVMValueRef ret, func;
7001 int last_sgpr, num_params, num_returns, i;
7002 bool status = true;
7003
7004 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7005 ctx.type = PIPE_SHADER_VERTEX;
7006 ctx.param_vertex_id = key->vs_prolog.num_input_sgprs;
7007 ctx.param_instance_id = key->vs_prolog.num_input_sgprs + 3;
7008
7009 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7010 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
7011 sizeof(LLVMTypeRef));
7012 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
7013 key->vs_prolog.last_input + 1) *
7014 sizeof(LLVMTypeRef));
7015 num_params = 0;
7016 num_returns = 0;
7017
7018 /* Declare input and output SGPRs. */
7019 num_params = 0;
7020 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7021 params[num_params++] = ctx.i32;
7022 returns[num_returns++] = ctx.i32;
7023 }
7024 last_sgpr = num_params - 1;
7025
7026 /* 4 preloaded VGPRs (outputs must be floats) */
7027 for (i = 0; i < 4; i++) {
7028 params[num_params++] = ctx.i32;
7029 returns[num_returns++] = ctx.f32;
7030 }
7031
7032 /* Vertex load indices. */
7033 for (i = 0; i <= key->vs_prolog.last_input; i++)
7034 returns[num_returns++] = ctx.f32;
7035
7036 /* Create the function. */
7037 si_create_function(&ctx, returns, num_returns, params,
7038 num_params, last_sgpr);
7039 func = ctx.radeon_bld.main_fn;
7040
7041 /* Copy inputs to outputs. This should be no-op, as the registers match,
7042 * but it will prevent the compiler from overwriting them unintentionally.
7043 */
7044 ret = ctx.return_value;
7045 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7046 LLVMValueRef p = LLVMGetParam(func, i);
7047 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7048 }
7049 for (i = num_params - 4; i < num_params; i++) {
7050 LLVMValueRef p = LLVMGetParam(func, i);
7051 p = LLVMBuildBitCast(gallivm->builder, p, ctx.f32, "");
7052 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7053 }
7054
7055 /* Compute vertex load indices from instance divisors. */
7056 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7057 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
7058 LLVMValueRef index;
7059
7060 if (divisor) {
7061 /* InstanceID / Divisor + StartInstance */
7062 index = get_instance_index_for_fetch(&ctx.radeon_bld,
7063 SI_SGPR_START_INSTANCE,
7064 divisor);
7065 } else {
7066 /* VertexID + BaseVertex */
7067 index = LLVMBuildAdd(gallivm->builder,
7068 LLVMGetParam(func, ctx.param_vertex_id),
7069 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
7070 }
7071
7072 index = LLVMBuildBitCast(gallivm->builder, index, ctx.f32, "");
7073 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
7074 num_params++, "");
7075 }
7076
7077 /* Compile. */
7078 si_llvm_build_ret(&ctx, ret);
7079 radeon_llvm_finalize_module(&ctx.radeon_bld);
7080
7081 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7082 gallivm->module, debug, ctx.type,
7083 "Vertex Shader Prolog"))
7084 status = false;
7085
7086 radeon_llvm_dispose(&ctx.radeon_bld);
7087 return status;
7088 }
7089
7090 /**
7091 * Compile the vertex shader epilog. This is also used by the tessellation
7092 * evaluation shader compiled as VS.
7093 *
7094 * The input is PrimitiveID.
7095 *
7096 * If PrimitiveID is required by the pixel shader, export it.
7097 * Otherwise, do nothing.
7098 */
7099 static bool si_compile_vs_epilog(struct si_screen *sscreen,
7100 LLVMTargetMachineRef tm,
7101 struct pipe_debug_callback *debug,
7102 struct si_shader_part *out)
7103 {
7104 union si_shader_part_key *key = &out->key;
7105 struct si_shader_context ctx;
7106 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7107 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
7108 LLVMTypeRef params[5];
7109 int num_params, i;
7110 bool status = true;
7111
7112 si_init_shader_ctx(&ctx, sscreen, NULL, tm);
7113 ctx.type = PIPE_SHADER_VERTEX;
7114
7115 /* Declare input VGPRs. */
7116 num_params = key->vs_epilog.states.export_prim_id ?
7117 (VS_EPILOG_PRIMID_LOC + 1) : 0;
7118 assert(num_params <= ARRAY_SIZE(params));
7119
7120 for (i = 0; i < num_params; i++)
7121 params[i] = ctx.f32;
7122
7123 /* Create the function. */
7124 si_create_function(&ctx, NULL, 0, params, num_params, -1);
7125
7126 /* Emit exports. */
7127 if (key->vs_epilog.states.export_prim_id) {
7128 struct lp_build_context *base = &bld_base->base;
7129 struct lp_build_context *uint = &bld_base->uint_bld;
7130 LLVMValueRef args[9];
7131
7132 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
7133 args[1] = uint->zero; /* whether the EXEC mask is valid */
7134 args[2] = uint->zero; /* DONE bit */
7135 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
7136 key->vs_epilog.prim_id_param_offset);
7137 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
7138 args[5] = LLVMGetParam(ctx.radeon_bld.main_fn,
7139 VS_EPILOG_PRIMID_LOC); /* X */
7140 args[6] = uint->undef; /* Y */
7141 args[7] = uint->undef; /* Z */
7142 args[8] = uint->undef; /* W */
7143
7144 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
7145 LLVMVoidTypeInContext(base->gallivm->context),
7146 args, 9, 0);
7147 }
7148
7149 /* Compile. */
7150 LLVMBuildRetVoid(gallivm->builder);
7151 radeon_llvm_finalize_module(&ctx.radeon_bld);
7152
7153 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7154 gallivm->module, debug, ctx.type,
7155 "Vertex Shader Epilog"))
7156 status = false;
7157
7158 radeon_llvm_dispose(&ctx.radeon_bld);
7159 return status;
7160 }
7161
7162 /**
7163 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7164 */
7165 static bool si_get_vs_epilog(struct si_screen *sscreen,
7166 LLVMTargetMachineRef tm,
7167 struct si_shader *shader,
7168 struct pipe_debug_callback *debug,
7169 struct si_vs_epilog_bits *states)
7170 {
7171 union si_shader_part_key epilog_key;
7172
7173 memset(&epilog_key, 0, sizeof(epilog_key));
7174 epilog_key.vs_epilog.states = *states;
7175
7176 /* Set up the PrimitiveID output. */
7177 if (shader->key.vs.epilog.export_prim_id) {
7178 unsigned index = shader->selector->info.num_outputs;
7179 unsigned offset = shader->info.nr_param_exports++;
7180
7181 epilog_key.vs_epilog.prim_id_param_offset = offset;
7182 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
7183 shader->info.vs_output_param_offset[index] = offset;
7184 }
7185
7186 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
7187 &epilog_key, tm, debug,
7188 si_compile_vs_epilog);
7189 return shader->epilog != NULL;
7190 }
7191
7192 /**
7193 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7194 */
7195 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7196 LLVMTargetMachineRef tm,
7197 struct si_shader *shader,
7198 struct pipe_debug_callback *debug)
7199 {
7200 struct tgsi_shader_info *info = &shader->selector->info;
7201 union si_shader_part_key prolog_key;
7202 unsigned i;
7203
7204 /* Get the prolog. */
7205 memset(&prolog_key, 0, sizeof(prolog_key));
7206 prolog_key.vs_prolog.states = shader->key.vs.prolog;
7207 prolog_key.vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7208 prolog_key.vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
7209
7210 /* The prolog is a no-op if there are no inputs. */
7211 if (info->num_inputs) {
7212 shader->prolog =
7213 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7214 &prolog_key, tm, debug,
7215 si_compile_vs_prolog);
7216 if (!shader->prolog)
7217 return false;
7218 }
7219
7220 /* Get the epilog. */
7221 if (!shader->key.vs.as_es && !shader->key.vs.as_ls &&
7222 !si_get_vs_epilog(sscreen, tm, shader, debug,
7223 &shader->key.vs.epilog))
7224 return false;
7225
7226 /* Set the instanceID flag. */
7227 for (i = 0; i < info->num_inputs; i++)
7228 if (prolog_key.vs_prolog.states.instance_divisors[i])
7229 shader->info.uses_instanceid = true;
7230
7231 return true;
7232 }
7233
7234 /**
7235 * Select and compile (or reuse) TES parts (epilog).
7236 */
7237 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
7238 LLVMTargetMachineRef tm,
7239 struct si_shader *shader,
7240 struct pipe_debug_callback *debug)
7241 {
7242 if (shader->key.tes.as_es)
7243 return true;
7244
7245 /* TES compiled as VS. */
7246 return si_get_vs_epilog(sscreen, tm, shader, debug,
7247 &shader->key.tes.epilog);
7248 }
7249
7250 /**
7251 * Compile the TCS epilog. This writes tesselation factors to memory based on
7252 * the output primitive type of the tesselator (determined by TES).
7253 */
7254 static bool si_compile_tcs_epilog(struct si_screen *sscreen,
7255 LLVMTargetMachineRef tm,
7256 struct pipe_debug_callback *debug,
7257 struct si_shader_part *out)
7258 {
7259 union si_shader_part_key *key = &out->key;
7260 struct si_shader shader = {};
7261 struct si_shader_context ctx;
7262 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7263 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
7264 LLVMTypeRef params[16];
7265 LLVMValueRef func;
7266 int last_sgpr, num_params;
7267 bool status = true;
7268
7269 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7270 ctx.type = PIPE_SHADER_TESS_CTRL;
7271 shader.key.tcs.epilog = key->tcs_epilog.states;
7272
7273 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
7274 params[SI_PARAM_RW_BUFFERS] = const_array(ctx.v16i8, SI_NUM_RW_BUFFERS);
7275 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
7276 params[SI_PARAM_SAMPLERS] = ctx.i64;
7277 params[SI_PARAM_IMAGES] = ctx.i64;
7278 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
7279 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx.i32;
7280 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx.i32;
7281 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx.i32;
7282 params[SI_PARAM_TCS_IN_LAYOUT] = ctx.i32;
7283 params[ctx.param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx.i32;
7284 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx.i32;
7285 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
7286 num_params = last_sgpr + 1;
7287
7288 params[num_params++] = ctx.i32; /* patch index within the wave (REL_PATCH_ID) */
7289 params[num_params++] = ctx.i32; /* invocation ID within the patch */
7290 params[num_params++] = ctx.i32; /* LDS offset where tess factors should be loaded from */
7291
7292 /* Create the function. */
7293 si_create_function(&ctx, NULL, 0, params, num_params, last_sgpr);
7294 declare_tess_lds(&ctx);
7295 func = ctx.radeon_bld.main_fn;
7296
7297 si_write_tess_factors(bld_base,
7298 LLVMGetParam(func, last_sgpr + 1),
7299 LLVMGetParam(func, last_sgpr + 2),
7300 LLVMGetParam(func, last_sgpr + 3));
7301
7302 /* Compile. */
7303 LLVMBuildRetVoid(gallivm->builder);
7304 radeon_llvm_finalize_module(&ctx.radeon_bld);
7305
7306 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7307 gallivm->module, debug, ctx.type,
7308 "Tessellation Control Shader Epilog"))
7309 status = false;
7310
7311 radeon_llvm_dispose(&ctx.radeon_bld);
7312 return status;
7313 }
7314
7315 /**
7316 * Select and compile (or reuse) TCS parts (epilog).
7317 */
7318 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7319 LLVMTargetMachineRef tm,
7320 struct si_shader *shader,
7321 struct pipe_debug_callback *debug)
7322 {
7323 union si_shader_part_key epilog_key;
7324
7325 /* Get the epilog. */
7326 memset(&epilog_key, 0, sizeof(epilog_key));
7327 epilog_key.tcs_epilog.states = shader->key.tcs.epilog;
7328
7329 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7330 &epilog_key, tm, debug,
7331 si_compile_tcs_epilog);
7332 return shader->epilog != NULL;
7333 }
7334
7335 /**
7336 * Compile the pixel shader prolog. This handles:
7337 * - two-side color selection and interpolation
7338 * - overriding interpolation parameters for the API PS
7339 * - polygon stippling
7340 *
7341 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7342 * overriden by other states. (e.g. per-sample interpolation)
7343 * Interpolated colors are stored after the preloaded VGPRs.
7344 */
7345 static bool si_compile_ps_prolog(struct si_screen *sscreen,
7346 LLVMTargetMachineRef tm,
7347 struct pipe_debug_callback *debug,
7348 struct si_shader_part *out)
7349 {
7350 union si_shader_part_key *key = &out->key;
7351 struct si_shader shader = {};
7352 struct si_shader_context ctx;
7353 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7354 LLVMTypeRef *params;
7355 LLVMValueRef ret, func;
7356 int last_sgpr, num_params, num_returns, i, num_color_channels;
7357 bool status = true;
7358
7359 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7360 ctx.type = PIPE_SHADER_FRAGMENT;
7361 shader.key.ps.prolog = key->ps_prolog.states;
7362
7363 /* Number of inputs + 8 color elements. */
7364 params = alloca((key->ps_prolog.num_input_sgprs +
7365 key->ps_prolog.num_input_vgprs + 8) *
7366 sizeof(LLVMTypeRef));
7367
7368 /* Declare inputs. */
7369 num_params = 0;
7370 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7371 params[num_params++] = ctx.i32;
7372 last_sgpr = num_params - 1;
7373
7374 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7375 params[num_params++] = ctx.f32;
7376
7377 /* Declare outputs (same as inputs + add colors if needed) */
7378 num_returns = num_params;
7379 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7380 for (i = 0; i < num_color_channels; i++)
7381 params[num_returns++] = ctx.f32;
7382
7383 /* Create the function. */
7384 si_create_function(&ctx, params, num_returns, params,
7385 num_params, last_sgpr);
7386 func = ctx.radeon_bld.main_fn;
7387
7388 /* Copy inputs to outputs. This should be no-op, as the registers match,
7389 * but it will prevent the compiler from overwriting them unintentionally.
7390 */
7391 ret = ctx.return_value;
7392 for (i = 0; i < num_params; i++) {
7393 LLVMValueRef p = LLVMGetParam(func, i);
7394 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7395 }
7396
7397 /* Polygon stippling. */
7398 if (key->ps_prolog.states.poly_stipple) {
7399 /* POS_FIXED_PT is always last. */
7400 unsigned pos = key->ps_prolog.num_input_sgprs +
7401 key->ps_prolog.num_input_vgprs - 1;
7402 LLVMValueRef ptr[2], list;
7403
7404 /* Get the pointer to rw buffers. */
7405 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
7406 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
7407 list = lp_build_gather_values(gallivm, ptr, 2);
7408 list = LLVMBuildBitCast(gallivm->builder, list, ctx.i64, "");
7409 list = LLVMBuildIntToPtr(gallivm->builder, list,
7410 const_array(ctx.v16i8, SI_NUM_RW_BUFFERS), "");
7411
7412 si_llvm_emit_polygon_stipple(&ctx, list, pos);
7413 }
7414
7415 if (key->ps_prolog.states.bc_optimize_for_persp ||
7416 key->ps_prolog.states.bc_optimize_for_linear) {
7417 unsigned i, base = key->ps_prolog.num_input_sgprs;
7418 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7419
7420 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7421 * The hw doesn't compute CENTROID if the whole wave only
7422 * contains fully-covered quads.
7423 *
7424 * PRIM_MASK is after user SGPRs.
7425 */
7426 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7427 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
7428 LLVMConstInt(ctx.i32, 31, 0), "");
7429 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
7430 ctx.i1, "");
7431
7432 if (key->ps_prolog.states.bc_optimize_for_persp) {
7433 /* Read PERSP_CENTER. */
7434 for (i = 0; i < 2; i++)
7435 center[i] = LLVMGetParam(func, base + 2 + i);
7436 /* Read PERSP_CENTROID. */
7437 for (i = 0; i < 2; i++)
7438 centroid[i] = LLVMGetParam(func, base + 4 + i);
7439 /* Select PERSP_CENTROID. */
7440 for (i = 0; i < 2; i++) {
7441 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7442 center[i], centroid[i], "");
7443 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7444 tmp, base + 4 + i, "");
7445 }
7446 }
7447 if (key->ps_prolog.states.bc_optimize_for_linear) {
7448 /* Read LINEAR_CENTER. */
7449 for (i = 0; i < 2; i++)
7450 center[i] = LLVMGetParam(func, base + 8 + i);
7451 /* Read LINEAR_CENTROID. */
7452 for (i = 0; i < 2; i++)
7453 centroid[i] = LLVMGetParam(func, base + 10 + i);
7454 /* Select LINEAR_CENTROID. */
7455 for (i = 0; i < 2; i++) {
7456 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7457 center[i], centroid[i], "");
7458 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7459 tmp, base + 10 + i, "");
7460 }
7461 }
7462 }
7463
7464 /* Interpolate colors. */
7465 for (i = 0; i < 2; i++) {
7466 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7467 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7468 key->ps_prolog.face_vgpr_index;
7469 LLVMValueRef interp[2], color[4];
7470 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7471
7472 if (!writemask)
7473 continue;
7474
7475 /* If the interpolation qualifier is not CONSTANT (-1). */
7476 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7477 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7478 key->ps_prolog.color_interp_vgpr_index[i];
7479
7480 /* Get the (i,j) updated by bc_optimize handling. */
7481 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
7482 interp_vgpr, "");
7483 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
7484 interp_vgpr + 1, "");
7485 interp_ij = lp_build_gather_values(gallivm, interp, 2);
7486 interp_ij = LLVMBuildBitCast(gallivm->builder, interp_ij,
7487 ctx.v2i32, "");
7488 }
7489
7490 /* Use the absolute location of the input. */
7491 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7492
7493 if (key->ps_prolog.states.color_two_side) {
7494 face = LLVMGetParam(func, face_vgpr);
7495 face = LLVMBuildBitCast(gallivm->builder, face, ctx.i32, "");
7496 }
7497
7498 interp_fs_input(&ctx,
7499 key->ps_prolog.color_attr_index[i],
7500 TGSI_SEMANTIC_COLOR, i,
7501 key->ps_prolog.num_interp_inputs,
7502 key->ps_prolog.colors_read, interp_ij,
7503 prim_mask, face, color);
7504
7505 while (writemask) {
7506 unsigned chan = u_bit_scan(&writemask);
7507 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
7508 num_params++, "");
7509 }
7510 }
7511
7512 /* Force per-sample interpolation. */
7513 if (key->ps_prolog.states.force_persp_sample_interp) {
7514 unsigned i, base = key->ps_prolog.num_input_sgprs;
7515 LLVMValueRef persp_sample[2];
7516
7517 /* Read PERSP_SAMPLE. */
7518 for (i = 0; i < 2; i++)
7519 persp_sample[i] = LLVMGetParam(func, base + i);
7520 /* Overwrite PERSP_CENTER. */
7521 for (i = 0; i < 2; i++)
7522 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7523 persp_sample[i], base + 2 + i, "");
7524 /* Overwrite PERSP_CENTROID. */
7525 for (i = 0; i < 2; i++)
7526 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7527 persp_sample[i], base + 4 + i, "");
7528 }
7529 if (key->ps_prolog.states.force_linear_sample_interp) {
7530 unsigned i, base = key->ps_prolog.num_input_sgprs;
7531 LLVMValueRef linear_sample[2];
7532
7533 /* Read LINEAR_SAMPLE. */
7534 for (i = 0; i < 2; i++)
7535 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7536 /* Overwrite LINEAR_CENTER. */
7537 for (i = 0; i < 2; i++)
7538 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7539 linear_sample[i], base + 8 + i, "");
7540 /* Overwrite LINEAR_CENTROID. */
7541 for (i = 0; i < 2; i++)
7542 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7543 linear_sample[i], base + 10 + i, "");
7544 }
7545
7546 /* Force center interpolation. */
7547 if (key->ps_prolog.states.force_persp_center_interp) {
7548 unsigned i, base = key->ps_prolog.num_input_sgprs;
7549 LLVMValueRef persp_center[2];
7550
7551 /* Read PERSP_CENTER. */
7552 for (i = 0; i < 2; i++)
7553 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7554 /* Overwrite PERSP_SAMPLE. */
7555 for (i = 0; i < 2; i++)
7556 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7557 persp_center[i], base + i, "");
7558 /* Overwrite PERSP_CENTROID. */
7559 for (i = 0; i < 2; i++)
7560 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7561 persp_center[i], base + 4 + i, "");
7562 }
7563 if (key->ps_prolog.states.force_linear_center_interp) {
7564 unsigned i, base = key->ps_prolog.num_input_sgprs;
7565 LLVMValueRef linear_center[2];
7566
7567 /* Read LINEAR_CENTER. */
7568 for (i = 0; i < 2; i++)
7569 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7570 /* Overwrite LINEAR_SAMPLE. */
7571 for (i = 0; i < 2; i++)
7572 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7573 linear_center[i], base + 6 + i, "");
7574 /* Overwrite LINEAR_CENTROID. */
7575 for (i = 0; i < 2; i++)
7576 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7577 linear_center[i], base + 10 + i, "");
7578 }
7579
7580 /* Tell LLVM to insert WQM instruction sequence when needed. */
7581 if (key->ps_prolog.wqm) {
7582 LLVMAddTargetDependentFunctionAttr(func,
7583 "amdgpu-ps-wqm-outputs", "");
7584 }
7585
7586 /* Compile. */
7587 si_llvm_build_ret(&ctx, ret);
7588 radeon_llvm_finalize_module(&ctx.radeon_bld);
7589
7590 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7591 gallivm->module, debug, ctx.type,
7592 "Fragment Shader Prolog"))
7593 status = false;
7594
7595 radeon_llvm_dispose(&ctx.radeon_bld);
7596 return status;
7597 }
7598
7599 /**
7600 * Compile the pixel shader epilog. This handles everything that must be
7601 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7602 */
7603 static bool si_compile_ps_epilog(struct si_screen *sscreen,
7604 LLVMTargetMachineRef tm,
7605 struct pipe_debug_callback *debug,
7606 struct si_shader_part *out)
7607 {
7608 union si_shader_part_key *key = &out->key;
7609 struct si_shader shader = {};
7610 struct si_shader_context ctx;
7611 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7612 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
7613 LLVMTypeRef params[16+8*4+3];
7614 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7615 int last_sgpr, num_params, i;
7616 bool status = true;
7617 struct si_ps_exports exp = {};
7618
7619 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7620 ctx.type = PIPE_SHADER_FRAGMENT;
7621 shader.key.ps.epilog = key->ps_epilog.states;
7622
7623 /* Declare input SGPRs. */
7624 params[SI_PARAM_RW_BUFFERS] = ctx.i64;
7625 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
7626 params[SI_PARAM_SAMPLERS] = ctx.i64;
7627 params[SI_PARAM_IMAGES] = ctx.i64;
7628 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
7629 params[SI_PARAM_ALPHA_REF] = ctx.f32;
7630 last_sgpr = SI_PARAM_ALPHA_REF;
7631
7632 /* Declare input VGPRs. */
7633 num_params = (last_sgpr + 1) +
7634 util_bitcount(key->ps_epilog.colors_written) * 4 +
7635 key->ps_epilog.writes_z +
7636 key->ps_epilog.writes_stencil +
7637 key->ps_epilog.writes_samplemask;
7638
7639 num_params = MAX2(num_params,
7640 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7641
7642 assert(num_params <= ARRAY_SIZE(params));
7643
7644 for (i = last_sgpr + 1; i < num_params; i++)
7645 params[i] = ctx.f32;
7646
7647 /* Create the function. */
7648 si_create_function(&ctx, NULL, 0, params, num_params, last_sgpr);
7649 /* Disable elimination of unused inputs. */
7650 radeon_llvm_add_attribute(ctx.radeon_bld.main_fn,
7651 "InitialPSInputAddr", 0xffffff);
7652
7653 /* Process colors. */
7654 unsigned vgpr = last_sgpr + 1;
7655 unsigned colors_written = key->ps_epilog.colors_written;
7656 int last_color_export = -1;
7657
7658 /* Find the last color export. */
7659 if (!key->ps_epilog.writes_z &&
7660 !key->ps_epilog.writes_stencil &&
7661 !key->ps_epilog.writes_samplemask) {
7662 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7663
7664 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7665 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7666 /* Just set this if any of the colorbuffers are enabled. */
7667 if (spi_format &
7668 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7669 last_color_export = 0;
7670 } else {
7671 for (i = 0; i < 8; i++)
7672 if (colors_written & (1 << i) &&
7673 (spi_format >> (i * 4)) & 0xf)
7674 last_color_export = i;
7675 }
7676 }
7677
7678 while (colors_written) {
7679 LLVMValueRef color[4];
7680 int mrt = u_bit_scan(&colors_written);
7681
7682 for (i = 0; i < 4; i++)
7683 color[i] = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7684
7685 si_export_mrt_color(bld_base, color, mrt,
7686 num_params - 1,
7687 mrt == last_color_export, &exp);
7688 }
7689
7690 /* Process depth, stencil, samplemask. */
7691 if (key->ps_epilog.writes_z)
7692 depth = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7693 if (key->ps_epilog.writes_stencil)
7694 stencil = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7695 if (key->ps_epilog.writes_samplemask)
7696 samplemask = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7697
7698 if (depth || stencil || samplemask)
7699 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7700 else if (last_color_export == -1)
7701 si_export_null(bld_base);
7702
7703 if (exp.num)
7704 si_emit_ps_exports(&ctx, &exp);
7705
7706 /* Compile. */
7707 LLVMBuildRetVoid(gallivm->builder);
7708 radeon_llvm_finalize_module(&ctx.radeon_bld);
7709
7710 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7711 gallivm->module, debug, ctx.type,
7712 "Fragment Shader Epilog"))
7713 status = false;
7714
7715 radeon_llvm_dispose(&ctx.radeon_bld);
7716 return status;
7717 }
7718
7719 /**
7720 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7721 */
7722 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7723 LLVMTargetMachineRef tm,
7724 struct si_shader *shader,
7725 struct pipe_debug_callback *debug)
7726 {
7727 struct tgsi_shader_info *info = &shader->selector->info;
7728 union si_shader_part_key prolog_key;
7729 union si_shader_part_key epilog_key;
7730 unsigned i;
7731
7732 /* Get the prolog. */
7733 memset(&prolog_key, 0, sizeof(prolog_key));
7734 prolog_key.ps_prolog.states = shader->key.ps.prolog;
7735 prolog_key.ps_prolog.colors_read = info->colors_read;
7736 prolog_key.ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7737 prolog_key.ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
7738 prolog_key.ps_prolog.wqm = info->uses_derivatives &&
7739 (prolog_key.ps_prolog.colors_read ||
7740 prolog_key.ps_prolog.states.force_persp_sample_interp ||
7741 prolog_key.ps_prolog.states.force_linear_sample_interp ||
7742 prolog_key.ps_prolog.states.force_persp_center_interp ||
7743 prolog_key.ps_prolog.states.force_linear_center_interp ||
7744 prolog_key.ps_prolog.states.bc_optimize_for_persp ||
7745 prolog_key.ps_prolog.states.bc_optimize_for_linear);
7746
7747 if (info->colors_read) {
7748 unsigned *color = shader->selector->color_attr_index;
7749
7750 if (shader->key.ps.prolog.color_two_side) {
7751 /* BCOLORs are stored after the last input. */
7752 prolog_key.ps_prolog.num_interp_inputs = info->num_inputs;
7753 prolog_key.ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
7754 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
7755 }
7756
7757 for (i = 0; i < 2; i++) {
7758 unsigned interp = info->input_interpolate[color[i]];
7759 unsigned location = info->input_interpolate_loc[color[i]];
7760
7761 if (!(info->colors_read & (0xf << i*4)))
7762 continue;
7763
7764 prolog_key.ps_prolog.color_attr_index[i] = color[i];
7765
7766 if (shader->key.ps.prolog.flatshade_colors &&
7767 interp == TGSI_INTERPOLATE_COLOR)
7768 interp = TGSI_INTERPOLATE_CONSTANT;
7769
7770 switch (interp) {
7771 case TGSI_INTERPOLATE_CONSTANT:
7772 prolog_key.ps_prolog.color_interp_vgpr_index[i] = -1;
7773 break;
7774 case TGSI_INTERPOLATE_PERSPECTIVE:
7775 case TGSI_INTERPOLATE_COLOR:
7776 /* Force the interpolation location for colors here. */
7777 if (shader->key.ps.prolog.force_persp_sample_interp)
7778 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7779 if (shader->key.ps.prolog.force_persp_center_interp)
7780 location = TGSI_INTERPOLATE_LOC_CENTER;
7781
7782 switch (location) {
7783 case TGSI_INTERPOLATE_LOC_SAMPLE:
7784 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 0;
7785 shader->config.spi_ps_input_ena |=
7786 S_0286CC_PERSP_SAMPLE_ENA(1);
7787 break;
7788 case TGSI_INTERPOLATE_LOC_CENTER:
7789 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 2;
7790 shader->config.spi_ps_input_ena |=
7791 S_0286CC_PERSP_CENTER_ENA(1);
7792 break;
7793 case TGSI_INTERPOLATE_LOC_CENTROID:
7794 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 4;
7795 shader->config.spi_ps_input_ena |=
7796 S_0286CC_PERSP_CENTROID_ENA(1);
7797 break;
7798 default:
7799 assert(0);
7800 }
7801 break;
7802 case TGSI_INTERPOLATE_LINEAR:
7803 /* Force the interpolation location for colors here. */
7804 if (shader->key.ps.prolog.force_linear_sample_interp)
7805 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7806 if (shader->key.ps.prolog.force_linear_center_interp)
7807 location = TGSI_INTERPOLATE_LOC_CENTER;
7808
7809 switch (location) {
7810 case TGSI_INTERPOLATE_LOC_SAMPLE:
7811 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 6;
7812 shader->config.spi_ps_input_ena |=
7813 S_0286CC_LINEAR_SAMPLE_ENA(1);
7814 break;
7815 case TGSI_INTERPOLATE_LOC_CENTER:
7816 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 8;
7817 shader->config.spi_ps_input_ena |=
7818 S_0286CC_LINEAR_CENTER_ENA(1);
7819 break;
7820 case TGSI_INTERPOLATE_LOC_CENTROID:
7821 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 10;
7822 shader->config.spi_ps_input_ena |=
7823 S_0286CC_LINEAR_CENTROID_ENA(1);
7824 break;
7825 default:
7826 assert(0);
7827 }
7828 break;
7829 default:
7830 assert(0);
7831 }
7832 }
7833 }
7834
7835 /* The prolog is a no-op if these aren't set. */
7836 if (prolog_key.ps_prolog.colors_read ||
7837 prolog_key.ps_prolog.states.force_persp_sample_interp ||
7838 prolog_key.ps_prolog.states.force_linear_sample_interp ||
7839 prolog_key.ps_prolog.states.force_persp_center_interp ||
7840 prolog_key.ps_prolog.states.force_linear_center_interp ||
7841 prolog_key.ps_prolog.states.bc_optimize_for_persp ||
7842 prolog_key.ps_prolog.states.bc_optimize_for_linear ||
7843 prolog_key.ps_prolog.states.poly_stipple) {
7844 shader->prolog =
7845 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7846 &prolog_key, tm, debug,
7847 si_compile_ps_prolog);
7848 if (!shader->prolog)
7849 return false;
7850 }
7851
7852 /* Get the epilog. */
7853 memset(&epilog_key, 0, sizeof(epilog_key));
7854 epilog_key.ps_epilog.colors_written = info->colors_written;
7855 epilog_key.ps_epilog.writes_z = info->writes_z;
7856 epilog_key.ps_epilog.writes_stencil = info->writes_stencil;
7857 epilog_key.ps_epilog.writes_samplemask = info->writes_samplemask;
7858 epilog_key.ps_epilog.states = shader->key.ps.epilog;
7859
7860 shader->epilog =
7861 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7862 &epilog_key, tm, debug,
7863 si_compile_ps_epilog);
7864 if (!shader->epilog)
7865 return false;
7866
7867 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7868 if (shader->key.ps.prolog.poly_stipple) {
7869 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7870 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7871 }
7872
7873 /* Set up the enable bits for per-sample shading if needed. */
7874 if (shader->key.ps.prolog.force_persp_sample_interp &&
7875 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7876 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7877 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7878 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7879 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7880 }
7881 if (shader->key.ps.prolog.force_linear_sample_interp &&
7882 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7883 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7884 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7885 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7886 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7887 }
7888 if (shader->key.ps.prolog.force_persp_center_interp &&
7889 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7890 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7891 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7892 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7893 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7894 }
7895 if (shader->key.ps.prolog.force_linear_center_interp &&
7896 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7897 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7898 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7899 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7900 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7901 }
7902
7903 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7904 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7905 !(shader->config.spi_ps_input_ena & 0xf)) {
7906 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7907 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7908 }
7909
7910 /* At least one pair of interpolation weights must be enabled. */
7911 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7912 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7913 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7914 }
7915
7916 /* The sample mask input is always enabled, because the API shader always
7917 * passes it through to the epilog. Disable it here if it's unused.
7918 */
7919 if (!shader->key.ps.epilog.poly_line_smoothing &&
7920 !shader->selector->info.reads_samplemask)
7921 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7922
7923 return true;
7924 }
7925
7926 static void si_fix_num_sgprs(struct si_shader *shader)
7927 {
7928 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7929
7930 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7931 }
7932
7933 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7934 struct si_shader *shader,
7935 struct pipe_debug_callback *debug)
7936 {
7937 struct si_shader *mainp = shader->selector->main_shader_part;
7938 int r;
7939
7940 /* LS, ES, VS are compiled on demand if the main part hasn't been
7941 * compiled for that stage.
7942 */
7943 if (!mainp ||
7944 (shader->selector->type == PIPE_SHADER_VERTEX &&
7945 (shader->key.vs.as_es != mainp->key.vs.as_es ||
7946 shader->key.vs.as_ls != mainp->key.vs.as_ls)) ||
7947 (shader->selector->type == PIPE_SHADER_TESS_EVAL &&
7948 shader->key.tes.as_es != mainp->key.tes.as_es) ||
7949 (shader->selector->type == PIPE_SHADER_TESS_CTRL &&
7950 shader->key.tcs.epilog.inputs_to_copy) ||
7951 shader->selector->type == PIPE_SHADER_COMPUTE) {
7952 /* Monolithic shader (compiled as a whole, has many variants,
7953 * may take a long time to compile).
7954 */
7955 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7956 if (r)
7957 return r;
7958 } else {
7959 /* The shader consists of 2-3 parts:
7960 *
7961 * - the middle part is the user shader, it has 1 variant only
7962 * and it was compiled during the creation of the shader
7963 * selector
7964 * - the prolog part is inserted at the beginning
7965 * - the epilog part is inserted at the end
7966 *
7967 * The prolog and epilog have many (but simple) variants.
7968 */
7969
7970 /* Copy the compiled TGSI shader data over. */
7971 shader->is_binary_shared = true;
7972 shader->binary = mainp->binary;
7973 shader->config = mainp->config;
7974 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7975 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7976 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7977 memcpy(shader->info.vs_output_param_offset,
7978 mainp->info.vs_output_param_offset,
7979 sizeof(mainp->info.vs_output_param_offset));
7980 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7981 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7982 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7983
7984 /* Select prologs and/or epilogs. */
7985 switch (shader->selector->type) {
7986 case PIPE_SHADER_VERTEX:
7987 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7988 return -1;
7989 break;
7990 case PIPE_SHADER_TESS_CTRL:
7991 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7992 return -1;
7993 break;
7994 case PIPE_SHADER_TESS_EVAL:
7995 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
7996 return -1;
7997 break;
7998 case PIPE_SHADER_FRAGMENT:
7999 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8000 return -1;
8001
8002 /* Make sure we have at least as many VGPRs as there
8003 * are allocated inputs.
8004 */
8005 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8006 shader->info.num_input_vgprs);
8007 break;
8008 }
8009
8010 /* Update SGPR and VGPR counts. */
8011 if (shader->prolog) {
8012 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8013 shader->prolog->config.num_sgprs);
8014 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8015 shader->prolog->config.num_vgprs);
8016 }
8017 if (shader->epilog) {
8018 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8019 shader->epilog->config.num_sgprs);
8020 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8021 shader->epilog->config.num_vgprs);
8022 }
8023 }
8024
8025 si_fix_num_sgprs(shader);
8026 si_shader_dump(sscreen, shader, debug, shader->selector->info.processor,
8027 stderr);
8028
8029 /* Upload. */
8030 r = si_shader_binary_upload(sscreen, shader);
8031 if (r) {
8032 fprintf(stderr, "LLVM failed to upload shader\n");
8033 return r;
8034 }
8035
8036 return 0;
8037 }
8038
8039 void si_shader_destroy(struct si_shader *shader)
8040 {
8041 if (shader->gs_copy_shader) {
8042 si_shader_destroy(shader->gs_copy_shader);
8043 FREE(shader->gs_copy_shader);
8044 }
8045
8046 if (shader->scratch_bo)
8047 r600_resource_reference(&shader->scratch_bo, NULL);
8048
8049 r600_resource_reference(&shader->bo, NULL);
8050
8051 if (!shader->is_binary_shared)
8052 radeon_shader_binary_clean(&shader->binary);
8053
8054 free(shader->shader_log);
8055 }