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[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "util/u_memory.h"
26 #include "util/u_string.h"
27 #include "tgsi/tgsi_build.h"
28 #include "tgsi/tgsi_strings.h"
29 #include "tgsi/tgsi_util.h"
30 #include "tgsi/tgsi_dump.h"
31
32 #include "ac_exp_param.h"
33 #include "ac_shader_util.h"
34 #include "ac_llvm_util.h"
35 #include "si_shader_internal.h"
36 #include "si_pipe.h"
37 #include "sid.h"
38
39 #include "compiler/nir/nir.h"
40
41 static const char *scratch_rsrc_dword0_symbol =
42 "SCRATCH_RSRC_DWORD0";
43
44 static const char *scratch_rsrc_dword1_symbol =
45 "SCRATCH_RSRC_DWORD1";
46
47 struct si_shader_output_values
48 {
49 LLVMValueRef values[4];
50 unsigned semantic_name;
51 unsigned semantic_index;
52 ubyte vertex_stream[4];
53 };
54
55 static void si_init_shader_ctx(struct si_shader_context *ctx,
56 struct si_screen *sscreen,
57 struct ac_llvm_compiler *compiler);
58
59 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
60 struct lp_build_tgsi_context *bld_base,
61 struct lp_build_emit_data *emit_data);
62
63 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
64 FILE *f);
65
66 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
67 union si_shader_part_key *key);
68 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
69 union si_shader_part_key *key);
70 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
71 union si_shader_part_key *key);
72 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
73 union si_shader_part_key *key);
74 static void si_fix_resource_usage(struct si_screen *sscreen,
75 struct si_shader *shader);
76
77 /* Ideally pass the sample mask input to the PS epilog as v14, which
78 * is its usual location, so that the shader doesn't have to add v_mov.
79 */
80 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
81
82 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
83 LLVMTypeRef type)
84 {
85 if (type == ctx->ac.i64 || type == ctx->ac.f64)
86 return true;
87
88 return false;
89 }
90
91 static bool is_merged_shader(struct si_shader_context *ctx)
92 {
93 if (ctx->screen->info.chip_class <= GFX8)
94 return false;
95
96 return ctx->shader->key.as_ls ||
97 ctx->shader->key.as_es ||
98 ctx->type == PIPE_SHADER_TESS_CTRL ||
99 ctx->type == PIPE_SHADER_GEOMETRY;
100 }
101
102 void si_init_function_info(struct si_function_info *fninfo)
103 {
104 fninfo->num_params = 0;
105 fninfo->num_sgpr_params = 0;
106 }
107
108 unsigned add_arg_assign(struct si_function_info *fninfo,
109 enum si_arg_regfile regfile, LLVMTypeRef type,
110 LLVMValueRef *assign)
111 {
112 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
113
114 unsigned idx = fninfo->num_params++;
115 assert(idx < ARRAY_SIZE(fninfo->types));
116
117 if (regfile == ARG_SGPR)
118 fninfo->num_sgpr_params = fninfo->num_params;
119
120 fninfo->types[idx] = type;
121 fninfo->assign[idx] = assign;
122 return idx;
123 }
124
125 static unsigned add_arg(struct si_function_info *fninfo,
126 enum si_arg_regfile regfile, LLVMTypeRef type)
127 {
128 return add_arg_assign(fninfo, regfile, type, NULL);
129 }
130
131 static void add_arg_assign_checked(struct si_function_info *fninfo,
132 enum si_arg_regfile regfile, LLVMTypeRef type,
133 LLVMValueRef *assign, unsigned idx)
134 {
135 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
136 assert(actual == idx);
137 }
138
139 static void add_arg_checked(struct si_function_info *fninfo,
140 enum si_arg_regfile regfile, LLVMTypeRef type,
141 unsigned idx)
142 {
143 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
144 }
145
146 /**
147 * Returns a unique index for a per-patch semantic name and index. The index
148 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
149 * can be calculated.
150 */
151 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
152 {
153 switch (semantic_name) {
154 case TGSI_SEMANTIC_TESSOUTER:
155 return 0;
156 case TGSI_SEMANTIC_TESSINNER:
157 return 1;
158 case TGSI_SEMANTIC_PATCH:
159 assert(index < 30);
160 return 2 + index;
161
162 default:
163 assert(!"invalid semantic name");
164 return 0;
165 }
166 }
167
168 /**
169 * Returns a unique index for a semantic name and index. The index must be
170 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
171 * calculated.
172 */
173 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index,
174 unsigned is_varying)
175 {
176 switch (semantic_name) {
177 case TGSI_SEMANTIC_POSITION:
178 return 0;
179 case TGSI_SEMANTIC_GENERIC:
180 /* Since some shader stages use the the highest used IO index
181 * to determine the size to allocate for inputs/outputs
182 * (in LDS, tess and GS rings). GENERIC should be placed right
183 * after POSITION to make that size as small as possible.
184 */
185 if (index < SI_MAX_IO_GENERIC)
186 return 1 + index;
187
188 assert(!"invalid generic index");
189 return 0;
190 case TGSI_SEMANTIC_PSIZE:
191 return SI_MAX_IO_GENERIC + 1;
192 case TGSI_SEMANTIC_CLIPDIST:
193 assert(index <= 1);
194 return SI_MAX_IO_GENERIC + 2 + index;
195 case TGSI_SEMANTIC_FOG:
196 return SI_MAX_IO_GENERIC + 4;
197 case TGSI_SEMANTIC_LAYER:
198 return SI_MAX_IO_GENERIC + 5;
199 case TGSI_SEMANTIC_VIEWPORT_INDEX:
200 return SI_MAX_IO_GENERIC + 6;
201 case TGSI_SEMANTIC_PRIMID:
202 return SI_MAX_IO_GENERIC + 7;
203 case TGSI_SEMANTIC_COLOR:
204 assert(index < 2);
205 return SI_MAX_IO_GENERIC + 8 + index;
206 case TGSI_SEMANTIC_BCOLOR:
207 assert(index < 2);
208 /* If it's a varying, COLOR and BCOLOR alias. */
209 if (is_varying)
210 return SI_MAX_IO_GENERIC + 8 + index;
211 else
212 return SI_MAX_IO_GENERIC + 10 + index;
213 case TGSI_SEMANTIC_TEXCOORD:
214 assert(index < 8);
215 STATIC_ASSERT(SI_MAX_IO_GENERIC + 12 + 8 <= 63);
216 return SI_MAX_IO_GENERIC + 12 + index;
217 case TGSI_SEMANTIC_CLIPVERTEX:
218 return 63;
219 default:
220 fprintf(stderr, "invalid semantic name = %u\n", semantic_name);
221 assert(!"invalid semantic name");
222 return 0;
223 }
224 }
225
226 /**
227 * Get the value of a shader input parameter and extract a bitfield.
228 */
229 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
230 LLVMValueRef value, unsigned rshift,
231 unsigned bitwidth)
232 {
233 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
234 value = ac_to_integer(&ctx->ac, value);
235
236 if (rshift)
237 value = LLVMBuildLShr(ctx->ac.builder, value,
238 LLVMConstInt(ctx->i32, rshift, 0), "");
239
240 if (rshift + bitwidth < 32) {
241 unsigned mask = (1 << bitwidth) - 1;
242 value = LLVMBuildAnd(ctx->ac.builder, value,
243 LLVMConstInt(ctx->i32, mask, 0), "");
244 }
245
246 return value;
247 }
248
249 LLVMValueRef si_unpack_param(struct si_shader_context *ctx,
250 unsigned param, unsigned rshift,
251 unsigned bitwidth)
252 {
253 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
254
255 return unpack_llvm_param(ctx, value, rshift, bitwidth);
256 }
257
258 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
259 {
260 switch (ctx->type) {
261 case PIPE_SHADER_TESS_CTRL:
262 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
263
264 case PIPE_SHADER_TESS_EVAL:
265 return LLVMGetParam(ctx->main_fn,
266 ctx->param_tes_rel_patch_id);
267
268 default:
269 assert(0);
270 return NULL;
271 }
272 }
273
274 /* Tessellation shaders pass outputs to the next shader using LDS.
275 *
276 * LS outputs = TCS inputs
277 * TCS outputs = TES inputs
278 *
279 * The LDS layout is:
280 * - TCS inputs for patch 0
281 * - TCS inputs for patch 1
282 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
283 * - ...
284 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
285 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
286 * - TCS outputs for patch 1
287 * - Per-patch TCS outputs for patch 1
288 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
289 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
290 * - ...
291 *
292 * All three shaders VS(LS), TCS, TES share the same LDS space.
293 */
294
295 static LLVMValueRef
296 get_tcs_in_patch_stride(struct si_shader_context *ctx)
297 {
298 return si_unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
299 }
300
301 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
302 {
303 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
304
305 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
306 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
307
308 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
309 }
310
311 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
312 {
313 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
314
315 return LLVMConstInt(ctx->i32, stride, 0);
316 }
317
318 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
319 {
320 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
321 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
322
323 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
324 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
325 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
326 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
327 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
328 num_patch_outputs * 4;
329 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
330 }
331
332 static LLVMValueRef
333 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
334 {
335 return LLVMBuildMul(ctx->ac.builder,
336 si_unpack_param(ctx,
337 ctx->param_tcs_out_lds_offsets,
338 0, 16),
339 LLVMConstInt(ctx->i32, 4, 0), "");
340 }
341
342 static LLVMValueRef
343 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
344 {
345 return LLVMBuildMul(ctx->ac.builder,
346 si_unpack_param(ctx,
347 ctx->param_tcs_out_lds_offsets,
348 16, 16),
349 LLVMConstInt(ctx->i32, 4, 0), "");
350 }
351
352 static LLVMValueRef
353 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
354 {
355 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
356 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
357
358 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
359 }
360
361 static LLVMValueRef
362 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
363 {
364 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
365 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
366 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
367
368 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_offset);
369 }
370
371 static LLVMValueRef
372 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
373 {
374 LLVMValueRef patch0_patch_data_offset =
375 get_tcs_out_patch0_patch_data_offset(ctx);
376 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
377 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
378
379 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_patch_data_offset);
380 }
381
382 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
383 {
384 unsigned tcs_out_vertices =
385 ctx->shader->selector ?
386 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
387
388 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
389 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
390 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
391
392 return si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
393 }
394
395 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
396 {
397 unsigned stride;
398
399 switch (ctx->type) {
400 case PIPE_SHADER_VERTEX:
401 stride = ctx->shader->selector->lshs_vertex_stride / 4;
402 return LLVMConstInt(ctx->i32, stride, 0);
403
404 case PIPE_SHADER_TESS_CTRL:
405 if (ctx->screen->info.chip_class >= GFX9 &&
406 ctx->shader->is_monolithic) {
407 stride = ctx->shader->key.part.tcs.ls->lshs_vertex_stride / 4;
408 return LLVMConstInt(ctx->i32, stride, 0);
409 }
410 return si_unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
411
412 default:
413 assert(0);
414 return NULL;
415 }
416 }
417
418 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
419 LLVMValueRef i32, unsigned index)
420 {
421 assert(index <= 1);
422
423 if (index == 1)
424 return LLVMBuildAShr(ctx->ac.builder, i32,
425 LLVMConstInt(ctx->i32, 16, 0), "");
426
427 return LLVMBuildSExt(ctx->ac.builder,
428 LLVMBuildTrunc(ctx->ac.builder, i32,
429 ctx->ac.i16, ""),
430 ctx->i32, "");
431 }
432
433 void si_llvm_load_input_vs(
434 struct si_shader_context *ctx,
435 unsigned input_index,
436 LLVMValueRef out[4])
437 {
438 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
439 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
440
441 if (vs_blit_property) {
442 LLVMValueRef vertex_id = ctx->abi.vertex_id;
443 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
444 LLVMIntULE, vertex_id,
445 ctx->i32_1, "");
446 /* Use LLVMIntNE, because we have 3 vertices and only
447 * the middle one should use y2.
448 */
449 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
450 LLVMIntNE, vertex_id,
451 ctx->i32_1, "");
452
453 if (input_index == 0) {
454 /* Position: */
455 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
456 ctx->param_vs_blit_inputs);
457 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
458 ctx->param_vs_blit_inputs + 1);
459
460 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
461 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
462 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
463 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
464
465 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
466 x1, x2, "");
467 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
468 y1, y2, "");
469
470 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
471 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
472 out[2] = LLVMGetParam(ctx->main_fn,
473 ctx->param_vs_blit_inputs + 2);
474 out[3] = ctx->ac.f32_1;
475 return;
476 }
477
478 /* Color or texture coordinates: */
479 assert(input_index == 1);
480
481 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
482 for (int i = 0; i < 4; i++) {
483 out[i] = LLVMGetParam(ctx->main_fn,
484 ctx->param_vs_blit_inputs + 3 + i);
485 }
486 } else {
487 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
488 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
489 ctx->param_vs_blit_inputs + 3);
490 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
491 ctx->param_vs_blit_inputs + 4);
492 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
493 ctx->param_vs_blit_inputs + 5);
494 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
495 ctx->param_vs_blit_inputs + 6);
496
497 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
498 x1, x2, "");
499 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
500 y1, y2, "");
501 out[2] = LLVMGetParam(ctx->main_fn,
502 ctx->param_vs_blit_inputs + 7);
503 out[3] = LLVMGetParam(ctx->main_fn,
504 ctx->param_vs_blit_inputs + 8);
505 }
506 return;
507 }
508
509 union si_vs_fix_fetch fix_fetch;
510 LLVMValueRef t_list_ptr;
511 LLVMValueRef t_offset;
512 LLVMValueRef t_list;
513 LLVMValueRef vertex_index;
514 LLVMValueRef tmp;
515
516 /* Load the T list */
517 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
518
519 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
520
521 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
522
523 vertex_index = LLVMGetParam(ctx->main_fn,
524 ctx->param_vertex_index0 +
525 input_index);
526
527 /* Use the open-coded implementation for all loads of doubles and
528 * of dword-sized data that needs fixups. We need to insert conversion
529 * code anyway, and the amd/common code does it for us.
530 *
531 * Note: On LLVM <= 8, we can only open-code formats with
532 * channel size >= 4 bytes.
533 */
534 bool opencode = ctx->shader->key.mono.vs_fetch_opencode & (1 << input_index);
535 fix_fetch.bits = ctx->shader->key.mono.vs_fix_fetch[input_index].bits;
536 if (opencode ||
537 (fix_fetch.u.log_size == 3 && fix_fetch.u.format == AC_FETCH_FORMAT_FLOAT) ||
538 (fix_fetch.u.log_size == 2)) {
539 tmp = ac_build_opencoded_load_format(
540 &ctx->ac, fix_fetch.u.log_size, fix_fetch.u.num_channels_m1 + 1,
541 fix_fetch.u.format, fix_fetch.u.reverse, !opencode,
542 t_list, vertex_index, ctx->ac.i32_0, ctx->ac.i32_0,
543 false, false, true);
544 for (unsigned i = 0; i < 4; ++i)
545 out[i] = LLVMBuildExtractElement(ctx->ac.builder, tmp, LLVMConstInt(ctx->i32, i, false), "");
546 return;
547 }
548
549 /* Do multiple loads for special formats. */
550 unsigned required_channels = util_last_bit(info->input_usage_mask[input_index]);
551 LLVMValueRef fetches[4];
552 unsigned num_fetches;
553 unsigned fetch_stride;
554 unsigned channels_per_fetch;
555
556 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2) {
557 num_fetches = MIN2(required_channels, 3);
558 fetch_stride = 1 << fix_fetch.u.log_size;
559 channels_per_fetch = 1;
560 } else {
561 num_fetches = 1;
562 fetch_stride = 0;
563 channels_per_fetch = required_channels;
564 }
565
566 for (unsigned i = 0; i < num_fetches; ++i) {
567 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
568 fetches[i] = ac_build_buffer_load_format(&ctx->ac, t_list, vertex_index, voffset,
569 channels_per_fetch, false, true);
570 }
571
572 if (num_fetches == 1 && channels_per_fetch > 1) {
573 LLVMValueRef fetch = fetches[0];
574 for (unsigned i = 0; i < channels_per_fetch; ++i) {
575 tmp = LLVMConstInt(ctx->i32, i, false);
576 fetches[i] = LLVMBuildExtractElement(
577 ctx->ac.builder, fetch, tmp, "");
578 }
579 num_fetches = channels_per_fetch;
580 channels_per_fetch = 1;
581 }
582
583 for (unsigned i = num_fetches; i < 4; ++i)
584 fetches[i] = LLVMGetUndef(ctx->f32);
585
586 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2 &&
587 required_channels == 4) {
588 if (fix_fetch.u.format == AC_FETCH_FORMAT_UINT || fix_fetch.u.format == AC_FETCH_FORMAT_SINT)
589 fetches[3] = ctx->ac.i32_1;
590 else
591 fetches[3] = ctx->ac.f32_1;
592 } else if (fix_fetch.u.log_size == 3 &&
593 (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ||
594 fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED ||
595 fix_fetch.u.format == AC_FETCH_FORMAT_SINT) &&
596 required_channels == 4) {
597 /* For 2_10_10_10, the hardware returns an unsigned value;
598 * convert it to a signed one.
599 */
600 LLVMValueRef tmp = fetches[3];
601 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
602
603 /* First, recover the sign-extended signed integer value. */
604 if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED)
605 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
606 else
607 tmp = ac_to_integer(&ctx->ac, tmp);
608
609 /* For the integer-like cases, do a natural sign extension.
610 *
611 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
612 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
613 * exponent.
614 */
615 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
616 fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ?
617 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
618 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
619
620 /* Convert back to the right type. */
621 if (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM) {
622 LLVMValueRef clamp;
623 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
624 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
625 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
626 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
627 } else if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED) {
628 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
629 }
630
631 fetches[3] = tmp;
632 }
633
634 for (unsigned i = 0; i < 4; ++i)
635 out[i] = ac_to_float(&ctx->ac, fetches[i]);
636 }
637
638 static void declare_input_vs(
639 struct si_shader_context *ctx,
640 unsigned input_index,
641 const struct tgsi_full_declaration *decl,
642 LLVMValueRef out[4])
643 {
644 si_llvm_load_input_vs(ctx, input_index, out);
645 }
646
647 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
648 unsigned swizzle)
649 {
650 if (swizzle > 0)
651 return ctx->i32_0;
652
653 switch (ctx->type) {
654 case PIPE_SHADER_VERTEX:
655 return LLVMGetParam(ctx->main_fn,
656 ctx->param_vs_prim_id);
657 case PIPE_SHADER_TESS_CTRL:
658 return ctx->abi.tcs_patch_id;
659 case PIPE_SHADER_TESS_EVAL:
660 return ctx->abi.tes_patch_id;
661 case PIPE_SHADER_GEOMETRY:
662 return ctx->abi.gs_prim_id;
663 default:
664 assert(0);
665 return ctx->i32_0;
666 }
667 }
668
669 /**
670 * Return the value of tgsi_ind_register for indexing.
671 * This is the indirect index with the constant offset added to it.
672 */
673 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
674 const struct tgsi_ind_register *ind,
675 unsigned addr_mul,
676 int rel_index)
677 {
678 LLVMValueRef result;
679
680 if (ind->File == TGSI_FILE_ADDRESS) {
681 result = ctx->addrs[ind->Index][ind->Swizzle];
682 result = LLVMBuildLoad(ctx->ac.builder, result, "");
683 } else {
684 struct tgsi_full_src_register src = {};
685
686 src.Register.File = ind->File;
687 src.Register.Index = ind->Index;
688
689 /* Set the second index to 0 for constants. */
690 if (ind->File == TGSI_FILE_CONSTANT)
691 src.Register.Dimension = 1;
692
693 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
694 TGSI_TYPE_SIGNED,
695 ind->Swizzle);
696 result = ac_to_integer(&ctx->ac, result);
697 }
698
699 return ac_build_imad(&ctx->ac, result, LLVMConstInt(ctx->i32, addr_mul, 0),
700 LLVMConstInt(ctx->i32, rel_index, 0));
701 }
702
703 /**
704 * Like si_get_indirect_index, but restricts the return value to a (possibly
705 * undefined) value inside [0..num).
706 */
707 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
708 const struct tgsi_ind_register *ind,
709 int rel_index, unsigned num)
710 {
711 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
712
713 return si_llvm_bound_index(ctx, result, num);
714 }
715
716 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
717 LLVMValueRef vertex_dw_stride,
718 LLVMValueRef base_addr,
719 LLVMValueRef vertex_index,
720 LLVMValueRef param_index,
721 unsigned input_index,
722 ubyte *name,
723 ubyte *index,
724 bool is_patch)
725 {
726 if (vertex_dw_stride) {
727 base_addr = ac_build_imad(&ctx->ac, vertex_index,
728 vertex_dw_stride, base_addr);
729 }
730
731 if (param_index) {
732 base_addr = ac_build_imad(&ctx->ac, param_index,
733 LLVMConstInt(ctx->i32, 4, 0), base_addr);
734 }
735
736 int param = is_patch ?
737 si_shader_io_get_unique_index_patch(name[input_index],
738 index[input_index]) :
739 si_shader_io_get_unique_index(name[input_index],
740 index[input_index], false);
741
742 /* Add the base address of the element. */
743 return LLVMBuildAdd(ctx->ac.builder, base_addr,
744 LLVMConstInt(ctx->i32, param * 4, 0), "");
745 }
746
747 /**
748 * Calculate a dword address given an input or output register and a stride.
749 */
750 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
751 const struct tgsi_full_dst_register *dst,
752 const struct tgsi_full_src_register *src,
753 LLVMValueRef vertex_dw_stride,
754 LLVMValueRef base_addr)
755 {
756 struct tgsi_shader_info *info = &ctx->shader->selector->info;
757 ubyte *name, *index, *array_first;
758 int input_index;
759 struct tgsi_full_dst_register reg;
760 LLVMValueRef vertex_index = NULL;
761 LLVMValueRef ind_index = NULL;
762
763 /* Set the register description. The address computation is the same
764 * for sources and destinations. */
765 if (src) {
766 reg.Register.File = src->Register.File;
767 reg.Register.Index = src->Register.Index;
768 reg.Register.Indirect = src->Register.Indirect;
769 reg.Register.Dimension = src->Register.Dimension;
770 reg.Indirect = src->Indirect;
771 reg.Dimension = src->Dimension;
772 reg.DimIndirect = src->DimIndirect;
773 } else
774 reg = *dst;
775
776 /* If the register is 2-dimensional (e.g. an array of vertices
777 * in a primitive), calculate the base address of the vertex. */
778 if (reg.Register.Dimension) {
779 if (reg.Dimension.Indirect)
780 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
781 1, reg.Dimension.Index);
782 else
783 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
784 }
785
786 /* Get information about the register. */
787 if (reg.Register.File == TGSI_FILE_INPUT) {
788 name = info->input_semantic_name;
789 index = info->input_semantic_index;
790 array_first = info->input_array_first;
791 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
792 name = info->output_semantic_name;
793 index = info->output_semantic_index;
794 array_first = info->output_array_first;
795 } else {
796 assert(0);
797 return NULL;
798 }
799
800 if (reg.Register.Indirect) {
801 /* Add the relative address of the element. */
802 if (reg.Indirect.ArrayID)
803 input_index = array_first[reg.Indirect.ArrayID];
804 else
805 input_index = reg.Register.Index;
806
807 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
808 1, reg.Register.Index - input_index);
809 } else {
810 input_index = reg.Register.Index;
811 }
812
813 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
814 base_addr, vertex_index,
815 ind_index, input_index,
816 name, index,
817 !reg.Register.Dimension);
818 }
819
820 /* The offchip buffer layout for TCS->TES is
821 *
822 * - attribute 0 of patch 0 vertex 0
823 * - attribute 0 of patch 0 vertex 1
824 * - attribute 0 of patch 0 vertex 2
825 * ...
826 * - attribute 0 of patch 1 vertex 0
827 * - attribute 0 of patch 1 vertex 1
828 * ...
829 * - attribute 1 of patch 0 vertex 0
830 * - attribute 1 of patch 0 vertex 1
831 * ...
832 * - per patch attribute 0 of patch 0
833 * - per patch attribute 0 of patch 1
834 * ...
835 *
836 * Note that every attribute has 4 components.
837 */
838 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
839 LLVMValueRef rel_patch_id,
840 LLVMValueRef vertex_index,
841 LLVMValueRef param_index)
842 {
843 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
844 LLVMValueRef param_stride, constant16;
845
846 vertices_per_patch = get_num_tcs_out_vertices(ctx);
847 num_patches = si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
848 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
849 num_patches, "");
850
851 constant16 = LLVMConstInt(ctx->i32, 16, 0);
852 if (vertex_index) {
853 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
854 vertices_per_patch, vertex_index);
855 param_stride = total_vertices;
856 } else {
857 base_addr = rel_patch_id;
858 param_stride = num_patches;
859 }
860
861 base_addr = ac_build_imad(&ctx->ac, param_index, param_stride, base_addr);
862 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
863
864 if (!vertex_index) {
865 LLVMValueRef patch_data_offset =
866 si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
867
868 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
869 patch_data_offset, "");
870 }
871 return base_addr;
872 }
873
874 /* This is a generic helper that can be shared by the NIR and TGSI backends */
875 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
876 struct si_shader_context *ctx,
877 LLVMValueRef vertex_index,
878 LLVMValueRef param_index,
879 unsigned param_base,
880 ubyte *name,
881 ubyte *index,
882 bool is_patch)
883 {
884 unsigned param_index_base;
885
886 param_index_base = is_patch ?
887 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
888 si_shader_io_get_unique_index(name[param_base], index[param_base], false);
889
890 if (param_index) {
891 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
892 LLVMConstInt(ctx->i32, param_index_base, 0),
893 "");
894 } else {
895 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
896 }
897
898 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
899 vertex_index, param_index);
900 }
901
902 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
903 struct si_shader_context *ctx,
904 const struct tgsi_full_dst_register *dst,
905 const struct tgsi_full_src_register *src)
906 {
907 struct tgsi_shader_info *info = &ctx->shader->selector->info;
908 ubyte *name, *index, *array_first;
909 struct tgsi_full_src_register reg;
910 LLVMValueRef vertex_index = NULL;
911 LLVMValueRef param_index = NULL;
912 unsigned param_base;
913
914 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
915
916 if (reg.Register.Dimension) {
917
918 if (reg.Dimension.Indirect)
919 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
920 1, reg.Dimension.Index);
921 else
922 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
923 }
924
925 /* Get information about the register. */
926 if (reg.Register.File == TGSI_FILE_INPUT) {
927 name = info->input_semantic_name;
928 index = info->input_semantic_index;
929 array_first = info->input_array_first;
930 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
931 name = info->output_semantic_name;
932 index = info->output_semantic_index;
933 array_first = info->output_array_first;
934 } else {
935 assert(0);
936 return NULL;
937 }
938
939 if (reg.Register.Indirect) {
940 if (reg.Indirect.ArrayID)
941 param_base = array_first[reg.Indirect.ArrayID];
942 else
943 param_base = reg.Register.Index;
944
945 param_index = si_get_indirect_index(ctx, &reg.Indirect,
946 1, reg.Register.Index - param_base);
947
948 } else {
949 param_base = reg.Register.Index;
950 }
951
952 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
953 param_index, param_base,
954 name, index, !reg.Register.Dimension);
955 }
956
957 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
958 LLVMTypeRef type, unsigned swizzle,
959 LLVMValueRef buffer, LLVMValueRef offset,
960 LLVMValueRef base, bool can_speculate)
961 {
962 struct si_shader_context *ctx = si_shader_context(bld_base);
963 LLVMValueRef value, value2;
964 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
965
966 if (swizzle == ~0) {
967 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
968 0, 1, 0, can_speculate, false);
969
970 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
971 }
972
973 if (!llvm_type_is_64bit(ctx, type)) {
974 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
975 0, 1, 0, can_speculate, false);
976
977 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
978 return LLVMBuildExtractElement(ctx->ac.builder, value,
979 LLVMConstInt(ctx->i32, swizzle, 0), "");
980 }
981
982 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
983 swizzle * 4, 1, 0, can_speculate, false);
984
985 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
986 swizzle * 4 + 4, 1, 0, can_speculate, false);
987
988 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
989 }
990
991 /**
992 * Load from LDS.
993 *
994 * \param type output value type
995 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
996 * \param dw_addr address in dwords
997 */
998 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
999 LLVMTypeRef type, unsigned swizzle,
1000 LLVMValueRef dw_addr)
1001 {
1002 struct si_shader_context *ctx = si_shader_context(bld_base);
1003 LLVMValueRef value;
1004
1005 if (swizzle == ~0) {
1006 LLVMValueRef values[TGSI_NUM_CHANNELS];
1007
1008 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1009 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1010
1011 return ac_build_gather_values(&ctx->ac, values,
1012 TGSI_NUM_CHANNELS);
1013 }
1014
1015 /* Split 64-bit loads. */
1016 if (llvm_type_is_64bit(ctx, type)) {
1017 LLVMValueRef lo, hi;
1018
1019 lo = lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1020 hi = lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1021 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1022 }
1023
1024 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1025 LLVMConstInt(ctx->i32, swizzle, 0), "");
1026
1027 value = ac_lds_load(&ctx->ac, dw_addr);
1028
1029 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1030 }
1031
1032 /**
1033 * Store to LDS.
1034 *
1035 * \param swizzle offset (typically 0..3)
1036 * \param dw_addr address in dwords
1037 * \param value value to store
1038 */
1039 static void lds_store(struct si_shader_context *ctx,
1040 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1041 LLVMValueRef value)
1042 {
1043 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1044 LLVMConstInt(ctx->i32, dw_offset_imm, 0), "");
1045
1046 ac_lds_store(&ctx->ac, dw_addr, value);
1047 }
1048
1049 enum si_tess_ring {
1050 TCS_FACTOR_RING,
1051 TESS_OFFCHIP_RING_TCS,
1052 TESS_OFFCHIP_RING_TES,
1053 };
1054
1055 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
1056 enum si_tess_ring ring)
1057 {
1058 LLVMBuilderRef builder = ctx->ac.builder;
1059 unsigned param = ring == TESS_OFFCHIP_RING_TES ? ctx->param_tes_offchip_addr :
1060 ctx->param_tcs_out_lds_layout;
1061 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1062
1063 /* TCS only receives high 13 bits of the address. */
1064 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
1065 addr = LLVMBuildAnd(builder, addr,
1066 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
1067 }
1068
1069 if (ring == TCS_FACTOR_RING) {
1070 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
1071 addr = LLVMBuildAdd(builder, addr,
1072 LLVMConstInt(ctx->i32, tf_offset, 0), "");
1073 }
1074
1075 LLVMValueRef desc[4];
1076 desc[0] = addr;
1077 desc[1] = LLVMConstInt(ctx->i32,
1078 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1079 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
1080 desc[3] = LLVMConstInt(ctx->i32,
1081 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1082 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1083 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1084 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1085 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1086 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0);
1087
1088 return ac_build_gather_values(&ctx->ac, desc, 4);
1089 }
1090
1091 static LLVMValueRef fetch_input_tcs(
1092 struct lp_build_tgsi_context *bld_base,
1093 const struct tgsi_full_src_register *reg,
1094 enum tgsi_opcode_type type, unsigned swizzle_in)
1095 {
1096 struct si_shader_context *ctx = si_shader_context(bld_base);
1097 LLVMValueRef dw_addr, stride;
1098 unsigned swizzle = swizzle_in & 0xffff;
1099 stride = get_tcs_in_vertex_dw_stride(ctx);
1100 dw_addr = get_tcs_in_current_patch_offset(ctx);
1101 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1102
1103 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1104 }
1105
1106 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1107 LLVMTypeRef type,
1108 LLVMValueRef vertex_index,
1109 LLVMValueRef param_index,
1110 unsigned const_index,
1111 unsigned location,
1112 unsigned driver_location,
1113 unsigned component,
1114 unsigned num_components,
1115 bool is_patch,
1116 bool is_compact,
1117 bool load_input)
1118 {
1119 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1120 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1121 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1122 LLVMValueRef dw_addr, stride;
1123
1124 driver_location = driver_location / 4;
1125
1126 if (load_input) {
1127 stride = get_tcs_in_vertex_dw_stride(ctx);
1128 dw_addr = get_tcs_in_current_patch_offset(ctx);
1129 } else {
1130 if (is_patch) {
1131 stride = NULL;
1132 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1133 } else {
1134 stride = get_tcs_out_vertex_dw_stride(ctx);
1135 dw_addr = get_tcs_out_current_patch_offset(ctx);
1136 }
1137 }
1138
1139 if (param_index) {
1140 /* Add the constant index to the indirect index */
1141 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1142 LLVMConstInt(ctx->i32, const_index, 0), "");
1143 } else {
1144 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1145 }
1146
1147 ubyte *names;
1148 ubyte *indices;
1149 if (load_input) {
1150 names = info->input_semantic_name;
1151 indices = info->input_semantic_index;
1152 } else {
1153 names = info->output_semantic_name;
1154 indices = info->output_semantic_index;
1155 }
1156
1157 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1158 vertex_index, param_index,
1159 driver_location,
1160 names, indices,
1161 is_patch);
1162
1163 LLVMValueRef value[4];
1164 for (unsigned i = 0; i < num_components; i++) {
1165 unsigned offset = i;
1166 if (llvm_type_is_64bit(ctx, type))
1167 offset *= 2;
1168
1169 offset += component;
1170 value[i + component] = lds_load(bld_base, type, offset, dw_addr);
1171 }
1172
1173 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1174 }
1175
1176 static LLVMValueRef fetch_output_tcs(
1177 struct lp_build_tgsi_context *bld_base,
1178 const struct tgsi_full_src_register *reg,
1179 enum tgsi_opcode_type type, unsigned swizzle_in)
1180 {
1181 struct si_shader_context *ctx = si_shader_context(bld_base);
1182 LLVMValueRef dw_addr, stride;
1183 unsigned swizzle = (swizzle_in & 0xffff);
1184
1185 if (reg->Register.Dimension) {
1186 stride = get_tcs_out_vertex_dw_stride(ctx);
1187 dw_addr = get_tcs_out_current_patch_offset(ctx);
1188 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1189 } else {
1190 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1191 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1192 }
1193
1194 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1195 }
1196
1197 static LLVMValueRef fetch_input_tes(
1198 struct lp_build_tgsi_context *bld_base,
1199 const struct tgsi_full_src_register *reg,
1200 enum tgsi_opcode_type type, unsigned swizzle_in)
1201 {
1202 struct si_shader_context *ctx = si_shader_context(bld_base);
1203 LLVMValueRef base, addr;
1204 unsigned swizzle = (swizzle_in & 0xffff);
1205
1206 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1207 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1208
1209 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1210 ctx->tess_offchip_ring, base, addr, true);
1211 }
1212
1213 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1214 LLVMTypeRef type,
1215 LLVMValueRef vertex_index,
1216 LLVMValueRef param_index,
1217 unsigned const_index,
1218 unsigned location,
1219 unsigned driver_location,
1220 unsigned component,
1221 unsigned num_components,
1222 bool is_patch,
1223 bool is_compact,
1224 bool load_input)
1225 {
1226 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1227 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1228 LLVMValueRef base, addr;
1229
1230 driver_location = driver_location / 4;
1231
1232 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1233
1234 if (param_index) {
1235 /* Add the constant index to the indirect index */
1236 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1237 LLVMConstInt(ctx->i32, const_index, 0), "");
1238 } else {
1239 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1240 }
1241
1242 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1243 param_index, driver_location,
1244 info->input_semantic_name,
1245 info->input_semantic_index,
1246 is_patch);
1247
1248 /* TODO: This will generate rather ordinary llvm code, although it
1249 * should be easy for the optimiser to fix up. In future we might want
1250 * to refactor buffer_load(), but for now this maximises code sharing
1251 * between the NIR and TGSI backends.
1252 */
1253 LLVMValueRef value[4];
1254 for (unsigned i = 0; i < num_components; i++) {
1255 unsigned offset = i;
1256 if (llvm_type_is_64bit(ctx, type)) {
1257 offset *= 2;
1258 if (offset == 4) {
1259 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1260 vertex_index,
1261 param_index,
1262 driver_location + 1,
1263 info->input_semantic_name,
1264 info->input_semantic_index,
1265 is_patch);
1266 }
1267
1268 offset = offset % 4;
1269 }
1270
1271 offset += component;
1272 value[i + component] = buffer_load(&ctx->bld_base, type, offset,
1273 ctx->tess_offchip_ring, base, addr, true);
1274 }
1275
1276 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1277 }
1278
1279 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1280 const struct tgsi_full_instruction *inst,
1281 const struct tgsi_opcode_info *info,
1282 unsigned index,
1283 LLVMValueRef dst[4])
1284 {
1285 struct si_shader_context *ctx = si_shader_context(bld_base);
1286 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1287 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1288 unsigned chan_index;
1289 LLVMValueRef dw_addr, stride;
1290 LLVMValueRef buffer, base, buf_addr;
1291 LLVMValueRef values[4];
1292 bool skip_lds_store;
1293 bool is_tess_factor = false, is_tess_inner = false;
1294
1295 /* Only handle per-patch and per-vertex outputs here.
1296 * Vectors will be lowered to scalars and this function will be called again.
1297 */
1298 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1299 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1300 si_llvm_emit_store(bld_base, inst, info, index, dst);
1301 return;
1302 }
1303
1304 if (reg->Register.Dimension) {
1305 stride = get_tcs_out_vertex_dw_stride(ctx);
1306 dw_addr = get_tcs_out_current_patch_offset(ctx);
1307 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1308 skip_lds_store = !sh_info->reads_pervertex_outputs;
1309 } else {
1310 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1311 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1312 skip_lds_store = !sh_info->reads_perpatch_outputs;
1313
1314 if (!reg->Register.Indirect) {
1315 int name = sh_info->output_semantic_name[reg->Register.Index];
1316
1317 /* Always write tess factors into LDS for the TCS epilog. */
1318 if (name == TGSI_SEMANTIC_TESSINNER ||
1319 name == TGSI_SEMANTIC_TESSOUTER) {
1320 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1321 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1322 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1323 is_tess_factor = true;
1324 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1325 }
1326 }
1327 }
1328
1329 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1330
1331 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1332 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1333
1334 uint32_t writemask = reg->Register.WriteMask;
1335 while (writemask) {
1336 chan_index = u_bit_scan(&writemask);
1337 LLVMValueRef value = dst[chan_index];
1338
1339 if (inst->Instruction.Saturate)
1340 value = ac_build_clamp(&ctx->ac, value);
1341
1342 /* Skip LDS stores if there is no LDS read of this output. */
1343 if (!skip_lds_store)
1344 lds_store(ctx, chan_index, dw_addr, value);
1345
1346 value = ac_to_integer(&ctx->ac, value);
1347 values[chan_index] = value;
1348
1349 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1350 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1351 buf_addr, base,
1352 4 * chan_index, 1, 0, true, false);
1353 }
1354
1355 /* Write tess factors into VGPRs for the epilog. */
1356 if (is_tess_factor &&
1357 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1358 if (!is_tess_inner) {
1359 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1360 ctx->invoc0_tess_factors[chan_index]);
1361 } else if (chan_index < 2) {
1362 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1363 ctx->invoc0_tess_factors[4 + chan_index]);
1364 }
1365 }
1366 }
1367
1368 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1369 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1370 values, 4);
1371 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1372 base, 0, 1, 0, true, false);
1373 }
1374 }
1375
1376 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1377 const struct nir_variable *var,
1378 LLVMValueRef vertex_index,
1379 LLVMValueRef param_index,
1380 unsigned const_index,
1381 LLVMValueRef src,
1382 unsigned writemask)
1383 {
1384 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1385 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1386 const unsigned component = var->data.location_frac;
1387 const bool is_patch = var->data.patch;
1388 unsigned driver_location = var->data.driver_location;
1389 LLVMValueRef dw_addr, stride;
1390 LLVMValueRef buffer, base, addr;
1391 LLVMValueRef values[8];
1392 bool skip_lds_store;
1393 bool is_tess_factor = false, is_tess_inner = false;
1394
1395 driver_location = driver_location / 4;
1396
1397 if (param_index) {
1398 /* Add the constant index to the indirect index */
1399 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1400 LLVMConstInt(ctx->i32, const_index, 0), "");
1401 } else {
1402 if (const_index != 0)
1403 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1404 }
1405
1406 if (!is_patch) {
1407 stride = get_tcs_out_vertex_dw_stride(ctx);
1408 dw_addr = get_tcs_out_current_patch_offset(ctx);
1409 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1410 vertex_index, param_index,
1411 driver_location,
1412 info->output_semantic_name,
1413 info->output_semantic_index,
1414 is_patch);
1415
1416 skip_lds_store = !info->reads_pervertex_outputs;
1417 } else {
1418 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1419 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1420 vertex_index, param_index,
1421 driver_location,
1422 info->output_semantic_name,
1423 info->output_semantic_index,
1424 is_patch);
1425
1426 skip_lds_store = !info->reads_perpatch_outputs;
1427
1428 if (!param_index) {
1429 int name = info->output_semantic_name[driver_location];
1430
1431 /* Always write tess factors into LDS for the TCS epilog. */
1432 if (name == TGSI_SEMANTIC_TESSINNER ||
1433 name == TGSI_SEMANTIC_TESSOUTER) {
1434 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1435 skip_lds_store = !info->reads_tessfactor_outputs &&
1436 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1437 is_tess_factor = true;
1438 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1439 }
1440 }
1441 }
1442
1443 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1444
1445 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1446
1447 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1448 param_index, driver_location,
1449 info->output_semantic_name,
1450 info->output_semantic_index,
1451 is_patch);
1452
1453 for (unsigned chan = 0; chan < 8; chan++) {
1454 if (!(writemask & (1 << chan)))
1455 continue;
1456 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1457
1458 unsigned buffer_store_offset = chan % 4;
1459 if (chan == 4) {
1460 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1461 vertex_index,
1462 param_index,
1463 driver_location + 1,
1464 info->output_semantic_name,
1465 info->output_semantic_index,
1466 is_patch);
1467 }
1468
1469 /* Skip LDS stores if there is no LDS read of this output. */
1470 if (!skip_lds_store)
1471 lds_store(ctx, chan, dw_addr, value);
1472
1473 value = ac_to_integer(&ctx->ac, value);
1474 values[chan] = value;
1475
1476 if (writemask != 0xF && !is_tess_factor) {
1477 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1478 addr, base,
1479 4 * buffer_store_offset,
1480 1, 0, true, false);
1481 }
1482
1483 /* Write tess factors into VGPRs for the epilog. */
1484 if (is_tess_factor &&
1485 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1486 if (!is_tess_inner) {
1487 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1488 ctx->invoc0_tess_factors[chan]);
1489 } else if (chan < 2) {
1490 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1491 ctx->invoc0_tess_factors[4 + chan]);
1492 }
1493 }
1494 }
1495
1496 if (writemask == 0xF && !is_tess_factor) {
1497 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1498 values, 4);
1499 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1500 base, 0, 1, 0, true, false);
1501 }
1502 }
1503
1504 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1505 unsigned input_index,
1506 unsigned vtx_offset_param,
1507 LLVMTypeRef type,
1508 unsigned swizzle)
1509 {
1510 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1511 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1512 struct si_shader *shader = ctx->shader;
1513 LLVMValueRef vtx_offset, soffset;
1514 struct tgsi_shader_info *info = &shader->selector->info;
1515 unsigned semantic_name = info->input_semantic_name[input_index];
1516 unsigned semantic_index = info->input_semantic_index[input_index];
1517 unsigned param;
1518 LLVMValueRef value;
1519
1520 param = si_shader_io_get_unique_index(semantic_name, semantic_index, false);
1521
1522 /* GFX9 has the ESGS ring in LDS. */
1523 if (ctx->screen->info.chip_class >= GFX9) {
1524 unsigned index = vtx_offset_param;
1525
1526 switch (index / 2) {
1527 case 0:
1528 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx01_offset,
1529 index % 2 ? 16 : 0, 16);
1530 break;
1531 case 1:
1532 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx23_offset,
1533 index % 2 ? 16 : 0, 16);
1534 break;
1535 case 2:
1536 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx45_offset,
1537 index % 2 ? 16 : 0, 16);
1538 break;
1539 default:
1540 assert(0);
1541 return NULL;
1542 }
1543
1544 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1545 LLVMConstInt(ctx->i32, param * 4, 0), "");
1546 return lds_load(bld_base, type, swizzle, vtx_offset);
1547 }
1548
1549 /* GFX6: input load from the ESGS ring in memory. */
1550 if (swizzle == ~0) {
1551 LLVMValueRef values[TGSI_NUM_CHANNELS];
1552 unsigned chan;
1553 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1554 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1555 type, chan);
1556 }
1557 return ac_build_gather_values(&ctx->ac, values,
1558 TGSI_NUM_CHANNELS);
1559 }
1560
1561 /* Get the vertex offset parameter on GFX6. */
1562 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1563
1564 vtx_offset = LLVMBuildMul(ctx->ac.builder, gs_vtx_offset,
1565 LLVMConstInt(ctx->i32, 4, 0), "");
1566
1567 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1568
1569 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1570 vtx_offset, soffset, 0, 1, 0, true, false);
1571 if (llvm_type_is_64bit(ctx, type)) {
1572 LLVMValueRef value2;
1573 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1574
1575 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1576 ctx->i32_0, vtx_offset, soffset,
1577 0, 1, 0, true, false);
1578 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1579 }
1580 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1581 }
1582
1583 static LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
1584 unsigned location,
1585 unsigned driver_location,
1586 unsigned component,
1587 unsigned num_components,
1588 unsigned vertex_index,
1589 unsigned const_index,
1590 LLVMTypeRef type)
1591 {
1592 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1593
1594 LLVMValueRef value[4];
1595 for (unsigned i = 0; i < num_components; i++) {
1596 unsigned offset = i;
1597 if (llvm_type_is_64bit(ctx, type))
1598 offset *= 2;
1599
1600 offset += component;
1601 value[i + component] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4,
1602 vertex_index, type, offset);
1603 }
1604
1605 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1606 }
1607
1608 static LLVMValueRef fetch_input_gs(
1609 struct lp_build_tgsi_context *bld_base,
1610 const struct tgsi_full_src_register *reg,
1611 enum tgsi_opcode_type type,
1612 unsigned swizzle_in)
1613 {
1614 struct si_shader_context *ctx = si_shader_context(bld_base);
1615 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1616 unsigned swizzle = swizzle_in & 0xffff;
1617
1618 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1619 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1620 return get_primitive_id(ctx, swizzle);
1621
1622 if (!reg->Register.Dimension)
1623 return NULL;
1624
1625 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1626 reg->Dimension.Index,
1627 tgsi2llvmtype(bld_base, type),
1628 swizzle);
1629 }
1630
1631 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1632 {
1633 switch (interpolate) {
1634 case TGSI_INTERPOLATE_CONSTANT:
1635 return 0;
1636
1637 case TGSI_INTERPOLATE_LINEAR:
1638 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1639 return SI_PARAM_LINEAR_SAMPLE;
1640 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1641 return SI_PARAM_LINEAR_CENTROID;
1642 else
1643 return SI_PARAM_LINEAR_CENTER;
1644 break;
1645 case TGSI_INTERPOLATE_COLOR:
1646 case TGSI_INTERPOLATE_PERSPECTIVE:
1647 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1648 return SI_PARAM_PERSP_SAMPLE;
1649 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1650 return SI_PARAM_PERSP_CENTROID;
1651 else
1652 return SI_PARAM_PERSP_CENTER;
1653 break;
1654 default:
1655 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1656 return -1;
1657 }
1658 }
1659
1660 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1661 unsigned attr_index, unsigned chan,
1662 LLVMValueRef prim_mask,
1663 LLVMValueRef i, LLVMValueRef j)
1664 {
1665 if (i || j) {
1666 return ac_build_fs_interp(&ctx->ac,
1667 LLVMConstInt(ctx->i32, chan, 0),
1668 LLVMConstInt(ctx->i32, attr_index, 0),
1669 prim_mask, i, j);
1670 }
1671 return ac_build_fs_interp_mov(&ctx->ac,
1672 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1673 LLVMConstInt(ctx->i32, chan, 0),
1674 LLVMConstInt(ctx->i32, attr_index, 0),
1675 prim_mask);
1676 }
1677
1678 /**
1679 * Interpolate a fragment shader input.
1680 *
1681 * @param ctx context
1682 * @param input_index index of the input in hardware
1683 * @param semantic_name TGSI_SEMANTIC_*
1684 * @param semantic_index semantic index
1685 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1686 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1687 * @param interp_param interpolation weights (i,j)
1688 * @param prim_mask SI_PARAM_PRIM_MASK
1689 * @param face SI_PARAM_FRONT_FACE
1690 * @param result the return value (4 components)
1691 */
1692 static void interp_fs_input(struct si_shader_context *ctx,
1693 unsigned input_index,
1694 unsigned semantic_name,
1695 unsigned semantic_index,
1696 unsigned num_interp_inputs,
1697 unsigned colors_read_mask,
1698 LLVMValueRef interp_param,
1699 LLVMValueRef prim_mask,
1700 LLVMValueRef face,
1701 LLVMValueRef result[4])
1702 {
1703 LLVMValueRef i = NULL, j = NULL;
1704 unsigned chan;
1705
1706 /* fs.constant returns the param from the middle vertex, so it's not
1707 * really useful for flat shading. It's meant to be used for custom
1708 * interpolation (but the intrinsic can't fetch from the other two
1709 * vertices).
1710 *
1711 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1712 * to do the right thing. The only reason we use fs.constant is that
1713 * fs.interp cannot be used on integers, because they can be equal
1714 * to NaN.
1715 *
1716 * When interp is false we will use fs.constant or for newer llvm,
1717 * amdgcn.interp.mov.
1718 */
1719 bool interp = interp_param != NULL;
1720
1721 if (interp) {
1722 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1723 LLVMVectorType(ctx->f32, 2), "");
1724
1725 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1726 ctx->i32_0, "");
1727 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1728 ctx->i32_1, "");
1729 }
1730
1731 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1732 ctx->shader->key.part.ps.prolog.color_two_side) {
1733 LLVMValueRef is_face_positive;
1734
1735 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1736 * otherwise it's at offset "num_inputs".
1737 */
1738 unsigned back_attr_offset = num_interp_inputs;
1739 if (semantic_index == 1 && colors_read_mask & 0xf)
1740 back_attr_offset += 1;
1741
1742 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1743 face, ctx->i32_0, "");
1744
1745 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1746 LLVMValueRef front, back;
1747
1748 front = si_build_fs_interp(ctx,
1749 input_index, chan,
1750 prim_mask, i, j);
1751 back = si_build_fs_interp(ctx,
1752 back_attr_offset, chan,
1753 prim_mask, i, j);
1754
1755 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1756 is_face_positive,
1757 front,
1758 back,
1759 "");
1760 }
1761 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1762 result[0] = si_build_fs_interp(ctx, input_index,
1763 0, prim_mask, i, j);
1764 result[1] =
1765 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1766 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1767 } else {
1768 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1769 result[chan] = si_build_fs_interp(ctx,
1770 input_index, chan,
1771 prim_mask, i, j);
1772 }
1773 }
1774 }
1775
1776 void si_llvm_load_input_fs(
1777 struct si_shader_context *ctx,
1778 unsigned input_index,
1779 LLVMValueRef out[4])
1780 {
1781 struct si_shader *shader = ctx->shader;
1782 struct tgsi_shader_info *info = &shader->selector->info;
1783 LLVMValueRef main_fn = ctx->main_fn;
1784 LLVMValueRef interp_param = NULL;
1785 int interp_param_idx;
1786 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1787 unsigned semantic_index = info->input_semantic_index[input_index];
1788 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1789 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1790
1791 /* Get colors from input VGPRs (set by the prolog). */
1792 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1793 unsigned colors_read = shader->selector->info.colors_read;
1794 unsigned mask = colors_read >> (semantic_index * 4);
1795 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1796 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1797 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1798
1799 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1800 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1801 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1802 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1803 return;
1804 }
1805
1806 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1807 if (interp_param_idx == -1)
1808 return;
1809 else if (interp_param_idx) {
1810 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1811 }
1812
1813 interp_fs_input(ctx, input_index, semantic_name,
1814 semantic_index, 0, /* this param is unused */
1815 shader->selector->info.colors_read, interp_param,
1816 ctx->abi.prim_mask,
1817 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1818 &out[0]);
1819 }
1820
1821 static void declare_input_fs(
1822 struct si_shader_context *ctx,
1823 unsigned input_index,
1824 const struct tgsi_full_declaration *decl,
1825 LLVMValueRef out[4])
1826 {
1827 si_llvm_load_input_fs(ctx, input_index, out);
1828 }
1829
1830 LLVMValueRef si_get_sample_id(struct si_shader_context *ctx)
1831 {
1832 return si_unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1833 }
1834
1835 static LLVMValueRef get_base_vertex(struct ac_shader_abi *abi)
1836 {
1837 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1838
1839 /* For non-indexed draws, the base vertex set by the driver
1840 * (for direct draws) or the CP (for indirect draws) is the
1841 * first vertex ID, but GLSL expects 0 to be returned.
1842 */
1843 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn,
1844 ctx->param_vs_state_bits);
1845 LLVMValueRef indexed;
1846
1847 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1848 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1849
1850 return LLVMBuildSelect(ctx->ac.builder, indexed, ctx->abi.base_vertex,
1851 ctx->i32_0, "");
1852 }
1853
1854 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1855 {
1856 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1857
1858 LLVMValueRef values[3];
1859 LLVMValueRef result;
1860 unsigned i;
1861 unsigned *properties = ctx->shader->selector->info.properties;
1862
1863 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1864 unsigned sizes[3] = {
1865 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1866 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1867 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1868 };
1869
1870 for (i = 0; i < 3; ++i)
1871 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1872
1873 result = ac_build_gather_values(&ctx->ac, values, 3);
1874 } else {
1875 result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1876 }
1877
1878 return result;
1879 }
1880
1881 /**
1882 * Load a dword from a constant buffer.
1883 */
1884 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1885 LLVMValueRef resource,
1886 LLVMValueRef offset)
1887 {
1888 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1889 0, 0, 0, true, true);
1890 }
1891
1892 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1893 {
1894 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1895 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1896 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1897 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1898
1899 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1900 LLVMValueRef offset0 = LLVMBuildMul(ctx->ac.builder, sample_id, LLVMConstInt(ctx->i32, 8, 0), "");
1901 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1902
1903 LLVMValueRef pos[4] = {
1904 buffer_load_const(ctx, resource, offset0),
1905 buffer_load_const(ctx, resource, offset1),
1906 LLVMConstReal(ctx->f32, 0),
1907 LLVMConstReal(ctx->f32, 0)
1908 };
1909
1910 return ac_build_gather_values(&ctx->ac, pos, 4);
1911 }
1912
1913 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1914 {
1915 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1916 return ac_to_integer(&ctx->ac, abi->sample_coverage);
1917 }
1918
1919 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
1920 {
1921 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1922 LLVMValueRef coord[4] = {
1923 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1924 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1925 ctx->ac.f32_0,
1926 ctx->ac.f32_0
1927 };
1928
1929 /* For triangles, the vector should be (u, v, 1-u-v). */
1930 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1931 PIPE_PRIM_TRIANGLES) {
1932 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1933 LLVMBuildFAdd(ctx->ac.builder,
1934 coord[0], coord[1], ""), "");
1935 }
1936 return ac_build_gather_values(&ctx->ac, coord, 4);
1937 }
1938
1939 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
1940 unsigned semantic_name)
1941 {
1942 LLVMValueRef base, addr;
1943
1944 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
1945
1946 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1947 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1948 LLVMConstInt(ctx->i32, param, 0));
1949
1950 return buffer_load(&ctx->bld_base, ctx->f32,
1951 ~0, ctx->tess_offchip_ring, base, addr, true);
1952
1953 }
1954
1955 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
1956 unsigned varying_id)
1957 {
1958 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1959 unsigned semantic_name;
1960
1961 switch (varying_id) {
1962 case VARYING_SLOT_TESS_LEVEL_INNER:
1963 semantic_name = TGSI_SEMANTIC_TESSINNER;
1964 break;
1965 case VARYING_SLOT_TESS_LEVEL_OUTER:
1966 semantic_name = TGSI_SEMANTIC_TESSOUTER;
1967 break;
1968 default:
1969 unreachable("unknown tess level");
1970 }
1971
1972 return load_tess_level(ctx, semantic_name);
1973
1974 }
1975
1976 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
1977 {
1978 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1979 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1980 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
1981 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1982 return get_num_tcs_out_vertices(ctx);
1983 else
1984 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1985 }
1986
1987 void si_load_system_value(struct si_shader_context *ctx,
1988 unsigned index,
1989 const struct tgsi_full_declaration *decl)
1990 {
1991 LLVMValueRef value = 0;
1992
1993 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
1994
1995 switch (decl->Semantic.Name) {
1996 case TGSI_SEMANTIC_INSTANCEID:
1997 value = ctx->abi.instance_id;
1998 break;
1999
2000 case TGSI_SEMANTIC_VERTEXID:
2001 value = LLVMBuildAdd(ctx->ac.builder,
2002 ctx->abi.vertex_id,
2003 ctx->abi.base_vertex, "");
2004 break;
2005
2006 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2007 /* Unused. Clarify the meaning in indexed vs. non-indexed
2008 * draws if this is ever used again. */
2009 assert(false);
2010 break;
2011
2012 case TGSI_SEMANTIC_BASEVERTEX:
2013 value = get_base_vertex(&ctx->abi);
2014 break;
2015
2016 case TGSI_SEMANTIC_BASEINSTANCE:
2017 value = ctx->abi.start_instance;
2018 break;
2019
2020 case TGSI_SEMANTIC_DRAWID:
2021 value = ctx->abi.draw_id;
2022 break;
2023
2024 case TGSI_SEMANTIC_INVOCATIONID:
2025 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2026 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2027 else if (ctx->type == PIPE_SHADER_GEOMETRY)
2028 value = ctx->abi.gs_invocation_id;
2029 else
2030 assert(!"INVOCATIONID not implemented");
2031 break;
2032
2033 case TGSI_SEMANTIC_POSITION:
2034 {
2035 LLVMValueRef pos[4] = {
2036 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2037 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2038 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2039 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2040 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT)),
2041 };
2042 value = ac_build_gather_values(&ctx->ac, pos, 4);
2043 break;
2044 }
2045
2046 case TGSI_SEMANTIC_FACE:
2047 value = ctx->abi.front_face;
2048 break;
2049
2050 case TGSI_SEMANTIC_SAMPLEID:
2051 value = si_get_sample_id(ctx);
2052 break;
2053
2054 case TGSI_SEMANTIC_SAMPLEPOS: {
2055 LLVMValueRef pos[4] = {
2056 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2057 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2058 LLVMConstReal(ctx->f32, 0),
2059 LLVMConstReal(ctx->f32, 0)
2060 };
2061 pos[0] = ac_build_fract(&ctx->ac, pos[0], 32);
2062 pos[1] = ac_build_fract(&ctx->ac, pos[1], 32);
2063 value = ac_build_gather_values(&ctx->ac, pos, 4);
2064 break;
2065 }
2066
2067 case TGSI_SEMANTIC_SAMPLEMASK:
2068 /* This can only occur with the OpenGL Core profile, which
2069 * doesn't support smoothing.
2070 */
2071 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2072 break;
2073
2074 case TGSI_SEMANTIC_TESSCOORD:
2075 value = si_load_tess_coord(&ctx->abi);
2076 break;
2077
2078 case TGSI_SEMANTIC_VERTICESIN:
2079 value = si_load_patch_vertices_in(&ctx->abi);
2080 break;
2081
2082 case TGSI_SEMANTIC_TESSINNER:
2083 case TGSI_SEMANTIC_TESSOUTER:
2084 value = load_tess_level(ctx, decl->Semantic.Name);
2085 break;
2086
2087 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
2088 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
2089 {
2090 LLVMValueRef buf, slot, val[4];
2091 int i, offset;
2092
2093 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
2094 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2095 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
2096 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
2097
2098 for (i = 0; i < 4; i++)
2099 val[i] = buffer_load_const(ctx, buf,
2100 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
2101 value = ac_build_gather_values(&ctx->ac, val, 4);
2102 break;
2103 }
2104
2105 case TGSI_SEMANTIC_PRIMID:
2106 value = get_primitive_id(ctx, 0);
2107 break;
2108
2109 case TGSI_SEMANTIC_GRID_SIZE:
2110 value = ctx->abi.num_work_groups;
2111 break;
2112
2113 case TGSI_SEMANTIC_BLOCK_SIZE:
2114 value = get_block_size(&ctx->abi);
2115 break;
2116
2117 case TGSI_SEMANTIC_BLOCK_ID:
2118 {
2119 LLVMValueRef values[3];
2120
2121 for (int i = 0; i < 3; i++) {
2122 values[i] = ctx->i32_0;
2123 if (ctx->abi.workgroup_ids[i]) {
2124 values[i] = ctx->abi.workgroup_ids[i];
2125 }
2126 }
2127 value = ac_build_gather_values(&ctx->ac, values, 3);
2128 break;
2129 }
2130
2131 case TGSI_SEMANTIC_THREAD_ID:
2132 value = ctx->abi.local_invocation_ids;
2133 break;
2134
2135 case TGSI_SEMANTIC_HELPER_INVOCATION:
2136 value = ac_build_load_helper_invocation(&ctx->ac);
2137 break;
2138
2139 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2140 value = LLVMConstInt(ctx->i32, 64, 0);
2141 break;
2142
2143 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2144 value = ac_get_thread_id(&ctx->ac);
2145 break;
2146
2147 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2148 {
2149 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2150 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2151 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
2152 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2153 break;
2154 }
2155
2156 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2157 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2158 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2159 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2160 {
2161 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2162 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2163 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2164 /* All bits set except LSB */
2165 value = LLVMConstInt(ctx->i64, -2, 0);
2166 } else {
2167 /* All bits set */
2168 value = LLVMConstInt(ctx->i64, -1, 0);
2169 }
2170 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2171 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2172 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2173 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2174 value = LLVMBuildNot(ctx->ac.builder, value, "");
2175 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2176 break;
2177 }
2178
2179 case TGSI_SEMANTIC_CS_USER_DATA:
2180 value = LLVMGetParam(ctx->main_fn, ctx->param_cs_user_data);
2181 break;
2182
2183 default:
2184 assert(!"unknown system value");
2185 return;
2186 }
2187
2188 ctx->system_values[index] = value;
2189 }
2190
2191 void si_declare_compute_memory(struct si_shader_context *ctx)
2192 {
2193 struct si_shader_selector *sel = ctx->shader->selector;
2194 unsigned lds_size = sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE];
2195
2196 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_ADDR_SPACE_LDS);
2197 LLVMValueRef var;
2198
2199 assert(!ctx->ac.lds);
2200
2201 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2202 LLVMArrayType(ctx->i8, lds_size),
2203 "compute_lds",
2204 AC_ADDR_SPACE_LDS);
2205 LLVMSetAlignment(var, 4);
2206
2207 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2208 }
2209
2210 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
2211 const struct tgsi_full_declaration *decl)
2212 {
2213 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2214 assert(decl->Range.First == decl->Range.Last);
2215
2216 si_declare_compute_memory(ctx);
2217 }
2218
2219 static LLVMValueRef load_const_buffer_desc_fast_path(struct si_shader_context *ctx)
2220 {
2221 LLVMValueRef ptr =
2222 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2223 struct si_shader_selector *sel = ctx->shader->selector;
2224
2225 /* Do the bounds checking with a descriptor, because
2226 * doing computation and manual bounds checking of 64-bit
2227 * addresses generates horrible VALU code with very high
2228 * VGPR usage and very low SIMD occupancy.
2229 */
2230 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->ac.intptr, "");
2231
2232 LLVMValueRef desc0, desc1;
2233 desc0 = ptr;
2234 desc1 = LLVMConstInt(ctx->i32,
2235 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
2236
2237 LLVMValueRef desc_elems[] = {
2238 desc0,
2239 desc1,
2240 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2241 LLVMConstInt(ctx->i32,
2242 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2243 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2244 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2245 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2246 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2247 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2248 };
2249
2250 return ac_build_gather_values(&ctx->ac, desc_elems, 4);
2251 }
2252
2253 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2254 {
2255 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2256 ctx->param_const_and_shader_buffers);
2257
2258 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2259 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2260 }
2261
2262 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2263 {
2264 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2265 struct si_shader_selector *sel = ctx->shader->selector;
2266
2267 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2268
2269 if (sel->info.const_buffers_declared == 1 &&
2270 sel->info.shader_buffers_declared == 0) {
2271 return load_const_buffer_desc_fast_path(ctx);
2272 }
2273
2274 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2275 index = LLVMBuildAdd(ctx->ac.builder, index,
2276 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2277
2278 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2279 }
2280
2281 static LLVMValueRef
2282 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2283 {
2284 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2285 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2286 ctx->param_const_and_shader_buffers);
2287
2288 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2289 index = LLVMBuildSub(ctx->ac.builder,
2290 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2291 index, "");
2292
2293 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2294 }
2295
2296 static LLVMValueRef fetch_constant(
2297 struct lp_build_tgsi_context *bld_base,
2298 const struct tgsi_full_src_register *reg,
2299 enum tgsi_opcode_type type,
2300 unsigned swizzle_in)
2301 {
2302 struct si_shader_context *ctx = si_shader_context(bld_base);
2303 struct si_shader_selector *sel = ctx->shader->selector;
2304 const struct tgsi_ind_register *ireg = &reg->Indirect;
2305 unsigned buf, idx;
2306 unsigned swizzle = swizzle_in & 0xffff;
2307
2308 LLVMValueRef addr, bufp;
2309
2310 if (swizzle_in == LP_CHAN_ALL) {
2311 unsigned chan;
2312 LLVMValueRef values[4];
2313 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2314 values[chan] = fetch_constant(bld_base, reg, type, chan);
2315
2316 return ac_build_gather_values(&ctx->ac, values, 4);
2317 }
2318
2319 /* Split 64-bit loads. */
2320 if (tgsi_type_is_64bit(type)) {
2321 LLVMValueRef lo, hi;
2322
2323 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2324 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, (swizzle_in >> 16));
2325 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2326 lo, hi);
2327 }
2328
2329 idx = reg->Register.Index * 4 + swizzle;
2330 if (reg->Register.Indirect) {
2331 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2332 } else {
2333 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2334 }
2335
2336 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2337 if (sel->info.const_buffers_declared == 1 &&
2338 sel->info.shader_buffers_declared == 0) {
2339 LLVMValueRef desc = load_const_buffer_desc_fast_path(ctx);
2340 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2341 return bitcast(bld_base, type, result);
2342 }
2343
2344 assert(reg->Register.Dimension);
2345 buf = reg->Dimension.Index;
2346
2347 if (reg->Dimension.Indirect) {
2348 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2349 LLVMValueRef index;
2350 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2351 reg->Dimension.Index,
2352 ctx->num_const_buffers);
2353 index = LLVMBuildAdd(ctx->ac.builder, index,
2354 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2355 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2356 } else
2357 bufp = load_const_buffer_desc(ctx, buf);
2358
2359 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2360 }
2361
2362 /* Initialize arguments for the shader export intrinsic */
2363 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2364 LLVMValueRef *values,
2365 unsigned target,
2366 struct ac_export_args *args)
2367 {
2368 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2369 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2370 unsigned chan;
2371 bool is_int8, is_int10;
2372
2373 /* Default is 0xf. Adjusted below depending on the format. */
2374 args->enabled_channels = 0xf; /* writemask */
2375
2376 /* Specify whether the EXEC mask represents the valid mask */
2377 args->valid_mask = 0;
2378
2379 /* Specify whether this is the last export */
2380 args->done = 0;
2381
2382 /* Specify the target we are exporting */
2383 args->target = target;
2384
2385 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2386 const struct si_shader_key *key = &ctx->shader->key;
2387 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2388 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2389
2390 assert(cbuf >= 0 && cbuf < 8);
2391 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2392 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2393 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2394 }
2395
2396 args->compr = false;
2397 args->out[0] = f32undef;
2398 args->out[1] = f32undef;
2399 args->out[2] = f32undef;
2400 args->out[3] = f32undef;
2401
2402 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2403 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2404 unsigned bits, bool hi) = NULL;
2405
2406 switch (spi_shader_col_format) {
2407 case V_028714_SPI_SHADER_ZERO:
2408 args->enabled_channels = 0; /* writemask */
2409 args->target = V_008DFC_SQ_EXP_NULL;
2410 break;
2411
2412 case V_028714_SPI_SHADER_32_R:
2413 args->enabled_channels = 1; /* writemask */
2414 args->out[0] = values[0];
2415 break;
2416
2417 case V_028714_SPI_SHADER_32_GR:
2418 args->enabled_channels = 0x3; /* writemask */
2419 args->out[0] = values[0];
2420 args->out[1] = values[1];
2421 break;
2422
2423 case V_028714_SPI_SHADER_32_AR:
2424 args->enabled_channels = 0x9; /* writemask */
2425 args->out[0] = values[0];
2426 args->out[3] = values[3];
2427 break;
2428
2429 case V_028714_SPI_SHADER_FP16_ABGR:
2430 packf = ac_build_cvt_pkrtz_f16;
2431 break;
2432
2433 case V_028714_SPI_SHADER_UNORM16_ABGR:
2434 packf = ac_build_cvt_pknorm_u16;
2435 break;
2436
2437 case V_028714_SPI_SHADER_SNORM16_ABGR:
2438 packf = ac_build_cvt_pknorm_i16;
2439 break;
2440
2441 case V_028714_SPI_SHADER_UINT16_ABGR:
2442 packi = ac_build_cvt_pk_u16;
2443 break;
2444
2445 case V_028714_SPI_SHADER_SINT16_ABGR:
2446 packi = ac_build_cvt_pk_i16;
2447 break;
2448
2449 case V_028714_SPI_SHADER_32_ABGR:
2450 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2451 break;
2452 }
2453
2454 /* Pack f16 or norm_i16/u16. */
2455 if (packf) {
2456 for (chan = 0; chan < 2; chan++) {
2457 LLVMValueRef pack_args[2] = {
2458 values[2 * chan],
2459 values[2 * chan + 1]
2460 };
2461 LLVMValueRef packed;
2462
2463 packed = packf(&ctx->ac, pack_args);
2464 args->out[chan] = ac_to_float(&ctx->ac, packed);
2465 }
2466 args->compr = 1; /* COMPR flag */
2467 }
2468 /* Pack i16/u16. */
2469 if (packi) {
2470 for (chan = 0; chan < 2; chan++) {
2471 LLVMValueRef pack_args[2] = {
2472 ac_to_integer(&ctx->ac, values[2 * chan]),
2473 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2474 };
2475 LLVMValueRef packed;
2476
2477 packed = packi(&ctx->ac, pack_args,
2478 is_int8 ? 8 : is_int10 ? 10 : 16,
2479 chan == 1);
2480 args->out[chan] = ac_to_float(&ctx->ac, packed);
2481 }
2482 args->compr = 1; /* COMPR flag */
2483 }
2484 }
2485
2486 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2487 LLVMValueRef alpha)
2488 {
2489 struct si_shader_context *ctx = si_shader_context(bld_base);
2490
2491 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2492 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2493 [PIPE_FUNC_LESS] = LLVMRealOLT,
2494 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2495 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2496 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2497 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2498 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2499 };
2500 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2501 assert(cond);
2502
2503 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2504 SI_PARAM_ALPHA_REF);
2505 LLVMValueRef alpha_pass =
2506 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2507 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2508 } else {
2509 ac_build_kill_if_false(&ctx->ac, ctx->i1false);
2510 }
2511 }
2512
2513 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2514 LLVMValueRef alpha,
2515 unsigned samplemask_param)
2516 {
2517 struct si_shader_context *ctx = si_shader_context(bld_base);
2518 LLVMValueRef coverage;
2519
2520 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2521 coverage = LLVMGetParam(ctx->main_fn,
2522 samplemask_param);
2523 coverage = ac_to_integer(&ctx->ac, coverage);
2524
2525 coverage = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32",
2526 ctx->i32,
2527 &coverage, 1, AC_FUNC_ATTR_READNONE);
2528
2529 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2530 ctx->f32, "");
2531
2532 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2533 LLVMConstReal(ctx->f32,
2534 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2535
2536 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2537 }
2538
2539 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2540 struct ac_export_args *pos, LLVMValueRef *out_elts)
2541 {
2542 unsigned reg_index;
2543 unsigned chan;
2544 unsigned const_chan;
2545 LLVMValueRef base_elt;
2546 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2547 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2548 SI_VS_CONST_CLIP_PLANES, 0);
2549 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2550
2551 for (reg_index = 0; reg_index < 2; reg_index ++) {
2552 struct ac_export_args *args = &pos[2 + reg_index];
2553
2554 args->out[0] =
2555 args->out[1] =
2556 args->out[2] =
2557 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2558
2559 /* Compute dot products of position and user clip plane vectors */
2560 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2561 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2562 LLVMValueRef addr =
2563 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2564 const_chan) * 4, 0);
2565 base_elt = buffer_load_const(ctx, const_resource,
2566 addr);
2567 args->out[chan] = ac_build_fmad(&ctx->ac, base_elt,
2568 out_elts[const_chan], args->out[chan]);
2569 }
2570 }
2571
2572 args->enabled_channels = 0xf;
2573 args->valid_mask = 0;
2574 args->done = 0;
2575 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2576 args->compr = 0;
2577 }
2578 }
2579
2580 static void si_dump_streamout(struct pipe_stream_output_info *so)
2581 {
2582 unsigned i;
2583
2584 if (so->num_outputs)
2585 fprintf(stderr, "STREAMOUT\n");
2586
2587 for (i = 0; i < so->num_outputs; i++) {
2588 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2589 so->output[i].start_component;
2590 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2591 i, so->output[i].output_buffer,
2592 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2593 so->output[i].register_index,
2594 mask & 1 ? "x" : "",
2595 mask & 2 ? "y" : "",
2596 mask & 4 ? "z" : "",
2597 mask & 8 ? "w" : "");
2598 }
2599 }
2600
2601 static void emit_streamout_output(struct si_shader_context *ctx,
2602 LLVMValueRef const *so_buffers,
2603 LLVMValueRef const *so_write_offsets,
2604 struct pipe_stream_output *stream_out,
2605 struct si_shader_output_values *shader_out)
2606 {
2607 unsigned buf_idx = stream_out->output_buffer;
2608 unsigned start = stream_out->start_component;
2609 unsigned num_comps = stream_out->num_components;
2610 LLVMValueRef out[4];
2611
2612 assert(num_comps && num_comps <= 4);
2613 if (!num_comps || num_comps > 4)
2614 return;
2615
2616 /* Load the output as int. */
2617 for (int j = 0; j < num_comps; j++) {
2618 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2619
2620 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2621 }
2622
2623 /* Pack the output. */
2624 LLVMValueRef vdata = NULL;
2625
2626 switch (num_comps) {
2627 case 1: /* as i32 */
2628 vdata = out[0];
2629 break;
2630 case 2: /* as v2i32 */
2631 case 3: /* as v4i32 (aligned to 4) */
2632 out[3] = LLVMGetUndef(ctx->i32);
2633 /* fall through */
2634 case 4: /* as v4i32 */
2635 vdata = ac_build_gather_values(&ctx->ac, out, util_next_power_of_two(num_comps));
2636 break;
2637 }
2638
2639 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2640 vdata, num_comps,
2641 so_write_offsets[buf_idx],
2642 ctx->i32_0,
2643 stream_out->dst_offset * 4, 1, 1, true, false);
2644 }
2645
2646 /**
2647 * Write streamout data to buffers for vertex stream @p stream (different
2648 * vertex streams can occur for GS copy shaders).
2649 */
2650 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2651 struct si_shader_output_values *outputs,
2652 unsigned noutput, unsigned stream)
2653 {
2654 struct si_shader_selector *sel = ctx->shader->selector;
2655 struct pipe_stream_output_info *so = &sel->so;
2656 LLVMBuilderRef builder = ctx->ac.builder;
2657 int i;
2658 struct lp_build_if_state if_ctx;
2659
2660 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2661 LLVMValueRef so_vtx_count =
2662 si_unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2663
2664 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2665
2666 /* can_emit = tid < so_vtx_count; */
2667 LLVMValueRef can_emit =
2668 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2669
2670 /* Emit the streamout code conditionally. This actually avoids
2671 * out-of-bounds buffer access. The hw tells us via the SGPR
2672 * (so_vtx_count) which threads are allowed to emit streamout data. */
2673 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2674 {
2675 /* The buffer offset is computed as follows:
2676 * ByteOffset = streamout_offset[buffer_id]*4 +
2677 * (streamout_write_index + thread_id)*stride[buffer_id] +
2678 * attrib_offset
2679 */
2680
2681 LLVMValueRef so_write_index =
2682 LLVMGetParam(ctx->main_fn,
2683 ctx->param_streamout_write_index);
2684
2685 /* Compute (streamout_write_index + thread_id). */
2686 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2687
2688 /* Load the descriptor and compute the write offset for each
2689 * enabled buffer. */
2690 LLVMValueRef so_write_offset[4] = {};
2691 LLVMValueRef so_buffers[4];
2692 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2693 ctx->param_rw_buffers);
2694
2695 for (i = 0; i < 4; i++) {
2696 if (!so->stride[i])
2697 continue;
2698
2699 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2700 SI_VS_STREAMOUT_BUF0 + i, 0);
2701
2702 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2703
2704 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2705 ctx->param_streamout_offset[i]);
2706 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2707
2708 so_write_offset[i] = ac_build_imad(&ctx->ac, so_write_index,
2709 LLVMConstInt(ctx->i32, so->stride[i]*4, 0),
2710 so_offset);
2711 }
2712
2713 /* Write streamout data. */
2714 for (i = 0; i < so->num_outputs; i++) {
2715 unsigned reg = so->output[i].register_index;
2716
2717 if (reg >= noutput)
2718 continue;
2719
2720 if (stream != so->output[i].stream)
2721 continue;
2722
2723 emit_streamout_output(ctx, so_buffers, so_write_offset,
2724 &so->output[i], &outputs[reg]);
2725 }
2726 }
2727 lp_build_endif(&if_ctx);
2728 }
2729
2730 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2731 LLVMValueRef *values)
2732 {
2733 struct ac_export_args args;
2734
2735 si_llvm_init_export_args(ctx, values,
2736 V_008DFC_SQ_EXP_PARAM + index, &args);
2737 ac_build_export(&ctx->ac, &args);
2738 }
2739
2740 static void si_build_param_exports(struct si_shader_context *ctx,
2741 struct si_shader_output_values *outputs,
2742 unsigned noutput)
2743 {
2744 struct si_shader *shader = ctx->shader;
2745 unsigned param_count = 0;
2746
2747 for (unsigned i = 0; i < noutput; i++) {
2748 unsigned semantic_name = outputs[i].semantic_name;
2749 unsigned semantic_index = outputs[i].semantic_index;
2750
2751 if (outputs[i].vertex_stream[0] != 0 &&
2752 outputs[i].vertex_stream[1] != 0 &&
2753 outputs[i].vertex_stream[2] != 0 &&
2754 outputs[i].vertex_stream[3] != 0)
2755 continue;
2756
2757 switch (semantic_name) {
2758 case TGSI_SEMANTIC_LAYER:
2759 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2760 case TGSI_SEMANTIC_CLIPDIST:
2761 case TGSI_SEMANTIC_COLOR:
2762 case TGSI_SEMANTIC_BCOLOR:
2763 case TGSI_SEMANTIC_PRIMID:
2764 case TGSI_SEMANTIC_FOG:
2765 case TGSI_SEMANTIC_TEXCOORD:
2766 case TGSI_SEMANTIC_GENERIC:
2767 break;
2768 default:
2769 continue;
2770 }
2771
2772 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2773 semantic_index < SI_MAX_IO_GENERIC) &&
2774 shader->key.opt.kill_outputs &
2775 (1ull << si_shader_io_get_unique_index(semantic_name,
2776 semantic_index, true)))
2777 continue;
2778
2779 si_export_param(ctx, param_count, outputs[i].values);
2780
2781 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2782 shader->info.vs_output_param_offset[i] = param_count++;
2783 }
2784
2785 shader->info.nr_param_exports = param_count;
2786 }
2787
2788 /* Generate export instructions for hardware VS shader stage */
2789 static void si_llvm_export_vs(struct si_shader_context *ctx,
2790 struct si_shader_output_values *outputs,
2791 unsigned noutput)
2792 {
2793 struct si_shader *shader = ctx->shader;
2794 struct ac_export_args pos_args[4] = {};
2795 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2796 unsigned pos_idx;
2797 int i;
2798
2799 /* Build position exports. */
2800 for (i = 0; i < noutput; i++) {
2801 switch (outputs[i].semantic_name) {
2802 case TGSI_SEMANTIC_POSITION:
2803 si_llvm_init_export_args(ctx, outputs[i].values,
2804 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2805 break;
2806 case TGSI_SEMANTIC_PSIZE:
2807 psize_value = outputs[i].values[0];
2808 break;
2809 case TGSI_SEMANTIC_LAYER:
2810 layer_value = outputs[i].values[0];
2811 break;
2812 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2813 viewport_index_value = outputs[i].values[0];
2814 break;
2815 case TGSI_SEMANTIC_EDGEFLAG:
2816 edgeflag_value = outputs[i].values[0];
2817 break;
2818 case TGSI_SEMANTIC_CLIPDIST:
2819 if (!shader->key.opt.clip_disable) {
2820 unsigned index = 2 + outputs[i].semantic_index;
2821 si_llvm_init_export_args(ctx, outputs[i].values,
2822 V_008DFC_SQ_EXP_POS + index,
2823 &pos_args[index]);
2824 }
2825 break;
2826 case TGSI_SEMANTIC_CLIPVERTEX:
2827 if (!shader->key.opt.clip_disable) {
2828 si_llvm_emit_clipvertex(ctx, pos_args,
2829 outputs[i].values);
2830 }
2831 break;
2832 }
2833 }
2834
2835 /* We need to add the position output manually if it's missing. */
2836 if (!pos_args[0].out[0]) {
2837 pos_args[0].enabled_channels = 0xf; /* writemask */
2838 pos_args[0].valid_mask = 0; /* EXEC mask */
2839 pos_args[0].done = 0; /* last export? */
2840 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2841 pos_args[0].compr = 0; /* COMPR flag */
2842 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2843 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2844 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2845 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2846 }
2847
2848 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2849 if (shader->selector->info.writes_psize ||
2850 shader->selector->info.writes_edgeflag ||
2851 shader->selector->info.writes_viewport_index ||
2852 shader->selector->info.writes_layer) {
2853 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2854 (shader->selector->info.writes_edgeflag << 1) |
2855 (shader->selector->info.writes_layer << 2);
2856
2857 pos_args[1].valid_mask = 0; /* EXEC mask */
2858 pos_args[1].done = 0; /* last export? */
2859 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2860 pos_args[1].compr = 0; /* COMPR flag */
2861 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2862 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2863 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2864 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2865
2866 if (shader->selector->info.writes_psize)
2867 pos_args[1].out[0] = psize_value;
2868
2869 if (shader->selector->info.writes_edgeflag) {
2870 /* The output is a float, but the hw expects an integer
2871 * with the first bit containing the edge flag. */
2872 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2873 edgeflag_value,
2874 ctx->i32, "");
2875 edgeflag_value = ac_build_umin(&ctx->ac,
2876 edgeflag_value,
2877 ctx->i32_1);
2878
2879 /* The LLVM intrinsic expects a float. */
2880 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2881 }
2882
2883 if (ctx->screen->info.chip_class >= GFX9) {
2884 /* GFX9 has the layer in out.z[10:0] and the viewport
2885 * index in out.z[19:16].
2886 */
2887 if (shader->selector->info.writes_layer)
2888 pos_args[1].out[2] = layer_value;
2889
2890 if (shader->selector->info.writes_viewport_index) {
2891 LLVMValueRef v = viewport_index_value;
2892
2893 v = ac_to_integer(&ctx->ac, v);
2894 v = LLVMBuildShl(ctx->ac.builder, v,
2895 LLVMConstInt(ctx->i32, 16, 0), "");
2896 v = LLVMBuildOr(ctx->ac.builder, v,
2897 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2898 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2899 pos_args[1].enabled_channels |= 1 << 2;
2900 }
2901 } else {
2902 if (shader->selector->info.writes_layer)
2903 pos_args[1].out[2] = layer_value;
2904
2905 if (shader->selector->info.writes_viewport_index) {
2906 pos_args[1].out[3] = viewport_index_value;
2907 pos_args[1].enabled_channels |= 1 << 3;
2908 }
2909 }
2910 }
2911
2912 for (i = 0; i < 4; i++)
2913 if (pos_args[i].out[0])
2914 shader->info.nr_pos_exports++;
2915
2916 pos_idx = 0;
2917 for (i = 0; i < 4; i++) {
2918 if (!pos_args[i].out[0])
2919 continue;
2920
2921 /* Specify the target we are exporting */
2922 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2923
2924 if (pos_idx == shader->info.nr_pos_exports)
2925 /* Specify that this is the last export */
2926 pos_args[i].done = 1;
2927
2928 ac_build_export(&ctx->ac, &pos_args[i]);
2929 }
2930
2931 /* Build parameter exports. */
2932 si_build_param_exports(ctx, outputs, noutput);
2933 }
2934
2935 /**
2936 * Forward all outputs from the vertex shader to the TES. This is only used
2937 * for the fixed function TCS.
2938 */
2939 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2940 {
2941 struct si_shader_context *ctx = si_shader_context(bld_base);
2942 LLVMValueRef invocation_id, buffer, buffer_offset;
2943 LLVMValueRef lds_vertex_stride, lds_base;
2944 uint64_t inputs;
2945
2946 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2947 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
2948 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2949
2950 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
2951 lds_base = get_tcs_in_current_patch_offset(ctx);
2952 lds_base = ac_build_imad(&ctx->ac, invocation_id, lds_vertex_stride,
2953 lds_base);
2954
2955 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
2956 while (inputs) {
2957 unsigned i = u_bit_scan64(&inputs);
2958
2959 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2960 LLVMConstInt(ctx->i32, 4 * i, 0),
2961 "");
2962
2963 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2964 get_rel_patch_id(ctx),
2965 invocation_id,
2966 LLVMConstInt(ctx->i32, i, 0));
2967
2968 LLVMValueRef value = lds_load(bld_base, ctx->ac.i32, ~0,
2969 lds_ptr);
2970
2971 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
2972 buffer_offset, 0, 1, 0, true, false);
2973 }
2974 }
2975
2976 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2977 LLVMValueRef rel_patch_id,
2978 LLVMValueRef invocation_id,
2979 LLVMValueRef tcs_out_current_patch_data_offset,
2980 LLVMValueRef invoc0_tf_outer[4],
2981 LLVMValueRef invoc0_tf_inner[2])
2982 {
2983 struct si_shader_context *ctx = si_shader_context(bld_base);
2984 struct si_shader *shader = ctx->shader;
2985 unsigned tess_inner_index, tess_outer_index;
2986 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2987 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2988 unsigned stride, outer_comps, inner_comps, i, offset;
2989 struct lp_build_if_state if_ctx, inner_if_ctx;
2990
2991 /* Add a barrier before loading tess factors from LDS. */
2992 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
2993 si_llvm_emit_barrier(NULL, bld_base, NULL);
2994
2995 /* Do this only for invocation 0, because the tess levels are per-patch,
2996 * not per-vertex.
2997 *
2998 * This can't jump, because invocation 0 executes this. It should
2999 * at least mask out the loads and stores for other invocations.
3000 */
3001 lp_build_if(&if_ctx, &ctx->gallivm,
3002 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3003 invocation_id, ctx->i32_0, ""));
3004
3005 /* Determine the layout of one tess factor element in the buffer. */
3006 switch (shader->key.part.tcs.epilog.prim_mode) {
3007 case PIPE_PRIM_LINES:
3008 stride = 2; /* 2 dwords, 1 vec2 store */
3009 outer_comps = 2;
3010 inner_comps = 0;
3011 break;
3012 case PIPE_PRIM_TRIANGLES:
3013 stride = 4; /* 4 dwords, 1 vec4 store */
3014 outer_comps = 3;
3015 inner_comps = 1;
3016 break;
3017 case PIPE_PRIM_QUADS:
3018 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3019 outer_comps = 4;
3020 inner_comps = 2;
3021 break;
3022 default:
3023 assert(0);
3024 return;
3025 }
3026
3027 for (i = 0; i < 4; i++) {
3028 inner[i] = LLVMGetUndef(ctx->i32);
3029 outer[i] = LLVMGetUndef(ctx->i32);
3030 }
3031
3032 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3033 /* Tess factors are in VGPRs. */
3034 for (i = 0; i < outer_comps; i++)
3035 outer[i] = out[i] = invoc0_tf_outer[i];
3036 for (i = 0; i < inner_comps; i++)
3037 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3038 } else {
3039 /* Load tess_inner and tess_outer from LDS.
3040 * Any invocation can write them, so we can't get them from a temporary.
3041 */
3042 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3043 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3044
3045 lds_base = tcs_out_current_patch_data_offset;
3046 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3047 LLVMConstInt(ctx->i32,
3048 tess_inner_index * 4, 0), "");
3049 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3050 LLVMConstInt(ctx->i32,
3051 tess_outer_index * 4, 0), "");
3052
3053 for (i = 0; i < outer_comps; i++) {
3054 outer[i] = out[i] =
3055 lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3056 }
3057 for (i = 0; i < inner_comps; i++) {
3058 inner[i] = out[outer_comps+i] =
3059 lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3060 }
3061 }
3062
3063 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3064 /* For isolines, the hardware expects tess factors in the
3065 * reverse order from what GLSL / TGSI specify.
3066 */
3067 LLVMValueRef tmp = out[0];
3068 out[0] = out[1];
3069 out[1] = tmp;
3070 }
3071
3072 /* Convert the outputs to vectors for stores. */
3073 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3074 vec1 = NULL;
3075
3076 if (stride > 4)
3077 vec1 = ac_build_gather_values(&ctx->ac, out+4, stride - 4);
3078
3079 /* Get the buffer. */
3080 buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
3081
3082 /* Get the offset. */
3083 tf_base = LLVMGetParam(ctx->main_fn,
3084 ctx->param_tcs_factor_offset);
3085 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3086 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3087
3088 lp_build_if(&inner_if_ctx, &ctx->gallivm,
3089 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3090 rel_patch_id, ctx->i32_0, ""));
3091
3092 /* Store the dynamic HS control word. */
3093 offset = 0;
3094 if (ctx->screen->info.chip_class <= GFX8) {
3095 ac_build_buffer_store_dword(&ctx->ac, buffer,
3096 LLVMConstInt(ctx->i32, 0x80000000, 0),
3097 1, ctx->i32_0, tf_base,
3098 offset, 1, 0, true, false);
3099 offset += 4;
3100 }
3101
3102 lp_build_endif(&inner_if_ctx);
3103
3104 /* Store the tessellation factors. */
3105 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3106 MIN2(stride, 4), byteoffset, tf_base,
3107 offset, 1, 0, true, false);
3108 offset += 16;
3109 if (vec1)
3110 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3111 stride - 4, byteoffset, tf_base,
3112 offset, 1, 0, true, false);
3113
3114 /* Store the tess factors into the offchip buffer if TES reads them. */
3115 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3116 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3117 LLVMValueRef tf_inner_offset;
3118 unsigned param_outer, param_inner;
3119
3120 buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3121 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3122
3123 param_outer = si_shader_io_get_unique_index_patch(
3124 TGSI_SEMANTIC_TESSOUTER, 0);
3125 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3126 LLVMConstInt(ctx->i32, param_outer, 0));
3127
3128 outer_vec = ac_build_gather_values(&ctx->ac, outer,
3129 util_next_power_of_two(outer_comps));
3130
3131 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3132 outer_comps, tf_outer_offset,
3133 base, 0, 1, 0, true, false);
3134 if (inner_comps) {
3135 param_inner = si_shader_io_get_unique_index_patch(
3136 TGSI_SEMANTIC_TESSINNER, 0);
3137 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3138 LLVMConstInt(ctx->i32, param_inner, 0));
3139
3140 inner_vec = inner_comps == 1 ? inner[0] :
3141 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3142 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3143 inner_comps, tf_inner_offset,
3144 base, 0, 1, 0, true, false);
3145 }
3146 }
3147
3148 lp_build_endif(&if_ctx);
3149 }
3150
3151 static LLVMValueRef
3152 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3153 unsigned param, unsigned return_index)
3154 {
3155 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3156 LLVMGetParam(ctx->main_fn, param),
3157 return_index, "");
3158 }
3159
3160 static LLVMValueRef
3161 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3162 unsigned param, unsigned return_index)
3163 {
3164 LLVMBuilderRef builder = ctx->ac.builder;
3165 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3166
3167 return LLVMBuildInsertValue(builder, ret,
3168 ac_to_float(&ctx->ac, p),
3169 return_index, "");
3170 }
3171
3172 static LLVMValueRef
3173 si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret,
3174 unsigned param, unsigned return_index)
3175 {
3176 LLVMBuilderRef builder = ctx->ac.builder;
3177 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, param);
3178 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i32, "");
3179 return LLVMBuildInsertValue(builder, ret, ptr, return_index, "");
3180 }
3181
3182 /* This only writes the tessellation factor levels. */
3183 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
3184 unsigned max_outputs,
3185 LLVMValueRef *addrs)
3186 {
3187 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3188 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
3189 LLVMBuilderRef builder = ctx->ac.builder;
3190 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3191
3192 si_copy_tcs_inputs(bld_base);
3193
3194 rel_patch_id = get_rel_patch_id(ctx);
3195 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3196 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3197
3198 if (ctx->screen->info.chip_class >= GFX9) {
3199 LLVMBasicBlockRef blocks[2] = {
3200 LLVMGetInsertBlock(builder),
3201 ctx->merged_wrap_if_state.entry_block
3202 };
3203 LLVMValueRef values[2];
3204
3205 lp_build_endif(&ctx->merged_wrap_if_state);
3206
3207 values[0] = rel_patch_id;
3208 values[1] = LLVMGetUndef(ctx->i32);
3209 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3210
3211 values[0] = tf_lds_offset;
3212 values[1] = LLVMGetUndef(ctx->i32);
3213 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3214
3215 values[0] = invocation_id;
3216 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3217 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3218 }
3219
3220 /* Return epilog parameters from this function. */
3221 LLVMValueRef ret = ctx->return_value;
3222 unsigned vgpr;
3223
3224 if (ctx->screen->info.chip_class >= GFX9) {
3225 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3226 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3227 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3228 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3229 /* Tess offchip and tess factor offsets are at the beginning. */
3230 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3231 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3232 vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
3233 } else {
3234 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3235 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3236 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3237 GFX6_SGPR_TCS_OUT_LAYOUT);
3238 /* Tess offchip and tess factor offsets are after user SGPRs. */
3239 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3240 GFX6_TCS_NUM_USER_SGPR);
3241 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3242 GFX6_TCS_NUM_USER_SGPR + 1);
3243 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3244 }
3245
3246 /* VGPRs */
3247 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3248 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3249 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3250
3251 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3252 * the invocation_id output does not alias the tcs_rel_ids input,
3253 * which saves a V_MOV on gfx9.
3254 */
3255 vgpr += 2;
3256
3257 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3258 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3259
3260 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3261 vgpr++; /* skip the tess factor LDS offset */
3262 for (unsigned i = 0; i < 6; i++) {
3263 LLVMValueRef value =
3264 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3265 value = ac_to_float(&ctx->ac, value);
3266 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3267 }
3268 } else {
3269 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3270 }
3271 ctx->return_value = ret;
3272 }
3273
3274 /* Pass TCS inputs from LS to TCS on GFX9. */
3275 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3276 {
3277 LLVMValueRef ret = ctx->return_value;
3278
3279 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3280 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3281 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3282 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3283 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3284 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3285
3286 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3287 8 + SI_SGPR_RW_BUFFERS);
3288 ret = si_insert_input_ptr(ctx, ret,
3289 ctx->param_bindless_samplers_and_images,
3290 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3291
3292 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3293 8 + SI_SGPR_VS_STATE_BITS);
3294
3295 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3296 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3297 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3298 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3299 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3300 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3301
3302 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3303 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3304 ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
3305 vgpr++, "");
3306 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3307 ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
3308 vgpr++, "");
3309 ctx->return_value = ret;
3310 }
3311
3312 /* Pass GS inputs from ES to GS on GFX9. */
3313 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3314 {
3315 LLVMValueRef ret = ctx->return_value;
3316
3317 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3318 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3319 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3320 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3321 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3322
3323 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3324 8 + SI_SGPR_RW_BUFFERS);
3325 ret = si_insert_input_ptr(ctx, ret,
3326 ctx->param_bindless_samplers_and_images,
3327 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3328
3329 unsigned vgpr;
3330 if (ctx->type == PIPE_SHADER_VERTEX)
3331 vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
3332 else
3333 vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
3334
3335 for (unsigned i = 0; i < 5; i++) {
3336 unsigned param = ctx->param_gs_vtx01_offset + i;
3337 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3338 }
3339 ctx->return_value = ret;
3340 }
3341
3342 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3343 unsigned max_outputs,
3344 LLVMValueRef *addrs)
3345 {
3346 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3347 struct si_shader *shader = ctx->shader;
3348 struct tgsi_shader_info *info = &shader->selector->info;
3349 unsigned i, chan;
3350 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3351 ctx->param_rel_auto_id);
3352 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3353 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3354 vertex_dw_stride, "");
3355
3356 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3357 * its inputs from it. */
3358 for (i = 0; i < info->num_outputs; i++) {
3359 unsigned name = info->output_semantic_name[i];
3360 unsigned index = info->output_semantic_index[i];
3361
3362 /* The ARB_shader_viewport_layer_array spec contains the
3363 * following issue:
3364 *
3365 * 2) What happens if gl_ViewportIndex or gl_Layer is
3366 * written in the vertex shader and a geometry shader is
3367 * present?
3368 *
3369 * RESOLVED: The value written by the last vertex processing
3370 * stage is used. If the last vertex processing stage
3371 * (vertex, tessellation evaluation or geometry) does not
3372 * statically assign to gl_ViewportIndex or gl_Layer, index
3373 * or layer zero is assumed.
3374 *
3375 * So writes to those outputs in VS-as-LS are simply ignored.
3376 */
3377 if (name == TGSI_SEMANTIC_LAYER ||
3378 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3379 continue;
3380
3381 int param = si_shader_io_get_unique_index(name, index, false);
3382 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3383 LLVMConstInt(ctx->i32, param * 4, 0), "");
3384
3385 for (chan = 0; chan < 4; chan++) {
3386 if (!(info->output_usagemask[i] & (1 << chan)))
3387 continue;
3388
3389 lds_store(ctx, chan, dw_addr,
3390 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3391 }
3392 }
3393
3394 if (ctx->screen->info.chip_class >= GFX9)
3395 si_set_ls_return_value_for_tcs(ctx);
3396 }
3397
3398 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3399 unsigned max_outputs,
3400 LLVMValueRef *addrs)
3401 {
3402 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3403 struct si_shader *es = ctx->shader;
3404 struct tgsi_shader_info *info = &es->selector->info;
3405 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3406 ctx->param_es2gs_offset);
3407 LLVMValueRef lds_base = NULL;
3408 unsigned chan;
3409 int i;
3410
3411 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3412 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3413 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3414 LLVMValueRef wave_idx = si_unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3415 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3416 LLVMBuildMul(ctx->ac.builder, wave_idx,
3417 LLVMConstInt(ctx->i32, 64, false), ""), "");
3418 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3419 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3420 }
3421
3422 for (i = 0; i < info->num_outputs; i++) {
3423 int param;
3424
3425 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3426 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3427 continue;
3428
3429 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3430 info->output_semantic_index[i], false);
3431
3432 for (chan = 0; chan < 4; chan++) {
3433 if (!(info->output_usagemask[i] & (1 << chan)))
3434 continue;
3435
3436 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3437 out_val = ac_to_integer(&ctx->ac, out_val);
3438
3439 /* GFX9 has the ESGS ring in LDS. */
3440 if (ctx->screen->info.chip_class >= GFX9) {
3441 lds_store(ctx, param * 4 + chan, lds_base, out_val);
3442 continue;
3443 }
3444
3445 ac_build_buffer_store_dword(&ctx->ac,
3446 ctx->esgs_ring,
3447 out_val, 1, NULL, soffset,
3448 (4 * param + chan) * 4,
3449 1, 1, true, true);
3450 }
3451 }
3452
3453 if (ctx->screen->info.chip_class >= GFX9)
3454 si_set_es_return_value_for_gs(ctx);
3455 }
3456
3457 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3458 {
3459 if (ctx->screen->info.chip_class >= GFX9)
3460 return si_unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3461 else
3462 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3463 }
3464
3465 static void emit_gs_epilogue(struct si_shader_context *ctx)
3466 {
3467 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3468 si_get_gs_wave_id(ctx));
3469
3470 if (ctx->screen->info.chip_class >= GFX9)
3471 lp_build_endif(&ctx->merged_wrap_if_state);
3472 }
3473
3474 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3475 unsigned max_outputs,
3476 LLVMValueRef *addrs)
3477 {
3478 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3479 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3480
3481 assert(info->num_outputs <= max_outputs);
3482
3483 emit_gs_epilogue(ctx);
3484 }
3485
3486 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3487 {
3488 struct si_shader_context *ctx = si_shader_context(bld_base);
3489 emit_gs_epilogue(ctx);
3490 }
3491
3492 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3493 unsigned max_outputs,
3494 LLVMValueRef *addrs)
3495 {
3496 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3497 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3498 struct si_shader_output_values *outputs = NULL;
3499 int i,j;
3500
3501 assert(!ctx->shader->is_gs_copy_shader);
3502 assert(info->num_outputs <= max_outputs);
3503
3504 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3505
3506 /* Vertex color clamping.
3507 *
3508 * This uses a state constant loaded in a user data SGPR and
3509 * an IF statement is added that clamps all colors if the constant
3510 * is true.
3511 */
3512 struct lp_build_if_state if_ctx;
3513 LLVMValueRef cond = NULL;
3514 LLVMValueRef addr, val;
3515
3516 for (i = 0; i < info->num_outputs; i++) {
3517 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3518 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3519 continue;
3520
3521 /* We've found a color. */
3522 if (!cond) {
3523 /* The state is in the first bit of the user SGPR. */
3524 cond = LLVMGetParam(ctx->main_fn,
3525 ctx->param_vs_state_bits);
3526 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3527 ctx->i1, "");
3528 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3529 }
3530
3531 for (j = 0; j < 4; j++) {
3532 addr = addrs[4 * i + j];
3533 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3534 val = ac_build_clamp(&ctx->ac, val);
3535 LLVMBuildStore(ctx->ac.builder, val, addr);
3536 }
3537 }
3538
3539 if (cond)
3540 lp_build_endif(&if_ctx);
3541
3542 for (i = 0; i < info->num_outputs; i++) {
3543 outputs[i].semantic_name = info->output_semantic_name[i];
3544 outputs[i].semantic_index = info->output_semantic_index[i];
3545
3546 for (j = 0; j < 4; j++) {
3547 outputs[i].values[j] =
3548 LLVMBuildLoad(ctx->ac.builder,
3549 addrs[4 * i + j],
3550 "");
3551 outputs[i].vertex_stream[j] =
3552 (info->output_streams[i] >> (2 * j)) & 3;
3553 }
3554 }
3555
3556 if (ctx->shader->selector->so.num_outputs)
3557 si_llvm_emit_streamout(ctx, outputs, i, 0);
3558
3559 /* Export PrimitiveID. */
3560 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3561 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3562 outputs[i].semantic_index = 0;
3563 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3564 for (j = 1; j < 4; j++)
3565 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3566
3567 memset(outputs[i].vertex_stream, 0,
3568 sizeof(outputs[i].vertex_stream));
3569 i++;
3570 }
3571
3572 si_llvm_export_vs(ctx, outputs, i);
3573 FREE(outputs);
3574 }
3575
3576 static void si_llvm_emit_prim_discard_cs_epilogue(struct ac_shader_abi *abi,
3577 unsigned max_outputs,
3578 LLVMValueRef *addrs)
3579 {
3580 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3581 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3582 LLVMValueRef pos[4] = {};
3583
3584 assert(info->num_outputs <= max_outputs);
3585
3586 for (unsigned i = 0; i < info->num_outputs; i++) {
3587 if (info->output_semantic_name[i] != TGSI_SEMANTIC_POSITION)
3588 continue;
3589
3590 for (unsigned chan = 0; chan < 4; chan++)
3591 pos[chan] = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3592 break;
3593 }
3594 assert(pos[0] != NULL);
3595
3596 /* Return the position output. */
3597 LLVMValueRef ret = ctx->return_value;
3598 for (unsigned chan = 0; chan < 4; chan++)
3599 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, pos[chan], chan, "");
3600 ctx->return_value = ret;
3601 }
3602
3603 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3604 {
3605 struct si_shader_context *ctx = si_shader_context(bld_base);
3606
3607 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3608 &ctx->outputs[0][0]);
3609 }
3610
3611 struct si_ps_exports {
3612 unsigned num;
3613 struct ac_export_args args[10];
3614 };
3615
3616 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3617 LLVMValueRef depth, LLVMValueRef stencil,
3618 LLVMValueRef samplemask, struct si_ps_exports *exp)
3619 {
3620 struct si_shader_context *ctx = si_shader_context(bld_base);
3621 struct ac_export_args args;
3622
3623 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3624
3625 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3626 }
3627
3628 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3629 LLVMValueRef *color, unsigned index,
3630 unsigned samplemask_param,
3631 bool is_last, struct si_ps_exports *exp)
3632 {
3633 struct si_shader_context *ctx = si_shader_context(bld_base);
3634 int i;
3635
3636 /* Clamp color */
3637 if (ctx->shader->key.part.ps.epilog.clamp_color)
3638 for (i = 0; i < 4; i++)
3639 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3640
3641 /* Alpha to one */
3642 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3643 color[3] = ctx->ac.f32_1;
3644
3645 /* Alpha test */
3646 if (index == 0 &&
3647 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3648 si_alpha_test(bld_base, color[3]);
3649
3650 /* Line & polygon smoothing */
3651 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3652 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3653 samplemask_param);
3654
3655 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3656 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3657 struct ac_export_args args[8];
3658 int c, last = -1;
3659
3660 /* Get the export arguments, also find out what the last one is. */
3661 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3662 si_llvm_init_export_args(ctx, color,
3663 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3664 if (args[c].enabled_channels)
3665 last = c;
3666 }
3667
3668 /* Emit all exports. */
3669 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3670 if (is_last && last == c) {
3671 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3672 args[c].done = 1; /* DONE bit */
3673 } else if (!args[c].enabled_channels)
3674 continue; /* unnecessary NULL export */
3675
3676 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3677 }
3678 } else {
3679 struct ac_export_args args;
3680
3681 /* Export */
3682 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3683 &args);
3684 if (is_last) {
3685 args.valid_mask = 1; /* whether the EXEC mask is valid */
3686 args.done = 1; /* DONE bit */
3687 } else if (!args.enabled_channels)
3688 return; /* unnecessary NULL export */
3689
3690 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3691 }
3692 }
3693
3694 static void si_emit_ps_exports(struct si_shader_context *ctx,
3695 struct si_ps_exports *exp)
3696 {
3697 for (unsigned i = 0; i < exp->num; i++)
3698 ac_build_export(&ctx->ac, &exp->args[i]);
3699 }
3700
3701 /**
3702 * Return PS outputs in this order:
3703 *
3704 * v[0:3] = color0.xyzw
3705 * v[4:7] = color1.xyzw
3706 * ...
3707 * vN+0 = Depth
3708 * vN+1 = Stencil
3709 * vN+2 = SampleMask
3710 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3711 *
3712 * The alpha-ref SGPR is returned via its original location.
3713 */
3714 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3715 unsigned max_outputs,
3716 LLVMValueRef *addrs)
3717 {
3718 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3719 struct si_shader *shader = ctx->shader;
3720 struct tgsi_shader_info *info = &shader->selector->info;
3721 LLVMBuilderRef builder = ctx->ac.builder;
3722 unsigned i, j, first_vgpr, vgpr;
3723
3724 LLVMValueRef color[8][4] = {};
3725 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3726 LLVMValueRef ret;
3727
3728 if (ctx->postponed_kill)
3729 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3730
3731 /* Read the output values. */
3732 for (i = 0; i < info->num_outputs; i++) {
3733 unsigned semantic_name = info->output_semantic_name[i];
3734 unsigned semantic_index = info->output_semantic_index[i];
3735
3736 switch (semantic_name) {
3737 case TGSI_SEMANTIC_COLOR:
3738 assert(semantic_index < 8);
3739 for (j = 0; j < 4; j++) {
3740 LLVMValueRef ptr = addrs[4 * i + j];
3741 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3742 color[semantic_index][j] = result;
3743 }
3744 break;
3745 case TGSI_SEMANTIC_POSITION:
3746 depth = LLVMBuildLoad(builder,
3747 addrs[4 * i + 2], "");
3748 break;
3749 case TGSI_SEMANTIC_STENCIL:
3750 stencil = LLVMBuildLoad(builder,
3751 addrs[4 * i + 1], "");
3752 break;
3753 case TGSI_SEMANTIC_SAMPLEMASK:
3754 samplemask = LLVMBuildLoad(builder,
3755 addrs[4 * i + 0], "");
3756 break;
3757 default:
3758 fprintf(stderr, "Warning: GFX6 unhandled fs output type:%d\n",
3759 semantic_name);
3760 }
3761 }
3762
3763 /* Fill the return structure. */
3764 ret = ctx->return_value;
3765
3766 /* Set SGPRs. */
3767 ret = LLVMBuildInsertValue(builder, ret,
3768 ac_to_integer(&ctx->ac,
3769 LLVMGetParam(ctx->main_fn,
3770 SI_PARAM_ALPHA_REF)),
3771 SI_SGPR_ALPHA_REF, "");
3772
3773 /* Set VGPRs */
3774 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3775 for (i = 0; i < ARRAY_SIZE(color); i++) {
3776 if (!color[i][0])
3777 continue;
3778
3779 for (j = 0; j < 4; j++)
3780 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3781 }
3782 if (depth)
3783 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3784 if (stencil)
3785 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3786 if (samplemask)
3787 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3788
3789 /* Add the input sample mask for smoothing at the end. */
3790 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3791 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3792 ret = LLVMBuildInsertValue(builder, ret,
3793 LLVMGetParam(ctx->main_fn,
3794 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3795
3796 ctx->return_value = ret;
3797 }
3798
3799 static void membar_emit(
3800 const struct lp_build_tgsi_action *action,
3801 struct lp_build_tgsi_context *bld_base,
3802 struct lp_build_emit_data *emit_data)
3803 {
3804 struct si_shader_context *ctx = si_shader_context(bld_base);
3805 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3806 unsigned flags = LLVMConstIntGetZExtValue(src0);
3807 unsigned waitcnt = NOOP_WAITCNT;
3808
3809 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3810 waitcnt &= VM_CNT & LGKM_CNT;
3811
3812 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3813 TGSI_MEMBAR_SHADER_BUFFER |
3814 TGSI_MEMBAR_SHADER_IMAGE))
3815 waitcnt &= VM_CNT;
3816
3817 if (flags & TGSI_MEMBAR_SHARED)
3818 waitcnt &= LGKM_CNT;
3819
3820 if (waitcnt != NOOP_WAITCNT)
3821 ac_build_waitcnt(&ctx->ac, waitcnt);
3822 }
3823
3824 static void clock_emit(
3825 const struct lp_build_tgsi_action *action,
3826 struct lp_build_tgsi_context *bld_base,
3827 struct lp_build_emit_data *emit_data)
3828 {
3829 struct si_shader_context *ctx = si_shader_context(bld_base);
3830 LLVMValueRef tmp = ac_build_shader_clock(&ctx->ac);
3831
3832 emit_data->output[0] =
3833 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3834 emit_data->output[1] =
3835 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3836 }
3837
3838 static void si_llvm_emit_ddxy(
3839 const struct lp_build_tgsi_action *action,
3840 struct lp_build_tgsi_context *bld_base,
3841 struct lp_build_emit_data *emit_data)
3842 {
3843 struct si_shader_context *ctx = si_shader_context(bld_base);
3844 unsigned opcode = emit_data->info->opcode;
3845 LLVMValueRef val;
3846 int idx;
3847 unsigned mask;
3848
3849 if (opcode == TGSI_OPCODE_DDX_FINE)
3850 mask = AC_TID_MASK_LEFT;
3851 else if (opcode == TGSI_OPCODE_DDY_FINE)
3852 mask = AC_TID_MASK_TOP;
3853 else
3854 mask = AC_TID_MASK_TOP_LEFT;
3855
3856 /* for DDX we want to next X pixel, DDY next Y pixel. */
3857 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3858
3859 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3860 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3861 emit_data->output[emit_data->chan] = val;
3862 }
3863
3864 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3865 struct lp_build_tgsi_context *bld_base,
3866 struct lp_build_emit_data *emit_data)
3867 {
3868 struct si_shader_context *ctx = si_shader_context(bld_base);
3869 struct si_shader *shader = ctx->shader;
3870 const struct tgsi_shader_info *info = &shader->selector->info;
3871 LLVMValueRef interp_param;
3872 const struct tgsi_full_instruction *inst = emit_data->inst;
3873 const struct tgsi_full_src_register *input = &inst->Src[0];
3874 int input_base, input_array_size;
3875 int chan;
3876 int i;
3877 LLVMValueRef prim_mask = ctx->abi.prim_mask;
3878 LLVMValueRef array_idx, offset_x = NULL, offset_y = NULL;
3879 int interp_param_idx;
3880 unsigned interp;
3881 unsigned location;
3882
3883 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3884 /* offset is in second src, first two channels */
3885 offset_x = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
3886 TGSI_CHAN_X);
3887 offset_y = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
3888 TGSI_CHAN_Y);
3889 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3890 LLVMValueRef sample_position;
3891 LLVMValueRef sample_id;
3892 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3893
3894 /* fetch sample ID, then fetch its sample position,
3895 * and place into first two channels.
3896 */
3897 sample_id = lp_build_emit_fetch(bld_base,
3898 emit_data->inst, 1, TGSI_CHAN_X);
3899 sample_id = ac_to_integer(&ctx->ac, sample_id);
3900
3901 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
3902 * Language 4.50 spec says about interpolateAtSample:
3903 *
3904 * "Returns the value of the input interpolant variable at
3905 * the location of sample number sample. If multisample
3906 * buffers are not available, the input variable will be
3907 * evaluated at the center of the pixel. If sample sample
3908 * does not exist, the position used to interpolate the
3909 * input variable is undefined."
3910 *
3911 * This means that sample_id values outside of the valid are
3912 * in fact valid input, and the usual mechanism for loading the
3913 * sample position doesn't work.
3914 */
3915 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
3916 LLVMValueRef center[4] = {
3917 LLVMConstReal(ctx->f32, 0.5),
3918 LLVMConstReal(ctx->f32, 0.5),
3919 ctx->ac.f32_0,
3920 ctx->ac.f32_0,
3921 };
3922
3923 sample_position = ac_build_gather_values(&ctx->ac, center, 4);
3924 } else {
3925 sample_position = load_sample_position(&ctx->abi, sample_id);
3926 }
3927
3928 offset_x = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
3929 ctx->i32_0, "");
3930
3931 offset_x = LLVMBuildFSub(ctx->ac.builder, offset_x, halfval, "");
3932 offset_y = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
3933 ctx->i32_1, "");
3934 offset_y = LLVMBuildFSub(ctx->ac.builder, offset_y, halfval, "");
3935 }
3936
3937 assert(input->Register.File == TGSI_FILE_INPUT);
3938
3939 if (input->Register.Indirect) {
3940 unsigned array_id = input->Indirect.ArrayID;
3941
3942 if (array_id) {
3943 input_base = info->input_array_first[array_id];
3944 input_array_size = info->input_array_last[array_id] - input_base + 1;
3945 } else {
3946 input_base = inst->Src[0].Register.Index;
3947 input_array_size = info->num_inputs - input_base;
3948 }
3949
3950 array_idx = si_get_indirect_index(ctx, &input->Indirect,
3951 1, input->Register.Index - input_base);
3952 } else {
3953 input_base = inst->Src[0].Register.Index;
3954 input_array_size = 1;
3955 array_idx = ctx->i32_0;
3956 }
3957
3958 interp = shader->selector->info.input_interpolate[input_base];
3959
3960 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3961 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3962 location = TGSI_INTERPOLATE_LOC_CENTER;
3963 else
3964 location = TGSI_INTERPOLATE_LOC_CENTROID;
3965
3966 interp_param_idx = lookup_interp_param_index(interp, location);
3967 if (interp_param_idx == -1)
3968 return;
3969 else if (interp_param_idx)
3970 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
3971 else
3972 interp_param = NULL;
3973
3974 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3975 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3976 LLVMValueRef ij_out[2];
3977 LLVMValueRef ddxy_out = ac_build_ddxy_interp(&ctx->ac, interp_param);
3978
3979 /*
3980 * take the I then J parameters, and the DDX/Y for it, and
3981 * calculate the IJ inputs for the interpolator.
3982 * temp1 = ddx * offset/sample.x + I;
3983 * interp_param.I = ddy * offset/sample.y + temp1;
3984 * temp1 = ddx * offset/sample.x + J;
3985 * interp_param.J = ddy * offset/sample.y + temp1;
3986 */
3987 for (i = 0; i < 2; i++) {
3988 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
3989 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
3990 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
3991 ddxy_out, ix_ll, "");
3992 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
3993 ddxy_out, iy_ll, "");
3994 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
3995 interp_param, ix_ll, "");
3996 LLVMValueRef temp;
3997
3998 interp_el = ac_to_float(&ctx->ac, interp_el);
3999
4000 temp = ac_build_fmad(&ctx->ac, ddx_el, offset_x, interp_el);
4001 ij_out[i] = ac_build_fmad(&ctx->ac, ddy_el, offset_y, temp);
4002 }
4003 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4004 }
4005
4006 if (interp_param)
4007 interp_param = ac_to_float(&ctx->ac, interp_param);
4008
4009 for (chan = 0; chan < 4; chan++) {
4010 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
4011 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4012
4013 for (unsigned idx = 0; idx < input_array_size; ++idx) {
4014 LLVMValueRef v, i = NULL, j = NULL;
4015
4016 if (interp_param) {
4017 i = LLVMBuildExtractElement(
4018 ctx->ac.builder, interp_param, ctx->i32_0, "");
4019 j = LLVMBuildExtractElement(
4020 ctx->ac.builder, interp_param, ctx->i32_1, "");
4021 }
4022 v = si_build_fs_interp(ctx, input_base + idx, schan,
4023 prim_mask, i, j);
4024
4025 gather = LLVMBuildInsertElement(ctx->ac.builder,
4026 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
4027 }
4028
4029 emit_data->output[chan] = LLVMBuildExtractElement(
4030 ctx->ac.builder, gather, array_idx, "");
4031 }
4032 }
4033
4034 static void vote_all_emit(
4035 const struct lp_build_tgsi_action *action,
4036 struct lp_build_tgsi_context *bld_base,
4037 struct lp_build_emit_data *emit_data)
4038 {
4039 struct si_shader_context *ctx = si_shader_context(bld_base);
4040
4041 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
4042 emit_data->output[emit_data->chan] =
4043 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4044 }
4045
4046 static void vote_any_emit(
4047 const struct lp_build_tgsi_action *action,
4048 struct lp_build_tgsi_context *bld_base,
4049 struct lp_build_emit_data *emit_data)
4050 {
4051 struct si_shader_context *ctx = si_shader_context(bld_base);
4052
4053 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
4054 emit_data->output[emit_data->chan] =
4055 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4056 }
4057
4058 static void vote_eq_emit(
4059 const struct lp_build_tgsi_action *action,
4060 struct lp_build_tgsi_context *bld_base,
4061 struct lp_build_emit_data *emit_data)
4062 {
4063 struct si_shader_context *ctx = si_shader_context(bld_base);
4064
4065 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4066 emit_data->output[emit_data->chan] =
4067 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4068 }
4069
4070 static void ballot_emit(
4071 const struct lp_build_tgsi_action *action,
4072 struct lp_build_tgsi_context *bld_base,
4073 struct lp_build_emit_data *emit_data)
4074 {
4075 struct si_shader_context *ctx = si_shader_context(bld_base);
4076 LLVMBuilderRef builder = ctx->ac.builder;
4077 LLVMValueRef tmp;
4078
4079 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4080 tmp = ac_build_ballot(&ctx->ac, tmp);
4081 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4082
4083 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4084 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4085 }
4086
4087 static void read_lane_emit(
4088 const struct lp_build_tgsi_action *action,
4089 struct lp_build_tgsi_context *bld_base,
4090 struct lp_build_emit_data *emit_data)
4091 {
4092 struct si_shader_context *ctx = si_shader_context(bld_base);
4093
4094 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_READ_INVOC) {
4095 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4096 0, emit_data->src_chan);
4097
4098 /* Always read the source invocation (= lane) from the X channel. */
4099 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4100 1, TGSI_CHAN_X);
4101 emit_data->arg_count = 2;
4102 }
4103
4104 /* We currently have no other way to prevent LLVM from lifting the icmp
4105 * calls to a dominating basic block.
4106 */
4107 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4108
4109 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4110 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4111
4112 emit_data->output[emit_data->chan] =
4113 ac_build_intrinsic(&ctx->ac, action->intr_name,
4114 ctx->i32, emit_data->args, emit_data->arg_count,
4115 AC_FUNC_ATTR_READNONE |
4116 AC_FUNC_ATTR_CONVERGENT);
4117 }
4118
4119 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4120 struct lp_build_emit_data *emit_data)
4121 {
4122 struct si_shader_context *ctx = si_shader_context(bld_base);
4123 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4124 LLVMValueRef imm;
4125 unsigned stream;
4126
4127 assert(src0.File == TGSI_FILE_IMMEDIATE);
4128
4129 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4130 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4131 return stream;
4132 }
4133
4134 /* Emit one vertex from the geometry shader */
4135 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4136 unsigned stream,
4137 LLVMValueRef *addrs)
4138 {
4139 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4140 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4141 struct si_shader *shader = ctx->shader;
4142 struct lp_build_if_state if_state;
4143 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4144 ctx->param_gs2vs_offset);
4145 LLVMValueRef gs_next_vertex;
4146 LLVMValueRef can_emit;
4147 unsigned chan, offset;
4148 int i;
4149
4150 /* Write vertex attribute values to GSVS ring */
4151 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4152 ctx->gs_next_vertex[stream],
4153 "");
4154
4155 /* If this thread has already emitted the declared maximum number of
4156 * vertices, skip the write: excessive vertex emissions are not
4157 * supposed to have any effect.
4158 *
4159 * If the shader has no writes to memory, kill it instead. This skips
4160 * further memory loads and may allow LLVM to skip to the end
4161 * altogether.
4162 */
4163 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4164 LLVMConstInt(ctx->i32,
4165 shader->selector->gs_max_out_vertices, 0), "");
4166
4167 bool use_kill = !info->writes_memory;
4168 if (use_kill) {
4169 ac_build_kill_if_false(&ctx->ac, can_emit);
4170 } else {
4171 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4172 }
4173
4174 offset = 0;
4175 for (i = 0; i < info->num_outputs; i++) {
4176 for (chan = 0; chan < 4; chan++) {
4177 if (!(info->output_usagemask[i] & (1 << chan)) ||
4178 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4179 continue;
4180
4181 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4182 LLVMValueRef voffset =
4183 LLVMConstInt(ctx->i32, offset *
4184 shader->selector->gs_max_out_vertices, 0);
4185 offset++;
4186
4187 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4188 voffset = LLVMBuildMul(ctx->ac.builder, voffset,
4189 LLVMConstInt(ctx->i32, 4, 0), "");
4190
4191 out_val = ac_to_integer(&ctx->ac, out_val);
4192
4193 ac_build_buffer_store_dword(&ctx->ac,
4194 ctx->gsvs_ring[stream],
4195 out_val, 1,
4196 voffset, soffset, 0,
4197 1, 1, true, true);
4198 }
4199 }
4200
4201 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex, ctx->i32_1, "");
4202 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4203
4204 /* Signal vertex emission if vertex data was written. */
4205 if (offset) {
4206 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4207 si_get_gs_wave_id(ctx));
4208 }
4209
4210 if (!use_kill)
4211 lp_build_endif(&if_state);
4212 }
4213
4214 /* Emit one vertex from the geometry shader */
4215 static void si_tgsi_emit_vertex(
4216 const struct lp_build_tgsi_action *action,
4217 struct lp_build_tgsi_context *bld_base,
4218 struct lp_build_emit_data *emit_data)
4219 {
4220 struct si_shader_context *ctx = si_shader_context(bld_base);
4221 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4222
4223 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4224 }
4225
4226 /* Cut one primitive from the geometry shader */
4227 static void si_llvm_emit_primitive(struct ac_shader_abi *abi,
4228 unsigned stream)
4229 {
4230 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4231
4232 /* Signal primitive cut */
4233 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4234 si_get_gs_wave_id(ctx));
4235 }
4236
4237 /* Cut one primitive from the geometry shader */
4238 static void si_tgsi_emit_primitive(
4239 const struct lp_build_tgsi_action *action,
4240 struct lp_build_tgsi_context *bld_base,
4241 struct lp_build_emit_data *emit_data)
4242 {
4243 struct si_shader_context *ctx = si_shader_context(bld_base);
4244
4245 si_llvm_emit_primitive(&ctx->abi, si_llvm_get_stream(bld_base, emit_data));
4246 }
4247
4248 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4249 struct lp_build_tgsi_context *bld_base,
4250 struct lp_build_emit_data *emit_data)
4251 {
4252 struct si_shader_context *ctx = si_shader_context(bld_base);
4253
4254 /* GFX6 only (thanks to a hw bug workaround):
4255 * The real barrier instruction isn’t needed, because an entire patch
4256 * always fits into a single wave.
4257 */
4258 if (ctx->screen->info.chip_class == GFX6 &&
4259 ctx->type == PIPE_SHADER_TESS_CTRL) {
4260 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
4261 return;
4262 }
4263
4264 ac_build_s_barrier(&ctx->ac);
4265 }
4266
4267 void si_create_function(struct si_shader_context *ctx,
4268 const char *name,
4269 LLVMTypeRef *returns, unsigned num_returns,
4270 struct si_function_info *fninfo,
4271 unsigned max_workgroup_size)
4272 {
4273 int i;
4274
4275 si_llvm_create_func(ctx, name, returns, num_returns,
4276 fninfo->types, fninfo->num_params);
4277 ctx->return_value = LLVMGetUndef(ctx->return_type);
4278
4279 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4280 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4281
4282 /* The combination of:
4283 * - noalias
4284 * - dereferenceable
4285 * - invariant.load
4286 * allows the optimization passes to move loads and reduces
4287 * SGPR spilling significantly.
4288 */
4289 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4290 AC_FUNC_ATTR_INREG);
4291
4292 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4293 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4294 AC_FUNC_ATTR_NOALIAS);
4295 ac_add_attr_dereferenceable(P, UINT64_MAX);
4296 }
4297 }
4298
4299 for (i = 0; i < fninfo->num_params; ++i) {
4300 if (fninfo->assign[i])
4301 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4302 }
4303
4304 if (ctx->screen->info.address32_hi) {
4305 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4306 "amdgpu-32bit-address-high-bits",
4307 ctx->screen->info.address32_hi);
4308 }
4309
4310 ac_llvm_set_workgroup_size(ctx->main_fn, max_workgroup_size);
4311
4312 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4313 "no-signed-zeros-fp-math",
4314 "true");
4315
4316 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4317 /* These were copied from some LLVM test. */
4318 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4319 "less-precise-fpmad",
4320 "true");
4321 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4322 "no-infs-fp-math",
4323 "true");
4324 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4325 "no-nans-fp-math",
4326 "true");
4327 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4328 "unsafe-fp-math",
4329 "true");
4330 }
4331 }
4332
4333 static void declare_streamout_params(struct si_shader_context *ctx,
4334 struct pipe_stream_output_info *so,
4335 struct si_function_info *fninfo)
4336 {
4337 int i;
4338
4339 /* Streamout SGPRs. */
4340 if (so->num_outputs) {
4341 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4342 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4343 else
4344 ctx->param_streamout_config = fninfo->num_params - 1;
4345
4346 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4347 }
4348 /* A streamout buffer offset is loaded if the stride is non-zero. */
4349 for (i = 0; i < 4; i++) {
4350 if (!so->stride[i])
4351 continue;
4352
4353 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4354 }
4355 }
4356
4357 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4358 {
4359 switch (shader->selector->type) {
4360 case PIPE_SHADER_TESS_CTRL:
4361 /* Return this so that LLVM doesn't remove s_barrier
4362 * instructions on chips where we use s_barrier. */
4363 return shader->selector->screen->info.chip_class >= GFX7 ? 128 : 64;
4364
4365 case PIPE_SHADER_GEOMETRY:
4366 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4367
4368 case PIPE_SHADER_COMPUTE:
4369 break; /* see below */
4370
4371 default:
4372 return 0;
4373 }
4374
4375 const unsigned *properties = shader->selector->info.properties;
4376 unsigned max_work_group_size =
4377 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4378 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4379 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4380
4381 if (!max_work_group_size) {
4382 /* This is a variable group size compute shader,
4383 * compile it for the maximum possible group size.
4384 */
4385 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4386 }
4387 return max_work_group_size;
4388 }
4389
4390 static void declare_const_and_shader_buffers(struct si_shader_context *ctx,
4391 struct si_function_info *fninfo,
4392 bool assign_params)
4393 {
4394 LLVMTypeRef const_shader_buf_type;
4395
4396 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4397 ctx->shader->selector->info.shader_buffers_declared == 0)
4398 const_shader_buf_type = ctx->f32;
4399 else
4400 const_shader_buf_type = ctx->v4i32;
4401
4402 unsigned const_and_shader_buffers =
4403 add_arg(fninfo, ARG_SGPR,
4404 ac_array_in_const32_addr_space(const_shader_buf_type));
4405
4406 if (assign_params)
4407 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4408 }
4409
4410 static void declare_samplers_and_images(struct si_shader_context *ctx,
4411 struct si_function_info *fninfo,
4412 bool assign_params)
4413 {
4414 unsigned samplers_and_images =
4415 add_arg(fninfo, ARG_SGPR,
4416 ac_array_in_const32_addr_space(ctx->v8i32));
4417
4418 if (assign_params)
4419 ctx->param_samplers_and_images = samplers_and_images;
4420 }
4421
4422 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4423 struct si_function_info *fninfo,
4424 bool assign_params)
4425 {
4426 declare_const_and_shader_buffers(ctx, fninfo, assign_params);
4427 declare_samplers_and_images(ctx, fninfo, assign_params);
4428 }
4429
4430 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4431 struct si_function_info *fninfo)
4432 {
4433 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4434 ac_array_in_const32_addr_space(ctx->v4i32));
4435 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4436 ac_array_in_const32_addr_space(ctx->v8i32));
4437 }
4438
4439 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4440 struct si_function_info *fninfo)
4441 {
4442 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4443 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4444 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4445 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4446 }
4447
4448 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4449 struct si_function_info *fninfo,
4450 unsigned *num_prolog_vgprs)
4451 {
4452 struct si_shader *shader = ctx->shader;
4453
4454 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4455 if (shader->key.as_ls) {
4456 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4457 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4458 } else {
4459 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4460 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4461 }
4462 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4463
4464 if (!shader->is_gs_copy_shader) {
4465 /* Vertex load indices. */
4466 ctx->param_vertex_index0 = fninfo->num_params;
4467 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4468 add_arg(fninfo, ARG_VGPR, ctx->i32);
4469 *num_prolog_vgprs += shader->selector->info.num_inputs;
4470 }
4471 }
4472
4473 static void declare_vs_blit_inputs(struct si_shader_context *ctx,
4474 struct si_function_info *fninfo,
4475 unsigned vs_blit_property)
4476 {
4477 ctx->param_vs_blit_inputs = fninfo->num_params;
4478 add_arg(fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4479 add_arg(fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4480 add_arg(fninfo, ARG_SGPR, ctx->f32); /* depth */
4481
4482 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4483 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color0 */
4484 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color1 */
4485 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color2 */
4486 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color3 */
4487 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4488 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4489 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4490 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4491 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4492 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4493 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4494 }
4495 }
4496
4497 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4498 struct si_function_info *fninfo)
4499 {
4500 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4501 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4502 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4503 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
4504 }
4505
4506 enum {
4507 /* Convenient merged shader definitions. */
4508 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4509 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4510 };
4511
4512 static void create_function(struct si_shader_context *ctx)
4513 {
4514 struct si_shader *shader = ctx->shader;
4515 struct si_function_info fninfo;
4516 LLVMTypeRef returns[16+32*4];
4517 unsigned i, num_return_sgprs;
4518 unsigned num_returns = 0;
4519 unsigned num_prolog_vgprs = 0;
4520 unsigned type = ctx->type;
4521 unsigned vs_blit_property =
4522 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4523
4524 si_init_function_info(&fninfo);
4525
4526 /* Set MERGED shaders. */
4527 if (ctx->screen->info.chip_class >= GFX9) {
4528 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4529 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4530 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4531 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4532 }
4533
4534 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4535
4536 switch (type) {
4537 case PIPE_SHADER_VERTEX:
4538 declare_global_desc_pointers(ctx, &fninfo);
4539
4540 if (vs_blit_property) {
4541 declare_vs_blit_inputs(ctx, &fninfo, vs_blit_property);
4542
4543 /* VGPRs */
4544 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4545 break;
4546 }
4547
4548 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4549 declare_vs_specific_input_sgprs(ctx, &fninfo);
4550 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4551 ac_array_in_const32_addr_space(ctx->v4i32));
4552
4553 if (shader->key.as_es) {
4554 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4555 } else if (shader->key.as_ls) {
4556 /* no extra parameters */
4557 } else {
4558 if (shader->is_gs_copy_shader) {
4559 fninfo.num_params = ctx->param_vs_state_bits + 1;
4560 fninfo.num_sgpr_params = fninfo.num_params;
4561 }
4562
4563 /* The locations of the other parameters are assigned dynamically. */
4564 declare_streamout_params(ctx, &shader->selector->so,
4565 &fninfo);
4566 }
4567
4568 /* VGPRs */
4569 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4570
4571 /* Return values */
4572 if (shader->key.opt.vs_as_prim_discard_cs) {
4573 for (i = 0; i < 4; i++)
4574 returns[num_returns++] = ctx->f32; /* VGPRs */
4575 }
4576 break;
4577
4578 case PIPE_SHADER_TESS_CTRL: /* GFX6-GFX8 */
4579 declare_global_desc_pointers(ctx, &fninfo);
4580 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4581 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4582 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4583 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4584 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4585 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4586 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4587
4588 /* VGPRs */
4589 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4590 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4591
4592 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4593 * placed after the user SGPRs.
4594 */
4595 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4596 returns[num_returns++] = ctx->i32; /* SGPRs */
4597 for (i = 0; i < 11; i++)
4598 returns[num_returns++] = ctx->f32; /* VGPRs */
4599 break;
4600
4601 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4602 /* Merged stages have 8 system SGPRs at the beginning. */
4603 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
4604 declare_per_stage_desc_pointers(ctx, &fninfo,
4605 ctx->type == PIPE_SHADER_TESS_CTRL);
4606 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4607 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4608 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4609 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4610 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4611 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4612
4613 declare_global_desc_pointers(ctx, &fninfo);
4614 declare_per_stage_desc_pointers(ctx, &fninfo,
4615 ctx->type == PIPE_SHADER_VERTEX);
4616 declare_vs_specific_input_sgprs(ctx, &fninfo);
4617
4618 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4619 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4620 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4621 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4622 ac_array_in_const32_addr_space(ctx->v4i32));
4623
4624 /* VGPRs (first TCS, then VS) */
4625 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4626 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4627
4628 if (ctx->type == PIPE_SHADER_VERTEX) {
4629 declare_vs_input_vgprs(ctx, &fninfo,
4630 &num_prolog_vgprs);
4631
4632 /* LS return values are inputs to the TCS main shader part. */
4633 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4634 returns[num_returns++] = ctx->i32; /* SGPRs */
4635 for (i = 0; i < 2; i++)
4636 returns[num_returns++] = ctx->f32; /* VGPRs */
4637 } else {
4638 /* TCS return values are inputs to the TCS epilog.
4639 *
4640 * param_tcs_offchip_offset, param_tcs_factor_offset,
4641 * param_tcs_offchip_layout, and param_rw_buffers
4642 * should be passed to the epilog.
4643 */
4644 for (i = 0; i <= 8 + GFX9_SGPR_TCS_OUT_LAYOUT; i++)
4645 returns[num_returns++] = ctx->i32; /* SGPRs */
4646 for (i = 0; i < 11; i++)
4647 returns[num_returns++] = ctx->f32; /* VGPRs */
4648 }
4649 break;
4650
4651 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4652 /* Merged stages have 8 system SGPRs at the beginning. */
4653 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
4654 declare_per_stage_desc_pointers(ctx, &fninfo,
4655 ctx->type == PIPE_SHADER_GEOMETRY);
4656 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4657 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4658 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4659 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4660 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4661 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4662
4663 declare_global_desc_pointers(ctx, &fninfo);
4664 declare_per_stage_desc_pointers(ctx, &fninfo,
4665 (ctx->type == PIPE_SHADER_VERTEX ||
4666 ctx->type == PIPE_SHADER_TESS_EVAL));
4667 if (ctx->type == PIPE_SHADER_VERTEX) {
4668 declare_vs_specific_input_sgprs(ctx, &fninfo);
4669 } else {
4670 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4671 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4672 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4673 /* Declare as many input SGPRs as the VS has. */
4674 }
4675
4676 if (ctx->type == PIPE_SHADER_VERTEX) {
4677 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4678 ac_array_in_const32_addr_space(ctx->v4i32));
4679 }
4680
4681 /* VGPRs (first GS, then VS/TES) */
4682 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4683 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4684 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4685 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4686 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4687
4688 if (ctx->type == PIPE_SHADER_VERTEX) {
4689 declare_vs_input_vgprs(ctx, &fninfo,
4690 &num_prolog_vgprs);
4691 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4692 declare_tes_input_vgprs(ctx, &fninfo);
4693 }
4694
4695 if (ctx->type == PIPE_SHADER_VERTEX ||
4696 ctx->type == PIPE_SHADER_TESS_EVAL) {
4697 unsigned num_user_sgprs;
4698
4699 if (ctx->type == PIPE_SHADER_VERTEX)
4700 num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR;
4701 else
4702 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
4703
4704 /* ES return values are inputs to GS. */
4705 for (i = 0; i < 8 + num_user_sgprs; i++)
4706 returns[num_returns++] = ctx->i32; /* SGPRs */
4707 for (i = 0; i < 5; i++)
4708 returns[num_returns++] = ctx->f32; /* VGPRs */
4709 }
4710 break;
4711
4712 case PIPE_SHADER_TESS_EVAL:
4713 declare_global_desc_pointers(ctx, &fninfo);
4714 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4715 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4716 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4717 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4718
4719 if (shader->key.as_es) {
4720 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4721 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4722 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4723 } else {
4724 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4725 declare_streamout_params(ctx, &shader->selector->so,
4726 &fninfo);
4727 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4728 }
4729
4730 /* VGPRs */
4731 declare_tes_input_vgprs(ctx, &fninfo);
4732 break;
4733
4734 case PIPE_SHADER_GEOMETRY:
4735 declare_global_desc_pointers(ctx, &fninfo);
4736 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4737 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4738 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4739
4740 /* VGPRs */
4741 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4742 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4743 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4744 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4745 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4746 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4747 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4748 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4749 break;
4750
4751 case PIPE_SHADER_FRAGMENT:
4752 declare_global_desc_pointers(ctx, &fninfo);
4753 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4754 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4755 add_arg_assign_checked(&fninfo, ARG_SGPR, ctx->i32,
4756 &ctx->abi.prim_mask, SI_PARAM_PRIM_MASK);
4757
4758 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4759 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4760 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4761 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4762 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4763 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4764 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4765 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4766 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4767 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4768 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4769 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4770 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4771 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4772 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4773 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4774 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4775 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4776 shader->info.face_vgpr_index = 20;
4777 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4778 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4779 shader->info.ancillary_vgpr_index = 21;
4780 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4781 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4782 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4783
4784 /* Color inputs from the prolog. */
4785 if (shader->selector->info.colors_read) {
4786 unsigned num_color_elements =
4787 util_bitcount(shader->selector->info.colors_read);
4788
4789 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4790 for (i = 0; i < num_color_elements; i++)
4791 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4792
4793 num_prolog_vgprs += num_color_elements;
4794 }
4795
4796 /* Outputs for the epilog. */
4797 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4798 num_returns =
4799 num_return_sgprs +
4800 util_bitcount(shader->selector->info.colors_written) * 4 +
4801 shader->selector->info.writes_z +
4802 shader->selector->info.writes_stencil +
4803 shader->selector->info.writes_samplemask +
4804 1 /* SampleMaskIn */;
4805
4806 num_returns = MAX2(num_returns,
4807 num_return_sgprs +
4808 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4809
4810 for (i = 0; i < num_return_sgprs; i++)
4811 returns[i] = ctx->i32;
4812 for (; i < num_returns; i++)
4813 returns[i] = ctx->f32;
4814 break;
4815
4816 case PIPE_SHADER_COMPUTE:
4817 declare_global_desc_pointers(ctx, &fninfo);
4818 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4819 if (shader->selector->info.uses_grid_size)
4820 add_arg_assign(&fninfo, ARG_SGPR, v3i32, &ctx->abi.num_work_groups);
4821 if (shader->selector->info.uses_block_size &&
4822 shader->selector->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
4823 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4824
4825 unsigned cs_user_data_dwords =
4826 shader->selector->info.properties[TGSI_PROPERTY_CS_USER_DATA_DWORDS];
4827 if (cs_user_data_dwords) {
4828 ctx->param_cs_user_data = add_arg(&fninfo, ARG_SGPR,
4829 LLVMVectorType(ctx->i32, cs_user_data_dwords));
4830 }
4831
4832 for (i = 0; i < 3; i++) {
4833 ctx->abi.workgroup_ids[i] = NULL;
4834 if (shader->selector->info.uses_block_id[i])
4835 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->abi.workgroup_ids[i]);
4836 }
4837
4838 add_arg_assign(&fninfo, ARG_VGPR, v3i32, &ctx->abi.local_invocation_ids);
4839 break;
4840 default:
4841 assert(0 && "unimplemented shader");
4842 return;
4843 }
4844
4845 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4846 si_get_max_workgroup_size(shader));
4847
4848 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4849 if (ctx->type == PIPE_SHADER_FRAGMENT && !ctx->shader->is_monolithic) {
4850 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4851 "InitialPSInputAddr",
4852 S_0286D0_PERSP_SAMPLE_ENA(1) |
4853 S_0286D0_PERSP_CENTER_ENA(1) |
4854 S_0286D0_PERSP_CENTROID_ENA(1) |
4855 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4856 S_0286D0_LINEAR_CENTER_ENA(1) |
4857 S_0286D0_LINEAR_CENTROID_ENA(1) |
4858 S_0286D0_FRONT_FACE_ENA(1) |
4859 S_0286D0_ANCILLARY_ENA(1) |
4860 S_0286D0_POS_FIXED_PT_ENA(1));
4861 }
4862
4863 shader->info.num_input_sgprs = 0;
4864 shader->info.num_input_vgprs = 0;
4865
4866 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4867 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
4868
4869 for (; i < fninfo.num_params; ++i)
4870 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
4871
4872 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4873 shader->info.num_input_vgprs -= num_prolog_vgprs;
4874
4875 if (shader->key.as_ls ||
4876 ctx->type == PIPE_SHADER_TESS_CTRL ||
4877 /* GFX9 has the ESGS ring buffer in LDS. */
4878 type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY)
4879 ac_declare_lds_as_pointer(&ctx->ac);
4880 }
4881
4882 /**
4883 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4884 * for later use.
4885 */
4886 static void preload_ring_buffers(struct si_shader_context *ctx)
4887 {
4888 LLVMBuilderRef builder = ctx->ac.builder;
4889
4890 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
4891 ctx->param_rw_buffers);
4892
4893 if (ctx->screen->info.chip_class <= GFX8 &&
4894 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
4895 unsigned ring =
4896 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
4897 : SI_ES_RING_ESGS;
4898 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
4899
4900 ctx->esgs_ring =
4901 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4902 }
4903
4904 if (ctx->shader->is_gs_copy_shader) {
4905 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4906
4907 ctx->gsvs_ring[0] =
4908 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4909 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
4910 const struct si_shader_selector *sel = ctx->shader->selector;
4911 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4912 LLVMValueRef base_ring;
4913
4914 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4915
4916 /* The conceptual layout of the GSVS ring is
4917 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4918 * but the real memory layout is swizzled across
4919 * threads:
4920 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4921 * t16v0c0 ..
4922 * Override the buffer descriptor accordingly.
4923 */
4924 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
4925 uint64_t stream_offset = 0;
4926
4927 for (unsigned stream = 0; stream < 4; ++stream) {
4928 unsigned num_components;
4929 unsigned stride;
4930 unsigned num_records;
4931 LLVMValueRef ring, tmp;
4932
4933 num_components = sel->info.num_stream_output_components[stream];
4934 if (!num_components)
4935 continue;
4936
4937 stride = 4 * num_components * sel->gs_max_out_vertices;
4938
4939 /* Limit on the stride field for <= GFX7. */
4940 assert(stride < (1 << 14));
4941
4942 num_records = 64;
4943
4944 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
4945 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
4946 tmp = LLVMBuildAdd(builder, tmp,
4947 LLVMConstInt(ctx->i64,
4948 stream_offset, 0), "");
4949 stream_offset += stride * 64;
4950
4951 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
4952 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
4953 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
4954 tmp = LLVMBuildOr(builder, tmp,
4955 LLVMConstInt(ctx->i32,
4956 S_008F04_STRIDE(stride) |
4957 S_008F04_SWIZZLE_ENABLE(1), 0), "");
4958 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
4959 ring = LLVMBuildInsertElement(builder, ring,
4960 LLVMConstInt(ctx->i32, num_records, 0),
4961 LLVMConstInt(ctx->i32, 2, 0), "");
4962 ring = LLVMBuildInsertElement(builder, ring,
4963 LLVMConstInt(ctx->i32,
4964 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4965 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4966 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4967 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
4968 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4969 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
4970 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
4971 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
4972 S_008F0C_ADD_TID_ENABLE(1),
4973 0),
4974 LLVMConstInt(ctx->i32, 3, 0), "");
4975
4976 ctx->gsvs_ring[stream] = ring;
4977 }
4978 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4979 ctx->tess_offchip_ring = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TES);
4980 }
4981 }
4982
4983 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
4984 LLVMValueRef param_rw_buffers,
4985 unsigned param_pos_fixed_pt)
4986 {
4987 LLVMBuilderRef builder = ctx->ac.builder;
4988 LLVMValueRef slot, desc, offset, row, bit, address[2];
4989
4990 /* Use the fixed-point gl_FragCoord input.
4991 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
4992 * per coordinate to get the repeating effect.
4993 */
4994 address[0] = si_unpack_param(ctx, param_pos_fixed_pt, 0, 5);
4995 address[1] = si_unpack_param(ctx, param_pos_fixed_pt, 16, 5);
4996
4997 /* Load the buffer descriptor. */
4998 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
4999 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
5000
5001 /* The stipple pattern is 32x32, each row has 32 bits. */
5002 offset = LLVMBuildMul(builder, address[1],
5003 LLVMConstInt(ctx->i32, 4, 0), "");
5004 row = buffer_load_const(ctx, desc, offset);
5005 row = ac_to_integer(&ctx->ac, row);
5006 bit = LLVMBuildLShr(builder, row, address[0], "");
5007 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5008 ac_build_kill_if_false(&ctx->ac, bit);
5009 }
5010
5011 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5012 struct si_shader_config *conf,
5013 unsigned symbol_offset)
5014 {
5015 unsigned i;
5016 const unsigned char *config =
5017 ac_shader_binary_config_start(binary, symbol_offset);
5018 bool really_needs_scratch = false;
5019
5020 /* LLVM adds SGPR spills to the scratch size.
5021 * Find out if we really need the scratch buffer.
5022 */
5023 for (i = 0; i < binary->reloc_count; i++) {
5024 const struct ac_shader_reloc *reloc = &binary->relocs[i];
5025
5026 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5027 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5028 really_needs_scratch = true;
5029 break;
5030 }
5031 }
5032
5033 /* XXX: We may be able to emit some of these values directly rather than
5034 * extracting fields to be emitted later.
5035 */
5036
5037 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5038 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5039 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5040 switch (reg) {
5041 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5042 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5043 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5044 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
5045 case R_00B848_COMPUTE_PGM_RSRC1:
5046 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5047 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5048 conf->float_mode = G_00B028_FLOAT_MODE(value);
5049 conf->rsrc1 = value;
5050 break;
5051 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5052 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5053 break;
5054 case R_00B84C_COMPUTE_PGM_RSRC2:
5055 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5056 conf->rsrc2 = value;
5057 break;
5058 case R_0286CC_SPI_PS_INPUT_ENA:
5059 conf->spi_ps_input_ena = value;
5060 break;
5061 case R_0286D0_SPI_PS_INPUT_ADDR:
5062 conf->spi_ps_input_addr = value;
5063 break;
5064 case R_0286E8_SPI_TMPRING_SIZE:
5065 case R_00B860_COMPUTE_TMPRING_SIZE:
5066 /* WAVESIZE is in units of 256 dwords. */
5067 if (really_needs_scratch)
5068 conf->scratch_bytes_per_wave =
5069 G_00B860_WAVESIZE(value) * 256 * 4;
5070 break;
5071 case 0x4: /* SPILLED_SGPRS */
5072 conf->spilled_sgprs = value;
5073 break;
5074 case 0x8: /* SPILLED_VGPRS */
5075 conf->spilled_vgprs = value;
5076 break;
5077 default:
5078 {
5079 static bool printed;
5080
5081 if (!printed) {
5082 fprintf(stderr, "Warning: LLVM emitted unknown "
5083 "config register: 0x%x\n", reg);
5084 printed = true;
5085 }
5086 }
5087 break;
5088 }
5089 }
5090
5091 if (!conf->spi_ps_input_addr)
5092 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5093 }
5094
5095 void si_shader_apply_scratch_relocs(struct si_shader *shader,
5096 uint64_t scratch_va)
5097 {
5098 unsigned i;
5099 uint32_t scratch_rsrc_dword0 = scratch_va;
5100 uint32_t scratch_rsrc_dword1 =
5101 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5102
5103 /* Enable scratch coalescing. */
5104 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5105
5106 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5107 const struct ac_shader_reloc *reloc =
5108 &shader->binary.relocs[i];
5109 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5110 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5111 &scratch_rsrc_dword0, 4);
5112 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5113 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5114 &scratch_rsrc_dword1, 4);
5115 }
5116 }
5117 }
5118
5119 /* For the UMR disassembler. */
5120 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
5121 #define DEBUGGER_NUM_MARKERS 5
5122
5123 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
5124 {
5125 unsigned size = shader->binary.code_size;
5126
5127 if (shader->prolog)
5128 size += shader->prolog->binary.code_size;
5129 if (shader->previous_stage)
5130 size += shader->previous_stage->binary.code_size;
5131 if (shader->prolog2)
5132 size += shader->prolog2->binary.code_size;
5133 if (shader->epilog)
5134 size += shader->epilog->binary.code_size;
5135 return size + DEBUGGER_NUM_MARKERS * 4;
5136 }
5137
5138 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5139 {
5140 const struct ac_shader_binary *prolog =
5141 shader->prolog ? &shader->prolog->binary : NULL;
5142 const struct ac_shader_binary *previous_stage =
5143 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5144 const struct ac_shader_binary *prolog2 =
5145 shader->prolog2 ? &shader->prolog2->binary : NULL;
5146 const struct ac_shader_binary *epilog =
5147 shader->epilog ? &shader->epilog->binary : NULL;
5148 const struct ac_shader_binary *mainb = &shader->binary;
5149 unsigned bo_size = si_get_shader_binary_size(shader) +
5150 (!epilog ? mainb->rodata_size : 0);
5151 unsigned char *ptr;
5152
5153 assert(!prolog || !prolog->rodata_size);
5154 assert(!previous_stage || !previous_stage->rodata_size);
5155 assert(!prolog2 || !prolog2->rodata_size);
5156 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5157 !mainb->rodata_size);
5158 assert(!epilog || !epilog->rodata_size);
5159
5160 si_resource_reference(&shader->bo, NULL);
5161 shader->bo = si_aligned_buffer_create(&sscreen->b,
5162 sscreen->cpdma_prefetch_writes_memory ?
5163 0 : SI_RESOURCE_FLAG_READ_ONLY,
5164 PIPE_USAGE_IMMUTABLE,
5165 align(bo_size, SI_CPDMA_ALIGNMENT),
5166 256);
5167 if (!shader->bo)
5168 return -ENOMEM;
5169
5170 /* Upload. */
5171 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5172 PIPE_TRANSFER_READ_WRITE |
5173 PIPE_TRANSFER_UNSYNCHRONIZED |
5174 RADEON_TRANSFER_TEMPORARY);
5175
5176 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5177 * endian-independent. */
5178 if (prolog) {
5179 memcpy(ptr, prolog->code, prolog->code_size);
5180 ptr += prolog->code_size;
5181 }
5182 if (previous_stage) {
5183 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5184 ptr += previous_stage->code_size;
5185 }
5186 if (prolog2) {
5187 memcpy(ptr, prolog2->code, prolog2->code_size);
5188 ptr += prolog2->code_size;
5189 }
5190
5191 memcpy(ptr, mainb->code, mainb->code_size);
5192 ptr += mainb->code_size;
5193
5194 if (epilog) {
5195 memcpy(ptr, epilog->code, epilog->code_size);
5196 ptr += epilog->code_size;
5197 } else if (mainb->rodata_size > 0) {
5198 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5199 ptr += mainb->rodata_size;
5200 }
5201
5202 /* Add end-of-code markers for the UMR disassembler. */
5203 uint32_t *ptr32 = (uint32_t*)ptr;
5204 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
5205 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
5206
5207 sscreen->ws->buffer_unmap(shader->bo->buf);
5208 return 0;
5209 }
5210
5211 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5212 struct pipe_debug_callback *debug,
5213 const char *name, FILE *file)
5214 {
5215 char *line, *p;
5216 unsigned i, count;
5217
5218 if (binary->disasm_string) {
5219 fprintf(file, "Shader %s disassembly:\n", name);
5220 fprintf(file, "%s", binary->disasm_string);
5221
5222 if (debug && debug->debug_message) {
5223 /* Very long debug messages are cut off, so send the
5224 * disassembly one line at a time. This causes more
5225 * overhead, but on the plus side it simplifies
5226 * parsing of resulting logs.
5227 */
5228 pipe_debug_message(debug, SHADER_INFO,
5229 "Shader Disassembly Begin");
5230
5231 line = binary->disasm_string;
5232 while (*line) {
5233 p = util_strchrnul(line, '\n');
5234 count = p - line;
5235
5236 if (count) {
5237 pipe_debug_message(debug, SHADER_INFO,
5238 "%.*s", count, line);
5239 }
5240
5241 if (!*p)
5242 break;
5243 line = p + 1;
5244 }
5245
5246 pipe_debug_message(debug, SHADER_INFO,
5247 "Shader Disassembly End");
5248 }
5249 } else {
5250 fprintf(file, "Shader %s binary:\n", name);
5251 for (i = 0; i < binary->code_size; i += 4) {
5252 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5253 binary->code[i + 3], binary->code[i + 2],
5254 binary->code[i + 1], binary->code[i]);
5255 }
5256 }
5257 }
5258
5259 static void si_calculate_max_simd_waves(struct si_shader *shader)
5260 {
5261 struct si_screen *sscreen = shader->selector->screen;
5262 struct si_shader_config *conf = &shader->config;
5263 unsigned num_inputs = shader->selector->info.num_inputs;
5264 unsigned lds_increment = sscreen->info.chip_class >= GFX7 ? 512 : 256;
5265 unsigned lds_per_wave = 0;
5266 unsigned max_simd_waves;
5267
5268 max_simd_waves = ac_get_max_simd_waves(sscreen->info.family);
5269
5270 /* Compute LDS usage for PS. */
5271 switch (shader->selector->type) {
5272 case PIPE_SHADER_FRAGMENT:
5273 /* The minimum usage per wave is (num_inputs * 48). The maximum
5274 * usage is (num_inputs * 48 * 16).
5275 * We can get anything in between and it varies between waves.
5276 *
5277 * The 48 bytes per input for a single primitive is equal to
5278 * 4 bytes/component * 4 components/input * 3 points.
5279 *
5280 * Other stages don't know the size at compile time or don't
5281 * allocate LDS per wave, but instead they do it per thread group.
5282 */
5283 lds_per_wave = conf->lds_size * lds_increment +
5284 align(num_inputs * 48, lds_increment);
5285 break;
5286 case PIPE_SHADER_COMPUTE:
5287 if (shader->selector) {
5288 unsigned max_workgroup_size =
5289 si_get_max_workgroup_size(shader);
5290 lds_per_wave = (conf->lds_size * lds_increment) /
5291 DIV_ROUND_UP(max_workgroup_size, 64);
5292 }
5293 break;
5294 }
5295
5296 /* Compute the per-SIMD wave counts. */
5297 if (conf->num_sgprs) {
5298 max_simd_waves =
5299 MIN2(max_simd_waves,
5300 ac_get_num_physical_sgprs(sscreen->info.chip_class) / conf->num_sgprs);
5301 }
5302
5303 if (conf->num_vgprs)
5304 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5305
5306 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5307 * 16KB makes some SIMDs unoccupied). */
5308 if (lds_per_wave)
5309 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5310
5311 conf->max_simd_waves = max_simd_waves;
5312 }
5313
5314 void si_shader_dump_stats_for_shader_db(const struct si_shader *shader,
5315 struct pipe_debug_callback *debug)
5316 {
5317 const struct si_shader_config *conf = &shader->config;
5318
5319 pipe_debug_message(debug, SHADER_INFO,
5320 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5321 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5322 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5323 conf->num_sgprs, conf->num_vgprs,
5324 si_get_shader_binary_size(shader),
5325 conf->lds_size, conf->scratch_bytes_per_wave,
5326 conf->max_simd_waves, conf->spilled_sgprs,
5327 conf->spilled_vgprs, conf->private_mem_vgprs);
5328 }
5329
5330 static void si_shader_dump_stats(struct si_screen *sscreen,
5331 const struct si_shader *shader,
5332 unsigned processor,
5333 FILE *file,
5334 bool check_debug_option)
5335 {
5336 const struct si_shader_config *conf = &shader->config;
5337
5338 if (!check_debug_option ||
5339 si_can_dump_shader(sscreen, processor)) {
5340 if (processor == PIPE_SHADER_FRAGMENT) {
5341 fprintf(file, "*** SHADER CONFIG ***\n"
5342 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5343 "SPI_PS_INPUT_ENA = 0x%04x\n",
5344 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5345 }
5346
5347 fprintf(file, "*** SHADER STATS ***\n"
5348 "SGPRS: %d\n"
5349 "VGPRS: %d\n"
5350 "Spilled SGPRs: %d\n"
5351 "Spilled VGPRs: %d\n"
5352 "Private memory VGPRs: %d\n"
5353 "Code Size: %d bytes\n"
5354 "LDS: %d blocks\n"
5355 "Scratch: %d bytes per wave\n"
5356 "Max Waves: %d\n"
5357 "********************\n\n\n",
5358 conf->num_sgprs, conf->num_vgprs,
5359 conf->spilled_sgprs, conf->spilled_vgprs,
5360 conf->private_mem_vgprs,
5361 si_get_shader_binary_size(shader),
5362 conf->lds_size, conf->scratch_bytes_per_wave,
5363 conf->max_simd_waves);
5364 }
5365 }
5366
5367 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5368 {
5369 switch (processor) {
5370 case PIPE_SHADER_VERTEX:
5371 if (shader->key.as_es)
5372 return "Vertex Shader as ES";
5373 else if (shader->key.as_ls)
5374 return "Vertex Shader as LS";
5375 else if (shader->key.opt.vs_as_prim_discard_cs)
5376 return "Vertex Shader as Primitive Discard CS";
5377 else
5378 return "Vertex Shader as VS";
5379 case PIPE_SHADER_TESS_CTRL:
5380 return "Tessellation Control Shader";
5381 case PIPE_SHADER_TESS_EVAL:
5382 if (shader->key.as_es)
5383 return "Tessellation Evaluation Shader as ES";
5384 else
5385 return "Tessellation Evaluation Shader as VS";
5386 case PIPE_SHADER_GEOMETRY:
5387 if (shader->is_gs_copy_shader)
5388 return "GS Copy Shader as VS";
5389 else
5390 return "Geometry Shader";
5391 case PIPE_SHADER_FRAGMENT:
5392 return "Pixel Shader";
5393 case PIPE_SHADER_COMPUTE:
5394 return "Compute Shader";
5395 default:
5396 return "Unknown Shader";
5397 }
5398 }
5399
5400 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5401 struct pipe_debug_callback *debug, unsigned processor,
5402 FILE *file, bool check_debug_option)
5403 {
5404 if (!check_debug_option ||
5405 si_can_dump_shader(sscreen, processor))
5406 si_dump_shader_key(processor, shader, file);
5407
5408 if (!check_debug_option && shader->binary.llvm_ir_string) {
5409 if (shader->previous_stage &&
5410 shader->previous_stage->binary.llvm_ir_string) {
5411 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5412 si_get_shader_name(shader, processor));
5413 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5414 }
5415
5416 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5417 si_get_shader_name(shader, processor));
5418 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5419 }
5420
5421 if (!check_debug_option ||
5422 (si_can_dump_shader(sscreen, processor) &&
5423 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5424 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5425
5426 if (shader->prolog)
5427 si_shader_dump_disassembly(&shader->prolog->binary,
5428 debug, "prolog", file);
5429 if (shader->previous_stage)
5430 si_shader_dump_disassembly(&shader->previous_stage->binary,
5431 debug, "previous stage", file);
5432 if (shader->prolog2)
5433 si_shader_dump_disassembly(&shader->prolog2->binary,
5434 debug, "prolog2", file);
5435
5436 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5437
5438 if (shader->epilog)
5439 si_shader_dump_disassembly(&shader->epilog->binary,
5440 debug, "epilog", file);
5441 fprintf(file, "\n");
5442 }
5443
5444 si_shader_dump_stats(sscreen, shader, processor, file,
5445 check_debug_option);
5446 }
5447
5448 static int si_compile_llvm(struct si_screen *sscreen,
5449 struct ac_shader_binary *binary,
5450 struct si_shader_config *conf,
5451 struct ac_llvm_compiler *compiler,
5452 LLVMModuleRef mod,
5453 struct pipe_debug_callback *debug,
5454 unsigned processor,
5455 const char *name,
5456 bool less_optimized)
5457 {
5458 int r = 0;
5459 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5460
5461 if (si_can_dump_shader(sscreen, processor)) {
5462 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5463
5464 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5465 fprintf(stderr, "%s LLVM IR:\n\n", name);
5466 ac_dump_module(mod);
5467 fprintf(stderr, "\n");
5468 }
5469 }
5470
5471 if (sscreen->record_llvm_ir) {
5472 char *ir = LLVMPrintModuleToString(mod);
5473 binary->llvm_ir_string = strdup(ir);
5474 LLVMDisposeMessage(ir);
5475 }
5476
5477 if (!si_replace_shader(count, binary)) {
5478 r = si_llvm_compile(mod, binary, compiler, debug,
5479 less_optimized);
5480 if (r)
5481 return r;
5482 }
5483
5484 si_shader_binary_read_config(binary, conf, 0);
5485
5486 /* Enable 64-bit and 16-bit denormals, because there is no performance
5487 * cost.
5488 *
5489 * If denormals are enabled, all floating-point output modifiers are
5490 * ignored.
5491 *
5492 * Don't enable denormals for 32-bit floats, because:
5493 * - Floating-point output modifiers would be ignored by the hw.
5494 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5495 * have to stop using those.
5496 * - GFX6 & GFX7 would be very slow.
5497 */
5498 conf->float_mode |= V_00B028_FP_64_DENORMS;
5499
5500 FREE(binary->config);
5501 FREE(binary->global_symbol_offsets);
5502 binary->config = NULL;
5503 binary->global_symbol_offsets = NULL;
5504
5505 /* Some shaders can't have rodata because their binaries can be
5506 * concatenated.
5507 */
5508 if (binary->rodata_size &&
5509 (processor == PIPE_SHADER_VERTEX ||
5510 processor == PIPE_SHADER_TESS_CTRL ||
5511 processor == PIPE_SHADER_TESS_EVAL ||
5512 processor == PIPE_SHADER_FRAGMENT)) {
5513 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5514 return -EINVAL;
5515 }
5516
5517 return r;
5518 }
5519
5520 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5521 {
5522 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5523 LLVMBuildRetVoid(ctx->ac.builder);
5524 else
5525 LLVMBuildRet(ctx->ac.builder, ret);
5526 }
5527
5528 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5529 struct si_shader *
5530 si_generate_gs_copy_shader(struct si_screen *sscreen,
5531 struct ac_llvm_compiler *compiler,
5532 struct si_shader_selector *gs_selector,
5533 struct pipe_debug_callback *debug)
5534 {
5535 struct si_shader_context ctx;
5536 struct si_shader *shader;
5537 LLVMBuilderRef builder;
5538 struct si_shader_output_values outputs[SI_MAX_VS_OUTPUTS];
5539 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5540 int i, r;
5541
5542
5543 shader = CALLOC_STRUCT(si_shader);
5544 if (!shader)
5545 return NULL;
5546
5547 /* We can leave the fence as permanently signaled because the GS copy
5548 * shader only becomes visible globally after it has been compiled. */
5549 util_queue_fence_init(&shader->ready);
5550
5551 shader->selector = gs_selector;
5552 shader->is_gs_copy_shader = true;
5553
5554 si_init_shader_ctx(&ctx, sscreen, compiler);
5555 ctx.shader = shader;
5556 ctx.type = PIPE_SHADER_VERTEX;
5557
5558 builder = ctx.ac.builder;
5559
5560 create_function(&ctx);
5561 preload_ring_buffers(&ctx);
5562
5563 LLVMValueRef voffset =
5564 LLVMBuildMul(ctx.ac.builder, ctx.abi.vertex_id,
5565 LLVMConstInt(ctx.i32, 4, 0), "");
5566
5567 /* Fetch the vertex stream ID.*/
5568 LLVMValueRef stream_id;
5569
5570 if (gs_selector->so.num_outputs)
5571 stream_id = si_unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5572 else
5573 stream_id = ctx.i32_0;
5574
5575 /* Fill in output information. */
5576 for (i = 0; i < gsinfo->num_outputs; ++i) {
5577 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5578 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5579
5580 for (int chan = 0; chan < 4; chan++) {
5581 outputs[i].vertex_stream[chan] =
5582 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5583 }
5584 }
5585
5586 LLVMBasicBlockRef end_bb;
5587 LLVMValueRef switch_inst;
5588
5589 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5590 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5591
5592 for (int stream = 0; stream < 4; stream++) {
5593 LLVMBasicBlockRef bb;
5594 unsigned offset;
5595
5596 if (!gsinfo->num_stream_output_components[stream])
5597 continue;
5598
5599 if (stream > 0 && !gs_selector->so.num_outputs)
5600 continue;
5601
5602 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5603 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5604 LLVMPositionBuilderAtEnd(builder, bb);
5605
5606 /* Fetch vertex data from GSVS ring */
5607 offset = 0;
5608 for (i = 0; i < gsinfo->num_outputs; ++i) {
5609 for (unsigned chan = 0; chan < 4; chan++) {
5610 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5611 outputs[i].vertex_stream[chan] != stream) {
5612 outputs[i].values[chan] = LLVMGetUndef(ctx.f32);
5613 continue;
5614 }
5615
5616 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5617 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5618 offset++;
5619
5620 outputs[i].values[chan] =
5621 ac_build_buffer_load(&ctx.ac,
5622 ctx.gsvs_ring[0], 1,
5623 ctx.i32_0, voffset,
5624 soffset, 0, 1, 1,
5625 true, false);
5626 }
5627 }
5628
5629 /* Streamout and exports. */
5630 if (gs_selector->so.num_outputs) {
5631 si_llvm_emit_streamout(&ctx, outputs,
5632 gsinfo->num_outputs,
5633 stream);
5634 }
5635
5636 if (stream == 0) {
5637 /* Vertex color clamping.
5638 *
5639 * This uses a state constant loaded in a user data SGPR and
5640 * an IF statement is added that clamps all colors if the constant
5641 * is true.
5642 */
5643 struct lp_build_if_state if_ctx;
5644 LLVMValueRef v[2], cond = NULL;
5645 LLVMBasicBlockRef blocks[2];
5646
5647 for (unsigned i = 0; i < gsinfo->num_outputs; i++) {
5648 if (gsinfo->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
5649 gsinfo->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
5650 continue;
5651
5652 /* We've found a color. */
5653 if (!cond) {
5654 /* The state is in the first bit of the user SGPR. */
5655 cond = LLVMGetParam(ctx.main_fn,
5656 ctx.param_vs_state_bits);
5657 cond = LLVMBuildTrunc(ctx.ac.builder, cond,
5658 ctx.i1, "");
5659 lp_build_if(&if_ctx, &ctx.gallivm, cond);
5660 /* Remember blocks for Phi. */
5661 blocks[0] = if_ctx.true_block;
5662 blocks[1] = if_ctx.entry_block;
5663 }
5664
5665 for (unsigned j = 0; j < 4; j++) {
5666 /* Insert clamp into the true block. */
5667 v[0] = ac_build_clamp(&ctx.ac, outputs[i].values[j]);
5668 v[1] = outputs[i].values[j];
5669
5670 /* Insert Phi into the endif block. */
5671 LLVMPositionBuilderAtEnd(ctx.ac.builder, if_ctx.merge_block);
5672 outputs[i].values[j] = ac_build_phi(&ctx.ac, ctx.f32, 2, v, blocks);
5673 LLVMPositionBuilderAtEnd(ctx.ac.builder, if_ctx.true_block);
5674 }
5675 }
5676 if (cond)
5677 lp_build_endif(&if_ctx);
5678
5679 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5680 }
5681
5682 LLVMBuildBr(builder, end_bb);
5683 }
5684
5685 LLVMPositionBuilderAtEnd(builder, end_bb);
5686
5687 LLVMBuildRetVoid(ctx.ac.builder);
5688
5689 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5690 si_llvm_optimize_module(&ctx);
5691
5692 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5693 &ctx.shader->config, ctx.compiler,
5694 ctx.ac.module,
5695 debug, PIPE_SHADER_GEOMETRY,
5696 "GS Copy Shader", false);
5697 if (!r) {
5698 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5699 fprintf(stderr, "GS Copy Shader:\n");
5700 si_shader_dump(sscreen, ctx.shader, debug,
5701 PIPE_SHADER_GEOMETRY, stderr, true);
5702 r = si_shader_binary_upload(sscreen, ctx.shader);
5703 }
5704
5705 si_llvm_dispose(&ctx);
5706
5707 if (r != 0) {
5708 FREE(shader);
5709 shader = NULL;
5710 } else {
5711 si_fix_resource_usage(sscreen, shader);
5712 }
5713 return shader;
5714 }
5715
5716 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5717 const struct si_vs_prolog_bits *prolog,
5718 const char *prefix, FILE *f)
5719 {
5720 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5721 prefix, prolog->instance_divisor_is_one);
5722 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5723 prefix, prolog->instance_divisor_is_fetched);
5724 fprintf(f, " %s.unpack_instance_id_from_vertex_id = %u\n",
5725 prefix, prolog->unpack_instance_id_from_vertex_id);
5726 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5727 prefix, prolog->ls_vgpr_fix);
5728
5729 fprintf(f, " mono.vs.fetch_opencode = %x\n", key->mono.vs_fetch_opencode);
5730 fprintf(f, " mono.vs.fix_fetch = {");
5731 for (int i = 0; i < SI_MAX_ATTRIBS; i++) {
5732 union si_vs_fix_fetch fix = key->mono.vs_fix_fetch[i];
5733 if (i)
5734 fprintf(f, ", ");
5735 if (!fix.bits)
5736 fprintf(f, "0");
5737 else
5738 fprintf(f, "%u.%u.%u.%u", fix.u.reverse, fix.u.log_size,
5739 fix.u.num_channels_m1, fix.u.format);
5740 }
5741 fprintf(f, "}\n");
5742 }
5743
5744 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5745 FILE *f)
5746 {
5747 const struct si_shader_key *key = &shader->key;
5748
5749 fprintf(f, "SHADER KEY\n");
5750
5751 switch (processor) {
5752 case PIPE_SHADER_VERTEX:
5753 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5754 "part.vs.prolog", f);
5755 fprintf(f, " as_es = %u\n", key->as_es);
5756 fprintf(f, " as_ls = %u\n", key->as_ls);
5757 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5758 key->mono.u.vs_export_prim_id);
5759 fprintf(f, " opt.vs_as_prim_discard_cs = %u\n",
5760 key->opt.vs_as_prim_discard_cs);
5761 fprintf(f, " opt.cs_prim_type = %s\n",
5762 tgsi_primitive_names[key->opt.cs_prim_type]);
5763 fprintf(f, " opt.cs_indexed = %u\n",
5764 key->opt.cs_indexed);
5765 fprintf(f, " opt.cs_instancing = %u\n",
5766 key->opt.cs_instancing);
5767 fprintf(f, " opt.cs_primitive_restart = %u\n",
5768 key->opt.cs_primitive_restart);
5769 fprintf(f, " opt.cs_provoking_vertex_first = %u\n",
5770 key->opt.cs_provoking_vertex_first);
5771 fprintf(f, " opt.cs_need_correct_orientation = %u\n",
5772 key->opt.cs_need_correct_orientation);
5773 fprintf(f, " opt.cs_cull_front = %u\n",
5774 key->opt.cs_cull_front);
5775 fprintf(f, " opt.cs_cull_back = %u\n",
5776 key->opt.cs_cull_back);
5777 fprintf(f, " opt.cs_cull_z = %u\n",
5778 key->opt.cs_cull_z);
5779 fprintf(f, " opt.cs_halfz_clip_space = %u\n",
5780 key->opt.cs_halfz_clip_space);
5781 break;
5782
5783 case PIPE_SHADER_TESS_CTRL:
5784 if (shader->selector->screen->info.chip_class >= GFX9) {
5785 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5786 "part.tcs.ls_prolog", f);
5787 }
5788 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5789 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5790 break;
5791
5792 case PIPE_SHADER_TESS_EVAL:
5793 fprintf(f, " as_es = %u\n", key->as_es);
5794 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5795 key->mono.u.vs_export_prim_id);
5796 break;
5797
5798 case PIPE_SHADER_GEOMETRY:
5799 if (shader->is_gs_copy_shader)
5800 break;
5801
5802 if (shader->selector->screen->info.chip_class >= GFX9 &&
5803 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5804 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5805 "part.gs.vs_prolog", f);
5806 }
5807 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5808 break;
5809
5810 case PIPE_SHADER_COMPUTE:
5811 break;
5812
5813 case PIPE_SHADER_FRAGMENT:
5814 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5815 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5816 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5817 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5818 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5819 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5820 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5821 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5822 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5823 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5824 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5825 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5826 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5827 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5828 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5829 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5830 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5831 break;
5832
5833 default:
5834 assert(0);
5835 }
5836
5837 if ((processor == PIPE_SHADER_GEOMETRY ||
5838 processor == PIPE_SHADER_TESS_EVAL ||
5839 processor == PIPE_SHADER_VERTEX) &&
5840 !key->as_es && !key->as_ls) {
5841 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5842 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5843 }
5844 }
5845
5846 static void si_init_shader_ctx(struct si_shader_context *ctx,
5847 struct si_screen *sscreen,
5848 struct ac_llvm_compiler *compiler)
5849 {
5850 struct lp_build_tgsi_context *bld_base;
5851
5852 si_llvm_context_init(ctx, sscreen, compiler);
5853
5854 bld_base = &ctx->bld_base;
5855 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5856
5857 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID].emit = build_interp_intrinsic;
5858 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE].emit = build_interp_intrinsic;
5859 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET].emit = build_interp_intrinsic;
5860
5861 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5862
5863 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5864
5865 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5866 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5867 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5868 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5869
5870 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5871 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5872 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5873 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5874 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5875 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5876 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5877 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5878
5879 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5880 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_tgsi_emit_primitive;
5881 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5882 }
5883
5884 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5885 {
5886 struct si_shader *shader = ctx->shader;
5887 struct tgsi_shader_info *info = &shader->selector->info;
5888
5889 if ((ctx->type != PIPE_SHADER_VERTEX &&
5890 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5891 shader->key.as_ls ||
5892 shader->key.as_es)
5893 return;
5894
5895 ac_optimize_vs_outputs(&ctx->ac,
5896 ctx->main_fn,
5897 shader->info.vs_output_param_offset,
5898 info->num_outputs,
5899 &shader->info.nr_param_exports);
5900 }
5901
5902 static void si_init_exec_from_input(struct si_shader_context *ctx,
5903 unsigned param, unsigned bitoffset)
5904 {
5905 LLVMValueRef args[] = {
5906 LLVMGetParam(ctx->main_fn, param),
5907 LLVMConstInt(ctx->i32, bitoffset, 0),
5908 };
5909 ac_build_intrinsic(&ctx->ac,
5910 "llvm.amdgcn.init.exec.from.input",
5911 ctx->voidt, args, 2, AC_FUNC_ATTR_CONVERGENT);
5912 }
5913
5914 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
5915 const struct si_vs_prolog_bits *key)
5916 {
5917 /* VGPR initialization fixup for Vega10 and Raven is always done in the
5918 * VS prolog. */
5919 return sel->vs_needs_prolog || key->ls_vgpr_fix;
5920 }
5921
5922 static bool si_compile_tgsi_main(struct si_shader_context *ctx)
5923 {
5924 struct si_shader *shader = ctx->shader;
5925 struct si_shader_selector *sel = shader->selector;
5926 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5927
5928 // TODO clean all this up!
5929 switch (ctx->type) {
5930 case PIPE_SHADER_VERTEX:
5931 ctx->load_input = declare_input_vs;
5932 if (shader->key.as_ls)
5933 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
5934 else if (shader->key.as_es)
5935 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5936 else if (shader->key.opt.vs_as_prim_discard_cs)
5937 ctx->abi.emit_outputs = si_llvm_emit_prim_discard_cs_epilogue;
5938 else
5939 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5940 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5941 ctx->abi.load_base_vertex = get_base_vertex;
5942 break;
5943 case PIPE_SHADER_TESS_CTRL:
5944 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5945 ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
5946 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5947 bld_base->emit_store = store_output_tcs;
5948 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
5949 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
5950 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
5951 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5952 break;
5953 case PIPE_SHADER_TESS_EVAL:
5954 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
5955 ctx->abi.load_tess_varyings = si_nir_load_input_tes;
5956 ctx->abi.load_tess_coord = si_load_tess_coord;
5957 ctx->abi.load_tess_level = si_load_tess_level;
5958 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
5959 if (shader->key.as_es)
5960 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5961 else
5962 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5963 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5964 break;
5965 case PIPE_SHADER_GEOMETRY:
5966 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
5967 ctx->abi.load_inputs = si_nir_load_input_gs;
5968 ctx->abi.emit_vertex = si_llvm_emit_vertex;
5969 ctx->abi.emit_primitive = si_llvm_emit_primitive;
5970 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
5971 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
5972 break;
5973 case PIPE_SHADER_FRAGMENT:
5974 ctx->load_input = declare_input_fs;
5975 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
5976 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5977 ctx->abi.lookup_interp_param = si_nir_lookup_interp_param;
5978 ctx->abi.load_sample_position = load_sample_position;
5979 ctx->abi.load_sample_mask_in = load_sample_mask_in;
5980 ctx->abi.emit_kill = si_llvm_emit_kill;
5981 break;
5982 case PIPE_SHADER_COMPUTE:
5983 ctx->abi.load_local_group_size = get_block_size;
5984 break;
5985 default:
5986 assert(!"Unsupported shader type");
5987 return false;
5988 }
5989
5990 ctx->abi.load_ubo = load_ubo;
5991 ctx->abi.load_ssbo = load_ssbo;
5992
5993 create_function(ctx);
5994 preload_ring_buffers(ctx);
5995
5996 /* For GFX9 merged shaders:
5997 * - Set EXEC for the first shader. If the prolog is present, set
5998 * EXEC there instead.
5999 * - Add a barrier before the second shader.
6000 * - In the second shader, reset EXEC to ~0 and wrap the main part in
6001 * an if-statement. This is required for correctness in geometry
6002 * shaders, to ensure that empty GS waves do not send GS_EMIT and
6003 * GS_CUT messages.
6004 *
6005 * For monolithic merged shaders, the first shader is wrapped in an
6006 * if-block together with its prolog in si_build_wrapper_function.
6007 */
6008 if (ctx->screen->info.chip_class >= GFX9) {
6009 if (!shader->is_monolithic &&
6010 sel->info.num_instructions > 1 && /* not empty shader */
6011 (shader->key.as_es || shader->key.as_ls) &&
6012 (ctx->type == PIPE_SHADER_TESS_EVAL ||
6013 (ctx->type == PIPE_SHADER_VERTEX &&
6014 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
6015 si_init_exec_from_input(ctx,
6016 ctx->param_merged_wave_info, 0);
6017 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6018 ctx->type == PIPE_SHADER_GEOMETRY) {
6019 if (!shader->is_monolithic)
6020 ac_init_exec_full_mask(&ctx->ac);
6021
6022 LLVMValueRef num_threads = si_unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
6023 LLVMValueRef ena =
6024 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
6025 ac_get_thread_id(&ctx->ac), num_threads, "");
6026 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
6027
6028 /* The barrier must execute for all shaders in a
6029 * threadgroup.
6030 *
6031 * Execute the barrier inside the conditional block,
6032 * so that empty waves can jump directly to s_endpgm,
6033 * which will also signal the barrier.
6034 *
6035 * If the shader is TCS and the TCS epilog is present
6036 * and contains a barrier, it will wait there and then
6037 * reach s_endpgm.
6038 */
6039 si_llvm_emit_barrier(NULL, bld_base, NULL);
6040 }
6041 }
6042
6043 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
6044 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
6045 for (unsigned i = 0; i < 6; i++) {
6046 ctx->invoc0_tess_factors[i] =
6047 ac_build_alloca_undef(&ctx->ac, ctx->i32, "");
6048 }
6049 }
6050
6051 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6052 int i;
6053 for (i = 0; i < 4; i++) {
6054 ctx->gs_next_vertex[i] =
6055 ac_build_alloca(&ctx->ac, ctx->i32, "");
6056 }
6057 }
6058
6059 if (sel->force_correct_derivs_after_kill) {
6060 ctx->postponed_kill = ac_build_alloca_undef(&ctx->ac, ctx->i1, "");
6061 /* true = don't kill. */
6062 LLVMBuildStore(ctx->ac.builder, ctx->i1true,
6063 ctx->postponed_kill);
6064 }
6065
6066 if (sel->tokens) {
6067 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6068 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6069 return false;
6070 }
6071 } else {
6072 if (!si_nir_build_llvm(ctx, sel->nir)) {
6073 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
6074 return false;
6075 }
6076 }
6077
6078 si_llvm_build_ret(ctx, ctx->return_value);
6079 return true;
6080 }
6081
6082 /**
6083 * Compute the VS prolog key, which contains all the information needed to
6084 * build the VS prolog function, and set shader->info bits where needed.
6085 *
6086 * \param info Shader info of the vertex shader.
6087 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6088 * \param prolog_key Key of the VS prolog
6089 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6090 * \param key Output shader part key.
6091 */
6092 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
6093 unsigned num_input_sgprs,
6094 const struct si_vs_prolog_bits *prolog_key,
6095 struct si_shader *shader_out,
6096 union si_shader_part_key *key)
6097 {
6098 memset(key, 0, sizeof(*key));
6099 key->vs_prolog.states = *prolog_key;
6100 key->vs_prolog.num_input_sgprs = num_input_sgprs;
6101 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6102 key->vs_prolog.as_ls = shader_out->key.as_ls;
6103 key->vs_prolog.as_es = shader_out->key.as_es;
6104
6105 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
6106 key->vs_prolog.as_ls = 1;
6107 key->vs_prolog.num_merged_next_stage_vgprs = 2;
6108 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
6109 key->vs_prolog.as_es = 1;
6110 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6111 }
6112
6113 /* Enable loading the InstanceID VGPR. */
6114 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
6115
6116 if ((key->vs_prolog.states.instance_divisor_is_one |
6117 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
6118 shader_out->info.uses_instanceid = true;
6119 }
6120
6121 /**
6122 * Compute the PS prolog key, which contains all the information needed to
6123 * build the PS prolog function, and set related bits in shader->config.
6124 */
6125 static void si_get_ps_prolog_key(struct si_shader *shader,
6126 union si_shader_part_key *key,
6127 bool separate_prolog)
6128 {
6129 struct tgsi_shader_info *info = &shader->selector->info;
6130
6131 memset(key, 0, sizeof(*key));
6132 key->ps_prolog.states = shader->key.part.ps.prolog;
6133 key->ps_prolog.colors_read = info->colors_read;
6134 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6135 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6136 key->ps_prolog.wqm = info->uses_derivatives &&
6137 (key->ps_prolog.colors_read ||
6138 key->ps_prolog.states.force_persp_sample_interp ||
6139 key->ps_prolog.states.force_linear_sample_interp ||
6140 key->ps_prolog.states.force_persp_center_interp ||
6141 key->ps_prolog.states.force_linear_center_interp ||
6142 key->ps_prolog.states.bc_optimize_for_persp ||
6143 key->ps_prolog.states.bc_optimize_for_linear);
6144 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
6145
6146 if (info->colors_read) {
6147 unsigned *color = shader->selector->color_attr_index;
6148
6149 if (shader->key.part.ps.prolog.color_two_side) {
6150 /* BCOLORs are stored after the last input. */
6151 key->ps_prolog.num_interp_inputs = info->num_inputs;
6152 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6153 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6154 }
6155
6156 for (unsigned i = 0; i < 2; i++) {
6157 unsigned interp = info->input_interpolate[color[i]];
6158 unsigned location = info->input_interpolate_loc[color[i]];
6159
6160 if (!(info->colors_read & (0xf << i*4)))
6161 continue;
6162
6163 key->ps_prolog.color_attr_index[i] = color[i];
6164
6165 if (shader->key.part.ps.prolog.flatshade_colors &&
6166 interp == TGSI_INTERPOLATE_COLOR)
6167 interp = TGSI_INTERPOLATE_CONSTANT;
6168
6169 switch (interp) {
6170 case TGSI_INTERPOLATE_CONSTANT:
6171 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6172 break;
6173 case TGSI_INTERPOLATE_PERSPECTIVE:
6174 case TGSI_INTERPOLATE_COLOR:
6175 /* Force the interpolation location for colors here. */
6176 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6177 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6178 if (shader->key.part.ps.prolog.force_persp_center_interp)
6179 location = TGSI_INTERPOLATE_LOC_CENTER;
6180
6181 switch (location) {
6182 case TGSI_INTERPOLATE_LOC_SAMPLE:
6183 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6184 shader->config.spi_ps_input_ena |=
6185 S_0286CC_PERSP_SAMPLE_ENA(1);
6186 break;
6187 case TGSI_INTERPOLATE_LOC_CENTER:
6188 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6189 shader->config.spi_ps_input_ena |=
6190 S_0286CC_PERSP_CENTER_ENA(1);
6191 break;
6192 case TGSI_INTERPOLATE_LOC_CENTROID:
6193 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6194 shader->config.spi_ps_input_ena |=
6195 S_0286CC_PERSP_CENTROID_ENA(1);
6196 break;
6197 default:
6198 assert(0);
6199 }
6200 break;
6201 case TGSI_INTERPOLATE_LINEAR:
6202 /* Force the interpolation location for colors here. */
6203 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6204 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6205 if (shader->key.part.ps.prolog.force_linear_center_interp)
6206 location = TGSI_INTERPOLATE_LOC_CENTER;
6207
6208 /* The VGPR assignment for non-monolithic shaders
6209 * works because InitialPSInputAddr is set on the
6210 * main shader and PERSP_PULL_MODEL is never used.
6211 */
6212 switch (location) {
6213 case TGSI_INTERPOLATE_LOC_SAMPLE:
6214 key->ps_prolog.color_interp_vgpr_index[i] =
6215 separate_prolog ? 6 : 9;
6216 shader->config.spi_ps_input_ena |=
6217 S_0286CC_LINEAR_SAMPLE_ENA(1);
6218 break;
6219 case TGSI_INTERPOLATE_LOC_CENTER:
6220 key->ps_prolog.color_interp_vgpr_index[i] =
6221 separate_prolog ? 8 : 11;
6222 shader->config.spi_ps_input_ena |=
6223 S_0286CC_LINEAR_CENTER_ENA(1);
6224 break;
6225 case TGSI_INTERPOLATE_LOC_CENTROID:
6226 key->ps_prolog.color_interp_vgpr_index[i] =
6227 separate_prolog ? 10 : 13;
6228 shader->config.spi_ps_input_ena |=
6229 S_0286CC_LINEAR_CENTROID_ENA(1);
6230 break;
6231 default:
6232 assert(0);
6233 }
6234 break;
6235 default:
6236 assert(0);
6237 }
6238 }
6239 }
6240 }
6241
6242 /**
6243 * Check whether a PS prolog is required based on the key.
6244 */
6245 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6246 {
6247 return key->ps_prolog.colors_read ||
6248 key->ps_prolog.states.force_persp_sample_interp ||
6249 key->ps_prolog.states.force_linear_sample_interp ||
6250 key->ps_prolog.states.force_persp_center_interp ||
6251 key->ps_prolog.states.force_linear_center_interp ||
6252 key->ps_prolog.states.bc_optimize_for_persp ||
6253 key->ps_prolog.states.bc_optimize_for_linear ||
6254 key->ps_prolog.states.poly_stipple ||
6255 key->ps_prolog.states.samplemask_log_ps_iter;
6256 }
6257
6258 /**
6259 * Compute the PS epilog key, which contains all the information needed to
6260 * build the PS epilog function.
6261 */
6262 static void si_get_ps_epilog_key(struct si_shader *shader,
6263 union si_shader_part_key *key)
6264 {
6265 struct tgsi_shader_info *info = &shader->selector->info;
6266 memset(key, 0, sizeof(*key));
6267 key->ps_epilog.colors_written = info->colors_written;
6268 key->ps_epilog.writes_z = info->writes_z;
6269 key->ps_epilog.writes_stencil = info->writes_stencil;
6270 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6271 key->ps_epilog.states = shader->key.part.ps.epilog;
6272 }
6273
6274 /**
6275 * Build the GS prolog function. Rotate the input vertices for triangle strips
6276 * with adjacency.
6277 */
6278 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6279 union si_shader_part_key *key)
6280 {
6281 unsigned num_sgprs, num_vgprs;
6282 struct si_function_info fninfo;
6283 LLVMBuilderRef builder = ctx->ac.builder;
6284 LLVMTypeRef returns[48];
6285 LLVMValueRef func, ret;
6286
6287 si_init_function_info(&fninfo);
6288
6289 if (ctx->screen->info.chip_class >= GFX9) {
6290 if (key->gs_prolog.states.gfx9_prev_is_vs)
6291 num_sgprs = 8 + GFX9_VSGS_NUM_USER_SGPR;
6292 else
6293 num_sgprs = 8 + GFX9_TESGS_NUM_USER_SGPR;
6294 num_vgprs = 5; /* ES inputs are not needed by GS */
6295 } else {
6296 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6297 num_vgprs = 8;
6298 }
6299
6300 for (unsigned i = 0; i < num_sgprs; ++i) {
6301 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6302 returns[i] = ctx->i32;
6303 }
6304
6305 for (unsigned i = 0; i < num_vgprs; ++i) {
6306 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6307 returns[num_sgprs + i] = ctx->f32;
6308 }
6309
6310 /* Create the function. */
6311 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6312 &fninfo, 0);
6313 func = ctx->main_fn;
6314
6315 /* Set the full EXEC mask for the prolog, because we are only fiddling
6316 * with registers here. The main shader part will set the correct EXEC
6317 * mask.
6318 */
6319 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6320 ac_init_exec_full_mask(&ctx->ac);
6321
6322 /* Copy inputs to outputs. This should be no-op, as the registers match,
6323 * but it will prevent the compiler from overwriting them unintentionally.
6324 */
6325 ret = ctx->return_value;
6326 for (unsigned i = 0; i < num_sgprs; i++) {
6327 LLVMValueRef p = LLVMGetParam(func, i);
6328 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6329 }
6330 for (unsigned i = 0; i < num_vgprs; i++) {
6331 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6332 p = ac_to_float(&ctx->ac, p);
6333 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6334 }
6335
6336 if (key->gs_prolog.states.tri_strip_adj_fix) {
6337 /* Remap the input vertices for every other primitive. */
6338 const unsigned gfx6_vtx_params[6] = {
6339 num_sgprs,
6340 num_sgprs + 1,
6341 num_sgprs + 3,
6342 num_sgprs + 4,
6343 num_sgprs + 5,
6344 num_sgprs + 6
6345 };
6346 const unsigned gfx9_vtx_params[3] = {
6347 num_sgprs,
6348 num_sgprs + 1,
6349 num_sgprs + 4,
6350 };
6351 LLVMValueRef vtx_in[6], vtx_out[6];
6352 LLVMValueRef prim_id, rotate;
6353
6354 if (ctx->screen->info.chip_class >= GFX9) {
6355 for (unsigned i = 0; i < 3; i++) {
6356 vtx_in[i*2] = si_unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6357 vtx_in[i*2+1] = si_unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6358 }
6359 } else {
6360 for (unsigned i = 0; i < 6; i++)
6361 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6362 }
6363
6364 prim_id = LLVMGetParam(func, num_sgprs + 2);
6365 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6366
6367 for (unsigned i = 0; i < 6; ++i) {
6368 LLVMValueRef base, rotated;
6369 base = vtx_in[i];
6370 rotated = vtx_in[(i + 4) % 6];
6371 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6372 }
6373
6374 if (ctx->screen->info.chip_class >= GFX9) {
6375 for (unsigned i = 0; i < 3; i++) {
6376 LLVMValueRef hi, out;
6377
6378 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6379 LLVMConstInt(ctx->i32, 16, 0), "");
6380 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6381 out = ac_to_float(&ctx->ac, out);
6382 ret = LLVMBuildInsertValue(builder, ret, out,
6383 gfx9_vtx_params[i], "");
6384 }
6385 } else {
6386 for (unsigned i = 0; i < 6; i++) {
6387 LLVMValueRef out;
6388
6389 out = ac_to_float(&ctx->ac, vtx_out[i]);
6390 ret = LLVMBuildInsertValue(builder, ret, out,
6391 gfx6_vtx_params[i], "");
6392 }
6393 }
6394 }
6395
6396 LLVMBuildRet(builder, ret);
6397 }
6398
6399 /**
6400 * Given a list of shader part functions, build a wrapper function that
6401 * runs them in sequence to form a monolithic shader.
6402 */
6403 static void si_build_wrapper_function(struct si_shader_context *ctx,
6404 LLVMValueRef *parts,
6405 unsigned num_parts,
6406 unsigned main_part,
6407 unsigned next_shader_first_part)
6408 {
6409 LLVMBuilderRef builder = ctx->ac.builder;
6410 /* PS epilog has one arg per color component; gfx9 merged shader
6411 * prologs need to forward 32 user SGPRs.
6412 */
6413 struct si_function_info fninfo;
6414 LLVMValueRef initial[64], out[64];
6415 LLVMTypeRef function_type;
6416 unsigned num_first_params;
6417 unsigned num_out, initial_num_out;
6418 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6419 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6420 unsigned num_sgprs, num_vgprs;
6421 unsigned gprs;
6422 struct lp_build_if_state if_state;
6423
6424 si_init_function_info(&fninfo);
6425
6426 for (unsigned i = 0; i < num_parts; ++i) {
6427 ac_add_function_attr(ctx->ac.context, parts[i], -1,
6428 AC_FUNC_ATTR_ALWAYSINLINE);
6429 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6430 }
6431
6432 /* The parameters of the wrapper function correspond to those of the
6433 * first part in terms of SGPRs and VGPRs, but we use the types of the
6434 * main part to get the right types. This is relevant for the
6435 * dereferenceable attribute on descriptor table pointers.
6436 */
6437 num_sgprs = 0;
6438 num_vgprs = 0;
6439
6440 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6441 num_first_params = LLVMCountParamTypes(function_type);
6442
6443 for (unsigned i = 0; i < num_first_params; ++i) {
6444 LLVMValueRef param = LLVMGetParam(parts[0], i);
6445
6446 if (ac_is_sgpr_param(param)) {
6447 assert(num_vgprs == 0);
6448 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6449 } else {
6450 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6451 }
6452 }
6453
6454 gprs = 0;
6455 while (gprs < num_sgprs + num_vgprs) {
6456 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6457 LLVMTypeRef type = LLVMTypeOf(param);
6458 unsigned size = ac_get_type_size(type) / 4;
6459
6460 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6461
6462 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6463 assert(gprs + size <= num_sgprs + num_vgprs &&
6464 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6465
6466 gprs += size;
6467 }
6468
6469 /* Prepare the return type. */
6470 unsigned num_returns = 0;
6471 LLVMTypeRef returns[32], last_func_type, return_type;
6472
6473 last_func_type = LLVMGetElementType(LLVMTypeOf(parts[num_parts - 1]));
6474 return_type = LLVMGetReturnType(last_func_type);
6475
6476 switch (LLVMGetTypeKind(return_type)) {
6477 case LLVMStructTypeKind:
6478 num_returns = LLVMCountStructElementTypes(return_type);
6479 assert(num_returns <= ARRAY_SIZE(returns));
6480 LLVMGetStructElementTypes(return_type, returns);
6481 break;
6482 case LLVMVoidTypeKind:
6483 break;
6484 default:
6485 unreachable("unexpected type");
6486 }
6487
6488 si_create_function(ctx, "wrapper", returns, num_returns, &fninfo,
6489 si_get_max_workgroup_size(ctx->shader));
6490
6491 if (is_merged_shader(ctx))
6492 ac_init_exec_full_mask(&ctx->ac);
6493
6494 /* Record the arguments of the function as if they were an output of
6495 * a previous part.
6496 */
6497 num_out = 0;
6498 num_out_sgpr = 0;
6499
6500 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6501 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6502 LLVMTypeRef param_type = LLVMTypeOf(param);
6503 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6504 unsigned size = ac_get_type_size(param_type) / 4;
6505
6506 if (size == 1) {
6507 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6508 param = LLVMBuildPtrToInt(builder, param, ctx->i32, "");
6509 param_type = ctx->i32;
6510 }
6511
6512 if (param_type != out_type)
6513 param = LLVMBuildBitCast(builder, param, out_type, "");
6514 out[num_out++] = param;
6515 } else {
6516 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6517
6518 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6519 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6520 param_type = ctx->i64;
6521 }
6522
6523 if (param_type != vector_type)
6524 param = LLVMBuildBitCast(builder, param, vector_type, "");
6525
6526 for (unsigned j = 0; j < size; ++j)
6527 out[num_out++] = LLVMBuildExtractElement(
6528 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6529 }
6530
6531 if (i < fninfo.num_sgpr_params)
6532 num_out_sgpr = num_out;
6533 }
6534
6535 memcpy(initial, out, sizeof(out));
6536 initial_num_out = num_out;
6537 initial_num_out_sgpr = num_out_sgpr;
6538
6539 /* Now chain the parts. */
6540 LLVMValueRef ret;
6541 for (unsigned part = 0; part < num_parts; ++part) {
6542 LLVMValueRef in[48];
6543 LLVMTypeRef ret_type;
6544 unsigned out_idx = 0;
6545 unsigned num_params = LLVMCountParams(parts[part]);
6546
6547 /* Merged shaders are executed conditionally depending
6548 * on the number of enabled threads passed in the input SGPRs. */
6549 if (is_merged_shader(ctx) && part == 0) {
6550 LLVMValueRef ena, count = initial[3];
6551
6552 count = LLVMBuildAnd(builder, count,
6553 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6554 ena = LLVMBuildICmp(builder, LLVMIntULT,
6555 ac_get_thread_id(&ctx->ac), count, "");
6556 lp_build_if(&if_state, &ctx->gallivm, ena);
6557 }
6558
6559 /* Derive arguments for the next part from outputs of the
6560 * previous one.
6561 */
6562 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6563 LLVMValueRef param;
6564 LLVMTypeRef param_type;
6565 bool is_sgpr;
6566 unsigned param_size;
6567 LLVMValueRef arg = NULL;
6568
6569 param = LLVMGetParam(parts[part], param_idx);
6570 param_type = LLVMTypeOf(param);
6571 param_size = ac_get_type_size(param_type) / 4;
6572 is_sgpr = ac_is_sgpr_param(param);
6573
6574 if (is_sgpr) {
6575 ac_add_function_attr(ctx->ac.context, parts[part],
6576 param_idx + 1, AC_FUNC_ATTR_INREG);
6577 } else if (out_idx < num_out_sgpr) {
6578 /* Skip returned SGPRs the current part doesn't
6579 * declare on the input. */
6580 out_idx = num_out_sgpr;
6581 }
6582
6583 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6584
6585 if (param_size == 1)
6586 arg = out[out_idx];
6587 else
6588 arg = ac_build_gather_values(&ctx->ac, &out[out_idx], param_size);
6589
6590 if (LLVMTypeOf(arg) != param_type) {
6591 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6592 if (LLVMGetPointerAddressSpace(param_type) ==
6593 AC_ADDR_SPACE_CONST_32BIT) {
6594 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
6595 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6596 } else {
6597 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6598 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6599 }
6600 } else {
6601 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6602 }
6603 }
6604
6605 in[param_idx] = arg;
6606 out_idx += param_size;
6607 }
6608
6609 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6610
6611 if (is_merged_shader(ctx) &&
6612 part + 1 == next_shader_first_part) {
6613 lp_build_endif(&if_state);
6614
6615 /* The second half of the merged shader should use
6616 * the inputs from the toplevel (wrapper) function,
6617 * not the return value from the last call.
6618 *
6619 * That's because the last call was executed condi-
6620 * tionally, so we can't consume it in the main
6621 * block.
6622 */
6623 memcpy(out, initial, sizeof(initial));
6624 num_out = initial_num_out;
6625 num_out_sgpr = initial_num_out_sgpr;
6626 continue;
6627 }
6628
6629 /* Extract the returned GPRs. */
6630 ret_type = LLVMTypeOf(ret);
6631 num_out = 0;
6632 num_out_sgpr = 0;
6633
6634 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6635 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6636
6637 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6638
6639 for (unsigned i = 0; i < ret_size; ++i) {
6640 LLVMValueRef val =
6641 LLVMBuildExtractValue(builder, ret, i, "");
6642
6643 assert(num_out < ARRAY_SIZE(out));
6644 out[num_out++] = val;
6645
6646 if (LLVMTypeOf(val) == ctx->i32) {
6647 assert(num_out_sgpr + 1 == num_out);
6648 num_out_sgpr = num_out;
6649 }
6650 }
6651 }
6652 }
6653
6654 /* Return the value from the last part. */
6655 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6656 LLVMBuildRetVoid(builder);
6657 else
6658 LLVMBuildRet(builder, ret);
6659 }
6660
6661 static bool si_should_optimize_less(struct ac_llvm_compiler *compiler,
6662 struct si_shader_selector *sel)
6663 {
6664 if (!compiler->low_opt_passes)
6665 return false;
6666
6667 /* Assume a slow CPU. */
6668 assert(!sel->screen->info.has_dedicated_vram &&
6669 sel->screen->info.chip_class <= GFX8);
6670
6671 /* For a crazy dEQP test containing 2597 memory opcodes, mostly
6672 * buffer stores. */
6673 return sel->type == PIPE_SHADER_COMPUTE &&
6674 sel->info.num_memory_instructions > 1000;
6675 }
6676
6677 int si_compile_tgsi_shader(struct si_screen *sscreen,
6678 struct ac_llvm_compiler *compiler,
6679 struct si_shader *shader,
6680 struct pipe_debug_callback *debug)
6681 {
6682 struct si_shader_selector *sel = shader->selector;
6683 struct si_shader_context ctx;
6684 int r = -1;
6685
6686 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6687 * conversion fails. */
6688 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6689 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6690 if (sel->tokens)
6691 tgsi_dump(sel->tokens, 0);
6692 else
6693 nir_print_shader(sel->nir, stderr);
6694 si_dump_streamout(&sel->so);
6695 }
6696
6697 si_init_shader_ctx(&ctx, sscreen, compiler);
6698 si_llvm_context_set_tgsi(&ctx, shader);
6699
6700 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6701 sizeof(shader->info.vs_output_param_offset));
6702
6703 shader->info.uses_instanceid = sel->info.uses_instanceid;
6704
6705 if (!si_compile_tgsi_main(&ctx)) {
6706 si_llvm_dispose(&ctx);
6707 return -1;
6708 }
6709
6710 if (shader->is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6711 LLVMValueRef parts[2];
6712 bool need_prolog = sel->vs_needs_prolog;
6713
6714 parts[1] = ctx.main_fn;
6715
6716 if (need_prolog) {
6717 union si_shader_part_key prolog_key;
6718 si_get_vs_prolog_key(&sel->info,
6719 shader->info.num_input_sgprs,
6720 &shader->key.part.vs.prolog,
6721 shader, &prolog_key);
6722 si_build_vs_prolog_function(&ctx, &prolog_key);
6723 parts[0] = ctx.main_fn;
6724 }
6725
6726 si_build_wrapper_function(&ctx, parts + !need_prolog,
6727 1 + need_prolog, need_prolog, 0);
6728
6729 if (ctx.shader->key.opt.vs_as_prim_discard_cs)
6730 si_build_prim_discard_compute_shader(&ctx);
6731 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6732 if (sscreen->info.chip_class >= GFX9) {
6733 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6734 LLVMValueRef parts[4];
6735 bool vs_needs_prolog =
6736 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6737
6738 /* TCS main part */
6739 parts[2] = ctx.main_fn;
6740
6741 /* TCS epilog */
6742 union si_shader_part_key tcs_epilog_key;
6743 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6744 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6745 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6746 parts[3] = ctx.main_fn;
6747
6748 /* VS as LS main part */
6749 struct si_shader shader_ls = {};
6750 shader_ls.selector = ls;
6751 shader_ls.key.as_ls = 1;
6752 shader_ls.key.mono = shader->key.mono;
6753 shader_ls.key.opt = shader->key.opt;
6754 shader_ls.is_monolithic = true;
6755 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6756
6757 if (!si_compile_tgsi_main(&ctx)) {
6758 si_llvm_dispose(&ctx);
6759 return -1;
6760 }
6761 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6762 parts[1] = ctx.main_fn;
6763
6764 /* LS prolog */
6765 if (vs_needs_prolog) {
6766 union si_shader_part_key vs_prolog_key;
6767 si_get_vs_prolog_key(&ls->info,
6768 shader_ls.info.num_input_sgprs,
6769 &shader->key.part.tcs.ls_prolog,
6770 shader, &vs_prolog_key);
6771 vs_prolog_key.vs_prolog.is_monolithic = true;
6772 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6773 parts[0] = ctx.main_fn;
6774 }
6775
6776 /* Reset the shader context. */
6777 ctx.shader = shader;
6778 ctx.type = PIPE_SHADER_TESS_CTRL;
6779
6780 si_build_wrapper_function(&ctx,
6781 parts + !vs_needs_prolog,
6782 4 - !vs_needs_prolog, vs_needs_prolog,
6783 vs_needs_prolog ? 2 : 1);
6784 } else {
6785 LLVMValueRef parts[2];
6786 union si_shader_part_key epilog_key;
6787
6788 parts[0] = ctx.main_fn;
6789
6790 memset(&epilog_key, 0, sizeof(epilog_key));
6791 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6792 si_build_tcs_epilog_function(&ctx, &epilog_key);
6793 parts[1] = ctx.main_fn;
6794
6795 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6796 }
6797 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6798 if (ctx.screen->info.chip_class >= GFX9) {
6799 struct si_shader_selector *es = shader->key.part.gs.es;
6800 LLVMValueRef es_prolog = NULL;
6801 LLVMValueRef es_main = NULL;
6802 LLVMValueRef gs_prolog = NULL;
6803 LLVMValueRef gs_main = ctx.main_fn;
6804
6805 /* GS prolog */
6806 union si_shader_part_key gs_prolog_key;
6807 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6808 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6809 gs_prolog_key.gs_prolog.is_monolithic = true;
6810 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6811 gs_prolog = ctx.main_fn;
6812
6813 /* ES main part */
6814 struct si_shader shader_es = {};
6815 shader_es.selector = es;
6816 shader_es.key.as_es = 1;
6817 shader_es.key.mono = shader->key.mono;
6818 shader_es.key.opt = shader->key.opt;
6819 shader_es.is_monolithic = true;
6820 si_llvm_context_set_tgsi(&ctx, &shader_es);
6821
6822 if (!si_compile_tgsi_main(&ctx)) {
6823 si_llvm_dispose(&ctx);
6824 return -1;
6825 }
6826 shader->info.uses_instanceid |= es->info.uses_instanceid;
6827 es_main = ctx.main_fn;
6828
6829 /* ES prolog */
6830 if (es->vs_needs_prolog) {
6831 union si_shader_part_key vs_prolog_key;
6832 si_get_vs_prolog_key(&es->info,
6833 shader_es.info.num_input_sgprs,
6834 &shader->key.part.gs.vs_prolog,
6835 shader, &vs_prolog_key);
6836 vs_prolog_key.vs_prolog.is_monolithic = true;
6837 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6838 es_prolog = ctx.main_fn;
6839 }
6840
6841 /* Reset the shader context. */
6842 ctx.shader = shader;
6843 ctx.type = PIPE_SHADER_GEOMETRY;
6844
6845 /* Prepare the array of shader parts. */
6846 LLVMValueRef parts[4];
6847 unsigned num_parts = 0, main_part, next_first_part;
6848
6849 if (es_prolog)
6850 parts[num_parts++] = es_prolog;
6851
6852 parts[main_part = num_parts++] = es_main;
6853 parts[next_first_part = num_parts++] = gs_prolog;
6854 parts[num_parts++] = gs_main;
6855
6856 si_build_wrapper_function(&ctx, parts, num_parts,
6857 main_part, next_first_part);
6858 } else {
6859 LLVMValueRef parts[2];
6860 union si_shader_part_key prolog_key;
6861
6862 parts[1] = ctx.main_fn;
6863
6864 memset(&prolog_key, 0, sizeof(prolog_key));
6865 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6866 si_build_gs_prolog_function(&ctx, &prolog_key);
6867 parts[0] = ctx.main_fn;
6868
6869 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6870 }
6871 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6872 LLVMValueRef parts[3];
6873 union si_shader_part_key prolog_key;
6874 union si_shader_part_key epilog_key;
6875 bool need_prolog;
6876
6877 si_get_ps_prolog_key(shader, &prolog_key, false);
6878 need_prolog = si_need_ps_prolog(&prolog_key);
6879
6880 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6881
6882 if (need_prolog) {
6883 si_build_ps_prolog_function(&ctx, &prolog_key);
6884 parts[0] = ctx.main_fn;
6885 }
6886
6887 si_get_ps_epilog_key(shader, &epilog_key);
6888 si_build_ps_epilog_function(&ctx, &epilog_key);
6889 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6890
6891 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6892 need_prolog ? 1 : 0, 0);
6893 }
6894
6895 si_llvm_optimize_module(&ctx);
6896
6897 /* Post-optimization transformations and analysis. */
6898 si_optimize_vs_outputs(&ctx);
6899
6900 if ((debug && debug->debug_message) ||
6901 si_can_dump_shader(sscreen, ctx.type)) {
6902 ctx.shader->config.private_mem_vgprs =
6903 ac_count_scratch_private_memory(ctx.main_fn);
6904 }
6905
6906 /* Make sure the input is a pointer and not integer followed by inttoptr. */
6907 assert(LLVMGetTypeKind(LLVMTypeOf(LLVMGetParam(ctx.main_fn, 0))) ==
6908 LLVMPointerTypeKind);
6909
6910 /* Compile to bytecode. */
6911 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, compiler,
6912 ctx.ac.module, debug, ctx.type,
6913 si_get_shader_name(shader, ctx.type),
6914 si_should_optimize_less(compiler, shader->selector));
6915 si_llvm_dispose(&ctx);
6916 if (r) {
6917 fprintf(stderr, "LLVM failed to compile shader\n");
6918 return r;
6919 }
6920
6921 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6922 * LLVM 3.9svn has this bug.
6923 */
6924 if (sel->type == PIPE_SHADER_COMPUTE) {
6925 unsigned wave_size = 64;
6926 unsigned max_vgprs = 256;
6927 unsigned max_sgprs = sscreen->info.chip_class >= GFX8 ? 800 : 512;
6928 unsigned max_sgprs_per_wave = 128;
6929 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6930 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6931 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6932
6933 max_vgprs = max_vgprs / min_waves_per_simd;
6934 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6935
6936 if (shader->config.num_sgprs > max_sgprs ||
6937 shader->config.num_vgprs > max_vgprs) {
6938 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6939 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6940 shader->config.num_sgprs, shader->config.num_vgprs,
6941 max_sgprs, max_vgprs);
6942
6943 /* Just terminate the process, because dependent
6944 * shaders can hang due to bad input data, but use
6945 * the env var to allow shader-db to work.
6946 */
6947 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6948 abort();
6949 }
6950 }
6951
6952 /* Add the scratch offset to input SGPRs. */
6953 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(&ctx))
6954 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6955
6956 /* Calculate the number of fragment input VGPRs. */
6957 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6958 shader->info.num_input_vgprs = 0;
6959 shader->info.face_vgpr_index = -1;
6960 shader->info.ancillary_vgpr_index = -1;
6961
6962 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6963 shader->info.num_input_vgprs += 2;
6964 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6965 shader->info.num_input_vgprs += 2;
6966 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6967 shader->info.num_input_vgprs += 2;
6968 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6969 shader->info.num_input_vgprs += 3;
6970 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6971 shader->info.num_input_vgprs += 2;
6972 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6973 shader->info.num_input_vgprs += 2;
6974 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6975 shader->info.num_input_vgprs += 2;
6976 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6977 shader->info.num_input_vgprs += 1;
6978 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6979 shader->info.num_input_vgprs += 1;
6980 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6981 shader->info.num_input_vgprs += 1;
6982 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6983 shader->info.num_input_vgprs += 1;
6984 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6985 shader->info.num_input_vgprs += 1;
6986 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6987 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6988 shader->info.num_input_vgprs += 1;
6989 }
6990 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
6991 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
6992 shader->info.num_input_vgprs += 1;
6993 }
6994 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6995 shader->info.num_input_vgprs += 1;
6996 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6997 shader->info.num_input_vgprs += 1;
6998 }
6999
7000 si_calculate_max_simd_waves(shader);
7001 si_shader_dump_stats_for_shader_db(shader, debug);
7002 return 0;
7003 }
7004
7005 /**
7006 * Create, compile and return a shader part (prolog or epilog).
7007 *
7008 * \param sscreen screen
7009 * \param list list of shader parts of the same category
7010 * \param type shader type
7011 * \param key shader part key
7012 * \param prolog whether the part being requested is a prolog
7013 * \param tm LLVM target machine
7014 * \param debug debug callback
7015 * \param build the callback responsible for building the main function
7016 * \return non-NULL on success
7017 */
7018 static struct si_shader_part *
7019 si_get_shader_part(struct si_screen *sscreen,
7020 struct si_shader_part **list,
7021 enum pipe_shader_type type,
7022 bool prolog,
7023 union si_shader_part_key *key,
7024 struct ac_llvm_compiler *compiler,
7025 struct pipe_debug_callback *debug,
7026 void (*build)(struct si_shader_context *,
7027 union si_shader_part_key *),
7028 const char *name)
7029 {
7030 struct si_shader_part *result;
7031
7032 mtx_lock(&sscreen->shader_parts_mutex);
7033
7034 /* Find existing. */
7035 for (result = *list; result; result = result->next) {
7036 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7037 mtx_unlock(&sscreen->shader_parts_mutex);
7038 return result;
7039 }
7040 }
7041
7042 /* Compile a new one. */
7043 result = CALLOC_STRUCT(si_shader_part);
7044 result->key = *key;
7045
7046 struct si_shader shader = {};
7047 struct si_shader_context ctx;
7048
7049 si_init_shader_ctx(&ctx, sscreen, compiler);
7050 ctx.shader = &shader;
7051 ctx.type = type;
7052
7053 switch (type) {
7054 case PIPE_SHADER_VERTEX:
7055 shader.key.as_ls = key->vs_prolog.as_ls;
7056 shader.key.as_es = key->vs_prolog.as_es;
7057 break;
7058 case PIPE_SHADER_TESS_CTRL:
7059 assert(!prolog);
7060 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7061 break;
7062 case PIPE_SHADER_GEOMETRY:
7063 assert(prolog);
7064 break;
7065 case PIPE_SHADER_FRAGMENT:
7066 if (prolog)
7067 shader.key.part.ps.prolog = key->ps_prolog.states;
7068 else
7069 shader.key.part.ps.epilog = key->ps_epilog.states;
7070 break;
7071 default:
7072 unreachable("bad shader part");
7073 }
7074
7075 build(&ctx, key);
7076
7077 /* Compile. */
7078 si_llvm_optimize_module(&ctx);
7079
7080 if (si_compile_llvm(sscreen, &result->binary, &result->config, compiler,
7081 ctx.ac.module, debug, ctx.type, name, false)) {
7082 FREE(result);
7083 result = NULL;
7084 goto out;
7085 }
7086
7087 result->next = *list;
7088 *list = result;
7089
7090 out:
7091 si_llvm_dispose(&ctx);
7092 mtx_unlock(&sscreen->shader_parts_mutex);
7093 return result;
7094 }
7095
7096 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
7097 {
7098 LLVMValueRef ptr[2], list;
7099 bool merged_shader = is_merged_shader(ctx);
7100
7101 ptr[0] = LLVMGetParam(ctx->main_fn, (merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7102 list = LLVMBuildIntToPtr(ctx->ac.builder, ptr[0],
7103 ac_array_in_const32_addr_space(ctx->v4i32), "");
7104 return list;
7105 }
7106
7107 /**
7108 * Build the vertex shader prolog function.
7109 *
7110 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7111 * All inputs are returned unmodified. The vertex load indices are
7112 * stored after them, which will be used by the API VS for fetching inputs.
7113 *
7114 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7115 * input_v0,
7116 * input_v1,
7117 * input_v2,
7118 * input_v3,
7119 * (VertexID + BaseVertex),
7120 * (InstanceID + StartInstance),
7121 * (InstanceID / 2 + StartInstance)
7122 */
7123 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7124 union si_shader_part_key *key)
7125 {
7126 struct si_function_info fninfo;
7127 LLVMTypeRef *returns;
7128 LLVMValueRef ret, func;
7129 int num_returns, i;
7130 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
7131 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
7132 LLVMValueRef input_vgprs[9];
7133 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
7134 num_input_vgprs;
7135 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
7136
7137 si_init_function_info(&fninfo);
7138
7139 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7140 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
7141 sizeof(LLVMTypeRef));
7142 num_returns = 0;
7143
7144 /* Declare input and output SGPRs. */
7145 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7146 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7147 returns[num_returns++] = ctx->i32;
7148 }
7149
7150 /* Preloaded VGPRs (outputs must be floats) */
7151 for (i = 0; i < num_input_vgprs; i++) {
7152 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
7153 returns[num_returns++] = ctx->f32;
7154 }
7155
7156 /* Vertex load indices. */
7157 for (i = 0; i <= key->vs_prolog.last_input; i++)
7158 returns[num_returns++] = ctx->f32;
7159
7160 /* Create the function. */
7161 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
7162 func = ctx->main_fn;
7163
7164 if (key->vs_prolog.num_merged_next_stage_vgprs) {
7165 if (!key->vs_prolog.is_monolithic)
7166 si_init_exec_from_input(ctx, 3, 0);
7167
7168 if (key->vs_prolog.as_ls &&
7169 ctx->screen->has_ls_vgpr_init_bug) {
7170 /* If there are no HS threads, SPI loads the LS VGPRs
7171 * starting at VGPR 0. Shift them back to where they
7172 * belong.
7173 */
7174 LLVMValueRef has_hs_threads =
7175 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
7176 si_unpack_param(ctx, 3, 8, 8),
7177 ctx->i32_0, "");
7178
7179 for (i = 4; i > 0; --i) {
7180 input_vgprs[i + 1] =
7181 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
7182 input_vgprs[i + 1],
7183 input_vgprs[i - 1], "");
7184 }
7185 }
7186 }
7187
7188 unsigned vertex_id_vgpr = first_vs_vgpr;
7189 unsigned instance_id_vgpr = first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1);
7190
7191 ctx->abi.vertex_id = input_vgprs[vertex_id_vgpr];
7192 ctx->abi.instance_id = input_vgprs[instance_id_vgpr];
7193
7194 /* InstanceID = VertexID >> 16;
7195 * VertexID = VertexID & 0xffff;
7196 */
7197 if (key->vs_prolog.states.unpack_instance_id_from_vertex_id) {
7198 ctx->abi.instance_id = LLVMBuildLShr(ctx->ac.builder, ctx->abi.vertex_id,
7199 LLVMConstInt(ctx->i32, 16, 0), "");
7200 ctx->abi.vertex_id = LLVMBuildAnd(ctx->ac.builder, ctx->abi.vertex_id,
7201 LLVMConstInt(ctx->i32, 0xffff, 0), "");
7202 }
7203
7204 /* Copy inputs to outputs. This should be no-op, as the registers match,
7205 * but it will prevent the compiler from overwriting them unintentionally.
7206 */
7207 ret = ctx->return_value;
7208 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7209 LLVMValueRef p = LLVMGetParam(func, i);
7210 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7211 }
7212 for (i = 0; i < num_input_vgprs; i++) {
7213 LLVMValueRef p = input_vgprs[i];
7214
7215 if (i == vertex_id_vgpr)
7216 p = ctx->abi.vertex_id;
7217 else if (i == instance_id_vgpr)
7218 p = ctx->abi.instance_id;
7219
7220 p = ac_to_float(&ctx->ac, p);
7221 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
7222 key->vs_prolog.num_input_sgprs + i, "");
7223 }
7224
7225 /* Compute vertex load indices from instance divisors. */
7226 LLVMValueRef instance_divisor_constbuf = NULL;
7227
7228 if (key->vs_prolog.states.instance_divisor_is_fetched) {
7229 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7230 LLVMValueRef buf_index =
7231 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
7232 instance_divisor_constbuf =
7233 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
7234 }
7235
7236 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7237 bool divisor_is_one =
7238 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
7239 bool divisor_is_fetched =
7240 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
7241 LLVMValueRef index = NULL;
7242
7243 if (divisor_is_one) {
7244 index = ctx->abi.instance_id;
7245 } else if (divisor_is_fetched) {
7246 LLVMValueRef udiv_factors[4];
7247
7248 for (unsigned j = 0; j < 4; j++) {
7249 udiv_factors[j] =
7250 buffer_load_const(ctx, instance_divisor_constbuf,
7251 LLVMConstInt(ctx->i32, i*16 + j*4, 0));
7252 udiv_factors[j] = ac_to_integer(&ctx->ac, udiv_factors[j]);
7253 }
7254 /* The faster NUW version doesn't work when InstanceID == UINT_MAX.
7255 * Such InstanceID might not be achievable in a reasonable time though.
7256 */
7257 index = ac_build_fast_udiv_nuw(&ctx->ac, ctx->abi.instance_id,
7258 udiv_factors[0], udiv_factors[1],
7259 udiv_factors[2], udiv_factors[3]);
7260 }
7261
7262 if (divisor_is_one || divisor_is_fetched) {
7263 /* Add StartInstance. */
7264 index = LLVMBuildAdd(ctx->ac.builder, index,
7265 LLVMGetParam(ctx->main_fn, user_sgpr_base +
7266 SI_SGPR_START_INSTANCE), "");
7267 } else {
7268 /* VertexID + BaseVertex */
7269 index = LLVMBuildAdd(ctx->ac.builder,
7270 ctx->abi.vertex_id,
7271 LLVMGetParam(func, user_sgpr_base +
7272 SI_SGPR_BASE_VERTEX), "");
7273 }
7274
7275 index = ac_to_float(&ctx->ac, index);
7276 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7277 fninfo.num_params + i, "");
7278 }
7279
7280 si_llvm_build_ret(ctx, ret);
7281 }
7282
7283 static bool si_get_vs_prolog(struct si_screen *sscreen,
7284 struct ac_llvm_compiler *compiler,
7285 struct si_shader *shader,
7286 struct pipe_debug_callback *debug,
7287 struct si_shader *main_part,
7288 const struct si_vs_prolog_bits *key)
7289 {
7290 struct si_shader_selector *vs = main_part->selector;
7291
7292 if (!si_vs_needs_prolog(vs, key))
7293 return true;
7294
7295 /* Get the prolog. */
7296 union si_shader_part_key prolog_key;
7297 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7298 key, shader, &prolog_key);
7299
7300 shader->prolog =
7301 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7302 PIPE_SHADER_VERTEX, true, &prolog_key, compiler,
7303 debug, si_build_vs_prolog_function,
7304 "Vertex Shader Prolog");
7305 return shader->prolog != NULL;
7306 }
7307
7308 /**
7309 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7310 */
7311 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7312 struct ac_llvm_compiler *compiler,
7313 struct si_shader *shader,
7314 struct pipe_debug_callback *debug)
7315 {
7316 return si_get_vs_prolog(sscreen, compiler, shader, debug, shader,
7317 &shader->key.part.vs.prolog);
7318 }
7319
7320 /**
7321 * Compile the TCS epilog function. This writes tesselation factors to memory
7322 * based on the output primitive type of the tesselator (determined by TES).
7323 */
7324 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7325 union si_shader_part_key *key)
7326 {
7327 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7328 struct si_function_info fninfo;
7329 LLVMValueRef func;
7330
7331 si_init_function_info(&fninfo);
7332
7333 if (ctx->screen->info.chip_class >= GFX9) {
7334 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7335 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7336 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7337 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7338 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7339 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7340 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7341 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7342 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7343 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7344 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7345 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7346 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7347 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7348 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7349 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7350 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7351 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7352 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7353 } else {
7354 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7355 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7356 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7357 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7358 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7359 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7360 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7361 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7362 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7363 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7364 }
7365
7366 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7367 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7368 unsigned tess_factors_idx =
7369 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7370 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7371 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7372
7373 for (unsigned i = 0; i < 6; i++)
7374 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7375
7376 /* Create the function. */
7377 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7378 ctx->screen->info.chip_class >= GFX7 ? 128 : 64);
7379 ac_declare_lds_as_pointer(&ctx->ac);
7380 func = ctx->main_fn;
7381
7382 LLVMValueRef invoc0_tess_factors[6];
7383 for (unsigned i = 0; i < 6; i++)
7384 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7385
7386 si_write_tess_factors(bld_base,
7387 LLVMGetParam(func, tess_factors_idx),
7388 LLVMGetParam(func, tess_factors_idx + 1),
7389 LLVMGetParam(func, tess_factors_idx + 2),
7390 invoc0_tess_factors, invoc0_tess_factors + 4);
7391
7392 LLVMBuildRetVoid(ctx->ac.builder);
7393 }
7394
7395 /**
7396 * Select and compile (or reuse) TCS parts (epilog).
7397 */
7398 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7399 struct ac_llvm_compiler *compiler,
7400 struct si_shader *shader,
7401 struct pipe_debug_callback *debug)
7402 {
7403 if (sscreen->info.chip_class >= GFX9) {
7404 struct si_shader *ls_main_part =
7405 shader->key.part.tcs.ls->main_shader_part_ls;
7406
7407 if (!si_get_vs_prolog(sscreen, compiler, shader, debug, ls_main_part,
7408 &shader->key.part.tcs.ls_prolog))
7409 return false;
7410
7411 shader->previous_stage = ls_main_part;
7412 }
7413
7414 /* Get the epilog. */
7415 union si_shader_part_key epilog_key;
7416 memset(&epilog_key, 0, sizeof(epilog_key));
7417 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7418
7419 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7420 PIPE_SHADER_TESS_CTRL, false,
7421 &epilog_key, compiler, debug,
7422 si_build_tcs_epilog_function,
7423 "Tessellation Control Shader Epilog");
7424 return shader->epilog != NULL;
7425 }
7426
7427 /**
7428 * Select and compile (or reuse) GS parts (prolog).
7429 */
7430 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7431 struct ac_llvm_compiler *compiler,
7432 struct si_shader *shader,
7433 struct pipe_debug_callback *debug)
7434 {
7435 if (sscreen->info.chip_class >= GFX9) {
7436 struct si_shader *es_main_part =
7437 shader->key.part.gs.es->main_shader_part_es;
7438
7439 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7440 !si_get_vs_prolog(sscreen, compiler, shader, debug, es_main_part,
7441 &shader->key.part.gs.vs_prolog))
7442 return false;
7443
7444 shader->previous_stage = es_main_part;
7445 }
7446
7447 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7448 return true;
7449
7450 union si_shader_part_key prolog_key;
7451 memset(&prolog_key, 0, sizeof(prolog_key));
7452 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7453
7454 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7455 PIPE_SHADER_GEOMETRY, true,
7456 &prolog_key, compiler, debug,
7457 si_build_gs_prolog_function,
7458 "Geometry Shader Prolog");
7459 return shader->prolog2 != NULL;
7460 }
7461
7462 /**
7463 * Build the pixel shader prolog function. This handles:
7464 * - two-side color selection and interpolation
7465 * - overriding interpolation parameters for the API PS
7466 * - polygon stippling
7467 *
7468 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7469 * overriden by other states. (e.g. per-sample interpolation)
7470 * Interpolated colors are stored after the preloaded VGPRs.
7471 */
7472 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7473 union si_shader_part_key *key)
7474 {
7475 struct si_function_info fninfo;
7476 LLVMValueRef ret, func;
7477 int num_returns, i, num_color_channels;
7478
7479 assert(si_need_ps_prolog(key));
7480
7481 si_init_function_info(&fninfo);
7482
7483 /* Declare inputs. */
7484 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7485 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7486
7487 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7488 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7489
7490 /* Declare outputs (same as inputs + add colors if needed) */
7491 num_returns = fninfo.num_params;
7492 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7493 for (i = 0; i < num_color_channels; i++)
7494 fninfo.types[num_returns++] = ctx->f32;
7495
7496 /* Create the function. */
7497 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7498 &fninfo, 0);
7499 func = ctx->main_fn;
7500
7501 /* Copy inputs to outputs. This should be no-op, as the registers match,
7502 * but it will prevent the compiler from overwriting them unintentionally.
7503 */
7504 ret = ctx->return_value;
7505 for (i = 0; i < fninfo.num_params; i++) {
7506 LLVMValueRef p = LLVMGetParam(func, i);
7507 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7508 }
7509
7510 /* Polygon stippling. */
7511 if (key->ps_prolog.states.poly_stipple) {
7512 /* POS_FIXED_PT is always last. */
7513 unsigned pos = key->ps_prolog.num_input_sgprs +
7514 key->ps_prolog.num_input_vgprs - 1;
7515 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7516
7517 si_llvm_emit_polygon_stipple(ctx, list, pos);
7518 }
7519
7520 if (key->ps_prolog.states.bc_optimize_for_persp ||
7521 key->ps_prolog.states.bc_optimize_for_linear) {
7522 unsigned i, base = key->ps_prolog.num_input_sgprs;
7523 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7524
7525 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7526 * The hw doesn't compute CENTROID if the whole wave only
7527 * contains fully-covered quads.
7528 *
7529 * PRIM_MASK is after user SGPRs.
7530 */
7531 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7532 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7533 LLVMConstInt(ctx->i32, 31, 0), "");
7534 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7535 ctx->i1, "");
7536
7537 if (key->ps_prolog.states.bc_optimize_for_persp) {
7538 /* Read PERSP_CENTER. */
7539 for (i = 0; i < 2; i++)
7540 center[i] = LLVMGetParam(func, base + 2 + i);
7541 /* Read PERSP_CENTROID. */
7542 for (i = 0; i < 2; i++)
7543 centroid[i] = LLVMGetParam(func, base + 4 + i);
7544 /* Select PERSP_CENTROID. */
7545 for (i = 0; i < 2; i++) {
7546 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7547 center[i], centroid[i], "");
7548 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7549 tmp, base + 4 + i, "");
7550 }
7551 }
7552 if (key->ps_prolog.states.bc_optimize_for_linear) {
7553 /* Read LINEAR_CENTER. */
7554 for (i = 0; i < 2; i++)
7555 center[i] = LLVMGetParam(func, base + 8 + i);
7556 /* Read LINEAR_CENTROID. */
7557 for (i = 0; i < 2; i++)
7558 centroid[i] = LLVMGetParam(func, base + 10 + i);
7559 /* Select LINEAR_CENTROID. */
7560 for (i = 0; i < 2; i++) {
7561 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7562 center[i], centroid[i], "");
7563 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7564 tmp, base + 10 + i, "");
7565 }
7566 }
7567 }
7568
7569 /* Force per-sample interpolation. */
7570 if (key->ps_prolog.states.force_persp_sample_interp) {
7571 unsigned i, base = key->ps_prolog.num_input_sgprs;
7572 LLVMValueRef persp_sample[2];
7573
7574 /* Read PERSP_SAMPLE. */
7575 for (i = 0; i < 2; i++)
7576 persp_sample[i] = LLVMGetParam(func, base + i);
7577 /* Overwrite PERSP_CENTER. */
7578 for (i = 0; i < 2; i++)
7579 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7580 persp_sample[i], base + 2 + i, "");
7581 /* Overwrite PERSP_CENTROID. */
7582 for (i = 0; i < 2; i++)
7583 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7584 persp_sample[i], base + 4 + i, "");
7585 }
7586 if (key->ps_prolog.states.force_linear_sample_interp) {
7587 unsigned i, base = key->ps_prolog.num_input_sgprs;
7588 LLVMValueRef linear_sample[2];
7589
7590 /* Read LINEAR_SAMPLE. */
7591 for (i = 0; i < 2; i++)
7592 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7593 /* Overwrite LINEAR_CENTER. */
7594 for (i = 0; i < 2; i++)
7595 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7596 linear_sample[i], base + 8 + i, "");
7597 /* Overwrite LINEAR_CENTROID. */
7598 for (i = 0; i < 2; i++)
7599 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7600 linear_sample[i], base + 10 + i, "");
7601 }
7602
7603 /* Force center interpolation. */
7604 if (key->ps_prolog.states.force_persp_center_interp) {
7605 unsigned i, base = key->ps_prolog.num_input_sgprs;
7606 LLVMValueRef persp_center[2];
7607
7608 /* Read PERSP_CENTER. */
7609 for (i = 0; i < 2; i++)
7610 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7611 /* Overwrite PERSP_SAMPLE. */
7612 for (i = 0; i < 2; i++)
7613 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7614 persp_center[i], base + i, "");
7615 /* Overwrite PERSP_CENTROID. */
7616 for (i = 0; i < 2; i++)
7617 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7618 persp_center[i], base + 4 + i, "");
7619 }
7620 if (key->ps_prolog.states.force_linear_center_interp) {
7621 unsigned i, base = key->ps_prolog.num_input_sgprs;
7622 LLVMValueRef linear_center[2];
7623
7624 /* Read LINEAR_CENTER. */
7625 for (i = 0; i < 2; i++)
7626 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7627 /* Overwrite LINEAR_SAMPLE. */
7628 for (i = 0; i < 2; i++)
7629 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7630 linear_center[i], base + 6 + i, "");
7631 /* Overwrite LINEAR_CENTROID. */
7632 for (i = 0; i < 2; i++)
7633 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7634 linear_center[i], base + 10 + i, "");
7635 }
7636
7637 /* Interpolate colors. */
7638 unsigned color_out_idx = 0;
7639 for (i = 0; i < 2; i++) {
7640 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7641 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7642 key->ps_prolog.face_vgpr_index;
7643 LLVMValueRef interp[2], color[4];
7644 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7645
7646 if (!writemask)
7647 continue;
7648
7649 /* If the interpolation qualifier is not CONSTANT (-1). */
7650 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7651 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7652 key->ps_prolog.color_interp_vgpr_index[i];
7653
7654 /* Get the (i,j) updated by bc_optimize handling. */
7655 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7656 interp_vgpr, "");
7657 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7658 interp_vgpr + 1, "");
7659 interp_ij = ac_build_gather_values(&ctx->ac, interp, 2);
7660 }
7661
7662 /* Use the absolute location of the input. */
7663 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7664
7665 if (key->ps_prolog.states.color_two_side) {
7666 face = LLVMGetParam(func, face_vgpr);
7667 face = ac_to_integer(&ctx->ac, face);
7668 }
7669
7670 interp_fs_input(ctx,
7671 key->ps_prolog.color_attr_index[i],
7672 TGSI_SEMANTIC_COLOR, i,
7673 key->ps_prolog.num_interp_inputs,
7674 key->ps_prolog.colors_read, interp_ij,
7675 prim_mask, face, color);
7676
7677 while (writemask) {
7678 unsigned chan = u_bit_scan(&writemask);
7679 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7680 fninfo.num_params + color_out_idx++, "");
7681 }
7682 }
7683
7684 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7685 * says:
7686 *
7687 * "When per-sample shading is active due to the use of a fragment
7688 * input qualified by sample or due to the use of the gl_SampleID
7689 * or gl_SamplePosition variables, only the bit for the current
7690 * sample is set in gl_SampleMaskIn. When state specifies multiple
7691 * fragment shader invocations for a given fragment, the sample
7692 * mask for any single fragment shader invocation may specify a
7693 * subset of the covered samples for the fragment. In this case,
7694 * the bit corresponding to each covered sample will be set in
7695 * exactly one fragment shader invocation."
7696 *
7697 * The samplemask loaded by hardware is always the coverage of the
7698 * entire pixel/fragment, so mask bits out based on the sample ID.
7699 */
7700 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7701 /* The bit pattern matches that used by fixed function fragment
7702 * processing. */
7703 static const uint16_t ps_iter_masks[] = {
7704 0xffff, /* not used */
7705 0x5555,
7706 0x1111,
7707 0x0101,
7708 0x0001,
7709 };
7710 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7711
7712 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7713 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7714 key->ps_prolog.ancillary_vgpr_index;
7715 LLVMValueRef sampleid = si_unpack_param(ctx, ancillary_vgpr, 8, 4);
7716 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7717
7718 samplemask = ac_to_integer(&ctx->ac, samplemask);
7719 samplemask = LLVMBuildAnd(
7720 ctx->ac.builder,
7721 samplemask,
7722 LLVMBuildShl(ctx->ac.builder,
7723 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7724 sampleid, ""),
7725 "");
7726 samplemask = ac_to_float(&ctx->ac, samplemask);
7727
7728 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7729 ancillary_vgpr + 1, "");
7730 }
7731
7732 /* Tell LLVM to insert WQM instruction sequence when needed. */
7733 if (key->ps_prolog.wqm) {
7734 LLVMAddTargetDependentFunctionAttr(func,
7735 "amdgpu-ps-wqm-outputs", "");
7736 }
7737
7738 si_llvm_build_ret(ctx, ret);
7739 }
7740
7741 /**
7742 * Build the pixel shader epilog function. This handles everything that must be
7743 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7744 */
7745 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7746 union si_shader_part_key *key)
7747 {
7748 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7749 struct si_function_info fninfo;
7750 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7751 int i;
7752 struct si_ps_exports exp = {};
7753
7754 si_init_function_info(&fninfo);
7755
7756 /* Declare input SGPRs. */
7757 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7758 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7759 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7760 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7761 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7762
7763 /* Declare input VGPRs. */
7764 unsigned required_num_params =
7765 fninfo.num_sgpr_params +
7766 util_bitcount(key->ps_epilog.colors_written) * 4 +
7767 key->ps_epilog.writes_z +
7768 key->ps_epilog.writes_stencil +
7769 key->ps_epilog.writes_samplemask;
7770
7771 required_num_params = MAX2(required_num_params,
7772 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7773
7774 while (fninfo.num_params < required_num_params)
7775 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7776
7777 /* Create the function. */
7778 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7779 /* Disable elimination of unused inputs. */
7780 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
7781 "InitialPSInputAddr", 0xffffff);
7782
7783 /* Process colors. */
7784 unsigned vgpr = fninfo.num_sgpr_params;
7785 unsigned colors_written = key->ps_epilog.colors_written;
7786 int last_color_export = -1;
7787
7788 /* Find the last color export. */
7789 if (!key->ps_epilog.writes_z &&
7790 !key->ps_epilog.writes_stencil &&
7791 !key->ps_epilog.writes_samplemask) {
7792 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7793
7794 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7795 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7796 /* Just set this if any of the colorbuffers are enabled. */
7797 if (spi_format &
7798 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7799 last_color_export = 0;
7800 } else {
7801 for (i = 0; i < 8; i++)
7802 if (colors_written & (1 << i) &&
7803 (spi_format >> (i * 4)) & 0xf)
7804 last_color_export = i;
7805 }
7806 }
7807
7808 while (colors_written) {
7809 LLVMValueRef color[4];
7810 int mrt = u_bit_scan(&colors_written);
7811
7812 for (i = 0; i < 4; i++)
7813 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7814
7815 si_export_mrt_color(bld_base, color, mrt,
7816 fninfo.num_params - 1,
7817 mrt == last_color_export, &exp);
7818 }
7819
7820 /* Process depth, stencil, samplemask. */
7821 if (key->ps_epilog.writes_z)
7822 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7823 if (key->ps_epilog.writes_stencil)
7824 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7825 if (key->ps_epilog.writes_samplemask)
7826 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7827
7828 if (depth || stencil || samplemask)
7829 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7830 else if (last_color_export == -1)
7831 ac_build_export_null(&ctx->ac);
7832
7833 if (exp.num)
7834 si_emit_ps_exports(ctx, &exp);
7835
7836 /* Compile. */
7837 LLVMBuildRetVoid(ctx->ac.builder);
7838 }
7839
7840 /**
7841 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7842 */
7843 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7844 struct ac_llvm_compiler *compiler,
7845 struct si_shader *shader,
7846 struct pipe_debug_callback *debug)
7847 {
7848 union si_shader_part_key prolog_key;
7849 union si_shader_part_key epilog_key;
7850
7851 /* Get the prolog. */
7852 si_get_ps_prolog_key(shader, &prolog_key, true);
7853
7854 /* The prolog is a no-op if these aren't set. */
7855 if (si_need_ps_prolog(&prolog_key)) {
7856 shader->prolog =
7857 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7858 PIPE_SHADER_FRAGMENT, true,
7859 &prolog_key, compiler, debug,
7860 si_build_ps_prolog_function,
7861 "Fragment Shader Prolog");
7862 if (!shader->prolog)
7863 return false;
7864 }
7865
7866 /* Get the epilog. */
7867 si_get_ps_epilog_key(shader, &epilog_key);
7868
7869 shader->epilog =
7870 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7871 PIPE_SHADER_FRAGMENT, false,
7872 &epilog_key, compiler, debug,
7873 si_build_ps_epilog_function,
7874 "Fragment Shader Epilog");
7875 if (!shader->epilog)
7876 return false;
7877
7878 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7879 if (shader->key.part.ps.prolog.poly_stipple) {
7880 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7881 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7882 }
7883
7884 /* Set up the enable bits for per-sample shading if needed. */
7885 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7886 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7887 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7888 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7889 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7890 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7891 }
7892 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7893 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7894 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7895 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7896 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7897 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7898 }
7899 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7900 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7901 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7902 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7903 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7904 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7905 }
7906 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7907 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7908 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7909 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7910 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7911 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7912 }
7913
7914 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7915 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7916 !(shader->config.spi_ps_input_ena & 0xf)) {
7917 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7918 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7919 }
7920
7921 /* At least one pair of interpolation weights must be enabled. */
7922 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7923 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7924 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7925 }
7926
7927 /* Samplemask fixup requires the sample ID. */
7928 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7929 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7930 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7931 }
7932
7933 /* The sample mask input is always enabled, because the API shader always
7934 * passes it through to the epilog. Disable it here if it's unused.
7935 */
7936 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7937 !shader->selector->info.reads_samplemask)
7938 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7939
7940 return true;
7941 }
7942
7943 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7944 unsigned *lds_size)
7945 {
7946 /* If tessellation is all offchip and on-chip GS isn't used, this
7947 * workaround is not needed.
7948 */
7949 return;
7950
7951 /* SPI barrier management bug:
7952 * Make sure we have at least 4k of LDS in use to avoid the bug.
7953 * It applies to workgroup sizes of more than one wavefront.
7954 */
7955 if (sscreen->info.family == CHIP_BONAIRE ||
7956 sscreen->info.family == CHIP_KABINI)
7957 *lds_size = MAX2(*lds_size, 8);
7958 }
7959
7960 static void si_fix_resource_usage(struct si_screen *sscreen,
7961 struct si_shader *shader)
7962 {
7963 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7964
7965 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7966
7967 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7968 si_get_max_workgroup_size(shader) > 64) {
7969 si_multiwave_lds_size_workaround(sscreen,
7970 &shader->config.lds_size);
7971 }
7972 }
7973
7974 int si_shader_create(struct si_screen *sscreen, struct ac_llvm_compiler *compiler,
7975 struct si_shader *shader,
7976 struct pipe_debug_callback *debug)
7977 {
7978 struct si_shader_selector *sel = shader->selector;
7979 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7980 int r;
7981
7982 /* LS, ES, VS are compiled on demand if the main part hasn't been
7983 * compiled for that stage.
7984 *
7985 * Vertex shaders are compiled on demand when a vertex fetch
7986 * workaround must be applied.
7987 */
7988 if (shader->is_monolithic) {
7989 /* Monolithic shader (compiled as a whole, has many variants,
7990 * may take a long time to compile).
7991 */
7992 r = si_compile_tgsi_shader(sscreen, compiler, shader, debug);
7993 if (r)
7994 return r;
7995 } else {
7996 /* The shader consists of several parts:
7997 *
7998 * - the middle part is the user shader, it has 1 variant only
7999 * and it was compiled during the creation of the shader
8000 * selector
8001 * - the prolog part is inserted at the beginning
8002 * - the epilog part is inserted at the end
8003 *
8004 * The prolog and epilog have many (but simple) variants.
8005 *
8006 * Starting with gfx9, geometry and tessellation control
8007 * shaders also contain the prolog and user shader parts of
8008 * the previous shader stage.
8009 */
8010
8011 if (!mainp)
8012 return -1;
8013
8014 /* Copy the compiled TGSI shader data over. */
8015 shader->is_binary_shared = true;
8016 shader->binary = mainp->binary;
8017 shader->config = mainp->config;
8018 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8019 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8020 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8021 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
8022 memcpy(shader->info.vs_output_param_offset,
8023 mainp->info.vs_output_param_offset,
8024 sizeof(mainp->info.vs_output_param_offset));
8025 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8026 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8027 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8028
8029 /* Select prologs and/or epilogs. */
8030 switch (sel->type) {
8031 case PIPE_SHADER_VERTEX:
8032 if (!si_shader_select_vs_parts(sscreen, compiler, shader, debug))
8033 return -1;
8034 break;
8035 case PIPE_SHADER_TESS_CTRL:
8036 if (!si_shader_select_tcs_parts(sscreen, compiler, shader, debug))
8037 return -1;
8038 break;
8039 case PIPE_SHADER_TESS_EVAL:
8040 break;
8041 case PIPE_SHADER_GEOMETRY:
8042 if (!si_shader_select_gs_parts(sscreen, compiler, shader, debug))
8043 return -1;
8044 break;
8045 case PIPE_SHADER_FRAGMENT:
8046 if (!si_shader_select_ps_parts(sscreen, compiler, shader, debug))
8047 return -1;
8048
8049 /* Make sure we have at least as many VGPRs as there
8050 * are allocated inputs.
8051 */
8052 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8053 shader->info.num_input_vgprs);
8054 break;
8055 }
8056
8057 /* Update SGPR and VGPR counts. */
8058 if (shader->prolog) {
8059 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8060 shader->prolog->config.num_sgprs);
8061 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8062 shader->prolog->config.num_vgprs);
8063 }
8064 if (shader->previous_stage) {
8065 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8066 shader->previous_stage->config.num_sgprs);
8067 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8068 shader->previous_stage->config.num_vgprs);
8069 shader->config.spilled_sgprs =
8070 MAX2(shader->config.spilled_sgprs,
8071 shader->previous_stage->config.spilled_sgprs);
8072 shader->config.spilled_vgprs =
8073 MAX2(shader->config.spilled_vgprs,
8074 shader->previous_stage->config.spilled_vgprs);
8075 shader->config.private_mem_vgprs =
8076 MAX2(shader->config.private_mem_vgprs,
8077 shader->previous_stage->config.private_mem_vgprs);
8078 shader->config.scratch_bytes_per_wave =
8079 MAX2(shader->config.scratch_bytes_per_wave,
8080 shader->previous_stage->config.scratch_bytes_per_wave);
8081 shader->info.uses_instanceid |=
8082 shader->previous_stage->info.uses_instanceid;
8083 }
8084 if (shader->prolog2) {
8085 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8086 shader->prolog2->config.num_sgprs);
8087 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8088 shader->prolog2->config.num_vgprs);
8089 }
8090 if (shader->epilog) {
8091 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8092 shader->epilog->config.num_sgprs);
8093 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8094 shader->epilog->config.num_vgprs);
8095 }
8096 si_calculate_max_simd_waves(shader);
8097 }
8098
8099 si_fix_resource_usage(sscreen, shader);
8100 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8101 stderr, true);
8102
8103 /* Upload. */
8104 r = si_shader_binary_upload(sscreen, shader);
8105 if (r) {
8106 fprintf(stderr, "LLVM failed to upload shader\n");
8107 return r;
8108 }
8109
8110 return 0;
8111 }
8112
8113 void si_shader_destroy(struct si_shader *shader)
8114 {
8115 if (shader->scratch_bo)
8116 si_resource_reference(&shader->scratch_bo, NULL);
8117
8118 si_resource_reference(&shader->bo, NULL);
8119
8120 if (!shader->is_binary_shared)
8121 ac_shader_binary_clean(&shader->binary);
8122
8123 free(shader->shader_log);
8124 }