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winsys/radeon: fix a race condition between winsys_create and winsys_destroy
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "radeon_llvm.h"
36 #include "radeon_llvm_emit.h"
37 #include "util/u_memory.h"
38 #include "tgsi/tgsi_parse.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "si_pipe.h"
43 #include "si_shader.h"
44 #include "sid.h"
45
46 #include <errno.h>
47
48 struct si_shader_output_values
49 {
50 LLVMValueRef values[4];
51 unsigned name;
52 unsigned index;
53 unsigned sid;
54 unsigned usage;
55 };
56
57 struct si_shader_context
58 {
59 struct radeon_llvm_context radeon_bld;
60 struct tgsi_parse_context parse;
61 struct tgsi_token * tokens;
62 struct si_pipe_shader *shader;
63 struct si_shader *gs_for_vs;
64 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
65 int param_streamout_config;
66 int param_streamout_write_index;
67 int param_streamout_offset[4];
68 int param_vertex_id;
69 int param_instance_id;
70 LLVMValueRef const_md;
71 LLVMValueRef const_resource[NUM_CONST_BUFFERS];
72 #if HAVE_LLVM >= 0x0304
73 LLVMValueRef ddxy_lds;
74 #endif
75 LLVMValueRef *constants[NUM_CONST_BUFFERS];
76 LLVMValueRef *resources;
77 LLVMValueRef *samplers;
78 LLVMValueRef so_buffers[4];
79 LLVMValueRef gs_next_vertex;
80 };
81
82 static struct si_shader_context * si_shader_context(
83 struct lp_build_tgsi_context * bld_base)
84 {
85 return (struct si_shader_context *)bld_base;
86 }
87
88
89 #define PERSPECTIVE_BASE 0
90 #define LINEAR_BASE 9
91
92 #define SAMPLE_OFFSET 0
93 #define CENTER_OFFSET 2
94 #define CENTROID_OFSET 4
95
96 #define USE_SGPR_MAX_SUFFIX_LEN 5
97 #define CONST_ADDR_SPACE 2
98 #define LOCAL_ADDR_SPACE 3
99 #define USER_SGPR_ADDR_SPACE 8
100
101
102 #define SENDMSG_GS 2
103 #define SENDMSG_GS_DONE 3
104
105 #define SENDMSG_GS_OP_NOP (0 << 4)
106 #define SENDMSG_GS_OP_CUT (1 << 4)
107 #define SENDMSG_GS_OP_EMIT (2 << 4)
108 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
109
110
111 /**
112 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
113 *
114 * @param offset The offset parameter specifies the number of
115 * elements to offset, not the number of bytes or dwords. An element is the
116 * the type pointed to by the base_ptr parameter (e.g. int is the element of
117 * an int* pointer)
118 *
119 * When LLVM lowers the load instruction, it will convert the element offset
120 * into a dword offset automatically.
121 *
122 */
123 static LLVMValueRef build_indexed_load(
124 struct si_shader_context * si_shader_ctx,
125 LLVMValueRef base_ptr,
126 LLVMValueRef offset)
127 {
128 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
129
130 LLVMValueRef indices[2] = {
131 LLVMConstInt(LLVMInt64TypeInContext(base->gallivm->context), 0, false),
132 offset
133 };
134 LLVMValueRef computed_ptr = LLVMBuildGEP(
135 base->gallivm->builder, base_ptr, indices, 2, "");
136
137 LLVMValueRef result = LLVMBuildLoad(base->gallivm->builder, computed_ptr, "");
138 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
139 return result;
140 }
141
142 static LLVMValueRef get_instance_index_for_fetch(
143 struct radeon_llvm_context * radeon_bld,
144 unsigned divisor)
145 {
146 struct si_shader_context *si_shader_ctx =
147 si_shader_context(&radeon_bld->soa.bld_base);
148 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
149
150 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
151 si_shader_ctx->param_instance_id);
152 result = LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
153 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
154
155 if (divisor > 1)
156 result = LLVMBuildUDiv(gallivm->builder, result,
157 lp_build_const_int32(gallivm, divisor), "");
158
159 return result;
160 }
161
162 static int si_store_shader_io_attribs(struct si_shader *shader,
163 const struct tgsi_full_declaration *d)
164 {
165 int i = -1;
166
167 switch (d->Declaration.File) {
168 case TGSI_FILE_INPUT:
169 i = shader->ninput++;
170 assert(i < Elements(shader->input));
171 shader->input[i].name = d->Semantic.Name;
172 shader->input[i].sid = d->Semantic.Index;
173 shader->input[i].index = d->Range.First;
174 shader->input[i].interpolate = d->Interp.Interpolate;
175 shader->input[i].centroid = d->Interp.Centroid;
176 return -1;
177
178 case TGSI_FILE_OUTPUT:
179 i = shader->noutput++;
180 assert(i < Elements(shader->output));
181 shader->output[i].name = d->Semantic.Name;
182 shader->output[i].sid = d->Semantic.Index;
183 shader->output[i].index = d->Range.First;
184 shader->output[i].usage = d->Declaration.UsageMask;
185 break;
186 }
187
188 return i;
189 }
190
191 static void declare_input_vs(
192 struct radeon_llvm_context *radeon_bld,
193 unsigned input_index,
194 const struct tgsi_full_declaration *decl)
195 {
196 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
197 struct gallivm_state *gallivm = base->gallivm;
198 struct si_shader_context *si_shader_ctx =
199 si_shader_context(&radeon_bld->soa.bld_base);
200 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
201
202 unsigned chan;
203
204 LLVMValueRef t_list_ptr;
205 LLVMValueRef t_offset;
206 LLVMValueRef t_list;
207 LLVMValueRef attribute_offset;
208 LLVMValueRef buffer_index;
209 LLVMValueRef args[3];
210 LLVMTypeRef vec4_type;
211 LLVMValueRef input;
212
213 /* Load the T list */
214 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
215
216 t_offset = lp_build_const_int32(gallivm, input_index);
217
218 t_list = build_indexed_load(si_shader_ctx, t_list_ptr, t_offset);
219
220 /* Build the attribute offset */
221 attribute_offset = lp_build_const_int32(gallivm, 0);
222
223 if (divisor) {
224 /* Build index from instance ID, start instance and divisor */
225 si_shader_ctx->shader->shader.uses_instanceid = true;
226 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
227 } else {
228 /* Load the buffer index, which is always stored in VGPR0
229 * for Vertex Shaders */
230 buffer_index = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
231 si_shader_ctx->param_vertex_id);
232 }
233
234 vec4_type = LLVMVectorType(base->elem_type, 4);
235 args[0] = t_list;
236 args[1] = attribute_offset;
237 args[2] = buffer_index;
238 input = build_intrinsic(gallivm->builder,
239 "llvm.SI.vs.load.input", vec4_type, args, 3,
240 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
241
242 /* Break up the vec4 into individual components */
243 for (chan = 0; chan < 4; chan++) {
244 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
245 /* XXX: Use a helper function for this. There is one in
246 * tgsi_llvm.c. */
247 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
248 LLVMBuildExtractElement(gallivm->builder,
249 input, llvm_chan, "");
250 }
251 }
252
253 static void declare_input_gs(
254 struct radeon_llvm_context *radeon_bld,
255 unsigned input_index,
256 const struct tgsi_full_declaration *decl)
257 {
258 struct si_shader_context *si_shader_ctx =
259 si_shader_context(&radeon_bld->soa.bld_base);
260 struct si_shader *shader = &si_shader_ctx->shader->shader;
261
262 si_store_shader_io_attribs(shader, decl);
263
264 if (decl->Semantic.Name != TGSI_SEMANTIC_PRIMID)
265 shader->input[input_index].param_offset = shader->nparam++;
266 }
267
268 static LLVMValueRef fetch_input_gs(
269 struct lp_build_tgsi_context *bld_base,
270 const struct tgsi_full_src_register *reg,
271 enum tgsi_opcode_type type,
272 unsigned swizzle)
273 {
274 struct lp_build_context *base = &bld_base->base;
275 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
276 struct si_shader *shader = &si_shader_ctx->shader->shader;
277 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
278 struct gallivm_state *gallivm = base->gallivm;
279 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
280 LLVMValueRef vtx_offset;
281 LLVMValueRef t_list_ptr;
282 LLVMValueRef t_list;
283 LLVMValueRef args[9];
284 unsigned vtx_offset_param;
285
286 if (swizzle != ~0 &&
287 shader->input[reg->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
288 if (swizzle == 0)
289 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
290 SI_PARAM_PRIMITIVE_ID);
291 else
292 return uint->zero;
293 }
294
295 if (!reg->Register.Dimension)
296 return NULL;
297
298 if (swizzle == ~0) {
299 LLVMValueRef values[TGSI_NUM_CHANNELS];
300 unsigned chan;
301 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
302 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
303 }
304 return lp_build_gather_values(bld_base->base.gallivm, values,
305 TGSI_NUM_CHANNELS);
306 }
307
308 /* Get the vertex offset parameter */
309 vtx_offset_param = reg->Dimension.Index;
310 if (vtx_offset_param < 2) {
311 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
312 } else {
313 assert(vtx_offset_param < 6);
314 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
315 }
316 vtx_offset = lp_build_mul_imm(uint,
317 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
318 vtx_offset_param),
319 4);
320
321 /* Load the ESGS ring resource descriptor */
322 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
323 SI_PARAM_RW_BUFFERS);
324 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
325 lp_build_const_int32(gallivm, SI_RING_ESGS));
326
327 args[0] = t_list;
328 args[1] = vtx_offset;
329 args[2] = lp_build_const_int32(gallivm,
330 ((shader->input[reg->Register.Index].param_offset * 4) +
331 swizzle) * 256);
332 args[3] = uint->zero;
333 args[4] = uint->one; /* OFFEN */
334 args[5] = uint->zero; /* IDXEN */
335 args[6] = uint->one; /* GLC */
336 args[7] = uint->zero; /* SLC */
337 args[8] = uint->zero; /* TFE */
338
339 return LLVMBuildBitCast(gallivm->builder,
340 build_intrinsic(gallivm->builder,
341 "llvm.SI.buffer.load.dword.i32.i32",
342 i32, args, 9,
343 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
344 tgsi2llvmtype(bld_base, type), "");
345 }
346
347 static void declare_input_fs(
348 struct radeon_llvm_context *radeon_bld,
349 unsigned input_index,
350 const struct tgsi_full_declaration *decl)
351 {
352 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
353 struct si_shader_context *si_shader_ctx =
354 si_shader_context(&radeon_bld->soa.bld_base);
355 struct si_shader *shader = &si_shader_ctx->shader->shader;
356 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
357 struct gallivm_state *gallivm = base->gallivm;
358 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
359 LLVMValueRef main_fn = radeon_bld->main_fn;
360
361 LLVMValueRef interp_param;
362 const char * intr_name;
363
364 /* This value is:
365 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
366 * quad begins a new primitive. Bit 0 always needs
367 * to be unset)
368 * [32:16] ParamOffset
369 *
370 */
371 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
372 LLVMValueRef attr_number;
373
374 unsigned chan;
375
376 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
377 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
378 unsigned soa_index =
379 radeon_llvm_reg_index_soa(input_index, chan);
380 radeon_bld->inputs[soa_index] =
381 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
382
383 if (chan == 3)
384 /* RCP for fragcoord.w */
385 radeon_bld->inputs[soa_index] =
386 LLVMBuildFDiv(gallivm->builder,
387 lp_build_const_float(gallivm, 1.0f),
388 radeon_bld->inputs[soa_index],
389 "");
390 }
391 return;
392 }
393
394 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
395 LLVMValueRef face, is_face_positive;
396
397 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
398
399 is_face_positive = LLVMBuildFCmp(gallivm->builder,
400 LLVMRealUGT, face,
401 lp_build_const_float(gallivm, 0.0f),
402 "");
403
404 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
405 LLVMBuildSelect(gallivm->builder,
406 is_face_positive,
407 lp_build_const_float(gallivm, 1.0f),
408 lp_build_const_float(gallivm, 0.0f),
409 "");
410 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
411 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
412 lp_build_const_float(gallivm, 0.0f);
413 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
414 lp_build_const_float(gallivm, 1.0f);
415
416 return;
417 }
418
419 shader->input[input_index].param_offset = shader->nparam++;
420 attr_number = lp_build_const_int32(gallivm,
421 shader->input[input_index].param_offset);
422
423 switch (decl->Interp.Interpolate) {
424 case TGSI_INTERPOLATE_COLOR:
425 if (si_shader_ctx->shader->key.ps.flatshade) {
426 interp_param = 0;
427 } else {
428 if (decl->Interp.Centroid)
429 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
430 else
431 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
432 }
433 break;
434 case TGSI_INTERPOLATE_CONSTANT:
435 interp_param = 0;
436 break;
437 case TGSI_INTERPOLATE_LINEAR:
438 if (decl->Interp.Centroid)
439 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
440 else
441 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
442 break;
443 case TGSI_INTERPOLATE_PERSPECTIVE:
444 if (decl->Interp.Centroid)
445 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
446 else
447 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
448 break;
449 default:
450 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
451 return;
452 }
453
454 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
455
456 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
457 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
458 si_shader_ctx->shader->key.ps.color_two_side) {
459 LLVMValueRef args[4];
460 LLVMValueRef face, is_face_positive;
461 LLVMValueRef back_attr_number =
462 lp_build_const_int32(gallivm,
463 shader->input[input_index].param_offset + 1);
464
465 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
466
467 is_face_positive = LLVMBuildFCmp(gallivm->builder,
468 LLVMRealUGT, face,
469 lp_build_const_float(gallivm, 0.0f),
470 "");
471
472 args[2] = params;
473 args[3] = interp_param;
474 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
475 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
476 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
477 LLVMValueRef front, back;
478
479 args[0] = llvm_chan;
480 args[1] = attr_number;
481 front = build_intrinsic(gallivm->builder, intr_name,
482 input_type, args, args[3] ? 4 : 3,
483 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
484
485 args[1] = back_attr_number;
486 back = build_intrinsic(gallivm->builder, intr_name,
487 input_type, args, args[3] ? 4 : 3,
488 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
489
490 radeon_bld->inputs[soa_index] =
491 LLVMBuildSelect(gallivm->builder,
492 is_face_positive,
493 front,
494 back,
495 "");
496 }
497
498 shader->nparam++;
499 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
500 LLVMValueRef args[4];
501
502 args[0] = uint->zero;
503 args[1] = attr_number;
504 args[2] = params;
505 args[3] = interp_param;
506 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
507 build_intrinsic(gallivm->builder, intr_name,
508 input_type, args, args[3] ? 4 : 3,
509 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
510 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
511 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
512 lp_build_const_float(gallivm, 0.0f);
513 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
514 lp_build_const_float(gallivm, 1.0f);
515 } else {
516 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
517 LLVMValueRef args[4];
518 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
519 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
520 args[0] = llvm_chan;
521 args[1] = attr_number;
522 args[2] = params;
523 args[3] = interp_param;
524 radeon_bld->inputs[soa_index] =
525 build_intrinsic(gallivm->builder, intr_name,
526 input_type, args, args[3] ? 4 : 3,
527 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
528 }
529 }
530 }
531
532 static void declare_system_value(
533 struct radeon_llvm_context * radeon_bld,
534 unsigned index,
535 const struct tgsi_full_declaration *decl)
536 {
537 struct si_shader_context *si_shader_ctx =
538 si_shader_context(&radeon_bld->soa.bld_base);
539 LLVMValueRef value = 0;
540
541 switch (decl->Semantic.Name) {
542 case TGSI_SEMANTIC_INSTANCEID:
543 value = LLVMGetParam(radeon_bld->main_fn,
544 si_shader_ctx->param_instance_id);
545 break;
546
547 case TGSI_SEMANTIC_VERTEXID:
548 value = LLVMGetParam(radeon_bld->main_fn,
549 si_shader_ctx->param_vertex_id);
550 break;
551
552 default:
553 assert(!"unknown system value");
554 return;
555 }
556
557 radeon_bld->system_values[index] = value;
558 }
559
560 static LLVMValueRef fetch_constant(
561 struct lp_build_tgsi_context * bld_base,
562 const struct tgsi_full_src_register *reg,
563 enum tgsi_opcode_type type,
564 unsigned swizzle)
565 {
566 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
567 struct lp_build_context * base = &bld_base->base;
568 const struct tgsi_ind_register *ireg = &reg->Indirect;
569 unsigned buf, idx;
570
571 LLVMValueRef args[2];
572 LLVMValueRef addr;
573 LLVMValueRef result;
574
575 if (swizzle == LP_CHAN_ALL) {
576 unsigned chan;
577 LLVMValueRef values[4];
578 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
579 values[chan] = fetch_constant(bld_base, reg, type, chan);
580
581 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
582 }
583
584 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
585 idx = reg->Register.Index * 4 + swizzle;
586
587 if (!reg->Register.Indirect)
588 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
589
590 args[0] = si_shader_ctx->const_resource[buf];
591 args[1] = lp_build_const_int32(base->gallivm, idx * 4);
592 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
593 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
594 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
595 args[1] = lp_build_add(&bld_base->uint_bld, addr, args[1]);
596
597 result = build_intrinsic(base->gallivm->builder, "llvm.SI.load.const", base->elem_type,
598 args, 2, LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
599
600 return bitcast(bld_base, type, result);
601 }
602
603 /* Initialize arguments for the shader export intrinsic */
604 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
605 LLVMValueRef *values,
606 unsigned target,
607 LLVMValueRef *args)
608 {
609 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
610 struct lp_build_context *uint =
611 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
612 struct lp_build_context *base = &bld_base->base;
613 unsigned compressed = 0;
614 unsigned chan;
615
616 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
617 int cbuf = target - V_008DFC_SQ_EXP_MRT;
618
619 if (cbuf >= 0 && cbuf < 8) {
620 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
621
622 if (compressed)
623 si_shader_ctx->shader->spi_shader_col_format |=
624 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
625 else
626 si_shader_ctx->shader->spi_shader_col_format |=
627 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
628
629 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
630 }
631 }
632
633 if (compressed) {
634 /* Pixel shader needs to pack output values before export */
635 for (chan = 0; chan < 2; chan++ ) {
636 args[0] = values[2 * chan];
637 args[1] = values[2 * chan + 1];
638 args[chan + 5] =
639 build_intrinsic(base->gallivm->builder,
640 "llvm.SI.packf16",
641 LLVMInt32TypeInContext(base->gallivm->context),
642 args, 2,
643 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
644 args[chan + 7] = args[chan + 5] =
645 LLVMBuildBitCast(base->gallivm->builder,
646 args[chan + 5],
647 LLVMFloatTypeInContext(base->gallivm->context),
648 "");
649 }
650
651 /* Set COMPR flag */
652 args[4] = uint->one;
653 } else {
654 for (chan = 0; chan < 4; chan++ )
655 /* +5 because the first output value will be
656 * the 6th argument to the intrinsic. */
657 args[chan + 5] = values[chan];
658
659 /* Clear COMPR flag */
660 args[4] = uint->zero;
661 }
662
663 /* XXX: This controls which components of the output
664 * registers actually get exported. (e.g bit 0 means export
665 * X component, bit 1 means export Y component, etc.) I'm
666 * hard coding this to 0xf for now. In the future, we might
667 * want to do something else. */
668 args[0] = lp_build_const_int32(base->gallivm, 0xf);
669
670 /* Specify whether the EXEC mask represents the valid mask */
671 args[1] = uint->zero;
672
673 /* Specify whether this is the last export */
674 args[2] = uint->zero;
675
676 /* Specify the target we are exporting */
677 args[3] = lp_build_const_int32(base->gallivm, target);
678
679 /* XXX: We probably need to keep track of the output
680 * values, so we know what we are passing to the next
681 * stage. */
682 }
683
684 /* Load from output pointers and initialize arguments for the shader export intrinsic */
685 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
686 LLVMValueRef *out_ptr,
687 unsigned target,
688 LLVMValueRef *args)
689 {
690 struct gallivm_state *gallivm = bld_base->base.gallivm;
691 LLVMValueRef values[4];
692 int i;
693
694 for (i = 0; i < 4; i++)
695 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
696
697 si_llvm_init_export_args(bld_base, values, target, args);
698 }
699
700 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
701 LLVMValueRef *out_ptr)
702 {
703 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
704 struct gallivm_state *gallivm = bld_base->base.gallivm;
705
706 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
707 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
708 SI_PARAM_ALPHA_REF);
709
710 LLVMValueRef alpha_pass =
711 lp_build_cmp(&bld_base->base,
712 si_shader_ctx->shader->key.ps.alpha_func,
713 LLVMBuildLoad(gallivm->builder, out_ptr[3], ""),
714 alpha_ref);
715 LLVMValueRef arg =
716 lp_build_select(&bld_base->base,
717 alpha_pass,
718 lp_build_const_float(gallivm, 1.0f),
719 lp_build_const_float(gallivm, -1.0f));
720
721 build_intrinsic(gallivm->builder,
722 "llvm.AMDGPU.kill",
723 LLVMVoidTypeInContext(gallivm->context),
724 &arg, 1, 0);
725 } else {
726 build_intrinsic(gallivm->builder,
727 "llvm.AMDGPU.kilp",
728 LLVMVoidTypeInContext(gallivm->context),
729 NULL, 0, 0);
730 }
731 }
732
733 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
734 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
735 {
736 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
737 struct si_pipe_shader *shader = si_shader_ctx->shader;
738 struct lp_build_context *base = &bld_base->base;
739 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
740 unsigned reg_index;
741 unsigned chan;
742 unsigned const_chan;
743 LLVMValueRef base_elt;
744 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
745 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, NUM_PIPE_CONST_BUFFERS);
746 LLVMValueRef const_resource = build_indexed_load(si_shader_ctx, ptr, constbuf_index);
747
748 for (reg_index = 0; reg_index < 2; reg_index ++) {
749 LLVMValueRef *args = pos[2 + reg_index];
750
751 if (!(shader->key.vs.ucps_enabled & (1 << reg_index)))
752 continue;
753
754 shader->shader.clip_dist_write |= 0xf << (4 * reg_index);
755
756 args[5] =
757 args[6] =
758 args[7] =
759 args[8] = lp_build_const_float(base->gallivm, 0.0f);
760
761 /* Compute dot products of position and user clip plane vectors */
762 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
763 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
764 args[0] = const_resource;
765 args[1] = lp_build_const_int32(base->gallivm,
766 ((reg_index * 4 + chan) * 4 +
767 const_chan) * 4);
768 base_elt = build_intrinsic(base->gallivm->builder,
769 "llvm.SI.load.const",
770 base->elem_type,
771 args, 2,
772 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
773 args[5 + chan] =
774 lp_build_add(base, args[5 + chan],
775 lp_build_mul(base, base_elt,
776 out_elts[const_chan]));
777 }
778 }
779
780 args[0] = lp_build_const_int32(base->gallivm, 0xf);
781 args[1] = uint->zero;
782 args[2] = uint->zero;
783 args[3] = lp_build_const_int32(base->gallivm,
784 V_008DFC_SQ_EXP_POS + 2 + reg_index);
785 args[4] = uint->zero;
786 }
787 }
788
789 static void si_dump_streamout(struct pipe_stream_output_info *so)
790 {
791 unsigned i;
792
793 if (so->num_outputs)
794 fprintf(stderr, "STREAMOUT\n");
795
796 for (i = 0; i < so->num_outputs; i++) {
797 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
798 so->output[i].start_component;
799 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
800 i, so->output[i].output_buffer,
801 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
802 so->output[i].register_index,
803 mask & 1 ? "x" : "",
804 mask & 2 ? "y" : "",
805 mask & 4 ? "z" : "",
806 mask & 8 ? "w" : "");
807 }
808 }
809
810 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
811 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
812 * or v4i32 (num_channels=3,4). */
813 static void build_tbuffer_store(struct si_shader_context *shader,
814 LLVMValueRef rsrc,
815 LLVMValueRef vdata,
816 unsigned num_channels,
817 LLVMValueRef vaddr,
818 LLVMValueRef soffset,
819 unsigned inst_offset,
820 unsigned dfmt,
821 unsigned nfmt,
822 unsigned offen,
823 unsigned idxen,
824 unsigned glc,
825 unsigned slc,
826 unsigned tfe)
827 {
828 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
829 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
830 LLVMValueRef args[] = {
831 rsrc,
832 vdata,
833 LLVMConstInt(i32, num_channels, 0),
834 vaddr,
835 soffset,
836 LLVMConstInt(i32, inst_offset, 0),
837 LLVMConstInt(i32, dfmt, 0),
838 LLVMConstInt(i32, nfmt, 0),
839 LLVMConstInt(i32, offen, 0),
840 LLVMConstInt(i32, idxen, 0),
841 LLVMConstInt(i32, glc, 0),
842 LLVMConstInt(i32, slc, 0),
843 LLVMConstInt(i32, tfe, 0)
844 };
845
846 /* The instruction offset field has 12 bits */
847 assert(offen || inst_offset < (1 << 12));
848
849 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
850 unsigned func = CLAMP(num_channels, 1, 3) - 1;
851 const char *types[] = {"i32", "v2i32", "v4i32"};
852 char name[256];
853 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
854
855 lp_build_intrinsic(gallivm->builder, name,
856 LLVMVoidTypeInContext(gallivm->context),
857 args, Elements(args));
858 }
859
860 static void build_streamout_store(struct si_shader_context *shader,
861 LLVMValueRef rsrc,
862 LLVMValueRef vdata,
863 unsigned num_channels,
864 LLVMValueRef vaddr,
865 LLVMValueRef soffset,
866 unsigned inst_offset)
867 {
868 static unsigned dfmt[] = {
869 V_008F0C_BUF_DATA_FORMAT_32,
870 V_008F0C_BUF_DATA_FORMAT_32_32,
871 V_008F0C_BUF_DATA_FORMAT_32_32_32,
872 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
873 };
874 assert(num_channels >= 1 && num_channels <= 4);
875
876 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
877 inst_offset, dfmt[num_channels-1],
878 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
879 }
880
881 /* On SI, the vertex shader is responsible for writing streamout data
882 * to buffers. */
883 static void si_llvm_emit_streamout(struct si_shader_context *shader,
884 struct si_shader_output_values *outputs,
885 unsigned noutput)
886 {
887 struct pipe_stream_output_info *so = &shader->shader->selector->so;
888 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
889 LLVMBuilderRef builder = gallivm->builder;
890 int i, j;
891 struct lp_build_if_state if_ctx;
892
893 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
894
895 LLVMValueRef so_param =
896 LLVMGetParam(shader->radeon_bld.main_fn,
897 shader->param_streamout_config);
898
899 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
900 LLVMValueRef so_vtx_count =
901 LLVMBuildAnd(builder,
902 LLVMBuildLShr(builder, so_param,
903 LLVMConstInt(i32, 16, 0), ""),
904 LLVMConstInt(i32, 127, 0), "");
905
906 LLVMValueRef tid = build_intrinsic(builder, "llvm.SI.tid", i32,
907 NULL, 0, LLVMReadNoneAttribute);
908
909 /* can_emit = tid < so_vtx_count; */
910 LLVMValueRef can_emit =
911 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
912
913 /* Emit the streamout code conditionally. This actually avoids
914 * out-of-bounds buffer access. The hw tells us via the SGPR
915 * (so_vtx_count) which threads are allowed to emit streamout data. */
916 lp_build_if(&if_ctx, gallivm, can_emit);
917 {
918 /* The buffer offset is computed as follows:
919 * ByteOffset = streamout_offset[buffer_id]*4 +
920 * (streamout_write_index + thread_id)*stride[buffer_id] +
921 * attrib_offset
922 */
923
924 LLVMValueRef so_write_index =
925 LLVMGetParam(shader->radeon_bld.main_fn,
926 shader->param_streamout_write_index);
927
928 /* Compute (streamout_write_index + thread_id). */
929 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
930
931 /* Compute the write offset for each enabled buffer. */
932 LLVMValueRef so_write_offset[4] = {};
933 for (i = 0; i < 4; i++) {
934 if (!so->stride[i])
935 continue;
936
937 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
938 shader->param_streamout_offset[i]);
939 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
940
941 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
942 LLVMConstInt(i32, so->stride[i]*4, 0), "");
943 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
944 }
945
946 /* Write streamout data. */
947 for (i = 0; i < so->num_outputs; i++) {
948 unsigned buf_idx = so->output[i].output_buffer;
949 unsigned reg = so->output[i].register_index;
950 unsigned start = so->output[i].start_component;
951 unsigned num_comps = so->output[i].num_components;
952 LLVMValueRef out[4];
953
954 assert(num_comps && num_comps <= 4);
955 if (!num_comps || num_comps > 4)
956 continue;
957
958 /* Load the output as int. */
959 for (j = 0; j < num_comps; j++) {
960 unsigned outidx = 0;
961
962 while (outidx < noutput && outputs[outidx].index != reg)
963 outidx++;
964
965 if (outidx < noutput)
966 out[j] = LLVMBuildBitCast(builder,
967 outputs[outidx].values[start+j],
968 i32, "");
969 else
970 out[j] = NULL;
971 }
972
973 if (!out[0])
974 continue;
975
976 /* Pack the output. */
977 LLVMValueRef vdata = NULL;
978
979 switch (num_comps) {
980 case 1: /* as i32 */
981 vdata = out[0];
982 break;
983 case 2: /* as v2i32 */
984 case 3: /* as v4i32 (aligned to 4) */
985 case 4: /* as v4i32 */
986 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
987 for (j = 0; j < num_comps; j++) {
988 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
989 LLVMConstInt(i32, j, 0), "");
990 }
991 break;
992 }
993
994 build_streamout_store(shader, shader->so_buffers[buf_idx],
995 vdata, num_comps,
996 so_write_offset[buf_idx],
997 LLVMConstInt(i32, 0, 0),
998 so->output[i].dst_offset*4);
999 }
1000 }
1001 lp_build_endif(&if_ctx);
1002 }
1003
1004
1005 /* Generate export instructions for hardware VS shader stage */
1006 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1007 struct si_shader_output_values *outputs,
1008 unsigned noutput)
1009 {
1010 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1011 struct si_shader * shader = &si_shader_ctx->shader->shader;
1012 struct lp_build_context * base = &bld_base->base;
1013 struct lp_build_context * uint =
1014 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1015 LLVMValueRef args[9];
1016 LLVMValueRef pos_args[4][9] = { { 0 } };
1017 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL;
1018 unsigned semantic_name, semantic_index, semantic_usage;
1019 unsigned target;
1020 unsigned param_count = 0;
1021 unsigned pos_idx;
1022 int i;
1023
1024 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1025 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1026 }
1027
1028 for (i = 0; i < noutput; i++) {
1029 semantic_name = outputs[i].name;
1030 semantic_index = outputs[i].sid;
1031 semantic_usage = outputs[i].usage;
1032
1033 handle_semantic:
1034 /* Select the correct target */
1035 switch(semantic_name) {
1036 case TGSI_SEMANTIC_PSIZE:
1037 shader->vs_out_misc_write = true;
1038 shader->vs_out_point_size = true;
1039 psize_value = outputs[i].values[0];
1040 continue;
1041 case TGSI_SEMANTIC_EDGEFLAG:
1042 shader->vs_out_misc_write = true;
1043 shader->vs_out_edgeflag = true;
1044 edgeflag_value = outputs[i].values[0];
1045 continue;
1046 case TGSI_SEMANTIC_LAYER:
1047 shader->vs_out_misc_write = true;
1048 shader->vs_out_layer = true;
1049 layer_value = outputs[i].values[0];
1050 continue;
1051 case TGSI_SEMANTIC_POSITION:
1052 target = V_008DFC_SQ_EXP_POS;
1053 break;
1054 case TGSI_SEMANTIC_COLOR:
1055 case TGSI_SEMANTIC_BCOLOR:
1056 target = V_008DFC_SQ_EXP_PARAM + param_count;
1057 shader->output[i].param_offset = param_count;
1058 param_count++;
1059 break;
1060 case TGSI_SEMANTIC_CLIPDIST:
1061 if (!(si_shader_ctx->shader->key.vs.ucps_enabled &
1062 (1 << semantic_index)))
1063 continue;
1064 shader->clip_dist_write |=
1065 semantic_usage << (semantic_index << 2);
1066 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1067 break;
1068 case TGSI_SEMANTIC_CLIPVERTEX:
1069 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1070 continue;
1071 case TGSI_SEMANTIC_PRIMID:
1072 case TGSI_SEMANTIC_FOG:
1073 case TGSI_SEMANTIC_GENERIC:
1074 target = V_008DFC_SQ_EXP_PARAM + param_count;
1075 shader->output[i].param_offset = param_count;
1076 param_count++;
1077 break;
1078 default:
1079 target = 0;
1080 fprintf(stderr,
1081 "Warning: SI unhandled vs output type:%d\n",
1082 semantic_name);
1083 }
1084
1085 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1086
1087 if (target >= V_008DFC_SQ_EXP_POS &&
1088 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1089 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1090 args, sizeof(args));
1091 } else {
1092 lp_build_intrinsic(base->gallivm->builder,
1093 "llvm.SI.export",
1094 LLVMVoidTypeInContext(base->gallivm->context),
1095 args, 9);
1096 }
1097
1098 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1099 semantic_name = TGSI_SEMANTIC_GENERIC;
1100 goto handle_semantic;
1101 }
1102 }
1103
1104 /* We need to add the position output manually if it's missing. */
1105 if (!pos_args[0][0]) {
1106 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1107 pos_args[0][1] = uint->zero; /* EXEC mask */
1108 pos_args[0][2] = uint->zero; /* last export? */
1109 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1110 pos_args[0][4] = uint->zero; /* COMPR flag */
1111 pos_args[0][5] = base->zero; /* X */
1112 pos_args[0][6] = base->zero; /* Y */
1113 pos_args[0][7] = base->zero; /* Z */
1114 pos_args[0][8] = base->one; /* W */
1115 }
1116
1117 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1118 if (shader->vs_out_misc_write) {
1119 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1120 shader->vs_out_point_size |
1121 (shader->vs_out_edgeflag << 1) |
1122 (shader->vs_out_layer << 2));
1123 pos_args[1][1] = uint->zero; /* EXEC mask */
1124 pos_args[1][2] = uint->zero; /* last export? */
1125 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1126 pos_args[1][4] = uint->zero; /* COMPR flag */
1127 pos_args[1][5] = base->zero; /* X */
1128 pos_args[1][6] = base->zero; /* Y */
1129 pos_args[1][7] = base->zero; /* Z */
1130 pos_args[1][8] = base->zero; /* W */
1131
1132 if (shader->vs_out_point_size)
1133 pos_args[1][5] = psize_value;
1134
1135 if (shader->vs_out_edgeflag) {
1136 /* The output is a float, but the hw expects an integer
1137 * with the first bit containing the edge flag. */
1138 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1139 edgeflag_value,
1140 bld_base->uint_bld.elem_type, "");
1141 edgeflag_value = lp_build_min(&bld_base->int_bld,
1142 edgeflag_value,
1143 bld_base->int_bld.one);
1144
1145 /* The LLVM intrinsic expects a float. */
1146 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1147 edgeflag_value,
1148 base->elem_type, "");
1149 }
1150
1151 if (shader->vs_out_layer)
1152 pos_args[1][7] = layer_value;
1153 }
1154
1155 for (i = 0; i < 4; i++)
1156 if (pos_args[i][0])
1157 shader->nr_pos_exports++;
1158
1159 pos_idx = 0;
1160 for (i = 0; i < 4; i++) {
1161 if (!pos_args[i][0])
1162 continue;
1163
1164 /* Specify the target we are exporting */
1165 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1166
1167 if (pos_idx == shader->nr_pos_exports)
1168 /* Specify that this is the last export */
1169 pos_args[i][2] = uint->one;
1170
1171 lp_build_intrinsic(base->gallivm->builder,
1172 "llvm.SI.export",
1173 LLVMVoidTypeInContext(base->gallivm->context),
1174 pos_args[i], 9);
1175 }
1176 }
1177
1178 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1179 {
1180 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1181 struct gallivm_state *gallivm = bld_base->base.gallivm;
1182 struct si_shader *es = &si_shader_ctx->shader->shader;
1183 struct si_shader *gs = si_shader_ctx->gs_for_vs;
1184 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1185 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1186 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1187 SI_PARAM_ES2GS_OFFSET);
1188 LLVMValueRef t_list_ptr;
1189 LLVMValueRef t_list;
1190 unsigned chan;
1191 int i;
1192
1193 while (!tgsi_parse_end_of_tokens(parse)) {
1194 struct tgsi_full_declaration *d =
1195 &parse->FullToken.FullDeclaration;
1196
1197 tgsi_parse_token(parse);
1198
1199 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1200 continue;
1201
1202 si_store_shader_io_attribs(es, d);
1203 }
1204
1205 /* Load the ESGS ring resource descriptor */
1206 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1207 SI_PARAM_RW_BUFFERS);
1208 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
1209 lp_build_const_int32(gallivm, SI_RING_ESGS));
1210
1211 for (i = 0; i < es->noutput; i++) {
1212 LLVMValueRef *out_ptr =
1213 si_shader_ctx->radeon_bld.soa.outputs[es->output[i].index];
1214 int j;
1215
1216 for (j = 0; j < gs->ninput; j++) {
1217 if (gs->input[j].name == es->output[i].name &&
1218 gs->input[j].sid == es->output[i].sid)
1219 break;
1220 }
1221 if (j == gs->ninput)
1222 continue;
1223
1224 for (chan = 0; chan < 4; chan++) {
1225 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1226 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1227
1228 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
1229 LLVMGetUndef(i32), soffset,
1230 (4 * gs->input[j].param_offset + chan) * 4,
1231 V_008F0C_BUF_DATA_FORMAT_32,
1232 V_008F0C_BUF_NUM_FORMAT_UINT,
1233 0, 0, 1, 1, 0);
1234 }
1235 }
1236 }
1237
1238 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
1239 {
1240 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1241 struct gallivm_state *gallivm = bld_base->base.gallivm;
1242 LLVMValueRef args[2];
1243
1244 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
1245 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1246 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1247 LLVMVoidTypeInContext(gallivm->context), args, 2,
1248 LLVMNoUnwindAttribute);
1249 }
1250
1251 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
1252 {
1253 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1254 struct gallivm_state *gallivm = bld_base->base.gallivm;
1255 struct si_pipe_shader *shader = si_shader_ctx->shader;
1256 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1257 struct si_shader_output_values *outputs = NULL;
1258 unsigned noutput = 0;
1259 int i;
1260
1261 while (!tgsi_parse_end_of_tokens(parse)) {
1262 struct tgsi_full_declaration *d =
1263 &parse->FullToken.FullDeclaration;
1264 unsigned index;
1265
1266 tgsi_parse_token(parse);
1267
1268 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1269 continue;
1270
1271 i = si_store_shader_io_attribs(&shader->shader, d);
1272 if (i < 0)
1273 continue;
1274
1275 outputs = REALLOC(outputs, noutput * sizeof(outputs[0]),
1276 (noutput + 1) * sizeof(outputs[0]));
1277 for (index = d->Range.First; index <= d->Range.Last; index++) {
1278 outputs[noutput].index = index;
1279 outputs[noutput].name = d->Semantic.Name;
1280 outputs[noutput].sid = d->Semantic.Index;
1281 outputs[noutput].usage = d->Declaration.UsageMask;
1282
1283 for (i = 0; i < 4; i++)
1284 outputs[noutput].values[i] =
1285 LLVMBuildLoad(gallivm->builder,
1286 si_shader_ctx->radeon_bld.soa.outputs[index][i],
1287 "");
1288 }
1289 noutput++;
1290 }
1291
1292 si_llvm_export_vs(bld_base, outputs, noutput);
1293 FREE(outputs);
1294 }
1295
1296 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
1297 {
1298 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1299 struct si_shader * shader = &si_shader_ctx->shader->shader;
1300 struct lp_build_context * base = &bld_base->base;
1301 struct lp_build_context * uint =
1302 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1303 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1304 LLVMValueRef args[9];
1305 LLVMValueRef last_args[9] = { 0 };
1306 unsigned semantic_name;
1307 int depth_index = -1, stencil_index = -1;
1308 int i;
1309
1310 while (!tgsi_parse_end_of_tokens(parse)) {
1311 struct tgsi_full_declaration *d =
1312 &parse->FullToken.FullDeclaration;
1313 unsigned target;
1314 unsigned index;
1315
1316 tgsi_parse_token(parse);
1317
1318 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_PROPERTY &&
1319 parse->FullToken.FullProperty.Property.PropertyName ==
1320 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS)
1321 shader->fs_write_all = TRUE;
1322
1323 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1324 continue;
1325
1326 i = si_store_shader_io_attribs(shader, d);
1327 if (i < 0)
1328 continue;
1329
1330 semantic_name = d->Semantic.Name;
1331 for (index = d->Range.First; index <= d->Range.Last; index++) {
1332 /* Select the correct target */
1333 switch(semantic_name) {
1334 case TGSI_SEMANTIC_POSITION:
1335 depth_index = index;
1336 continue;
1337 case TGSI_SEMANTIC_STENCIL:
1338 stencil_index = index;
1339 continue;
1340 case TGSI_SEMANTIC_COLOR:
1341 target = V_008DFC_SQ_EXP_MRT + d->Semantic.Index;
1342 if (si_shader_ctx->shader->key.ps.alpha_to_one)
1343 LLVMBuildStore(bld_base->base.gallivm->builder,
1344 bld_base->base.one,
1345 si_shader_ctx->radeon_bld.soa.outputs[index][3]);
1346
1347 if (d->Semantic.Index == 0 &&
1348 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
1349 si_alpha_test(bld_base,
1350 si_shader_ctx->radeon_bld.soa.outputs[index]);
1351 break;
1352 default:
1353 target = 0;
1354 fprintf(stderr,
1355 "Warning: SI unhandled fs output type:%d\n",
1356 semantic_name);
1357 }
1358
1359 si_llvm_init_export_args_load(bld_base,
1360 si_shader_ctx->radeon_bld.soa.outputs[index],
1361 target, args);
1362
1363 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1364 /* If there is an export instruction waiting to be emitted, do so now. */
1365 if (last_args[0]) {
1366 lp_build_intrinsic(base->gallivm->builder,
1367 "llvm.SI.export",
1368 LLVMVoidTypeInContext(base->gallivm->context),
1369 last_args, 9);
1370 }
1371
1372 /* This instruction will be emitted at the end of the shader. */
1373 memcpy(last_args, args, sizeof(args));
1374
1375 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
1376 if (shader->fs_write_all && shader->output[i].sid == 0 &&
1377 si_shader_ctx->shader->key.ps.nr_cbufs > 1) {
1378 for (int c = 1; c < si_shader_ctx->shader->key.ps.nr_cbufs; c++) {
1379 si_llvm_init_export_args_load(bld_base,
1380 si_shader_ctx->radeon_bld.soa.outputs[index],
1381 V_008DFC_SQ_EXP_MRT + c, args);
1382 lp_build_intrinsic(base->gallivm->builder,
1383 "llvm.SI.export",
1384 LLVMVoidTypeInContext(base->gallivm->context),
1385 args, 9);
1386 }
1387 }
1388 } else {
1389 lp_build_intrinsic(base->gallivm->builder,
1390 "llvm.SI.export",
1391 LLVMVoidTypeInContext(base->gallivm->context),
1392 args, 9);
1393 }
1394 }
1395 }
1396
1397 if (depth_index >= 0 || stencil_index >= 0) {
1398 LLVMValueRef out_ptr;
1399 unsigned mask = 0;
1400
1401 /* Specify the target we are exporting */
1402 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
1403
1404 if (depth_index >= 0) {
1405 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
1406 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1407 mask |= 0x1;
1408
1409 if (stencil_index < 0) {
1410 args[6] =
1411 args[7] =
1412 args[8] = args[5];
1413 }
1414 }
1415
1416 if (stencil_index >= 0) {
1417 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
1418 args[7] =
1419 args[8] =
1420 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1421 /* Only setting the stencil component bit (0x2) here
1422 * breaks some stencil piglit tests
1423 */
1424 mask |= 0x3;
1425
1426 if (depth_index < 0)
1427 args[5] = args[6];
1428 }
1429
1430 /* Specify which components to enable */
1431 args[0] = lp_build_const_int32(base->gallivm, mask);
1432
1433 args[1] =
1434 args[2] =
1435 args[4] = uint->zero;
1436
1437 if (last_args[0])
1438 lp_build_intrinsic(base->gallivm->builder,
1439 "llvm.SI.export",
1440 LLVMVoidTypeInContext(base->gallivm->context),
1441 args, 9);
1442 else
1443 memcpy(last_args, args, sizeof(args));
1444 }
1445
1446 if (!last_args[0]) {
1447 /* Specify which components to enable */
1448 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
1449
1450 /* Specify the target we are exporting */
1451 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
1452
1453 /* Set COMPR flag to zero to export data as 32-bit */
1454 last_args[4] = uint->zero;
1455
1456 /* dummy bits */
1457 last_args[5]= uint->zero;
1458 last_args[6]= uint->zero;
1459 last_args[7]= uint->zero;
1460 last_args[8]= uint->zero;
1461
1462 si_shader_ctx->shader->spi_shader_col_format |=
1463 V_028714_SPI_SHADER_32_ABGR;
1464 si_shader_ctx->shader->cb_shader_mask |= S_02823C_OUTPUT0_ENABLE(0xf);
1465 }
1466
1467 /* Specify whether the EXEC mask represents the valid mask */
1468 last_args[1] = uint->one;
1469
1470 /* Specify that this is the last export */
1471 last_args[2] = lp_build_const_int32(base->gallivm, 1);
1472
1473 lp_build_intrinsic(base->gallivm->builder,
1474 "llvm.SI.export",
1475 LLVMVoidTypeInContext(base->gallivm->context),
1476 last_args, 9);
1477 }
1478
1479 static const struct lp_build_tgsi_action txf_action;
1480
1481 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1482 struct lp_build_tgsi_context * bld_base,
1483 struct lp_build_emit_data * emit_data);
1484
1485 static void tex_fetch_args(
1486 struct lp_build_tgsi_context * bld_base,
1487 struct lp_build_emit_data * emit_data)
1488 {
1489 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1490 struct gallivm_state *gallivm = bld_base->base.gallivm;
1491 const struct tgsi_full_instruction * inst = emit_data->inst;
1492 unsigned opcode = inst->Instruction.Opcode;
1493 unsigned target = inst->Texture.Texture;
1494 LLVMValueRef coords[4];
1495 LLVMValueRef address[16];
1496 int ref_pos;
1497 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
1498 unsigned count = 0;
1499 unsigned chan;
1500 unsigned sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1501 unsigned sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
1502
1503 if (target == TGSI_TEXTURE_BUFFER) {
1504 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
1505 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
1506 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
1507 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
1508
1509 /* Truncate v32i8 to v16i8. */
1510 LLVMValueRef res = si_shader_ctx->resources[sampler_index];
1511 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
1512 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.zero, "");
1513 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
1514
1515 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
1516 emit_data->args[0] = res;
1517 emit_data->args[1] = bld_base->uint_bld.zero;
1518 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
1519 emit_data->arg_count = 3;
1520 return;
1521 }
1522
1523 /* Fetch and project texture coordinates */
1524 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1525 for (chan = 0; chan < 3; chan++ ) {
1526 coords[chan] = lp_build_emit_fetch(bld_base,
1527 emit_data->inst, 0,
1528 chan);
1529 if (opcode == TGSI_OPCODE_TXP)
1530 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1531 TGSI_OPCODE_DIV,
1532 coords[chan],
1533 coords[3]);
1534 }
1535
1536 if (opcode == TGSI_OPCODE_TXP)
1537 coords[3] = bld_base->base.one;
1538
1539 /* Pack LOD bias value */
1540 if (opcode == TGSI_OPCODE_TXB)
1541 address[count++] = coords[3];
1542
1543 if (target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE)
1544 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
1545
1546 /* Pack depth comparison value */
1547 switch (target) {
1548 case TGSI_TEXTURE_SHADOW1D:
1549 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1550 case TGSI_TEXTURE_SHADOW2D:
1551 case TGSI_TEXTURE_SHADOWRECT:
1552 case TGSI_TEXTURE_SHADOWCUBE:
1553 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1554 assert(ref_pos >= 0);
1555 address[count++] = coords[ref_pos];
1556 break;
1557 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1558 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1559 }
1560
1561 /* Pack user derivatives */
1562 if (opcode == TGSI_OPCODE_TXD) {
1563 for (chan = 0; chan < 2; chan++) {
1564 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, chan);
1565 if (num_coords > 1)
1566 address[count++] = lp_build_emit_fetch(bld_base, inst, 2, chan);
1567 }
1568 }
1569
1570 /* Pack texture coordinates */
1571 address[count++] = coords[0];
1572 if (num_coords > 1)
1573 address[count++] = coords[1];
1574 if (num_coords > 2)
1575 address[count++] = coords[2];
1576
1577 /* Pack LOD or sample index */
1578 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1579 address[count++] = coords[3];
1580
1581 if (count > 16) {
1582 assert(!"Cannot handle more than 16 texture address parameters");
1583 count = 16;
1584 }
1585
1586 for (chan = 0; chan < count; chan++ ) {
1587 address[chan] = LLVMBuildBitCast(gallivm->builder,
1588 address[chan],
1589 LLVMInt32TypeInContext(gallivm->context),
1590 "");
1591 }
1592
1593 /* Adjust the sample index according to FMASK.
1594 *
1595 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1596 * which is the identity mapping. Each nibble says which physical sample
1597 * should be fetched to get that sample.
1598 *
1599 * For example, 0x11111100 means there are only 2 samples stored and
1600 * the second sample covers 3/4 of the pixel. When reading samples 0
1601 * and 1, return physical sample 0 (determined by the first two 0s
1602 * in FMASK), otherwise return physical sample 1.
1603 *
1604 * The sample index should be adjusted as follows:
1605 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1606 */
1607 if (target == TGSI_TEXTURE_2D_MSAA ||
1608 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1609 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1610 struct lp_build_emit_data txf_emit_data = *emit_data;
1611 LLVMValueRef txf_address[4];
1612 unsigned txf_count = count;
1613
1614 memcpy(txf_address, address, sizeof(txf_address));
1615
1616 if (target == TGSI_TEXTURE_2D_MSAA) {
1617 txf_address[2] = bld_base->uint_bld.zero;
1618 }
1619 txf_address[3] = bld_base->uint_bld.zero;
1620
1621 /* Pad to a power-of-two size. */
1622 while (txf_count < util_next_power_of_two(txf_count))
1623 txf_address[txf_count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1624
1625 /* Read FMASK using TXF. */
1626 txf_emit_data.chan = 0;
1627 txf_emit_data.dst_type = LLVMVectorType(
1628 LLVMInt32TypeInContext(bld_base->base.gallivm->context), 4);
1629 txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
1630 txf_emit_data.args[1] = si_shader_ctx->resources[FMASK_TEX_OFFSET + sampler_index];
1631 txf_emit_data.args[2] = lp_build_const_int32(bld_base->base.gallivm,
1632 target == TGSI_TEXTURE_2D_MSAA ? TGSI_TEXTURE_2D : TGSI_TEXTURE_2D_ARRAY);
1633 txf_emit_data.arg_count = 3;
1634
1635 build_tex_intrinsic(&txf_action, bld_base, &txf_emit_data);
1636
1637 /* Initialize some constants. */
1638 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
1639 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
1640
1641 /* Apply the formula. */
1642 LLVMValueRef fmask =
1643 LLVMBuildExtractElement(gallivm->builder,
1644 txf_emit_data.output[0],
1645 uint_bld->zero, "");
1646
1647 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1648
1649 LLVMValueRef sample_index4 =
1650 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1651
1652 LLVMValueRef shifted_fmask =
1653 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1654
1655 LLVMValueRef final_sample =
1656 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1657
1658 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1659 * resource descriptor is 0 (invalid),
1660 */
1661 LLVMValueRef fmask_desc =
1662 LLVMBuildBitCast(gallivm->builder,
1663 si_shader_ctx->resources[FMASK_TEX_OFFSET + sampler_index],
1664 LLVMVectorType(uint_bld->elem_type, 8), "");
1665
1666 LLVMValueRef fmask_word1 =
1667 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1668 uint_bld->one, "");
1669
1670 LLVMValueRef word1_is_nonzero =
1671 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1672 fmask_word1, uint_bld->zero, "");
1673
1674 /* Replace the MSAA sample index. */
1675 address[sample_chan] =
1676 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1677 final_sample, address[sample_chan], "");
1678 }
1679
1680 /* Resource */
1681 emit_data->args[1] = si_shader_ctx->resources[sampler_index];
1682
1683 if (opcode == TGSI_OPCODE_TXF) {
1684 /* add tex offsets */
1685 if (inst->Texture.NumOffsets) {
1686 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1687 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
1688 const struct tgsi_texture_offset * off = inst->TexOffsets;
1689
1690 assert(inst->Texture.NumOffsets == 1);
1691
1692 switch (target) {
1693 case TGSI_TEXTURE_3D:
1694 address[2] = lp_build_add(uint_bld, address[2],
1695 bld->immediates[off->Index][off->SwizzleZ]);
1696 /* fall through */
1697 case TGSI_TEXTURE_2D:
1698 case TGSI_TEXTURE_SHADOW2D:
1699 case TGSI_TEXTURE_RECT:
1700 case TGSI_TEXTURE_SHADOWRECT:
1701 case TGSI_TEXTURE_2D_ARRAY:
1702 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1703 address[1] =
1704 lp_build_add(uint_bld, address[1],
1705 bld->immediates[off->Index][off->SwizzleY]);
1706 /* fall through */
1707 case TGSI_TEXTURE_1D:
1708 case TGSI_TEXTURE_SHADOW1D:
1709 case TGSI_TEXTURE_1D_ARRAY:
1710 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1711 address[0] =
1712 lp_build_add(uint_bld, address[0],
1713 bld->immediates[off->Index][off->SwizzleX]);
1714 break;
1715 /* texture offsets do not apply to other texture targets */
1716 }
1717 }
1718
1719 emit_data->dst_type = LLVMVectorType(
1720 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
1721 4);
1722
1723 emit_data->arg_count = 3;
1724 } else {
1725 /* Sampler */
1726 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1727
1728 emit_data->dst_type = LLVMVectorType(
1729 LLVMFloatTypeInContext(bld_base->base.gallivm->context),
1730 4);
1731
1732 emit_data->arg_count = 4;
1733 }
1734
1735 /* Dimensions */
1736 emit_data->args[emit_data->arg_count - 1] =
1737 lp_build_const_int32(bld_base->base.gallivm, target);
1738
1739 /* Pad to power of two vector */
1740 while (count < util_next_power_of_two(count))
1741 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1742
1743 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
1744 }
1745
1746 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1747 struct lp_build_tgsi_context * bld_base,
1748 struct lp_build_emit_data * emit_data)
1749 {
1750 struct lp_build_context * base = &bld_base->base;
1751 char intr_name[127];
1752
1753 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1754 emit_data->output[emit_data->chan] = build_intrinsic(
1755 base->gallivm->builder,
1756 "llvm.SI.vs.load.input", emit_data->dst_type,
1757 emit_data->args, emit_data->arg_count,
1758 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1759 return;
1760 }
1761
1762 sprintf(intr_name, "%sv%ui32", action->intr_name,
1763 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
1764
1765 emit_data->output[emit_data->chan] = build_intrinsic(
1766 base->gallivm->builder, intr_name, emit_data->dst_type,
1767 emit_data->args, emit_data->arg_count,
1768 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1769 }
1770
1771 static void txq_fetch_args(
1772 struct lp_build_tgsi_context * bld_base,
1773 struct lp_build_emit_data * emit_data)
1774 {
1775 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1776 const struct tgsi_full_instruction *inst = emit_data->inst;
1777 struct gallivm_state *gallivm = bld_base->base.gallivm;
1778
1779 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1780 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1781 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
1782
1783 /* Read the size from the buffer descriptor directly. */
1784 LLVMValueRef size = si_shader_ctx->resources[inst->Src[1].Register.Index];
1785 size = LLVMBuildBitCast(gallivm->builder, size, v8i32, "");
1786 size = LLVMBuildExtractElement(gallivm->builder, size,
1787 lp_build_const_int32(gallivm, 2), "");
1788 emit_data->args[0] = size;
1789 return;
1790 }
1791
1792 /* Mip level */
1793 emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1794
1795 /* Resource */
1796 emit_data->args[1] = si_shader_ctx->resources[inst->Src[1].Register.Index];
1797
1798 /* Dimensions */
1799 emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
1800 inst->Texture.Texture);
1801
1802 emit_data->arg_count = 3;
1803
1804 emit_data->dst_type = LLVMVectorType(
1805 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
1806 4);
1807 }
1808
1809 static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
1810 struct lp_build_tgsi_context * bld_base,
1811 struct lp_build_emit_data * emit_data)
1812 {
1813 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1814 /* Just return the buffer size. */
1815 emit_data->output[emit_data->chan] = emit_data->args[0];
1816 return;
1817 }
1818
1819 build_tgsi_intrinsic_nomem(action, bld_base, emit_data);
1820 }
1821
1822 #if HAVE_LLVM >= 0x0304
1823
1824 static void si_llvm_emit_ddxy(
1825 const struct lp_build_tgsi_action * action,
1826 struct lp_build_tgsi_context * bld_base,
1827 struct lp_build_emit_data * emit_data)
1828 {
1829 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1830 struct gallivm_state *gallivm = bld_base->base.gallivm;
1831 struct lp_build_context * base = &bld_base->base;
1832 const struct tgsi_full_instruction *inst = emit_data->inst;
1833 unsigned opcode = inst->Instruction.Opcode;
1834 LLVMValueRef indices[2];
1835 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
1836 LLVMValueRef tl, trbl, result[4];
1837 LLVMTypeRef i32;
1838 unsigned swizzle[4];
1839 unsigned c;
1840
1841 i32 = LLVMInt32TypeInContext(gallivm->context);
1842
1843 indices[0] = bld_base->uint_bld.zero;
1844 indices[1] = build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
1845 NULL, 0, LLVMReadNoneAttribute);
1846 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
1847 indices, 2, "");
1848
1849 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
1850 lp_build_const_int32(gallivm, 0xfffffffc), "");
1851 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
1852 indices, 2, "");
1853
1854 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
1855 lp_build_const_int32(gallivm,
1856 opcode == TGSI_OPCODE_DDX ? 1 : 2),
1857 "");
1858 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
1859 indices, 2, "");
1860
1861 for (c = 0; c < 4; ++c) {
1862 unsigned i;
1863
1864 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
1865 for (i = 0; i < c; ++i) {
1866 if (swizzle[i] == swizzle[c]) {
1867 result[c] = result[i];
1868 break;
1869 }
1870 }
1871 if (i != c)
1872 continue;
1873
1874 LLVMBuildStore(gallivm->builder,
1875 LLVMBuildBitCast(gallivm->builder,
1876 lp_build_emit_fetch(bld_base, inst, 0, c),
1877 i32, ""),
1878 store_ptr);
1879
1880 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
1881 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
1882
1883 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
1884 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
1885
1886 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
1887 }
1888
1889 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
1890 }
1891
1892 #endif /* HAVE_LLVM >= 0x0304 */
1893
1894 /* Emit one vertex from the geometry shader */
1895 static void si_llvm_emit_vertex(
1896 const struct lp_build_tgsi_action *action,
1897 struct lp_build_tgsi_context *bld_base,
1898 struct lp_build_emit_data *emit_data)
1899 {
1900 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1901 struct lp_build_context *uint = &bld_base->uint_bld;
1902 struct si_shader *shader = &si_shader_ctx->shader->shader;
1903 struct gallivm_state *gallivm = bld_base->base.gallivm;
1904 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1905 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1906 SI_PARAM_GS2VS_OFFSET);
1907 LLVMValueRef gs_next_vertex;
1908 LLVMValueRef can_emit, kill;
1909 LLVMValueRef t_list_ptr;
1910 LLVMValueRef t_list;
1911 LLVMValueRef args[2];
1912 unsigned chan;
1913 int i;
1914
1915 /* Load the GSVS ring resource descriptor */
1916 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1917 SI_PARAM_RW_BUFFERS);
1918 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
1919 lp_build_const_int32(gallivm, SI_RING_GSVS));
1920
1921 if (shader->noutput == 0) {
1922 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1923
1924 while (!tgsi_parse_end_of_tokens(parse)) {
1925 tgsi_parse_token(parse);
1926
1927 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1928 struct tgsi_full_declaration *d = &parse->FullToken.FullDeclaration;
1929
1930 if (d->Declaration.File == TGSI_FILE_OUTPUT)
1931 si_store_shader_io_attribs(shader, d);
1932 }
1933 }
1934 }
1935
1936 /* Write vertex attribute values to GSVS ring */
1937 gs_next_vertex = LLVMBuildLoad(gallivm->builder, si_shader_ctx->gs_next_vertex, "");
1938
1939 /* If this thread has already emitted the declared maximum number of
1940 * vertices, kill it: excessive vertex emissions are not supposed to
1941 * have any effect, and GS threads have no externally observable
1942 * effects other than emitting vertices.
1943 */
1944 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
1945 lp_build_const_int32(gallivm,
1946 shader->gs_max_out_vertices), "");
1947 kill = lp_build_select(&bld_base->base, can_emit,
1948 lp_build_const_float(gallivm, 1.0f),
1949 lp_build_const_float(gallivm, -1.0f));
1950 build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
1951 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
1952
1953 for (i = 0; i < shader->noutput; i++) {
1954 LLVMValueRef *out_ptr =
1955 si_shader_ctx->radeon_bld.soa.outputs[shader->output[i].index];
1956
1957 for (chan = 0; chan < 4; chan++) {
1958 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1959 LLVMValueRef voffset =
1960 lp_build_const_int32(gallivm, (i * 4 + chan) *
1961 shader->gs_max_out_vertices);
1962
1963 voffset = lp_build_add(uint, voffset, gs_next_vertex);
1964 voffset = lp_build_mul_imm(uint, voffset, 4);
1965
1966 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1967
1968 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
1969 voffset, soffset, 0,
1970 V_008F0C_BUF_DATA_FORMAT_32,
1971 V_008F0C_BUF_NUM_FORMAT_UINT,
1972 1, 0, 1, 1, 0);
1973 }
1974 }
1975 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
1976 lp_build_const_int32(gallivm, 1));
1977 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex);
1978
1979 /* Signal vertex emission */
1980 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS);
1981 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1982 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1983 LLVMVoidTypeInContext(gallivm->context), args, 2,
1984 LLVMNoUnwindAttribute);
1985 }
1986
1987 /* Cut one primitive from the geometry shader */
1988 static void si_llvm_emit_primitive(
1989 const struct lp_build_tgsi_action *action,
1990 struct lp_build_tgsi_context *bld_base,
1991 struct lp_build_emit_data *emit_data)
1992 {
1993 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1994 struct gallivm_state *gallivm = bld_base->base.gallivm;
1995 LLVMValueRef args[2];
1996
1997 /* Signal primitive cut */
1998 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS);
1999 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2000 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2001 LLVMVoidTypeInContext(gallivm->context), args, 2,
2002 LLVMNoUnwindAttribute);
2003 }
2004
2005 static const struct lp_build_tgsi_action tex_action = {
2006 .fetch_args = tex_fetch_args,
2007 .emit = build_tex_intrinsic,
2008 .intr_name = "llvm.SI.sample."
2009 };
2010
2011 static const struct lp_build_tgsi_action txb_action = {
2012 .fetch_args = tex_fetch_args,
2013 .emit = build_tex_intrinsic,
2014 .intr_name = "llvm.SI.sampleb."
2015 };
2016
2017 #if HAVE_LLVM >= 0x0304
2018 static const struct lp_build_tgsi_action txd_action = {
2019 .fetch_args = tex_fetch_args,
2020 .emit = build_tex_intrinsic,
2021 .intr_name = "llvm.SI.sampled."
2022 };
2023 #endif
2024
2025 static const struct lp_build_tgsi_action txf_action = {
2026 .fetch_args = tex_fetch_args,
2027 .emit = build_tex_intrinsic,
2028 .intr_name = "llvm.SI.imageload."
2029 };
2030
2031 static const struct lp_build_tgsi_action txl_action = {
2032 .fetch_args = tex_fetch_args,
2033 .emit = build_tex_intrinsic,
2034 .intr_name = "llvm.SI.samplel."
2035 };
2036
2037 static const struct lp_build_tgsi_action txq_action = {
2038 .fetch_args = txq_fetch_args,
2039 .emit = build_txq_intrinsic,
2040 .intr_name = "llvm.SI.resinfo"
2041 };
2042
2043 static void create_meta_data(struct si_shader_context *si_shader_ctx)
2044 {
2045 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2046 LLVMValueRef args[3];
2047
2048 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
2049 args[1] = 0;
2050 args[2] = lp_build_const_int32(gallivm, 1);
2051
2052 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
2053 }
2054
2055 static void create_function(struct si_shader_context *si_shader_ctx)
2056 {
2057 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2058 struct gallivm_state *gallivm = bld_base->base.gallivm;
2059 struct si_pipe_shader *shader = si_shader_ctx->shader;
2060 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32;
2061 unsigned i, last_sgpr, num_params;
2062
2063 i8 = LLVMInt8TypeInContext(gallivm->context);
2064 i32 = LLVMInt32TypeInContext(gallivm->context);
2065 f32 = LLVMFloatTypeInContext(gallivm->context);
2066 v2i32 = LLVMVectorType(i32, 2);
2067 v3i32 = LLVMVectorType(i32, 3);
2068
2069 params[SI_PARAM_CONST] = LLVMPointerType(
2070 LLVMArrayType(LLVMVectorType(i8, 16), NUM_CONST_BUFFERS), CONST_ADDR_SPACE);
2071 params[SI_PARAM_RW_BUFFERS] = params[SI_PARAM_CONST];
2072
2073 /* We assume at most 16 textures per program at the moment.
2074 * This need probably need to be changed to support bindless textures */
2075 params[SI_PARAM_SAMPLER] = LLVMPointerType(
2076 LLVMArrayType(LLVMVectorType(i8, 16), NUM_SAMPLER_VIEWS), CONST_ADDR_SPACE);
2077 params[SI_PARAM_RESOURCE] = LLVMPointerType(
2078 LLVMArrayType(LLVMVectorType(i8, 32), NUM_SAMPLER_STATES), CONST_ADDR_SPACE);
2079
2080 switch (si_shader_ctx->type) {
2081 case TGSI_PROCESSOR_VERTEX:
2082 params[SI_PARAM_VERTEX_BUFFER] = params[SI_PARAM_CONST];
2083 params[SI_PARAM_START_INSTANCE] = i32;
2084 num_params = SI_PARAM_START_INSTANCE+1;
2085 if (shader->key.vs.as_es) {
2086 params[SI_PARAM_ES2GS_OFFSET] = i32;
2087 num_params++;
2088 } else {
2089 /* The locations of the other parameters are assigned dynamically. */
2090
2091 /* Streamout SGPRs. */
2092 if (shader->selector->so.num_outputs) {
2093 params[si_shader_ctx->param_streamout_config = num_params++] = i32;
2094 params[si_shader_ctx->param_streamout_write_index = num_params++] = i32;
2095 }
2096 /* A streamout buffer offset is loaded if the stride is non-zero. */
2097 for (i = 0; i < 4; i++) {
2098 if (!shader->selector->so.stride[i])
2099 continue;
2100
2101 params[si_shader_ctx->param_streamout_offset[i] = num_params++] = i32;
2102 }
2103 }
2104
2105 last_sgpr = num_params-1;
2106
2107 /* VGPRs */
2108 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
2109 params[num_params++] = i32; /* unused*/
2110 params[num_params++] = i32; /* unused */
2111 params[si_shader_ctx->param_instance_id = num_params++] = i32;
2112 break;
2113
2114 case TGSI_PROCESSOR_GEOMETRY:
2115 params[SI_PARAM_GS2VS_OFFSET] = i32;
2116 params[SI_PARAM_GS_WAVE_ID] = i32;
2117 last_sgpr = SI_PARAM_GS_WAVE_ID;
2118
2119 /* VGPRs */
2120 params[SI_PARAM_VTX0_OFFSET] = i32;
2121 params[SI_PARAM_VTX1_OFFSET] = i32;
2122 params[SI_PARAM_PRIMITIVE_ID] = i32;
2123 params[SI_PARAM_VTX2_OFFSET] = i32;
2124 params[SI_PARAM_VTX3_OFFSET] = i32;
2125 params[SI_PARAM_VTX4_OFFSET] = i32;
2126 params[SI_PARAM_VTX5_OFFSET] = i32;
2127 params[SI_PARAM_GS_INSTANCE_ID] = i32;
2128 num_params = SI_PARAM_GS_INSTANCE_ID+1;
2129 break;
2130
2131 case TGSI_PROCESSOR_FRAGMENT:
2132 params[SI_PARAM_ALPHA_REF] = f32;
2133 params[SI_PARAM_PRIM_MASK] = i32;
2134 last_sgpr = SI_PARAM_PRIM_MASK;
2135 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
2136 params[SI_PARAM_PERSP_CENTER] = v2i32;
2137 params[SI_PARAM_PERSP_CENTROID] = v2i32;
2138 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
2139 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
2140 params[SI_PARAM_LINEAR_CENTER] = v2i32;
2141 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
2142 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
2143 params[SI_PARAM_POS_X_FLOAT] = f32;
2144 params[SI_PARAM_POS_Y_FLOAT] = f32;
2145 params[SI_PARAM_POS_Z_FLOAT] = f32;
2146 params[SI_PARAM_POS_W_FLOAT] = f32;
2147 params[SI_PARAM_FRONT_FACE] = f32;
2148 params[SI_PARAM_ANCILLARY] = f32;
2149 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
2150 params[SI_PARAM_POS_FIXED_PT] = f32;
2151 num_params = SI_PARAM_POS_FIXED_PT+1;
2152 break;
2153
2154 default:
2155 assert(0 && "unimplemented shader");
2156 return;
2157 }
2158
2159 assert(num_params <= Elements(params));
2160 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
2161 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
2162
2163 for (i = 0; i <= last_sgpr; ++i) {
2164 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
2165 switch (i) {
2166 default:
2167 LLVMAddAttribute(P, LLVMInRegAttribute);
2168 break;
2169 #if HAVE_LLVM >= 0x0304
2170 /* We tell llvm that array inputs are passed by value to allow Sinking pass
2171 * to move load. Inputs are constant so this is fine. */
2172 case SI_PARAM_CONST:
2173 case SI_PARAM_SAMPLER:
2174 case SI_PARAM_RESOURCE:
2175 LLVMAddAttribute(P, LLVMByValAttribute);
2176 break;
2177 #endif
2178 }
2179 }
2180
2181 #if HAVE_LLVM >= 0x0304
2182 if (bld_base->info &&
2183 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
2184 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0))
2185 si_shader_ctx->ddxy_lds =
2186 LLVMAddGlobalInAddressSpace(gallivm->module,
2187 LLVMArrayType(i32, 64),
2188 "ddxy_lds",
2189 LOCAL_ADDR_SPACE);
2190 #endif
2191 }
2192
2193 static void preload_constants(struct si_shader_context *si_shader_ctx)
2194 {
2195 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2196 struct gallivm_state * gallivm = bld_base->base.gallivm;
2197 const struct tgsi_shader_info * info = bld_base->info;
2198 unsigned buf;
2199 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
2200
2201 for (buf = 0; buf < NUM_CONST_BUFFERS; buf++) {
2202 unsigned i, num_const = info->const_file_max[buf] + 1;
2203
2204 if (num_const == 0)
2205 continue;
2206
2207 /* Allocate space for the constant values */
2208 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
2209
2210 /* Load the resource descriptor */
2211 si_shader_ctx->const_resource[buf] =
2212 build_indexed_load(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
2213
2214 /* Load the constants, we rely on the code sinking to do the rest */
2215 for (i = 0; i < num_const * 4; ++i) {
2216 LLVMValueRef args[2] = {
2217 si_shader_ctx->const_resource[buf],
2218 lp_build_const_int32(gallivm, i * 4)
2219 };
2220 si_shader_ctx->constants[buf][i] =
2221 build_intrinsic(gallivm->builder, "llvm.SI.load.const",
2222 bld_base->base.elem_type, args, 2,
2223 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2224 }
2225 }
2226 }
2227
2228 static void preload_samplers(struct si_shader_context *si_shader_ctx)
2229 {
2230 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2231 struct gallivm_state * gallivm = bld_base->base.gallivm;
2232 const struct tgsi_shader_info * info = bld_base->info;
2233
2234 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
2235
2236 LLVMValueRef res_ptr, samp_ptr;
2237 LLVMValueRef offset;
2238
2239 if (num_samplers == 0)
2240 return;
2241
2242 /* Allocate space for the values */
2243 si_shader_ctx->resources = CALLOC(NUM_SAMPLER_VIEWS, sizeof(LLVMValueRef));
2244 si_shader_ctx->samplers = CALLOC(num_samplers, sizeof(LLVMValueRef));
2245
2246 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2247 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2248
2249 /* Load the resources and samplers, we rely on the code sinking to do the rest */
2250 for (i = 0; i < num_samplers; ++i) {
2251 /* Resource */
2252 offset = lp_build_const_int32(gallivm, i);
2253 si_shader_ctx->resources[i] = build_indexed_load(si_shader_ctx, res_ptr, offset);
2254
2255 /* Sampler */
2256 offset = lp_build_const_int32(gallivm, i);
2257 si_shader_ctx->samplers[i] = build_indexed_load(si_shader_ctx, samp_ptr, offset);
2258
2259 /* FMASK resource */
2260 if (info->is_msaa_sampler[i]) {
2261 offset = lp_build_const_int32(gallivm, FMASK_TEX_OFFSET + i);
2262 si_shader_ctx->resources[FMASK_TEX_OFFSET + i] =
2263 build_indexed_load(si_shader_ctx, res_ptr, offset);
2264 }
2265 }
2266 }
2267
2268 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
2269 {
2270 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2271 struct gallivm_state * gallivm = bld_base->base.gallivm;
2272 unsigned i;
2273
2274 if (si_shader_ctx->type != TGSI_PROCESSOR_VERTEX ||
2275 si_shader_ctx->shader->key.vs.as_es ||
2276 !si_shader_ctx->shader->selector->so.num_outputs)
2277 return;
2278
2279 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2280 SI_PARAM_RW_BUFFERS);
2281
2282 /* Load the resources, we rely on the code sinking to do the rest */
2283 for (i = 0; i < 4; ++i) {
2284 if (si_shader_ctx->shader->selector->so.stride[i]) {
2285 LLVMValueRef offset = lp_build_const_int32(gallivm,
2286 SI_RW_SO + i);
2287
2288 si_shader_ctx->so_buffers[i] = build_indexed_load(si_shader_ctx, buf_ptr, offset);
2289 }
2290 }
2291 }
2292
2293 int si_compile_llvm(struct si_context *sctx, struct si_pipe_shader *shader,
2294 LLVMModuleRef mod)
2295 {
2296 unsigned i;
2297 uint32_t *ptr;
2298 struct radeon_shader_binary binary;
2299 bool dump = r600_can_dump_shader(&sctx->screen->b,
2300 shader->selector ? shader->selector->tokens : NULL);
2301 memset(&binary, 0, sizeof(binary));
2302 radeon_llvm_compile(mod, &binary,
2303 r600_get_llvm_processor_name(sctx->screen->b.family), dump);
2304 if (dump && ! binary.disassembled) {
2305 fprintf(stderr, "SI CODE:\n");
2306 for (i = 0; i < binary.code_size; i+=4 ) {
2307 fprintf(stderr, "%02x%02x%02x%02x\n", binary.code[i + 3],
2308 binary.code[i + 2], binary.code[i + 1],
2309 binary.code[i]);
2310 }
2311 }
2312
2313 /* XXX: We may be able to emit some of these values directly rather than
2314 * extracting fields to be emitted later.
2315 */
2316 for (i = 0; i < binary.config_size; i+= 8) {
2317 unsigned reg = util_le32_to_cpu(*(uint32_t*)(binary.config + i));
2318 unsigned value = util_le32_to_cpu(*(uint32_t*)(binary.config + i + 4));
2319 switch (reg) {
2320 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
2321 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
2322 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
2323 case R_00B848_COMPUTE_PGM_RSRC1:
2324 shader->num_sgprs = (G_00B028_SGPRS(value) + 1) * 8;
2325 shader->num_vgprs = (G_00B028_VGPRS(value) + 1) * 4;
2326 break;
2327 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
2328 shader->lds_size = G_00B02C_EXTRA_LDS_SIZE(value);
2329 break;
2330 case R_00B84C_COMPUTE_PGM_RSRC2:
2331 shader->lds_size = G_00B84C_LDS_SIZE(value);
2332 break;
2333 case R_0286CC_SPI_PS_INPUT_ENA:
2334 shader->spi_ps_input_ena = value;
2335 break;
2336 default:
2337 fprintf(stderr, "Warning: Compiler emitted unknown "
2338 "config register: 0x%x\n", reg);
2339 break;
2340 }
2341 }
2342
2343 /* copy new shader */
2344 r600_resource_reference(&shader->bo, NULL);
2345 shader->bo = si_resource_create_custom(sctx->b.b.screen, PIPE_USAGE_IMMUTABLE,
2346 binary.code_size);
2347 if (shader->bo == NULL) {
2348 return -ENOMEM;
2349 }
2350
2351 ptr = (uint32_t*)sctx->b.ws->buffer_map(shader->bo->cs_buf, sctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE);
2352 if (SI_BIG_ENDIAN) {
2353 for (i = 0; i < binary.code_size / 4; ++i) {
2354 ptr[i] = util_cpu_to_le32((*(uint32_t*)(binary.code + i*4)));
2355 }
2356 } else {
2357 memcpy(ptr, binary.code, binary.code_size);
2358 }
2359 sctx->b.ws->buffer_unmap(shader->bo->cs_buf);
2360
2361 free(binary.code);
2362 free(binary.config);
2363
2364 return 0;
2365 }
2366
2367 /* Generate code for the hardware VS shader stage to go with a geometry shader */
2368 static int si_generate_gs_copy_shader(struct si_context *sctx,
2369 struct si_shader_context *si_shader_ctx,
2370 bool dump)
2371 {
2372 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
2373 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2374 struct lp_build_context *base = &bld_base->base;
2375 struct lp_build_context *uint = &bld_base->uint_bld;
2376 struct si_shader *shader = &si_shader_ctx->shader->shader;
2377 struct si_shader *gs = &si_shader_ctx->shader->selector->current->shader;
2378 struct si_shader_output_values *outputs;
2379 LLVMValueRef t_list_ptr, t_list;
2380 LLVMValueRef args[9];
2381 int i, r;
2382
2383 outputs = MALLOC(gs->noutput * sizeof(outputs[0]));
2384
2385 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
2386 si_shader_ctx->gs_for_vs = gs;
2387
2388 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
2389
2390 create_meta_data(si_shader_ctx);
2391 create_function(si_shader_ctx);
2392 preload_streamout_buffers(si_shader_ctx);
2393
2394 /* Load the GSVS ring resource descriptor */
2395 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2396 SI_PARAM_RW_BUFFERS);
2397 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
2398 lp_build_const_int32(gallivm, SI_RING_GSVS));
2399
2400 args[0] = t_list;
2401 args[1] = lp_build_mul_imm(uint,
2402 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2403 si_shader_ctx->param_vertex_id),
2404 4);
2405 args[3] = uint->zero;
2406 args[4] = uint->one; /* OFFEN */
2407 args[5] = uint->zero; /* IDXEN */
2408 args[6] = uint->one; /* GLC */
2409 args[7] = uint->one; /* SLC */
2410 args[8] = uint->zero; /* TFE */
2411
2412 /* Fetch vertex data from GSVS ring */
2413 for (i = 0; i < gs->noutput; ++i) {
2414 struct si_shader_output *out = gs->output + i;
2415 unsigned chan;
2416
2417 shader->output[i] = *out;
2418
2419 outputs[i].name = out->name;
2420 outputs[i].index = out->index;
2421 outputs[i].sid = out->sid;
2422 outputs[i].usage = out->usage;
2423
2424 for (chan = 0; chan < 4; chan++) {
2425 args[2] = lp_build_const_int32(gallivm,
2426 (i * 4 + chan) *
2427 gs->gs_max_out_vertices * 16 * 4);
2428
2429 outputs[i].values[chan] =
2430 LLVMBuildBitCast(gallivm->builder,
2431 build_intrinsic(gallivm->builder,
2432 "llvm.SI.buffer.load.dword.i32.i32",
2433 LLVMInt32TypeInContext(gallivm->context),
2434 args, 9,
2435 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
2436 base->elem_type, "");
2437 }
2438 }
2439 shader->noutput = gs->noutput;
2440
2441 si_llvm_export_vs(bld_base, outputs, gs->noutput);
2442
2443 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
2444
2445 if (dump)
2446 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
2447
2448 r = si_compile_llvm(sctx, si_shader_ctx->shader,
2449 bld_base->base.gallivm->module);
2450
2451 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
2452
2453 FREE(outputs);
2454 return r;
2455 }
2456
2457 int si_pipe_shader_create(
2458 struct pipe_context *ctx,
2459 struct si_pipe_shader *shader)
2460 {
2461 struct si_context *sctx = (struct si_context*)ctx;
2462 struct si_pipe_shader_selector *sel = shader->selector;
2463 struct si_shader_context si_shader_ctx;
2464 struct tgsi_shader_info shader_info;
2465 struct lp_build_tgsi_context * bld_base;
2466 LLVMModuleRef mod;
2467 int r = 0;
2468 bool dump = r600_can_dump_shader(&sctx->screen->b, sel->tokens);
2469
2470 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2471 * conversion fails. */
2472 if (dump) {
2473 tgsi_dump(sel->tokens, 0);
2474 si_dump_streamout(&sel->so);
2475 }
2476
2477 assert(shader->shader.noutput == 0);
2478 assert(shader->shader.nparam == 0);
2479 assert(shader->shader.ninput == 0);
2480
2481 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
2482 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
2483 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
2484
2485 tgsi_scan_shader(sel->tokens, &shader_info);
2486
2487 shader->shader.uses_kill = shader_info.uses_kill;
2488 shader->shader.uses_instanceid = shader_info.uses_instanceid;
2489 bld_base->info = &shader_info;
2490 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
2491
2492 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
2493 bld_base->op_actions[TGSI_OPCODE_TXB] = txb_action;
2494 #if HAVE_LLVM >= 0x0304
2495 bld_base->op_actions[TGSI_OPCODE_TXD] = txd_action;
2496 #endif
2497 bld_base->op_actions[TGSI_OPCODE_TXF] = txf_action;
2498 bld_base->op_actions[TGSI_OPCODE_TXL] = txl_action;
2499 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
2500 bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
2501
2502 #if HAVE_LLVM >= 0x0304
2503 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
2504 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
2505 #endif
2506
2507 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
2508 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
2509
2510 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
2511 si_shader_ctx.tokens = sel->tokens;
2512 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
2513 si_shader_ctx.shader = shader;
2514 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
2515
2516 switch (si_shader_ctx.type) {
2517 case TGSI_PROCESSOR_VERTEX:
2518 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
2519 if (shader->key.vs.as_es) {
2520 si_shader_ctx.gs_for_vs = &sctx->gs_shader->current->shader;
2521 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
2522 } else {
2523 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
2524 }
2525 break;
2526 case TGSI_PROCESSOR_GEOMETRY: {
2527 int i;
2528
2529 si_shader_ctx.radeon_bld.load_input = declare_input_gs;
2530 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
2531 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
2532
2533 for (i = 0; i < shader_info.num_properties; i++) {
2534 switch (shader_info.properties[i].name) {
2535 case TGSI_PROPERTY_GS_INPUT_PRIM:
2536 shader->shader.gs_input_prim = shader_info.properties[i].data[0];
2537 break;
2538 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
2539 shader->shader.gs_output_prim = shader_info.properties[i].data[0];
2540 break;
2541 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
2542 shader->shader.gs_max_out_vertices = shader_info.properties[i].data[0];
2543 break;
2544 }
2545 }
2546 break;
2547 }
2548 case TGSI_PROCESSOR_FRAGMENT:
2549 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
2550 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
2551 break;
2552 default:
2553 assert(!"Unsupported shader type");
2554 return -1;
2555 }
2556
2557 create_meta_data(&si_shader_ctx);
2558 create_function(&si_shader_ctx);
2559 preload_constants(&si_shader_ctx);
2560 preload_samplers(&si_shader_ctx);
2561 preload_streamout_buffers(&si_shader_ctx);
2562
2563 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2564 si_shader_ctx.gs_next_vertex =
2565 lp_build_alloca(bld_base->base.gallivm,
2566 bld_base->uint_bld.elem_type, "");
2567 }
2568
2569 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
2570 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
2571 goto out;
2572 }
2573
2574 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
2575
2576 mod = bld_base->base.gallivm->module;
2577 r = si_compile_llvm(sctx, shader, mod);
2578 if (r) {
2579 fprintf(stderr, "LLVM failed to compile shader\n");
2580 goto out;
2581 }
2582
2583 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
2584
2585 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2586 shader->gs_copy_shader = CALLOC_STRUCT(si_pipe_shader);
2587 shader->gs_copy_shader->selector = shader->selector;
2588 shader->gs_copy_shader->key = shader->key;
2589 si_shader_ctx.shader = shader->gs_copy_shader;
2590 if ((r = si_generate_gs_copy_shader(sctx, &si_shader_ctx, dump))) {
2591 free(shader->gs_copy_shader);
2592 shader->gs_copy_shader = NULL;
2593 goto out;
2594 }
2595 }
2596
2597 tgsi_parse_free(&si_shader_ctx.parse);
2598
2599 out:
2600 for (int i = 0; i < NUM_CONST_BUFFERS; i++)
2601 FREE(si_shader_ctx.constants[i]);
2602 FREE(si_shader_ctx.resources);
2603 FREE(si_shader_ctx.samplers);
2604
2605 return r;
2606 }
2607
2608 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
2609 {
2610 r600_resource_reference(&shader->bo, NULL);
2611 }