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[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "gallivm/lp_bld_const.h"
25 #include "gallivm/lp_bld_gather.h"
26 #include "gallivm/lp_bld_intr.h"
27 #include "gallivm/lp_bld_logic.h"
28 #include "gallivm/lp_bld_arit.h"
29 #include "gallivm/lp_bld_flow.h"
30 #include "gallivm/lp_bld_misc.h"
31 #include "util/u_memory.h"
32 #include "util/u_string.h"
33 #include "tgsi/tgsi_build.h"
34 #include "tgsi/tgsi_util.h"
35 #include "tgsi/tgsi_dump.h"
36
37 #include "ac_binary.h"
38 #include "ac_llvm_util.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41 #include "si_shader_internal.h"
42 #include "si_pipe.h"
43 #include "sid.h"
44
45 #include "compiler/nir/nir.h"
46
47 static const char *scratch_rsrc_dword0_symbol =
48 "SCRATCH_RSRC_DWORD0";
49
50 static const char *scratch_rsrc_dword1_symbol =
51 "SCRATCH_RSRC_DWORD1";
52
53 struct si_shader_output_values
54 {
55 LLVMValueRef values[4];
56 unsigned semantic_name;
57 unsigned semantic_index;
58 ubyte vertex_stream[4];
59 };
60
61 /**
62 * Used to collect types and other info about arguments of the LLVM function
63 * before the function is created.
64 */
65 struct si_function_info {
66 LLVMTypeRef types[100];
67 LLVMValueRef *assign[100];
68 unsigned num_sgpr_params;
69 unsigned num_params;
70 };
71
72 enum si_arg_regfile {
73 ARG_SGPR,
74 ARG_VGPR
75 };
76
77 static void si_init_shader_ctx(struct si_shader_context *ctx,
78 struct si_screen *sscreen,
79 LLVMTargetMachineRef tm);
80
81 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
82 struct lp_build_tgsi_context *bld_base,
83 struct lp_build_emit_data *emit_data);
84
85 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
86 FILE *f);
87
88 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
89 union si_shader_part_key *key);
90 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
91 union si_shader_part_key *key);
92 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
93 union si_shader_part_key *key);
94 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
95 union si_shader_part_key *key);
96
97 /* Ideally pass the sample mask input to the PS epilog as v14, which
98 * is its usual location, so that the shader doesn't have to add v_mov.
99 */
100 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
101
102 enum {
103 CONST_ADDR_SPACE = 2,
104 LOCAL_ADDR_SPACE = 3,
105 };
106
107 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
108 LLVMTypeRef type)
109 {
110 if (type == ctx->ac.i64 || type == ctx->ac.f64)
111 return true;
112
113 return false;
114 }
115
116 static bool is_merged_shader(struct si_shader *shader)
117 {
118 if (shader->selector->screen->info.chip_class <= VI)
119 return false;
120
121 return shader->key.as_ls ||
122 shader->key.as_es ||
123 shader->selector->type == PIPE_SHADER_TESS_CTRL ||
124 shader->selector->type == PIPE_SHADER_GEOMETRY;
125 }
126
127 static void si_init_function_info(struct si_function_info *fninfo)
128 {
129 fninfo->num_params = 0;
130 fninfo->num_sgpr_params = 0;
131 }
132
133 static unsigned add_arg_assign(struct si_function_info *fninfo,
134 enum si_arg_regfile regfile, LLVMTypeRef type,
135 LLVMValueRef *assign)
136 {
137 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
138
139 unsigned idx = fninfo->num_params++;
140 assert(idx < ARRAY_SIZE(fninfo->types));
141
142 if (regfile == ARG_SGPR)
143 fninfo->num_sgpr_params = fninfo->num_params;
144
145 fninfo->types[idx] = type;
146 fninfo->assign[idx] = assign;
147 return idx;
148 }
149
150 static unsigned add_arg(struct si_function_info *fninfo,
151 enum si_arg_regfile regfile, LLVMTypeRef type)
152 {
153 return add_arg_assign(fninfo, regfile, type, NULL);
154 }
155
156 static void add_arg_assign_checked(struct si_function_info *fninfo,
157 enum si_arg_regfile regfile, LLVMTypeRef type,
158 LLVMValueRef *assign, unsigned idx)
159 {
160 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
161 assert(actual == idx);
162 }
163
164 static void add_arg_checked(struct si_function_info *fninfo,
165 enum si_arg_regfile regfile, LLVMTypeRef type,
166 unsigned idx)
167 {
168 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
169 }
170
171 /**
172 * Returns a unique index for a per-patch semantic name and index. The index
173 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
174 * can be calculated.
175 */
176 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
177 {
178 switch (semantic_name) {
179 case TGSI_SEMANTIC_TESSOUTER:
180 return 0;
181 case TGSI_SEMANTIC_TESSINNER:
182 return 1;
183 case TGSI_SEMANTIC_PATCH:
184 assert(index < 30);
185 return 2 + index;
186
187 default:
188 assert(!"invalid semantic name");
189 return 0;
190 }
191 }
192
193 /**
194 * Returns a unique index for a semantic name and index. The index must be
195 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
196 * calculated.
197 */
198 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
199 {
200 switch (semantic_name) {
201 case TGSI_SEMANTIC_POSITION:
202 return 0;
203 case TGSI_SEMANTIC_GENERIC:
204 /* Since some shader stages use the the highest used IO index
205 * to determine the size to allocate for inputs/outputs
206 * (in LDS, tess and GS rings). GENERIC should be placed right
207 * after POSITION to make that size as small as possible.
208 */
209 if (index < SI_MAX_IO_GENERIC)
210 return 1 + index;
211
212 assert(!"invalid generic index");
213 return 0;
214 case TGSI_SEMANTIC_PSIZE:
215 return SI_MAX_IO_GENERIC + 1;
216 case TGSI_SEMANTIC_CLIPDIST:
217 assert(index <= 1);
218 return SI_MAX_IO_GENERIC + 2 + index;
219 case TGSI_SEMANTIC_FOG:
220 return SI_MAX_IO_GENERIC + 4;
221 case TGSI_SEMANTIC_LAYER:
222 return SI_MAX_IO_GENERIC + 5;
223 case TGSI_SEMANTIC_VIEWPORT_INDEX:
224 return SI_MAX_IO_GENERIC + 6;
225 case TGSI_SEMANTIC_PRIMID:
226 return SI_MAX_IO_GENERIC + 7;
227 case TGSI_SEMANTIC_COLOR: /* these alias */
228 case TGSI_SEMANTIC_BCOLOR:
229 assert(index < 2);
230 return SI_MAX_IO_GENERIC + 8 + index;
231 case TGSI_SEMANTIC_TEXCOORD:
232 assert(index < 8);
233 assert(SI_MAX_IO_GENERIC + 10 + index < 64);
234 return SI_MAX_IO_GENERIC + 10 + index;
235 default:
236 assert(!"invalid semantic name");
237 return 0;
238 }
239 }
240
241 /**
242 * Get the value of a shader input parameter and extract a bitfield.
243 */
244 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
245 unsigned param, unsigned rshift,
246 unsigned bitwidth)
247 {
248 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
249 param);
250
251 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
252 value = ac_to_integer(&ctx->ac, value);
253
254 if (rshift)
255 value = LLVMBuildLShr(ctx->ac.builder, value,
256 LLVMConstInt(ctx->i32, rshift, 0), "");
257
258 if (rshift + bitwidth < 32) {
259 unsigned mask = (1 << bitwidth) - 1;
260 value = LLVMBuildAnd(ctx->ac.builder, value,
261 LLVMConstInt(ctx->i32, mask, 0), "");
262 }
263
264 return value;
265 }
266
267 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
268 {
269 switch (ctx->type) {
270 case PIPE_SHADER_TESS_CTRL:
271 return unpack_param(ctx, ctx->param_tcs_rel_ids, 0, 8);
272
273 case PIPE_SHADER_TESS_EVAL:
274 return LLVMGetParam(ctx->main_fn,
275 ctx->param_tes_rel_patch_id);
276
277 default:
278 assert(0);
279 return NULL;
280 }
281 }
282
283 /* Tessellation shaders pass outputs to the next shader using LDS.
284 *
285 * LS outputs = TCS inputs
286 * TCS outputs = TES inputs
287 *
288 * The LDS layout is:
289 * - TCS inputs for patch 0
290 * - TCS inputs for patch 1
291 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
292 * - ...
293 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
294 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
295 * - TCS outputs for patch 1
296 * - Per-patch TCS outputs for patch 1
297 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
298 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
299 * - ...
300 *
301 * All three shaders VS(LS), TCS, TES share the same LDS space.
302 */
303
304 static LLVMValueRef
305 get_tcs_in_patch_stride(struct si_shader_context *ctx)
306 {
307 return unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
308 }
309
310 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
311 {
312 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
313
314 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
315 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
316
317 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
318 }
319
320 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
321 {
322 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
323
324 return LLVMConstInt(ctx->i32, stride, 0);
325 }
326
327 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
328 {
329 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
330 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
331
332 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
333 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
334 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
335 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
336 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
337 num_patch_outputs * 4;
338 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
339 }
340
341 static LLVMValueRef
342 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
343 {
344 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
345 unpack_param(ctx,
346 ctx->param_tcs_out_lds_offsets,
347 0, 16),
348 4);
349 }
350
351 static LLVMValueRef
352 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
353 {
354 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
355 unpack_param(ctx,
356 ctx->param_tcs_out_lds_offsets,
357 16, 16),
358 4);
359 }
360
361 static LLVMValueRef
362 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
363 {
364 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
365 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
366
367 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
368 }
369
370 static LLVMValueRef
371 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
372 {
373 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
374 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
375 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
376
377 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
378 LLVMBuildMul(ctx->ac.builder, patch_stride,
379 rel_patch_id, ""),
380 "");
381 }
382
383 static LLVMValueRef
384 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
385 {
386 LLVMValueRef patch0_patch_data_offset =
387 get_tcs_out_patch0_patch_data_offset(ctx);
388 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
389 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
390
391 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
392 LLVMBuildMul(ctx->ac.builder, patch_stride,
393 rel_patch_id, ""),
394 "");
395 }
396
397 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
398 {
399 unsigned tcs_out_vertices =
400 ctx->shader->selector ?
401 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
402
403 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
404 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
405 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
406
407 return unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
408 }
409
410 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
411 {
412 unsigned stride;
413
414 switch (ctx->type) {
415 case PIPE_SHADER_VERTEX:
416 stride = util_last_bit64(ctx->shader->selector->outputs_written);
417 return LLVMConstInt(ctx->i32, stride * 4, 0);
418
419 case PIPE_SHADER_TESS_CTRL:
420 if (ctx->screen->info.chip_class >= GFX9 &&
421 ctx->shader->is_monolithic) {
422 stride = util_last_bit64(ctx->shader->key.part.tcs.ls->outputs_written);
423 return LLVMConstInt(ctx->i32, stride * 4, 0);
424 }
425 return unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
426
427 default:
428 assert(0);
429 return NULL;
430 }
431 }
432
433 static LLVMValueRef get_instance_index_for_fetch(
434 struct si_shader_context *ctx,
435 unsigned param_start_instance, LLVMValueRef divisor)
436 {
437 LLVMValueRef result = ctx->abi.instance_id;
438
439 /* The division must be done before START_INSTANCE is added. */
440 if (divisor != ctx->i32_1)
441 result = LLVMBuildUDiv(ctx->ac.builder, result, divisor, "");
442
443 return LLVMBuildAdd(ctx->ac.builder, result,
444 LLVMGetParam(ctx->main_fn, param_start_instance), "");
445 }
446
447 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
448 * to float. */
449 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
450 LLVMValueRef vec4,
451 unsigned double_index)
452 {
453 LLVMBuilderRef builder = ctx->ac.builder;
454 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->ac.context);
455 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
456 LLVMVectorType(f64, 2), "");
457 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
458 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
459 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
460 }
461
462 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
463 LLVMValueRef i32, unsigned index)
464 {
465 assert(index <= 1);
466
467 if (index == 1)
468 return LLVMBuildAShr(ctx->ac.builder, i32,
469 LLVMConstInt(ctx->i32, 16, 0), "");
470
471 return LLVMBuildSExt(ctx->ac.builder,
472 LLVMBuildTrunc(ctx->ac.builder, i32,
473 ctx->ac.i16, ""),
474 ctx->i32, "");
475 }
476
477 void si_llvm_load_input_vs(
478 struct si_shader_context *ctx,
479 unsigned input_index,
480 LLVMValueRef out[4])
481 {
482 unsigned vs_blit_property =
483 ctx->shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
484
485 if (vs_blit_property) {
486 LLVMValueRef vertex_id = ctx->abi.vertex_id;
487 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
488 LLVMIntULE, vertex_id,
489 ctx->i32_1, "");
490 /* Use LLVMIntNE, because we have 3 vertices and only
491 * the middle one should use y2.
492 */
493 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
494 LLVMIntNE, vertex_id,
495 ctx->i32_1, "");
496
497 if (input_index == 0) {
498 /* Position: */
499 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
500 ctx->param_vs_blit_inputs);
501 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
502 ctx->param_vs_blit_inputs + 1);
503
504 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
505 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
506 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
507 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
508
509 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
510 x1, x2, "");
511 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
512 y1, y2, "");
513
514 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
515 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
516 out[2] = LLVMGetParam(ctx->main_fn,
517 ctx->param_vs_blit_inputs + 2);
518 out[3] = ctx->ac.f32_1;
519 return;
520 }
521
522 /* Color or texture coordinates: */
523 assert(input_index == 1);
524
525 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
526 for (int i = 0; i < 4; i++) {
527 out[i] = LLVMGetParam(ctx->main_fn,
528 ctx->param_vs_blit_inputs + 3 + i);
529 }
530 } else {
531 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
532 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
533 ctx->param_vs_blit_inputs + 3);
534 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
535 ctx->param_vs_blit_inputs + 4);
536 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
537 ctx->param_vs_blit_inputs + 5);
538 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
539 ctx->param_vs_blit_inputs + 6);
540
541 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
542 x1, x2, "");
543 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
544 y1, y2, "");
545 out[2] = LLVMGetParam(ctx->main_fn,
546 ctx->param_vs_blit_inputs + 7);
547 out[3] = LLVMGetParam(ctx->main_fn,
548 ctx->param_vs_blit_inputs + 8);
549 }
550 return;
551 }
552
553 unsigned chan;
554 unsigned fix_fetch;
555 unsigned num_fetches;
556 unsigned fetch_stride;
557
558 LLVMValueRef t_list_ptr;
559 LLVMValueRef t_offset;
560 LLVMValueRef t_list;
561 LLVMValueRef vertex_index;
562 LLVMValueRef input[3];
563
564 /* Load the T list */
565 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
566
567 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
568
569 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
570
571 vertex_index = LLVMGetParam(ctx->main_fn,
572 ctx->param_vertex_index0 +
573 input_index);
574
575 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
576
577 /* Do multiple loads for special formats. */
578 switch (fix_fetch) {
579 case SI_FIX_FETCH_RGB_64_FLOAT:
580 num_fetches = 3; /* 3 2-dword loads */
581 fetch_stride = 8;
582 break;
583 case SI_FIX_FETCH_RGBA_64_FLOAT:
584 num_fetches = 2; /* 2 4-dword loads */
585 fetch_stride = 16;
586 break;
587 case SI_FIX_FETCH_RGB_8:
588 case SI_FIX_FETCH_RGB_8_INT:
589 num_fetches = 3;
590 fetch_stride = 1;
591 break;
592 case SI_FIX_FETCH_RGB_16:
593 case SI_FIX_FETCH_RGB_16_INT:
594 num_fetches = 3;
595 fetch_stride = 2;
596 break;
597 default:
598 num_fetches = 1;
599 fetch_stride = 0;
600 }
601
602 for (unsigned i = 0; i < num_fetches; i++) {
603 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
604
605 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
606 vertex_index, voffset,
607 true);
608 }
609
610 /* Break up the vec4 into individual components */
611 for (chan = 0; chan < 4; chan++) {
612 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
613 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
614 input[0], llvm_chan, "");
615 }
616
617 switch (fix_fetch) {
618 case SI_FIX_FETCH_A2_SNORM:
619 case SI_FIX_FETCH_A2_SSCALED:
620 case SI_FIX_FETCH_A2_SINT: {
621 /* The hardware returns an unsigned value; convert it to a
622 * signed one.
623 */
624 LLVMValueRef tmp = out[3];
625 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
626
627 /* First, recover the sign-extended signed integer value. */
628 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
629 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
630 else
631 tmp = ac_to_integer(&ctx->ac, tmp);
632
633 /* For the integer-like cases, do a natural sign extension.
634 *
635 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
636 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
637 * exponent.
638 */
639 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
640 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
641 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
642 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
643
644 /* Convert back to the right type. */
645 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
646 LLVMValueRef clamp;
647 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
648 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
649 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
650 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
651 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
652 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
653 }
654
655 out[3] = tmp;
656 break;
657 }
658 case SI_FIX_FETCH_RGBA_32_UNORM:
659 case SI_FIX_FETCH_RGBX_32_UNORM:
660 for (chan = 0; chan < 4; chan++) {
661 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
662 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
663 out[chan], ctx->f32, "");
664 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
665 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
666 }
667 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
668 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
669 out[3] = LLVMConstReal(ctx->f32, 1);
670 break;
671 case SI_FIX_FETCH_RGBA_32_SNORM:
672 case SI_FIX_FETCH_RGBX_32_SNORM:
673 case SI_FIX_FETCH_RGBA_32_FIXED:
674 case SI_FIX_FETCH_RGBX_32_FIXED: {
675 double scale;
676 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
677 scale = 1.0 / 0x10000;
678 else
679 scale = 1.0 / INT_MAX;
680
681 for (chan = 0; chan < 4; chan++) {
682 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
683 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
684 out[chan], ctx->f32, "");
685 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
686 LLVMConstReal(ctx->f32, scale), "");
687 }
688 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
689 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
690 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
691 out[3] = LLVMConstReal(ctx->f32, 1);
692 break;
693 }
694 case SI_FIX_FETCH_RGBA_32_USCALED:
695 for (chan = 0; chan < 4; chan++) {
696 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
697 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
698 out[chan], ctx->f32, "");
699 }
700 break;
701 case SI_FIX_FETCH_RGBA_32_SSCALED:
702 for (chan = 0; chan < 4; chan++) {
703 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
704 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
705 out[chan], ctx->f32, "");
706 }
707 break;
708 case SI_FIX_FETCH_RG_64_FLOAT:
709 for (chan = 0; chan < 2; chan++)
710 out[chan] = extract_double_to_float(ctx, input[0], chan);
711
712 out[2] = LLVMConstReal(ctx->f32, 0);
713 out[3] = LLVMConstReal(ctx->f32, 1);
714 break;
715 case SI_FIX_FETCH_RGB_64_FLOAT:
716 for (chan = 0; chan < 3; chan++)
717 out[chan] = extract_double_to_float(ctx, input[chan], 0);
718
719 out[3] = LLVMConstReal(ctx->f32, 1);
720 break;
721 case SI_FIX_FETCH_RGBA_64_FLOAT:
722 for (chan = 0; chan < 4; chan++) {
723 out[chan] = extract_double_to_float(ctx, input[chan / 2],
724 chan % 2);
725 }
726 break;
727 case SI_FIX_FETCH_RGB_8:
728 case SI_FIX_FETCH_RGB_8_INT:
729 case SI_FIX_FETCH_RGB_16:
730 case SI_FIX_FETCH_RGB_16_INT:
731 for (chan = 0; chan < 3; chan++) {
732 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
733 input[chan],
734 ctx->i32_0, "");
735 }
736 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
737 fix_fetch == SI_FIX_FETCH_RGB_16) {
738 out[3] = LLVMConstReal(ctx->f32, 1);
739 } else {
740 out[3] = ac_to_float(&ctx->ac, ctx->i32_1);
741 }
742 break;
743 }
744 }
745
746 static void declare_input_vs(
747 struct si_shader_context *ctx,
748 unsigned input_index,
749 const struct tgsi_full_declaration *decl,
750 LLVMValueRef out[4])
751 {
752 si_llvm_load_input_vs(ctx, input_index, out);
753 }
754
755 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
756 unsigned swizzle)
757 {
758 if (swizzle > 0)
759 return ctx->i32_0;
760
761 switch (ctx->type) {
762 case PIPE_SHADER_VERTEX:
763 return LLVMGetParam(ctx->main_fn,
764 ctx->param_vs_prim_id);
765 case PIPE_SHADER_TESS_CTRL:
766 return LLVMGetParam(ctx->main_fn,
767 ctx->param_tcs_patch_id);
768 case PIPE_SHADER_TESS_EVAL:
769 return LLVMGetParam(ctx->main_fn,
770 ctx->param_tes_patch_id);
771 case PIPE_SHADER_GEOMETRY:
772 return ctx->abi.gs_prim_id;
773 default:
774 assert(0);
775 return ctx->i32_0;
776 }
777 }
778
779 /**
780 * Return the value of tgsi_ind_register for indexing.
781 * This is the indirect index with the constant offset added to it.
782 */
783 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
784 const struct tgsi_ind_register *ind,
785 unsigned addr_mul,
786 int rel_index)
787 {
788 LLVMValueRef result;
789
790 if (ind->File == TGSI_FILE_ADDRESS) {
791 result = ctx->addrs[ind->Index][ind->Swizzle];
792 result = LLVMBuildLoad(ctx->ac.builder, result, "");
793 } else {
794 struct tgsi_full_src_register src = {};
795
796 src.Register.File = ind->File;
797 src.Register.Index = ind->Index;
798
799 /* Set the second index to 0 for constants. */
800 if (ind->File == TGSI_FILE_CONSTANT)
801 src.Register.Dimension = 1;
802
803 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
804 TGSI_TYPE_SIGNED,
805 ind->Swizzle);
806 result = ac_to_integer(&ctx->ac, result);
807 }
808
809 if (addr_mul != 1)
810 result = LLVMBuildMul(ctx->ac.builder, result,
811 LLVMConstInt(ctx->i32, addr_mul, 0), "");
812 result = LLVMBuildAdd(ctx->ac.builder, result,
813 LLVMConstInt(ctx->i32, rel_index, 0), "");
814 return result;
815 }
816
817 /**
818 * Like si_get_indirect_index, but restricts the return value to a (possibly
819 * undefined) value inside [0..num).
820 */
821 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
822 const struct tgsi_ind_register *ind,
823 int rel_index, unsigned num)
824 {
825 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
826
827 return si_llvm_bound_index(ctx, result, num);
828 }
829
830
831 /**
832 * Calculate a dword address given an input or output register and a stride.
833 */
834 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
835 const struct tgsi_full_dst_register *dst,
836 const struct tgsi_full_src_register *src,
837 LLVMValueRef vertex_dw_stride,
838 LLVMValueRef base_addr)
839 {
840 struct tgsi_shader_info *info = &ctx->shader->selector->info;
841 ubyte *name, *index, *array_first;
842 int first, param;
843 struct tgsi_full_dst_register reg;
844
845 /* Set the register description. The address computation is the same
846 * for sources and destinations. */
847 if (src) {
848 reg.Register.File = src->Register.File;
849 reg.Register.Index = src->Register.Index;
850 reg.Register.Indirect = src->Register.Indirect;
851 reg.Register.Dimension = src->Register.Dimension;
852 reg.Indirect = src->Indirect;
853 reg.Dimension = src->Dimension;
854 reg.DimIndirect = src->DimIndirect;
855 } else
856 reg = *dst;
857
858 /* If the register is 2-dimensional (e.g. an array of vertices
859 * in a primitive), calculate the base address of the vertex. */
860 if (reg.Register.Dimension) {
861 LLVMValueRef index;
862
863 if (reg.Dimension.Indirect)
864 index = si_get_indirect_index(ctx, &reg.DimIndirect,
865 1, reg.Dimension.Index);
866 else
867 index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
868
869 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
870 LLVMBuildMul(ctx->ac.builder, index,
871 vertex_dw_stride, ""), "");
872 }
873
874 /* Get information about the register. */
875 if (reg.Register.File == TGSI_FILE_INPUT) {
876 name = info->input_semantic_name;
877 index = info->input_semantic_index;
878 array_first = info->input_array_first;
879 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
880 name = info->output_semantic_name;
881 index = info->output_semantic_index;
882 array_first = info->output_array_first;
883 } else {
884 assert(0);
885 return NULL;
886 }
887
888 if (reg.Register.Indirect) {
889 /* Add the relative address of the element. */
890 LLVMValueRef ind_index;
891
892 if (reg.Indirect.ArrayID)
893 first = array_first[reg.Indirect.ArrayID];
894 else
895 first = reg.Register.Index;
896
897 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
898 1, reg.Register.Index - first);
899
900 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
901 LLVMBuildMul(ctx->ac.builder, ind_index,
902 LLVMConstInt(ctx->i32, 4, 0), ""), "");
903
904 param = reg.Register.Dimension ?
905 si_shader_io_get_unique_index(name[first], index[first]) :
906 si_shader_io_get_unique_index_patch(name[first], index[first]);
907 } else {
908 param = reg.Register.Dimension ?
909 si_shader_io_get_unique_index(name[reg.Register.Index],
910 index[reg.Register.Index]) :
911 si_shader_io_get_unique_index_patch(name[reg.Register.Index],
912 index[reg.Register.Index]);
913 }
914
915 /* Add the base address of the element. */
916 return LLVMBuildAdd(ctx->ac.builder, base_addr,
917 LLVMConstInt(ctx->i32, param * 4, 0), "");
918 }
919
920 /* The offchip buffer layout for TCS->TES is
921 *
922 * - attribute 0 of patch 0 vertex 0
923 * - attribute 0 of patch 0 vertex 1
924 * - attribute 0 of patch 0 vertex 2
925 * ...
926 * - attribute 0 of patch 1 vertex 0
927 * - attribute 0 of patch 1 vertex 1
928 * ...
929 * - attribute 1 of patch 0 vertex 0
930 * - attribute 1 of patch 0 vertex 1
931 * ...
932 * - per patch attribute 0 of patch 0
933 * - per patch attribute 0 of patch 1
934 * ...
935 *
936 * Note that every attribute has 4 components.
937 */
938 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
939 LLVMValueRef rel_patch_id,
940 LLVMValueRef vertex_index,
941 LLVMValueRef param_index)
942 {
943 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
944 LLVMValueRef param_stride, constant16;
945
946 vertices_per_patch = get_num_tcs_out_vertices(ctx);
947 num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
948 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
949 num_patches, "");
950
951 constant16 = LLVMConstInt(ctx->i32, 16, 0);
952 if (vertex_index) {
953 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
954 vertices_per_patch, "");
955
956 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
957 vertex_index, "");
958
959 param_stride = total_vertices;
960 } else {
961 base_addr = rel_patch_id;
962 param_stride = num_patches;
963 }
964
965 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
966 LLVMBuildMul(ctx->ac.builder, param_index,
967 param_stride, ""), "");
968
969 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
970
971 if (!vertex_index) {
972 LLVMValueRef patch_data_offset =
973 unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
974
975 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
976 patch_data_offset, "");
977 }
978 return base_addr;
979 }
980
981 /* This is a generic helper that can be shared by the NIR and TGSI backends */
982 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
983 struct si_shader_context *ctx,
984 LLVMValueRef vertex_index,
985 LLVMValueRef param_index,
986 unsigned param_base,
987 ubyte *name,
988 ubyte *index,
989 bool is_patch)
990 {
991 unsigned param_index_base;
992
993 param_index_base = is_patch ?
994 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
995 si_shader_io_get_unique_index(name[param_base], index[param_base]);
996
997 if (param_index) {
998 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
999 LLVMConstInt(ctx->i32, param_index_base, 0),
1000 "");
1001 } else {
1002 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
1003 }
1004
1005 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
1006 vertex_index, param_index);
1007 }
1008
1009 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
1010 struct si_shader_context *ctx,
1011 const struct tgsi_full_dst_register *dst,
1012 const struct tgsi_full_src_register *src)
1013 {
1014 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1015 ubyte *name, *index, *array_first;
1016 struct tgsi_full_src_register reg;
1017 LLVMValueRef vertex_index = NULL;
1018 LLVMValueRef param_index = NULL;
1019 unsigned param_base;
1020
1021 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
1022
1023 if (reg.Register.Dimension) {
1024
1025 if (reg.Dimension.Indirect)
1026 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
1027 1, reg.Dimension.Index);
1028 else
1029 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
1030 }
1031
1032 /* Get information about the register. */
1033 if (reg.Register.File == TGSI_FILE_INPUT) {
1034 name = info->input_semantic_name;
1035 index = info->input_semantic_index;
1036 array_first = info->input_array_first;
1037 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1038 name = info->output_semantic_name;
1039 index = info->output_semantic_index;
1040 array_first = info->output_array_first;
1041 } else {
1042 assert(0);
1043 return NULL;
1044 }
1045
1046 if (reg.Register.Indirect) {
1047 if (reg.Indirect.ArrayID)
1048 param_base = array_first[reg.Indirect.ArrayID];
1049 else
1050 param_base = reg.Register.Index;
1051
1052 param_index = si_get_indirect_index(ctx, &reg.Indirect,
1053 1, reg.Register.Index - param_base);
1054
1055 } else {
1056 param_base = reg.Register.Index;
1057 }
1058
1059 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1060 param_index, param_base,
1061 name, index, !reg.Register.Dimension);
1062 }
1063
1064 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
1065 LLVMTypeRef type, unsigned swizzle,
1066 LLVMValueRef buffer, LLVMValueRef offset,
1067 LLVMValueRef base, bool can_speculate)
1068 {
1069 struct si_shader_context *ctx = si_shader_context(bld_base);
1070 LLVMValueRef value, value2;
1071 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
1072
1073 if (swizzle == ~0) {
1074 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1075 0, 1, 0, can_speculate, false);
1076
1077 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1078 }
1079
1080 if (!llvm_type_is_64bit(ctx, type)) {
1081 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1082 0, 1, 0, can_speculate, false);
1083
1084 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1085 return LLVMBuildExtractElement(ctx->ac.builder, value,
1086 LLVMConstInt(ctx->i32, swizzle, 0), "");
1087 }
1088
1089 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1090 swizzle * 4, 1, 0, can_speculate, false);
1091
1092 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1093 swizzle * 4 + 4, 1, 0, can_speculate, false);
1094
1095 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1096 }
1097
1098 /**
1099 * Load from LDS.
1100 *
1101 * \param type output value type
1102 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1103 * \param dw_addr address in dwords
1104 */
1105 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1106 LLVMTypeRef type, unsigned swizzle,
1107 LLVMValueRef dw_addr)
1108 {
1109 struct si_shader_context *ctx = si_shader_context(bld_base);
1110 LLVMValueRef value;
1111
1112 if (swizzle == ~0) {
1113 LLVMValueRef values[TGSI_NUM_CHANNELS];
1114
1115 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1116 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1117
1118 return lp_build_gather_values(&ctx->gallivm, values,
1119 TGSI_NUM_CHANNELS);
1120 }
1121
1122 /* Split 64-bit loads. */
1123 if (llvm_type_is_64bit(ctx, type)) {
1124 LLVMValueRef lo, hi;
1125
1126 lo = lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1127 hi = lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1128 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1129 }
1130
1131 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1132 LLVMConstInt(ctx->i32, swizzle, 0));
1133
1134 value = ac_lds_load(&ctx->ac, dw_addr);
1135
1136 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1137 }
1138
1139 /**
1140 * Store to LDS.
1141 *
1142 * \param swizzle offset (typically 0..3)
1143 * \param dw_addr address in dwords
1144 * \param value value to store
1145 */
1146 static void lds_store(struct si_shader_context *ctx,
1147 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1148 LLVMValueRef value)
1149 {
1150 dw_addr = lp_build_add(&ctx->bld_base.uint_bld, dw_addr,
1151 LLVMConstInt(ctx->i32, dw_offset_imm, 0));
1152
1153 ac_lds_store(&ctx->ac, dw_addr, value);
1154 }
1155
1156 static LLVMValueRef desc_from_addr_base64k(struct si_shader_context *ctx,
1157 unsigned param)
1158 {
1159 LLVMBuilderRef builder = ctx->ac.builder;
1160
1161 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1162 addr = LLVMBuildZExt(builder, addr, ctx->i64, "");
1163 addr = LLVMBuildShl(builder, addr, LLVMConstInt(ctx->i64, 16, 0), "");
1164
1165 uint64_t desc2 = 0xffffffff;
1166 uint64_t desc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1167 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1168 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1169 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1170 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1171 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1172 LLVMValueRef hi = LLVMConstInt(ctx->i64, desc2 | (desc3 << 32), 0);
1173
1174 LLVMValueRef desc = LLVMGetUndef(LLVMVectorType(ctx->i64, 2));
1175 desc = LLVMBuildInsertElement(builder, desc, addr, ctx->i32_0, "");
1176 desc = LLVMBuildInsertElement(builder, desc, hi, ctx->i32_1, "");
1177 return LLVMBuildBitCast(builder, desc, ctx->v4i32, "");
1178 }
1179
1180 static LLVMValueRef fetch_input_tcs(
1181 struct lp_build_tgsi_context *bld_base,
1182 const struct tgsi_full_src_register *reg,
1183 enum tgsi_opcode_type type, unsigned swizzle)
1184 {
1185 struct si_shader_context *ctx = si_shader_context(bld_base);
1186 LLVMValueRef dw_addr, stride;
1187
1188 stride = get_tcs_in_vertex_dw_stride(ctx);
1189 dw_addr = get_tcs_in_current_patch_offset(ctx);
1190 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1191
1192 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1193 }
1194
1195 static LLVMValueRef fetch_output_tcs(
1196 struct lp_build_tgsi_context *bld_base,
1197 const struct tgsi_full_src_register *reg,
1198 enum tgsi_opcode_type type, unsigned swizzle)
1199 {
1200 struct si_shader_context *ctx = si_shader_context(bld_base);
1201 LLVMValueRef dw_addr, stride;
1202
1203 if (reg->Register.Dimension) {
1204 stride = get_tcs_out_vertex_dw_stride(ctx);
1205 dw_addr = get_tcs_out_current_patch_offset(ctx);
1206 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1207 } else {
1208 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1209 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1210 }
1211
1212 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1213 }
1214
1215 static LLVMValueRef fetch_input_tes(
1216 struct lp_build_tgsi_context *bld_base,
1217 const struct tgsi_full_src_register *reg,
1218 enum tgsi_opcode_type type, unsigned swizzle)
1219 {
1220 struct si_shader_context *ctx = si_shader_context(bld_base);
1221 LLVMValueRef buffer, base, addr;
1222
1223 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1224
1225 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1226 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1227
1228 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1229 buffer, base, addr, true);
1230 }
1231
1232 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1233 const struct tgsi_full_instruction *inst,
1234 const struct tgsi_opcode_info *info,
1235 unsigned index,
1236 LLVMValueRef dst[4])
1237 {
1238 struct si_shader_context *ctx = si_shader_context(bld_base);
1239 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1240 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1241 unsigned chan_index;
1242 LLVMValueRef dw_addr, stride;
1243 LLVMValueRef buffer, base, buf_addr;
1244 LLVMValueRef values[4];
1245 bool skip_lds_store;
1246 bool is_tess_factor = false, is_tess_inner = false;
1247
1248 /* Only handle per-patch and per-vertex outputs here.
1249 * Vectors will be lowered to scalars and this function will be called again.
1250 */
1251 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1252 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1253 si_llvm_emit_store(bld_base, inst, info, index, dst);
1254 return;
1255 }
1256
1257 if (reg->Register.Dimension) {
1258 stride = get_tcs_out_vertex_dw_stride(ctx);
1259 dw_addr = get_tcs_out_current_patch_offset(ctx);
1260 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1261 skip_lds_store = !sh_info->reads_pervertex_outputs;
1262 } else {
1263 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1264 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1265 skip_lds_store = !sh_info->reads_perpatch_outputs;
1266
1267 if (!reg->Register.Indirect) {
1268 int name = sh_info->output_semantic_name[reg->Register.Index];
1269
1270 /* Always write tess factors into LDS for the TCS epilog. */
1271 if (name == TGSI_SEMANTIC_TESSINNER ||
1272 name == TGSI_SEMANTIC_TESSOUTER) {
1273 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1274 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1275 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1276 is_tess_factor = true;
1277 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1278 }
1279 }
1280 }
1281
1282 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1283
1284 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1285 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1286
1287 uint32_t writemask = reg->Register.WriteMask;
1288 while (writemask) {
1289 chan_index = u_bit_scan(&writemask);
1290 LLVMValueRef value = dst[chan_index];
1291
1292 if (inst->Instruction.Saturate)
1293 value = ac_build_clamp(&ctx->ac, value);
1294
1295 /* Skip LDS stores if there is no LDS read of this output. */
1296 if (!skip_lds_store)
1297 lds_store(ctx, chan_index, dw_addr, value);
1298
1299 value = ac_to_integer(&ctx->ac, value);
1300 values[chan_index] = value;
1301
1302 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1303 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1304 buf_addr, base,
1305 4 * chan_index, 1, 0, true, false);
1306 }
1307
1308 /* Write tess factors into VGPRs for the epilog. */
1309 if (is_tess_factor &&
1310 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1311 if (!is_tess_inner) {
1312 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1313 ctx->invoc0_tess_factors[chan_index]);
1314 } else if (chan_index < 2) {
1315 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1316 ctx->invoc0_tess_factors[4 + chan_index]);
1317 }
1318 }
1319 }
1320
1321 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1322 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1323 values, 4);
1324 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1325 base, 0, 1, 0, true, false);
1326 }
1327 }
1328
1329 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1330 unsigned input_index,
1331 unsigned vtx_offset_param,
1332 LLVMTypeRef type,
1333 unsigned swizzle)
1334 {
1335 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1336 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1337 struct si_shader *shader = ctx->shader;
1338 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1339 LLVMValueRef vtx_offset, soffset;
1340 struct tgsi_shader_info *info = &shader->selector->info;
1341 unsigned semantic_name = info->input_semantic_name[input_index];
1342 unsigned semantic_index = info->input_semantic_index[input_index];
1343 unsigned param;
1344 LLVMValueRef value;
1345
1346 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1347
1348 /* GFX9 has the ESGS ring in LDS. */
1349 if (ctx->screen->info.chip_class >= GFX9) {
1350 unsigned index = vtx_offset_param;
1351
1352 switch (index / 2) {
1353 case 0:
1354 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx01_offset,
1355 index % 2 ? 16 : 0, 16);
1356 break;
1357 case 1:
1358 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx23_offset,
1359 index % 2 ? 16 : 0, 16);
1360 break;
1361 case 2:
1362 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx45_offset,
1363 index % 2 ? 16 : 0, 16);
1364 break;
1365 default:
1366 assert(0);
1367 return NULL;
1368 }
1369
1370 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1371 LLVMConstInt(ctx->i32, param * 4, 0), "");
1372 return lds_load(bld_base, type, swizzle, vtx_offset);
1373 }
1374
1375 /* GFX6: input load from the ESGS ring in memory. */
1376 if (swizzle == ~0) {
1377 LLVMValueRef values[TGSI_NUM_CHANNELS];
1378 unsigned chan;
1379 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1380 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1381 type, chan);
1382 }
1383 return lp_build_gather_values(&ctx->gallivm, values,
1384 TGSI_NUM_CHANNELS);
1385 }
1386
1387 /* Get the vertex offset parameter on GFX6. */
1388 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1389
1390 vtx_offset = lp_build_mul_imm(uint, gs_vtx_offset, 4);
1391
1392 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1393
1394 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1395 vtx_offset, soffset, 0, 1, 0, true, false);
1396 if (llvm_type_is_64bit(ctx, type)) {
1397 LLVMValueRef value2;
1398 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1399
1400 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1401 ctx->i32_0, vtx_offset, soffset,
1402 0, 1, 0, true, false);
1403 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1404 }
1405 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1406 }
1407
1408 static LLVMValueRef fetch_input_gs(
1409 struct lp_build_tgsi_context *bld_base,
1410 const struct tgsi_full_src_register *reg,
1411 enum tgsi_opcode_type type,
1412 unsigned swizzle)
1413 {
1414 struct si_shader_context *ctx = si_shader_context(bld_base);
1415 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1416
1417 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1418 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1419 return get_primitive_id(ctx, swizzle);
1420
1421 if (!reg->Register.Dimension)
1422 return NULL;
1423
1424 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1425 reg->Dimension.Index,
1426 tgsi2llvmtype(bld_base, type),
1427 swizzle);
1428 }
1429
1430 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1431 {
1432 switch (interpolate) {
1433 case TGSI_INTERPOLATE_CONSTANT:
1434 return 0;
1435
1436 case TGSI_INTERPOLATE_LINEAR:
1437 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1438 return SI_PARAM_LINEAR_SAMPLE;
1439 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1440 return SI_PARAM_LINEAR_CENTROID;
1441 else
1442 return SI_PARAM_LINEAR_CENTER;
1443 break;
1444 case TGSI_INTERPOLATE_COLOR:
1445 case TGSI_INTERPOLATE_PERSPECTIVE:
1446 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1447 return SI_PARAM_PERSP_SAMPLE;
1448 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1449 return SI_PARAM_PERSP_CENTROID;
1450 else
1451 return SI_PARAM_PERSP_CENTER;
1452 break;
1453 default:
1454 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1455 return -1;
1456 }
1457 }
1458
1459 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1460 unsigned attr_index, unsigned chan,
1461 LLVMValueRef prim_mask,
1462 LLVMValueRef i, LLVMValueRef j)
1463 {
1464 if (i || j) {
1465 return ac_build_fs_interp(&ctx->ac,
1466 LLVMConstInt(ctx->i32, chan, 0),
1467 LLVMConstInt(ctx->i32, attr_index, 0),
1468 prim_mask, i, j);
1469 }
1470 return ac_build_fs_interp_mov(&ctx->ac,
1471 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1472 LLVMConstInt(ctx->i32, chan, 0),
1473 LLVMConstInt(ctx->i32, attr_index, 0),
1474 prim_mask);
1475 }
1476
1477 /**
1478 * Interpolate a fragment shader input.
1479 *
1480 * @param ctx context
1481 * @param input_index index of the input in hardware
1482 * @param semantic_name TGSI_SEMANTIC_*
1483 * @param semantic_index semantic index
1484 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1485 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1486 * @param interp_param interpolation weights (i,j)
1487 * @param prim_mask SI_PARAM_PRIM_MASK
1488 * @param face SI_PARAM_FRONT_FACE
1489 * @param result the return value (4 components)
1490 */
1491 static void interp_fs_input(struct si_shader_context *ctx,
1492 unsigned input_index,
1493 unsigned semantic_name,
1494 unsigned semantic_index,
1495 unsigned num_interp_inputs,
1496 unsigned colors_read_mask,
1497 LLVMValueRef interp_param,
1498 LLVMValueRef prim_mask,
1499 LLVMValueRef face,
1500 LLVMValueRef result[4])
1501 {
1502 LLVMValueRef i = NULL, j = NULL;
1503 unsigned chan;
1504
1505 /* fs.constant returns the param from the middle vertex, so it's not
1506 * really useful for flat shading. It's meant to be used for custom
1507 * interpolation (but the intrinsic can't fetch from the other two
1508 * vertices).
1509 *
1510 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1511 * to do the right thing. The only reason we use fs.constant is that
1512 * fs.interp cannot be used on integers, because they can be equal
1513 * to NaN.
1514 *
1515 * When interp is false we will use fs.constant or for newer llvm,
1516 * amdgcn.interp.mov.
1517 */
1518 bool interp = interp_param != NULL;
1519
1520 if (interp) {
1521 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1522 LLVMVectorType(ctx->f32, 2), "");
1523
1524 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1525 ctx->i32_0, "");
1526 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1527 ctx->i32_1, "");
1528 }
1529
1530 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1531 ctx->shader->key.part.ps.prolog.color_two_side) {
1532 LLVMValueRef is_face_positive;
1533
1534 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1535 * otherwise it's at offset "num_inputs".
1536 */
1537 unsigned back_attr_offset = num_interp_inputs;
1538 if (semantic_index == 1 && colors_read_mask & 0xf)
1539 back_attr_offset += 1;
1540
1541 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1542 face, ctx->i32_0, "");
1543
1544 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1545 LLVMValueRef front, back;
1546
1547 front = si_build_fs_interp(ctx,
1548 input_index, chan,
1549 prim_mask, i, j);
1550 back = si_build_fs_interp(ctx,
1551 back_attr_offset, chan,
1552 prim_mask, i, j);
1553
1554 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1555 is_face_positive,
1556 front,
1557 back,
1558 "");
1559 }
1560 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1561 result[0] = si_build_fs_interp(ctx, input_index,
1562 0, prim_mask, i, j);
1563 result[1] =
1564 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1565 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1566 } else {
1567 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1568 result[chan] = si_build_fs_interp(ctx,
1569 input_index, chan,
1570 prim_mask, i, j);
1571 }
1572 }
1573 }
1574
1575 void si_llvm_load_input_fs(
1576 struct si_shader_context *ctx,
1577 unsigned input_index,
1578 LLVMValueRef out[4])
1579 {
1580 struct lp_build_context *base = &ctx->bld_base.base;
1581 struct si_shader *shader = ctx->shader;
1582 struct tgsi_shader_info *info = &shader->selector->info;
1583 LLVMValueRef main_fn = ctx->main_fn;
1584 LLVMValueRef interp_param = NULL;
1585 int interp_param_idx;
1586 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1587 unsigned semantic_index = info->input_semantic_index[input_index];
1588 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1589 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1590
1591 /* Get colors from input VGPRs (set by the prolog). */
1592 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1593 unsigned colors_read = shader->selector->info.colors_read;
1594 unsigned mask = colors_read >> (semantic_index * 4);
1595 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1596 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1597
1598 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1599 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1600 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1601 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1602 return;
1603 }
1604
1605 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1606 if (interp_param_idx == -1)
1607 return;
1608 else if (interp_param_idx) {
1609 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1610 }
1611
1612 interp_fs_input(ctx, input_index, semantic_name,
1613 semantic_index, 0, /* this param is unused */
1614 shader->selector->info.colors_read, interp_param,
1615 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1616 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1617 &out[0]);
1618 }
1619
1620 static void declare_input_fs(
1621 struct si_shader_context *ctx,
1622 unsigned input_index,
1623 const struct tgsi_full_declaration *decl,
1624 LLVMValueRef out[4])
1625 {
1626 si_llvm_load_input_fs(ctx, input_index, out);
1627 }
1628
1629 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1630 {
1631 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1632 }
1633
1634
1635 /**
1636 * Load a dword from a constant buffer.
1637 */
1638 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1639 LLVMValueRef resource,
1640 LLVMValueRef offset)
1641 {
1642 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1643 0, 0, 0, true, true);
1644 }
1645
1646 static LLVMValueRef load_sample_position(struct si_shader_context *ctx, LLVMValueRef sample_id)
1647 {
1648 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1649 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1650 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1651 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1652
1653 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1654 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1655 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1656
1657 LLVMValueRef pos[4] = {
1658 buffer_load_const(ctx, resource, offset0),
1659 buffer_load_const(ctx, resource, offset1),
1660 LLVMConstReal(ctx->f32, 0),
1661 LLVMConstReal(ctx->f32, 0)
1662 };
1663
1664 return lp_build_gather_values(&ctx->gallivm, pos, 4);
1665 }
1666
1667 void si_load_system_value(struct si_shader_context *ctx,
1668 unsigned index,
1669 const struct tgsi_full_declaration *decl)
1670 {
1671 struct lp_build_context *bld = &ctx->bld_base.base;
1672 LLVMValueRef value = 0;
1673
1674 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
1675
1676 switch (decl->Semantic.Name) {
1677 case TGSI_SEMANTIC_INSTANCEID:
1678 value = ctx->abi.instance_id;
1679 break;
1680
1681 case TGSI_SEMANTIC_VERTEXID:
1682 value = LLVMBuildAdd(ctx->ac.builder,
1683 ctx->abi.vertex_id,
1684 ctx->abi.base_vertex, "");
1685 break;
1686
1687 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1688 /* Unused. Clarify the meaning in indexed vs. non-indexed
1689 * draws if this is ever used again. */
1690 assert(false);
1691 break;
1692
1693 case TGSI_SEMANTIC_BASEVERTEX:
1694 {
1695 /* For non-indexed draws, the base vertex set by the driver
1696 * (for direct draws) or the CP (for indirect draws) is the
1697 * first vertex ID, but GLSL expects 0 to be returned.
1698 */
1699 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
1700 LLVMValueRef indexed;
1701
1702 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1703 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1704
1705 value = LLVMBuildSelect(ctx->ac.builder, indexed,
1706 ctx->abi.base_vertex, ctx->i32_0, "");
1707 break;
1708 }
1709
1710 case TGSI_SEMANTIC_BASEINSTANCE:
1711 value = ctx->abi.start_instance;
1712 break;
1713
1714 case TGSI_SEMANTIC_DRAWID:
1715 value = ctx->abi.draw_id;
1716 break;
1717
1718 case TGSI_SEMANTIC_INVOCATIONID:
1719 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1720 value = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
1721 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1722 value = ctx->abi.gs_invocation_id;
1723 else
1724 assert(!"INVOCATIONID not implemented");
1725 break;
1726
1727 case TGSI_SEMANTIC_POSITION:
1728 {
1729 LLVMValueRef pos[4] = {
1730 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1731 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1732 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
1733 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
1734 LLVMGetParam(ctx->main_fn,
1735 SI_PARAM_POS_W_FLOAT)),
1736 };
1737 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
1738 break;
1739 }
1740
1741 case TGSI_SEMANTIC_FACE:
1742 value = ctx->abi.front_face;
1743 break;
1744
1745 case TGSI_SEMANTIC_SAMPLEID:
1746 value = get_sample_id(ctx);
1747 break;
1748
1749 case TGSI_SEMANTIC_SAMPLEPOS: {
1750 LLVMValueRef pos[4] = {
1751 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1752 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1753 LLVMConstReal(ctx->f32, 0),
1754 LLVMConstReal(ctx->f32, 0)
1755 };
1756 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
1757 TGSI_OPCODE_FRC, pos[0]);
1758 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
1759 TGSI_OPCODE_FRC, pos[1]);
1760 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
1761 break;
1762 }
1763
1764 case TGSI_SEMANTIC_SAMPLEMASK:
1765 /* This can only occur with the OpenGL Core profile, which
1766 * doesn't support smoothing.
1767 */
1768 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1769 break;
1770
1771 case TGSI_SEMANTIC_TESSCOORD:
1772 {
1773 LLVMValueRef coord[4] = {
1774 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1775 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1776 ctx->ac.f32_0,
1777 ctx->ac.f32_0
1778 };
1779
1780 /* For triangles, the vector should be (u, v, 1-u-v). */
1781 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1782 PIPE_PRIM_TRIANGLES)
1783 coord[2] = lp_build_sub(bld, ctx->ac.f32_1,
1784 lp_build_add(bld, coord[0], coord[1]));
1785
1786 value = lp_build_gather_values(&ctx->gallivm, coord, 4);
1787 break;
1788 }
1789
1790 case TGSI_SEMANTIC_VERTICESIN:
1791 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1792 value = unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6);
1793 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1794 value = get_num_tcs_out_vertices(ctx);
1795 else
1796 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1797 break;
1798
1799 case TGSI_SEMANTIC_TESSINNER:
1800 case TGSI_SEMANTIC_TESSOUTER:
1801 {
1802 LLVMValueRef buffer, base, addr;
1803 int param = si_shader_io_get_unique_index_patch(decl->Semantic.Name, 0);
1804
1805 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1806
1807 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1808 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1809 LLVMConstInt(ctx->i32, param, 0));
1810
1811 value = buffer_load(&ctx->bld_base, ctx->f32,
1812 ~0, buffer, base, addr, true);
1813
1814 break;
1815 }
1816
1817 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1818 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1819 {
1820 LLVMValueRef buf, slot, val[4];
1821 int i, offset;
1822
1823 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
1824 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1825 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
1826 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1827
1828 for (i = 0; i < 4; i++)
1829 val[i] = buffer_load_const(ctx, buf,
1830 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
1831 value = lp_build_gather_values(&ctx->gallivm, val, 4);
1832 break;
1833 }
1834
1835 case TGSI_SEMANTIC_PRIMID:
1836 value = get_primitive_id(ctx, 0);
1837 break;
1838
1839 case TGSI_SEMANTIC_GRID_SIZE:
1840 value = LLVMGetParam(ctx->main_fn, ctx->param_grid_size);
1841 break;
1842
1843 case TGSI_SEMANTIC_BLOCK_SIZE:
1844 {
1845 LLVMValueRef values[3];
1846 unsigned i;
1847 unsigned *properties = ctx->shader->selector->info.properties;
1848
1849 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1850 unsigned sizes[3] = {
1851 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1852 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1853 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1854 };
1855
1856 for (i = 0; i < 3; ++i)
1857 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1858
1859 value = lp_build_gather_values(&ctx->gallivm, values, 3);
1860 } else {
1861 value = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1862 }
1863 break;
1864 }
1865
1866 case TGSI_SEMANTIC_BLOCK_ID:
1867 {
1868 LLVMValueRef values[3];
1869
1870 for (int i = 0; i < 3; i++) {
1871 values[i] = ctx->i32_0;
1872 if (ctx->param_block_id[i] >= 0) {
1873 values[i] = LLVMGetParam(ctx->main_fn,
1874 ctx->param_block_id[i]);
1875 }
1876 }
1877 value = lp_build_gather_values(&ctx->gallivm, values, 3);
1878 break;
1879 }
1880
1881 case TGSI_SEMANTIC_THREAD_ID:
1882 value = LLVMGetParam(ctx->main_fn, ctx->param_thread_id);
1883 break;
1884
1885 case TGSI_SEMANTIC_HELPER_INVOCATION:
1886 value = lp_build_intrinsic(ctx->ac.builder,
1887 "llvm.amdgcn.ps.live",
1888 ctx->i1, NULL, 0,
1889 LP_FUNC_ATTR_READNONE);
1890 value = LLVMBuildNot(ctx->ac.builder, value, "");
1891 value = LLVMBuildSExt(ctx->ac.builder, value, ctx->i32, "");
1892 break;
1893
1894 case TGSI_SEMANTIC_SUBGROUP_SIZE:
1895 value = LLVMConstInt(ctx->i32, 64, 0);
1896 break;
1897
1898 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
1899 value = ac_get_thread_id(&ctx->ac);
1900 break;
1901
1902 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
1903 {
1904 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1905 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
1906 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
1907 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
1908 break;
1909 }
1910
1911 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
1912 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
1913 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
1914 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
1915 {
1916 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1917 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
1918 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
1919 /* All bits set except LSB */
1920 value = LLVMConstInt(ctx->i64, -2, 0);
1921 } else {
1922 /* All bits set */
1923 value = LLVMConstInt(ctx->i64, -1, 0);
1924 }
1925 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
1926 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
1927 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
1928 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
1929 value = LLVMBuildNot(ctx->ac.builder, value, "");
1930 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
1931 break;
1932 }
1933
1934 default:
1935 assert(!"unknown system value");
1936 return;
1937 }
1938
1939 ctx->system_values[index] = value;
1940 }
1941
1942 void si_declare_compute_memory(struct si_shader_context *ctx,
1943 const struct tgsi_full_declaration *decl)
1944 {
1945 struct si_shader_selector *sel = ctx->shader->selector;
1946
1947 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1948 LLVMValueRef var;
1949
1950 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1951 assert(decl->Range.First == decl->Range.Last);
1952 assert(!ctx->ac.lds);
1953
1954 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
1955 LLVMArrayType(ctx->i8, sel->local_size),
1956 "compute_lds",
1957 LOCAL_ADDR_SPACE);
1958 LLVMSetAlignment(var, 4);
1959
1960 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
1961 }
1962
1963 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1964 {
1965 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1966 ctx->param_const_and_shader_buffers);
1967
1968 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
1969 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
1970 }
1971
1972 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
1973 {
1974 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1975 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
1976
1977 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
1978 index = LLVMBuildAdd(ctx->ac.builder, index,
1979 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
1980
1981 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
1982 }
1983
1984 static LLVMValueRef
1985 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
1986 {
1987 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1988 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
1989 ctx->param_const_and_shader_buffers);
1990
1991 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
1992 index = LLVMBuildSub(ctx->ac.builder,
1993 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
1994 index, "");
1995
1996 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
1997 }
1998
1999 static LLVMValueRef fetch_constant(
2000 struct lp_build_tgsi_context *bld_base,
2001 const struct tgsi_full_src_register *reg,
2002 enum tgsi_opcode_type type,
2003 unsigned swizzle)
2004 {
2005 struct si_shader_context *ctx = si_shader_context(bld_base);
2006 struct si_shader_selector *sel = ctx->shader->selector;
2007 const struct tgsi_ind_register *ireg = &reg->Indirect;
2008 unsigned buf, idx;
2009
2010 LLVMValueRef addr, bufp;
2011
2012 if (swizzle == LP_CHAN_ALL) {
2013 unsigned chan;
2014 LLVMValueRef values[4];
2015 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2016 values[chan] = fetch_constant(bld_base, reg, type, chan);
2017
2018 return lp_build_gather_values(&ctx->gallivm, values, 4);
2019 }
2020
2021 /* Split 64-bit loads. */
2022 if (tgsi_type_is_64bit(type)) {
2023 LLVMValueRef lo, hi;
2024
2025 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2026 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle + 1);
2027 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2028 lo, hi);
2029 }
2030
2031 idx = reg->Register.Index * 4 + swizzle;
2032 if (reg->Register.Indirect) {
2033 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2034 } else {
2035 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2036 }
2037
2038 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2039 if (sel->info.const_buffers_declared == 1 &&
2040 sel->info.shader_buffers_declared == 0) {
2041 LLVMValueRef ptr =
2042 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2043
2044 /* This enables use of s_load_dword and flat_load_dword for const buffer 0
2045 * loads, and up to x4 load opcode merging. However, it leads to horrible
2046 * code reducing SIMD wave occupancy from 8 to 2 in many cases.
2047 *
2048 * Using s_buffer_load_dword (x1) seems to be the best option right now.
2049 *
2050 * LLVM 5.0 on SI doesn't insert a required s_nop between SALU setting
2051 * a descriptor and s_buffer_load_dword using it, so we can't expand
2052 * the pointer into a full descriptor like below. We have to use
2053 * s_load_dword instead. The only case when LLVM 5.0 would select
2054 * s_buffer_load_dword (that we have to prevent) is when we use use
2055 * a literal offset where we don't need bounds checking.
2056 */
2057 if (ctx->screen->info.chip_class == SI &&
2058 HAVE_LLVM < 0x0600 &&
2059 !reg->Register.Indirect) {
2060 addr = LLVMBuildLShr(ctx->ac.builder, addr, LLVMConstInt(ctx->i32, 2, 0), "");
2061 LLVMValueRef result = ac_build_load_invariant(&ctx->ac, ptr, addr);
2062 return bitcast(bld_base, type, result);
2063 }
2064
2065 /* Do the bounds checking with a descriptor, because
2066 * doing computation and manual bounds checking of 64-bit
2067 * addresses generates horrible VALU code with very high
2068 * VGPR usage and very low SIMD occupancy.
2069 */
2070 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->i64, "");
2071 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ctx->v2i32, "");
2072
2073 LLVMValueRef desc_elems[] = {
2074 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_0, ""),
2075 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_1, ""),
2076 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2077 LLVMConstInt(ctx->i32,
2078 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2079 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2080 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2081 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2082 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2083 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2084 };
2085 LLVMValueRef desc = ac_build_gather_values(&ctx->ac, desc_elems, 4);
2086 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2087 return bitcast(bld_base, type, result);
2088 }
2089
2090 assert(reg->Register.Dimension);
2091 buf = reg->Dimension.Index;
2092
2093 if (reg->Dimension.Indirect) {
2094 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2095 LLVMValueRef index;
2096 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2097 reg->Dimension.Index,
2098 ctx->num_const_buffers);
2099 index = LLVMBuildAdd(ctx->ac.builder, index,
2100 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2101 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2102 } else
2103 bufp = load_const_buffer_desc(ctx, buf);
2104
2105 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2106 }
2107
2108 /* Upper 16 bits must be zero. */
2109 static LLVMValueRef si_llvm_pack_two_int16(struct si_shader_context *ctx,
2110 LLVMValueRef val[2])
2111 {
2112 return LLVMBuildOr(ctx->ac.builder, val[0],
2113 LLVMBuildShl(ctx->ac.builder, val[1],
2114 LLVMConstInt(ctx->i32, 16, 0),
2115 ""), "");
2116 }
2117
2118 /* Upper 16 bits are ignored and will be dropped. */
2119 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct si_shader_context *ctx,
2120 LLVMValueRef val[2])
2121 {
2122 LLVMValueRef v[2] = {
2123 LLVMBuildAnd(ctx->ac.builder, val[0],
2124 LLVMConstInt(ctx->i32, 0xffff, 0), ""),
2125 val[1],
2126 };
2127 return si_llvm_pack_two_int16(ctx, v);
2128 }
2129
2130 /* Initialize arguments for the shader export intrinsic */
2131 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2132 LLVMValueRef *values,
2133 unsigned target,
2134 struct ac_export_args *args)
2135 {
2136 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2137 LLVMBuilderRef builder = ctx->ac.builder;
2138 LLVMValueRef val[4];
2139 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2140 unsigned chan;
2141 bool is_int8, is_int10;
2142
2143 /* Default is 0xf. Adjusted below depending on the format. */
2144 args->enabled_channels = 0xf; /* writemask */
2145
2146 /* Specify whether the EXEC mask represents the valid mask */
2147 args->valid_mask = 0;
2148
2149 /* Specify whether this is the last export */
2150 args->done = 0;
2151
2152 /* Specify the target we are exporting */
2153 args->target = target;
2154
2155 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2156 const struct si_shader_key *key = &ctx->shader->key;
2157 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2158 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2159
2160 assert(cbuf >= 0 && cbuf < 8);
2161 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2162 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2163 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2164 }
2165
2166 args->compr = false;
2167 args->out[0] = f32undef;
2168 args->out[1] = f32undef;
2169 args->out[2] = f32undef;
2170 args->out[3] = f32undef;
2171
2172 switch (spi_shader_col_format) {
2173 case V_028714_SPI_SHADER_ZERO:
2174 args->enabled_channels = 0; /* writemask */
2175 args->target = V_008DFC_SQ_EXP_NULL;
2176 break;
2177
2178 case V_028714_SPI_SHADER_32_R:
2179 args->enabled_channels = 1; /* writemask */
2180 args->out[0] = values[0];
2181 break;
2182
2183 case V_028714_SPI_SHADER_32_GR:
2184 args->enabled_channels = 0x3; /* writemask */
2185 args->out[0] = values[0];
2186 args->out[1] = values[1];
2187 break;
2188
2189 case V_028714_SPI_SHADER_32_AR:
2190 args->enabled_channels = 0x9; /* writemask */
2191 args->out[0] = values[0];
2192 args->out[3] = values[3];
2193 break;
2194
2195 case V_028714_SPI_SHADER_FP16_ABGR:
2196 args->compr = 1; /* COMPR flag */
2197
2198 for (chan = 0; chan < 2; chan++) {
2199 LLVMValueRef pack_args[2] = {
2200 values[2 * chan],
2201 values[2 * chan + 1]
2202 };
2203 LLVMValueRef packed;
2204
2205 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
2206 args->out[chan] = ac_to_float(&ctx->ac, packed);
2207 }
2208 break;
2209
2210 case V_028714_SPI_SHADER_UNORM16_ABGR:
2211 for (chan = 0; chan < 4; chan++) {
2212 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
2213 val[chan] = LLVMBuildFMul(builder, val[chan],
2214 LLVMConstReal(ctx->f32, 65535), "");
2215 val[chan] = LLVMBuildFAdd(builder, val[chan],
2216 LLVMConstReal(ctx->f32, 0.5), "");
2217 val[chan] = LLVMBuildFPToUI(builder, val[chan],
2218 ctx->i32, "");
2219 }
2220
2221 args->compr = 1; /* COMPR flag */
2222 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val));
2223 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val+2));
2224 break;
2225
2226 case V_028714_SPI_SHADER_SNORM16_ABGR:
2227 for (chan = 0; chan < 4; chan++) {
2228 /* Clamp between [-1, 1]. */
2229 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base, TGSI_OPCODE_MIN,
2230 values[chan],
2231 LLVMConstReal(ctx->f32, 1));
2232 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base, TGSI_OPCODE_MAX,
2233 val[chan],
2234 LLVMConstReal(ctx->f32, -1));
2235 /* Convert to a signed integer in [-32767, 32767]. */
2236 val[chan] = LLVMBuildFMul(builder, val[chan],
2237 LLVMConstReal(ctx->f32, 32767), "");
2238 /* If positive, add 0.5, else add -0.5. */
2239 val[chan] = LLVMBuildFAdd(builder, val[chan],
2240 LLVMBuildSelect(builder,
2241 LLVMBuildFCmp(builder, LLVMRealOGE,
2242 val[chan], ctx->ac.f32_0, ""),
2243 LLVMConstReal(ctx->f32, 0.5),
2244 LLVMConstReal(ctx->f32, -0.5), ""), "");
2245 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2246 }
2247
2248 args->compr = 1; /* COMPR flag */
2249 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val));
2250 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val+2));
2251 break;
2252
2253 case V_028714_SPI_SHADER_UINT16_ABGR: {
2254 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2255 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
2256 LLVMValueRef max_alpha =
2257 !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
2258
2259 /* Clamp. */
2260 for (chan = 0; chan < 4; chan++) {
2261 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
2262 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base, TGSI_OPCODE_UMIN,
2263 val[chan],
2264 chan == 3 ? max_alpha : max_rgb);
2265 }
2266
2267 args->compr = 1; /* COMPR flag */
2268 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val));
2269 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val+2));
2270 break;
2271 }
2272
2273 case V_028714_SPI_SHADER_SINT16_ABGR: {
2274 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2275 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
2276 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
2277 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
2278 LLVMValueRef max_alpha =
2279 !is_int10 ? max_rgb : ctx->i32_1;
2280 LLVMValueRef min_alpha =
2281 !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
2282
2283 /* Clamp. */
2284 for (chan = 0; chan < 4; chan++) {
2285 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
2286 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base,
2287 TGSI_OPCODE_IMIN,
2288 val[chan], chan == 3 ? max_alpha : max_rgb);
2289 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base,
2290 TGSI_OPCODE_IMAX,
2291 val[chan], chan == 3 ? min_alpha : min_rgb);
2292 }
2293
2294 args->compr = 1; /* COMPR flag */
2295 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val));
2296 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val+2));
2297 break;
2298 }
2299
2300 case V_028714_SPI_SHADER_32_ABGR:
2301 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2302 break;
2303 }
2304 }
2305
2306 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2307 LLVMValueRef alpha)
2308 {
2309 struct si_shader_context *ctx = si_shader_context(bld_base);
2310
2311 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2312 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2313 [PIPE_FUNC_LESS] = LLVMRealOLT,
2314 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2315 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2316 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2317 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2318 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2319 };
2320 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2321 assert(cond);
2322
2323 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2324 SI_PARAM_ALPHA_REF);
2325 LLVMValueRef alpha_pass =
2326 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2327 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2328 } else {
2329 ac_build_kill_if_false(&ctx->ac, LLVMConstInt(ctx->i1, 0, 0));
2330 }
2331 }
2332
2333 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2334 LLVMValueRef alpha,
2335 unsigned samplemask_param)
2336 {
2337 struct si_shader_context *ctx = si_shader_context(bld_base);
2338 LLVMValueRef coverage;
2339
2340 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2341 coverage = LLVMGetParam(ctx->main_fn,
2342 samplemask_param);
2343 coverage = ac_to_integer(&ctx->ac, coverage);
2344
2345 coverage = lp_build_intrinsic(ctx->ac.builder, "llvm.ctpop.i32",
2346 ctx->i32,
2347 &coverage, 1, LP_FUNC_ATTR_READNONE);
2348
2349 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2350 ctx->f32, "");
2351
2352 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2353 LLVMConstReal(ctx->f32,
2354 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2355
2356 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2357 }
2358
2359 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2360 struct ac_export_args *pos, LLVMValueRef *out_elts)
2361 {
2362 unsigned reg_index;
2363 unsigned chan;
2364 unsigned const_chan;
2365 LLVMValueRef base_elt;
2366 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2367 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2368 SI_VS_CONST_CLIP_PLANES, 0);
2369 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2370
2371 for (reg_index = 0; reg_index < 2; reg_index ++) {
2372 struct ac_export_args *args = &pos[2 + reg_index];
2373
2374 args->out[0] =
2375 args->out[1] =
2376 args->out[2] =
2377 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2378
2379 /* Compute dot products of position and user clip plane vectors */
2380 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2381 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2382 LLVMValueRef addr =
2383 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2384 const_chan) * 4, 0);
2385 base_elt = buffer_load_const(ctx, const_resource,
2386 addr);
2387 args->out[chan] =
2388 lp_build_add(&ctx->bld_base.base, args->out[chan],
2389 lp_build_mul(&ctx->bld_base.base, base_elt,
2390 out_elts[const_chan]));
2391 }
2392 }
2393
2394 args->enabled_channels = 0xf;
2395 args->valid_mask = 0;
2396 args->done = 0;
2397 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2398 args->compr = 0;
2399 }
2400 }
2401
2402 static void si_dump_streamout(struct pipe_stream_output_info *so)
2403 {
2404 unsigned i;
2405
2406 if (so->num_outputs)
2407 fprintf(stderr, "STREAMOUT\n");
2408
2409 for (i = 0; i < so->num_outputs; i++) {
2410 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2411 so->output[i].start_component;
2412 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2413 i, so->output[i].output_buffer,
2414 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2415 so->output[i].register_index,
2416 mask & 1 ? "x" : "",
2417 mask & 2 ? "y" : "",
2418 mask & 4 ? "z" : "",
2419 mask & 8 ? "w" : "");
2420 }
2421 }
2422
2423 static void emit_streamout_output(struct si_shader_context *ctx,
2424 LLVMValueRef const *so_buffers,
2425 LLVMValueRef const *so_write_offsets,
2426 struct pipe_stream_output *stream_out,
2427 struct si_shader_output_values *shader_out)
2428 {
2429 unsigned buf_idx = stream_out->output_buffer;
2430 unsigned start = stream_out->start_component;
2431 unsigned num_comps = stream_out->num_components;
2432 LLVMValueRef out[4];
2433
2434 assert(num_comps && num_comps <= 4);
2435 if (!num_comps || num_comps > 4)
2436 return;
2437
2438 /* Load the output as int. */
2439 for (int j = 0; j < num_comps; j++) {
2440 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2441
2442 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2443 }
2444
2445 /* Pack the output. */
2446 LLVMValueRef vdata = NULL;
2447
2448 switch (num_comps) {
2449 case 1: /* as i32 */
2450 vdata = out[0];
2451 break;
2452 case 2: /* as v2i32 */
2453 case 3: /* as v4i32 (aligned to 4) */
2454 case 4: /* as v4i32 */
2455 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2456 for (int j = 0; j < num_comps; j++) {
2457 vdata = LLVMBuildInsertElement(ctx->ac.builder, vdata, out[j],
2458 LLVMConstInt(ctx->i32, j, 0), "");
2459 }
2460 break;
2461 }
2462
2463 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2464 vdata, num_comps,
2465 so_write_offsets[buf_idx],
2466 ctx->i32_0,
2467 stream_out->dst_offset * 4, 1, 1, true, false);
2468 }
2469
2470 /**
2471 * Write streamout data to buffers for vertex stream @p stream (different
2472 * vertex streams can occur for GS copy shaders).
2473 */
2474 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2475 struct si_shader_output_values *outputs,
2476 unsigned noutput, unsigned stream)
2477 {
2478 struct si_shader_selector *sel = ctx->shader->selector;
2479 struct pipe_stream_output_info *so = &sel->so;
2480 LLVMBuilderRef builder = ctx->ac.builder;
2481 int i;
2482 struct lp_build_if_state if_ctx;
2483
2484 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2485 LLVMValueRef so_vtx_count =
2486 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2487
2488 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2489
2490 /* can_emit = tid < so_vtx_count; */
2491 LLVMValueRef can_emit =
2492 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2493
2494 /* Emit the streamout code conditionally. This actually avoids
2495 * out-of-bounds buffer access. The hw tells us via the SGPR
2496 * (so_vtx_count) which threads are allowed to emit streamout data. */
2497 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2498 {
2499 /* The buffer offset is computed as follows:
2500 * ByteOffset = streamout_offset[buffer_id]*4 +
2501 * (streamout_write_index + thread_id)*stride[buffer_id] +
2502 * attrib_offset
2503 */
2504
2505 LLVMValueRef so_write_index =
2506 LLVMGetParam(ctx->main_fn,
2507 ctx->param_streamout_write_index);
2508
2509 /* Compute (streamout_write_index + thread_id). */
2510 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2511
2512 /* Load the descriptor and compute the write offset for each
2513 * enabled buffer. */
2514 LLVMValueRef so_write_offset[4] = {};
2515 LLVMValueRef so_buffers[4];
2516 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2517 ctx->param_rw_buffers);
2518
2519 for (i = 0; i < 4; i++) {
2520 if (!so->stride[i])
2521 continue;
2522
2523 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2524 SI_VS_STREAMOUT_BUF0 + i, 0);
2525
2526 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2527
2528 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2529 ctx->param_streamout_offset[i]);
2530 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2531
2532 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2533 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2534 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2535 }
2536
2537 /* Write streamout data. */
2538 for (i = 0; i < so->num_outputs; i++) {
2539 unsigned reg = so->output[i].register_index;
2540
2541 if (reg >= noutput)
2542 continue;
2543
2544 if (stream != so->output[i].stream)
2545 continue;
2546
2547 emit_streamout_output(ctx, so_buffers, so_write_offset,
2548 &so->output[i], &outputs[reg]);
2549 }
2550 }
2551 lp_build_endif(&if_ctx);
2552 }
2553
2554 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2555 LLVMValueRef *values)
2556 {
2557 struct ac_export_args args;
2558
2559 si_llvm_init_export_args(ctx, values,
2560 V_008DFC_SQ_EXP_PARAM + index, &args);
2561 ac_build_export(&ctx->ac, &args);
2562 }
2563
2564 static void si_build_param_exports(struct si_shader_context *ctx,
2565 struct si_shader_output_values *outputs,
2566 unsigned noutput)
2567 {
2568 struct si_shader *shader = ctx->shader;
2569 unsigned param_count = 0;
2570
2571 for (unsigned i = 0; i < noutput; i++) {
2572 unsigned semantic_name = outputs[i].semantic_name;
2573 unsigned semantic_index = outputs[i].semantic_index;
2574
2575 if (outputs[i].vertex_stream[0] != 0 &&
2576 outputs[i].vertex_stream[1] != 0 &&
2577 outputs[i].vertex_stream[2] != 0 &&
2578 outputs[i].vertex_stream[3] != 0)
2579 continue;
2580
2581 switch (semantic_name) {
2582 case TGSI_SEMANTIC_LAYER:
2583 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2584 case TGSI_SEMANTIC_CLIPDIST:
2585 case TGSI_SEMANTIC_COLOR:
2586 case TGSI_SEMANTIC_BCOLOR:
2587 case TGSI_SEMANTIC_PRIMID:
2588 case TGSI_SEMANTIC_FOG:
2589 case TGSI_SEMANTIC_TEXCOORD:
2590 case TGSI_SEMANTIC_GENERIC:
2591 break;
2592 default:
2593 continue;
2594 }
2595
2596 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2597 semantic_index < SI_MAX_IO_GENERIC) &&
2598 shader->key.opt.kill_outputs &
2599 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2600 continue;
2601
2602 si_export_param(ctx, param_count, outputs[i].values);
2603
2604 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2605 shader->info.vs_output_param_offset[i] = param_count++;
2606 }
2607
2608 shader->info.nr_param_exports = param_count;
2609 }
2610
2611 /* Generate export instructions for hardware VS shader stage */
2612 static void si_llvm_export_vs(struct si_shader_context *ctx,
2613 struct si_shader_output_values *outputs,
2614 unsigned noutput)
2615 {
2616 struct si_shader *shader = ctx->shader;
2617 struct ac_export_args pos_args[4] = {};
2618 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2619 unsigned pos_idx;
2620 int i;
2621
2622 /* Build position exports. */
2623 for (i = 0; i < noutput; i++) {
2624 switch (outputs[i].semantic_name) {
2625 case TGSI_SEMANTIC_POSITION:
2626 si_llvm_init_export_args(ctx, outputs[i].values,
2627 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2628 break;
2629 case TGSI_SEMANTIC_PSIZE:
2630 psize_value = outputs[i].values[0];
2631 break;
2632 case TGSI_SEMANTIC_LAYER:
2633 layer_value = outputs[i].values[0];
2634 break;
2635 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2636 viewport_index_value = outputs[i].values[0];
2637 break;
2638 case TGSI_SEMANTIC_EDGEFLAG:
2639 edgeflag_value = outputs[i].values[0];
2640 break;
2641 case TGSI_SEMANTIC_CLIPDIST:
2642 if (!shader->key.opt.clip_disable) {
2643 unsigned index = 2 + outputs[i].semantic_index;
2644 si_llvm_init_export_args(ctx, outputs[i].values,
2645 V_008DFC_SQ_EXP_POS + index,
2646 &pos_args[index]);
2647 }
2648 break;
2649 case TGSI_SEMANTIC_CLIPVERTEX:
2650 if (!shader->key.opt.clip_disable) {
2651 si_llvm_emit_clipvertex(ctx, pos_args,
2652 outputs[i].values);
2653 }
2654 break;
2655 }
2656 }
2657
2658 /* We need to add the position output manually if it's missing. */
2659 if (!pos_args[0].out[0]) {
2660 pos_args[0].enabled_channels = 0xf; /* writemask */
2661 pos_args[0].valid_mask = 0; /* EXEC mask */
2662 pos_args[0].done = 0; /* last export? */
2663 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2664 pos_args[0].compr = 0; /* COMPR flag */
2665 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2666 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2667 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2668 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2669 }
2670
2671 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2672 if (shader->selector->info.writes_psize ||
2673 shader->selector->info.writes_edgeflag ||
2674 shader->selector->info.writes_viewport_index ||
2675 shader->selector->info.writes_layer) {
2676 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2677 (shader->selector->info.writes_edgeflag << 1) |
2678 (shader->selector->info.writes_layer << 2);
2679
2680 pos_args[1].valid_mask = 0; /* EXEC mask */
2681 pos_args[1].done = 0; /* last export? */
2682 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2683 pos_args[1].compr = 0; /* COMPR flag */
2684 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2685 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2686 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2687 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2688
2689 if (shader->selector->info.writes_psize)
2690 pos_args[1].out[0] = psize_value;
2691
2692 if (shader->selector->info.writes_edgeflag) {
2693 /* The output is a float, but the hw expects an integer
2694 * with the first bit containing the edge flag. */
2695 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2696 edgeflag_value,
2697 ctx->i32, "");
2698 edgeflag_value = ac_build_umin(&ctx->ac,
2699 edgeflag_value,
2700 ctx->i32_1);
2701
2702 /* The LLVM intrinsic expects a float. */
2703 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2704 }
2705
2706 if (ctx->screen->info.chip_class >= GFX9) {
2707 /* GFX9 has the layer in out.z[10:0] and the viewport
2708 * index in out.z[19:16].
2709 */
2710 if (shader->selector->info.writes_layer)
2711 pos_args[1].out[2] = layer_value;
2712
2713 if (shader->selector->info.writes_viewport_index) {
2714 LLVMValueRef v = viewport_index_value;
2715
2716 v = ac_to_integer(&ctx->ac, v);
2717 v = LLVMBuildShl(ctx->ac.builder, v,
2718 LLVMConstInt(ctx->i32, 16, 0), "");
2719 v = LLVMBuildOr(ctx->ac.builder, v,
2720 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2721 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2722 pos_args[1].enabled_channels |= 1 << 2;
2723 }
2724 } else {
2725 if (shader->selector->info.writes_layer)
2726 pos_args[1].out[2] = layer_value;
2727
2728 if (shader->selector->info.writes_viewport_index) {
2729 pos_args[1].out[3] = viewport_index_value;
2730 pos_args[1].enabled_channels |= 1 << 3;
2731 }
2732 }
2733 }
2734
2735 for (i = 0; i < 4; i++)
2736 if (pos_args[i].out[0])
2737 shader->info.nr_pos_exports++;
2738
2739 pos_idx = 0;
2740 for (i = 0; i < 4; i++) {
2741 if (!pos_args[i].out[0])
2742 continue;
2743
2744 /* Specify the target we are exporting */
2745 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2746
2747 if (pos_idx == shader->info.nr_pos_exports)
2748 /* Specify that this is the last export */
2749 pos_args[i].done = 1;
2750
2751 ac_build_export(&ctx->ac, &pos_args[i]);
2752 }
2753
2754 /* Build parameter exports. */
2755 si_build_param_exports(ctx, outputs, noutput);
2756 }
2757
2758 /**
2759 * Forward all outputs from the vertex shader to the TES. This is only used
2760 * for the fixed function TCS.
2761 */
2762 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2763 {
2764 struct si_shader_context *ctx = si_shader_context(bld_base);
2765 LLVMValueRef invocation_id, buffer, buffer_offset;
2766 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2767 uint64_t inputs;
2768
2769 invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
2770 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
2771 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2772
2773 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
2774 lds_vertex_offset = LLVMBuildMul(ctx->ac.builder, invocation_id,
2775 lds_vertex_stride, "");
2776 lds_base = get_tcs_in_current_patch_offset(ctx);
2777 lds_base = LLVMBuildAdd(ctx->ac.builder, lds_base, lds_vertex_offset, "");
2778
2779 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
2780 while (inputs) {
2781 unsigned i = u_bit_scan64(&inputs);
2782
2783 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2784 LLVMConstInt(ctx->i32, 4 * i, 0),
2785 "");
2786
2787 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2788 get_rel_patch_id(ctx),
2789 invocation_id,
2790 LLVMConstInt(ctx->i32, i, 0));
2791
2792 LLVMValueRef value = lds_load(bld_base, ctx->ac.i32, ~0,
2793 lds_ptr);
2794
2795 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
2796 buffer_offset, 0, 1, 0, true, false);
2797 }
2798 }
2799
2800 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2801 LLVMValueRef rel_patch_id,
2802 LLVMValueRef invocation_id,
2803 LLVMValueRef tcs_out_current_patch_data_offset,
2804 LLVMValueRef invoc0_tf_outer[4],
2805 LLVMValueRef invoc0_tf_inner[2])
2806 {
2807 struct si_shader_context *ctx = si_shader_context(bld_base);
2808 struct si_shader *shader = ctx->shader;
2809 unsigned tess_inner_index, tess_outer_index;
2810 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2811 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2812 unsigned stride, outer_comps, inner_comps, i, offset;
2813 struct lp_build_if_state if_ctx, inner_if_ctx;
2814
2815 /* Add a barrier before loading tess factors from LDS. */
2816 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
2817 si_llvm_emit_barrier(NULL, bld_base, NULL);
2818
2819 /* Do this only for invocation 0, because the tess levels are per-patch,
2820 * not per-vertex.
2821 *
2822 * This can't jump, because invocation 0 executes this. It should
2823 * at least mask out the loads and stores for other invocations.
2824 */
2825 lp_build_if(&if_ctx, &ctx->gallivm,
2826 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2827 invocation_id, ctx->i32_0, ""));
2828
2829 /* Determine the layout of one tess factor element in the buffer. */
2830 switch (shader->key.part.tcs.epilog.prim_mode) {
2831 case PIPE_PRIM_LINES:
2832 stride = 2; /* 2 dwords, 1 vec2 store */
2833 outer_comps = 2;
2834 inner_comps = 0;
2835 break;
2836 case PIPE_PRIM_TRIANGLES:
2837 stride = 4; /* 4 dwords, 1 vec4 store */
2838 outer_comps = 3;
2839 inner_comps = 1;
2840 break;
2841 case PIPE_PRIM_QUADS:
2842 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2843 outer_comps = 4;
2844 inner_comps = 2;
2845 break;
2846 default:
2847 assert(0);
2848 return;
2849 }
2850
2851 for (i = 0; i < 4; i++) {
2852 inner[i] = LLVMGetUndef(ctx->i32);
2853 outer[i] = LLVMGetUndef(ctx->i32);
2854 }
2855
2856 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
2857 /* Tess factors are in VGPRs. */
2858 for (i = 0; i < outer_comps; i++)
2859 outer[i] = out[i] = invoc0_tf_outer[i];
2860 for (i = 0; i < inner_comps; i++)
2861 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
2862 } else {
2863 /* Load tess_inner and tess_outer from LDS.
2864 * Any invocation can write them, so we can't get them from a temporary.
2865 */
2866 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
2867 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
2868
2869 lds_base = tcs_out_current_patch_data_offset;
2870 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2871 LLVMConstInt(ctx->i32,
2872 tess_inner_index * 4, 0), "");
2873 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2874 LLVMConstInt(ctx->i32,
2875 tess_outer_index * 4, 0), "");
2876
2877 for (i = 0; i < outer_comps; i++) {
2878 outer[i] = out[i] =
2879 lds_load(bld_base, ctx->ac.i32, i, lds_outer);
2880 }
2881 for (i = 0; i < inner_comps; i++) {
2882 inner[i] = out[outer_comps+i] =
2883 lds_load(bld_base, ctx->ac.i32, i, lds_inner);
2884 }
2885 }
2886
2887 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2888 /* For isolines, the hardware expects tess factors in the
2889 * reverse order from what GLSL / TGSI specify.
2890 */
2891 LLVMValueRef tmp = out[0];
2892 out[0] = out[1];
2893 out[1] = tmp;
2894 }
2895
2896 /* Convert the outputs to vectors for stores. */
2897 vec0 = lp_build_gather_values(&ctx->gallivm, out, MIN2(stride, 4));
2898 vec1 = NULL;
2899
2900 if (stride > 4)
2901 vec1 = lp_build_gather_values(&ctx->gallivm, out+4, stride - 4);
2902
2903 /* Get the buffer. */
2904 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_factor_addr_base64k);
2905
2906 /* Get the offset. */
2907 tf_base = LLVMGetParam(ctx->main_fn,
2908 ctx->param_tcs_factor_offset);
2909 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2910 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
2911
2912 lp_build_if(&inner_if_ctx, &ctx->gallivm,
2913 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2914 rel_patch_id, ctx->i32_0, ""));
2915
2916 /* Store the dynamic HS control word. */
2917 offset = 0;
2918 if (ctx->screen->info.chip_class <= VI) {
2919 ac_build_buffer_store_dword(&ctx->ac, buffer,
2920 LLVMConstInt(ctx->i32, 0x80000000, 0),
2921 1, ctx->i32_0, tf_base,
2922 offset, 1, 0, true, false);
2923 offset += 4;
2924 }
2925
2926 lp_build_endif(&inner_if_ctx);
2927
2928 /* Store the tessellation factors. */
2929 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2930 MIN2(stride, 4), byteoffset, tf_base,
2931 offset, 1, 0, true, false);
2932 offset += 16;
2933 if (vec1)
2934 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2935 stride - 4, byteoffset, tf_base,
2936 offset, 1, 0, true, false);
2937
2938 /* Store the tess factors into the offchip buffer if TES reads them. */
2939 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
2940 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
2941 LLVMValueRef tf_inner_offset;
2942 unsigned param_outer, param_inner;
2943
2944 buf = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
2945 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2946
2947 param_outer = si_shader_io_get_unique_index_patch(
2948 TGSI_SEMANTIC_TESSOUTER, 0);
2949 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2950 LLVMConstInt(ctx->i32, param_outer, 0));
2951
2952 outer_vec = lp_build_gather_values(&ctx->gallivm, outer,
2953 util_next_power_of_two(outer_comps));
2954
2955 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
2956 outer_comps, tf_outer_offset,
2957 base, 0, 1, 0, true, false);
2958 if (inner_comps) {
2959 param_inner = si_shader_io_get_unique_index_patch(
2960 TGSI_SEMANTIC_TESSINNER, 0);
2961 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2962 LLVMConstInt(ctx->i32, param_inner, 0));
2963
2964 inner_vec = inner_comps == 1 ? inner[0] :
2965 lp_build_gather_values(&ctx->gallivm, inner, inner_comps);
2966 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
2967 inner_comps, tf_inner_offset,
2968 base, 0, 1, 0, true, false);
2969 }
2970 }
2971
2972 lp_build_endif(&if_ctx);
2973 }
2974
2975 static LLVMValueRef
2976 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
2977 unsigned param, unsigned return_index)
2978 {
2979 return LLVMBuildInsertValue(ctx->ac.builder, ret,
2980 LLVMGetParam(ctx->main_fn, param),
2981 return_index, "");
2982 }
2983
2984 static LLVMValueRef
2985 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
2986 unsigned param, unsigned return_index)
2987 {
2988 LLVMBuilderRef builder = ctx->ac.builder;
2989 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
2990
2991 return LLVMBuildInsertValue(builder, ret,
2992 ac_to_float(&ctx->ac, p),
2993 return_index, "");
2994 }
2995
2996 static LLVMValueRef
2997 si_insert_input_ptr_as_2xi32(struct si_shader_context *ctx, LLVMValueRef ret,
2998 unsigned param, unsigned return_index)
2999 {
3000 LLVMBuilderRef builder = ctx->ac.builder;
3001 LLVMValueRef ptr, lo, hi;
3002
3003 ptr = LLVMGetParam(ctx->main_fn, param);
3004 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
3005 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
3006 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
3007 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
3008 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
3009 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
3010 }
3011
3012 /* This only writes the tessellation factor levels. */
3013 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
3014 {
3015 struct si_shader_context *ctx = si_shader_context(bld_base);
3016 LLVMBuilderRef builder = ctx->ac.builder;
3017 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3018
3019 si_copy_tcs_inputs(bld_base);
3020
3021 rel_patch_id = get_rel_patch_id(ctx);
3022 invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
3023 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3024
3025 if (ctx->screen->info.chip_class >= GFX9) {
3026 LLVMBasicBlockRef blocks[2] = {
3027 LLVMGetInsertBlock(builder),
3028 ctx->merged_wrap_if_state.entry_block
3029 };
3030 LLVMValueRef values[2];
3031
3032 lp_build_endif(&ctx->merged_wrap_if_state);
3033
3034 values[0] = rel_patch_id;
3035 values[1] = LLVMGetUndef(ctx->i32);
3036 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3037
3038 values[0] = tf_lds_offset;
3039 values[1] = LLVMGetUndef(ctx->i32);
3040 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3041
3042 values[0] = invocation_id;
3043 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3044 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3045 }
3046
3047 /* Return epilog parameters from this function. */
3048 LLVMValueRef ret = ctx->return_value;
3049 unsigned vgpr;
3050
3051 if (ctx->screen->info.chip_class >= GFX9) {
3052 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3053 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3054 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3055 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3056 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3057 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
3058 /* Tess offchip and tess factor offsets are at the beginning. */
3059 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3060 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3061 vgpr = 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K + 1;
3062 } else {
3063 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3064 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3065 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3066 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3067 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3068 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K);
3069 /* Tess offchip and tess factor offsets are after user SGPRs. */
3070 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3071 GFX6_TCS_NUM_USER_SGPR);
3072 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3073 GFX6_TCS_NUM_USER_SGPR + 1);
3074 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3075 }
3076
3077 /* VGPRs */
3078 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3079 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3080 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3081
3082 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3083 * the invocation_id output does not alias the param_tcs_rel_ids input,
3084 * which saves a V_MOV on gfx9.
3085 */
3086 vgpr += 2;
3087
3088 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3089 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3090
3091 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3092 vgpr++; /* skip the tess factor LDS offset */
3093 for (unsigned i = 0; i < 6; i++) {
3094 LLVMValueRef value =
3095 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3096 value = ac_to_float(&ctx->ac, value);
3097 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3098 }
3099 } else {
3100 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3101 }
3102 ctx->return_value = ret;
3103 }
3104
3105 /* Pass TCS inputs from LS to TCS on GFX9. */
3106 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3107 {
3108 LLVMValueRef ret = ctx->return_value;
3109
3110 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3111 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3112 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3113 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3114
3115 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
3116 8 + SI_SGPR_RW_BUFFERS);
3117 ret = si_insert_input_ptr_as_2xi32(ctx, ret,
3118 ctx->param_bindless_samplers_and_images,
3119 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3120
3121 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3122 8 + SI_SGPR_VS_STATE_BITS);
3123 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3124 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3125 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3126 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3127 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3128 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3129 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3130 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3131 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3132 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
3133
3134 unsigned desc_param = ctx->param_tcs_factor_addr_base64k + 2;
3135 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
3136 8 + GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS);
3137 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
3138 8 + GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES);
3139
3140 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3141 ret = si_insert_input_ret_float(ctx, ret,
3142 ctx->param_tcs_patch_id, vgpr++);
3143 ret = si_insert_input_ret_float(ctx, ret,
3144 ctx->param_tcs_rel_ids, vgpr++);
3145 ctx->return_value = ret;
3146 }
3147
3148 /* Pass GS inputs from ES to GS on GFX9. */
3149 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3150 {
3151 LLVMValueRef ret = ctx->return_value;
3152
3153 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3154 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3155 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3156
3157 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
3158 8 + SI_SGPR_RW_BUFFERS);
3159 ret = si_insert_input_ptr_as_2xi32(ctx, ret,
3160 ctx->param_bindless_samplers_and_images,
3161 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3162
3163 unsigned desc_param = ctx->param_vs_state_bits + 1;
3164 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
3165 8 + GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS);
3166 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
3167 8 + GFX9_SGPR_GS_SAMPLERS_AND_IMAGES);
3168
3169 unsigned vgpr = 8 + GFX9_GS_NUM_USER_SGPR;
3170 for (unsigned i = 0; i < 5; i++) {
3171 unsigned param = ctx->param_gs_vtx01_offset + i;
3172 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3173 }
3174 ctx->return_value = ret;
3175 }
3176
3177 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3178 unsigned max_outputs,
3179 LLVMValueRef *addrs)
3180 {
3181 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3182 struct si_shader *shader = ctx->shader;
3183 struct tgsi_shader_info *info = &shader->selector->info;
3184 unsigned i, chan;
3185 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3186 ctx->param_rel_auto_id);
3187 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3188 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3189 vertex_dw_stride, "");
3190
3191 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3192 * its inputs from it. */
3193 for (i = 0; i < info->num_outputs; i++) {
3194 unsigned name = info->output_semantic_name[i];
3195 unsigned index = info->output_semantic_index[i];
3196
3197 /* The ARB_shader_viewport_layer_array spec contains the
3198 * following issue:
3199 *
3200 * 2) What happens if gl_ViewportIndex or gl_Layer is
3201 * written in the vertex shader and a geometry shader is
3202 * present?
3203 *
3204 * RESOLVED: The value written by the last vertex processing
3205 * stage is used. If the last vertex processing stage
3206 * (vertex, tessellation evaluation or geometry) does not
3207 * statically assign to gl_ViewportIndex or gl_Layer, index
3208 * or layer zero is assumed.
3209 *
3210 * So writes to those outputs in VS-as-LS are simply ignored.
3211 */
3212 if (name == TGSI_SEMANTIC_LAYER ||
3213 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3214 continue;
3215
3216 int param = si_shader_io_get_unique_index(name, index);
3217 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3218 LLVMConstInt(ctx->i32, param * 4, 0), "");
3219
3220 for (chan = 0; chan < 4; chan++) {
3221 if (!(info->output_usagemask[i] & (1 << chan)))
3222 continue;
3223
3224 lds_store(ctx, chan, dw_addr,
3225 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3226 }
3227 }
3228
3229 if (ctx->screen->info.chip_class >= GFX9)
3230 si_set_ls_return_value_for_tcs(ctx);
3231 }
3232
3233 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3234 unsigned max_outputs,
3235 LLVMValueRef *addrs)
3236 {
3237 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3238 struct si_shader *es = ctx->shader;
3239 struct tgsi_shader_info *info = &es->selector->info;
3240 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3241 ctx->param_es2gs_offset);
3242 LLVMValueRef lds_base = NULL;
3243 unsigned chan;
3244 int i;
3245
3246 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3247 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3248 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3249 LLVMValueRef wave_idx = unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3250 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3251 LLVMBuildMul(ctx->ac.builder, wave_idx,
3252 LLVMConstInt(ctx->i32, 64, false), ""), "");
3253 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3254 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3255 }
3256
3257 for (i = 0; i < info->num_outputs; i++) {
3258 int param;
3259
3260 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3261 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3262 continue;
3263
3264 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3265 info->output_semantic_index[i]);
3266
3267 for (chan = 0; chan < 4; chan++) {
3268 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3269 out_val = ac_to_integer(&ctx->ac, out_val);
3270
3271 /* GFX9 has the ESGS ring in LDS. */
3272 if (ctx->screen->info.chip_class >= GFX9) {
3273 lds_store(ctx, param * 4 + chan, lds_base, out_val);
3274 continue;
3275 }
3276
3277 ac_build_buffer_store_dword(&ctx->ac,
3278 ctx->esgs_ring,
3279 out_val, 1, NULL, soffset,
3280 (4 * param + chan) * 4,
3281 1, 1, true, true);
3282 }
3283 }
3284
3285 if (ctx->screen->info.chip_class >= GFX9)
3286 si_set_es_return_value_for_gs(ctx);
3287 }
3288
3289 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3290 {
3291 if (ctx->screen->info.chip_class >= GFX9)
3292 return unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3293 else
3294 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3295 }
3296
3297 static void emit_gs_epilogue(struct si_shader_context *ctx)
3298 {
3299 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3300 si_get_gs_wave_id(ctx));
3301
3302 if (ctx->screen->info.chip_class >= GFX9)
3303 lp_build_endif(&ctx->merged_wrap_if_state);
3304 }
3305
3306 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3307 unsigned max_outputs,
3308 LLVMValueRef *addrs)
3309 {
3310 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3311 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3312
3313 assert(info->num_outputs <= max_outputs);
3314
3315 emit_gs_epilogue(ctx);
3316 }
3317
3318 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3319 {
3320 struct si_shader_context *ctx = si_shader_context(bld_base);
3321 emit_gs_epilogue(ctx);
3322 }
3323
3324 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3325 unsigned max_outputs,
3326 LLVMValueRef *addrs)
3327 {
3328 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3329 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3330 struct si_shader_output_values *outputs = NULL;
3331 int i,j;
3332
3333 assert(!ctx->shader->is_gs_copy_shader);
3334 assert(info->num_outputs <= max_outputs);
3335
3336 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3337
3338 /* Vertex color clamping.
3339 *
3340 * This uses a state constant loaded in a user data SGPR and
3341 * an IF statement is added that clamps all colors if the constant
3342 * is true.
3343 */
3344 if (ctx->type == PIPE_SHADER_VERTEX) {
3345 struct lp_build_if_state if_ctx;
3346 LLVMValueRef cond = NULL;
3347 LLVMValueRef addr, val;
3348
3349 for (i = 0; i < info->num_outputs; i++) {
3350 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3351 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3352 continue;
3353
3354 /* We've found a color. */
3355 if (!cond) {
3356 /* The state is in the first bit of the user SGPR. */
3357 cond = LLVMGetParam(ctx->main_fn,
3358 ctx->param_vs_state_bits);
3359 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3360 ctx->i1, "");
3361 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3362 }
3363
3364 for (j = 0; j < 4; j++) {
3365 addr = addrs[4 * i + j];
3366 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3367 val = ac_build_clamp(&ctx->ac, val);
3368 LLVMBuildStore(ctx->ac.builder, val, addr);
3369 }
3370 }
3371
3372 if (cond)
3373 lp_build_endif(&if_ctx);
3374 }
3375
3376 for (i = 0; i < info->num_outputs; i++) {
3377 outputs[i].semantic_name = info->output_semantic_name[i];
3378 outputs[i].semantic_index = info->output_semantic_index[i];
3379
3380 for (j = 0; j < 4; j++) {
3381 outputs[i].values[j] =
3382 LLVMBuildLoad(ctx->ac.builder,
3383 addrs[4 * i + j],
3384 "");
3385 outputs[i].vertex_stream[j] =
3386 (info->output_streams[i] >> (2 * j)) & 3;
3387 }
3388 }
3389
3390 if (ctx->shader->selector->so.num_outputs)
3391 si_llvm_emit_streamout(ctx, outputs, i, 0);
3392
3393 /* Export PrimitiveID. */
3394 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3395 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3396 outputs[i].semantic_index = 0;
3397 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3398 for (j = 1; j < 4; j++)
3399 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3400
3401 memset(outputs[i].vertex_stream, 0,
3402 sizeof(outputs[i].vertex_stream));
3403 i++;
3404 }
3405
3406 si_llvm_export_vs(ctx, outputs, i);
3407 FREE(outputs);
3408 }
3409
3410 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3411 {
3412 struct si_shader_context *ctx = si_shader_context(bld_base);
3413
3414 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3415 &ctx->outputs[0][0]);
3416 }
3417
3418 struct si_ps_exports {
3419 unsigned num;
3420 struct ac_export_args args[10];
3421 };
3422
3423 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3424 LLVMValueRef depth, LLVMValueRef stencil,
3425 LLVMValueRef samplemask, struct si_ps_exports *exp)
3426 {
3427 struct si_shader_context *ctx = si_shader_context(bld_base);
3428 struct ac_export_args args;
3429
3430 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3431
3432 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3433 }
3434
3435 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3436 LLVMValueRef *color, unsigned index,
3437 unsigned samplemask_param,
3438 bool is_last, struct si_ps_exports *exp)
3439 {
3440 struct si_shader_context *ctx = si_shader_context(bld_base);
3441 int i;
3442
3443 /* Clamp color */
3444 if (ctx->shader->key.part.ps.epilog.clamp_color)
3445 for (i = 0; i < 4; i++)
3446 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3447
3448 /* Alpha to one */
3449 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3450 color[3] = ctx->ac.f32_1;
3451
3452 /* Alpha test */
3453 if (index == 0 &&
3454 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3455 si_alpha_test(bld_base, color[3]);
3456
3457 /* Line & polygon smoothing */
3458 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3459 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3460 samplemask_param);
3461
3462 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3463 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3464 struct ac_export_args args[8];
3465 int c, last = -1;
3466
3467 /* Get the export arguments, also find out what the last one is. */
3468 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3469 si_llvm_init_export_args(ctx, color,
3470 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3471 if (args[c].enabled_channels)
3472 last = c;
3473 }
3474
3475 /* Emit all exports. */
3476 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3477 if (is_last && last == c) {
3478 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3479 args[c].done = 1; /* DONE bit */
3480 } else if (!args[c].enabled_channels)
3481 continue; /* unnecessary NULL export */
3482
3483 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3484 }
3485 } else {
3486 struct ac_export_args args;
3487
3488 /* Export */
3489 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3490 &args);
3491 if (is_last) {
3492 args.valid_mask = 1; /* whether the EXEC mask is valid */
3493 args.done = 1; /* DONE bit */
3494 } else if (!args.enabled_channels)
3495 return; /* unnecessary NULL export */
3496
3497 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3498 }
3499 }
3500
3501 static void si_emit_ps_exports(struct si_shader_context *ctx,
3502 struct si_ps_exports *exp)
3503 {
3504 for (unsigned i = 0; i < exp->num; i++)
3505 ac_build_export(&ctx->ac, &exp->args[i]);
3506 }
3507
3508 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3509 {
3510 struct si_shader_context *ctx = si_shader_context(bld_base);
3511 struct lp_build_context *base = &bld_base->base;
3512 struct ac_export_args args;
3513
3514 args.enabled_channels = 0x0; /* enabled channels */
3515 args.valid_mask = 1; /* whether the EXEC mask is valid */
3516 args.done = 1; /* DONE bit */
3517 args.target = V_008DFC_SQ_EXP_NULL;
3518 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
3519 args.out[0] = base->undef; /* R */
3520 args.out[1] = base->undef; /* G */
3521 args.out[2] = base->undef; /* B */
3522 args.out[3] = base->undef; /* A */
3523
3524 ac_build_export(&ctx->ac, &args);
3525 }
3526
3527 /**
3528 * Return PS outputs in this order:
3529 *
3530 * v[0:3] = color0.xyzw
3531 * v[4:7] = color1.xyzw
3532 * ...
3533 * vN+0 = Depth
3534 * vN+1 = Stencil
3535 * vN+2 = SampleMask
3536 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3537 *
3538 * The alpha-ref SGPR is returned via its original location.
3539 */
3540 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3541 unsigned max_outputs,
3542 LLVMValueRef *addrs)
3543 {
3544 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3545 struct si_shader *shader = ctx->shader;
3546 struct tgsi_shader_info *info = &shader->selector->info;
3547 LLVMBuilderRef builder = ctx->ac.builder;
3548 unsigned i, j, first_vgpr, vgpr;
3549
3550 LLVMValueRef color[8][4] = {};
3551 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3552 LLVMValueRef ret;
3553
3554 if (ctx->postponed_kill)
3555 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3556
3557 /* Read the output values. */
3558 for (i = 0; i < info->num_outputs; i++) {
3559 unsigned semantic_name = info->output_semantic_name[i];
3560 unsigned semantic_index = info->output_semantic_index[i];
3561
3562 switch (semantic_name) {
3563 case TGSI_SEMANTIC_COLOR:
3564 assert(semantic_index < 8);
3565 for (j = 0; j < 4; j++) {
3566 LLVMValueRef ptr = addrs[4 * i + j];
3567 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3568 color[semantic_index][j] = result;
3569 }
3570 break;
3571 case TGSI_SEMANTIC_POSITION:
3572 depth = LLVMBuildLoad(builder,
3573 addrs[4 * i + 2], "");
3574 break;
3575 case TGSI_SEMANTIC_STENCIL:
3576 stencil = LLVMBuildLoad(builder,
3577 addrs[4 * i + 1], "");
3578 break;
3579 case TGSI_SEMANTIC_SAMPLEMASK:
3580 samplemask = LLVMBuildLoad(builder,
3581 addrs[4 * i + 0], "");
3582 break;
3583 default:
3584 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3585 semantic_name);
3586 }
3587 }
3588
3589 /* Fill the return structure. */
3590 ret = ctx->return_value;
3591
3592 /* Set SGPRs. */
3593 ret = LLVMBuildInsertValue(builder, ret,
3594 ac_to_integer(&ctx->ac,
3595 LLVMGetParam(ctx->main_fn,
3596 SI_PARAM_ALPHA_REF)),
3597 SI_SGPR_ALPHA_REF, "");
3598
3599 /* Set VGPRs */
3600 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3601 for (i = 0; i < ARRAY_SIZE(color); i++) {
3602 if (!color[i][0])
3603 continue;
3604
3605 for (j = 0; j < 4; j++)
3606 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3607 }
3608 if (depth)
3609 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3610 if (stencil)
3611 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3612 if (samplemask)
3613 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3614
3615 /* Add the input sample mask for smoothing at the end. */
3616 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3617 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3618 ret = LLVMBuildInsertValue(builder, ret,
3619 LLVMGetParam(ctx->main_fn,
3620 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3621
3622 ctx->return_value = ret;
3623 }
3624
3625 static void membar_emit(
3626 const struct lp_build_tgsi_action *action,
3627 struct lp_build_tgsi_context *bld_base,
3628 struct lp_build_emit_data *emit_data)
3629 {
3630 struct si_shader_context *ctx = si_shader_context(bld_base);
3631 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3632 unsigned flags = LLVMConstIntGetZExtValue(src0);
3633 unsigned waitcnt = NOOP_WAITCNT;
3634
3635 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3636 waitcnt &= VM_CNT & LGKM_CNT;
3637
3638 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3639 TGSI_MEMBAR_SHADER_BUFFER |
3640 TGSI_MEMBAR_SHADER_IMAGE))
3641 waitcnt &= VM_CNT;
3642
3643 if (flags & TGSI_MEMBAR_SHARED)
3644 waitcnt &= LGKM_CNT;
3645
3646 if (waitcnt != NOOP_WAITCNT)
3647 ac_build_waitcnt(&ctx->ac, waitcnt);
3648 }
3649
3650 static void clock_emit(
3651 const struct lp_build_tgsi_action *action,
3652 struct lp_build_tgsi_context *bld_base,
3653 struct lp_build_emit_data *emit_data)
3654 {
3655 struct si_shader_context *ctx = si_shader_context(bld_base);
3656 LLVMValueRef tmp;
3657
3658 tmp = lp_build_intrinsic(ctx->ac.builder, "llvm.readcyclecounter",
3659 ctx->i64, NULL, 0, 0);
3660 tmp = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->v2i32, "");
3661
3662 emit_data->output[0] =
3663 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3664 emit_data->output[1] =
3665 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3666 }
3667
3668 LLVMTypeRef si_const_array(LLVMTypeRef elem_type, int num_elements)
3669 {
3670 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3671 CONST_ADDR_SPACE);
3672 }
3673
3674 static void si_llvm_emit_ddxy(
3675 const struct lp_build_tgsi_action *action,
3676 struct lp_build_tgsi_context *bld_base,
3677 struct lp_build_emit_data *emit_data)
3678 {
3679 struct si_shader_context *ctx = si_shader_context(bld_base);
3680 unsigned opcode = emit_data->info->opcode;
3681 LLVMValueRef val;
3682 int idx;
3683 unsigned mask;
3684
3685 if (opcode == TGSI_OPCODE_DDX_FINE)
3686 mask = AC_TID_MASK_LEFT;
3687 else if (opcode == TGSI_OPCODE_DDY_FINE)
3688 mask = AC_TID_MASK_TOP;
3689 else
3690 mask = AC_TID_MASK_TOP_LEFT;
3691
3692 /* for DDX we want to next X pixel, DDY next Y pixel. */
3693 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3694
3695 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3696 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3697 emit_data->output[emit_data->chan] = val;
3698 }
3699
3700 /*
3701 * this takes an I,J coordinate pair,
3702 * and works out the X and Y derivatives.
3703 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3704 */
3705 static LLVMValueRef si_llvm_emit_ddxy_interp(
3706 struct lp_build_tgsi_context *bld_base,
3707 LLVMValueRef interp_ij)
3708 {
3709 struct si_shader_context *ctx = si_shader_context(bld_base);
3710 LLVMValueRef result[4], a;
3711 unsigned i;
3712
3713 for (i = 0; i < 2; i++) {
3714 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
3715 LLVMConstInt(ctx->i32, i, 0), "");
3716 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
3717 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
3718 }
3719
3720 return lp_build_gather_values(&ctx->gallivm, result, 4);
3721 }
3722
3723 static void interp_fetch_args(
3724 struct lp_build_tgsi_context *bld_base,
3725 struct lp_build_emit_data *emit_data)
3726 {
3727 struct si_shader_context *ctx = si_shader_context(bld_base);
3728 const struct tgsi_full_instruction *inst = emit_data->inst;
3729
3730 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3731 /* offset is in second src, first two channels */
3732 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3733 emit_data->inst, 1,
3734 TGSI_CHAN_X);
3735 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3736 emit_data->inst, 1,
3737 TGSI_CHAN_Y);
3738 emit_data->arg_count = 2;
3739 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3740 LLVMValueRef sample_position;
3741 LLVMValueRef sample_id;
3742 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3743
3744 /* fetch sample ID, then fetch its sample position,
3745 * and place into first two channels.
3746 */
3747 sample_id = lp_build_emit_fetch(bld_base,
3748 emit_data->inst, 1, TGSI_CHAN_X);
3749 sample_id = ac_to_integer(&ctx->ac, sample_id);
3750
3751 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
3752 * Language 4.50 spec says about interpolateAtSample:
3753 *
3754 * "Returns the value of the input interpolant variable at
3755 * the location of sample number sample. If multisample
3756 * buffers are not available, the input variable will be
3757 * evaluated at the center of the pixel. If sample sample
3758 * does not exist, the position used to interpolate the
3759 * input variable is undefined."
3760 *
3761 * This means that sample_id values outside of the valid are
3762 * in fact valid input, and the usual mechanism for loading the
3763 * sample position doesn't work.
3764 */
3765 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
3766 LLVMValueRef center[4] = {
3767 LLVMConstReal(ctx->f32, 0.5),
3768 LLVMConstReal(ctx->f32, 0.5),
3769 ctx->ac.f32_0,
3770 ctx->ac.f32_0,
3771 };
3772
3773 sample_position = lp_build_gather_values(&ctx->gallivm, center, 4);
3774 } else {
3775 sample_position = load_sample_position(ctx, sample_id);
3776 }
3777
3778 emit_data->args[0] = LLVMBuildExtractElement(ctx->ac.builder,
3779 sample_position,
3780 ctx->i32_0, "");
3781
3782 emit_data->args[0] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[0], halfval, "");
3783 emit_data->args[1] = LLVMBuildExtractElement(ctx->ac.builder,
3784 sample_position,
3785 ctx->i32_1, "");
3786 emit_data->args[1] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[1], halfval, "");
3787 emit_data->arg_count = 2;
3788 }
3789 }
3790
3791 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3792 struct lp_build_tgsi_context *bld_base,
3793 struct lp_build_emit_data *emit_data)
3794 {
3795 struct si_shader_context *ctx = si_shader_context(bld_base);
3796 struct si_shader *shader = ctx->shader;
3797 const struct tgsi_shader_info *info = &shader->selector->info;
3798 LLVMValueRef interp_param;
3799 const struct tgsi_full_instruction *inst = emit_data->inst;
3800 const struct tgsi_full_src_register *input = &inst->Src[0];
3801 int input_base, input_array_size;
3802 int chan;
3803 int i;
3804 LLVMValueRef prim_mask = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
3805 LLVMValueRef array_idx;
3806 int interp_param_idx;
3807 unsigned interp;
3808 unsigned location;
3809
3810 assert(input->Register.File == TGSI_FILE_INPUT);
3811
3812 if (input->Register.Indirect) {
3813 unsigned array_id = input->Indirect.ArrayID;
3814
3815 if (array_id) {
3816 input_base = info->input_array_first[array_id];
3817 input_array_size = info->input_array_last[array_id] - input_base + 1;
3818 } else {
3819 input_base = inst->Src[0].Register.Index;
3820 input_array_size = info->num_inputs - input_base;
3821 }
3822
3823 array_idx = si_get_indirect_index(ctx, &input->Indirect,
3824 1, input->Register.Index - input_base);
3825 } else {
3826 input_base = inst->Src[0].Register.Index;
3827 input_array_size = 1;
3828 array_idx = ctx->i32_0;
3829 }
3830
3831 interp = shader->selector->info.input_interpolate[input_base];
3832
3833 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3834 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3835 location = TGSI_INTERPOLATE_LOC_CENTER;
3836 else
3837 location = TGSI_INTERPOLATE_LOC_CENTROID;
3838
3839 interp_param_idx = lookup_interp_param_index(interp, location);
3840 if (interp_param_idx == -1)
3841 return;
3842 else if (interp_param_idx)
3843 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
3844 else
3845 interp_param = NULL;
3846
3847 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3848 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3849 LLVMValueRef ij_out[2];
3850 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3851
3852 /*
3853 * take the I then J parameters, and the DDX/Y for it, and
3854 * calculate the IJ inputs for the interpolator.
3855 * temp1 = ddx * offset/sample.x + I;
3856 * interp_param.I = ddy * offset/sample.y + temp1;
3857 * temp1 = ddx * offset/sample.x + J;
3858 * interp_param.J = ddy * offset/sample.y + temp1;
3859 */
3860 for (i = 0; i < 2; i++) {
3861 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
3862 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
3863 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
3864 ddxy_out, ix_ll, "");
3865 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
3866 ddxy_out, iy_ll, "");
3867 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
3868 interp_param, ix_ll, "");
3869 LLVMValueRef temp1, temp2;
3870
3871 interp_el = ac_to_float(&ctx->ac, interp_el);
3872
3873 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, emit_data->args[0], "");
3874
3875 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
3876
3877 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, emit_data->args[1], "");
3878
3879 ij_out[i] = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
3880 }
3881 interp_param = lp_build_gather_values(&ctx->gallivm, ij_out, 2);
3882 }
3883
3884 if (interp_param)
3885 interp_param = ac_to_float(&ctx->ac, interp_param);
3886
3887 for (chan = 0; chan < 4; chan++) {
3888 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
3889 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3890
3891 for (unsigned idx = 0; idx < input_array_size; ++idx) {
3892 LLVMValueRef v, i = NULL, j = NULL;
3893
3894 if (interp_param) {
3895 i = LLVMBuildExtractElement(
3896 ctx->ac.builder, interp_param, ctx->i32_0, "");
3897 j = LLVMBuildExtractElement(
3898 ctx->ac.builder, interp_param, ctx->i32_1, "");
3899 }
3900 v = si_build_fs_interp(ctx, input_base + idx, schan,
3901 prim_mask, i, j);
3902
3903 gather = LLVMBuildInsertElement(ctx->ac.builder,
3904 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
3905 }
3906
3907 emit_data->output[chan] = LLVMBuildExtractElement(
3908 ctx->ac.builder, gather, array_idx, "");
3909 }
3910 }
3911
3912 static void vote_all_emit(
3913 const struct lp_build_tgsi_action *action,
3914 struct lp_build_tgsi_context *bld_base,
3915 struct lp_build_emit_data *emit_data)
3916 {
3917 struct si_shader_context *ctx = si_shader_context(bld_base);
3918
3919 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
3920 emit_data->output[emit_data->chan] =
3921 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
3922 }
3923
3924 static void vote_any_emit(
3925 const struct lp_build_tgsi_action *action,
3926 struct lp_build_tgsi_context *bld_base,
3927 struct lp_build_emit_data *emit_data)
3928 {
3929 struct si_shader_context *ctx = si_shader_context(bld_base);
3930
3931 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
3932 emit_data->output[emit_data->chan] =
3933 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
3934 }
3935
3936 static void vote_eq_emit(
3937 const struct lp_build_tgsi_action *action,
3938 struct lp_build_tgsi_context *bld_base,
3939 struct lp_build_emit_data *emit_data)
3940 {
3941 struct si_shader_context *ctx = si_shader_context(bld_base);
3942
3943 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
3944 emit_data->output[emit_data->chan] =
3945 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
3946 }
3947
3948 static void ballot_emit(
3949 const struct lp_build_tgsi_action *action,
3950 struct lp_build_tgsi_context *bld_base,
3951 struct lp_build_emit_data *emit_data)
3952 {
3953 struct si_shader_context *ctx = si_shader_context(bld_base);
3954 LLVMBuilderRef builder = ctx->ac.builder;
3955 LLVMValueRef tmp;
3956
3957 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
3958 tmp = ac_build_ballot(&ctx->ac, tmp);
3959 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
3960
3961 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
3962 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
3963 }
3964
3965 static void read_invoc_fetch_args(
3966 struct lp_build_tgsi_context *bld_base,
3967 struct lp_build_emit_data *emit_data)
3968 {
3969 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
3970 0, emit_data->src_chan);
3971
3972 /* Always read the source invocation (= lane) from the X channel. */
3973 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
3974 1, TGSI_CHAN_X);
3975 emit_data->arg_count = 2;
3976 }
3977
3978 static void read_lane_emit(
3979 const struct lp_build_tgsi_action *action,
3980 struct lp_build_tgsi_context *bld_base,
3981 struct lp_build_emit_data *emit_data)
3982 {
3983 struct si_shader_context *ctx = si_shader_context(bld_base);
3984
3985 /* We currently have no other way to prevent LLVM from lifting the icmp
3986 * calls to a dominating basic block.
3987 */
3988 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
3989
3990 for (unsigned i = 0; i < emit_data->arg_count; ++i)
3991 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
3992
3993 emit_data->output[emit_data->chan] =
3994 ac_build_intrinsic(&ctx->ac, action->intr_name,
3995 ctx->i32, emit_data->args, emit_data->arg_count,
3996 AC_FUNC_ATTR_READNONE |
3997 AC_FUNC_ATTR_CONVERGENT);
3998 }
3999
4000 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4001 struct lp_build_emit_data *emit_data)
4002 {
4003 struct si_shader_context *ctx = si_shader_context(bld_base);
4004 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4005 LLVMValueRef imm;
4006 unsigned stream;
4007
4008 assert(src0.File == TGSI_FILE_IMMEDIATE);
4009
4010 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4011 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4012 return stream;
4013 }
4014
4015 /* Emit one vertex from the geometry shader */
4016 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4017 unsigned stream,
4018 LLVMValueRef *addrs)
4019 {
4020 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4021 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4022 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
4023 struct si_shader *shader = ctx->shader;
4024 struct lp_build_if_state if_state;
4025 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4026 ctx->param_gs2vs_offset);
4027 LLVMValueRef gs_next_vertex;
4028 LLVMValueRef can_emit;
4029 unsigned chan, offset;
4030 int i;
4031
4032 /* Write vertex attribute values to GSVS ring */
4033 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4034 ctx->gs_next_vertex[stream],
4035 "");
4036
4037 /* If this thread has already emitted the declared maximum number of
4038 * vertices, skip the write: excessive vertex emissions are not
4039 * supposed to have any effect.
4040 *
4041 * If the shader has no writes to memory, kill it instead. This skips
4042 * further memory loads and may allow LLVM to skip to the end
4043 * altogether.
4044 */
4045 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4046 LLVMConstInt(ctx->i32,
4047 shader->selector->gs_max_out_vertices, 0), "");
4048
4049 bool use_kill = !info->writes_memory;
4050 if (use_kill) {
4051 ac_build_kill_if_false(&ctx->ac, can_emit);
4052 } else {
4053 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4054 }
4055
4056 offset = 0;
4057 for (i = 0; i < info->num_outputs; i++) {
4058 for (chan = 0; chan < 4; chan++) {
4059 if (!(info->output_usagemask[i] & (1 << chan)) ||
4060 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4061 continue;
4062
4063 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4064 LLVMValueRef voffset =
4065 LLVMConstInt(ctx->i32, offset *
4066 shader->selector->gs_max_out_vertices, 0);
4067 offset++;
4068
4069 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4070 voffset = lp_build_mul_imm(uint, voffset, 4);
4071
4072 out_val = ac_to_integer(&ctx->ac, out_val);
4073
4074 ac_build_buffer_store_dword(&ctx->ac,
4075 ctx->gsvs_ring[stream],
4076 out_val, 1,
4077 voffset, soffset, 0,
4078 1, 1, true, true);
4079 }
4080 }
4081
4082 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4083 ctx->i32_1);
4084
4085 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4086
4087 /* Signal vertex emission */
4088 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4089 si_get_gs_wave_id(ctx));
4090 if (!use_kill)
4091 lp_build_endif(&if_state);
4092 }
4093
4094 /* Emit one vertex from the geometry shader */
4095 static void si_tgsi_emit_vertex(
4096 const struct lp_build_tgsi_action *action,
4097 struct lp_build_tgsi_context *bld_base,
4098 struct lp_build_emit_data *emit_data)
4099 {
4100 struct si_shader_context *ctx = si_shader_context(bld_base);
4101 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4102
4103 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4104 }
4105
4106 /* Cut one primitive from the geometry shader */
4107 static void si_llvm_emit_primitive(
4108 const struct lp_build_tgsi_action *action,
4109 struct lp_build_tgsi_context *bld_base,
4110 struct lp_build_emit_data *emit_data)
4111 {
4112 struct si_shader_context *ctx = si_shader_context(bld_base);
4113 unsigned stream;
4114
4115 /* Signal primitive cut */
4116 stream = si_llvm_get_stream(bld_base, emit_data);
4117 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4118 si_get_gs_wave_id(ctx));
4119 }
4120
4121 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4122 struct lp_build_tgsi_context *bld_base,
4123 struct lp_build_emit_data *emit_data)
4124 {
4125 struct si_shader_context *ctx = si_shader_context(bld_base);
4126
4127 /* SI only (thanks to a hw bug workaround):
4128 * The real barrier instruction isn’t needed, because an entire patch
4129 * always fits into a single wave.
4130 */
4131 if (ctx->screen->info.chip_class == SI &&
4132 ctx->type == PIPE_SHADER_TESS_CTRL) {
4133 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
4134 return;
4135 }
4136
4137 lp_build_intrinsic(ctx->ac.builder,
4138 "llvm.amdgcn.s.barrier",
4139 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
4140 }
4141
4142 static const struct lp_build_tgsi_action interp_action = {
4143 .fetch_args = interp_fetch_args,
4144 .emit = build_interp_intrinsic,
4145 };
4146
4147 static void si_create_function(struct si_shader_context *ctx,
4148 const char *name,
4149 LLVMTypeRef *returns, unsigned num_returns,
4150 struct si_function_info *fninfo,
4151 unsigned max_workgroup_size)
4152 {
4153 int i;
4154
4155 si_llvm_create_func(ctx, name, returns, num_returns,
4156 fninfo->types, fninfo->num_params);
4157 ctx->return_value = LLVMGetUndef(ctx->return_type);
4158
4159 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4160 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4161
4162 /* The combination of:
4163 * - ByVal
4164 * - dereferenceable
4165 * - invariant.load
4166 * allows the optimization passes to move loads and reduces
4167 * SGPR spilling significantly.
4168 */
4169 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4170 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
4171 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
4172 ac_add_attr_dereferenceable(P, UINT64_MAX);
4173 } else
4174 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
4175 }
4176
4177 for (i = 0; i < fninfo->num_params; ++i) {
4178 if (fninfo->assign[i])
4179 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4180 }
4181
4182 if (max_workgroup_size) {
4183 si_llvm_add_attribute(ctx->main_fn, "amdgpu-max-work-group-size",
4184 max_workgroup_size);
4185 }
4186 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4187 "no-signed-zeros-fp-math",
4188 "true");
4189
4190 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4191 /* These were copied from some LLVM test. */
4192 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4193 "less-precise-fpmad",
4194 "true");
4195 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4196 "no-infs-fp-math",
4197 "true");
4198 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4199 "no-nans-fp-math",
4200 "true");
4201 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4202 "unsafe-fp-math",
4203 "true");
4204 }
4205 }
4206
4207 static void declare_streamout_params(struct si_shader_context *ctx,
4208 struct pipe_stream_output_info *so,
4209 struct si_function_info *fninfo)
4210 {
4211 int i;
4212
4213 /* Streamout SGPRs. */
4214 if (so->num_outputs) {
4215 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4216 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4217 else
4218 ctx->param_streamout_config = fninfo->num_params - 1;
4219
4220 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4221 }
4222 /* A streamout buffer offset is loaded if the stride is non-zero. */
4223 for (i = 0; i < 4; i++) {
4224 if (!so->stride[i])
4225 continue;
4226
4227 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4228 }
4229 }
4230
4231 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4232 {
4233 switch (shader->selector->type) {
4234 case PIPE_SHADER_TESS_CTRL:
4235 /* Return this so that LLVM doesn't remove s_barrier
4236 * instructions on chips where we use s_barrier. */
4237 return shader->selector->screen->info.chip_class >= CIK ? 128 : 64;
4238
4239 case PIPE_SHADER_GEOMETRY:
4240 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4241
4242 case PIPE_SHADER_COMPUTE:
4243 break; /* see below */
4244
4245 default:
4246 return 0;
4247 }
4248
4249 const unsigned *properties = shader->selector->info.properties;
4250 unsigned max_work_group_size =
4251 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4252 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4253 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4254
4255 if (!max_work_group_size) {
4256 /* This is a variable group size compute shader,
4257 * compile it for the maximum possible group size.
4258 */
4259 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4260 }
4261 return max_work_group_size;
4262 }
4263
4264 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4265 struct si_function_info *fninfo,
4266 bool assign_params)
4267 {
4268 LLVMTypeRef const_shader_buf_type;
4269
4270 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4271 ctx->shader->selector->info.shader_buffers_declared == 0)
4272 const_shader_buf_type = ctx->f32;
4273 else
4274 const_shader_buf_type = ctx->v4i32;
4275
4276 unsigned const_and_shader_buffers =
4277 add_arg(fninfo, ARG_SGPR,
4278 si_const_array(const_shader_buf_type, 0));
4279
4280 unsigned samplers_and_images =
4281 add_arg(fninfo, ARG_SGPR,
4282 si_const_array(ctx->v8i32,
4283 SI_NUM_IMAGES + SI_NUM_SAMPLERS * 2));
4284
4285 if (assign_params) {
4286 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4287 ctx->param_samplers_and_images = samplers_and_images;
4288 }
4289 }
4290
4291 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4292 struct si_function_info *fninfo)
4293 {
4294 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4295 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS));
4296 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4297 si_const_array(ctx->v8i32, 0));
4298 }
4299
4300 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4301 struct si_function_info *fninfo)
4302 {
4303 ctx->param_vertex_buffers = add_arg(fninfo, ARG_SGPR,
4304 si_const_array(ctx->v4i32, SI_NUM_VERTEX_BUFFERS));
4305 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4306 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4307 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4308 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4309 }
4310
4311 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4312 struct si_function_info *fninfo,
4313 unsigned *num_prolog_vgprs)
4314 {
4315 struct si_shader *shader = ctx->shader;
4316
4317 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4318 if (shader->key.as_ls) {
4319 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4320 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4321 } else {
4322 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4323 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4324 }
4325 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4326
4327 if (!shader->is_gs_copy_shader) {
4328 /* Vertex load indices. */
4329 ctx->param_vertex_index0 = fninfo->num_params;
4330 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4331 add_arg(fninfo, ARG_VGPR, ctx->i32);
4332 *num_prolog_vgprs += shader->selector->info.num_inputs;
4333 }
4334 }
4335
4336 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4337 struct si_function_info *fninfo)
4338 {
4339 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4340 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4341 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4342 ctx->param_tes_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4343 }
4344
4345 enum {
4346 /* Convenient merged shader definitions. */
4347 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4348 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4349 };
4350
4351 static void create_function(struct si_shader_context *ctx)
4352 {
4353 struct si_shader *shader = ctx->shader;
4354 struct si_function_info fninfo;
4355 LLVMTypeRef returns[16+32*4];
4356 unsigned i, num_return_sgprs;
4357 unsigned num_returns = 0;
4358 unsigned num_prolog_vgprs = 0;
4359 unsigned type = ctx->type;
4360 unsigned vs_blit_property =
4361 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4362
4363 si_init_function_info(&fninfo);
4364
4365 /* Set MERGED shaders. */
4366 if (ctx->screen->info.chip_class >= GFX9) {
4367 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4368 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4369 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4370 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4371 }
4372
4373 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4374
4375 switch (type) {
4376 case PIPE_SHADER_VERTEX:
4377 declare_global_desc_pointers(ctx, &fninfo);
4378
4379 if (vs_blit_property) {
4380 ctx->param_vs_blit_inputs = fninfo.num_params;
4381 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4382 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4383 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* depth */
4384
4385 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4386 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color0 */
4387 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color1 */
4388 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color2 */
4389 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color3 */
4390 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4391 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4392 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4393 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4394 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4395 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4396 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4397 }
4398
4399 /* VGPRs */
4400 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4401 break;
4402 }
4403
4404 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4405 declare_vs_specific_input_sgprs(ctx, &fninfo);
4406
4407 if (shader->key.as_es) {
4408 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4409 } else if (shader->key.as_ls) {
4410 /* no extra parameters */
4411 } else {
4412 if (shader->is_gs_copy_shader) {
4413 fninfo.num_params = ctx->param_rw_buffers + 1;
4414 fninfo.num_sgpr_params = fninfo.num_params;
4415 }
4416
4417 /* The locations of the other parameters are assigned dynamically. */
4418 declare_streamout_params(ctx, &shader->selector->so,
4419 &fninfo);
4420 }
4421
4422 /* VGPRs */
4423 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4424 break;
4425
4426 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4427 declare_global_desc_pointers(ctx, &fninfo);
4428 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4429 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4430 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4431 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4432 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4433 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4434 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4435 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4436 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4437
4438 /* VGPRs */
4439 ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4440 ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4441
4442 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4443 * placed after the user SGPRs.
4444 */
4445 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4446 returns[num_returns++] = ctx->i32; /* SGPRs */
4447 for (i = 0; i < 11; i++)
4448 returns[num_returns++] = ctx->f32; /* VGPRs */
4449 break;
4450
4451 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4452 /* Merged stages have 8 system SGPRs at the beginning. */
4453 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_LO_HS */
4454 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_HI_HS */
4455 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4456 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4457 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4458 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4459 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4460 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4461
4462 declare_global_desc_pointers(ctx, &fninfo);
4463 declare_per_stage_desc_pointers(ctx, &fninfo,
4464 ctx->type == PIPE_SHADER_VERTEX);
4465 declare_vs_specific_input_sgprs(ctx, &fninfo);
4466
4467 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4468 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4469 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4470 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4471 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4472 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4473
4474 declare_per_stage_desc_pointers(ctx, &fninfo,
4475 ctx->type == PIPE_SHADER_TESS_CTRL);
4476
4477 /* VGPRs (first TCS, then VS) */
4478 ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4479 ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4480
4481 if (ctx->type == PIPE_SHADER_VERTEX) {
4482 declare_vs_input_vgprs(ctx, &fninfo,
4483 &num_prolog_vgprs);
4484
4485 /* LS return values are inputs to the TCS main shader part. */
4486 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4487 returns[num_returns++] = ctx->i32; /* SGPRs */
4488 for (i = 0; i < 2; i++)
4489 returns[num_returns++] = ctx->f32; /* VGPRs */
4490 } else {
4491 /* TCS return values are inputs to the TCS epilog.
4492 *
4493 * param_tcs_offchip_offset, param_tcs_factor_offset,
4494 * param_tcs_offchip_layout, and param_rw_buffers
4495 * should be passed to the epilog.
4496 */
4497 for (i = 0; i <= 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K; i++)
4498 returns[num_returns++] = ctx->i32; /* SGPRs */
4499 for (i = 0; i < 11; i++)
4500 returns[num_returns++] = ctx->f32; /* VGPRs */
4501 }
4502 break;
4503
4504 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4505 /* Merged stages have 8 system SGPRs at the beginning. */
4506 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_LO_GS) */
4507 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_HI_GS) */
4508 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4509 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4510 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4511 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4512 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4513 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4514
4515 declare_global_desc_pointers(ctx, &fninfo);
4516 declare_per_stage_desc_pointers(ctx, &fninfo,
4517 (ctx->type == PIPE_SHADER_VERTEX ||
4518 ctx->type == PIPE_SHADER_TESS_EVAL));
4519 if (ctx->type == PIPE_SHADER_VERTEX) {
4520 declare_vs_specific_input_sgprs(ctx, &fninfo);
4521 } else {
4522 /* TESS_EVAL (and also GEOMETRY):
4523 * Declare as many input SGPRs as the VS has. */
4524 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4525 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4526 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4527 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4528 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4529 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4530 }
4531
4532 declare_per_stage_desc_pointers(ctx, &fninfo,
4533 ctx->type == PIPE_SHADER_GEOMETRY);
4534
4535 /* VGPRs (first GS, then VS/TES) */
4536 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4537 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4538 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4539 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4540 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4541
4542 if (ctx->type == PIPE_SHADER_VERTEX) {
4543 declare_vs_input_vgprs(ctx, &fninfo,
4544 &num_prolog_vgprs);
4545 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4546 declare_tes_input_vgprs(ctx, &fninfo);
4547 }
4548
4549 if (ctx->type == PIPE_SHADER_VERTEX ||
4550 ctx->type == PIPE_SHADER_TESS_EVAL) {
4551 /* ES return values are inputs to GS. */
4552 for (i = 0; i < 8 + GFX9_GS_NUM_USER_SGPR; i++)
4553 returns[num_returns++] = ctx->i32; /* SGPRs */
4554 for (i = 0; i < 5; i++)
4555 returns[num_returns++] = ctx->f32; /* VGPRs */
4556 }
4557 break;
4558
4559 case PIPE_SHADER_TESS_EVAL:
4560 declare_global_desc_pointers(ctx, &fninfo);
4561 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4562 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4563 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4564
4565 if (shader->key.as_es) {
4566 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4567 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4568 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4569 } else {
4570 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4571 declare_streamout_params(ctx, &shader->selector->so,
4572 &fninfo);
4573 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4574 }
4575
4576 /* VGPRs */
4577 declare_tes_input_vgprs(ctx, &fninfo);
4578 break;
4579
4580 case PIPE_SHADER_GEOMETRY:
4581 declare_global_desc_pointers(ctx, &fninfo);
4582 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4583 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4584 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4585
4586 /* VGPRs */
4587 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4588 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4589 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4590 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4591 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4592 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4593 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4594 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4595 break;
4596
4597 case PIPE_SHADER_FRAGMENT:
4598 declare_global_desc_pointers(ctx, &fninfo);
4599 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4600 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4601 add_arg_checked(&fninfo, ARG_SGPR, ctx->i32, SI_PARAM_PRIM_MASK);
4602
4603 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4604 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4605 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4606 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4607 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4608 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4609 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4610 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4611 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4612 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4613 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4614 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4615 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4616 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4617 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4618 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4619 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4620 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4621 shader->info.face_vgpr_index = 20;
4622 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4623 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4624 shader->info.ancillary_vgpr_index = 21;
4625 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4626 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4627 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4628
4629 /* Color inputs from the prolog. */
4630 if (shader->selector->info.colors_read) {
4631 unsigned num_color_elements =
4632 util_bitcount(shader->selector->info.colors_read);
4633
4634 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4635 for (i = 0; i < num_color_elements; i++)
4636 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4637
4638 num_prolog_vgprs += num_color_elements;
4639 }
4640
4641 /* Outputs for the epilog. */
4642 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4643 num_returns =
4644 num_return_sgprs +
4645 util_bitcount(shader->selector->info.colors_written) * 4 +
4646 shader->selector->info.writes_z +
4647 shader->selector->info.writes_stencil +
4648 shader->selector->info.writes_samplemask +
4649 1 /* SampleMaskIn */;
4650
4651 num_returns = MAX2(num_returns,
4652 num_return_sgprs +
4653 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4654
4655 for (i = 0; i < num_return_sgprs; i++)
4656 returns[i] = ctx->i32;
4657 for (; i < num_returns; i++)
4658 returns[i] = ctx->f32;
4659 break;
4660
4661 case PIPE_SHADER_COMPUTE:
4662 declare_global_desc_pointers(ctx, &fninfo);
4663 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4664 if (shader->selector->info.uses_grid_size)
4665 ctx->param_grid_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4666 if (shader->selector->info.uses_block_size)
4667 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4668
4669 for (i = 0; i < 3; i++) {
4670 ctx->param_block_id[i] = -1;
4671 if (shader->selector->info.uses_block_id[i])
4672 ctx->param_block_id[i] = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4673 }
4674
4675 ctx->param_thread_id = add_arg(&fninfo, ARG_VGPR, v3i32);
4676 break;
4677 default:
4678 assert(0 && "unimplemented shader");
4679 return;
4680 }
4681
4682 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4683 si_get_max_workgroup_size(shader));
4684
4685 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4686 if (ctx->type == PIPE_SHADER_FRAGMENT &&
4687 ctx->separate_prolog) {
4688 si_llvm_add_attribute(ctx->main_fn,
4689 "InitialPSInputAddr",
4690 S_0286D0_PERSP_SAMPLE_ENA(1) |
4691 S_0286D0_PERSP_CENTER_ENA(1) |
4692 S_0286D0_PERSP_CENTROID_ENA(1) |
4693 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4694 S_0286D0_LINEAR_CENTER_ENA(1) |
4695 S_0286D0_LINEAR_CENTROID_ENA(1) |
4696 S_0286D0_FRONT_FACE_ENA(1) |
4697 S_0286D0_ANCILLARY_ENA(1) |
4698 S_0286D0_POS_FIXED_PT_ENA(1));
4699 }
4700
4701 shader->info.num_input_sgprs = 0;
4702 shader->info.num_input_vgprs = 0;
4703
4704 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4705 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
4706
4707 for (; i < fninfo.num_params; ++i)
4708 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
4709
4710 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4711 shader->info.num_input_vgprs -= num_prolog_vgprs;
4712
4713 if (shader->key.as_ls ||
4714 ctx->type == PIPE_SHADER_TESS_CTRL ||
4715 /* GFX9 has the ESGS ring buffer in LDS. */
4716 type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY)
4717 ac_declare_lds_as_pointer(&ctx->ac);
4718 }
4719
4720 /**
4721 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4722 * for later use.
4723 */
4724 static void preload_ring_buffers(struct si_shader_context *ctx)
4725 {
4726 LLVMBuilderRef builder = ctx->ac.builder;
4727
4728 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
4729 ctx->param_rw_buffers);
4730
4731 if (ctx->screen->info.chip_class <= VI &&
4732 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
4733 unsigned ring =
4734 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
4735 : SI_ES_RING_ESGS;
4736 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
4737
4738 ctx->esgs_ring =
4739 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4740 }
4741
4742 if (ctx->shader->is_gs_copy_shader) {
4743 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4744
4745 ctx->gsvs_ring[0] =
4746 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4747 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
4748 const struct si_shader_selector *sel = ctx->shader->selector;
4749 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4750 LLVMValueRef base_ring;
4751
4752 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4753
4754 /* The conceptual layout of the GSVS ring is
4755 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4756 * but the real memory layout is swizzled across
4757 * threads:
4758 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4759 * t16v0c0 ..
4760 * Override the buffer descriptor accordingly.
4761 */
4762 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
4763 uint64_t stream_offset = 0;
4764
4765 for (unsigned stream = 0; stream < 4; ++stream) {
4766 unsigned num_components;
4767 unsigned stride;
4768 unsigned num_records;
4769 LLVMValueRef ring, tmp;
4770
4771 num_components = sel->info.num_stream_output_components[stream];
4772 if (!num_components)
4773 continue;
4774
4775 stride = 4 * num_components * sel->gs_max_out_vertices;
4776
4777 /* Limit on the stride field for <= CIK. */
4778 assert(stride < (1 << 14));
4779
4780 num_records = 64;
4781
4782 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
4783 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
4784 tmp = LLVMBuildAdd(builder, tmp,
4785 LLVMConstInt(ctx->i64,
4786 stream_offset, 0), "");
4787 stream_offset += stride * 64;
4788
4789 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
4790 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
4791 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
4792 tmp = LLVMBuildOr(builder, tmp,
4793 LLVMConstInt(ctx->i32,
4794 S_008F04_STRIDE(stride) |
4795 S_008F04_SWIZZLE_ENABLE(1), 0), "");
4796 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
4797 ring = LLVMBuildInsertElement(builder, ring,
4798 LLVMConstInt(ctx->i32, num_records, 0),
4799 LLVMConstInt(ctx->i32, 2, 0), "");
4800 ring = LLVMBuildInsertElement(builder, ring,
4801 LLVMConstInt(ctx->i32,
4802 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4803 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4804 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4805 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
4806 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4807 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
4808 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
4809 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
4810 S_008F0C_ADD_TID_ENABLE(1),
4811 0),
4812 LLVMConstInt(ctx->i32, 3, 0), "");
4813
4814 ctx->gsvs_ring[stream] = ring;
4815 }
4816 }
4817 }
4818
4819 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
4820 LLVMValueRef param_rw_buffers,
4821 unsigned param_pos_fixed_pt)
4822 {
4823 LLVMBuilderRef builder = ctx->ac.builder;
4824 LLVMValueRef slot, desc, offset, row, bit, address[2];
4825
4826 /* Use the fixed-point gl_FragCoord input.
4827 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
4828 * per coordinate to get the repeating effect.
4829 */
4830 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
4831 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
4832
4833 /* Load the buffer descriptor. */
4834 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
4835 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
4836
4837 /* The stipple pattern is 32x32, each row has 32 bits. */
4838 offset = LLVMBuildMul(builder, address[1],
4839 LLVMConstInt(ctx->i32, 4, 0), "");
4840 row = buffer_load_const(ctx, desc, offset);
4841 row = ac_to_integer(&ctx->ac, row);
4842 bit = LLVMBuildLShr(builder, row, address[0], "");
4843 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
4844 ac_build_kill_if_false(&ctx->ac, bit);
4845 }
4846
4847 void si_shader_binary_read_config(struct ac_shader_binary *binary,
4848 struct si_shader_config *conf,
4849 unsigned symbol_offset)
4850 {
4851 unsigned i;
4852 const unsigned char *config =
4853 ac_shader_binary_config_start(binary, symbol_offset);
4854 bool really_needs_scratch = false;
4855
4856 /* LLVM adds SGPR spills to the scratch size.
4857 * Find out if we really need the scratch buffer.
4858 */
4859 for (i = 0; i < binary->reloc_count; i++) {
4860 const struct ac_shader_reloc *reloc = &binary->relocs[i];
4861
4862 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
4863 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4864 really_needs_scratch = true;
4865 break;
4866 }
4867 }
4868
4869 /* XXX: We may be able to emit some of these values directly rather than
4870 * extracting fields to be emitted later.
4871 */
4872
4873 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
4874 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
4875 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
4876 switch (reg) {
4877 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
4878 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
4879 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
4880 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
4881 case R_00B848_COMPUTE_PGM_RSRC1:
4882 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
4883 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
4884 conf->float_mode = G_00B028_FLOAT_MODE(value);
4885 conf->rsrc1 = value;
4886 break;
4887 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
4888 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
4889 break;
4890 case R_00B84C_COMPUTE_PGM_RSRC2:
4891 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
4892 conf->rsrc2 = value;
4893 break;
4894 case R_0286CC_SPI_PS_INPUT_ENA:
4895 conf->spi_ps_input_ena = value;
4896 break;
4897 case R_0286D0_SPI_PS_INPUT_ADDR:
4898 conf->spi_ps_input_addr = value;
4899 break;
4900 case R_0286E8_SPI_TMPRING_SIZE:
4901 case R_00B860_COMPUTE_TMPRING_SIZE:
4902 /* WAVESIZE is in units of 256 dwords. */
4903 if (really_needs_scratch)
4904 conf->scratch_bytes_per_wave =
4905 G_00B860_WAVESIZE(value) * 256 * 4;
4906 break;
4907 case 0x4: /* SPILLED_SGPRS */
4908 conf->spilled_sgprs = value;
4909 break;
4910 case 0x8: /* SPILLED_VGPRS */
4911 conf->spilled_vgprs = value;
4912 break;
4913 default:
4914 {
4915 static bool printed;
4916
4917 if (!printed) {
4918 fprintf(stderr, "Warning: LLVM emitted unknown "
4919 "config register: 0x%x\n", reg);
4920 printed = true;
4921 }
4922 }
4923 break;
4924 }
4925 }
4926
4927 if (!conf->spi_ps_input_addr)
4928 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
4929 }
4930
4931 void si_shader_apply_scratch_relocs(struct si_shader *shader,
4932 uint64_t scratch_va)
4933 {
4934 unsigned i;
4935 uint32_t scratch_rsrc_dword0 = scratch_va;
4936 uint32_t scratch_rsrc_dword1 =
4937 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
4938
4939 /* Enable scratch coalescing. */
4940 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
4941
4942 for (i = 0 ; i < shader->binary.reloc_count; i++) {
4943 const struct ac_shader_reloc *reloc =
4944 &shader->binary.relocs[i];
4945 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
4946 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4947 &scratch_rsrc_dword0, 4);
4948 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4949 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4950 &scratch_rsrc_dword1, 4);
4951 }
4952 }
4953 }
4954
4955 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
4956 {
4957 unsigned size = shader->binary.code_size;
4958
4959 if (shader->prolog)
4960 size += shader->prolog->binary.code_size;
4961 if (shader->previous_stage)
4962 size += shader->previous_stage->binary.code_size;
4963 if (shader->prolog2)
4964 size += shader->prolog2->binary.code_size;
4965 if (shader->epilog)
4966 size += shader->epilog->binary.code_size;
4967 return size;
4968 }
4969
4970 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
4971 {
4972 const struct ac_shader_binary *prolog =
4973 shader->prolog ? &shader->prolog->binary : NULL;
4974 const struct ac_shader_binary *previous_stage =
4975 shader->previous_stage ? &shader->previous_stage->binary : NULL;
4976 const struct ac_shader_binary *prolog2 =
4977 shader->prolog2 ? &shader->prolog2->binary : NULL;
4978 const struct ac_shader_binary *epilog =
4979 shader->epilog ? &shader->epilog->binary : NULL;
4980 const struct ac_shader_binary *mainb = &shader->binary;
4981 unsigned bo_size = si_get_shader_binary_size(shader) +
4982 (!epilog ? mainb->rodata_size : 0);
4983 unsigned char *ptr;
4984
4985 assert(!prolog || !prolog->rodata_size);
4986 assert(!previous_stage || !previous_stage->rodata_size);
4987 assert(!prolog2 || !prolog2->rodata_size);
4988 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
4989 !mainb->rodata_size);
4990 assert(!epilog || !epilog->rodata_size);
4991
4992 r600_resource_reference(&shader->bo, NULL);
4993 shader->bo = (struct r600_resource*)
4994 si_aligned_buffer_create(&sscreen->b,
4995 sscreen->cpdma_prefetch_writes_memory ?
4996 0 : R600_RESOURCE_FLAG_READ_ONLY,
4997 PIPE_USAGE_IMMUTABLE,
4998 align(bo_size, SI_CPDMA_ALIGNMENT),
4999 256);
5000 if (!shader->bo)
5001 return -ENOMEM;
5002
5003 /* Upload. */
5004 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5005 PIPE_TRANSFER_READ_WRITE |
5006 PIPE_TRANSFER_UNSYNCHRONIZED);
5007
5008 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5009 * endian-independent. */
5010 if (prolog) {
5011 memcpy(ptr, prolog->code, prolog->code_size);
5012 ptr += prolog->code_size;
5013 }
5014 if (previous_stage) {
5015 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5016 ptr += previous_stage->code_size;
5017 }
5018 if (prolog2) {
5019 memcpy(ptr, prolog2->code, prolog2->code_size);
5020 ptr += prolog2->code_size;
5021 }
5022
5023 memcpy(ptr, mainb->code, mainb->code_size);
5024 ptr += mainb->code_size;
5025
5026 if (epilog)
5027 memcpy(ptr, epilog->code, epilog->code_size);
5028 else if (mainb->rodata_size > 0)
5029 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5030
5031 sscreen->ws->buffer_unmap(shader->bo->buf);
5032 return 0;
5033 }
5034
5035 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5036 struct pipe_debug_callback *debug,
5037 const char *name, FILE *file)
5038 {
5039 char *line, *p;
5040 unsigned i, count;
5041
5042 if (binary->disasm_string) {
5043 fprintf(file, "Shader %s disassembly:\n", name);
5044 fprintf(file, "%s", binary->disasm_string);
5045
5046 if (debug && debug->debug_message) {
5047 /* Very long debug messages are cut off, so send the
5048 * disassembly one line at a time. This causes more
5049 * overhead, but on the plus side it simplifies
5050 * parsing of resulting logs.
5051 */
5052 pipe_debug_message(debug, SHADER_INFO,
5053 "Shader Disassembly Begin");
5054
5055 line = binary->disasm_string;
5056 while (*line) {
5057 p = util_strchrnul(line, '\n');
5058 count = p - line;
5059
5060 if (count) {
5061 pipe_debug_message(debug, SHADER_INFO,
5062 "%.*s", count, line);
5063 }
5064
5065 if (!*p)
5066 break;
5067 line = p + 1;
5068 }
5069
5070 pipe_debug_message(debug, SHADER_INFO,
5071 "Shader Disassembly End");
5072 }
5073 } else {
5074 fprintf(file, "Shader %s binary:\n", name);
5075 for (i = 0; i < binary->code_size; i += 4) {
5076 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5077 binary->code[i + 3], binary->code[i + 2],
5078 binary->code[i + 1], binary->code[i]);
5079 }
5080 }
5081 }
5082
5083 static void si_shader_dump_stats(struct si_screen *sscreen,
5084 const struct si_shader *shader,
5085 struct pipe_debug_callback *debug,
5086 unsigned processor,
5087 FILE *file,
5088 bool check_debug_option)
5089 {
5090 const struct si_shader_config *conf = &shader->config;
5091 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
5092 unsigned code_size = si_get_shader_binary_size(shader);
5093 unsigned lds_increment = sscreen->info.chip_class >= CIK ? 512 : 256;
5094 unsigned lds_per_wave = 0;
5095 unsigned max_simd_waves;
5096
5097 switch (sscreen->info.family) {
5098 /* These always have 8 waves: */
5099 case CHIP_POLARIS10:
5100 case CHIP_POLARIS11:
5101 case CHIP_POLARIS12:
5102 max_simd_waves = 8;
5103 break;
5104 default:
5105 max_simd_waves = 10;
5106 }
5107
5108 /* Compute LDS usage for PS. */
5109 switch (processor) {
5110 case PIPE_SHADER_FRAGMENT:
5111 /* The minimum usage per wave is (num_inputs * 48). The maximum
5112 * usage is (num_inputs * 48 * 16).
5113 * We can get anything in between and it varies between waves.
5114 *
5115 * The 48 bytes per input for a single primitive is equal to
5116 * 4 bytes/component * 4 components/input * 3 points.
5117 *
5118 * Other stages don't know the size at compile time or don't
5119 * allocate LDS per wave, but instead they do it per thread group.
5120 */
5121 lds_per_wave = conf->lds_size * lds_increment +
5122 align(num_inputs * 48, lds_increment);
5123 break;
5124 case PIPE_SHADER_COMPUTE:
5125 if (shader->selector) {
5126 unsigned max_workgroup_size =
5127 si_get_max_workgroup_size(shader);
5128 lds_per_wave = (conf->lds_size * lds_increment) /
5129 DIV_ROUND_UP(max_workgroup_size, 64);
5130 }
5131 break;
5132 }
5133
5134 /* Compute the per-SIMD wave counts. */
5135 if (conf->num_sgprs) {
5136 if (sscreen->info.chip_class >= VI)
5137 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5138 else
5139 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5140 }
5141
5142 if (conf->num_vgprs)
5143 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5144
5145 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5146 * 16KB makes some SIMDs unoccupied). */
5147 if (lds_per_wave)
5148 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5149
5150 if (!check_debug_option ||
5151 si_can_dump_shader(sscreen, processor)) {
5152 if (processor == PIPE_SHADER_FRAGMENT) {
5153 fprintf(file, "*** SHADER CONFIG ***\n"
5154 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5155 "SPI_PS_INPUT_ENA = 0x%04x\n",
5156 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5157 }
5158
5159 fprintf(file, "*** SHADER STATS ***\n"
5160 "SGPRS: %d\n"
5161 "VGPRS: %d\n"
5162 "Spilled SGPRs: %d\n"
5163 "Spilled VGPRs: %d\n"
5164 "Private memory VGPRs: %d\n"
5165 "Code Size: %d bytes\n"
5166 "LDS: %d blocks\n"
5167 "Scratch: %d bytes per wave\n"
5168 "Max Waves: %d\n"
5169 "********************\n\n\n",
5170 conf->num_sgprs, conf->num_vgprs,
5171 conf->spilled_sgprs, conf->spilled_vgprs,
5172 conf->private_mem_vgprs, code_size,
5173 conf->lds_size, conf->scratch_bytes_per_wave,
5174 max_simd_waves);
5175 }
5176
5177 pipe_debug_message(debug, SHADER_INFO,
5178 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5179 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5180 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5181 conf->num_sgprs, conf->num_vgprs, code_size,
5182 conf->lds_size, conf->scratch_bytes_per_wave,
5183 max_simd_waves, conf->spilled_sgprs,
5184 conf->spilled_vgprs, conf->private_mem_vgprs);
5185 }
5186
5187 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5188 {
5189 switch (processor) {
5190 case PIPE_SHADER_VERTEX:
5191 if (shader->key.as_es)
5192 return "Vertex Shader as ES";
5193 else if (shader->key.as_ls)
5194 return "Vertex Shader as LS";
5195 else
5196 return "Vertex Shader as VS";
5197 case PIPE_SHADER_TESS_CTRL:
5198 return "Tessellation Control Shader";
5199 case PIPE_SHADER_TESS_EVAL:
5200 if (shader->key.as_es)
5201 return "Tessellation Evaluation Shader as ES";
5202 else
5203 return "Tessellation Evaluation Shader as VS";
5204 case PIPE_SHADER_GEOMETRY:
5205 if (shader->is_gs_copy_shader)
5206 return "GS Copy Shader as VS";
5207 else
5208 return "Geometry Shader";
5209 case PIPE_SHADER_FRAGMENT:
5210 return "Pixel Shader";
5211 case PIPE_SHADER_COMPUTE:
5212 return "Compute Shader";
5213 default:
5214 return "Unknown Shader";
5215 }
5216 }
5217
5218 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5219 struct pipe_debug_callback *debug, unsigned processor,
5220 FILE *file, bool check_debug_option)
5221 {
5222 if (!check_debug_option ||
5223 si_can_dump_shader(sscreen, processor))
5224 si_dump_shader_key(processor, shader, file);
5225
5226 if (!check_debug_option && shader->binary.llvm_ir_string) {
5227 if (shader->previous_stage &&
5228 shader->previous_stage->binary.llvm_ir_string) {
5229 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5230 si_get_shader_name(shader, processor));
5231 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5232 }
5233
5234 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5235 si_get_shader_name(shader, processor));
5236 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5237 }
5238
5239 if (!check_debug_option ||
5240 (si_can_dump_shader(sscreen, processor) &&
5241 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5242 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5243
5244 if (shader->prolog)
5245 si_shader_dump_disassembly(&shader->prolog->binary,
5246 debug, "prolog", file);
5247 if (shader->previous_stage)
5248 si_shader_dump_disassembly(&shader->previous_stage->binary,
5249 debug, "previous stage", file);
5250 if (shader->prolog2)
5251 si_shader_dump_disassembly(&shader->prolog2->binary,
5252 debug, "prolog2", file);
5253
5254 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5255
5256 if (shader->epilog)
5257 si_shader_dump_disassembly(&shader->epilog->binary,
5258 debug, "epilog", file);
5259 fprintf(file, "\n");
5260 }
5261
5262 si_shader_dump_stats(sscreen, shader, debug, processor, file,
5263 check_debug_option);
5264 }
5265
5266 static int si_compile_llvm(struct si_screen *sscreen,
5267 struct ac_shader_binary *binary,
5268 struct si_shader_config *conf,
5269 LLVMTargetMachineRef tm,
5270 LLVMModuleRef mod,
5271 struct pipe_debug_callback *debug,
5272 unsigned processor,
5273 const char *name)
5274 {
5275 int r = 0;
5276 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5277
5278 if (si_can_dump_shader(sscreen, processor)) {
5279 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5280
5281 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5282 fprintf(stderr, "%s LLVM IR:\n\n", name);
5283 ac_dump_module(mod);
5284 fprintf(stderr, "\n");
5285 }
5286 }
5287
5288 if (sscreen->record_llvm_ir) {
5289 char *ir = LLVMPrintModuleToString(mod);
5290 binary->llvm_ir_string = strdup(ir);
5291 LLVMDisposeMessage(ir);
5292 }
5293
5294 if (!si_replace_shader(count, binary)) {
5295 r = si_llvm_compile(mod, binary, tm, debug);
5296 if (r)
5297 return r;
5298 }
5299
5300 si_shader_binary_read_config(binary, conf, 0);
5301
5302 /* Enable 64-bit and 16-bit denormals, because there is no performance
5303 * cost.
5304 *
5305 * If denormals are enabled, all floating-point output modifiers are
5306 * ignored.
5307 *
5308 * Don't enable denormals for 32-bit floats, because:
5309 * - Floating-point output modifiers would be ignored by the hw.
5310 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5311 * have to stop using those.
5312 * - SI & CI would be very slow.
5313 */
5314 conf->float_mode |= V_00B028_FP_64_DENORMS;
5315
5316 FREE(binary->config);
5317 FREE(binary->global_symbol_offsets);
5318 binary->config = NULL;
5319 binary->global_symbol_offsets = NULL;
5320
5321 /* Some shaders can't have rodata because their binaries can be
5322 * concatenated.
5323 */
5324 if (binary->rodata_size &&
5325 (processor == PIPE_SHADER_VERTEX ||
5326 processor == PIPE_SHADER_TESS_CTRL ||
5327 processor == PIPE_SHADER_TESS_EVAL ||
5328 processor == PIPE_SHADER_FRAGMENT)) {
5329 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5330 return -EINVAL;
5331 }
5332
5333 return r;
5334 }
5335
5336 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5337 {
5338 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5339 LLVMBuildRetVoid(ctx->ac.builder);
5340 else
5341 LLVMBuildRet(ctx->ac.builder, ret);
5342 }
5343
5344 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5345 struct si_shader *
5346 si_generate_gs_copy_shader(struct si_screen *sscreen,
5347 LLVMTargetMachineRef tm,
5348 struct si_shader_selector *gs_selector,
5349 struct pipe_debug_callback *debug)
5350 {
5351 struct si_shader_context ctx;
5352 struct si_shader *shader;
5353 LLVMBuilderRef builder;
5354 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
5355 struct lp_build_context *uint = &bld_base->uint_bld;
5356 struct si_shader_output_values *outputs;
5357 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5358 int i, r;
5359
5360 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5361
5362 if (!outputs)
5363 return NULL;
5364
5365 shader = CALLOC_STRUCT(si_shader);
5366 if (!shader) {
5367 FREE(outputs);
5368 return NULL;
5369 }
5370
5371 /* We can leave the fence as permanently signaled because the GS copy
5372 * shader only becomes visible globally after it has been compiled. */
5373 util_queue_fence_init(&shader->ready);
5374
5375 shader->selector = gs_selector;
5376 shader->is_gs_copy_shader = true;
5377
5378 si_init_shader_ctx(&ctx, sscreen, tm);
5379 ctx.shader = shader;
5380 ctx.type = PIPE_SHADER_VERTEX;
5381
5382 builder = ctx.ac.builder;
5383
5384 create_function(&ctx);
5385 preload_ring_buffers(&ctx);
5386
5387 LLVMValueRef voffset =
5388 lp_build_mul_imm(uint, ctx.abi.vertex_id, 4);
5389
5390 /* Fetch the vertex stream ID.*/
5391 LLVMValueRef stream_id;
5392
5393 if (gs_selector->so.num_outputs)
5394 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5395 else
5396 stream_id = ctx.i32_0;
5397
5398 /* Fill in output information. */
5399 for (i = 0; i < gsinfo->num_outputs; ++i) {
5400 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5401 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5402
5403 for (int chan = 0; chan < 4; chan++) {
5404 outputs[i].vertex_stream[chan] =
5405 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5406 }
5407 }
5408
5409 LLVMBasicBlockRef end_bb;
5410 LLVMValueRef switch_inst;
5411
5412 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5413 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5414
5415 for (int stream = 0; stream < 4; stream++) {
5416 LLVMBasicBlockRef bb;
5417 unsigned offset;
5418
5419 if (!gsinfo->num_stream_output_components[stream])
5420 continue;
5421
5422 if (stream > 0 && !gs_selector->so.num_outputs)
5423 continue;
5424
5425 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5426 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5427 LLVMPositionBuilderAtEnd(builder, bb);
5428
5429 /* Fetch vertex data from GSVS ring */
5430 offset = 0;
5431 for (i = 0; i < gsinfo->num_outputs; ++i) {
5432 for (unsigned chan = 0; chan < 4; chan++) {
5433 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5434 outputs[i].vertex_stream[chan] != stream) {
5435 outputs[i].values[chan] = ctx.bld_base.base.undef;
5436 continue;
5437 }
5438
5439 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5440 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5441 offset++;
5442
5443 outputs[i].values[chan] =
5444 ac_build_buffer_load(&ctx.ac,
5445 ctx.gsvs_ring[0], 1,
5446 ctx.i32_0, voffset,
5447 soffset, 0, 1, 1,
5448 true, false);
5449 }
5450 }
5451
5452 /* Streamout and exports. */
5453 if (gs_selector->so.num_outputs) {
5454 si_llvm_emit_streamout(&ctx, outputs,
5455 gsinfo->num_outputs,
5456 stream);
5457 }
5458
5459 if (stream == 0)
5460 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5461
5462 LLVMBuildBr(builder, end_bb);
5463 }
5464
5465 LLVMPositionBuilderAtEnd(builder, end_bb);
5466
5467 LLVMBuildRetVoid(ctx.ac.builder);
5468
5469 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5470 si_llvm_optimize_module(&ctx);
5471
5472 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5473 &ctx.shader->config, ctx.tm,
5474 ctx.gallivm.module,
5475 debug, PIPE_SHADER_GEOMETRY,
5476 "GS Copy Shader");
5477 if (!r) {
5478 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5479 fprintf(stderr, "GS Copy Shader:\n");
5480 si_shader_dump(sscreen, ctx.shader, debug,
5481 PIPE_SHADER_GEOMETRY, stderr, true);
5482 r = si_shader_binary_upload(sscreen, ctx.shader);
5483 }
5484
5485 si_llvm_dispose(&ctx);
5486
5487 FREE(outputs);
5488
5489 if (r != 0) {
5490 FREE(shader);
5491 shader = NULL;
5492 }
5493 return shader;
5494 }
5495
5496 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5497 const struct si_vs_prolog_bits *prolog,
5498 const char *prefix, FILE *f)
5499 {
5500 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5501 prefix, prolog->instance_divisor_is_one);
5502 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5503 prefix, prolog->instance_divisor_is_fetched);
5504 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5505 prefix, prolog->ls_vgpr_fix);
5506
5507 fprintf(f, " mono.vs.fix_fetch = {");
5508 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5509 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5510 fprintf(f, "}\n");
5511 }
5512
5513 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5514 FILE *f)
5515 {
5516 const struct si_shader_key *key = &shader->key;
5517
5518 fprintf(f, "SHADER KEY\n");
5519
5520 switch (processor) {
5521 case PIPE_SHADER_VERTEX:
5522 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5523 "part.vs.prolog", f);
5524 fprintf(f, " as_es = %u\n", key->as_es);
5525 fprintf(f, " as_ls = %u\n", key->as_ls);
5526 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5527 key->mono.u.vs_export_prim_id);
5528 break;
5529
5530 case PIPE_SHADER_TESS_CTRL:
5531 if (shader->selector->screen->info.chip_class >= GFX9) {
5532 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5533 "part.tcs.ls_prolog", f);
5534 }
5535 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5536 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5537 break;
5538
5539 case PIPE_SHADER_TESS_EVAL:
5540 fprintf(f, " as_es = %u\n", key->as_es);
5541 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5542 key->mono.u.vs_export_prim_id);
5543 break;
5544
5545 case PIPE_SHADER_GEOMETRY:
5546 if (shader->is_gs_copy_shader)
5547 break;
5548
5549 if (shader->selector->screen->info.chip_class >= GFX9 &&
5550 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5551 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5552 "part.gs.vs_prolog", f);
5553 }
5554 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5555 break;
5556
5557 case PIPE_SHADER_COMPUTE:
5558 break;
5559
5560 case PIPE_SHADER_FRAGMENT:
5561 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5562 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5563 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5564 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5565 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5566 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5567 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5568 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5569 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5570 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5571 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5572 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5573 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5574 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5575 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5576 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5577 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5578 break;
5579
5580 default:
5581 assert(0);
5582 }
5583
5584 if ((processor == PIPE_SHADER_GEOMETRY ||
5585 processor == PIPE_SHADER_TESS_EVAL ||
5586 processor == PIPE_SHADER_VERTEX) &&
5587 !key->as_es && !key->as_ls) {
5588 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5589 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5590 }
5591 }
5592
5593 static void si_init_shader_ctx(struct si_shader_context *ctx,
5594 struct si_screen *sscreen,
5595 LLVMTargetMachineRef tm)
5596 {
5597 struct lp_build_tgsi_context *bld_base;
5598
5599 si_llvm_context_init(ctx, sscreen, tm);
5600
5601 bld_base = &ctx->bld_base;
5602 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5603
5604 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5605 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5606 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5607
5608 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5609
5610 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5611
5612 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5613 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5614 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5615 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5616
5617 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5618 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5619 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5620 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5621 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5622 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5623 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5624 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
5625 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5626
5627 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5628 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
5629 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5630 }
5631
5632 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5633 {
5634 struct si_shader *shader = ctx->shader;
5635 struct tgsi_shader_info *info = &shader->selector->info;
5636
5637 if ((ctx->type != PIPE_SHADER_VERTEX &&
5638 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5639 shader->key.as_ls ||
5640 shader->key.as_es)
5641 return;
5642
5643 ac_optimize_vs_outputs(&ctx->ac,
5644 ctx->main_fn,
5645 shader->info.vs_output_param_offset,
5646 info->num_outputs,
5647 &shader->info.nr_param_exports);
5648 }
5649
5650 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
5651 {
5652 ctx->shader->config.private_mem_vgprs = 0;
5653
5654 /* Process all LLVM instructions. */
5655 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
5656 while (bb) {
5657 LLVMValueRef next = LLVMGetFirstInstruction(bb);
5658
5659 while (next) {
5660 LLVMValueRef inst = next;
5661 next = LLVMGetNextInstruction(next);
5662
5663 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
5664 continue;
5665
5666 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
5667 /* No idea why LLVM aligns allocas to 4 elements. */
5668 unsigned alignment = LLVMGetAlignment(inst);
5669 unsigned dw_size = align(ac_get_type_size(type) / 4, alignment);
5670 ctx->shader->config.private_mem_vgprs += dw_size;
5671 }
5672 bb = LLVMGetNextBasicBlock(bb);
5673 }
5674 }
5675
5676 static void si_init_exec_from_input(struct si_shader_context *ctx,
5677 unsigned param, unsigned bitoffset)
5678 {
5679 LLVMValueRef args[] = {
5680 LLVMGetParam(ctx->main_fn, param),
5681 LLVMConstInt(ctx->i32, bitoffset, 0),
5682 };
5683 lp_build_intrinsic(ctx->ac.builder,
5684 "llvm.amdgcn.init.exec.from.input",
5685 ctx->voidt, args, 2, LP_FUNC_ATTR_CONVERGENT);
5686 }
5687
5688 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
5689 const struct si_vs_prolog_bits *key)
5690 {
5691 /* VGPR initialization fixup for Vega10 and Raven is always done in the
5692 * VS prolog. */
5693 return sel->vs_needs_prolog || key->ls_vgpr_fix;
5694 }
5695
5696 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
5697 bool is_monolithic)
5698 {
5699 struct si_shader *shader = ctx->shader;
5700 struct si_shader_selector *sel = shader->selector;
5701 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5702
5703 // TODO clean all this up!
5704 switch (ctx->type) {
5705 case PIPE_SHADER_VERTEX:
5706 ctx->load_input = declare_input_vs;
5707 if (shader->key.as_ls)
5708 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
5709 else if (shader->key.as_es)
5710 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5711 else
5712 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5713 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5714 break;
5715 case PIPE_SHADER_TESS_CTRL:
5716 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5717 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5718 bld_base->emit_store = store_output_tcs;
5719 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
5720 break;
5721 case PIPE_SHADER_TESS_EVAL:
5722 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
5723 if (shader->key.as_es)
5724 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5725 else
5726 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5727 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5728 break;
5729 case PIPE_SHADER_GEOMETRY:
5730 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
5731 ctx->abi.load_inputs = si_nir_load_input_gs;
5732 ctx->abi.emit_vertex = si_llvm_emit_vertex;
5733 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
5734 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
5735 break;
5736 case PIPE_SHADER_FRAGMENT:
5737 ctx->load_input = declare_input_fs;
5738 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
5739 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5740 break;
5741 case PIPE_SHADER_COMPUTE:
5742 break;
5743 default:
5744 assert(!"Unsupported shader type");
5745 return false;
5746 }
5747
5748 ctx->abi.load_ubo = load_ubo;
5749 ctx->abi.load_ssbo = load_ssbo;
5750
5751 create_function(ctx);
5752 preload_ring_buffers(ctx);
5753
5754 /* For GFX9 merged shaders:
5755 * - Set EXEC for the first shader. If the prolog is present, set
5756 * EXEC there instead.
5757 * - Add a barrier before the second shader.
5758 * - In the second shader, reset EXEC to ~0 and wrap the main part in
5759 * an if-statement. This is required for correctness in geometry
5760 * shaders, to ensure that empty GS waves do not send GS_EMIT and
5761 * GS_CUT messages.
5762 *
5763 * For monolithic merged shaders, the first shader is wrapped in an
5764 * if-block together with its prolog in si_build_wrapper_function.
5765 */
5766 if (ctx->screen->info.chip_class >= GFX9) {
5767 if (!is_monolithic &&
5768 sel->info.num_instructions > 1 && /* not empty shader */
5769 (shader->key.as_es || shader->key.as_ls) &&
5770 (ctx->type == PIPE_SHADER_TESS_EVAL ||
5771 (ctx->type == PIPE_SHADER_VERTEX &&
5772 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
5773 si_init_exec_from_input(ctx,
5774 ctx->param_merged_wave_info, 0);
5775 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
5776 ctx->type == PIPE_SHADER_GEOMETRY) {
5777 if (!is_monolithic)
5778 ac_init_exec_full_mask(&ctx->ac);
5779
5780 /* The barrier must execute for all shaders in a
5781 * threadgroup.
5782 */
5783 si_llvm_emit_barrier(NULL, bld_base, NULL);
5784
5785 LLVMValueRef num_threads = unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
5786 LLVMValueRef ena =
5787 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
5788 ac_get_thread_id(&ctx->ac), num_threads, "");
5789 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
5790 }
5791 }
5792
5793 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
5794 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
5795 for (unsigned i = 0; i < 6; i++) {
5796 ctx->invoc0_tess_factors[i] =
5797 lp_build_alloca_undef(&ctx->gallivm, ctx->i32, "");
5798 }
5799 }
5800
5801 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5802 int i;
5803 for (i = 0; i < 4; i++) {
5804 ctx->gs_next_vertex[i] =
5805 lp_build_alloca(&ctx->gallivm,
5806 ctx->i32, "");
5807 }
5808 }
5809
5810 if (sel->force_correct_derivs_after_kill) {
5811 ctx->postponed_kill = lp_build_alloca_undef(&ctx->gallivm, ctx->i1, "");
5812 /* true = don't kill. */
5813 LLVMBuildStore(ctx->ac.builder, LLVMConstInt(ctx->i1, 1, 0),
5814 ctx->postponed_kill);
5815 }
5816
5817 if (sel->tokens) {
5818 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
5819 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
5820 return false;
5821 }
5822 } else {
5823 if (!si_nir_build_llvm(ctx, sel->nir)) {
5824 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
5825 return false;
5826 }
5827 }
5828
5829 si_llvm_build_ret(ctx, ctx->return_value);
5830 return true;
5831 }
5832
5833 /**
5834 * Compute the VS prolog key, which contains all the information needed to
5835 * build the VS prolog function, and set shader->info bits where needed.
5836 *
5837 * \param info Shader info of the vertex shader.
5838 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
5839 * \param prolog_key Key of the VS prolog
5840 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
5841 * \param key Output shader part key.
5842 */
5843 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
5844 unsigned num_input_sgprs,
5845 const struct si_vs_prolog_bits *prolog_key,
5846 struct si_shader *shader_out,
5847 union si_shader_part_key *key)
5848 {
5849 memset(key, 0, sizeof(*key));
5850 key->vs_prolog.states = *prolog_key;
5851 key->vs_prolog.num_input_sgprs = num_input_sgprs;
5852 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
5853 key->vs_prolog.as_ls = shader_out->key.as_ls;
5854 key->vs_prolog.as_es = shader_out->key.as_es;
5855
5856 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
5857 key->vs_prolog.as_ls = 1;
5858 key->vs_prolog.num_merged_next_stage_vgprs = 2;
5859 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
5860 key->vs_prolog.as_es = 1;
5861 key->vs_prolog.num_merged_next_stage_vgprs = 5;
5862 }
5863
5864 /* Enable loading the InstanceID VGPR. */
5865 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
5866
5867 if ((key->vs_prolog.states.instance_divisor_is_one |
5868 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
5869 shader_out->info.uses_instanceid = true;
5870 }
5871
5872 /**
5873 * Compute the PS prolog key, which contains all the information needed to
5874 * build the PS prolog function, and set related bits in shader->config.
5875 */
5876 static void si_get_ps_prolog_key(struct si_shader *shader,
5877 union si_shader_part_key *key,
5878 bool separate_prolog)
5879 {
5880 struct tgsi_shader_info *info = &shader->selector->info;
5881
5882 memset(key, 0, sizeof(*key));
5883 key->ps_prolog.states = shader->key.part.ps.prolog;
5884 key->ps_prolog.colors_read = info->colors_read;
5885 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
5886 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
5887 key->ps_prolog.wqm = info->uses_derivatives &&
5888 (key->ps_prolog.colors_read ||
5889 key->ps_prolog.states.force_persp_sample_interp ||
5890 key->ps_prolog.states.force_linear_sample_interp ||
5891 key->ps_prolog.states.force_persp_center_interp ||
5892 key->ps_prolog.states.force_linear_center_interp ||
5893 key->ps_prolog.states.bc_optimize_for_persp ||
5894 key->ps_prolog.states.bc_optimize_for_linear);
5895 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
5896
5897 if (info->colors_read) {
5898 unsigned *color = shader->selector->color_attr_index;
5899
5900 if (shader->key.part.ps.prolog.color_two_side) {
5901 /* BCOLORs are stored after the last input. */
5902 key->ps_prolog.num_interp_inputs = info->num_inputs;
5903 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
5904 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
5905 }
5906
5907 for (unsigned i = 0; i < 2; i++) {
5908 unsigned interp = info->input_interpolate[color[i]];
5909 unsigned location = info->input_interpolate_loc[color[i]];
5910
5911 if (!(info->colors_read & (0xf << i*4)))
5912 continue;
5913
5914 key->ps_prolog.color_attr_index[i] = color[i];
5915
5916 if (shader->key.part.ps.prolog.flatshade_colors &&
5917 interp == TGSI_INTERPOLATE_COLOR)
5918 interp = TGSI_INTERPOLATE_CONSTANT;
5919
5920 switch (interp) {
5921 case TGSI_INTERPOLATE_CONSTANT:
5922 key->ps_prolog.color_interp_vgpr_index[i] = -1;
5923 break;
5924 case TGSI_INTERPOLATE_PERSPECTIVE:
5925 case TGSI_INTERPOLATE_COLOR:
5926 /* Force the interpolation location for colors here. */
5927 if (shader->key.part.ps.prolog.force_persp_sample_interp)
5928 location = TGSI_INTERPOLATE_LOC_SAMPLE;
5929 if (shader->key.part.ps.prolog.force_persp_center_interp)
5930 location = TGSI_INTERPOLATE_LOC_CENTER;
5931
5932 switch (location) {
5933 case TGSI_INTERPOLATE_LOC_SAMPLE:
5934 key->ps_prolog.color_interp_vgpr_index[i] = 0;
5935 shader->config.spi_ps_input_ena |=
5936 S_0286CC_PERSP_SAMPLE_ENA(1);
5937 break;
5938 case TGSI_INTERPOLATE_LOC_CENTER:
5939 key->ps_prolog.color_interp_vgpr_index[i] = 2;
5940 shader->config.spi_ps_input_ena |=
5941 S_0286CC_PERSP_CENTER_ENA(1);
5942 break;
5943 case TGSI_INTERPOLATE_LOC_CENTROID:
5944 key->ps_prolog.color_interp_vgpr_index[i] = 4;
5945 shader->config.spi_ps_input_ena |=
5946 S_0286CC_PERSP_CENTROID_ENA(1);
5947 break;
5948 default:
5949 assert(0);
5950 }
5951 break;
5952 case TGSI_INTERPOLATE_LINEAR:
5953 /* Force the interpolation location for colors here. */
5954 if (shader->key.part.ps.prolog.force_linear_sample_interp)
5955 location = TGSI_INTERPOLATE_LOC_SAMPLE;
5956 if (shader->key.part.ps.prolog.force_linear_center_interp)
5957 location = TGSI_INTERPOLATE_LOC_CENTER;
5958
5959 /* The VGPR assignment for non-monolithic shaders
5960 * works because InitialPSInputAddr is set on the
5961 * main shader and PERSP_PULL_MODEL is never used.
5962 */
5963 switch (location) {
5964 case TGSI_INTERPOLATE_LOC_SAMPLE:
5965 key->ps_prolog.color_interp_vgpr_index[i] =
5966 separate_prolog ? 6 : 9;
5967 shader->config.spi_ps_input_ena |=
5968 S_0286CC_LINEAR_SAMPLE_ENA(1);
5969 break;
5970 case TGSI_INTERPOLATE_LOC_CENTER:
5971 key->ps_prolog.color_interp_vgpr_index[i] =
5972 separate_prolog ? 8 : 11;
5973 shader->config.spi_ps_input_ena |=
5974 S_0286CC_LINEAR_CENTER_ENA(1);
5975 break;
5976 case TGSI_INTERPOLATE_LOC_CENTROID:
5977 key->ps_prolog.color_interp_vgpr_index[i] =
5978 separate_prolog ? 10 : 13;
5979 shader->config.spi_ps_input_ena |=
5980 S_0286CC_LINEAR_CENTROID_ENA(1);
5981 break;
5982 default:
5983 assert(0);
5984 }
5985 break;
5986 default:
5987 assert(0);
5988 }
5989 }
5990 }
5991 }
5992
5993 /**
5994 * Check whether a PS prolog is required based on the key.
5995 */
5996 static bool si_need_ps_prolog(const union si_shader_part_key *key)
5997 {
5998 return key->ps_prolog.colors_read ||
5999 key->ps_prolog.states.force_persp_sample_interp ||
6000 key->ps_prolog.states.force_linear_sample_interp ||
6001 key->ps_prolog.states.force_persp_center_interp ||
6002 key->ps_prolog.states.force_linear_center_interp ||
6003 key->ps_prolog.states.bc_optimize_for_persp ||
6004 key->ps_prolog.states.bc_optimize_for_linear ||
6005 key->ps_prolog.states.poly_stipple ||
6006 key->ps_prolog.states.samplemask_log_ps_iter;
6007 }
6008
6009 /**
6010 * Compute the PS epilog key, which contains all the information needed to
6011 * build the PS epilog function.
6012 */
6013 static void si_get_ps_epilog_key(struct si_shader *shader,
6014 union si_shader_part_key *key)
6015 {
6016 struct tgsi_shader_info *info = &shader->selector->info;
6017 memset(key, 0, sizeof(*key));
6018 key->ps_epilog.colors_written = info->colors_written;
6019 key->ps_epilog.writes_z = info->writes_z;
6020 key->ps_epilog.writes_stencil = info->writes_stencil;
6021 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6022 key->ps_epilog.states = shader->key.part.ps.epilog;
6023 }
6024
6025 /**
6026 * Build the GS prolog function. Rotate the input vertices for triangle strips
6027 * with adjacency.
6028 */
6029 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6030 union si_shader_part_key *key)
6031 {
6032 unsigned num_sgprs, num_vgprs;
6033 struct si_function_info fninfo;
6034 LLVMBuilderRef builder = ctx->ac.builder;
6035 LLVMTypeRef returns[48];
6036 LLVMValueRef func, ret;
6037
6038 si_init_function_info(&fninfo);
6039
6040 if (ctx->screen->info.chip_class >= GFX9) {
6041 num_sgprs = 8 + GFX9_GS_NUM_USER_SGPR;
6042 num_vgprs = 5; /* ES inputs are not needed by GS */
6043 } else {
6044 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6045 num_vgprs = 8;
6046 }
6047
6048 for (unsigned i = 0; i < num_sgprs; ++i) {
6049 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6050 returns[i] = ctx->i32;
6051 }
6052
6053 for (unsigned i = 0; i < num_vgprs; ++i) {
6054 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6055 returns[num_sgprs + i] = ctx->f32;
6056 }
6057
6058 /* Create the function. */
6059 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6060 &fninfo, 0);
6061 func = ctx->main_fn;
6062
6063 /* Set the full EXEC mask for the prolog, because we are only fiddling
6064 * with registers here. The main shader part will set the correct EXEC
6065 * mask.
6066 */
6067 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6068 ac_init_exec_full_mask(&ctx->ac);
6069
6070 /* Copy inputs to outputs. This should be no-op, as the registers match,
6071 * but it will prevent the compiler from overwriting them unintentionally.
6072 */
6073 ret = ctx->return_value;
6074 for (unsigned i = 0; i < num_sgprs; i++) {
6075 LLVMValueRef p = LLVMGetParam(func, i);
6076 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6077 }
6078 for (unsigned i = 0; i < num_vgprs; i++) {
6079 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6080 p = ac_to_float(&ctx->ac, p);
6081 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6082 }
6083
6084 if (key->gs_prolog.states.tri_strip_adj_fix) {
6085 /* Remap the input vertices for every other primitive. */
6086 const unsigned gfx6_vtx_params[6] = {
6087 num_sgprs,
6088 num_sgprs + 1,
6089 num_sgprs + 3,
6090 num_sgprs + 4,
6091 num_sgprs + 5,
6092 num_sgprs + 6
6093 };
6094 const unsigned gfx9_vtx_params[3] = {
6095 num_sgprs,
6096 num_sgprs + 1,
6097 num_sgprs + 4,
6098 };
6099 LLVMValueRef vtx_in[6], vtx_out[6];
6100 LLVMValueRef prim_id, rotate;
6101
6102 if (ctx->screen->info.chip_class >= GFX9) {
6103 for (unsigned i = 0; i < 3; i++) {
6104 vtx_in[i*2] = unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6105 vtx_in[i*2+1] = unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6106 }
6107 } else {
6108 for (unsigned i = 0; i < 6; i++)
6109 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6110 }
6111
6112 prim_id = LLVMGetParam(func, num_sgprs + 2);
6113 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6114
6115 for (unsigned i = 0; i < 6; ++i) {
6116 LLVMValueRef base, rotated;
6117 base = vtx_in[i];
6118 rotated = vtx_in[(i + 4) % 6];
6119 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6120 }
6121
6122 if (ctx->screen->info.chip_class >= GFX9) {
6123 for (unsigned i = 0; i < 3; i++) {
6124 LLVMValueRef hi, out;
6125
6126 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6127 LLVMConstInt(ctx->i32, 16, 0), "");
6128 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6129 out = ac_to_float(&ctx->ac, out);
6130 ret = LLVMBuildInsertValue(builder, ret, out,
6131 gfx9_vtx_params[i], "");
6132 }
6133 } else {
6134 for (unsigned i = 0; i < 6; i++) {
6135 LLVMValueRef out;
6136
6137 out = ac_to_float(&ctx->ac, vtx_out[i]);
6138 ret = LLVMBuildInsertValue(builder, ret, out,
6139 gfx6_vtx_params[i], "");
6140 }
6141 }
6142 }
6143
6144 LLVMBuildRet(builder, ret);
6145 }
6146
6147 /**
6148 * Given a list of shader part functions, build a wrapper function that
6149 * runs them in sequence to form a monolithic shader.
6150 */
6151 static void si_build_wrapper_function(struct si_shader_context *ctx,
6152 LLVMValueRef *parts,
6153 unsigned num_parts,
6154 unsigned main_part,
6155 unsigned next_shader_first_part)
6156 {
6157 LLVMBuilderRef builder = ctx->ac.builder;
6158 /* PS epilog has one arg per color component; gfx9 merged shader
6159 * prologs need to forward 32 user SGPRs.
6160 */
6161 struct si_function_info fninfo;
6162 LLVMValueRef initial[64], out[64];
6163 LLVMTypeRef function_type;
6164 unsigned num_first_params;
6165 unsigned num_out, initial_num_out;
6166 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6167 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6168 unsigned num_sgprs, num_vgprs;
6169 unsigned gprs;
6170 struct lp_build_if_state if_state;
6171
6172 si_init_function_info(&fninfo);
6173
6174 for (unsigned i = 0; i < num_parts; ++i) {
6175 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6176 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6177 }
6178
6179 /* The parameters of the wrapper function correspond to those of the
6180 * first part in terms of SGPRs and VGPRs, but we use the types of the
6181 * main part to get the right types. This is relevant for the
6182 * dereferenceable attribute on descriptor table pointers.
6183 */
6184 num_sgprs = 0;
6185 num_vgprs = 0;
6186
6187 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6188 num_first_params = LLVMCountParamTypes(function_type);
6189
6190 for (unsigned i = 0; i < num_first_params; ++i) {
6191 LLVMValueRef param = LLVMGetParam(parts[0], i);
6192
6193 if (ac_is_sgpr_param(param)) {
6194 assert(num_vgprs == 0);
6195 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6196 } else {
6197 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6198 }
6199 }
6200
6201 gprs = 0;
6202 while (gprs < num_sgprs + num_vgprs) {
6203 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6204 LLVMTypeRef type = LLVMTypeOf(param);
6205 unsigned size = ac_get_type_size(type) / 4;
6206
6207 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6208
6209 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6210 assert(gprs + size <= num_sgprs + num_vgprs &&
6211 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6212
6213 gprs += size;
6214 }
6215
6216 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6217 si_get_max_workgroup_size(ctx->shader));
6218
6219 if (is_merged_shader(ctx->shader))
6220 ac_init_exec_full_mask(&ctx->ac);
6221
6222 /* Record the arguments of the function as if they were an output of
6223 * a previous part.
6224 */
6225 num_out = 0;
6226 num_out_sgpr = 0;
6227
6228 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6229 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6230 LLVMTypeRef param_type = LLVMTypeOf(param);
6231 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6232 unsigned size = ac_get_type_size(param_type) / 4;
6233
6234 if (size == 1) {
6235 if (param_type != out_type)
6236 param = LLVMBuildBitCast(builder, param, out_type, "");
6237 out[num_out++] = param;
6238 } else {
6239 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6240
6241 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6242 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6243 param_type = ctx->i64;
6244 }
6245
6246 if (param_type != vector_type)
6247 param = LLVMBuildBitCast(builder, param, vector_type, "");
6248
6249 for (unsigned j = 0; j < size; ++j)
6250 out[num_out++] = LLVMBuildExtractElement(
6251 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6252 }
6253
6254 if (i < fninfo.num_sgpr_params)
6255 num_out_sgpr = num_out;
6256 }
6257
6258 memcpy(initial, out, sizeof(out));
6259 initial_num_out = num_out;
6260 initial_num_out_sgpr = num_out_sgpr;
6261
6262 /* Now chain the parts. */
6263 for (unsigned part = 0; part < num_parts; ++part) {
6264 LLVMValueRef in[48];
6265 LLVMValueRef ret;
6266 LLVMTypeRef ret_type;
6267 unsigned out_idx = 0;
6268 unsigned num_params = LLVMCountParams(parts[part]);
6269
6270 /* Merged shaders are executed conditionally depending
6271 * on the number of enabled threads passed in the input SGPRs. */
6272 if (is_merged_shader(ctx->shader) && part == 0) {
6273 LLVMValueRef ena, count = initial[3];
6274
6275 count = LLVMBuildAnd(builder, count,
6276 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6277 ena = LLVMBuildICmp(builder, LLVMIntULT,
6278 ac_get_thread_id(&ctx->ac), count, "");
6279 lp_build_if(&if_state, &ctx->gallivm, ena);
6280 }
6281
6282 /* Derive arguments for the next part from outputs of the
6283 * previous one.
6284 */
6285 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6286 LLVMValueRef param;
6287 LLVMTypeRef param_type;
6288 bool is_sgpr;
6289 unsigned param_size;
6290 LLVMValueRef arg = NULL;
6291
6292 param = LLVMGetParam(parts[part], param_idx);
6293 param_type = LLVMTypeOf(param);
6294 param_size = ac_get_type_size(param_type) / 4;
6295 is_sgpr = ac_is_sgpr_param(param);
6296
6297 if (is_sgpr) {
6298 #if HAVE_LLVM < 0x0400
6299 LLVMRemoveAttribute(param, LLVMByValAttribute);
6300 #else
6301 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
6302 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
6303 #endif
6304 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
6305 }
6306
6307 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6308 assert(is_sgpr || out_idx >= num_out_sgpr);
6309
6310 if (param_size == 1)
6311 arg = out[out_idx];
6312 else
6313 arg = lp_build_gather_values(&ctx->gallivm, &out[out_idx], param_size);
6314
6315 if (LLVMTypeOf(arg) != param_type) {
6316 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6317 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6318 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6319 } else {
6320 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6321 }
6322 }
6323
6324 in[param_idx] = arg;
6325 out_idx += param_size;
6326 }
6327
6328 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6329
6330 if (is_merged_shader(ctx->shader) &&
6331 part + 1 == next_shader_first_part) {
6332 lp_build_endif(&if_state);
6333
6334 /* The second half of the merged shader should use
6335 * the inputs from the toplevel (wrapper) function,
6336 * not the return value from the last call.
6337 *
6338 * That's because the last call was executed condi-
6339 * tionally, so we can't consume it in the main
6340 * block.
6341 */
6342 memcpy(out, initial, sizeof(initial));
6343 num_out = initial_num_out;
6344 num_out_sgpr = initial_num_out_sgpr;
6345 continue;
6346 }
6347
6348 /* Extract the returned GPRs. */
6349 ret_type = LLVMTypeOf(ret);
6350 num_out = 0;
6351 num_out_sgpr = 0;
6352
6353 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6354 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6355
6356 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6357
6358 for (unsigned i = 0; i < ret_size; ++i) {
6359 LLVMValueRef val =
6360 LLVMBuildExtractValue(builder, ret, i, "");
6361
6362 assert(num_out < ARRAY_SIZE(out));
6363 out[num_out++] = val;
6364
6365 if (LLVMTypeOf(val) == ctx->i32) {
6366 assert(num_out_sgpr + 1 == num_out);
6367 num_out_sgpr = num_out;
6368 }
6369 }
6370 }
6371 }
6372
6373 LLVMBuildRetVoid(builder);
6374 }
6375
6376 int si_compile_tgsi_shader(struct si_screen *sscreen,
6377 LLVMTargetMachineRef tm,
6378 struct si_shader *shader,
6379 bool is_monolithic,
6380 struct pipe_debug_callback *debug)
6381 {
6382 struct si_shader_selector *sel = shader->selector;
6383 struct si_shader_context ctx;
6384 int r = -1;
6385
6386 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6387 * conversion fails. */
6388 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6389 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6390 if (sel->tokens)
6391 tgsi_dump(sel->tokens, 0);
6392 else
6393 nir_print_shader(sel->nir, stderr);
6394 si_dump_streamout(&sel->so);
6395 }
6396
6397 si_init_shader_ctx(&ctx, sscreen, tm);
6398 si_llvm_context_set_tgsi(&ctx, shader);
6399 ctx.separate_prolog = !is_monolithic;
6400
6401 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6402 sizeof(shader->info.vs_output_param_offset));
6403
6404 shader->info.uses_instanceid = sel->info.uses_instanceid;
6405
6406 if (!si_compile_tgsi_main(&ctx, is_monolithic)) {
6407 si_llvm_dispose(&ctx);
6408 return -1;
6409 }
6410
6411 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6412 LLVMValueRef parts[2];
6413 bool need_prolog = sel->vs_needs_prolog;
6414
6415 parts[1] = ctx.main_fn;
6416
6417 if (need_prolog) {
6418 union si_shader_part_key prolog_key;
6419 si_get_vs_prolog_key(&sel->info,
6420 shader->info.num_input_sgprs,
6421 &shader->key.part.vs.prolog,
6422 shader, &prolog_key);
6423 si_build_vs_prolog_function(&ctx, &prolog_key);
6424 parts[0] = ctx.main_fn;
6425 }
6426
6427 si_build_wrapper_function(&ctx, parts + !need_prolog,
6428 1 + need_prolog, need_prolog, 0);
6429 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6430 if (sscreen->info.chip_class >= GFX9) {
6431 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6432 LLVMValueRef parts[4];
6433 bool vs_needs_prolog =
6434 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6435
6436 /* TCS main part */
6437 parts[2] = ctx.main_fn;
6438
6439 /* TCS epilog */
6440 union si_shader_part_key tcs_epilog_key;
6441 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6442 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6443 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6444 parts[3] = ctx.main_fn;
6445
6446 /* VS prolog */
6447 if (vs_needs_prolog) {
6448 union si_shader_part_key vs_prolog_key;
6449 si_get_vs_prolog_key(&ls->info,
6450 shader->info.num_input_sgprs,
6451 &shader->key.part.tcs.ls_prolog,
6452 shader, &vs_prolog_key);
6453 vs_prolog_key.vs_prolog.is_monolithic = true;
6454 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6455 parts[0] = ctx.main_fn;
6456 }
6457
6458 /* VS as LS main part */
6459 struct si_shader shader_ls = {};
6460 shader_ls.selector = ls;
6461 shader_ls.key.as_ls = 1;
6462 shader_ls.key.mono = shader->key.mono;
6463 shader_ls.key.opt = shader->key.opt;
6464 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6465
6466 if (!si_compile_tgsi_main(&ctx, true)) {
6467 si_llvm_dispose(&ctx);
6468 return -1;
6469 }
6470 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6471 parts[1] = ctx.main_fn;
6472
6473 /* Reset the shader context. */
6474 ctx.shader = shader;
6475 ctx.type = PIPE_SHADER_TESS_CTRL;
6476
6477 si_build_wrapper_function(&ctx,
6478 parts + !vs_needs_prolog,
6479 4 - !vs_needs_prolog, 0,
6480 vs_needs_prolog ? 2 : 1);
6481 } else {
6482 LLVMValueRef parts[2];
6483 union si_shader_part_key epilog_key;
6484
6485 parts[0] = ctx.main_fn;
6486
6487 memset(&epilog_key, 0, sizeof(epilog_key));
6488 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6489 si_build_tcs_epilog_function(&ctx, &epilog_key);
6490 parts[1] = ctx.main_fn;
6491
6492 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6493 }
6494 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6495 if (ctx.screen->info.chip_class >= GFX9) {
6496 struct si_shader_selector *es = shader->key.part.gs.es;
6497 LLVMValueRef es_prolog = NULL;
6498 LLVMValueRef es_main = NULL;
6499 LLVMValueRef gs_prolog = NULL;
6500 LLVMValueRef gs_main = ctx.main_fn;
6501
6502 /* GS prolog */
6503 union si_shader_part_key gs_prolog_key;
6504 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6505 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6506 gs_prolog_key.gs_prolog.is_monolithic = true;
6507 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6508 gs_prolog = ctx.main_fn;
6509
6510 /* ES prolog */
6511 if (es->vs_needs_prolog) {
6512 union si_shader_part_key vs_prolog_key;
6513 si_get_vs_prolog_key(&es->info,
6514 shader->info.num_input_sgprs,
6515 &shader->key.part.gs.vs_prolog,
6516 shader, &vs_prolog_key);
6517 vs_prolog_key.vs_prolog.is_monolithic = true;
6518 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6519 es_prolog = ctx.main_fn;
6520 }
6521
6522 /* ES main part */
6523 struct si_shader shader_es = {};
6524 shader_es.selector = es;
6525 shader_es.key.as_es = 1;
6526 shader_es.key.mono = shader->key.mono;
6527 shader_es.key.opt = shader->key.opt;
6528 si_llvm_context_set_tgsi(&ctx, &shader_es);
6529
6530 if (!si_compile_tgsi_main(&ctx, true)) {
6531 si_llvm_dispose(&ctx);
6532 return -1;
6533 }
6534 shader->info.uses_instanceid |= es->info.uses_instanceid;
6535 es_main = ctx.main_fn;
6536
6537 /* Reset the shader context. */
6538 ctx.shader = shader;
6539 ctx.type = PIPE_SHADER_GEOMETRY;
6540
6541 /* Prepare the array of shader parts. */
6542 LLVMValueRef parts[4];
6543 unsigned num_parts = 0, main_part, next_first_part;
6544
6545 if (es_prolog)
6546 parts[num_parts++] = es_prolog;
6547
6548 parts[main_part = num_parts++] = es_main;
6549 parts[next_first_part = num_parts++] = gs_prolog;
6550 parts[num_parts++] = gs_main;
6551
6552 si_build_wrapper_function(&ctx, parts, num_parts,
6553 main_part, next_first_part);
6554 } else {
6555 LLVMValueRef parts[2];
6556 union si_shader_part_key prolog_key;
6557
6558 parts[1] = ctx.main_fn;
6559
6560 memset(&prolog_key, 0, sizeof(prolog_key));
6561 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6562 si_build_gs_prolog_function(&ctx, &prolog_key);
6563 parts[0] = ctx.main_fn;
6564
6565 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6566 }
6567 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6568 LLVMValueRef parts[3];
6569 union si_shader_part_key prolog_key;
6570 union si_shader_part_key epilog_key;
6571 bool need_prolog;
6572
6573 si_get_ps_prolog_key(shader, &prolog_key, false);
6574 need_prolog = si_need_ps_prolog(&prolog_key);
6575
6576 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6577
6578 if (need_prolog) {
6579 si_build_ps_prolog_function(&ctx, &prolog_key);
6580 parts[0] = ctx.main_fn;
6581 }
6582
6583 si_get_ps_epilog_key(shader, &epilog_key);
6584 si_build_ps_epilog_function(&ctx, &epilog_key);
6585 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6586
6587 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6588 need_prolog ? 1 : 0, 0);
6589 }
6590
6591 si_llvm_optimize_module(&ctx);
6592
6593 /* Post-optimization transformations and analysis. */
6594 si_optimize_vs_outputs(&ctx);
6595
6596 if ((debug && debug->debug_message) ||
6597 si_can_dump_shader(sscreen, ctx.type))
6598 si_count_scratch_private_memory(&ctx);
6599
6600 /* Compile to bytecode. */
6601 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6602 ctx.gallivm.module, debug, ctx.type, "TGSI shader");
6603 si_llvm_dispose(&ctx);
6604 if (r) {
6605 fprintf(stderr, "LLVM failed to compile shader\n");
6606 return r;
6607 }
6608
6609 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6610 * LLVM 3.9svn has this bug.
6611 */
6612 if (sel->type == PIPE_SHADER_COMPUTE) {
6613 unsigned wave_size = 64;
6614 unsigned max_vgprs = 256;
6615 unsigned max_sgprs = sscreen->info.chip_class >= VI ? 800 : 512;
6616 unsigned max_sgprs_per_wave = 128;
6617 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6618 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6619 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6620
6621 max_vgprs = max_vgprs / min_waves_per_simd;
6622 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6623
6624 if (shader->config.num_sgprs > max_sgprs ||
6625 shader->config.num_vgprs > max_vgprs) {
6626 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6627 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6628 shader->config.num_sgprs, shader->config.num_vgprs,
6629 max_sgprs, max_vgprs);
6630
6631 /* Just terminate the process, because dependent
6632 * shaders can hang due to bad input data, but use
6633 * the env var to allow shader-db to work.
6634 */
6635 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6636 abort();
6637 }
6638 }
6639
6640 /* Add the scratch offset to input SGPRs. */
6641 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(shader))
6642 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6643
6644 /* Calculate the number of fragment input VGPRs. */
6645 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6646 shader->info.num_input_vgprs = 0;
6647 shader->info.face_vgpr_index = -1;
6648 shader->info.ancillary_vgpr_index = -1;
6649
6650 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6651 shader->info.num_input_vgprs += 2;
6652 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6653 shader->info.num_input_vgprs += 2;
6654 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6655 shader->info.num_input_vgprs += 2;
6656 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6657 shader->info.num_input_vgprs += 3;
6658 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6659 shader->info.num_input_vgprs += 2;
6660 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6661 shader->info.num_input_vgprs += 2;
6662 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6663 shader->info.num_input_vgprs += 2;
6664 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6665 shader->info.num_input_vgprs += 1;
6666 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6667 shader->info.num_input_vgprs += 1;
6668 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6669 shader->info.num_input_vgprs += 1;
6670 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6671 shader->info.num_input_vgprs += 1;
6672 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6673 shader->info.num_input_vgprs += 1;
6674 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6675 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6676 shader->info.num_input_vgprs += 1;
6677 }
6678 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
6679 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
6680 shader->info.num_input_vgprs += 1;
6681 }
6682 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6683 shader->info.num_input_vgprs += 1;
6684 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6685 shader->info.num_input_vgprs += 1;
6686 }
6687
6688 return 0;
6689 }
6690
6691 /**
6692 * Create, compile and return a shader part (prolog or epilog).
6693 *
6694 * \param sscreen screen
6695 * \param list list of shader parts of the same category
6696 * \param type shader type
6697 * \param key shader part key
6698 * \param prolog whether the part being requested is a prolog
6699 * \param tm LLVM target machine
6700 * \param debug debug callback
6701 * \param build the callback responsible for building the main function
6702 * \return non-NULL on success
6703 */
6704 static struct si_shader_part *
6705 si_get_shader_part(struct si_screen *sscreen,
6706 struct si_shader_part **list,
6707 enum pipe_shader_type type,
6708 bool prolog,
6709 union si_shader_part_key *key,
6710 LLVMTargetMachineRef tm,
6711 struct pipe_debug_callback *debug,
6712 void (*build)(struct si_shader_context *,
6713 union si_shader_part_key *),
6714 const char *name)
6715 {
6716 struct si_shader_part *result;
6717
6718 mtx_lock(&sscreen->shader_parts_mutex);
6719
6720 /* Find existing. */
6721 for (result = *list; result; result = result->next) {
6722 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6723 mtx_unlock(&sscreen->shader_parts_mutex);
6724 return result;
6725 }
6726 }
6727
6728 /* Compile a new one. */
6729 result = CALLOC_STRUCT(si_shader_part);
6730 result->key = *key;
6731
6732 struct si_shader shader = {};
6733 struct si_shader_context ctx;
6734
6735 si_init_shader_ctx(&ctx, sscreen, tm);
6736 ctx.shader = &shader;
6737 ctx.type = type;
6738
6739 switch (type) {
6740 case PIPE_SHADER_VERTEX:
6741 shader.key.as_ls = key->vs_prolog.as_ls;
6742 shader.key.as_es = key->vs_prolog.as_es;
6743 break;
6744 case PIPE_SHADER_TESS_CTRL:
6745 assert(!prolog);
6746 shader.key.part.tcs.epilog = key->tcs_epilog.states;
6747 break;
6748 case PIPE_SHADER_GEOMETRY:
6749 assert(prolog);
6750 break;
6751 case PIPE_SHADER_FRAGMENT:
6752 if (prolog)
6753 shader.key.part.ps.prolog = key->ps_prolog.states;
6754 else
6755 shader.key.part.ps.epilog = key->ps_epilog.states;
6756 break;
6757 default:
6758 unreachable("bad shader part");
6759 }
6760
6761 build(&ctx, key);
6762
6763 /* Compile. */
6764 si_llvm_optimize_module(&ctx);
6765
6766 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
6767 ctx.ac.module, debug, ctx.type, name)) {
6768 FREE(result);
6769 result = NULL;
6770 goto out;
6771 }
6772
6773 result->next = *list;
6774 *list = result;
6775
6776 out:
6777 si_llvm_dispose(&ctx);
6778 mtx_unlock(&sscreen->shader_parts_mutex);
6779 return result;
6780 }
6781
6782 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
6783 {
6784 LLVMValueRef ptr[2], list;
6785 bool is_merged_shader =
6786 ctx->screen->info.chip_class >= GFX9 &&
6787 (ctx->type == PIPE_SHADER_TESS_CTRL ||
6788 ctx->type == PIPE_SHADER_GEOMETRY ||
6789 ctx->shader->key.as_ls || ctx->shader->key.as_es);
6790
6791 /* Get the pointer to rw buffers. */
6792 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
6793 ptr[1] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS_HI);
6794 list = lp_build_gather_values(&ctx->gallivm, ptr, 2);
6795 list = LLVMBuildBitCast(ctx->ac.builder, list, ctx->i64, "");
6796 list = LLVMBuildIntToPtr(ctx->ac.builder, list,
6797 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS), "");
6798 return list;
6799 }
6800
6801 /**
6802 * Build the vertex shader prolog function.
6803 *
6804 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6805 * All inputs are returned unmodified. The vertex load indices are
6806 * stored after them, which will be used by the API VS for fetching inputs.
6807 *
6808 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6809 * input_v0,
6810 * input_v1,
6811 * input_v2,
6812 * input_v3,
6813 * (VertexID + BaseVertex),
6814 * (InstanceID + StartInstance),
6815 * (InstanceID / 2 + StartInstance)
6816 */
6817 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
6818 union si_shader_part_key *key)
6819 {
6820 struct si_function_info fninfo;
6821 LLVMTypeRef *returns;
6822 LLVMValueRef ret, func;
6823 int num_returns, i;
6824 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
6825 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
6826 LLVMValueRef input_vgprs[9];
6827 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
6828 num_input_vgprs;
6829 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
6830
6831 si_init_function_info(&fninfo);
6832
6833 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6834 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
6835 sizeof(LLVMTypeRef));
6836 num_returns = 0;
6837
6838 /* Declare input and output SGPRs. */
6839 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6840 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6841 returns[num_returns++] = ctx->i32;
6842 }
6843
6844 /* Preloaded VGPRs (outputs must be floats) */
6845 for (i = 0; i < num_input_vgprs; i++) {
6846 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
6847 returns[num_returns++] = ctx->f32;
6848 }
6849
6850 /* Vertex load indices. */
6851 for (i = 0; i <= key->vs_prolog.last_input; i++)
6852 returns[num_returns++] = ctx->f32;
6853
6854 /* Create the function. */
6855 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
6856 func = ctx->main_fn;
6857
6858 if (key->vs_prolog.num_merged_next_stage_vgprs) {
6859 if (!key->vs_prolog.is_monolithic)
6860 si_init_exec_from_input(ctx, 3, 0);
6861
6862 if (key->vs_prolog.as_ls &&
6863 ctx->screen->has_ls_vgpr_init_bug) {
6864 /* If there are no HS threads, SPI loads the LS VGPRs
6865 * starting at VGPR 0. Shift them back to where they
6866 * belong.
6867 */
6868 LLVMValueRef has_hs_threads =
6869 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
6870 unpack_param(ctx, 3, 8, 8),
6871 ctx->i32_0, "");
6872
6873 for (i = 4; i > 0; --i) {
6874 input_vgprs[i + 1] =
6875 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
6876 input_vgprs[i + 1],
6877 input_vgprs[i - 1], "");
6878 }
6879 }
6880 }
6881
6882 ctx->abi.vertex_id = input_vgprs[first_vs_vgpr];
6883 ctx->abi.instance_id = input_vgprs[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)];
6884
6885 /* Copy inputs to outputs. This should be no-op, as the registers match,
6886 * but it will prevent the compiler from overwriting them unintentionally.
6887 */
6888 ret = ctx->return_value;
6889 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6890 LLVMValueRef p = LLVMGetParam(func, i);
6891 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
6892 }
6893 for (i = 0; i < num_input_vgprs; i++) {
6894 LLVMValueRef p = input_vgprs[i];
6895 p = ac_to_float(&ctx->ac, p);
6896 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
6897 key->vs_prolog.num_input_sgprs + i, "");
6898 }
6899
6900 /* Compute vertex load indices from instance divisors. */
6901 LLVMValueRef instance_divisor_constbuf = NULL;
6902
6903 if (key->vs_prolog.states.instance_divisor_is_fetched) {
6904 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
6905 LLVMValueRef buf_index =
6906 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
6907 instance_divisor_constbuf =
6908 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
6909 }
6910
6911 for (i = 0; i <= key->vs_prolog.last_input; i++) {
6912 bool divisor_is_one =
6913 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
6914 bool divisor_is_fetched =
6915 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
6916 LLVMValueRef index;
6917
6918 if (divisor_is_one || divisor_is_fetched) {
6919 LLVMValueRef divisor = ctx->i32_1;
6920
6921 if (divisor_is_fetched) {
6922 divisor = buffer_load_const(ctx, instance_divisor_constbuf,
6923 LLVMConstInt(ctx->i32, i * 4, 0));
6924 divisor = ac_to_integer(&ctx->ac, divisor);
6925 }
6926
6927 /* InstanceID / Divisor + StartInstance */
6928 index = get_instance_index_for_fetch(ctx,
6929 user_sgpr_base +
6930 SI_SGPR_START_INSTANCE,
6931 divisor);
6932 } else {
6933 /* VertexID + BaseVertex */
6934 index = LLVMBuildAdd(ctx->ac.builder,
6935 ctx->abi.vertex_id,
6936 LLVMGetParam(func, user_sgpr_base +
6937 SI_SGPR_BASE_VERTEX), "");
6938 }
6939
6940 index = ac_to_float(&ctx->ac, index);
6941 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
6942 fninfo.num_params + i, "");
6943 }
6944
6945 si_llvm_build_ret(ctx, ret);
6946 }
6947
6948 static bool si_get_vs_prolog(struct si_screen *sscreen,
6949 LLVMTargetMachineRef tm,
6950 struct si_shader *shader,
6951 struct pipe_debug_callback *debug,
6952 struct si_shader *main_part,
6953 const struct si_vs_prolog_bits *key)
6954 {
6955 struct si_shader_selector *vs = main_part->selector;
6956
6957 if (!si_vs_needs_prolog(vs, key))
6958 return true;
6959
6960 /* Get the prolog. */
6961 union si_shader_part_key prolog_key;
6962 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
6963 key, shader, &prolog_key);
6964
6965 shader->prolog =
6966 si_get_shader_part(sscreen, &sscreen->vs_prologs,
6967 PIPE_SHADER_VERTEX, true, &prolog_key, tm,
6968 debug, si_build_vs_prolog_function,
6969 "Vertex Shader Prolog");
6970 return shader->prolog != NULL;
6971 }
6972
6973 /**
6974 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
6975 */
6976 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
6977 LLVMTargetMachineRef tm,
6978 struct si_shader *shader,
6979 struct pipe_debug_callback *debug)
6980 {
6981 return si_get_vs_prolog(sscreen, tm, shader, debug, shader,
6982 &shader->key.part.vs.prolog);
6983 }
6984
6985 /**
6986 * Compile the TCS epilog function. This writes tesselation factors to memory
6987 * based on the output primitive type of the tesselator (determined by TES).
6988 */
6989 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
6990 union si_shader_part_key *key)
6991 {
6992 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6993 struct si_function_info fninfo;
6994 LLVMValueRef func;
6995
6996 si_init_function_info(&fninfo);
6997
6998 if (ctx->screen->info.chip_class >= GFX9) {
6999 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7000 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7001 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7002 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7003 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7004 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7005 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7006 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7007 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7008 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7009 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7010 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7011 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7012 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7013 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7014 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7015 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7016 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7017 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7018 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7019 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7020 } else {
7021 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7022 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7023 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7024 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7025 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7026 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7027 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7028 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7029 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7030 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7031 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7032 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7033 }
7034
7035 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7036 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7037 unsigned tess_factors_idx =
7038 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7039 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7040 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7041
7042 for (unsigned i = 0; i < 6; i++)
7043 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7044
7045 /* Create the function. */
7046 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7047 ctx->screen->info.chip_class >= CIK ? 128 : 64);
7048 ac_declare_lds_as_pointer(&ctx->ac);
7049 func = ctx->main_fn;
7050
7051 LLVMValueRef invoc0_tess_factors[6];
7052 for (unsigned i = 0; i < 6; i++)
7053 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7054
7055 si_write_tess_factors(bld_base,
7056 LLVMGetParam(func, tess_factors_idx),
7057 LLVMGetParam(func, tess_factors_idx + 1),
7058 LLVMGetParam(func, tess_factors_idx + 2),
7059 invoc0_tess_factors, invoc0_tess_factors + 4);
7060
7061 LLVMBuildRetVoid(ctx->ac.builder);
7062 }
7063
7064 /**
7065 * Select and compile (or reuse) TCS parts (epilog).
7066 */
7067 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7068 LLVMTargetMachineRef tm,
7069 struct si_shader *shader,
7070 struct pipe_debug_callback *debug)
7071 {
7072 if (sscreen->info.chip_class >= GFX9) {
7073 struct si_shader *ls_main_part =
7074 shader->key.part.tcs.ls->main_shader_part_ls;
7075
7076 if (!si_get_vs_prolog(sscreen, tm, shader, debug, ls_main_part,
7077 &shader->key.part.tcs.ls_prolog))
7078 return false;
7079
7080 shader->previous_stage = ls_main_part;
7081 }
7082
7083 /* Get the epilog. */
7084 union si_shader_part_key epilog_key;
7085 memset(&epilog_key, 0, sizeof(epilog_key));
7086 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7087
7088 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7089 PIPE_SHADER_TESS_CTRL, false,
7090 &epilog_key, tm, debug,
7091 si_build_tcs_epilog_function,
7092 "Tessellation Control Shader Epilog");
7093 return shader->epilog != NULL;
7094 }
7095
7096 /**
7097 * Select and compile (or reuse) GS parts (prolog).
7098 */
7099 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7100 LLVMTargetMachineRef tm,
7101 struct si_shader *shader,
7102 struct pipe_debug_callback *debug)
7103 {
7104 if (sscreen->info.chip_class >= GFX9) {
7105 struct si_shader *es_main_part =
7106 shader->key.part.gs.es->main_shader_part_es;
7107
7108 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7109 !si_get_vs_prolog(sscreen, tm, shader, debug, es_main_part,
7110 &shader->key.part.gs.vs_prolog))
7111 return false;
7112
7113 shader->previous_stage = es_main_part;
7114 }
7115
7116 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7117 return true;
7118
7119 union si_shader_part_key prolog_key;
7120 memset(&prolog_key, 0, sizeof(prolog_key));
7121 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7122
7123 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7124 PIPE_SHADER_GEOMETRY, true,
7125 &prolog_key, tm, debug,
7126 si_build_gs_prolog_function,
7127 "Geometry Shader Prolog");
7128 return shader->prolog2 != NULL;
7129 }
7130
7131 /**
7132 * Build the pixel shader prolog function. This handles:
7133 * - two-side color selection and interpolation
7134 * - overriding interpolation parameters for the API PS
7135 * - polygon stippling
7136 *
7137 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7138 * overriden by other states. (e.g. per-sample interpolation)
7139 * Interpolated colors are stored after the preloaded VGPRs.
7140 */
7141 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7142 union si_shader_part_key *key)
7143 {
7144 struct si_function_info fninfo;
7145 LLVMValueRef ret, func;
7146 int num_returns, i, num_color_channels;
7147
7148 assert(si_need_ps_prolog(key));
7149
7150 si_init_function_info(&fninfo);
7151
7152 /* Declare inputs. */
7153 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7154 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7155
7156 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7157 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7158
7159 /* Declare outputs (same as inputs + add colors if needed) */
7160 num_returns = fninfo.num_params;
7161 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7162 for (i = 0; i < num_color_channels; i++)
7163 fninfo.types[num_returns++] = ctx->f32;
7164
7165 /* Create the function. */
7166 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7167 &fninfo, 0);
7168 func = ctx->main_fn;
7169
7170 /* Copy inputs to outputs. This should be no-op, as the registers match,
7171 * but it will prevent the compiler from overwriting them unintentionally.
7172 */
7173 ret = ctx->return_value;
7174 for (i = 0; i < fninfo.num_params; i++) {
7175 LLVMValueRef p = LLVMGetParam(func, i);
7176 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7177 }
7178
7179 /* Polygon stippling. */
7180 if (key->ps_prolog.states.poly_stipple) {
7181 /* POS_FIXED_PT is always last. */
7182 unsigned pos = key->ps_prolog.num_input_sgprs +
7183 key->ps_prolog.num_input_vgprs - 1;
7184 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7185
7186 si_llvm_emit_polygon_stipple(ctx, list, pos);
7187 }
7188
7189 if (key->ps_prolog.states.bc_optimize_for_persp ||
7190 key->ps_prolog.states.bc_optimize_for_linear) {
7191 unsigned i, base = key->ps_prolog.num_input_sgprs;
7192 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7193
7194 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7195 * The hw doesn't compute CENTROID if the whole wave only
7196 * contains fully-covered quads.
7197 *
7198 * PRIM_MASK is after user SGPRs.
7199 */
7200 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7201 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7202 LLVMConstInt(ctx->i32, 31, 0), "");
7203 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7204 ctx->i1, "");
7205
7206 if (key->ps_prolog.states.bc_optimize_for_persp) {
7207 /* Read PERSP_CENTER. */
7208 for (i = 0; i < 2; i++)
7209 center[i] = LLVMGetParam(func, base + 2 + i);
7210 /* Read PERSP_CENTROID. */
7211 for (i = 0; i < 2; i++)
7212 centroid[i] = LLVMGetParam(func, base + 4 + i);
7213 /* Select PERSP_CENTROID. */
7214 for (i = 0; i < 2; i++) {
7215 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7216 center[i], centroid[i], "");
7217 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7218 tmp, base + 4 + i, "");
7219 }
7220 }
7221 if (key->ps_prolog.states.bc_optimize_for_linear) {
7222 /* Read LINEAR_CENTER. */
7223 for (i = 0; i < 2; i++)
7224 center[i] = LLVMGetParam(func, base + 8 + i);
7225 /* Read LINEAR_CENTROID. */
7226 for (i = 0; i < 2; i++)
7227 centroid[i] = LLVMGetParam(func, base + 10 + i);
7228 /* Select LINEAR_CENTROID. */
7229 for (i = 0; i < 2; i++) {
7230 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7231 center[i], centroid[i], "");
7232 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7233 tmp, base + 10 + i, "");
7234 }
7235 }
7236 }
7237
7238 /* Force per-sample interpolation. */
7239 if (key->ps_prolog.states.force_persp_sample_interp) {
7240 unsigned i, base = key->ps_prolog.num_input_sgprs;
7241 LLVMValueRef persp_sample[2];
7242
7243 /* Read PERSP_SAMPLE. */
7244 for (i = 0; i < 2; i++)
7245 persp_sample[i] = LLVMGetParam(func, base + i);
7246 /* Overwrite PERSP_CENTER. */
7247 for (i = 0; i < 2; i++)
7248 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7249 persp_sample[i], base + 2 + i, "");
7250 /* Overwrite PERSP_CENTROID. */
7251 for (i = 0; i < 2; i++)
7252 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7253 persp_sample[i], base + 4 + i, "");
7254 }
7255 if (key->ps_prolog.states.force_linear_sample_interp) {
7256 unsigned i, base = key->ps_prolog.num_input_sgprs;
7257 LLVMValueRef linear_sample[2];
7258
7259 /* Read LINEAR_SAMPLE. */
7260 for (i = 0; i < 2; i++)
7261 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7262 /* Overwrite LINEAR_CENTER. */
7263 for (i = 0; i < 2; i++)
7264 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7265 linear_sample[i], base + 8 + i, "");
7266 /* Overwrite LINEAR_CENTROID. */
7267 for (i = 0; i < 2; i++)
7268 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7269 linear_sample[i], base + 10 + i, "");
7270 }
7271
7272 /* Force center interpolation. */
7273 if (key->ps_prolog.states.force_persp_center_interp) {
7274 unsigned i, base = key->ps_prolog.num_input_sgprs;
7275 LLVMValueRef persp_center[2];
7276
7277 /* Read PERSP_CENTER. */
7278 for (i = 0; i < 2; i++)
7279 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7280 /* Overwrite PERSP_SAMPLE. */
7281 for (i = 0; i < 2; i++)
7282 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7283 persp_center[i], base + i, "");
7284 /* Overwrite PERSP_CENTROID. */
7285 for (i = 0; i < 2; i++)
7286 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7287 persp_center[i], base + 4 + i, "");
7288 }
7289 if (key->ps_prolog.states.force_linear_center_interp) {
7290 unsigned i, base = key->ps_prolog.num_input_sgprs;
7291 LLVMValueRef linear_center[2];
7292
7293 /* Read LINEAR_CENTER. */
7294 for (i = 0; i < 2; i++)
7295 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7296 /* Overwrite LINEAR_SAMPLE. */
7297 for (i = 0; i < 2; i++)
7298 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7299 linear_center[i], base + 6 + i, "");
7300 /* Overwrite LINEAR_CENTROID. */
7301 for (i = 0; i < 2; i++)
7302 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7303 linear_center[i], base + 10 + i, "");
7304 }
7305
7306 /* Interpolate colors. */
7307 unsigned color_out_idx = 0;
7308 for (i = 0; i < 2; i++) {
7309 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7310 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7311 key->ps_prolog.face_vgpr_index;
7312 LLVMValueRef interp[2], color[4];
7313 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7314
7315 if (!writemask)
7316 continue;
7317
7318 /* If the interpolation qualifier is not CONSTANT (-1). */
7319 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7320 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7321 key->ps_prolog.color_interp_vgpr_index[i];
7322
7323 /* Get the (i,j) updated by bc_optimize handling. */
7324 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7325 interp_vgpr, "");
7326 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7327 interp_vgpr + 1, "");
7328 interp_ij = lp_build_gather_values(&ctx->gallivm, interp, 2);
7329 }
7330
7331 /* Use the absolute location of the input. */
7332 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7333
7334 if (key->ps_prolog.states.color_two_side) {
7335 face = LLVMGetParam(func, face_vgpr);
7336 face = ac_to_integer(&ctx->ac, face);
7337 }
7338
7339 interp_fs_input(ctx,
7340 key->ps_prolog.color_attr_index[i],
7341 TGSI_SEMANTIC_COLOR, i,
7342 key->ps_prolog.num_interp_inputs,
7343 key->ps_prolog.colors_read, interp_ij,
7344 prim_mask, face, color);
7345
7346 while (writemask) {
7347 unsigned chan = u_bit_scan(&writemask);
7348 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7349 fninfo.num_params + color_out_idx++, "");
7350 }
7351 }
7352
7353 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7354 * says:
7355 *
7356 * "When per-sample shading is active due to the use of a fragment
7357 * input qualified by sample or due to the use of the gl_SampleID
7358 * or gl_SamplePosition variables, only the bit for the current
7359 * sample is set in gl_SampleMaskIn. When state specifies multiple
7360 * fragment shader invocations for a given fragment, the sample
7361 * mask for any single fragment shader invocation may specify a
7362 * subset of the covered samples for the fragment. In this case,
7363 * the bit corresponding to each covered sample will be set in
7364 * exactly one fragment shader invocation."
7365 *
7366 * The samplemask loaded by hardware is always the coverage of the
7367 * entire pixel/fragment, so mask bits out based on the sample ID.
7368 */
7369 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7370 /* The bit pattern matches that used by fixed function fragment
7371 * processing. */
7372 static const uint16_t ps_iter_masks[] = {
7373 0xffff, /* not used */
7374 0x5555,
7375 0x1111,
7376 0x0101,
7377 0x0001,
7378 };
7379 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7380
7381 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7382 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7383 key->ps_prolog.ancillary_vgpr_index;
7384 LLVMValueRef sampleid = unpack_param(ctx, ancillary_vgpr, 8, 4);
7385 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7386
7387 samplemask = ac_to_integer(&ctx->ac, samplemask);
7388 samplemask = LLVMBuildAnd(
7389 ctx->ac.builder,
7390 samplemask,
7391 LLVMBuildShl(ctx->ac.builder,
7392 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7393 sampleid, ""),
7394 "");
7395 samplemask = ac_to_float(&ctx->ac, samplemask);
7396
7397 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7398 ancillary_vgpr + 1, "");
7399 }
7400
7401 /* Tell LLVM to insert WQM instruction sequence when needed. */
7402 if (key->ps_prolog.wqm) {
7403 LLVMAddTargetDependentFunctionAttr(func,
7404 "amdgpu-ps-wqm-outputs", "");
7405 }
7406
7407 si_llvm_build_ret(ctx, ret);
7408 }
7409
7410 /**
7411 * Build the pixel shader epilog function. This handles everything that must be
7412 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7413 */
7414 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7415 union si_shader_part_key *key)
7416 {
7417 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7418 struct si_function_info fninfo;
7419 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7420 int i;
7421 struct si_ps_exports exp = {};
7422
7423 si_init_function_info(&fninfo);
7424
7425 /* Declare input SGPRs. */
7426 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7427 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7428 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7429 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7430 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7431
7432 /* Declare input VGPRs. */
7433 unsigned required_num_params =
7434 fninfo.num_sgpr_params +
7435 util_bitcount(key->ps_epilog.colors_written) * 4 +
7436 key->ps_epilog.writes_z +
7437 key->ps_epilog.writes_stencil +
7438 key->ps_epilog.writes_samplemask;
7439
7440 required_num_params = MAX2(required_num_params,
7441 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7442
7443 while (fninfo.num_params < required_num_params)
7444 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7445
7446 /* Create the function. */
7447 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7448 /* Disable elimination of unused inputs. */
7449 si_llvm_add_attribute(ctx->main_fn,
7450 "InitialPSInputAddr", 0xffffff);
7451
7452 /* Process colors. */
7453 unsigned vgpr = fninfo.num_sgpr_params;
7454 unsigned colors_written = key->ps_epilog.colors_written;
7455 int last_color_export = -1;
7456
7457 /* Find the last color export. */
7458 if (!key->ps_epilog.writes_z &&
7459 !key->ps_epilog.writes_stencil &&
7460 !key->ps_epilog.writes_samplemask) {
7461 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7462
7463 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7464 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7465 /* Just set this if any of the colorbuffers are enabled. */
7466 if (spi_format &
7467 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7468 last_color_export = 0;
7469 } else {
7470 for (i = 0; i < 8; i++)
7471 if (colors_written & (1 << i) &&
7472 (spi_format >> (i * 4)) & 0xf)
7473 last_color_export = i;
7474 }
7475 }
7476
7477 while (colors_written) {
7478 LLVMValueRef color[4];
7479 int mrt = u_bit_scan(&colors_written);
7480
7481 for (i = 0; i < 4; i++)
7482 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7483
7484 si_export_mrt_color(bld_base, color, mrt,
7485 fninfo.num_params - 1,
7486 mrt == last_color_export, &exp);
7487 }
7488
7489 /* Process depth, stencil, samplemask. */
7490 if (key->ps_epilog.writes_z)
7491 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7492 if (key->ps_epilog.writes_stencil)
7493 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7494 if (key->ps_epilog.writes_samplemask)
7495 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7496
7497 if (depth || stencil || samplemask)
7498 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7499 else if (last_color_export == -1)
7500 si_export_null(bld_base);
7501
7502 if (exp.num)
7503 si_emit_ps_exports(ctx, &exp);
7504
7505 /* Compile. */
7506 LLVMBuildRetVoid(ctx->ac.builder);
7507 }
7508
7509 /**
7510 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7511 */
7512 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7513 LLVMTargetMachineRef tm,
7514 struct si_shader *shader,
7515 struct pipe_debug_callback *debug)
7516 {
7517 union si_shader_part_key prolog_key;
7518 union si_shader_part_key epilog_key;
7519
7520 /* Get the prolog. */
7521 si_get_ps_prolog_key(shader, &prolog_key, true);
7522
7523 /* The prolog is a no-op if these aren't set. */
7524 if (si_need_ps_prolog(&prolog_key)) {
7525 shader->prolog =
7526 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7527 PIPE_SHADER_FRAGMENT, true,
7528 &prolog_key, tm, debug,
7529 si_build_ps_prolog_function,
7530 "Fragment Shader Prolog");
7531 if (!shader->prolog)
7532 return false;
7533 }
7534
7535 /* Get the epilog. */
7536 si_get_ps_epilog_key(shader, &epilog_key);
7537
7538 shader->epilog =
7539 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7540 PIPE_SHADER_FRAGMENT, false,
7541 &epilog_key, tm, debug,
7542 si_build_ps_epilog_function,
7543 "Fragment Shader Epilog");
7544 if (!shader->epilog)
7545 return false;
7546
7547 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7548 if (shader->key.part.ps.prolog.poly_stipple) {
7549 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7550 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7551 }
7552
7553 /* Set up the enable bits for per-sample shading if needed. */
7554 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7555 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7556 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7557 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7558 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7559 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7560 }
7561 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7562 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7563 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7564 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7565 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7566 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7567 }
7568 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7569 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7570 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7571 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7572 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7573 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7574 }
7575 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7576 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7577 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7578 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7579 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7580 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7581 }
7582
7583 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7584 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7585 !(shader->config.spi_ps_input_ena & 0xf)) {
7586 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7587 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7588 }
7589
7590 /* At least one pair of interpolation weights must be enabled. */
7591 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7592 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7593 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7594 }
7595
7596 /* Samplemask fixup requires the sample ID. */
7597 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7598 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7599 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7600 }
7601
7602 /* The sample mask input is always enabled, because the API shader always
7603 * passes it through to the epilog. Disable it here if it's unused.
7604 */
7605 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7606 !shader->selector->info.reads_samplemask)
7607 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7608
7609 return true;
7610 }
7611
7612 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7613 unsigned *lds_size)
7614 {
7615 /* SPI barrier management bug:
7616 * Make sure we have at least 4k of LDS in use to avoid the bug.
7617 * It applies to workgroup sizes of more than one wavefront.
7618 */
7619 if (sscreen->info.family == CHIP_BONAIRE ||
7620 sscreen->info.family == CHIP_KABINI ||
7621 sscreen->info.family == CHIP_MULLINS)
7622 *lds_size = MAX2(*lds_size, 8);
7623 }
7624
7625 static void si_fix_resource_usage(struct si_screen *sscreen,
7626 struct si_shader *shader)
7627 {
7628 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7629
7630 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7631
7632 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7633 si_get_max_workgroup_size(shader) > 64) {
7634 si_multiwave_lds_size_workaround(sscreen,
7635 &shader->config.lds_size);
7636 }
7637 }
7638
7639 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7640 struct si_shader *shader,
7641 struct pipe_debug_callback *debug)
7642 {
7643 struct si_shader_selector *sel = shader->selector;
7644 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7645 int r;
7646
7647 /* LS, ES, VS are compiled on demand if the main part hasn't been
7648 * compiled for that stage.
7649 *
7650 * Vertex shaders are compiled on demand when a vertex fetch
7651 * workaround must be applied.
7652 */
7653 if (shader->is_monolithic) {
7654 /* Monolithic shader (compiled as a whole, has many variants,
7655 * may take a long time to compile).
7656 */
7657 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7658 if (r)
7659 return r;
7660 } else {
7661 /* The shader consists of several parts:
7662 *
7663 * - the middle part is the user shader, it has 1 variant only
7664 * and it was compiled during the creation of the shader
7665 * selector
7666 * - the prolog part is inserted at the beginning
7667 * - the epilog part is inserted at the end
7668 *
7669 * The prolog and epilog have many (but simple) variants.
7670 *
7671 * Starting with gfx9, geometry and tessellation control
7672 * shaders also contain the prolog and user shader parts of
7673 * the previous shader stage.
7674 */
7675
7676 if (!mainp)
7677 return -1;
7678
7679 /* Copy the compiled TGSI shader data over. */
7680 shader->is_binary_shared = true;
7681 shader->binary = mainp->binary;
7682 shader->config = mainp->config;
7683 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7684 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7685 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7686 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
7687 memcpy(shader->info.vs_output_param_offset,
7688 mainp->info.vs_output_param_offset,
7689 sizeof(mainp->info.vs_output_param_offset));
7690 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7691 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7692 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7693
7694 /* Select prologs and/or epilogs. */
7695 switch (sel->type) {
7696 case PIPE_SHADER_VERTEX:
7697 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7698 return -1;
7699 break;
7700 case PIPE_SHADER_TESS_CTRL:
7701 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7702 return -1;
7703 break;
7704 case PIPE_SHADER_TESS_EVAL:
7705 break;
7706 case PIPE_SHADER_GEOMETRY:
7707 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
7708 return -1;
7709 break;
7710 case PIPE_SHADER_FRAGMENT:
7711 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7712 return -1;
7713
7714 /* Make sure we have at least as many VGPRs as there
7715 * are allocated inputs.
7716 */
7717 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7718 shader->info.num_input_vgprs);
7719 break;
7720 }
7721
7722 /* Update SGPR and VGPR counts. */
7723 if (shader->prolog) {
7724 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7725 shader->prolog->config.num_sgprs);
7726 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7727 shader->prolog->config.num_vgprs);
7728 }
7729 if (shader->previous_stage) {
7730 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7731 shader->previous_stage->config.num_sgprs);
7732 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7733 shader->previous_stage->config.num_vgprs);
7734 shader->config.spilled_sgprs =
7735 MAX2(shader->config.spilled_sgprs,
7736 shader->previous_stage->config.spilled_sgprs);
7737 shader->config.spilled_vgprs =
7738 MAX2(shader->config.spilled_vgprs,
7739 shader->previous_stage->config.spilled_vgprs);
7740 shader->config.private_mem_vgprs =
7741 MAX2(shader->config.private_mem_vgprs,
7742 shader->previous_stage->config.private_mem_vgprs);
7743 shader->config.scratch_bytes_per_wave =
7744 MAX2(shader->config.scratch_bytes_per_wave,
7745 shader->previous_stage->config.scratch_bytes_per_wave);
7746 shader->info.uses_instanceid |=
7747 shader->previous_stage->info.uses_instanceid;
7748 }
7749 if (shader->prolog2) {
7750 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7751 shader->prolog2->config.num_sgprs);
7752 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7753 shader->prolog2->config.num_vgprs);
7754 }
7755 if (shader->epilog) {
7756 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7757 shader->epilog->config.num_sgprs);
7758 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7759 shader->epilog->config.num_vgprs);
7760 }
7761 }
7762
7763 si_fix_resource_usage(sscreen, shader);
7764 si_shader_dump(sscreen, shader, debug, sel->info.processor,
7765 stderr, true);
7766
7767 /* Upload. */
7768 r = si_shader_binary_upload(sscreen, shader);
7769 if (r) {
7770 fprintf(stderr, "LLVM failed to upload shader\n");
7771 return r;
7772 }
7773
7774 return 0;
7775 }
7776
7777 void si_shader_destroy(struct si_shader *shader)
7778 {
7779 if (shader->scratch_bo)
7780 r600_resource_reference(&shader->scratch_bo, NULL);
7781
7782 r600_resource_reference(&shader->bo, NULL);
7783
7784 if (!shader->is_binary_shared)
7785 ac_shader_binary_clean(&shader->binary);
7786
7787 free(shader->shader_log);
7788 }